| Category | Difficulty |
|---|---|
| HW | 4 |
| Labs | 7 |
| Exams | 9 |
This class gives a comprehensive introduction to the concepts and implementation details of modern computer processors, specifically about RISC-V processors. You will implement simple versions of processors in System Verilog, and will also learn topics related to measuring the performance of your processor.
The HW in this class is very standard. They are essentially textbook problems, and ask for calculations and exercises with concepts learned in class.
Exams in 18-447 are difficult because they have quite a bit of time pressure, except for the final. The 2 midterms are to completed in 50 minutes, and usually contain 4-5 questions. Questions are also graded quite harshly, especially the conceptual ones.
One topic in particular that is tested quite subtly is energy and efficiency. It is important to practice energy questions a lot and understand how to derive all of the formulas. You are usually asked to explain why parallel processing is more efficient, or why pipelining helps save energy. You need to say the correct specific set of explanations to get full credit. A "kinda similar explanation" is not good enough.
This class also has a unique policy where you try to guess your exam score before you take the test. If you are within 5 points of your guess, you get a free bonus point. You should probably decide this number before you take the exam, and maybe adjust it at the end of the exam if you feel differently.
Labs are the equivalent of programming assignments in CS classes. In 18-447 you will code System Verilog implementations of a processor, starting from the basics, eventually to a simple, modern 5-stage pipeline processor. Because each lab is related to one another, they flow really nicely. On the other hand, in the later labs, you will likely be reusing code from earlier labs, especially when you first implement the 5-stage pipeline. So you should make sure that you write reasonably styled code. In later labs, it might benefit you to write multiple files so you can more easily organize your code -- a big file will be hard to maintain.
The later labs in this class will be a bit different every year, as they focus on different optimizations to the 5-stage pipeline.
Labs are distributed via Github, so if you are not familiar with git, you might want to learn some basic version control before this class.
The labs are done with a partner, so you should find someone to work with beforehand in the class.
Very straightforward lab. You decode bits and figure out what instructions are encoded, and you perform operations based on what you decode.
It's important in this lab to make your decoding logic modular so you don't rewrite a bunch of code over and over again.
This lab is the only lab where you will write C code.
Basically just Lab 1a but written in System Verilog instead of C.
It is a good idea to start implementing your processor in the form of blocks of the 5 stage pipeline in this lab, even though not required, because it will make it much easier to do Lab 2.
You essentially just take Lab 1b and split up the various stages into 5 stages, and add FFs in between them. As mentioned earlier, if your Lab 1b code is similar to the 5 stage pipeline format, it will be much easier to do this lab.
You extend your 5-stage pipeline and make it faster by adding forwarding, which significantly speeds up instructions that do not need to go through all the stages. The most tricky part of this lab is figuring out the logic that determines when it is safe to perform forwarding. Most of this logic is gone over in lecture, so use that as a starting point.
Be careful about your forwarding logic, since you will be penalized a lot if it is wrong.
This labs varies every semester, but focuses on implementing an improvement or architecture change from lab 3. The main component in this lab is that your processor is competed with the rest of the class, and your grade depends on your relative performance with the rest of the class. You're given freedom to choose how to implement your processor besides the guidelines set in the project.
Some ideas you can use to speed up your processor are:
- Reducing critical paths where possible
- Splitting complicated logic into smaller blocks
- Doing things out of order if you can
- Prefetching as early as possible if there is a memory component
- Professor Hoe's Website As long as Prof. Hoe teaches this class, his version of the course will be on his website. You can find previous years' lectures and extra resources, as well as course information.