From 790efd81920d74b10934347a35f31971616aea65 Mon Sep 17 00:00:00 2001 From: cdrewes Date: Wed, 11 May 2022 22:36:51 -0700 Subject: [PATCH] Fix IP export --- .../new => pulsegen_sync}/component.xml | 29 +- .../new => pulsegen_sync}/pulsegen_v.v | 17 - .../xgui/pulsegen_v_v1_0.tcl | 0 .../pulsegen_v.cache/wt/gui_handlers.wdf | 60 --- .../wt/java_command_handlers.wdf | 14 - .../pulsegen_v.cache/wt/project.wpc | 3 - .../pulsegen_v.cache/wt/synthesis.wdf | 39 -- .../pulsegen_v.cache/wt/synthesis_details.wdf | 3 - .../pulsegen_v.cache/wt/webtalk_pa.xml | 100 ---- .../pulsegen_v/pulsegen_v.hw/pulsegen_v.lpr | 6 - .../pulsegen_v.runs/.jobs/vrs_config_1.xml | 5 - .../pulsegen_v.runs/.jobs/vrs_config_2.xml | 5 - .../pulsegen_v.runs/.jobs/vrs_config_3.xml | 5 - .../pulsegen_v.runs/.jobs/vrs_config_4.xml | 5 - .../pulsegen_v.runs/.jobs/vrs_config_5.xml | 5 - .../pulsegen_v.runs/.jobs/vrs_config_6.xml | 5 - .../pulsegen_v.runs/.jobs/vrs_config_7.xml | 5 - .../impl_1/.Vivado_Implementation.queue.rst | 0 .../impl_1/.init_design.begin.rst | 5 - .../impl_1/.init_design.end.rst | 0 .../impl_1/.opt_design.begin.rst | 5 - .../impl_1/.opt_design.end.rst | 0 .../impl_1/.place_design.begin.rst | 5 - .../impl_1/.place_design.end.rst | 0 .../impl_1/.route_design.begin.rst | 5 - .../impl_1/.route_design.end.rst | 0 .../pulsegen_v.runs/impl_1/.vivado.begin.rst | 5 - .../pulsegen_v.runs/impl_1/.vivado.end.rst | 0 .../pulsegen_v.runs/impl_1/ISEWrap.js | 244 ---------- .../pulsegen_v.runs/impl_1/ISEWrap.sh | 63 --- .../pulsegen_v.runs/impl_1/gen_run.xml | 108 ----- .../pulsegen_v/pulsegen_v.runs/impl_1/htr.txt | 9 - .../pulsegen_v.runs/impl_1/init_design.pb | Bin 1651 -> 0 bytes .../pulsegen_v.runs/impl_1/opt_design.pb | Bin 9396 -> 0 bytes .../pulsegen_v.runs/impl_1/place_design.pb | Bin 12981 -> 0 bytes .../pulsegen_v.runs/impl_1/project.wdf | 31 -- .../pulsegen_v.runs/impl_1/pulsegen_v.tcl | 151 ------ .../pulsegen_v.runs/impl_1/pulsegen_v.vdi | 424 ----------------- .../impl_1/pulsegen_v_bus_skew_routed.pb | Bin 30 -> 0 bytes .../impl_1/pulsegen_v_bus_skew_routed.rpt | 15 - .../impl_1/pulsegen_v_bus_skew_routed.rpx | Bin 1053 -> 0 bytes .../pulsegen_v_clock_utilization_routed.rpt | 145 ------ .../impl_1/pulsegen_v_control_sets_placed.rpt | 67 --- .../impl_1/pulsegen_v_drc_opted.pb | Bin 37 -> 0 bytes .../impl_1/pulsegen_v_drc_opted.rpt | 53 --- .../impl_1/pulsegen_v_drc_opted.rpx | Bin 4260 -> 0 bytes .../impl_1/pulsegen_v_drc_routed.pb | Bin 37 -> 0 bytes .../impl_1/pulsegen_v_drc_routed.rpt | 53 --- .../impl_1/pulsegen_v_drc_routed.rpx | Bin 4261 -> 0 bytes .../impl_1/pulsegen_v_io_placed.rpt | 442 ------------------ .../pulsegen_v_methodology_drc_routed.pb | Bin 52 -> 0 bytes .../pulsegen_v_methodology_drc_routed.rpt | 50 -- .../pulsegen_v_methodology_drc_routed.rpx | Bin 795 -> 0 bytes .../pulsegen_v.runs/impl_1/pulsegen_v_opt.dcp | Bin 8356 -> 0 bytes .../impl_1/pulsegen_v_placed.dcp | Bin 210291 -> 0 bytes .../impl_1/pulsegen_v_power_routed.rpt | 150 ------ .../impl_1/pulsegen_v_power_routed.rpx | Bin 7651 -> 0 bytes .../impl_1/pulsegen_v_power_summary_routed.pb | Bin 722 -> 0 bytes .../impl_1/pulsegen_v_route_status.pb | Bin 43 -> 0 bytes .../impl_1/pulsegen_v_route_status.rpt | 11 - .../impl_1/pulsegen_v_routed.dcp | Bin 213646 -> 0 bytes .../pulsegen_v_timing_summary_routed.pb | 2 - .../pulsegen_v_timing_summary_routed.rpt | 173 ------- .../pulsegen_v_timing_summary_routed.rpx | Bin 4414 -> 0 bytes .../impl_1/pulsegen_v_utilization_placed.pb | Bin 224 -> 0 bytes .../impl_1/pulsegen_v_utilization_placed.rpt | 200 -------- .../pulsegen_v.runs/impl_1/route_design.pb | Bin 12838 -> 0 bytes .../pulsegen_v.runs/impl_1/rundef.js | 44 -- .../pulsegen_v.runs/impl_1/runme.bat | 11 - .../pulsegen_v.runs/impl_1/runme.sh | 43 -- .../pulsegen_v.runs/impl_1/vivado.pb | Bin 149 -> 0 bytes .../synth_1/.Vivado_Synthesis.queue.rst | 0 .../pulsegen_v.runs/synth_1/.vivado.begin.rst | 5 - .../pulsegen_v.runs/synth_1/.vivado.end.rst | 0 .../pulsegen_v.runs/synth_1/ISEWrap.js | 244 ---------- .../pulsegen_v.runs/synth_1/ISEWrap.sh | 63 --- .../synth_1/__synthesis_is_complete__ | 0 .../pulsegen_v.runs/synth_1/gen_run.xml | 40 -- .../pulsegen_v.runs/synth_1/htr.txt | 9 - .../pulsegen_v.runs/synth_1/project.wdf | 31 -- .../pulsegen_v.runs/synth_1/pulsegen_v.dcp | Bin 8032 -> 0 bytes .../pulsegen_v.runs/synth_1/pulsegen_v.tcl | 52 --- .../pulsegen_v.runs/synth_1/pulsegen_v.vds | 252 ---------- .../synth_1/pulsegen_v_utilization_synth.pb | Bin 224 -> 0 bytes .../synth_1/pulsegen_v_utilization_synth.rpt | 173 ------- .../pulsegen_v.runs/synth_1/rundef.js | 40 -- .../pulsegen_v.runs/synth_1/runme.bat | 11 - .../pulsegen_v.runs/synth_1/runme.sh | 39 -- .../pulsegen_v.runs/synth_1/vivado.pb | Bin 27185 -> 0 bytes .../sources_1/new/xgui/pulsegen_sync_v1_0.tcl | 10 - burn/ip/pulsegen_v/pulsegen_v.xpr | 151 ------ burn/z1/base/base.bit | Bin 4045672 -> 4045672 bytes burn/z1/base/base.rpt | 2 +- burn/z1/base/base.tcl | 4 +- burn/z1/picorv/picorv32.bit | Bin 4045676 -> 4045676 bytes burn/z1/picorv/picorv32.rpt | 2 +- burn/z1/picorv/picorv32.tcl | 4 +- 97 files changed, 21 insertions(+), 3931 deletions(-) rename burn/ip/{pulsegen_v/pulsegen_v.srcs/sources_1/new => pulsegen_sync}/component.xml (88%) rename burn/ip/{pulsegen_v/pulsegen_v.srcs/sources_1/new => pulsegen_sync}/pulsegen_v.v (67%) rename burn/ip/{pulsegen_v/pulsegen_v.srcs/sources_1/new => pulsegen_sync}/xgui/pulsegen_v_v1_0.tcl (100%) delete mode 100644 burn/ip/pulsegen_v/pulsegen_v.cache/wt/gui_handlers.wdf delete mode 100644 burn/ip/pulsegen_v/pulsegen_v.cache/wt/java_command_handlers.wdf delete mode 100644 burn/ip/pulsegen_v/pulsegen_v.cache/wt/project.wpc delete mode 100644 burn/ip/pulsegen_v/pulsegen_v.cache/wt/synthesis.wdf delete mode 100644 burn/ip/pulsegen_v/pulsegen_v.cache/wt/synthesis_details.wdf delete mode 100644 burn/ip/pulsegen_v/pulsegen_v.cache/wt/webtalk_pa.xml delete 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burn/ip/pulsegen_v/pulsegen_v.srcs/sources_1/new/component.xml rename to burn/ip/pulsegen_sync/component.xml index b43ae69..cdc70e7 100644 --- a/burn/ip/pulsegen_v/pulsegen_v.srcs/sources_1/new/component.xml +++ b/burn/ip/pulsegen_sync/component.xml @@ -1,8 +1,8 @@ - user.org - user - pulsegen_sync + colindrewes.com + colindrewes + pulsegen_v 1.0 @@ -36,7 +36,7 @@ viewChecksum - 8b34af51 + b02efd88 @@ -52,7 +52,7 @@ viewChecksum - 8b34af51 + b02efd88 @@ -123,7 +123,7 @@ pulsegen_v.v verilogSource - CHECKSUM_8b34af51 + CHECKSUM_b02efd88 @@ -136,14 +136,14 @@ xilinx_xpgui_view_fileset - xgui/pulsegen_sync_v1_0.tcl + xgui/pulsegen_v_v1_0.tcl tclSource CHECKSUM_f92e9879 XGUI_VERSION_2 - pulsegen_sync + pulsegen_v Component_Name @@ -177,19 +177,20 @@ /UserIP - pulsegen_sync + pulsegen_v package_project - 3 - 2020-12-25T09:21:19Z + 2 + 2022-05-11T23:35:22Z - /home/colin/Desktop/PL-Sensors/burn/ip/pulsegen_v/pulsegen_v.srcs/sources_1/new - /home/colin/Desktop/PL-Sensors/burn/ip/pulsegen_v/pulsegen_v.srcs/sources_1/new + /data/cdrewes/Tunable-TDC/burn/ip/pulsegen_sync + /data/cdrewes/Tunable-TDC/burn/ip/pulsegen_sync + /data/cdrewes/Tunable-TDC/burn/ip/pulsegen_sync 2018.2 - + diff --git a/burn/ip/pulsegen_v/pulsegen_v.srcs/sources_1/new/pulsegen_v.v b/burn/ip/pulsegen_sync/pulsegen_v.v similarity index 67% rename from burn/ip/pulsegen_v/pulsegen_v.srcs/sources_1/new/pulsegen_v.v rename to burn/ip/pulsegen_sync/pulsegen_v.v index b84d98b..7fb8c1f 100644 --- a/burn/ip/pulsegen_v/pulsegen_v.srcs/sources_1/new/pulsegen_v.v +++ b/burn/ip/pulsegen_sync/pulsegen_v.v @@ -22,33 +22,16 @@ module pulsegen_v( input clk, - //input reset_in, output reg[7:0] O, output reg syncer ); reg[1:0] count = 2'b00; -//reg trigger = 1'b0; -//reg reset = 1'b0; - -//always @(*) begin -// if (reset_in == 1'b1) begin -// trigger = 1'b1; -// end -//end always @(posedge clk) begin count <= count + 1; O <= (count[1] == 1'b0) ? 8'b00000000 : 8'b00000001; syncer <= (count == 2'b10) ? 1'b1 : 1'b0; - //if (reset == 1'b1) begin - // trigger <= 1'b0; - // reset <= 1'b0; - //end - //if (trigger == 1'b1 && count == 2'b10) begin - // synced_reset <= 1'b1; - // reset <= 1'b1; - //end end endmodule diff --git a/burn/ip/pulsegen_v/pulsegen_v.srcs/sources_1/new/xgui/pulsegen_v_v1_0.tcl b/burn/ip/pulsegen_sync/xgui/pulsegen_v_v1_0.tcl similarity index 100% rename from burn/ip/pulsegen_v/pulsegen_v.srcs/sources_1/new/xgui/pulsegen_v_v1_0.tcl rename to burn/ip/pulsegen_sync/xgui/pulsegen_v_v1_0.tcl diff --git a/burn/ip/pulsegen_v/pulsegen_v.cache/wt/gui_handlers.wdf b/burn/ip/pulsegen_v/pulsegen_v.cache/wt/gui_handlers.wdf deleted file mode 100644 index 2ebf2b5..0000000 --- a/burn/ip/pulsegen_v/pulsegen_v.cache/wt/gui_handlers.wdf +++ /dev/null @@ -1,60 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:34:00:00 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a/burn/ip/pulsegen_v/pulsegen_v.cache/wt/synthesis_details.wdf b/burn/ip/pulsegen_v/pulsegen_v.cache/wt/synthesis_details.wdf deleted file mode 100644 index 78f8d66..0000000 --- a/burn/ip/pulsegen_v/pulsegen_v.cache/wt/synthesis_details.wdf +++ /dev/null @@ -1,3 +0,0 @@ -version:1 -73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00 -eof:2511430288 diff --git a/burn/ip/pulsegen_v/pulsegen_v.cache/wt/webtalk_pa.xml b/burn/ip/pulsegen_v/pulsegen_v.cache/wt/webtalk_pa.xml deleted file mode 100644 index 8fc02ac..0000000 --- a/burn/ip/pulsegen_v/pulsegen_v.cache/wt/webtalk_pa.xml +++ /dev/null @@ -1,100 +0,0 @@ - - - - -
- - -
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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - diff --git a/burn/ip/pulsegen_v/pulsegen_v.hw/pulsegen_v.lpr b/burn/ip/pulsegen_v/pulsegen_v.hw/pulsegen_v.lpr deleted file mode 100644 index 4577eea..0000000 --- a/burn/ip/pulsegen_v/pulsegen_v.hw/pulsegen_v.lpr +++ /dev/null @@ -1,6 +0,0 @@ - - - - - - diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/.jobs/vrs_config_1.xml b/burn/ip/pulsegen_v/pulsegen_v.runs/.jobs/vrs_config_1.xml deleted file mode 100644 index 951d257..0000000 --- a/burn/ip/pulsegen_v/pulsegen_v.runs/.jobs/vrs_config_1.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/.jobs/vrs_config_2.xml b/burn/ip/pulsegen_v/pulsegen_v.runs/.jobs/vrs_config_2.xml deleted file mode 100644 index 0a85373..0000000 --- a/burn/ip/pulsegen_v/pulsegen_v.runs/.jobs/vrs_config_2.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/.jobs/vrs_config_3.xml b/burn/ip/pulsegen_v/pulsegen_v.runs/.jobs/vrs_config_3.xml deleted file mode 100644 index 951d257..0000000 --- a/burn/ip/pulsegen_v/pulsegen_v.runs/.jobs/vrs_config_3.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/.jobs/vrs_config_4.xml b/burn/ip/pulsegen_v/pulsegen_v.runs/.jobs/vrs_config_4.xml deleted file mode 100644 index 0a85373..0000000 --- a/burn/ip/pulsegen_v/pulsegen_v.runs/.jobs/vrs_config_4.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/.jobs/vrs_config_5.xml b/burn/ip/pulsegen_v/pulsegen_v.runs/.jobs/vrs_config_5.xml deleted file mode 100644 index 951d257..0000000 --- a/burn/ip/pulsegen_v/pulsegen_v.runs/.jobs/vrs_config_5.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/.jobs/vrs_config_6.xml b/burn/ip/pulsegen_v/pulsegen_v.runs/.jobs/vrs_config_6.xml deleted file mode 100644 index 951d257..0000000 --- a/burn/ip/pulsegen_v/pulsegen_v.runs/.jobs/vrs_config_6.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/.jobs/vrs_config_7.xml b/burn/ip/pulsegen_v/pulsegen_v.runs/.jobs/vrs_config_7.xml deleted file mode 100644 index 0a85373..0000000 --- a/burn/ip/pulsegen_v/pulsegen_v.runs/.jobs/vrs_config_7.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/.Vivado_Implementation.queue.rst b/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/.Vivado_Implementation.queue.rst deleted file mode 100644 index e69de29..0000000 diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/.init_design.begin.rst b/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/.init_design.begin.rst deleted file mode 100644 index 5c9bb5b..0000000 --- a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/.init_design.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/.init_design.end.rst b/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/.init_design.end.rst deleted file mode 100644 index e69de29..0000000 diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/.opt_design.begin.rst b/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/.opt_design.begin.rst deleted file mode 100644 index 5c9bb5b..0000000 --- a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/.opt_design.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/.opt_design.end.rst b/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/.opt_design.end.rst deleted file mode 100644 index e69de29..0000000 diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/.place_design.begin.rst b/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/.place_design.begin.rst deleted file mode 100644 index 5c9bb5b..0000000 --- a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/.place_design.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/.place_design.end.rst b/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/.place_design.end.rst deleted file mode 100644 index e69de29..0000000 diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/.route_design.begin.rst b/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/.route_design.begin.rst deleted file mode 100644 index 5c9bb5b..0000000 --- a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/.route_design.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/.route_design.end.rst b/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/.route_design.end.rst deleted file mode 100644 index e69de29..0000000 diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/.vivado.begin.rst b/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/.vivado.begin.rst deleted file mode 100644 index 778db82..0000000 --- a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/.vivado.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/.vivado.end.rst b/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/.vivado.end.rst deleted file mode 100644 index e69de29..0000000 diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/ISEWrap.js b/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/ISEWrap.js deleted file mode 100755 index 8284d2d..0000000 --- a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/ISEWrap.js +++ /dev/null @@ -1,244 +0,0 @@ -// -// Vivado(TM) -// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 -// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. -// - -// GLOBAL VARIABLES -var ISEShell = new ActiveXObject( "WScript.Shell" ); -var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); -var ISERunDir = ""; -var ISELogFile = "runme.log"; -var ISELogFileStr = null; -var ISELogEcho = true; -var ISEOldVersionWSH = false; - - - -// BOOTSTRAP -ISEInit(); - - - -// -// ISE FUNCTIONS -// -function ISEInit() { - - // 1. RUN DIR setup - var ISEScrFP = WScript.ScriptFullName; - var ISEScrN = WScript.ScriptName; - ISERunDir = - ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); - - // 2. LOG file setup - ISELogFileStr = ISEOpenFile( ISELogFile ); - - // 3. LOG echo? - var ISEScriptArgs = WScript.Arguments; - for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; - ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); - ISELogFileStr = ISEOpenFile( ISELogFile ); - - } else { // WSH 5.6 - - // LAUNCH! - ISEShell.CurrentDirectory = ISERunDir; - - // Redirect STDERR to STDOUT - ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; - var ISEProcess = ISEShell.Exec( ISECmdLine ); - - // BEGIN file creation - var ISENetwork = WScript.CreateObject( "WScript.Network" ); - var ISEHost = ISENetwork.ComputerName; - var ISEUser = ISENetwork.UserName; - var ISEPid = ISEProcess.ProcessID; - var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.Close(); - - var ISEOutStr = ISEProcess.StdOut; - var ISEErrStr = ISEProcess.StdErr; - - // WAIT for ISEStep to finish - while ( ISEProcess.Status == 0 ) { - - // dump stdout then stderr - feels a little arbitrary - while ( !ISEOutStr.AtEndOfStream ) { - ISEStdOut( ISEOutStr.ReadLine() ); - } - - WScript.Sleep( 100 ); - } - - ISEExitCode = ISEProcess.ExitCode; - } - - ISELogFileStr.Close(); - - // END/ERROR file creation - if ( ISEExitCode != 0 ) { - ISETouchFile( ISEStep, "error" ); - - } else { - ISETouchFile( ISEStep, "end" ); - } - - return ISEExitCode; -} - - -// -// UTILITIES -// -function ISEStdOut( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdOut.WriteLine( ISELine ); - } -} - -function ISEStdErr( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdErr.WriteLine( ISELine ); - } -} - -function ISETouchFile( ISERoot, ISEStatus ) { - - var ISETFile = - ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); - ISETFile.Close(); -} - -function ISEOpenFile( ISEFilename ) { - - // This function has been updated to deal with a problem seen in CR #870871. - // In that case the user runs a script that runs impl_1, and then turns around - // and runs impl_1 -to_step write_bitstream. That second run takes place in - // the same directory, which means we may hit some of the same files, and in - // particular, we will open the runme.log file. Even though this script closes - // the file (now), we see cases where a subsequent attempt to open the file - // fails. Perhaps the OS is slow to release the lock, or the disk comes into - // play? In any case, we try to work around this by first waiting if the file - // is already there for an arbitrary 5 seconds. Then we use a try-catch block - // and try to open the file 10 times with a one second delay after each attempt. - // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. - // If there is an unrecognized exception when trying to open the file, we output - // an error message and write details to an exception.log file. - var ISEFullPath = ISERunDir + "/" + ISEFilename; - if (ISEFileSys.FileExists(ISEFullPath)) { - // File is already there. This could be a problem. Wait in case it is still in use. - WScript.Sleep(5000); - } - var i; - for (i = 0; i < 10; ++i) { - try { - return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); - } catch (exception) { - var error_code = exception.number & 0xFFFF; // The other bits are a facility code. - if (error_code == 52) { // 52 is bad file name or number. - // Wait a second and try again. - WScript.Sleep(1000); - continue; - } else { - WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - var exceptionFilePath = ISERunDir + "/exception.log"; - if (!ISEFileSys.FileExists(exceptionFilePath)) { - WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); - var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); - exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - exceptionFile.WriteLine("\tException name: " + exception.name); - exceptionFile.WriteLine("\tException error code: " + error_code); - exceptionFile.WriteLine("\tException message: " + exception.message); - exceptionFile.Close(); - } - throw exception; - } - } - } - // If we reached this point, we failed to open the file after 10 attempts. - // We need to error out. - WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); - WScript.Quit(1); -} diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/ISEWrap.sh b/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/ISEWrap.sh deleted file mode 100755 index e1a8f5d..0000000 --- a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/ISEWrap.sh +++ /dev/null @@ -1,63 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# ISEWrap.sh: Vivado Runs Script for UNIX -# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. -# - -HD_LOG=$1 -shift - -# CHECK for a STOP FILE -if [ -f .stop.rst ] -then -echo "" >> $HD_LOG -echo "*** Halting run - EA reset detected ***" >> $HD_LOG -echo "" >> $HD_LOG -exit 1 -fi - -ISE_STEP=$1 -shift - -# WRITE STEP HEADER to LOG -echo "" >> $HD_LOG -echo "*** Running $ISE_STEP" >> $HD_LOG -echo " with args $@" >> $HD_LOG -echo "" >> $HD_LOG - -# LAUNCH! -$ISE_STEP "$@" >> $HD_LOG 2>&1 & - -# BEGIN file creation -ISE_PID=$! -if [ X != X$HOSTNAME ] -then -ISE_HOST=$HOSTNAME #bash -else -ISE_HOST=$HOST #csh -fi -ISE_USER=$USER -ISE_BEGINFILE=.$ISE_STEP.begin.rst -/bin/touch $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE - -# WAIT for ISEStep to finish -wait $ISE_PID - -# END/ERROR file creation -RETVAL=$? -if [ $RETVAL -eq 0 ] -then - /bin/touch .$ISE_STEP.end.rst -else - /bin/touch .$ISE_STEP.error.rst -fi - -exit $RETVAL - diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/gen_run.xml b/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/gen_run.xml deleted file mode 100644 index 71358a9..0000000 --- a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/gen_run.xml +++ /dev/null @@ -1,108 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/htr.txt b/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/htr.txt deleted file mode 100644 index b4c7087..0000000 --- a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/htr.txt +++ /dev/null @@ -1,9 +0,0 @@ -# -# Vivado(TM) -# htr.txt: a Vivado-generated description of how-to-repeat the -# the basic steps of a run. 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set retval [eval catch { $command } msg] - if { $retval != 0 } { - set fp [open $status w] - close $fp - send_msg_id runtcl-5 warning "$msg" - } -} -proc start_step { step } { - set stopFile ".stop.rst" - if {[file isfile .stop.rst]} { - puts "" - puts "*** Halting run - EA reset detected ***" - puts "" - puts "" - return -code error - } - set beginFile ".$step.begin.rst" - set platform "$::tcl_platform(platform)" - set user "$::tcl_platform(user)" - set pid [pid] - set host "" - if { [string equal $platform unix] } { - if { [info exist ::env(HOSTNAME)] } { - set host $::env(HOSTNAME) - } - } else { - if { [info exist ::env(COMPUTERNAME)] } { - set host $::env(COMPUTERNAME) - } - } - set ch [open $beginFile w] - puts $ch "" - puts $ch "" - puts $ch " " - puts $ch " " - puts $ch "" - close $ch -} - -proc end_step { step } { - set endFile ".$step.end.rst" - set ch [open $endFile w] - close $ch -} - -proc step_failed { step } { - set endFile ".$step.error.rst" - set ch [open $endFile w] - close $ch -} - - -start_step init_design -set ACTIVE_STEP init_design -set rc [catch { - create_msg_db init_design.pb - create_project -in_memory -part xc7z020clg400-1 - set_property design_mode GateLvl [current_fileset] - set_param project.singleFileAddWarning.threshold 0 - set_property webtalk.parent_dir /home/colin/Desktop/PL-Sensors/burn/ip/pulsegen_v/pulsegen_v.cache/wt [current_project] - set_property parent.project_path /home/colin/Desktop/PL-Sensors/burn/ip/pulsegen_v/pulsegen_v.xpr [current_project] - set_property ip_repo_paths /home/colin/Desktop/PL-Sensors/burn/ip/pulsegen_v/pulsegen_v.srcs/sources_1/new [current_project] - set_property ip_output_repo /home/colin/Desktop/PL-Sensors/burn/ip/pulsegen_v/pulsegen_v.cache/ip [current_project] - set_property ip_cache_permissions {read write} [current_project] - add_files -quiet /home/colin/Desktop/PL-Sensors/burn/ip/pulsegen_v/pulsegen_v.runs/synth_1/pulsegen_v.dcp - link_design -top pulsegen_v -part xc7z020clg400-1 - close_msg_db -file init_design.pb -} RESULT] -if {$rc} { - step_failed init_design - return -code error $RESULT -} else { - end_step init_design - unset ACTIVE_STEP -} - -start_step opt_design -set ACTIVE_STEP opt_design -set rc [catch { - create_msg_db opt_design.pb - opt_design - write_checkpoint -force pulsegen_v_opt.dcp - create_report "impl_1_opt_report_drc_0" "report_drc -file pulsegen_v_drc_opted.rpt -pb pulsegen_v_drc_opted.pb -rpx pulsegen_v_drc_opted.rpx" - close_msg_db -file opt_design.pb -} RESULT] -if {$rc} { - step_failed opt_design - return -code error $RESULT -} else { - end_step opt_design - unset ACTIVE_STEP -} - -start_step place_design -set ACTIVE_STEP place_design -set rc [catch { - create_msg_db place_design.pb - if { [llength [get_debug_cores -quiet] ] > 0 } { - implement_debug_core - } - place_design - write_checkpoint -force pulsegen_v_placed.dcp - create_report "impl_1_place_report_io_0" "report_io -file pulsegen_v_io_placed.rpt" - create_report "impl_1_place_report_utilization_0" "report_utilization -file pulsegen_v_utilization_placed.rpt -pb pulsegen_v_utilization_placed.pb" - create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file pulsegen_v_control_sets_placed.rpt" - close_msg_db -file place_design.pb -} RESULT] -if {$rc} { - step_failed place_design - return -code error $RESULT -} else { - end_step place_design - unset ACTIVE_STEP -} - -start_step route_design -set ACTIVE_STEP route_design -set rc [catch { - create_msg_db route_design.pb - route_design - write_checkpoint -force pulsegen_v_routed.dcp - create_report "impl_1_route_report_drc_0" "report_drc -file pulsegen_v_drc_routed.rpt -pb pulsegen_v_drc_routed.pb -rpx pulsegen_v_drc_routed.rpx" - create_report "impl_1_route_report_methodology_0" "report_methodology -file pulsegen_v_methodology_drc_routed.rpt -pb pulsegen_v_methodology_drc_routed.pb -rpx pulsegen_v_methodology_drc_routed.rpx" - create_report "impl_1_route_report_power_0" "report_power -file pulsegen_v_power_routed.rpt -pb pulsegen_v_power_summary_routed.pb -rpx pulsegen_v_power_routed.rpx" - create_report "impl_1_route_report_route_status_0" "report_route_status -file pulsegen_v_route_status.rpt -pb pulsegen_v_route_status.pb" - create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file pulsegen_v_timing_summary_routed.rpt -pb pulsegen_v_timing_summary_routed.pb -rpx pulsegen_v_timing_summary_routed.rpx -warn_on_violation " - create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file pulsegen_v_incremental_reuse_routed.rpt" - create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file pulsegen_v_clock_utilization_routed.rpt" - create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file pulsegen_v_bus_skew_routed.rpt -pb pulsegen_v_bus_skew_routed.pb -rpx pulsegen_v_bus_skew_routed.rpx" - close_msg_db -file route_design.pb -} RESULT] -if {$rc} { - write_checkpoint -force pulsegen_v_routed_error.dcp - step_failed route_design - return -code error $RESULT -} else { - end_step route_design - unset ACTIVE_STEP -} - diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v.vdi b/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v.vdi deleted file mode 100644 index e027b6e..0000000 --- a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v.vdi +++ /dev/null @@ -1,424 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.2 (64-bit) -# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 -# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 -# Start of session at: Thu Dec 24 23:23:21 2020 -# Process ID: 17637 -# Current directory: /home/colin/Desktop/PL-Sensors/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1 -# Command line: vivado -log pulsegen_v.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source pulsegen_v.tcl -notrace -# Log file: /home/colin/Desktop/PL-Sensors/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v.vdi -# Journal file: /home/colin/Desktop/PL-Sensors/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/vivado.jou -#----------------------------------------------------------- -source pulsegen_v.tcl -notrace -Command: link_design -top pulsegen_v -part xc7z020clg400-1 -Design is defaulting to srcset: sources_1 -Design is defaulting to constrset: constrs_1 -INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-479] Netlist was created with Vivado 2018.2 -INFO: [Device 21-403] Loading part xc7z020clg400-1 -INFO: [Project 1-570] Preparing netlist for logic optimization -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -6 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -link_design completed successfully -link_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:47 . Memory (MB): peak = 1485.812 ; gain = 273.438 ; free physical = 630 ; free virtual = 33081 -Command: opt_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z020' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020' -Running DRC as a precondition to command opt_design - -Starting DRC Task -INFO: [DRC 23-27] Running DRC with 8 threads -INFO: [Project 1-461] DRC finished with 0 Errors -INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1580.844 ; gain = 95.031 ; free physical = 565 ; free virtual = 33013 - -Starting Cache Timing Information Task -INFO: [Timing 38-35] Done setting XDC timing constraints. -Ending Cache Timing Information Task | Checksum: 6b677f95 - -Time (s): cpu = 00:00:18 ; elapsed = 00:00:36 . Memory (MB): peak = 1985.406 ; gain = 404.562 ; free physical = 268 ; free virtual = 32718 - -Starting Logic Optimization Task - -Phase 1 Retarget -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 1 Retarget | Checksum: 6b677f95 - -Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.08 . Memory (MB): peak = 1985.406 ; gain = 0.000 ; free physical = 268 ; free virtual = 32717 -INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells - -Phase 2 Constant propagation -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 2 Constant propagation | Checksum: 6b677f95 - -Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.09 . Memory (MB): peak = 1985.406 ; gain = 0.000 ; free physical = 268 ; free virtual = 32717 -INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells - -Phase 3 Sweep -Phase 3 Sweep | Checksum: 6b677f95 - -Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.09 . Memory (MB): peak = 1985.406 ; gain = 0.000 ; free physical = 268 ; free virtual = 32717 -INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells - -Phase 4 BUFG optimization -Phase 4 BUFG optimization | Checksum: 6b677f95 - -Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.09 . Memory (MB): peak = 1985.406 ; gain = 0.000 ; free physical = 268 ; free virtual = 32717 -INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. - -Phase 5 Shift Register Optimization -Phase 5 Shift Register Optimization | Checksum: 6b677f95 - -Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.09 . Memory (MB): peak = 1985.406 ; gain = 0.000 ; free physical = 268 ; free virtual = 32717 -INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells - -Phase 6 Post Processing Netlist -Phase 6 Post Processing Netlist | Checksum: 6b677f95 - -Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.09 . Memory (MB): peak = 1985.406 ; gain = 0.000 ; free physical = 268 ; free virtual = 32717 -INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells - -Starting Connectivity Check Task - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1985.406 ; gain = 0.000 ; free physical = 268 ; free virtual = 32717 -Ending Logic Optimization Task | Checksum: 6b677f95 - -Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.10 . Memory (MB): peak = 1985.406 ; gain = 0.000 ; free physical = 268 ; free virtual = 32717 - -Starting Power Optimization Task -INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -Ending Power Optimization Task | Checksum: 6b677f95 - -Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1985.406 ; gain = 0.000 ; free physical = 268 ; free virtual = 32717 - -Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: 6b677f95 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1985.406 ; gain = 0.000 ; free physical = 268 ; free virtual = 32717 -INFO: [Common 17-83] Releasing license: Implementation -22 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -opt_design completed successfully -opt_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:39 . Memory (MB): peak = 1985.406 ; gain = 499.594 ; free physical = 268 ; free virtual = 32717 -WARNING: [Constraints 18-5210] No constraint will be written out. -INFO: [Common 17-1381] The checkpoint '/home/colin/Desktop/PL-Sensors/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_opt.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file pulsegen_v_drc_opted.rpt -pb pulsegen_v_drc_opted.pb -rpx pulsegen_v_drc_opted.rpx -Command: report_drc -file pulsegen_v_drc_opted.rpt -pb pulsegen_v_drc_opted.pb -rpx pulsegen_v_drc_opted.rpx -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/colin/Desktop/PL-Sensors/burn/ip/pulsegen_v/pulsegen_v.srcs/sources_1/new'. -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/colin/Xilinx/Vivado/2018.2/data/ip'. -INFO: [DRC 23-27] Running DRC with 8 threads -INFO: [Coretcl 2-168] The results of DRC are in file /home/colin/Desktop/PL-Sensors/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_drc_opted.rpt. -report_drc completed successfully -report_drc: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2060.742 ; gain = 43.320 ; free physical = 214 ; free virtual = 32674 -Command: place_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z020' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020' -INFO: [DRC 23-27] Running DRC with 8 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. -Running DRC as a precondition to command place_design -INFO: [DRC 23-27] Running DRC with 8 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - -Starting Placer Task -INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs - -Phase 1 Placer Initialization - -Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2063.742 ; gain = 0.000 ; free physical = 210 ; free virtual = 32671 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 691c43b1 - -Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2063.742 ; gain = 0.000 ; free physical = 210 ; free virtual = 32671 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2063.742 ; gain = 0.000 ; free physical = 210 ; free virtual = 32671 - -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device -INFO: [Timing 38-35] Done setting XDC timing constraints. -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 17826bee5 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2104.754 ; gain = 41.012 ; free physical = 206 ; free virtual = 32670 - -Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: 26f7aab94 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2104.754 ; gain = 41.012 ; free physical = 206 ; free virtual = 32670 - -Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 26f7aab94 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2104.754 ; gain = 41.012 ; free physical = 206 ; free virtual = 32670 -Phase 1 Placer Initialization | Checksum: 26f7aab94 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2104.754 ; gain = 41.012 ; free physical = 206 ; free virtual = 32670 - -Phase 2 Global Placement - -Phase 2.1 Floorplanning -Phase 2.1 Floorplanning | Checksum: 26f7aab94 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2104.754 ; gain = 41.012 ; free physical = 204 ; free virtual = 32668 -WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer -Phase 2 Global Placement | Checksum: 1c49c0887 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2216.809 ; gain = 153.066 ; free physical = 189 ; free virtual = 32654 - -Phase 3 Detail Placement - -Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 1c49c0887 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2216.809 ; gain = 153.066 ; free physical = 189 ; free virtual = 32654 - -Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1e5eeba96 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2216.809 ; gain = 153.066 ; free physical = 189 ; free virtual = 32654 - -Phase 3.3 Area Swap Optimization -Phase 3.3 Area Swap Optimization | Checksum: 1c49c0887 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2216.809 ; gain = 153.066 ; free physical = 188 ; free virtual = 32654 - -Phase 3.4 Pipeline Register Optimization -Phase 3.4 Pipeline Register Optimization | Checksum: 1c49c0887 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2216.809 ; gain = 153.066 ; free physical = 188 ; free virtual = 32654 - -Phase 3.5 Small Shape Detail Placement -Phase 3.5 Small Shape Detail Placement | Checksum: 11c76aecc - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2216.809 ; gain = 153.066 ; free physical = 185 ; free virtual = 32650 - -Phase 3.6 Re-assign LUT pins -Phase 3.6 Re-assign LUT pins | Checksum: 11c76aecc - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2216.809 ; gain = 153.066 ; free physical = 185 ; free virtual = 32650 - -Phase 3.7 Pipeline Register Optimization -Phase 3.7 Pipeline Register Optimization | Checksum: 11c76aecc - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2216.809 ; gain = 153.066 ; free physical = 185 ; free virtual = 32650 -Phase 3 Detail Placement | Checksum: 11c76aecc - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2216.809 ; gain = 153.066 ; free physical = 185 ; free virtual = 32650 - -Phase 4 Post Placement Optimization and Clean-Up - -Phase 4.1 Post Commit Optimization -Phase 4.1 Post Commit Optimization | Checksum: 11c76aecc - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2216.809 ; gain = 153.066 ; free physical = 185 ; free virtual = 32650 - -Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: 11c76aecc - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2216.809 ; gain = 153.066 ; free physical = 186 ; free virtual = 32651 - -Phase 4.3 Placer Reporting -Phase 4.3 Placer Reporting | Checksum: 11c76aecc - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2216.809 ; gain = 153.066 ; free physical = 186 ; free virtual = 32651 - -Phase 4.4 Final Placement Cleanup -Phase 4.4 Final Placement Cleanup | Checksum: a397bd22 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2216.809 ; gain = 153.066 ; free physical = 186 ; free virtual = 32651 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: a397bd22 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2216.809 ; gain = 153.066 ; free physical = 186 ; free virtual = 32651 -Ending Placer Task | Checksum: 363e4a43 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2216.809 ; gain = 153.066 ; free physical = 202 ; free virtual = 32668 -INFO: [Common 17-83] Releasing license: Implementation -39 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. -place_design completed successfully -WARNING: [Constraints 18-5210] No constraint will be written out. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2216.809 ; gain = 0.000 ; free physical = 200 ; free virtual = 32667 -INFO: [Common 17-1381] The checkpoint '/home/colin/Desktop/PL-Sensors/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_placed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_io -file pulsegen_v_io_placed.rpt -report_io: Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.34 . Memory (MB): peak = 2216.809 ; gain = 0.000 ; free physical = 192 ; free virtual = 32658 -INFO: [runtcl-4] Executing : report_utilization -file pulsegen_v_utilization_placed.rpt -pb pulsegen_v_utilization_placed.pb -report_utilization: Time (s): cpu = 00:00:00.20 ; elapsed = 00:00:00.25 . Memory (MB): peak = 2216.809 ; gain = 0.000 ; free physical = 197 ; free virtual = 32667 -INFO: [runtcl-4] Executing : report_control_sets -verbose -file pulsegen_v_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.20 . Memory (MB): peak = 2216.809 ; gain = 0.000 ; free physical = 197 ; free virtual = 32667 -Command: route_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z020' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020' -Running DRC as a precondition to command route_design -INFO: [DRC 23-27] Running DRC with 8 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - - -Starting Routing Task -INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs -Checksum: PlaceDB: be0f21a ConstDB: 0 ShapeSum: 2a5d5829 RouteDB: 0 - -Phase 1 Build RT Design -Phase 1 Build RT Design | Checksum: 1d809f0ef - -Time (s): cpu = 00:00:34 ; elapsed = 00:00:29 . Memory (MB): peak = 2259.559 ; gain = 42.750 ; free physical = 160 ; free virtual = 32501 -Post Restoration Checksum: NetGraph: f1a99fb2 NumContArr: e660513d Constraints: 0 Timing: 0 - -Phase 2 Router Initialization -INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. - -Phase 2.1 Fix Topology Constraints -Phase 2.1 Fix Topology Constraints | Checksum: 1d809f0ef - -Time (s): cpu = 00:00:34 ; elapsed = 00:00:29 . Memory (MB): peak = 2266.547 ; gain = 49.738 ; free physical = 137 ; free virtual = 32474 - -Phase 2.2 Pre Route Cleanup -Phase 2.2 Pre Route Cleanup | Checksum: 1d809f0ef - -Time (s): cpu = 00:00:34 ; elapsed = 00:00:29 . Memory (MB): peak = 2266.547 ; gain = 49.738 ; free physical = 137 ; free virtual = 32474 - Number of Nodes with overlaps = 0 -Phase 2 Router Initialization | Checksum: 13fff9d78 - -Time (s): cpu = 00:00:34 ; elapsed = 00:00:29 . Memory (MB): peak = 2279.602 ; gain = 62.793 ; free physical = 165 ; free virtual = 32443 - -Phase 3 Initial Routing - Number of Nodes with overlaps = 0 -Phase 3 Initial Routing | Checksum: 96e098fa - -Time (s): cpu = 00:00:35 ; elapsed = 00:00:30 . Memory (MB): peak = 2279.602 ; gain = 62.793 ; free physical = 167 ; free virtual = 32445 - -Phase 4 Rip-up And Reroute - -Phase 4.1 Global Iteration 0 -Phase 4.1 Global Iteration 0 | Checksum: 96e098fa - -Time (s): cpu = 00:00:35 ; elapsed = 00:00:30 . Memory (MB): peak = 2279.602 ; gain = 62.793 ; free physical = 167 ; free virtual = 32445 -Phase 4 Rip-up And Reroute | Checksum: 96e098fa - -Time (s): cpu = 00:00:35 ; elapsed = 00:00:30 . Memory (MB): peak = 2279.602 ; gain = 62.793 ; free physical = 167 ; free virtual = 32445 - -Phase 5 Delay and Skew Optimization -Phase 5 Delay and Skew Optimization | Checksum: 96e098fa - -Time (s): cpu = 00:00:35 ; elapsed = 00:00:30 . Memory (MB): peak = 2279.602 ; gain = 62.793 ; free physical = 167 ; free virtual = 32445 - -Phase 6 Post Hold Fix - -Phase 6.1 Hold Fix Iter -Phase 6.1 Hold Fix Iter | Checksum: 96e098fa - -Time (s): cpu = 00:00:35 ; elapsed = 00:00:30 . Memory (MB): peak = 2279.602 ; gain = 62.793 ; free physical = 167 ; free virtual = 32445 -Phase 6 Post Hold Fix | Checksum: 96e098fa - -Time (s): cpu = 00:00:35 ; elapsed = 00:00:30 . Memory (MB): peak = 2279.602 ; gain = 62.793 ; free physical = 167 ; free virtual = 32445 - -Phase 7 Route finalize - -Router Utilization Summary - Global Vertical Routing Utilization = 0.000362431 % - Global Horizontal Routing Utilization = 0.00025355 % - Routable Net Status* - *Does not include unroutable nets such as driverless and loadless. - Run report_route_status for detailed report. - Number of Failed Nets = 0 - Number of Unrouted Nets = 0 - Number of Partially Routed Nets = 0 - Number of Node Overlaps = 0 - -Congestion Report -North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. -South Dir 1x1 Area, Max Cong = 0.900901%, No Congested Regions. -East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. -West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. - ------------------------------- -Reporting congestion hotspots ------------------------------- -Direction: North ----------------- -Congested clusters found at Level 0 -Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 -Direction: South ----------------- -Congested clusters found at Level 0 -Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 -Direction: East ----------------- -Congested clusters found at Level 0 -Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 -Direction: West ----------------- -Congested clusters found at Level 0 -Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 - -Phase 7 Route finalize | Checksum: 96e098fa - -Time (s): cpu = 00:00:35 ; elapsed = 00:00:30 . Memory (MB): peak = 2279.602 ; gain = 62.793 ; free physical = 166 ; free virtual = 32444 - -Phase 8 Verifying routed nets - - Verification completed successfully -Phase 8 Verifying routed nets | Checksum: 96e098fa - -Time (s): cpu = 00:00:35 ; elapsed = 00:00:30 . Memory (MB): peak = 2279.602 ; gain = 62.793 ; free physical = 167 ; free virtual = 32445 - -Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: 3d9d23af - -Time (s): cpu = 00:00:35 ; elapsed = 00:00:30 . Memory (MB): peak = 2279.602 ; gain = 62.793 ; free physical = 167 ; free virtual = 32445 -INFO: [Route 35-16] Router Completed Successfully - -Time (s): cpu = 00:00:35 ; elapsed = 00:00:30 . Memory (MB): peak = 2279.602 ; gain = 62.793 ; free physical = 200 ; free virtual = 32478 - -Routing Is Done. -INFO: [Common 17-83] Releasing license: Implementation -51 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. -route_design completed successfully -route_design: Time (s): cpu = 00:00:38 ; elapsed = 00:00:33 . Memory (MB): peak = 2279.602 ; gain = 62.793 ; free physical = 200 ; free virtual = 32478 -WARNING: [Constraints 18-5210] No constraint will be written out. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2279.602 ; gain = 0.000 ; free physical = 199 ; free virtual = 32478 -INFO: [Common 17-1381] The checkpoint '/home/colin/Desktop/PL-Sensors/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_routed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file pulsegen_v_drc_routed.rpt -pb pulsegen_v_drc_routed.pb -rpx pulsegen_v_drc_routed.rpx -Command: report_drc -file pulsegen_v_drc_routed.rpt -pb pulsegen_v_drc_routed.pb -rpx pulsegen_v_drc_routed.rpx -INFO: [DRC 23-27] Running DRC with 8 threads -INFO: [Coretcl 2-168] The results of DRC are in file /home/colin/Desktop/PL-Sensors/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_drc_routed.rpt. -report_drc completed successfully -INFO: [runtcl-4] Executing : report_methodology -file pulsegen_v_methodology_drc_routed.rpt -pb pulsegen_v_methodology_drc_routed.pb -rpx pulsegen_v_methodology_drc_routed.rpx -Command: report_methodology -file pulsegen_v_methodology_drc_routed.rpt -pb pulsegen_v_methodology_drc_routed.pb -rpx pulsegen_v_methodology_drc_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [DRC 23-133] Running Methodology with 8 threads -INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/colin/Desktop/PL-Sensors/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_methodology_drc_routed.rpt. -report_methodology completed successfully -INFO: [runtcl-4] Executing : report_power -file pulsegen_v_power_routed.rpt -pb pulsegen_v_power_summary_routed.pb -rpx pulsegen_v_power_routed.rpx -Command: report_power -file pulsegen_v_power_routed.rpt -pb pulsegen_v_power_summary_routed.pb -rpx pulsegen_v_power_routed.rpx -WARNING: [Power 33-232] No user defined clocks were found in the design! -Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate -INFO: [Timing 38-35] Done setting XDC timing constraints. -Running Vector-less Activity Propagation... - -Finished Running Vector-less Activity Propagation -62 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered. -report_power completed successfully -INFO: [runtcl-4] Executing : report_route_status -file pulsegen_v_route_status.rpt -pb pulsegen_v_route_status.pb -INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file pulsegen_v_timing_summary_routed.rpt -pb pulsegen_v_timing_summary_routed.pb -rpx pulsegen_v_timing_summary_routed.rpx -warn_on_violation -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs -WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. -INFO: [runtcl-4] Executing : report_incremental_reuse -file pulsegen_v_incremental_reuse_routed.rpt -INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. -INFO: [runtcl-4] Executing : report_clock_utilization -file pulsegen_v_clock_utilization_routed.rpt -INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file pulsegen_v_bus_skew_routed.rpt -pb pulsegen_v_bus_skew_routed.pb -rpx pulsegen_v_bus_skew_routed.rpx -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs -INFO: [Common 17-206] Exiting Vivado at Thu Dec 24 23:25:58 2020... diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_bus_skew_routed.pb b/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_bus_skew_routed.pb deleted file mode 100644 index 3390588d5da71a6f6866045d7ae5646edfab7b0e..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 30 lcmd;LGcqu=&@-IGEZ|gHtWcbtTCPx(T3nh_Qapp10RVJW2(bVF diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_bus_skew_routed.rpt b/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_bus_skew_routed.rpt deleted file mode 100644 index bcfb595..0000000 --- a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_bus_skew_routed.rpt +++ /dev/null @@ -1,15 +0,0 @@ -Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018 -| Date : Thu Dec 24 23:25:57 2020 -| Host : colindrewes running 64-bit Ubuntu 18.04.5 LTS -| Command : report_bus_skew -warn_on_violation -file pulsegen_v_bus_skew_routed.rpt -pb pulsegen_v_bus_skew_routed.pb -rpx pulsegen_v_bus_skew_routed.rpx -| Design : pulsegen_v -| Device : 7z020-clg400 -| Speed File : -1 PRODUCTION 1.11 2014-09-11 ---------------------------------------------------------------------------------------------------------------------------------------------------------------- - -Bus Skew Report - -No bus skew constraints - diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_bus_skew_routed.rpx b/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_bus_skew_routed.rpx deleted file mode 100644 index 1d835a9759a251302466776fd210e5e98aed5dea..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1053 zcmd6mJxtp`6vyAYKoXtWf}##-hU&y*1|!=fkVcAxk_^xah!R7qF0PXt!NRd!e}ojN zQkP0Bl@Jr%P^XNHjEtxgBO@att<zV$CxkvSi(a^_-&jm}z&Jib=ORTRRNC^c?#|iq3CdZlnpE`X?lQkY#T_;2TrAA-Tsk$i&tJZkm zYV-2)fubpl)y?*v+2!T7-OVfFzv*$_Da$I8>W$6XR#jiy++ga0sxr~-ysW&CRdt@~ zG_}qBK=dH9wr%yzj?4O^X=qGZ%F8V)oEK8BStYXU4%4(kaVfvVM91{qh`o#)rsjoS zNzqD+MYdkkWAP$obgE{CJd=&78gDaAP>Ut4P%117LR08hq^YVa#_V(++Jq`I!YLDP z#TKf^&Lgs#fn2I*IY!SMu-}t~(zF7_^vZ2&72e=G*aZ&;@Co4%;RxXb;S^zrc!qF} zc!6+ScqlUm>!@dn`z z@r2+h!6AV&0_TKW5V$08Mc|s?4S`z%cLdY%lZRQz0)w2`KbH2Kjakeh0|`VYVFgxU HE3W?!Es{`# diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_clock_utilization_routed.rpt b/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_clock_utilization_routed.rpt deleted file mode 100644 index d0b15b7..0000000 --- a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_clock_utilization_routed.rpt +++ /dev/null @@ -1,145 +0,0 @@ -Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018 -| Date : Thu Dec 24 23:25:57 2020 -| Host : colindrewes running 64-bit Ubuntu 18.04.5 LTS -| Command : report_clock_utilization -file pulsegen_v_clock_utilization_routed.rpt -| Design : pulsegen_v -| Device : 7z020-clg400 -| Speed File : -1 PRODUCTION 1.11 2014-09-11 ----------------------------------------------------------------------------------------- - -Clock Utilization Report - -Table of Contents ------------------ -1. Clock Primitive Utilization -2. Global Clock Resources -3. Global Clock Source Details -4. Clock Regions: Key Resource Utilization -5. Clock Regions : Global Clock Summary -6. Device Cell Placement Summary for Global Clock g0 -7. Clock Region Cell Placement per Global Clock: Region X0Y0 - -1. Clock Primitive Utilization ------------------------------- - -+----------+------+-----------+-----+--------------+--------+ -| Type | Used | Available | LOC | Clock Region | Pblock | -+----------+------+-----------+-----+--------------+--------+ -| BUFGCTRL | 1 | 32 | 0 | 0 | 0 | -| BUFH | 0 | 72 | 0 | 0 | 0 | -| BUFIO | 0 | 16 | 0 | 0 | 0 | -| BUFMR | 0 | 8 | 0 | 0 | 0 | -| BUFR | 0 | 16 | 0 | 0 | 0 | -| MMCM | 0 | 4 | 0 | 0 | 0 | -| PLL | 0 | 4 | 0 | 0 | 0 | -+----------+------+-----------+-----+--------------+--------+ - - -2. Global Clock Resources -------------------------- - -+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ -| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | -+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ -| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 3 | 0 | | | clk_IBUF_BUFG_inst/O | clk_IBUF_BUFG | -+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ -* Clock Loads column represents the clock pin loads (pin count) -** Non-Clock Loads column represents the non-clock pin loads (pin count) - - -3. Global Clock Source Details ------------------------------- - -+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ -| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | -+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ -| src0 | g0 | IBUF/O | None | IOB_X0Y28 | X0Y0 | 1 | 0 | | | clk_IBUF_inst/O | clk_IBUF | -+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ -* Clock Loads column represents the clock pin loads (pin count) -** Non-Clock Loads column represents the non-clock pin loads (pin count) - - -4. Clock Regions: Key Resource Utilization ------------------------------------------- - -+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ -| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | -+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ -| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | -+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ -| X0Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 3 | 2500 | 3 | 1000 | 0 | 60 | 0 | 30 | 0 | 60 | -| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 3200 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 40 | -| X0Y1 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | -| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2600 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 40 | -| X0Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | -| X1Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2600 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 40 | -+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ -* Global Clock column represents track count; while other columns represents cell counts - - -5. Clock Regions : Global Clock Summary ---------------------------------------- - -All Modules -+----+----+----+ -| | X0 | X1 | -+----+----+----+ -| Y2 | 0 | 0 | -| Y1 | 0 | 0 | -| Y0 | 1 | 0 | -+----+----+----+ - - -6. Device Cell Placement Summary for Global Clock g0 ----------------------------------------------------- - -+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ -| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | -+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ -| g0 | BUFG/O | n/a | | | | 3 | 0 | 0 | 0 | clk_IBUF_BUFG | -+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ -* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources -** IO Loads column represents load cell count of IO types -*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) -**** GT Loads column represents load cell count of GT types - - -+----+----+----+ -| | X0 | X1 | -+----+----+----+ -| Y2 | 0 | 0 | -| Y1 | 0 | 0 | -| Y0 | 3 | 0 | -+----+----+----+ - - -7. Clock Region Cell Placement per Global Clock: Region X0Y0 ------------------------------------------------------------- - -+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ -| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | -+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ -| g0 | n/a | BUFG/O | None | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG | -+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ -* Clock Loads column represents the clock pin loads (pin count) -** Non-Clock Loads column represents the non-clock pin loads (pin count) -*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts - - - -# Location of BUFG Primitives -set_property LOC BUFGCTRL_X0Y0 [get_cells clk_IBUF_BUFG_inst] - -# Location of IO Primitives which is load of clock spine - -# Location of clock ports -set_property LOC IOB_X0Y28 [get_ports clk] - -# Clock net "clk_IBUF_BUFG" driven by instance "clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0" -#startgroup -create_pblock {CLKAG_clk_IBUF_BUFG} -add_cells_to_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_IBUF_BUFG"}]]] -resize_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0} -#endgroup diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_control_sets_placed.rpt b/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_control_sets_placed.rpt deleted file mode 100644 index af2938e..0000000 --- a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_control_sets_placed.rpt +++ /dev/null @@ -1,67 +0,0 @@ -Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018 -| Date : Thu Dec 24 23:25:15 2020 -| Host : colindrewes running 64-bit Ubuntu 18.04.5 LTS -| Command : report_control_sets -verbose -file pulsegen_v_control_sets_placed.rpt -| Design : pulsegen_v -| Device : xc7z020 ---------------------------------------------------------------------------------------- - -Control Set Information - -Table of Contents ------------------ -1. Summary -2. Histogram -3. Flip-Flop Distribution -4. Detailed Control Set Information - -1. Summary ----------- - -+----------------------------------------------------------+-------+ -| Status | Count | -+----------------------------------------------------------+-------+ -| Number of unique control sets | 2 | -| Unused register locations in slices containing registers | 10 | -+----------------------------------------------------------+-------+ - - -2. Histogram ------------- - -+--------+--------------+ -| Fanout | Control Sets | -+--------+--------------+ -| 2 | 1 | -| 4 | 1 | -+--------+--------------+ - - -3. Flip-Flop Distribution -------------------------- - -+--------------+-----------------------+------------------------+-----------------+--------------+ -| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | -+--------------+-----------------------+------------------------+-----------------+--------------+ -| No | No | No | 4 | 1 | -| No | No | Yes | 0 | 0 | -| No | Yes | No | 2 | 1 | -| Yes | No | No | 0 | 0 | -| Yes | No | Yes | 0 | 0 | -| Yes | Yes | No | 0 | 0 | -+--------------+-----------------------+------------------------+-----------------+--------------+ - - -4. Detailed Control Set Information ------------------------------------ - -+----------------+---------------+------------------+------------------+----------------+ -| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | -+----------------+---------------+------------------+------------------+----------------+ -| clk_IBUF_BUFG | | O2 | 1 | 2 | -| clk_IBUF_BUFG | | | 1 | 4 | -+----------------+---------------+------------------+------------------+----------------+ - - diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_drc_opted.pb b/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_drc_opted.pb deleted file mode 100644 index 0158a2ad826bcd75c8436a6a29252340aee67559..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 37 scmd;LGcqtV(KDRH% - Ruledeck: default - Max violations: - Violations found: 3 -+--------+------------------+----------------------------+------------+ -| Rule | Severity | Description | Violations | -+--------+------------------+----------------------------+------------+ -| NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 | -| UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 | -| ZPS7-1 | Warning | PS7 block required | 1 | -+--------+------------------+----------------------------+------------+ - -2. REPORT DETAILS ------------------ -NSTD-1#1 Critical Warning -Unspecified I/O Standard -10 out of 10 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: O[7:0], clk, valid_out. -Related violations: - -UCIO-1#1 Critical Warning -Unconstrained Logical Port -10 out of 10 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: O[7:0], clk, valid_out. -Related violations: - -ZPS7-1#1 Warning -PS7 block required -The PS7 cell must be used in this Zynq design in order to enable correct default configuration. -Related violations: - - diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_drc_opted.rpx b/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_drc_opted.rpx deleted file mode 100644 index b13a398b79cf2d42692c6bf02c58c12a23e1d833..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 4260 zcmeHL-)dVo7`J0^yp%H2Q3&46M|aVrxM#83wIg>)oIy&6gYBfOp&0ob*+=A9I+b+n zgl(|P-VDYbVNb9}*vsq%cC*XvC!I5I9$hGdtgyuwvL$``^wal8KYjkNR4Uc(*6%i| z?XA|6;L*L?$GgK*p?ch8i8Z^JUaPc%_MP=KOAMcIIh+k69S&7$c@*gMV*OWq-j6G3 z>7w*?dF6Gv{B61PUFBA%w?~DRA6KzSxxUhrp`n0tBdbPDhDzl`5)=*}+UulY!v~kew z4|a|^JH5^(%~+Cgy5HIVZ0F=~aKA}H8p~PaR57HXgg*azZKB zW2L7|hP+7*0}Ldfe*$Y==K6_WSk0##5DYg3kcds$gp*Z%uZYh?$ep;`*#S}#5RIFk z$0CeLSi(UH5bz!i6na_%2G(F|CRBn`CEA{0*;#hNqdMrycfL5v%dt< zvLZtpQdz=r)pW{b#G}ooj~ah=H;9niCd2J8)e265@%#Iy`@Ms~=k!Gpv0u^I1OhGv z!kCBWhVuA)84w+H2m9OfJmwN=onxINPQ{Exih95Xr;as)U9!+-n$rdkCIKZZlVLp6 zPGArw&T|e3u(2r0{Zb4$8#4+lgvKI)@nlrUFk6hk(3EQaFjnfE5L7fr4DsO~?m*C| ze!^iB(=oMAh~2X%zWv0vkA3^dw{73HeEWu!{l2==+VaiM)z;drTBTlTl)F@VP+GfPtD{pv zj{EKhwFbKHEwbGWet89lpX?oU!QqV)&>&bav6H2Z!|vW@K}-K*mQIDlizqkGb+fbqsSwQW9uv94EiGu;JuBXxr - Ruledeck: default - Max violations: - Violations found: 3 -+--------+------------------+----------------------------+------------+ -| Rule | Severity | Description | Violations | -+--------+------------------+----------------------------+------------+ -| NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 | -| UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 | -| ZPS7-1 | Warning | PS7 block required | 1 | -+--------+------------------+----------------------------+------------+ - -2. REPORT DETAILS ------------------ -NSTD-1#1 Critical Warning -Unspecified I/O Standard -10 out of 10 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: O[7:0], clk, valid_out. -Related violations: - -UCIO-1#1 Critical Warning -Unconstrained Logical Port -10 out of 10 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: O[7:0], clk, valid_out. -Related violations: - -ZPS7-1#1 Warning -PS7 block required -The PS7 cell must be used in this Zynq design in order to enable correct default configuration. -Related violations: - - diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_drc_routed.rpx b/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_drc_routed.rpx deleted file mode 100644 index b2810b108394c21650945fcbae7a2a429cacd83d..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 4261 zcmeHL-EJF26t-i@F{vu7qDsZw9F>bEmAk|)v?zC}9i&uI9NA7P8dcVKckCTyJ+qye zwG#mnm%TwkJOWR^Bk(f305@F1H?xbus6-V~s07KyBs+8FoNvz0d~@ZkDiQ9gz9sXCDwGXyisWd?OX4sSz`E<%h7xk>2Rb~W_c9o^!(1R_<1+3 zq^0xH*X6ZWn_!vLgz#6Qre0a9v^A6&?suAECvEQc z2E*OM?ry)kMRS&9obGk^KHEJ$7~X4=kj8QrIaSQ<)x?YuQwjS8k}%&C&@dK;X6%AO z_Pdc#Nz0`bN|Msh6{=avtQd<#*b7<+8k z2xA_e8OrnXML=}e8}9AUvzSY$b%Aw(I1zIeDe40of;!O*e#t_cX-=CwmHJImAbQgab*R z`UQtg%+dr&C2j6QKnUnat1%{#v?!__>YYB`*?!TaFga_wdJxeF1sFX2;kp#BOYyoC z|K(CdA@)um`SBA!e(cAGer)@(<;T~Q?Dy5R*0vvhuC_LA)GGB#quis?{nEzGS{)x1 z)VTkAuhzilJIiW!lV4uK;m4i*9yq*l3>pNhYUZwMIw;ur2p37amdkh+|EYQji+fg( z>hBmiQDJ^pEiGBvJm__{3R?OfvvevXUPQTju9~F{NQK~b_n627ZfQx=?pg8XJiP+@ zY8X1tz5fhDzbQq3a~VZn*V#XP4X-5Z6~BhB>+CJQgkMus+?cTyK8sp|aLu>Og6PlxG&euHMj)r*YJDHH9SDR(V(wIAbjnI$e{l)VO`4acH p@8~e6bcB8t%?6hYy}+_Z#0}5zZvl7dPsB7stA|!GczV?aeglizz)b)E diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_io_placed.rpt b/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_io_placed.rpt deleted file mode 100644 index f8e33cd..0000000 --- a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_io_placed.rpt +++ /dev/null @@ -1,442 +0,0 @@ -Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018 -| Date : Thu Dec 24 23:25:14 2020 -| Host : colindrewes running 64-bit Ubuntu 18.04.5 LTS -| Command : report_io -file pulsegen_v_io_placed.rpt -| Design : pulsegen_v -| Device : xc7z020 -| Speed File : -1 -| Package : clg400 -| Package Version : FINAL 2012-06-26 -| Package Pin Delay Version : VERS. 2.0 2012-06-26 -------------------------------------------------------------------------------------------------- - -IO Information - -Table of Contents ------------------ -1. Summary -2. IO Assignments by Package Pin - -1. Summary ----------- - -+---------------+ -| Total User IO | -+---------------+ -| 11 | -+---------------+ - - -2. IO Assignments by Package Pin --------------------------------- - -+------------+-------------+------------+-------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ -| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | -+------------+-------------+------------+-------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ -| A1 | | | PS_DDR_DM0_502 | PSS IO | | | | | | | | | | | | | | | | -| A2 | | | PS_DDR_DQ2_502 | PSS IO | | | | | | | | | | | | | | | | -| A3 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | -| A4 | | | PS_DDR_DQ3_502 | PSS IO | | | | | | | | | | | | | | | | -| A5 | | | PS_MIO6_500 | PSS IO | | | | | | | | | | | | | | | | -| A6 | | | PS_MIO5_500 | PSS IO | | | | | | | | | | | | | | | | -| A7 | | | PS_MIO1_500 | PSS IO | | | | | | | | | | | | | | | | -| A8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| A9 | | | PS_MIO43_501 | PSS IO | | | | | | | | | | | | | | | | -| A10 | | | PS_MIO37_501 | PSS IO | | | | | | | | | | | | | | | | -| A11 | | | PS_MIO36_501 | PSS IO | | | | | | | | | | | | | | | | -| A12 | | | PS_MIO34_501 | PSS IO | | | | | | | | | | | | | | | | -| A13 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | | -| A14 | | | PS_MIO32_501 | PSS IO | | | | | | | | | | | | | | | | -| A15 | | | PS_MIO26_501 | PSS IO | | | | | | | | | | | | | | | | -| A16 | | | PS_MIO24_501 | PSS IO | | | | | | | | | | | | | | | | -| A17 | | | PS_MIO20_501 | PSS IO | | | | | | | | | | | | | | | | -| A18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| A19 | | | PS_MIO16_501 | PSS IO | | | | | | | | | | | | | | | | -| A20 | | High Range | IO_L2N_T0_AD8N_35 | User IO | | 35 | | | | | | | | | | | | | | -| B1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| B2 | | | PS_DDR_DQS_N0_502 | PSS IO | | | | | | | | | | | | | | | | -| B3 | | | PS_DDR_DQ1_502 | PSS IO | | | | | | | | | | | | | | | | -| B4 | | | PS_DDR_DRST_B_502 | PSS IO | | | | | | | | | | | | | | | | -| B5 | | | PS_MIO9_500 | PSS IO | | | | | | | | | | | | | | | | -| B6 | | | VCCO_MIO0_500 | VCCO | | | | | | | any** | | | | | | | | | -| B7 | | | PS_MIO4_500 | PSS IO | | | | | | | | | | | | | | | | -| B8 | | | PS_MIO2_500 | PSS IO | | | | | | | | | | | | | | | | -| B9 | | | PS_MIO51_501 | PSS IO | | | | | | | | | | | | | | | | -| B10 | | | PS_SRST_B_501 | PSS IO | | | | | | | | | | | | | | | | -| B11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| B12 | | | PS_MIO48_501 | PSS IO | | | | | | | | | | | | | | | | -| B13 | | | PS_MIO50_501 | PSS IO | | | | | | | | | | | | | | | | -| B14 | | | PS_MIO47_501 | PSS IO | | | | | | | | | | | | | | | | -| B15 | | | PS_MIO45_501 | PSS IO | | | | | | | | | | | | | | | | -| B16 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | | -| B17 | | | PS_MIO22_501 | PSS IO | | | | | | | | | | | | | | | | -| B18 | | | PS_MIO18_501 | PSS IO | | | | | | | | | | | | | | | | -| B19 | | High Range | IO_L2P_T0_AD8P_35 | User IO | | 35 | | | | | | | | | | | | | | -| B20 | | High Range | IO_L1N_T0_AD0N_35 | User IO | | 35 | | | | | | | | | | | | | | -| C1 | | | PS_DDR_DQ6_502 | PSS IO | | | | | | | | | | | | | | | | -| C2 | | | PS_DDR_DQS_P0_502 | PSS IO | | | | | | | | | | | | | | | | -| C3 | | | PS_DDR_DQ0_502 | PSS IO | | | | | | | | | | | | | | | | -| C4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| C5 | | | PS_MIO14_500 | PSS IO | | | | | | | | | | | | | | | | -| C6 | | | PS_MIO11_500 | PSS IO | | | | | | | | | | | | | | | | -| C7 | | | PS_POR_B_500 | PSS IO | | | | | | | | | | | | | | | | -| C8 | | | PS_MIO15_500 | PSS IO | | | | | | | | | | | | | | | | -| C9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| C10 | | | PS_MIO52_501 | PSS IO | | | | | | | | | | | | | | | | -| C11 | | | PS_MIO53_501 | PSS IO | | | | | | | | | | | | | | | | -| C12 | | | PS_MIO49_501 | PSS IO | | | | | | | | | | | | | | | | -| C13 | | | PS_MIO29_501 | PSS IO | | | | | | | | | | | | | | | | -| C14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| C15 | | | PS_MIO30_501 | PSS IO | | | | | | | | | | | | | | | | -| C16 | | | PS_MIO28_501 | PSS IO | | | | | | | | | | | | | | | | -| C17 | | | PS_MIO41_501 | PSS IO | | | | | | | | | | | | | | | | -| C18 | | | PS_MIO39_501 | PSS IO | | | | | | | | | | | | | | | | -| C19 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | -| C20 | | High Range | IO_L1P_T0_AD0P_35 | User IO | | 35 | | | | | | | | | | | | | | -| D1 | | | PS_DDR_DQ5_502 | PSS IO | | | | | | | | | | | | | | | | -| D2 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | -| D3 | | | PS_DDR_DQ4_502 | PSS IO | | | | | | | | | | | | | | | | -| D4 | | | PS_DDR_A13_502 | PSS IO | | | | | | | | | | | | | | | | -| D5 | | | PS_MIO8_500 | PSS IO | | | | | | | | | | | | | | | | -| D6 | | | PS_MIO3_500 | PSS IO | | | | | | | | | | | | | | | | -| D7 | | | VCCO_MIO0_500 | VCCO | | | | | | | any** | | | | | | | | | -| D8 | | | PS_MIO7_500 | PSS IO | | | | | | | | | | | | | | | | -| D9 | | | PS_MIO12_500 | PSS IO | | | | | | | | | | | | | | | | -| D10 | | | PS_MIO19_501 | PSS IO | | | | | | | | | | | | | | | | -| D11 | | | PS_MIO23_501 | PSS IO | | | | | | | | | | | | | | | | -| D12 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | | -| D13 | | | PS_MIO27_501 | PSS IO | | | | | | | | | | | | | | | | -| D14 | | | PS_MIO40_501 | PSS IO | | | | | | | | | | | | | | | | -| D15 | | | PS_MIO33_501 | PSS IO | | | | | | | | | | | | | | | | -| D16 | | | PS_MIO46_501 | PSS IO | | | | | | | | | | | | | | | | -| D17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| D18 | | High Range | IO_L3N_T0_DQS_AD1N_35 | User IO | | 35 | | | | | | | | | | | | | | -| D19 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | -| D20 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | | -| E1 | | | PS_DDR_DQ7_502 | PSS IO | | | | | | | | | | | | | | | | -| E2 | | | PS_DDR_DQ8_502 | PSS IO | | | | | | | | | | | | | | | | -| E3 | | | PS_DDR_DQ9_502 | PSS IO | | | | | | | | | | | | | | | | -| E4 | | | PS_DDR_A12_502 | PSS IO | | | | | | | | | | | | | | | | -| E5 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | -| E6 | | | PS_MIO0_500 | PSS IO | | | | | | | | | | | | | | | | -| E7 | | | PS_CLK_500 | PSS Clock | | | | | | | | | | | | | | | | -| E8 | | | PS_MIO13_500 | PSS IO | | | | | | | | | | | | | | | | -| E9 | | | PS_MIO10_500 | PSS IO | | | | | | | | | | | | | | | | -| E10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| E11 | | | PS_MIO_VREF_501 | PSS IO | | | | | | | | | | | | | | | | -| E12 | | | PS_MIO42_501 | PSS IO | | | | | | | | | | | | | | | | -| E13 | | | PS_MIO38_501 | PSS IO | | | | | | | | | | | | | | | | -| E14 | | | PS_MIO17_501 | PSS IO | | | | | | | | | | | | | | | | -| E15 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | | -| E16 | | | PS_MIO31_501 | PSS IO | | | | | | | | | | | | | | | | -| E17 | | High Range | IO_L3P_T0_DQS_AD1P_35 | User IO | | 35 | | | | | | | | | | | | | | -| E18 | | High Range | IO_L5P_T0_AD9P_35 | User IO | | 35 | | | | | | | | | | | | | | -| E19 | | High Range | IO_L5N_T0_AD9N_35 | User IO | | 35 | | | | | | | | | | | | | | -| E20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| F1 | | | PS_DDR_DM1_502 | PSS IO | | | | | | | | | | | | | | | | -| F2 | | | PS_DDR_DQS_N1_502 | PSS IO | | | | | | | | | | | | | | | | -| F3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| F4 | | | PS_DDR_A14_502 | PSS IO | | | | | | | | | | | | | | | | -| F5 | | | PS_DDR_A10_502 | PSS IO | | | | | | | | | | | | | | | | -| F6 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | -| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| F8 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | | | | -| F9 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | -| F10 | | | RSVDGND | GND | | | | | | | | | | | | | | | | -| F11 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | -| F12 | | | PS_MIO35_501 | PSS IO | | | | | | | | | | | | | | | | -| F13 | | | PS_MIO44_501 | PSS IO | | | | | | | | | | | | | | | | -| F14 | | | PS_MIO21_501 | PSS IO | | | | | | | | | | | | | | | | -| F15 | | | PS_MIO25_501 | PSS IO | | | | | | | | | | | | | | | | -| F16 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | -| F17 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | -| F18 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | -| F19 | | High Range | IO_L15P_T2_DQS_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | | -| F20 | | High Range | IO_L15N_T2_DQS_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | | -| G1 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | -| G2 | | | PS_DDR_DQS_P1_502 | PSS IO | | | | | | | | | | | | | | | | -| G3 | | | PS_DDR_DQ10_502 | PSS IO | | | | | | | | | | | | | | | | -| G4 | | | PS_DDR_A11_502 | PSS IO | | | | | | | | | | | | | | | | -| G5 | | | PS_DDR_VRN_502 | PSS IO | | | | | | | | | | | | | | | | -| G6 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | -| G7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | | -| G8 | | | VCCPLL | PSS VCCPLL | | | | | | | | | | | | | | | | -| G9 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | | | | -| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | -| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| G13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| G14 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | | -| G15 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | -| G16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| G17 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | -| G18 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | -| G19 | | High Range | IO_L18P_T2_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | | -| G20 | | High Range | IO_L18N_T2_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | | -| H1 | | | PS_DDR_DQ14_502 | PSS IO | | | | | | | | | | | | | | | | -| H2 | | | PS_DDR_DQ13_502 | PSS IO | | | | | | | | | | | | | | | | -| H3 | | | PS_DDR_DQ11_502 | PSS IO | | | | | | | | | | | | | | | | -| H4 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | -| H5 | | | PS_DDR_VRP_502 | PSS IO | | | | | | | | | | | | | | | | -| H6 | | | PS_DDR_VREF0_502 | PSS IO | | | | | | | | | | | | | | | | -| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| H8 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | | | | -| H9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| H10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | -| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| H12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| H13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| H14 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | -| H15 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | -| H16 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | -| H17 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | -| H18 | | High Range | IO_L14N_T2_AD4N_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | -| H19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| H20 | | High Range | IO_L17N_T2_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | | -| J1 | | | PS_DDR_DQ15_502 | PSS IO | | | | | | | | | | | | | | | | -| J2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| J3 | | | PS_DDR_DQ12_502 | PSS IO | | | | | | | | | | | | | | | | -| J4 | | | PS_DDR_A9_502 | PSS IO | | | | | | | | | | | | | | | | -| J5 | | | PS_DDR_BA2_502 | PSS IO | | | | | | | | | | | | | | | | -| J6 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | -| J7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | | -| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| J9 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | -| J10 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | -| J11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | -| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| J13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| J14 | | High Range | IO_L20N_T3_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | | -| J15 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | | -| J16 | | High Range | IO_L24N_T3_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | | -| J17 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | -| J18 | | High Range | IO_L14P_T2_AD4P_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | -| J19 | | High Range | IO_L10N_T1_AD11N_35 | User IO | | 35 | | | | | | | | | | | | | | -| J20 | | High Range | IO_L17P_T2_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | | -| K1 | | | PS_DDR_A8_502 | PSS IO | | | | | | | | | | | | | | | | -| K2 | | | PS_DDR_A1_502 | PSS IO | | | | | | | | | | | | | | | | -| K3 | | | PS_DDR_A3_502 | PSS IO | | | | | | | | | | | | | | | | -| K4 | | | PS_DDR_A7_502 | PSS IO | | | | | | | | | | | | | | | | -| K5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| K6 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | -| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| K8 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | | | | -| K9 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | -| K10 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | -| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| K12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| K13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| K14 | | High Range | IO_L20P_T3_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | | -| K15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| K16 | | High Range | IO_L24P_T3_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | | -| K17 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | -| K18 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | -| K19 | | High Range | IO_L10P_T1_AD11P_35 | User IO | | 35 | | | | | | | | | | | | | | -| K20 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | -| L1 | | | PS_DDR_A5_502 | PSS IO | | | | | | | | | | | | | | | | -| L2 | | | PS_DDR_CKP_502 | PSS IO | | | | | | | | | | | | | | | | -| L3 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | -| L4 | | | PS_DDR_A6_502 | PSS IO | | | | | | | | | | | | | | | | -| L5 | | | PS_DDR_BA0_502 | PSS IO | | | | | | | | | | | | | | | | -| L6 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | -| L7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | | -| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| L9 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | -| L10 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | -| L11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | -| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| L13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| L14 | | High Range | IO_L22P_T3_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | | -| L15 | | High Range | IO_L22N_T3_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | | -| L16 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | -| L17 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | -| L18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| L19 | | High Range | IO_L9P_T1_DQS_AD3P_35 | User IO | | 35 | | | | | | | | | | | | | | -| L20 | | High Range | IO_L9N_T1_DQS_AD3N_35 | User IO | | 35 | | | | | | | | | | | | | | -| M1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| M2 | | | PS_DDR_CKN_502 | PSS IO | | | | | | | | | | | | | | | | -| M3 | | | PS_DDR_A2_502 | PSS IO | | | | | | | | | | | | | | | | -| M4 | | | PS_DDR_A4_502 | PSS IO | | | | | | | | | | | | | | | | -| M5 | | | PS_DDR_WE_B_502 | PSS IO | | | | | | | | | | | | | | | | -| M6 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | | -| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| M8 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | | | | -| M9 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | -| M10 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | -| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| M12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| M13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| M14 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | -| M15 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | -| M16 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | -| M17 | | High Range | IO_L8P_T1_AD10P_35 | User IO | | 35 | | | | | | | | | | | | | | -| M18 | | High Range | IO_L8N_T1_AD10N_35 | User IO | | 35 | | | | | | | | | | | | | | -| M19 | | High Range | IO_L7P_T1_AD2P_35 | User IO | | 35 | | | | | | | | | | | | | | -| M20 | | High Range | IO_L7N_T1_AD2N_35 | User IO | | 35 | | | | | | | | | | | | | | -| N1 | | | PS_DDR_CS_B_502 | PSS IO | | | | | | | | | | | | | | | | -| N2 | | | PS_DDR_A0_502 | PSS IO | | | | | | | | | | | | | | | | -| N3 | | | PS_DDR_CKE_502 | PSS IO | | | | | | | | | | | | | | | | -| N4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| N5 | | | PS_DDR_ODT_502 | PSS IO | | | | | | | | | | | | | | | | -| N6 | | | RSVDVCC3 | Reserved | | | | | | | | | | | | | | | | -| N7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | | -| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| N9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | -| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| N11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | -| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| N13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| N14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| N15 | | High Range | IO_L21P_T3_DQS_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | | -| N16 | | High Range | IO_L21N_T3_DQS_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | | -| N17 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | -| N18 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| N19 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | -| N20 | | High Range | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| P1 | | | PS_DDR_DQ16_502 | PSS IO | | | | | | | | | | | | | | | | -| P2 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | -| P3 | | | PS_DDR_DQ17_502 | PSS IO | | | | | | | | | | | | | | | | -| P4 | | | PS_DDR_RAS_B_502 | PSS IO | | | | | | | | | | | | | | | | -| P5 | | | PS_DDR_CAS_B_502 | PSS IO | | | | | | | | | | | | | | | | -| P6 | | | PS_DDR_VREF1_502 | PSS IO | | | | | | | | | | | | | | | | -| P7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| P8 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | | -| P9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| P10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | -| P11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| P12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| P13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| P14 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| P15 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | -| P16 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | -| P17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| P18 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | -| P19 | | High Range | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| P20 | | High Range | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| R1 | | | PS_DDR_DQ19_502 | PSS IO | | | | | | | | | | | | | | | | -| R2 | | | PS_DDR_DQS_P2_502 | PSS IO | | | | | | | | | | | | | | | | -| R3 | | | PS_DDR_DQ18_502 | PSS IO | | | | | | | | | | | | | | | | -| R4 | | | PS_DDR_BA1_502 | PSS IO | | | | | | | | | | | | | | | | -| R5 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | -| R6 | | | RSVDVCC2 | Reserved | | | | | | | | | | | | | | | | -| R7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | | -| R8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| R9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | -| R10 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | -| R11 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | -| R12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| R13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| R14 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | -| R15 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | -| R16 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | -| R17 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | -| R18 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | -| R19 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | | -| R20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| T1 | | | PS_DDR_DM2_502 | PSS IO | | | | | | | | | | | | | | | | -| T2 | | | PS_DDR_DQS_N2_502 | PSS IO | | | | | | | | | | | | | | | | -| T3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| T4 | | | PS_DDR_DQ20_502 | PSS IO | | | | | | | | | | | | | | | | -| T5 | O[7] | High Range | IO_L19P_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | -| T6 | | | RSVDVCC1 | Reserved | | | | | | | | | | | | | | | | -| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| T8 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | -| T9 | | High Range | IO_L12P_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | -| T10 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| T11 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| T12 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| T13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| T14 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| T15 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| T16 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | -| T17 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | -| T18 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | -| T19 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | | -| T20 | | High Range | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | -| U1 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | -| U2 | | | PS_DDR_DQ22_502 | PSS IO | | | | | | | | | | | | | | | | -| U3 | | | PS_DDR_DQ23_502 | PSS IO | | | | | | | | | | | | | | | | -| U4 | | | PS_DDR_DQ21_502 | PSS IO | | | | | | | | | | | | | | | | -| U5 | O[6] | High Range | IO_L19N_T3_VREF_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | -| U6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| U7 | clk | High Range | IO_L11P_T1_SRCC_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | | -| U8 | | High Range | IO_L17N_T2_13 | User IO | | 13 | | | | | | | | | | | | | | -| U9 | | High Range | IO_L17P_T2_13 | User IO | | 13 | | | | | | | | | | | | | | -| U10 | | High Range | IO_L12N_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | -| U11 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | -| U12 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| U13 | | High Range | IO_L3P_T0_DQS_PUDC_B_34 | User IO | | 34 | | | | | | | | | | | | | | -| U14 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| U15 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| U16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| U17 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | -| U18 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| U19 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| U20 | | High Range | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | -| V1 | | | PS_DDR_DQ24_502 | PSS IO | | | | | | | | | | | | | | | | -| V2 | | | PS_DDR_DQ30_502 | PSS IO | | | | | | | | | | | | | | | | -| V3 | | | PS_DDR_DQ31_502 | PSS IO | | | | | | | | | | | | | | | | -| V4 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | -| V5 | | High Range | IO_L6N_T0_VREF_13 | User IO | | 13 | | | | | | | | | | | | | | -| V6 | O[1] | High Range | IO_L22P_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | -| V7 | | High Range | IO_L11N_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | -| V8 | | High Range | IO_L15P_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | -| V9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| V10 | O[2] | High Range | IO_L21N_T3_DQS_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | -| V11 | O[3] | High Range | IO_L21P_T3_DQS_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | -| V12 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| V13 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | -| V14 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | -| V15 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | -| V16 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | -| V17 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | -| V18 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | -| V19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| V20 | | High Range | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | -| W1 | | | PS_DDR_DQ26_502 | PSS IO | | | | | | | | | | | | | | | | -| W2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| W3 | | | PS_DDR_DQ29_502 | PSS IO | | | | | | | | | | | | | | | | -| W4 | | | PS_DDR_DQS_N3_502 | PSS IO | | | | | | | | | | | | | | | | -| W5 | | | PS_DDR_DQS_P3_502 | PSS IO | | | | | | | | | | | | | | | | -| W6 | O[0] | High Range | IO_L22N_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | -| W7 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | -| W8 | | High Range | IO_L15N_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | -| W9 | | High Range | IO_L16N_T2_13 | User IO | | 13 | | | | | | | | | | | | | | -| W10 | | High Range | IO_L16P_T2_13 | User IO | | 13 | | | | | | | | | | | | | | -| W11 | | High Range | IO_L18P_T2_13 | User IO | | 13 | | | | | | | | | | | | | | -| W12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| W13 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| W14 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | -| W15 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | -| W16 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | -| W17 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | -| W18 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | -| W19 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | -| W20 | | High Range | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | -| Y1 | | | PS_DDR_DM3_502 | PSS IO | | | | | | | | | | | | | | | | -| Y2 | | | PS_DDR_DQ28_502 | PSS IO | | | | | | | | | | | | | | | | -| Y3 | | | PS_DDR_DQ25_502 | PSS IO | | | | | | | | | | | | | | | | -| Y4 | | | PS_DDR_DQ27_502 | PSS IO | | | | | | | | | | | | | | | | -| Y5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| Y6 | | High Range | IO_L13N_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | -| Y7 | | High Range | IO_L13P_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | -| Y8 | | High Range | IO_L14N_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | -| Y9 | | High Range | IO_L14P_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | -| Y10 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | -| Y11 | valid_out | High Range | IO_L18N_T2_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | -| Y12 | O[5] | High Range | IO_L20P_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | -| Y13 | O[4] | High Range | IO_L20N_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | -| Y14 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | -| Y15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| Y16 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | -| Y17 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | -| Y18 | | High Range | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | -| Y19 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | -| Y20 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | -+------------+-------------+------------+-------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ -* Default value -** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. - - diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_methodology_drc_routed.pb b/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_methodology_drc_routed.pb deleted file mode 100644 index e0f8955b965a8fae888d67ffd231ba8ecfecdc25..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 52 zcmd;LGcqtV(=(jJEajV8l98X1pOc?nso - Max violations: - Violations found: 3 -+-----------+----------+-----------------------------+------------+ -| Rule | Severity | Description | Violations | -+-----------+----------+-----------------------------+------------+ -| TIMING-17 | Warning | Non-clocked sequential cell | 3 | -+-----------+----------+-----------------------------+------------+ - -2. REPORT DETAILS ------------------ -TIMING-17#1 Warning -Non-clocked sequential cell -The clock pin O_reg[0]/C is not reached by a timing clock -Related violations: - -TIMING-17#2 Warning -Non-clocked sequential cell -The clock pin count_reg[0]/C is not reached by a timing clock -Related violations: - -TIMING-17#3 Warning -Non-clocked sequential cell -The clock pin count_reg[1]/C is not reached by a timing clock -Related violations: - - diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_methodology_drc_routed.rpx b/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_methodology_drc_routed.rpx deleted file mode 100644 index a293d1c9970c077537efed4b2e31a4ceecb2604b..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 795 zcmb1UU|`@76A+VPGcqtV(=%4$4RDGN%ghf-EiTO|DUJh5b1@t0840Ntl;#wtrl;n` zm&NC%mSp6o+0cT)$ucA(RROG4p&&C)!9TtzH9guOR^M46vsfW7 zzeJ%ZH8D8@Xiie4LZU)RW-ib!h(AWR~03JZmnW1VOrjTq40RZ?z0RV7sS1rt)n7!=nVw05} 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BUFG | 0.006 | 1 | 32 | 3.13 | -| Register | 0.004 | 3 | 106400 | <0.01 | -| Others | 0.000 | 2 | --- | --- | -| Signals | 0.034 | 6 | --- | --- | -| I/O | 0.954 | 10 | 125 | 8.00 | -| Static Power | 0.122 | | | | -| Total | 1.142 | | | | -+----------------+-----------+----------+-----------+-----------------+ - - -1.2 Power Supply Summary ------------------------- - -+-----------+-------------+-----------+-------------+------------+ -| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | -+-----------+-------------+-----------+-------------+------------+ -| Vccint | 1.000 | 0.082 | 0.070 | 0.012 | -| Vccaux | 1.800 | 0.091 | 0.078 | 0.013 | -| Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 | -| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | -| Vcco18 | 1.800 | 0.451 | 0.450 | 0.001 | -| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | -| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | -| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | -| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | -| Vccbram | 1.000 | 0.001 | 0.000 | 0.001 | -| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | -| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | -| MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 | -| Vccpint | 1.000 | 0.024 | 0.000 | 0.024 | -| Vccpaux | 1.800 | 0.010 | 0.000 | 0.010 | -| Vccpll | 1.800 | 0.003 | 0.000 | 0.003 | -| Vcco_ddr | 1.500 | 0.000 | 0.000 | 0.000 | -| Vcco_mio0 | 1.800 | 0.000 | 0.000 | 0.000 | -| Vcco_mio1 | 1.800 | 0.000 | 0.000 | 0.000 | -| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | -+-----------+-------------+-----------+-------------+------------+ - - -1.3 Confidence Level --------------------- - -+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ -| User Input Data | Confidence | Details | Action | -+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ -| Design implementation state | High | Design is routed | | -| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view | -| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | -| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | -| Device models | High | Device models are Production | | -| | | | | -| Overall confidence level | Low | | | -+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ - - -2. Settings ------------ - -2.1 Environment ---------------- - -+-----------------------+------------------------+ -| Ambient Temp (C) | 25.0 | -| ThetaJA (C/W) | 11.5 | -| Airflow (LFM) | 250 | -| Heat Sink | none | -| ThetaSA (C/W) | 0.0 | -| Board Selection | medium (10"x10") | -| # of Board Layers | 8to11 (8 to 11 Layers) | -| Board Temperature (C) | 25.0 | -+-----------------------+------------------------+ - - -2.2 Clock Constraints ---------------------- - -+-------+--------+-----------------+ -| Clock | Domain | Constraint (ns) | -+-------+--------+-----------------+ - - -3. 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zM&y^CE-9eFT0QzF(u}E0hz(pPTJ2(d=G%^L z3+I;hLxI!aV;iu>q5BW5sqIJpP-XI{U1^}*eGks_3=;YdWwejs3ZNK^!OF6-tV77bF)XoFMGRxgOmx{ z8rYwsp)o(^f0*e1Kh^uCJ!1bCFKuCN`EP8{N;Aca$6t*;=6{OuPkKCj6nOS1|9`Om zT~FW5{~zgPPt^7?9=XP!Ng>OQ(x^}KYKr>HUfR`sg{Qm>*6-Sl; diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_timing_summary_routed.pb b/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_timing_summary_routed.pb deleted file mode 100644 index 4526e93..0000000 --- a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_timing_summary_routed.pb +++ /dev/null @@ -1,2 +0,0 @@ - -2012.4’)Timing analysis from Implemented netlist. \ No newline at end of file diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_timing_summary_routed.rpt b/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_timing_summary_routed.rpt deleted file mode 100644 index f88e755..0000000 --- a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_timing_summary_routed.rpt +++ /dev/null @@ -1,173 +0,0 @@ -Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018 -| Date : Thu Dec 24 23:25:56 2020 -| Host : colindrewes running 64-bit Ubuntu 18.04.5 LTS -| Command : report_timing_summary -max_paths 10 -file pulsegen_v_timing_summary_routed.rpt -pb pulsegen_v_timing_summary_routed.pb -rpx pulsegen_v_timing_summary_routed.rpx -warn_on_violation -| Design : pulsegen_v -| Device : 7z020-clg400 -| Speed File : -1 PRODUCTION 1.11 2014-09-11 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - -Timing Summary Report - ------------------------------------------------------------------------------------------------- -| Timer Settings -| -------------- ------------------------------------------------------------------------------------------------- - - Enable Multi Corner Analysis : Yes - Enable Pessimism Removal : Yes - Pessimism Removal Resolution : Nearest Common Node - Enable Input Delay Default Clock : No - Enable Preset / Clear Arcs : No - Disable Flight Delays : No - Ignore I/O Paths : No - Timing Early Launch at Borrowing Latches : false - - Corner Analyze Analyze - Name Max Paths Min Paths - ------ --------- --------- - Slow Yes Yes - Fast Yes Yes - - - -check_timing report - -Table of Contents ------------------ -1. checking no_clock -2. checking constant_clock -3. checking pulse_width_clock -4. checking unconstrained_internal_endpoints -5. checking no_input_delay -6. checking no_output_delay -7. checking multiple_clock -8. checking generated_clocks -9. checking loops -10. checking partial_input_delay -11. checking partial_output_delay -12. checking latch_loops - -1. checking no_clock --------------------- - There are 3 register/latch pins with no clock driven by root clock pin: clk (HIGH) - - -2. checking constant_clock --------------------------- - There are 0 register/latch pins with constant_clock. - - -3. checking pulse_width_clock ------------------------------ - There are 0 register/latch pins which need pulse_width check - - -4. checking unconstrained_internal_endpoints --------------------------------------------- - There are 3 pins that are not constrained for maximum delay. (HIGH) - - There are 0 pins that are not constrained for maximum delay due to constant clock. - - -5. checking no_input_delay --------------------------- - There are 0 input ports with no input delay specified. - - There are 0 input ports with no input delay but user has a false path constraint. - - -6. checking no_output_delay ---------------------------- - There is 1 port with no output delay specified. (HIGH) - - There are 0 ports with no output delay but user has a false path constraint - - There are 0 ports with no output delay but with a timing clock defined on it or propagating through it - - -7. checking multiple_clock --------------------------- - There are 0 register/latch pins with multiple clocks. - - -8. checking generated_clocks ----------------------------- - There are 0 generated clocks that are not connected to a clock source. - - -9. checking loops ------------------ - There are 0 combinational loops in the design. - - -10. checking partial_input_delay --------------------------------- - There are 0 input ports with partial input delay specified. - - -11. checking partial_output_delay ---------------------------------- - There are 0 ports with partial output delay specified. - - -12. checking latch_loops ------------------------- - There are 0 combinational latch loops in the design through latch input - - - ------------------------------------------------------------------------------------------------- -| Design Timing Summary -| --------------------- ------------------------------------------------------------------------------------------------- - - WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints - ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- - NA NA NA NA NA NA NA NA NA NA NA NA - - -There are no user specified timing constraints. - - ------------------------------------------------------------------------------------------------- -| Clock Summary -| ------------- ------------------------------------------------------------------------------------------------- - - ------------------------------------------------------------------------------------------------- -| Intra Clock Table -| ----------------- ------------------------------------------------------------------------------------------------- - -Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------ ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- - - ------------------------------------------------------------------------------------------------- -| Inter Clock Table -| ----------------- ------------------------------------------------------------------------------------------------- - -From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ----------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- - - ------------------------------------------------------------------------------------------------- -| Other Path Groups Table -| ----------------------- ------------------------------------------------------------------------------------------------- - -Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ----------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- - - ------------------------------------------------------------------------------------------------- -| Timing Details -| -------------- ------------------------------------------------------------------------------------------------- - - diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_timing_summary_routed.rpx b/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_timing_summary_routed.rpx deleted file mode 100644 index 3291a3a28565eac440cb90a57c80a20f5c377fb9..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 4414 zcmds5O>7&-6`onzk~(dj^;k|+#z9`xqL7M^BB>wCYJ}Pn9g~f05tMAFX$yKqj<^dg zcQ^Z^p8x^cLjfO+9@?M<0wX84haf;vG^aMlpobtqFFv|AAKjvd=9IqKKkZ7ERUKOb zB8G3?y!Yn)eDj`OC4`L7;!v$poheU`e{BR7z{LbZ~Sa)sngDpW{{sr?pk@~ zmxak_4>U_N_dLUcP1hbkbKsa_AS_?>z!JV`cz*d+H9m)0_-~cBhEYvtpzUs)_Drq2 zr89@V``3Rq|M3fo-*4Zgg?n`91NsN*3deT+jvt!U@glpRgeNKO4)UMC^;L)Ga^sPb#{+uluV@^&9yojxd`!tF zlzd9b=af98^bsXbD1A?%_Z9j;As;E^V@3HyA)hMbbA>!q=p%(bR>%{D7F$dyRXHgp zE`qO;51lw&A@d`b9}hRkoAeIRi9>eD&nUS|$vsNmqvSp%4=4@Q(?mTT|8s%8%!b;b zEBX02W^s%mBC}C8R2QDnw>aDPBzuFMYH6;|m+NBN=!(UQ?^J3PfEI>K>x;#%*`KN4 z?=?q=-eRc=6Rq}Y{pRv|bM*#P%hf8#yed^Lm8#WAw$6rc3D-jx@#ZaKTkF}djr;TE z8cfX1lr{{15=GsHrNA(IP^-<(&&|w%ZNa)8zz+ipsxv5Wp;B9zo`>u8bt!zF0XtRK ze8I;gS6y_WhFsGNwb_N)IpnBS*k33cUbZo#tseiM%&6~?+WQ4|rmKtYRusLqv&+f& zDjTuvPS>=%Tg4x=MIQ@IxKk^d-_^k}EDv@JUkA&EkOg|Ku`Mjv*aO$L{g{Y+3%J~x zP#SccqY~Tle9iJBu?;eQo}CR7qO)W4d_5(vFbJ%W+0_h7^g0ICyNfu`5mwK!@t0Tp z&dn?bw4_O!whLIj#vm9#PngW25PI#)sT|iu?F&wuZ$oTmc&XO@o`{czE)} zISvzz=C#J8y2jTtZpcT5Ut+Tvot2|?=FgSYS>Ab8SosyUc)VcUz}mGCO{3Q*Dmn-~ zrY`c&=n0a8H&{KRa5{3AuWNqjO-n+6EcU2=4;N-Raaa9794aT31ie6jk1!NtO9VY- zjKhaC6Nr2Y^Y62Z8S^U;rWnX}U>^Y@T8J3nIihQ98u-$y7x^vLKGETgz=yySF6f#E z8f1+)i(c?a&&2BEXG!-8k(9ya2BgFrY1hV$XjeBXL0_bx#RzhvFZxn zV*Qgy3?B;(qE;(;GQ_3?clih#J|J{EuI*@j>~jzcd>uQhzK%O;pWn;`G7l_#fz9RY zII@b9bCGhdtj=-$8L-6PVApbjQ{0LLpoRHlw?tPqrI?CZd_m6++^#6A*Z9?gD95MS zR8D-?9&8v^*yCwtgoK!ss6^lsBwMGlI>qli8yxv%_F7Kpp{$M(HBR?Ksr?%N$uR(% zNkfU6SgrddlL*hHQ?77&N8s}cYvk-c;Eb^62p@;MOVT8X5IelB+9-aP5$tdk%Ns9T zZ@e>6sF0;|A;`tOJEE?%dg<4N5z19|YR$BFc;QFFE6OiPd0q4TeM<4$?7~$`+rT;C zx@-Vo*>>^Ghb!@55^=uF#$u+H@H`wTyaBeq1AALDBZg^q;m{6pc(xhH&YqvUA<(6s zkKzXdtce?TPvBi3mfDp43-+Mc)!_H0hL*sx?9RAy!!80VCfZSk@L>u!Q65}zyI#og zB0FCa4gY85+h9Dc$>RW=cK^j9_4+=CSjy9OOF@t17Z zwRdEtuE_A9-%f|PHonAOjE^ka)~3-9usOo(;Z3E}4+drwVH=qeV2C2qeni<9G>js7 z1!uzWGnp)^$>LJ7xRNZI$wDV@C(C!`A{}FJhWQ;$w*DBd(qZZ$C4W!%9?O}Ee3}0K zxssf^tB`w2GBtgLW7q!rerEk3vwotGe=B63TqX_DB5#sA?!>J$79*j^Y|}- zsLR1eQo1P0EF5a-E*Zj5juccfM$X6;0U5d}w;0OypWsa52ChMe|O Y<aN)fBQ(ms?$~JF>7=S{1g&8jRySIvfM0zEGA`EvW89ubTEtLYX*UB?6 zC^-HFlE0jeDgXr>&#HpN=c+L<@HjsOk_-&JMj-Mokc@F&Y7AnpwP0Xqu>T7r8Jvz< tGB9{JOtRu|3UzaL4hix(YX?#?*B+?E;VF=0V0h~SBKNw2L|WZIYygIYI~D){ diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_utilization_placed.rpt b/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_utilization_placed.rpt deleted file mode 100644 index ec33d9f..0000000 --- a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/pulsegen_v_utilization_placed.rpt +++ /dev/null @@ -1,200 +0,0 @@ -Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------ -| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018 -| Date : Thu Dec 24 23:25:15 2020 -| Host : colindrewes running 64-bit Ubuntu 18.04.5 LTS -| Command : report_utilization -file pulsegen_v_utilization_placed.rpt -pb pulsegen_v_utilization_placed.pb -| Design : pulsegen_v -| Device : 7z020clg400-1 -| Design State : Fully Placed ------------------------------------------------------------------------------------------------------------------ - -Utilization Design Information - -Table of Contents ------------------ -1. Slice Logic -1.1 Summary of Registers by Type -2. Slice Logic Distribution -3. Memory -4. DSP -5. IO and GT Specific -6. Clocking -7. Specific Feature -8. Primitives -9. Black Boxes -10. Instantiated Netlists - -1. Slice Logic --------------- - -+-------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------------------+------+-------+-----------+-------+ -| Slice LUTs | 2 | 0 | 53200 | <0.01 | -| LUT as Logic | 2 | 0 | 53200 | <0.01 | -| LUT as Memory | 0 | 0 | 17400 | 0.00 | -| Slice Registers | 3 | 0 | 106400 | <0.01 | -| Register as Flip Flop | 3 | 0 | 106400 | <0.01 | -| Register as Latch | 0 | 0 | 106400 | 0.00 | -| F7 Muxes | 0 | 0 | 26600 | 0.00 | -| F8 Muxes | 0 | 0 | 13300 | 0.00 | -+-------------------------+------+-------+-----------+-------+ - - -1.1 Summary of Registers by Type --------------------------------- - -+-------+--------------+-------------+--------------+ -| Total | Clock Enable | Synchronous | Asynchronous | -+-------+--------------+-------------+--------------+ -| 0 | _ | - | - | -| 0 | _ | - | Set | -| 0 | _ | - | Reset | -| 0 | _ | Set | - | -| 0 | _ | Reset | - | -| 0 | Yes | - | - | -| 0 | Yes | - | Set | -| 0 | Yes | - | Reset | -| 0 | Yes | Set | - | -| 3 | Yes | Reset | - | -+-------+--------------+-------------+--------------+ - - -2. Slice Logic Distribution ---------------------------- - -+-------------------------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------------------------------------+------+-------+-----------+-------+ -| Slice | 2 | 0 | 13300 | 0.02 | -| SLICEL | 0 | 0 | | | -| SLICEM | 2 | 0 | | | -| LUT as Logic | 2 | 0 | 53200 | <0.01 | -| using O5 output only | 0 | | | | -| using O6 output only | 1 | | | | -| using O5 and O6 | 1 | | | | -| LUT as Memory | 0 | 0 | 17400 | 0.00 | -| LUT as Distributed RAM | 0 | 0 | | | -| LUT as Shift Register | 0 | 0 | | | -| LUT Flip Flop Pairs | 1 | 0 | 53200 | <0.01 | -| fully used LUT-FF pairs | 1 | | | | -| LUT-FF pairs with one unused LUT output | 0 | | | | -| LUT-FF pairs with one unused Flip Flop | 0 | | | | -| Unique Control Sets | 2 | | | | -+-------------------------------------------+------+-------+-----------+-------+ -* Note: Review the Control Sets Report for more information regarding control sets. - - -3. Memory ---------- - -+----------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+----------------+------+-------+-----------+-------+ -| Block RAM Tile | 0 | 0 | 140 | 0.00 | -| RAMB36/FIFO* | 0 | 0 | 140 | 0.00 | -| RAMB18 | 0 | 0 | 280 | 0.00 | -+----------------+------+-------+-----------+-------+ -* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 - - -4. DSP ------- - -+-----------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------+------+-------+-----------+-------+ -| DSPs | 0 | 0 | 220 | 0.00 | -+-----------+------+-------+-----------+-------+ - - -5. IO and GT Specific ---------------------- - -+-----------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------------------------+------+-------+-----------+-------+ -| Bonded IOB | 10 | 0 | 125 | 8.00 | -| IOB Master Pads | 5 | | | | -| IOB Slave Pads | 5 | | | | -| Bonded IPADs | 0 | 0 | 2 | 0.00 | -| Bonded IOPADs | 0 | 0 | 130 | 0.00 | -| PHY_CONTROL | 0 | 0 | 4 | 0.00 | -| PHASER_REF | 0 | 0 | 4 | 0.00 | -| OUT_FIFO | 0 | 0 | 16 | 0.00 | -| IN_FIFO | 0 | 0 | 16 | 0.00 | -| IDELAYCTRL | 0 | 0 | 4 | 0.00 | -| IBUFDS | 0 | 0 | 121 | 0.00 | -| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 16 | 0.00 | -| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 16 | 0.00 | -| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 200 | 0.00 | -| ILOGIC | 0 | 0 | 125 | 0.00 | -| OLOGIC | 0 | 0 | 125 | 0.00 | -+-----------------------------+------+-------+-----------+-------+ - - -6. Clocking ------------ - -+------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+------------+------+-------+-----------+-------+ -| BUFGCTRL | 1 | 0 | 32 | 3.13 | -| BUFIO | 0 | 0 | 16 | 0.00 | -| MMCME2_ADV | 0 | 0 | 4 | 0.00 | -| PLLE2_ADV | 0 | 0 | 4 | 0.00 | -| BUFMRCE | 0 | 0 | 8 | 0.00 | -| BUFHCE | 0 | 0 | 72 | 0.00 | -| BUFR | 0 | 0 | 16 | 0.00 | -+------------+------+-------+-----------+-------+ - - -7. Specific Feature -------------------- - -+-------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------+------+-------+-----------+-------+ -| BSCANE2 | 0 | 0 | 4 | 0.00 | -| CAPTUREE2 | 0 | 0 | 1 | 0.00 | -| DNA_PORT | 0 | 0 | 1 | 0.00 | -| EFUSE_USR | 0 | 0 | 1 | 0.00 | -| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | -| ICAPE2 | 0 | 0 | 2 | 0.00 | -| STARTUPE2 | 0 | 0 | 1 | 0.00 | -| XADC | 0 | 0 | 1 | 0.00 | -+-------------+------+-------+-----------+-------+ - - -8. Primitives -------------- - -+----------+------+---------------------+ -| Ref Name | Used | Functional Category | -+----------+------+---------------------+ -| OBUF | 9 | IO | -| FDRE | 3 | Flop & Latch | -| LUT1 | 2 | LUT | -| LUT2 | 1 | LUT | -| IBUF | 1 | IO | -| BUFG | 1 | Clock | -+----------+------+---------------------+ - - -9. Black Boxes --------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - -10. Instantiated Netlists -------------------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/route_design.pb b/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/route_design.pb deleted file mode 100644 index e02a8364be0ddac8968ea52a9221234b9c7f26d2..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 12838 zcmeHN&2Jn@72mc!W41Pguu`&%vs!8s%qGS&(;xF`v?z(~WW$ohINt1Ht=4K!*VwJ} zbT|Fsk8C*Y0Rb02E@%&M0KtI+7q}rIE}Re&7Z4IB{s1oU2k@)v>2bHa#xq%xkX4W( z#Z%Q?_4>WvdsXlE9{CzMwe0o#rfV(H`H-BMnVV`D3(xM^d#2?@T}P+nRN%!C+p<__ z@3{J`#d>D!L`&%(o27b1(~R9`{F#H9?p_p7tkIvqc~vn)%oyMitTF{v)CS<5JOy&X+v!4x~+Svt`;XZ%UY{q)LU6Of2a`kh8I1UTqVe*sSjJO4&*8wloI{?(48N!uIE}d|8%ZVt`?{*HJYwJn9*kH6TXUERECsB`0rZQ{mj9@8WJ;sO@6j)kPhE>`$D->SbY)av zNIqK2e)KY_CR=Ls*!%Q8UEXEgyJ6g4qMFrKJ3W>4pz74qvdjEVAu~kCoEP`U3i-CO zVfPum6kcAUT|cI;QB_^SKch~+NSR~$AvBy0>K$68w-}&tNH5*GhF5%M-o>=8H#*fu zql0&LU|x*W^=hl3;&(4#jQYEWq1`ndOlZyF=$;)!u^2S;hN>0ymi>mk$<(jQ)PI?r zF?zHb&EOD!5eW4^?-7Eok%^dFDpWwq^Br|$dio8Yg z;&uCgZg{@ucsqx5Ipczb6G8U%Z<0;|LB7GLrJgi2Hk;K(y_G>@r`j^wGBg_eDS^=} z8tbk4$!LrwHHs9E^W@WOfR4Z_;`&}5+fLCcun8WslU@?YNy>ZAENfTj*g#EhC1?$dI0Uqqe8uLvi8FXq5`f6 zb(!`*Po7`5{Yvc9tGK4FGjSXgx03~hc!F(lLe%9a1UA0mc-uIKZ{ma$=OUFS1cj4v z7>)SS#YLVr^RE&$afCW8n(}E=#{CIE314W)e4$3pufVSld7?{i-(~ystC@S#WKJ=> zw={6$9=X=jW)*ibt2AX+d4+s(%?l&?x`#vtH^Is5Fv*F8;M9}{C+wMSC&JTYdk#+| zzH09Mr_J71$QP23)TBAvJ#BjMCc}M8hWiWTbaGP%F~d_wHW>)7lEp;zt-(bf_ zIxfv79e2Ad412NT9CDIX0XHq6&Iw9E2x(2^cte`_qp*38N)Ng!W%KGS3FDp3Q#Z-E zb;cQK4yHk!BdMr>p=}!}i8)CbW3z-xMVoWQLk;~wAveJI-UNFcE^_YoZ8PBIf#k<> z01R_7G94AyOgxnk>fn{TUhEnXjRA-#2eX_au5oJp1>=X_X_O^q1dM4h3Y zORnD|bC3+xivd`|99Xz;xx&Es@)O@7SIPLt6ba_T<18>X&F0qlDQAAga|6y-{C%A7 zJsLbBGB_1|YHqrYYC@)7B``mzn=Q#g5U+Y99r_$8Csd4N z?gcUpluIT)LrR7&MLLr7R;48hMyC!=B}J+?$OW*-NAz*R5pOfP4>(55r68!QXUcOk z+VN7!<}5hrhOViAc=@25EVn|=zs+$B_wgOG3u@akBXb+&iE34#b_PT{N-jwm5_J|Q z+?>_biq`Jr$||psbLl$otgK!aXDk*KOHAt;>KoY=%2)w|Sx^2lxhPwJf^8N~#!u_P zYHCNan#$`(!&2y|)k2?j!P|?oKb1|DtR|E+T?z{W!(ELJXkZ@9O}bkXq0<+qj1l3u|FXW{bhgWWOUu1DA@ZXxb4xf{lxC4Td3 zh5SU3I8L8MyPlQQDhm#jnH=LxBc7Bv)`%y^JK5jHI@vE2@&jd{s?0XUz>t}I4BsU& zS+OT+mCUbrE~6of#3kdMm1Ri@T=>tF(O4)a<#A*y?TXRJg6p9z^mX#NwBzPh1|+i1 zo7TylH)V9*Xhtq$_|p{8k41}h5g*a+a0EzG5mK0PSV?!q)f=`Q^86QtdYxe)`&r_r=59eAR4zYrw^3jqBB@Dx8|efDVloG zjGTFpl(9z;5+jBm3Qv*TKLrqqVix`U`w~Boi7B~5Bt$}pzSlS`I(v4uD!GT}=Kbw4 zSM7gEr230OelLqY$r-sdh$FOu{=_ZcjCMn+sYN;SPp45wBCz~HNqCY!$PxL}T2V8JPWWX>g^U>L9yIw$s31b>$=l{;1cmC6atcs>BkO> $HD_LOG 2>&1 - if [ $? -ne 0 ] - then - exit - fi -} - -# pre-commands: -/bin/touch .init_design.begin.rst -EAStep vivado -log pulsegen_v.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source pulsegen_v.tcl -notrace - - diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/vivado.pb b/burn/ip/pulsegen_v/pulsegen_v.runs/impl_1/vivado.pb deleted file mode 100644 index a2977292365523c77cf419fc758f1ce6001281dc..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 149 zcmd;TVB`{Ut;j6N%u82LEmlY@0g`%pdRzjmQp`pMW?F2?`MJ6Ic}7xPY+;#Yi7EL; z>?x^fiKRIuRxpN<4wpnoMyY~JYO;cniGq=_m655HsfB`(0T99z!Bt1G8Jg - - - - diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/synth_1/.vivado.end.rst b/burn/ip/pulsegen_v/pulsegen_v.runs/synth_1/.vivado.end.rst deleted file mode 100644 index e69de29..0000000 diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/synth_1/ISEWrap.js b/burn/ip/pulsegen_v/pulsegen_v.runs/synth_1/ISEWrap.js deleted file mode 100755 index 8284d2d..0000000 --- a/burn/ip/pulsegen_v/pulsegen_v.runs/synth_1/ISEWrap.js +++ /dev/null @@ -1,244 +0,0 @@ -// -// Vivado(TM) -// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 -// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. -// - -// GLOBAL VARIABLES -var ISEShell = new ActiveXObject( "WScript.Shell" ); -var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); -var ISERunDir = ""; -var ISELogFile = "runme.log"; -var ISELogFileStr = null; -var ISELogEcho = true; -var ISEOldVersionWSH = false; - - - -// BOOTSTRAP -ISEInit(); - - - -// -// ISE FUNCTIONS -// -function ISEInit() { - - // 1. RUN DIR setup - var ISEScrFP = WScript.ScriptFullName; - var ISEScrN = WScript.ScriptName; - ISERunDir = - ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); - - // 2. LOG file setup - ISELogFileStr = ISEOpenFile( ISELogFile ); - - // 3. LOG echo? - var ISEScriptArgs = WScript.Arguments; - for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; - ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); - ISELogFileStr = ISEOpenFile( ISELogFile ); - - } else { // WSH 5.6 - - // LAUNCH! - ISEShell.CurrentDirectory = ISERunDir; - - // Redirect STDERR to STDOUT - ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; - var ISEProcess = ISEShell.Exec( ISECmdLine ); - - // BEGIN file creation - var ISENetwork = WScript.CreateObject( "WScript.Network" ); - var ISEHost = ISENetwork.ComputerName; - var ISEUser = ISENetwork.UserName; - var ISEPid = ISEProcess.ProcessID; - var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.Close(); - - var ISEOutStr = ISEProcess.StdOut; - var ISEErrStr = ISEProcess.StdErr; - - // WAIT for ISEStep to finish - while ( ISEProcess.Status == 0 ) { - - // dump stdout then stderr - feels a little arbitrary - while ( !ISEOutStr.AtEndOfStream ) { - ISEStdOut( ISEOutStr.ReadLine() ); - } - - WScript.Sleep( 100 ); - } - - ISEExitCode = ISEProcess.ExitCode; - } - - ISELogFileStr.Close(); - - // END/ERROR file creation - if ( ISEExitCode != 0 ) { - ISETouchFile( ISEStep, "error" ); - - } else { - ISETouchFile( ISEStep, "end" ); - } - - return ISEExitCode; -} - - -// -// UTILITIES -// -function ISEStdOut( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdOut.WriteLine( ISELine ); - } -} - -function ISEStdErr( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdErr.WriteLine( ISELine ); - } -} - -function ISETouchFile( ISERoot, ISEStatus ) { - - var ISETFile = - ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); - ISETFile.Close(); -} - -function ISEOpenFile( ISEFilename ) { - - // This function has been updated to deal with a problem seen in CR #870871. - // In that case the user runs a script that runs impl_1, and then turns around - // and runs impl_1 -to_step write_bitstream. That second run takes place in - // the same directory, which means we may hit some of the same files, and in - // particular, we will open the runme.log file. Even though this script closes - // the file (now), we see cases where a subsequent attempt to open the file - // fails. Perhaps the OS is slow to release the lock, or the disk comes into - // play? In any case, we try to work around this by first waiting if the file - // is already there for an arbitrary 5 seconds. Then we use a try-catch block - // and try to open the file 10 times with a one second delay after each attempt. - // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. - // If there is an unrecognized exception when trying to open the file, we output - // an error message and write details to an exception.log file. - var ISEFullPath = ISERunDir + "/" + ISEFilename; - if (ISEFileSys.FileExists(ISEFullPath)) { - // File is already there. This could be a problem. Wait in case it is still in use. - WScript.Sleep(5000); - } - var i; - for (i = 0; i < 10; ++i) { - try { - return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); - } catch (exception) { - var error_code = exception.number & 0xFFFF; // The other bits are a facility code. - if (error_code == 52) { // 52 is bad file name or number. - // Wait a second and try again. - WScript.Sleep(1000); - continue; - } else { - WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - var exceptionFilePath = ISERunDir + "/exception.log"; - if (!ISEFileSys.FileExists(exceptionFilePath)) { - WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); - var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); - exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - exceptionFile.WriteLine("\tException name: " + exception.name); - exceptionFile.WriteLine("\tException error code: " + error_code); - exceptionFile.WriteLine("\tException message: " + exception.message); - exceptionFile.Close(); - } - throw exception; - } - } - } - // If we reached this point, we failed to open the file after 10 attempts. - // We need to error out. - WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); - WScript.Quit(1); -} diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/synth_1/ISEWrap.sh b/burn/ip/pulsegen_v/pulsegen_v.runs/synth_1/ISEWrap.sh deleted file mode 100755 index e1a8f5d..0000000 --- a/burn/ip/pulsegen_v/pulsegen_v.runs/synth_1/ISEWrap.sh +++ /dev/null @@ -1,63 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# ISEWrap.sh: Vivado Runs Script for UNIX -# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. -# - -HD_LOG=$1 -shift - -# CHECK for a STOP FILE -if [ -f .stop.rst ] -then -echo "" >> $HD_LOG -echo "*** Halting run - EA reset detected ***" >> $HD_LOG -echo "" >> $HD_LOG -exit 1 -fi - -ISE_STEP=$1 -shift - -# WRITE STEP HEADER to LOG -echo "" >> $HD_LOG -echo "*** Running $ISE_STEP" >> $HD_LOG -echo " with args $@" >> $HD_LOG -echo "" >> $HD_LOG - -# LAUNCH! -$ISE_STEP "$@" >> $HD_LOG 2>&1 & - -# BEGIN file creation -ISE_PID=$! -if [ X != X$HOSTNAME ] -then -ISE_HOST=$HOSTNAME #bash -else -ISE_HOST=$HOST #csh -fi -ISE_USER=$USER -ISE_BEGINFILE=.$ISE_STEP.begin.rst -/bin/touch $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE - -# WAIT for ISEStep to finish -wait $ISE_PID - -# END/ERROR file creation -RETVAL=$? -if [ $RETVAL -eq 0 ] -then - /bin/touch .$ISE_STEP.end.rst -else - /bin/touch .$ISE_STEP.error.rst -fi - -exit $RETVAL - diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/synth_1/__synthesis_is_complete__ b/burn/ip/pulsegen_v/pulsegen_v.runs/synth_1/__synthesis_is_complete__ deleted file mode 100644 index e69de29..0000000 diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/synth_1/gen_run.xml b/burn/ip/pulsegen_v/pulsegen_v.runs/synth_1/gen_run.xml deleted file mode 100644 index 896b268..0000000 --- a/burn/ip/pulsegen_v/pulsegen_v.runs/synth_1/gen_run.xml +++ /dev/null @@ -1,40 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/synth_1/htr.txt b/burn/ip/pulsegen_v/pulsegen_v.runs/synth_1/htr.txt deleted file mode 100644 index 0fae7a7..0000000 --- a/burn/ip/pulsegen_v/pulsegen_v.runs/synth_1/htr.txt +++ /dev/null @@ -1,9 +0,0 @@ -# -# Vivado(TM) -# htr.txt: a Vivado-generated description of how-to-repeat the -# the basic steps of a run. Note that runme.bat/sh needs -# to be invoked for Vivado to track run status. -# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -# - -vivado -log pulsegen_v.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source pulsegen_v.tcl diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/synth_1/project.wdf b/burn/ip/pulsegen_v/pulsegen_v.runs/synth_1/project.wdf deleted file mode 100644 index e679594..0000000 --- a/burn/ip/pulsegen_v/pulsegen_v.runs/synth_1/project.wdf +++ /dev/null @@ -1,31 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:32:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 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All Rights Reserved. ---------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018 -| Date : Thu Dec 24 23:23:08 2020 -| Host : colindrewes running 64-bit Ubuntu 18.04.5 LTS -| Command : report_utilization -file pulsegen_v_utilization_synth.rpt -pb pulsegen_v_utilization_synth.pb -| Design : pulsegen_v -| Device : 7z020clg400-1 -| Design State : Synthesized ---------------------------------------------------------------------------------------------------------------- - -Utilization Design Information - -Table of Contents ------------------ -1. Slice Logic -1.1 Summary of Registers by Type -2. Memory -3. DSP -4. IO and GT Specific -5. Clocking -6. Specific Feature -7. Primitives -8. Black Boxes -9. Instantiated Netlists - -1. Slice Logic --------------- - -+-------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------------------+------+-------+-----------+-------+ -| Slice LUTs* | 2 | 0 | 53200 | <0.01 | -| LUT as Logic | 2 | 0 | 53200 | <0.01 | -| LUT as Memory | 0 | 0 | 17400 | 0.00 | -| Slice Registers | 3 | 0 | 106400 | <0.01 | -| Register as Flip Flop | 3 | 0 | 106400 | <0.01 | -| Register as Latch | 0 | 0 | 106400 | 0.00 | -| F7 Muxes | 0 | 0 | 26600 | 0.00 | -| F8 Muxes | 0 | 0 | 13300 | 0.00 | -+-------------------------+------+-------+-----------+-------+ -* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. - - -1.1 Summary of Registers by Type --------------------------------- - -+-------+--------------+-------------+--------------+ -| Total | Clock Enable | Synchronous | Asynchronous | -+-------+--------------+-------------+--------------+ -| 0 | _ | - | - | -| 0 | _ | - | Set | -| 0 | _ | - | Reset | -| 0 | _ | Set | - | -| 0 | _ | Reset | - | -| 0 | Yes | - | - | -| 0 | Yes | - | Set | -| 0 | Yes | - | Reset | -| 0 | Yes | Set | - | -| 3 | Yes | Reset | - | -+-------+--------------+-------------+--------------+ - - -2. Memory ---------- - -+----------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+----------------+------+-------+-----------+-------+ -| Block RAM Tile | 0 | 0 | 140 | 0.00 | -| RAMB36/FIFO* | 0 | 0 | 140 | 0.00 | -| RAMB18 | 0 | 0 | 280 | 0.00 | -+----------------+------+-------+-----------+-------+ -* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 - - -3. DSP ------- - -+-----------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------+------+-------+-----------+-------+ -| DSPs | 0 | 0 | 220 | 0.00 | -+-----------+------+-------+-----------+-------+ - - -4. IO and GT Specific ---------------------- - -+-----------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------------------------+------+-------+-----------+-------+ -| Bonded IOB | 10 | 0 | 125 | 8.00 | -| Bonded IPADs | 0 | 0 | 2 | 0.00 | -| Bonded IOPADs | 0 | 0 | 130 | 0.00 | -| PHY_CONTROL | 0 | 0 | 4 | 0.00 | -| PHASER_REF | 0 | 0 | 4 | 0.00 | -| OUT_FIFO | 0 | 0 | 16 | 0.00 | -| IN_FIFO | 0 | 0 | 16 | 0.00 | -| IDELAYCTRL | 0 | 0 | 4 | 0.00 | -| IBUFDS | 0 | 0 | 121 | 0.00 | -| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 16 | 0.00 | -| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 16 | 0.00 | -| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 200 | 0.00 | -| ILOGIC | 0 | 0 | 125 | 0.00 | -| OLOGIC | 0 | 0 | 125 | 0.00 | -+-----------------------------+------+-------+-----------+-------+ - - -5. Clocking ------------ - -+------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+------------+------+-------+-----------+-------+ -| BUFGCTRL | 1 | 0 | 32 | 3.13 | -| BUFIO | 0 | 0 | 16 | 0.00 | -| MMCME2_ADV | 0 | 0 | 4 | 0.00 | -| PLLE2_ADV | 0 | 0 | 4 | 0.00 | -| BUFMRCE | 0 | 0 | 8 | 0.00 | -| BUFHCE | 0 | 0 | 72 | 0.00 | -| BUFR | 0 | 0 | 16 | 0.00 | -+------------+------+-------+-----------+-------+ - - -6. Specific Feature -------------------- - -+-------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------+------+-------+-----------+-------+ -| BSCANE2 | 0 | 0 | 4 | 0.00 | -| CAPTUREE2 | 0 | 0 | 1 | 0.00 | -| DNA_PORT | 0 | 0 | 1 | 0.00 | -| EFUSE_USR | 0 | 0 | 1 | 0.00 | -| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | -| ICAPE2 | 0 | 0 | 2 | 0.00 | -| STARTUPE2 | 0 | 0 | 1 | 0.00 | -| XADC | 0 | 0 | 1 | 0.00 | -+-------------+------+-------+-----------+-------+ - - -7. Primitives -------------- - -+----------+------+---------------------+ -| Ref Name | Used | Functional Category | -+----------+------+---------------------+ -| OBUF | 9 | IO | -| FDRE | 3 | Flop & Latch | -| LUT1 | 2 | LUT | -| LUT2 | 1 | LUT | -| IBUF | 1 | IO | -| BUFG | 1 | Clock | -+----------+------+---------------------+ - - -8. Black Boxes --------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - -9. Instantiated Netlists ------------------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/synth_1/rundef.js b/burn/ip/pulsegen_v/pulsegen_v.runs/synth_1/rundef.js deleted file mode 100644 index e47c104..0000000 --- a/burn/ip/pulsegen_v/pulsegen_v.runs/synth_1/rundef.js +++ /dev/null @@ -1,40 +0,0 @@ -// -// Vivado(TM) -// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 -// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -// - -echo "This script was generated under a different operating system." -echo "Please update the PATH variable below, before executing this script" -exit - -var WshShell = new ActiveXObject( "WScript.Shell" ); -var ProcEnv = WshShell.Environment( "Process" ); -var PathVal = ProcEnv("PATH"); -if ( PathVal.length == 0 ) { - PathVal = "/home/colin/Xilinx/SDK/2018.2/bin:/home/colin/Xilinx/Vivado/2018.2/ids_lite/ISE/bin/lin64;/home/colin/Xilinx/Vivado/2018.2/ids_lite/ISE/lib/lin64;/home/colin/Xilinx/Vivado/2018.2/bin;"; -} else { - PathVal = "/home/colin/Xilinx/SDK/2018.2/bin:/home/colin/Xilinx/Vivado/2018.2/ids_lite/ISE/bin/lin64;/home/colin/Xilinx/Vivado/2018.2/ids_lite/ISE/lib/lin64;/home/colin/Xilinx/Vivado/2018.2/bin;" + PathVal; -} - -ProcEnv("PATH") = PathVal; - -var RDScrFP = WScript.ScriptFullName; -var RDScrN = WScript.ScriptName; -var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); -var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; -eval( EAInclude(ISEJScriptLib) ); - - -ISEStep( "vivado", - "-log pulsegen_v.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source pulsegen_v.tcl" ); - - - -function EAInclude( EAInclFilename ) { - var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); - var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); - var EAIFContents = EAInclFile.ReadAll(); - EAInclFile.Close(); - return EAIFContents; -} diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/synth_1/runme.bat b/burn/ip/pulsegen_v/pulsegen_v.runs/synth_1/runme.bat deleted file mode 100644 index 8eb74b1..0000000 --- a/burn/ip/pulsegen_v/pulsegen_v.runs/synth_1/runme.bat +++ /dev/null @@ -1,11 +0,0 @@ -@echo off - -rem Vivado (TM) -rem runme.bat: a Vivado-generated Script -rem Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. - - -set HD_SDIR=%~dp0 -cd /d "%HD_SDIR%" -set PATH=%SYSTEMROOT%\system32;%PATH% -cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/synth_1/runme.sh b/burn/ip/pulsegen_v/pulsegen_v.runs/synth_1/runme.sh deleted file mode 100755 index 3dab469..0000000 --- a/burn/ip/pulsegen_v/pulsegen_v.runs/synth_1/runme.sh +++ /dev/null @@ -1,39 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# runme.sh: a Vivado-generated Runs Script for UNIX -# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -# - -if [ -z "$PATH" ]; then - PATH=/home/colin/Xilinx/SDK/2018.2/bin:/home/colin/Xilinx/Vivado/2018.2/ids_lite/ISE/bin/lin64:/home/colin/Xilinx/Vivado/2018.2/bin -else - PATH=/home/colin/Xilinx/SDK/2018.2/bin:/home/colin/Xilinx/Vivado/2018.2/ids_lite/ISE/bin/lin64:/home/colin/Xilinx/Vivado/2018.2/bin:$PATH -fi -export PATH - -if [ -z "$LD_LIBRARY_PATH" ]; then - LD_LIBRARY_PATH=/home/colin/Xilinx/Vivado/2018.2/ids_lite/ISE/lib/lin64 -else - LD_LIBRARY_PATH=/home/colin/Xilinx/Vivado/2018.2/ids_lite/ISE/lib/lin64:$LD_LIBRARY_PATH -fi -export LD_LIBRARY_PATH - -HD_PWD='/home/colin/Desktop/PL-Sensors/burn/ip/pulsegen_v/pulsegen_v.runs/synth_1' -cd "$HD_PWD" - -HD_LOG=runme.log -/bin/touch $HD_LOG - -ISEStep="./ISEWrap.sh" -EAStep() -{ - $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 - if [ $? -ne 0 ] - then - exit - fi -} - -EAStep vivado -log pulsegen_v.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source pulsegen_v.tcl diff --git a/burn/ip/pulsegen_v/pulsegen_v.runs/synth_1/vivado.pb b/burn/ip/pulsegen_v/pulsegen_v.runs/synth_1/vivado.pb deleted file mode 100644 index fae4826a24929f247974f33a1a385768110bb300..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 27185 zcmeGlX>TM)HEpkLQdx)*$m)NW+$t~WF8W2WbTkgSj0EZM{HUf^W0dS}Yx&bGUU z?jEnb8bwI(84zC(d_W)s3gHHUI3yxY@rmOTh*O9!@SPvPtLkIAr>oueuDxwXW36_k zyQg2hdR6b$t9KQ;jSkORYipX>tm8=sjUSpADl1bDuIuYs({dYzdfyp9WP&35rdqjE=-#fH%;iDE&L$C_kC>lki5__8!oDoB#D`at{8 z#-UFO4~!3?Iy!RMg_m`+g`-VSB!;C@ErJDoTal&c+g}jS^QT>xthE^c*TOC0VhtO5 zgP0D%E0&E{h~{=|f{#x+$1!wq8tyg8I{bp&Vht%`b!xN$B(O~Rz39Qqw6D-pC)ox0 zJ!s7DXY%3Fs8lH^rAidVPYOspYq>i^X=Gwpk;Gj@sRk&GY>ap`|DAw_CY|xaQzMMx z@(%>`MIju8p!0VKuH!5E8o?)=lXcu^ckr`V6zlX~3BL~$Lu)&v*}GZBMSOv*S@tGA zabX5tX%p=hJeCwuEh;j7r={s8+^MQXwIajyicJV^uWmYeLo?ukTqy^4*LBk%>d4QmryIVrkB%BR`2yZ}KJq z%a5Q3ICpLI%JizWMy4BWjoV1JGMEkx2Jo+BVUV--EgKI zt7A8avn)-U74YbQoc8;Jc@MJmd*O27(H2B}guVr&y-keVcAFvx3+H>+kbov&<65Y^e=r> z{ked?(WC0DWjd}6;=#q&G(&G{u5Ov>0%#8jtndje^1ByGp!^A(KL*$0lk5X%imfX6 zyrng%P+p)~0xZFFS)teGOjw}T*iiGS8&015`}VV;&?~C@)ccj6eczw|^syrd zy`S{hG3eVCBer|YSuNJel}8v@lG=rw(>krFsk+Wc6_kIf>WprTdJ9VaGU4xiJoGC8eY?j)i&xI$ORzCn z)9-kz*}|#@dlGrq7)Mo$HI?#7z&ND}Fb>rt5_)wxR3@ToL$y}o%c*^|s?EpcZUH@x z7D?NJg@n?V$|s$w3QisKyAm!T*W-YmL#Iv^PQ`Vg*k$D6)Q&-SaW{q@T#`2IO1+8D zJqOB;X2L!IcXteW53$}g(D}3G`S@s;5cX6NIx1l6Xu}o>R86?&>W-^7oUGZCe~(^_ z_eeoc%@J4A4cL;zJ4LlBkTDq(s~!h;484O+_|wfMv7PL!5422vInD~RXgVg7W30xL9~qpM zzjVwWgBRi?7SR))d}bDwMdJAd@Z}D;;q1+QPtT8gJKxZrd<$KVb;PNoxyuW%DU)Rp zp8$smHi+4BSL>>H63r~0zCa&U7EoNld_w(gOTn@}5>AGf{V7jYQV}@oJ z#0Y(N4sO^w?09qy>kc--i@XNz?TjvdMnG!Yw%S??_O@UVY*5dN2AkbU2Wt&RLWg{` z1KVF6+^fVOYjh_JK0)RXRNyag2&VY(j-t1(Qy0y$)p7aeL+Y5MfTCu~&k5+*8nIgx zCEYiFcs_aBGzQl_bIUY2eo1%do-G<;@mk@FyYP3FADu&Y+p zUBr&p%r>x7?hkgnX10M{>Hc8HYi1kRmG2LByk@q6oqB(;<2ADl>?+&D?o+!dN<jmm*5TfYZLI}yA(KuK zTq1`+M#+Jw$@Gb2M2+~!%25}^_lD4^HHd)H3r$;JCnh#QeuEsot-GuAlijs(8=_*E z^c$lnm8AeB5Wp`bsX_->a$L>>kjxRc&NT1coE$r)QmSKztrcZTwy}*d&$ILTUXe{U zn;fzMJp)7QeBkOBI6)tvse)$u_1D$S`^FN*btHH;#O<>KX7Z{;)ZCL(3G^dj`_Eci~CI6 zl2Akwo|(iCu8W4AWS9){7diQ3@aI0E_ojf}=m|XzO>>cPRD33)f7NP@Kfr@9o75?}RB;1Y|I_X&%1S&>#&m7WXl2It0ggbW$g6SLr;jNa*pZf#Z7I6f> z6jz38XwoC&83>4X3H7hx83NfR1P=&HwSeAV#^kyZC+z#tiO|12ply$e{BIewO^XQu z3WIC*B5@4}c*U~@(acUe16Ka(MgACU5sNV(DSw6*GN#oZ`*g-13Fyl`oiQp))3rrv zn2TqNgUwIb6`LP78}=Y*i*s?Y`V4w3NNbs0C5>AF^Jj+fcj9nvpmYBIF0#!FMn1R| zeD+kw-kspLg{;kTvf-{53E4dd^%(r1NdKcdZ`+U`kGp=T3w(ps+3mn5WYI&63uH+_ zwy*zw#*9oh>|@XCgx{Usqu^Wc8TJ>5vEzojUN%FQx!;yO7w?b#aC{RT7*Sn&%t7zWO1m}RR^rP1J23joWJ#P&MyV@tsdua zcBquD1GYI>Y?G#}U5BhUy5t0<79H%B{K=5E`D>r2ZaL!w}28f&)7V;*f}n~*?Q*cnX|s7T1v4& zZ-GnKt2fgJS5j>XWSIQch%&nzjFgcvYHh+5aLzS5;ElI;{p zLfiu!eMX_x&b>kPKD@~xRZ@mE49wYm9P?k|wzdYOt=t36j4^WXA75mL^Tv+z-x500 z(}Y%nI@BzORK!sC6I`p$V1?BRU=^Njdj$m`-5;`GRUBLvGg|cvG>3^8tUzg_1P?)^eQ-xN~1M{C>|#NFNgNs&^WTjep`W&dUn zzG7>p0|9STcXs?U4DNty6kO6Yk_bU{g<+*EPK`l*h*u#obZJB?lq>W^g|M0|L50&0 ze6-1m=tG9`Rj7KduLWfy99CHt%4>l(%j!l@kV8^sYRqpUrSALEh+Hd3u|oB)BH4${ zunr4BL!PQf`zDl$pgGdB3s)pK5;LpgQsk3rkXnzYM{U7p=rd-X;(X2_@G} zhti%jdE$Xi5J`$nkgMp(A`}hL97;+5oDJ{P5Ez@PvduFq0C1&HjTHz1+t^v49j#so z;tak8!6NKpmTn2@ArZk{CfwjxerO3X8&s!;K0!z50VXg_A_tfpK|@k4nS)Cyukvpz z{M(%2TRK!KlqikDLrp${CIGYEM0Pq2sP*csbPQwDLoRx*iHy-<#;yM8D#?af3p7JM zY~kNS$ewf{D=Bt52Q(Uuw1P|ii5%>Ae$im|y}w>??`E%DFg+ON@WgPb+B=s7vY?}g zLrJILq?ho>7a1~-y+cD3IsGZbgH`xXCAB0LE9DaBDV)SoQsiQ_${Q-k>6azm&_0ev z6d8af0kYFuDl(;Wxb1ln9Rt>3sq^091VK@W+b|y?t{6iN99Bs}l0;?dq23Rjr7@{m zD9aL+8)3<6h^E6=RtcTm>^K@I2n`h~01Oc`>ZYQpiY9cA`N;!rB%bj*!G! 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All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------------------------ | Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018 -| Date : Fri Apr 15 14:10:48 2022 +| Date : Wed May 11 17:31:06 2022 | Host : fabricant running 64-bit Ubuntu 18.04.4 LTS | Command : report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 200 -input_pins -name timing -file picorv32.rpt | Design : picorv32_wrapper diff --git a/burn/z1/picorv/picorv32.tcl b/burn/z1/picorv/picorv32.tcl index 62ae7a9..825c328 100644 --- a/burn/z1/picorv/picorv32.tcl +++ b/burn/z1/picorv/picorv32.tcl @@ -59,7 +59,7 @@ xilinx.com:ip:xlconcat:2.1\ user.org:user:launchpad:1.0\ xilinx.com:ip:axi_protocol_converter:2.1\ UCSD:hlsip:pulsegen:1.0\ -user.org:user:pulsegen_sync:1.0\ +colindrewes.com:colindrewes:pulsegen_v:1.0\ xilinx.com:ip:axi_gpio:2.0\ cliffordwolf:ip:picorv32_bram:1.0\ xilinx.com:ip:axi_bram_ctrl:4.0\ @@ -390,7 +390,7 @@ proc create_hier_cell_chain0 { parentCell nameHier } { set pulsegen [ create_bd_cell -type ip -vlnv UCSD:hlsip:pulsegen:1.0 pulsegen ] # Create instance: pulsegen_sync_0, and set properties - set pulsegen_sync_0 [ create_bd_cell -type ip -vlnv user.org:user:pulsegen_sync:1.0 pulsegen_sync_0 ] + set pulsegen_sync_0 [ create_bd_cell -type ip -vlnv colindrewes.com:colindrewes:pulsegen_v:1.0 pulsegen_sync_0 ] # Create instance: resetGpio, and set properties set resetGpio [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 resetGpio ]