diff --git a/config.json b/config.json index dd8541f..ae2405f 100644 --- a/config.json +++ b/config.json @@ -39,12 +39,13 @@ "darkriscv": { "name": "darkriscv", "folder": "darkriscv", - "sim_files": [ - ], + "sim_files": [], "files": [ "rtl/darkriscv.v" ], - "include_dirs": ["rtl"], + "include_dirs": [ + "rtl" + ], "repository": "https://github.com/darklife/darkriscv", "top_module": "darkriscv", "extra_flags": [], @@ -66,9 +67,7 @@ "tinyriscv": { "name": "tinyriscv", "folder": "tinyriscv", - "sim_files": [ - - ], + "sim_files": [], "files": [ "rtl/core/clint.v", "rtl/core/csr_reg.v", @@ -95,9 +94,7 @@ "AUK-V-Aethia": { "name": "AUK-V-Aethia", "folder": "AUK-V-Aethia", - "sim_files": [ - - ], + "sim_files": [], "files": [ "rtl/core/aukv.v", "rtl/core/aukv_alu.v", @@ -140,8 +137,7 @@ ], "language_version": "2005", "top_module": "rv_core", - "sim_files": [ - ], + "sim_files": [], "include_dirs": [], "extra_flags": [], "enable": false @@ -236,8 +232,7 @@ "riscado-v": { "name": "riscado-v", "folder": "riscado-v", - "sim_files": [ - ], + "sim_files": [], "files": [ "alu.v", "control_unit.v", @@ -255,8 +250,7 @@ "rv3n": { "name": "rv3n", "folder": "rv3n", - "sim_files": [ - ], + "sim_files": [], "files": [ "rtl/define.v", "rtl/define_para.v", @@ -275,7 +269,9 @@ "rtl/rv3n_stage_if.v", "rtl/rv3n_top.v" ], - "include_dirs": ["rtl"], + "include_dirs": [ + "rtl" + ], "repository": "https://github.com/risclite/rv3n", "top_module": "rv3n_top", "extra_flags": [], @@ -284,8 +280,7 @@ "riskow": { "name": "riskow", "folder": "riskow", - "sim_files": [ - ], + "sim_files": [], "files": [ "cpu/alu.v", "cpu/comp.v", @@ -303,8 +298,7 @@ "biriscv": { "name": "biriscv", "folder": "biriscv", - "sim_files": [ - ], + "sim_files": [], "files": [ "src/core/biriscv_alu.v", "src/core/biriscv_csr.v", @@ -338,8 +332,7 @@ "picorv32": { "name": "picorv32", "folder": "picorv32", - "sim_files": [ - ], + "sim_files": [], "files": [ "picorv32.v" ], @@ -352,8 +345,7 @@ "dv-cpu-rv": { "name": "dv-cpu-rv", "folder": "dv-cpu-rv", - "sim_files": [ - ], + "sim_files": [], "files": [ "core/rtl/rv_alu.v", "core/rtl/rv_alu_ctrl.v", @@ -377,9 +369,7 @@ "neorv32": { "name": "neorv32", "folder": "neorv32", - "sim_files": [ - - ], + "sim_files": [], "files": [ "rtl/core/neorv32_application_image.vhd", "rtl/core/neorv32_boot_rom.vhd", @@ -495,9 +485,7 @@ "Pequeno-Risco-5": { "name": "Pequeno-Risco-5", "folder": "Pequeno-Risco-5", - "sim_files": [ - - ], + "sim_files": [], "files": [ "src/alu.v", "src/alu_control.v", @@ -519,9 +507,7 @@ "nerv": { "name": "nerv", "folder": "nerv", - "sim_files": [ - - ], + "sim_files": [], "files": [ "nerv.sv" ], @@ -534,9 +520,7 @@ "cv32e40p": { "name": "cv32e40p", "folder": "cv32e40p", - "sim_files": [ - - ], + "sim_files": [], "files": [ "rtl/cv32e40p_aligner.sv", "rtl/cv32e40p_alu.sv", @@ -577,9 +561,7 @@ "ibex": { "name": "ibex", "folder": "ibex", - "sim_files": [ - - ], + "sim_files": [], "files": [ "rtl/ibex_alu.sv", "rtl/ibex_branch_predict.sv", @@ -621,8 +603,7 @@ "RV12": { "name": "RV12", "folder": "RV12", - "sim_files": [ - ], + "sim_files": [], "files": [ "rtl/verilog/ahb3lite/biu_ahb3lite.sv", "rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv", @@ -687,8 +668,7 @@ "scr1": { "name": "scr1", "folder": "scr1", - "sim_files": [ - ], + "sim_files": [], "files": [ "src/core/scr1_clk_ctrl.sv", "src/core/scr1_core_top.sv", @@ -713,7 +693,9 @@ "src/core/primitives/scr1_cg.sv", "src/core/primitives/scr1_reset_cells.sv" ], - "include_dirs": ["src/includes"], + "include_dirs": [ + "src/includes" + ], "repository": "https://github.com/syntacore/scr1", "top_module": "scr1_core_top", "extra_flags": [], @@ -722,8 +704,7 @@ "Cores-SweRV": { "name": "Cores-SweRV", "folder": "Cores-SweRV", - "sim_files": [ - ], + "sim_files": [], "files": [ "design/dmi/dmi_jtag_to_core_sync.v", "design/dmi/dmi_wrapper.v", @@ -769,7 +750,9 @@ "design/lsu/lsu_lsc_ctl.sv", "design/lsu/lsu_trigger.sv" ], - "include_dirs": ["design/include"], + "include_dirs": [ + "design/include" + ], "repository": "https://github.com/chipsalliance/Cores-SweRV", "top_module": "veer", "extra_flags": [], @@ -778,8 +761,7 @@ "Cores-SweRV-EL2": { "name": "Cores-SweRV-EL2", "folder": "Cores-SweRV-EL2", - "sim_files": [ - ], + "sim_files": [], "files": [ "design/dmi/dmi_jtag_to_core_sync.v", "design/dmi/dmi_mux.v", @@ -829,7 +811,9 @@ "design/lsu/el2_lsu_lsc_ctl.sv", "design/lsu/el2_lsu_trigger.sv" ], - "include_dirs": ["design/include"], + "include_dirs": [ + "design/include" + ], "repository": "https://github.com/chipsalliance/Cores-SweRV-EL2", "top_module": "el2_veer", "extra_flags": [], @@ -838,8 +822,7 @@ "Cores-SweRV-EH2": { "name": "Cores-SweRV-EH2", "folder": "Cores-SweRV-EH2", - "sim_files": [ - ], + "sim_files": [], "files": [ "design/dmi/dmi_jtag_to_core_sync.v", "design/dmi/dmi_wrapper.v", @@ -888,7 +871,9 @@ "design/lsu/eh2_lsu_lsc_ctl.sv", "design/lsu/eh2_lsu_trigger.sv" ], - "include_dirs": ["design/include"], + "include_dirs": [ + "design/include" + ], "repository": "https://github.com/chipsalliance/Cores-SweRV-EH2", "top_module": "eh2_veer", "extra_flags": [], @@ -897,8 +882,7 @@ "RPU": { "name": "RPU", "folder": "RPU", - "sim_files": [ - ], + "sim_files": [], "files": [ "vhdl/constants.vhd", "vhdl/alu_int32_div.vhd", @@ -921,8 +905,7 @@ "Taiga": { "name": "Taiga", "folder": "Taiga", - "sim_files": [ - ], + "sim_files": [], "files": [ "core/addr_hash.sv", "core/alu_unit.sv", @@ -998,8 +981,7 @@ "maestro": { "name": "maestro", "folder": "maestro", - "sim_files": [ - ], + "sim_files": [], "files": [ "Project/Components/ALU.vhd", "Project/Components/EX_MEM_DIV.vhd", @@ -1036,8 +1018,7 @@ "rsd": { "name": "rsd", "folder": "rsd", - "sim_files": [ - ], + "sim_files": [], "files": [ "Processor/Src/BasicMacros.sv", "Processor/Src/BasicTypes.sv", @@ -1208,8 +1189,7 @@ "kronos": { "name": "kronos", "folder": "kronos", - "sim_files": [ - ], + "sim_files": [], "files": [ "rtl/core/kronos_EX.sv", "rtl/core/kronos_ID.sv", @@ -1234,8 +1214,7 @@ "RS5": { "name": "RS5", "folder": "RS5", - "sim_files": [ - ], + "sim_files": [], "files": [ "rtl/CSRBank.sv", "rtl/RS5.sv", @@ -1262,7 +1241,9 @@ "rtl/aes/riscv_crypto_sbox_aes_top.sv", "rtl/aes/riscv_crypto_sbox_inv_mid.sv" ], - "include_dirs": ["rtl/"], + "include_dirs": [ + "rtl/" + ], "repository": "https://github.com/gaph-pucrs/RS5", "top_module": "RS5", "extra_flags": [], @@ -1271,8 +1252,7 @@ "e203_hbirdv2": { "name": "e203_hbirdv2", "folder": "e203_hbirdv2", - "sim_files": [ - ], + "sim_files": [], "files": [ "rtl/e203/core/config.v", "rtl/e203/core/e203_biu.v", @@ -1351,8 +1331,7 @@ "Cores-VeeR-EH2": { "name": "Cores-VeeR-EH2", "folder": "Cores-VeeR-EH2", - "sim_files": [ - ], + "sim_files": [], "files": [ "design/dmi/dmi_jtag_to_core_sync.v", "design/dmi/dmi_wrapper.v", @@ -1410,8 +1389,7 @@ "Cores-VeeR-EL2": { "name": "Cores-VeeR-EL2", "folder": "Cores-VeeR-EL2", - "sim_files": [ - ], + "sim_files": [], "files": [ "design/dmi/dmi_jtag_to_core_sync.v", "design/dmi/dmi_mux.v", @@ -1471,8 +1449,7 @@ "Cores-VeeR-EH1": { "name": "Cores-VeeR-EH1", "folder": "Cores-VeeR-EH1", - "sim_files": [ - ], + "sim_files": [], "files": [ "design/dmi/dmi_jtag_to_core_sync.v", "design/dmi/dmi_wrapper.v", @@ -1529,8 +1506,7 @@ "mriscv": { "name": "mriscv", "folder": "mriscv", - "sim_files": [ - ], + "sim_files": [], "files": [ "mriscvcore/mriscvcore.v", "mriscvcore/ALU/ALU.v", @@ -1551,8 +1527,7 @@ "serv": { "name": "serv", "folder": "serv", - "sim_files": [ - ], + "sim_files": [], "files": [ "rtl/serv_aligner.v", "rtl/serv_alu.v", @@ -1578,11 +1553,11 @@ "extra_flags": [], "language_version": "2005" }, - "VexRiscv":{ - "name":"VexRiscv", - "folder":"VexRiscv", - "sim_files":[], - "files":[ + "VexRiscv": { + "name": "VexRiscv", + "folder": "VexRiscv", + "sim_files": [], + "files": [ "VexRiscv.v" ], "include_dirs": [], @@ -1591,6 +1566,25 @@ "extra_flags": [], "language_version": "2005", "pre_script": "sbt \"runMain vexriscv.demo.GenFull\"" + }, + "Grande-Risco-5": { + "name": "Grande-Risco-5", + "folder": "Grande-Risco-5", + "sim_files": [], + "files": [ + "src/core/alu.v", + "src/core/alu_control.v", + "src/core/core.v", + "src/core/forwarding_unit.v", + "src/core/immediate_generator.v", + "src/core/mux.v", + "src/core/registers.v" + ], + "include_dirs": [], + "repository": "https://github.com/JN513/Grande-Risco-5", + "top_module": "Grande_Risco5", + "extra_flags": [], + "language_version": "2005" } } } \ No newline at end of file diff --git a/core/fpga.py b/core/fpga.py index 02464e4..c53971b 100644 --- a/core/fpga.py +++ b/core/fpga.py @@ -154,7 +154,9 @@ def make_build_file(config: dict, board: str, toolchain_path: str) -> str: ) for i in config['files']: - prefix = get_prefix(board, vhdl=i.endswith('.vhd'), sverilog=i.endswith('.sv')) + prefix = get_prefix( + board, vhdl=i.endswith('.vhd'), sverilog=i.endswith('.sv') + ) file.write(prefix + f' {CURRENT_DIR}/' + i + '\n') file.write(base_config) diff --git a/core/jenkins.py b/core/jenkins.py index 59cc3c9..bf85e48 100644 --- a/core/jenkins.py +++ b/core/jenkins.py @@ -111,7 +111,8 @@ def generate_jenkinsfile( elif is_verilog and not is_vhdl: # Verilog simulation command simulation_command = ( - f'sh "iverilog -o simulation.out -g{lang_version} {extra_flags_str}' + f'sh "/eda/oss-cad-suite/bin/iverilog -o simulation.out -g{lang_version} \ + {extra_flags_str}' + f' -s {config["top_module"]} {include_dirs} {files} {sim_files}"' ) else: diff --git a/jenkins_pipeline/AUK-V-Aethia.Jenkinsfile b/jenkins_pipeline/AUK-V-Aethia.Jenkinsfile index 740c2cd..5de7fa0 100644 --- a/jenkins_pipeline/AUK-V-Aethia.Jenkinsfile +++ b/jenkins_pipeline/AUK-V-Aethia.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf AUK-V-Aethia' - sh 'git clone --recursive https://github.com/veeYceeY/AUK-V-Aethia AUK-V-Aethia' + sh 'git clone --recursive --depth=1 https://github.com/veeYceeY/AUK-V-Aethia AUK-V-Aethia' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("AUK-V-Aethia") { - sh "iverilog -o simulation.out -g2005 -s aukv rtl/core/aukv.v rtl/core/aukv_alu.v rtl/core/aukv_csr_regfile.v rtl/core/aukv_decode.v rtl/core/aukv_execute.v rtl/core/aukv_fetch.v rtl/core/aukv_gpr_regfilie.v rtl/core/aukv_mem.v " + sh "/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s aukv rtl/core/aukv.v rtl/core/aukv_alu.v rtl/core/aukv_csr_regfile.v rtl/core/aukv_decode.v rtl/core/aukv_execute.v rtl/core/aukv_fetch.v rtl/core/aukv_gpr_regfilie.v rtl/core/aukv_mem.v " } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("AUK-V-Aethia") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p AUK-V-Aethia -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p AUK-V-Aethia -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("AUK-V-Aethia") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p AUK-V-Aethia -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p AUK-V-Aethia -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("AUK-V-Aethia") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("AUK-V-Aethia") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p AUK-V-Aethia -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p AUK-V-Aethia -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("AUK-V-Aethia") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p AUK-V-Aethia -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p AUK-V-Aethia -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("AUK-V-Aethia") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/Cores-SweRV-EH2.Jenkinsfile b/jenkins_pipeline/Cores-SweRV-EH2.Jenkinsfile index a4ba033..932ab31 100644 --- a/jenkins_pipeline/Cores-SweRV-EH2.Jenkinsfile +++ b/jenkins_pipeline/Cores-SweRV-EH2.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf Cores-SweRV-EH2' - sh 'git clone --recursive https://github.com/chipsalliance/Cores-SweRV-EH2 Cores-SweRV-EH2' + sh 'git clone --recursive --depth=1 https://github.com/chipsalliance/Cores-SweRV-EH2 Cores-SweRV-EH2' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("Cores-SweRV-EH2") { - sh "iverilog -o simulation.out -g2012 -s eh2_veer -I design/include design/dmi/dmi_jtag_to_core_sync.v design/dmi/dmi_wrapper.v design/dmi/rvjtag_tap.v design/eh2_dma_ctrl.sv design/eh2_mem.sv design/eh2_pic_ctrl.sv design/eh2_veer.sv design/eh2_veer_wrapper.sv design/dbg/eh2_dbg.sv design/dec/eh2_dec.sv design/dec/eh2_dec_csr.sv design/dec/eh2_dec_decode_ctl.sv design/dec/eh2_dec_gpr_ctl.sv design/dec/eh2_dec_ib_ctl.sv design/dec/eh2_dec_tlu_ctl.sv design/dec/eh2_dec_tlu_top.sv design/dec/eh2_dec_trigger.sv design/exu/eh2_exu.sv design/exu/eh2_exu_alu_ctl.sv design/exu/eh2_exu_div_ctl.sv design/exu/eh2_exu_mul_ctl.sv design/ifu/eh2_ifu.sv design/ifu/eh2_ifu_aln_ctl.sv design/ifu/eh2_ifu_bp_ctl.sv design/ifu/eh2_ifu_compress_ctl.sv design/ifu/eh2_ifu_ic_mem.sv design/ifu/eh2_ifu_iccm_mem.sv design/ifu/eh2_ifu_ifc_ctl.sv design/ifu/eh2_ifu_mem_ctl.sv design/include/eh2_def.sv design/lib/ahb_to_axi4.sv design/lib/axi4_to_ahb.sv design/lib/beh_lib.sv design/lib/eh2_lib.sv design/lib/mem_lib.sv design/lsu/eh2_lsu.sv design/lsu/eh2_lsu_addrcheck.sv design/lsu/eh2_lsu_amo.sv design/lsu/eh2_lsu_bus_buffer.sv design/lsu/eh2_lsu_bus_intf.sv design/lsu/eh2_lsu_clkdomain.sv design/lsu/eh2_lsu_dccm_ctl.sv design/lsu/eh2_lsu_dccm_mem.sv design/lsu/eh2_lsu_ecc.sv design/lsu/eh2_lsu_lsc_ctl.sv design/lsu/eh2_lsu_trigger.sv " + sh "/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2012 -s eh2_veer -I design/include design/dmi/dmi_jtag_to_core_sync.v design/dmi/dmi_wrapper.v design/dmi/rvjtag_tap.v design/eh2_dma_ctrl.sv design/eh2_mem.sv design/eh2_pic_ctrl.sv design/eh2_veer.sv design/eh2_veer_wrapper.sv design/dbg/eh2_dbg.sv design/dec/eh2_dec.sv design/dec/eh2_dec_csr.sv design/dec/eh2_dec_decode_ctl.sv design/dec/eh2_dec_gpr_ctl.sv design/dec/eh2_dec_ib_ctl.sv design/dec/eh2_dec_tlu_ctl.sv design/dec/eh2_dec_tlu_top.sv design/dec/eh2_dec_trigger.sv design/exu/eh2_exu.sv design/exu/eh2_exu_alu_ctl.sv design/exu/eh2_exu_div_ctl.sv design/exu/eh2_exu_mul_ctl.sv design/ifu/eh2_ifu.sv design/ifu/eh2_ifu_aln_ctl.sv design/ifu/eh2_ifu_bp_ctl.sv design/ifu/eh2_ifu_compress_ctl.sv design/ifu/eh2_ifu_ic_mem.sv design/ifu/eh2_ifu_iccm_mem.sv design/ifu/eh2_ifu_ifc_ctl.sv design/ifu/eh2_ifu_mem_ctl.sv design/include/eh2_def.sv design/lib/ahb_to_axi4.sv design/lib/axi4_to_ahb.sv design/lib/beh_lib.sv design/lib/eh2_lib.sv design/lib/mem_lib.sv design/lsu/eh2_lsu.sv design/lsu/eh2_lsu_addrcheck.sv design/lsu/eh2_lsu_amo.sv design/lsu/eh2_lsu_bus_buffer.sv design/lsu/eh2_lsu_bus_intf.sv design/lsu/eh2_lsu_clkdomain.sv design/lsu/eh2_lsu_dccm_ctl.sv design/lsu/eh2_lsu_dccm_mem.sv design/lsu/eh2_lsu_ecc.sv design/lsu/eh2_lsu_lsc_ctl.sv design/lsu/eh2_lsu_trigger.sv " } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("Cores-SweRV-EH2") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Cores-SweRV-EH2 -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Cores-SweRV-EH2 -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("Cores-SweRV-EH2") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Cores-SweRV-EH2 -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Cores-SweRV-EH2 -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("Cores-SweRV-EH2") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("Cores-SweRV-EH2") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Cores-SweRV-EH2 -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Cores-SweRV-EH2 -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("Cores-SweRV-EH2") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Cores-SweRV-EH2 -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Cores-SweRV-EH2 -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("Cores-SweRV-EH2") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/Cores-SweRV-EL2.Jenkinsfile b/jenkins_pipeline/Cores-SweRV-EL2.Jenkinsfile index 1a92935..f64d362 100644 --- a/jenkins_pipeline/Cores-SweRV-EL2.Jenkinsfile +++ b/jenkins_pipeline/Cores-SweRV-EL2.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf Cores-SweRV-EL2' - sh 'git clone --recursive https://github.com/chipsalliance/Cores-SweRV-EL2 Cores-SweRV-EL2' + sh 'git clone --recursive --depth=1 https://github.com/chipsalliance/Cores-SweRV-EL2 Cores-SweRV-EL2' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("Cores-SweRV-EL2") { - sh "iverilog -o simulation.out -g2012 -s el2_veer -I design/include design/dmi/dmi_jtag_to_core_sync.v design/dmi/dmi_mux.v design/dmi/dmi_wrapper.v design/dmi/rvjtag_tap.v design/el2_dma_ctrl.sv design/el2_mem.sv design/el2_pic_ctrl.sv design/el2_pmp.sv design/el2_veer.sv design/el2_veer_wrapper.sv design/dbg/el2_dbg.sv design/dec/el2_dec.sv design/dec/el2_dec_decode_ctl.sv design/dec/el2_dec_gpr_ctl.sv design/dec/el2_dec_ib_ctl.sv design/dec/el2_dec_pmp_ctl.sv design/dec/el2_dec_tlu_ctl.sv design/dec/el2_dec_trigger.sv design/exu/el2_exu.sv design/exu/el2_exu_alu_ctl.sv design/exu/el2_exu_div_ctl.sv design/exu/el2_exu_mul_ctl.sv design/ifu/el2_ifu.sv design/ifu/el2_ifu_aln_ctl.sv design/ifu/el2_ifu_bp_ctl.sv design/ifu/el2_ifu_compress_ctl.sv design/ifu/el2_ifu_ic_mem.sv design/ifu/el2_ifu_iccm_mem.sv design/ifu/el2_ifu_ifc_ctl.sv design/ifu/el2_ifu_mem_ctl.sv design/include/el2_def.sv design/lib/ahb_to_axi4.sv design/lib/axi4_to_ahb.sv design/lib/beh_lib.sv design/lib/el2_lib.sv design/lib/el2_mem_if.sv design/lib/mem_lib.sv design/lsu/el2_lsu.sv design/lsu/el2_lsu_addrcheck.sv design/lsu/el2_lsu_bus_buffer.sv design/lsu/el2_lsu_bus_intf.sv design/lsu/el2_lsu_clkdomain.sv design/lsu/el2_lsu_dccm_ctl.sv design/lsu/el2_lsu_dccm_mem.sv design/lsu/el2_lsu_ecc.sv design/lsu/el2_lsu_lsc_ctl.sv design/lsu/el2_lsu_trigger.sv " + sh "/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2012 -s el2_veer -I design/include design/dmi/dmi_jtag_to_core_sync.v design/dmi/dmi_mux.v design/dmi/dmi_wrapper.v design/dmi/rvjtag_tap.v design/el2_dma_ctrl.sv design/el2_mem.sv design/el2_pic_ctrl.sv design/el2_pmp.sv design/el2_veer.sv design/el2_veer_wrapper.sv design/dbg/el2_dbg.sv design/dec/el2_dec.sv design/dec/el2_dec_decode_ctl.sv design/dec/el2_dec_gpr_ctl.sv design/dec/el2_dec_ib_ctl.sv design/dec/el2_dec_pmp_ctl.sv design/dec/el2_dec_tlu_ctl.sv design/dec/el2_dec_trigger.sv design/exu/el2_exu.sv design/exu/el2_exu_alu_ctl.sv design/exu/el2_exu_div_ctl.sv design/exu/el2_exu_mul_ctl.sv design/ifu/el2_ifu.sv design/ifu/el2_ifu_aln_ctl.sv design/ifu/el2_ifu_bp_ctl.sv design/ifu/el2_ifu_compress_ctl.sv design/ifu/el2_ifu_ic_mem.sv design/ifu/el2_ifu_iccm_mem.sv design/ifu/el2_ifu_ifc_ctl.sv design/ifu/el2_ifu_mem_ctl.sv design/include/el2_def.sv design/lib/ahb_to_axi4.sv design/lib/axi4_to_ahb.sv design/lib/beh_lib.sv design/lib/el2_lib.sv design/lib/el2_mem_if.sv design/lib/mem_lib.sv design/lsu/el2_lsu.sv design/lsu/el2_lsu_addrcheck.sv design/lsu/el2_lsu_bus_buffer.sv design/lsu/el2_lsu_bus_intf.sv design/lsu/el2_lsu_clkdomain.sv design/lsu/el2_lsu_dccm_ctl.sv design/lsu/el2_lsu_dccm_mem.sv design/lsu/el2_lsu_ecc.sv design/lsu/el2_lsu_lsc_ctl.sv design/lsu/el2_lsu_trigger.sv " } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("Cores-SweRV-EL2") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Cores-SweRV-EL2 -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Cores-SweRV-EL2 -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("Cores-SweRV-EL2") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Cores-SweRV-EL2 -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Cores-SweRV-EL2 -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("Cores-SweRV-EL2") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("Cores-SweRV-EL2") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Cores-SweRV-EL2 -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Cores-SweRV-EL2 -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("Cores-SweRV-EL2") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Cores-SweRV-EL2 -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Cores-SweRV-EL2 -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("Cores-SweRV-EL2") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/Cores-SweRV.Jenkinsfile b/jenkins_pipeline/Cores-SweRV.Jenkinsfile index b3c3534..88c210e 100644 --- a/jenkins_pipeline/Cores-SweRV.Jenkinsfile +++ b/jenkins_pipeline/Cores-SweRV.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf Cores-SweRV' - sh 'git clone --recursive https://github.com/chipsalliance/Cores-SweRV Cores-SweRV' + sh 'git clone --recursive --depth=1 https://github.com/chipsalliance/Cores-SweRV Cores-SweRV' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("Cores-SweRV") { - sh "iverilog -o simulation.out -g2012 -s veer -I design/include design/dmi/dmi_jtag_to_core_sync.v design/dmi/dmi_wrapper.v design/dma_ctrl.sv design/mem.sv design/pic_ctrl.sv design/veer.sv design/veer_wrapper.sv design/dbg/dbg.sv design/dec/dec.sv design/dec/dec_decode_ctl.sv design/dec/dec_gpr_ctl.sv design/dec/dec_ib_ctl.sv design/dec/dec_tlu_ctl.sv design/dec/dec_trigger.sv design/dmi/rvjtag_tap.sv design/exu/exu.sv design/exu/exu_alu_ctl.sv design/exu/exu_div_ctl.sv design/exu/exu_mul_ctl.sv design/ifu/ifu.sv design/ifu/ifu_aln_ctl.sv design/ifu/ifu_bp_ctl.sv design/ifu/ifu_compress_ctl.sv design/ifu/ifu_ic_mem.sv design/ifu/ifu_iccm_mem.sv design/ifu/ifu_ifc_ctl.sv design/ifu/ifu_mem_ctl.sv design/include/veer_types.sv design/lib/ahb_to_axi4.sv design/lib/axi4_to_ahb.sv design/lib/beh_lib.sv design/lib/mem_lib.sv design/lib/svci_to_axi4.sv design/lsu/lsu.sv design/lsu/lsu_addrcheck.sv design/lsu/lsu_bus_buffer.sv design/lsu/lsu_bus_intf.sv design/lsu/lsu_clkdomain.sv design/lsu/lsu_dccm_ctl.sv design/lsu/lsu_dccm_mem.sv design/lsu/lsu_ecc.sv design/lsu/lsu_lsc_ctl.sv design/lsu/lsu_trigger.sv " + sh "/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2012 -s veer -I design/include design/dmi/dmi_jtag_to_core_sync.v design/dmi/dmi_wrapper.v design/dma_ctrl.sv design/mem.sv design/pic_ctrl.sv design/veer.sv design/veer_wrapper.sv design/dbg/dbg.sv design/dec/dec.sv design/dec/dec_decode_ctl.sv design/dec/dec_gpr_ctl.sv design/dec/dec_ib_ctl.sv design/dec/dec_tlu_ctl.sv design/dec/dec_trigger.sv design/dmi/rvjtag_tap.sv design/exu/exu.sv design/exu/exu_alu_ctl.sv design/exu/exu_div_ctl.sv design/exu/exu_mul_ctl.sv design/ifu/ifu.sv design/ifu/ifu_aln_ctl.sv design/ifu/ifu_bp_ctl.sv design/ifu/ifu_compress_ctl.sv design/ifu/ifu_ic_mem.sv design/ifu/ifu_iccm_mem.sv design/ifu/ifu_ifc_ctl.sv design/ifu/ifu_mem_ctl.sv design/include/veer_types.sv design/lib/ahb_to_axi4.sv design/lib/axi4_to_ahb.sv design/lib/beh_lib.sv design/lib/mem_lib.sv design/lib/svci_to_axi4.sv design/lsu/lsu.sv design/lsu/lsu_addrcheck.sv design/lsu/lsu_bus_buffer.sv design/lsu/lsu_bus_intf.sv design/lsu/lsu_clkdomain.sv design/lsu/lsu_dccm_ctl.sv design/lsu/lsu_dccm_mem.sv design/lsu/lsu_ecc.sv design/lsu/lsu_lsc_ctl.sv design/lsu/lsu_trigger.sv " } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("Cores-SweRV") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Cores-SweRV -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Cores-SweRV -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("Cores-SweRV") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Cores-SweRV -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Cores-SweRV -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("Cores-SweRV") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("Cores-SweRV") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Cores-SweRV -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Cores-SweRV -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("Cores-SweRV") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Cores-SweRV -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Cores-SweRV -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("Cores-SweRV") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/Cores-VeeR-EH1.Jenkinsfile b/jenkins_pipeline/Cores-VeeR-EH1.Jenkinsfile index cb7393c..16c427c 100644 --- a/jenkins_pipeline/Cores-VeeR-EH1.Jenkinsfile +++ b/jenkins_pipeline/Cores-VeeR-EH1.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf Cores-VeeR-EH1' - sh 'git clone --recursive https://github.com/chipsalliance/Cores-VeeR-EH1 Cores-VeeR-EH1' + sh 'git clone --recursive --depth=1 https://github.com/chipsalliance/Cores-VeeR-EH1 Cores-VeeR-EH1' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("Cores-VeeR-EH1") { - sh "iverilog -o simulation.out -g2012 -s veer -I design/include design/dmi/dmi_jtag_to_core_sync.v design/dmi/dmi_wrapper.v design/dma_ctrl.sv design/mem.sv design/pic_ctrl.sv design/veer.sv design/veer_wrapper.sv design/dbg/dbg.sv design/dec/dec.sv design/dec/dec_decode_ctl.sv design/dec/dec_gpr_ctl.sv design/dec/dec_ib_ctl.sv design/dec/dec_tlu_ctl.sv design/dec/dec_trigger.sv design/dmi/rvjtag_tap.sv design/exu/exu.sv design/exu/exu_alu_ctl.sv design/exu/exu_div_ctl.sv design/exu/exu_mul_ctl.sv design/ifu/ifu.sv design/ifu/ifu_aln_ctl.sv design/ifu/ifu_bp_ctl.sv design/ifu/ifu_compress_ctl.sv design/ifu/ifu_ic_mem.sv design/ifu/ifu_iccm_mem.sv design/ifu/ifu_ifc_ctl.sv design/ifu/ifu_mem_ctl.sv design/include/veer_types.sv design/lib/ahb_to_axi4.sv design/lib/axi4_to_ahb.sv design/lib/beh_lib.sv design/lib/mem_lib.sv design/lib/svci_to_axi4.sv design/lsu/lsu.sv design/lsu/lsu_addrcheck.sv design/lsu/lsu_bus_buffer.sv design/lsu/lsu_bus_intf.sv design/lsu/lsu_clkdomain.sv design/lsu/lsu_dccm_ctl.sv design/lsu/lsu_dccm_mem.sv design/lsu/lsu_ecc.sv design/lsu/lsu_lsc_ctl.sv design/lsu/lsu_trigger.sv " + sh "/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2012 -s veer -I design/include design/dmi/dmi_jtag_to_core_sync.v design/dmi/dmi_wrapper.v design/dma_ctrl.sv design/mem.sv design/pic_ctrl.sv design/veer.sv design/veer_wrapper.sv design/dbg/dbg.sv design/dec/dec.sv design/dec/dec_decode_ctl.sv design/dec/dec_gpr_ctl.sv design/dec/dec_ib_ctl.sv design/dec/dec_tlu_ctl.sv design/dec/dec_trigger.sv design/dmi/rvjtag_tap.sv design/exu/exu.sv design/exu/exu_alu_ctl.sv design/exu/exu_div_ctl.sv design/exu/exu_mul_ctl.sv design/ifu/ifu.sv design/ifu/ifu_aln_ctl.sv design/ifu/ifu_bp_ctl.sv design/ifu/ifu_compress_ctl.sv design/ifu/ifu_ic_mem.sv design/ifu/ifu_iccm_mem.sv design/ifu/ifu_ifc_ctl.sv design/ifu/ifu_mem_ctl.sv design/include/veer_types.sv design/lib/ahb_to_axi4.sv design/lib/axi4_to_ahb.sv design/lib/beh_lib.sv design/lib/mem_lib.sv design/lib/svci_to_axi4.sv design/lsu/lsu.sv design/lsu/lsu_addrcheck.sv design/lsu/lsu_bus_buffer.sv design/lsu/lsu_bus_intf.sv design/lsu/lsu_clkdomain.sv design/lsu/lsu_dccm_ctl.sv design/lsu/lsu_dccm_mem.sv design/lsu/lsu_ecc.sv design/lsu/lsu_lsc_ctl.sv design/lsu/lsu_trigger.sv " } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("Cores-VeeR-EH1") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Cores-VeeR-EH1 -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Cores-VeeR-EH1 -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("Cores-VeeR-EH1") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Cores-VeeR-EH1 -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Cores-VeeR-EH1 -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("Cores-VeeR-EH1") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("Cores-VeeR-EH1") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Cores-VeeR-EH1 -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Cores-VeeR-EH1 -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("Cores-VeeR-EH1") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Cores-VeeR-EH1 -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Cores-VeeR-EH1 -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("Cores-VeeR-EH1") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/Cores-VeeR-EH2.Jenkinsfile b/jenkins_pipeline/Cores-VeeR-EH2.Jenkinsfile index 6066c6c..b2ce016 100644 --- a/jenkins_pipeline/Cores-VeeR-EH2.Jenkinsfile +++ b/jenkins_pipeline/Cores-VeeR-EH2.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf Cores-VeeR-EH2' - sh 'git clone --recursive https://github.com/chipsalliance/Cores-VeeR-EH2 Cores-VeeR-EH2' + sh 'git clone --recursive --depth=1 https://github.com/chipsalliance/Cores-VeeR-EH2 Cores-VeeR-EH2' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("Cores-VeeR-EH2") { - sh "iverilog -o simulation.out -g2012 -s eh2_veer -I design/include design/dmi/dmi_jtag_to_core_sync.v design/dmi/dmi_wrapper.v design/dmi/rvjtag_tap.v design/eh2_dma_ctrl.sv design/eh2_pic_ctrl.sv design/eh2_veer.sv design/dbg/eh2_dbg.sv design/dec/eh2_dec.sv design/dec/eh2_dec_csr.sv design/dec/eh2_dec_decode_ctl.sv design/dec/eh2_dec_gpr_ctl.sv design/dec/eh2_dec_ib_ctl.sv design/dec/eh2_dec_tlu_ctl.sv design/dec/eh2_dec_tlu_top.sv design/dec/eh2_dec_trigger.sv design/exu/eh2_exu.sv design/exu/eh2_exu_alu_ctl.sv design/exu/eh2_exu_div_ctl.sv design/exu/eh2_exu_mul_ctl.sv design/ifu/eh2_ifu.sv design/ifu/eh2_ifu_aln_ctl.sv design/ifu/eh2_ifu_bp_ctl.sv design/ifu/eh2_ifu_compress_ctl.sv design/ifu/eh2_ifu_ic_mem.sv design/ifu/eh2_ifu_iccm_mem.sv design/ifu/eh2_ifu_ifc_ctl.sv design/ifu/eh2_ifu_mem_ctl.sv design/include/eh2_def.sv design/lib/ahb_to_axi4.sv design/lib/axi4_to_ahb.sv design/lib/beh_lib.sv design/lib/eh2_lib.sv design/lib/mem_lib.sv design/lsu/eh2_lsu.sv design/lsu/eh2_lsu_addrcheck.sv design/lsu/eh2_lsu_amo.sv design/lsu/eh2_lsu_bus_buffer.sv design/lsu/eh2_lsu_bus_intf.sv design/lsu/eh2_lsu_clkdomain.sv design/lsu/eh2_lsu_dccm_ctl.sv design/lsu/eh2_lsu_dccm_mem.sv design/lsu/eh2_lsu_ecc.sv design/lsu/eh2_lsu_lsc_ctl.sv design/lsu/eh2_lsu_trigger.sv " + sh "/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2012 -s eh2_veer -I design/include design/dmi/dmi_jtag_to_core_sync.v design/dmi/dmi_wrapper.v design/dmi/rvjtag_tap.v design/eh2_dma_ctrl.sv design/eh2_pic_ctrl.sv design/eh2_veer.sv design/dbg/eh2_dbg.sv design/dec/eh2_dec.sv design/dec/eh2_dec_csr.sv design/dec/eh2_dec_decode_ctl.sv design/dec/eh2_dec_gpr_ctl.sv design/dec/eh2_dec_ib_ctl.sv design/dec/eh2_dec_tlu_ctl.sv design/dec/eh2_dec_tlu_top.sv design/dec/eh2_dec_trigger.sv design/exu/eh2_exu.sv design/exu/eh2_exu_alu_ctl.sv design/exu/eh2_exu_div_ctl.sv design/exu/eh2_exu_mul_ctl.sv design/ifu/eh2_ifu.sv design/ifu/eh2_ifu_aln_ctl.sv design/ifu/eh2_ifu_bp_ctl.sv design/ifu/eh2_ifu_compress_ctl.sv design/ifu/eh2_ifu_ic_mem.sv design/ifu/eh2_ifu_iccm_mem.sv design/ifu/eh2_ifu_ifc_ctl.sv design/ifu/eh2_ifu_mem_ctl.sv design/include/eh2_def.sv design/lib/ahb_to_axi4.sv design/lib/axi4_to_ahb.sv design/lib/beh_lib.sv design/lib/eh2_lib.sv design/lib/mem_lib.sv design/lsu/eh2_lsu.sv design/lsu/eh2_lsu_addrcheck.sv design/lsu/eh2_lsu_amo.sv design/lsu/eh2_lsu_bus_buffer.sv design/lsu/eh2_lsu_bus_intf.sv design/lsu/eh2_lsu_clkdomain.sv design/lsu/eh2_lsu_dccm_ctl.sv design/lsu/eh2_lsu_dccm_mem.sv design/lsu/eh2_lsu_ecc.sv design/lsu/eh2_lsu_lsc_ctl.sv design/lsu/eh2_lsu_trigger.sv " } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("Cores-VeeR-EH2") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Cores-VeeR-EH2 -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Cores-VeeR-EH2 -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("Cores-VeeR-EH2") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Cores-VeeR-EH2 -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Cores-VeeR-EH2 -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("Cores-VeeR-EH2") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("Cores-VeeR-EH2") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Cores-VeeR-EH2 -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Cores-VeeR-EH2 -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("Cores-VeeR-EH2") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Cores-VeeR-EH2 -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Cores-VeeR-EH2 -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("Cores-VeeR-EH2") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/Cores-VeeR-EL2.Jenkinsfile b/jenkins_pipeline/Cores-VeeR-EL2.Jenkinsfile index af29f90..1776b9d 100644 --- a/jenkins_pipeline/Cores-VeeR-EL2.Jenkinsfile +++ b/jenkins_pipeline/Cores-VeeR-EL2.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf Cores-VeeR-EL2' - sh 'git clone --recursive https://github.com/chipsalliance/Cores-VeeR-EL2 Cores-VeeR-EL2' + sh 'git clone --recursive --depth=1 https://github.com/chipsalliance/Cores-VeeR-EL2 Cores-VeeR-EL2' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("Cores-VeeR-EL2") { - sh "iverilog -o simulation.out -g2012 -s el2_veer -I design/include/ design/dmi/dmi_jtag_to_core_sync.v design/dmi/dmi_mux.v design/dmi/dmi_wrapper.v design/dmi/rvjtag_tap.v design/el2_dma_ctrl.sv design/el2_mem.sv design/el2_pic_ctrl.sv design/el2_pmp.sv design/el2_veer.sv design/dbg/el2_dbg.sv design/dec/el2_dec.sv design/dec/el2_dec_decode_ctl.sv design/dec/el2_dec_gpr_ctl.sv design/dec/el2_dec_ib_ctl.sv design/dec/el2_dec_pmp_ctl.sv design/dec/el2_dec_tlu_ctl.sv design/dec/el2_dec_trigger.sv design/exu/el2_exu.sv design/exu/el2_exu_alu_ctl.sv design/exu/el2_exu_div_ctl.sv design/exu/el2_exu_mul_ctl.sv design/ifu/el2_ifu.sv design/ifu/el2_ifu_aln_ctl.sv design/ifu/el2_ifu_bp_ctl.sv design/ifu/el2_ifu_compress_ctl.sv design/ifu/el2_ifu_ic_mem.sv design/ifu/el2_ifu_iccm_mem.sv design/ifu/el2_ifu_ifc_ctl.sv design/ifu/el2_ifu_mem_ctl.sv design/include/el2_def.sv design/lib/ahb_to_axi4.sv design/lib/axi4_to_ahb.sv design/lib/beh_lib.sv design/lib/el2_lib.sv design/lib/el2_mem_if.sv design/lib/mem_lib.sv design/lsu/el2_lsu.sv design/lsu/el2_lsu_addrcheck.sv design/lsu/el2_lsu_bus_buffer.sv design/lsu/el2_lsu_bus_intf.sv design/lsu/el2_lsu_clkdomain.sv design/lsu/el2_lsu_dccm_ctl.sv design/lsu/el2_lsu_dccm_mem.sv design/lsu/el2_lsu_ecc.sv design/lsu/el2_lsu_lsc_ctl.sv design/lsu/el2_lsu_trigger.sv " + sh "/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2012 -s el2_veer -I design/include/ design/dmi/dmi_jtag_to_core_sync.v design/dmi/dmi_mux.v design/dmi/dmi_wrapper.v design/dmi/rvjtag_tap.v design/el2_dma_ctrl.sv design/el2_mem.sv design/el2_pic_ctrl.sv design/el2_pmp.sv design/el2_veer.sv design/dbg/el2_dbg.sv design/dec/el2_dec.sv design/dec/el2_dec_decode_ctl.sv design/dec/el2_dec_gpr_ctl.sv design/dec/el2_dec_ib_ctl.sv design/dec/el2_dec_pmp_ctl.sv design/dec/el2_dec_tlu_ctl.sv design/dec/el2_dec_trigger.sv design/exu/el2_exu.sv design/exu/el2_exu_alu_ctl.sv design/exu/el2_exu_div_ctl.sv design/exu/el2_exu_mul_ctl.sv design/ifu/el2_ifu.sv design/ifu/el2_ifu_aln_ctl.sv design/ifu/el2_ifu_bp_ctl.sv design/ifu/el2_ifu_compress_ctl.sv design/ifu/el2_ifu_ic_mem.sv design/ifu/el2_ifu_iccm_mem.sv design/ifu/el2_ifu_ifc_ctl.sv design/ifu/el2_ifu_mem_ctl.sv design/include/el2_def.sv design/lib/ahb_to_axi4.sv design/lib/axi4_to_ahb.sv design/lib/beh_lib.sv design/lib/el2_lib.sv design/lib/el2_mem_if.sv design/lib/mem_lib.sv design/lsu/el2_lsu.sv design/lsu/el2_lsu_addrcheck.sv design/lsu/el2_lsu_bus_buffer.sv design/lsu/el2_lsu_bus_intf.sv design/lsu/el2_lsu_clkdomain.sv design/lsu/el2_lsu_dccm_ctl.sv design/lsu/el2_lsu_dccm_mem.sv design/lsu/el2_lsu_ecc.sv design/lsu/el2_lsu_lsc_ctl.sv design/lsu/el2_lsu_trigger.sv " } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("Cores-VeeR-EL2") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Cores-VeeR-EL2 -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Cores-VeeR-EL2 -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("Cores-VeeR-EL2") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Cores-VeeR-EL2 -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Cores-VeeR-EL2 -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("Cores-VeeR-EL2") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("Cores-VeeR-EL2") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Cores-VeeR-EL2 -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Cores-VeeR-EL2 -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("Cores-VeeR-EL2") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Cores-VeeR-EL2 -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Cores-VeeR-EL2 -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("Cores-VeeR-EL2") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/DV-CPU-RV.Jenkinsfile b/jenkins_pipeline/DV-CPU-RV.Jenkinsfile index e0cab85..0dc6770 100644 --- a/jenkins_pipeline/DV-CPU-RV.Jenkinsfile +++ b/jenkins_pipeline/DV-CPU-RV.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf DV-CPU-RV' - sh 'git clone --recursive https://github.com/devindang/dv-cpu-rv.git DV-CPU-RV' + sh 'git clone --recursive --depth=1 https://github.com/devindang/dv-cpu-rv.git DV-CPU-RV' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("DV-CPU-RV") { - sh "iverilog -o simulation.out -g2005 -s rv_core core/rtl/rv_alu.v core/rtl/rv_alu_ctrl.v core/rtl/rv_branch_predict.v core/rtl/rv_branch_test.v core/rtl/rv_core.v core/rtl/rv_ctrl.v core/rtl/rv_data_mem.v core/rtl/rv_div.v core/rtl/rv_dpram.v core/rtl/rv_forward.v core/rtl/rv_hzd_detect.v core/rtl/rv_imm_gen.v core/rtl/rv_instr_mem.v core/rtl/rv_mem_map.v core/rtl/rv_mul.v core/rtl/rv_rf.v core/rtl/rv_instr_mem.v core/rtl/rv_data_mem.v " + sh "/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s rv_core core/rtl/rv_alu.v core/rtl/rv_alu_ctrl.v core/rtl/rv_branch_predict.v core/rtl/rv_branch_test.v core/rtl/rv_core.v core/rtl/rv_ctrl.v core/rtl/rv_data_mem.v core/rtl/rv_div.v core/rtl/rv_dpram.v core/rtl/rv_forward.v core/rtl/rv_hzd_detect.v core/rtl/rv_imm_gen.v core/rtl/rv_instr_mem.v core/rtl/rv_mem_map.v core/rtl/rv_mul.v core/rtl/rv_rf.v core/rtl/rv_instr_mem.v core/rtl/rv_data_mem.v " } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("DV-CPU-RV") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p DV-CPU-RV -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p DV-CPU-RV -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("DV-CPU-RV") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p DV-CPU-RV -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p DV-CPU-RV -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("DV-CPU-RV") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("DV-CPU-RV") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p DV-CPU-RV -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p DV-CPU-RV -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("DV-CPU-RV") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p DV-CPU-RV -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p DV-CPU-RV -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("DV-CPU-RV") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/F03x.Jenkinsfile b/jenkins_pipeline/F03x.Jenkinsfile index b26b7f0..085ff04 100644 --- a/jenkins_pipeline/F03x.Jenkinsfile +++ b/jenkins_pipeline/F03x.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf F03x' - sh 'git clone --recursive https://github.com/klessydra/F03x F03x' + sh 'git clone --recursive --depth=1 https://github.com/klessydra/F03x F03x' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("F03x") { - sh "ghdl -a --std=08 klessydra-f0-3th/PKG_RiscV_Klessydra_thread_parameters.vhd klessydra-f0-3th/PKG_RiscV_Klessydra.vhd klessydra-f0-3th/TMR_REG_PKG.vhd klessydra-f0-3th/CMP-TMR_REG.vhd klessydra-f0-3th/RTL-CSR_Unit_TMR.vhd klessydra-f0-3th/RTL-Debug_Unit.vhd klessydra-f0-3th/RTL-Processing_Pipeline_TMR.vhd klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd klessydra-f0-3th/STR-Klessydra_top.vhd " + sh "ghdl -a --std=08 klessydra-f0-3th/PKG_RiscV_Klessydra_thread_parameters.vhd klessydra-f0-3th/PKG_RiscV_Klessydra.vhd klessydra-f0-3th/TMR_REG_PKG.vhd klessydra-f0-3th/CMP-TMR_REG.vhd klessydra-f0-3th/RTL-CSR_Unit_TMR.vhd klessydra-f0-3th/RTL-Debug_Unit.vhd klessydra-f0-3th/RTL-Processing_Pipeline_TMR.vhd klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd klessydra-f0-3th/STR-Klessydra_top.vhd " } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("F03x") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p F03x -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p F03x -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("F03x") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p F03x -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p F03x -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("F03x") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("F03x") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p F03x -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p F03x -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("F03x") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p F03x -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p F03x -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("F03x") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/Grande-Risco-5.Jenkinsfile b/jenkins_pipeline/Grande-Risco-5.Jenkinsfile new file mode 100644 index 0000000..556dce9 --- /dev/null +++ b/jenkins_pipeline/Grande-Risco-5.Jenkinsfile @@ -0,0 +1,102 @@ + +pipeline { + agent any + stages { + stage('Git Clone') { + steps { + sh 'rm -rf Grande-Risco-5' + sh 'git clone --recursive --depth=1 https://github.com/JN513/Grande-Risco-5 Grande-Risco-5' + } + } + + + + stage('Simulation') { + steps { + dir("Grande-Risco-5") { + sh "/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s Grande_Risco5 src/core/alu.v src/core/alu_control.v src/core/core.v src/core/forwarding_unit.v src/core/immediate_generator.v src/core/mux.v src/core/registers.v " + } + } + } + + stage('FPGA Build Pipeline') { + parallel { + + stage('colorlight_i9') { + options { + lock(resource: 'colorlight_i9') + } + stages { + stage('Synthesis and PnR') { + steps { + dir("Grande-Risco-5") { + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Grande-Risco-5 -b colorlight_i9' + } + } + } + stage('Flash colorlight_i9') { + steps { + dir("Grande-Risco-5") { + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Grande-Risco-5 -b colorlight_i9 -l' + } + } + } + stage('Test colorlight_i9') { + steps { + echo 'Testing FPGA colorlight_i9.' + dir("Grande-Risco-5") { + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' + } + } + } + } + } + + stage('digilent_nexys4_ddr') { + options { + lock(resource: 'digilent_nexys4_ddr') + } + stages { + stage('Synthesis and PnR') { + steps { + dir("Grande-Risco-5") { + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Grande-Risco-5 -b digilent_nexys4_ddr' + } + } + } + stage('Flash digilent_nexys4_ddr') { + steps { + dir("Grande-Risco-5") { + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Grande-Risco-5 -b digilent_nexys4_ddr -l' + } + } + } + stage('Test digilent_nexys4_ddr') { + steps { + echo 'Testing FPGA digilent_nexys4_ddr.' + dir("Grande-Risco-5") { + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' + } + } + } + } + } + } + } + } + post { + always { + junit '**/test-reports/*.xml' + } + } +} diff --git a/jenkins_pipeline/Pequeno-Risco-5.Jenkinsfile b/jenkins_pipeline/Pequeno-Risco-5.Jenkinsfile index 088a7e3..f9b1c20 100644 --- a/jenkins_pipeline/Pequeno-Risco-5.Jenkinsfile +++ b/jenkins_pipeline/Pequeno-Risco-5.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf Pequeno-Risco-5' - sh 'git clone --recursive https://github.com/JN513/Pequeno-Risco-5 Pequeno-Risco-5' + sh 'git clone --recursive --depth=1 https://github.com/JN513/Pequeno-Risco-5 Pequeno-Risco-5' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("Pequeno-Risco-5") { - sh "iverilog -o simulation.out -g2005 -s Core src/alu.v src/alu_control.v src/control_unit.v src/core.v src/immediate_generator.v src/mux.v src/pc.v src/registers.v src/instruction_memory.v src/data_memory.v " + sh "/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s Core src/alu.v src/alu_control.v src/control_unit.v src/core.v src/immediate_generator.v src/mux.v src/pc.v src/registers.v src/instruction_memory.v src/data_memory.v " } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("Pequeno-Risco-5") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Pequeno-Risco-5 -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Pequeno-Risco-5 -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("Pequeno-Risco-5") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Pequeno-Risco-5 -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Pequeno-Risco-5 -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("Pequeno-Risco-5") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("Pequeno-Risco-5") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Pequeno-Risco-5 -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Pequeno-Risco-5 -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("Pequeno-Risco-5") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Pequeno-Risco-5 -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Pequeno-Risco-5 -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("Pequeno-Risco-5") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/RPU.Jenkinsfile b/jenkins_pipeline/RPU.Jenkinsfile index 62801f8..7866593 100644 --- a/jenkins_pipeline/RPU.Jenkinsfile +++ b/jenkins_pipeline/RPU.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf RPU' - sh 'git clone --recursive https://github.com/Domipheus/RPU RPU' + sh 'git clone --recursive --depth=1 https://github.com/Domipheus/RPU RPU' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("RPU") { - sh "ghdl -a --std=08 vhdl/constants.vhd vhdl/alu_int32_div.vhd vhdl/control_unit.vhd vhdl/core.vhd vhdl/csr_unit.vhd vhdl/lint_unit.vhd vhdl/mem_controller.vhd vhdl/pc_unit.vhd vhdl/register_set.vhd vhdl/unit_alu_RV32_I.vhd vhdl/unit_decoder_RV32I.vhd " + sh "ghdl -a --std=08 vhdl/constants.vhd vhdl/alu_int32_div.vhd vhdl/control_unit.vhd vhdl/core.vhd vhdl/csr_unit.vhd vhdl/lint_unit.vhd vhdl/mem_controller.vhd vhdl/pc_unit.vhd vhdl/register_set.vhd vhdl/unit_alu_RV32_I.vhd vhdl/unit_decoder_RV32I.vhd " } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("RPU") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p RPU -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p RPU -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("RPU") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p RPU -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p RPU -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("RPU") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("RPU") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p RPU -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p RPU -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("RPU") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p RPU -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p RPU -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("RPU") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/RS5.Jenkinsfile b/jenkins_pipeline/RS5.Jenkinsfile index 4a8ac5a..7bf68cf 100644 --- a/jenkins_pipeline/RS5.Jenkinsfile +++ b/jenkins_pipeline/RS5.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf RS5' - sh 'git clone --recursive https://github.com/gaph-pucrs/RS5 RS5' + sh 'git clone --recursive --depth=1 https://github.com/gaph-pucrs/RS5 RS5' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("RS5") { - sh "iverilog -o simulation.out -g2012 -s RS5 -I rtl/ rtl/CSRBank.sv rtl/RS5.sv rtl/aes_unit.sv rtl/align.sv rtl/decode.sv rtl/decompresser.sv rtl/div.sv rtl/execute.sv rtl/fetch.sv rtl/mmu.sv rtl/mul.sv rtl/mulNbits.sv rtl/regbank.sv rtl/retire.sv rtl/vectorALU.sv rtl/vectorCSRs.sv rtl/vectorLSU.sv rtl/vectorRegbank.sv rtl/vectorUnit.sv rtl/aes/riscv_crypto_aes_fwd_sbox.sv rtl/aes/riscv_crypto_aes_sbox.sv rtl/aes/riscv_crypto_sbox_aes_out.sv rtl/aes/riscv_crypto_sbox_aes_top.sv rtl/aes/riscv_crypto_sbox_inv_mid.sv " + sh "/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2012 -s RS5 -I rtl/ rtl/CSRBank.sv rtl/RS5.sv rtl/aes_unit.sv rtl/align.sv rtl/decode.sv rtl/decompresser.sv rtl/div.sv rtl/execute.sv rtl/fetch.sv rtl/mmu.sv rtl/mul.sv rtl/mulNbits.sv rtl/regbank.sv rtl/retire.sv rtl/vectorALU.sv rtl/vectorCSRs.sv rtl/vectorLSU.sv rtl/vectorRegbank.sv rtl/vectorUnit.sv rtl/aes/riscv_crypto_aes_fwd_sbox.sv rtl/aes/riscv_crypto_aes_sbox.sv rtl/aes/riscv_crypto_sbox_aes_out.sv rtl/aes/riscv_crypto_sbox_aes_top.sv rtl/aes/riscv_crypto_sbox_inv_mid.sv " } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("RS5") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p RS5 -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p RS5 -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("RS5") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p RS5 -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p RS5 -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("RS5") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("RS5") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p RS5 -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p RS5 -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("RS5") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p RS5 -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p RS5 -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("RS5") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/RV12.Jenkinsfile b/jenkins_pipeline/RV12.Jenkinsfile index 8baa505..6840fad 100644 --- a/jenkins_pipeline/RV12.Jenkinsfile +++ b/jenkins_pipeline/RV12.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf RV12' - sh 'git clone --recursive https://github.com/roalogic/RV12 RV12' + sh 'git clone --recursive --depth=1 https://github.com/roalogic/RV12 RV12' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("RV12") { - sh "iverilog -o simulation.out -g2012 -s riscv_core rtl/verilog/ahb3lite/biu_ahb3lite.sv rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv rtl/verilog/core/riscv_bp.sv rtl/verilog/core/riscv_core.sv rtl/verilog/core/riscv_du.sv rtl/verilog/core/riscv_dwb.sv rtl/verilog/core/riscv_ex.sv rtl/verilog/core/riscv_id.sv rtl/verilog/core/riscv_if.sv rtl/verilog/core/riscv_mem.sv rtl/verilog/core/riscv_parcel_queue.sv rtl/verilog/core/riscv_pd.sv rtl/verilog/core/riscv_rf.sv rtl/verilog/core/riscv_rsb.sv rtl/verilog/core/riscv_state1.10.sv rtl/verilog/core/riscv_state1.7.sv rtl/verilog/core/riscv_state1.9.sv rtl/verilog/core/riscv_state_20240411.sv rtl/verilog/core/riscv_wb.sv rtl/verilog/core/cache/riscv_cache_biu_ctrl.sv rtl/verilog/core/cache/riscv_cache_memory.sv rtl/verilog/core/cache/riscv_cache_setup.sv rtl/verilog/core/cache/riscv_cache_tag.sv rtl/verilog/core/cache/riscv_dcache_core.sv rtl/verilog/core/cache/riscv_dcache_fsm.sv rtl/verilog/core/cache/riscv_icache_core.sv rtl/verilog/core/cache/riscv_icache_fsm.sv rtl/verilog/core/cache/riscv_nodcache_core.sv rtl/verilog/core/cache/riscv_noicache_core.sv rtl/verilog/core/ex/riscv_alu.sv rtl/verilog/core/ex/riscv_bu.sv rtl/verilog/core/ex/riscv_div.sv rtl/verilog/core/ex/riscv_lsu.sv rtl/verilog/core/ex/riscv_mul.sv rtl/verilog/core/memory/riscv_dmem_ctrl.sv rtl/verilog/core/memory/riscv_imem_ctrl.sv rtl/verilog/core/memory/riscv_membuf.sv rtl/verilog/core/memory/riscv_memmisaligned.sv rtl/verilog/core/memory/riscv_mmu.sv rtl/verilog/core/memory/riscv_pmachk.sv rtl/verilog/core/memory/riscv_pmpchk.sv rtl/verilog/core/memory/riscv_wbuf.sv rtl/verilog/core/mmu/riscv_nommu.sv rtl/verilog/pkg/biu_constants_pkg.sv rtl/verilog/pkg/riscv_cache_pkg.sv rtl/verilog/pkg/riscv_du_pkg.sv rtl/verilog/pkg/riscv_opcodes_pkg.sv rtl/verilog/pkg/riscv_pma_pkg.sv rtl/verilog/pkg/riscv_rv12_pkg.sv rtl/verilog/pkg/riscv_state1.10_pkg.sv rtl/verilog/pkg/riscv_state1.7_pkg.sv rtl/verilog/pkg/riscv_state1.9_pkg.sv rtl/verilog/pkg/riscv_state_20240411_pkg.sv " + sh "/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2012 -s riscv_core rtl/verilog/ahb3lite/biu_ahb3lite.sv rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv rtl/verilog/core/riscv_bp.sv rtl/verilog/core/riscv_core.sv rtl/verilog/core/riscv_du.sv rtl/verilog/core/riscv_dwb.sv rtl/verilog/core/riscv_ex.sv rtl/verilog/core/riscv_id.sv rtl/verilog/core/riscv_if.sv rtl/verilog/core/riscv_mem.sv rtl/verilog/core/riscv_parcel_queue.sv rtl/verilog/core/riscv_pd.sv rtl/verilog/core/riscv_rf.sv rtl/verilog/core/riscv_rsb.sv rtl/verilog/core/riscv_state1.10.sv rtl/verilog/core/riscv_state1.7.sv rtl/verilog/core/riscv_state1.9.sv rtl/verilog/core/riscv_state_20240411.sv rtl/verilog/core/riscv_wb.sv rtl/verilog/core/cache/riscv_cache_biu_ctrl.sv rtl/verilog/core/cache/riscv_cache_memory.sv rtl/verilog/core/cache/riscv_cache_setup.sv rtl/verilog/core/cache/riscv_cache_tag.sv rtl/verilog/core/cache/riscv_dcache_core.sv rtl/verilog/core/cache/riscv_dcache_fsm.sv rtl/verilog/core/cache/riscv_icache_core.sv rtl/verilog/core/cache/riscv_icache_fsm.sv rtl/verilog/core/cache/riscv_nodcache_core.sv rtl/verilog/core/cache/riscv_noicache_core.sv rtl/verilog/core/ex/riscv_alu.sv rtl/verilog/core/ex/riscv_bu.sv rtl/verilog/core/ex/riscv_div.sv rtl/verilog/core/ex/riscv_lsu.sv rtl/verilog/core/ex/riscv_mul.sv rtl/verilog/core/memory/riscv_dmem_ctrl.sv rtl/verilog/core/memory/riscv_imem_ctrl.sv rtl/verilog/core/memory/riscv_membuf.sv rtl/verilog/core/memory/riscv_memmisaligned.sv rtl/verilog/core/memory/riscv_mmu.sv rtl/verilog/core/memory/riscv_pmachk.sv rtl/verilog/core/memory/riscv_pmpchk.sv rtl/verilog/core/memory/riscv_wbuf.sv rtl/verilog/core/mmu/riscv_nommu.sv rtl/verilog/pkg/biu_constants_pkg.sv rtl/verilog/pkg/riscv_cache_pkg.sv rtl/verilog/pkg/riscv_du_pkg.sv rtl/verilog/pkg/riscv_opcodes_pkg.sv rtl/verilog/pkg/riscv_pma_pkg.sv rtl/verilog/pkg/riscv_rv12_pkg.sv rtl/verilog/pkg/riscv_state1.10_pkg.sv rtl/verilog/pkg/riscv_state1.7_pkg.sv rtl/verilog/pkg/riscv_state1.9_pkg.sv rtl/verilog/pkg/riscv_state_20240411_pkg.sv " } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("RV12") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p RV12 -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p RV12 -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("RV12") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p RV12 -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p RV12 -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("RV12") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("RV12") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p RV12 -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p RV12 -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("RV12") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p RV12 -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p RV12 -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("RV12") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/Risco-5.Jenkinsfile b/jenkins_pipeline/Risco-5.Jenkinsfile index f8370d9..b76b4c2 100644 --- a/jenkins_pipeline/Risco-5.Jenkinsfile +++ b/jenkins_pipeline/Risco-5.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf Risco-5' - sh 'git clone --recursive https://github.com/JN513/Risco-5.git Risco-5' + sh 'git clone --recursive --depth=1 https://github.com/JN513/Risco-5.git Risco-5' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("Risco-5") { - sh "iverilog -o simulation.out -g2005 -s soc_tb src/core/alu.v src/core/alu_control.v src/core/control_unit.v src/core/core.v src/core/csr_unit.v src/core/immediate_generator.v src/core/mdu.v src/core/mux.v src/core/pc.v src/core/registers.v tests/soc_test.v src/peripheral/bus.v src/peripheral/fifo.v src/peripheral/gpios.v src/peripheral/gpio.v src/peripheral/leds.v src/peripheral/memory.v src/peripheral/pwm.v src/peripheral/soc.v src/peripheral/uart_rx.v src/peripheral/uart_tx.v src/peripheral/uart.v" + sh "/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s soc_tb src/core/alu.v src/core/alu_control.v src/core/control_unit.v src/core/core.v src/core/csr_unit.v src/core/immediate_generator.v src/core/mdu.v src/core/mux.v src/core/pc.v src/core/registers.v tests/soc_test.v src/peripheral/bus.v src/peripheral/fifo.v src/peripheral/gpios.v src/peripheral/gpio.v src/peripheral/leds.v src/peripheral/memory.v src/peripheral/pwm.v src/peripheral/soc.v src/peripheral/uart_rx.v src/peripheral/uart_tx.v src/peripheral/uart.v" } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("Risco-5") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Risco-5 -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Risco-5 -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("Risco-5") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Risco-5 -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Risco-5 -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("Risco-5") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("Risco-5") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Risco-5 -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Risco-5 -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("Risco-5") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Risco-5 -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Risco-5 -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("Risco-5") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/T02x.Jenkinsfile b/jenkins_pipeline/T02x.Jenkinsfile index 915ece1..719ef9d 100644 --- a/jenkins_pipeline/T02x.Jenkinsfile +++ b/jenkins_pipeline/T02x.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf T02x' - sh 'git clone --recursive https://github.com/klessydra/T02x T02x' + sh 'git clone --recursive --depth=1 https://github.com/klessydra/T02x T02x' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("T02x") { - sh "ghdl -a --std=08 klessydra-t0-2th/PKG_RiscV_Klessydra_thread_parameters.vhd klessydra-t0-2th/PKG_RiscV_Klessydra.vhd klessydra-t0-2th/RTL-CSR_Unit.vhd klessydra-t0-2th/RTL-Debug_Unit.vhd klessydra-t0-2th/RTL-Processing_Pipeline.vhd klessydra-t0-2th/RTL-Program_Counter_unit.vhd klessydra-t0-2th/STR-Klessydra_top.vhd " + sh "ghdl -a --std=08 klessydra-t0-2th/PKG_RiscV_Klessydra_thread_parameters.vhd klessydra-t0-2th/PKG_RiscV_Klessydra.vhd klessydra-t0-2th/RTL-CSR_Unit.vhd klessydra-t0-2th/RTL-Debug_Unit.vhd klessydra-t0-2th/RTL-Processing_Pipeline.vhd klessydra-t0-2th/RTL-Program_Counter_unit.vhd klessydra-t0-2th/STR-Klessydra_top.vhd " } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("T02x") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p T02x -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p T02x -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("T02x") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p T02x -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p T02x -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("T02x") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("T02x") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p T02x -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p T02x -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("T02x") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p T02x -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p T02x -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("T02x") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/T03x.Jenkinsfile b/jenkins_pipeline/T03x.Jenkinsfile index 6e56e7b..1d07575 100644 --- a/jenkins_pipeline/T03x.Jenkinsfile +++ b/jenkins_pipeline/T03x.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf T03x' - sh 'git clone --recursive https://github.com/klessydra/T03x T03x' + sh 'git clone --recursive --depth=1 https://github.com/klessydra/T03x T03x' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("T03x") { - sh "ghdl -a --std=08 klessydra-t0-3th/PKG_RiscV_Klessydra_thread_parameters.vhd klessydra-t0-3th/PKG_RiscV_Klessydra.vhd klessydra-t0-3th/PKG_RiscV_Klessydra.vhd klessydra-t0-3th/RTL-CSR_Unit.vhd klessydra-t0-3th/RTL-Debug_Unit.vhd klessydra-t0-3th/RTL-Processing_Pipeline.vhd klessydra-t0-3th/RTL-Program_Counter_unit.vhd klessydra-t0-3th/STR-Klessydra_top.vhd " + sh "ghdl -a --std=08 klessydra-t0-3th/PKG_RiscV_Klessydra_thread_parameters.vhd klessydra-t0-3th/PKG_RiscV_Klessydra.vhd klessydra-t0-3th/PKG_RiscV_Klessydra.vhd klessydra-t0-3th/RTL-CSR_Unit.vhd klessydra-t0-3th/RTL-Debug_Unit.vhd klessydra-t0-3th/RTL-Processing_Pipeline.vhd klessydra-t0-3th/RTL-Program_Counter_unit.vhd klessydra-t0-3th/STR-Klessydra_top.vhd " } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("T03x") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p T03x -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p T03x -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("T03x") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p T03x -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p T03x -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("T03x") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("T03x") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p T03x -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p T03x -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("T03x") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p T03x -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p T03x -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("T03x") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/T13x.Jenkinsfile b/jenkins_pipeline/T13x.Jenkinsfile index fc56150..e46d00a 100644 --- a/jenkins_pipeline/T13x.Jenkinsfile +++ b/jenkins_pipeline/T13x.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf T13x' - sh 'git clone --recursive https://github.com/klessydra/T13x T13x' + sh 'git clone --recursive --depth=1 https://github.com/klessydra/T13x T13x' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("T13x") { - sh "ghdl -a --std=08 klessydra-t1-3th/PKG_RiscV_Klessydra.vhd klessydra-t1-3th/RTL-Accumulator.vhd klessydra-t1-3th/RTL-Debug_Unit.vhd klessydra-t1-3th/RTL-CSR_Unit.vhd klessydra-t1-3th/RTL-DSP_Unit.vhd klessydra-t1-3th/RTL-ID_STAGE.vhd klessydra-t1-3th/RTL-IE_STAGE.vhd klessydra-t1-3th/RTL-IF_STAGE.vhd klessydra-t1-3th/RTL-Load_Store_Unit.vhd klessydra-t1-3th/RTL-Processing_Pipeline.vhd klessydra-t1-3th/RTL-Program_Counter_unit.vhd klessydra-t1-3th/RTL-Registerfile.vhd klessydra-t1-3th/STR-Klessydra_top.vhd klessydra-t1-3th/RTL-Scratchpad_Memory.vhd klessydra-t1-3th/RTL-Scratchpad_Memory_Interface.vhd " + sh "ghdl -a --std=08 klessydra-t1-3th/PKG_RiscV_Klessydra.vhd klessydra-t1-3th/RTL-Accumulator.vhd klessydra-t1-3th/RTL-Debug_Unit.vhd klessydra-t1-3th/RTL-CSR_Unit.vhd klessydra-t1-3th/RTL-DSP_Unit.vhd klessydra-t1-3th/RTL-ID_STAGE.vhd klessydra-t1-3th/RTL-IE_STAGE.vhd klessydra-t1-3th/RTL-IF_STAGE.vhd klessydra-t1-3th/RTL-Load_Store_Unit.vhd klessydra-t1-3th/RTL-Processing_Pipeline.vhd klessydra-t1-3th/RTL-Program_Counter_unit.vhd klessydra-t1-3th/RTL-Registerfile.vhd klessydra-t1-3th/STR-Klessydra_top.vhd klessydra-t1-3th/RTL-Scratchpad_Memory.vhd klessydra-t1-3th/RTL-Scratchpad_Memory_Interface.vhd " } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("T13x") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p T13x -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p T13x -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("T13x") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p T13x -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p T13x -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("T13x") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("T13x") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p T13x -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p T13x -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("T13x") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p T13x -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p T13x -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("T13x") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/Taiga.Jenkinsfile b/jenkins_pipeline/Taiga.Jenkinsfile index 2171dfc..a67924a 100644 --- a/jenkins_pipeline/Taiga.Jenkinsfile +++ b/jenkins_pipeline/Taiga.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf Taiga' - sh 'git clone --recursive https://gitlab.com/sfu-rcl/Taiga Taiga' + sh 'git clone --recursive --depth=1 https://gitlab.com/sfu-rcl/Taiga Taiga' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("Taiga") { - sh "iverilog -o simulation.out -g2005 -s taiga core/addr_hash.sv core/alu_unit.sv core/amo_alu.sv core/avalon_master.sv core/axi_master.sv core/axi_to_arb.sv core/barrel_shifter.sv core/binary_occupancy.sv core/branch_comparator.sv core/branch_predictor.sv core/branch_predictor_ram.sv core/branch_unit.sv core/byte_en_BRAM.sv core/clz.sv core/csr_types.sv core/csr_unit.sv core/cycler.sv core/dbram.sv core/dcache.sv core/ddata_bank.sv core/decode_and_issue.sv core/div_core.sv core/div_unit.sv core/dtag_banks.sv core/external_interfaces.sv core/fetch.sv core/gc_unit.sv core/ibram.sv core/icache.sv core/illegal_instruction_checker.sv core/instruction_metadata_and_id_management.sv core/interfaces.sv core/itag_banks.sv core/l1_arbiter.sv core/lfsr.sv core/load_queue.sv core/load_store_queue.sv core/load_store_unit.sv core/mmu.sv core/mul_unit.sv core/one_hot_occupancy.sv core/one_hot_to_integer.sv core/placer_randomizer.sv core/priority_encoder.sv core/ras.sv core/reg_inuse.sv core/register_bank.sv core/register_file.sv core/register_free_list.sv core/renamer.sv core/riscv_types.sv core/set_clr_reg_with_rst.sv core/shift_counter.sv core/store_queue.sv core/tag_bank.sv core/taiga.sv core/taiga_config.sv core/taiga_fifo.sv core/taiga_types.sv core/tlb_lut_ram.sv core/toggle_memory.sv core/toggle_memory_set.sv core/wishbone_master.sv core/writeback.sv " + sh "/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s taiga core/addr_hash.sv core/alu_unit.sv core/amo_alu.sv core/avalon_master.sv core/axi_master.sv core/axi_to_arb.sv core/barrel_shifter.sv core/binary_occupancy.sv core/branch_comparator.sv core/branch_predictor.sv core/branch_predictor_ram.sv core/branch_unit.sv core/byte_en_BRAM.sv core/clz.sv core/csr_types.sv core/csr_unit.sv core/cycler.sv core/dbram.sv core/dcache.sv core/ddata_bank.sv core/decode_and_issue.sv core/div_core.sv core/div_unit.sv core/dtag_banks.sv core/external_interfaces.sv core/fetch.sv core/gc_unit.sv core/ibram.sv core/icache.sv core/illegal_instruction_checker.sv core/instruction_metadata_and_id_management.sv core/interfaces.sv core/itag_banks.sv core/l1_arbiter.sv core/lfsr.sv core/load_queue.sv core/load_store_queue.sv core/load_store_unit.sv core/mmu.sv core/mul_unit.sv core/one_hot_occupancy.sv core/one_hot_to_integer.sv core/placer_randomizer.sv core/priority_encoder.sv core/ras.sv core/reg_inuse.sv core/register_bank.sv core/register_file.sv core/register_free_list.sv core/renamer.sv core/riscv_types.sv core/set_clr_reg_with_rst.sv core/shift_counter.sv core/store_queue.sv core/tag_bank.sv core/taiga.sv core/taiga_config.sv core/taiga_fifo.sv core/taiga_types.sv core/tlb_lut_ram.sv core/toggle_memory.sv core/toggle_memory_set.sv core/wishbone_master.sv core/writeback.sv " } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("Taiga") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Taiga -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Taiga -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("Taiga") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Taiga -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Taiga -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("Taiga") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("Taiga") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Taiga -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Taiga -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("Taiga") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Taiga -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Taiga -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("Taiga") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/Tethorax.Jenkinsfile b/jenkins_pipeline/Tethorax.Jenkinsfile index a28385f..b00d331 100644 --- a/jenkins_pipeline/Tethorax.Jenkinsfile +++ b/jenkins_pipeline/Tethorax.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf Tethorax' - sh 'git clone --recursive https://github.com/NikosDelijohn/Tethorax Tethorax' + sh 'git clone --recursive --depth=1 https://github.com/NikosDelijohn/Tethorax Tethorax' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("Tethorax") { - sh "ghdl -a --std=08 PIPELINE.vhd RV32I.vhd TOOLBOX.vhd PIPELINE Components/EXE.vhd PIPELINE Components/INSTRUCTION_DECODE.vhd PIPELINE Components/INSTRUCTION_FETCH.vhd PIPELINE Components/MEMORY.vhd PIPELINE Components/PC_REGISTER.vhd PIPELINE Components/PIPE_EXE_TO_MEM_REGISTER.vhd PIPELINE Components/PIPE_ID_TO_EXE_REGISTER.vhd PIPELINE Components/PIPE_IF_TO_ID_REGISTER.vhd PIPELINE Components/PIPE_MEM_TO_WB_REGISTER.vhd PIPELINE Components/WRITE_BACK.vhd TOOLBOX Components/ADDER_2B.vhd TOOLBOX Components/ADDER_2B_MSB.vhd TOOLBOX Components/BARREL_CELL.vhd TOOLBOX Components/BARREL_SHIFTER.vhd TOOLBOX Components/CONTROL_WORD_REGROUP.vhd TOOLBOX Components/DEC5X32.vhd TOOLBOX Components/DECODE_TO_EXECUTE.vhd TOOLBOX Components/EXE_ADDER_SUBBER.vhd TOOLBOX Components/EXE_ADDER_SUBBER_CELL.vhd TOOLBOX Components/EXE_ADDER_SUBBER_CELL_MSB.vhd TOOLBOX Components/EXE_BRANCH_RESOLVE.vhd TOOLBOX Components/EXE_LOGIC_MODULE.vhd TOOLBOX Components/EXE_SLT_MODULE.vhd TOOLBOX Components/ID_ADDER.vhd TOOLBOX Components/ID_DECODER.vhd TOOLBOX Components/ID_IMM_GENERATOR.vhd TOOLBOX Components/IF_INSTRMEM.vhd TOOLBOX Components/MEM_DATAMEM.vhd TOOLBOX Components/MEM_LOADS_MASKING.vhd TOOLBOX Components/MEM_STORE_BYTEEN.vhd TOOLBOX Components/MEM_TO_WB.vhd TOOLBOX Components/MUX2X1.vhd TOOLBOX Components/MUX2X1_BIT.vhd TOOLBOX Components/MUX32X1.vhd TOOLBOX Components/MUX4X1.vhd TOOLBOX Components/MUX8X1.vhd TOOLBOX Components/PC_PLUS_4.vhd TOOLBOX Components/REGISTER_FILE.vhd TOOLBOX Components/REG_32B_CASUAL.vhd TOOLBOX Components/REG_32B_ZERO.vhd TOOLBOX Components/STALL_FWD_PREDICT.vhd " + sh "ghdl -a --std=08 PIPELINE.vhd RV32I.vhd TOOLBOX.vhd PIPELINE Components/EXE.vhd PIPELINE Components/INSTRUCTION_DECODE.vhd PIPELINE Components/INSTRUCTION_FETCH.vhd PIPELINE Components/MEMORY.vhd PIPELINE Components/PC_REGISTER.vhd PIPELINE Components/PIPE_EXE_TO_MEM_REGISTER.vhd PIPELINE Components/PIPE_ID_TO_EXE_REGISTER.vhd PIPELINE Components/PIPE_IF_TO_ID_REGISTER.vhd PIPELINE Components/PIPE_MEM_TO_WB_REGISTER.vhd PIPELINE Components/WRITE_BACK.vhd TOOLBOX Components/ADDER_2B.vhd TOOLBOX Components/ADDER_2B_MSB.vhd TOOLBOX Components/BARREL_CELL.vhd TOOLBOX Components/BARREL_SHIFTER.vhd TOOLBOX Components/CONTROL_WORD_REGROUP.vhd TOOLBOX Components/DEC5X32.vhd TOOLBOX Components/DECODE_TO_EXECUTE.vhd TOOLBOX Components/EXE_ADDER_SUBBER.vhd TOOLBOX Components/EXE_ADDER_SUBBER_CELL.vhd TOOLBOX Components/EXE_ADDER_SUBBER_CELL_MSB.vhd TOOLBOX Components/EXE_BRANCH_RESOLVE.vhd TOOLBOX Components/EXE_LOGIC_MODULE.vhd TOOLBOX Components/EXE_SLT_MODULE.vhd TOOLBOX Components/ID_ADDER.vhd TOOLBOX Components/ID_DECODER.vhd TOOLBOX Components/ID_IMM_GENERATOR.vhd TOOLBOX Components/IF_INSTRMEM.vhd TOOLBOX Components/MEM_DATAMEM.vhd TOOLBOX Components/MEM_LOADS_MASKING.vhd TOOLBOX Components/MEM_STORE_BYTEEN.vhd TOOLBOX Components/MEM_TO_WB.vhd TOOLBOX Components/MUX2X1.vhd TOOLBOX Components/MUX2X1_BIT.vhd TOOLBOX Components/MUX32X1.vhd TOOLBOX Components/MUX4X1.vhd TOOLBOX Components/MUX8X1.vhd TOOLBOX Components/PC_PLUS_4.vhd TOOLBOX Components/REGISTER_FILE.vhd TOOLBOX Components/REG_32B_CASUAL.vhd TOOLBOX Components/REG_32B_ZERO.vhd TOOLBOX Components/STALL_FWD_PREDICT.vhd " } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("Tethorax") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Tethorax -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Tethorax -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("Tethorax") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Tethorax -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Tethorax -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("Tethorax") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("Tethorax") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Tethorax -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Tethorax -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("Tethorax") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Tethorax -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p Tethorax -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("Tethorax") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/VexRiscv.Jenkinsfile b/jenkins_pipeline/VexRiscv.Jenkinsfile index 903e820..f903f8d 100644 --- a/jenkins_pipeline/VexRiscv.Jenkinsfile +++ b/jenkins_pipeline/VexRiscv.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf VexRiscv' - sh 'git clone --recursive https://github.com/SpinalHDL/VexRiscv VexRiscv' + sh 'git clone --recursive --depth=1 https://github.com/SpinalHDL/VexRiscv VexRiscv' } } @@ -22,7 +22,7 @@ pipeline { stage('Simulation') { steps { dir("VexRiscv") { - sh "iverilog -o simulation.out -g2005 -s VexRiscv VexRiscv.v " + sh "/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s VexRiscv VexRiscv.v " } } } @@ -35,27 +35,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("VexRiscv") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p VexRiscv -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p VexRiscv -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("VexRiscv") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p VexRiscv -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p VexRiscv -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("VexRiscv") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -67,27 +70,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("VexRiscv") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p VexRiscv -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p VexRiscv -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("VexRiscv") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p VexRiscv -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p VexRiscv -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("VexRiscv") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/biriscv.Jenkinsfile b/jenkins_pipeline/biriscv.Jenkinsfile index b407f54..db805df 100644 --- a/jenkins_pipeline/biriscv.Jenkinsfile +++ b/jenkins_pipeline/biriscv.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf biriscv' - sh 'git clone --recursive https://github.com/ultraembedded/biriscv biriscv' + sh 'git clone --recursive --depth=1 https://github.com/ultraembedded/biriscv biriscv' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("biriscv") { - sh "iverilog -o simulation.out -g2005 -s riscv_core -I src/core src/core/biriscv_alu.v src/core/biriscv_csr.v src/core/biriscv_csr_regfile.v src/core/biriscv_decode.v src/core/biriscv_decoder.v src/core/biriscv_defs.v src/core/biriscv_divider.v src/core/biriscv_exec.v src/core/biriscv_fetch.v src/core/biriscv_frontend.v src/core/biriscv_issue.v src/core/biriscv_lsu.v src/core/biriscv_mmu.v src/core/biriscv_multiplier.v src/core/biriscv_npc.v src/core/biriscv_pipe_ctrl.v src/core/biriscv_regfile.v src/core/biriscv_trace_sim.v src/core/biriscv_xilinx_2r1w.v src/core/riscv_core.v " + sh "/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s riscv_core -I src/core src/core/biriscv_alu.v src/core/biriscv_csr.v src/core/biriscv_csr_regfile.v src/core/biriscv_decode.v src/core/biriscv_decoder.v src/core/biriscv_defs.v src/core/biriscv_divider.v src/core/biriscv_exec.v src/core/biriscv_fetch.v src/core/biriscv_frontend.v src/core/biriscv_issue.v src/core/biriscv_lsu.v src/core/biriscv_mmu.v src/core/biriscv_multiplier.v src/core/biriscv_npc.v src/core/biriscv_pipe_ctrl.v src/core/biriscv_regfile.v src/core/biriscv_trace_sim.v src/core/biriscv_xilinx_2r1w.v src/core/riscv_core.v " } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("biriscv") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p biriscv -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p biriscv -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("biriscv") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p biriscv -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p biriscv -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("biriscv") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("biriscv") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p biriscv -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p biriscv -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("biriscv") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p biriscv -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p biriscv -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("biriscv") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/cv32e40p.Jenkinsfile b/jenkins_pipeline/cv32e40p.Jenkinsfile index 62d1136..3919d1c 100644 --- a/jenkins_pipeline/cv32e40p.Jenkinsfile +++ b/jenkins_pipeline/cv32e40p.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf cv32e40p' - sh 'git clone --recursive https://github.com/openhwgroup/cv32e40p cv32e40p' + sh 'git clone --recursive --depth=1 https://github.com/openhwgroup/cv32e40p cv32e40p' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("cv32e40p") { - sh "iverilog -o simulation.out -g2012 -s -I rtl/include/ rtl/cv32e40p_aligner.sv rtl/cv32e40p_alu.sv rtl/cv32e40p_alu_div.sv rtl/cv32e40p_apu_disp.sv rtl/cv32e40p_compressed_decoder.sv rtl/cv32e40p_controller.sv rtl/cv32e40p_core.sv rtl/cv32e40p_cs_registers.sv rtl/cv32e40p_decoder.sv rtl/cv32e40p_ex_stage.sv rtl/cv32e40p_ff_one.sv rtl/cv32e40p_fifo.sv rtl/cv32e40p_fp_wrapper.sv rtl/cv32e40p_hwloop_regs.sv rtl/cv32e40p_id_stage.sv rtl/cv32e40p_if_stage.sv rtl/cv32e40p_int_controller.sv rtl/cv32e40p_load_store_unit.sv rtl/cv32e40p_mult.sv rtl/cv32e40p_obi_interface.sv rtl/cv32e40p_popcnt.sv rtl/cv32e40p_prefetch_buffer.sv rtl/cv32e40p_prefetch_controller.sv rtl/cv32e40p_register_file_ff.sv rtl/cv32e40p_register_file_latch.sv rtl/cv32e40p_sleep_unit.sv rtl/cv32e40p_top.sv " + sh "/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2012 -s -I rtl/include/ rtl/cv32e40p_aligner.sv rtl/cv32e40p_alu.sv rtl/cv32e40p_alu_div.sv rtl/cv32e40p_apu_disp.sv rtl/cv32e40p_compressed_decoder.sv rtl/cv32e40p_controller.sv rtl/cv32e40p_core.sv rtl/cv32e40p_cs_registers.sv rtl/cv32e40p_decoder.sv rtl/cv32e40p_ex_stage.sv rtl/cv32e40p_ff_one.sv rtl/cv32e40p_fifo.sv rtl/cv32e40p_fp_wrapper.sv rtl/cv32e40p_hwloop_regs.sv rtl/cv32e40p_id_stage.sv rtl/cv32e40p_if_stage.sv rtl/cv32e40p_int_controller.sv rtl/cv32e40p_load_store_unit.sv rtl/cv32e40p_mult.sv rtl/cv32e40p_obi_interface.sv rtl/cv32e40p_popcnt.sv rtl/cv32e40p_prefetch_buffer.sv rtl/cv32e40p_prefetch_controller.sv rtl/cv32e40p_register_file_ff.sv rtl/cv32e40p_register_file_latch.sv rtl/cv32e40p_sleep_unit.sv rtl/cv32e40p_top.sv " } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("cv32e40p") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p cv32e40p -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p cv32e40p -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("cv32e40p") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p cv32e40p -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p cv32e40p -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("cv32e40p") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("cv32e40p") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p cv32e40p -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p cv32e40p -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("cv32e40p") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p cv32e40p -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p cv32e40p -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("cv32e40p") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/darkriscv.Jenkinsfile b/jenkins_pipeline/darkriscv.Jenkinsfile index 32a5157..5ac5616 100644 --- a/jenkins_pipeline/darkriscv.Jenkinsfile +++ b/jenkins_pipeline/darkriscv.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf darkriscv' - sh 'git clone --recursive https://github.com/darklife/darkriscv darkriscv' + sh 'git clone --recursive --depth=1 https://github.com/darklife/darkriscv darkriscv' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("darkriscv") { - sh "iverilog -o simulation.out -g2005 -s darkriscv -I rtl rtl/darkriscv.v " + sh "/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s darkriscv -I rtl rtl/darkriscv.v " } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("darkriscv") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p darkriscv -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p darkriscv -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("darkriscv") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p darkriscv -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p darkriscv -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("darkriscv") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("darkriscv") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p darkriscv -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p darkriscv -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("darkriscv") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p darkriscv -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p darkriscv -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("darkriscv") { - ' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/dv-cpu-rv.Jenkinsfile b/jenkins_pipeline/dv-cpu-rv.Jenkinsfile index 94b0350..712fb48 100644 --- a/jenkins_pipeline/dv-cpu-rv.Jenkinsfile +++ b/jenkins_pipeline/dv-cpu-rv.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf dv-cpu-rv' - sh 'git clone --recursive https://github.com/devindang/dv-cpu-rv dv-cpu-rv' + sh 'git clone --recursive --depth=1 https://github.com/devindang/dv-cpu-rv dv-cpu-rv' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("dv-cpu-rv") { - sh "iverilog -o simulation.out -g2005 -s rv_core core/rtl/rv_alu.v core/rtl/rv_alu_ctrl.v core/rtl/rv_branch_predict.v core/rtl/rv_core.v core/rtl/rv_ctrl.v core/rtl/rv_div.v core/rtl/rv_forward.v core/rtl/rv_hzd_detect.v core/rtl/rv_imm_gen.v core/rtl/rv_mem_map.v core/rtl/rv_mul.v core/rtl/rv_rf.v " + sh "/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s rv_core core/rtl/rv_alu.v core/rtl/rv_alu_ctrl.v core/rtl/rv_branch_predict.v core/rtl/rv_core.v core/rtl/rv_ctrl.v core/rtl/rv_div.v core/rtl/rv_forward.v core/rtl/rv_hzd_detect.v core/rtl/rv_imm_gen.v core/rtl/rv_mem_map.v core/rtl/rv_mul.v core/rtl/rv_rf.v " } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("dv-cpu-rv") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p dv-cpu-rv -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p dv-cpu-rv -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("dv-cpu-rv") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p dv-cpu-rv -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p dv-cpu-rv -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("dv-cpu-rv") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("dv-cpu-rv") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p dv-cpu-rv -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p dv-cpu-rv -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("dv-cpu-rv") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p dv-cpu-rv -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p dv-cpu-rv -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("dv-cpu-rv") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/e203_hbirdv2.Jenkinsfile b/jenkins_pipeline/e203_hbirdv2.Jenkinsfile index 548a682..92cc14f 100644 --- a/jenkins_pipeline/e203_hbirdv2.Jenkinsfile +++ b/jenkins_pipeline/e203_hbirdv2.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf e203_hbirdv2' - sh 'git clone --recursive https://github.com/riscv-mcu/e203_hbirdv2 e203_hbirdv2' + sh 'git clone --recursive --depth=1 https://github.com/riscv-mcu/e203_hbirdv2 e203_hbirdv2' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("e203_hbirdv2") { - sh "iverilog -o simulation.out -g2009 -DDISABLE_SV_ASSERTION=1 -gsupported-assertions -s e203_cpu_top -I rtl/e203/core/ rtl/e203/core/config.v rtl/e203/core/e203_biu.v rtl/e203/core/e203_clk_ctrl.v rtl/e203/core/e203_clkgate.v rtl/e203/core/e203_core.v rtl/e203/core/e203_cpu.v rtl/e203/core/e203_cpu_top.v rtl/e203/core/e203_defines.v rtl/e203/core/e203_dtcm_ctrl.v rtl/e203/core/e203_dtcm_ram.v rtl/e203/core/e203_extend_csr.v rtl/e203/core/e203_exu.v rtl/e203/core/e203_exu_alu.v rtl/e203/core/e203_exu_alu_bjp.v rtl/e203/core/e203_exu_alu_csrctrl.v rtl/e203/core/e203_exu_alu_dpath.v rtl/e203/core/e203_exu_alu_lsuagu.v rtl/e203/core/e203_exu_alu_muldiv.v rtl/e203/core/e203_exu_alu_rglr.v rtl/e203/core/e203_exu_branchslv.v rtl/e203/core/e203_exu_commit.v rtl/e203/core/e203_exu_csr.v rtl/e203/core/e203_exu_decode.v rtl/e203/core/e203_exu_disp.v rtl/e203/core/e203_exu_excp.v rtl/e203/core/e203_exu_longpwbck.v rtl/e203/core/e203_exu_nice.v rtl/e203/core/e203_exu_oitf.v rtl/e203/core/e203_exu_regfile.v rtl/e203/core/e203_exu_wbck.v rtl/e203/core/e203_ifu.v rtl/e203/core/e203_ifu_ifetch.v rtl/e203/core/e203_ifu_ift2icb.v rtl/e203/core/e203_ifu_litebpu.v rtl/e203/core/e203_ifu_minidec.v rtl/e203/core/e203_irq_sync.v rtl/e203/core/e203_itcm_ctrl.v rtl/e203/core/e203_itcm_ram.v rtl/e203/core/e203_lsu.v rtl/e203/core/e203_lsu_ctrl.v rtl/e203/core/e203_reset_ctrl.v rtl/e203/core/e203_srams.v rtl/e203/general/sirv_1cyc_sram_ctrl.v rtl/e203/general/sirv_gnrl_bufs.v rtl/e203/general/sirv_gnrl_dffs.v rtl/e203/general/sirv_gnrl_icbs.v rtl/e203/general/sirv_gnrl_ram.v rtl/e203/general/sirv_gnrl_xchecker.v rtl/e203/general/sirv_sim_ram.v rtl/e203/general/sirv_sram_icb_ctrl.v rtl/e203/subsys/e203_subsys_clint.v rtl/e203/subsys/e203_subsys_gfcm.v rtl/e203/subsys/e203_subsys_hclkgen.v rtl/e203/subsys/e203_subsys_hclkgen_rstsync.v rtl/e203/subsys/e203_subsys_main.v rtl/e203/subsys/e203_subsys_mems.v rtl/e203/subsys/e203_subsys_nice_core.v rtl/e203/subsys/e203_subsys_perips.v rtl/e203/subsys/e203_subsys_plic.v rtl/e203/subsys/e203_subsys_pll.v rtl/e203/subsys/e203_subsys_pllclkdiv.v rtl/e203/subsys/e203_subsys_top.v " + sh "/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2009 -DDISABLE_SV_ASSERTION=1 -gsupported-assertions -s e203_cpu_top -I rtl/e203/core/ rtl/e203/core/config.v rtl/e203/core/e203_biu.v rtl/e203/core/e203_clk_ctrl.v rtl/e203/core/e203_clkgate.v rtl/e203/core/e203_core.v rtl/e203/core/e203_cpu.v rtl/e203/core/e203_cpu_top.v rtl/e203/core/e203_defines.v rtl/e203/core/e203_dtcm_ctrl.v rtl/e203/core/e203_dtcm_ram.v rtl/e203/core/e203_extend_csr.v rtl/e203/core/e203_exu.v rtl/e203/core/e203_exu_alu.v rtl/e203/core/e203_exu_alu_bjp.v rtl/e203/core/e203_exu_alu_csrctrl.v rtl/e203/core/e203_exu_alu_dpath.v rtl/e203/core/e203_exu_alu_lsuagu.v rtl/e203/core/e203_exu_alu_muldiv.v rtl/e203/core/e203_exu_alu_rglr.v rtl/e203/core/e203_exu_branchslv.v rtl/e203/core/e203_exu_commit.v rtl/e203/core/e203_exu_csr.v rtl/e203/core/e203_exu_decode.v rtl/e203/core/e203_exu_disp.v rtl/e203/core/e203_exu_excp.v rtl/e203/core/e203_exu_longpwbck.v rtl/e203/core/e203_exu_nice.v rtl/e203/core/e203_exu_oitf.v rtl/e203/core/e203_exu_regfile.v rtl/e203/core/e203_exu_wbck.v rtl/e203/core/e203_ifu.v rtl/e203/core/e203_ifu_ifetch.v rtl/e203/core/e203_ifu_ift2icb.v rtl/e203/core/e203_ifu_litebpu.v rtl/e203/core/e203_ifu_minidec.v rtl/e203/core/e203_irq_sync.v rtl/e203/core/e203_itcm_ctrl.v rtl/e203/core/e203_itcm_ram.v rtl/e203/core/e203_lsu.v rtl/e203/core/e203_lsu_ctrl.v rtl/e203/core/e203_reset_ctrl.v rtl/e203/core/e203_srams.v rtl/e203/general/sirv_1cyc_sram_ctrl.v rtl/e203/general/sirv_gnrl_bufs.v rtl/e203/general/sirv_gnrl_dffs.v rtl/e203/general/sirv_gnrl_icbs.v rtl/e203/general/sirv_gnrl_ram.v rtl/e203/general/sirv_gnrl_xchecker.v rtl/e203/general/sirv_sim_ram.v rtl/e203/general/sirv_sram_icb_ctrl.v rtl/e203/subsys/e203_subsys_clint.v rtl/e203/subsys/e203_subsys_gfcm.v rtl/e203/subsys/e203_subsys_hclkgen.v rtl/e203/subsys/e203_subsys_hclkgen_rstsync.v rtl/e203/subsys/e203_subsys_main.v rtl/e203/subsys/e203_subsys_mems.v rtl/e203/subsys/e203_subsys_nice_core.v rtl/e203/subsys/e203_subsys_perips.v rtl/e203/subsys/e203_subsys_plic.v rtl/e203/subsys/e203_subsys_pll.v rtl/e203/subsys/e203_subsys_pllclkdiv.v rtl/e203/subsys/e203_subsys_top.v " } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("e203_hbirdv2") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p e203_hbirdv2 -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p e203_hbirdv2 -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("e203_hbirdv2") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p e203_hbirdv2 -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p e203_hbirdv2 -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("e203_hbirdv2") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("e203_hbirdv2") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p e203_hbirdv2 -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p e203_hbirdv2 -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("e203_hbirdv2") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p e203_hbirdv2 -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p e203_hbirdv2 -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("e203_hbirdv2") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/ibex.Jenkinsfile b/jenkins_pipeline/ibex.Jenkinsfile index 5f13d8f..f5ad5c2 100644 --- a/jenkins_pipeline/ibex.Jenkinsfile +++ b/jenkins_pipeline/ibex.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf ibex' - sh 'git clone --recursive https://github.com/lowRISC/ibex ibex' + sh 'git clone --recursive --depth=1 https://github.com/lowRISC/ibex ibex' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("ibex") { - sh "iverilog -o simulation.out -g2012 -s ibex_core rtl/ibex_alu.sv rtl/ibex_branch_predict.sv rtl/ibex_compressed_decoder.sv rtl/ibex_controller.sv rtl/ibex_core.sv rtl/ibex_counter.sv rtl/ibex_cs_registers.sv rtl/ibex_csr.sv rtl/ibex_decoder.sv rtl/ibex_dummy_instr.sv rtl/ibex_ex_block.sv rtl/ibex_fetch_fifo.sv rtl/ibex_icache.sv rtl/ibex_id_stage.sv rtl/ibex_if_stage.sv rtl/ibex_load_store_unit.sv rtl/ibex_lockstep.sv rtl/ibex_multdiv_fast.sv rtl/ibex_multdiv_slow.sv rtl/ibex_pkg.sv rtl/ibex_pmp.sv rtl/ibex_prefetch_buffer.sv rtl/ibex_register_file_ff.sv rtl/ibex_register_file_fpga.sv rtl/ibex_register_file_latch.sv rtl/ibex_top.sv rtl/ibex_top_tracing.sv rtl/ibex_tracer.sv rtl/ibex_tracer_pkg.sv rtl/ibex_wb_stage.sv " + sh "/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2012 -s ibex_core rtl/ibex_alu.sv rtl/ibex_branch_predict.sv rtl/ibex_compressed_decoder.sv rtl/ibex_controller.sv rtl/ibex_core.sv rtl/ibex_counter.sv rtl/ibex_cs_registers.sv rtl/ibex_csr.sv rtl/ibex_decoder.sv rtl/ibex_dummy_instr.sv rtl/ibex_ex_block.sv rtl/ibex_fetch_fifo.sv rtl/ibex_icache.sv rtl/ibex_id_stage.sv rtl/ibex_if_stage.sv rtl/ibex_load_store_unit.sv rtl/ibex_lockstep.sv rtl/ibex_multdiv_fast.sv rtl/ibex_multdiv_slow.sv rtl/ibex_pkg.sv rtl/ibex_pmp.sv rtl/ibex_prefetch_buffer.sv rtl/ibex_register_file_ff.sv rtl/ibex_register_file_fpga.sv rtl/ibex_register_file_latch.sv rtl/ibex_top.sv rtl/ibex_top_tracing.sv rtl/ibex_tracer.sv rtl/ibex_tracer_pkg.sv rtl/ibex_wb_stage.sv " } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("ibex") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p ibex -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p ibex -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("ibex") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p ibex -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p ibex -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("ibex") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("ibex") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p ibex -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p ibex -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("ibex") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p ibex -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p ibex -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("ibex") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/kronos.Jenkinsfile b/jenkins_pipeline/kronos.Jenkinsfile index c1d336a..43951a9 100644 --- a/jenkins_pipeline/kronos.Jenkinsfile +++ b/jenkins_pipeline/kronos.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf kronos' - sh 'git clone --recursive https://github.com/SonalPinto/kronos kronos' + sh 'git clone --recursive --depth=1 https://github.com/SonalPinto/kronos kronos' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("kronos") { - sh "iverilog -o simulation.out -g2012 -s kronos_core rtl/core/kronos_EX.sv rtl/core/kronos_ID.sv rtl/core/kronos_IF.sv rtl/core/kronos_RF.sv rtl/core/kronos_agu.sv rtl/core/kronos_alu.sv rtl/core/kronos_branch.sv rtl/core/kronos_core.sv rtl/core/kronos_counter64.sv rtl/core/kronos_csr.sv rtl/core/kronos_hcu.sv rtl/core/kronos_lsu.sv rtl/core/kronos_types.sv " + sh "/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2012 -s kronos_core rtl/core/kronos_EX.sv rtl/core/kronos_ID.sv rtl/core/kronos_IF.sv rtl/core/kronos_RF.sv rtl/core/kronos_agu.sv rtl/core/kronos_alu.sv rtl/core/kronos_branch.sv rtl/core/kronos_core.sv rtl/core/kronos_counter64.sv rtl/core/kronos_csr.sv rtl/core/kronos_hcu.sv rtl/core/kronos_lsu.sv rtl/core/kronos_types.sv " } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("kronos") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p kronos -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p kronos -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("kronos") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p kronos -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p kronos -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("kronos") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("kronos") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p kronos -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p kronos -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("kronos") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p kronos -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p kronos -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("kronos") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/maestro.Jenkinsfile b/jenkins_pipeline/maestro.Jenkinsfile index 76e60cc..f60a089 100644 --- a/jenkins_pipeline/maestro.Jenkinsfile +++ b/jenkins_pipeline/maestro.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf maestro' - sh 'git clone --recursive https://github.com/Artoriuz/maestro maestro' + sh 'git clone --recursive --depth=1 https://github.com/Artoriuz/maestro maestro' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("maestro") { - sh "ghdl -a --std=08 Project/Components/ALU.vhd Project/Components/EX_MEM_DIV.vhd Project/Components/ID_EX_DIV.vhd Project/Components/IF_ID_DIV.vhd Project/Components/MEM_WB_DIV.vhd Project/Components/adder.vhd Project/Components/controller.vhd Project/Components/datapath.vhd Project/Components/flushing_unit.vhd Project/Components/forwarding_unit.vhd Project/Components/jump_target_unit.vhd Project/Components/mux_2_1.vhd Project/Components/mux_32_1.vhd Project/Components/mux_3_1.vhd Project/Components/mux_5_1.vhd Project/Components/progmem_interface.vhd Project/Components/program_counter.vhd Project/Components/reg1b.vhd Project/Components/reg2b.vhd Project/Components/reg32b.vhd Project/Components/reg32b_falling_edge.vhd Project/Components/reg3b.vhd Project/Components/reg4b.vhd Project/Components/reg5b.vhd Project/Components/register_file.vhd " + sh "ghdl -a --std=08 Project/Components/ALU.vhd Project/Components/EX_MEM_DIV.vhd Project/Components/ID_EX_DIV.vhd Project/Components/IF_ID_DIV.vhd Project/Components/MEM_WB_DIV.vhd Project/Components/adder.vhd Project/Components/controller.vhd Project/Components/datapath.vhd Project/Components/flushing_unit.vhd Project/Components/forwarding_unit.vhd Project/Components/jump_target_unit.vhd Project/Components/mux_2_1.vhd Project/Components/mux_32_1.vhd Project/Components/mux_3_1.vhd Project/Components/mux_5_1.vhd Project/Components/progmem_interface.vhd Project/Components/program_counter.vhd Project/Components/reg1b.vhd Project/Components/reg2b.vhd Project/Components/reg32b.vhd Project/Components/reg32b_falling_edge.vhd Project/Components/reg3b.vhd Project/Components/reg4b.vhd Project/Components/reg5b.vhd Project/Components/register_file.vhd " } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("maestro") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p maestro -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p maestro -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("maestro") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p maestro -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p maestro -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("maestro") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("maestro") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p maestro -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p maestro -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("maestro") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p maestro -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p maestro -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("maestro") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/mriscv.Jenkinsfile b/jenkins_pipeline/mriscv.Jenkinsfile index fc54365..ebe9914 100644 --- a/jenkins_pipeline/mriscv.Jenkinsfile +++ b/jenkins_pipeline/mriscv.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf mriscv' - sh 'git clone --recursive https://github.com/onchipuis/mriscv mriscv' + sh 'git clone --recursive --depth=1 https://github.com/onchipuis/mriscv mriscv' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("mriscv") { - sh "iverilog -o simulation.out -g2005 -s mriscvcore mriscvcore/mriscvcore.v mriscvcore/ALU/ALU.v mriscvcore/DECO_INSTR/DECO_INSTR.v mriscvcore/FSM/FSM.v mriscvcore/IRQ/IRQ.v mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v mriscvcore/MULT/MULT.v mriscvcore/REG_FILE/REG_FILE.v mriscvcore/UTILITIES/UTILITY.v " + sh "/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s mriscvcore mriscvcore/mriscvcore.v mriscvcore/ALU/ALU.v mriscvcore/DECO_INSTR/DECO_INSTR.v mriscvcore/FSM/FSM.v mriscvcore/IRQ/IRQ.v mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v mriscvcore/MULT/MULT.v mriscvcore/REG_FILE/REG_FILE.v mriscvcore/UTILITIES/UTILITY.v " } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("mriscv") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p mriscv -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p mriscv -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("mriscv") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p mriscv -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p mriscv -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("mriscv") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("mriscv") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p mriscv -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p mriscv -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("mriscv") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p mriscv -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p mriscv -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("mriscv") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/neorv32.Jenkinsfile b/jenkins_pipeline/neorv32.Jenkinsfile index e0a5e46..ecdc1d1 100644 --- a/jenkins_pipeline/neorv32.Jenkinsfile +++ b/jenkins_pipeline/neorv32.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf neorv32' - sh 'git clone --recursive https://github.com/stnolting/neorv32.git neorv32' + sh 'git clone --recursive --depth=1 https://github.com/stnolting/neorv32.git neorv32' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("neorv32") { - sh "ghdl -a --std=08 rtl/core/neorv32_application_image.vhd rtl/core/neorv32_boot_rom.vhd rtl/core/neorv32_bootloader_image.vhd rtl/core/neorv32_bus.vhd rtl/core/neorv32_cache.vhd rtl/core/neorv32_cfs.vhd rtl/core/neorv32_clockgate.vhd rtl/core/neorv32_cpu.vhd rtl/core/neorv32_cpu_alu.vhd rtl/core/neorv32_cpu_control.vhd rtl/core/neorv32_cpu_cp_bitmanip.vhd rtl/core/neorv32_cpu_cp_cfu.vhd rtl/core/neorv32_cpu_cp_cond.vhd rtl/core/neorv32_cpu_cp_crypto.vhd rtl/core/neorv32_cpu_cp_fpu.vhd rtl/core/neorv32_cpu_cp_muldiv.vhd rtl/core/neorv32_cpu_cp_shifter.vhd rtl/core/neorv32_cpu_decompressor.vhd rtl/core/neorv32_cpu_lsu.vhd rtl/core/neorv32_cpu_pmp.vhd rtl/core/neorv32_cpu_regfile.vhd rtl/core/neorv32_crc.vhd rtl/core/neorv32_debug_dm.vhd rtl/core/neorv32_debug_dtm.vhd rtl/core/neorv32_dma.vhd rtl/core/neorv32_dmem.vhd rtl/core/neorv32_fifo.vhd rtl/core/neorv32_gpio.vhd rtl/core/neorv32_gptmr.vhd rtl/core/neorv32_imem.vhd rtl/core/neorv32_mtime.vhd rtl/core/neorv32_neoled.vhd rtl/core/neorv32_onewire.vhd rtl/core/neorv32_package.vhd rtl/core/neorv32_pwm.vhd rtl/core/neorv32_sdi.vhd rtl/core/neorv32_slink.vhd rtl/core/neorv32_spi.vhd rtl/core/neorv32_sys.vhd rtl/core/neorv32_sysinfo.vhd rtl/core/neorv32_top.vhd rtl/core/neorv32_trng.vhd rtl/core/neorv32_twi.vhd rtl/core/neorv32_uart.vhd rtl/core/neorv32_wdt.vhd rtl/core/neorv32_xbus.vhd rtl/core/neorv32_xip.vhd rtl/core/neorv32_xirq.vhd " + sh "ghdl -a --std=08 rtl/core/neorv32_application_image.vhd rtl/core/neorv32_boot_rom.vhd rtl/core/neorv32_bootloader_image.vhd rtl/core/neorv32_bus.vhd rtl/core/neorv32_cache.vhd rtl/core/neorv32_cfs.vhd rtl/core/neorv32_clockgate.vhd rtl/core/neorv32_cpu.vhd rtl/core/neorv32_cpu_alu.vhd rtl/core/neorv32_cpu_control.vhd rtl/core/neorv32_cpu_cp_bitmanip.vhd rtl/core/neorv32_cpu_cp_cfu.vhd rtl/core/neorv32_cpu_cp_cond.vhd rtl/core/neorv32_cpu_cp_crypto.vhd rtl/core/neorv32_cpu_cp_fpu.vhd rtl/core/neorv32_cpu_cp_muldiv.vhd rtl/core/neorv32_cpu_cp_shifter.vhd rtl/core/neorv32_cpu_decompressor.vhd rtl/core/neorv32_cpu_lsu.vhd rtl/core/neorv32_cpu_pmp.vhd rtl/core/neorv32_cpu_regfile.vhd rtl/core/neorv32_crc.vhd rtl/core/neorv32_debug_dm.vhd rtl/core/neorv32_debug_dtm.vhd rtl/core/neorv32_dma.vhd rtl/core/neorv32_dmem.vhd rtl/core/neorv32_fifo.vhd rtl/core/neorv32_gpio.vhd rtl/core/neorv32_gptmr.vhd rtl/core/neorv32_imem.vhd rtl/core/neorv32_mtime.vhd rtl/core/neorv32_neoled.vhd rtl/core/neorv32_onewire.vhd rtl/core/neorv32_package.vhd rtl/core/neorv32_pwm.vhd rtl/core/neorv32_sdi.vhd rtl/core/neorv32_slink.vhd rtl/core/neorv32_spi.vhd rtl/core/neorv32_sys.vhd rtl/core/neorv32_sysinfo.vhd rtl/core/neorv32_top.vhd rtl/core/neorv32_trng.vhd rtl/core/neorv32_twi.vhd rtl/core/neorv32_uart.vhd rtl/core/neorv32_wdt.vhd rtl/core/neorv32_xbus.vhd rtl/core/neorv32_xip.vhd rtl/core/neorv32_xirq.vhd " } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("neorv32") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p neorv32 -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p neorv32 -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("neorv32") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p neorv32 -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p neorv32 -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("neorv32") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("neorv32") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p neorv32 -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p neorv32 -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("neorv32") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p neorv32 -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p neorv32 -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("neorv32") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/nerv.Jenkinsfile b/jenkins_pipeline/nerv.Jenkinsfile index be8ad76..e84446b 100644 --- a/jenkins_pipeline/nerv.Jenkinsfile +++ b/jenkins_pipeline/nerv.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf nerv' - sh 'git clone --recursive https://github.com/YosysHQ/nerv nerv' + sh 'git clone --recursive --depth=1 https://github.com/YosysHQ/nerv nerv' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("nerv") { - sh "iverilog -o simulation.out -g2012 -s nerv nerv.sv " + sh "/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2012 -s nerv nerv.sv " } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("nerv") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p nerv -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p nerv -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("nerv") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p nerv -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p nerv -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("nerv") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("nerv") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p nerv -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p nerv -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("nerv") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p nerv -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p nerv -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("nerv") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/picorv32.Jenkinsfile b/jenkins_pipeline/picorv32.Jenkinsfile index 1002f8b..79df483 100644 --- a/jenkins_pipeline/picorv32.Jenkinsfile +++ b/jenkins_pipeline/picorv32.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf picorv32' - sh 'git clone --recursive https://github.com/YosysHQ/picorv32 picorv32' + sh 'git clone --recursive --depth=1 https://github.com/YosysHQ/picorv32 picorv32' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("picorv32") { - sh "iverilog -o simulation.out -g2005 -s picorv32.v " + sh "/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s picorv32.v " } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("picorv32") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p picorv32 -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p picorv32 -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("picorv32") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p picorv32 -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p picorv32 -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("picorv32") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("picorv32") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p picorv32 -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p picorv32 -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("picorv32") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p picorv32 -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p picorv32 -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("picorv32") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/riscado-v.Jenkinsfile b/jenkins_pipeline/riscado-v.Jenkinsfile index 040d0ab..73d62a7 100644 --- a/jenkins_pipeline/riscado-v.Jenkinsfile +++ b/jenkins_pipeline/riscado-v.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf riscado-v' - sh 'git clone --recursive https://github.com/zxmarcos/riscado-v riscado-v' + sh 'git clone --recursive --depth=1 https://github.com/zxmarcos/riscado-v riscado-v' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("riscado-v") { - sh "iverilog -o simulation.out -g2005 -s RISCV alu.v control_unit.v program_counter.v register_file.v riscv.v load_store.v " + sh "/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s RISCV alu.v control_unit.v program_counter.v register_file.v riscv.v load_store.v " } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("riscado-v") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p riscado-v -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p riscado-v -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("riscado-v") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p riscado-v -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p riscado-v -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("riscado-v") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("riscado-v") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p riscado-v -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p riscado-v -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("riscado-v") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p riscado-v -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p riscado-v -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("riscado-v") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/riscv-steel.Jenkinsfile b/jenkins_pipeline/riscv-steel.Jenkinsfile index 89840a8..016c285 100644 --- a/jenkins_pipeline/riscv-steel.Jenkinsfile +++ b/jenkins_pipeline/riscv-steel.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf riscv-steel' - sh 'git clone --recursive https://github.com/riscv-steel/riscv-steel riscv-steel' + sh 'git clone --recursive --depth=1 https://github.com/riscv-steel/riscv-steel riscv-steel' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("riscv-steel") { - sh "iverilog -o simulation.out -g2005 -s rvsteel_core hardware/core/rvsteel_core.v " + sh "/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s rvsteel_core hardware/rvsteel_core.v " } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("riscv-steel") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p riscv-steel -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p riscv-steel -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("riscv-steel") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p riscv-steel -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p riscv-steel -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("riscv-steel") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("riscv-steel") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p riscv-steel -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p riscv-steel -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("riscv-steel") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p riscv-steel -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p riscv-steel -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("riscv-steel") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/riskow.Jenkinsfile b/jenkins_pipeline/riskow.Jenkinsfile index f356473..1eecda4 100644 --- a/jenkins_pipeline/riskow.Jenkinsfile +++ b/jenkins_pipeline/riskow.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf riskow' - sh 'git clone --recursive https://github.com/racerxdl/riskow riskow' + sh 'git clone --recursive --depth=1 https://github.com/racerxdl/riskow riskow' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("riskow") { - sh "iverilog -o simulation.out -g2005 -s CPU cpu/alu.v cpu/comp.v cpu/cpu.v cpu/instruction_decoder.v cpu/program_counter.v cpu/register_bank.v " + sh "/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s CPU cpu/alu.v cpu/comp.v cpu/cpu.v cpu/instruction_decoder.v cpu/program_counter.v cpu/register_bank.v " } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("riskow") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p riskow -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p riskow -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("riskow") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p riskow -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p riskow -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("riskow") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("riskow") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p riskow -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p riskow -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("riskow") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p riskow -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p riskow -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("riskow") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/rsd.Jenkinsfile b/jenkins_pipeline/rsd.Jenkinsfile index 9de10fd..10783ef 100644 --- a/jenkins_pipeline/rsd.Jenkinsfile +++ b/jenkins_pipeline/rsd.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf rsd' - sh 'git clone --recursive https://github.com/rsd-devel/rsd rsd' + sh 'git clone --recursive --depth=1 https://github.com/rsd-devel/rsd rsd' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("rsd") { - sh "iverilog -o simulation.out -g2012 -s Processor/Src/BasicMacros.sv Processor/Src/BasicTypes.sv Processor/Src/Controller.sv Processor/Src/ControllerIF.sv Processor/Src/Core.sv Processor/Src/Main.sv Processor/Src/MicroArchConf.sv Processor/Src/ResetController.sv Processor/Src/SynthesisMacros.sv Processor/Src/Cache/CacheFlushManager.sv Processor/Src/Cache/CacheFlushManagerIF.sv Processor/Src/Cache/CacheSystemIF.sv Processor/Src/Cache/CacheSystemTypes.sv Processor/Src/Cache/DCache.sv Processor/Src/Cache/DCacheIF.sv Processor/Src/Cache/ICache.sv Processor/Src/Cache/MemoryAccessController.sv Processor/Src/Debug/Debug.sv Processor/Src/Debug/DebugIF.sv Processor/Src/Debug/DebugTypes.sv Processor/Src/Debug/PerformanceCounter.sv Processor/Src/Debug/PerformanceCounterIF.sv Processor/Src/Decoder/DecodedBranchResolver.sv Processor/Src/Decoder/Decoder.sv Processor/Src/Decoder/MicroOp.sv Processor/Src/Decoder/OpFormat.sv Processor/Src/ExecUnit/BitCounter.sv Processor/Src/ExecUnit/DividerUnit.sv Processor/Src/ExecUnit/IntALU.sv Processor/Src/ExecUnit/MultiplierUnit.sv Processor/Src/ExecUnit/PipelinedRefDivider.sv Processor/Src/ExecUnit/Shifter.sv Processor/Src/FetchUnit/Bimodal.sv Processor/Src/FetchUnit/BranchPredictor.sv Processor/Src/FetchUnit/FetchUnitTypes.sv Processor/Src/FetchUnit/Gshare.sv Processor/Src/FloatingPointUnit/FP32DivSqrter.sv Processor/Src/FloatingPointUnit/FP32PipelinedAdder.sv Processor/Src/FloatingPointUnit/FP32PipelinedFMA.sv Processor/Src/FloatingPointUnit/FP32PipelinedMultiplier.sv Processor/Src/FloatingPointUnit/FP32PipelinedOther.sv Processor/Src/FloatingPointUnit/FPDivSqrtUnit.sv Processor/Src/FloatingPointUnit/FPDivSqrtUnitIF.sv Processor/Src/FloatingPointUnit/FPUTypes.sv Processor/Src/IO/IO_Unit.sv Processor/Src/IO/IO_UnitIF.sv Processor/Src/IO/IO_UnitTypes.sv Processor/Src/LoadStoreUnit/LoadQueue.sv Processor/Src/LoadStoreUnit/LoadStoreUnit.sv Processor/Src/LoadStoreUnit/LoadStoreUnitIF.sv Processor/Src/LoadStoreUnit/LoadStoreUnitTypes.sv Processor/Src/LoadStoreUnit/StoreCommitter.sv Processor/Src/LoadStoreUnit/StoreQueue.sv Processor/Src/Memory/Axi4LiteControlMemoryIF.sv Processor/Src/Memory/Axi4LiteControlRegister.sv Processor/Src/Memory/Axi4LiteControlRegisterIF.sv Processor/Src/Memory/Axi4LiteMemory.sv Processor/Src/Memory/Axi4Memory.sv Processor/Src/Memory/Axi4MemoryIF.sv Processor/Src/Memory/ControlQueue.sv Processor/Src/Memory/Memory.sv Processor/Src/Memory/MemoryLatencySimulator.sv Processor/Src/Memory/MemoryMapTypes.sv Processor/Src/Memory/MemoryReadReqQueue.sv Processor/Src/Memory/MemoryTypes.sv Processor/Src/Memory/MemoryWriteDataQueue.sv Processor/Src/MulDivUnit/MulDivUnit.sv Processor/Src/MulDivUnit/MulDivUnitIF.sv Processor/Src/Pipeline/CommitStage.sv Processor/Src/Pipeline/CommitStageIF.sv Processor/Src/Pipeline/DecodeStage.sv Processor/Src/Pipeline/DecodeStageIF.sv Processor/Src/Pipeline/DispatchStage.sv Processor/Src/Pipeline/DispatchStageIF.sv Processor/Src/Pipeline/PipelineTypes.sv Processor/Src/Pipeline/PreDecodeStage.sv Processor/Src/Pipeline/PreDecodeStageIF.sv Processor/Src/Pipeline/RenameStage.sv Processor/Src/Pipeline/RenameStageIF.sv Processor/Src/Pipeline/ScheduleStage.sv Processor/Src/Pipeline/ScheduleStageIF.sv Processor/Src/Pipeline/ComplexIntegerBackEnd/ComplexIntegerExecutionStage.sv Processor/Src/Pipeline/ComplexIntegerBackEnd/ComplexIntegerExecutionStageIF.sv Processor/Src/Pipeline/ComplexIntegerBackEnd/ComplexIntegerIssueStage.sv Processor/Src/Pipeline/ComplexIntegerBackEnd/ComplexIntegerIssueStageIF.sv Processor/Src/Pipeline/ComplexIntegerBackEnd/ComplexIntegerRegisterReadStage.sv Processor/Src/Pipeline/ComplexIntegerBackEnd/ComplexIntegerRegisterReadStageIF.sv Processor/Src/Pipeline/FPBackEnd/FPExecutionStage.sv Processor/Src/Pipeline/FPBackEnd/FPExecutionStageIF.sv Processor/Src/Pipeline/FPBackEnd/FPIssueStage.sv Processor/Src/Pipeline/FPBackEnd/FPIssueStageIF.sv Processor/Src/Pipeline/FPBackEnd/FPRegisterReadStage.sv Processor/Src/Pipeline/FPBackEnd/FPRegisterReadStageIF.sv Processor/Src/Pipeline/FetchStage/FetchStage.sv Processor/Src/Pipeline/FetchStage/FetchStageIF.sv Processor/Src/Pipeline/FetchStage/NextPCStage.sv Processor/Src/Pipeline/FetchStage/NextPCStageIF.sv Processor/Src/Pipeline/FetchStage/PC.sv Processor/Src/Pipeline/IntegerBackEnd/IntegerExecutionStage.sv Processor/Src/Pipeline/IntegerBackEnd/IntegerExecutionStageIF.sv Processor/Src/Pipeline/IntegerBackEnd/IntegerIssueStage.sv Processor/Src/Pipeline/IntegerBackEnd/IntegerIssueStageIF.sv Processor/Src/Pipeline/IntegerBackEnd/IntegerRegisterReadStage.sv Processor/Src/Pipeline/IntegerBackEnd/IntegerRegisterReadStageIF.sv Processor/Src/Pipeline/MemoryBackEnd/MemoryAccessStage.sv Processor/Src/Pipeline/MemoryBackEnd/MemoryAccessStageIF.sv Processor/Src/Pipeline/MemoryBackEnd/MemoryExecutionStage.sv Processor/Src/Pipeline/MemoryBackEnd/MemoryExecutionStageIF.sv Processor/Src/Pipeline/MemoryBackEnd/MemoryIssueStage.sv Processor/Src/Pipeline/MemoryBackEnd/MemoryIssueStageIF.sv Processor/Src/Pipeline/MemoryBackEnd/MemoryRegisterReadStage.sv Processor/Src/Pipeline/MemoryBackEnd/MemoryRegisterReadStageIF.sv Processor/Src/Pipeline/MemoryBackEnd/MemoryTagAccessStage.sv Processor/Src/Pipeline/MemoryBackEnd/MemoryTagAccessStageIF.sv Processor/Src/Primitives/Divider.sv Processor/Src/Primitives/FlipFlop.sv Processor/Src/Primitives/FreeList.sv Processor/Src/Primitives/LRU_Counter.sv Processor/Src/Primitives/Multiplier.sv Processor/Src/Primitives/Picker.sv Processor/Src/Primitives/Queue.sv Processor/Src/Primitives/RAM.sv Processor/Src/Primitives/RAM_Synplify.sv Processor/Src/Primitives/RAM_Vivado.sv Processor/Src/Privileged/CSR_Unit.sv Processor/Src/Privileged/CSR_UnitIF.sv Processor/Src/Privileged/CSR_UnitTypes.sv Processor/Src/Privileged/InterruptController.sv Processor/Src/Recovery/RecoveryManager.sv Processor/Src/Recovery/RecoveryManagerIF.sv Processor/Src/RegisterFile/BypassController.sv Processor/Src/RegisterFile/BypassNetwork.sv Processor/Src/RegisterFile/BypassNetworkIF.sv Processor/Src/RegisterFile/BypassTypes.sv Processor/Src/RegisterFile/RegisterFile.sv Processor/Src/RegisterFile/RegisterFileIF.sv Processor/Src/RenameLogic/ActiveList.sv Processor/Src/RenameLogic/ActiveListIF.sv Processor/Src/RenameLogic/ActiveListIndexTypes.sv Processor/Src/RenameLogic/RMT.sv Processor/Src/RenameLogic/RenameLogic.sv Processor/Src/RenameLogic/RenameLogicCommitter.sv Processor/Src/RenameLogic/RenameLogicIF.sv Processor/Src/RenameLogic/RenameLogicTypes.sv Processor/Src/RenameLogic/RetirementRMT.sv Processor/Src/Scheduler/DestinationRAM.sv Processor/Src/Scheduler/IssueQueue.sv Processor/Src/Scheduler/MemoryDependencyPredictor.sv Processor/Src/Scheduler/ProducerMatrix.sv Processor/Src/Scheduler/ReadyBitTable.sv Processor/Src/Scheduler/ReplayQueue.sv Processor/Src/Scheduler/Scheduler.sv Processor/Src/Scheduler/SchedulerIF.sv Processor/Src/Scheduler/SchedulerTypes.sv Processor/Src/Scheduler/SelectLogic.sv Processor/Src/Scheduler/SourceCAM.sv Processor/Src/Scheduler/WakeupLogic.sv Processor/Src/Scheduler/WakeupPipelineRegister.sv Processor/Src/Scheduler/WakeupSelectIF.sv " + sh "/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2012 -s Processor/Src/BasicMacros.sv Processor/Src/BasicTypes.sv Processor/Src/Controller.sv Processor/Src/ControllerIF.sv Processor/Src/Core.sv Processor/Src/Main.sv Processor/Src/MicroArchConf.sv Processor/Src/ResetController.sv Processor/Src/SynthesisMacros.sv Processor/Src/Cache/CacheFlushManager.sv Processor/Src/Cache/CacheFlushManagerIF.sv Processor/Src/Cache/CacheSystemIF.sv Processor/Src/Cache/CacheSystemTypes.sv Processor/Src/Cache/DCache.sv Processor/Src/Cache/DCacheIF.sv Processor/Src/Cache/ICache.sv Processor/Src/Cache/MemoryAccessController.sv Processor/Src/Debug/Debug.sv Processor/Src/Debug/DebugIF.sv Processor/Src/Debug/DebugTypes.sv Processor/Src/Debug/PerformanceCounter.sv Processor/Src/Debug/PerformanceCounterIF.sv Processor/Src/Decoder/DecodedBranchResolver.sv Processor/Src/Decoder/Decoder.sv Processor/Src/Decoder/MicroOp.sv Processor/Src/Decoder/OpFormat.sv Processor/Src/ExecUnit/BitCounter.sv Processor/Src/ExecUnit/DividerUnit.sv Processor/Src/ExecUnit/IntALU.sv Processor/Src/ExecUnit/MultiplierUnit.sv Processor/Src/ExecUnit/PipelinedRefDivider.sv Processor/Src/ExecUnit/Shifter.sv Processor/Src/FetchUnit/Bimodal.sv Processor/Src/FetchUnit/BranchPredictor.sv Processor/Src/FetchUnit/FetchUnitTypes.sv Processor/Src/FetchUnit/Gshare.sv Processor/Src/FloatingPointUnit/FP32DivSqrter.sv Processor/Src/FloatingPointUnit/FP32PipelinedAdder.sv Processor/Src/FloatingPointUnit/FP32PipelinedFMA.sv Processor/Src/FloatingPointUnit/FP32PipelinedMultiplier.sv Processor/Src/FloatingPointUnit/FP32PipelinedOther.sv Processor/Src/FloatingPointUnit/FPDivSqrtUnit.sv Processor/Src/FloatingPointUnit/FPDivSqrtUnitIF.sv Processor/Src/FloatingPointUnit/FPUTypes.sv Processor/Src/IO/IO_Unit.sv Processor/Src/IO/IO_UnitIF.sv Processor/Src/IO/IO_UnitTypes.sv Processor/Src/LoadStoreUnit/LoadQueue.sv Processor/Src/LoadStoreUnit/LoadStoreUnit.sv Processor/Src/LoadStoreUnit/LoadStoreUnitIF.sv Processor/Src/LoadStoreUnit/LoadStoreUnitTypes.sv Processor/Src/LoadStoreUnit/StoreCommitter.sv Processor/Src/LoadStoreUnit/StoreQueue.sv Processor/Src/Memory/Axi4LiteControlMemoryIF.sv Processor/Src/Memory/Axi4LiteControlRegister.sv Processor/Src/Memory/Axi4LiteControlRegisterIF.sv Processor/Src/Memory/Axi4LiteMemory.sv Processor/Src/Memory/Axi4Memory.sv Processor/Src/Memory/Axi4MemoryIF.sv Processor/Src/Memory/ControlQueue.sv Processor/Src/Memory/Memory.sv Processor/Src/Memory/MemoryLatencySimulator.sv Processor/Src/Memory/MemoryMapTypes.sv Processor/Src/Memory/MemoryReadReqQueue.sv Processor/Src/Memory/MemoryTypes.sv Processor/Src/Memory/MemoryWriteDataQueue.sv Processor/Src/MulDivUnit/MulDivUnit.sv Processor/Src/MulDivUnit/MulDivUnitIF.sv Processor/Src/Pipeline/CommitStage.sv Processor/Src/Pipeline/CommitStageIF.sv Processor/Src/Pipeline/DecodeStage.sv Processor/Src/Pipeline/DecodeStageIF.sv Processor/Src/Pipeline/DispatchStage.sv Processor/Src/Pipeline/DispatchStageIF.sv Processor/Src/Pipeline/PipelineTypes.sv Processor/Src/Pipeline/PreDecodeStage.sv Processor/Src/Pipeline/PreDecodeStageIF.sv Processor/Src/Pipeline/RenameStage.sv Processor/Src/Pipeline/RenameStageIF.sv Processor/Src/Pipeline/ScheduleStage.sv Processor/Src/Pipeline/ScheduleStageIF.sv Processor/Src/Pipeline/ComplexIntegerBackEnd/ComplexIntegerExecutionStage.sv Processor/Src/Pipeline/ComplexIntegerBackEnd/ComplexIntegerExecutionStageIF.sv Processor/Src/Pipeline/ComplexIntegerBackEnd/ComplexIntegerIssueStage.sv Processor/Src/Pipeline/ComplexIntegerBackEnd/ComplexIntegerIssueStageIF.sv Processor/Src/Pipeline/ComplexIntegerBackEnd/ComplexIntegerRegisterReadStage.sv Processor/Src/Pipeline/ComplexIntegerBackEnd/ComplexIntegerRegisterReadStageIF.sv Processor/Src/Pipeline/FPBackEnd/FPExecutionStage.sv Processor/Src/Pipeline/FPBackEnd/FPExecutionStageIF.sv Processor/Src/Pipeline/FPBackEnd/FPIssueStage.sv Processor/Src/Pipeline/FPBackEnd/FPIssueStageIF.sv Processor/Src/Pipeline/FPBackEnd/FPRegisterReadStage.sv Processor/Src/Pipeline/FPBackEnd/FPRegisterReadStageIF.sv Processor/Src/Pipeline/FetchStage/FetchStage.sv Processor/Src/Pipeline/FetchStage/FetchStageIF.sv Processor/Src/Pipeline/FetchStage/NextPCStage.sv Processor/Src/Pipeline/FetchStage/NextPCStageIF.sv Processor/Src/Pipeline/FetchStage/PC.sv Processor/Src/Pipeline/IntegerBackEnd/IntegerExecutionStage.sv Processor/Src/Pipeline/IntegerBackEnd/IntegerExecutionStageIF.sv Processor/Src/Pipeline/IntegerBackEnd/IntegerIssueStage.sv Processor/Src/Pipeline/IntegerBackEnd/IntegerIssueStageIF.sv Processor/Src/Pipeline/IntegerBackEnd/IntegerRegisterReadStage.sv Processor/Src/Pipeline/IntegerBackEnd/IntegerRegisterReadStageIF.sv Processor/Src/Pipeline/MemoryBackEnd/MemoryAccessStage.sv Processor/Src/Pipeline/MemoryBackEnd/MemoryAccessStageIF.sv Processor/Src/Pipeline/MemoryBackEnd/MemoryExecutionStage.sv Processor/Src/Pipeline/MemoryBackEnd/MemoryExecutionStageIF.sv Processor/Src/Pipeline/MemoryBackEnd/MemoryIssueStage.sv Processor/Src/Pipeline/MemoryBackEnd/MemoryIssueStageIF.sv Processor/Src/Pipeline/MemoryBackEnd/MemoryRegisterReadStage.sv Processor/Src/Pipeline/MemoryBackEnd/MemoryRegisterReadStageIF.sv Processor/Src/Pipeline/MemoryBackEnd/MemoryTagAccessStage.sv Processor/Src/Pipeline/MemoryBackEnd/MemoryTagAccessStageIF.sv Processor/Src/Primitives/Divider.sv Processor/Src/Primitives/FlipFlop.sv Processor/Src/Primitives/FreeList.sv Processor/Src/Primitives/LRU_Counter.sv Processor/Src/Primitives/Multiplier.sv Processor/Src/Primitives/Picker.sv Processor/Src/Primitives/Queue.sv Processor/Src/Primitives/RAM.sv Processor/Src/Primitives/RAM_Synplify.sv Processor/Src/Primitives/RAM_Vivado.sv Processor/Src/Privileged/CSR_Unit.sv Processor/Src/Privileged/CSR_UnitIF.sv Processor/Src/Privileged/CSR_UnitTypes.sv Processor/Src/Privileged/InterruptController.sv Processor/Src/Recovery/RecoveryManager.sv Processor/Src/Recovery/RecoveryManagerIF.sv Processor/Src/RegisterFile/BypassController.sv Processor/Src/RegisterFile/BypassNetwork.sv Processor/Src/RegisterFile/BypassNetworkIF.sv Processor/Src/RegisterFile/BypassTypes.sv Processor/Src/RegisterFile/RegisterFile.sv Processor/Src/RegisterFile/RegisterFileIF.sv Processor/Src/RenameLogic/ActiveList.sv Processor/Src/RenameLogic/ActiveListIF.sv Processor/Src/RenameLogic/ActiveListIndexTypes.sv Processor/Src/RenameLogic/RMT.sv Processor/Src/RenameLogic/RenameLogic.sv Processor/Src/RenameLogic/RenameLogicCommitter.sv Processor/Src/RenameLogic/RenameLogicIF.sv Processor/Src/RenameLogic/RenameLogicTypes.sv Processor/Src/RenameLogic/RetirementRMT.sv Processor/Src/Scheduler/DestinationRAM.sv Processor/Src/Scheduler/IssueQueue.sv Processor/Src/Scheduler/MemoryDependencyPredictor.sv Processor/Src/Scheduler/ProducerMatrix.sv Processor/Src/Scheduler/ReadyBitTable.sv Processor/Src/Scheduler/ReplayQueue.sv Processor/Src/Scheduler/Scheduler.sv Processor/Src/Scheduler/SchedulerIF.sv Processor/Src/Scheduler/SchedulerTypes.sv Processor/Src/Scheduler/SelectLogic.sv Processor/Src/Scheduler/SourceCAM.sv Processor/Src/Scheduler/WakeupLogic.sv Processor/Src/Scheduler/WakeupPipelineRegister.sv Processor/Src/Scheduler/WakeupSelectIF.sv " } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("rsd") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p rsd -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p rsd -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("rsd") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p rsd -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p rsd -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("rsd") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("rsd") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p rsd -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p rsd -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("rsd") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p rsd -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p rsd -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("rsd") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/rv3n.Jenkinsfile b/jenkins_pipeline/rv3n.Jenkinsfile index 2855349..3eff37a 100644 --- a/jenkins_pipeline/rv3n.Jenkinsfile +++ b/jenkins_pipeline/rv3n.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf rv3n' - sh 'git clone --recursive https://github.com/risclite/rv3n rv3n' + sh 'git clone --recursive --depth=1 https://github.com/risclite/rv3n rv3n' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("rv3n") { - sh "iverilog -o simulation.out -g2005 -s rv3n_top -I rtl rtl/define.v rtl/define_para.v rtl/include_func.v rtl/rv3n_chain_manager.v rtl/rv3n_csr.v rtl/rv3n_func_jcond.v rtl/rv3n_func_lsu.v rtl/rv3n_func_muldiv.v rtl/rv3n_func_op.v rtl/rv3n_gsr.v rtl/rv3n_predictor.v rtl/rv3n_stage_ch.v rtl/rv3n_stage_dc.v rtl/rv3n_stage_id.v rtl/rv3n_stage_if.v rtl/rv3n_top.v " + sh "/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s rv3n_top -I rtl rtl/define.v rtl/define_para.v rtl/include_func.v rtl/rv3n_chain_manager.v rtl/rv3n_csr.v rtl/rv3n_func_jcond.v rtl/rv3n_func_lsu.v rtl/rv3n_func_muldiv.v rtl/rv3n_func_op.v rtl/rv3n_gsr.v rtl/rv3n_predictor.v rtl/rv3n_stage_ch.v rtl/rv3n_stage_dc.v rtl/rv3n_stage_id.v rtl/rv3n_stage_if.v rtl/rv3n_top.v " } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("rv3n") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p rv3n -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p rv3n -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("rv3n") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p rv3n -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p rv3n -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("rv3n") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("rv3n") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p rv3n -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p rv3n -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("rv3n") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p rv3n -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p rv3n -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("rv3n") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/scr1.Jenkinsfile b/jenkins_pipeline/scr1.Jenkinsfile index 6048378..ec16f72 100644 --- a/jenkins_pipeline/scr1.Jenkinsfile +++ b/jenkins_pipeline/scr1.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf scr1' - sh 'git clone --recursive https://github.com/syntacore/scr1 scr1' + sh 'git clone --recursive --depth=1 https://github.com/syntacore/scr1 scr1' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("scr1") { - sh "iverilog -o simulation.out -g2012 -s scr1_core_top -I src/includes src/core/scr1_clk_ctrl.sv src/core/scr1_core_top.sv src/core/scr1_dm.sv src/core/scr1_dmi.sv src/core/scr1_scu.sv src/core/scr1_tapc.sv src/core/scr1_tapc_shift_reg.sv src/core/scr1_tapc_synchronizer.sv src/core/pipeline/scr1_ipic.sv src/core/pipeline/scr1_pipe_csr.sv src/core/pipeline/scr1_pipe_exu.sv src/core/pipeline/scr1_pipe_hdu.sv src/core/pipeline/scr1_pipe_ialu.sv src/core/pipeline/scr1_pipe_idu.sv src/core/pipeline/scr1_pipe_ifu.sv src/core/pipeline/scr1_pipe_lsu.sv src/core/pipeline/scr1_pipe_mprf.sv src/core/pipeline/scr1_pipe_tdu.sv src/core/pipeline/scr1_pipe_top.sv src/core/pipeline/scr1_tracelog.sv src/core/primitives/scr1_cg.sv src/core/primitives/scr1_reset_cells.sv " + sh "/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2012 -s scr1_core_top -I src/includes src/core/scr1_clk_ctrl.sv src/core/scr1_core_top.sv src/core/scr1_dm.sv src/core/scr1_dmi.sv src/core/scr1_scu.sv src/core/scr1_tapc.sv src/core/scr1_tapc_shift_reg.sv src/core/scr1_tapc_synchronizer.sv src/core/pipeline/scr1_ipic.sv src/core/pipeline/scr1_pipe_csr.sv src/core/pipeline/scr1_pipe_exu.sv src/core/pipeline/scr1_pipe_hdu.sv src/core/pipeline/scr1_pipe_ialu.sv src/core/pipeline/scr1_pipe_idu.sv src/core/pipeline/scr1_pipe_ifu.sv src/core/pipeline/scr1_pipe_lsu.sv src/core/pipeline/scr1_pipe_mprf.sv src/core/pipeline/scr1_pipe_tdu.sv src/core/pipeline/scr1_pipe_top.sv src/core/pipeline/scr1_tracelog.sv src/core/primitives/scr1_cg.sv src/core/primitives/scr1_reset_cells.sv " } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("scr1") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p scr1 -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p scr1 -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("scr1") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p scr1 -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p scr1 -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("scr1") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("scr1") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p scr1 -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p scr1 -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("scr1") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p scr1 -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p scr1 -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("scr1") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/serv.Jenkinsfile b/jenkins_pipeline/serv.Jenkinsfile index ebacb6e..6037e0a 100644 --- a/jenkins_pipeline/serv.Jenkinsfile +++ b/jenkins_pipeline/serv.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf serv' - sh 'git clone --recursive https://github.com/olofk/serv serv' + sh 'git clone --recursive --depth=1 https://github.com/olofk/serv serv' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("serv") { - sh "iverilog -o simulation.out -g2005 -s serv_top rtl/serv_aligner.v rtl/serv_alu.v rtl/serv_bufreg.v rtl/serv_bufreg2.v rtl/serv_compdec.v rtl/serv_csr.v rtl/serv_ctrl.v rtl/serv_decode.v rtl/serv_immdec.v rtl/serv_mem_if.v rtl/serv_rf_if.v rtl/serv_rf_ram.v rtl/serv_rf_ram_if.v rtl/serv_rf_top.v rtl/serv_state.v rtl/serv_synth_wrapper.v rtl/serv_top.v " + sh "/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s serv_top rtl/serv_aligner.v rtl/serv_alu.v rtl/serv_bufreg.v rtl/serv_bufreg2.v rtl/serv_compdec.v rtl/serv_csr.v rtl/serv_ctrl.v rtl/serv_decode.v rtl/serv_immdec.v rtl/serv_mem_if.v rtl/serv_rf_if.v rtl/serv_rf_ram.v rtl/serv_rf_ram_if.v rtl/serv_rf_top.v rtl/serv_state.v rtl/serv_synth_wrapper.v rtl/serv_top.v " } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("serv") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p serv -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p serv -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("serv") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p serv -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p serv -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("serv") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("serv") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p serv -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p serv -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("serv") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p serv -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p serv -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("serv") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/jenkins_pipeline/tinyriscv.Jenkinsfile b/jenkins_pipeline/tinyriscv.Jenkinsfile index 3f38313..2817cff 100644 --- a/jenkins_pipeline/tinyriscv.Jenkinsfile +++ b/jenkins_pipeline/tinyriscv.Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stage('Git Clone') { steps { sh 'rm -rf tinyriscv' - sh 'git clone --recursive https://github.com/liangkangnan/tinyriscv tinyriscv' + sh 'git clone --recursive --depth=1 https://github.com/liangkangnan/tinyriscv tinyriscv' } } @@ -14,7 +14,7 @@ pipeline { stage('Simulation') { steps { dir("tinyriscv") { - sh "iverilog -o simulation.out -g2005 -s tinyriscv -I rtl/core/ rtl/core/clint.v rtl/core/csr_reg.v rtl/core/ctrl.v rtl/core/div.v rtl/core/ex.v rtl/core/id.v rtl/core/id_ex.v rtl/core/if_id.v rtl/core/pc_reg.v rtl/core/regs.v rtl/core/rib.v rtl/core/tinyriscv.v rtl/utils/gen_dff.v " + sh "/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s tinyriscv -I rtl/core/ rtl/core/clint.v rtl/core/csr_reg.v rtl/core/ctrl.v rtl/core/div.v rtl/core/ex.v rtl/core/id.v rtl/core/id_ex.v rtl/core/if_id.v rtl/core/pc_reg.v rtl/core/regs.v rtl/core/rib.v rtl/core/tinyriscv.v rtl/utils/gen_dff.v " } } } @@ -27,27 +27,30 @@ pipeline { lock(resource: 'colorlight_i9') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("tinyriscv") { - echo 'Iniciando síntese para FPGA colorlight_i9.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p tinyriscv -b colorlight_i9' + echo 'Starting synthesis for FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p tinyriscv -b colorlight_i9' } } } stage('Flash colorlight_i9') { steps { dir("tinyriscv") { - echo 'FPGA colorlight_i9 bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p tinyriscv -b colorlight_i9 -l' + echo 'Flashing FPGA colorlight_i9.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p tinyriscv -b colorlight_i9 -l' } } } - stage('Teste colorlight_i9') { + stage('Test colorlight_i9') { steps { - echo 'Testando FPGA colorlight_i9.' + echo 'Testing FPGA colorlight_i9.' dir("tinyriscv") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \ + python /eda/processor-ci-communication/run_tests.py' } } } @@ -59,27 +62,30 @@ pipeline { lock(resource: 'digilent_nexys4_ddr') } stages { - stage('Síntese e PnR') { + stage('Synthesis and PnR') { steps { dir("tinyriscv") { - echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p tinyriscv -b digilent_nexys4_ddr' + echo 'Starting synthesis for FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p tinyriscv -b digilent_nexys4_ddr' } } } stage('Flash digilent_nexys4_ddr') { steps { dir("tinyriscv") { - echo 'FPGA digilent_nexys4_ddr bloqueada para flash.' - sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p tinyriscv -b digilent_nexys4_ddr -l' + echo 'Flashing FPGA digilent_nexys4_ddr.' + sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \ + -p tinyriscv -b digilent_nexys4_ddr -l' } } } - stage('Teste digilent_nexys4_ddr') { + stage('Test digilent_nexys4_ddr') { steps { - echo 'Testando FPGA digilent_nexys4_ddr.' + echo 'Testing FPGA digilent_nexys4_ddr.' dir("tinyriscv") { - sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' + sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \ + python /eda/processor-ci-communication/run_tests.py' } } } diff --git a/logs/Grande-Risco-5_1732851664.1604455.json b/logs/Grande-Risco-5_1732851664.1604455.json new file mode 100644 index 0000000..49570b5 --- /dev/null +++ b/logs/Grande-Risco-5_1732851664.1604455.json @@ -0,0 +1,361 @@ +{ + "name": "Grande-Risco-5", + "folder": "Grande-Risco-5", + "sim_files": [ + "tests/alu_test.v", + "tests/clk_divider.v", + "tests/core_test.v", + "tests/fifo_test.v", + "tests/gpio_test.v", + "tests/immediate_generator_test.v", + "tests/mux_test.v", + "tests/pc_test.v", + "tests/registers_test.v", + "tests/reset_test.v", + "tests/soc_test.v" + ], + "files": [ + "src/core/alu.v", + "src/core/alu_control.v", + "src/core/core.v", + "src/core/forwarding_unit.v", + "src/core/immediate_generator.v", + "src/core/mux.v", + "src/core/registers.v" + ], + "include_dirs": [], + "repository": "https://github.com/JN513/Grande-Risco-5", + "top_module": "Grande_Risco5", + "extra_flags": [], + "language_version": "2005", + "modules": [ + { + "module": "ClkDivider", + "file": "debug/clk_divider.v" + }, + { + "module": "Debug", + "file": "debug/debug.v" + }, + { + "module": "ResetBootSystem", + "file": "debug/reset.v" + }, + { + "module": "top", + "file": "fpga/colorlight_i9/main.v" + }, + { + "module": "top", + "file": "fpga/digilent_arty/main.v" + }, + { + "module": "top", + "file": "fpga/nexys4_ddr/main.v" + }, + { + "module": "top", + "file": "fpga/tangnano20k/main.v" + }, + { + "module": "top", + "file": "fpga/tangnano20k_yosys/main.v" + }, + { + "module": "Alu", + "file": "src/core/alu.v" + }, + { + "module": "ALU_Control", + "file": "src/core/alu_control.v" + }, + { + "module": "Grande_Risco5", + "file": "src/core/core.v" + }, + { + "module": "Forwarding_Unit", + "file": "src/core/forwarding_unit.v" + }, + { + "module": "Immediate_Generator", + "file": "src/core/immediate_generator.v" + }, + { + "module": "MUX", + "file": "src/core/mux.v" + }, + { + "module": "Registers", + "file": "src/core/registers.v" + }, + { + "module": "BUS", + "file": "src/peripheral/bus.v" + }, + { + "module": "GPIO", + "file": "src/peripheral/gpio.v" + }, + { + "module": "GPIOS", + "file": "src/peripheral/gpios.v" + }, + { + "module": "LEDs", + "file": "src/peripheral/leds.v" + }, + { + "module": "Memory", + "file": "src/peripheral/memory.v" + }, + { + "module": "Risco_5_SOC", + "file": "src/peripheral/soc.v" + }, + { + "module": "UART", + "file": "src/peripheral/uart.v" + }, + { + "module": "uart_tool_rx", + "file": "src/peripheral/uart_rx.v" + }, + { + "module": "uart_tool_tx", + "file": "src/peripheral/uart_tx.v" + }, + { + "module": "alu_tb", + "file": "tests/alu_test.v" + }, + { + "module": "clk_divider_tb", + "file": "tests/clk_divider.v" + }, + { + "module": "core_tb", + "file": "tests/core_test.v" + }, + { + "module": "fifo_tb", + "file": "tests/fifo_test.v" + }, + { + "module": "gpio_tb", + "file": "tests/gpio_test.v" + }, + { + "module": "immediate_generator_tb", + "file": "tests/immediate_generator_test.v" + }, + { + "module": "mux_tb", + "file": "tests/mux_test.v" + }, + { + "module": "pc_tb", + "file": "tests/pc_test.v" + }, + { + "module": "registers_tb", + "file": "tests/registers_test.v" + }, + { + "module": "reset_tb", + "file": "tests/reset_test.v" + }, + { + "module": "soc_tb", + "file": "tests/soc_test.v" + } + ], + "module_graph": { + "ClkDivider": [ + "clk_divider_tb" + ], + "Debug": [ + "Debug" + ], + "ResetBootSystem": [ + "top", + "top", + "top", + "top", + "top", + "reset_tb" + ], + "top": [], + "Alu": [ + "Grande_Risco5" + ], + "ALU_Control": [ + "Grande_Risco5" + ], + "Grande_Risco5": [ + "top", + "top" + ], + "Forwarding_Unit": [ + "Grande_Risco5" + ], + "Immediate_Generator": [ + "Grande_Risco5" + ], + "MUX": [ + "Grande_Risco5", + "Grande_Risco5", + "mux_tb" + ], + "Registers": [ + "registers_tb" + ], + "BUS": [], + "GPIO": [], + "GPIOS": [ + "gpio_tb" + ], + "LEDs": [ + "top", + "top" + ], + "Memory": [ + "top", + "top", + "top", + "top", + "core_tb", + "core_tb" + ], + "Risco_5_SOC": [ + "top", + "top", + "top", + "soc_tb" + ], + "UART": [ + "UART" + ], + "uart_tool_rx": [ + "UART" + ], + "uart_tool_tx": [ + "UART" + ], + "alu_tb": [], + "clk_divider_tb": [], + "core_tb": [], + "fifo_tb": [], + "gpio_tb": [], + "immediate_generator_tb": [], + "mux_tb": [], + "pc_tb": [], + "registers_tb": [], + "reset_tb": [], + "soc_tb": [] + }, + "module_graph_inverse": { + "ClkDivider": [], + "Debug": [ + "Debug" + ], + "ResetBootSystem": [], + "top": [ + "ResetBootSystem", + "Grande_Risco5", + "LEDs", + "Memory", + "Memory", + "ResetBootSystem", + "Risco_5_SOC", + "ResetBootSystem", + "Grande_Risco5", + "LEDs", + "Memory", + "Memory", + "ResetBootSystem", + "Risco_5_SOC", + "ResetBootSystem", + "Risco_5_SOC" + ], + "Alu": [], + "ALU_Control": [], + "Grande_Risco5": [ + "ALU_Control", + "Alu", + "Immediate_Generator", + "Forwarding_Unit", + "MUX", + "MUX" + ], + "Forwarding_Unit": [], + "Immediate_Generator": [], + "MUX": [], + "Registers": [], + "BUS": [], + "GPIO": [], + "GPIOS": [], + "LEDs": [], + "Memory": [], + "Risco_5_SOC": [], + "UART": [ + "UART", + "uart_tool_rx", + "uart_tool_tx" + ], + "uart_tool_rx": [], + "uart_tool_tx": [], + "alu_tb": [], + "clk_divider_tb": [ + "ClkDivider" + ], + "core_tb": [ + "Memory", + "Memory" + ], + "fifo_tb": [], + "gpio_tb": [ + "GPIOS" + ], + "immediate_generator_tb": [], + "mux_tb": [ + "MUX" + ], + "pc_tb": [], + "registers_tb": [ + "Registers" + ], + "reset_tb": [ + "ResetBootSystem" + ], + "soc_tb": [ + "Risco_5_SOC" + ] + }, + "non_tb_files": [ + "debug/clk_divider.v", + "debug/debug.v", + "debug/reset.v", + "fpga/colorlight_i9/main.v", + "fpga/digilent_arty/main.v", + "fpga/nexys4_ddr/main.v", + "fpga/tangnano20k/main.v", + "fpga/tangnano20k_yosys/main.v", + "src/core/alu.v", + "src/core/alu_control.v", + "src/core/core.v", + "src/core/forwarding_unit.v", + "src/core/immediate_generator.v", + "src/core/mux.v", + "src/core/registers.v", + "src/peripheral/bus.v", + "src/peripheral/gpio.v", + "src/peripheral/gpios.v", + "src/peripheral/leds.v", + "src/peripheral/memory.v", + "src/peripheral/soc.v", + "src/peripheral/uart.v", + "src/peripheral/uart_rx.v", + "src/peripheral/uart_tx.v" + ] +} \ No newline at end of file diff --git a/rtl/Grande-Risco-5.v b/rtl/Grande-Risco-5.v new file mode 100644 index 0000000..ebbae7e --- /dev/null +++ b/rtl/Grande-Risco-5.v @@ -0,0 +1,158 @@ +module processorci_top ( + `ifdef DIFERENCIAL_CLK + input wire clk_ref_p, + input wire clk_ref_n, + `else + input wire clk, + `endif + + input wire reset, + + // UART pins + input wire rx, + output wire tx + `ifndef DIFERENCIAL_CLK + , + + // SPI pins + input wire sck, + input wire cs, + input wire mosi, + output wire miso, + + //SPI control pins + input wire rw, + output wire intr + `endif +); + +wire clk_core, reset_core, reset_o; + +wire [31:0] instruction_address, instruction_data; +wire [31:0] data_address, data_write_data, data_read_data; +wire data_read, data_write, instruction_response, data_memory_response; + +Controller #( + .CLK_FREQ (`CLOCK_FREQ), + .BIT_RATE (115200), + .PAYLOAD_BITS (8), + .BUFFER_SIZE (8), + .PULSE_CONTROL_BITS(32), + .BUS_WIDTH (32), + .WORD_SIZE_BY (4), + .ID (0), + .RESET_CLK_CYCLES (20), + .MEMORY_FILE (""), + .MEMORY_SIZE (`MEMORY_SIZE) +) Controller( + `ifdef HIGH_CLK + .clk (clk_o), + `else + .clk (clk), + `endif + + .reset(reset_o), + + .tx(tx), + .rx(rx), + + .sck (sck), + .cs (cs), + .mosi(mosi), + .miso(miso), + + .rw (rw), + .intr(intr), + + .clk_core (clk_core), + .reset_core(reset_core), + + // main memory - instruction memory + .core_memory_response (instruction_response), // Memory response signal, 1 means that the memory operation is done + .core_read_memory (1'b0), // Read memory signal + .core_write_memory (1'b1), // Write memory signal + .core_address_memory (instruction_address), // Address to read or write + .core_write_data_memory(32'h00000000), // Data to write + .core_read_data_memory (instruction_data), // Data read from memory + + // Data memory + .core_memory_response_data (data_memory_response), // Memory response signal, 1 means that the memory operation is done + .core_read_memory_data (data_read), // Read memory signal + .core_write_memory_data (data_write), // Write memory signal + .core_address_memory_data (data_address), // Address to read or write + .core_write_data_memory_data(data_write_data), // Data to write + .core_read_data_memory_data (data_read_data) // Data read from memory +); + + +// Core space + +Grande_Risco5 Core( + .clk (clk_core), + .reset(reset_core), + + .instruction_response(instruction_response), + .instruction_address (instruction_address), + .instruction_data (instruction_data), + + .data_memory_response(data_memory_response), + .data_address (data_address), + .data_memory_read (data_read), + .data_memory_write (data_write), + .write_data (data_write_data), + .read_data (data_read_data) +); + +// Clock inflaestructure + +`ifdef HIGH_CLK + +reg clk_o; + +initial begin + clk_o = 1'b0; // 50mhz or 100mhz +end + +`ifdef DIFERENCIAL_CLK +wire clk_ref; // Sinal de clock single-ended + +// Instância do buffer diferencial +IBUFDS #( + .DIFF_TERM("FALSE"), // Habilita ou desabilita o terminador diferencial + .IBUF_LOW_PWR("TRUE"), // Ativa o modo de baixa potência + .IOSTANDARD("DIFF_SSTL15") +) ibufds_inst ( + .O(clk_ref), // Clock single-ended de saída + .I(clk_ref_p), // Entrada diferencial positiva + .IB(clk_ref_n) // Entrada diferencial negativa +); + + +always @(posedge clk_ref) begin + clk_o = ~clk_o; +end +`else +always @(posedge clk) begin + clk_o = ~clk_o; +end +`endif + +`endif + +// Reset Inflaestructure + +wire reset_o; + +ResetBootSystem #( + .CYCLES(20) +) ResetBootSystem( + `ifdef HIGH_CLK + .clk (clk_o), + `else + .clk (clk), + `endif + + .reset_o(reset_o) +); + +endmodule