From 58ac10d629a7ad9bc1f7a0efe63bb1f8e046975b Mon Sep 17 00:00:00 2001 From: Nikodem Kastelik Date: Mon, 22 Nov 2021 10:28:11 +0100 Subject: [PATCH] nrfx 2.6.0 release --- CHANGELOG.md | 21 + doc/nrfx.doxyfile | 52 +- doc/sphinx/nrfx_api/flag32_allocator.rst | 6 + drivers/include/nrf_bitmask.h | 9 + drivers/include/nrfx_dppi.h | 26 +- drivers/include/nrfx_gpiote.h | 256 ++- drivers/include/nrfx_nfct.h | 1 + drivers/include/nrfx_ppi.h | 20 +- drivers/include/nrfx_temp.h | 2 +- drivers/include/nrfx_usbd.h | 3 + drivers/nrfx_common.h | 18 + drivers/src/nrfx_clock.c | 24 +- drivers/src/nrfx_dppi.c | 157 +- drivers/src/nrfx_egu.c | 4 +- drivers/src/nrfx_gpiote.c | 1324 ++++++++----- drivers/src/nrfx_ipc.c | 2 +- drivers/src/nrfx_nfct.c | 42 +- drivers/src/nrfx_ppi.c | 207 +- drivers/src/nrfx_qdec.c | 4 +- drivers/src/nrfx_qspi.c | 11 + drivers/src/nrfx_saadc.c | 4 +- drivers/src/nrfx_usbd.c | 10 +- drivers/src/nrfx_usbreg.c | 3 + hal/nrf_common.h | 12 + hal/nrf_gpio.h | 62 +- hal/nrf_gpiote.h | 8 +- hal/nrf_timer.h | 52 + helpers/nrfx_flag32_allocator.c | 93 + helpers/nrfx_flag32_allocator.h | 120 ++ helpers/nrfx_gppi.h | 131 ++ mdk/arm_startup_nrf9160.s | 4 +- mdk/compiler_abstraction.h | 2 +- mdk/gcc_startup_nrf9160.S | 4 +- mdk/nrf.h | 16 +- mdk/nrf51.h | 6 +- mdk/nrf51_common.ld | 13 +- mdk/nrf52.h | 6 +- mdk/nrf52.svd | 37 +- mdk/nrf52805.h | 9 +- mdk/nrf52805.svd | 24 +- mdk/nrf52805_bitfields.h | 10 +- mdk/nrf52810.h | 9 +- mdk/nrf52810.svd | 24 +- mdk/nrf52810_bitfields.h | 10 +- mdk/nrf52811.h | 73 +- mdk/nrf52811.svd | 398 ++-- mdk/nrf52811_bitfields.h | 169 +- mdk/nrf52820.h | 21 +- mdk/nrf52820.svd | 92 +- mdk/nrf52820_bitfields.h | 80 +- mdk/nrf52833.h | 21 +- mdk/nrf52833.svd | 56 +- mdk/nrf52833_bitfields.h | 44 +- mdk/nrf52840.h | 18 +- mdk/nrf52840.svd | 73 +- mdk/nrf52840_bitfields.h | 59 +- mdk/nrf52_bitfields.h | 7 + mdk/nrf52_common.ld | 13 +- mdk/nrf52_erratas.h | 444 ++++- mdk/nrf5340_application.h | 11 +- mdk/nrf5340_application.svd | 14 +- mdk/nrf5340_application_bitfields.h | 6 +- mdk/nrf5340_application_peripherals.h | 2 + mdk/nrf5340_network.h | 11 +- mdk/nrf5340_network.svd | 1968 ++++++++++++++++--- mdk/nrf5340_network_bitfields.h | 422 +++- mdk/nrf5340_network_peripherals.h | 2 +- mdk/nrf5340_xxaa_application.ld | 2 +- mdk/nrf53_erratas.h | 673 +++++-- mdk/nrf9160.h | 6 +- mdk/nrf9160_peripherals.h | 42 +- mdk/nrf9160_xxaa.ld | 2 +- mdk/nrf91_erratas.h | 250 ++- mdk/nrf_common.ld | 13 +- mdk/ses_startup_nrf_common.s | 23 + mdk/system_nrf.h | 3 +- mdk/system_nrf51.c | 2 +- mdk/system_nrf51.h | 4 +- mdk/system_nrf52.c | 14 +- mdk/system_nrf52.h | 4 +- mdk/system_nrf52805.h | 4 +- mdk/system_nrf52810.h | 4 +- mdk/system_nrf52811.h | 4 +- mdk/system_nrf52820.h | 4 +- mdk/system_nrf52833.h | 4 +- mdk/system_nrf52840.h | 4 +- mdk/system_nrf52_approtect.h | 8 +- mdk/system_nrf5340_application.c | 53 +- mdk/system_nrf5340_application.h | 4 +- mdk/system_nrf5340_network.c | 2 +- mdk/system_nrf5340_network.h | 4 +- mdk/system_nrf53_approtect.h | 8 +- mdk/system_nrf9160.c | 168 +- mdk/system_nrf9160.h | 4 +- soc/nrfx_atomic.c | 62 +- templates/nrfx_config_nrf51.h | 13 +- templates/nrfx_config_nrf52805.h | 13 +- templates/nrfx_config_nrf52810.h | 13 +- templates/nrfx_config_nrf52811.h | 13 +- templates/nrfx_config_nrf52820.h | 13 +- templates/nrfx_config_nrf52832.h | 13 +- templates/nrfx_config_nrf52833.h | 13 +- templates/nrfx_config_nrf52840.h | 13 +- templates/nrfx_config_nrf5340_application.h | 7 +- templates/nrfx_config_nrf5340_network.h | 7 +- templates/nrfx_config_nrf9160.h | 7 +- templates/nrfx_glue.h | 34 + 107 files changed, 6301 insertions(+), 2095 deletions(-) create mode 100644 doc/sphinx/nrfx_api/flag32_allocator.rst create mode 100644 helpers/nrfx_flag32_allocator.c create mode 100644 helpers/nrfx_flag32_allocator.h diff --git a/CHANGELOG.md b/CHANGELOG.md index 2fce3121b3..9dc10105de 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,6 +1,27 @@ # Changelog All notable changes to this project are documented in this file. +## [2.6.0] - 2021-11-22 +### Added +- Added new functions for the GPIOTE peripheral management in the GPIOTE driver. Legacy API is now deprecated. +- Added support for the TIMER CC channels 6 and 7. +- Added the nrfx_flag32_allocator helper layer to unify resource allocation mechanism across several drivers. +- Added functions for getting shortcut bitmask associated with specified channel in the TIMER HAL. +- Added functions for channel allocation and deallocation in the nrfx_gppi helper layer. +- Added the nrf_gpio_reconfigure() function for selective reconfiguration of the specified pin. +- Introduced the NRFX_CLOCK_CONFIG_CT_ENABLED symbol for enabling the calibration timer support in the CLOCK driver. The symbol is enabled by default on supported SoCs. +- Introduced the NRFX_CTZ and NRFX_CLZ macros to allow providing custom implementation for these functionalities. By default `__RBIT()` and `__CLZ()` CMSIS macros are used. +- Introduced the NRFX_ATOMIC_CAS macro to allow providing custom implementation for atomic compare-and-swap functionality. +- Implemented workaround for the nRF9160 anomaly 7 in the NVMC driver. + +### Changed +- Updated MDK to version 8.44.1. + +### Fixed +- Fixed missing disabling of interrupts in the nrfx_qspi_lfm_start() and nrfx_qspi_lfm_xfer() functions. +- Fixed manual sample fetching when REPORTPER is disabled in the QDEC driver. +- Fixed a race condition in the NFCT driver when starting the transfer. + ## [2.5.0] - 2021-05-05 ### Added - Added support for double-buffered transfers in the QSPI driver. diff --git a/doc/nrfx.doxyfile b/doc/nrfx.doxyfile index ba6895481b..b0211543a3 100644 --- a/doc/nrfx.doxyfile +++ b/doc/nrfx.doxyfile @@ -40,7 +40,7 @@ PROJECT_NAME = "nrfx" ### EDIT THIS ### -PROJECT_NUMBER = "2.5" +PROJECT_NUMBER = "2.6" # Using the PROJECT_BRIEF tag one can provide an optional one line description # for a project that appears at the top of each page and should give viewer a @@ -243,7 +243,7 @@ ALIASES = "tagGreenTick=\htmlonly
# A mapping has the form "name=value". For example adding "class=itcl::class" # will allow you to use the command class in the itcl::class meaning. -TCL_SUBST = +# TCL_SUBST = # Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C sources # only. Doxygen will then generate output that is more tailored for C. For @@ -1082,7 +1082,7 @@ ALPHABETICAL_INDEX = NO # Minimum value: 1, maximum value: 20, default value: 5. # This tag requires that the tag ALPHABETICAL_INDEX is set to YES. -COLS_IN_ALPHA_INDEX = 5 +# COLS_IN_ALPHA_INDEX = 5 # In case all classes in a project start with a common prefix, all classes will # be put under the same header in the alphabetical index. The IGNORE_PREFIX tag @@ -1789,16 +1789,6 @@ LATEX_BATCHMODE = NO LATEX_HIDE_INDICES = NO -# If the LATEX_SOURCE_CODE tag is set to YES then doxygen will include source -# code with syntax highlighting in the LaTeX output. -# -# Note that which sources are shown also depends on other settings such as -# SOURCE_BROWSER. -# The default value is: NO. -# This tag requires that the tag GENERATE_LATEX is set to YES. - -LATEX_SOURCE_CODE = NO - # The LATEX_BIB_STYLE tag can be used to specify the style to use for the # bibliography, e.g. plainnat, or ieeetr. See # https://en.wikipedia.org/wiki/BibTeX and \cite for more info. @@ -2088,30 +2078,14 @@ INCLUDE_FILE_PATTERNS = PREDEFINED = SUPPRESS_INLINE_IMPLEMENTATION \ __NRFX_DOXYGEN__ \ - CONFIG_PURGE_ENABLED \ - == \ - 1 \ - CONFIG_DISASSOCIATE_ENABLED \ - == \ - 1 \ - CONFIG_GTS_ENABLED \ - == \ - 1 \ - CONFIG_ORPHAN_ENABLED \ - == \ - 1 \ - CONFIG_RXE_ENABLED \ - == \ - 1 \ - CONFIG_START_ENABLED \ - == \ - 1 \ - CONFIG_SYNC_ENABLED \ - == \ - 1 \ - CONFIG_PANID_CONFLICT_ENABLED \ - == \ - 1 + CONFIG_PURGE_ENABLED=1 \ + CONFIG_DISASSOCIATE_ENABLED=1 \ + CONFIG_GTS_ENABLED=1 \ + CONFIG_ORPHAN_ENABLED=1 \ + CONFIG_RXE_ENABLED=1 \ + CONFIG_START_ENABLED=1 \ + CONFIG_SYNC_ENABLED=1 \ + CONFIG_PANID_CONFLICT_ENABLED=1 # If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then this # tag can be used to specify a list of macro names that should be expanded. The @@ -2184,7 +2158,7 @@ EXTERNAL_GROUPS = NO # interpreter (i.e. the result of 'which perl'). # The default file (with absolute path) is: /usr/bin/perl. -PERL_PATH = /usr/bin/perl +# PERL_PATH = /usr/bin/perl #--------------------------------------------------------------------------- # Configuration options related to the dot tool @@ -2206,7 +2180,7 @@ CLASS_DIAGRAMS = YES # the mscgen tool resides. If left empty the tool is assumed to be found in the # default search path. -MSCGEN_PATH = +# MSCGEN_PATH = # You can include diagrams made with dia in doxygen documentation. Doxygen will # then run dia to produce the diagram and insert it in the documentation. The diff --git a/doc/sphinx/nrfx_api/flag32_allocator.rst b/doc/sphinx/nrfx_api/flag32_allocator.rst new file mode 100644 index 0000000000..580c173b50 --- /dev/null +++ b/doc/sphinx/nrfx_api/flag32_allocator.rst @@ -0,0 +1,6 @@ +Generic flag allocator +====================== + +.. doxygengroup:: nrfx_flag32_allocator + :project: nrfx + :members: diff --git a/drivers/include/nrf_bitmask.h b/drivers/include/nrf_bitmask.h index 19aa9f7d43..9a6432abba 100644 --- a/drivers/include/nrf_bitmask.h +++ b/drivers/include/nrf_bitmask.h @@ -47,6 +47,15 @@ extern "C" { * @brief Bitmask managing module. */ +/** + * @brief Get number of bytes needed to store the given bitmask. + * + * @param[in] bits_count Number of bits in the bitmask. + * + * @return Number of bytes to store requested bit mask. + */ +#define BITMASK_BYTES_CALCULATE(bits_count) NRFX_CEIL_DIV(bits_count, 8) + /** @brief Macro for getting index of byte in byte stream where @c abs_bit is put. */ #define BITMASK_BYTE_GET(abs_bit) ((abs_bit)/8) diff --git a/drivers/include/nrfx_dppi.h b/drivers/include/nrfx_dppi.h index 34f8df74fa..5fd86adbb3 100644 --- a/drivers/include/nrfx_dppi.h +++ b/drivers/include/nrfx_dppi.h @@ -55,10 +55,7 @@ void nrfx_dppi_free(void); * @brief Function for allocating a DPPI channel. * @details This function allocates the first unused DPPI channel. * - * @note To ensure the thread safety of the operation, this function uses the - * @ref NRFX_CRITICAL_SECTION_ENTER and @ref NRFX_CRITICAL_SECTION_EXIT - * macros. No further synchronization mechanism is needed, provided the - * macros are properly implemented (see @ref nrfx_glue). + * @note Function is thread safe as it uses @ref nrfx_flag32_alloc. * * @param[out] p_channel Pointer to the DPPI channel number that has been allocated. * @@ -69,12 +66,10 @@ nrfx_err_t nrfx_dppi_channel_alloc(uint8_t * p_channel); /** * @brief Function for freeing a DPPI channel. - * @details This function also disables the chosen channel. + * @details This function also disables the chosen channel. Configuration in + * PUBLISH/SUBSCRIBE registers used for the channel is not cleared. * - * @note To ensure the thread safety of the operation, this function uses the - * @ref NRFX_CRITICAL_SECTION_ENTER and @ref NRFX_CRITICAL_SECTION_EXIT - * macros. No further synchronization mechanism is needed, provided the - * macros are properly implemented (see @ref nrfx_glue). + * @note Function is thread safe as it uses @ref nrfx_flag32_free. * * @param[in] channel DPPI channel to be freed. * @@ -96,6 +91,9 @@ nrfx_err_t nrfx_dppi_channel_enable(uint8_t channel); /** * @brief Function for disabling a DPPI channel. * + * @note Disabling channel does not modify PUBLISH/SUBSCRIBE registers configured to use + * that channel. + * * @param[in] channel DPPI channel to be disabled. * * @retval NRFX_SUCCESS The channel was successfully disabled. @@ -107,10 +105,7 @@ nrfx_err_t nrfx_dppi_channel_disable(uint8_t channel); * @brief Function for allocating a DPPI channel group. * @details This function allocates the first unused DPPI group. * - * @note To ensure the thread safety of the operation, this function uses the - * @ref NRFX_CRITICAL_SECTION_ENTER and @ref NRFX_CRITICAL_SECTION_EXIT - * macros. No further synchronization mechanism is needed, provided the - * macros are properly implemented (see @ref nrfx_glue). + * @note Function is thread safe as it uses @ref nrfx_flag32_alloc. * * @param[out] p_group Pointer to the DPPI channel group that has been allocated. * @@ -123,10 +118,7 @@ nrfx_err_t nrfx_dppi_group_alloc(nrf_dppi_channel_group_t * p_group); * @brief Function for freeing a DPPI channel group. * @details This function also disables the chosen group. * - * @note To ensure the thread safety of the operation, this function uses the - * @ref NRFX_CRITICAL_SECTION_ENTER and @ref NRFX_CRITICAL_SECTION_EXIT - * macros. No further synchronization mechanism is needed, provided the - * macros are properly implemented (see @ref nrfx_glue). + * @note Function is thread safe as it uses @ref nrfx_flag32_free. * * @param[in] group DPPI channel group to be freed. * diff --git a/drivers/include/nrfx_gpiote.h b/drivers/include/nrfx_gpiote.h index 9048514372..f145da1951 100644 --- a/drivers/include/nrfx_gpiote.h +++ b/drivers/include/nrfx_gpiote.h @@ -49,6 +49,78 @@ extern "C" { * @brief GPIO Task Event (GPIOTE) peripheral driver. */ +/** @brief Pin. */ +typedef uint32_t nrfx_gpiote_pin_t; + +/** @brief Triggering options. */ +typedef enum +{ + NRFX_GPIOTE_TRIGGER_NONE, ///< No trigger on a pin. + NRFX_GPIOTE_TRIGGER_LOTOHI = GPIOTE_CONFIG_POLARITY_LoToHi, ///< Low to high edge trigger. + NRFX_GPIOTE_TRIGGER_HITOLO, ///< High to low edge trigger. + NRFX_GPIOTE_TRIGGER_TOGGLE, ///< Edge toggle trigger. + NRFX_GPIOTE_TRIGGER_LOW, ///< Level low trigger. + NRFX_GPIOTE_TRIGGER_HIGH, ///< Level high trigger. + NRFX_GPIOTE_TRIGGER_MAX, ///< Triggering options count. +} nrfx_gpiote_trigger_t; + +/** + * @brief Pin interrupt handler prototype. + * + * @param[in] pin Pin that triggered this event. + * @param[in] trigger Trigger that led to this event. + * @param[in] p_context User context. + */ +typedef void (*nrfx_gpiote_interrupt_handler_t)(nrfx_gpiote_pin_t pin, + nrfx_gpiote_trigger_t trigger, + void * p_context); + +/** @brief Structure for configuring a GPIOTE task. */ +typedef struct +{ + uint8_t task_ch; ///< GPIOTE channel to be used. + /**< Set to value allocated using + * @ref nrfx_gpiote_channel_alloc. It is a user + * responsibility to free the channel. */ + nrf_gpiote_polarity_t polarity; ///< Task polarity configuration. + /**< @ref NRF_GPIOTE_POLARITY_NONE is used + * to disable previously configured task. */ + nrf_gpiote_outinit_t init_val; ///< Initial pin state. +} nrfx_gpiote_task_config_t; + +/** @brief Structure for configuring an output pin. */ +typedef struct +{ + nrf_gpio_pin_drive_t drive; ///< Drive configuration. + nrf_gpio_pin_input_t input_connect; ///< Input buffer connection. + nrf_gpio_pin_pull_t pull; ///< Pull configuration. + /**< Pull setting is used together with + * drive configurations D0 and D1. */ +} nrfx_gpiote_output_config_t; + +/** @brief Structure for configuring an input pin. */ +typedef struct +{ + nrf_gpio_pin_pull_t pull; ///< Pull configuration. +} nrfx_gpiote_input_config_t; + +/** @brief Structure for configuring pin interrupt/event. */ +typedef struct +{ + nrfx_gpiote_trigger_t trigger; ///< Specify trigger. + uint8_t const * p_in_channel; ///< Pointer to GPIOTE channel for IN event. + /**< If NULL, the sensing mechanism is used + * instead. Note that when channel is provided + * only edge triggering can be used. */ +} nrfx_gpiote_trigger_config_t; + +/** @brief Structure for configuring a pin interrupt handler. */ +typedef struct +{ + nrfx_gpiote_interrupt_handler_t handler; ///< User handler. + void * p_context; ///< Context passed to the event handler. +} nrfx_gpiote_handler_config_t; + /** @brief Input pin configuration. */ typedef struct { @@ -59,6 +131,20 @@ typedef struct bool skip_gpio_setup : 1; /**< Do not change GPIO configuration */ } nrfx_gpiote_in_config_t; +/** @brief Output pin default configuration. */ +#define NRFX_GPIOTE_DEFAULT_OUTPUT_CONFIG \ +{ \ + .drive = NRF_GPIO_PIN_S0S1, \ + .input_connect = NRF_GPIO_PIN_INPUT_DISCONNECT, \ + .pull = NRF_GPIO_PIN_NOPULL \ +} + +/** @brief Input pin default configuration. */ +#define NRFX_GPIOTE_DEFAULT_INPUT_CONFIG \ +{ \ + .pull = NRF_GPIO_PIN_NOPULL \ +} + /** * @brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect low-to-high transition. * @details Set hi_accu to true to use IN_EVENT. @@ -195,20 +281,11 @@ typedef struct #define NRFX_GPIOTE_CHANNELS_USED 0 #endif -#if (GPIOTE_CH_NUM == 4) || defined(__NRFX_DOXYGEN__) /** @brief Bitfield representing all GPIOTE channels available to the application. */ -#define NRFX_GPIOTE_APP_CHANNELS_MASK ((uint32_t)0x0000000F & ~(NRFX_GPIOTE_CHANNELS_USED)) -#elif (GPIOTE_CH_NUM == 8) -#define NRFX_GPIOTE_APP_CHANNELS_MASK ((uint32_t)0x000000FF & ~(NRFX_GPIOTE_CHANNELS_USED)) -#else -#error Unsupported number of GPIOTE channels. -#endif - -/** @brief Pin. */ -typedef uint32_t nrfx_gpiote_pin_t; +#define NRFX_GPIOTE_APP_CHANNELS_MASK (NRFX_BIT_MASK(GPIOTE_CH_NUM) & ~NRFX_GPIOTE_CHANNELS_USED) /** - * @brief Pin event handler prototype. + * @brief Legacy pin event handler prototype. * * @param[in] pin Pin that triggered this event. * @param[in] action Action that led to triggering this event. @@ -244,10 +321,7 @@ void nrfx_gpiote_uninit(void); * @details This function allocates the first unused GPIOTE channel from * pool defined in @ref NRFX_GPIOTE_APP_CHANNELS_MASK. * - * @note To ensure the thread safety of the operation, this function uses the - * @ref NRFX_CRITICAL_SECTION_ENTER and @ref NRFX_CRITICAL_SECTION_EXIT - * macros. No further synchronization mechanism is needed, provided the - * macros are properly implemented (see @ref nrfx_glue). + * @note Function is thread safe as it uses @ref nrfx_flag32_alloc. * @note Routines that allocate and free the GPIOTE channels are independent * from the rest of the driver. In particular, the driver does not need * to be initialized when this function is called. @@ -264,10 +338,7 @@ nrfx_err_t nrfx_gpiote_channel_alloc(uint8_t * p_channel); * @details This function frees a GPIOTE channel that was allocated using * @ref nrfx_gpiote_channel_alloc. * - * @note To ensure the thread safety of the operation, this function uses the - * @ref NRFX_CRITICAL_SECTION_ENTER and @ref NRFX_CRITICAL_SECTION_EXIT - * macros. No further synchronization mechanism is needed, provided the - * macros are properly implemented (see @ref nrfx_glue). + * @note Function is thread safe as it uses @ref nrfx_flag32_free. * @note Routines that allocate and free the GPIOTE channels are independent * from the rest of the driver. In particular, the driver does not need * to be initialized when this function is called. @@ -279,6 +350,118 @@ nrfx_err_t nrfx_gpiote_channel_alloc(uint8_t * p_channel); */ nrfx_err_t nrfx_gpiote_channel_free(uint8_t channel); +/** + * @brief Function for configuring the specified input pin and input event/interrupt. + * + * Prior to calling this function pin can be uninitialized or configured as input or + * output. However, following transitions and configurations are invalid and result + * in error returned by the function: + * + * - Setting level trigger (e.g. @ref NRFX_GPIOTE_TRIGGER_HIGH) and using GPIOTE + * channel for the same pin. + * - Reconfiguring pin to input (@p p_input_config not NULL) when pin was configured + * to use GPIOTE task. Prior to that, task must be disabled by configuring it with + * polarity set to @ref NRF_GPIOTE_POLARITY_NONE. + * - Configuring trigger using GPIOTE channel for pin previously configured as output + * pin. Only sensing can be used for an output pin. + * + * Function can be used to configure trigger and handler for sensing input changes + * on an output pin. In that case, prior to that output pin must be configured with + * input buffer connected. In that case @p p_input_config is NULL to avoid reconfiguration + * of the pin. + * + * @param[in] pin Absolute pin number. + * @param[in] p_input_config Pin configuration. If NULL, the current configuration is untouched. + * @param[in] p_trigger_config Interrupt/event configuration. If NULL, the current configuration + * is untouched. + * @param[in] p_handler_config Handler configuration. If NULL it is untouched. + * + * @retval NRFX_SUCCESS Configuration was successful. + * @retval NRFX_ERROR_INVALID_PARAM Invalid configuration. + */ +nrfx_err_t nrfx_gpiote_input_configure(nrfx_gpiote_pin_t pin, + nrfx_gpiote_input_config_t const * p_input_config, + nrfx_gpiote_trigger_config_t const * p_trigger_config, + nrfx_gpiote_handler_config_t const * p_handler_config); + +/** + * @brief Function for configuring the specified output pin to be used by the driver. + * + * Prior to calling this function pin can be uninitialized or configured as input or + * output. However, following transitions and configurations are invalid and result + * in error returned by the function: + * + * - Reconfiguring pin to output when pin was configured as input with trigger using + * GPIOTE channel. Prior to that, trigger must be disabled by configuring it as + * @ref NRFX_GPIOTE_TRIGGER_NONE. + * - Configuring pin as output without input buffer connected when prior to that + * trigger was configured. In that case input buffer must be connected. + * - Configuring GPIOTE task for pin which was previously configured as input. Before + * using GPIOTE task pin must be configured as output by providing @p p_config. + * + * @param[in] pin Absolute pin number. + * @param[in] p_config Pin configuration. If NULL pin configuration is not applied. + * @param[in] p_task_config GPIOTE task configuration. If NULL task is not used. + * + * @retval NRFX_SUCCESS Configuration was successful. + * @retval NRFX_ERROR_INVALID_PARAM Invalid configuration. + */ +nrfx_err_t nrfx_gpiote_output_configure(nrfx_gpiote_pin_t pin, + nrfx_gpiote_output_config_t const * p_config, + nrfx_gpiote_task_config_t const * p_task_config); + +/** + * @brief Function for deinitializing the specified pin. + * + * Specified pin and associated GPIOTE channel are restored to the default configuration. + * + * @warning GPIOTE channel used by the pin is not freed. + * + * @param[in] pin Absolute pin number. + * + * @retval NRFX_SUCCESS Uninitialization was successful. + * @retval NRFX_ERROR_INVALID_PARAM Pin not used by the driver. + */ +nrfx_err_t nrfx_gpiote_pin_uninit(nrfx_gpiote_pin_t pin); + +/** + * @brief Function for enabling trigger for the given pin. + * + * When GPIOTE event is used trigger can be enabled without enabling interrupt, + * e.g. for PPI. + * + * @param[in] pin Absolute pin number. + * @param[in] int_enable True to enable the interrupt. Must be true when sensing is used. + */ +void nrfx_gpiote_trigger_enable(nrfx_gpiote_pin_t pin, bool int_enable); + +/** + * @brief Function for disabling trigger for the given pin. + * + * @param[in] pin Absolute pin number. + */ +void nrfx_gpiote_trigger_disable(nrfx_gpiote_pin_t pin); + +/** + * @brief Set global callback called for each event. + * + * @param[in] handler Global handler. + * @param[in] p_context Context passed to the handler. + */ +void nrfx_gpiote_global_callback_set(nrfx_gpiote_interrupt_handler_t handler, + void * p_context); + +/** + * @brief Function for retrieving Task/Event channel index associated with the given pin. + * + * @param[in] pin Absolute pin number. + * @param[out] p_channel Location to write the channel index. + * + * @retval NRFX_SUCCESS Channel successfully written. + * @retval NRFX_ERROR_INVALID_PARAM Pin is not configured or not using Task or Event. + */ +nrfx_err_t nrfx_gpiote_channel_get(nrfx_gpiote_pin_t pin, uint8_t *p_channel); + /** * @brief Function for initializing a GPIOTE output pin. * @details The output pin can be controlled by the CPU or by PPI. The initial @@ -286,6 +469,9 @@ nrfx_err_t nrfx_gpiote_channel_free(uint8_t channel); * attempts to allocate one of the available GPIOTE channels. If no channel is * available, an error is returned. * + * @note This function is deprecated. Use @ref nrfx_gpiote_output_configure + * preceded by @ref nrfx_gpiote_channel_alloc (provided that GPIOTE task is to be utilized) instead. + * * @param[in] pin Pin. * @param[in] p_config Initial configuration. * @@ -304,6 +490,8 @@ nrfx_err_t nrfx_gpiote_out_init(nrfx_gpiote_pin_t pin, * @param[in] p_config Initial configuration. * @param[in] channel GPIOTE channel allocated with @ref nrfx_gpiote_channel_alloc. * + * @note This function is deprecated. Use @ref nrfx_gpiote_output_configure instead. + * * @retval NRFX_SUCCESS Initialization was successful. * @retval NRFX_ERROR_BUSY The pin is already used. * @retval NRFX_ERROR_INVALID_PARAM Pin is configured to not be controlled by @@ -319,6 +507,9 @@ nrfx_err_t nrfx_gpiote_out_prealloc_init(nrfx_gpiote_pin_t pin, * @brief Function for uninitializing a GPIOTE output pin. * @details The driver frees the GPIOTE channel if the output pin was using one. * + * @note This function is deprecated. Use @ref nrfx_gpiote_pin_uninit, + * followed by @ref nrfx_gpiote_channel_free (provided that GPIOTE task was utilized) instead. + * * @param[in] pin Pin. */ void nrfx_gpiote_out_uninit(nrfx_gpiote_pin_t pin); @@ -440,6 +631,9 @@ uint32_t nrfx_gpiote_clr_task_addr_get(nrfx_gpiote_pin_t pin); * low accuracy pins to toggle mode. * For more information about SENSE functionality, refer to Product Specification. * + * @note This function is deprecated. Use @ref nrfx_gpiote_input_configure + * preceded by @ref nrfx_gpiote_channel_alloc (provided that IN event is to be utilized) instead. + * * @param[in] pin Pin. * @param[in] p_config Initial configuration. * @param[in] evt_handler User function to be called when the configured transition occurs. @@ -462,6 +656,8 @@ nrfx_err_t nrfx_gpiote_in_init(nrfx_gpiote_pin_t pin, * @param[in] channel GPIOTE channel allocated with @ref nrfx_gpiote_channel_alloc. * @param[in] evt_handler User function to be called when the configured transition occurs. * + * @note This function is deprecated. Use @ref nrfx_gpiote_input_configure instead. + * * @retval NRFX_SUCCESS Initialization was successful. * @retval NRFX_ERROR_BUSY The pin is already used. * @retval NRFX_ERROR_INVALID_PARAM Pin is configured to not be controlled by @@ -473,10 +669,14 @@ nrfx_err_t nrfx_gpiote_in_prealloc_init(nrfx_gpiote_pin_t pin, nrfx_gpiote_in_config_t const * p_config, uint8_t channel, nrfx_gpiote_evt_handler_t evt_handler); + /** * @brief Function for uninitializing a GPIOTE input pin. * @details The driver frees the GPIOTE channel if the input pin was using one. * + * @note This function is deprecated. Use @ref nrfx_gpiote_pin_uninit, + * followed by @ref nrfx_gpiote_channel_free (provided that IN event was utilized) instead. + * * @param[in] pin Pin. */ void nrfx_gpiote_in_uninit(nrfx_gpiote_pin_t pin); @@ -488,17 +688,21 @@ void nrfx_gpiote_in_uninit(nrfx_gpiote_pin_t pin); * enables an IN_EVENT. Otherwise, the function enables the GPIO sense mechanism. * The PORT event is shared between multiple pins, therefore the interrupt is always enabled. * + * @note This function is deprecated. Use @ref nrfx_gpiote_trigger_enable instead. + * * @param[in] pin Pin. * @param[in] int_enable True to enable the interrupt. Always valid for a high-accuracy pin. */ -void nrfx_gpiote_in_event_enable(nrfx_gpiote_pin_t pin, bool int_enable); +NRFX_STATIC_INLINE void nrfx_gpiote_in_event_enable(nrfx_gpiote_pin_t pin, bool int_enable); /** * @brief Function for disabling a GPIOTE input pin. * + * @note This function is deprecated. Use @ref nrfx_gpiote_trigger_disable instead. + * * @param[in] pin Pin. */ -void nrfx_gpiote_in_event_disable(nrfx_gpiote_pin_t pin); +NRFX_STATIC_INLINE void nrfx_gpiote_in_event_disable(nrfx_gpiote_pin_t pin); /** * @brief Function for checking if a GPIOTE input pin is set. @@ -588,6 +792,16 @@ NRFX_STATIC_INLINE nrf_gpiote_latency_t nrfx_gpiote_latency_get(void); #ifndef NRFX_DECLARE_ONLY +NRFX_STATIC_INLINE void nrfx_gpiote_in_event_enable(nrfx_gpiote_pin_t pin, bool int_enable) +{ + nrfx_gpiote_trigger_enable(pin, int_enable); +} + +NRFX_STATIC_INLINE void nrfx_gpiote_in_event_disable(nrfx_gpiote_pin_t pin) +{ + nrfx_gpiote_trigger_disable(pin); +} + #if NRF_GPIOTE_HAS_LATENCY NRFX_STATIC_INLINE void nrfx_gpiote_latency_set(nrf_gpiote_latency_t latency) { diff --git a/drivers/include/nrfx_nfct.h b/drivers/include/nrfx_nfct.h index b89509ba05..aa83fcb6dc 100644 --- a/drivers/include/nrfx_nfct.h +++ b/drivers/include/nrfx_nfct.h @@ -234,6 +234,7 @@ void nrfx_nfct_rx(nrfx_nfct_data_desc_t const * p_rx_data); * * @retval NRFX_SUCCESS The operation was successful. * @retval NRFX_ERROR_INVALID_LENGTH The TX buffer size is invalid. + * @retval NRFX_ERROR_BUSY Driver is already transferring. */ nrfx_err_t nrfx_nfct_tx(nrfx_nfct_data_desc_t const * p_tx_data, nrf_nfct_frame_delay_mode_t delay_mode); diff --git a/drivers/include/nrfx_ppi.h b/drivers/include/nrfx_ppi.h index 4824361b28..33520db6c2 100644 --- a/drivers/include/nrfx_ppi.h +++ b/drivers/include/nrfx_ppi.h @@ -82,10 +82,7 @@ void nrfx_ppi_free_all(void); * @brief Function for allocating a PPI channel. * @details This function allocates the first unused PPI channel. * - * @note To ensure the thread safety of the operation, this function uses the - * @ref NRFX_CRITICAL_SECTION_ENTER and @ref NRFX_CRITICAL_SECTION_EXIT - * macros. No further synchronization mechanism is needed, provided the - * macros are properly implemented (see @ref nrfx_glue). + * @note Function is thread safe as it uses @ref nrfx_flag32_alloc. * * @param[out] p_channel Pointer to the PPI channel that has been allocated. * @@ -98,10 +95,7 @@ nrfx_err_t nrfx_ppi_channel_alloc(nrf_ppi_channel_t * p_channel); * @brief Function for freeing a PPI channel. * @details This function also disables the chosen channel. * - * @note To ensure the thread safety of the operation, this function uses the - * @ref NRFX_CRITICAL_SECTION_ENTER and @ref NRFX_CRITICAL_SECTION_EXIT - * macros. No further synchronization mechanism is needed, provided the - * macros are properly implemented (see @ref nrfx_glue). + * @note Function is thread safe as it uses @ref nrfx_flag32_free. * * @param[in] channel PPI channel to be freed. * @@ -161,10 +155,7 @@ nrfx_err_t nrfx_ppi_channel_disable(nrf_ppi_channel_t channel); * @brief Function for allocating a PPI channel group. * @details This function allocates the first unused PPI group. * - * @note To ensure the thread safety of the operation, this function uses the - * @ref NRFX_CRITICAL_SECTION_ENTER and @ref NRFX_CRITICAL_SECTION_EXIT - * macros. No further synchronization mechanism is needed, provided the - * macros are properly implemented (see @ref nrfx_glue). + * @note Function is thread safe as it uses @ref nrfx_flag32_alloc. * * @param[out] p_group Pointer to the PPI channel group that has been allocated. * @@ -177,10 +168,7 @@ nrfx_err_t nrfx_ppi_group_alloc(nrf_ppi_channel_group_t * p_group); * @brief Function for freeing a PPI channel group. * @details This function also disables the chosen group. * - * @note To ensure the thread safety of the operation, this function uses the - * @ref NRFX_CRITICAL_SECTION_ENTER and @ref NRFX_CRITICAL_SECTION_EXIT - * macros. No further synchronization mechanism is needed, provided the - * macros are properly implemented (see @ref nrfx_glue). + * @note Function is thread safe as it uses @ref nrfx_flag32_free. * * @param[in] group PPI channel group to be freed. * diff --git a/drivers/include/nrfx_temp.h b/drivers/include/nrfx_temp.h index 09a780d016..3a9ac0bd6b 100644 --- a/drivers/include/nrfx_temp.h +++ b/drivers/include/nrfx_temp.h @@ -67,7 +67,7 @@ typedef struct * representation. This value can be converted to Celsius * scale using the @ref nrfx_temp_calculate() function. */ -typedef void (* nrfx_temp_data_handler_t)(int32_t raw_temperature); +typedef void (* nrfx_temp_data_handler_t)(int32_t temperature); /** * @brief Function for initializing the TEMP driver. diff --git a/drivers/include/nrfx_usbd.h b/drivers/include/nrfx_usbd.h index 26db0a47a0..009179d08d 100644 --- a/drivers/include/nrfx_usbd.h +++ b/drivers/include/nrfx_usbd.h @@ -76,6 +76,9 @@ extern "C" { * * Auxiliary macros for creating endpoint identifiers compatible with the USB specification. * @{ + */ + +/** * @brief Create identifier for IN endpoint. * * Simple macro to create IN endpoint identifier for given endpoint number. diff --git a/drivers/nrfx_common.h b/drivers/nrfx_common.h index b6d86ca3cf..a51a7c92a0 100644 --- a/drivers/nrfx_common.h +++ b/drivers/nrfx_common.h @@ -80,6 +80,24 @@ extern "C" { */ #define NRFX_CHECK(module_enabled) (module_enabled) +/** + * @brief Macro for creating unsigned integer with bit position @p x set. + * + * @param[in] x Bit position to be set. + * + * @return Unsigned integer with requested bit position set. + */ +#define NRFX_BIT(x) (1UL << (x)) + +/** + * @brief Macro for returning bit mask or 0 if @p x is 0. + * + * @param[in] x Bit mask size. Bit mask has bits 0 through x-1 (inclusive) set. + * + * @return Bit mask. + */ +#define NRFX_BIT_MASK(x) (NRFX_BIT(x) - 1UL) + /** * @brief Macro for concatenating two tokens in macro expansion. * diff --git a/drivers/src/nrfx_clock.c b/drivers/src/nrfx_clock.c index 26ffc1bb39..777c7962db 100644 --- a/drivers/src/nrfx_clock.c +++ b/drivers/src/nrfx_clock.c @@ -111,6 +111,14 @@ extern bool nrfx_power_irq_enabled; #error "Two-stage LFXO start procedure enabled but LFCLK source is not set to LFXO!" #endif +#if !defined(NRFX_CLOCK_CONFIG_CT_ENABLED) && NRF_CLOCK_HAS_CALIBRATION_TIMER +#define NRFX_CLOCK_CONFIG_CT_ENABLED 1 +#endif + +#if NRFX_CHECK(NRFX_CLOCK_CONFIG_CT_ENABLED) && !NRF_CLOCK_HAS_CALIBRATION_TIMER + #error "Calibration timer is not available in the SoC that is used." +#endif + #if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED) typedef enum { @@ -433,7 +441,8 @@ nrfx_err_t nrfx_clock_is_calibrating(void) void nrfx_clock_calibration_timer_start(uint8_t interval) { -#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED) && NRF_CLOCK_HAS_CALIBRATION_TIMER +#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED) && \ + NRFX_CHECK(NRFX_CLOCK_CONFIG_CT_ENABLED) && NRF_CLOCK_HAS_CALIBRATION_TIMER nrf_clock_cal_timer_timeout_set(NRF_CLOCK, interval); nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_CTTO); nrf_clock_int_enable(NRF_CLOCK, NRF_CLOCK_INT_CTTO_MASK); @@ -445,7 +454,8 @@ void nrfx_clock_calibration_timer_start(uint8_t interval) void nrfx_clock_calibration_timer_stop(void) { -#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED) && NRF_CLOCK_HAS_CALIBRATION_TIMER +#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED) && \ + NRFX_CHECK(NRFX_CLOCK_CONFIG_CT_ENABLED) && NRF_CLOCK_HAS_CALIBRATION_TIMER nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_CTTO_MASK); nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_CTSTOP); #endif @@ -570,8 +580,9 @@ void nrfx_clock_irq_handler(void) } #if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED) -#if NRF_CLOCK_HAS_CALIBRATION_TIMER - if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_CTTO)) +#if NRF_CLOCK_HAS_CALIBRATION_TIMER && NRFX_CHECK(NRFX_CLOCK_CONFIG_CT_ENABLED) + if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_CTTO) && + nrf_clock_int_enable_check(NRF_CLOCK, NRF_CLOCK_INT_CTTO_MASK)) { nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_CTTO); NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_CTTO"); @@ -579,9 +590,10 @@ void nrfx_clock_irq_handler(void) m_clock_cb.event_handler(NRFX_CLOCK_EVT_CTTO); } -#endif // NRF_CLOCK_HAS_CALIBRATION_TIMER +#endif // NRF_CLOCK_HAS_CALIBRATION_TIMER && NRFX_CHECK(NRFX_CLOCK_CONFIG_CT_ENABLED) - if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_DONE)) + if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_DONE) && + nrf_clock_int_enable_check(NRF_CLOCK, NRF_CLOCK_INT_DONE_MASK)) { #if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_192) *(volatile uint32_t *)0x40000C34 = 0x00000000; diff --git a/drivers/src/nrfx_dppi.c b/drivers/src/nrfx_dppi.c index 8dd93dd7cd..e12f7970ae 100644 --- a/drivers/src/nrfx_dppi.c +++ b/drivers/src/nrfx_dppi.c @@ -36,6 +36,7 @@ #if NRFX_CHECK(NRFX_DPPI_ENABLED) #include +#include #define NRFX_LOG_MODULE DPPI #include @@ -59,27 +60,19 @@ /** @brief Set bit at given position. */ #define DPPI_BIT_SET(pos) (1uL << (pos)) -static uint32_t m_allocated_channels; - -static uint8_t m_allocated_groups; - -static bool channel_is_allocated(uint8_t channel) -{ - return ((m_allocated_channels & DPPI_BIT_SET(channel)) != 0); -} - -static bool group_is_allocated(nrf_dppi_channel_group_t group) -{ - return ((m_allocated_groups & DPPI_BIT_SET(group)) != 0); -} +/**< Bitmap representing channels availability. */ +static nrfx_atomic_t m_allocated_channels = DPPI_AVAILABLE_CHANNELS_MASK; +/**< Bitmap representing groups availability. */ +static nrfx_atomic_t m_allocated_groups = DPPI_AVAILABLE_GROUPS_MASK; void nrfx_dppi_free(void) { - uint32_t mask = m_allocated_groups; + uint32_t mask = DPPI_AVAILABLE_GROUPS_MASK & ~m_allocated_groups; uint8_t group_idx = NRF_DPPI_CHANNEL_GROUP0; // Disable all channels - nrf_dppi_channels_disable(NRF_DPPIC, m_allocated_channels); + nrf_dppi_channels_disable(NRF_DPPIC, + DPPI_AVAILABLE_CHANNELS_MASK & ~m_allocated_channels); // Clear all groups configurations while (mask) @@ -94,79 +87,28 @@ void nrfx_dppi_free(void) } // Clear all allocated channels. - m_allocated_channels = 0; + m_allocated_channels = DPPI_AVAILABLE_CHANNELS_MASK; // Clear all allocated groups. - m_allocated_groups = 0; + m_allocated_groups = DPPI_AVAILABLE_GROUPS_MASK; } nrfx_err_t nrfx_dppi_channel_alloc(uint8_t * p_channel) { - nrfx_err_t err_code; - - NRFX_CRITICAL_SECTION_ENTER(); - // Get mask of available DPPI channels - uint32_t remaining_channels = DPPI_AVAILABLE_CHANNELS_MASK & ~(m_allocated_channels); - uint8_t channel = 0; - - if (!remaining_channels) - { - err_code = NRFX_ERROR_NO_MEM; - } - else - { - // Find first free channel - while (!(remaining_channels & DPPI_BIT_SET(channel))) - { - channel++; - } - - m_allocated_channels |= DPPI_BIT_SET(channel); - *p_channel = channel; - - err_code = NRFX_SUCCESS; - } - NRFX_CRITICAL_SECTION_EXIT(); - - if (err_code == NRFX_SUCCESS) - { - NRFX_LOG_INFO("Allocated channel: %d.", *p_channel); - } - else - { - NRFX_LOG_INFO("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - } - return err_code; + return nrfx_flag32_alloc(&m_allocated_channels, p_channel); } nrfx_err_t nrfx_dppi_channel_free(uint8_t channel) { - nrfx_err_t err_code = NRFX_SUCCESS; - - NRFX_CRITICAL_SECTION_ENTER(); - if (!channel_is_allocated(channel)) - { - err_code = NRFX_ERROR_INVALID_PARAM; - } - else - { - // First disable this channel - nrf_dppi_channels_disable(NRF_DPPIC, DPPI_BIT_SET(channel)); - // Clear channel allocated indication. - m_allocated_channels &= ~DPPI_BIT_SET(channel); - } - NRFX_CRITICAL_SECTION_EXIT(); - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; + nrf_dppi_channels_disable(NRF_DPPIC, NRFX_BIT(channel)); + return nrfx_flag32_free(&m_allocated_channels, channel); } nrfx_err_t nrfx_dppi_channel_enable(uint8_t channel) { nrfx_err_t err_code = NRFX_SUCCESS; - if (!channel_is_allocated(channel)) + if (!nrfx_flag32_is_allocated(m_allocated_channels, channel)) { err_code = NRFX_ERROR_INVALID_PARAM; } @@ -182,7 +124,7 @@ nrfx_err_t nrfx_dppi_channel_disable(uint8_t channel) { nrfx_err_t err_code = NRFX_SUCCESS; - if (!channel_is_allocated(channel)) + if (!nrfx_flag32_is_allocated(m_allocated_channels, channel)) { err_code = NRFX_ERROR_INVALID_PARAM; } @@ -197,64 +139,13 @@ nrfx_err_t nrfx_dppi_channel_disable(uint8_t channel) nrfx_err_t nrfx_dppi_group_alloc(nrf_dppi_channel_group_t * p_group) { - nrfx_err_t err_code; - - NRFX_CRITICAL_SECTION_ENTER(); - // Get mask of available DPPI groups - uint32_t remaining_groups = DPPI_AVAILABLE_GROUPS_MASK & ~(m_allocated_groups); - uint8_t group_idx = NRF_DPPI_CHANNEL_GROUP0; - - if (!remaining_groups) - { - err_code = NRFX_ERROR_NO_MEM; - } - else - { - // Find first free group - while (!(remaining_groups & DPPI_BIT_SET((nrf_dppi_channel_group_t)group_idx))) - { - group_idx++; - } - - nrf_dppi_channel_group_t group = (nrf_dppi_channel_group_t)group_idx; - m_allocated_groups |= DPPI_BIT_SET(group); - *p_group = group; - - err_code = NRFX_SUCCESS; - } - NRFX_CRITICAL_SECTION_EXIT(); - - if (err_code == NRFX_SUCCESS) - { - NRFX_LOG_INFO("Allocated channel: %d.", *p_group); - } - else - { - NRFX_LOG_INFO("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - } - return err_code; + return nrfx_flag32_alloc(&m_allocated_groups, (uint8_t *)p_group); } nrfx_err_t nrfx_dppi_group_free(nrf_dppi_channel_group_t group) { - nrfx_err_t err_code = NRFX_SUCCESS; - - NRFX_CRITICAL_SECTION_ENTER(); - if (!group_is_allocated(group)) - { - err_code = NRFX_ERROR_INVALID_PARAM; - } - else - { - nrf_dppi_group_disable(NRF_DPPIC, group); - // Set bit value to zero at position corresponding to the group number. - m_allocated_groups &= ~DPPI_BIT_SET(group); - } - NRFX_CRITICAL_SECTION_EXIT(); - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; + nrf_dppi_group_disable(NRF_DPPIC, group); + return nrfx_flag32_free(&m_allocated_groups, group); } nrfx_err_t nrfx_dppi_channel_include_in_group(uint8_t channel, @@ -262,7 +153,8 @@ nrfx_err_t nrfx_dppi_channel_include_in_group(uint8_t channel, { nrfx_err_t err_code = NRFX_SUCCESS; - if (!group_is_allocated(group) || !channel_is_allocated(channel)) + if (!nrfx_flag32_is_allocated(m_allocated_groups, group) || + !nrfx_flag32_is_allocated(m_allocated_channels, channel)) { err_code = NRFX_ERROR_INVALID_PARAM; } @@ -281,7 +173,8 @@ nrfx_err_t nrfx_dppi_channel_remove_from_group(uint8_t channel, { nrfx_err_t err_code = NRFX_SUCCESS; - if (!group_is_allocated(group) || !channel_is_allocated(channel)) + if (!nrfx_flag32_is_allocated(m_allocated_groups, group) || + !nrfx_flag32_is_allocated(m_allocated_channels, channel)) { err_code = NRFX_ERROR_INVALID_PARAM; } @@ -299,7 +192,7 @@ nrfx_err_t nrfx_dppi_group_clear(nrf_dppi_channel_group_t group) { nrfx_err_t err_code = NRFX_SUCCESS; - if (!group_is_allocated(group)) + if (!nrfx_flag32_is_allocated(m_allocated_groups, group)) { err_code = NRFX_ERROR_INVALID_PARAM; } @@ -315,7 +208,7 @@ nrfx_err_t nrfx_dppi_group_enable(nrf_dppi_channel_group_t group) { nrfx_err_t err_code = NRFX_SUCCESS; - if (!group_is_allocated(group)) + if (!nrfx_flag32_is_allocated(m_allocated_groups, group)) { err_code = NRFX_ERROR_INVALID_PARAM; } @@ -331,7 +224,7 @@ nrfx_err_t nrfx_dppi_group_disable(nrf_dppi_channel_group_t group) { nrfx_err_t err_code = NRFX_SUCCESS; - if (!group_is_allocated(group)) + if (!nrfx_flag32_is_allocated(m_allocated_groups, group)) { err_code = NRFX_ERROR_INVALID_PARAM; } diff --git a/drivers/src/nrfx_egu.c b/drivers/src/nrfx_egu.c index 8a8f4f783b..147e872017 100644 --- a/drivers/src/nrfx_egu.c +++ b/drivers/src/nrfx_egu.c @@ -79,7 +79,7 @@ static uint32_t egu_event_mask_get_and_clear(NRF_EGU_Type * p_reg, uint32_t int_ uint32_t event_mask = 0; while (int_mask) { - uint8_t event_idx = __CLZ(__RBIT(int_mask)); + uint8_t event_idx = NRF_CTZ(int_mask); int_mask &= ~(1uL << event_idx); nrf_egu_event_t event = nrf_egu_triggered_event_get(event_idx); @@ -166,7 +166,7 @@ static void egu_irq_handler(NRF_EGU_Type * p_reg, egu_control_block_t * p_cb) uint32_t event_mask = egu_event_mask_get_and_clear(p_reg, int_mask); while (event_mask) { - uint8_t event_idx = __CLZ(__RBIT(event_mask)); + uint8_t event_idx = NRF_CTZ(event_mask); event_mask &= ~(1uL << event_idx); p_cb->handler(event_idx, p_cb->p_context); } diff --git a/drivers/src/nrfx_gpiote.c b/drivers/src/nrfx_gpiote.c index babd2106a1..b44cbb3da3 100644 --- a/drivers/src/nrfx_gpiote.c +++ b/drivers/src/nrfx_gpiote.c @@ -35,6 +35,7 @@ #if NRFX_CHECK(NRFX_GPIOTE_ENABLED) #include +#include #include "nrf_bitmask.h" #include @@ -49,191 +50,543 @@ #error "Not supported." #endif -#define UNALLOCATED_HANDLER_ADDRESS ((nrfx_gpiote_evt_handler_t)UINT32_MAX) -#define ALLOCATED_HANDLER_ADDRESS ((nrfx_gpiote_evt_handler_t)(UINT32_MAX-1)) -#define PIN_NOT_USED (-1) -#define PIN_USED (-2) -#define NO_CHANNELS (-1) -#define POLARITY_FIELD_POS (6) -#define POLARITY_FIELD_MASK (0xC0) +/* Use legacy configuration if new is not present. That will lead to slight + * increase of RAM usage since number of slots will exceed application need. + */ +#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS +#define NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS \ + (GPIOTE_CH_NUM + NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS) +#endif + +/* Verify that trigger matches gpiote enum. */ +NRFX_STATIC_ASSERT(NRFX_GPIOTE_TRIGGER_LOTOHI == GPIOTE_CONFIG_POLARITY_LoToHi); +NRFX_STATIC_ASSERT(NRFX_GPIOTE_TRIGGER_HITOLO == GPIOTE_CONFIG_POLARITY_HiToLo); +NRFX_STATIC_ASSERT(NRFX_GPIOTE_TRIGGER_TOGGLE == GPIOTE_CONFIG_POLARITY_Toggle); + +/* + * 2 bytes are dedicated for each pin to store it's current state. + * + * +--------+-------+-----------------------+-----+--------+--------+---------+-------+ + * | 0 | 1 | 2-4 | 5 | 6 | 7 | 8-12 | 13-15 | + * +--------+-------+-----------------------+-----+--------+--------+---------+-------+ + * | in use | dir | nrfx_gpiote_trigger_t | te | skip | legacy |8: | TE | + * | 0: no | 0:in | | used| config | api | present | index | + * | 1: yes | 1:out | | | | |9-12: | (when | + * | | | | | | | handler | used)| + * | | | | | | | index | | + * +--------+-------+-----------------------+-----+--------+--------+---------+-------+ + * + */ + +/* Flags content when pin is not used by the driver. */ +#define PIN_FLAG_NOT_USED 0 + +#define PIN_FLAG_IN_USE NRFX_BIT(0) + +#define PIN_FLAG_DIR_MASK NRFX_BIT(1) + +/* Flag indicating output direction. */ +#define PIN_FLAG_OUTPUT PIN_FLAG_DIR_MASK + +/* Macro checks if pin is output. */ +#define PIN_FLAG_IS_OUTPUT(flags) ((flags & PIN_FLAG_DIR_MASK) == PIN_FLAG_OUTPUT) + +/* Trigger mode field. It stores the information about a trigger type. If trigger + * is not enabled, it holds information about task usage and pin direction. */ +#define PIN_FLAG_TRIG_MODE_OFFSET 2 +#define PIN_FLAG_TRIG_MODE_BITS 3 +#define PIN_FLAG_TRIG_MODE_MASK \ + (NRFX_BIT_MASK(PIN_FLAG_TRIG_MODE_BITS) << PIN_FLAG_TRIG_MODE_OFFSET) +NRFX_STATIC_ASSERT(NRFX_GPIOTE_TRIGGER_MAX <= NRFX_BIT(PIN_FLAG_TRIG_MODE_BITS)); + +/* Macro sets trigger mode field. */ +#define PIN_FLAG_TRIG_MODE_SET(trigger) (trigger << PIN_FLAG_TRIG_MODE_OFFSET) -/* Check if every pin can be encoded on provided number of bits. */ -NRFX_STATIC_ASSERT(MAX_PIN_NUMBER <= (1 << POLARITY_FIELD_POS)); +/* Macro gets trigger mode from pin flags. */ +#define PIN_FLAG_TRIG_MODE_GET(flags) \ + (nrfx_gpiote_trigger_t)((flags & PIN_FLAG_TRIG_MODE_MASK) >> PIN_FLAG_TRIG_MODE_OFFSET) +#define PIN_FLAG_TE_USED NRFX_BIT(5) +#define PIN_FLAG_SKIP_CONFIG NRFX_BIT(6) +#define PIN_FLAG_LEGACY_API_PIN NRFX_BIT(7) + +#define PIN_FLAG_HANDLER_PRESENT NRFX_BIT(8) + +#define PIN_HANDLER_ID_SHIFT 9 +#define PIN_HANDLER_ID_BITS 4 +#define PIN_HANDLER_ID_MASK (NRFX_BIT_MASK(PIN_HANDLER_ID_BITS) << PIN_HANDLER_ID_SHIFT) +#define PIN_HANDLER_MASK (PIN_FLAG_HANDLER_PRESENT | PIN_HANDLER_ID_MASK) + +/* Macro for encoding handler index into the flags. */ +#define PIN_FLAG_HANDLER(x) \ + (PIN_FLAG_HANDLER_PRESENT | ((x) << PIN_HANDLER_ID_SHIFT)) + +/* Pin in use but no handler attached. */ +#define PIN_FLAG_NO_HANDLER -1 + +/* Macro for getting handler index from flags. -1 is returned when no handler */ +#define PIN_GET_HANDLER_ID(flags) \ + ((flags & PIN_FLAG_HANDLER_PRESENT) \ + ? (int32_t)((flags & PIN_HANDLER_ID_MASK) >> PIN_HANDLER_ID_SHIFT) \ + : PIN_FLAG_NO_HANDLER) + +#define PIN_HANDLER_MAX_COUNT NRFX_BIT_MASK(PIN_HANDLER_ID_BITS) +NRFX_STATIC_ASSERT(NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS <= PIN_HANDLER_MAX_COUNT); + +#define PIN_TE_ID_SHIFT 13 +#define PIN_TE_ID_BITS 3 +#define PIN_TE_ID_MASK (NRFX_BIT_MASK(PIN_TE_ID_BITS) << PIN_TE_ID_SHIFT) + +/* Validate that field is big enough for number of channels. */ +NRFX_STATIC_ASSERT((NRFX_BIT(PIN_TE_ID_BITS)) >= GPIOTE_CH_NUM); + +/* Macro for encoding Task/Event index into the flags. */ +#define PIN_FLAG_TE_ID(x) \ + (PIN_FLAG_TE_USED | (((x) << PIN_TE_ID_SHIFT) & PIN_TE_ID_MASK)) + +/* Macro for getting Task/Event index from flags. */ +#define PIN_GET_TE_ID(flags) ((flags & PIN_TE_ID_MASK) >> PIN_TE_ID_SHIFT) + +/* Structure holding state of the pins */ typedef struct { - nrfx_gpiote_evt_handler_t handlers[GPIOTE_CH_NUM + NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS]; - int8_t pin_assignments[MAX_PIN_NUMBER]; - int8_t port_handlers_pins[NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS]; - uint8_t configured_pins[((MAX_PIN_NUMBER)+7) / 8]; - nrfx_drv_state_t state; - uint32_t allocated_channels_mask; + /* Pin specific handlers. */ + nrfx_gpiote_handler_config_t handlers[NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS]; + + /* Global handler called on each event */ + nrfx_gpiote_handler_config_t global_handler; + + /* Each pin state */ + uint16_t pin_flags[MAX_PIN_NUMBER]; + + /* Mask for tracking gpiote channel allocation. */ + nrfx_atomic_t available_channels_mask; + + /* Mask for tracking event handler entries allocation. */ + nrfx_atomic_t available_evt_handlers; + +#if !defined(NRF_GPIO_LATCH_PRESENT) + uint32_t port_pins[GPIO_COUNT]; +#endif + nrfx_drv_state_t state; } gpiote_control_block_t; -static gpiote_control_block_t m_cb; +static gpiote_control_block_t m_cb = { + .available_channels_mask = NRFX_GPIOTE_APP_CHANNELS_MASK +}; +/** @brief Checks if pin is in use by the driver. + * + * @param[in] pin Absolute pin. + * + * @return True if pin is in use. + */ static bool pin_in_use(uint32_t pin) { - return (m_cb.pin_assignments[pin] != PIN_NOT_USED); + return m_cb.pin_flags[pin] & PIN_FLAG_IN_USE; } - -static bool pin_in_use_as_non_task_out(uint32_t pin) +/** @brief Check if Task/Event is used. + * + * Assuming that pin is in use. + * + * @param[in] pin Absolute pin. + * + * @return True if pin uses GPIOTE task/event. + */ +static bool pin_in_use_by_te(uint32_t pin) { - return (m_cb.pin_assignments[pin] == PIN_USED); + return m_cb.pin_flags[pin] & PIN_FLAG_TE_USED; } - -static bool pin_in_use_by_te(uint32_t pin) +/** @brief Check if pin has trigger. + * + * @param[in] pin Absolute pin. + * + * @return True if pin has trigger. + */ +static bool pin_has_trigger(uint32_t pin) { - return (m_cb.pin_assignments[pin] >= 0 && m_cb.pin_assignments[pin] < GPIOTE_CH_NUM) ? - true : false; + return PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]) != NRFX_GPIOTE_TRIGGER_NONE; } - -static bool pin_in_use_by_port(uint32_t pin) +/** @brief Check if pin is output. + * + * Assuming that pin is in use. + * + * @param[in] pin Absolute pin. + * + * @return True if pin is output. + */ +static bool pin_is_output(uint32_t pin) { - return (m_cb.pin_assignments[pin] >= GPIOTE_CH_NUM); + return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]); } - -static bool pin_in_use_by_gpiote(uint32_t pin) +/** @brief Check if pin is output controlled by GPIOTE task. + * + * @param[in] pin Absolute pin. + * + * @return True if pin is task output. + */ +static bool pin_is_task_output(uint32_t pin) { - return (m_cb.pin_assignments[pin] >= 0); + return pin_is_output(pin) && pin_in_use_by_te(pin); } - -static void pin_in_use_by_te_set(uint32_t pin, - uint32_t channel_id, - nrfx_gpiote_evt_handler_t handler, - bool is_channel) +/** @brief Check if pin is used by the driver and configured as input. + * + * @param[in] pin Absolute pin. + * + * @return True if pin is configured as input. + */ +static bool pin_is_input(uint32_t pin) { - m_cb.pin_assignments[pin] = channel_id; - m_cb.handlers[channel_id] = handler; - if (!is_channel) - { - m_cb.port_handlers_pins[channel_id - GPIOTE_CH_NUM] = (int8_t)pin; - } + return !pin_is_output(pin); } - -static void pin_in_use_set(uint32_t pin) +/* Convert polarity enum (HAL) to trigger enum. */ +static nrfx_gpiote_trigger_t gpiote_polarity_to_trigger(nrf_gpiote_polarity_t polarity) { - m_cb.pin_assignments[pin] = PIN_USED; + return (nrfx_gpiote_trigger_t)polarity; } - -static void pin_in_use_clear(uint32_t pin) +/* Convert trigger enum to polarity enum (HAL). */ +static nrf_gpiote_polarity_t gpiote_trigger_to_polarity(nrfx_gpiote_trigger_t trigger) { - m_cb.pin_assignments[pin] = PIN_NOT_USED; + return (nrf_gpiote_polarity_t)trigger; } - -static void pin_configured_set(uint32_t pin) +/* Returns gpiote TE channel associated with the pin */ +static uint8_t pin_te_get(nrfx_gpiote_pin_t pin) { - nrf_bitmask_bit_set(pin, m_cb.configured_pins); + return PIN_GET_TE_ID(m_cb.pin_flags[pin]); } -static void pin_configured_clear(uint32_t pin) +static bool is_level(nrfx_gpiote_trigger_t trigger) { - nrf_bitmask_bit_clear(pin, m_cb.configured_pins); + return trigger >= NRFX_GPIOTE_TRIGGER_LOW; } -static bool pin_configured_check(uint32_t pin) +static bool handler_in_use(int32_t handler_id) { - return 0 != nrf_bitmask_bit_is_set(pin, m_cb.configured_pins); + + for (uint32_t i = 0; i < MAX_PIN_NUMBER; i++) + { + if (PIN_GET_HANDLER_ID(m_cb.pin_flags[i]) == handler_id) + { + return true; + } + } + + return false; } -static int8_t channel_port_get(uint32_t pin) +/* Function clears pin handler flag and releases handler slot if handler+context + * pair is not used by other pin. */ +static void release_handler(nrfx_gpiote_pin_t pin) { - return m_cb.pin_assignments[pin]; -} + int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]); + + if (handler_id == PIN_FLAG_NO_HANDLER) + { + return; + } + + m_cb.pin_flags[pin] &= ~PIN_HANDLER_MASK; + /* Check if other pin is using same handler and release handler only if handler + * is not used by others. + */ + if (!handler_in_use(handler_id)) + { + m_cb.handlers[handler_id].handler = NULL; + nrfx_err_t err = nrfx_flag32_free(&m_cb.available_evt_handlers, handler_id); + (void)err; + NRFX_ASSERT(err == NRFX_SUCCESS); + } +} -static nrfx_gpiote_evt_handler_t channel_handler_get(uint32_t channel) +/* Function releases the handler associated with the pin and sets GPIOTE channel + * configuration to default if it was used with the pin. + */ +static void pin_handler_trigger_uninit(nrfx_gpiote_pin_t pin) { - if ((m_cb.handlers[channel] != UNALLOCATED_HANDLER_ADDRESS) - && (m_cb.handlers[channel] != ALLOCATED_HANDLER_ADDRESS)) + if (pin_in_use_by_te(pin)) { - return m_cb.handlers[channel]; + /* te to default */ + nrf_gpiote_te_default(NRF_GPIOTE, pin_te_get(pin)); } else { - return NULL; +#if !defined(NRF_GPIO_LATCH_PRESENT) + nrf_bitmask_bit_clear(pin, (uint8_t *)m_cb.port_pins); +#endif + } + + release_handler(pin); + m_cb.pin_flags[pin] = PIN_FLAG_NOT_USED; +} + +nrfx_err_t nrfx_gpiote_pin_uninit(nrfx_gpiote_pin_t pin) +{ + if (!pin_in_use(pin)) + { + return NRFX_ERROR_INVALID_PARAM; } + + nrfx_gpiote_trigger_disable(pin); + pin_handler_trigger_uninit(pin); + nrf_gpio_cfg_default(pin); + + return NRFX_SUCCESS; } -static nrfx_gpiote_pin_t port_handler_pin_get(uint32_t handler_idx) +static int32_t find_handler(nrfx_gpiote_interrupt_handler_t handler, void * p_context) { - uint8_t pin_and_polarity = (uint8_t)m_cb.port_handlers_pins[handler_idx]; - return (nrfx_gpiote_pin_t)(pin_and_polarity & ~POLARITY_FIELD_MASK); + for (uint32_t i = 0; i < NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS; i++) + { + if ((m_cb.handlers[i].handler == handler) && (m_cb.handlers[i].p_context == p_context)) + { + return i; + } + } + + return -1; } -static nrf_gpiote_polarity_t port_handler_polarity_get(uint32_t handler_idx) +/** @brief Set new handler, if handler was not previously set allocate it. */ +static nrfx_err_t pin_handler_set(nrfx_gpiote_pin_t pin, + nrfx_gpiote_interrupt_handler_t handler, + void * p_context) { - uint8_t pin_and_polarity = (uint8_t)m_cb.port_handlers_pins[handler_idx]; - return (nrf_gpiote_polarity_t)((pin_and_polarity & POLARITY_FIELD_MASK) >> POLARITY_FIELD_POS); + nrfx_err_t err; + int32_t handler_id; + + release_handler(pin); + if (!handler) + { + return NRFX_SUCCESS; + } + + handler_id = find_handler(handler, p_context); + /* Handler not found, new must be allocated. */ + if (handler_id < 0) + { + uint8_t id; + + err = nrfx_flag32_alloc(&m_cb.available_evt_handlers, &id); + if (err != NRFX_SUCCESS) + { + return err; + } + handler_id = (int32_t)id; + } + + m_cb.handlers[handler_id].handler = handler; + m_cb.handlers[handler_id].p_context = p_context; + m_cb.pin_flags[pin] |= PIN_FLAG_HANDLER(handler_id); + + return NRFX_SUCCESS; } -static bool low_accuracy_channel_alloc(uint8_t channel_id) +static inline nrf_gpio_pin_sense_t get_initial_sense(nrfx_gpiote_pin_t pin) { - bool ret = false; + nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]); + nrf_gpio_pin_sense_t sense; - NRFX_CRITICAL_SECTION_ENTER(); - if (m_cb.handlers[channel_id] == UNALLOCATED_HANDLER_ADDRESS) + if (trigger == NRFX_GPIOTE_TRIGGER_LOW) { - m_cb.handlers[channel_id] = ALLOCATED_HANDLER_ADDRESS; - ret = true; + sense = NRF_GPIO_PIN_SENSE_LOW; + } + else if (trigger == NRFX_GPIOTE_TRIGGER_HIGH) + { + sense = NRF_GPIO_PIN_SENSE_HIGH; + } + else + { + /* If edge detection start with sensing opposite state. */ + sense = nrf_gpio_pin_read(pin) ? NRF_GPIO_PIN_SENSE_LOW : NRF_GPIO_PIN_SENSE_HIGH; } - NRFX_CRITICAL_SECTION_EXIT(); - return ret; + return sense; } -static int8_t accuracy_channel_alloc(bool hi_accuracy) +nrfx_err_t nrfx_gpiote_input_configure(nrfx_gpiote_pin_t pin, + nrfx_gpiote_input_config_t const * p_input_config, + nrfx_gpiote_trigger_config_t const * p_trigger_config, + nrfx_gpiote_handler_config_t const * p_handler_config) { - int8_t channel_id = NO_CHANNELS; + nrfx_err_t err; - if (hi_accuracy) + if (p_input_config) { - uint8_t i; - if (nrfx_gpiote_channel_alloc(&i) == NRFX_SUCCESS) + if (pin_is_task_output(pin)) { - channel_id = i; + return NRFX_ERROR_INVALID_PARAM; } + + nrf_gpio_pin_dir_t dir = NRF_GPIO_PIN_DIR_INPUT; + nrf_gpio_pin_input_t input_connect = NRF_GPIO_PIN_INPUT_CONNECT; + + nrf_gpio_reconfigure(pin, &dir, &input_connect, &p_input_config->pull, NULL, NULL); + + m_cb.pin_flags[pin] &= ~PIN_FLAG_OUTPUT; + m_cb.pin_flags[pin] |= PIN_FLAG_IN_USE; } - else + + if (p_trigger_config) { - for (uint8_t i = GPIOTE_CH_NUM; i < (GPIOTE_CH_NUM + NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS); i++) + nrfx_gpiote_trigger_t trigger = p_trigger_config->trigger; + bool use_evt = p_trigger_config->p_in_channel ? true : false; + + if (pin_is_output(pin)) { - if (low_accuracy_channel_alloc(i)) + if (use_evt) { - channel_id = i; - break; + return NRFX_ERROR_INVALID_PARAM; } } + else + { + m_cb.pin_flags[pin] &= ~(PIN_TE_ID_MASK | PIN_FLAG_TE_USED); + if (use_evt) + { + bool edge = trigger <= NRFX_GPIOTE_TRIGGER_TOGGLE; + + /* IN event used. */ + if (!edge) + { + /* IN event supports only edge trigger. */ + return NRFX_ERROR_INVALID_PARAM; + } + + uint8_t ch = *p_trigger_config->p_in_channel; + + if (trigger == NRFX_GPIOTE_TRIGGER_NONE) + { + nrf_gpiote_te_default(NRF_GPIOTE, ch); + } + else + { + nrf_gpiote_polarity_t polarity = gpiote_trigger_to_polarity(trigger); + + nrf_gpiote_event_disable(NRF_GPIOTE, ch); + nrf_gpiote_event_configure(NRF_GPIOTE, ch, pin, polarity); + + m_cb.pin_flags[pin] |= PIN_FLAG_TE_ID(ch); + } + } + } +#if !defined(NRF_GPIO_LATCH_PRESENT) + if (use_evt || trigger == NRFX_GPIOTE_TRIGGER_NONE) + { + nrf_bitmask_bit_clear(pin, (uint8_t *)m_cb.port_pins); + } + else + { + nrf_bitmask_bit_set(pin, (uint8_t *)m_cb.port_pins); + } +#endif + m_cb.pin_flags[pin] &= ~PIN_FLAG_TRIG_MODE_MASK; + m_cb.pin_flags[pin] |= PIN_FLAG_TRIG_MODE_SET(trigger); + } + + if (p_handler_config) + { + err = pin_handler_set(pin, p_handler_config->handler, p_handler_config->p_context); + } + else + { + err = NRFX_SUCCESS; + } + + return err; +} + +nrfx_err_t nrfx_gpiote_output_configure(nrfx_gpiote_pin_t pin, + nrfx_gpiote_output_config_t const * p_config, + nrfx_gpiote_task_config_t const * p_task_config) +{ + if (p_config) + { + /* Cannot configure pin to output if pin was using TE event. */ + if (pin_is_input(pin) && pin_in_use_by_te(pin)) + { + return NRFX_ERROR_INVALID_PARAM; + } + + /* If reconfiguring to output pin that has trigger configured then accept + * only when input is still connected. */ + if (pin_has_trigger(pin) && (p_config->input_connect == NRF_GPIO_PIN_INPUT_DISCONNECT)) + { + return NRFX_ERROR_INVALID_PARAM; + } + + nrf_gpio_pin_dir_t dir = NRF_GPIO_PIN_DIR_OUTPUT; + + nrf_gpio_reconfigure(pin, &dir, &p_config->input_connect, &p_config->pull, + &p_config->drive, NULL); + + m_cb.pin_flags[pin] |= PIN_FLAG_IN_USE | PIN_FLAG_OUTPUT; + } + + if (p_task_config) + { + if (pin_is_input(pin)) + { + return NRFX_ERROR_INVALID_PARAM; + } + + uint32_t ch = p_task_config->task_ch; + + nrf_gpiote_te_default(NRF_GPIOTE, ch); + m_cb.pin_flags[pin] &= ~(PIN_FLAG_TE_USED | PIN_TE_ID_MASK); + if (p_task_config->polarity != NRF_GPIOTE_POLARITY_NONE) + { + nrf_gpiote_task_configure(NRF_GPIOTE, ch, pin, + p_task_config->polarity, + p_task_config->init_val); + m_cb.pin_flags[pin] |= PIN_FLAG_TE_ID(ch); + } } - return channel_id; + return NRFX_SUCCESS; } +void nrfx_gpiote_global_callback_set(nrfx_gpiote_interrupt_handler_t handler, void * p_context) +{ + m_cb.global_handler.handler = handler; + m_cb.global_handler.p_context = p_context; +} -static void channel_free(uint8_t channel_id) +nrfx_err_t nrfx_gpiote_channel_get(nrfx_gpiote_pin_t pin, uint8_t *p_channel) { - NRFX_CRITICAL_SECTION_ENTER(); - m_cb.handlers[channel_id] = UNALLOCATED_HANDLER_ADDRESS; + NRFX_ASSERT(p_channel); - if (channel_id >= GPIOTE_CH_NUM) + if (pin_in_use_by_te(pin)) { - m_cb.port_handlers_pins[channel_id - GPIOTE_CH_NUM] = (int8_t)PIN_NOT_USED; + *p_channel = PIN_GET_TE_ID(m_cb.pin_flags[pin]); + return NRFX_SUCCESS; } else { - nrfx_gpiote_channel_free(channel_id); + return NRFX_ERROR_INVALID_PARAM; } - NRFX_CRITICAL_SECTION_EXIT(); } +/* Return handler associated with given pin or null. */ +static nrfx_gpiote_handler_config_t const * channel_handler_get(nrfx_gpiote_pin_t pin) +{ + int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]); + + if (handler_id == PIN_FLAG_NO_HANDLER) + { + return NULL; + } + + return &m_cb.handlers[handler_id]; +} nrfx_err_t nrfx_gpiote_init(uint8_t interrupt_priority) { @@ -248,32 +601,15 @@ nrfx_err_t nrfx_gpiote_init(uint8_t interrupt_priority) return err_code; } - uint8_t i; - - for (i = 0; i < MAX_PIN_NUMBER; i++) - { - if (nrf_gpio_pin_present_check(i)) - { - pin_in_use_clear(i); - } - } - - for (i = 0; i < (GPIOTE_CH_NUM + NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS); i++) - { - m_cb.handlers[i] = UNALLOCATED_HANDLER_ADDRESS; - if (i >= GPIOTE_CH_NUM) - { - m_cb.port_handlers_pins[i - GPIOTE_CH_NUM] = (int8_t)PIN_NOT_USED; - } - } - - memset(m_cb.configured_pins, 0, sizeof(m_cb.configured_pins)); + memset(m_cb.pin_flags, 0, sizeof(m_cb.pin_flags)); NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(NRF_GPIOTE), interrupt_priority); NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_GPIOTE)); + nrf_gpiote_event_clear(NRF_GPIOTE, NRF_GPIOTE_EVENT_PORT); - nrf_gpiote_int_enable(NRF_GPIOTE, GPIOTE_INTENSET_PORT_Msk); + nrf_gpiote_int_enable(NRF_GPIOTE, (uint32_t)NRF_GPIOTE_INT_PORT_MASK); m_cb.state = NRFX_DRV_STATE_INITIALIZED; + m_cb.available_evt_handlers = NRFX_BIT_MASK(NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS); err_code = NRFX_SUCCESS; NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); @@ -295,18 +631,23 @@ void nrfx_gpiote_uninit(void) for (i = 0; i < MAX_PIN_NUMBER; i++) { - if (nrf_gpio_pin_present_check(i)) + if (nrf_gpio_pin_present_check(i) && pin_in_use(i)) { - if (pin_in_use_as_non_task_out(i)) + if (m_cb.pin_flags[i] & PIN_FLAG_LEGACY_API_PIN) { - nrfx_gpiote_out_uninit(i); + m_cb.pin_flags[i] &= ~PIN_FLAG_LEGACY_API_PIN; + if (pin_has_trigger(i)) + { + nrfx_gpiote_in_uninit(i); + } + else + { + nrfx_gpiote_out_uninit(i); + } } - else if (pin_in_use_by_gpiote(i)) + else { - /* Disable gpiote_in is having the same effect on out pin as gpiote_out_uninit on - * so it can be called on all pins used by GPIOTE. - */ - nrfx_gpiote_in_uninit(i); + nrfx_gpiote_pin_uninit(i); } } } @@ -314,166 +655,79 @@ void nrfx_gpiote_uninit(void) NRFX_LOG_INFO("Uninitialized."); } -static bool is_allocated_channel(uint8_t index) -{ - return m_cb.allocated_channels_mask & (1UL << index); -} - -static bool is_app_channel(uint8_t index) -{ - return NRFX_GPIOTE_APP_CHANNELS_MASK & (1UL << index); -} - -static void channel_allocated_set(uint8_t index) +nrfx_err_t nrfx_gpiote_channel_free(uint8_t channel) { - m_cb.allocated_channels_mask |= (1UL << index); + return nrfx_flag32_free(&m_cb.available_channels_mask, channel); } -static void channel_allocated_clr(uint8_t index) +nrfx_err_t nrfx_gpiote_channel_alloc(uint8_t * p_channel) { - m_cb.allocated_channels_mask &= ~(1UL << index); + return nrfx_flag32_alloc(&m_cb.available_channels_mask, p_channel); } -nrfx_err_t nrfx_gpiote_channel_free(uint8_t channel) +nrfx_err_t nrfx_gpiote_out_init(nrfx_gpiote_pin_t pin, + nrfx_gpiote_out_config_t const * p_config) { - nrfx_err_t err_code = NRFX_SUCCESS; + uint8_t ch; + nrfx_err_t err; - if (!is_app_channel(channel)) + if (p_config->task_pin) { - err_code = NRFX_ERROR_INVALID_PARAM; + err = nrfx_gpiote_channel_alloc(&ch); + if (err != NRFX_SUCCESS) + { + return err; + } } else { - NRFX_CRITICAL_SECTION_ENTER(); - channel_allocated_clr(channel); - NRFX_CRITICAL_SECTION_EXIT(); + /* Value will not be used. */ + ch = 0xFF; } - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -nrfx_err_t nrfx_gpiote_channel_alloc(uint8_t * p_channel) -{ - nrfx_err_t err_code = NRFX_ERROR_NO_MEM; - uint32_t mask = NRFX_GPIOTE_APP_CHANNELS_MASK; - - for (uint8_t ch_idx = 0; mask != 0; ch_idx++) + err = nrfx_gpiote_out_prealloc_init(pin, p_config, ch); + if (err == NRFX_ERROR_BUSY && p_config->task_pin) { - NRFX_CRITICAL_SECTION_ENTER(); - if ((mask & (1UL << ch_idx)) && (!is_allocated_channel(ch_idx))) - { - channel_allocated_set(ch_idx); - *p_channel = ch_idx; - err_code = NRFX_SUCCESS; - } - NRFX_CRITICAL_SECTION_EXIT(); - - if (err_code == NRFX_SUCCESS) - { - NRFX_LOG_INFO("Allocated channel: %d.", ch_idx); - break; - } - - mask &= ~(1UL << ch_idx); + nrfx_gpiote_channel_free(ch); } - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; + return err; } -static nrfx_err_t gpiote_out_init(nrfx_gpiote_pin_t pin, - nrfx_gpiote_out_config_t const * p_config, - bool prealloc, - uint8_t channel) +nrfx_err_t nrfx_gpiote_out_prealloc_init(nrfx_gpiote_pin_t pin, + nrfx_gpiote_out_config_t const * p_config, + uint8_t channel) { - NRFX_ASSERT(nrf_gpio_pin_present_check(pin)); - NRFX_ASSERT(m_cb.state == NRFX_DRV_STATE_INITIALIZED); - NRFX_ASSERT(p_config); - - nrfx_err_t err_code = NRFX_SUCCESS; + nrfx_gpiote_output_config_t config = NRFX_GPIOTE_DEFAULT_OUTPUT_CONFIG; + nrfx_gpiote_task_config_t task_config; + bool use_task = p_config->task_pin; + nrfx_err_t err; if (pin_in_use(pin)) { - err_code = NRFX_ERROR_BUSY; + return NRFX_ERROR_BUSY; } - else - { - if (p_config->task_pin) - { - int8_t ch = NO_CHANNELS; - if (prealloc) - { - ch = channel; - } - else - { - ch = accuracy_channel_alloc(true); - } - - if (ch != NO_CHANNELS) - { - pin_in_use_by_te_set(pin, ch, NULL, true); - nrf_gpiote_task_configure(NRF_GPIOTE, - (uint32_t)ch, - pin, - p_config->action, - p_config->init_state); - } - else - { - err_code = NRFX_ERROR_NO_MEM; - } - } - else if (prealloc) - { - /* Calling this function with preallocated channel - * does not make sense when task_pin is false. - */ - err_code = NRFX_ERROR_INVALID_PARAM; - } - else - { - pin_in_use_set(pin); - } - - if (err_code == NRFX_SUCCESS) - { - if (p_config->init_state == NRF_GPIOTE_INITIAL_VALUE_HIGH) - { - nrf_gpio_pin_set(pin); - } - else - { - nrf_gpio_pin_clear(pin); - } - - nrf_gpio_cfg_output(pin); - pin_configured_set(pin); - } + if (p_config->init_state == NRF_GPIOTE_INITIAL_VALUE_HIGH) + { + nrf_gpio_pin_set(pin); } - return err_code; -} - -nrfx_err_t nrfx_gpiote_out_init(nrfx_gpiote_pin_t pin, - nrfx_gpiote_out_config_t const * p_config) -{ - nrfx_err_t err_code = gpiote_out_init(pin, p_config, false, 0); + if (use_task) + { - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} + task_config.task_ch = channel; + task_config.init_val = p_config->init_state; + task_config.polarity = p_config->action; + } -nrfx_err_t nrfx_gpiote_out_prealloc_init(nrfx_gpiote_pin_t pin, - nrfx_gpiote_out_config_t const * p_config, - uint8_t channel) -{ - nrfx_err_t err_code = gpiote_out_init(pin, p_config, true, channel); + err = nrfx_gpiote_output_configure(pin, &config, use_task ? &task_config : NULL); + if (err == NRFX_SUCCESS) + { + m_cb.pin_flags[pin] |= PIN_FLAG_LEGACY_API_PIN; + } - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; + return err; } void nrfx_gpiote_out_uninit(nrfx_gpiote_pin_t pin) @@ -481,26 +735,24 @@ void nrfx_gpiote_out_uninit(nrfx_gpiote_pin_t pin) NRFX_ASSERT(nrf_gpio_pin_present_check(pin)); NRFX_ASSERT(pin_in_use(pin)); - if (pin_in_use_by_te(pin)) - { - channel_free((uint8_t)channel_port_get(pin)); - nrf_gpiote_te_default(NRF_GPIOTE, (uint32_t)channel_port_get(pin)); - } - pin_in_use_clear(pin); + uint8_t ch = pin_in_use_by_te(pin) ? pin_te_get(pin) : 0xFF; - if (pin_configured_check(pin)) + nrfx_err_t err = nrfx_gpiote_pin_uninit(pin); + NRFX_ASSERT(err == NRFX_SUCCESS); + + if (ch != 0xFF) { - nrf_gpio_cfg_default(pin); - pin_configured_clear(pin); + nrfx_gpiote_channel_free(ch); } + + (void)err; } void nrfx_gpiote_out_set(nrfx_gpiote_pin_t pin) { NRFX_ASSERT(nrf_gpio_pin_present_check(pin)); - NRFX_ASSERT(pin_in_use(pin)); - NRFX_ASSERT(!pin_in_use_by_te(pin)); + NRFX_ASSERT(pin_is_output(pin) && !pin_in_use_by_te(pin)); nrf_gpio_pin_set(pin); } @@ -509,8 +761,7 @@ void nrfx_gpiote_out_set(nrfx_gpiote_pin_t pin) void nrfx_gpiote_out_clear(nrfx_gpiote_pin_t pin) { NRFX_ASSERT(nrf_gpio_pin_present_check(pin)); - NRFX_ASSERT(pin_in_use(pin)); - NRFX_ASSERT(!pin_in_use_by_te(pin)); + NRFX_ASSERT(pin_is_output(pin) && !pin_in_use_by_te(pin)); nrf_gpio_pin_clear(pin); } @@ -519,39 +770,36 @@ void nrfx_gpiote_out_clear(nrfx_gpiote_pin_t pin) void nrfx_gpiote_out_toggle(nrfx_gpiote_pin_t pin) { NRFX_ASSERT(nrf_gpio_pin_present_check(pin)); - NRFX_ASSERT(pin_in_use(pin)); - NRFX_ASSERT(!pin_in_use_by_te(pin)); + NRFX_ASSERT(pin_is_output(pin) && !pin_in_use_by_te(pin)); nrf_gpio_pin_toggle(pin); } - void nrfx_gpiote_out_task_enable(nrfx_gpiote_pin_t pin) { + (void)pin_is_task_output; /* Add to avoid compiler warnings when asserts disabled.*/ NRFX_ASSERT(nrf_gpio_pin_present_check(pin)); - NRFX_ASSERT(pin_in_use(pin)); - NRFX_ASSERT(pin_in_use_by_te(pin)); + NRFX_ASSERT(pin_is_task_output(pin)); - nrf_gpiote_task_enable(NRF_GPIOTE, (uint32_t)m_cb.pin_assignments[pin]); + nrf_gpiote_task_enable(NRF_GPIOTE, (uint32_t)pin_te_get(pin)); } void nrfx_gpiote_out_task_disable(nrfx_gpiote_pin_t pin) { NRFX_ASSERT(nrf_gpio_pin_present_check(pin)); - NRFX_ASSERT(pin_in_use(pin)); - NRFX_ASSERT(pin_in_use_by_te(pin)); + NRFX_ASSERT(pin_is_task_output(pin)); - nrf_gpiote_task_disable(NRF_GPIOTE, (uint32_t)m_cb.pin_assignments[pin]); + nrf_gpiote_task_disable(NRF_GPIOTE, (uint32_t)pin_te_get(pin)); } nrf_gpiote_task_t nrfx_gpiote_out_task_get(nrfx_gpiote_pin_t pin) { NRFX_ASSERT(nrf_gpio_pin_present_check(pin)); - NRFX_ASSERT(pin_in_use_by_te(pin)); + NRFX_ASSERT(pin_is_task_output(pin)); - return nrf_gpiote_out_task_get((uint8_t)channel_port_get(pin)); + return nrf_gpiote_out_task_get((uint8_t)pin_te_get(pin)); } @@ -566,9 +814,9 @@ uint32_t nrfx_gpiote_out_task_addr_get(nrfx_gpiote_pin_t pin) nrf_gpiote_task_t nrfx_gpiote_set_task_get(nrfx_gpiote_pin_t pin) { NRFX_ASSERT(nrf_gpio_pin_present_check(pin)); - NRFX_ASSERT(pin_in_use_by_te(pin)); + NRFX_ASSERT(pin_is_task_output(pin)); - return nrf_gpiote_set_task_get((uint8_t)channel_port_get(pin)); + return nrf_gpiote_set_task_get((uint8_t)pin_te_get(pin)); } @@ -584,9 +832,9 @@ uint32_t nrfx_gpiote_set_task_addr_get(nrfx_gpiote_pin_t pin) nrf_gpiote_task_t nrfx_gpiote_clr_task_get(nrfx_gpiote_pin_t pin) { NRFX_ASSERT(nrf_gpio_pin_present_check(pin)); - NRFX_ASSERT(pin_in_use_by_te(pin)); + NRFX_ASSERT(pin_is_task_output(pin)); - return nrf_gpiote_clr_task_get((uint8_t)channel_port_get(pin)); + return nrf_gpiote_clr_task_get((uint8_t)pin_te_get(pin)); } @@ -601,22 +849,20 @@ uint32_t nrfx_gpiote_clr_task_addr_get(nrfx_gpiote_pin_t pin) void nrfx_gpiote_out_task_force(nrfx_gpiote_pin_t pin, uint8_t state) { NRFX_ASSERT(nrf_gpio_pin_present_check(pin)); - NRFX_ASSERT(pin_in_use(pin)); - NRFX_ASSERT(pin_in_use_by_te(pin)); + NRFX_ASSERT(pin_is_task_output(pin)); nrf_gpiote_outinit_t init_val = state ? NRF_GPIOTE_INITIAL_VALUE_HIGH : NRF_GPIOTE_INITIAL_VALUE_LOW; - nrf_gpiote_task_force(NRF_GPIOTE, (uint32_t)m_cb.pin_assignments[pin], init_val); + nrf_gpiote_task_force(NRF_GPIOTE, (uint32_t)pin_te_get(pin), init_val); } void nrfx_gpiote_out_task_trigger(nrfx_gpiote_pin_t pin) { NRFX_ASSERT(nrf_gpio_pin_present_check(pin)); - NRFX_ASSERT(pin_in_use(pin)); - NRFX_ASSERT(pin_in_use_by_te(pin)); + NRFX_ASSERT(pin_is_task_output(pin)); - nrf_gpiote_task_t task = nrf_gpiote_out_task_get((uint8_t)channel_port_get(pin)); + nrf_gpiote_task_t task = nrf_gpiote_out_task_get((uint8_t)pin_te_get(pin)); nrf_gpiote_task_trigger(NRF_GPIOTE, task); } @@ -628,7 +874,7 @@ void nrfx_gpiote_set_task_trigger(nrfx_gpiote_pin_t pin) NRFX_ASSERT(pin_in_use(pin)); NRFX_ASSERT(pin_in_use_by_te(pin)); - nrf_gpiote_task_t task = nrf_gpiote_set_task_get((uint8_t)channel_port_get(pin)); + nrf_gpiote_task_t task = nrf_gpiote_set_task_get((uint8_t)pin_te_get(pin)); nrf_gpiote_task_trigger(NRF_GPIOTE, task); } @@ -642,94 +888,49 @@ void nrfx_gpiote_clr_task_trigger(nrfx_gpiote_pin_t pin) NRFX_ASSERT(pin_in_use(pin)); NRFX_ASSERT(pin_in_use_by_te(pin)); - nrf_gpiote_task_t task = nrf_gpiote_clr_task_get((uint8_t)channel_port_get(pin)); + nrf_gpiote_task_t task = nrf_gpiote_clr_task_get((uint8_t)pin_te_get(pin)); nrf_gpiote_task_trigger(NRF_GPIOTE, task); } #endif // defined(GPIOTE_FEATURE_CLR_PRESENT) -static nrfx_err_t gpiote_in_init(nrfx_gpiote_pin_t pin, - nrfx_gpiote_in_config_t const * p_config, - nrfx_gpiote_evt_handler_t evt_handler, - bool prealloc, - uint8_t channel) -{ - NRFX_ASSERT(nrf_gpio_pin_present_check(pin)); - NRFX_ASSERT(m_cb.state == NRFX_DRV_STATE_INITIALIZED); - NRFX_ASSERT(p_config); - nrfx_err_t err_code = NRFX_SUCCESS; - - if (prealloc && !p_config->hi_accuracy) - { - return NRFX_ERROR_INVALID_PARAM; - } +nrfx_err_t nrfx_gpiote_in_init(nrfx_gpiote_pin_t pin, + nrfx_gpiote_in_config_t const * p_config, + nrfx_gpiote_evt_handler_t evt_handler) +{ + uint8_t ch; + nrfx_err_t err; - /* Only one GPIOTE channel can be assigned to one physical pin. */ - if (pin_in_use_by_gpiote(pin)) + if (p_config->hi_accuracy) { - err_code = NRFX_ERROR_BUSY; + err = nrfx_gpiote_channel_alloc(&ch); + if (err != NRFX_SUCCESS) + { + return err; + } } else { - int8_t ch = NO_CHANNELS; - - if (prealloc) - { - ch = channel; - } - else - { - ch = accuracy_channel_alloc(p_config->hi_accuracy); - } - - if (ch != NO_CHANNELS) - { - pin_in_use_by_te_set(pin, ch, evt_handler, p_config->hi_accuracy); - - if (!p_config->skip_gpio_setup) - { - if (p_config->is_watcher) - { - nrf_gpio_cfg_watcher(pin); - } - else - { - nrf_gpio_cfg_input(pin, p_config->pull); - } - pin_configured_set(pin); - } + /* Value will not be used. */ + ch = 0xFF; + } - if (p_config->hi_accuracy) - { - nrf_gpiote_event_configure(NRF_GPIOTE, (uint32_t)ch, pin, p_config->sense); - } - else - { - m_cb.port_handlers_pins[ch - GPIOTE_CH_NUM] |= (p_config->sense) << - POLARITY_FIELD_POS; - } - } - else - { - err_code = NRFX_ERROR_NO_MEM; - } + err = nrfx_gpiote_in_prealloc_init(pin, p_config, ch, evt_handler); + if ((err == NRFX_ERROR_NO_MEM) && p_config->hi_accuracy) + { + nrfx_gpiote_channel_free(ch); } - return err_code; + return err; } -nrfx_err_t nrfx_gpiote_in_init(nrfx_gpiote_pin_t pin, - nrfx_gpiote_in_config_t const * p_config, - nrfx_gpiote_evt_handler_t evt_handler) +static void legacy_handler(nrfx_gpiote_pin_t pin, nrfx_gpiote_trigger_t trigger, void * p_context) { - nrfx_err_t err_code; - - err_code = gpiote_in_init(pin, p_config, evt_handler, false, 0); + NRFX_ASSERT(trigger <= NRFX_GPIOTE_TRIGGER_TOGGLE); - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; + ((nrfx_gpiote_evt_handler_t)p_context)(pin, gpiote_trigger_to_polarity(trigger)); } nrfx_err_t nrfx_gpiote_in_prealloc_init(nrfx_gpiote_pin_t pin, @@ -737,93 +938,122 @@ nrfx_err_t nrfx_gpiote_in_prealloc_init(nrfx_gpiote_pin_t pin, uint8_t channel, nrfx_gpiote_evt_handler_t evt_handler) { - nrfx_err_t err_code; - - err_code = gpiote_in_init(pin, p_config, evt_handler, true, channel); - - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; -} - -void nrfx_gpiote_in_event_enable(nrfx_gpiote_pin_t pin, bool int_enable) -{ - NRFX_ASSERT(nrf_gpio_pin_present_check(pin)); - NRFX_ASSERT(pin_in_use_by_gpiote(pin)); - if (pin_in_use_by_port(pin)) + nrfx_err_t err; + bool skip_in_config = false; + nrfx_gpiote_input_config_t input_config; + nrfx_gpiote_trigger_config_t trigger_config = { + .trigger = gpiote_polarity_to_trigger(p_config->sense), + .p_in_channel = p_config->hi_accuracy ? &channel : NULL + }; + nrfx_gpiote_handler_config_t handler_config = { + .handler = legacy_handler, + .p_context = (void *)evt_handler + }; + + if (p_config->is_watcher) { - nrf_gpiote_polarity_t polarity = - port_handler_polarity_get(channel_port_get(pin) - GPIOTE_CH_NUM); - nrf_gpio_pin_sense_t sense; - if (polarity == NRF_GPIOTE_POLARITY_TOGGLE) - { - /* read current pin state and set for next sense to oposit */ - sense = (nrf_gpio_pin_read(pin)) ? - NRF_GPIO_PIN_SENSE_LOW : NRF_GPIO_PIN_SENSE_HIGH; - } - else + nrfx_gpiote_output_config_t output_config = { + .input_connect = NRF_GPIO_PIN_INPUT_CONNECT + }; + + skip_in_config = true; + err = nrfx_gpiote_output_configure(pin, &output_config, NULL); + if (err != NRFX_SUCCESS) { - sense = (polarity == NRF_GPIOTE_POLARITY_LOTOHI) ? - NRF_GPIO_PIN_SENSE_HIGH : NRF_GPIO_PIN_SENSE_LOW; + return err; } - nrf_gpio_cfg_sense_set(pin, sense); } - else if (pin_in_use_by_te(pin)) + else + { + input_config.pull = p_config->pull; + } + + if (p_config->skip_gpio_setup) { - int32_t channel = (int32_t)channel_port_get(pin); - nrf_gpiote_event_t event = nrf_gpiote_in_event_get((uint8_t)channel); + m_cb.pin_flags[pin] |= PIN_FLAG_SKIP_CONFIG; + skip_in_config = true; + } + + err = nrfx_gpiote_input_configure(pin, + skip_in_config ? NULL : &input_config, + &trigger_config, + &handler_config); + if (err == NRFX_SUCCESS) + { + m_cb.pin_flags[pin] |= PIN_FLAG_LEGACY_API_PIN; + } + + return err; +} + +void nrfx_gpiote_trigger_enable(nrfx_gpiote_pin_t pin, bool int_enable) +{ + NRFX_ASSERT(pin_has_trigger(pin)); - nrf_gpiote_event_enable(NRF_GPIOTE, (uint32_t)channel); + if (pin_in_use_by_te(pin) && pin_is_input(pin)) + { + uint8_t ch = pin_te_get(pin); - nrf_gpiote_event_clear(NRF_GPIOTE, event); + nrf_gpiote_event_clear(NRF_GPIOTE, nrf_gpiote_in_event_get(ch)); + nrf_gpiote_event_enable(NRF_GPIOTE, ch); if (int_enable) { - nrfx_gpiote_evt_handler_t handler = channel_handler_get((uint32_t)channel_port_get(pin)); - // Enable the interrupt only if event handler was provided. - if (handler) - { - nrf_gpiote_int_enable(NRF_GPIOTE, 1 << channel); - } + nrf_gpiote_int_enable(NRF_GPIOTE, NRFX_BIT(ch)); } } + else + { + NRFX_ASSERT(int_enable); + nrf_gpio_cfg_sense_set(pin, get_initial_sense(pin)); + } } - -void nrfx_gpiote_in_event_disable(nrfx_gpiote_pin_t pin) +void nrfx_gpiote_trigger_disable(nrfx_gpiote_pin_t pin) { - NRFX_ASSERT(nrf_gpio_pin_present_check(pin)); - NRFX_ASSERT(pin_in_use_by_gpiote(pin)); - if (pin_in_use_by_port(pin)) + if (pin_in_use_by_te(pin) && pin_is_input(pin)) { - nrf_gpio_cfg_sense_set(pin, NRF_GPIO_PIN_NOSENSE); + uint8_t ch = pin_te_get(pin); + + nrf_gpiote_int_disable(NRF_GPIOTE, NRFX_BIT(ch)); + nrf_gpiote_event_disable(NRF_GPIOTE, ch); } - else if (pin_in_use_by_te(pin)) + else { - int32_t channel = (int32_t)channel_port_get(pin); - nrf_gpiote_event_disable(NRF_GPIOTE, (uint32_t)channel); - nrf_gpiote_int_disable(NRF_GPIOTE, 1 << channel); + nrf_gpio_cfg_sense_set(pin, NRF_GPIO_PIN_NOSENSE); } } - void nrfx_gpiote_in_uninit(nrfx_gpiote_pin_t pin) { - NRFX_ASSERT(nrf_gpio_pin_present_check(pin)); - NRFX_ASSERT(pin_in_use_by_gpiote(pin)); - nrfx_gpiote_in_event_disable(pin); - if (pin_in_use_by_te(pin)) + NRFX_ASSERT(pin_in_use(pin)); + NRFX_ASSERT(pin_is_input(pin) || pin_has_trigger(pin)); + nrfx_err_t err; + uint8_t ch; + + if (!pin_in_use(pin)) { - nrf_gpiote_te_default(NRF_GPIOTE, (uint32_t)channel_port_get(pin)); + return; } - if (pin_configured_check(pin)) + + ch = pin_in_use_by_te(pin) ? pin_te_get(pin) : 0xFF; + + if (m_cb.pin_flags[pin] & PIN_FLAG_SKIP_CONFIG) { - nrf_gpio_cfg_default(pin); - pin_configured_clear(pin); + pin_handler_trigger_uninit(pin); + m_cb.pin_flags[pin] &= ~PIN_FLAG_SKIP_CONFIG; } - if (pin_in_use_by_gpiote(pin)) + else { - channel_free((uint8_t)channel_port_get(pin)); + err = nrfx_gpiote_pin_uninit(pin); + NRFX_ASSERT(err == NRFX_SUCCESS); } - pin_in_use_clear(pin); + + if (ch != 0xFF) + { + nrfx_gpiote_channel_free(ch); + } + + (void)err; } @@ -837,11 +1067,12 @@ bool nrfx_gpiote_in_is_set(nrfx_gpiote_pin_t pin) nrf_gpiote_event_t nrfx_gpiote_in_event_get(nrfx_gpiote_pin_t pin) { NRFX_ASSERT(nrf_gpio_pin_present_check(pin)); - NRFX_ASSERT(pin_in_use_by_port(pin) || pin_in_use_by_te(pin)); + NRFX_ASSERT(pin_is_input(pin)); + NRFX_ASSERT(pin_has_trigger(pin)); if (pin_in_use_by_te(pin)) { - return nrf_gpiote_in_event_get((uint8_t)channel_port_get(pin)); + return nrf_gpiote_in_event_get((uint8_t)pin_te_get(pin)); } return NRF_GPIOTE_EVENT_PORT; @@ -854,6 +1085,57 @@ uint32_t nrfx_gpiote_in_event_addr_get(nrfx_gpiote_pin_t pin) return nrf_gpiote_event_address_get(NRF_GPIOTE, event); } +static void call_handler(nrfx_gpiote_pin_t pin, nrfx_gpiote_trigger_t trigger) +{ + nrfx_gpiote_handler_config_t const * handler = channel_handler_get(pin); + + if (handler) + { + handler->handler(pin, trigger, handler->p_context); + } + if (m_cb.global_handler.handler) + { + m_cb.global_handler.handler(pin, trigger, m_cb.global_handler.p_context); + } +} + +static void next_sense_cond_call_handler(nrfx_gpiote_pin_t pin, + nrfx_gpiote_trigger_t trigger, + nrf_gpio_pin_sense_t sense) +{ + if (is_level(trigger)) + { + call_handler(pin, trigger); + if (nrf_gpio_pin_sense_get(pin) == sense) + { + /* The sensing mechanism needs to be reenabled here so that the PORT event + * is generated again for the pin if it stays at the sensed level. */ + nrf_gpio_cfg_sense_set(pin, NRF_GPIO_PIN_NOSENSE); + nrf_gpio_cfg_sense_set(pin, sense); + } + } + else + { + /* Reconfigure sense to the opposite level, so the internal PINx.DETECT signal + * can be deasserted. Therefore PORT event can be generated again, + * unless some other PINx.DETECT signal is still active. */ + nrf_gpio_pin_sense_t next_sense = (sense == NRF_GPIO_PIN_SENSE_HIGH) ? + NRF_GPIO_PIN_SENSE_LOW : NRF_GPIO_PIN_SENSE_HIGH; + + nrf_gpio_cfg_sense_set(pin, next_sense); + + /* Invoke user handler only if the sensed pin level matches its polarity + * configuration. Call handler unconditionally in case of toggle trigger or + * level trigger. */ + if ((trigger == NRFX_GPIOTE_TRIGGER_TOGGLE) || + (sense == NRF_GPIO_PIN_SENSE_HIGH && trigger == NRFX_GPIOTE_TRIGGER_LOTOHI) || + (sense == NRF_GPIO_PIN_SENSE_LOW && trigger == NRFX_GPIOTE_TRIGGER_HITOLO)) + { + call_handler(pin, trigger); + } + } +} + #if defined(NRF_GPIO_LATCH_PRESENT) static bool latch_pending_read_and_check(uint32_t * latch) { @@ -872,52 +1154,39 @@ static bool latch_pending_read_and_check(uint32_t * latch) return false; } -static void port_event_handle(uint32_t * latch) +static void port_event_handle(void) { + uint32_t latch[GPIO_COUNT]; + + nrf_gpio_latches_read_and_clear(0, GPIO_COUNT, latch); + do { - for (uint32_t i = 0; i < NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS; i++) + for (uint32_t i = 0; i < GPIO_COUNT; i++) { - if (m_cb.port_handlers_pins[i] == PIN_NOT_USED) - { - continue; - } - - /* Process pin further only if LATCH bit associated with this pin was set. */ - nrfx_gpiote_pin_t pin = port_handler_pin_get(i); - if (nrf_bitmask_bit_is_set(pin, latch)) + while (latch[i]) { - nrf_gpiote_polarity_t polarity = port_handler_polarity_get(i); - nrf_gpio_pin_sense_t sense = nrf_gpio_pin_sense_get(pin); + uint32_t pin = NRF_CTZ(latch[i]); - NRFX_LOG_DEBUG("PORT event for pin: %d, polarity: %d.", pin, polarity); + /* Convert to absolute value. */ + pin += 32 * i; + nrf_gpio_pin_sense_t sense; + nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]); - /* Reconfigure sense to the opposite level, so the internal PINx.DETECT signal - * can be deasserted. Therefore PORT event generated again, - * unless some other PINx.DETECT signal is still active. */ - nrf_gpio_pin_sense_t next_sense = - (sense == NRF_GPIO_PIN_SENSE_HIGH) ? NRF_GPIO_PIN_SENSE_LOW : - NRF_GPIO_PIN_SENSE_HIGH; - nrf_gpio_cfg_sense_set(pin, next_sense); + nrf_bitmask_bit_clear(pin, latch); + sense = nrf_gpio_pin_sense_get(pin); + next_sense_cond_call_handler(pin, trigger, sense); /* Try to clear LATCH bit corresponding to currently processed pin. * This may not succeed if the pin's state changed during the interrupt processing * and now it matches the new sense configuration. In such case, * the pin will be processed again in another iteration of the outer loop. */ nrf_gpio_pin_latch_clear(pin); - - /* Invoke user handler only if the sensed pin level - * matches its polarity configuration. */ - nrfx_gpiote_evt_handler_t handler = - channel_handler_get((uint32_t)channel_port_get(pin)); - if (handler && - ((polarity == NRF_GPIOTE_POLARITY_TOGGLE) || - (sense == NRF_GPIO_PIN_SENSE_HIGH && polarity == NRF_GPIOTE_POLARITY_LOTOHI) || - (sense == NRF_GPIO_PIN_SENSE_LOW && polarity == NRF_GPIOTE_POLARITY_HITOLO))) - { - handler(pin, polarity); - } - } + } } + + /* All pins have been handled, clear PORT, check latch again in case + * something came between deciding to exit and clearing PORT event. */ + nrf_gpiote_event_clear(NRF_GPIOTE, NRF_GPIOTE_EVENT_PORT); } while (latch_pending_read_and_check(latch)); } @@ -940,7 +1209,7 @@ static bool input_read_and_check(uint32_t * input, uint32_t * pins_to_check) { /* If any differences among inputs were found, mark those pins * to be processed again. */ - pins_to_check[port_idx] = input_diff; + pins_to_check[port_idx] &= input_diff; process_inputs_again = true; } else @@ -951,73 +1220,107 @@ static bool input_read_and_check(uint32_t * input, uint32_t * pins_to_check) return process_inputs_again; } -static void port_event_handle(uint32_t * input) +static void port_event_handle(void) { uint32_t pins_to_check[GPIO_COUNT]; + uint32_t input[GPIO_COUNT] = {0}; + uint8_t rel_pin; + uint8_t pin; + nrfx_gpiote_trigger_t trigger; + + nrf_gpio_ports_read(0, GPIO_COUNT, input); for (uint32_t port_idx = 0; port_idx < GPIO_COUNT; port_idx++) { - pins_to_check[port_idx] = 0xFFFFFFFF; + pins_to_check[port_idx] = m_cb.port_pins[port_idx]; } do { - for (uint32_t i = 0; i < NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS; i++) + for (uint32_t i = 0; i < GPIO_COUNT; i++) { - if (m_cb.port_handlers_pins[i] == PIN_NOT_USED) + while (pins_to_check[i]) { - continue; - } + nrf_gpio_pin_sense_t sense; + bool pin_state; - nrfx_gpiote_pin_t pin = port_handler_pin_get(i); - if (nrf_bitmask_bit_is_set(pin, pins_to_check)) - { - nrf_gpiote_polarity_t polarity = port_handler_polarity_get(i); - nrf_gpio_pin_sense_t sense = nrf_gpio_pin_sense_get(pin); - bool pin_state = nrf_bitmask_bit_is_set(pin, input); + rel_pin = NRF_CTZ(pins_to_check[i]); + pins_to_check[i] &= ~NRFX_BIT(rel_pin); + /* Absolute */ + pin = rel_pin + 32 * i; + + trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]); + sense = nrf_gpio_pin_sense_get(pin); + pin_state = nrf_bitmask_bit_is_set(pin, input); /* Process pin further only if its state matches its sense level. */ if ((pin_state && (sense == NRF_GPIO_PIN_SENSE_HIGH)) || (!pin_state && (sense == NRF_GPIO_PIN_SENSE_LOW)) ) { - /* Reconfigure sense to the opposite level, so the internal PINx.DETECT signal - * can be deasserted. Therefore PORT event can be generated again, - * unless some other PINx.DETECT signal is still active. */ - NRFX_LOG_DEBUG("PORT event for pin: %d, polarity: %d.", pin, polarity); - nrf_gpio_pin_sense_t next_sense = - (sense == NRF_GPIO_PIN_SENSE_HIGH) ? NRF_GPIO_PIN_SENSE_LOW : - NRF_GPIO_PIN_SENSE_HIGH; - nrf_gpio_cfg_sense_set(pin, next_sense); - - /* Invoke user handler only if the sensed pin level - * matches its polarity configuration. */ - nrfx_gpiote_evt_handler_t handler = - channel_handler_get((uint32_t)channel_port_get(pin)); - if (handler && - ((polarity == NRF_GPIOTE_POLARITY_TOGGLE) || - (sense == NRF_GPIO_PIN_SENSE_HIGH && - polarity == NRF_GPIOTE_POLARITY_LOTOHI) || - (sense == NRF_GPIO_PIN_SENSE_LOW && - polarity == NRF_GPIOTE_POLARITY_HITOLO))) + next_sense_cond_call_handler(pin, trigger, sense); + } + } + } + + /* All pins used with PORT must be rechecked because it's content and + * number of port pins may have changed during handler execution. */ + for (uint32_t port_idx = 0; port_idx < GPIO_COUNT; port_idx++) + { + pins_to_check[port_idx] = m_cb.port_pins[port_idx]; + } + + /* Small trick to continue check if input level is equal to the trigger: + * Set input to the opposite level. If input equals trigger level that + * it will be set in pins_to_check. */ + for (uint32_t i = 0; i < GPIO_COUNT; i++) + { + uint32_t pin_mask = pins_to_check[i]; + + while (pin_mask) + { + rel_pin = NRF_CTZ(pin_mask); + pin_mask &= ~NRFX_BIT(rel_pin); + pin = rel_pin + 32 * i; + if (nrf_gpio_pin_sense_get(pin) != NRF_GPIO_PIN_NOSENSE) + { + trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]); + if (trigger == NRFX_GPIOTE_TRIGGER_HIGH) + { + input[i] &= ~NRFX_BIT(rel_pin); + } + else if (trigger == NRFX_GPIOTE_TRIGGER_LOW) { - handler(pin, polarity); + input[i] |= NRFX_BIT(rel_pin); } } } } + + nrf_gpiote_event_clear(NRF_GPIOTE, NRF_GPIOTE_EVENT_PORT); } while (input_read_and_check(input, pins_to_check)); } #endif // defined(NRF_GPIO_LATCH_PRESENT) -void nrfx_gpiote_irq_handler(void) +static void gpiote_evt_handle(uint32_t mask) { - uint32_t status = 0; - uint32_t input[GPIO_COUNT] = {0}; + while (mask) + { + uint32_t ch = NRF_CTZ(mask); + mask &= ~NRFX_BIT(ch); + nrfx_gpiote_pin_t pin = nrf_gpiote_event_pin_get(NRF_GPIOTE, ch); + nrf_gpiote_polarity_t polarity = nrf_gpiote_event_polarity_get(NRF_GPIOTE, ch); - /* collect status of all GPIOTE pin events. Processing is done once all are collected and cleared.*/ - uint32_t i; + call_handler(pin, gpiote_polarity_to_trigger(polarity)); + } +} + +void nrfx_gpiote_irq_handler(void) +{ + uint32_t status = 0; + uint32_t i; nrf_gpiote_event_t event = NRF_GPIOTE_EVENT_IN_0; - uint32_t mask = (uint32_t)NRF_GPIOTE_INT_IN0_MASK; + uint32_t mask = (uint32_t)NRF_GPIOTE_INT_IN0_MASK; + /* collect status of all GPIOTE pin events. Processing is done once all are collected and cleared.*/ for (i = 0; i < GPIOTE_CH_NUM; i++) { if (nrf_gpiote_event_check(NRF_GPIOTE, event) && @@ -1032,47 +1335,14 @@ void nrfx_gpiote_irq_handler(void) event = (nrf_gpiote_event_t)((uint32_t)event + sizeof(uint32_t)); } - /* collect PORT status event, if event is set read pins state. Processing is postponed to the - * end of interrupt. */ + /* handle PORT event */ if (nrf_gpiote_event_check(NRF_GPIOTE, NRF_GPIOTE_EVENT_PORT)) { - nrf_gpiote_event_clear(NRF_GPIOTE, NRF_GPIOTE_EVENT_PORT); - status |= (uint32_t)NRF_GPIOTE_INT_PORT_MASK; -#if defined(NRF_GPIO_LATCH_PRESENT) - nrf_gpio_latches_read_and_clear(0, GPIO_COUNT, input); -#else - nrf_gpio_ports_read(0, GPIO_COUNT, input); -#endif + port_event_handle(); } /* Process pin events. */ - if (status & NRF_GPIOTE_INT_IN_MASK) - { - mask = (uint32_t)NRF_GPIOTE_INT_IN0_MASK; - - for (i = 0; i < GPIOTE_CH_NUM; i++) - { - if (mask & status) - { - nrfx_gpiote_pin_t pin = nrf_gpiote_event_pin_get(NRF_GPIOTE, i); - NRFX_LOG_DEBUG("Event in number: %d.", i); - nrf_gpiote_polarity_t polarity = nrf_gpiote_event_polarity_get(NRF_GPIOTE, i); - nrfx_gpiote_evt_handler_t handler = channel_handler_get(i); - NRFX_LOG_DEBUG("Pin: %d, polarity: %d.", pin, polarity); - if (handler) - { - handler(pin, polarity); - } - } - mask <<= 1; - } - } - - /* Process PORT event. */ - if (status & (uint32_t)NRF_GPIOTE_INT_PORT_MASK) - { - port_event_handle(input); - } + gpiote_evt_handle(status); } #endif // NRFX_CHECK(NRFX_GPIOTE_ENABLED) diff --git a/drivers/src/nrfx_ipc.c b/drivers/src/nrfx_ipc.c index c6b91545e5..938038abcd 100644 --- a/drivers/src/nrfx_ipc.c +++ b/drivers/src/nrfx_ipc.c @@ -152,7 +152,7 @@ void nrfx_ipc_irq_handler(void) uint32_t bitmask = events_map; while (bitmask) { - uint8_t event_idx = __CLZ(__RBIT(bitmask)); + uint8_t event_idx = NRF_CTZ(bitmask); bitmask &= ~(1UL << event_idx); nrf_ipc_event_clear(NRF_IPC, nrf_ipc_receive_event_get(event_idx)); } diff --git a/drivers/src/nrfx_nfct.c b/drivers/src/nrfx_nfct.c index c31062096e..31abade567 100644 --- a/drivers/src/nrfx_nfct.c +++ b/drivers/src/nrfx_nfct.c @@ -513,21 +513,47 @@ nrfx_err_t nrfx_nfct_tx(nrfx_nfct_data_desc_t const * p_tx_data, NRFX_ASSERT(p_tx_data); NRFX_ASSERT(p_tx_data->p_data); + nrfx_err_t err = NRFX_SUCCESS; + if (p_tx_data->data_size == 0) { return NRFX_ERROR_INVALID_LENGTH; } - nrf_nfct_rxtx_buffer_set(NRF_NFCT, (uint8_t *) p_tx_data->p_data, p_tx_data->data_size); - nrf_nfct_tx_bits_set(NRF_NFCT, NRFX_NFCT_BYTES_TO_BITS(p_tx_data->data_size)); - nrf_nfct_frame_delay_mode_set(NRF_NFCT, (nrf_nfct_frame_delay_mode_t) delay_mode); - nrfx_nfct_frame_delay_max_set(false); + NRFX_CRITICAL_SECTION_ENTER(); + + /* In case when NFC frame transmission has already started, it returns an error. */ + if (NRFX_NFCT_EVT_ACTIVE(TXFRAMESTART)) + { + err = NRFX_ERROR_BUSY; + } + else + { + /* In case when Tx operation was scheduled with delay, stop scheduled Tx operation. */ +#if defined(NRF52_SERIES) + *(volatile uint32_t *)0x40005010 = 0x01; +#elif defined(NRF5340_XXAA_APPLICATION) && defined(NRF_TRUSTZONE_NONSECURE) + *(volatile uint32_t *)0x4002D010 = 0x01; +#elif defined(NRF5340_XXAA_APPLICATION) + *(volatile uint32_t *)0x5002D010 = 0x01; +#endif + nrf_nfct_rxtx_buffer_set(NRF_NFCT, (uint8_t *) p_tx_data->p_data, p_tx_data->data_size); + nrf_nfct_tx_bits_set(NRF_NFCT, NRFX_NFCT_BYTES_TO_BITS(p_tx_data->data_size)); + nrf_nfct_frame_delay_mode_set(NRF_NFCT, (nrf_nfct_frame_delay_mode_t) delay_mode); + nrfx_nfct_frame_delay_max_set(false); - nrfx_nfct_rxtx_int_enable(NRFX_NFCT_TX_INT_MASK); - nrf_nfct_task_trigger(NRF_NFCT, NRF_NFCT_TASK_STARTTX); + nrfx_nfct_rxtx_int_enable(NRFX_NFCT_TX_INT_MASK); + nrf_nfct_task_trigger(NRF_NFCT, NRF_NFCT_TASK_STARTTX); + } - NRFX_LOG_INFO("Tx start"); - return NRFX_SUCCESS; + NRFX_CRITICAL_SECTION_EXIT(); + + if (err == NRFX_SUCCESS) + { + NRFX_LOG_INFO("Tx start"); + } + + return err; } void nrfx_nfct_state_force(nrfx_nfct_state_t state) diff --git a/drivers/src/nrfx_ppi.c b/drivers/src/nrfx_ppi.c index 547b9c6025..fc87cca265 100644 --- a/drivers/src/nrfx_ppi.c +++ b/drivers/src/nrfx_ppi.c @@ -36,13 +36,16 @@ #if NRFX_CHECK(NRFX_PPI_ENABLED) #include +#include #define NRFX_LOG_MODULE PPI #include +/** @brief Bitmask representing channels availability. */ +static nrfx_atomic_t m_channels_allocated = NRFX_PPI_PROG_APP_CHANNELS_MASK; -static uint32_t m_channels_allocated; /**< Bitmap representing channels availability. 1 when a channel is allocated, 0 otherwise. */ -static uint8_t m_groups_allocated; /**< Bitmap representing groups availability. 1 when a group is allocated, 0 otherwise.*/ +/** @brief Bitmask representing groups availability. */ +static nrfx_atomic_t m_groups_allocated = NRFX_PPI_ALL_APP_GROUPS_MASK; /** @@ -115,96 +118,6 @@ static bool is_app_group(nrf_ppi_channel_group_t group) } -/** - * @brief Check whether a channel is allocated. - * - * @param[in] channel_num Channel number to check. - * - * @retval true The channel is allocated. - * @retval false The channel is not allocated. - */ -static bool is_allocated_channel(nrf_ppi_channel_t channel) -{ - return ((m_channels_allocated & nrfx_ppi_channel_to_mask(channel)) != 0); -} - - -/** - * @brief Set channel allocated indication. - * - * @param[in] channel_num Specifies the channel to set the "allocated" indication. - */ -static void channel_allocated_set(nrf_ppi_channel_t channel) -{ - m_channels_allocated |= nrfx_ppi_channel_to_mask(channel); -} - - -/** - * @brief Clear channel allocated indication. - * - * @param[in] channel_num Specifies the channel to clear the "allocated" indication. - */ -static void channel_allocated_clr(nrf_ppi_channel_t channel) -{ - m_channels_allocated &= ~nrfx_ppi_channel_to_mask(channel); -} - - -/** - * @brief Clear all allocated channels. - */ -static void channel_allocated_clr_all(void) -{ - m_channels_allocated &= ~NRFX_PPI_ALL_APP_CHANNELS_MASK; -} - - -/** - * @brief Check whether a group is allocated. - * - * @param[in] group_num Group number to check. - * - * @retval true The group is allocated. - * false The group is not allocated. - */ -static bool is_allocated_group(nrf_ppi_channel_group_t group) -{ - return ((m_groups_allocated & group_to_mask(group)) != 0); -} - - -/** - * @brief Set group allocated indication. - * - * @param[in] group_num Specifies the group to set the "allocated" indication. - */ -static void group_allocated_set(nrf_ppi_channel_group_t group) -{ - m_groups_allocated |= group_to_mask(group); -} - - -/** - * @brief Clear group allocated indication. - * - * @param[in] group_num Specifies the group to clear the "allocated" indication. - */ -static void group_allocated_clr(nrf_ppi_channel_group_t group) -{ - m_groups_allocated &= ~group_to_mask(group); -} - - -/** - * @brief Clear all allocated groups. - */ -static void group_allocated_clr_all() -{ - m_groups_allocated &= ~NRFX_PPI_ALL_APP_GROUPS_MASK; -} - - void nrfx_ppi_free_all(void) { uint32_t mask = NRFX_PPI_ALL_APP_GROUPS_MASK; @@ -221,58 +134,27 @@ void nrfx_ppi_free_all(void) } mask &= ~group_to_mask(group); } - channel_allocated_clr_all(); - group_allocated_clr_all(); + nrfx_flag32_init(&m_channels_allocated, NRFX_PPI_PROG_APP_CHANNELS_MASK); + nrfx_flag32_init(&m_groups_allocated, NRFX_PPI_ALL_APP_GROUPS_MASK); } nrfx_err_t nrfx_ppi_channel_alloc(nrf_ppi_channel_t * p_channel) { - nrfx_err_t err_code = NRFX_ERROR_NO_MEM; - uint32_t mask = NRFX_PPI_PROG_APP_CHANNELS_MASK; - - for (uint8_t ch_idx = NRF_PPI_CHANNEL0; mask != 0; ch_idx++) - { - nrf_ppi_channel_t channel = (nrf_ppi_channel_t)ch_idx; - NRFX_CRITICAL_SECTION_ENTER(); - if ((mask & nrfx_ppi_channel_to_mask(channel)) && (!is_allocated_channel(channel))) - { - channel_allocated_set(channel); - *p_channel = channel; - err_code = NRFX_SUCCESS; - } - NRFX_CRITICAL_SECTION_EXIT(); - if (err_code == NRFX_SUCCESS) - { - NRFX_LOG_INFO("Allocated channel: %d.", channel); - break; - } - mask &= ~nrfx_ppi_channel_to_mask(channel); - } - - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; + return nrfx_flag32_alloc(&m_channels_allocated, (uint8_t *)p_channel); } nrfx_err_t nrfx_ppi_channel_free(nrf_ppi_channel_t channel) { - nrfx_err_t err_code = NRFX_SUCCESS; - if (!is_programmable_app_channel(channel)) { - err_code = NRFX_ERROR_INVALID_PARAM; + return NRFX_ERROR_INVALID_PARAM; } - else - { - // First disable this channel - nrf_ppi_channel_disable(NRF_PPI, channel); - NRFX_CRITICAL_SECTION_ENTER(); - channel_allocated_clr(channel); - NRFX_CRITICAL_SECTION_EXIT(); - } - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; + + nrf_ppi_channel_disable(NRF_PPI, channel); + + return nrfx_flag32_free(&m_channels_allocated, channel); } @@ -289,7 +171,7 @@ nrfx_err_t nrfx_ppi_channel_assign(nrf_ppi_channel_t channel, uint32_t eep, uint { err_code = NRFX_ERROR_INVALID_PARAM; } - else if (!is_allocated_channel(channel)) + else if (!nrfx_flag32_is_allocated(m_channels_allocated, channel)) { err_code = NRFX_ERROR_INVALID_STATE; } @@ -309,7 +191,7 @@ nrfx_err_t nrfx_ppi_channel_fork_assign(nrf_ppi_channel_t channel, uint32_t fork { nrfx_err_t err_code = NRFX_SUCCESS; #ifdef PPI_FEATURE_FORKS_PRESENT - if (!is_allocated_channel(channel)) + if (!nrfx_flag32_is_allocated(m_channels_allocated, channel)) { err_code = NRFX_ERROR_INVALID_STATE; } @@ -340,7 +222,8 @@ nrfx_err_t nrfx_ppi_channel_enable(nrf_ppi_channel_t channel) { err_code = NRFX_ERROR_INVALID_PARAM; } - else if (is_programmable_app_channel(channel) && !is_allocated_channel(channel)) + else if (is_programmable_app_channel(channel) && + !nrfx_flag32_is_allocated(m_channels_allocated, channel)) { err_code = NRFX_ERROR_INVALID_STATE; } @@ -361,7 +244,8 @@ nrfx_err_t nrfx_ppi_channel_disable(nrf_ppi_channel_t channel) { err_code = NRFX_ERROR_INVALID_PARAM; } - else if (is_programmable_app_channel(channel) && !is_allocated_channel(channel)) + else if (is_programmable_app_channel(channel) && + !nrfx_flag32_is_allocated(m_channels_allocated, channel)) { err_code = NRFX_ERROR_INVALID_STATE; } @@ -377,55 +261,14 @@ nrfx_err_t nrfx_ppi_channel_disable(nrf_ppi_channel_t channel) nrfx_err_t nrfx_ppi_group_alloc(nrf_ppi_channel_group_t * p_group) { - nrfx_err_t err_code = NRFX_ERROR_NO_MEM; - uint32_t mask = NRFX_PPI_ALL_APP_GROUPS_MASK; - - for (uint8_t group_idx = NRF_PPI_CHANNEL_GROUP0; mask != 0; group_idx++) - { - nrf_ppi_channel_group_t group = (nrf_ppi_channel_group_t)group_idx; - NRFX_CRITICAL_SECTION_ENTER(); - if ((mask & group_to_mask(group)) && (!is_allocated_group(group))) - { - group_allocated_set(group); - *p_group = group; - err_code = NRFX_SUCCESS; - } - NRFX_CRITICAL_SECTION_EXIT(); - if (err_code == NRFX_SUCCESS) - { - NRFX_LOG_INFO("Allocated group: %d.", group); - break; - } - - mask &= ~group_to_mask(group); - } - - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; + return nrfx_flag32_alloc(&m_groups_allocated, (uint8_t *)p_group); } nrfx_err_t nrfx_ppi_group_free(nrf_ppi_channel_group_t group) { - nrfx_err_t err_code = NRFX_SUCCESS; - - if (!is_app_group(group)) - { - err_code = NRFX_ERROR_INVALID_PARAM; - } - if (!is_allocated_group(group)) - { - err_code = NRFX_ERROR_INVALID_STATE; - } - else - { - nrf_ppi_group_disable(NRF_PPI, group); - NRFX_CRITICAL_SECTION_ENTER(); - group_allocated_clr(group); - NRFX_CRITICAL_SECTION_EXIT(); - } - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; + nrf_ppi_group_disable(NRF_PPI, group); + return nrfx_flag32_free(&m_groups_allocated, group); } @@ -437,7 +280,7 @@ nrfx_err_t nrfx_ppi_group_enable(nrf_ppi_channel_group_t group) { err_code = NRFX_ERROR_INVALID_PARAM; } - else if (!is_allocated_group(group)) + else if (!nrfx_flag32_is_allocated(m_groups_allocated, group)) { err_code = NRFX_ERROR_INVALID_STATE; } @@ -475,7 +318,7 @@ nrfx_err_t nrfx_ppi_channels_remove_from_group(uint32_t channel_m { err_code = NRFX_ERROR_INVALID_PARAM; } - else if (!is_allocated_group(group)) + else if (!nrfx_flag32_is_allocated(m_groups_allocated, group)) { err_code = NRFX_ERROR_INVALID_STATE; } @@ -502,7 +345,7 @@ nrfx_err_t nrfx_ppi_channels_include_in_group(uint32_t channel_ma { err_code = NRFX_ERROR_INVALID_PARAM; } - else if (!is_allocated_group(group)) + else if (!nrfx_flag32_is_allocated(m_groups_allocated, group)) { err_code = NRFX_ERROR_INVALID_STATE; } diff --git a/drivers/src/nrfx_qdec.c b/drivers/src/nrfx_qdec.c index 40b152d79b..19789eece1 100644 --- a/drivers/src/nrfx_qdec.c +++ b/drivers/src/nrfx_qdec.c @@ -118,7 +118,6 @@ nrfx_err_t nrfx_qdec_init(nrfx_qdec_config_t const * p_config, nrf_qdec_ledpol_set(NRF_QDEC, p_config->ledpol); } nrf_qdec_pins_set(NRF_QDEC, p_config->psela, p_config->pselb, p_config->pselled); - nrf_qdec_shorts_enable(NRF_QDEC, NRF_QDEC_SHORT_REPORTRDY_READCLRACC_MASK); if (p_config->dbfen) { @@ -133,6 +132,7 @@ nrfx_err_t nrfx_qdec_init(nrfx_qdec_config_t const * p_config, if (p_config->reportper != NRF_QDEC_REPORTPER_DISABLED) { + nrf_qdec_shorts_enable(NRF_QDEC, NRF_QDEC_SHORT_REPORTRDY_READCLRACC_MASK); nrf_qdec_reportper_set(NRF_QDEC, p_config->reportper); int_mask |= NRF_QDEC_INT_REPORTRDY_MASK; } @@ -159,6 +159,8 @@ void nrfx_qdec_uninit(void) nrfx_qdec_disable(); NRFX_IRQ_DISABLE(nrfx_get_irq_number(NRF_QDEC)); + nrf_qdec_shorts_disable(NRF_QDEC, NRF_QDEC_SHORT_REPORTRDY_READCLRACC_MASK); + nrf_gpio_cfg_default(nrf_qdec_phase_a_pin_get(NRF_QDEC)); nrf_gpio_cfg_default(nrf_qdec_phase_b_pin_get(NRF_QDEC)); diff --git a/drivers/src/nrfx_qspi.c b/drivers/src/nrfx_qspi.c index cc49196ab2..23877acc0d 100644 --- a/drivers/src/nrfx_qspi.c +++ b/drivers/src/nrfx_qspi.c @@ -298,6 +298,7 @@ nrfx_err_t nrfx_qspi_init(nrfx_qspi_config_t const * p_config, } m_cb.p_buffer_primary = NULL; + m_cb.p_buffer_secondary = NULL; m_cb.state = NRFX_QSPI_STATE_IDLE; nrf_qspi_enable(NRF_QSPI); @@ -330,6 +331,10 @@ nrfx_err_t nrfx_qspi_cinstr_xfer(nrf_qspi_cinstr_conf_t const * p_config, nrf_qspi_cinstrdata_set(NRF_QSPI, p_config->length, p_tx_buffer); } + /* For custom instruction transfer driver has to switch to blocking mode. + * If driver was previously configured to non-blocking mode, interrupts + * will get reenabled before next standard transfer. + */ nrf_qspi_int_disable(NRF_QSPI, NRF_QSPI_INT_READY_MASK); nrf_qspi_cinstr_transfer_start(NRF_QSPI, p_config); @@ -372,6 +377,12 @@ nrfx_err_t nrfx_qspi_lfm_start(nrf_qspi_cinstr_conf_t const * p_config) return NRFX_ERROR_BUSY; } + /* For transferring arbitrary byte length custom instructions driver has to switch to + * blocking mode. If driver was previously configured to non-blocking mode, interrupts + * will get reenabled before next standard transfer. + */ + nrf_qspi_int_disable(NRF_QSPI, NRF_QSPI_INT_READY_MASK); + nrf_qspi_cinstr_long_transfer_start(NRF_QSPI, p_config); if (qspi_ready_wait() == NRFX_ERROR_TIMEOUT) diff --git a/drivers/src/nrfx_saadc.c b/drivers/src/nrfx_saadc.c index c80612c131..45090bb9dc 100644 --- a/drivers/src/nrfx_saadc.c +++ b/drivers/src/nrfx_saadc.c @@ -163,7 +163,7 @@ static void saadc_channels_deconfig(uint32_t channel_mask) { while (channel_mask) { - uint8_t channel = __CLZ(__RBIT(channel_mask)); + uint8_t channel = NRF_CTZ(channel_mask); channel_mask &= ~(1 << channel); m_cb.channels_configured &= ~(1 << channel); @@ -837,7 +837,7 @@ static void saadc_event_limits_handle(uint8_t limits_activated, nrf_saadc_limit_ { while (limits_activated) { - uint8_t channel = __CLZ(__RBIT((uint32_t)limits_activated)); + uint8_t channel = NRF_CTZ((uint32_t)limits_activated); limits_activated &= ~(1 << channel); nrf_saadc_event_t event = nrf_saadc_limit_event_get(channel, limit_type); diff --git a/drivers/src/nrfx_usbd.c b/drivers/src/nrfx_usbd.c index 60e952ce48..4dcc0bc825 100644 --- a/drivers/src/nrfx_usbd.c +++ b/drivers/src/nrfx_usbd.c @@ -848,7 +848,7 @@ static void usbd_ep_abort_all(void) uint32_t ep_waiting = m_ep_dma_waiting | (m_ep_ready & NRFX_USBD_EPOUT_BIT_MASK); while (0 != ep_waiting) { - uint8_t bitpos = __CLZ(__RBIT(ep_waiting)); + uint8_t bitpos = NRF_CTZ(ep_waiting); if (!NRF_USBD_EPISO_CHECK(bit2ep(bitpos))) { usbd_ep_abort(bit2ep(bitpos)); @@ -1282,7 +1282,7 @@ static void ev_epdata_handler(void) /* All finished endpoint have to be marked as busy */ while (dataepstatus) { - uint8_t bitpos = __CLZ(__RBIT(dataepstatus)); + uint8_t bitpos = NRF_CTZ(dataepstatus); nrfx_usbd_ep_t ep = bit2ep(bitpos); dataepstatus &= ~(1UL << bitpos); @@ -1311,7 +1311,7 @@ static void ev_epdata_handler(void) static uint8_t usbd_dma_scheduler_algorithm(uint32_t req) { /* Only prioritized scheduling mode is supported. */ - return __CLZ(__RBIT(req)); + return NRF_CTZ(req); } /** @@ -1628,7 +1628,7 @@ void nrfx_usbd_irq_handler(void) /* Check all enabled interrupts */ while (to_process) { - uint8_t event_nr = __CLZ(__RBIT(to_process)); + uint8_t event_nr = NRF_CTZ(to_process); if (nrf_usbd_event_get_and_clear(NRF_USBD, (nrf_usbd_event_t)nrfx_bitpos_to_event(event_nr))) { @@ -1643,7 +1643,7 @@ void nrfx_usbd_irq_handler(void) while (active) { - uint8_t event_nr = __CLZ(__RBIT(active)); + uint8_t event_nr = NRF_CTZ(active); m_isr[event_nr](); active &= ~(1UL << event_nr); } diff --git a/drivers/src/nrfx_usbreg.c b/drivers/src/nrfx_usbreg.c index 533cb4a300..944f5ed300 100644 --- a/drivers/src/nrfx_usbreg.c +++ b/drivers/src/nrfx_usbreg.c @@ -51,6 +51,9 @@ void nrfx_usbreg_init(nrfx_usbreg_config_t const * p_config) nrfx_usbreg_uninit(); m_usbevt_handler = p_config->handler; + nrf_usbreg_event_clear(NRF_USBREGULATOR, NRF_USBREG_EVENT_USBDETECTED); + nrf_usbreg_event_clear(NRF_USBREGULATOR, NRF_USBREG_EVENT_USBPWRRDY); + nrf_usbreg_event_clear(NRF_USBREGULATOR, NRF_USBREG_EVENT_USBREMOVED); NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(NRF_USBREGULATOR), p_config->irq_priority); NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_USBREGULATOR)); diff --git a/hal/nrf_common.h b/hal/nrf_common.h index 7f0dd3d776..cceb533e8e 100644 --- a/hal/nrf_common.h +++ b/hal/nrf_common.h @@ -42,6 +42,18 @@ extern "C" { #define NRFX_EVENT_READBACK_ENABLED 1 #endif +#if defined(NRFX_CLZ) +#define NRF_CLZ(value) NRFX_CLZ(value) +#else +#define NRF_CLZ(value) __CLZ(value) +#endif + +#if defined(NRFX_CTZ) +#define NRF_CTZ(value) NRFX_CTZ(value) +#else +#define NRF_CTZ(value) __CLZ(__RBIT(value)) +#endif + #ifndef NRF_DECLARE_ONLY NRF_STATIC_INLINE void nrf_event_readback(void * p_event_reg) diff --git a/hal/nrf_gpio.h b/hal/nrf_gpio.h index 0364b6da43..be14dc94ff 100644 --- a/hal/nrf_gpio.h +++ b/hal/nrf_gpio.h @@ -200,6 +200,27 @@ NRF_STATIC_INLINE void nrf_gpio_cfg( nrf_gpio_pin_drive_t drive, nrf_gpio_pin_sense_t sense); +/** + * @brief Function for reconfiguring pin. + * + * @note This function selectively updates fields in PIN_CNF register. Reconfiguration + * is performed in single register write. Fields for which new configuration is + * not provided remain unchanged. + * + * @param pin_number Specifies the pin number. + * @param p_dir Pin direction. If NULL, previous setting remains. + * @param p_input Connect or disconnect the input buffer. If NULL, previous setting remains. + * @param p_pull Pull configuration. If NULL, previous setting remains. + * @param p_drive Drive configuration. If NULL, previous setting remains. + * @param p_sense Pin sensing mechanism. If NULL, previous setting remains. + */ +NRF_STATIC_INLINE void nrf_gpio_reconfigure(uint32_t pin_number, + const nrf_gpio_pin_dir_t * p_dir, + const nrf_gpio_pin_input_t * p_input, + const nrf_gpio_pin_pull_t * p_pull, + const nrf_gpio_pin_drive_t * p_drive, + const nrf_gpio_pin_sense_t * p_sense); + /** * @brief Function for configuring the given GPIO pin number as output, hiding inner details. * This function can be used to configure a pin as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases). @@ -592,6 +613,31 @@ NRF_STATIC_INLINE void nrf_gpio_cfg( reg->PIN_CNF[pin_number] = cnf; } +NRF_STATIC_INLINE void nrf_gpio_reconfigure(uint32_t pin_number, + const nrf_gpio_pin_dir_t * p_dir, + const nrf_gpio_pin_input_t * p_input, + const nrf_gpio_pin_pull_t * p_pull, + const nrf_gpio_pin_drive_t * p_drive, + const nrf_gpio_pin_sense_t * p_sense) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + uint32_t cnf = reg->PIN_CNF[pin_number]; + uint32_t to_update = (p_dir ? GPIO_PIN_CNF_DIR_Msk : 0) | + (p_input ? GPIO_PIN_CNF_INPUT_Msk : 0) | + (p_pull ? GPIO_PIN_CNF_PULL_Msk : 0) | + (p_drive ? GPIO_PIN_CNF_DRIVE_Msk : 0) | + (p_sense ? GPIO_PIN_CNF_SENSE_Msk : 0); + + /* Clear fields that will be updated. */ + cnf &= ~to_update; + cnf |= ((uint32_t)(p_dir ? *p_dir : 0) << GPIO_PIN_CNF_DIR_Pos) | + ((uint32_t)(p_input ? *p_input : 0) << GPIO_PIN_CNF_INPUT_Pos) | + ((uint32_t)(p_pull ? *p_pull : 0) << GPIO_PIN_CNF_PULL_Pos) | + ((uint32_t)(p_drive ? *p_drive : 0) << GPIO_PIN_CNF_DRIVE_Pos) | + ((uint32_t)(p_sense ? *p_sense : 0)<< GPIO_PIN_CNF_SENSE_Pos); + + reg->PIN_CNF[pin_number] = cnf; +} NRF_STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number) { @@ -631,19 +677,17 @@ NRF_STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number) NRF_STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number) { - NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); - uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_INPUT_Msk; + nrf_gpio_pin_input_t input = NRF_GPIO_PIN_INPUT_CONNECT; - reg->PIN_CNF[pin_number] = cnf | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos); + nrf_gpio_reconfigure(pin_number, NULL, &input, NULL, NULL, NULL); } NRF_STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number) { - NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); - uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_INPUT_Msk; + nrf_gpio_pin_input_t input = NRF_GPIO_PIN_INPUT_DISCONNECT; - reg->PIN_CNF[pin_number] = cnf | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos); + nrf_gpio_reconfigure(pin_number, NULL, &input, NULL, NULL, NULL); } @@ -664,13 +708,9 @@ NRF_STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number, NRF_STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number, nrf_gpio_pin_sense_t sense_config) { - NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); - uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_SENSE_Msk; - - reg->PIN_CNF[pin_number] = cnf | (sense_config << GPIO_PIN_CNF_SENSE_Pos); + nrf_gpio_reconfigure(pin_number, NULL, NULL, NULL, NULL, &sense_config); } - NRF_STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction) { if (direction == NRF_GPIO_PIN_DIR_INPUT) diff --git a/hal/nrf_gpiote.h b/hal/nrf_gpiote.h index 6a58ac2e9c..8c4b5f874b 100644 --- a/hal/nrf_gpiote.h +++ b/hal/nrf_gpiote.h @@ -64,6 +64,7 @@ extern "C" { /** @brief Polarity for the GPIOTE channel. */ typedef enum { + NRF_GPIOTE_POLARITY_NONE = GPIOTE_CONFIG_POLARITY_None, /**< None. */ NRF_GPIOTE_POLARITY_LOTOHI = GPIOTE_CONFIG_POLARITY_LoToHi, /**< Low to high. */ NRF_GPIOTE_POLARITY_HITOLO = GPIOTE_CONFIG_POLARITY_HiToLo, /**< High to low. */ NRF_GPIOTE_POLARITY_TOGGLE = GPIOTE_CONFIG_POLARITY_Toggle, /**< Toggle. */ @@ -540,7 +541,7 @@ NRF_STATIC_INLINE void nrf_gpiote_event_enable(NRF_GPIOTE_Type * p_reg, uint32_t NRF_STATIC_INLINE void nrf_gpiote_event_disable(NRF_GPIOTE_Type * p_reg, uint32_t idx) { - p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Event; + p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Msk; } NRF_STATIC_INLINE void nrf_gpiote_event_configure(NRF_GPIOTE_Type * p_reg, @@ -585,7 +586,7 @@ NRF_STATIC_INLINE void nrf_gpiote_task_enable(NRF_GPIOTE_Type * p_reg, uint32_t NRF_STATIC_INLINE void nrf_gpiote_task_disable(NRF_GPIOTE_Type * p_reg, uint32_t idx) { - p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Task; + p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Msk; } NRF_STATIC_INLINE void nrf_gpiote_task_configure(NRF_GPIOTE_Type * p_reg, @@ -614,6 +615,9 @@ NRF_STATIC_INLINE void nrf_gpiote_task_force(NRF_GPIOTE_Type * p_reg, NRF_STATIC_INLINE void nrf_gpiote_te_default(NRF_GPIOTE_Type * p_reg, uint32_t idx) { p_reg->CONFIG[idx] = 0; +#if defined(NRF9160_XXAA) || defined(NRF5340_XXAA) + p_reg->CONFIG[idx] = 0; +#endif } NRF_STATIC_INLINE bool nrf_gpiote_te_is_enabled(NRF_GPIOTE_Type const * p_reg, uint32_t idx) diff --git a/hal/nrf_timer.h b/hal/nrf_timer.h index 64da71c586..d38d09c1ee 100644 --- a/hal/nrf_timer.h +++ b/hal/nrf_timer.h @@ -177,6 +177,12 @@ typedef enum #endif #if defined(TIMER_INTENSET_COMPARE5_Msk) || defined(__NRFX_DOXYGEN__) NRF_TIMER_SHORT_COMPARE5_STOP_MASK = TIMER_SHORTS_COMPARE5_STOP_Msk, ///< Shortcut for stopping the timer based on compare 5. +#endif +#if defined(TIMER_INTENSET_COMPARE6_Msk) || defined(__NRFX_DOXYGEN__) + NRF_TIMER_SHORT_COMPARE6_STOP_MASK = TIMER_SHORTS_COMPARE6_STOP_Msk, ///< Shortcut for stopping the timer based on compare 6. +#endif +#if defined(TIMER_INTENSET_COMPARE7_Msk) || defined(__NRFX_DOXYGEN__) + NRF_TIMER_SHORT_COMPARE7_STOP_MASK = TIMER_SHORTS_COMPARE7_STOP_Msk, ///< Shortcut for stopping the timer based on compare 7. #endif NRF_TIMER_SHORT_COMPARE0_CLEAR_MASK = TIMER_SHORTS_COMPARE0_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 0. NRF_TIMER_SHORT_COMPARE1_CLEAR_MASK = TIMER_SHORTS_COMPARE1_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 1. @@ -188,6 +194,12 @@ typedef enum #if defined(TIMER_INTENSET_COMPARE5_Msk) || defined(__NRFX_DOXYGEN__) NRF_TIMER_SHORT_COMPARE5_CLEAR_MASK = TIMER_SHORTS_COMPARE5_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 5. #endif +#if defined(TIMER_INTENSET_COMPARE6_Msk) || defined(__NRFX_DOXYGEN__) + NRF_TIMER_SHORT_COMPARE6_CLEAR_MASK = TIMER_SHORTS_COMPARE6_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 6. +#endif +#if defined(TIMER_INTENSET_COMPARE7_Msk) || defined(__NRFX_DOXYGEN__) + NRF_TIMER_SHORT_COMPARE7_CLEAR_MASK = TIMER_SHORTS_COMPARE7_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 7. +#endif } nrf_timer_short_mask_t; /** @brief Timer modes. */ @@ -237,6 +249,12 @@ typedef enum #if defined(TIMER_INTENSET_COMPARE5_Msk) || defined(__NRFX_DOXYGEN__) NRF_TIMER_CC_CHANNEL5, ///< Timer capture/compare channel 5. #endif +#if defined(TIMER_INTENSET_COMPARE6_Msk) || defined(__NRFX_DOXYGEN__) + NRF_TIMER_CC_CHANNEL6, ///< Timer capture/compare channel 6. +#endif +#if defined(TIMER_INTENSET_COMPARE7_Msk) || defined(__NRFX_DOXYGEN__) + NRF_TIMER_CC_CHANNEL7, ///< Timer capture/compare channel 7. +#endif } nrf_timer_cc_channel_t; /** @brief Timer interrupts. */ @@ -252,6 +270,12 @@ typedef enum #if defined(TIMER_INTENSET_COMPARE5_Msk) || defined(__NRFX_DOXYGEN__) NRF_TIMER_INT_COMPARE5_MASK = TIMER_INTENSET_COMPARE5_Msk, ///< Timer interrupt from compare event on channel 5. #endif +#if defined(TIMER_INTENSET_COMPARE6_Msk) || defined(__NRFX_DOXYGEN__) + NRF_TIMER_INT_COMPARE6_MASK = TIMER_INTENSET_COMPARE6_Msk, ///< Timer interrupt from compare event on channel 6. +#endif +#if defined(TIMER_INTENSET_COMPARE7_Msk) || defined(__NRFX_DOXYGEN__) + NRF_TIMER_INT_COMPARE7_MASK = TIMER_INTENSET_COMPARE7_Msk, ///< Timer interrupt from compare event on channel 7. +#endif } nrf_timer_int_mask_t; @@ -334,6 +358,24 @@ NRF_STATIC_INLINE void nrf_timer_shorts_disable(NRF_TIMER_Type * p_reg, NRF_STATIC_INLINE void nrf_timer_shorts_set(NRF_TIMER_Type * p_reg, uint32_t mask); +/** + * @brief Function for getting COMPARE_CLEAR short mask for the specified channel. + * + * @param[in] channel Channel. + * + * @return Short mask. + */ +NRF_STATIC_INLINE nrf_timer_short_mask_t nrf_timer_short_compare_clear_get(uint8_t channel); + +/** + * @brief Function for getting COMPARE_STOP short mask for the specified channel. + * + * @param[in] channel Channel. + * + * @return Short mask. + */ +NRF_STATIC_INLINE nrf_timer_short_mask_t nrf_timer_short_compare_stop_get(uint8_t channel); + /** * @brief Function for enabling the specified interrupts. * @@ -607,6 +649,16 @@ NRF_STATIC_INLINE void nrf_timer_shorts_set(NRF_TIMER_Type * p_reg, p_reg->SHORTS = mask; } +NRF_STATIC_INLINE nrf_timer_short_mask_t nrf_timer_short_compare_clear_get(uint8_t channel) +{ + return (nrf_timer_short_mask_t)((uint32_t)NRF_TIMER_SHORT_COMPARE0_CLEAR_MASK << channel); +} + +NRF_STATIC_INLINE nrf_timer_short_mask_t nrf_timer_short_compare_stop_get(uint8_t channel) +{ + return (nrf_timer_short_mask_t)((uint32_t)NRF_TIMER_SHORT_COMPARE0_STOP_MASK << channel); +} + NRF_STATIC_INLINE void nrf_timer_int_enable(NRF_TIMER_Type * p_reg, uint32_t mask) { diff --git a/helpers/nrfx_flag32_allocator.c b/helpers/nrfx_flag32_allocator.c new file mode 100644 index 0000000000..f0f0be3b78 --- /dev/null +++ b/helpers/nrfx_flag32_allocator.c @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2021, Nordic Semiconductor ASA + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include + +#if !defined(NRFX_ATOMIC_CAS) +static bool nrfx_flag32_atomic_cas(nrfx_atomic_t * p_data, uint32_t old_value, uint32_t new_value) +{ + bool status = false; + NRFX_CRITICAL_SECTION_ENTER(); + if (*p_data == old_value) + { + *p_data = new_value; + status = true; + } + NRFX_CRITICAL_SECTION_EXIT(); + return status; +} + +#define NRFX_ATOMIC_CAS(p_data, old_value, new_value) \ + nrfx_flag32_atomic_cas(p_data, old_value, new_value) +#endif // !defined(NRFX_ATOMIC_CAS) + +bool nrfx_flag32_is_allocated(nrfx_atomic_t mask, uint8_t bitpos) +{ + return (mask & NRFX_BIT(bitpos)) ? false : true; +} + +nrfx_err_t nrfx_flag32_alloc(nrfx_atomic_t * p_mask, uint8_t *p_flag) +{ + int8_t idx; + uint32_t new_mask, prev_mask; + + do { + prev_mask = *p_mask; + idx = 31 - NRF_CLZ(prev_mask); + if (idx < 0) { + return NRFX_ERROR_NO_MEM; + } + + new_mask = prev_mask & ~NRFX_BIT(idx); + } while (!NRFX_ATOMIC_CAS(p_mask, prev_mask, new_mask)); + + *p_flag = idx; + + return NRFX_SUCCESS; +} + +nrfx_err_t nrfx_flag32_free(nrfx_atomic_t * p_mask, uint8_t flag) +{ + uint32_t new_mask, prev_mask; + + if ((NRFX_BIT(flag) & *p_mask)) + { + return NRFX_ERROR_INVALID_PARAM; + } + + do { + prev_mask = *p_mask; + new_mask = prev_mask | NRFX_BIT(flag); + } while (!NRFX_ATOMIC_CAS(p_mask, prev_mask, new_mask)); + + return NRFX_SUCCESS; +} diff --git a/helpers/nrfx_flag32_allocator.h b/helpers/nrfx_flag32_allocator.h new file mode 100644 index 0000000000..186772f596 --- /dev/null +++ b/helpers/nrfx_flag32_allocator.h @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2021, Nordic Semiconductor ASA + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_FLAG32_ALLOCATOR_H__ +#define NRFX_FLAG32_ALLOCATOR_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_flag32_allocator Generic flag allocator + * @{ + * @ingroup nrfx + * @brief Generic flag allocator. + */ + +/** + * @brief Function for initializing allocator mask. + * + * Initialization value contains mask where each bit indicates availablility of + * a given flag, e.g. init value 0x0000000A indicates that flag 3 and 1 (counting + * from 0) can be allocated. + * + * Alternatively, mask can be set to init value by direct assignment. + * + * @param[out] p_mask Mask to be initilized. + * @param[in] init_mask Mask with pool of available flags where bit being set means that + * flag is free and can be allocated. + */ +__STATIC_INLINE void nrfx_flag32_init(nrfx_atomic_t * p_mask, uint32_t init_mask) +{ + *p_mask = init_mask; +} + +/** + * @brief Function for checking if given flag is allocated. + * + * @note This check may not be valid if context is preempted and state is changed. + * + * @param[in] mask Mask. + * @param[in] bitpos Flag bit position. + * + * @return True if specified flag is allocated, false otherwise. + */ +bool nrfx_flag32_is_allocated(nrfx_atomic_t mask, uint8_t bitpos); + +/** + * @brief Function for allocating a flag in the mask. + * + * @note Function is thread safe, it uses @ref NRFX_ATOMIC_CAS macro. No further + * synchronization mechanism is needed, provided the macro is properly implemented + * (see @ref nrfx_glue). + * + * Mask must be initialized before first allocation. Flags are allocated from the + * highest bit position, e.g. if mask is set to 0x0000000A, 3 is returned and bit 3 + * is cleared in the mask. Mask is set to 0x00000002 on return after successful allocation. + * + * @param[in,out] p_mask Mask with available flags set. On successful allocation flag is cleared. + * @param[out] p_flag Index of the allocated flag. + * + * @retval NRFX_SUCCESS Allocation was successful. + * @retval NRFX_ERROR_NO_MEM No resource available. + */ +nrfx_err_t nrfx_flag32_alloc(nrfx_atomic_t * p_mask, uint8_t * p_flag); + +/** + * @brief Function for freeing a flag allocated with @ref nrfx_flag32_alloc. + * + * @note Function is thread safe, it uses @ref NRFX_ATOMIC_CAS macro. No further + * synchronization mechanism is needed, provided the macro is properly implemented + * (see @ref nrfx_glue). + * + * @param[in,out] p_mask Mask with available flags set. On successful allocation flag is set. + * @param[in] flag Flag index. + * + * @retval NRFX_SUCCESS Freeing was successful. + * @retval NRFX_ERROR_INVALID_PARAM Flag was not allocated. + */ +nrfx_err_t nrfx_flag32_free(nrfx_atomic_t * p_mask, uint8_t flag); + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_FLAG32_ALLOCATOR_H__ diff --git a/helpers/nrfx_gppi.h b/helpers/nrfx_gppi.h index 3b35bc9cb6..d78c345aa4 100644 --- a/helpers/nrfx_gppi.h +++ b/helpers/nrfx_gppi.h @@ -36,6 +36,14 @@ #include +#if NRFX_CHECK(NRFX_DPPI_ENABLED) +#include +#endif + +#if NRFX_CHECK(NRFX_PPI_ENABLED) +#include +#endif + #ifdef __cplusplus extern "C" { #endif @@ -342,6 +350,51 @@ __STATIC_INLINE nrfx_gppi_task_t nrfx_gppi_group_disable_task_get(nrfx_gppi_chan */ __STATIC_INLINE nrfx_gppi_task_t nrfx_gppi_group_enable_task_get(nrfx_gppi_channel_group_t group); +/** + * @brief Function for allocating a channel. + * + * @param[out] p_channel After successful allocation, index of the allocated channel. + * + * @retval NRFX_SUCCESS Channel was successfully allocated. + * @retval NRFX_ERROR_NO_MEM There is no available channel to be used. + * @retval NRFX_ERROR_NOT_SUPPORTED Driver is not enabled. + */ +__STATIC_INLINE nrfx_err_t nrfx_gppi_channel_alloc(uint8_t * p_channel); + +/** + * @brief Function for freeing a channel. + * + * @param[in] channel (D)PPI channel to be freed. + * + * @retval NRFX_SUCCESS The channel was successfully freed. + * @retval NRFX_ERROR_INVALID_PARAM The specified channel is not allocated or + * is not user-configurable. + * @retval NRFX_ERROR_NOT_SUPPORTED Driver is not enabled. + */ +__STATIC_INLINE nrfx_err_t nrfx_gppi_channel_free(uint8_t channel); + +/** + * @brief Function for allocating a channel group. + * + * @param[out] p_group Pointer to the (D)PPI channel group that has been allocated. + * + * @retval NRFX_SUCCESS The channel group was successfully allocated. + * @retval NRFX_ERROR_NO_MEM There is no available channel group to be used. + * @retval NRFX_ERROR_NOT_SUPPORTED Driver is not enabled. + */ +__STATIC_INLINE nrfx_err_t nrfx_gppi_group_alloc(nrfx_gppi_channel_group_t * p_group); + +/** + * @brief Function for freeing a channel group. + * + * @param[in] group (D)PPI channel group to be freed. + * + * @retval NRFX_SUCCESS The channel was successfully freed. + * @retval NRFX_ERROR_INVALID_PARAM The specified channel is not allocated or + * is not user-configurable. + * @retval NRFX_ERROR_NOT_SUPPORTED Driver is not enabled. + */ +__STATIC_INLINE nrfx_err_t nrfx_gppi_group_free(nrfx_gppi_channel_group_t group); /** @} */ #if defined(PPI_PRESENT) @@ -460,6 +513,45 @@ __STATIC_INLINE nrfx_gppi_task_t nrfx_gppi_group_enable_task_get(nrfx_gppi_chann return (nrfx_gppi_task_t)nrf_ppi_group_enable_task_get(NRF_PPI, (uint8_t)group); } +__STATIC_INLINE nrfx_err_t nrfx_gppi_channel_alloc(uint8_t * p_channel) +{ +#if NRFX_CHECK(NRFX_PPI_ENABLED) + return nrfx_ppi_channel_alloc((nrf_ppi_channel_t *)p_channel); +#else + (void)p_channel; + return NRFX_ERROR_NOT_SUPPORTED; +#endif +} + +__STATIC_INLINE nrfx_err_t nrfx_gppi_channel_free(uint8_t channel) +{ +#if NRFX_CHECK(NRFX_PPI_ENABLED) + return nrfx_ppi_channel_free((nrf_ppi_channel_t)channel); +#else + (void)channel; + return NRFX_ERROR_NOT_SUPPORTED; +#endif +} + +__STATIC_INLINE nrfx_err_t nrfx_gppi_group_alloc(nrfx_gppi_channel_group_t * p_group) +{ +#if NRFX_CHECK(NRFX_PPI_ENABLED) + return nrfx_ppi_group_alloc((nrf_ppi_channel_group_t *)p_group); +#else + (void)p_group; + return NRFX_ERROR_NOT_SUPPORTED; +#endif +} + +__STATIC_INLINE nrfx_err_t nrfx_gppi_group_free(nrfx_gppi_channel_group_t group) +{ +#if NRFX_CHECK(NRFX_PPI_ENABLED) + return nrfx_ppi_group_free((nrf_ppi_channel_group_t)group); +#else + (void)group; + return NRFX_ERROR_NOT_SUPPORTED; +#endif +} #elif defined(DPPI_PRESENT) __STATIC_INLINE bool nrfx_gppi_channel_check(uint8_t channel) @@ -577,6 +669,45 @@ __STATIC_INLINE nrfx_gppi_task_t nrfx_gppi_group_enable_task_get(nrfx_gppi_chann return (nrfx_gppi_task_t) nrf_dppi_group_enable_task_get((uint8_t)group); } +__STATIC_INLINE nrfx_err_t nrfx_gppi_channel_alloc(uint8_t * p_channel) +{ +#if NRFX_CHECK(NRFX_DPPI_ENABLED) + return nrfx_dppi_channel_alloc(p_channel); +#else + (void)p_channel; + return NRFX_ERROR_NOT_SUPPORTED; +#endif +} + +__STATIC_INLINE nrfx_err_t nrfx_gppi_channel_free(uint8_t channel) +{ +#if NRFX_CHECK(NRFX_DPPI_ENABLED) + return nrfx_dppi_channel_free(channel); +#else + (void)channel; + return NRFX_ERROR_NOT_SUPPORTED; +#endif +} + +__STATIC_INLINE nrfx_err_t nrfx_gppi_group_alloc(nrfx_gppi_channel_group_t * p_group) +{ +#if NRFX_CHECK(NRFX_DPPI_ENABLED) + return nrfx_dppi_group_alloc((nrf_dppi_channel_group_t *)p_group); +#else + (void)p_group; + return NRFX_ERROR_NOT_SUPPORTED; +#endif +} + +__STATIC_INLINE nrfx_err_t nrfx_gppi_group_free(nrfx_gppi_channel_group_t group) +{ +#if NRFX_CHECK(NRFX_DPPI_ENABLED) + return nrfx_dppi_group_free((nrf_dppi_channel_group_t)group); +#else + (void)group; + return NRFX_ERROR_NOT_SUPPORTED; +#endif +} #else #error "Neither PPI nor DPPI is present in the SoC currently in use." #endif diff --git a/mdk/arm_startup_nrf9160.s b/mdk/arm_startup_nrf9160.s index 917bf61bc8..323886ba19 100644 --- a/mdk/arm_startup_nrf9160.s +++ b/mdk/arm_startup_nrf9160.s @@ -30,7 +30,7 @@ Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE ELIF :DEF: __STACK_SIZE Stack_Size EQU __STACK_SIZE ELSE -Stack_Size EQU 16384 +Stack_Size EQU 15872 ENDIF IF :DEF: __STARTUP_CONFIG @@ -48,7 +48,7 @@ Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE ELIF :DEF: __HEAP_SIZE Heap_Size EQU __HEAP_SIZE ELSE -Heap_Size EQU 16384 +Heap_Size EQU 15872 ENDIF AREA HEAP, NOINIT, READWRITE, ALIGN=3 diff --git a/mdk/compiler_abstraction.h b/mdk/compiler_abstraction.h index b687bfabea..ee94959731 100644 --- a/mdk/compiler_abstraction.h +++ b/mdk/compiler_abstraction.h @@ -130,7 +130,7 @@ POSSIBILITY OF SUCH DAMAGE. #if (__VER__ >= 8000000) #ifndef __ALIGN - #define __ALIGN(n) __attribute__((aligned(x))) + #define __ALIGN(n) __attribute__((aligned(n))) #endif #ifndef __PACKED diff --git a/mdk/gcc_startup_nrf9160.S b/mdk/gcc_startup_nrf9160.S index 9c310dff22..9d635ccf10 100644 --- a/mdk/gcc_startup_nrf9160.S +++ b/mdk/gcc_startup_nrf9160.S @@ -39,7 +39,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. .equ Stack_Size, __STACK_SIZE #else .align 3 - .equ Stack_Size, 16384 + .equ Stack_Size, 15872 #endif .globl __StackTop .globl __StackLimit @@ -56,7 +56,7 @@ __StackTop: #elif defined(__HEAP_SIZE) .equ Heap_Size, __HEAP_SIZE #else - .equ Heap_Size, 16384 + .equ Heap_Size, 15872 #endif .globl __HeapBase .globl __HeapLimit diff --git a/mdk/nrf.h b/mdk/nrf.h index 8a122273da..63906a44b0 100644 --- a/mdk/nrf.h +++ b/mdk/nrf.h @@ -37,8 +37,8 @@ POSSIBILITY OF SUCH DAMAGE. /* MDK version */ #define MDK_MAJOR_VERSION 8 -#define MDK_MINOR_VERSION 40 -#define MDK_MICRO_VERSION 2 +#define MDK_MINOR_VERSION 44 +#define MDK_MICRO_VERSION 1 /* Define coprocessor domains */ @@ -170,6 +170,12 @@ POSSIBILITY OF SUCH DAMAGE. #include "nrf5340_application.h" #include "nrf5340_application_bitfields.h" #include "nrf5340_application_name_change.h" + + /* Address of locations in RAM that will be used to store a NS-accessible version of FICR */ + #if !defined(NRF_FICR_NS) + #define NRF_FICR_NS_BASE 0x2007F000 + #define NRF_FICR_NS ((NRF_FICR_Type*) NRF_FICR_NS_BASE) + #endif #elif defined (NRF_NETWORK) #include "nrf5340_network.h" #include "nrf5340_network_bitfields.h" @@ -181,6 +187,12 @@ POSSIBILITY OF SUCH DAMAGE. #include "nrf9160_bitfields.h" #include "nrf9160_name_change.h" + /* Address of locations in RAM that will be used to store a NS-accessible version of FICR */ + #if !defined(NRF_FICR_NS) + #define NRF_FICR_NS_BASE 0x2003E000 + #define NRF_FICR_NS ((NRF_FICR_Type*) NRF_FICR_NS_BASE) + #endif + #else #error "Device must be defined. See nrf.h." #endif /* NRF51, NRF52805_XXAA, NRF52810_XXAA, NRF52811_XXAA, NRF52820_XXAA, NRF52832_XXAA, NRF52832_XXAB, NRF52833_XXAA, NRF52840_XXAA, NRF5340_XXAA_APPLICATION, NRF5340_XXAA_NETWORK, NRF9160_XXAA */ diff --git a/mdk/nrf51.h b/mdk/nrf51.h index 0bf8fb6a38..fff9d076cc 100644 --- a/mdk/nrf51.h +++ b/mdk/nrf51.h @@ -32,10 +32,10 @@ * @file nrf51.h * @brief CMSIS HeaderFile * @version 522 - * @date 29. April 2021 - * @note Generated by SVDConv V3.3.35 on Thursday, 29.04.2021 12:43:41 + * @date 19. November 2021 + * @note Generated by SVDConv V3.3.35 on Friday, 19.11.2021 12:44:56 * from File 'nrf51.svd', - * last modified on Thursday, 29.04.2021 10:43:40 + * last modified on Friday, 19.11.2021 11:44:55 */ diff --git a/mdk/nrf51_common.ld b/mdk/nrf51_common.ld index 98a10037f1..e757a2338d 100644 --- a/mdk/nrf51_common.ld +++ b/mdk/nrf51_common.ld @@ -77,17 +77,24 @@ SECTIONS KEEP(*(.eh_frame*)) } > FLASH - .ARM.extab : + .gnu.sgstubs : + { + . = ALIGN(32); + } > FLASH + + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH - __exidx_start = .; + .ARM.exidx : { + __exidx_start = .; *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; } > FLASH - __exidx_end = .; . = ALIGN(4); __etext = .; diff --git a/mdk/nrf52.h b/mdk/nrf52.h index 6aab0ea8bd..53ac88713a 100644 --- a/mdk/nrf52.h +++ b/mdk/nrf52.h @@ -32,10 +32,10 @@ * @file nrf52.h * @brief CMSIS HeaderFile * @version 1 - * @date 29. April 2021 - * @note Generated by SVDConv V3.3.35 on Thursday, 29.04.2021 12:43:45 + * @date 19. November 2021 + * @note Generated by SVDConv V3.3.35 on Friday, 19.11.2021 12:45:00 * from File 'nrf52.svd', - * last modified on Thursday, 29.04.2021 10:43:40 + * last modified on Friday, 19.11.2021 11:44:55 */ diff --git a/mdk/nrf52.svd b/mdk/nrf52.svd index f052a928c9..32a409254c 100644 --- a/mdk/nrf52.svd +++ b/mdk/nrf52.svd @@ -6,7 +6,7 @@ nrf52 nrf52 1 - nRF52832 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller + nRF52 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.\n \n @@ -251,6 +251,11 @@ POSSIBILITY OF SUCH DAMAGE.\n AAAB 0x41414142 + + AAAC + AAAC + 0x41414143 + AABA AABA @@ -266,11 +271,41 @@ POSSIBILITY OF SUCH DAMAGE.\n AAB0 0x41414230 + + ABB0 + ABB0 + 0x41424230 + AAE0 AAE0 0x41414530 + + ABE0 + ABE0 + 0x41424530 + + + AAGB + AAGB + 0x41414742 + + + ABGB + ABGB + 0x41424742 + + + AAG0 + AAG0 + 0x41414730 + + + ABG0 + ABG0 + 0x41424730 + Unspecified Unspecified diff --git a/mdk/nrf52805.h b/mdk/nrf52805.h index 9cc4024ef6..0903e79f2c 100644 --- a/mdk/nrf52805.h +++ b/mdk/nrf52805.h @@ -32,10 +32,10 @@ * @file nrf52805.h * @brief CMSIS HeaderFile * @version 1 - * @date 29. April 2021 - * @note Generated by SVDConv V3.3.35 on Thursday, 29.04.2021 12:43:42 + * @date 19. November 2021 + * @note Generated by SVDConv V3.3.35 on Friday, 19.11.2021 12:44:56 * from File 'nrf52805.svd', - * last modified on Thursday, 29.04.2021 10:43:40 + * last modified on Friday, 19.11.2021 11:44:55 */ @@ -551,7 +551,8 @@ typedef struct { /*!< (@ 0x10001000) UICR Structu __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection: Reserved for Nordic hardware design */ __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection: Reserved for customer */ - __IM uint32_t RESERVED2[64]; + __IOM uint32_t NRFMDK[8]; /*!< (@ 0x00000100) Description collection: Reserved for Nordic MDK */ + __IM uint32_t RESERVED2[56]; __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection: Mapping of the nRESET function (see POWER chapter for details) */ __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access port protection */ diff --git a/mdk/nrf52805.svd b/mdk/nrf52805.svd index 912d89d2a9..27f1725aa6 100644 --- a/mdk/nrf52805.svd +++ b/mdk/nrf52805.svd @@ -716,6 +716,23 @@ POSSIBILITY OF SUCH DAMAGE.\n + + 0x8 + 0x4 + NRFMDK[%s] + Description collection: Reserved for Nordic MDK + 0x100 + read-write + 0xFFFFFFFF + + + NRFMDK + Reserved for Nordic MDK + 0 + 31 + + + 0x2 0x4 @@ -766,9 +783,14 @@ POSSIBILITY OF SUCH DAMAGE.\n Disabled - Disable + Hardware disable of access port protection for devices where access port protection is controlled by hardware 0xFF + + HwDisabled + Hardware disable of access port protection for devices where access port protection is controlled by hardware and software + 0x5A + Enabled Enable diff --git a/mdk/nrf52805_bitfields.h b/mdk/nrf52805_bitfields.h index ac54eeedac..9cc0e2dc18 100644 --- a/mdk/nrf52805_bitfields.h +++ b/mdk/nrf52805_bitfields.h @@ -10149,6 +10149,13 @@ POSSIBILITY OF SUCH DAMAGE. #define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */ #define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */ +/* Register: UICR_NRFMDK */ +/* Description: Description collection: Reserved for Nordic MDK */ + +/* Bits 31..0 : Reserved for Nordic MDK */ +#define UICR_NRFMDK_NRFMDK_Pos (0UL) /*!< Position of NRFMDK field. */ +#define UICR_NRFMDK_NRFMDK_Msk (0xFFFFFFFFUL << UICR_NRFMDK_NRFMDK_Pos) /*!< Bit mask of NRFMDK field. */ + /* Register: UICR_PSELRESET */ /* Description: Description collection: Mapping of the nRESET function (see POWER chapter for details) */ @@ -10169,7 +10176,8 @@ POSSIBILITY OF SUCH DAMAGE. #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ #define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ #define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */ -#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */ +#define UICR_APPROTECT_PALL_HwDisabled (0x5AUL) /*!< Hardware disable of access port protection for devices where access port protection is controlled by hardware and software */ +#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Hardware disable of access port protection for devices where access port protection is controlled by hardware */ /* Peripheral: WDT */ diff --git a/mdk/nrf52810.h b/mdk/nrf52810.h index 1c0b1be603..a30bfcab75 100644 --- a/mdk/nrf52810.h +++ b/mdk/nrf52810.h @@ -32,10 +32,10 @@ * @file nrf52810.h * @brief CMSIS HeaderFile * @version 1 - * @date 29. April 2021 - * @note Generated by SVDConv V3.3.35 on Thursday, 29.04.2021 12:43:43 + * @date 19. November 2021 + * @note Generated by SVDConv V3.3.35 on Friday, 19.11.2021 12:44:57 * from File 'nrf52810.svd', - * last modified on Thursday, 29.04.2021 10:43:40 + * last modified on Friday, 19.11.2021 11:44:55 */ @@ -599,7 +599,8 @@ typedef struct { /*!< (@ 0x10001000) UICR Structu __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection: Reserved for Nordic hardware design */ __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection: Reserved for customer */ - __IM uint32_t RESERVED2[64]; + __IOM uint32_t NRFMDK[8]; /*!< (@ 0x00000100) Description collection: Reserved for Nordic MDK */ + __IM uint32_t RESERVED2[56]; __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection: Mapping of the nRESET function (see POWER chapter for details) */ __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access port protection */ diff --git a/mdk/nrf52810.svd b/mdk/nrf52810.svd index bb685077d2..5130b5f847 100644 --- a/mdk/nrf52810.svd +++ b/mdk/nrf52810.svd @@ -721,6 +721,23 @@ POSSIBILITY OF SUCH DAMAGE.\n + + 0x8 + 0x4 + NRFMDK[%s] + Description collection: Reserved for Nordic MDK + 0x100 + read-write + 0xFFFFFFFF + + + NRFMDK + Reserved for Nordic MDK + 0 + 31 + + + 0x2 0x4 @@ -771,9 +788,14 @@ POSSIBILITY OF SUCH DAMAGE.\n Disabled - Disable + Hardware disable of access port protection for devices where access port protection is controlled by hardware 0xFF + + HwDisabled + Hardware disable of access port protection for devices where access port protection is controlled by hardware and software + 0x5A + Enabled Enable diff --git a/mdk/nrf52810_bitfields.h b/mdk/nrf52810_bitfields.h index c66acf1293..e949c665bb 100644 --- a/mdk/nrf52810_bitfields.h +++ b/mdk/nrf52810_bitfields.h @@ -11157,6 +11157,13 @@ POSSIBILITY OF SUCH DAMAGE. #define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */ #define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */ +/* Register: UICR_NRFMDK */ +/* Description: Description collection: Reserved for Nordic MDK */ + +/* Bits 31..0 : Reserved for Nordic MDK */ +#define UICR_NRFMDK_NRFMDK_Pos (0UL) /*!< Position of NRFMDK field. */ +#define UICR_NRFMDK_NRFMDK_Msk (0xFFFFFFFFUL << UICR_NRFMDK_NRFMDK_Pos) /*!< Bit mask of NRFMDK field. */ + /* Register: UICR_PSELRESET */ /* Description: Description collection: Mapping of the nRESET function (see POWER chapter for details) */ @@ -11177,7 +11184,8 @@ POSSIBILITY OF SUCH DAMAGE. #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ #define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ #define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */ -#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */ +#define UICR_APPROTECT_PALL_HwDisabled (0x5AUL) /*!< Hardware disable of access port protection for devices where access port protection is controlled by hardware and software */ +#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Hardware disable of access port protection for devices where access port protection is controlled by hardware */ /* Peripheral: WDT */ diff --git a/mdk/nrf52811.h b/mdk/nrf52811.h index 330d0c678c..88088cfc4d 100644 --- a/mdk/nrf52811.h +++ b/mdk/nrf52811.h @@ -32,10 +32,10 @@ * @file nrf52811.h * @brief CMSIS HeaderFile * @version 1 - * @date 29. April 2021 - * @note Generated by SVDConv V3.3.35 on Thursday, 29.04.2021 12:43:43 + * @date 19. November 2021 + * @note Generated by SVDConv V3.3.35 on Friday, 19.11.2021 12:44:58 * from File 'nrf52811.svd', - * last modified on Thursday, 29.04.2021 10:43:40 + * last modified on Friday, 19.11.2021 11:44:55 */ @@ -618,7 +618,8 @@ typedef struct { /*!< (@ 0x10001000) UICR Structu __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection: Reserved for Nordic hardware design */ __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection: Reserved for customer */ - __IM uint32_t RESERVED2[64]; + __IOM uint32_t NRFMDK[8]; /*!< (@ 0x00000100) Description collection: Reserved for Nordic MDK */ + __IM uint32_t RESERVED2[56]; __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection: Mapping of the nRESET function (see POWER chapter for details) */ __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access port protection */ @@ -627,39 +628,39 @@ typedef struct { /*!< (@ 0x10001000) UICR Structu /* =========================================================================================================================== */ -/* ================ BPROT ================ */ +/* ================ APPROTECT ================ */ /* =========================================================================================================================== */ /** - * @brief Block Protect (BPROT) + * @brief Access Port Protection (APPROTECT) */ -typedef struct { /*!< (@ 0x40000000) BPROT Structure */ - __IM uint32_t RESERVED[384]; - __IOM uint32_t CONFIG0; /*!< (@ 0x00000600) Block protect configuration register 0 */ - __IOM uint32_t CONFIG1; /*!< (@ 0x00000604) Block protect configuration register 1 */ - __IOM uint32_t DISABLEINDEBUG; /*!< (@ 0x00000608) Disable protection mechanism in debug mode */ -} NRF_BPROT_Type; /*!< Size = 1548 (0x60c) */ +typedef struct { /*!< (@ 0x40000000) APPROTECT Structure */ + __IM uint32_t RESERVED[340]; + __IOM uint32_t FORCEPROTECT; /*!< (@ 0x00000550) Software force enable APPROTECT mechanism until + next reset. */ + __IM uint32_t RESERVED1; + __IOM uint32_t DISABLE; /*!< (@ 0x00000558) Software disable APPROTECT mechanism */ +} NRF_APPROTECT_Type; /*!< Size = 1372 (0x55c) */ /* =========================================================================================================================== */ -/* ================ APPROTECT ================ */ +/* ================ BPROT ================ */ /* =========================================================================================================================== */ /** - * @brief Only for emulation on devices that support hardened AP-PROTECT. (APPROTECT) + * @brief Block Protect (BPROT) */ -typedef struct { /*!< (@ 0x40000000) APPROTECT Structure */ - __IM uint32_t RESERVED[340]; - __IOM uint32_t FORCEPROTECT; /*!< (@ 0x00000550) Software force enable APPROTECT mechanism until - next reset. */ - __IM uint32_t RESERVED1; - __IOM uint32_t DISABLE; /*!< (@ 0x00000558) Software disable APPROTECT mechanism */ -} NRF_APPROTECT_Type; /*!< Size = 1372 (0x55c) */ +typedef struct { /*!< (@ 0x40000000) BPROT Structure */ + __IM uint32_t RESERVED[384]; + __IOM uint32_t CONFIG0; /*!< (@ 0x00000600) Block protect configuration register 0 */ + __IOM uint32_t CONFIG1; /*!< (@ 0x00000604) Block protect configuration register 1 */ + __IOM uint32_t DISABLEINDEBUG; /*!< (@ 0x00000608) Disable protection mechanism in debug mode */ +} NRF_BPROT_Type; /*!< Size = 1548 (0x60c) */ @@ -820,7 +821,7 @@ typedef struct { /*!< (@ 0x40001000) RADIO Struct __IOM uint32_t EVENTS_FRAMESTART; /*!< (@ 0x00000138) IEEE 802.15.4 length field received */ __IOM uint32_t EVENTS_EDEND; /*!< (@ 0x0000013C) Sampling of energy detection complete. A new ED sample is ready for readout from the - RADIO.EDSAMPLE register */ + RADIO.EDSAMPLE register. */ __IOM uint32_t EVENTS_EDSTOPPED; /*!< (@ 0x00000140) The sampling of energy detection has stopped */ __IOM uint32_t EVENTS_CCAIDLE; /*!< (@ 0x00000144) Wireless medium in idle - clear to send */ __IOM uint32_t EVENTS_CCABUSY; /*!< (@ 0x00000148) Wireless medium busy - do not send */ @@ -832,8 +833,10 @@ typedef struct { /*!< (@ 0x40001000) RADIO Struct __IOM uint32_t EVENTS_RXREADY; /*!< (@ 0x00000158) RADIO has ramped up and is ready to be started RX path */ __IOM uint32_t EVENTS_MHRMATCH; /*!< (@ 0x0000015C) MAC header match found */ - __IM uint32_t RESERVED3[3]; - __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated when last bit is sent on air */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t EVENTS_SYNC; /*!< (@ 0x00000168) Preamble indicator */ + __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated when last bit is sent on air, or received + from air */ __IOM uint32_t EVENTS_CTEPRESENT; /*!< (@ 0x00000170) CTE is present (early warning right after receiving CTEInfo byte) */ __IM uint32_t RESERVED4[35]; @@ -889,7 +892,7 @@ typedef struct { /*!< (@ 0x40001000) RADIO Struct __IM uint32_t RESERVED16[3]; __IOM uint32_t SFD; /*!< (@ 0x00000660) IEEE 802.15.4 start of frame delimiter */ __IOM uint32_t EDCNT; /*!< (@ 0x00000664) IEEE 802.15.4 energy detect loop count */ - __IOM uint32_t EDSAMPLE; /*!< (@ 0x00000668) IEEE 802.15.4 energy detect level */ + __IM uint32_t EDSAMPLE; /*!< (@ 0x00000668) IEEE 802.15.4 energy detect level */ __IOM uint32_t CCACTRL; /*!< (@ 0x0000066C) IEEE 802.15.4 clear channel assessment control */ __IM uint32_t RESERVED17[164]; __IOM uint32_t DFEMODE; /*!< (@ 0x00000900) Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure @@ -1608,11 +1611,11 @@ typedef struct { /*!< (@ 0x4000F000) AAR Structur /** - * @brief AES CCM Mode Encryption (CCM) + * @brief AES CCM mode encryption (CCM) */ typedef struct { /*!< (@ 0x4000F000) CCM Structure */ - __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. This operation + __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of keystream. This operation will stop by itself when completed. */ __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will stop by itself when completed. */ @@ -1621,7 +1624,7 @@ typedef struct { /*!< (@ 0x4000F000) CCM Structur the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */ __IM uint32_t RESERVED[60]; - __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Key-stream generation complete */ + __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Keystream generation complete */ __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */ __IM uint32_t RESERVED1[61]; @@ -1634,13 +1637,13 @@ typedef struct { /*!< (@ 0x4000F000) CCM Structur __IM uint32_t RESERVED4[63]; __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ - __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding AES key and - NONCE vector */ + __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding the AES key + and the NONCE vector */ __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ - __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of key-stream generated when MODE.LENGTH - = Extended. */ + __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of keystream generated when MODE.LENGTH + = Extended */ __IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */ } NRF_CCM_Type; /*!< Size = 1312 (0x520) */ @@ -1769,7 +1772,7 @@ typedef struct { /*!< (@ 0x40013000) COMP Structu /** - * @brief Event Generator Unit 0 (EGU0) + * @brief Event generator unit 0 (EGU0) */ typedef struct { /*!< (@ 0x40014000) EGU0 Structure */ @@ -1965,8 +1968,8 @@ typedef struct { /*!< (@ 0x4001F000) PPI Structur #define NRF_FICR_BASE 0x10000000UL #define NRF_UICR_BASE 0x10001000UL -#define NRF_BPROT_BASE 0x40000000UL #define NRF_APPROTECT_BASE 0x40000000UL +#define NRF_BPROT_BASE 0x40000000UL #define NRF_CLOCK_BASE 0x40000000UL #define NRF_POWER_BASE 0x40000000UL #define NRF_P0_BASE 0x50000000UL @@ -2024,8 +2027,8 @@ typedef struct { /*!< (@ 0x4001F000) PPI Structur #define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) #define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) -#define NRF_BPROT ((NRF_BPROT_Type*) NRF_BPROT_BASE) #define NRF_APPROTECT ((NRF_APPROTECT_Type*) NRF_APPROTECT_BASE) +#define NRF_BPROT ((NRF_BPROT_Type*) NRF_BPROT_BASE) #define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) #define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) #define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) diff --git a/mdk/nrf52811.svd b/mdk/nrf52811.svd index 2f12943631..7b8db95963 100644 --- a/mdk/nrf52811.svd +++ b/mdk/nrf52811.svd @@ -405,7 +405,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Slope definition A0 0x000 read-only - 0x00000320 + 0xFFFFFFFF A @@ -420,7 +420,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Slope definition A1 0x004 read-only - 0x00000343 + 0xFFFFFFFF A @@ -435,7 +435,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Slope definition A2 0x008 read-only - 0x0000035D + 0xFFFFFFFF A @@ -450,7 +450,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Slope definition A3 0x00C read-only - 0x00000400 + 0xFFFFFFFF A @@ -465,7 +465,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Slope definition A4 0x010 read-only - 0x00000452 + 0xFFFFFFFF A @@ -480,7 +480,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Slope definition A5 0x014 read-only - 0x0000037B + 0xFFFFFFFF A @@ -495,7 +495,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Y-intercept B0 0x018 read-only - 0x00003FCC + 0xFFFFFFFF B @@ -510,7 +510,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Y-intercept B1 0x01C read-only - 0x00003F98 + 0xFFFFFFFF B @@ -525,7 +525,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Y-intercept B2 0x020 read-only - 0x00003F98 + 0xFFFFFFFF B @@ -540,7 +540,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Y-intercept B3 0x024 read-only - 0x00000012 + 0xFFFFFFFF B @@ -555,7 +555,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Y-intercept B4 0x028 read-only - 0x0000004D + 0xFFFFFFFF B @@ -570,7 +570,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Y-intercept B5 0x02C read-only - 0x00003E10 + 0xFFFFFFFF B @@ -585,7 +585,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Segment end T0 0x030 read-only - 0x000000E2 + 0xFFFFFFFF T @@ -600,7 +600,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Segment end T1 0x034 read-only - 0x00000000 + 0xFFFFFFFF T @@ -615,7 +615,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Segment end T2 0x038 read-only - 0x00000014 + 0xFFFFFFFF T @@ -630,7 +630,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Segment end T3 0x03C read-only - 0x00000019 + 0xFFFFFFFF T @@ -645,7 +645,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Segment end T4 0x040 read-only - 0x00000050 + 0xFFFFFFFF T @@ -721,6 +721,23 @@ POSSIBILITY OF SUCH DAMAGE.\n + + 0x8 + 0x4 + NRFMDK[%s] + Description collection: Reserved for Nordic MDK + 0x100 + read-write + 0xFFFFFFFF + + + NRFMDK + Reserved for Nordic MDK + 0 + 31 + + + 0x2 0x4 @@ -771,9 +788,14 @@ POSSIBILITY OF SUCH DAMAGE.\n Disabled - Disable + Hardware disable of access port protection for devices where access port protection is controlled by hardware 0xFF + + HwDisabled + Hardware disable of access port protection for devices where access port protection is controlled by hardware and software + 0x5A + Enabled Enable @@ -785,10 +807,70 @@ POSSIBILITY OF SUCH DAMAGE.\n + + APPROTECT + Access Port Protection + 0x40000000 + + 0 + 0x1000 + registers + + APPROTECT + 0x20 + + + FORCEPROTECT + Software force enable APPROTECT mechanism until next reset. + 0x550 + read-writeonce + 0xFFFFFFFF + + + FORCEPROTECT + Write 0x0 to force enable APPROTECT mechanism + 0 + 7 + + write + + Force + Software force enable APPROTECT mechanism + 0x0 + + + + + + + DISABLE + Software disable APPROTECT mechanism + 0x558 + read-write + 0x00000000 + + + DISABLE + Software disable APPROTECT mechanism + 0 + 7 + + + SwDisable + Software disable APPROTECT mechanism + 0x5A + + + + + + + BPROT Block Protect 0x40000000 + APPROTECT 0 0x1000 @@ -1706,71 +1788,11 @@ POSSIBILITY OF SUCH DAMAGE.\n - - APPROTECT - Only for emulation on devices that support hardened AP-PROTECT. - 0x40000000 - BPROT - - 0 - 0x1000 - registers - - APPROTECT - 0x20 - - - FORCEPROTECT - Software force enable APPROTECT mechanism until next reset. - 0x550 - read-writeonce - 0xFFFFFFFF - - - FORCEPROTECT - Write 0x0 to force enable APPROTECT mechanism - 0 - 7 - - write - - Force - Software force enable APPROTECT mechanism - 0x0 - - - - - - - DISABLE - Software disable APPROTECT mechanism - 0x558 - read-write - 0x00000000 - - - DISABLE - Software disable APPROTECT mechanism - 0 - 7 - - - SwDisable - Software disable APPROTECT mechanism - 0x5A - - - - - - - CLOCK Clock control 0x40000000 - BPROT + APPROTECT 0 0x1000 @@ -2529,7 +2551,7 @@ POSSIBILITY OF SUCH DAMAGE.\n POWER Power control 0x40000000 - BPROT + APPROTECT 0 0x1000 @@ -9952,13 +9974,13 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_EDEND - Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register + Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. 0x13C read-write EVENTS_EDEND - Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register + Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. 0 0 @@ -10184,15 +10206,41 @@ POSSIBILITY OF SUCH DAMAGE.\n + + EVENTS_SYNC + Preamble indicator + 0x168 + read-write + + + EVENTS_SYNC + Preamble indicator + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + EVENTS_PHYEND - Generated when last bit is sent on air + Generated when last bit is sent on air, or received from air 0x16C read-write EVENTS_PHYEND - Generated when last bit is sent on air + Generated when last bit is sent on air, or received from air 0 0 @@ -11159,6 +11207,33 @@ POSSIBILITY OF SUCH DAMAGE.\n + + SYNC + Write '1' to enable interrupt for event SYNC + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + PHYEND Write '1' to enable interrupt for event PHYEND @@ -11788,6 +11863,33 @@ POSSIBILITY OF SUCH DAMAGE.\n + + SYNC + Write '1' to disable interrupt for event SYNC + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + PHYEND Write '1' to disable interrupt for event PHYEND @@ -11944,12 +12046,12 @@ POSSIBILITY OF SUCH DAMAGE.\n LR125kbit - Frame is received at 125kbps + Frame is received at 125 kbps 0 LR500kbit - Frame is received at 500kbps + Frame is received at 500 kbps 1 @@ -12076,7 +12178,7 @@ POSSIBILITY OF SUCH DAMAGE.\n MAP - Channel map selection. + Channel map selection 8 8 @@ -12219,19 +12321,19 @@ POSSIBILITY OF SUCH DAMAGE.\n LFLEN - Length on air of LENGTH field in number of bits. + Length on air of LENGTH field in number of bits 0 3 S0LEN - Length on air of S0 field in number of bytes. + Length on air of S0 field in number of bytes 8 8 S1LEN - Length on air of S1 field in number of bits. + Length on air of S1 field in number of bits 16 19 @@ -12641,7 +12743,7 @@ POSSIBILITY OF SUCH DAMAGE.\n LEN - CRC length in number of bytes. + CRC length in number of bytes For MODE Ble_LR125Kbit and Ble_LR500Kbit, only LEN set to 3 is supported 0 1 @@ -12729,7 +12831,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TIFS - Interframe spacing in us + Interframe spacing in us. 0 9 @@ -12743,7 +12845,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RSSISAMPLE - RSSI sample + RSSI sample. 0 6 @@ -13119,7 +13221,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Fast - Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information + Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specifications for more information 1 @@ -13183,7 +13285,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EDSAMPLE IEEE 802.15.4 energy detect level 0x668 - read-write + read-only 0x00000000 @@ -13355,93 +13457,93 @@ POSSIBILITY OF SUCH DAMAGE.\n 20 - 20 in 8us unit (default) Set to 20 if parsed CTETime is larger han 20 + 20 in 8 us unit (default) Set to 20 if parsed CTETime is larger than 20 0 31 - 31 in 8us unit + 31 in 8 us unit 1 63 - 63 in 8us unit + 63 in 8 us unit 2 CTEINLINERXMODE1US - Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set + Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. 10 12 4us - 4us + 4 us 1 2us - 2us + 2 us 2 1us - 1us + 1 us 3 500ns - 0.5us + 0.5 us 4 250ns - 0.25us + 0.25 us 5 125ns - 0.125us + 0.125 us 6 CTEINLINERXMODE2US - Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set + Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. 13 15 4us - 4us + 4 us 1 2us - 2us + 2 us 2 1us - 1us + 1 us 3 500ns - 0.5us + 0.5 us 4 250ns - 0.25us + 0.25 us 5 125ns - 0.125us + 0.125 us 6 @@ -13499,17 +13601,17 @@ POSSIBILITY OF SUCH DAMAGE.\n 4us - 4us + 4 us 1 2us - 2us + 2 us 2 1us - 1us + 1 us 3 @@ -13522,32 +13624,32 @@ POSSIBILITY OF SUCH DAMAGE.\n 4us - 4us + 4 us 1 2us - 2us + 2 us 2 1us - 1us + 1 us 3 500ns - 0.5us + 0.5 us 4 250ns - 0.25us + 0.25 us 5 125ns - 0.125us + 0.125 us 6 @@ -13578,32 +13680,32 @@ POSSIBILITY OF SUCH DAMAGE.\n 4us - 4us + 4 us 1 2us - 2us + 2 us 2 1us - 1us + 1 us 3 500ns - 0.5us + 0.5 us 4 250ns - 0.25us + 0.25 us 5 125ns - 0.125us + 0.125 us 6 @@ -13646,7 +13748,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SWITCHPATTERN - Fill array of GPIO patterns for antenna control + Fill array of GPIO patterns for antenna control. 0 7 @@ -28767,7 +28869,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CCM - AES CCM Mode Encryption + AES CCM mode encryption 0x4000F000 AAR @@ -28784,13 +28886,13 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_KSGEN - Start generation of key-stream. This operation will stop by itself when completed. + Start generation of keystream. This operation will stop by itself when completed. 0x000 write-only TASKS_KSGEN - Start generation of key-stream. This operation will stop by itself when completed. + Start generation of keystream. This operation will stop by itself when completed. 0 0 @@ -28868,13 +28970,13 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_ENDKSGEN - Key-stream generation complete + Keystream generation complete 0x100 read-write EVENTS_ENDKSGEN - Key-stream generation complete + Keystream generation complete 0 0 @@ -29209,7 +29311,7 @@ POSSIBILITY OF SUCH DAMAGE.\n MODE - The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. + The mode of operation to be used. Settings in this register apply whenever either the KSGEN task or the CRYPT task is triggered. 0 0 @@ -29243,12 +29345,12 @@ POSSIBILITY OF SUCH DAMAGE.\n 125Kbps - 125 Kbps + 125 kbps 2 500Kbps - 500 Kbps + 500 kbps 3 @@ -29261,12 +29363,12 @@ POSSIBILITY OF SUCH DAMAGE.\n Default - Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated. + Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A keystream for packet payloads up to 27 bytes will be generated. 0 Extended - Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated. + Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A keystream for packet payloads up to MAXPACKETSIZE bytes will be generated. 1 @@ -29275,13 +29377,13 @@ POSSIBILITY OF SUCH DAMAGE.\n CNFPTR - Pointer to data structure holding AES key and NONCE vector + Pointer to data structure holding the AES key and the NONCE vector 0x508 read-write CNFPTR - Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) + Pointer to the data structure holding the AES key and the CCM NONCE vector (see table CCM data structure overview) 0 31 @@ -29323,7 +29425,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SCRATCHPTR - Pointer to a scratch data area used for temporary storage during key-stream generation, + Pointer to a scratch data area used for temporary storage during keystream generation, MIC generation and encryption/decryption. 0 31 @@ -29332,14 +29434,14 @@ POSSIBILITY OF SUCH DAMAGE.\n MAXPACKETSIZE - Length of key-stream generated when MODE.LENGTH = Extended. + Length of keystream generated when MODE.LENGTH = Extended 0x518 read-write 0x000000FB MAXPACKETSIZE - Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. + Length of keystream generated when MODE.LENGTH = Extended. This value must be greater than or equal to the subsequent packet payload to be encrypted/decrypted. 0 7 @@ -29354,7 +29456,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RATEOVERRIDE - Data rate override setting. + Data rate override setting 0 1 @@ -29370,12 +29472,12 @@ POSSIBILITY OF SUCH DAMAGE.\n 125Kbps - 125 Kbps + 125 kbps 2 500Kbps - 500 Kbps + 500 kbps 3 @@ -31919,7 +32021,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EGU0 - Event Generator Unit 0 + Event generator unit 0 0x40014000 EGU @@ -33192,7 +33294,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EGU1 - Event Generator Unit 1 + Event generator unit 1 0x40015000 SWI1_EGU1 diff --git a/mdk/nrf52811_bitfields.h b/mdk/nrf52811_bitfields.h index d24a16b31d..e1946bf7fb 100644 --- a/mdk/nrf52811_bitfields.h +++ b/mdk/nrf52811_bitfields.h @@ -177,7 +177,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: APPROTECT */ -/* Description: Only for emulation on devices that support hardened AP-PROTECT. */ +/* Description: Access Port Protection */ /* Register: APPROTECT_FORCEPROTECT */ /* Description: Software force enable APPROTECT mechanism until next reset. */ @@ -504,12 +504,12 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: CCM */ -/* Description: AES CCM Mode Encryption */ +/* Description: AES CCM mode encryption */ /* Register: CCM_TASKS_KSGEN */ -/* Description: Start generation of key-stream. This operation will stop by itself when completed. */ +/* Description: Start generation of keystream. This operation will stop by itself when completed. */ -/* Bit 0 : Start generation of key-stream. This operation will stop by itself when completed. */ +/* Bit 0 : Start generation of keystream. This operation will stop by itself when completed. */ #define CCM_TASKS_KSGEN_TASKS_KSGEN_Pos (0UL) /*!< Position of TASKS_KSGEN field. */ #define CCM_TASKS_KSGEN_TASKS_KSGEN_Msk (0x1UL << CCM_TASKS_KSGEN_TASKS_KSGEN_Pos) /*!< Bit mask of TASKS_KSGEN field. */ #define CCM_TASKS_KSGEN_TASKS_KSGEN_Trigger (1UL) /*!< Trigger task */ @@ -539,9 +539,9 @@ POSSIBILITY OF SUCH DAMAGE. #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Trigger (1UL) /*!< Trigger task */ /* Register: CCM_EVENTS_ENDKSGEN */ -/* Description: Key-stream generation complete */ +/* Description: Keystream generation complete */ -/* Bit 0 : Key-stream generation complete */ +/* Bit 0 : Keystream generation complete */ #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos (0UL) /*!< Position of EVENTS_ENDKSGEN field. */ #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Msk (0x1UL << CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos) /*!< Bit mask of EVENTS_ENDKSGEN field. */ #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_NotGenerated (0UL) /*!< Event not generated */ @@ -646,27 +646,27 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 24 : Packet length configuration */ #define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */ #define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */ -#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated. */ -#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated. */ +#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A keystream for packet payloads up to 27 bytes will be generated. */ +#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A keystream for packet payloads up to MAXPACKETSIZE bytes will be generated. */ /* Bits 17..16 : Radio data rate that the CCM shall run synchronous with */ #define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */ #define CCM_MODE_DATARATE_Msk (0x3UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */ #define CCM_MODE_DATARATE_1Mbit (0UL) /*!< 1 Mbps */ #define CCM_MODE_DATARATE_2Mbit (1UL) /*!< 2 Mbps */ -#define CCM_MODE_DATARATE_125Kbps (2UL) /*!< 125 Kbps */ -#define CCM_MODE_DATARATE_500Kbps (3UL) /*!< 500 Kbps */ +#define CCM_MODE_DATARATE_125Kbps (2UL) /*!< 125 kbps */ +#define CCM_MODE_DATARATE_500Kbps (3UL) /*!< 500 kbps */ -/* Bit 0 : The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. */ +/* Bit 0 : The mode of operation to be used. Settings in this register apply whenever either the KSGEN task or the CRYPT task is triggered. */ #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ #define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ #define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */ #define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */ /* Register: CCM_CNFPTR */ -/* Description: Pointer to data structure holding AES key and NONCE vector */ +/* Description: Pointer to data structure holding the AES key and the NONCE vector */ -/* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */ +/* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see table CCM data structure overview) */ #define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */ #define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */ @@ -687,28 +687,28 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CCM_SCRATCHPTR */ /* Description: Pointer to data area used for temporary storage */ -/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, +/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during keystream generation, MIC generation and encryption/decryption. */ #define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ #define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ /* Register: CCM_MAXPACKETSIZE */ -/* Description: Length of key-stream generated when MODE.LENGTH = Extended. */ +/* Description: Length of keystream generated when MODE.LENGTH = Extended */ -/* Bits 7..0 : Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. */ +/* Bits 7..0 : Length of keystream generated when MODE.LENGTH = Extended. This value must be greater than or equal to the subsequent packet payload to be encrypted/decrypted. */ #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos (0UL) /*!< Position of MAXPACKETSIZE field. */ #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Msk (0xFFUL << CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) /*!< Bit mask of MAXPACKETSIZE field. */ /* Register: CCM_RATEOVERRIDE */ /* Description: Data rate override setting. */ -/* Bits 1..0 : Data rate override setting. */ +/* Bits 1..0 : Data rate override setting */ #define CCM_RATEOVERRIDE_RATEOVERRIDE_Pos (0UL) /*!< Position of RATEOVERRIDE field. */ #define CCM_RATEOVERRIDE_RATEOVERRIDE_Msk (0x3UL << CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) /*!< Bit mask of RATEOVERRIDE field. */ #define CCM_RATEOVERRIDE_RATEOVERRIDE_1Mbit (0UL) /*!< 1 Mbps */ #define CCM_RATEOVERRIDE_RATEOVERRIDE_2Mbit (1UL) /*!< 2 Mbps */ -#define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (2UL) /*!< 125 Kbps */ -#define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (3UL) /*!< 500 Kbps */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (2UL) /*!< 125 kbps */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (3UL) /*!< 500 kbps */ /* Peripheral: CLOCK */ @@ -1319,7 +1319,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: EGU */ -/* Description: Event Generator Unit 0 */ +/* Description: Event generator unit 0 */ /* Register: EGU_TASKS_TRIGGER */ /* Description: Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event */ @@ -6211,9 +6211,9 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_EDEND */ -/* Description: Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register */ +/* Description: Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */ -/* Bit 0 : Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register */ +/* Bit 0 : Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */ #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos (0UL) /*!< Position of EVENTS_EDEND field. */ #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Msk (0x1UL << RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos) /*!< Bit mask of EVENTS_EDEND field. */ #define RADIO_EVENTS_EDEND_EVENTS_EDEND_NotGenerated (0UL) /*!< Event not generated */ @@ -6291,10 +6291,19 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_NotGenerated (0UL) /*!< Event not generated */ #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Generated (1UL) /*!< Event generated */ +/* Register: RADIO_EVENTS_SYNC */ +/* Description: Preamble indicator */ + +/* Bit 0 : Preamble indicator */ +#define RADIO_EVENTS_SYNC_EVENTS_SYNC_Pos (0UL) /*!< Position of EVENTS_SYNC field. */ +#define RADIO_EVENTS_SYNC_EVENTS_SYNC_Msk (0x1UL << RADIO_EVENTS_SYNC_EVENTS_SYNC_Pos) /*!< Bit mask of EVENTS_SYNC field. */ +#define RADIO_EVENTS_SYNC_EVENTS_SYNC_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_SYNC_EVENTS_SYNC_Generated (1UL) /*!< Event generated */ + /* Register: RADIO_EVENTS_PHYEND */ -/* Description: Generated when last bit is sent on air */ +/* Description: Generated when last bit is sent on air, or received from air */ -/* Bit 0 : Generated when last bit is sent on air */ +/* Bit 0 : Generated when last bit is sent on air, or received from air */ #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos (0UL) /*!< Position of EVENTS_PHYEND field. */ #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Msk (0x1UL << RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos) /*!< Bit mask of EVENTS_PHYEND field. */ #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_NotGenerated (0UL) /*!< Event not generated */ @@ -6443,6 +6452,13 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_INTENSET_PHYEND_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_PHYEND_Set (1UL) /*!< Enable */ +/* Bit 26 : Write '1' to enable interrupt for event SYNC */ +#define RADIO_INTENSET_SYNC_Pos (26UL) /*!< Position of SYNC field. */ +#define RADIO_INTENSET_SYNC_Msk (0x1UL << RADIO_INTENSET_SYNC_Pos) /*!< Bit mask of SYNC field. */ +#define RADIO_INTENSET_SYNC_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_SYNC_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_SYNC_Set (1UL) /*!< Enable */ + /* Bit 23 : Write '1' to enable interrupt for event MHRMATCH */ #define RADIO_INTENSET_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */ #define RADIO_INTENSET_MHRMATCH_Msk (0x1UL << RADIO_INTENSET_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ @@ -6607,6 +6623,13 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_INTENCLR_PHYEND_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_PHYEND_Clear (1UL) /*!< Disable */ +/* Bit 26 : Write '1' to disable interrupt for event SYNC */ +#define RADIO_INTENCLR_SYNC_Pos (26UL) /*!< Position of SYNC field. */ +#define RADIO_INTENCLR_SYNC_Msk (0x1UL << RADIO_INTENCLR_SYNC_Pos) /*!< Bit mask of SYNC field. */ +#define RADIO_INTENCLR_SYNC_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_SYNC_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_SYNC_Clear (1UL) /*!< Disable */ + /* Bit 23 : Write '1' to disable interrupt for event MHRMATCH */ #define RADIO_INTENCLR_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */ #define RADIO_INTENCLR_MHRMATCH_Msk (0x1UL << RADIO_INTENCLR_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ @@ -6790,8 +6813,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 2..1 : Status on what rate packet is received with in Long Range */ #define RADIO_PDUSTAT_CISTAT_Pos (1UL) /*!< Position of CISTAT field. */ #define RADIO_PDUSTAT_CISTAT_Msk (0x3UL << RADIO_PDUSTAT_CISTAT_Pos) /*!< Bit mask of CISTAT field. */ -#define RADIO_PDUSTAT_CISTAT_LR125kbit (0UL) /*!< Frame is received at 125kbps */ -#define RADIO_PDUSTAT_CISTAT_LR500kbit (1UL) /*!< Frame is received at 500kbps */ +#define RADIO_PDUSTAT_CISTAT_LR125kbit (0UL) /*!< Frame is received at 125 kbps */ +#define RADIO_PDUSTAT_CISTAT_LR500kbit (1UL) /*!< Frame is received at 500 kbps */ /* Bit 0 : Status on payload length vs. PCNF1.MAXLEN */ #define RADIO_PDUSTAT_PDUSTAT_Pos (0UL) /*!< Position of PDUSTAT field. */ @@ -6843,7 +6866,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_FREQUENCY */ /* Description: Frequency */ -/* Bit 8 : Channel map selection. */ +/* Bit 8 : Channel map selection */ #define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */ #define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */ #define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */ @@ -6915,15 +6938,15 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN > 0 */ #define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */ -/* Bits 19..16 : Length on air of S1 field in number of bits. */ +/* Bits 19..16 : Length on air of S1 field in number of bits */ #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */ #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */ -/* Bit 8 : Length on air of S0 field in number of bytes. */ +/* Bit 8 : Length on air of S0 field in number of bytes */ #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */ #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */ -/* Bits 3..0 : Length on air of LENGTH field in number of bits. */ +/* Bits 3..0 : Length on air of LENGTH field in number of bits */ #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */ #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */ @@ -7074,7 +7097,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */ #define RADIO_CRCCNF_SKIPADDR_Ieee802154 (2UL) /*!< CRC calculation as per 802.15.4 standard. Starting at first byte after length field. */ -/* Bits 1..0 : CRC length in number of bytes. */ +/* Bits 1..0 : CRC length in number of bytes For MODE Ble_LR125Kbit and Ble_LR500Kbit, only LEN set to 3 is supported */ #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */ #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */ #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */ @@ -7099,14 +7122,14 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_TIFS */ /* Description: Interframe spacing in us */ -/* Bits 9..0 : Interframe spacing in us */ +/* Bits 9..0 : Interframe spacing in us. */ #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */ #define RADIO_TIFS_TIFS_Msk (0x3FFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */ /* Register: RADIO_RSSISAMPLE */ /* Description: RSSI sample */ -/* Bits 6..0 : RSSI sample */ +/* Bits 6..0 : RSSI sample. */ #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */ #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */ @@ -7265,7 +7288,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */ #define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */ #define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 */ -#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information */ +#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specifications for more information */ /* Register: RADIO_SFD */ /* Description: IEEE 802.15.4 start of frame delimiter */ @@ -7333,32 +7356,32 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_CTEINLINECONF_S0CONF_Pos (16UL) /*!< Position of S0CONF field. */ #define RADIO_CTEINLINECONF_S0CONF_Msk (0xFFUL << RADIO_CTEINLINECONF_S0CONF_Pos) /*!< Bit mask of S0CONF field. */ -/* Bits 15..13 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set */ +/* Bits 15..13 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. */ #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos (13UL) /*!< Position of CTEINLINERXMODE2US field. */ #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos) /*!< Bit mask of CTEINLINERXMODE2US field. */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_4us (1UL) /*!< 4us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_2us (2UL) /*!< 2us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_1us (3UL) /*!< 1us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_500ns (4UL) /*!< 0.5us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_250ns (5UL) /*!< 0.25us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_125ns (6UL) /*!< 0.125us */ - -/* Bits 12..10 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_4us (1UL) /*!< 4 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_2us (2UL) /*!< 2 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_1us (3UL) /*!< 1 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_500ns (4UL) /*!< 0.5 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_250ns (5UL) /*!< 0.25 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_125ns (6UL) /*!< 0.125 us */ + +/* Bits 12..10 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. */ #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos (10UL) /*!< Position of CTEINLINERXMODE1US field. */ #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos) /*!< Bit mask of CTEINLINERXMODE1US field. */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_4us (1UL) /*!< 4us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_2us (2UL) /*!< 2us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_1us (3UL) /*!< 1us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_500ns (4UL) /*!< 0.5us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_250ns (5UL) /*!< 0.25us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_125ns (6UL) /*!< 0.125us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_4us (1UL) /*!< 4 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_2us (2UL) /*!< 2 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_1us (3UL) /*!< 1 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_500ns (4UL) /*!< 0.5 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_250ns (5UL) /*!< 0.25 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_125ns (6UL) /*!< 0.125 us */ /* Bits 7..6 : Max range of CTETime */ #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos (6UL) /*!< Position of CTETIMEVALIDRANGE field. */ #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Msk (0x3UL << RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos) /*!< Bit mask of CTETIMEVALIDRANGE field. */ -#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_20 (0UL) /*!< 20 in 8us unit (default) Set to 20 if parsed CTETime is larger han 20 */ -#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_31 (1UL) /*!< 31 in 8us unit */ -#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_63 (2UL) /*!< 63 in 8us unit */ +#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_20 (0UL) /*!< 20 in 8 us unit (default) Set to 20 if parsed CTETime is larger than 20 */ +#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_31 (1UL) /*!< 31 in 8 us unit */ +#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_63 (2UL) /*!< 63 in 8 us unit */ /* Bit 4 : Sampling/switching if CRC is not OK */ #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Pos (4UL) /*!< Position of CTEERRORHANDLING field. */ @@ -7388,12 +7411,12 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 18..16 : Interval between samples in the SWITCHING period when CTEINLINECTRLEN is 0 */ #define RADIO_DFECTRL1_TSAMPLESPACING_Pos (16UL) /*!< Position of TSAMPLESPACING field. */ #define RADIO_DFECTRL1_TSAMPLESPACING_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACING_Pos) /*!< Bit mask of TSAMPLESPACING field. */ -#define RADIO_DFECTRL1_TSAMPLESPACING_4us (1UL) /*!< 4us */ -#define RADIO_DFECTRL1_TSAMPLESPACING_2us (2UL) /*!< 2us */ -#define RADIO_DFECTRL1_TSAMPLESPACING_1us (3UL) /*!< 1us */ -#define RADIO_DFECTRL1_TSAMPLESPACING_500ns (4UL) /*!< 0.5us */ -#define RADIO_DFECTRL1_TSAMPLESPACING_250ns (5UL) /*!< 0.25us */ -#define RADIO_DFECTRL1_TSAMPLESPACING_125ns (6UL) /*!< 0.125us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_4us (1UL) /*!< 4 us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_2us (2UL) /*!< 2 us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_1us (3UL) /*!< 1 us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_500ns (4UL) /*!< 0.5 us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_250ns (5UL) /*!< 0.25 us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_125ns (6UL) /*!< 0.125 us */ /* Bit 15 : Whether to sample I/Q or magnitude/phase */ #define RADIO_DFECTRL1_SAMPLETYPE_Pos (15UL) /*!< Position of SAMPLETYPE field. */ @@ -7404,19 +7427,19 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 14..12 : Interval between samples in the REFERENCE period */ #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos (12UL) /*!< Position of TSAMPLESPACINGREF field. */ #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos) /*!< Bit mask of TSAMPLESPACINGREF field. */ -#define RADIO_DFECTRL1_TSAMPLESPACINGREF_4us (1UL) /*!< 4us */ -#define RADIO_DFECTRL1_TSAMPLESPACINGREF_2us (2UL) /*!< 2us */ -#define RADIO_DFECTRL1_TSAMPLESPACINGREF_1us (3UL) /*!< 1us */ -#define RADIO_DFECTRL1_TSAMPLESPACINGREF_500ns (4UL) /*!< 0.5us */ -#define RADIO_DFECTRL1_TSAMPLESPACINGREF_250ns (5UL) /*!< 0.25us */ -#define RADIO_DFECTRL1_TSAMPLESPACINGREF_125ns (6UL) /*!< 0.125us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_4us (1UL) /*!< 4 us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_2us (2UL) /*!< 2 us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_1us (3UL) /*!< 1 us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_500ns (4UL) /*!< 0.5 us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_250ns (5UL) /*!< 0.25 us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_125ns (6UL) /*!< 0.125 us */ /* Bits 10..8 : Interval between every time the antenna is changed in the SWITCHING state */ #define RADIO_DFECTRL1_TSWITCHSPACING_Pos (8UL) /*!< Position of TSWITCHSPACING field. */ #define RADIO_DFECTRL1_TSWITCHSPACING_Msk (0x7UL << RADIO_DFECTRL1_TSWITCHSPACING_Pos) /*!< Bit mask of TSWITCHSPACING field. */ -#define RADIO_DFECTRL1_TSWITCHSPACING_4us (1UL) /*!< 4us */ -#define RADIO_DFECTRL1_TSWITCHSPACING_2us (2UL) /*!< 2us */ -#define RADIO_DFECTRL1_TSWITCHSPACING_1us (3UL) /*!< 1us */ +#define RADIO_DFECTRL1_TSWITCHSPACING_4us (1UL) /*!< 4 us */ +#define RADIO_DFECTRL1_TSWITCHSPACING_2us (2UL) /*!< 2 us */ +#define RADIO_DFECTRL1_TSWITCHSPACING_1us (3UL) /*!< 1 us */ /* Bit 7 : Add CTE extension and do antenna switching/sampling in this extension */ #define RADIO_DFECTRL1_DFEINEXTENSION_Pos (7UL) /*!< Position of DFEINEXTENSION field. */ @@ -7442,7 +7465,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_SWITCHPATTERN */ /* Description: GPIO patterns to be used for each antenna */ -/* Bits 7..0 : Fill array of GPIO patterns for antenna control */ +/* Bits 7..0 : Fill array of GPIO patterns for antenna control. */ #define RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos (0UL) /*!< Position of SWITCHPATTERN field. */ #define RADIO_SWITCHPATTERN_SWITCHPATTERN_Msk (0xFFUL << RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos) /*!< Bit mask of SWITCHPATTERN field. */ @@ -11839,6 +11862,13 @@ POSSIBILITY OF SUCH DAMAGE. #define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */ #define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */ +/* Register: UICR_NRFMDK */ +/* Description: Description collection: Reserved for Nordic MDK */ + +/* Bits 31..0 : Reserved for Nordic MDK */ +#define UICR_NRFMDK_NRFMDK_Pos (0UL) /*!< Position of NRFMDK field. */ +#define UICR_NRFMDK_NRFMDK_Msk (0xFFFFFFFFUL << UICR_NRFMDK_NRFMDK_Pos) /*!< Bit mask of NRFMDK field. */ + /* Register: UICR_PSELRESET */ /* Description: Description collection: Mapping of the nRESET function (see POWER chapter for details) */ @@ -11859,7 +11889,8 @@ POSSIBILITY OF SUCH DAMAGE. #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ #define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ #define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */ -#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */ +#define UICR_APPROTECT_PALL_HwDisabled (0x5AUL) /*!< Hardware disable of access port protection for devices where access port protection is controlled by hardware and software */ +#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Hardware disable of access port protection for devices where access port protection is controlled by hardware */ /* Peripheral: WDT */ diff --git a/mdk/nrf52820.h b/mdk/nrf52820.h index b2c42a12db..dfa23f1673 100644 --- a/mdk/nrf52820.h +++ b/mdk/nrf52820.h @@ -32,10 +32,10 @@ * @file nrf52820.h * @brief CMSIS HeaderFile * @version 1 - * @date 29. April 2021 - * @note Generated by SVDConv V3.3.35 on Thursday, 29.04.2021 12:43:44 + * @date 19. November 2021 + * @note Generated by SVDConv V3.3.35 on Friday, 19.11.2021 12:44:59 * from File 'nrf52820.svd', - * last modified on Thursday, 29.04.2021 10:43:41 + * last modified on Friday, 19.11.2021 11:44:55 */ @@ -450,8 +450,8 @@ typedef struct { __IOM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Start address of region to protect. The start address must be word-aligned. */ __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Size of region to protect - counting from address ACL[n].ADDR. Write - '0' as no effect. */ + counting from address ACL[n].ADDR. Writing + a '0' has no effect. */ __IOM uint32_t PERM; /*!< (@ 0x00000008) Description cluster: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE */ @@ -1569,7 +1569,7 @@ typedef struct { /*!< (@ 0x4000F000) AAR Structur /** - * @brief AES CCM Mode Encryption (CCM) + * @brief AES CCM mode encryption (CCM) */ typedef struct { /*!< (@ 0x4000F000) CCM Structure */ @@ -1595,15 +1595,16 @@ typedef struct { /*!< (@ 0x4000F000) CCM Structur __IM uint32_t RESERVED4[63]; __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ - __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding AES key and - NONCE vector */ + __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding the AES key + and the NONCE vector */ __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of keystream generated when MODE.LENGTH - = Extended. */ + = Extended */ __IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */ -} NRF_CCM_Type; /*!< Size = 1312 (0x520) */ + __IOM uint32_t HEADERMASK; /*!< (@ 0x00000520) Header (S0) mask. */ +} NRF_CCM_Type; /*!< Size = 1316 (0x524) */ diff --git a/mdk/nrf52820.svd b/mdk/nrf52820.svd index 428c22d1e3..68c02e3c5a 100644 --- a/mdk/nrf52820.svd +++ b/mdk/nrf52820.svd @@ -273,6 +273,11 @@ POSSIBILITY OF SUCH DAMAGE.\n AAC1 0x41414331 + + AAD0 + AAD0 + 0x41414430 + Unspecified Unspecified @@ -324,27 +329,27 @@ POSSIBILITY OF SUCH DAMAGE.\n K16 - 16 kByte RAM + 16 kB RAM 0x10 K32 - 32 kByte RAM + 32 kB RAM 0x20 K64 - 64 kByte RAM + 64 kB RAM 0x40 K128 - 128 kByte RAM + 128 kB RAM 0x80 K256 - 256 kByte RAM + 256 kB RAM 0x100 @@ -371,27 +376,27 @@ POSSIBILITY OF SUCH DAMAGE.\n K128 - 128 kByte FLASH + 128 kB FLASH 0x80 K256 - 256 kByte FLASH + 256 kB FLASH 0x100 K512 - 512 kByte FLASH + 512 kB FLASH 0x200 K1024 - 1 MByte FLASH + 1 MB FLASH 0x400 K2048 - 2 MByte FLASH + 2 MB FLASH 0x800 @@ -12040,12 +12045,12 @@ POSSIBILITY OF SUCH DAMAGE.\n Default - Channel map between 2400 MHZ .. 2500 MHz + Channel map between 2400 MHz and 2500 MHz 0 Low - Channel map between 2360 MHZ .. 2460 MHz + Channel map between 2360 MHz and 2460 MHz 1 @@ -12177,12 +12182,12 @@ POSSIBILITY OF SUCH DAMAGE.\n Ble_LR125Kbit - Long range 125 kbps TX, 125 kbps and 500 kbps RX + Long Range 125 kbps TX, 125 kbps and 500 kbps RX 5 Ble_LR500Kbit - Long range 500 kbps TX, 125 kbps and 500 kbps RX + Long Range 500 kbps TX, 125 kbps and 500 kbps RX 6 @@ -12238,7 +12243,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CILEN - Length of code indicator - long range + Length of code indicator - Long Range 22 23 @@ -12265,7 +12270,7 @@ POSSIBILITY OF SUCH DAMAGE.\n LongRange - Preamble - used for BLE long range + Preamble - used for Bluetooth LE Long Range 3 @@ -13621,13 +13626,13 @@ POSSIBILITY OF SUCH DAMAGE.\n TSWITCHOFFSET - Signed value offset after the end of the CRC before starting switching in number of 16M cycles + Signed value offset after the end of the CRC before starting switching in number of 16 MHz clock cycles 0 12 TSAMPLEOFFSET - Signed value offset before starting sampling in number of 16M cycles relative to the beginning of the REFERENCE state - 12 us after switching start + Signed value offset in number of 16 MHz clock cycles for fine tuning of the sampling instant for all IQ samples. With TSAMPLEOFFSET=0 the first sample is taken immediately at the start of the reference period 16 27 @@ -26296,7 +26301,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CCM - AES CCM Mode Encryption + AES CCM mode encryption 0x4000F000 AAR @@ -26738,7 +26743,7 @@ POSSIBILITY OF SUCH DAMAGE.\n MODE - The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. + The mode of operation to be used. Settings in this register apply whenever either the KSGEN task or the CRYPT task is triggered. 0 0 @@ -26772,12 +26777,12 @@ POSSIBILITY OF SUCH DAMAGE.\n 125Kbps - 125 Kbps + 125 kbps 2 500Kbps - 500 Kbps + 500 kbps 3 @@ -26804,13 +26809,13 @@ POSSIBILITY OF SUCH DAMAGE.\n CNFPTR - Pointer to data structure holding AES key and NONCE vector + Pointer to data structure holding the AES key and the NONCE vector 0x508 read-write CNFPTR - Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) + Pointer to the data structure holding the AES key and the CCM NONCE vector (see table CCM data structure overview) 0 31 @@ -26861,14 +26866,14 @@ POSSIBILITY OF SUCH DAMAGE.\n MAXPACKETSIZE - Length of keystream generated when MODE.LENGTH = Extended. + Length of keystream generated when MODE.LENGTH = Extended 0x518 read-write 0x000000FB MAXPACKETSIZE - Length of keystream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. + Length of keystream generated when MODE.LENGTH = Extended. This value must be greater than or equal to the subsequent packet payload to be encrypted/decrypted. 0 7 @@ -26883,7 +26888,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RATEOVERRIDE - Data rate override setting. + Data rate override setting 0 1 @@ -26899,18 +26904,33 @@ POSSIBILITY OF SUCH DAMAGE.\n 125Kbps - 125 Kbps + 125 kbps 2 500Kbps - 500 Kbps + 500 kbps 3 + + HEADERMASK + Header (S0) mask. + 0x520 + read-write + 0x000000E3 + + + HEADERMASK + Header (S0) mask + 0 + 7 + + + @@ -30825,7 +30845,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SIZE - Description cluster: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. + Description cluster: Size of region to protect counting from address ACL[n].ADDR. Writing a '0' has no effect. 0x004 read-writeonce 0x00000000 @@ -30847,36 +30867,36 @@ POSSIBILITY OF SUCH DAMAGE.\n WRITE - Configure write and erase permissions for region n. Write '0' has no effect. + Configure write and erase permissions for region n. Writing a '0' has no effect. 1 1 Enable - Allow write and erase instructions to region n + Allow write and erase instructions to region n. 0 Disable - Block write and erase instructions to region n + Block write and erase instructions to region n. 1 READ - Configure read permissions for region n. Write '0' has no effect. + Configure read permissions for region n. Writing a '0' has no effect. 2 2 Enable - Allow read instructions to region n + Allow read instructions to region n. 0 Disable - Block read instructions to region n + Block read instructions to region n. 1 diff --git a/mdk/nrf52820_bitfields.h b/mdk/nrf52820_bitfields.h index 3c0d24d3e0..0501f1cf89 100644 --- a/mdk/nrf52820_bitfields.h +++ b/mdk/nrf52820_bitfields.h @@ -187,7 +187,7 @@ POSSIBILITY OF SUCH DAMAGE. #define ACL_ACL_ADDR_ADDR_Msk (0xFFFFFFFFUL << ACL_ACL_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */ /* Register: ACL_ACL_SIZE */ -/* Description: Description cluster: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. */ +/* Description: Description cluster: Size of region to protect counting from address ACL[n].ADDR. Writing a '0' has no effect. */ /* Bits 31..0 : Size of flash region n in bytes. Must be a multiple of the flash page size. */ #define ACL_ACL_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */ @@ -196,17 +196,17 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: ACL_ACL_PERM */ /* Description: Description cluster: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE */ -/* Bit 2 : Configure read permissions for region n. Write '0' has no effect. */ +/* Bit 2 : Configure read permissions for region n. Writing a '0' has no effect. */ #define ACL_ACL_PERM_READ_Pos (2UL) /*!< Position of READ field. */ #define ACL_ACL_PERM_READ_Msk (0x1UL << ACL_ACL_PERM_READ_Pos) /*!< Bit mask of READ field. */ -#define ACL_ACL_PERM_READ_Enable (0UL) /*!< Allow read instructions to region n */ -#define ACL_ACL_PERM_READ_Disable (1UL) /*!< Block read instructions to region n */ +#define ACL_ACL_PERM_READ_Enable (0UL) /*!< Allow read instructions to region n. */ +#define ACL_ACL_PERM_READ_Disable (1UL) /*!< Block read instructions to region n. */ -/* Bit 1 : Configure write and erase permissions for region n. Write '0' has no effect. */ +/* Bit 1 : Configure write and erase permissions for region n. Writing a '0' has no effect. */ #define ACL_ACL_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */ #define ACL_ACL_PERM_WRITE_Msk (0x1UL << ACL_ACL_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */ -#define ACL_ACL_PERM_WRITE_Enable (0UL) /*!< Allow write and erase instructions to region n */ -#define ACL_ACL_PERM_WRITE_Disable (1UL) /*!< Block write and erase instructions to region n */ +#define ACL_ACL_PERM_WRITE_Enable (0UL) /*!< Allow write and erase instructions to region n. */ +#define ACL_ACL_PERM_WRITE_Disable (1UL) /*!< Block write and erase instructions to region n. */ /* Peripheral: APPROTECT */ @@ -230,7 +230,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: CCM */ -/* Description: AES CCM Mode Encryption */ +/* Description: AES CCM mode encryption */ /* Register: CCM_TASKS_KSGEN */ /* Description: Start generation of keystream. This operation will stop by itself when completed. */ @@ -380,19 +380,19 @@ POSSIBILITY OF SUCH DAMAGE. #define CCM_MODE_DATARATE_Msk (0x3UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */ #define CCM_MODE_DATARATE_1Mbit (0UL) /*!< 1 Mbps */ #define CCM_MODE_DATARATE_2Mbit (1UL) /*!< 2 Mbps */ -#define CCM_MODE_DATARATE_125Kbps (2UL) /*!< 125 Kbps */ -#define CCM_MODE_DATARATE_500Kbps (3UL) /*!< 500 Kbps */ +#define CCM_MODE_DATARATE_125Kbps (2UL) /*!< 125 kbps */ +#define CCM_MODE_DATARATE_500Kbps (3UL) /*!< 500 kbps */ -/* Bit 0 : The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. */ +/* Bit 0 : The mode of operation to be used. Settings in this register apply whenever either the KSGEN task or the CRYPT task is triggered. */ #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ #define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ #define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */ #define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */ /* Register: CCM_CNFPTR */ -/* Description: Pointer to data structure holding AES key and NONCE vector */ +/* Description: Pointer to data structure holding the AES key and the NONCE vector */ -/* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */ +/* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see table CCM data structure overview) */ #define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */ #define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */ @@ -419,22 +419,29 @@ POSSIBILITY OF SUCH DAMAGE. #define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ /* Register: CCM_MAXPACKETSIZE */ -/* Description: Length of keystream generated when MODE.LENGTH = Extended. */ +/* Description: Length of keystream generated when MODE.LENGTH = Extended */ -/* Bits 7..0 : Length of keystream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. */ +/* Bits 7..0 : Length of keystream generated when MODE.LENGTH = Extended. This value must be greater than or equal to the subsequent packet payload to be encrypted/decrypted. */ #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos (0UL) /*!< Position of MAXPACKETSIZE field. */ #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Msk (0xFFUL << CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) /*!< Bit mask of MAXPACKETSIZE field. */ /* Register: CCM_RATEOVERRIDE */ /* Description: Data rate override setting. */ -/* Bits 1..0 : Data rate override setting. */ +/* Bits 1..0 : Data rate override setting */ #define CCM_RATEOVERRIDE_RATEOVERRIDE_Pos (0UL) /*!< Position of RATEOVERRIDE field. */ #define CCM_RATEOVERRIDE_RATEOVERRIDE_Msk (0x3UL << CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) /*!< Bit mask of RATEOVERRIDE field. */ #define CCM_RATEOVERRIDE_RATEOVERRIDE_1Mbit (0UL) /*!< 1 Mbps */ #define CCM_RATEOVERRIDE_RATEOVERRIDE_2Mbit (1UL) /*!< 2 Mbps */ -#define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (2UL) /*!< 125 Kbps */ -#define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (3UL) /*!< 500 Kbps */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (2UL) /*!< 125 kbps */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (3UL) /*!< 500 kbps */ + +/* Register: CCM_HEADERMASK */ +/* Description: Header (S0) mask. */ + +/* Bits 7..0 : Header (S0) mask */ +#define CCM_HEADERMASK_HEADERMASK_Pos (0UL) /*!< Position of HEADERMASK field. */ +#define CCM_HEADERMASK_HEADERMASK_Msk (0xFFUL << CCM_HEADERMASK_HEADERMASK_Pos) /*!< Bit mask of HEADERMASK field. */ /* Peripheral: CLOCK */ @@ -1526,6 +1533,7 @@ POSSIBILITY OF SUCH DAMAGE. #define FICR_INFO_VARIANT_VARIANT_AABC (0x41414243UL) /*!< AABC */ #define FICR_INFO_VARIANT_VARIANT_AAC0 (0x41414330UL) /*!< AAC0 */ #define FICR_INFO_VARIANT_VARIANT_AAC1 (0x41414331UL) /*!< AAC1 */ +#define FICR_INFO_VARIANT_VARIANT_AAD0 (0x41414430UL) /*!< AAD0 */ #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ /* Register: FICR_INFO_PACKAGE */ @@ -1543,11 +1551,11 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 31..0 : RAM variant */ #define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */ #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */ -#define FICR_INFO_RAM_RAM_K16 (0x10UL) /*!< 16 kByte RAM */ -#define FICR_INFO_RAM_RAM_K32 (0x20UL) /*!< 32 kByte RAM */ -#define FICR_INFO_RAM_RAM_K64 (0x40UL) /*!< 64 kByte RAM */ -#define FICR_INFO_RAM_RAM_K128 (0x80UL) /*!< 128 kByte RAM */ -#define FICR_INFO_RAM_RAM_K256 (0x100UL) /*!< 256 kByte RAM */ +#define FICR_INFO_RAM_RAM_K16 (0x10UL) /*!< 16 kB RAM */ +#define FICR_INFO_RAM_RAM_K32 (0x20UL) /*!< 32 kB RAM */ +#define FICR_INFO_RAM_RAM_K64 (0x40UL) /*!< 64 kB RAM */ +#define FICR_INFO_RAM_RAM_K128 (0x80UL) /*!< 128 kB RAM */ +#define FICR_INFO_RAM_RAM_K256 (0x100UL) /*!< 256 kB RAM */ #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ /* Register: FICR_INFO_FLASH */ @@ -1556,11 +1564,11 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 31..0 : Flash variant */ #define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */ #define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */ -#define FICR_INFO_FLASH_FLASH_K128 (0x80UL) /*!< 128 kByte FLASH */ -#define FICR_INFO_FLASH_FLASH_K256 (0x100UL) /*!< 256 kByte FLASH */ -#define FICR_INFO_FLASH_FLASH_K512 (0x200UL) /*!< 512 kByte FLASH */ -#define FICR_INFO_FLASH_FLASH_K1024 (0x400UL) /*!< 1 MByte FLASH */ -#define FICR_INFO_FLASH_FLASH_K2048 (0x800UL) /*!< 2 MByte FLASH */ +#define FICR_INFO_FLASH_FLASH_K128 (0x80UL) /*!< 128 kB FLASH */ +#define FICR_INFO_FLASH_FLASH_K256 (0x100UL) /*!< 256 kB FLASH */ +#define FICR_INFO_FLASH_FLASH_K512 (0x200UL) /*!< 512 kB FLASH */ +#define FICR_INFO_FLASH_FLASH_K1024 (0x400UL) /*!< 1 MB FLASH */ +#define FICR_INFO_FLASH_FLASH_K2048 (0x800UL) /*!< 2 MB FLASH */ #define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ /* Register: FICR_PRODTEST */ @@ -6233,8 +6241,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 8 : Channel map selection */ #define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */ #define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */ -#define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */ -#define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHZ .. 2460 MHz */ +#define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHz and 2500 MHz */ +#define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHz and 2460 MHz */ /* Bits 6..0 : Radio channel frequency */ #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ @@ -6272,8 +6280,8 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbps Nordic proprietary radio mode */ #define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbps BLE */ #define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbps BLE */ -#define RADIO_MODE_MODE_Ble_LR125Kbit (5UL) /*!< Long range 125 kbps TX, 125 kbps and 500 kbps RX */ -#define RADIO_MODE_MODE_Ble_LR500Kbit (6UL) /*!< Long range 500 kbps TX, 125 kbps and 500 kbps RX */ +#define RADIO_MODE_MODE_Ble_LR125Kbit (5UL) /*!< Long Range 125 kbps TX, 125 kbps and 500 kbps RX */ +#define RADIO_MODE_MODE_Ble_LR500Kbit (6UL) /*!< Long Range 500 kbps TX, 125 kbps and 500 kbps RX */ #define RADIO_MODE_MODE_Ieee802154_250Kbit (15UL) /*!< IEEE 802.15.4-2006 250 kbps */ /* Register: RADIO_PCNF0 */ @@ -6295,9 +6303,9 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */ #define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */ #define RADIO_PCNF0_PLEN_32bitZero (2UL) /*!< 32-bit zero preamble - used for IEEE 802.15.4 */ -#define RADIO_PCNF0_PLEN_LongRange (3UL) /*!< Preamble - used for BLE long range */ +#define RADIO_PCNF0_PLEN_LongRange (3UL) /*!< Preamble - used for Bluetooth LE Long Range */ -/* Bits 23..22 : Length of code indicator - long range */ +/* Bits 23..22 : Length of code indicator - Long Range */ #define RADIO_PCNF0_CILEN_Pos (22UL) /*!< Position of CILEN field. */ #define RADIO_PCNF0_CILEN_Msk (0x3UL << RADIO_PCNF0_CILEN_Pos) /*!< Bit mask of CILEN field. */ @@ -6828,11 +6836,11 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_DFECTRL2 */ /* Description: Start offset for Direction finding */ -/* Bits 27..16 : Signed value offset before starting sampling in number of 16M cycles relative to the beginning of the REFERENCE state - 12 us after switching start */ +/* Bits 27..16 : Signed value offset in number of 16 MHz clock cycles for fine tuning of the sampling instant for all IQ samples. With TSAMPLEOFFSET=0 the first sample is taken immediately at the start of the reference period */ #define RADIO_DFECTRL2_TSAMPLEOFFSET_Pos (16UL) /*!< Position of TSAMPLEOFFSET field. */ #define RADIO_DFECTRL2_TSAMPLEOFFSET_Msk (0xFFFUL << RADIO_DFECTRL2_TSAMPLEOFFSET_Pos) /*!< Bit mask of TSAMPLEOFFSET field. */ -/* Bits 12..0 : Signed value offset after the end of the CRC before starting switching in number of 16M cycles */ +/* Bits 12..0 : Signed value offset after the end of the CRC before starting switching in number of 16 MHz clock cycles */ #define RADIO_DFECTRL2_TSWITCHOFFSET_Pos (0UL) /*!< Position of TSWITCHOFFSET field. */ #define RADIO_DFECTRL2_TSWITCHOFFSET_Msk (0x1FFFUL << RADIO_DFECTRL2_TSWITCHOFFSET_Pos) /*!< Bit mask of TSWITCHOFFSET field. */ diff --git a/mdk/nrf52833.h b/mdk/nrf52833.h index dad362e219..6c34273a0a 100644 --- a/mdk/nrf52833.h +++ b/mdk/nrf52833.h @@ -32,10 +32,10 @@ * @file nrf52833.h * @brief CMSIS HeaderFile * @version 1 - * @date 29. April 2021 - * @note Generated by SVDConv V3.3.35 on Thursday, 29.04.2021 12:43:46 + * @date 19. November 2021 + * @note Generated by SVDConv V3.3.35 on Friday, 19.11.2021 12:45:01 * from File 'nrf52833.svd', - * last modified on Thursday, 29.04.2021 10:43:41 + * last modified on Friday, 19.11.2021 11:44:55 */ @@ -605,8 +605,8 @@ typedef struct { __IOM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Start address of region to protect. The start address must be word-aligned. */ __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Size of region to protect - counting from address ACL[n].ADDR. Write - '0' as no effect. */ + counting from address ACL[n].ADDR. Writing + a '0' has no effect. */ __IOM uint32_t PERM; /*!< (@ 0x00000008) Description cluster: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE */ @@ -1995,7 +1995,7 @@ typedef struct { /*!< (@ 0x4000F000) AAR Structur /** - * @brief AES CCM Mode Encryption (CCM) + * @brief AES CCM mode encryption (CCM) */ typedef struct { /*!< (@ 0x4000F000) CCM Structure */ @@ -2021,15 +2021,16 @@ typedef struct { /*!< (@ 0x4000F000) CCM Structur __IM uint32_t RESERVED4[63]; __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ - __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding AES key and - NONCE vector */ + __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding the AES key + and the NONCE vector */ __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of keystream generated when MODE.LENGTH - = Extended. */ + = Extended */ __IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */ -} NRF_CCM_Type; /*!< Size = 1312 (0x520) */ + __IOM uint32_t HEADERMASK; /*!< (@ 0x00000520) Header (S0) mask. */ +} NRF_CCM_Type; /*!< Size = 1316 (0x524) */ diff --git a/mdk/nrf52833.svd b/mdk/nrf52833.svd index c427c5cd65..3224e6a4aa 100644 --- a/mdk/nrf52833.svd +++ b/mdk/nrf52833.svd @@ -273,6 +273,11 @@ POSSIBILITY OF SUCH DAMAGE.\n AAA1 0x41414131 + + AAB0 + AAB0 + 0x41414230 + Unspecified Unspecified @@ -33303,7 +33308,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CCM - AES CCM Mode Encryption + AES CCM mode encryption 0x4000F000 AAR @@ -33745,7 +33750,7 @@ POSSIBILITY OF SUCH DAMAGE.\n MODE - The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. + The mode of operation to be used. Settings in this register apply whenever either the KSGEN task or the CRYPT task is triggered. 0 0 @@ -33779,12 +33784,12 @@ POSSIBILITY OF SUCH DAMAGE.\n 125Kbps - 125 Kbps + 125 kbps 2 500Kbps - 500 Kbps + 500 kbps 3 @@ -33811,13 +33816,13 @@ POSSIBILITY OF SUCH DAMAGE.\n CNFPTR - Pointer to data structure holding AES key and NONCE vector + Pointer to data structure holding the AES key and the NONCE vector 0x508 read-write CNFPTR - Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) + Pointer to the data structure holding the AES key and the CCM NONCE vector (see table CCM data structure overview) 0 31 @@ -33868,14 +33873,14 @@ POSSIBILITY OF SUCH DAMAGE.\n MAXPACKETSIZE - Length of keystream generated when MODE.LENGTH = Extended. + Length of keystream generated when MODE.LENGTH = Extended 0x518 read-write 0x000000FB MAXPACKETSIZE - Length of keystream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. + Length of keystream generated when MODE.LENGTH = Extended. This value must be greater than or equal to the subsequent packet payload to be encrypted/decrypted. 0 7 @@ -33890,7 +33895,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RATEOVERRIDE - Data rate override setting. + Data rate override setting 0 1 @@ -33906,18 +33911,33 @@ POSSIBILITY OF SUCH DAMAGE.\n 125Kbps - 125 Kbps + 125 kbps 2 500Kbps - 500 Kbps + 500 kbps 3 + + HEADERMASK + Header (S0) mask. + 0x520 + read-write + 0x000000E3 + + + HEADERMASK + Header (S0) mask + 0 + 7 + + + @@ -40584,7 +40604,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SIZE - Description cluster: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. + Description cluster: Size of region to protect counting from address ACL[n].ADDR. Writing a '0' has no effect. 0x004 read-writeonce 0x00000000 @@ -40606,36 +40626,36 @@ POSSIBILITY OF SUCH DAMAGE.\n WRITE - Configure write and erase permissions for region n. Write '0' has no effect. + Configure write and erase permissions for region n. Writing a '0' has no effect. 1 1 Enable - Allow write and erase instructions to region n + Allow write and erase instructions to region n. 0 Disable - Block write and erase instructions to region n + Block write and erase instructions to region n. 1 READ - Configure read permissions for region n. Write '0' has no effect. + Configure read permissions for region n. Writing a '0' has no effect. 2 2 Enable - Allow read instructions to region n + Allow read instructions to region n. 0 Disable - Block read instructions to region n + Block read instructions to region n. 1 diff --git a/mdk/nrf52833_bitfields.h b/mdk/nrf52833_bitfields.h index 372472b215..3cb05d3ab1 100644 --- a/mdk/nrf52833_bitfields.h +++ b/mdk/nrf52833_bitfields.h @@ -187,7 +187,7 @@ POSSIBILITY OF SUCH DAMAGE. #define ACL_ACL_ADDR_ADDR_Msk (0xFFFFFFFFUL << ACL_ACL_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */ /* Register: ACL_ACL_SIZE */ -/* Description: Description cluster: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. */ +/* Description: Description cluster: Size of region to protect counting from address ACL[n].ADDR. Writing a '0' has no effect. */ /* Bits 31..0 : Size of flash region n in bytes. Must be a multiple of the flash page size. */ #define ACL_ACL_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */ @@ -196,17 +196,17 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: ACL_ACL_PERM */ /* Description: Description cluster: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE */ -/* Bit 2 : Configure read permissions for region n. Write '0' has no effect. */ +/* Bit 2 : Configure read permissions for region n. Writing a '0' has no effect. */ #define ACL_ACL_PERM_READ_Pos (2UL) /*!< Position of READ field. */ #define ACL_ACL_PERM_READ_Msk (0x1UL << ACL_ACL_PERM_READ_Pos) /*!< Bit mask of READ field. */ -#define ACL_ACL_PERM_READ_Enable (0UL) /*!< Allow read instructions to region n */ -#define ACL_ACL_PERM_READ_Disable (1UL) /*!< Block read instructions to region n */ +#define ACL_ACL_PERM_READ_Enable (0UL) /*!< Allow read instructions to region n. */ +#define ACL_ACL_PERM_READ_Disable (1UL) /*!< Block read instructions to region n. */ -/* Bit 1 : Configure write and erase permissions for region n. Write '0' has no effect. */ +/* Bit 1 : Configure write and erase permissions for region n. Writing a '0' has no effect. */ #define ACL_ACL_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */ #define ACL_ACL_PERM_WRITE_Msk (0x1UL << ACL_ACL_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */ -#define ACL_ACL_PERM_WRITE_Enable (0UL) /*!< Allow write and erase instructions to region n */ -#define ACL_ACL_PERM_WRITE_Disable (1UL) /*!< Block write and erase instructions to region n */ +#define ACL_ACL_PERM_WRITE_Enable (0UL) /*!< Allow write and erase instructions to region n. */ +#define ACL_ACL_PERM_WRITE_Disable (1UL) /*!< Block write and erase instructions to region n. */ /* Peripheral: APPROTECT */ @@ -230,7 +230,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: CCM */ -/* Description: AES CCM Mode Encryption */ +/* Description: AES CCM mode encryption */ /* Register: CCM_TASKS_KSGEN */ /* Description: Start generation of keystream. This operation will stop by itself when completed. */ @@ -380,19 +380,19 @@ POSSIBILITY OF SUCH DAMAGE. #define CCM_MODE_DATARATE_Msk (0x3UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */ #define CCM_MODE_DATARATE_1Mbit (0UL) /*!< 1 Mbps */ #define CCM_MODE_DATARATE_2Mbit (1UL) /*!< 2 Mbps */ -#define CCM_MODE_DATARATE_125Kbps (2UL) /*!< 125 Kbps */ -#define CCM_MODE_DATARATE_500Kbps (3UL) /*!< 500 Kbps */ +#define CCM_MODE_DATARATE_125Kbps (2UL) /*!< 125 kbps */ +#define CCM_MODE_DATARATE_500Kbps (3UL) /*!< 500 kbps */ -/* Bit 0 : The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. */ +/* Bit 0 : The mode of operation to be used. Settings in this register apply whenever either the KSGEN task or the CRYPT task is triggered. */ #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ #define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ #define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */ #define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */ /* Register: CCM_CNFPTR */ -/* Description: Pointer to data structure holding AES key and NONCE vector */ +/* Description: Pointer to data structure holding the AES key and the NONCE vector */ -/* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */ +/* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see table CCM data structure overview) */ #define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */ #define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */ @@ -419,22 +419,29 @@ POSSIBILITY OF SUCH DAMAGE. #define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ /* Register: CCM_MAXPACKETSIZE */ -/* Description: Length of keystream generated when MODE.LENGTH = Extended. */ +/* Description: Length of keystream generated when MODE.LENGTH = Extended */ -/* Bits 7..0 : Length of keystream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. */ +/* Bits 7..0 : Length of keystream generated when MODE.LENGTH = Extended. This value must be greater than or equal to the subsequent packet payload to be encrypted/decrypted. */ #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos (0UL) /*!< Position of MAXPACKETSIZE field. */ #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Msk (0xFFUL << CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) /*!< Bit mask of MAXPACKETSIZE field. */ /* Register: CCM_RATEOVERRIDE */ /* Description: Data rate override setting. */ -/* Bits 1..0 : Data rate override setting. */ +/* Bits 1..0 : Data rate override setting */ #define CCM_RATEOVERRIDE_RATEOVERRIDE_Pos (0UL) /*!< Position of RATEOVERRIDE field. */ #define CCM_RATEOVERRIDE_RATEOVERRIDE_Msk (0x3UL << CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) /*!< Bit mask of RATEOVERRIDE field. */ #define CCM_RATEOVERRIDE_RATEOVERRIDE_1Mbit (0UL) /*!< 1 Mbps */ #define CCM_RATEOVERRIDE_RATEOVERRIDE_2Mbit (1UL) /*!< 2 Mbps */ -#define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (2UL) /*!< 125 Kbps */ -#define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (3UL) /*!< 500 Kbps */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (2UL) /*!< 125 kbps */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (3UL) /*!< 500 kbps */ + +/* Register: CCM_HEADERMASK */ +/* Description: Header (S0) mask. */ + +/* Bits 7..0 : Header (S0) mask */ +#define CCM_HEADERMASK_HEADERMASK_Pos (0UL) /*!< Position of HEADERMASK field. */ +#define CCM_HEADERMASK_HEADERMASK_Msk (0xFFUL << CCM_HEADERMASK_HEADERMASK_Pos) /*!< Bit mask of HEADERMASK field. */ /* Peripheral: CLOCK */ @@ -1551,6 +1558,7 @@ POSSIBILITY OF SUCH DAMAGE. #define FICR_INFO_VARIANT_VARIANT_AAA1 (0x41414131UL) /*!< AAA1 */ #define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */ #define FICR_INFO_VARIANT_VARIANT_AAAB (0x41414142UL) /*!< AAAB */ +#define FICR_INFO_VARIANT_VARIANT_AAB0 (0x41414230UL) /*!< AAB0 */ #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ /* Register: FICR_INFO_PACKAGE */ diff --git a/mdk/nrf52840.h b/mdk/nrf52840.h index 141e436929..25b6be8d14 100644 --- a/mdk/nrf52840.h +++ b/mdk/nrf52840.h @@ -32,10 +32,10 @@ * @file nrf52840.h * @brief CMSIS HeaderFile * @version 1 - * @date 29. April 2021 - * @note Generated by SVDConv V3.3.35 on Thursday, 29.04.2021 12:43:48 + * @date 19. November 2021 + * @note Generated by SVDConv V3.3.35 on Friday, 19.11.2021 12:45:03 * from File 'nrf52840.svd', - * last modified on Thursday, 29.04.2021 10:43:41 + * last modified on Friday, 19.11.2021 11:44:55 */ @@ -603,8 +603,8 @@ typedef struct { __IOM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Start address of region to protect. The start address must be word-aligned. */ __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Size of region to protect - counting from address ACL[n].ADDR. Write - '0' as no effect. */ + counting from address ACL[n].ADDR. Writing + a '0' has no effect. */ __IOM uint32_t PERM; /*!< (@ 0x00000008) Description cluster: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE */ @@ -2017,7 +2017,7 @@ typedef struct { /*!< (@ 0x4000F000) AAR Structur /** - * @brief AES CCM Mode Encryption (CCM) + * @brief AES CCM mode encryption (CCM) */ typedef struct { /*!< (@ 0x4000F000) CCM Structure */ @@ -2043,13 +2043,13 @@ typedef struct { /*!< (@ 0x4000F000) CCM Structur __IM uint32_t RESERVED4[63]; __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ - __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding AES key and - NONCE vector */ + __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding the AES key + and the NONCE vector */ __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of keystream generated when MODE.LENGTH - = Extended. */ + = Extended */ __IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */ } NRF_CCM_Type; /*!< Size = 1312 (0x520) */ diff --git a/mdk/nrf52840.svd b/mdk/nrf52840.svd index a5e5325c60..a664dfa6da 100644 --- a/mdk/nrf52840.svd +++ b/mdk/nrf52840.svd @@ -313,6 +313,16 @@ POSSIBILITY OF SUCH DAMAGE.\n AAEA 0x41414541 + + AAF0 + AAF0 + 0x41414630 + + + AAFA + AAFA + 0x41414641 + Unspecified Unspecified @@ -340,6 +350,11 @@ POSSIBILITY OF SUCH DAMAGE.\n QIxx - 7x7 73-pin aQFN 0x2004 + + QF + QFxx - 6x6 48-pin QFN + 0x2000 + CK CKxx - 3.544 x 3.607 WLCSP @@ -369,27 +384,27 @@ POSSIBILITY OF SUCH DAMAGE.\n K16 - 16 kByte RAM + 16 kB RAM 0x10 K32 - 32 kByte RAM + 32 kB RAM 0x20 K64 - 64 kByte RAM + 64 kB RAM 0x40 K128 - 128 kByte RAM + 128 kB RAM 0x80 K256 - 256 kByte RAM + 256 kB RAM 0x100 @@ -416,27 +431,27 @@ POSSIBILITY OF SUCH DAMAGE.\n K128 - 128 kByte FLASH + 128 kB FLASH 0x80 K256 - 256 kByte FLASH + 256 kB FLASH 0x100 K512 - 512 kByte FLASH + 512 kB FLASH 0x200 K1024 - 1 MByte FLASH + 1 MB FLASH 0x400 K2048 - 2 MByte FLASH + 2 MB FLASH 0x800 @@ -5613,8 +5628,8 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - 1 Write: a '1' sets the pin high; a '0' has no effect + 1 @@ -32694,7 +32709,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CCM - AES CCM Mode Encryption + AES CCM mode encryption 0x4000F000 AAR @@ -33136,7 +33151,7 @@ POSSIBILITY OF SUCH DAMAGE.\n MODE - The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. + The mode of operation to be used. Settings in this register apply whenever either the KSGEN task or the CRYPT task is triggered. 0 0 @@ -33170,12 +33185,12 @@ POSSIBILITY OF SUCH DAMAGE.\n 125Kbps - 125 Kbps + 125 kbps 2 500Kbps - 500 Kbps + 500 kbps 3 @@ -33202,13 +33217,13 @@ POSSIBILITY OF SUCH DAMAGE.\n CNFPTR - Pointer to data structure holding AES key and NONCE vector + Pointer to data structure holding the AES key and the NONCE vector 0x508 read-write CNFPTR - Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) + Pointer to the data structure holding the AES key and the CCM NONCE vector (see table CCM data structure overview) 0 31 @@ -33259,14 +33274,14 @@ POSSIBILITY OF SUCH DAMAGE.\n MAXPACKETSIZE - Length of keystream generated when MODE.LENGTH = Extended. + Length of keystream generated when MODE.LENGTH = Extended 0x518 read-write 0x000000FB MAXPACKETSIZE - Length of keystream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. + Length of keystream generated when MODE.LENGTH = Extended. This value must be greater than or equal to the subsequent packet payload to be encrypted/decrypted. 0 7 @@ -33281,7 +33296,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RATEOVERRIDE - Data rate override setting. + Data rate override setting 0 1 @@ -33297,12 +33312,12 @@ POSSIBILITY OF SUCH DAMAGE.\n 125Kbps - 125 Kbps + 125 kbps 2 500Kbps - 500 Kbps + 500 kbps 3 @@ -39975,7 +39990,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SIZE - Description cluster: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. + Description cluster: Size of region to protect counting from address ACL[n].ADDR. Writing a '0' has no effect. 0x004 read-writeonce 0x00000000 @@ -39997,36 +40012,36 @@ POSSIBILITY OF SUCH DAMAGE.\n WRITE - Configure write and erase permissions for region n. Write '0' has no effect. + Configure write and erase permissions for region n. Writing a '0' has no effect. 1 1 Enable - Allow write and erase instructions to region n + Allow write and erase instructions to region n. 0 Disable - Block write and erase instructions to region n + Block write and erase instructions to region n. 1 READ - Configure read permissions for region n. Write '0' has no effect. + Configure read permissions for region n. Writing a '0' has no effect. 2 2 Enable - Allow read instructions to region n + Allow read instructions to region n. 0 Disable - Block read instructions to region n + Block read instructions to region n. 1 diff --git a/mdk/nrf52840_bitfields.h b/mdk/nrf52840_bitfields.h index 2e8b24ac8c..a337d94224 100644 --- a/mdk/nrf52840_bitfields.h +++ b/mdk/nrf52840_bitfields.h @@ -187,7 +187,7 @@ POSSIBILITY OF SUCH DAMAGE. #define ACL_ACL_ADDR_ADDR_Msk (0xFFFFFFFFUL << ACL_ACL_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */ /* Register: ACL_ACL_SIZE */ -/* Description: Description cluster: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. */ +/* Description: Description cluster: Size of region to protect counting from address ACL[n].ADDR. Writing a '0' has no effect. */ /* Bits 31..0 : Size of flash region n in bytes. Must be a multiple of the flash page size. */ #define ACL_ACL_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */ @@ -196,17 +196,17 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: ACL_ACL_PERM */ /* Description: Description cluster: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE */ -/* Bit 2 : Configure read permissions for region n. Write '0' has no effect. */ +/* Bit 2 : Configure read permissions for region n. Writing a '0' has no effect. */ #define ACL_ACL_PERM_READ_Pos (2UL) /*!< Position of READ field. */ #define ACL_ACL_PERM_READ_Msk (0x1UL << ACL_ACL_PERM_READ_Pos) /*!< Bit mask of READ field. */ -#define ACL_ACL_PERM_READ_Enable (0UL) /*!< Allow read instructions to region n */ -#define ACL_ACL_PERM_READ_Disable (1UL) /*!< Block read instructions to region n */ +#define ACL_ACL_PERM_READ_Enable (0UL) /*!< Allow read instructions to region n. */ +#define ACL_ACL_PERM_READ_Disable (1UL) /*!< Block read instructions to region n. */ -/* Bit 1 : Configure write and erase permissions for region n. Write '0' has no effect. */ +/* Bit 1 : Configure write and erase permissions for region n. Writing a '0' has no effect. */ #define ACL_ACL_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */ #define ACL_ACL_PERM_WRITE_Msk (0x1UL << ACL_ACL_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */ -#define ACL_ACL_PERM_WRITE_Enable (0UL) /*!< Allow write and erase instructions to region n */ -#define ACL_ACL_PERM_WRITE_Disable (1UL) /*!< Block write and erase instructions to region n */ +#define ACL_ACL_PERM_WRITE_Enable (0UL) /*!< Allow write and erase instructions to region n. */ +#define ACL_ACL_PERM_WRITE_Disable (1UL) /*!< Block write and erase instructions to region n. */ /* Peripheral: APPROTECT */ @@ -230,7 +230,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: CCM */ -/* Description: AES CCM Mode Encryption */ +/* Description: AES CCM mode encryption */ /* Register: CCM_TASKS_KSGEN */ /* Description: Start generation of keystream. This operation will stop by itself when completed. */ @@ -380,19 +380,19 @@ POSSIBILITY OF SUCH DAMAGE. #define CCM_MODE_DATARATE_Msk (0x3UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */ #define CCM_MODE_DATARATE_1Mbit (0UL) /*!< 1 Mbps */ #define CCM_MODE_DATARATE_2Mbit (1UL) /*!< 2 Mbps */ -#define CCM_MODE_DATARATE_125Kbps (2UL) /*!< 125 Kbps */ -#define CCM_MODE_DATARATE_500Kbps (3UL) /*!< 500 Kbps */ +#define CCM_MODE_DATARATE_125Kbps (2UL) /*!< 125 kbps */ +#define CCM_MODE_DATARATE_500Kbps (3UL) /*!< 500 kbps */ -/* Bit 0 : The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. */ +/* Bit 0 : The mode of operation to be used. Settings in this register apply whenever either the KSGEN task or the CRYPT task is triggered. */ #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ #define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ #define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */ #define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */ /* Register: CCM_CNFPTR */ -/* Description: Pointer to data structure holding AES key and NONCE vector */ +/* Description: Pointer to data structure holding the AES key and the NONCE vector */ -/* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */ +/* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see table CCM data structure overview) */ #define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */ #define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */ @@ -419,22 +419,22 @@ POSSIBILITY OF SUCH DAMAGE. #define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ /* Register: CCM_MAXPACKETSIZE */ -/* Description: Length of keystream generated when MODE.LENGTH = Extended. */ +/* Description: Length of keystream generated when MODE.LENGTH = Extended */ -/* Bits 7..0 : Length of keystream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. */ +/* Bits 7..0 : Length of keystream generated when MODE.LENGTH = Extended. This value must be greater than or equal to the subsequent packet payload to be encrypted/decrypted. */ #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos (0UL) /*!< Position of MAXPACKETSIZE field. */ #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Msk (0xFFUL << CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) /*!< Bit mask of MAXPACKETSIZE field. */ /* Register: CCM_RATEOVERRIDE */ /* Description: Data rate override setting. */ -/* Bits 1..0 : Data rate override setting. */ +/* Bits 1..0 : Data rate override setting */ #define CCM_RATEOVERRIDE_RATEOVERRIDE_Pos (0UL) /*!< Position of RATEOVERRIDE field. */ #define CCM_RATEOVERRIDE_RATEOVERRIDE_Msk (0x3UL << CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) /*!< Bit mask of RATEOVERRIDE field. */ #define CCM_RATEOVERRIDE_RATEOVERRIDE_1Mbit (0UL) /*!< 1 Mbps */ #define CCM_RATEOVERRIDE_RATEOVERRIDE_2Mbit (1UL) /*!< 2 Mbps */ -#define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (2UL) /*!< 125 Kbps */ -#define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (3UL) /*!< 500 Kbps */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (2UL) /*!< 125 kbps */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (3UL) /*!< 500 kbps */ /* Peripheral: CC_HOST_RGF */ @@ -1642,6 +1642,8 @@ POSSIBILITY OF SUCH DAMAGE. #define FICR_INFO_VARIANT_VARIANT_AAD1 (0x41414431UL) /*!< AAD1 */ #define FICR_INFO_VARIANT_VARIANT_AADA (0x41414441UL) /*!< AADA */ #define FICR_INFO_VARIANT_VARIANT_AAEA (0x41414541UL) /*!< AAEA */ +#define FICR_INFO_VARIANT_VARIANT_AAF0 (0x41414630UL) /*!< AAF0 */ +#define FICR_INFO_VARIANT_VARIANT_AAFA (0x41414641UL) /*!< AAFA */ #define FICR_INFO_VARIANT_VARIANT_BAAA (0x42414141UL) /*!< BAAA */ #define FICR_INFO_VARIANT_VARIANT_CAAA (0x43414141UL) /*!< CAAA */ #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ @@ -1652,6 +1654,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 31..0 : Package option */ #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ +#define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL) /*!< QFxx - 6x6 48-pin QFN */ #define FICR_INFO_PACKAGE_PACKAGE_QI (0x2004UL) /*!< QIxx - 7x7 73-pin aQFN */ #define FICR_INFO_PACKAGE_PACKAGE_CK (0x2005UL) /*!< CKxx - 3.544 x 3.607 WLCSP */ #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ @@ -1662,11 +1665,11 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 31..0 : RAM variant */ #define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */ #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */ -#define FICR_INFO_RAM_RAM_K16 (0x10UL) /*!< 16 kByte RAM */ -#define FICR_INFO_RAM_RAM_K32 (0x20UL) /*!< 32 kByte RAM */ -#define FICR_INFO_RAM_RAM_K64 (0x40UL) /*!< 64 kByte RAM */ -#define FICR_INFO_RAM_RAM_K128 (0x80UL) /*!< 128 kByte RAM */ -#define FICR_INFO_RAM_RAM_K256 (0x100UL) /*!< 256 kByte RAM */ +#define FICR_INFO_RAM_RAM_K16 (0x10UL) /*!< 16 kB RAM */ +#define FICR_INFO_RAM_RAM_K32 (0x20UL) /*!< 32 kB RAM */ +#define FICR_INFO_RAM_RAM_K64 (0x40UL) /*!< 64 kB RAM */ +#define FICR_INFO_RAM_RAM_K128 (0x80UL) /*!< 128 kB RAM */ +#define FICR_INFO_RAM_RAM_K256 (0x100UL) /*!< 256 kB RAM */ #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ /* Register: FICR_INFO_FLASH */ @@ -1675,11 +1678,11 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 31..0 : Flash variant */ #define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */ #define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */ -#define FICR_INFO_FLASH_FLASH_K128 (0x80UL) /*!< 128 kByte FLASH */ -#define FICR_INFO_FLASH_FLASH_K256 (0x100UL) /*!< 256 kByte FLASH */ -#define FICR_INFO_FLASH_FLASH_K512 (0x200UL) /*!< 512 kByte FLASH */ -#define FICR_INFO_FLASH_FLASH_K1024 (0x400UL) /*!< 1 MByte FLASH */ -#define FICR_INFO_FLASH_FLASH_K2048 (0x800UL) /*!< 2 MByte FLASH */ +#define FICR_INFO_FLASH_FLASH_K128 (0x80UL) /*!< 128 kB FLASH */ +#define FICR_INFO_FLASH_FLASH_K256 (0x100UL) /*!< 256 kB FLASH */ +#define FICR_INFO_FLASH_FLASH_K512 (0x200UL) /*!< 512 kB FLASH */ +#define FICR_INFO_FLASH_FLASH_K1024 (0x400UL) /*!< 1 MB FLASH */ +#define FICR_INFO_FLASH_FLASH_K2048 (0x800UL) /*!< 2 MB FLASH */ #define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ /* Register: FICR_PRODTEST */ diff --git a/mdk/nrf52_bitfields.h b/mdk/nrf52_bitfields.h index 220ada67e4..1f820f30be 100644 --- a/mdk/nrf52_bitfields.h +++ b/mdk/nrf52_bitfields.h @@ -1928,10 +1928,17 @@ POSSIBILITY OF SUCH DAMAGE. #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ #define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */ #define FICR_INFO_VARIANT_VARIANT_AAAB (0x41414142UL) /*!< AAAB */ +#define FICR_INFO_VARIANT_VARIANT_AAAC (0x41414143UL) /*!< AAAC */ #define FICR_INFO_VARIANT_VARIANT_AAB0 (0x41414230UL) /*!< AAB0 */ #define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */ #define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */ #define FICR_INFO_VARIANT_VARIANT_AAE0 (0x41414530UL) /*!< AAE0 */ +#define FICR_INFO_VARIANT_VARIANT_AAG0 (0x41414730UL) /*!< AAG0 */ +#define FICR_INFO_VARIANT_VARIANT_AAGB (0x41414742UL) /*!< AAGB */ +#define FICR_INFO_VARIANT_VARIANT_ABB0 (0x41424230UL) /*!< ABB0 */ +#define FICR_INFO_VARIANT_VARIANT_ABE0 (0x41424530UL) /*!< ABE0 */ +#define FICR_INFO_VARIANT_VARIANT_ABG0 (0x41424730UL) /*!< ABG0 */ +#define FICR_INFO_VARIANT_VARIANT_ABGB (0x41424742UL) /*!< ABGB */ #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ /* Register: FICR_INFO_PACKAGE */ diff --git a/mdk/nrf52_common.ld b/mdk/nrf52_common.ld index bb99b83079..c151390f22 100644 --- a/mdk/nrf52_common.ld +++ b/mdk/nrf52_common.ld @@ -77,17 +77,24 @@ SECTIONS KEEP(*(.eh_frame*)) } > FLASH - .ARM.extab : + .gnu.sgstubs : + { + . = ALIGN(32); + } > FLASH + + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH - __exidx_start = .; + .ARM.exidx : { + __exidx_start = .; *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; } > FLASH - __exidx_end = .; . = ALIGN(4); __etext = .; diff --git a/mdk/nrf52_erratas.h b/mdk/nrf52_erratas.h index e05d5678b4..1f95312427 100644 --- a/mdk/nrf52_erratas.h +++ b/mdk/nrf52_erratas.h @@ -221,8 +221,12 @@ static bool nrf52_errata_244(void) __UNUSED; static bool nrf52_errata_245(void) __UNUSED; static bool nrf52_errata_246(void) __UNUSED; static bool nrf52_errata_248(void) __UNUSED; -static bool nrf52_errata_249(void) __UNUSED; +static bool nrf52_configuration_249(void) __UNUSED; static bool nrf52_errata_250(void) __UNUSED; +static bool nrf52_configuration_254(void) __UNUSED; +static bool nrf52_configuration_255(void) __UNUSED; +static bool nrf52_configuration_256(void) __UNUSED; +static bool nrf52_configuration_257(void) __UNUSED; /* ========= Errata 1 ========= */ #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ @@ -800,6 +804,8 @@ static bool nrf52_errata_15(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -812,6 +818,8 @@ static bool nrf52_errata_15(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -824,6 +832,8 @@ static bool nrf52_errata_15(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -1026,6 +1036,8 @@ static bool nrf52_errata_20(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -1054,6 +1066,8 @@ static bool nrf52_errata_20(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -1066,6 +1080,8 @@ static bool nrf52_errata_20(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -1540,6 +1556,8 @@ static bool nrf52_errata_31(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -1552,6 +1570,8 @@ static bool nrf52_errata_31(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -1564,6 +1584,8 @@ static bool nrf52_errata_31(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -1860,6 +1882,8 @@ static bool nrf52_errata_36(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -1888,6 +1912,8 @@ static bool nrf52_errata_36(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -1900,6 +1926,8 @@ static bool nrf52_errata_36(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -3184,6 +3212,8 @@ static bool nrf52_errata_66(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -3212,6 +3242,8 @@ static bool nrf52_errata_66(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -3224,6 +3256,8 @@ static bool nrf52_errata_66(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -3404,6 +3438,8 @@ static bool nrf52_errata_68(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -3416,6 +3452,8 @@ static bool nrf52_errata_68(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -3428,6 +3466,8 @@ static bool nrf52_errata_68(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -3881,6 +3921,8 @@ static bool nrf52_errata_77(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -3893,6 +3935,8 @@ static bool nrf52_errata_77(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -3905,6 +3949,8 @@ static bool nrf52_errata_77(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -4013,6 +4059,8 @@ static bool nrf52_errata_78(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -4041,6 +4089,8 @@ static bool nrf52_errata_78(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -4053,6 +4103,8 @@ static bool nrf52_errata_78(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -4233,6 +4285,8 @@ static bool nrf52_errata_81(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -4245,6 +4299,8 @@ static bool nrf52_errata_81(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -4257,6 +4313,8 @@ static bool nrf52_errata_81(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -4361,6 +4419,8 @@ static bool nrf52_errata_83(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -4373,6 +4433,8 @@ static bool nrf52_errata_83(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -4385,6 +4447,8 @@ static bool nrf52_errata_83(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -4703,6 +4767,8 @@ static bool nrf52_errata_88(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -4715,6 +4781,8 @@ static bool nrf52_errata_88(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -4727,6 +4795,8 @@ static bool nrf52_errata_88(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -6563,6 +6633,8 @@ static bool nrf52_errata_136(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -6591,6 +6663,8 @@ static bool nrf52_errata_136(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -6603,6 +6677,8 @@ static bool nrf52_errata_136(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -7267,6 +7343,8 @@ static bool nrf52_errata_150(void) return true; case 0x01ul: return false; + case 0x02ul: + return false; default: return false; } @@ -7377,8 +7455,10 @@ static bool nrf52_errata_153(void) return false; case 0x01ul: return true; + case 0x02ul: + return false; default: - return true; + return false; } } #endif @@ -7389,6 +7469,8 @@ static bool nrf52_errata_153(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -7539,6 +7621,8 @@ static bool nrf52_errata_155(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -7551,6 +7635,8 @@ static bool nrf52_errata_155(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -7563,6 +7649,8 @@ static bool nrf52_errata_155(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -7667,6 +7755,8 @@ static bool nrf52_errata_156(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -7679,6 +7769,8 @@ static bool nrf52_errata_156(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -7691,6 +7783,8 @@ static bool nrf52_errata_156(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -8263,6 +8357,8 @@ static bool nrf52_errata_173(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -8291,6 +8387,8 @@ static bool nrf52_errata_173(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -8303,6 +8401,8 @@ static bool nrf52_errata_173(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -8475,6 +8575,8 @@ static bool nrf52_errata_176(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -8503,6 +8605,8 @@ static bool nrf52_errata_176(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -8515,6 +8619,8 @@ static bool nrf52_errata_176(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -8695,6 +8801,8 @@ static bool nrf52_errata_179(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -8707,6 +8815,8 @@ static bool nrf52_errata_179(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -8719,6 +8829,8 @@ static bool nrf52_errata_179(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -9002,6 +9114,8 @@ static bool nrf52_errata_183(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -9030,6 +9144,8 @@ static bool nrf52_errata_183(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -9118,6 +9234,8 @@ static bool nrf52_errata_184(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -9146,6 +9264,8 @@ static bool nrf52_errata_184(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -9158,6 +9278,8 @@ static bool nrf52_errata_184(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -9582,6 +9704,8 @@ static bool nrf52_errata_192(void) return true; case 0x01ul: return false; + case 0x02ul: + return false; default: return false; } @@ -10202,6 +10326,8 @@ static bool nrf52_errata_201(void) return true; case 0x01ul: return false; + case 0x02ul: + return false; default: return false; } @@ -10348,6 +10474,8 @@ static bool nrf52_errata_204(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -10548,6 +10676,8 @@ static bool nrf52_errata_210(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -10576,6 +10706,8 @@ static bool nrf52_errata_210(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -10588,6 +10720,8 @@ static bool nrf52_errata_210(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -10798,6 +10932,8 @@ static bool nrf52_errata_212(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -10826,6 +10962,8 @@ static bool nrf52_errata_212(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -10838,6 +10976,8 @@ static bool nrf52_errata_212(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -10958,6 +11098,8 @@ static bool nrf52_errata_213(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -10970,6 +11112,8 @@ static bool nrf52_errata_213(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -11150,8 +11294,10 @@ static bool nrf52_errata_217(void) return false; case 0x01ul: return true; + case 0x02ul: + return false; default: - return true; + return false; } } #endif @@ -11162,6 +11308,8 @@ static bool nrf52_errata_217(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -11174,6 +11322,8 @@ static bool nrf52_errata_217(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -11404,6 +11554,8 @@ static bool nrf52_errata_219(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -11432,6 +11584,8 @@ static bool nrf52_errata_219(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -11444,6 +11598,8 @@ static bool nrf52_errata_219(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -11708,8 +11864,10 @@ static bool nrf52_errata_228(void) return false; case 0x01ul: return true; + case 0x02ul: + return false; default: - return true; + return false; } } #endif @@ -11736,6 +11894,8 @@ static bool nrf52_errata_228(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -11878,8 +12038,10 @@ static bool nrf52_errata_232(void) return false; case 0x01ul: return true; + case 0x02ul: + return false; default: - return true; + return false; } } #endif @@ -11890,6 +12052,8 @@ static bool nrf52_errata_232(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -12042,8 +12206,10 @@ static bool nrf52_errata_236(void) return false; case 0x01ul: return true; + case 0x02ul: + return false; default: - return true; + return false; } } #endif @@ -12057,9 +12223,9 @@ static bool nrf52_errata_236(void) case 0x01ul: return true; case 0x02ul: - return true; + return false; default: - return true; + return false; } } #endif @@ -12070,6 +12236,8 @@ static bool nrf52_errata_236(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -12156,6 +12324,8 @@ static bool nrf52_errata_237(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -12184,6 +12354,8 @@ static bool nrf52_errata_237(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -12268,6 +12440,8 @@ static bool nrf52_errata_242(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -12280,6 +12454,8 @@ static bool nrf52_errata_242(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -12292,6 +12468,8 @@ static bool nrf52_errata_242(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -12530,6 +12708,8 @@ static bool nrf52_errata_245(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -12558,6 +12738,8 @@ static bool nrf52_errata_245(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -12570,6 +12752,8 @@ static bool nrf52_errata_245(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -12658,6 +12842,8 @@ static bool nrf52_errata_246(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -12686,6 +12872,8 @@ static bool nrf52_errata_246(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -12698,6 +12886,8 @@ static bool nrf52_errata_246(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -12784,8 +12974,10 @@ static bool nrf52_errata_248(void) return false; case 0x01ul: return true; + case 0x02ul: + return false; default: - return true; + return false; } } #endif @@ -12812,6 +13004,8 @@ static bool nrf52_errata_248(void) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } @@ -12840,26 +13034,32 @@ static bool nrf52_errata_248(void) } /* ========= Errata 249 ========= */ -#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) - #define NRF52_ERRATA_249_PRESENT 1 + #define NRF52_CONFIGURATION_249_PRESENT 1 #else - #define NRF52_ERRATA_249_PRESENT 0 + #define NRF52_CONFIGURATION_249_PRESENT 0 #endif -#ifndef NRF52_ERRATA_249_ENABLE_WORKAROUND - #define NRF52_ERRATA_249_ENABLE_WORKAROUND NRF52_ERRATA_249_PRESENT +#ifndef NRF52_CONFIGURATION_249_ENABLE + #define NRF52_CONFIGURATION_249_ENABLE NRF52_CONFIGURATION_249_PRESENT #endif -static bool nrf52_errata_249(void) +static bool nrf52_configuration_249(void) { #ifndef NRF52_SERIES return false; #else - #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ @@ -12902,7 +13102,7 @@ static bool nrf52_errata_249(void) case 0x03ul: return false; case 0x04ul: - return true; + return false; case 0x05ul: return true; default: @@ -12910,6 +13110,22 @@ static bool nrf52_errata_249(void) } } #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + default: + return true; + } + } + #endif #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) if (var1 == 0x0D) { @@ -12926,6 +13142,34 @@ static bool nrf52_errata_249(void) } } #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + default: + return true; + } + } + #endif #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) if (var1 == 0x10) { @@ -13008,4 +13252,170 @@ static bool nrf52_errata_250(void) #endif } +/* ========= Errata 254 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_CONFIGURATION_254_PRESENT 1 +#else + #define NRF52_CONFIGURATION_254_PRESENT 0 +#endif + +#ifndef NRF52_CONFIGURATION_254_ENABLE + #define NRF52_CONFIGURATION_254_ENABLE NRF52_CONFIGURATION_254_PRESENT +#endif + +static bool nrf52_configuration_254(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 255 ========= */ +#if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #define NRF52_CONFIGURATION_255_PRESENT 1 +#else + #define NRF52_CONFIGURATION_255_PRESENT 0 +#endif + +#ifndef NRF52_CONFIGURATION_255_ENABLE + #define NRF52_CONFIGURATION_255_ENABLE NRF52_CONFIGURATION_255_PRESENT +#endif + +static bool nrf52_configuration_255(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 256 ========= */ +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + #define NRF52_CONFIGURATION_256_PRESENT 1 +#else + #define NRF52_CONFIGURATION_256_PRESENT 0 +#endif + +#ifndef NRF52_CONFIGURATION_256_ENABLE + #define NRF52_CONFIGURATION_256_ENABLE NRF52_CONFIGURATION_256_PRESENT +#endif + +static bool nrf52_configuration_256(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 257 ========= */ +#if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + #define NRF52_CONFIGURATION_257_PRESENT 1 +#else + #define NRF52_CONFIGURATION_257_PRESENT 0 +#endif + +#ifndef NRF52_CONFIGURATION_257_ENABLE + #define NRF52_CONFIGURATION_257_ENABLE NRF52_CONFIGURATION_257_PRESENT +#endif + +static bool nrf52_configuration_257(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + #endif /* NRF52_ERRATAS_H */ diff --git a/mdk/nrf5340_application.h b/mdk/nrf5340_application.h index c130c5b33e..5eb14481a3 100644 --- a/mdk/nrf5340_application.h +++ b/mdk/nrf5340_application.h @@ -19,10 +19,10 @@ * @file nrf5340_application.h * @brief CMSIS HeaderFile * @version 1 - * @date 29. April 2021 - * @note Generated by SVDConv V3.3.35 on Thursday, 29.04.2021 12:43:49 + * @date 19. November 2021 + * @note Generated by SVDConv V3.3.35 on Friday, 19.11.2021 12:45:05 * from File 'nrf5340_application.svd', - * last modified on Thursday, 29.04.2021 10:43:41 + * last modified on Friday, 19.11.2021 11:44:55 */ @@ -573,8 +573,9 @@ typedef struct { typedef struct { __IOM uint32_t RXDELAY; /*!< (@ 0x00000000) Sample delay for input serial data on MISO */ __IOM uint32_t CSNDUR; /*!< (@ 0x00000004) Minimum duration between edge of CSN and edge - of SCK and minimum duration CSN must stay - high between transactions */ + of SCK. When SHORTS.END_START is used, this + is also the minimum duration CSN must stay + high between transactions. */ } SPIM_IFTIMING_Type; /*!< Size = 8 (0x8) */ diff --git a/mdk/nrf5340_application.svd b/mdk/nrf5340_application.svd index b6faf3369e..552a611d42 100644 --- a/mdk/nrf5340_application.svd +++ b/mdk/nrf5340_application.svd @@ -329,6 +329,11 @@ POSSIBILITY OF SUCH DAMAGE. QKAA 0x514B4141 + + CLAA + CLAA + 0x434C4141 + Unspecified Unspecified @@ -356,6 +361,11 @@ POSSIBILITY OF SUCH DAMAGE. QKxx - 94-pin aQFN 0x2000 + + CL + CLxx - WLCSP + 0x2005 + Unspecified Unspecified @@ -11587,14 +11597,14 @@ POSSIBILITY OF SUCH DAMAGE. CSNDUR - Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions + Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is also the minimum duration CSN must stay high between transactions. 0x004 read-write 0x00000002 CSNDUR - Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns). + Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is the minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns). 0 7 diff --git a/mdk/nrf5340_application_bitfields.h b/mdk/nrf5340_application_bitfields.h index ab1d1a112b..0821f136e8 100644 --- a/mdk/nrf5340_application_bitfields.h +++ b/mdk/nrf5340_application_bitfields.h @@ -3231,6 +3231,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 31..0 : Part Variant, Hardware version and Production configuration, encoded as ASCII */ #define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */ #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ +#define FICR_INFO_VARIANT_VARIANT_CLAA (0x434C4141UL) /*!< CLAA */ #define FICR_INFO_VARIANT_VARIANT_QKAA (0x514B4141UL) /*!< QKAA */ #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ @@ -3241,6 +3242,7 @@ POSSIBILITY OF SUCH DAMAGE. #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ #define FICR_INFO_PACKAGE_PACKAGE_QK (0x2000UL) /*!< QKxx - 94-pin aQFN */ +#define FICR_INFO_PACKAGE_PACKAGE_CL (0x2005UL) /*!< CLxx - WLCSP */ #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ /* Register: FICR_INFO_RAM */ @@ -12711,9 +12713,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIM_IFTIMING_RXDELAY_RXDELAY_Msk (0x7UL << SPIM_IFTIMING_RXDELAY_RXDELAY_Pos) /*!< Bit mask of RXDELAY field. */ /* Register: SPIM_IFTIMING_CSNDUR */ -/* Description: Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions */ +/* Description: Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is also the minimum duration CSN must stay high between transactions. */ -/* Bits 7..0 : Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns). */ +/* Bits 7..0 : Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is the minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns). */ #define SPIM_IFTIMING_CSNDUR_CSNDUR_Pos (0UL) /*!< Position of CSNDUR field. */ #define SPIM_IFTIMING_CSNDUR_CSNDUR_Msk (0xFFUL << SPIM_IFTIMING_CSNDUR_CSNDUR_Pos) /*!< Bit mask of CSNDUR field. */ diff --git a/mdk/nrf5340_application_peripherals.h b/mdk/nrf5340_application_peripherals.h index 58883cc935..ed4d92b42f 100644 --- a/mdk/nrf5340_application_peripherals.h +++ b/mdk/nrf5340_application_peripherals.h @@ -289,6 +289,8 @@ POSSIBILITY OF SUCH DAMAGE. #define SPU_PRESENT #define SPU_COUNT 1 +#define SPU_RAMREGION_SIZE 0x2000ul + /* Inter-IC Sound Interface */ #define I2S_PRESENT #define I2S_COUNT 1 diff --git a/mdk/nrf5340_network.h b/mdk/nrf5340_network.h index 67ff4c07b5..e13c809d2a 100644 --- a/mdk/nrf5340_network.h +++ b/mdk/nrf5340_network.h @@ -19,10 +19,10 @@ * @file nrf5340_network.h * @brief CMSIS HeaderFile * @version 1 - * @date 29. April 2021 - * @note Generated by SVDConv V3.3.35 on Thursday, 29.04.2021 12:43:57 + * @date 19. November 2021 + * @note Generated by SVDConv V3.3.35 on Friday, 19.11.2021 12:45:14 * from File 'nrf5340_network.svd', - * last modified on Thursday, 29.04.2021 10:43:41 + * last modified on Friday, 19.11.2021 11:44:55 */ @@ -292,8 +292,9 @@ typedef struct { typedef struct { __IOM uint32_t RXDELAY; /*!< (@ 0x00000000) Sample delay for input serial data on MISO */ __IOM uint32_t CSNDUR; /*!< (@ 0x00000004) Minimum duration between edge of CSN and edge - of SCK and minimum duration CSN must stay - high between transactions */ + of SCK. When SHORTS.END_START is used, this + is also the minimum duration CSN must stay + high between transactions. */ } SPIM_IFTIMING_Type; /*!< Size = 8 (0x8) */ diff --git a/mdk/nrf5340_network.svd b/mdk/nrf5340_network.svd index dbc86a68a9..807c922bcd 100644 --- a/mdk/nrf5340_network.svd +++ b/mdk/nrf5340_network.svd @@ -158,6 +158,11 @@ POSSIBILITY OF SUCH DAMAGE. QKAA 0x514B4141 + + CLAA + CLAA + 0x434C4141 + Unspecified Unspecified @@ -185,6 +190,11 @@ POSSIBILITY OF SUCH DAMAGE. QKxx - 94-pin aQFN 0x2000 + + CL + CLxx - WLCSP + 0x2005 + Unspecified Unspecified @@ -15893,236 +15903,308 @@ POSSIBILITY OF SUCH DAMAGE. - - - - CHENSET - Channel enable set register - 0x504 - read-write - oneToSet - - CH0 - Channel 0 enable set register. Writing 0 has no effect. - 0 - 0 + CH16 + Enable or disable channel 16 + 16 + 16 - read Disabled - Read: Channel disabled + Disable channel 0 Enabled - Read: Channel enabled + Enable channel 1 + + + CH17 + Enable or disable channel 17 + 17 + 17 - write - Set - Write: Enable channel + Disabled + Disable channel + 0 + + + Enabled + Enable channel 1 - CH1 - Channel 1 enable set register. Writing 0 has no effect. - 1 - 1 + CH18 + Enable or disable channel 18 + 18 + 18 - read Disabled - Read: Channel disabled + Disable channel 0 Enabled - Read: Channel enabled + Enable channel 1 + + + CH19 + Enable or disable channel 19 + 19 + 19 - write - Set - Write: Enable channel + Disabled + Disable channel + 0 + + + Enabled + Enable channel 1 - CH2 - Channel 2 enable set register. Writing 0 has no effect. - 2 - 2 + CH20 + Enable or disable channel 20 + 20 + 20 - read Disabled - Read: Channel disabled + Disable channel 0 Enabled - Read: Channel enabled + Enable channel 1 + + + CH21 + Enable or disable channel 21 + 21 + 21 - write - Set - Write: Enable channel + Disabled + Disable channel + 0 + + + Enabled + Enable channel 1 - CH3 - Channel 3 enable set register. Writing 0 has no effect. - 3 - 3 + CH22 + Enable or disable channel 22 + 22 + 22 - read Disabled - Read: Channel disabled + Disable channel 0 Enabled - Read: Channel enabled + Enable channel 1 + + + CH23 + Enable or disable channel 23 + 23 + 23 - write - Set - Write: Enable channel + Disabled + Disable channel + 0 + + + Enabled + Enable channel 1 - CH4 - Channel 4 enable set register. Writing 0 has no effect. - 4 - 4 + CH24 + Enable or disable channel 24 + 24 + 24 - read Disabled - Read: Channel disabled + Disable channel 0 Enabled - Read: Channel enabled + Enable channel 1 + + + CH25 + Enable or disable channel 25 + 25 + 25 - write - Set - Write: Enable channel + Disabled + Disable channel + 0 + + + Enabled + Enable channel 1 - CH5 - Channel 5 enable set register. Writing 0 has no effect. - 5 - 5 + CH26 + Enable or disable channel 26 + 26 + 26 - read Disabled - Read: Channel disabled + Disable channel 0 Enabled - Read: Channel enabled + Enable channel 1 + + + CH27 + Enable or disable channel 27 + 27 + 27 - write - Set - Write: Enable channel + Disabled + Disable channel + 0 + + + Enabled + Enable channel 1 - CH6 - Channel 6 enable set register. Writing 0 has no effect. - 6 - 6 + CH28 + Enable or disable channel 28 + 28 + 28 - read Disabled - Read: Channel disabled + Disable channel 0 Enabled - Read: Channel enabled + Enable channel 1 + + + CH29 + Enable or disable channel 29 + 29 + 29 - write - Set - Write: Enable channel + Disabled + Disable channel + 0 + + + Enabled + Enable channel 1 - CH7 - Channel 7 enable set register. Writing 0 has no effect. - 7 - 7 + CH30 + Enable or disable channel 30 + 30 + 30 - read Disabled - Read: Channel disabled + Disable channel 0 Enabled - Read: Channel enabled + Enable channel 1 + + + CH31 + Enable or disable channel 31 + 31 + 31 - write - Set - Write: Enable channel + Disabled + Disable channel + 0 + + + Enabled + Enable channel 1 + + + + CHENSET + Channel enable set register + 0x504 + read-write + oneToSet + - CH8 - Channel 8 enable set register. Writing 0 has no effect. - 8 - 8 + CH0 + Channel 0 enable set register. Writing 0 has no effect. + 0 + 0 read @@ -16146,10 +16228,10 @@ POSSIBILITY OF SUCH DAMAGE. - CH9 - Channel 9 enable set register. Writing 0 has no effect. - 9 - 9 + CH1 + Channel 1 enable set register. Writing 0 has no effect. + 1 + 1 read @@ -16173,10 +16255,10 @@ POSSIBILITY OF SUCH DAMAGE. - CH10 - Channel 10 enable set register. Writing 0 has no effect. - 10 - 10 + CH2 + Channel 2 enable set register. Writing 0 has no effect. + 2 + 2 read @@ -16200,10 +16282,10 @@ POSSIBILITY OF SUCH DAMAGE. - CH11 - Channel 11 enable set register. Writing 0 has no effect. - 11 - 11 + CH3 + Channel 3 enable set register. Writing 0 has no effect. + 3 + 3 read @@ -16227,10 +16309,10 @@ POSSIBILITY OF SUCH DAMAGE. - CH12 - Channel 12 enable set register. Writing 0 has no effect. - 12 - 12 + CH4 + Channel 4 enable set register. Writing 0 has no effect. + 4 + 4 read @@ -16254,10 +16336,10 @@ POSSIBILITY OF SUCH DAMAGE. - CH13 - Channel 13 enable set register. Writing 0 has no effect. - 13 - 13 + CH5 + Channel 5 enable set register. Writing 0 has no effect. + 5 + 5 read @@ -16281,10 +16363,10 @@ POSSIBILITY OF SUCH DAMAGE. - CH14 - Channel 14 enable set register. Writing 0 has no effect. - 14 - 14 + CH6 + Channel 6 enable set register. Writing 0 has no effect. + 6 + 6 read @@ -16308,10 +16390,10 @@ POSSIBILITY OF SUCH DAMAGE. - CH15 - Channel 15 enable set register. Writing 0 has no effect. - 15 - 15 + CH7 + Channel 7 enable set register. Writing 0 has no effect. + 7 + 7 read @@ -16334,20 +16416,11 @@ POSSIBILITY OF SUCH DAMAGE. - - - - CHENCLR - Channel enable clear register - 0x508 - read-write - oneToClear - - CH0 - Channel 0 enable clear register. Writing 0 has no effect. - 0 - 0 + CH8 + Channel 8 enable set register. Writing 0 has no effect. + 8 + 8 read @@ -16364,17 +16437,17 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Write: Disable channel + Set + Write: Enable channel 1 - CH1 - Channel 1 enable clear register. Writing 0 has no effect. - 1 - 1 + CH9 + Channel 9 enable set register. Writing 0 has no effect. + 9 + 9 read @@ -16391,17 +16464,17 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Write: Disable channel + Set + Write: Enable channel 1 - CH2 - Channel 2 enable clear register. Writing 0 has no effect. - 2 - 2 + CH10 + Channel 10 enable set register. Writing 0 has no effect. + 10 + 10 read @@ -16418,17 +16491,17 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Write: Disable channel + Set + Write: Enable channel 1 - CH3 - Channel 3 enable clear register. Writing 0 has no effect. - 3 - 3 + CH11 + Channel 11 enable set register. Writing 0 has no effect. + 11 + 11 read @@ -16445,17 +16518,17 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Write: Disable channel + Set + Write: Enable channel 1 - CH4 - Channel 4 enable clear register. Writing 0 has no effect. - 4 - 4 + CH12 + Channel 12 enable set register. Writing 0 has no effect. + 12 + 12 read @@ -16472,17 +16545,17 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Write: Disable channel + Set + Write: Enable channel 1 - CH5 - Channel 5 enable clear register. Writing 0 has no effect. - 5 - 5 + CH13 + Channel 13 enable set register. Writing 0 has no effect. + 13 + 13 read @@ -16499,17 +16572,17 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Write: Disable channel + Set + Write: Enable channel 1 - CH6 - Channel 6 enable clear register. Writing 0 has no effect. - 6 - 6 + CH14 + Channel 14 enable set register. Writing 0 has no effect. + 14 + 14 read @@ -16526,17 +16599,17 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Write: Disable channel + Set + Write: Enable channel 1 - CH7 - Channel 7 enable clear register. Writing 0 has no effect. - 7 - 7 + CH15 + Channel 15 enable set register. Writing 0 has no effect. + 15 + 15 read @@ -16553,17 +16626,17 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Write: Disable channel + Set + Write: Enable channel 1 - CH8 - Channel 8 enable clear register. Writing 0 has no effect. - 8 - 8 + CH16 + Channel 16 enable set register. Writing 0 has no effect. + 16 + 16 read @@ -16580,17 +16653,17 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Write: Disable channel + Set + Write: Enable channel 1 - CH9 - Channel 9 enable clear register. Writing 0 has no effect. - 9 - 9 + CH17 + Channel 17 enable set register. Writing 0 has no effect. + 17 + 17 read @@ -16607,17 +16680,17 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Write: Disable channel + Set + Write: Enable channel 1 - CH10 - Channel 10 enable clear register. Writing 0 has no effect. - 10 - 10 + CH18 + Channel 18 enable set register. Writing 0 has no effect. + 18 + 18 read @@ -16634,17 +16707,17 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Write: Disable channel + Set + Write: Enable channel 1 - CH11 - Channel 11 enable clear register. Writing 0 has no effect. - 11 - 11 + CH19 + Channel 19 enable set register. Writing 0 has no effect. + 19 + 19 read @@ -16661,17 +16734,17 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Write: Disable channel + Set + Write: Enable channel 1 - CH12 - Channel 12 enable clear register. Writing 0 has no effect. - 12 - 12 + CH20 + Channel 20 enable set register. Writing 0 has no effect. + 20 + 20 read @@ -16688,17 +16761,17 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Write: Disable channel + Set + Write: Enable channel 1 - CH13 - Channel 13 enable clear register. Writing 0 has no effect. - 13 - 13 + CH21 + Channel 21 enable set register. Writing 0 has no effect. + 21 + 21 read @@ -16715,17 +16788,17 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Write: Disable channel + Set + Write: Enable channel 1 - CH14 - Channel 14 enable clear register. Writing 0 has no effect. - 14 - 14 + CH22 + Channel 22 enable set register. Writing 0 has no effect. + 22 + 22 read @@ -16742,17 +16815,17 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Write: Disable channel + Set + Write: Enable channel 1 - CH15 - Channel 15 enable clear register. Writing 0 has no effect. - 15 - 15 + CH23 + Channel 23 enable set register. Writing 0 has no effect. + 23 + 23 read @@ -16769,54 +16842,1143 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Write: Disable channel + Set + Write: Enable channel 1 - - - - 0x6 - 0x4 - CHG[%s] - Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled - 0x800 - read-write - - CH0 - Include or exclude channel 0 - 0 - 0 + CH24 + Channel 24 enable set register. Writing 0 has no effect. + 24 + 24 + read - Excluded - Exclude + Disabled + Read: Channel disabled 0 - Included - Include + Enabled + Read: Channel enabled 1 - - - CH1 - Include or exclude channel 1 - 1 - 1 + write - Excluded - Exclude - 0 - - - Included - Include + Set + Write: Enable channel + 1 + + + + + CH25 + Channel 25 enable set register. Writing 0 has no effect. + 25 + 25 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH26 + Channel 26 enable set register. Writing 0 has no effect. + 26 + 26 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH27 + Channel 27 enable set register. Writing 0 has no effect. + 27 + 27 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH28 + Channel 28 enable set register. Writing 0 has no effect. + 28 + 28 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH29 + Channel 29 enable set register. Writing 0 has no effect. + 29 + 29 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH30 + Channel 30 enable set register. Writing 0 has no effect. + 30 + 30 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH31 + Channel 31 enable set register. Writing 0 has no effect. + 31 + 31 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + + + CHENCLR + Channel enable clear register + 0x508 + read-write + oneToClear + + + CH0 + Channel 0 enable clear register. Writing 0 has no effect. + 0 + 0 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH1 + Channel 1 enable clear register. Writing 0 has no effect. + 1 + 1 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH2 + Channel 2 enable clear register. Writing 0 has no effect. + 2 + 2 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH3 + Channel 3 enable clear register. Writing 0 has no effect. + 3 + 3 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH4 + Channel 4 enable clear register. Writing 0 has no effect. + 4 + 4 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH5 + Channel 5 enable clear register. Writing 0 has no effect. + 5 + 5 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH6 + Channel 6 enable clear register. Writing 0 has no effect. + 6 + 6 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH7 + Channel 7 enable clear register. Writing 0 has no effect. + 7 + 7 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH8 + Channel 8 enable clear register. Writing 0 has no effect. + 8 + 8 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH9 + Channel 9 enable clear register. Writing 0 has no effect. + 9 + 9 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH10 + Channel 10 enable clear register. Writing 0 has no effect. + 10 + 10 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH11 + Channel 11 enable clear register. Writing 0 has no effect. + 11 + 11 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH12 + Channel 12 enable clear register. Writing 0 has no effect. + 12 + 12 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH13 + Channel 13 enable clear register. Writing 0 has no effect. + 13 + 13 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH14 + Channel 14 enable clear register. Writing 0 has no effect. + 14 + 14 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH15 + Channel 15 enable clear register. Writing 0 has no effect. + 15 + 15 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH16 + Channel 16 enable clear register. Writing 0 has no effect. + 16 + 16 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH17 + Channel 17 enable clear register. Writing 0 has no effect. + 17 + 17 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH18 + Channel 18 enable clear register. Writing 0 has no effect. + 18 + 18 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH19 + Channel 19 enable clear register. Writing 0 has no effect. + 19 + 19 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH20 + Channel 20 enable clear register. Writing 0 has no effect. + 20 + 20 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH21 + Channel 21 enable clear register. Writing 0 has no effect. + 21 + 21 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH22 + Channel 22 enable clear register. Writing 0 has no effect. + 22 + 22 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH23 + Channel 23 enable clear register. Writing 0 has no effect. + 23 + 23 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH24 + Channel 24 enable clear register. Writing 0 has no effect. + 24 + 24 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH25 + Channel 25 enable clear register. Writing 0 has no effect. + 25 + 25 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH26 + Channel 26 enable clear register. Writing 0 has no effect. + 26 + 26 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH27 + Channel 27 enable clear register. Writing 0 has no effect. + 27 + 27 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH28 + Channel 28 enable clear register. Writing 0 has no effect. + 28 + 28 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH29 + Channel 29 enable clear register. Writing 0 has no effect. + 29 + 29 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH30 + Channel 30 enable clear register. Writing 0 has no effect. + 30 + 30 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH31 + Channel 31 enable clear register. Writing 0 has no effect. + 31 + 31 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + + + 0x6 + 0x4 + CHG[%s] + Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled + 0x800 + read-write + + + CH0 + Include or exclude channel 0 + 0 + 0 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH1 + Include or exclude channel 1 + 1 + 1 + + + Excluded + Exclude + 0 + + + Included + Include 1 @@ -17073,6 +18235,294 @@ POSSIBILITY OF SUCH DAMAGE. + + CH16 + Include or exclude channel 16 + 16 + 16 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH17 + Include or exclude channel 17 + 17 + 17 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH18 + Include or exclude channel 18 + 18 + 18 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH19 + Include or exclude channel 19 + 19 + 19 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH20 + Include or exclude channel 20 + 20 + 20 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH21 + Include or exclude channel 21 + 21 + 21 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH22 + Include or exclude channel 22 + 22 + 22 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH23 + Include or exclude channel 23 + 23 + 23 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH24 + Include or exclude channel 24 + 24 + 24 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH25 + Include or exclude channel 25 + 25 + 25 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH26 + Include or exclude channel 26 + 26 + 26 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH27 + Include or exclude channel 27 + 27 + 27 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH28 + Include or exclude channel 28 + 28 + 28 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH29 + Include or exclude channel 29 + 29 + 29 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH30 + Include or exclude channel 30 + 30 + 30 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH31 + Include or exclude channel 31 + 31 + 31 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + @@ -22575,14 +24025,14 @@ POSSIBILITY OF SUCH DAMAGE. CSNDUR - Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions + Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is also the minimum duration CSN must stay high between transactions. 0x004 read-write 0x00000002 CSNDUR - Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns). + Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is the minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns). 0 7 diff --git a/mdk/nrf5340_network_bitfields.h b/mdk/nrf5340_network_bitfields.h index 83cf42981b..f63655b35a 100644 --- a/mdk/nrf5340_network_bitfields.h +++ b/mdk/nrf5340_network_bitfields.h @@ -1604,6 +1604,102 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: DPPIC_CHEN */ /* Description: Channel enable register */ +/* Bit 31 : Enable or disable channel 31 */ +#define DPPIC_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define DPPIC_CHEN_CH31_Msk (0x1UL << DPPIC_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define DPPIC_CHEN_CH31_Disabled (0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH31_Enabled (1UL) /*!< Enable channel */ + +/* Bit 30 : Enable or disable channel 30 */ +#define DPPIC_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define DPPIC_CHEN_CH30_Msk (0x1UL << DPPIC_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define DPPIC_CHEN_CH30_Disabled (0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH30_Enabled (1UL) /*!< Enable channel */ + +/* Bit 29 : Enable or disable channel 29 */ +#define DPPIC_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define DPPIC_CHEN_CH29_Msk (0x1UL << DPPIC_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define DPPIC_CHEN_CH29_Disabled (0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH29_Enabled (1UL) /*!< Enable channel */ + +/* Bit 28 : Enable or disable channel 28 */ +#define DPPIC_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define DPPIC_CHEN_CH28_Msk (0x1UL << DPPIC_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define DPPIC_CHEN_CH28_Disabled (0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH28_Enabled (1UL) /*!< Enable channel */ + +/* Bit 27 : Enable or disable channel 27 */ +#define DPPIC_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define DPPIC_CHEN_CH27_Msk (0x1UL << DPPIC_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define DPPIC_CHEN_CH27_Disabled (0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH27_Enabled (1UL) /*!< Enable channel */ + +/* Bit 26 : Enable or disable channel 26 */ +#define DPPIC_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define DPPIC_CHEN_CH26_Msk (0x1UL << DPPIC_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define DPPIC_CHEN_CH26_Disabled (0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH26_Enabled (1UL) /*!< Enable channel */ + +/* Bit 25 : Enable or disable channel 25 */ +#define DPPIC_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define DPPIC_CHEN_CH25_Msk (0x1UL << DPPIC_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define DPPIC_CHEN_CH25_Disabled (0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH25_Enabled (1UL) /*!< Enable channel */ + +/* Bit 24 : Enable or disable channel 24 */ +#define DPPIC_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define DPPIC_CHEN_CH24_Msk (0x1UL << DPPIC_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define DPPIC_CHEN_CH24_Disabled (0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH24_Enabled (1UL) /*!< Enable channel */ + +/* Bit 23 : Enable or disable channel 23 */ +#define DPPIC_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define DPPIC_CHEN_CH23_Msk (0x1UL << DPPIC_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define DPPIC_CHEN_CH23_Disabled (0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH23_Enabled (1UL) /*!< Enable channel */ + +/* Bit 22 : Enable or disable channel 22 */ +#define DPPIC_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define DPPIC_CHEN_CH22_Msk (0x1UL << DPPIC_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define DPPIC_CHEN_CH22_Disabled (0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH22_Enabled (1UL) /*!< Enable channel */ + +/* Bit 21 : Enable or disable channel 21 */ +#define DPPIC_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define DPPIC_CHEN_CH21_Msk (0x1UL << DPPIC_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define DPPIC_CHEN_CH21_Disabled (0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH21_Enabled (1UL) /*!< Enable channel */ + +/* Bit 20 : Enable or disable channel 20 */ +#define DPPIC_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define DPPIC_CHEN_CH20_Msk (0x1UL << DPPIC_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define DPPIC_CHEN_CH20_Disabled (0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH20_Enabled (1UL) /*!< Enable channel */ + +/* Bit 19 : Enable or disable channel 19 */ +#define DPPIC_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define DPPIC_CHEN_CH19_Msk (0x1UL << DPPIC_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define DPPIC_CHEN_CH19_Disabled (0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH19_Enabled (1UL) /*!< Enable channel */ + +/* Bit 18 : Enable or disable channel 18 */ +#define DPPIC_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define DPPIC_CHEN_CH18_Msk (0x1UL << DPPIC_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define DPPIC_CHEN_CH18_Disabled (0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH18_Enabled (1UL) /*!< Enable channel */ + +/* Bit 17 : Enable or disable channel 17 */ +#define DPPIC_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define DPPIC_CHEN_CH17_Msk (0x1UL << DPPIC_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define DPPIC_CHEN_CH17_Disabled (0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH17_Enabled (1UL) /*!< Enable channel */ + +/* Bit 16 : Enable or disable channel 16 */ +#define DPPIC_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define DPPIC_CHEN_CH16_Msk (0x1UL << DPPIC_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define DPPIC_CHEN_CH16_Disabled (0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH16_Enabled (1UL) /*!< Enable channel */ + /* Bit 15 : Enable or disable channel 15 */ #define DPPIC_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */ #define DPPIC_CHEN_CH15_Msk (0x1UL << DPPIC_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */ @@ -1703,6 +1799,118 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: DPPIC_CHENSET */ /* Description: Channel enable set register */ +/* Bit 31 : Channel 31 enable set register. Writing 0 has no effect. */ +#define DPPIC_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define DPPIC_CHENSET_CH31_Msk (0x1UL << DPPIC_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define DPPIC_CHENSET_CH31_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH31_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 30 : Channel 30 enable set register. Writing 0 has no effect. */ +#define DPPIC_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define DPPIC_CHENSET_CH30_Msk (0x1UL << DPPIC_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define DPPIC_CHENSET_CH30_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH30_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 29 : Channel 29 enable set register. Writing 0 has no effect. */ +#define DPPIC_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define DPPIC_CHENSET_CH29_Msk (0x1UL << DPPIC_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define DPPIC_CHENSET_CH29_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH29_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 28 : Channel 28 enable set register. Writing 0 has no effect. */ +#define DPPIC_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define DPPIC_CHENSET_CH28_Msk (0x1UL << DPPIC_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define DPPIC_CHENSET_CH28_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH28_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 27 : Channel 27 enable set register. Writing 0 has no effect. */ +#define DPPIC_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define DPPIC_CHENSET_CH27_Msk (0x1UL << DPPIC_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define DPPIC_CHENSET_CH27_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH27_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 26 : Channel 26 enable set register. Writing 0 has no effect. */ +#define DPPIC_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define DPPIC_CHENSET_CH26_Msk (0x1UL << DPPIC_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define DPPIC_CHENSET_CH26_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH26_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 25 : Channel 25 enable set register. Writing 0 has no effect. */ +#define DPPIC_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define DPPIC_CHENSET_CH25_Msk (0x1UL << DPPIC_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define DPPIC_CHENSET_CH25_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH25_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 24 : Channel 24 enable set register. Writing 0 has no effect. */ +#define DPPIC_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define DPPIC_CHENSET_CH24_Msk (0x1UL << DPPIC_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define DPPIC_CHENSET_CH24_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH24_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 23 : Channel 23 enable set register. Writing 0 has no effect. */ +#define DPPIC_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define DPPIC_CHENSET_CH23_Msk (0x1UL << DPPIC_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define DPPIC_CHENSET_CH23_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH23_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 22 : Channel 22 enable set register. Writing 0 has no effect. */ +#define DPPIC_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define DPPIC_CHENSET_CH22_Msk (0x1UL << DPPIC_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define DPPIC_CHENSET_CH22_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH22_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 21 : Channel 21 enable set register. Writing 0 has no effect. */ +#define DPPIC_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define DPPIC_CHENSET_CH21_Msk (0x1UL << DPPIC_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define DPPIC_CHENSET_CH21_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH21_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 20 : Channel 20 enable set register. Writing 0 has no effect. */ +#define DPPIC_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define DPPIC_CHENSET_CH20_Msk (0x1UL << DPPIC_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define DPPIC_CHENSET_CH20_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH20_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 19 : Channel 19 enable set register. Writing 0 has no effect. */ +#define DPPIC_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define DPPIC_CHENSET_CH19_Msk (0x1UL << DPPIC_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define DPPIC_CHENSET_CH19_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH19_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 18 : Channel 18 enable set register. Writing 0 has no effect. */ +#define DPPIC_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define DPPIC_CHENSET_CH18_Msk (0x1UL << DPPIC_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define DPPIC_CHENSET_CH18_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH18_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 17 : Channel 17 enable set register. Writing 0 has no effect. */ +#define DPPIC_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define DPPIC_CHENSET_CH17_Msk (0x1UL << DPPIC_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define DPPIC_CHENSET_CH17_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH17_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 16 : Channel 16 enable set register. Writing 0 has no effect. */ +#define DPPIC_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define DPPIC_CHENSET_CH16_Msk (0x1UL << DPPIC_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define DPPIC_CHENSET_CH16_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH16_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */ + /* Bit 15 : Channel 15 enable set register. Writing 0 has no effect. */ #define DPPIC_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */ #define DPPIC_CHENSET_CH15_Msk (0x1UL << DPPIC_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */ @@ -1818,6 +2026,118 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: DPPIC_CHENCLR */ /* Description: Channel enable clear register */ +/* Bit 31 : Channel 31 enable clear register. Writing 0 has no effect. */ +#define DPPIC_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define DPPIC_CHENCLR_CH31_Msk (0x1UL << DPPIC_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define DPPIC_CHENCLR_CH31_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH31_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH31_Clear (1UL) /*!< Write: Disable channel */ + +/* Bit 30 : Channel 30 enable clear register. Writing 0 has no effect. */ +#define DPPIC_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define DPPIC_CHENCLR_CH30_Msk (0x1UL << DPPIC_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define DPPIC_CHENCLR_CH30_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH30_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH30_Clear (1UL) /*!< Write: Disable channel */ + +/* Bit 29 : Channel 29 enable clear register. Writing 0 has no effect. */ +#define DPPIC_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define DPPIC_CHENCLR_CH29_Msk (0x1UL << DPPIC_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define DPPIC_CHENCLR_CH29_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH29_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH29_Clear (1UL) /*!< Write: Disable channel */ + +/* Bit 28 : Channel 28 enable clear register. Writing 0 has no effect. */ +#define DPPIC_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define DPPIC_CHENCLR_CH28_Msk (0x1UL << DPPIC_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define DPPIC_CHENCLR_CH28_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH28_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH28_Clear (1UL) /*!< Write: Disable channel */ + +/* Bit 27 : Channel 27 enable clear register. Writing 0 has no effect. */ +#define DPPIC_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define DPPIC_CHENCLR_CH27_Msk (0x1UL << DPPIC_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define DPPIC_CHENCLR_CH27_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH27_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH27_Clear (1UL) /*!< Write: Disable channel */ + +/* Bit 26 : Channel 26 enable clear register. Writing 0 has no effect. */ +#define DPPIC_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define DPPIC_CHENCLR_CH26_Msk (0x1UL << DPPIC_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define DPPIC_CHENCLR_CH26_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH26_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH26_Clear (1UL) /*!< Write: Disable channel */ + +/* Bit 25 : Channel 25 enable clear register. Writing 0 has no effect. */ +#define DPPIC_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define DPPIC_CHENCLR_CH25_Msk (0x1UL << DPPIC_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define DPPIC_CHENCLR_CH25_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH25_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH25_Clear (1UL) /*!< Write: Disable channel */ + +/* Bit 24 : Channel 24 enable clear register. Writing 0 has no effect. */ +#define DPPIC_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define DPPIC_CHENCLR_CH24_Msk (0x1UL << DPPIC_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define DPPIC_CHENCLR_CH24_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH24_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH24_Clear (1UL) /*!< Write: Disable channel */ + +/* Bit 23 : Channel 23 enable clear register. Writing 0 has no effect. */ +#define DPPIC_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define DPPIC_CHENCLR_CH23_Msk (0x1UL << DPPIC_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define DPPIC_CHENCLR_CH23_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH23_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH23_Clear (1UL) /*!< Write: Disable channel */ + +/* Bit 22 : Channel 22 enable clear register. Writing 0 has no effect. */ +#define DPPIC_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define DPPIC_CHENCLR_CH22_Msk (0x1UL << DPPIC_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define DPPIC_CHENCLR_CH22_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH22_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH22_Clear (1UL) /*!< Write: Disable channel */ + +/* Bit 21 : Channel 21 enable clear register. Writing 0 has no effect. */ +#define DPPIC_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define DPPIC_CHENCLR_CH21_Msk (0x1UL << DPPIC_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define DPPIC_CHENCLR_CH21_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH21_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH21_Clear (1UL) /*!< Write: Disable channel */ + +/* Bit 20 : Channel 20 enable clear register. Writing 0 has no effect. */ +#define DPPIC_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define DPPIC_CHENCLR_CH20_Msk (0x1UL << DPPIC_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define DPPIC_CHENCLR_CH20_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH20_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH20_Clear (1UL) /*!< Write: Disable channel */ + +/* Bit 19 : Channel 19 enable clear register. Writing 0 has no effect. */ +#define DPPIC_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define DPPIC_CHENCLR_CH19_Msk (0x1UL << DPPIC_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define DPPIC_CHENCLR_CH19_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH19_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH19_Clear (1UL) /*!< Write: Disable channel */ + +/* Bit 18 : Channel 18 enable clear register. Writing 0 has no effect. */ +#define DPPIC_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define DPPIC_CHENCLR_CH18_Msk (0x1UL << DPPIC_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define DPPIC_CHENCLR_CH18_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH18_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH18_Clear (1UL) /*!< Write: Disable channel */ + +/* Bit 17 : Channel 17 enable clear register. Writing 0 has no effect. */ +#define DPPIC_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define DPPIC_CHENCLR_CH17_Msk (0x1UL << DPPIC_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define DPPIC_CHENCLR_CH17_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH17_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH17_Clear (1UL) /*!< Write: Disable channel */ + +/* Bit 16 : Channel 16 enable clear register. Writing 0 has no effect. */ +#define DPPIC_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define DPPIC_CHENCLR_CH16_Msk (0x1UL << DPPIC_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define DPPIC_CHENCLR_CH16_Disabled (0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH16_Enabled (1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH16_Clear (1UL) /*!< Write: Disable channel */ + /* Bit 15 : Channel 15 enable clear register. Writing 0 has no effect. */ #define DPPIC_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */ #define DPPIC_CHENCLR_CH15_Msk (0x1UL << DPPIC_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */ @@ -1933,6 +2253,102 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: DPPIC_CHG */ /* Description: Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled */ +/* Bit 31 : Include or exclude channel 31 */ +#define DPPIC_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define DPPIC_CHG_CH31_Msk (0x1UL << DPPIC_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define DPPIC_CHG_CH31_Excluded (0UL) /*!< Exclude */ +#define DPPIC_CHG_CH31_Included (1UL) /*!< Include */ + +/* Bit 30 : Include or exclude channel 30 */ +#define DPPIC_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define DPPIC_CHG_CH30_Msk (0x1UL << DPPIC_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define DPPIC_CHG_CH30_Excluded (0UL) /*!< Exclude */ +#define DPPIC_CHG_CH30_Included (1UL) /*!< Include */ + +/* Bit 29 : Include or exclude channel 29 */ +#define DPPIC_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define DPPIC_CHG_CH29_Msk (0x1UL << DPPIC_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define DPPIC_CHG_CH29_Excluded (0UL) /*!< Exclude */ +#define DPPIC_CHG_CH29_Included (1UL) /*!< Include */ + +/* Bit 28 : Include or exclude channel 28 */ +#define DPPIC_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define DPPIC_CHG_CH28_Msk (0x1UL << DPPIC_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define DPPIC_CHG_CH28_Excluded (0UL) /*!< Exclude */ +#define DPPIC_CHG_CH28_Included (1UL) /*!< Include */ + +/* Bit 27 : Include or exclude channel 27 */ +#define DPPIC_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define DPPIC_CHG_CH27_Msk (0x1UL << DPPIC_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define DPPIC_CHG_CH27_Excluded (0UL) /*!< Exclude */ +#define DPPIC_CHG_CH27_Included (1UL) /*!< Include */ + +/* Bit 26 : Include or exclude channel 26 */ +#define DPPIC_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define DPPIC_CHG_CH26_Msk (0x1UL << DPPIC_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define DPPIC_CHG_CH26_Excluded (0UL) /*!< Exclude */ +#define DPPIC_CHG_CH26_Included (1UL) /*!< Include */ + +/* Bit 25 : Include or exclude channel 25 */ +#define DPPIC_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define DPPIC_CHG_CH25_Msk (0x1UL << DPPIC_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define DPPIC_CHG_CH25_Excluded (0UL) /*!< Exclude */ +#define DPPIC_CHG_CH25_Included (1UL) /*!< Include */ + +/* Bit 24 : Include or exclude channel 24 */ +#define DPPIC_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define DPPIC_CHG_CH24_Msk (0x1UL << DPPIC_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define DPPIC_CHG_CH24_Excluded (0UL) /*!< Exclude */ +#define DPPIC_CHG_CH24_Included (1UL) /*!< Include */ + +/* Bit 23 : Include or exclude channel 23 */ +#define DPPIC_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define DPPIC_CHG_CH23_Msk (0x1UL << DPPIC_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define DPPIC_CHG_CH23_Excluded (0UL) /*!< Exclude */ +#define DPPIC_CHG_CH23_Included (1UL) /*!< Include */ + +/* Bit 22 : Include or exclude channel 22 */ +#define DPPIC_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define DPPIC_CHG_CH22_Msk (0x1UL << DPPIC_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define DPPIC_CHG_CH22_Excluded (0UL) /*!< Exclude */ +#define DPPIC_CHG_CH22_Included (1UL) /*!< Include */ + +/* Bit 21 : Include or exclude channel 21 */ +#define DPPIC_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define DPPIC_CHG_CH21_Msk (0x1UL << DPPIC_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define DPPIC_CHG_CH21_Excluded (0UL) /*!< Exclude */ +#define DPPIC_CHG_CH21_Included (1UL) /*!< Include */ + +/* Bit 20 : Include or exclude channel 20 */ +#define DPPIC_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define DPPIC_CHG_CH20_Msk (0x1UL << DPPIC_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define DPPIC_CHG_CH20_Excluded (0UL) /*!< Exclude */ +#define DPPIC_CHG_CH20_Included (1UL) /*!< Include */ + +/* Bit 19 : Include or exclude channel 19 */ +#define DPPIC_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define DPPIC_CHG_CH19_Msk (0x1UL << DPPIC_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define DPPIC_CHG_CH19_Excluded (0UL) /*!< Exclude */ +#define DPPIC_CHG_CH19_Included (1UL) /*!< Include */ + +/* Bit 18 : Include or exclude channel 18 */ +#define DPPIC_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define DPPIC_CHG_CH18_Msk (0x1UL << DPPIC_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define DPPIC_CHG_CH18_Excluded (0UL) /*!< Exclude */ +#define DPPIC_CHG_CH18_Included (1UL) /*!< Include */ + +/* Bit 17 : Include or exclude channel 17 */ +#define DPPIC_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define DPPIC_CHG_CH17_Msk (0x1UL << DPPIC_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define DPPIC_CHG_CH17_Excluded (0UL) /*!< Exclude */ +#define DPPIC_CHG_CH17_Included (1UL) /*!< Include */ + +/* Bit 16 : Include or exclude channel 16 */ +#define DPPIC_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define DPPIC_CHG_CH16_Msk (0x1UL << DPPIC_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define DPPIC_CHG_CH16_Excluded (0UL) /*!< Exclude */ +#define DPPIC_CHG_CH16_Included (1UL) /*!< Include */ + /* Bit 15 : Include or exclude channel 15 */ #define DPPIC_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */ #define DPPIC_CHG_CH15_Msk (0x1UL << DPPIC_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */ @@ -2569,6 +2985,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 31..0 : Part Variant, Hardware version and Production configuration, encoded as ASCII */ #define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */ #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ +#define FICR_INFO_VARIANT_VARIANT_CLAA (0x434C4141UL) /*!< CLAA */ #define FICR_INFO_VARIANT_VARIANT_QKAA (0x514B4141UL) /*!< QKAA */ #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ @@ -2579,6 +2996,7 @@ POSSIBILITY OF SUCH DAMAGE. #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ #define FICR_INFO_PACKAGE_PACKAGE_QK (0x2000UL) /*!< QKxx - 94-pin aQFN */ +#define FICR_INFO_PACKAGE_PACKAGE_CL (0x2005UL) /*!< CLxx - WLCSP */ #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ /* Register: FICR_INFO_RAM */ @@ -8825,9 +9243,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIM_IFTIMING_RXDELAY_RXDELAY_Msk (0x7UL << SPIM_IFTIMING_RXDELAY_RXDELAY_Pos) /*!< Bit mask of RXDELAY field. */ /* Register: SPIM_IFTIMING_CSNDUR */ -/* Description: Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions */ +/* Description: Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is also the minimum duration CSN must stay high between transactions. */ -/* Bits 7..0 : Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns). */ +/* Bits 7..0 : Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is the minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns). */ #define SPIM_IFTIMING_CSNDUR_CSNDUR_Pos (0UL) /*!< Position of CSNDUR field. */ #define SPIM_IFTIMING_CSNDUR_CSNDUR_Msk (0xFFUL << SPIM_IFTIMING_CSNDUR_CSNDUR_Pos) /*!< Bit mask of CSNDUR field. */ diff --git a/mdk/nrf5340_network_peripherals.h b/mdk/nrf5340_network_peripherals.h index 1c1e43a3b3..252012808e 100644 --- a/mdk/nrf5340_network_peripherals.h +++ b/mdk/nrf5340_network_peripherals.h @@ -115,7 +115,7 @@ POSSIBILITY OF SUCH DAMAGE. #define DPPI_PRESENT #define DPPI_COUNT 1 -#define DPPI_CH_NUM 16 +#define DPPI_CH_NUM 32 #define DPPI_GROUP_NUM 6 /* Event Generator Unit */ diff --git a/mdk/nrf5340_xxaa_application.ld b/mdk/nrf5340_xxaa_application.ld index f649da6fb9..89cb624ddb 100644 --- a/mdk/nrf5340_xxaa_application.ld +++ b/mdk/nrf5340_xxaa_application.ld @@ -8,7 +8,7 @@ MEMORY FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x100000 EXTFLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x8000000 RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x40000 - RAM1 (rwx) : ORIGIN = 0x20040000, LENGTH = 0x40000 + RAM1 (rwx) : ORIGIN = 0x20040000, LENGTH = 0x3F000 } diff --git a/mdk/nrf53_erratas.h b/mdk/nrf53_erratas.h index 4efda57785..27c32e471c 100644 --- a/mdk/nrf53_erratas.h +++ b/mdk/nrf53_erratas.h @@ -132,6 +132,8 @@ static bool nrf53_errata_117(void) __UNUSED; static bool nrf53_errata_119(void) __UNUSED; static bool nrf53_errata_121(void) __UNUSED; static bool nrf53_errata_122(void) __UNUSED; +static bool nrf53_errata_134(void) __UNUSED; +static bool nrf53_errata_138(void) __UNUSED; /* ========= Errata 1 ========= */ #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -155,8 +157,13 @@ static bool nrf53_errata_1(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -205,8 +212,13 @@ static bool nrf53_errata_2(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -255,8 +267,13 @@ static bool nrf53_errata_3(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -305,8 +322,13 @@ static bool nrf53_errata_4(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -355,8 +377,13 @@ static bool nrf53_errata_5(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -455,8 +482,13 @@ static bool nrf53_errata_7(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -505,8 +537,13 @@ static bool nrf53_errata_8(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -555,8 +592,13 @@ static bool nrf53_errata_9(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -705,8 +747,13 @@ static bool nrf53_errata_12(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -756,8 +803,13 @@ static bool nrf53_errata_13(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #elif defined(NRF_NETWORK) uint32_t var1 = *(uint32_t *)0x01FF0130ul; uint32_t var2 = *(uint32_t *)0x01FF0134ul; @@ -861,8 +913,13 @@ static bool nrf53_errata_15(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #elif defined(NRF_NETWORK) uint32_t var1 = *(uint32_t *)0x01FF0130ul; uint32_t var2 = *(uint32_t *)0x01FF0134ul; @@ -965,8 +1022,13 @@ static bool nrf53_errata_18(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -1015,8 +1077,13 @@ static bool nrf53_errata_19(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -1066,8 +1133,13 @@ static bool nrf53_errata_20(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #elif defined(NRF_NETWORK) uint32_t var1 = *(uint32_t *)0x01FF0130ul; uint32_t var2 = *(uint32_t *)0x01FF0134ul; @@ -1121,8 +1193,13 @@ static bool nrf53_errata_21(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #elif defined(NRF_NETWORK) uint32_t var1 = *(uint32_t *)0x01FF0130ul; uint32_t var2 = *(uint32_t *)0x01FF0134ul; @@ -1175,8 +1252,13 @@ static bool nrf53_errata_22(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -1225,8 +1307,13 @@ static bool nrf53_errata_23(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -1276,8 +1363,13 @@ static bool nrf53_errata_26(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #elif defined(NRF_NETWORK) uint32_t var1 = *(uint32_t *)0x01FF0130ul; uint32_t var2 = *(uint32_t *)0x01FF0134ul; @@ -1331,8 +1423,13 @@ static bool nrf53_errata_27(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #elif defined(NRF_NETWORK) uint32_t var1 = *(uint32_t *)0x01FF0130ul; uint32_t var2 = *(uint32_t *)0x01FF0134ul; @@ -1386,8 +1483,13 @@ static bool nrf53_errata_28(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #elif defined(NRF_NETWORK) uint32_t var1 = *(uint32_t *)0x01FF0130ul; uint32_t var2 = *(uint32_t *)0x01FF0134ul; @@ -1541,8 +1643,13 @@ static bool nrf53_errata_31(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #elif defined(NRF_NETWORK) uint32_t var1 = *(uint32_t *)0x01FF0130ul; uint32_t var2 = *(uint32_t *)0x01FF0134ul; @@ -1645,8 +1752,13 @@ static bool nrf53_errata_33(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -1745,8 +1857,13 @@ static bool nrf53_errata_36(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -1811,8 +1928,13 @@ static bool nrf53_errata_42(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -1861,8 +1983,13 @@ static bool nrf53_errata_43(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -1912,8 +2039,13 @@ static bool nrf53_errata_44(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #elif defined(NRF_NETWORK) uint32_t var1 = *(uint32_t *)0x01FF0130ul; uint32_t var2 = *(uint32_t *)0x01FF0134ul; @@ -1966,8 +2098,13 @@ static bool nrf53_errata_45(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -2016,8 +2153,13 @@ static bool nrf53_errata_46(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -2067,8 +2209,13 @@ static bool nrf53_errata_47(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #elif defined(NRF_NETWORK) uint32_t var1 = *(uint32_t *)0x01FF0130ul; uint32_t var2 = *(uint32_t *)0x01FF0134ul; @@ -2122,8 +2269,13 @@ static bool nrf53_errata_49(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #elif defined(NRF_NETWORK) uint32_t var1 = *(uint32_t *)0x01FF0130ul; uint32_t var2 = *(uint32_t *)0x01FF0134ul; @@ -2176,8 +2328,13 @@ static bool nrf53_errata_50(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -2226,8 +2383,13 @@ static bool nrf53_errata_51(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -2277,8 +2439,13 @@ static bool nrf53_errata_52(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #elif defined(NRF_NETWORK) uint32_t var1 = *(uint32_t *)0x01FF0130ul; uint32_t var2 = *(uint32_t *)0x01FF0134ul; @@ -2331,8 +2498,13 @@ static bool nrf53_errata_53(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -2432,8 +2604,13 @@ static bool nrf53_errata_55(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #elif defined(NRF_NETWORK) uint32_t var1 = *(uint32_t *)0x01FF0130ul; uint32_t var2 = *(uint32_t *)0x01FF0134ul; @@ -2486,8 +2663,13 @@ static bool nrf53_errata_57(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -2536,8 +2718,13 @@ static bool nrf53_errata_58(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -2586,8 +2773,13 @@ static bool nrf53_errata_59(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -2637,8 +2829,13 @@ static bool nrf53_errata_62(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #elif defined(NRF_NETWORK) uint32_t var1 = *(uint32_t *)0x01FF0130ul; uint32_t var2 = *(uint32_t *)0x01FF0134ul; @@ -2691,8 +2888,13 @@ static bool nrf53_errata_64(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -2741,8 +2943,13 @@ static bool nrf53_errata_65(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -2791,8 +2998,13 @@ static bool nrf53_errata_66(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -2842,8 +3054,13 @@ static bool nrf53_errata_67(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #elif defined(NRF_NETWORK) uint32_t var1 = *(uint32_t *)0x01FF0130ul; uint32_t var2 = *(uint32_t *)0x01FF0134ul; @@ -2896,8 +3113,13 @@ static bool nrf53_errata_69(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -2946,8 +3168,13 @@ static bool nrf53_errata_70(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -2996,8 +3223,13 @@ static bool nrf53_errata_71(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -3046,8 +3278,13 @@ static bool nrf53_errata_72(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -3097,8 +3334,13 @@ static bool nrf53_errata_73(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #elif defined(NRF_NETWORK) uint32_t var1 = *(uint32_t *)0x01FF0130ul; uint32_t var2 = *(uint32_t *)0x01FF0134ul; @@ -3152,8 +3394,13 @@ static bool nrf53_errata_74(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #elif defined(NRF_NETWORK) uint32_t var1 = *(uint32_t *)0x01FF0130ul; uint32_t var2 = *(uint32_t *)0x01FF0134ul; @@ -3206,8 +3453,13 @@ static bool nrf53_errata_75(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -3256,8 +3508,13 @@ static bool nrf53_errata_76(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -3307,8 +3564,13 @@ static bool nrf53_errata_77(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #elif defined(NRF_NETWORK) uint32_t var1 = *(uint32_t *)0x01FF0130ul; uint32_t var2 = *(uint32_t *)0x01FF0134ul; @@ -3361,8 +3623,13 @@ static bool nrf53_errata_79(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -3411,8 +3678,13 @@ static bool nrf53_errata_80(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -3461,8 +3733,13 @@ static bool nrf53_errata_81(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -3511,8 +3788,13 @@ static bool nrf53_errata_82(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -3561,8 +3843,13 @@ static bool nrf53_errata_83(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -3611,8 +3898,13 @@ static bool nrf53_errata_84(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -3661,8 +3953,13 @@ static bool nrf53_errata_85(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -3712,8 +4009,13 @@ static bool nrf53_errata_86(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #elif defined(NRF_NETWORK) uint32_t var1 = *(uint32_t *)0x01FF0130ul; uint32_t var2 = *(uint32_t *)0x01FF0134ul; @@ -3816,8 +4118,13 @@ static bool nrf53_errata_90(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -4017,8 +4324,13 @@ static bool nrf53_errata_97(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #elif defined(NRF_NETWORK) uint32_t var1 = *(uint32_t *)0x01FF0130ul; uint32_t var2 = *(uint32_t *)0x01FF0134ul; @@ -4071,8 +4383,13 @@ static bool nrf53_errata_99(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -4137,8 +4454,13 @@ static bool nrf53_errata_105(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -4187,8 +4509,13 @@ static bool nrf53_errata_106(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -4237,8 +4564,13 @@ static bool nrf53_errata_107(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -4287,8 +4619,13 @@ static bool nrf53_errata_109(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -4337,8 +4674,13 @@ static bool nrf53_errata_110(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -4387,8 +4729,13 @@ static bool nrf53_errata_112(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -4537,8 +4884,13 @@ static bool nrf53_errata_115(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -4737,8 +5089,13 @@ static bool nrf53_errata_121(void) #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -4815,4 +5172,36 @@ static bool nrf53_errata_122(void) #endif } +/* ========= Errata 134 ========= */ +#define NRF53_ERRATA_134_PRESENT 0 + +#ifndef NRF53_ERRATA_134_ENABLE_WORKAROUND + #define NRF53_ERRATA_134_ENABLE_WORKAROUND NRF53_ERRATA_134_PRESENT +#endif + +static bool nrf53_errata_134(void) +{ + #ifndef NRF53_SERIES + return false; + #else + return false; + #endif +} + +/* ========= Errata 138 ========= */ +#define NRF53_ERRATA_138_PRESENT 0 + +#ifndef NRF53_ERRATA_138_ENABLE_WORKAROUND + #define NRF53_ERRATA_138_ENABLE_WORKAROUND NRF53_ERRATA_138_PRESENT +#endif + +static bool nrf53_errata_138(void) +{ + #ifndef NRF53_SERIES + return false; + #else + return false; + #endif +} + #endif /* NRF53_ERRATAS_H */ diff --git a/mdk/nrf9160.h b/mdk/nrf9160.h index 333bc313e2..28061efdf7 100644 --- a/mdk/nrf9160.h +++ b/mdk/nrf9160.h @@ -32,10 +32,10 @@ * @file nrf9160.h * @brief CMSIS HeaderFile * @version 1 - * @date 29. April 2021 - * @note Generated by SVDConv V3.3.35 on Thursday, 29.04.2021 12:43:58 + * @date 19. November 2021 + * @note Generated by SVDConv V3.3.35 on Friday, 19.11.2021 12:45:15 * from File 'nrf9160.svd', - * last modified on Thursday, 29.04.2021 10:43:41 + * last modified on Friday, 19.11.2021 11:44:55 */ diff --git a/mdk/nrf9160_peripherals.h b/mdk/nrf9160_peripherals.h index 18fcd0a773..dc985a8d99 100644 --- a/mdk/nrf9160_peripherals.h +++ b/mdk/nrf9160_peripherals.h @@ -111,46 +111,46 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIM2_MAX_DATARATE 8 #define SPIM3_MAX_DATARATE 8 -#define SPIM0_EASYDMA_MAXCNT_SIZE 12 -#define SPIM1_EASYDMA_MAXCNT_SIZE 12 -#define SPIM2_EASYDMA_MAXCNT_SIZE 12 -#define SPIM3_EASYDMA_MAXCNT_SIZE 12 +#define SPIM0_EASYDMA_MAXCNT_SIZE 13 +#define SPIM1_EASYDMA_MAXCNT_SIZE 13 +#define SPIM2_EASYDMA_MAXCNT_SIZE 13 +#define SPIM3_EASYDMA_MAXCNT_SIZE 13 /* Serial Peripheral Interface Slave with DMA*/ #define SPIS_PRESENT #define SPIS_COUNT 4 -#define SPIS0_EASYDMA_MAXCNT_SIZE 12 -#define SPIS1_EASYDMA_MAXCNT_SIZE 12 -#define SPIS2_EASYDMA_MAXCNT_SIZE 12 -#define SPIS3_EASYDMA_MAXCNT_SIZE 12 +#define SPIS0_EASYDMA_MAXCNT_SIZE 13 +#define SPIS1_EASYDMA_MAXCNT_SIZE 13 +#define SPIS2_EASYDMA_MAXCNT_SIZE 13 +#define SPIS3_EASYDMA_MAXCNT_SIZE 13 /* Two Wire Interface Master with DMA */ #define TWIM_PRESENT #define TWIM_COUNT 4 -#define TWIM0_EASYDMA_MAXCNT_SIZE 12 -#define TWIM1_EASYDMA_MAXCNT_SIZE 12 -#define TWIM2_EASYDMA_MAXCNT_SIZE 12 -#define TWIM3_EASYDMA_MAXCNT_SIZE 12 +#define TWIM0_EASYDMA_MAXCNT_SIZE 13 +#define TWIM1_EASYDMA_MAXCNT_SIZE 13 +#define TWIM2_EASYDMA_MAXCNT_SIZE 13 +#define TWIM3_EASYDMA_MAXCNT_SIZE 13 /* Two Wire Interface Slave with DMA */ #define TWIS_PRESENT #define TWIS_COUNT 4 -#define TWIS0_EASYDMA_MAXCNT_SIZE 12 -#define TWIS1_EASYDMA_MAXCNT_SIZE 12 -#define TWIS2_EASYDMA_MAXCNT_SIZE 12 -#define TWIS3_EASYDMA_MAXCNT_SIZE 12 +#define TWIS0_EASYDMA_MAXCNT_SIZE 13 +#define TWIS1_EASYDMA_MAXCNT_SIZE 13 +#define TWIS2_EASYDMA_MAXCNT_SIZE 13 +#define TWIS3_EASYDMA_MAXCNT_SIZE 13 /* Universal Asynchronous Receiver-Transmitter with DMA */ #define UARTE_PRESENT #define UARTE_COUNT 4 -#define UARTE0_EASYDMA_MAXCNT_SIZE 12 -#define UARTE1_EASYDMA_MAXCNT_SIZE 12 -#define UARTE2_EASYDMA_MAXCNT_SIZE 12 -#define UARTE3_EASYDMA_MAXCNT_SIZE 12 +#define UARTE0_EASYDMA_MAXCNT_SIZE 13 +#define UARTE1_EASYDMA_MAXCNT_SIZE 13 +#define UARTE2_EASYDMA_MAXCNT_SIZE 13 +#define UARTE3_EASYDMA_MAXCNT_SIZE 13 /* Successive Approximation Analog to Digital Converter */ #define SAADC_PRESENT @@ -204,6 +204,8 @@ POSSIBILITY OF SUCH DAMAGE. #define SPU_PRESENT #define SPU_COUNT 1 +#define SPU_RAMREGION_SIZE 0x2000ul + /* CRYPTOCELL */ #define CRYPTOCELL_PRESENT #define CRYPTOCELL_COUNT 1 diff --git a/mdk/nrf9160_xxaa.ld b/mdk/nrf9160_xxaa.ld index 06b720425e..beaba29bc3 100644 --- a/mdk/nrf9160_xxaa.ld +++ b/mdk/nrf9160_xxaa.ld @@ -6,7 +6,7 @@ GROUP(-lgcc -lc -lnosys) MEMORY { FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x100000 - RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x40000 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x3E000 } diff --git a/mdk/nrf91_erratas.h b/mdk/nrf91_erratas.h index b58d58e08d..b4e5576433 100644 --- a/mdk/nrf91_erratas.h +++ b/mdk/nrf91_erratas.h @@ -82,10 +82,16 @@ static bool nrf91_errata_1(void) return false; #else #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + __DSB(); if (var1 == 0x09) { switch(var2) @@ -120,10 +126,16 @@ static bool nrf91_errata_2(void) return false; #else #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + __DSB(); if (var1 == 0x09) { switch(var2) @@ -158,10 +170,16 @@ static bool nrf91_errata_4(void) return false; #else #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + __DSB(); if (var1 == 0x09) { switch(var2) @@ -196,10 +214,16 @@ static bool nrf91_errata_6(void) return false; #else #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + __DSB(); if (var1 == 0x09) { switch(var2) @@ -234,10 +258,16 @@ static bool nrf91_errata_7(void) return false; #else #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + __DSB(); if (var1 == 0x09) { switch(var2) @@ -272,10 +302,16 @@ static bool nrf91_errata_8(void) return false; #else #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + __DSB(); if (var1 == 0x09) { switch(var2) @@ -310,10 +346,16 @@ static bool nrf91_errata_9(void) return false; #else #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + __DSB(); if (var1 == 0x09) { switch(var2) @@ -348,10 +390,16 @@ static bool nrf91_errata_10(void) return false; #else #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + __DSB(); if (var1 == 0x09) { switch(var2) @@ -386,10 +434,16 @@ static bool nrf91_errata_12(void) return false; #else #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + __DSB(); if (var1 == 0x09) { switch(var2) @@ -424,10 +478,16 @@ static bool nrf91_errata_14(void) return false; #else #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + __DSB(); if (var1 == 0x09) { switch(var2) @@ -462,10 +522,16 @@ static bool nrf91_errata_15(void) return false; #else #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + __DSB(); if (var1 == 0x09) { switch(var2) @@ -500,10 +566,16 @@ static bool nrf91_errata_16(void) return false; #else #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + __DSB(); if (var1 == 0x09) { switch(var2) @@ -538,10 +610,16 @@ static bool nrf91_errata_17(void) return false; #else #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + __DSB(); if (var1 == 0x09) { switch(var2) @@ -576,10 +654,16 @@ static bool nrf91_errata_20(void) return false; #else #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + __DSB(); if (var1 == 0x09) { switch(var2) @@ -614,10 +698,16 @@ static bool nrf91_errata_21(void) return false; #else #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + __DSB(); if (var1 == 0x09) { switch(var2) @@ -652,10 +742,16 @@ static bool nrf91_errata_23(void) return false; #else #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + __DSB(); if (var1 == 0x09) { switch(var2) @@ -690,10 +786,16 @@ static bool nrf91_errata_24(void) return false; #else #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + __DSB(); if (var1 == 0x09) { switch(var2) @@ -728,10 +830,16 @@ static bool nrf91_errata_26(void) return false; #else #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + __DSB(); if (var1 == 0x09) { switch(var2) @@ -766,10 +874,16 @@ static bool nrf91_errata_27(void) return false; #else #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + __DSB(); if (var1 == 0x09) { switch(var2) @@ -804,10 +918,16 @@ static bool nrf91_errata_28(void) return false; #else #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + __DSB(); if (var1 == 0x09) { switch(var2) @@ -842,10 +962,16 @@ static bool nrf91_errata_29(void) return false; #else #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + __DSB(); if (var1 == 0x09) { switch(var2) @@ -880,10 +1006,16 @@ static bool nrf91_errata_30(void) return false; #else #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + __DSB(); if (var1 == 0x09) { switch(var2) @@ -918,10 +1050,16 @@ static bool nrf91_errata_31(void) return false; #else #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + __DSB(); if (var1 == 0x09) { switch(var2) @@ -956,10 +1094,16 @@ static bool nrf91_errata_32(void) return false; #else #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + __DSB(); if (var1 == 0x09) { switch(var2) @@ -994,10 +1138,16 @@ static bool nrf91_errata_33(void) return false; #else #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif #endif #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + __DSB(); if (var1 == 0x09) { switch(var2) diff --git a/mdk/nrf_common.ld b/mdk/nrf_common.ld index fa7858349a..f2e0fae11e 100644 --- a/mdk/nrf_common.ld +++ b/mdk/nrf_common.ld @@ -75,17 +75,24 @@ SECTIONS KEEP(*(.eh_frame*)) } > FLASH - .ARM.extab : + .gnu.sgstubs : + { + . = ALIGN(32); + } > FLASH + + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH - __exidx_start = .; + .ARM.exidx : { + __exidx_start = .; *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; } > FLASH - __exidx_end = .; . = ALIGN(4); __etext = .; diff --git a/mdk/ses_startup_nrf_common.s b/mdk/ses_startup_nrf_common.s index c96271ec14..0944a9f154 100644 --- a/mdk/ses_startup_nrf_common.s +++ b/mdk/ses_startup_nrf_common.s @@ -246,4 +246,27 @@ Pass_StackPtr: // bx LR // Return +#ifdef INITIALIZE_USER_SECTIONS + .global InitializeUserMemorySections + .section .init, "ax" + .thumb_func +InitializeUserMemorySections: + ldr r0, =__start_nrf_sections + ldr r1, =__start_nrf_sections_run + ldr r2, =__end_nrf_sections_run + cmp r0, r1 + beq 2f + subs r2, r2, r1 + beq 2f +1: + ldrb r3, [r0] + adds r0, r0, #1 + strb r3, [r1] + adds r1, r1, #1 + subs r2, r2, #1 + bne 1b +2: + bx lr +#endif + /*************************** End of file ****************************/ \ No newline at end of file diff --git a/mdk/system_nrf.h b/mdk/system_nrf.h index bbc17985e0..c01a1bb676 100644 --- a/mdk/system_nrf.h +++ b/mdk/system_nrf.h @@ -22,7 +22,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. #ifndef SYSTEM_NRF_H #define SYSTEM_NRF_H - +#ifndef __ASSEMBLY__ #ifdef __cplusplus extern "C" { #endif @@ -58,4 +58,5 @@ extern void SystemCoreClockUpdate (void); } #endif +#endif /* __ASSEMBLY__ */ #endif /* SYSTEM_NRF_H */ diff --git a/mdk/system_nrf51.c b/mdk/system_nrf51.c index 3c036c8cbd..fc8809deef 100644 --- a/mdk/system_nrf51.c +++ b/mdk/system_nrf51.c @@ -26,7 +26,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. #include #include #include "nrf.h" -#include "nrf_erratas.h" +#include "nrf51_erratas.h" #include "system_nrf51.h" /*lint ++flb "Enter library region" */ diff --git a/mdk/system_nrf51.h b/mdk/system_nrf51.h index 9db78f961c..12c6c15bff 100644 --- a/mdk/system_nrf51.h +++ b/mdk/system_nrf51.h @@ -22,7 +22,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. #ifndef SYSTEM_NRF51_H #define SYSTEM_NRF51_H - +#ifndef __ASSEMBLY__ #ifdef __cplusplus extern "C" { #endif @@ -54,8 +54,10 @@ extern void SystemInit (void); */ extern void SystemCoreClockUpdate (void); + #ifdef __cplusplus } #endif +#endif /* __ASSEMBLY__ */ #endif /* SYSTEM_NRF51_H */ diff --git a/mdk/system_nrf52.c b/mdk/system_nrf52.c index c86045fa47..63d5f2f3c8 100644 --- a/mdk/system_nrf52.c +++ b/mdk/system_nrf52.c @@ -27,7 +27,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. #include #include "nrf.h" #include "nrf_peripherals.h" -#include "nrf_erratas.h" +#include "nrf52_erratas.h" #include "system_nrf52.h" #include "system_nrf52_approtect.h" @@ -271,6 +271,18 @@ void SystemInit(void) nrf52_handle_approtect(); + #if NRF52_CONFIGURATION_249_ENABLE && (defined(NRF52805_XXAA) || defined(NRF52810_XXAA) || defined(NRF52811_XXAA)) + if (nrf52_configuration_249() && (NRF_UICR->NRFMDK[0] == 0xFFFFFFFF || NRF_UICR->NRFMDK[1] == 0xFFFFFFFF)) + { + nvmc_config(NVMC_CONFIG_WEN_Wen); + NRF_UICR->NRFMDK[0] = 0; + nvmc_wait(); + NRF_UICR->NRFMDK[1] = 0; + nvmc_wait(); + nvmc_config(NVMC_CONFIG_WEN_Ren); + } + #endif + /* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined, two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as normal GPIOs. */ diff --git a/mdk/system_nrf52.h b/mdk/system_nrf52.h index bd3919cb02..09f905f06e 100644 --- a/mdk/system_nrf52.h +++ b/mdk/system_nrf52.h @@ -22,7 +22,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. #ifndef SYSTEM_NRF52_H #define SYSTEM_NRF52_H - +#ifndef __ASSEMBLY__ #ifdef __cplusplus extern "C" { #endif @@ -54,8 +54,10 @@ extern void SystemInit (void); */ extern void SystemCoreClockUpdate (void); + #ifdef __cplusplus } #endif +#endif /* __ASSEMBLY__ */ #endif /* SYSTEM_NRF52_H */ diff --git a/mdk/system_nrf52805.h b/mdk/system_nrf52805.h index 57e0a6bb71..ba3025ef40 100644 --- a/mdk/system_nrf52805.h +++ b/mdk/system_nrf52805.h @@ -22,7 +22,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. #ifndef SYSTEM_NRF52805_H #define SYSTEM_NRF52805_H - +#ifndef __ASSEMBLY__ #ifdef __cplusplus extern "C" { #endif @@ -54,8 +54,10 @@ extern void SystemInit (void); */ extern void SystemCoreClockUpdate (void); + #ifdef __cplusplus } #endif +#endif /* __ASSEMBLY__ */ #endif /* SYSTEM_NRF52805_H */ diff --git a/mdk/system_nrf52810.h b/mdk/system_nrf52810.h index 8b2958eff9..8dc0614a26 100644 --- a/mdk/system_nrf52810.h +++ b/mdk/system_nrf52810.h @@ -22,7 +22,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. #ifndef SYSTEM_NRF52810_H #define SYSTEM_NRF52810_H - +#ifndef __ASSEMBLY__ #ifdef __cplusplus extern "C" { #endif @@ -54,8 +54,10 @@ extern void SystemInit (void); */ extern void SystemCoreClockUpdate (void); + #ifdef __cplusplus } #endif +#endif /* __ASSEMBLY__ */ #endif /* SYSTEM_NRF52810_H */ diff --git a/mdk/system_nrf52811.h b/mdk/system_nrf52811.h index 6212d0aa4f..d0dd1023af 100644 --- a/mdk/system_nrf52811.h +++ b/mdk/system_nrf52811.h @@ -22,7 +22,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. #ifndef SYSTEM_NRF52811_H #define SYSTEM_NRF52811_H - +#ifndef __ASSEMBLY__ #ifdef __cplusplus extern "C" { #endif @@ -54,8 +54,10 @@ extern void SystemInit (void); */ extern void SystemCoreClockUpdate (void); + #ifdef __cplusplus } #endif +#endif /* __ASSEMBLY__ */ #endif /* SYSTEM_NRF52811_H */ diff --git a/mdk/system_nrf52820.h b/mdk/system_nrf52820.h index 5b5b77dd27..33a4e6bec0 100644 --- a/mdk/system_nrf52820.h +++ b/mdk/system_nrf52820.h @@ -22,7 +22,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. #ifndef SYSTEM_NRF52820_H #define SYSTEM_NRF52820_H - +#ifndef __ASSEMBLY__ #ifdef __cplusplus extern "C" { #endif @@ -54,8 +54,10 @@ extern void SystemInit (void); */ extern void SystemCoreClockUpdate (void); + #ifdef __cplusplus } #endif +#endif /* __ASSEMBLY__ */ #endif /* SYSTEM_NRF52820_H */ diff --git a/mdk/system_nrf52833.h b/mdk/system_nrf52833.h index 342967a84f..681075c690 100644 --- a/mdk/system_nrf52833.h +++ b/mdk/system_nrf52833.h @@ -22,7 +22,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. #ifndef SYSTEM_NRF52833_H #define SYSTEM_NRF52833_H - +#ifndef __ASSEMBLY__ #ifdef __cplusplus extern "C" { #endif @@ -54,8 +54,10 @@ extern void SystemInit (void); */ extern void SystemCoreClockUpdate (void); + #ifdef __cplusplus } #endif +#endif /* __ASSEMBLY__ */ #endif /* SYSTEM_NRF52833_H */ diff --git a/mdk/system_nrf52840.h b/mdk/system_nrf52840.h index 3df49a461f..e4d8424573 100644 --- a/mdk/system_nrf52840.h +++ b/mdk/system_nrf52840.h @@ -22,7 +22,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. #ifndef SYSTEM_NRF52840_H #define SYSTEM_NRF52840_H - +#ifndef __ASSEMBLY__ #ifdef __cplusplus extern "C" { #endif @@ -54,8 +54,10 @@ extern void SystemInit (void); */ extern void SystemCoreClockUpdate (void); + #ifdef __cplusplus } #endif +#endif /* __ASSEMBLY__ */ #endif /* SYSTEM_NRF52840_H */ diff --git a/mdk/system_nrf52_approtect.h b/mdk/system_nrf52_approtect.h index 86a8b65b49..866240e230 100644 --- a/mdk/system_nrf52_approtect.h +++ b/mdk/system_nrf52_approtect.h @@ -24,7 +24,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. #define SYSTEM_NRF52_APPROTECT_H #include "nrf.h" -#include "nrf_erratas.h" +#include "nrf52_erratas.h" #ifdef __cplusplus extern "C" { @@ -40,15 +40,15 @@ extern "C" { ENABLE_SECURE_APPROTECT and ENABLE_SECURE_APPROTECT_USER_HANDLING. */ static inline void nrf52_handle_approtect(void) { - #if NRF52_ERRATA_249_PRESENT + #if NRF52_CONFIGURATION_249_PRESENT #if defined (ENABLE_APPROTECT) - if (nrf52_errata_249()) + if (nrf52_configuration_249()) { /* Prevent processor from unlocking APPROTECT soft branch after this point. */ NRF_APPROTECT->FORCEPROTECT = APPROTECT_FORCEPROTECT_FORCEPROTECT_Force; } #else - if (nrf52_errata_249()) + if (nrf52_configuration_249()) { /* Load APPROTECT soft branch from UICR. If UICR->APPROTECT is disabled, POWER->APPROTECT will be disabled. */ diff --git a/mdk/system_nrf5340_application.c b/mdk/system_nrf5340_application.c index 867b0efcc6..67149a19f7 100644 --- a/mdk/system_nrf5340_application.c +++ b/mdk/system_nrf5340_application.c @@ -26,12 +26,14 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. #include #include #include "nrf.h" -#include "nrf_erratas.h" +#include "nrf_peripherals.h" +#include "nrf53_erratas.h" #include "system_nrf5340_application.h" #include "system_nrf53_approtect.h" /*lint ++flb "Enter library region" */ +void SystemStoreFICRNS(); /* NRF5340 application core uses a variable System Clock Frequency that starts at 64MHz */ #define __SYSTEM_CLOCK_MAX (128000000UL) @@ -154,6 +156,10 @@ void SystemInit(void) { *((volatile uint32_t *)0x5000470Cul) =0x65ul; } + + #if !defined(NRF_SKIP_FICR_NS_COPY_TO_RAM) + SystemStoreFICRNS(); + #endif #if defined(CONFIG_NFCT_PINS_AS_GPIOS) @@ -247,4 +253,49 @@ void SystemInit(void) SystemCoreClockUpdate(); } +/* Workaround to allow NS code to access FICR. Override NRF_FICR_NS to move FICR_NS buffer. */ +#define FICR_SIZE 0x1000ul +#define RAM_BASE 0x20000000ul +#define RAM_END 0x2FFFFFFFul + +/* Copy FICR_S to FICR_NS RAM region */ +void SystemStoreFICRNS() +{ + if ((uint32_t)NRF_FICR_NS < RAM_BASE || (uint32_t)NRF_FICR_NS + FICR_SIZE > RAM_END) + { + /* FICR_NS is not in RAM. */ + return; + } + /* Copy FICR to NS-accessible RAM block. */ + volatile uint32_t * from = (volatile uint32_t *)((uint32_t)NRF_FICR_S + (FICR_SIZE - sizeof(uint32_t))); + volatile uint32_t * to = (volatile uint32_t *)((uint32_t)NRF_FICR_NS + (FICR_SIZE - sizeof(uint32_t))); + volatile uint32_t * copy_from_end = (volatile uint32_t *)NRF_FICR_S; + while (from >= copy_from_end) + { + *(to--) = *(from--); + } + + /* Make RAM region NS. */ + uint32_t ram_region = ((uint32_t)NRF_FICR_NS - (uint32_t)RAM_BASE) / SPU_RAMREGION_SIZE; + NRF_SPU_S->RAMREGION[ram_region].PERM &= ~(1 << SPU_RAMREGION_PERM_SECATTR_Pos); +} + +/* Block write and execute access to FICR RAM region */ +void SystemLockFICRNS() +{ + if ((uint32_t)NRF_FICR_NS < RAM_BASE || (uint32_t)NRF_FICR_NS + FICR_SIZE > RAM_END) + { + /* FICR_NS is not in RAM. */ + return; + } + + uint32_t ram_region = ((uint32_t)NRF_FICR_NS - (uint32_t)RAM_BASE) / SPU_RAMREGION_SIZE; + NRF_SPU_S->RAMREGION[ram_region].PERM &= + ~( + (1 << SPU_RAMREGION_PERM_WRITE_Pos) | + (1 << SPU_RAMREGION_PERM_EXECUTE_Pos) + ); + NRF_SPU_S->RAMREGION[ram_region].PERM |= 1 << SPU_RAMREGION_PERM_LOCK_Pos; +} + /*lint --flb "Leave library region" */ diff --git a/mdk/system_nrf5340_application.h b/mdk/system_nrf5340_application.h index 3d5f24a4ac..edf4460864 100644 --- a/mdk/system_nrf5340_application.h +++ b/mdk/system_nrf5340_application.h @@ -22,7 +22,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. #ifndef SYSTEM_NRF5340_APPLICATION_H #define SYSTEM_NRF5340_APPLICATION_H - +#ifndef __ASSEMBLY__ #ifdef __cplusplus extern "C" { #endif @@ -54,8 +54,10 @@ extern void SystemInit (void); */ extern void SystemCoreClockUpdate (void); + #ifdef __cplusplus } #endif +#endif /* __ASSEMBLY__ */ #endif /* SYSTEM_NRF5340_APPLICATION_H */ diff --git a/mdk/system_nrf5340_network.c b/mdk/system_nrf5340_network.c index 4688b9753f..a43c3dcb43 100644 --- a/mdk/system_nrf5340_network.c +++ b/mdk/system_nrf5340_network.c @@ -26,7 +26,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. #include #include #include "nrf.h" -#include "nrf_erratas.h" +#include "nrf53_erratas.h" #include "system_nrf5340_network.h" #include "system_nrf53_approtect.h" diff --git a/mdk/system_nrf5340_network.h b/mdk/system_nrf5340_network.h index ab26179824..3faa4b7678 100644 --- a/mdk/system_nrf5340_network.h +++ b/mdk/system_nrf5340_network.h @@ -22,7 +22,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. #ifndef SYSTEM_NRF5340_NETWORK_H #define SYSTEM_NRF5340_NETWORK_H - +#ifndef __ASSEMBLY__ #ifdef __cplusplus extern "C" { #endif @@ -54,8 +54,10 @@ extern void SystemInit (void); */ extern void SystemCoreClockUpdate (void); + #ifdef __cplusplus } #endif +#endif /* __ASSEMBLY__ */ #endif /* SYSTEM_NRF5340_NETWORK_H */ diff --git a/mdk/system_nrf53_approtect.h b/mdk/system_nrf53_approtect.h index 1863e68d10..792a293ef5 100644 --- a/mdk/system_nrf53_approtect.h +++ b/mdk/system_nrf53_approtect.h @@ -24,7 +24,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. #define SYSTEM_NRF53_APPROTECT_H #include "nrf.h" -#include "nrf_erratas.h" +#include "nrf53_erratas.h" #ifdef __cplusplus extern "C" { @@ -46,7 +46,7 @@ static inline void nrf53_handle_approtect(void) #if defined(NRF_APPLICATION) #if defined (ENABLE_APPROTECT) /* Prevent processor from unlocking APPROTECT soft branch after this point. */ - NRF_CTRLAP_S->APPROTECT.LOCK = NRF_CTRLAP_S_APPROTECT_LOCK_LOCK_Locked; + NRF_CTRLAP_S->APPROTECT.LOCK = CTRLAPPERI_APPROTECT_LOCK_LOCK_Locked; #elif defined (ENABLE_APPROTECT_USER_HANDLING) /* Do nothing, allow user code to handle APPROTECT. Use this if you want to enable authenticated debug. */ @@ -60,7 +60,7 @@ static inline void nrf53_handle_approtect(void) /* Secure APPROTECT is only available for Application core. */ #if defined (ENABLE_SECURE_APPROTECT) /* Prevent processor from unlocking SECURE APPROTECT soft branch after this point. */ - NRF_CTRLAP_S->SECUREAPPROTECT.LOCK = NRF_CTRLAP_S_SECUREAPPROTECT_LOCK_LOCK_Locked; + NRF_CTRLAP_S->SECUREAPPROTECT.LOCK = CTRLAPPERI_SECUREAPPROTECT_LOCK_LOCK_Locked; #elif defined (ENABLE_SECURE_APPROTECT_USER_HANDLING) /* Do nothing, allow user code to handle SECURE APPROTECT. Use this if you want to enable authenticated debug. */ @@ -74,7 +74,7 @@ static inline void nrf53_handle_approtect(void) #if defined(NRF_NETWORK) #if defined (ENABLE_APPROTECT) /* Prevent processor from unlocking APPROTECT soft branch after this point. */ - NRF_CTRLAP_NS->APPROTECT.LOCK = NRF_CTRLAP_NS_APPROTECT_LOCK_LOCK_Locked; + NRF_CTRLAP_NS->APPROTECT.LOCK = CTRLAPPERI_APPROTECT_LOCK_LOCK_Locked; #elif defined (ENABLE_APPROTECT_USER_HANDLING) /* Do nothing, allow user code to handle APPROTECT. Use this if you want to enable authenticated debug. */ diff --git a/mdk/system_nrf9160.c b/mdk/system_nrf9160.c index 0363d41fb2..964b116169 100644 --- a/mdk/system_nrf9160.c +++ b/mdk/system_nrf9160.c @@ -26,11 +26,13 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. #include #include #include "nrf.h" -#include "nrf_erratas.h" +#include "nrf_peripherals.h" +#include "nrf91_erratas.h" #include "system_nrf9160.h" /*lint ++flb "Enter library region" */ +void SystemStoreFICRNS(); #define __SYSTEM_CLOCK (64000000UL) /*!< nRF9160 Application core uses a fixed System Clock Frequency of 64MHz */ @@ -64,6 +66,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. #if !defined(NRF_TRUSTZONE_NONSECURE) static bool uicr_HFXOSRC_erased(void); static bool uicr_HFXOCNT_erased(void); + static bool is_empty_word(uint32_t const volatile * word); #endif void SystemCoreClockUpdate(void) @@ -115,10 +118,14 @@ void SystemInit(void) *((volatile uint32_t *)0x50004710ul) = 0x1; } + #if !defined(NRF_SKIP_FICR_NS_COPY_TO_RAM) + SystemStoreFICRNS(); + #endif + /* Trimming of the device. Copy all the trimming values from FICR into the target addresses. Trim until one ADDR is not initialized. */ - uint32_t index = 0; - for (index = 0; index < 256ul && NRF_FICR_S->TRIMCNF[index].ADDR != 0xFFFFFFFFul; index++){ + + for (uint32_t index = 0; index < 256ul && !is_empty_word(&NRF_FICR_S->TRIMCNF[index].ADDR); index++){ #if defined ( __ICCARM__ ) #pragma diag_suppress=Pa082 #endif @@ -130,35 +137,37 @@ void SystemInit(void) /* Set UICR->HFXOSRC and UICR->HFXOCNT to working defaults if UICR was erased */ if (uicr_HFXOSRC_erased() || uicr_HFXOCNT_erased()) { - /* Wait for pending NVMC operations to finish */ - while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); - - /* Enable write mode in NVMC */ - NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Wen; - while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); - - if (uicr_HFXOSRC_erased()){ - /* Write default value to UICR->HFXOSRC */ - uicr_erased_value = NRF_UICR_S->HFXOSRC; - uicr_new_value = (uicr_erased_value & ~UICR_HFXOSRC_HFXOSRC_Msk) | UICR_HFXOSRC_HFXOSRC_TCXO; - NRF_UICR_S->HFXOSRC = uicr_new_value; - while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); - } - - if (uicr_HFXOCNT_erased()){ - /* Write default value to UICR->HFXOCNT */ - uicr_erased_value = NRF_UICR_S->HFXOCNT; - uicr_new_value = (uicr_erased_value & ~UICR_HFXOCNT_HFXOCNT_Msk) | 0x20; - NRF_UICR_S->HFXOCNT = uicr_new_value; - while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); - } - - /* Enable read mode in NVMC */ - NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Ren; - while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); - - /* Reset to apply clock select update */ - NVIC_SystemReset(); + /* Wait for pending NVMC operations to finish */ + while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); + + /* Enable write mode in NVMC */ + NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Wen; + while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); + + if (uicr_HFXOSRC_erased()){ + /* Write default value to UICR->HFXOSRC */ + uicr_erased_value = NRF_UICR_S->HFXOSRC; + uicr_new_value = (uicr_erased_value & ~UICR_HFXOSRC_HFXOSRC_Msk) | UICR_HFXOSRC_HFXOSRC_TCXO; + NRF_UICR_S->HFXOSRC = uicr_new_value; + __DSB(); + while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); + } + + if (uicr_HFXOCNT_erased()){ + /* Write default value to UICR->HFXOCNT */ + uicr_erased_value = NRF_UICR_S->HFXOCNT; + uicr_new_value = (uicr_erased_value & ~UICR_HFXOCNT_HFXOCNT_Msk) | 0x20; + NRF_UICR_S->HFXOCNT = uicr_new_value; + __DSB(); + while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); + } + + /* Enable read mode in NVMC */ + NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Ren; + while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); + + /* Reset to apply clock select update */ + NVIC_SystemReset(); } /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product @@ -192,24 +201,24 @@ void SystemInit(void) // Set trace port speed to 32 MHz NRF_TAD_S->TRACEPORTSPEED = TAD_TRACEPORTSPEED_TRACEPORTSPEED_32MHz; - *((uint32_t *)(0xE0053000ul)) = 0x00000001ul; + *((volatile uint32_t *)(0xE0053000ul)) = 0x00000001ul; - *((uint32_t *)(0xE005AFB0ul)) = 0xC5ACCE55ul; - *((uint32_t *)(0xE005A000ul)) &= 0xFFFFFF00ul; - *((uint32_t *)(0xE005A004ul)) = 0x00000009ul; - *((uint32_t *)(0xE005A000ul)) = 0x00000303ul; - *((uint32_t *)(0xE005AFB0ul)) = 0x00000000ul; - - *((uint32_t *)(0xE005BFB0ul)) = 0xC5ACCE55ul; - *((uint32_t *)(0xE005B000ul)) &= 0xFFFFFF00ul; - *((uint32_t *)(0xE005B004ul)) = 0x00003000ul; - *((uint32_t *)(0xE005B000ul)) = 0x00000308ul; - *((uint32_t *)(0xE005BFB0ul)) = 0x00000000ul; - - *((uint32_t *)(0xE0058FB0ul)) = 0xC5ACCE55ul; - *((uint32_t *)(0xE0058000ul)) = 0x00000000ul; - *((uint32_t *)(0xE0058004ul)) = 0x00000000ul; - *((uint32_t *)(0xE0058FB0ul)) = 0x00000000ul; + *((volatile uint32_t *)(0xE005AFB0ul)) = 0xC5ACCE55ul; + *((volatile uint32_t *)(0xE005A000ul)) &= 0xFFFFFF00ul; + *((volatile uint32_t *)(0xE005A004ul)) = 0x00000009ul; + *((volatile uint32_t *)(0xE005A000ul)) = 0x00000303ul; + *((volatile uint32_t *)(0xE005AFB0ul)) = 0x00000000ul; + + *((volatile uint32_t *)(0xE005BFB0ul)) = 0xC5ACCE55ul; + *((volatile uint32_t *)(0xE005B000ul)) &= 0xFFFFFF00ul; + *((volatile uint32_t *)(0xE005B004ul)) = 0x00003000ul; + *((volatile uint32_t *)(0xE005B000ul)) = 0x00000308ul; + *((volatile uint32_t *)(0xE005BFB0ul)) = 0x00000000ul; + + *((volatile uint32_t *)(0xE0058FB0ul)) = 0xC5ACCE55ul; + *((volatile uint32_t *)(0xE0058000ul)) = 0x00000000ul; + *((volatile uint32_t *)(0xE0058004ul)) = 0x00000000ul; + *((volatile uint32_t *)(0xE0058FB0ul)) = 0x00000000ul; /* Rom table does not list ETB, or TPIU base addresses. * Some debug probes may require manual configuration of these peripherals to enable tracing. @@ -240,7 +249,7 @@ void SystemInit(void) bool uicr_HFXOCNT_erased() { - if (NRF_UICR_S->HFXOCNT == 0xFFFFFFFFul) { + if (is_empty_word(&NRF_UICR_S->HFXOCNT)) { return true; } return false; @@ -249,11 +258,68 @@ void SystemInit(void) bool uicr_HFXOSRC_erased() { - if ((NRF_UICR_S->HFXOSRC & UICR_HFXOSRC_HFXOSRC_Msk) != UICR_HFXOSRC_HFXOSRC_TCXO) { + uint32_t HFXOSRC_readout = NRF_UICR_S->HFXOSRC; + __DSB(); + if ((HFXOSRC_readout & UICR_HFXOSRC_HFXOSRC_Msk) != UICR_HFXOSRC_HFXOSRC_TCXO) { return true; } return false; } + + bool is_empty_word(uint32_t const volatile * word) + { + uint32_t val = *word; + __DSB(); + return val == 0xFFFFFFFFul; + } #endif + +/* Workaround to allow NS code to access FICR. Override NRF_FICR_NS to move FICR_NS buffer. */ +#define FICR_SIZE 0x1000ul +#define RAM_BASE 0x20000000ul +#define RAM_END 0x2FFFFFFFul + +/* Copy FICR_S to FICR_NS RAM region */ +void SystemStoreFICRNS() +{ + if ((uint32_t)NRF_FICR_NS < RAM_BASE || (uint32_t)NRF_FICR_NS + FICR_SIZE > RAM_END) + { + /* FICR_NS is not in RAM. */ + return; + } + /* Copy FICR to NS-accessible RAM block. */ + volatile uint32_t * from = (volatile uint32_t *)((uint32_t)NRF_FICR_S + (FICR_SIZE - sizeof(uint32_t))); + volatile uint32_t * to = (volatile uint32_t *)((uint32_t)NRF_FICR_NS + (FICR_SIZE - sizeof(uint32_t))); + volatile uint32_t * copy_from_end = (volatile uint32_t *)NRF_FICR_S; + while (from >= copy_from_end) + { + *(to--) = *(from--); + } + + /* Make RAM region NS. */ + uint32_t ram_region = ((uint32_t)NRF_FICR_NS - (uint32_t)RAM_BASE) / SPU_RAMREGION_SIZE; + __DSB(); + NRF_SPU_S->RAMREGION[ram_region].PERM &= ~(1 << SPU_RAMREGION_PERM_SECATTR_Pos); +} + +/* Block write and execute access to FICR RAM region */ +void SystemLockFICRNS() +{ + if ((uint32_t)NRF_FICR_NS < RAM_BASE || (uint32_t)NRF_FICR_NS + FICR_SIZE > RAM_END) + { + /* FICR_NS is not in RAM. */ + return; + } + + uint32_t ram_region = ((uint32_t)NRF_FICR_NS - (uint32_t)RAM_BASE) / SPU_RAMREGION_SIZE; + __DSB(); + NRF_SPU_S->RAMREGION[ram_region].PERM &= + ~( + (1 << SPU_RAMREGION_PERM_WRITE_Pos) | + (1 << SPU_RAMREGION_PERM_EXECUTE_Pos) + ); + NRF_SPU_S->RAMREGION[ram_region].PERM |= 1 << SPU_RAMREGION_PERM_LOCK_Pos; +} + /*lint --flb "Leave library region" */ diff --git a/mdk/system_nrf9160.h b/mdk/system_nrf9160.h index 1afad0619b..767c725645 100644 --- a/mdk/system_nrf9160.h +++ b/mdk/system_nrf9160.h @@ -22,7 +22,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. #ifndef SYSTEM_NRF9160_H #define SYSTEM_NRF9160_H - +#ifndef __ASSEMBLY__ #ifdef __cplusplus extern "C" { #endif @@ -54,8 +54,10 @@ extern void SystemInit (void); */ extern void SystemCoreClockUpdate (void); + #ifdef __cplusplus } #endif +#endif /* __ASSEMBLY__ */ #endif /* SYSTEM_NRF9160_H */ diff --git a/soc/nrfx_atomic.c b/soc/nrfx_atomic.c index af7586c66d..eea6210956 100644 --- a/soc/nrfx_atomic.c +++ b/soc/nrfx_atomic.c @@ -32,14 +32,17 @@ */ #include "nrfx_atomic.h" -#ifndef NRFX_ATOMIC_USE_BUILT_IN - #define NRFX_ATOMIC_USE_BUILT_IN 0 -#endif // NRFX_ATOMIC_USE_BUILT_IN - #if ((__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)) #define NRFX_ATOMIC_STREX_LDREX_PRESENT +#else +/* Cortex-M0 does not have build-in atomic function. Force disabling to avoid linking failure. */ +#undef NRFX_ATOMIC_USE_BUILT_IN #endif +#ifndef NRFX_ATOMIC_USE_BUILT_IN + #define NRFX_ATOMIC_USE_BUILT_IN 0 +#endif // NRFX_ATOMIC_USE_BUILT_IN + #if (NRFX_ATOMIC_USE_BUILT_IN == 0) && defined(NRFX_ATOMIC_STREX_LDREX_PRESENT) #include "nrfx_atomic_internal.h" #endif @@ -55,8 +58,9 @@ uint32_t nrfx_atomic_u32_fetch_store(nrfx_atomic_u32_t * p_data, uint32_t value) (void) new_val; return old_val; #else + uint32_t old_val; NRFX_CRITICAL_SECTION_ENTER(); - uint32_t old_val = *p_data; + old_val = *p_data; *p_data = value; NRFX_CRITICAL_SECTION_EXIT(); return old_val; @@ -93,8 +97,9 @@ uint32_t nrfx_atomic_u32_fetch_or(nrfx_atomic_u32_t * p_data, uint32_t value) (void) new_val; return old_val; #else + uint32_t old_val; NRFX_CRITICAL_SECTION_ENTER(); - uint32_t old_val = *p_data; + old_val = *p_data; *p_data |= value; NRFX_CRITICAL_SECTION_EXIT(); return old_val; @@ -112,11 +117,12 @@ uint32_t nrfx_atomic_u32_or(nrfx_atomic_u32_t * p_data, uint32_t value) (void) old_val; return new_val; #else + uint32_t new_val; NRFX_CRITICAL_SECTION_ENTER(); *p_data |= value; - uint32_t new_value = *p_data; + new_val = *p_data; NRFX_CRITICAL_SECTION_EXIT(); - return new_value; + return new_val; #endif //NRFX_ATOMIC_USE_BUILT_IN } @@ -131,8 +137,9 @@ uint32_t nrfx_atomic_u32_fetch_and(nrfx_atomic_u32_t * p_data, uint32_t value) (void) new_val; return old_val; #else + uint32_t old_val; NRFX_CRITICAL_SECTION_ENTER(); - uint32_t old_val = *p_data; + old_val = *p_data; *p_data &= value; NRFX_CRITICAL_SECTION_EXIT(); return old_val; @@ -150,11 +157,12 @@ uint32_t nrfx_atomic_u32_and(nrfx_atomic_u32_t * p_data, uint32_t value) (void) old_val; return new_val; #else + uint32_t new_val; NRFX_CRITICAL_SECTION_ENTER(); *p_data &= value; - uint32_t new_value = *p_data; + new_val = *p_data; NRFX_CRITICAL_SECTION_EXIT(); - return new_value; + return new_val; #endif //NRFX_ATOMIC_USE_BUILT_IN } @@ -169,8 +177,9 @@ uint32_t nrfx_atomic_u32_fetch_xor(nrfx_atomic_u32_t * p_data, uint32_t value) (void) new_val; return old_val; #else + uint32_t old_val; NRFX_CRITICAL_SECTION_ENTER(); - uint32_t old_val = *p_data; + old_val = *p_data; *p_data ^= value; NRFX_CRITICAL_SECTION_EXIT(); return old_val; @@ -188,11 +197,12 @@ uint32_t nrfx_atomic_u32_xor(nrfx_atomic_u32_t * p_data, uint32_t value) (void) old_val; return new_val; #else + uint32_t new_val; NRFX_CRITICAL_SECTION_ENTER(); *p_data ^= value; - uint32_t new_value = *p_data; + new_val = *p_data; NRFX_CRITICAL_SECTION_EXIT(); - return new_value; + return new_val; #endif //NRFX_ATOMIC_USE_BUILT_IN } @@ -207,8 +217,9 @@ uint32_t nrfx_atomic_u32_fetch_add(nrfx_atomic_u32_t * p_data, uint32_t value) (void) new_val; return old_val; #else + uint32_t old_val; NRFX_CRITICAL_SECTION_ENTER(); - uint32_t old_val = *p_data; + old_val = *p_data; *p_data += value; NRFX_CRITICAL_SECTION_EXIT(); return old_val; @@ -226,11 +237,12 @@ uint32_t nrfx_atomic_u32_add(nrfx_atomic_u32_t * p_data, uint32_t value) (void) old_val; return new_val; #else + uint32_t new_val; NRFX_CRITICAL_SECTION_ENTER(); *p_data += value; - uint32_t new_value = *p_data; + new_val = *p_data; NRFX_CRITICAL_SECTION_EXIT(); - return new_value; + return new_val; #endif //NRFX_ATOMIC_USE_BUILT_IN } @@ -245,8 +257,9 @@ uint32_t nrfx_atomic_u32_fetch_sub(nrfx_atomic_u32_t * p_data, uint32_t value) (void) new_val; return old_val; #else + uint32_t old_val; NRFX_CRITICAL_SECTION_ENTER(); - uint32_t old_val = *p_data; + old_val = *p_data; *p_data -= value; NRFX_CRITICAL_SECTION_EXIT(); return old_val; @@ -264,11 +277,12 @@ uint32_t nrfx_atomic_u32_sub(nrfx_atomic_u32_t * p_data, uint32_t value) (void) old_val; return new_val; #else + uint32_t new_val; NRFX_CRITICAL_SECTION_ENTER(); *p_data -= value; - uint32_t new_value = *p_data; + new_val = *p_data; NRFX_CRITICAL_SECTION_EXIT(); - return new_value; + return new_val; #endif //NRFX_ATOMIC_USE_BUILT_IN } @@ -327,8 +341,9 @@ uint32_t nrfx_atomic_u32_fetch_sub_hs(nrfx_atomic_u32_t * p_data, uint32_t value (void) new_val; return old_val; #else + uint32_t old_val; NRFX_CRITICAL_SECTION_ENTER(); - uint32_t old_val = *p_data; + old_val = *p_data; *p_data -= value; NRFX_CRITICAL_SECTION_EXIT(); return old_val; @@ -359,11 +374,12 @@ uint32_t nrfx_atomic_u32_sub_hs(nrfx_atomic_u32_t * p_data, uint32_t value) (void) old_val; return new_val; #else + uint32_t new_val; NRFX_CRITICAL_SECTION_ENTER(); *p_data -= value; - uint32_t new_value = *p_data; + new_val = *p_data; NRFX_CRITICAL_SECTION_EXIT(); - return new_value; + return new_val; #endif //NRFX_ATOMIC_USE_BUILT_IN } diff --git a/templates/nrfx_config_nrf51.h b/templates/nrfx_config_nrf51.h index d3099a81ab..463fc14abf 100644 --- a/templates/nrfx_config_nrf51.h +++ b/templates/nrfx_config_nrf51.h @@ -132,6 +132,12 @@ #define NRFX_CLOCK_CONFIG_LF_CAL_ENABLED 0 #endif +// NRFX_CLOCK_CONFIG_CT_ENABLED - Enables Calibration Timer Support + +#ifndef NRFX_CLOCK_CONFIG_CT_ENABLED +#define NRFX_CLOCK_CONFIG_CT_ENABLED 1 +#endif + // NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED - Enables two-stage LFXO start procedure // If set to a non-zero value, LFRC will be started before LFXO and corresponding @@ -212,9 +218,10 @@ #ifndef NRFX_GPIOTE_ENABLED #define NRFX_GPIOTE_ENABLED 0 #endif -// NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins -#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS -#define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1 + +// NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS - Number of dedicated handlers +#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS +#define NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS 2 #endif // NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority diff --git a/templates/nrfx_config_nrf52805.h b/templates/nrfx_config_nrf52805.h index 9ccb5bcbd3..41d4d2330f 100644 --- a/templates/nrfx_config_nrf52805.h +++ b/templates/nrfx_config_nrf52805.h @@ -65,6 +65,12 @@ #define NRFX_CLOCK_CONFIG_LF_CAL_ENABLED 0 #endif +// NRFX_CLOCK_CONFIG_CT_ENABLED - Enables Calibration Timer Support + +#ifndef NRFX_CLOCK_CONFIG_CT_ENABLED +#define NRFX_CLOCK_CONFIG_CT_ENABLED 1 +#endif + // NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED - Enables two-stage LFXO start procedure // If set to a non-zero value, LFRC will be started before LFXO and corresponding @@ -184,9 +190,10 @@ #ifndef NRFX_GPIOTE_ENABLED #define NRFX_GPIOTE_ENABLED 0 #endif -// NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins -#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS -#define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1 + +// NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS - Number of dedicated handlers +#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS +#define NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS 2 #endif // NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority diff --git a/templates/nrfx_config_nrf52810.h b/templates/nrfx_config_nrf52810.h index c23a8b1a01..3952bd7bde 100644 --- a/templates/nrfx_config_nrf52810.h +++ b/templates/nrfx_config_nrf52810.h @@ -65,6 +65,12 @@ #define NRFX_CLOCK_CONFIG_LF_CAL_ENABLED 0 #endif +// NRFX_CLOCK_CONFIG_CT_ENABLED - Enables Calibration Timer Support + +#ifndef NRFX_CLOCK_CONFIG_CT_ENABLED +#define NRFX_CLOCK_CONFIG_CT_ENABLED 1 +#endif + // NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED - Enables two-stage LFXO start procedure // If set to a non-zero value, LFRC will be started before LFXO and corresponding @@ -258,9 +264,10 @@ #ifndef NRFX_GPIOTE_ENABLED #define NRFX_GPIOTE_ENABLED 0 #endif -// NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins -#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS -#define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1 + +// NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS - Number of dedicated handlers +#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS +#define NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS 2 #endif // NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority diff --git a/templates/nrfx_config_nrf52811.h b/templates/nrfx_config_nrf52811.h index fcc4ef3a8d..906ace7339 100644 --- a/templates/nrfx_config_nrf52811.h +++ b/templates/nrfx_config_nrf52811.h @@ -65,6 +65,12 @@ #define NRFX_CLOCK_CONFIG_LF_CAL_ENABLED 0 #endif +// NRFX_CLOCK_CONFIG_CT_ENABLED - Enables Calibration Timer Support + +#ifndef NRFX_CLOCK_CONFIG_CT_ENABLED +#define NRFX_CLOCK_CONFIG_CT_ENABLED 1 +#endif + // NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED - Enables two-stage LFXO start procedure // If set to a non-zero value, LFRC will be started before LFXO and corresponding @@ -258,9 +264,10 @@ #ifndef NRFX_GPIOTE_ENABLED #define NRFX_GPIOTE_ENABLED 0 #endif -// NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins -#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS -#define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1 + +// NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS - Number of dedicated handlers +#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS +#define NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS 2 #endif // NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority diff --git a/templates/nrfx_config_nrf52820.h b/templates/nrfx_config_nrf52820.h index 0dcf0af050..961f0b1ae7 100644 --- a/templates/nrfx_config_nrf52820.h +++ b/templates/nrfx_config_nrf52820.h @@ -65,6 +65,12 @@ #define NRFX_CLOCK_CONFIG_LF_CAL_ENABLED 0 #endif +// NRFX_CLOCK_CONFIG_CT_ENABLED - Enables Calibration Timer Support + +#ifndef NRFX_CLOCK_CONFIG_CT_ENABLED +#define NRFX_CLOCK_CONFIG_CT_ENABLED 1 +#endif + // NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED - Enables two-stage LFXO start procedure // If set to a non-zero value, LFRC will be started before LFXO and corresponding @@ -282,9 +288,10 @@ #ifndef NRFX_GPIOTE_ENABLED #define NRFX_GPIOTE_ENABLED 0 #endif -// NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins -#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS -#define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1 + +// NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS - Number of dedicated handlers +#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS +#define NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS 2 #endif // NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority diff --git a/templates/nrfx_config_nrf52832.h b/templates/nrfx_config_nrf52832.h index 2ebe2f5160..e270408070 100644 --- a/templates/nrfx_config_nrf52832.h +++ b/templates/nrfx_config_nrf52832.h @@ -65,6 +65,12 @@ #define NRFX_CLOCK_CONFIG_LF_CAL_ENABLED 0 #endif +// NRFX_CLOCK_CONFIG_CT_ENABLED - Enables Calibration Timer Support + +#ifndef NRFX_CLOCK_CONFIG_CT_ENABLED +#define NRFX_CLOCK_CONFIG_CT_ENABLED 1 +#endif + // NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED - Enables two-stage LFXO start procedure // If set to a non-zero value, LFRC will be started before LFXO and corresponding @@ -282,9 +288,10 @@ #ifndef NRFX_GPIOTE_ENABLED #define NRFX_GPIOTE_ENABLED 0 #endif -// NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins -#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS -#define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1 + +// NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS - Number of dedicated handlers +#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS +#define NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS 2 #endif // NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority diff --git a/templates/nrfx_config_nrf52833.h b/templates/nrfx_config_nrf52833.h index 1b65157eb3..657080638e 100644 --- a/templates/nrfx_config_nrf52833.h +++ b/templates/nrfx_config_nrf52833.h @@ -65,6 +65,12 @@ #define NRFX_CLOCK_CONFIG_LF_CAL_ENABLED 0 #endif +// NRFX_CLOCK_CONFIG_CT_ENABLED - Enables Calibration Timer Support + +#ifndef NRFX_CLOCK_CONFIG_CT_ENABLED +#define NRFX_CLOCK_CONFIG_CT_ENABLED 1 +#endif + // NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED - Enables two-stage LFXO start procedure // If set to a non-zero value, LFRC will be started before LFXO and corresponding @@ -282,9 +288,10 @@ #ifndef NRFX_GPIOTE_ENABLED #define NRFX_GPIOTE_ENABLED 0 #endif -// NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins -#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS -#define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1 + +// NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS - Number of dedicated handlers +#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS +#define NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS 2 #endif // NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority diff --git a/templates/nrfx_config_nrf52840.h b/templates/nrfx_config_nrf52840.h index 682aead829..e9a388b913 100644 --- a/templates/nrfx_config_nrf52840.h +++ b/templates/nrfx_config_nrf52840.h @@ -65,6 +65,12 @@ #define NRFX_CLOCK_CONFIG_LF_CAL_ENABLED 0 #endif +// NRFX_CLOCK_CONFIG_CT_ENABLED - Enables Calibration Timer Support + +#ifndef NRFX_CLOCK_CONFIG_CT_ENABLED +#define NRFX_CLOCK_CONFIG_CT_ENABLED 1 +#endif + // NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED - Enables two-stage LFXO start procedure // If set to a non-zero value, LFRC will be started before LFXO and corresponding @@ -282,9 +288,10 @@ #ifndef NRFX_GPIOTE_ENABLED #define NRFX_GPIOTE_ENABLED 0 #endif -// NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins -#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS -#define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1 + +// NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS - Number of dedicated handlers +#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS +#define NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS 2 #endif // NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority diff --git a/templates/nrfx_config_nrf5340_application.h b/templates/nrfx_config_nrf5340_application.h index 1a5ab391a4..40feb4c0f8 100644 --- a/templates/nrfx_config_nrf5340_application.h +++ b/templates/nrfx_config_nrf5340_application.h @@ -454,9 +454,10 @@ #ifndef NRFX_GPIOTE_ENABLED #define NRFX_GPIOTE_ENABLED 0 #endif -// NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins. -#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS -#define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1 + +// NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS - Number of dedicated handlers +#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS +#define NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS 2 #endif // NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. diff --git a/templates/nrfx_config_nrf5340_network.h b/templates/nrfx_config_nrf5340_network.h index 9d07ba6697..0e78d2d327 100644 --- a/templates/nrfx_config_nrf5340_network.h +++ b/templates/nrfx_config_nrf5340_network.h @@ -292,9 +292,10 @@ #ifndef NRFX_GPIOTE_ENABLED #define NRFX_GPIOTE_ENABLED 0 #endif -// NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins. -#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS -#define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1 + +// NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS - Number of dedicated handlers +#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS +#define NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS 2 #endif // NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. diff --git a/templates/nrfx_config_nrf9160.h b/templates/nrfx_config_nrf9160.h index 64b7cbc4d0..ed1a9e4751 100644 --- a/templates/nrfx_config_nrf9160.h +++ b/templates/nrfx_config_nrf9160.h @@ -342,9 +342,10 @@ #ifndef NRFX_GPIOTE_ENABLED #define NRFX_GPIOTE_ENABLED 0 #endif -// NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins. -#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS -#define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1 + +// NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS - Number of dedicated handlers +#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS +#define NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS 2 #endif // NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. diff --git a/templates/nrfx_glue.h b/templates/nrfx_glue.h index 57f46ecb9b..d40520f7a8 100644 --- a/templates/nrfx_glue.h +++ b/templates/nrfx_glue.h @@ -221,6 +221,40 @@ extern "C" { */ #define NRFX_ATOMIC_FETCH_SUB(p_data, value) +/** + * @brief Macro for running compare and swap on an atomic object. + * + * Value is updated to the new value only if it previously equaled old value. + * + * @param[in,out] p_data Atomic memory pointer. + * @param[in] old_value Expected old value. + * @param[in] new_value New value. + * + * @retval true If value was updated. + * @retval false If value was not updated because location was not equal to @p old_value. + */ +#define NRFX_ATOMIC_CAS(p_data, old_value, new_value) + +/** + * @brief Macro for counting leading zeros. + * + * @param[in] value A word value. + * + * @return Number of leading 0-bits in @p value, starting at the most significant bit position. + * If x is 0, the result is undefined. + */ +#define NRFX_CLZ(value) + +/** + * @brief Macro for counting trailing zeros. + * + * @param[in] value A word value. + * + * @return Number of trailing 0-bits in @p value, starting at the least significant bit position. + * If x is 0, the result is undefined. + */ +#define NRFX_CTZ(value) + //------------------------------------------------------------------------------ /**