diff --git a/CHANGELOG.md b/CHANGELOG.md index 570d7dc97..2c4adc3db 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,6 +1,13 @@ # Changelog All notable changes to this project are documented in this file. +## [1.6.2] - 2019-02-12 +### Added +- Added the possibility to use the macro NRFX_COREDEP_DELAY_US_LOOP_CYCLES to specify the number of cycles consumed by one iteration of the internal loop in the function nrfx_coredep_delay_us(). + +### Changed +- Updated MDK to version 8.24.1. + ## [1.6.1] - 2019-01-29 ### Fixed - Fixed an issue in the NFCT driver that caused a performance loss on nRF52832. The interrupt configuration is now properly restored after the NRFX_NFCT_EVT_FIELD_LOST event. diff --git a/mdk/nrf.h b/mdk/nrf.h index 8649d0bfe..a6df47a12 100644 --- a/mdk/nrf.h +++ b/mdk/nrf.h @@ -34,9 +34,9 @@ POSSIBILITY OF SUCH DAMAGE. #define NRF_H /* MDK version */ -#define MDK_MAJOR_VERSION 8 -#define MDK_MINOR_VERSION 23 -#define MDK_MICRO_VERSION 1 +#define MDK_MAJOR_VERSION 8 +#define MDK_MINOR_VERSION 24 +#define MDK_MICRO_VERSION 1 /* Redefine "old" too-generic name NRF52 to NRF52832_XXAA to keep backwards compatibility. */ #if defined (NRF52) diff --git a/mdk/nrf51.h b/mdk/nrf51.h index 903423952..cc758abe7 100644 --- a/mdk/nrf51.h +++ b/mdk/nrf51.h @@ -30,10 +30,10 @@ * @file nrf51.h * @brief CMSIS HeaderFile * @version 522 - * @date 17. January 2019 - * @note Generated by SVDConv V3.3.18 on Thursday, 17.01.2019 17:25:39 + * @date 08. February 2019 + * @note Generated by SVDConv V3.3.18 on Friday, 08.02.2019 16:46:56 * from File 'nrf51.svd', - * last modified on Thursday, 17.01.2019 16:25:34 + * last modified on Friday, 08.02.2019 15:46:51 */ diff --git a/mdk/nrf52.h b/mdk/nrf52.h index 5e67f0b1d..d47124130 100644 --- a/mdk/nrf52.h +++ b/mdk/nrf52.h @@ -30,10 +30,10 @@ * @file nrf52.h * @brief CMSIS HeaderFile * @version 1 - * @date 17. January 2019 - * @note Generated by SVDConv V3.3.18 on Thursday, 17.01.2019 17:25:39 + * @date 08. February 2019 + * @note Generated by SVDConv V3.3.18 on Friday, 08.02.2019 16:46:56 * from File 'nrf52.svd', - * last modified on Thursday, 17.01.2019 16:25:35 + * last modified on Friday, 08.02.2019 15:46:51 */ diff --git a/mdk/nrf52810.h b/mdk/nrf52810.h index 5f91e3bc7..2a7e5fcc1 100644 --- a/mdk/nrf52810.h +++ b/mdk/nrf52810.h @@ -30,10 +30,10 @@ * @file nrf52810.h * @brief CMSIS HeaderFile * @version 1 - * @date 17. January 2019 - * @note Generated by SVDConv V3.3.18 on Thursday, 17.01.2019 17:25:39 + * @date 08. February 2019 + * @note Generated by SVDConv V3.3.18 on Friday, 08.02.2019 16:46:56 * from File 'nrf52810.svd', - * last modified on Thursday, 17.01.2019 16:25:35 + * last modified on Friday, 08.02.2019 15:46:51 */ diff --git a/mdk/nrf52811.h b/mdk/nrf52811.h index 641c447d4..dc077e092 100644 --- a/mdk/nrf52811.h +++ b/mdk/nrf52811.h @@ -30,10 +30,10 @@ * @file nrf52811.h * @brief CMSIS HeaderFile * @version 1 - * @date 17. January 2019 - * @note Generated by SVDConv V3.3.18 on Thursday, 17.01.2019 17:25:39 + * @date 08. February 2019 + * @note Generated by SVDConv V3.3.18 on Friday, 08.02.2019 16:46:56 * from File 'nrf52811.svd', - * last modified on Thursday, 17.01.2019 16:25:35 + * last modified on Friday, 08.02.2019 15:46:52 */ @@ -230,6 +230,25 @@ typedef struct { } POWER_RAM_Type; /*!< Size = 16 (0x10) */ +/** + * @brief RADIO_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t DFEGPIO[8]; /*!< (@ 0x00000000) Description collection: Pin select for DFE pin + n */ +} RADIO_PSEL_Type; /*!< Size = 32 (0x20) */ + + +/** + * @brief RADIO_DFEPACKET [DFEPACKET] (DFE packet EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of samples transferred in the last transaction */ +} RADIO_DFEPACKET_Type; /*!< Size = 12 (0xc) */ + + /** * @brief UART_PSEL [PSEL] (Unspecified) */ @@ -677,8 +696,8 @@ typedef struct { /*!< (@ 0x40000000) CLOCK Struct typedef struct { /*!< (@ 0x40000000) POWER Structure */ __IM uint32_t RESERVED[30]; - __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode */ - __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency) */ + __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable Constant Latency mode */ + __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable Low-power mode (variable latency) */ __IM uint32_t RESERVED1[34]; __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ __IM uint32_t RESERVED2[2]; @@ -795,7 +814,9 @@ typedef struct { /*!< (@ 0x40001000) RADIO Struct __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. */ - __IM uint32_t RESERVED4[36]; + __IOM uint32_t EVENTS_CTEPRESENT; /*!< (@ 0x00000170) CTE is present (early warning right after receiving + CTEInfo byte) */ + __IM uint32_t RESERVED4[35]; __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED5[64]; __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ @@ -807,7 +828,11 @@ typedef struct { /*!< (@ 0x40001000) RADIO Struct __IM uint32_t RXCRC; /*!< (@ 0x0000040C) CRC field of previously received packet */ __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index */ __IM uint32_t PDUSTAT; /*!< (@ 0x00000414) Payload status */ - __IM uint32_t RESERVED8[59]; + __IM uint32_t RESERVED8[13]; + __IM uint32_t CTESTATUS; /*!< (@ 0x0000044C) CTEInfo parsed from received packet */ + __IM uint32_t RESERVED9[2]; + __IM uint32_t DFESTATUS; /*!< (@ 0x00000458) DFE status information */ + __IM uint32_t RESERVED10[42]; __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer */ __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency */ __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power */ @@ -823,15 +848,15 @@ typedef struct { /*!< (@ 0x40001000) RADIO Struct __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */ __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */ __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */ - __IM uint32_t RESERVED9; + __IM uint32_t RESERVED11; __IOM uint32_t TIFS; /*!< (@ 0x00000544) Interframe spacing in us */ __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */ - __IM uint32_t RESERVED10; + __IM uint32_t RESERVED12; __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */ __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */ - __IM uint32_t RESERVED11[2]; + __IM uint32_t RESERVED13[2]; __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */ - __IM uint32_t RESERVED12[39]; + __IM uint32_t RESERVED14[39]; __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection: Device address base segment n */ __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection: Device address prefix @@ -839,14 +864,26 @@ typedef struct { /*!< (@ 0x40001000) RADIO Struct __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */ __IOM uint32_t MHRMATCHCONF; /*!< (@ 0x00000644) Search pattern configuration */ __IOM uint32_t MHRMATCHMAS; /*!< (@ 0x00000648) Pattern mask */ - __IM uint32_t RESERVED13; + __IM uint32_t RESERVED15; __IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */ - __IM uint32_t RESERVED14[3]; + __IM uint32_t RESERVED16[3]; __IOM uint32_t SFD; /*!< (@ 0x00000660) IEEE 802.15.4 start of frame delimiter */ __IOM uint32_t EDCNT; /*!< (@ 0x00000664) IEEE 802.15.4 energy detect loop count */ __IOM uint32_t EDSAMPLE; /*!< (@ 0x00000668) IEEE 802.15.4 energy detect level */ __IOM uint32_t CCACTRL; /*!< (@ 0x0000066C) IEEE 802.15.4 clear channel assessment control */ - __IM uint32_t RESERVED15[611]; + __IM uint32_t RESERVED17[164]; + __IOM uint32_t DFEMODE; /*!< (@ 0x00000900) Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure + (AOD) */ + __IOM uint32_t CTEINLINECONF; /*!< (@ 0x00000904) Configuration for CTE inline mode */ + __IM uint32_t RESERVED18[2]; + __IOM uint32_t DFECTRL1; /*!< (@ 0x00000910) Various configuration for Direction finding */ + __IOM uint32_t DFECTRL2; /*!< (@ 0x00000914) Start offset for Direction finding */ + __IM uint32_t RESERVED19[4]; + __IOM uint32_t SWITCHPATTERN; /*!< (@ 0x00000928) GPIO patterns to be used for each antenna */ + __IOM uint32_t CLEARPATTERN; /*!< (@ 0x0000092C) Clear the GPIO pattern array for antenna control */ + __IOM RADIO_PSEL_Type PSEL; /*!< (@ 0x00000930) Unspecified */ + __IOM RADIO_DFEPACKET_Type DFEPACKET; /*!< (@ 0x00000950) DFE packet EasyDMA channel */ + __IM uint32_t RESERVED20[424]; __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */ } NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ diff --git a/mdk/nrf52811.svd b/mdk/nrf52811.svd index f9810a20a..b5c5f3545 100644 --- a/mdk/nrf52811.svd +++ b/mdk/nrf52811.svd @@ -318,6 +318,11 @@ POSSIBILITY OF SUCH DAMAGE.\n QCxx - 32-pin QFN 0x2003 + + CA + CAxx - WLCSP + 0x2004 + Unspecified Unspecified @@ -2472,13 +2477,13 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_CONSTLAT - Enable constant latency mode + Enable Constant Latency mode 0x078 write-only TASKS_CONSTLAT - Enable constant latency mode + Enable Constant Latency mode 0 0 @@ -2493,13 +2498,13 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_LOWPWR - Enable low power mode (variable latency) + Enable Low-power mode (variable latency) 0x07C write-only TASKS_LOWPWR - Enable low power mode (variable latency) + Enable Low-power mode (variable latency) 0 0 @@ -10138,6 +10143,32 @@ POSSIBILITY OF SUCH DAMAGE.\n + + EVENTS_CTEPRESENT + CTE is present (early warning right after receiving CTEInfo byte) + 0x170 + read-write + + + EVENTS_CTEPRESENT + CTE is present (early warning right after receiving CTEInfo byte) + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + SHORTS Shortcuts between local events and tasks @@ -11088,6 +11119,33 @@ POSSIBILITY OF SUCH DAMAGE.\n + + CTEPRESENT + Write '1' to enable interrupt for event CTEPRESENT + 28 + 28 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + @@ -11690,6 +11748,33 @@ POSSIBILITY OF SUCH DAMAGE.\n + + CTEPRESENT + Write '1' to disable interrupt for event CTEPRESENT + 28 + 28 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + @@ -11804,6 +11889,96 @@ POSSIBILITY OF SUCH DAMAGE.\n + + CTESTATUS + CTEInfo parsed from received packet + 0x44C + read-only + + + CTETIME + CTETime parsed from packet + 0 + 4 + + + RFU + RFU parsed from packet + 5 + 5 + + + CTETYPE + CTEType parsed from packet + 6 + 7 + + + + + DFESTATUS + DFE status information + 0x458 + read-only + + + SWITCHINGSTATE + Internal state of switching state machine + 0 + 2 + + + Idle + Switching state Idle + 0 + + + Offset + Switching state Offset + 1 + + + Guard + Switching state Guard + 2 + + + Ref + Switching state Ref + 3 + + + Switching + Switching state Switching + 4 + + + Ending + Switching state Ending + 5 + + + + + SAMPLINGSTATE + Internal state of sampling state machine + 4 + 4 + + + Idle + Sampling state Idle + 0 + + + Sampling + Sampling state Sampling + 1 + + + + + PACKETPTR Packet pointer @@ -13012,6 +13187,524 @@ POSSIBILITY OF SUCH DAMAGE.\n + + DFEMODE + Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD) + 0x900 + read-write + 0x00000000 + + + DFEOPMODE + Direction finding operation mode + 0 + 1 + + + Disabled + Direction finding mode disabled + 0 + + + AoD + Direction finding mode set to AoD + 2 + + + AoA + Direction finding mode set to AoA + 3 + + + + + + + CTEINLINECONF + Configuration for CTE inline mode + 0x904 + read-write + 0x00002800 + + + CTEINLINECTRLEN + Enable parsing of CTEInfo from received packet in BLE modes + 0 + 0 + + + Enabled + Parsing of CTEInfo is enabled + 1 + + + Disabled + Parsing of CTEInfo is disabled + 0 + + + + + CTEINFOINS1 + CTEInfo is S1 byte or not + 3 + 3 + + + InS1 + CTEInfo is in S1 byte (data PDU) + 1 + + + NotInS1 + CTEInfo is NOT in S1 byte (advertising PDU) + 0 + + + + + CTEERRORHANDLING + Sampling/switching if CRC is not OK + 4 + 4 + + + Yes + Sampling and antenna switching also when CRC is not OK + 1 + + + No + No sampling and antenna switching when CRC is not OK + 0 + + + + + CTETIMEVALIDRANGE + Max range of CTETime + 6 + 7 + + + 20 + 20 in 8us unit (default) Set to 20 if parsed CTETime is larger han 20 + 0 + + + 31 + 31 in 8us unit + 1 + + + 63 + 63 in 8us unit + 2 + + + + + CTEINLINERXMODE1US + Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set + 10 + 12 + + + 4us + 4us + 1 + + + 2us + 2us + 2 + + + 1us + 1us + 3 + + + 500ns + 0.5us + 4 + + + 250ns + 0.25us + 5 + + + 125ns + 0.125us + 6 + + + + + CTEINLINERXMODE2US + Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set + 13 + 15 + + + 4us + 4us + 1 + + + 2us + 2us + 2 + + + 1us + 1us + 3 + + + 500ns + 0.5us + 4 + + + 250ns + 0.25us + 5 + + + 125ns + 0.125us + 6 + + + + + S0CONF + S0 bit pattern to match + 16 + 23 + + + S0MASK + S0 bit mask to set which bit to match + 24 + 31 + + + + + DFECTRL1 + Various configuration for Direction finding + 0x910 + read-write + 0x00023282 + + + NUMBEROF8US + Length of the AoA/AoD procedure in number of 8 us units + 0 + 5 + + + DFEINEXTENSION + Add CTE extension and do antenna switching/sampling in this extension + 7 + 7 + + + CRC + AoA/AoD procedure triggered at end of CRC + 1 + + + Payload + Antenna switching/sampling is done in the packet payload + 0 + + + + + TSWITCHSPACING + Interval between every time the antenna is changed in the SWITCHING state + 8 + 10 + + + 4us + 4us + 1 + + + 2us + 2us + 2 + + + 1us + 1us + 3 + + + + + TSAMPLESPACINGREF + Interval between samples in the REFERENCE period + 12 + 14 + + + 4us + 4us + 1 + + + 2us + 2us + 2 + + + 1us + 1us + 3 + + + 500ns + 0.5us + 4 + + + 250ns + 0.25us + 5 + + + 125ns + 0.125us + 6 + + + + + SAMPLETYPE + Whether to sample I/Q or magnitude/phase + 15 + 15 + + + IQ + Complex samples in I and Q + 0 + + + MagPhase + Complex samples as magnitude and phase + 1 + + + + + TSAMPLESPACING + Interval between samples in the SWITCHING period when CTEINLINECTRLEN is 0 + 16 + 18 + + + 4us + 4us + 1 + + + 2us + 2us + 2 + + + 1us + 1us + 3 + + + 500ns + 0.5us + 4 + + + 250ns + 0.25us + 5 + + + 125ns + 0.125us + 6 + + + + + AGCBACKOFFGAIN + Gain will be lowered by the specified number of gain steps at the start of CTE + 24 + 27 + + + + + DFECTRL2 + Start offset for Direction finding + 0x914 + read-write + 0x00000000 + + + TSWITCHOFFSET + Signed value offset after the end of the CRC before starting switching in number of 16M cycles + 0 + 12 + + + TSAMPLEOFFSET + Signed value offset before starting sampling in number of 16M cycles relative to the beginning of the REFERENCE state - 12 us after switching start + 16 + 27 + + + + + SWITCHPATTERN + GPIO patterns to be used for each antenna + 0x928 + read-write + 0x00000000 + + + SWITCHPATTERN + Fill array of GPIO patterns for antenna control + 0 + 7 + + + + + CLEARPATTERN + Clear the GPIO pattern array for antenna control + 0x92C + read-write + + + CLEARPATTERN + Clears GPIO pattern array for antenna control + 0 + 0 + + + Clear + Writing a '1' clears the GPIO pattern; writing a '0' has no effect + 1 + + + + + + + PSEL + Unspecified + RADIO_PSEL + read-write + 0x930 + + 0x8 + 0x4 + DFEGPIO[%s] + Description collection: Pin select for DFE pin n + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + DFEPACKET + DFE packet EasyDMA channel + RADIO_DFEPACKET + read-write + 0x950 + + PTR + Data pointer + 0x000 + read-write + 0x00000000 + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of buffer words to transfer + 0x004 + read-write + 0x00001000 + + + MAXCNT + Maximum number of buffer words to transfer + 0 + 15 + + + + + AMOUNT + Number of samples transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of samples transferred in the last transaction + 0 + 15 + + + + POWER Peripheral power control @@ -27996,7 +28689,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SCRATCHPTR - Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. + Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved. 0 31 diff --git a/mdk/nrf52811_bitfields.h b/mdk/nrf52811_bitfields.h index 4d0e08388..58e331fdf 100644 --- a/mdk/nrf52811_bitfields.h +++ b/mdk/nrf52811_bitfields.h @@ -169,7 +169,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: AAR_SCRATCHPTR */ /* Description: Pointer to data area used for temporary storage */ -/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. */ +/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved. */ #define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ #define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ @@ -1734,6 +1734,7 @@ POSSIBILITY OF SUCH DAMAGE. #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ #define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL) /*!< QFxx - 48-pin QFN */ #define FICR_INFO_PACKAGE_PACKAGE_QC (0x2003UL) /*!< QCxx - 32-pin QFN */ +#define FICR_INFO_PACKAGE_PACKAGE_CA (0x2004UL) /*!< CAxx - WLCSP */ #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ /* Register: FICR_INFO_RAM */ @@ -4112,17 +4113,17 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: Power control */ /* Register: POWER_TASKS_CONSTLAT */ -/* Description: Enable constant latency mode */ +/* Description: Enable Constant Latency mode */ -/* Bit 0 : Enable constant latency mode */ +/* Bit 0 : Enable Constant Latency mode */ #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */ #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of TASKS_CONSTLAT field. */ #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (1UL) /*!< Trigger task */ /* Register: POWER_TASKS_LOWPWR */ -/* Description: Enable low power mode (variable latency) */ +/* Description: Enable Low-power mode (variable latency) */ -/* Bit 0 : Enable low power mode (variable latency) */ +/* Bit 0 : Enable Low-power mode (variable latency) */ #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */ #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR field. */ #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (1UL) /*!< Trigger task */ @@ -6276,6 +6277,15 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_NotGenerated (0UL) /*!< Event not generated */ #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Generated (1UL) /*!< Event generated */ +/* Register: RADIO_EVENTS_CTEPRESENT */ +/* Description: CTE is present (early warning right after receiving CTEInfo byte) */ + +/* Bit 0 : CTE is present (early warning right after receiving CTEInfo byte) */ +#define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Pos (0UL) /*!< Position of EVENTS_CTEPRESENT field. */ +#define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Msk (0x1UL << RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Pos) /*!< Bit mask of EVENTS_CTEPRESENT field. */ +#define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Generated (1UL) /*!< Event generated */ + /* Register: RADIO_SHORTS */ /* Description: Shortcuts between local events and tasks */ @@ -6396,6 +6406,13 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_INTENSET */ /* Description: Enable interrupt */ +/* Bit 28 : Write '1' to enable interrupt for event CTEPRESENT */ +#define RADIO_INTENSET_CTEPRESENT_Pos (28UL) /*!< Position of CTEPRESENT field. */ +#define RADIO_INTENSET_CTEPRESENT_Msk (0x1UL << RADIO_INTENSET_CTEPRESENT_Pos) /*!< Bit mask of CTEPRESENT field. */ +#define RADIO_INTENSET_CTEPRESENT_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_CTEPRESENT_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_CTEPRESENT_Set (1UL) /*!< Enable */ + /* Bit 27 : Write '1' to enable interrupt for event PHYEND */ #define RADIO_INTENSET_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */ #define RADIO_INTENSET_PHYEND_Msk (0x1UL << RADIO_INTENSET_PHYEND_Pos) /*!< Bit mask of PHYEND field. */ @@ -6553,6 +6570,13 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_INTENCLR */ /* Description: Disable interrupt */ +/* Bit 28 : Write '1' to disable interrupt for event CTEPRESENT */ +#define RADIO_INTENCLR_CTEPRESENT_Pos (28UL) /*!< Position of CTEPRESENT field. */ +#define RADIO_INTENCLR_CTEPRESENT_Msk (0x1UL << RADIO_INTENCLR_CTEPRESENT_Pos) /*!< Bit mask of CTEPRESENT field. */ +#define RADIO_INTENCLR_CTEPRESENT_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_CTEPRESENT_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_CTEPRESENT_Clear (1UL) /*!< Disable */ + /* Bit 27 : Write '1' to disable interrupt for event PHYEND */ #define RADIO_INTENCLR_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */ #define RADIO_INTENCLR_PHYEND_Msk (0x1UL << RADIO_INTENCLR_PHYEND_Pos) /*!< Bit mask of PHYEND field. */ @@ -6752,6 +6776,40 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PDUSTAT_PDUSTAT_LessThan (0UL) /*!< Payload less than PCNF1.MAXLEN */ #define RADIO_PDUSTAT_PDUSTAT_GreaterThan (1UL) /*!< Payload greater than PCNF1.MAXLEN */ +/* Register: RADIO_CTESTATUS */ +/* Description: CTEInfo parsed from received packet */ + +/* Bits 7..6 : CTEType parsed from packet */ +#define RADIO_CTESTATUS_CTETYPE_Pos (6UL) /*!< Position of CTETYPE field. */ +#define RADIO_CTESTATUS_CTETYPE_Msk (0x3UL << RADIO_CTESTATUS_CTETYPE_Pos) /*!< Bit mask of CTETYPE field. */ + +/* Bit 5 : RFU parsed from packet */ +#define RADIO_CTESTATUS_RFU_Pos (5UL) /*!< Position of RFU field. */ +#define RADIO_CTESTATUS_RFU_Msk (0x1UL << RADIO_CTESTATUS_RFU_Pos) /*!< Bit mask of RFU field. */ + +/* Bits 4..0 : CTETime parsed from packet */ +#define RADIO_CTESTATUS_CTETIME_Pos (0UL) /*!< Position of CTETIME field. */ +#define RADIO_CTESTATUS_CTETIME_Msk (0x1FUL << RADIO_CTESTATUS_CTETIME_Pos) /*!< Bit mask of CTETIME field. */ + +/* Register: RADIO_DFESTATUS */ +/* Description: DFE status information */ + +/* Bit 4 : Internal state of sampling state machine */ +#define RADIO_DFESTATUS_SAMPLINGSTATE_Pos (4UL) /*!< Position of SAMPLINGSTATE field. */ +#define RADIO_DFESTATUS_SAMPLINGSTATE_Msk (0x1UL << RADIO_DFESTATUS_SAMPLINGSTATE_Pos) /*!< Bit mask of SAMPLINGSTATE field. */ +#define RADIO_DFESTATUS_SAMPLINGSTATE_Idle (0UL) /*!< Sampling state Idle */ +#define RADIO_DFESTATUS_SAMPLINGSTATE_Sampling (1UL) /*!< Sampling state Sampling */ + +/* Bits 2..0 : Internal state of switching state machine */ +#define RADIO_DFESTATUS_SWITCHINGSTATE_Pos (0UL) /*!< Position of SWITCHINGSTATE field. */ +#define RADIO_DFESTATUS_SWITCHINGSTATE_Msk (0x7UL << RADIO_DFESTATUS_SWITCHINGSTATE_Pos) /*!< Bit mask of SWITCHINGSTATE field. */ +#define RADIO_DFESTATUS_SWITCHINGSTATE_Idle (0UL) /*!< Switching state Idle */ +#define RADIO_DFESTATUS_SWITCHINGSTATE_Offset (1UL) /*!< Switching state Offset */ +#define RADIO_DFESTATUS_SWITCHINGSTATE_Guard (2UL) /*!< Switching state Guard */ +#define RADIO_DFESTATUS_SWITCHINGSTATE_Ref (3UL) /*!< Switching state Ref */ +#define RADIO_DFESTATUS_SWITCHINGSTATE_Switching (4UL) /*!< Switching state Switching */ +#define RADIO_DFESTATUS_SWITCHINGSTATE_Ending (5UL) /*!< Switching state Ending */ + /* Register: RADIO_PACKETPTR */ /* Description: Packet pointer */ @@ -7231,6 +7289,186 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_CCACTRL_CCAMODE_CarrierOrEdMode (3UL) /*!< Energy above threshold OR carrier seen */ #define RADIO_CCACTRL_CCAMODE_EdModeTest1 (4UL) /*!< Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. */ +/* Register: RADIO_DFEMODE */ +/* Description: Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD) */ + +/* Bits 1..0 : Direction finding operation mode */ +#define RADIO_DFEMODE_DFEOPMODE_Pos (0UL) /*!< Position of DFEOPMODE field. */ +#define RADIO_DFEMODE_DFEOPMODE_Msk (0x3UL << RADIO_DFEMODE_DFEOPMODE_Pos) /*!< Bit mask of DFEOPMODE field. */ +#define RADIO_DFEMODE_DFEOPMODE_Disabled (0UL) /*!< Direction finding mode disabled */ +#define RADIO_DFEMODE_DFEOPMODE_AoD (2UL) /*!< Direction finding mode set to AoD */ +#define RADIO_DFEMODE_DFEOPMODE_AoA (3UL) /*!< Direction finding mode set to AoA */ + +/* Register: RADIO_CTEINLINECONF */ +/* Description: Configuration for CTE inline mode */ + +/* Bits 31..24 : S0 bit mask to set which bit to match */ +#define RADIO_CTEINLINECONF_S0MASK_Pos (24UL) /*!< Position of S0MASK field. */ +#define RADIO_CTEINLINECONF_S0MASK_Msk (0xFFUL << RADIO_CTEINLINECONF_S0MASK_Pos) /*!< Bit mask of S0MASK field. */ + +/* Bits 23..16 : S0 bit pattern to match */ +#define RADIO_CTEINLINECONF_S0CONF_Pos (16UL) /*!< Position of S0CONF field. */ +#define RADIO_CTEINLINECONF_S0CONF_Msk (0xFFUL << RADIO_CTEINLINECONF_S0CONF_Pos) /*!< Bit mask of S0CONF field. */ + +/* Bits 15..13 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos (13UL) /*!< Position of CTEINLINERXMODE2US field. */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos) /*!< Bit mask of CTEINLINERXMODE2US field. */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_4us (1UL) /*!< 4us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_2us (2UL) /*!< 2us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_1us (3UL) /*!< 1us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_500ns (4UL) /*!< 0.5us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_250ns (5UL) /*!< 0.25us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_125ns (6UL) /*!< 0.125us */ + +/* Bits 12..10 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos (10UL) /*!< Position of CTEINLINERXMODE1US field. */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos) /*!< Bit mask of CTEINLINERXMODE1US field. */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_4us (1UL) /*!< 4us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_2us (2UL) /*!< 2us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_1us (3UL) /*!< 1us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_500ns (4UL) /*!< 0.5us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_250ns (5UL) /*!< 0.25us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_125ns (6UL) /*!< 0.125us */ + +/* Bits 7..6 : Max range of CTETime */ +#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos (6UL) /*!< Position of CTETIMEVALIDRANGE field. */ +#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Msk (0x3UL << RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos) /*!< Bit mask of CTETIMEVALIDRANGE field. */ +#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_20 (0UL) /*!< 20 in 8us unit (default) Set to 20 if parsed CTETime is larger han 20 */ +#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_31 (1UL) /*!< 31 in 8us unit */ +#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_63 (2UL) /*!< 63 in 8us unit */ + +/* Bit 4 : Sampling/switching if CRC is not OK */ +#define RADIO_CTEINLINECONF_CTEERRORHANDLING_Pos (4UL) /*!< Position of CTEERRORHANDLING field. */ +#define RADIO_CTEINLINECONF_CTEERRORHANDLING_Msk (0x1UL << RADIO_CTEINLINECONF_CTEERRORHANDLING_Pos) /*!< Bit mask of CTEERRORHANDLING field. */ +#define RADIO_CTEINLINECONF_CTEERRORHANDLING_No (0UL) /*!< No sampling and antenna switching when CRC is not OK */ +#define RADIO_CTEINLINECONF_CTEERRORHANDLING_Yes (1UL) /*!< Sampling and antenna switching also when CRC is not OK */ + +/* Bit 3 : CTEInfo is S1 byte or not */ +#define RADIO_CTEINLINECONF_CTEINFOINS1_Pos (3UL) /*!< Position of CTEINFOINS1 field. */ +#define RADIO_CTEINLINECONF_CTEINFOINS1_Msk (0x1UL << RADIO_CTEINLINECONF_CTEINFOINS1_Pos) /*!< Bit mask of CTEINFOINS1 field. */ +#define RADIO_CTEINLINECONF_CTEINFOINS1_NotInS1 (0UL) /*!< CTEInfo is NOT in S1 byte (advertising PDU) */ +#define RADIO_CTEINLINECONF_CTEINFOINS1_InS1 (1UL) /*!< CTEInfo is in S1 byte (data PDU) */ + +/* Bit 0 : Enable parsing of CTEInfo from received packet in BLE modes */ +#define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Pos (0UL) /*!< Position of CTEINLINECTRLEN field. */ +#define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Msk (0x1UL << RADIO_CTEINLINECONF_CTEINLINECTRLEN_Pos) /*!< Bit mask of CTEINLINECTRLEN field. */ +#define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Disabled (0UL) /*!< Parsing of CTEInfo is disabled */ +#define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Enabled (1UL) /*!< Parsing of CTEInfo is enabled */ + +/* Register: RADIO_DFECTRL1 */ +/* Description: Various configuration for Direction finding */ + +/* Bits 27..24 : Gain will be lowered by the specified number of gain steps at the start of CTE */ +#define RADIO_DFECTRL1_AGCBACKOFFGAIN_Pos (24UL) /*!< Position of AGCBACKOFFGAIN field. */ +#define RADIO_DFECTRL1_AGCBACKOFFGAIN_Msk (0xFUL << RADIO_DFECTRL1_AGCBACKOFFGAIN_Pos) /*!< Bit mask of AGCBACKOFFGAIN field. */ + +/* Bits 18..16 : Interval between samples in the SWITCHING period when CTEINLINECTRLEN is 0 */ +#define RADIO_DFECTRL1_TSAMPLESPACING_Pos (16UL) /*!< Position of TSAMPLESPACING field. */ +#define RADIO_DFECTRL1_TSAMPLESPACING_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACING_Pos) /*!< Bit mask of TSAMPLESPACING field. */ +#define RADIO_DFECTRL1_TSAMPLESPACING_4us (1UL) /*!< 4us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_2us (2UL) /*!< 2us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_1us (3UL) /*!< 1us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_500ns (4UL) /*!< 0.5us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_250ns (5UL) /*!< 0.25us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_125ns (6UL) /*!< 0.125us */ + +/* Bit 15 : Whether to sample I/Q or magnitude/phase */ +#define RADIO_DFECTRL1_SAMPLETYPE_Pos (15UL) /*!< Position of SAMPLETYPE field. */ +#define RADIO_DFECTRL1_SAMPLETYPE_Msk (0x1UL << RADIO_DFECTRL1_SAMPLETYPE_Pos) /*!< Bit mask of SAMPLETYPE field. */ +#define RADIO_DFECTRL1_SAMPLETYPE_IQ (0UL) /*!< Complex samples in I and Q */ +#define RADIO_DFECTRL1_SAMPLETYPE_MagPhase (1UL) /*!< Complex samples as magnitude and phase */ + +/* Bits 14..12 : Interval between samples in the REFERENCE period */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos (12UL) /*!< Position of TSAMPLESPACINGREF field. */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos) /*!< Bit mask of TSAMPLESPACINGREF field. */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_4us (1UL) /*!< 4us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_2us (2UL) /*!< 2us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_1us (3UL) /*!< 1us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_500ns (4UL) /*!< 0.5us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_250ns (5UL) /*!< 0.25us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_125ns (6UL) /*!< 0.125us */ + +/* Bits 10..8 : Interval between every time the antenna is changed in the SWITCHING state */ +#define RADIO_DFECTRL1_TSWITCHSPACING_Pos (8UL) /*!< Position of TSWITCHSPACING field. */ +#define RADIO_DFECTRL1_TSWITCHSPACING_Msk (0x7UL << RADIO_DFECTRL1_TSWITCHSPACING_Pos) /*!< Bit mask of TSWITCHSPACING field. */ +#define RADIO_DFECTRL1_TSWITCHSPACING_4us (1UL) /*!< 4us */ +#define RADIO_DFECTRL1_TSWITCHSPACING_2us (2UL) /*!< 2us */ +#define RADIO_DFECTRL1_TSWITCHSPACING_1us (3UL) /*!< 1us */ + +/* Bit 7 : Add CTE extension and do antenna switching/sampling in this extension */ +#define RADIO_DFECTRL1_DFEINEXTENSION_Pos (7UL) /*!< Position of DFEINEXTENSION field. */ +#define RADIO_DFECTRL1_DFEINEXTENSION_Msk (0x1UL << RADIO_DFECTRL1_DFEINEXTENSION_Pos) /*!< Bit mask of DFEINEXTENSION field. */ +#define RADIO_DFECTRL1_DFEINEXTENSION_Payload (0UL) /*!< Antenna switching/sampling is done in the packet payload */ +#define RADIO_DFECTRL1_DFEINEXTENSION_CRC (1UL) /*!< AoA/AoD procedure triggered at end of CRC */ + +/* Bits 5..0 : Length of the AoA/AoD procedure in number of 8 us units */ +#define RADIO_DFECTRL1_NUMBEROF8US_Pos (0UL) /*!< Position of NUMBEROF8US field. */ +#define RADIO_DFECTRL1_NUMBEROF8US_Msk (0x3FUL << RADIO_DFECTRL1_NUMBEROF8US_Pos) /*!< Bit mask of NUMBEROF8US field. */ + +/* Register: RADIO_DFECTRL2 */ +/* Description: Start offset for Direction finding */ + +/* Bits 27..16 : Signed value offset before starting sampling in number of 16M cycles relative to the beginning of the REFERENCE state - 12 us after switching start */ +#define RADIO_DFECTRL2_TSAMPLEOFFSET_Pos (16UL) /*!< Position of TSAMPLEOFFSET field. */ +#define RADIO_DFECTRL2_TSAMPLEOFFSET_Msk (0xFFFUL << RADIO_DFECTRL2_TSAMPLEOFFSET_Pos) /*!< Bit mask of TSAMPLEOFFSET field. */ + +/* Bits 12..0 : Signed value offset after the end of the CRC before starting switching in number of 16M cycles */ +#define RADIO_DFECTRL2_TSWITCHOFFSET_Pos (0UL) /*!< Position of TSWITCHOFFSET field. */ +#define RADIO_DFECTRL2_TSWITCHOFFSET_Msk (0x1FFFUL << RADIO_DFECTRL2_TSWITCHOFFSET_Pos) /*!< Bit mask of TSWITCHOFFSET field. */ + +/* Register: RADIO_SWITCHPATTERN */ +/* Description: GPIO patterns to be used for each antenna */ + +/* Bits 7..0 : Fill array of GPIO patterns for antenna control */ +#define RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos (0UL) /*!< Position of SWITCHPATTERN field. */ +#define RADIO_SWITCHPATTERN_SWITCHPATTERN_Msk (0xFFUL << RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos) /*!< Bit mask of SWITCHPATTERN field. */ + +/* Register: RADIO_CLEARPATTERN */ +/* Description: Clear the GPIO pattern array for antenna control */ + +/* Bit 0 : Clears GPIO pattern array for antenna control */ +#define RADIO_CLEARPATTERN_CLEARPATTERN_Pos (0UL) /*!< Position of CLEARPATTERN field. */ +#define RADIO_CLEARPATTERN_CLEARPATTERN_Msk (0x1UL << RADIO_CLEARPATTERN_CLEARPATTERN_Pos) /*!< Bit mask of CLEARPATTERN field. */ +#define RADIO_CLEARPATTERN_CLEARPATTERN_Clear (1UL) /*!< Writing a '1' clears the GPIO pattern; writing a '0' has no effect */ + +/* Register: RADIO_PSEL_DFEGPIO */ +/* Description: Description collection: Pin select for DFE pin n */ + +/* Bit 31 : Connection */ +#define RADIO_PSEL_DFEGPIO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define RADIO_PSEL_DFEGPIO_CONNECT_Msk (0x1UL << RADIO_PSEL_DFEGPIO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define RADIO_PSEL_DFEGPIO_CONNECT_Connected (0UL) /*!< Connect */ +#define RADIO_PSEL_DFEGPIO_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define RADIO_PSEL_DFEGPIO_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define RADIO_PSEL_DFEGPIO_PORT_Msk (0x1UL << RADIO_PSEL_DFEGPIO_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define RADIO_PSEL_DFEGPIO_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define RADIO_PSEL_DFEGPIO_PIN_Msk (0x1FUL << RADIO_PSEL_DFEGPIO_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: RADIO_DFEPACKET_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define RADIO_DFEPACKET_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define RADIO_DFEPACKET_PTR_PTR_Msk (0xFFFFFFFFUL << RADIO_DFEPACKET_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: RADIO_DFEPACKET_MAXCNT */ +/* Description: Maximum number of buffer words to transfer */ + +/* Bits 15..0 : Maximum number of buffer words to transfer */ +#define RADIO_DFEPACKET_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define RADIO_DFEPACKET_MAXCNT_MAXCNT_Msk (0xFFFFUL << RADIO_DFEPACKET_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: RADIO_DFEPACKET_AMOUNT */ +/* Description: Number of samples transferred in the last transaction */ + +/* Bits 15..0 : Number of samples transferred in the last transaction */ +#define RADIO_DFEPACKET_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define RADIO_DFEPACKET_AMOUNT_AMOUNT_Msk (0xFFFFUL << RADIO_DFEPACKET_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + /* Register: RADIO_POWER */ /* Description: Peripheral power control */ diff --git a/mdk/nrf52840.h b/mdk/nrf52840.h index 0fefdd405..bb26f7c9b 100644 --- a/mdk/nrf52840.h +++ b/mdk/nrf52840.h @@ -30,10 +30,10 @@ * @file nrf52840.h * @brief CMSIS HeaderFile * @version 1 - * @date 17. January 2019 - * @note Generated by SVDConv V3.3.18 on Thursday, 17.01.2019 17:25:40 + * @date 08. February 2019 + * @note Generated by SVDConv V3.3.18 on Friday, 08.02.2019 16:46:56 * from File 'nrf52840.svd', - * last modified on Thursday, 17.01.2019 16:25:35 + * last modified on Friday, 08.02.2019 15:46:52 */ diff --git a/mdk/nrf9160.h b/mdk/nrf9160.h index c8d3eea1a..f41afa7e6 100644 --- a/mdk/nrf9160.h +++ b/mdk/nrf9160.h @@ -30,10 +30,10 @@ * @file nrf9160.h * @brief CMSIS HeaderFile * @version 1 - * @date 17. January 2019 - * @note Generated by SVDConv V3.3.18 on Thursday, 17.01.2019 17:25:40 + * @date 08. February 2019 + * @note Generated by SVDConv V3.3.18 on Friday, 08.02.2019 16:46:57 * from File 'nrf9160.svd', - * last modified on Thursday, 17.01.2019 16:25:35 + * last modified on Friday, 08.02.2019 15:46:52 */ diff --git a/mdk/system_nrf52810.c b/mdk/system_nrf52810.c index 26ef79b7d..d0cf25b55 100644 --- a/mdk/system_nrf52810.c +++ b/mdk/system_nrf52810.c @@ -36,6 +36,7 @@ static bool errata_31(void); static bool errata_36(void); static bool errata_66(void); static bool errata_103(void); +static bool errata_108(void); static bool errata_136(void); /* Helper functions for Errata workarounds in nRF52832 */ @@ -45,7 +46,6 @@ static bool errata_16(void); static bool errata_32(void); static bool errata_37(void); static bool errata_57(void); -static bool errata_108(void); static bool errata_182(void); #endif @@ -168,14 +168,12 @@ void SystemInit(void) if (errata_103()){ NRF_CCM->MAXPACKETSIZE = 0xFBul; } - - #if defined (DEVELOP_IN_NRF52832) + /* Workaround for Errata 108 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document for your device located at https://www.nordicsemi.com/DocLib */ if (errata_108()){ *(volatile uint32_t *)0x40000EE4 = *(volatile uint32_t *)0x10000258 & 0x0000004F; } - #endif /* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document for your device located at https://www.nordicsemi.com/DocLib */ @@ -248,10 +246,15 @@ static bool errata_16(void) static bool errata_31(void) { - if ((*(uint32_t *)0x10000130ul == 0xAul) && (*(uint32_t *)0x10000134ul == 0x0ul)){ - return true; + if (*(uint32_t *)0x10000130ul == 0xAul){ + if (*(uint32_t *)0x10000134ul == 0x0ul){ + return true; + } + if (*(uint32_t *)0x10000134ul == 0x1ul){ + return true; + } } - + #if defined (DEVELOP_IN_NRF52832) if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){ if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){ @@ -263,10 +266,11 @@ static bool errata_31(void) if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){ return true; } + return false; } #endif - /* Fix should always apply. */ + /* Apply by default for unknown devices until errata is confirmed fixed. */ return true; } @@ -285,10 +289,15 @@ static bool errata_32(void) static bool errata_36(void) { - if ((*(uint32_t *)0x10000130ul == 0xAul) && (*(uint32_t *)0x10000134ul == 0x0ul)){ - return true; + if (*(uint32_t *)0x10000130ul == 0xAul){ + if (*(uint32_t *)0x10000134ul == 0x0ul){ + return true; + } + if (*(uint32_t *)0x10000134ul == 0x1ul){ + return true; + } } - + #if defined (DEVELOP_IN_NRF52832) if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){ if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){ @@ -300,10 +309,12 @@ static bool errata_36(void) if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){ return true; } + return false; } + #endif - /* Fix should always apply. */ + /* Apply by default for unknown devices until errata is confirmed fixed. */ return true; } @@ -335,33 +346,39 @@ static bool errata_57(void) static bool errata_66(void) { - if ((*(uint32_t *)0x10000130ul == 0xAul) && (*(uint32_t *)0x10000134ul == 0x0ul)){ - return true; + if (*(uint32_t *)0x10000130ul == 0xAul){ + if (*(uint32_t *)0x10000134ul == 0x0ul){ + return true; + } + if (*(uint32_t *)0x10000134ul == 0x1ul){ + return true; + } } - + #if defined (DEVELOP_IN_NRF52832) if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){ if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){ return true; } + return false; } #endif - /* Fix should always apply. */ + /* Apply by default for unknown devices until errata is confirmed fixed. */ return true; } static bool errata_103(void) { - if ((*(uint32_t *)0x10000130ul == 0xAul) && (*(uint32_t *)0x10000134ul == 0x0ul)){ - return true; + if (*(uint32_t *)0x10000130ul == 0xAul){ + if (*(uint32_t *)0x10000134ul == 0x0ul){ + return true; + } } - /* Fix should always apply. */ - return true; + return false; } -#if defined (DEVELOP_IN_NRF52832) static bool errata_108(void) { if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){ @@ -378,14 +395,18 @@ static bool errata_108(void) return false; } -#endif static bool errata_136(void) { - if ((*(uint32_t *)0x10000130ul == 0xAul) && (*(uint32_t *)0x10000134ul == 0x0ul)){ - return true; + if (*(uint32_t *)0x10000130ul == 0xAul){ + if (*(uint32_t *)0x10000134ul == 0x0ul){ + return true; + } + if (*(uint32_t *)0x10000134ul == 0x1ul){ + return true; + } } - + #if defined (DEVELOP_IN_NRF52832) if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){ if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){ @@ -397,10 +418,11 @@ static bool errata_136(void) if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){ return true; } + return false; } #endif - /* Fix should always apply. */ + /* Apply by default for unknown devices until errata is confirmed fixed. */ return true; } diff --git a/mdk/system_nrf52811.c b/mdk/system_nrf52811.c index ddf76ed43..c2e42292a 100644 --- a/mdk/system_nrf52811.c +++ b/mdk/system_nrf52811.c @@ -35,8 +35,14 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. static bool errata_31(void); static bool errata_36(void); static bool errata_66(void); +static bool errata_108(void); static bool errata_136(void); +/* nRF52840 erratas */ +#ifdef DEVELOP_IN_NRF52840 + static bool errata_103(void); + static bool errata_115(void); +#endif #if defined ( __CC_ARM ) uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; @@ -88,6 +94,27 @@ void SystemInit(void) NRF_TEMP->T3 = NRF_FICR->TEMP.T3; NRF_TEMP->T4 = NRF_FICR->TEMP.T4; } + + #ifdef DEVELOP_IN_NRF52840 + + /* Workaround for Errata 103 "CCM: Wrong reset value of CCM MAXPACKETSIZE" found at the Errata document + for your device located at https://www.nordicsemi.com/DocLib */ + if (errata_103()){ + NRF_CCM->MAXPACKETSIZE = 0xFBul; + } + + /* Workaround for Errata 115 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document + for your device located at https://www.nordicsemi.com/DocLib */ + if (errata_115()){ + *(volatile uint32_t *)0x40000EE4 = (*(volatile uint32_t *)0x40000EE4 & 0xFFFFFFF0) | (*(uint32_t *)0x10000258 & 0x0000000F); + } + #endif + + /* Workaround for Errata 108 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document + for your device located at https://www.nordicsemi.com/DocLib */ + if (errata_108()){ + *(volatile uint32_t *)0x40000EE4 = *(volatile uint32_t *)0x10000258 & 0x0000004F; + } /* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document for your device located at https://www.nordicsemi.com/DocLib */ @@ -101,13 +128,20 @@ void SystemInit(void) defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be reserved for PinReset and not available as normal GPIO. */ #if defined (CONFIG_GPIO_AS_PINRESET) + + #ifdef DEVELOP_IN_NRF52840 + #define RESET_PIN 18 + #else + #define RESET_PIN 21 + #endif + if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) || ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){ NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - NRF_UICR->PSELRESET[0] = 21; + NRF_UICR->PSELRESET[0] = RESET_PIN; while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - NRF_UICR->PSELRESET[1] = 21; + NRF_UICR->PSELRESET[1] = RESET_PIN; while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} @@ -120,49 +154,140 @@ void SystemInit(void) static bool errata_31(void) { - #if !defined (DISABLE_WORKAROUND_31) - if ((*(uint32_t *)0x10000130ul == 0xEul) && (*(uint32_t *)0x10000134ul == 0x0ul)){ - return true; + if (*(uint32_t *)0x10000130ul == 0xEul){ + if (*(uint32_t *)0x10000134ul == 0x0ul){ + return true; + } } - #endif - - return false; + + /* Apply by default for unknown devices until errata is confirmed fixed. */ + return true; } static bool errata_36(void) { - #if !defined (DISABLE_WORKAROUND_36) - if ((*(uint32_t *)0x10000130ul == 0xEul) && (*(uint32_t *)0x10000134ul == 0x0ul)){ - return true; + if (*(uint32_t *)0x10000130ul == 0xEul){ + if (*(uint32_t *)0x10000134ul == 0x0ul){ + return true; + } } + + #ifdef DEVELOP_IN_NRF52840 + if (*(uint32_t *)0x10000130ul == 0x8ul){ + if (*(uint32_t *)0x10000134ul == 0x0ul){ + return true; + } + if (*(uint32_t *)0x10000134ul == 0x1ul){ + return true; + } + if (*(uint32_t *)0x10000134ul == 0x2ul){ + return true; + } + if (*(uint32_t *)0x10000134ul == 0x3ul){ + return true; + } + } #endif - - return false; + + /* Apply by default for unknown devices until errata is confirmed fixed. */ + return true; } static bool errata_66(void) { - #if !defined (DISABLE_WORKAROUND_66) - if ((*(uint32_t *)0x10000130ul == 0xEul) && (*(uint32_t *)0x10000134ul == 0x0ul)){ - return true; + if (*(uint32_t *)0x10000130ul == 0xEul){ + if (*(uint32_t *)0x10000134ul == 0x0ul){ + return true; + } } + + #ifdef DEVELOP_IN_NRF52840 + if (*(uint32_t *)0x10000130ul == 0x8ul){ + if (*(uint32_t *)0x10000134ul == 0x0ul){ + return true; + } + if (*(uint32_t *)0x10000134ul == 0x1ul){ + return true; + } + if (*(uint32_t *)0x10000134ul == 0x2ul){ + return true; + } + if (*(uint32_t *)0x10000134ul == 0x3ul){ + return true; + } + } #endif - - return false; + + /* Apply by default for unknown devices until errata is confirmed fixed. */ + return true; +} + +static bool errata_108(void) +{ + if (*(uint32_t *)0x10000130ul == 0xEul){ + if (*(uint32_t *)0x10000134ul == 0x0ul){ + return true; + } + } + + /* Apply by default for unknown devices until errata is confirmed fixed. */ + return true; } static bool errata_136(void) { - #if !defined (DISABLE_WORKAROUND_136) - if ((*(uint32_t *)0x10000130ul == 0xEul) && (*(uint32_t *)0x10000134ul == 0x0ul)){ - return true; + if (*(uint32_t *)0x10000130ul == 0xEul){ + if (*(uint32_t *)0x10000134ul == 0x0ul){ + return true; + } } + + #ifdef DEVELOP_IN_NRF52840 + if (*(uint32_t *)0x10000130ul == 0x8ul){ + if (*(uint32_t *)0x10000134ul == 0x0ul){ + return true; + } + if (*(uint32_t *)0x10000134ul == 0x1ul){ + return true; + } + if (*(uint32_t *)0x10000134ul == 0x2ul){ + return true; + } + if (*(uint32_t *)0x10000134ul == 0x3ul){ + return true; + } + } #endif - - return false; + + /* Apply by default for unknown devices until errata is confirmed fixed. */ + return true; } +#ifdef DEVELOP_IN_NRF52840 + static bool errata_103(void) + { + if (*(uint32_t *)0x10000130ul == 0x8ul){ + if (*(uint32_t *)0x10000134ul == 0x0ul){ + return true; + } + } + + return false; + } + + + static bool errata_115(void) + { + if (*(uint32_t *)0x10000130ul == 0x8ul){ + if (*(uint32_t *)0x10000134ul == 0x0ul){ + return true; + } + } + + return false; + } +#endif /*lint --flb "Leave library region" */ diff --git a/mdk/system_nrf52840.c b/mdk/system_nrf52840.c index bd84aa20e..07a878c86 100644 --- a/mdk/system_nrf52840.c +++ b/mdk/system_nrf52840.c @@ -200,7 +200,8 @@ static bool errata_36(void) return true; } } - + + /* Apply by default for unknown devices until errata is confirmed fixed. */ return true; } @@ -221,7 +222,8 @@ static bool errata_66(void) return true; } } - + + /* Apply by default for unknown devices until errata is confirmed fixed. */ return true; } @@ -290,7 +292,8 @@ static bool errata_136(void) return true; } } - + + /* Apply by default for unknown devices until errata is confirmed fixed. */ return true; } diff --git a/mdk/system_nrf9160.c b/mdk/system_nrf9160.c index 70e35ecfc..1cdc35953 100644 --- a/mdk/system_nrf9160.c +++ b/mdk/system_nrf9160.c @@ -33,6 +33,17 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. #define __SYSTEM_CLOCK (64000000UL) /*!< nRF9160 Application core uses a fixed System Clock Frequency of 64MHz */ +#define TRACE_PIN_CNF_VALUE ( (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos) | \ + (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | \ + (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) | \ + (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | \ + (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) | \ + (GPIO_PIN_CNF_MCUSEL_TND << GPIO_PIN_CNF_MCUSEL_Pos)) +#define TRACE_TRACECLK_PIN (21) +#define TRACE_TRACEDATA0_PIN (22) +#define TRACE_TRACEDATA1_PIN (23) +#define TRACE_TRACEDATA2_PIN (24) +#define TRACE_TRACEDATA3_PIN (25) #if defined ( __CC_ARM ) uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK; @@ -49,6 +60,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. static bool errata_6(void); static bool errata_14(void); static bool errata_15(void); + static bool errata_20(void); #endif void SystemCoreClockUpdate(void) @@ -110,26 +122,63 @@ void SystemInit(void) } /* Workaround for Errata 6 "POWER: SLEEPENTER and SLEEPEXIT events asserted after pin reset" found at the Errata document - for your device located at https://www.nordicsemi.com/DocLib */ + for your device located at https://www.nordicsemi.com/DocLib */ if (errata_6()){ NRF_POWER_S->EVENTS_SLEEPENTER = (POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos); NRF_POWER_S->EVENTS_SLEEPEXIT = (POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos); } - + /* Workaround for Errata 14 "REGULATORS: LDO mode at startup" found at the Errata document - for your device located at https://www.nordicsemi.com/DocLib */ + for your device located at https://www.nordicsemi.com/DocLib */ if (errata_14()){ - *(uint32_t *)0x50004A38 = 0x01ul; + *((volatile uint32_t *)0x50004A38) = 0x01ul; NRF_REGULATORS_S->DCDCEN = REGULATORS_DCDCEN_DCDCEN_Enabled << REGULATORS_DCDCEN_DCDCEN_Pos; } /* Workaround for Errata 15 "REGULATORS: LDO mode at startup" found at the Errata document - for your device located at https://www.nordicsemi.com/DocLib */ + for your device located at https://www.nordicsemi.com/DocLib */ if (errata_15()){ - *(uint32_t *)0x50004A38 = 0x00ul; + *((volatile uint32_t *)0x50004A38) = 0x00ul; NRF_REGULATORS_S->DCDCEN = REGULATORS_DCDCEN_DCDCEN_Enabled << REGULATORS_DCDCEN_DCDCEN_Pos; } + /* Workaround for Errata 20 "RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document + for your device located at https://www.nordicsemi.com/DocLib */ + if (errata_20()){ + *((volatile uint32_t *)0x5003AEE4) = 0xC; + } + + /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product + Specification to see which one). */ + #if defined (ENABLE_SWO) + NRF_TAD_S->ENABLE = TAD_ENABLE_ENABLE_Msk; + NRF_TAD_S->CLOCKSTART = TAD_CLOCKSTART_START_Msk; + NRF_TAD_S->PSEL.TRACEDATA0 = TRACE_TRACEDATA0_PIN; + NRF_TAD_S->TRACEPORTSPEED = TAD_TRACEPORTSPEED_TRACEPORTSPEED_32MHz; + + NRF_P0_S->PIN_CNF[TRACE_TRACEDATA0_PIN] = TRACE_PIN_CNF_VALUE; + #endif + + /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product + Specification to see which ones). */ + #if defined (ENABLE_TRACE) + NRF_TAD_S->ENABLE = TAD_ENABLE_ENABLE_Msk; + NRF_TAD_S->CLOCKSTART = TAD_CLOCKSTART_START_Msk; + NRF_TAD_S->PSEL.TRACECLK = TRACE_TRACECLK_PIN; + NRF_TAD_S->PSEL.TRACEDATA0 = TRACE_TRACEDATA0_PIN; + NRF_TAD_S->PSEL.TRACEDATA1 = TRACE_TRACEDATA1_PIN; + NRF_TAD_S->PSEL.TRACEDATA2 = TRACE_TRACEDATA2_PIN; + NRF_TAD_S->PSEL.TRACEDATA3 = TRACE_TRACEDATA3_PIN; + NRF_TAD_S->TRACEPORTSPEED = TAD_TRACEPORTSPEED_TRACEPORTSPEED_32MHz; + + NRF_P0_S->PIN_CNF[TRACE_TRACECLK_PIN] = TRACE_PIN_CNF_VALUE; + NRF_P0_S->PIN_CNF[TRACE_TRACEDATA0_PIN] = TRACE_PIN_CNF_VALUE; + NRF_P0_S->PIN_CNF[TRACE_TRACEDATA1_PIN] = TRACE_PIN_CNF_VALUE; + NRF_P0_S->PIN_CNF[TRACE_TRACEDATA2_PIN] = TRACE_PIN_CNF_VALUE; + NRF_P0_S->PIN_CNF[TRACE_TRACEDATA3_PIN] = TRACE_PIN_CNF_VALUE; + + #endif + /* Allow Non-Secure code to run FPU instructions. * If only the secure code should control FPU power state these registers should be configured accordingly in the secure application code. */ SCB->NSACR |= (3UL << 10); @@ -205,6 +254,18 @@ void SystemInit(void) return false; } + + + bool errata_20() + { + if (*(uint32_t *)0x00FF0130 == 0x9ul){ + if (*(uint32_t *)0x00FF0134 == 0x02ul){ + return true; + } + } + + return false; + } #endif /*lint --flb "Leave library region" */ diff --git a/soc/nrfx_coredep.h b/soc/nrfx_coredep.h index 541646254..10e2d8433 100644 --- a/soc/nrfx_coredep.h +++ b/soc/nrfx_coredep.h @@ -45,6 +45,13 @@ #define NRFX_DELAY_CPU_FREQ_MHZ /** @brief Availability of Data Watchpoint and Trace (DWT) unit in the given SoC. */ #define NRFX_DELAY_DWT_PRESENT +/** + * @brief Number of cycles consumed by one iteration of the internal loop + * in the function @ref nrfx_coredep_delay_us. + * + * This value can be specified externally (for example, when the SoC is emulated). + */ +#define NRFX_COREDEP_DELAY_US_LOOP_CYCLES #elif defined(NRF51) #define NRFX_DELAY_CPU_FREQ_MHZ 16 @@ -73,6 +80,8 @@ * - For SoCs working at 64MHz: 0xFFFFFFFF/64 = 0x03FFFFFF (67108863 microseconds) * - For SoCs working at 16MHz: 0xFFFFFFFF/16 = 0x0FFFFFFF (268435455 microseconds) * + * @sa NRFX_COREDEP_DELAY_US_LOOP_CYCLES + * * @param time_us Number of microseconds to wait. */ __STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us); @@ -126,37 +135,35 @@ __STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us) return; } - #if defined(NRF51) - // The loop takes 4 cycles: 1 for SUBS, 3 for BHI. - static const uint16_t delay_bytecode[] = { - 0x3804, // SUBS r0, #4 - 0xd8fd, // BHI .-2 - 0x4770 // BX LR - }; - #elif defined(NRF52810_XXAA) || defined(NRF52811_XXAA) - // The loop takes 7 cycles: 1 for SUBS, 2 for BHI, 2 flash wait states for each instruction. - static const uint16_t delay_bytecode[] = { - 0x3807, // SUBS r0, #7 - 0xd8fd, // BHI .-2 - 0x4770 // BX LR - }; - #elif (defined(NRF52832_XXAA) || \ - defined (NRF52832_XXAB) || \ - defined(NRF52840_XXAA) || \ - defined(NRF9160_XXAA)) - // The loop takes 3 cycles: 1 for SUBS, 2 for BHI. - // Make sure that code is cached properly, so that no extra wait states appear. + // Allow overriding the number of cycles per loop iteration, in case it is + // needed to adjust this number externally (for example, when the SoC is + // emulated). + #ifndef NRFX_COREDEP_DELAY_US_LOOP_CYCLES + #if defined(NRF51) + // The loop takes 4 cycles: 1 for SUBS, 3 for BHI. + #define NRFX_COREDEP_DELAY_US_LOOP_CYCLES 4 + #elif defined(NRF52810_XXAA) || defined(NRF52811_XXAA) + // The loop takes 7 cycles: 1 for SUBS, 2 for BHI, 2 wait states + // for each instruction. + #define NRFX_COREDEP_DELAY_US_LOOP_CYCLES 7 + #else + // The loop takes 3 cycles: 1 for SUBS, 2 for BHI. + #define NRFX_COREDEP_DELAY_US_LOOP_CYCLES 3 + #endif + #endif // NRFX_COREDEP_DELAY_US_LOOP_CYCLES + // Align the machine code, so that it can be cached properly and no extra + // wait states appear. __ALIGN(16) - static const uint16_t delay_bytecode[] = { - 0x3803, // SUBS r0, #3 + static const uint16_t delay_machine_code[] = { + 0x3800 + NRFX_COREDEP_DELAY_US_LOOP_CYCLES, // SUBS r0, #loop_cycles 0xd8fd, // BHI .-2 0x4770 // BX LR - }; - #endif + }; typedef void (* delay_func_t)(uint32_t); - // Set LSB to 1 to execute code in Thumb mode. - const delay_func_t delay_cycles = (delay_func_t)((((uint32_t)delay_bytecode) | 1)); + const delay_func_t delay_cycles = + // Set LSB to 1 to execute the code in the Thumb mode. + (delay_func_t)((((uint32_t)delay_machine_code) | 1)); uint32_t cycles = time_us * NRFX_DELAY_CPU_FREQ_MHZ; delay_cycles(cycles); }