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<!DOCTYPE html>
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<meta name="description" content="A Fast Forward Error Correction Toolbox (AFF3CT)">
<meta name="author" content="Adrien CASSAGNE">
<title>AFF3CT - A Fast Forward Error Correction Toolbox</title>
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<li class="nav-item"><a class="nav-link" href="comparator.html"><i class="fas fa-chart-bar" aria-hidden="true"> </i>BER/FER Comparator</a></li>
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<a class="nav-link dropdown-toggle" href="#" id="dropdown_hof" data-toggle="dropdown" aria-haspopup="true" aria-expanded="false"><i class="fa fa-list" aria-hidden="true"> </i>Software Decoders Hall of Fame </a>
<div class="dropdown-menu dropdown-menu-right" aria-labelledby="dropdown_hof">
<h6 class="dropdown-header">Synoptic tables</h6>
<a class="dropdown-item active" href="hof_turbo.html">Turbo Codes</a>
<a class="dropdown-item" href="hof_ldpc.html">LDPC Codes</a>
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<div class="container marketing">
<h1 class="display-4">FEC Software Decoders Hall of Fame</h1>
<p class="lead">This page presents <b>a Channel Coding Software Decoders "Hall of Fame"</b>. It allows to see at a glance what has been achieved, what can be expected from today software decoders, and easily compare their respective characteristics. For now, three wide code families are considered: <b>the Turbo codes (LTE, LTE-Advanced, CCSDS, etc.), the Low-Density Parity-Check (LDPC) codes (5G, Wi-Fi, WiMAX, CCSDS, WRAN, DVB-S2, etc.), and the more recently introduced Polar codes (5G)</b>.</p>
<p class="lead">All the presented results, collected from the state-of-the-art research papers published in the field, consider a <b>BPSK (Bit Phase-Shift Keying) modulation/demodulation</b> and an <b>AWGN (Additive White Gaussian Noise) channel</b>.</p>
<p class="lead"><b>This Hall of Fame strives to present results as fairly as possible</b>: for example, early termination criteria are not taken into consideration while computing throughput, in order to compare raw performances using a consistent method. It remains possible, however, for typos/glitches/mistakes to have inadvertantly made it to the scoreboard. In that eventuality, do not hesitate to contact us. If you would like to have your decoder listed as well in the Hall of Fame: <b>please send us the corresponding research paper references, and we will be delighted to add them</b>.</p>
<p class="lead">In <span class="bg-info text-white">blue</span>, the results simulated or reproducible with <a href="index.html">AFF3CT</a>: our Open-source communication chain dedicated to the Forward Error Correction (FEC) simulations.</p>
<p class="lead text-right">
<i>Last update: 2021-05-17.</i>
</p>
<hr>
<p>Do you like the FEC Software Decoders Hall of Fame? Is it useful in your research works? If yes, you can thank us by citing the following journal article: <strong>A. Cassagne et al., “<a href="https://doi.org/10.1016/j.softx.2019.100345" target="_blank" onclick="return trackOutboundLink('https://doi.org/10.1016/j.softx.2019.100345');">AFF3CT: A Fast Forward Error Correction Toolbox!</a>,“ <i>SoftwareX</i>, 2019</strong>. <a title="PDF Article" href="https://hal.inria.fr/hal-02358306/file/Cassagne2019a%20-%20AFF3CT%3A%20A%20Fast%20Forward%20Error%20Correction%20Toolbox.pdf" target="_blank" onclick="return trackOutboundLink('https://hal.inria.fr/hal-02358306/file/Cassagne2019a%20-%20AFF3CT%3A%20A%20Fast%20Forward%20Error%20Correction%20Toolbox.pdf');"><i class="fas fa-file-pdf" aria-hidden="true"></i></a> <a title="Bibtex Entry" href="resources/bibtex/Cassagne2019a%20-%20AFF3CT:%20A%20Fast%20Forward%20Error%20Correction%20Toolbox.bib" target="_blank" onclick="return trackOutboundLink('resources/bibtex/Cassagne2019a%20-%20AFF3CT:%20A%20Fast%20Forward%20Error%20Correction%20Toolbox.bib');"><i class="fas fa-file-alt" aria-hidden="true"></i></a></p>
</div>
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<div class="container marketing">
<ul class="nav nav-tabs">
<li class="nav-item"><a class="nav-link active" href="hof_turbo.html">Turbo</a></li>
<li class="nav-item"><a class="nav-link" href="hof_ldpc.html">LDPC</a></li>
<li class="nav-item"><a class="nav-link" href="hof_polar.html">Polar</a></li>
</ul>
<div class="mb-4"></div>
<div id="turbo-codes" class="codes">
<div class="bs-example" data-example-id="panel-without-body-with-table">
<p class="lead"><strong>Maximum A Posteriori (MAP) - <i>8-state trellis</i></strong></p>
<div class="table-responsive">
<table class="table sortable table-hover table-striped">
<thead>
<tr>
<th>Work</th>
<th id="year1">Year</th>
<th class="vl">Platform</th>
<th>Implem.</th>
<th><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Precision in bits">Pre.</span></th>
<th><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Inter frame level: number of frames computed in parallel">Inter</span></th>
<th><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Number of information bits in the frame"><math><mi>K</mi></math></span></th>
<th>
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Code rate:
<math>
<mi>R</mi>
<mo>=</mo>
<mfrac>
<mi>K</mi>
<mi>N</mi>
</mfrac>
</math>">
<math><mi>R</mi></math>
</span>
</th>
<th><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Number of iteration in the decoding process"><math><mi>i</mi></math></span></th>
<th class="vl"><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Latency in micro seconds: time to decode one frame"><math><mi>Lat.</mi></math></span></th>
<th>
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Information throughput in Mbps:<br/>
<math>
<mi>Thr.</mi>
<mo>=</mo>
<mfrac>
<mrow>
<mi>K</mi>
<mo>×</mo>
<mi>Inter</mi>
</mrow>
<mi>Lat.</mi>
</mfrac>
</math>">
<math><mi>Thr.</mi></math>
</span>
</th>
<th class="vl" id="nthr1">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Normalized throughput in Mbps:<br/>
<math>
<mi>NThr.</mi>
<mo>=</mo>
<mfrac>
<mrow>
<mrow><mi>Thr.</mi></mrow>
<mo>×</mo>
<mrow><mi>i</mi></mrow>
</mrow>
<mrow>
<mi>6</mi>
</mrow>
</mfrac>
</math>">
<math><mi>NThr.</mi></math>
</span>
</th>
<th>
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Throughput under Normalized Decoding Cost:<br/>
<math>
<mi>TNDC</mi>
<mo>=</mo>
<mfrac>
<mrow><mi>NThr.</mi></mrow>
<mrow>
<mrow><mi>Cores</mi></mrow>
<mo>×</mo>
<mrow><mi>Freq.</mi></mrow>
<mo>×</mo>
<mrow><mi>SIMD</mi></mrow>
</mrow>
</mfrac>
</math>">
<math><mi>TNDC</mi></math>
</span>
</th>
<th>
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Energy-per-bit (in nano Joules): <br />
<math>
<mrow><msub><mi>E</mi><mi>d</mi></msub></mrow>
<mo>=</mo>
<mfrac>
<mrow>
<mi>TDP</mi>
</mrow>
<mrow>
<mi>NThr.</mi>
</mrow>
</mfrac>
<mo>×</mo>
<msup>
<mn>10</mn>
<mn>3</mn>
</msup>
</math>">
<math><msub><mi>E</mi><mi>d</mi></msub></math>
</span>
</th>
</tr>
</thead>
<tbody>
<tr>
<td><a class="tt" href="#ref1" data-toggle="tooltip" data-placement="top" data-html="true" title="M. Wu, Y. Sun, and J. R. Cavallaro, <b>Implementation of a 3GPP LTE Turbo Decoder Accelerator on GPU</b>, <i>in Proceedings of the IEEE International Workshop on Signal Processing Systems (SiPS)</i>, October 2010.">[1]</a></td>
<td>2010</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: GPU<br />
<u>Full name</u>: Tesla C1060<br />
<u>Vendor</u>: Nvidia <br />
<u>Architecture</u>: Tesla<br />
<u>Frequency</u>: 1.30 GHz<br />
<u>SMX/Cores</u>: 15<br />
<u>SIMD type</u>: SIMT<br />
<u>SIMD length</u>: 16<br />
<u>TDP</u> : 200 Watts">
Tesla C1060
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="max-log-MAP algorithm (based on the BCJR)">ML-MAP</span></td>
<td>32</td>
<td>100</td>
<td>6144</td>
<td>1/3</td>
<td>5</td>
<td class="vl">76800</td>
<td>8.0</td>
<td class="vl">6.7</td>
<td>0.021</td>
<td>29851</td>
</tr>
<tr>
<td><a class="tt" href="#ref2" data-toggle="tooltip" data-placement="top" data-html="true" title="M. Wu, Y. Sun, G. Wang, and J. R. Cavallaro, <b>Implementation of a High Throughput 3GPP Turbo Decoder on GPU</b>, <i>Springer Journal of Signal Processing Systems (JSPS)</i>, September 2011.">[2]</a></td>
<td>2011</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: GPU<br />
<u>Full name</u>: GeForce GTX 470<br />
<u>Vendor</u>: Nvidia <br />
<u>Architecture</u>: Fermi<br />
<u>Frequency</u>: 1.22 GHz<br />
<u>SMX/Cores</u>: 14<br />
<u>SIMD type</u>: SIMT<br />
<u>SIMD length</u>: 32<br />
<u>TDP</u> : 215 Watts">
GTX 470
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="max-log-MAP algorithm (based on the BCJR)">ML-MAP</span></td>
<td>32</td>
<td>100</td>
<td>6144</td>
<td>1/3</td>
<td>5</td>
<td class="vl">20827</td>
<td>29.5</td>
<td class="vl">24.6</td>
<td>0.045</td>
<td>8740</td>
</tr>
<tr>
<td><a class="tt" href="#ref3" data-toggle="tooltip" data-placement="top" data-html="true" title="L. Huang and Y. Luo and H. Wang and F. Yang and Z. Shi and D. Gu, <b>A High Speed Turbo Decoder Implementation for CPU-Based SDR System</b>, <i>in Proceedings of the IEEE International Conference on Communication Technology and Applications (ICCTA)</i>, October 2011.">[3]</a></td>
<td>2011</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: CPU<br />
<u>Full name</u>: Core i7-960<br />
<u>Vendor</u>: Intel<br />
<u>Architecture</u>: Nehalem<br />
<u>Frequency</u>: 3.20 GHz<br />
<u>SMX/Cores</u>: 4 (only 1 used)<br />
<u>SIMD type</u>: SSE4.2 (128-bit)<br />
<u>SIMD length</u>: 8 (16-bit/elmt)<br />
<u>TDP</u> : 130 Watts">
i7-960
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="max-log-MAP algorithm (based on the BCJR)">ML-MAP</span></td>
<td>16</td>
<td>1</td>
<td>1008</td>
<td>1/3</td>
<td>8</td>
<td class="vl">138</td>
<td>7.3</td>
<td class="vl">9.7</td>
<td>0.380</td>
<td>13402</td>
</tr>
<tr>
<td><a class="tt" href="#ref4" data-toggle="tooltip" data-placement="top" data-html="true" title="D. Yoge and N. Chandrachoodan, <b>GPU Implementation of a Programmable Turbo Decoder for Software Defined Radio Applications</b>, <i>in Proceedings of the IEEE International Conference on VLSI Design (VLSID)</i>, January 2012.">[4]</a></td>
<td>2012</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: GPU<br />
<u>Full name</u>: GeForce 9800 GX2<br />
<u>Vendor</u>: Nvidia <br />
<u>Architecture</u>: Tesla<br />
<u>Frequency</u>: 1.50 GHz<br />
<u>SMX/Cores</u>: 16<br />
<u>SIMD type</u>: SIMT<br />
<u>SIMD length</u>: 16<br />
<u>TDP</u> : 197 Watts">
9800 GX2
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="max-log-MAP algorithm (based on the BCJR)">ML-MAP</span></td>
<td>32</td>
<td>1</td>
<td>6144</td>
<td>1/3</td>
<td>5</td>
<td class="vl">3072</td>
<td>2.0</td>
<td class="vl">1.7</td>
<td>0.0043</td>
<td>115882</td>
</tr>
<tr>
<td><a class="tt" href="#ref5" data-toggle="tooltip" data-placement="top" data-html="true" title="S. Chinnici and P. Spallaccini, <b>Fast Simulation of Turbo Codes on GPUs</b>, <i>in Proceedings of the IEEE International Symposium on Turbo Codes and Iterative Information Processing (ISTC)</i>, August 2012.">[5]</a></td>
<td>2012</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: GPU<br />
<u>Full name</u>: Tesla C2050<br />
<u>Vendor</u>: Nvidia <br />
<u>Architecture</u>: Fermi<br />
<u>Frequency</u>: 1.15 GHz<br />
<u>SMX/Cores</u>: 14<br />
<u>SIMD type</u>: SIMT<br />
<u>SIMD length</u>: 32<br />
<u>TDP</u> : 247 Watts">
Tesla C2050
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="log-MAP algorithm (based on the BCJR)">L-MAP</span></td>
<td>32</td>
<td>32</td>
<td>11918</td>
<td>1/3</td>
<td>5</td>
<td class="vl">108965</td>
<td>3.5</td>
<td class="vl">2.9</td>
<td>0.0057</td>
<td>85172</td>
</tr>
<tr>
<td><a class="tt" href="#ref6" data-toggle="tooltip" data-placement="top" data-html="true" title="S. Zhang, R. Qian, T. Peng, R. Duan, and K. Chen, <b>High Throughput Turbo Decoder Design for GPP Platform</b>, <i>in Proceedings of the IEEE International Conference on Communications and Networking in China (CHINACOM)</i>, August 2012.">[6]</a></td>
<td>2012</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: CPU<br />
<u>Full name</u>: Xeon X5670<br />
<u>Vendor</u>: Intel<br />
<u>Architecture</u>: Westmere<br />
<u>Frequency</u>: 2.93 GHz<br />
<u>SMX/Cores</u>: 6<br />
<u>SIMD type</u>: SSE4.2 (128-bit)<br />
<u>SIMD length</u>: 16 (8-bit/elmt)<br />
<u>TDP</u> : 95 Watts">
X5670
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Enhanced max-log-MAP algorithm (based on the BCJR)">EML-MAP</span></td>
<td>8</td>
<td>6</td>
<td>5824</td>
<td>1/3</td>
<td>3</td>
<td class="vl">157</td>
<td>222.6</td>
<td class="vl">111.3</td>
<td>0.396</td>
<td>854</td>
</tr>
<tr>
<td><a class="tt" href="#ref7" data-toggle="tooltip" data-placement="top" data-html="true" title="J. Xianjun, C. Canfeng, P. Jaaskelainen, V. Guzma, and H. Berg, <b>A 122Mb/s Turbo Decoder using a Mid-Range GPU</b>, <i>in Proceedings of the IEEE International Wireless Communications and Mobile Computing Conference (IWCMC)</i>, July 2013.">[7]</a></td>
<td>2013</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: GPU<br />
<u>Full name</u>: GeForce GTX 480<br />
<u>Vendor</u>: Nvidia <br />
<u>Architecture</u>: Fermi<br />
<u>Frequency</u>: 1.40 GHz<br />
<u>SMX/Cores</u>: 15<br />
<u>SIMD type</u>: SIMT<br />
<u>SIMD length</u>: 32<br />
<u>TDP</u> : 250 Watts">
GTX 480
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Enhanced max-log-MAP algorithm (based on the BCJR)">EML-MAP</span></td>
<td>32</td>
<td>1</td>
<td>6144</td>
<td>1/3</td>
<td>6</td>
<td class="vl"><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="It is unclear if the CPU/GPU data transfer times have been taken into account.">50</span></td>
<td>122.8</td>
<td class="vl">122.8</td>
<td>0.183</td>
<td>2036</td>
</tr>
<tr>
<td><a class="tt" href="#ref8" data-toggle="tooltip" data-placement="top" data-html="true" title="X. Chen, J. Zhu, Z. Wen, Y. Wang, and H. Yang, <b>BER Guaranteed Optimization and Implementation of Parallel Turbo Decoding on GPU</b>, <i>in Proceedings of the IEEE International Conference on Communications and Networking in China (CHINACOM)</i>, August 2013.">[8]</a></td>
<td>2013</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: GPU<br />
<u>Full name</u>: GeForce GTX 580<br />
<u>Vendor</u>: Nvidia <br />
<u>Architecture</u>: Fermi<br />
<u>Frequency</u>: 1.54 GHz<br />
<u>SMX/Cores</u>: 16<br />
<u>SIMD type</u>: SIMT<br />
<u>SIMD length</u>: 32<br />
<u>TDP</u> : 244 Watts">
GTX 580
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="max-log-MAP algorithm (based on the BCJR)">ML-MAP</span></td>
<td>32</td>
<td>1</td>
<td>6144</td>
<td>1/3</td>
<td>6</td>
<td class="vl">1660</td>
<td>3.7</td>
<td class="vl">3.7</td>
<td>0.0047</td>
<td>63946</td>
</tr>
<tr>
<td><a class="tt" href="#ref9" data-toggle="tooltip" data-placement="top" data-html="true" title="C. Liu, Z. Bie, C. Chen, and X. Jiao, <b>A Parallel LTE Turbo Decoder on GPU</b>, <i>in Proceedings of the IEEE International Conference on Communication Technology (ICCT)</i>, November 2013.">[9]</a></td>
<td>2013</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: GPU<br />
<u>Full name</u>: GeForce GTX 550 Ti<br />
<u>Vendor</u>: Nvidia <br />
<u>Architecture</u>: Fermi<br />
<u>Frequency</u>: 1.80 GHz<br />
<u>SMX/Cores</u>: 6<br />
<u>SIMD type</u>: SIMT<br />
<u>SIMD length</u>: 32<br />
<u>TDP</u> : 116 Watts">
GTX 550 Ti
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Enhanced max-log-MAP algorithm (based on the BCJR)">EML-MAP</span></td>
<td>32</td>
<td>1</td>
<td>6144</td>
<td>1/3</td>
<td>6</td>
<td class="vl"><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="It is unclear if the CPU/GPU data transfer times have been taken into account.">72</span></td>
<td>85.3</td>
<td class="vl">85.3</td>
<td>0.247</td>
<td>1360</td>
</tr>
<tr>
<td><a class="tt" href="#ref10" data-toggle="tooltip" data-placement="top" data-html="true" title="M. Wu, G. Wang, B. Yin, C. Studer, and J. R. Cavallaro, <b>HSPA+/LTE-A Turbo Decoder on GPU and Multicore CPU</b>, <i>in Proceedings of the IEEE Asilomar Conference on Signals, Systems, and Computers (ACSSC)</i>, November 2013.">[10]</a></td>
<td>2013</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: GPU<br />
<u>Full name</u>: GeForce GTX 680<br />
<u>Vendor</u>: Nvidia <br />
<u>Architecture</u>: Kepler<br />
<u>Frequency</u>: 1.01 GHz<br />
<u>SMX/Cores</u>: 8<br />
<u>SIMD type</u>: SIMT<br />
<u>SIMD length</u>: 192<br />
<u>TDP</u> : 195 Watts">
GTX 680
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Enhanced max-log-MAP algorithm (based on the BCJR)">EML-MAP</span></td>
<td>32</td>
<td>16</td>
<td>6144</td>
<td>1/3</td>
<td>6</td>
<td class="vl">2657</td>
<td>37.0</td>
<td class="vl">37.0</td>
<td>0.024</td>
<td>5270</td>
</tr>
<tr>
<td><a class="tt" href="#ref10" data-toggle="tooltip" data-placement="top" data-html="true" title="M. Wu, G. Wang, B. Yin, C. Studer, and J. R. Cavallaro, <b>HSPA+/LTE-A Turbo Decoder on GPU and Multicore CPU</b>, <i>in Proceedings of the IEEE Asilomar Conference on Signals, Systems, and Computers (ACSSC)</i>, November 2013.">[10]</a></td>
<td>2013</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: CPU<br />
<u>Full name</u>: Core i7-3770K<br />
<u>Vendor</u>: Intel<br />
<u>Architecture</u>: Ivy Bridge<br />
<u>Frequency</u>: 3.5 GHz<br />
<u>SMX/Cores</u>: 4<br />
<u>SIMD type</u>: SSE4.2 (128-bit)<br />
<u>SIMD length</u>: 8 (16-bit/elmt)<br />
<u>TDP</u> : 77 Watts">
i7-3770K
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Enhanced max-log-MAP algorithm (based on the BCJR)">EML-MAP</span></td>
<td>16</td>
<td>4</td>
<td>6144</td>
<td>1/3</td>
<td>6</td>
<td class="vl">323</td>
<td>76.2</td>
<td class="vl">76.2</td>
<td>0.680</td>
<td>1011</td>
</tr>
<tr>
<td><a class="tt" href="#ref11" data-toggle="tooltip" data-placement="top" data-html="true" title="Y. Zhang and Z. Xing and L. Yuan and C. Liu and Q. Wang, <b>The Acceleration of Turbo Decoder on the Newest GPGPU of Kepler Architecture</b>, <i>in Proceedings of the IEEE International Symposium on Communications and Information Technologies (ISCIT)</i>, September 2014.">[11]</a></td>
<td>2014</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: GPU<br />
<u>Full name</u>: Tesla K20c<br />
<u>Vendor</u>: Nvidia <br />
<u>Architecture</u>: Kepler<br />
<u>Frequency</u>: 0.71 GHz<br />
<u>SMX/Cores</u>: 13<br />
<u>SIMD type</u>: SIMT<br />
<u>SIMD length</u>: 192<br />
<u>TDP</u> : 225 Watts">
Tesla K20c
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="max-log-MAP algorithm (based on the BCJR)">ML-MAP</span></td>
<td>32</td>
<td>1</td>
<td>6144</td>
<td>1/3</td>
<td>5</td>
<td class="vl">1097</td>
<td>5.6</td>
<td class="vl">4.7</td>
<td>0.0026</td>
<td>47872</td>
</tr>
<tr>
<td><a class="tt" href="#ref12" data-toggle="tooltip" data-placement="top" data-html="true" title="R. Li, Y. Dou, J. Xu, X. Niu, and S. Ni, <b>An Efficient Parallel SOVA-Based Turbo Decoder for Software Defined Radio on GPU</b>, <i>IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences</i>, 2014.">[12]</a></td>
<td>2014</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: GPU<br />
<u>Full name</u>: GeForce GTX 580<br />
<u>Vendor</u>: Nvidia <br />
<u>Architecture</u>: Fermi<br />
<u>Frequency</u>: 1.54 GHz<br />
<u>SMX/Cores</u>: 16<br />
<u>SIMD type</u>: SIMT<br />
<u>SIMD length</u>: 32<br />
<u>TDP</u> : 244 Watts">
GTX 580
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="BER optimized Soft Output Viterbi Algorithm (BR-SOVA) algorithm">BR-SOVA</span></td>
<td>8</td>
<td>4</td>
<td>6144</td>
<td>1/3</td>
<td>5</td>
<td class="vl"><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="It is unclear if the CPU/GPU data transfer times have been taken into account.">192</span></td>
<td>127.8</td>
<td class="vl">106.5</td>
<td>0.135</td>
<td>2291</td>
</tr>
<tr>
<td><a class="tt" href="#ref13" data-toggle="tooltip" data-placement="top" data-html="true" title="A. Li, R. G. Maunder, B. M. Al-Hashimi, and L. Hanzo, <b>Implementation of a Fully-Parallel Turbo Decoder on a General-Purpose Graphics Processing Unit</b>, <i>IEEE Access, May 2016.</i>, June 2016.">[13]</a></td>
<td>2016</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: GPU<br />
<u>Full name</u>: GeForce GTX 680<br />
<u>Vendor</u>: Nvidia <br />
<u>Architecture</u>: Kepler<br />
<u>Frequency</u>: 1.01 GHz<br />
<u>SMX/Cores</u>: 8<br />
<u>SIMD type</u>: SIMT<br />
<u>SIMD length</u>: 192<br />
<u>TDP</u> : 195 Watts">
GTX 680
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Enhanced max-log-MAP algorithm (based on the BCJR)">EML-MAP</span></td>
<td>32</td>
<td>1</td>
<td>6144</td>
<td>1/3</td>
<td>7</td>
<td class="vl">817</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Following the formula, the throughput should be lower but the authors performed a specific data transfers overlapping with CUDA streams allowing to reach higher throughput.">8.2</span></td>
<td class="vl">9.6</td>
<td>0.0062</td>
<td>20313</td>
</tr>
<tr class="table-info">
<td class="vl"><a class="tt" href="#ref14" data-toggle="tooltip" data-placement="top" data-html="true" title="A. Cassagne, T. Tonnellier, C. Leroux, B. Le Gal, O. Aumage, and D. Barthou, <b>Beyond Gbps Turbo Decoder on Multi-Core CPUs</b>, <i>in Proceedings of the IEEE International Symposium on Turbo Codes and Iterative Information Processing (ISTC)</i>, September 2016.">[14]</a></td>
<td>2016</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: CPU<br />
<u>Full name</u>: 2 x Xeon E5-2680v3<br />
<u>Vendor</u>: Intel<br />
<u>Architecture</u>: Haswell<br />
<u>Frequency</u>: 2.5 GHz<br />
<u>SMX/Cores</u>: 24<br />
<u>SIMD type</u>: SSE4.2 (128-bit)<br />
<u>SIMD length</u>: 8 (16-bit/elmt)<br />
<u>TDP</u> : 240 Watts">
2xE5-2680v3
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Enhanced max-log-MAP algorithm (based on the BCJR)">EML-MAP</span></td>
<td>16</td>
<td>192</td>
<td>6144</td>
<td>1/3</td>
<td>6</td>
<td class="vl">2657</td>
<td>443.7</td>
<td class="vl">443.7</td>
<td>0.924</td>
<td>541</td>
</tr>
<tr class="table-info">
<td class="vl"><a class="tt" href="#ref14" data-toggle="tooltip" data-placement="top" data-html="true" title="A. Cassagne, T. Tonnellier, C. Leroux, B. Le Gal, O. Aumage, and D. Barthou, <b>Beyond Gbps Turbo Decoder on Multi-Core CPUs</b>, <i>in Proceedings of the IEEE International Symposium on Turbo Codes and Iterative Information Processing (ISTC)</i>, September 2016.">[14]</a></td>
<td>2016</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: CPU<br />
<u>Full name</u>: 2 x Xeon E5-2680v3<br />
<u>Vendor</u>: Intel<br />
<u>Architecture</u>: Haswell<br />
<u>Frequency</u>: 2.5 GHz<br />
<u>SMX/Cores</u>: 24<br />
<u>SIMD type</u>: SSE4.2 (128-bit)<br />
<u>SIMD length</u>: 16 (8-bit/elmt)<br />
<u>TDP</u> : 240 Watts">
2xE5-2680v3
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Enhanced max-log-MAP algorithm (based on the BCJR)">EML-MAP</span></td>
<td>8</td>
<td>384</td>
<td>6144</td>
<td>1/3</td>
<td>6</td>
<td class="vl">3293</td>
<td>716.4</td>
<td class="vl">716.4</td>
<td>0.746</td>
<td>335</td>
</tr>
<tr>
<td class="vl"><a class="tt" href="#ref15" data-toggle="tooltip" data-placement="top" data-html="true" title="B. Le Gal and C. Jégo, <b>Low-latency and High-throughput Software Turbo Decoders on Multi-core Architectures</b>, <i>Springer Annals of Telecommunications</i>, August 2019.">[15]</a></td>
<td>2019</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: CPU<br />
<u>Full name</u>: 2 x Xeon E5-2680v3<br />
<u>Vendor</u>: Intel<br />
<u>Architecture</u>: Haswell<br />
<u>Frequency</u>: 2.5 GHz<br />
<u>SMX/Cores</u>: 24<br />
<u>SIMD type</u>: AVX2 (256-bit)<br />
<u>SIMD length</u>: 32 (8-bit/elmt)<br />
<u>TDP</u> : 240 Watts">
2xE5-2680v3
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Enhanced max-log-MAP algorithm (based on the BCJR) + implementation specialized for the regular structure of the LTE interleaver">EML-MAP</span></td>
<td>8</td>
<td>24</td>
<td>6144</td>
<td>1/3</td>
<td>6</td>
<td class="vl">84</td>
<td>1735.0</td>
<td class="vl">1735.0</td>
<td>0.904</td>
<td>138</td>
</tr>
</tbody>
</table>
</div>
</div>
<div class="mb-4"></div>
<div class="bs-example" data-example-id="panel-without-body-with-table">
<p class="lead"><strong>Fully-Parallel Turbo Decoder (FPTD) - <i>8-state trellis</i></strong></p>
<div class="table-responsive">
<table class="table sortable table-hover table-striped">
<thead>
<tr>
<th>Work</th>
<th id="year2">Year</th>
<th class="vl">Platform</th>
<th>Implem.</th>
<th><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Precision in bits">Pre.</span></th>
<th><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Inter frame level: number of frames computed in parallel">Inter</span></th>
<th><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Number of information bits in the frame"><math><mi>K</mi></math></span></th>
<th>
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Code rate:
<math>
<mi>R</mi>
<mo>=</mo>
<mfrac>
<mi>K</mi>
<mi>N</mi>
</mfrac>
</math>">
<math><mi>R</mi></math>
</span>
</th>
<th><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Number of iteration in the decoding process"><math><mi>i</mi></math></span></th>
<th class="vl"><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Latency in micro seconds: time to decode one frame"><math><mi>Lat.</mi></math></span></th>
<th>
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Information throughput in Mbps:<br/>
<math>
<mi>Thr.</mi>
<mo>=</mo>
<mfrac>
<mrow>
<mi>K</mi>
<mo>×</mo>
<mi>Inter</mi>
</mrow>
<mi>Lat.</mi>
</mfrac>
</math>">
<math><mi>Thr.</mi></math>
</span>
</th>
<th class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Energy-per-bit (in nano Joules): <br />
<math>
<mrow><msub><mi>E</mi><mi>d</mi></msub></mrow>
<mo>=</mo>
<mfrac>
<mrow>
<mi>TDP</mi>
</mrow>
<mrow>
<mi>Thr.</mi>
</mrow>
</mfrac>
<mo>×</mo>
<msup>
<mn>10</mn>
<mn>3</mn>
</msup>
</math>">
<math><msub><mi>E</mi><mi>d</mi></msub></math>
</span>
</th>
</tr>
</thead>
<tbody>
<tr>
<td><a class="tt" href="#ref13" data-toggle="tooltip" data-placement="top" data-html="true" title="A. Li, R. G. Maunder, B. M. Al-Hashimi, and L. Hanzo, <b>Implementation of a Fully-Parallel Turbo Decoder on a General-Purpose Graphics Processing Unit</b>, <i>IEEE Access, May 2016.</i>, June 2016.">[13]</a></td>
<td>2016</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: GPU<br />
<u>Full name</u>: GeForce GTX 680<br />
<u>Vendor</u>: Nvidia <br />
<u>Architecture</u>: Kepler<br />
<u>Frequency</u>: 1.01 GHz<br />
<u>SMX/Cores</u>: 8<br />
<u>SIMD type</u>: SIMT<br />
<u>SIMD length</u>: 192<br />
<u>TDP</u> : 195 Watts">
GTX 680
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Fully-Parallel Turbo Decoder algorithm">FPTD</span></td>
<td>32</td>
<td>1</td>
<td>6144</td>
<td>1/3</td>
<td>36</td>
<td class="vl">403</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Following the formula, the throughput should be lower but the authors performed a specific data transfers overlapping with CUDA streams allowing to reach higher throughput.">18.7</span></td>
<td class="vl">10428</td>
</tr>
</tbody>
</table>
</div>
</div>
<h2>References</h2>
<ol>
<li id="ref1" >M. Wu, Y. Sun, and J. R. Cavallaro, “<a target="_blank" href="https://doi.org/10.1109/SIPS.2010.5624788" onclick="return trackOutboundLink('https://doi.org/10.1109/SIPS.2010.5624788' );">Implementation of a 3GPP LTE Turbo Decoder Accelerator on GPU</a>,” <i>in Proceedings of the IEEE International Workshop on Signal Processing Systems (SiPS)</i>, October 2010.</li>
<li id="ref2" >M. Wu, Y. Sun, G. Wang, and J. R. Cavallaro, “<a target="_blank" href="https://doi.org/10.1007/s11265-011-0617-7" onclick="return trackOutboundLink('https://doi.org/10.1007/s11265-011-0617-7' );">Implementation of a High Throughput 3GPP Turbo Decoder on GPU</a>,” <i>Springer Journal of Signal Processing Systems (JSPS)</i>, September 2011.</li>
<li id="ref3" >L. Huang and Y. Luo and H. Wang and F. Yang and Z. Shi and D. Gu, “<a target="_blank" href="https://doi.org/10.1049/cp.2011.0622" onclick="return trackOutboundLink('https://doi.org/10.1049/cp.2011.0622' );">A High Speed Turbo Decoder Implementation for CPU-Based SDR System</a>,” <i>in Proceedings of the IEEE International Conference on Communication Technology and Applications (ICCTA)</i>, October 2011.</li>
<li id="ref4" >D. Yoge and N. Chandrachoodan, “<a target="_blank" href="https://doi.org/10.1109/VLSID.2012.62" onclick="return trackOutboundLink('https://doi.org/10.1109/VLSID.2012.62' );">GPU Implementation of a Programmable Turbo Decoder for Software Defined Radio Applications</a>,” <i>in Proceedings of the IEEE International Conference on VLSI Design (VLSID)</i>, January 2012.</li>
<li id="ref5" >S. Chinnici and P. Spallaccini, “<a target="_blank" href="https://doi.org/10.1109/ISTC.2012.6325199" onclick="return trackOutboundLink('https://doi.org/10.1109/ISTC.2012.6325199' );">Fast Simulation of Turbo Codes on GPUs</a>,” <i>in Proceedings of the IEEE International Symposium on Turbo Codes and Iterative Information Processing (ISTC)</i>, August 2012.</li>
<li id="ref6" >S. Zhang, R. Qian, T. Peng, R. Duan, and K. Chen, “<a target="_blank" href="https://doi.org/10.1109/ChinaCom.2012.6417597" onclick="return trackOutboundLink('https://doi.org/10.1109/ChinaCom.2012.6417597');">High Throughput Turbo Decoder Design for GPP Platform</a>,” <i>in Proceedings of the IEEE International Conference on Communications and Networking in China (CHINACOM)</i>, August 2012.</li>
<li id="ref7" >J. Xianjun, C. Canfeng, P. Jaaskelainen, V. Guzma, and H. Berg, “<a target="_blank" href="https://doi.org/10.1109/IWCMC.2013.6583709" onclick="return trackOutboundLink('https://doi.org/10.1109/IWCMC.2013.6583709' );">A 122Mb/s Turbo Decoder using a Mid-Range GPU</a>,” <i>in Proceedings of the IEEE International Wireless Communications and Mobile Computing Conference (IWCMC)</i>, July 2013.</li>
<li id="ref8" >X. Chen, J. Zhu, Z. Wen, Y. Wang, and H. Yang, “<a target="_blank" href="https://doi.org/10.1109/ChinaCom.2013.6694588" onclick="return trackOutboundLink('https://doi.org/10.1109/ChinaCom.2013.6694588');">BER Guaranteed Optimization and Implementation of Parallel Turbo Decoding on GPU</a>,” <i>in Proceedings of the IEEE International Conference on Communications and Networking in China (CHINACOM)</i>, August 2013.</li>
<li id="ref9" >C. Liu, Z. Bie, C. Chen, and X. Jiao, “<a target="_blank" href="https://doi.org/10.1109/ICCT.2013.6820447" onclick="return trackOutboundLink('https://doi.org/10.1109/ICCT.2013.6820447' );">A Parallel LTE Turbo Decoder on GPU</a>,” <i>in Proceedings of the IEEE International Conference on Communication Technology (ICCT)</i>, November 2013.</li>
<li id="ref10">M. Wu, G. Wang, B. Yin, C. Studer, and J. R. Cavallaro, “<a target="_blank" href="https://doi.org/10.1109/ACSSC.2013.6810402" onclick="return trackOutboundLink('https://doi.org/10.1109/ACSSC.2013.6810402' );">HSPA+/LTE-A Turbo Decoder on GPU and Multicore CPU</a>,” <i>in Proceedings of the IEEE Asilomar Conference on Signals, Systems, and Computers (ACSSC)</i>, November 2013.</li>
<li id="ref11">Y. Zhang and Z. Xing and L. Yuan and C. Liu and Q. Wang, “<a target="_blank" href="https://doi.org/10.1109/ISCIT.2014.7011900" onclick="return trackOutboundLink('https://doi.org/10.1109/ISCIT.2014.7011900' );">The Acceleration of Turbo Decoder on the Newest GPGPU of Kepler Architecture</a>,” <i>in Proceedings of the IEEE International Symposium on Communications and Information Technologies (ISCIT)</i>, September 2014.</li>
<li id="ref12">R. Li, Y. Dou, J. Xu, X. Niu, and S. Ni, “<a target="_blank" href="https://doi.org/10.1587/transfun.E97.A.1027" onclick="return trackOutboundLink('https://doi.org/10.1587/transfun.E97.A.1027' );">An Efficient Parallel SOVA-Based Turbo Decoder for Software Defined Radio on GPU</a>,” <i>IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences</i>, 2014.</li>
<li id="ref13">A. Li, R. G. Maunder, B. M. Al-Hashimi, and L. Hanzo, “<a target="_blank" href="https://doi.org/10.1109/ACCESS.2016.2586309" onclick="return trackOutboundLink('https://doi.org/10.1109/ACCESS.2016.2586309' );">Implementation of a Fully-Parallel Turbo Decoder on a General-Purpose Graphics Processing Unit</a>,” <i>IEEE Access</i>, June 2016.</li>
<li id="ref14">A. Cassagne, T. Tonnellier, C. Leroux, B. Le Gal, O. Aumage, and D. Barthou, “<a target="_blank" href="https://doi.org/10.1109/ISTC.2016.7593092" onclick="return trackOutboundLink('https://doi.org/10.1109/ISTC.2016.7593092' );">Beyond Gbps Turbo Decoder on Multi-Core CPUs</a>,” <i>in Proceedings of the IEEE International Symposium on Turbo Codes and Iterative Information Processing (ISTC)</i>, September 2016.</li>
<li id="ref15">B. Le Gal and C. Jégo, “<a target="_blank" href="https://doi.org/10.1007/s12243-019-00727-5" onclick="return trackOutboundLink('https://doi.org/10.1007/s12243-019-00727-5' );">Low-latency and High-throughput Software Turbo Decoders on Multi-core Architectures</a>,” <i>Springer Annals of Telecommunications</i>, August 2019.</li>
</ol>
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