From b9313061bdc0d50d32160f1d0746e4a71d9e3932 Mon Sep 17 00:00:00 2001 From: Anderson Ignacio Date: Mon, 13 Nov 2023 00:55:07 +0000 Subject: [PATCH] Added info about AHB Master/Slave error response and added possibility for masters to ignore errors while issuing pip. transactions Signed-off-by: Anderson Ignacio --- README.md | 7 +++++++ cocotbext/ahb/ahb_monitor.py | 3 +++ cocotbext/ahb/ahb_slave.py | 3 +-- cocotbext/ahb/version.py | 2 +- 4 files changed, 12 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index 4860f02..c8e52eb 100644 --- a/README.md +++ b/README.md @@ -181,6 +181,8 @@ class AHBLiteMaster: ): ``` +In case of AHB Slave error response, the master will cancel the current transaction changing HTRANS from NSEQ to IDLE in the second clock cycle of the error response and then it will retry immediately after (following clock cycle). This is not mandatory but gives time for the master to decide whether it needs to be aborted or not the following transaction. + Its methods are composed by **read()**, **write()** and **custom()**. #### Write @@ -278,6 +280,11 @@ class AHBLiteSlave: The AHB slaves will not provide any specific data (always zero) or unexpected response, they serve as a basic slave just to check its connectivity while testing AHB Master and as a base class for the AHB Lite Slave RAM. The back-pressure feature is a way to force the slave to demonstrated unavailability while the master issue AHB transactions. The generator needs to return bool type values where bool True indicates slave available and bool False indicate slave unavailable. +In case of an AHB error response, the Slave inserts a wait state (HREADY == LOW && HRESP == OKAY) however this not required and might change in the future sticking only to the mandatory obligation of 2-cycle error response: + +* First: HREADY == LOW / HRESP == ERROR +* Second: HREADY == HIGH / HRESP == ERROR + #### AHB Lite Slave RAM The AHB Lite Slave RAM is a basic memory slave that can receive reads and write like a normal memory-mapped device. The only difference between the normal slave vs this one is the fact that as part of its constructor, a new argument **mem_size** is listed. This argument defines a memory size in bytes for the AHB slave. The only limitation for now, is the fact that all memory addresses have to be aligned to the data bus width, i.e for 32-bit slaves, address[1:0] == 2'b00. diff --git a/cocotbext/ahb/ahb_monitor.py b/cocotbext/ahb/ahb_monitor.py index f5360d5..3373460 100644 --- a/cocotbext/ahb/ahb_monitor.py +++ b/cocotbext/ahb/ahb_monitor.py @@ -52,6 +52,9 @@ async def _mon_master_txn(self): while True: await FallingEdge(self.clk) + if self.bus.htrans.value.is_resolvable and self.bus.hready.value.is_resolvable: + if self.bus.htrans.value == 0 and self.bus.hready == 0: + raise AssertionError("AHB PROTOCOL VIOLATION - TEST") # print(f"pending: {pending}") # Ensure master does not change its qualifiers before hready diff --git a/cocotbext/ahb/ahb_slave.py b/cocotbext/ahb/ahb_slave.py index 67e1b33..cb771c5 100644 --- a/cocotbext/ahb/ahb_slave.py +++ b/cocotbext/ahb/ahb_slave.py @@ -4,7 +4,7 @@ # License : MIT license # Author : Anderson I. da Silva (aignacio) # Date : 16.10.2023 -# Last Modified Date: 12.11.2023 +# Last Modified Date: 13.11.2023 import cocotb import logging @@ -118,7 +118,6 @@ async def _proc_txn(self): # Check for new txn if ( (cur_hready == 1) - and (cur_hresp != AHBResp.ERROR) and self._check_inputs() and self._check_valid_txn() ): diff --git a/cocotbext/ahb/version.py b/cocotbext/ahb/version.py index c11f861..d3ec452 100644 --- a/cocotbext/ahb/version.py +++ b/cocotbext/ahb/version.py @@ -1 +1 @@ -__version__ = "0.1.9" +__version__ = "0.2.0"