verilator_config.vlt

`verilator_config
lint_off -rule CASEINCOMPLETE -file "xlnx/rtl/verilog-axi/rtl/axi_ram.v"
lint_off -rule PINMISSING     -file "xlnx/rtl/verilog-axi/rtl/axi_ram.v"
lint_off -rule IMPLICIT       -file "xlnx/rtl/axi_interconnect_wrapper.sv"
lint_off -rule WIDTH          -file "xlnx/rtl/axi_mem_wrapper_2.sv"
lint_off -rule WIDTH          -file "xlnx/rtl/axi_interconnect_wrapper.sv"
lint_off -rule WIDTH          -file "xlnx/rtl/verilog-axi/rtl/axi_ram.v"
lint_off -rule WIDTH          -file "xlnx/rtl/verilog-axi/rtl/axi_interconnect.v"
lint_off -rule WIDTH          -file "xlnx/rtl/verilog-axi/rtl/priority_encoder.v"
lint_off -rule LITENDIAN      -file "xlnx/rtl/verilog-axi/rtl/priority_encoder.v"
lint_off -rule WIDTH          -file "xlnx/rtl/verilog-axi/rtl/arbiter.v"
lint_off -rule LITENDIAN      -file "xlnx/rtl/verilog-axi/rtl/arbiter.v"
lint_off -rule WIDTH          -file "xlnx/rtl/verilog-axi/rtl/axi_crossbar_addr.v"
lint_off -rule WIDTH          -file "xlnx/rtl/verilog-axi/rtl/axi_crossbar_wr.v"
lint_off -rule LITENDIAN      -file "xlnx/rtl/verilog-axi/rtl/axi_crossbar_wr.v"
lint_off -rule WIDTH          -file "xlnx/rtl/verilog-axi/rtl/axi_crossbar_rd.v"
lint_off -rule LITENDIAN      -file "xlnx/rtl/verilog-axi/rtl/axi_crossbar_rd.v"
lint_off -rule CASEINCOMPLETE -file "xlnx/rtl/verilog-axi/rtl/axi_crossbar_addr.v"
lint_off -rule INITIALDLY     -file "xlnx/rtl/verilog-axi/rtl/axi_crossbar_addr.v"