diff --git a/.DS_Store b/.DS_Store new file mode 100644 index 0000000..ea0d748 Binary files /dev/null and b/.DS_Store differ diff --git a/ahb_template.gtkw b/ahb_template.gtkw new file mode 100644 index 0000000..d55e2d3 --- /dev/null +++ b/ahb_template.gtkw @@ -0,0 +1,128 @@ +[*] +[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI +[*] Tue May 21 22:13:34 2024 +[*] +[dumpfile] "nox_waves.fst" +[dumpfile_mtime] "Tue May 21 22:05:46 2024" +[dumpfile_size] 3059157 +[savefile] "ahb_template.gtkw" +[timestart] 182791 +[size] 2384 1412 +[pos] 2005 426 +*-6.047431 182560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +[markername] AA +[markername] BB +[markername] CC +[markername] DD +[markername] EE +[markername] FF +[markername] GG +[markername] HH +[markername] II +[markername] JJ +[markername] KK +[markername] LL +[markername] MM +[markername] NN +[markername] OO +[markername] PP +[markername] QQ +[markername] RR +[markername] SS +[markername] TT +[markername] UU +[markername] VV +[markername] WW +[markername] XX +[markername] YY +[markername] ZZ +[treeopen] TOP. +[treeopen] TOP.nox_soc. +[treeopen] TOP.nox_soc.u_nox_wrapper. +[treeopen] TOP.nox_soc.u_nox_wrapper.u_nox. +[treeopen] TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch. +[sst_width] 362 +[signals_width] 296 +[sst_expanded] 1 +[sst_vpaned_height] 611 +@28 +TOP.nox_soc.rst +TOP.nox_soc.clk +@200 +- +@10023 +TOP.nox_soc.u_nox_intcon_wrapper.m0_cpu_fetch_mosi.haddr[31:0] +@800200 +-instr_nox +@28 +TOP.nox_soc.u_nox_intcon_wrapper.m0_cpu_fetch_mosi.hready +@22 +TOP.nox_soc.u_nox_intcon_wrapper.m0_cpu_fetch_mosi.haddr[31:0] +@28 +TOP.nox_soc.u_nox_intcon_wrapper.m0_cpu_fetch_mosi.hsel +@100000028 +TOP.nox_soc.u_nox_intcon_wrapper.m0_cpu_fetch_mosi.hsize[2:0] +TOP.nox_soc.u_nox_intcon_wrapper.m0_cpu_fetch_mosi.htrans[1:0] +@22 +TOP.nox_soc.u_nox_intcon_wrapper.m0_cpu_fetch_mosi.hwdata[31:0] +@28 +TOP.nox_soc.u_nox_intcon_wrapper.m0_cpu_fetch_mosi.hwrite +@200 +- +@28 +TOP.nox_soc.u_nox_intcon_wrapper.m0_cpu_fetch_miso.hready +TOP.nox_soc.u_nox_intcon_wrapper.m0_cpu_fetch_miso.hresp +@22 +TOP.nox_soc.u_nox_intcon_wrapper.m0_cpu_fetch_miso.hrdata[31:0] +@1000200 +-instr_nox +@c00200 +-lsu_nox +@28 +TOP.nox_soc.u_nox_intcon_wrapper.m1_cpu_lsu_mosi.hready +@22 +TOP.nox_soc.u_nox_intcon_wrapper.m1_cpu_lsu_mosi.haddr[31:0] +@28 +TOP.nox_soc.u_nox_intcon_wrapper.m1_cpu_lsu_mosi.hsel +@100000028 +TOP.nox_soc.u_nox_intcon_wrapper.m1_cpu_lsu_mosi.hsize[2:0] +TOP.nox_soc.u_nox_intcon_wrapper.m1_cpu_lsu_mosi.htrans[1:0] +@22 +TOP.nox_soc.u_nox_intcon_wrapper.m1_cpu_lsu_mosi.hwdata[31:0] +@28 +TOP.nox_soc.u_nox_intcon_wrapper.m1_cpu_lsu_mosi.hwrite +@200 +- +@28 +TOP.nox_soc.u_nox_intcon_wrapper.m1_cpu_lsu_miso.hready +TOP.nox_soc.u_nox_intcon_wrapper.m1_cpu_lsu_miso.hresp +@22 +TOP.nox_soc.u_nox_intcon_wrapper.m1_cpu_lsu_miso.hrdata[31:0] +@1401200 +-lsu_nox +@28 +TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch.fetch_req_i +@22 +TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch.fetch_addr_i[31:0] +@28 +TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch.next_req +@100000028 +TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch.st_ff[1:0] +@28 +TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch.jump +TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch.req_ff +TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch.dp_ff +@200 +- +@28 +TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch.fetch_valid_o +@22 +TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch.fetch_instr_o[31:0] +@28 +TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch.fetch_ready_i +@24 +TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch.buffer_space[1:0] +@420 +TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch.L0_BUFFER_SIZE +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/bus_arch_sv_pkg b/bus_arch_sv_pkg index 0e942f0..f9b15a0 160000 --- a/bus_arch_sv_pkg +++ b/bus_arch_sv_pkg @@ -1 +1 @@ -Subproject commit 0e942f0c65bd669ddfc98d03bb3839de1b1da366 +Subproject commit f9b15a03eeaa19379c0a291dedce28ce9d205fd6 diff --git a/makefile b/makefile index 7cc0cb8..4dcc74e 100644 --- a/makefile +++ b/makefile @@ -1,4 +1,4 @@ -AXI_IF ?= 1 +AXI_IF ?= 0 GTKWAVE_PRE := /Applications/gtkwave.app/Contents/Resources/bin/ # Design files _SRC_VERILOG ?= bus_arch_sv_pkg/amba_axi_pkg.sv @@ -42,7 +42,13 @@ _SOC_VERILOG += xlnx/rtl/nox_wrapper.sv _SOC_VERILOG += xlnx/rtl/cdc_async_fifo.sv _SOC_VERILOG += xlnx/rtl/axi_spi_master.sv _SOC_VERILOG += xlnx/rtl/axi_mtimer.sv +_SOC_VERILOG += xlnx/rtl/ahb_mem.sv +_SOC_VERILOG += xlnx/rtl/cmsdk_ahb_to_sram.v +_SOC_VERILOG += xlnx/rtl/cmsdk_fpga_sram.v +_SOC_VERILOG += xlnx/rtl/nox_ahb_ram.sv _SOC_VERILOG += sw/bootloader/output/boot_rom.sv +_SOC_VERILOG += $(shell find xlnx/rtl/ahb_interconnect -type f -iname *.v) +_SOC_VERILOG += $(shell find xlnx/rtl/ahb_interconnect -type f -iname *.sv) ifeq ($(AXI_IF),0) _SOC_VERILOG += xlnx/rtl/nox_soc_ahb.sv @@ -59,12 +65,12 @@ INCS_VLOG := $(addprefix -I,$(_INCS_VLOG)) #IRAM_KB_SIZE ?= 2*1024 #2MB due to J-Tests on RV Compliance tests IRAM_KB_SIZE ?= 128 DRAM_KB_SIZE ?= 32 -ENTRY_ADDR ?= \'h8000_0000 -IRAM_ADDR ?= 0x80000000 -DRAM_ADDR ?= 0x10000000 +ENTRY_ADDR ?= \'h0000_0000 +IRAM_ADDR ?= 0x00000000 +DRAM_ADDR ?= 0x00020000 # For NoX SoC -IRAM_ADDR_SOC ?= 0xa0000000 -DRAM_ADDR_SOC ?= 0x10000000 +IRAM_ADDR_SOC ?= 0x00000000 +DRAM_ADDR_SOC ?= 0x00020000 DISPLAY_TEST ?= 0 # Enable $display in axi_mem.sv [compliance test] WAVEFORM_USE ?= 1 # Use 0 to not generate waves [compliance test] @@ -120,7 +126,8 @@ RUN_CMD_COMP := docker run --rm --name ship_nox \ RUN_SW := sw/hello_world/output/hello_world.elf #RUN_SW_SOC := sw/bootloader/output/bootloader.elf -RUN_SW_SOC := sw/soc_hello_world/output/soc_hello_world.elf +#RUN_SW_SOC := sw/soc_hello_world/output/soc_hello_world.elf +RUN_SW_SOC := sw/hello_world/output/hello_world.elf #RUN_SW_SOC := sw/FreeRTOS_demo/output/FreeRTOS_demo.elf CPPFLAGS_VERI := "$(INCS_CPP) -O0 -g3 -Wall \ @@ -244,7 +251,7 @@ soc: clean $(VERI_EXE_SOC) @echo "\n" $(RUN_SW_SOC): - make -C sw/soc_hello_world all UART_MODE=UART_SIM + make -C sw/hello_world all UART_MODE=UART_SIM run_soc: $(RUN_SW_SOC) $(RUN_CMD) ./$(VERI_EXE_SOC) -s 100000 -e $< diff --git a/rtl/cb_to_ahb.sv b/rtl/cb_to_ahb.sv index 525ea9c..990923a 100644 --- a/rtl/cb_to_ahb.sv +++ b/rtl/cb_to_ahb.sv @@ -3,13 +3,15 @@ * License : MIT license * Author : Anderson Ignacio da Silva (aignacio) * Date : 23.10.2021 - * Last Modified Date: 25.02.2022 + * Last Modified Date: 15.05.2024 */ module cb_to_ahb import amba_axi_pkg::*; import amba_ahb_pkg::*; import nox_utils_pkg::*; ( + input clk, + input rst, // Core bus Master I/F input s_cb_mosi_t cb_mosi_i, output s_cb_miso_t cb_miso_o, @@ -17,6 +19,20 @@ module cb_to_ahb output s_ahb_mosi_t ahb_mosi_o, input s_ahb_miso_t ahb_miso_i ); + logic req_rd_ff, next_rd_req; + logic req_wr_ff, next_wr_req; + + `CLK_PROC(clk, rst) begin + `RST_TYPE(rst) begin + req_rd_ff <= 1'b0; + req_wr_ff <= '0; + end + else begin + req_rd_ff <= next_rd_req; + req_wr_ff <= next_wr_req; + end + end + always_comb begin ahb_mosi_o = s_ahb_mosi_t'('0); cb_miso_o = s_cb_miso_t'('0); @@ -33,15 +49,36 @@ module cb_to_ahb end ahb_mosi_o.hwdata = cb_mosi_i.wr_data_valid ? cb_mosi_i.wr_data : 'h0; + next_rd_req = req_rd_ff; + next_wr_req = req_wr_ff; + + if (req_rd_ff && ahb_miso_i.hready) begin + next_rd_req = 1'b0; + end + + if (req_wr_ff && ahb_miso_i.hready) begin + next_wr_req = 1'b0; + end + + + if (ahb_mosi_o.hsel && (ahb_mosi_o.htrans != AHB_IDLE) && ahb_miso_i.hready) begin + if (ahb_mosi_o.hwrite) begin + next_wr_req = 1'b1; + end + else begin + next_rd_req = 1'b1; + end + end + // MISO cb_miso_o.wr_addr_ready = ahb_miso_i.hready; - cb_miso_o.wr_data_ready = ahb_miso_i.hready; + cb_miso_o.wr_data_ready = ahb_miso_i.hready && req_wr_ff; cb_miso_o.wr_resp_error = cb_error_t'(ahb_miso_i.hresp); - cb_miso_o.wr_resp_valid = 'b1; + cb_miso_o.wr_resp_valid = ahb_miso_i.hready; cb_miso_o.rd_addr_ready = ahb_miso_i.hready; cb_miso_o.rd_data = ahb_miso_i.hrdata; cb_miso_o.rd_resp = cb_error_t'(ahb_miso_i.hresp); - cb_miso_o.rd_valid = ~ahb_miso_i.hready; + cb_miso_o.rd_valid = ahb_miso_i.hready && req_rd_ff; end endmodule diff --git a/rtl/fetch.sv b/rtl/fetch.sv index bb7c2b5..f90a271 100644 --- a/rtl/fetch.sv +++ b/rtl/fetch.sv @@ -3,7 +3,7 @@ * License : MIT license * Author : Anderson Ignacio da Silva (aignacio) * Date : 16.10.2021 - * Last Modified Date: 03.07.2022 + * Last Modified Date: 21.05.2024 */ module fetch import amba_axi_pkg::*; @@ -11,13 +11,14 @@ module fetch import nox_utils_pkg::*; #( parameter int SUPPORT_DEBUG = 1, - parameter int L0_BUFFER_SIZE = 2 // Max instrs locally stored + parameter int L0_BUFFER_SIZE = 4 // Max instrs locally stored )( input clk, input rst, // Core bus fetch I/F - output s_cb_mosi_t instr_cb_mosi_o, - input s_cb_miso_t instr_cb_miso_i, + output s_ahb_mosi_t ahb_mosi_o, + input s_ahb_miso_t ahb_miso_i, + // Start I/F input fetch_start_i, input pc_t fetch_start_addr_i, @@ -33,166 +34,119 @@ module fetch ); typedef logic [$clog2(L0_BUFFER_SIZE):0] buffer_t; - logic get_next_instr; + typedef enum logic [1:0] { + F_STP, + F_REQ, + F_CLR + } fetch_st_t; + + logic clear_fifo; logic write_instr; - buffer_t buffer_space; + logic get_next_instr; instr_raw_t instr_buffer; logic full_fifo; - logic data_valid; - logic data_ready; - logic jump; - logic clear_fifo; - logic valid_addr; - logic read_ot_fifo; - logic ot_empty; - - cb_addr_t pc_addr_ff, next_pc_addr; - cb_addr_t pc_buff_ff, next_pc_buff; + buffer_t buffer_space; + pc_t fetch_addr_ff, next_fetch_addr; + pc_t fetch_jmp_ff, next_jmp; + fetch_st_t st_ff, next_st; logic req_ff, next_req; - logic valid_txn_i, valid_txn_o; - logic addr_ready; + logic dp_ff, next_dp; logic instr_access_fault; + logic jump; - typedef enum logic [1:0] { - F_STP, - F_REQ, - F_CLR - } fetch_st_t; + always_comb begin + ahb_mosi_o = s_ahb_mosi_t'('0); + ahb_mosi_o.hready = 1'b1; + + if (req_ff) begin + ahb_mosi_o.haddr = fetch_addr_ff; + ahb_mosi_o.hsize = AHB_SZ_WORD; + ahb_mosi_o.htrans = AHB_NONSEQUENTIAL; + ahb_mosi_o.hsel = 1'b1; + end + end + + always_comb begin + clear_fifo = 1'b0; + write_instr = 1'b0; + + next_st = st_ff; + next_req = req_ff; + next_dp = dp_ff; + next_fetch_addr = fetch_addr_ff; + next_jmp = fetch_jmp_ff; - fetch_st_t st_ff, next_st; - buffer_t ot_cnt_ff, next_ot; - - always_comb begin : addr_chn_req - instr_cb_mosi_o.wr_addr = cb_addr_t'('0); - instr_cb_mosi_o.wr_size = cb_size_t'('0); - instr_cb_mosi_o.wr_addr_valid = 1'b0; - instr_cb_mosi_o.wr_data = cb_data_t'('0); - instr_cb_mosi_o.wr_strobe = cb_strb_t'('0); - instr_cb_mosi_o.wr_data_valid = 1'b0; - instr_cb_mosi_o.wr_resp_ready = 1'b0; - - data_valid = instr_cb_miso_i.rd_valid; - addr_ready = instr_cb_miso_i.rd_addr_ready; - clear_fifo = (fetch_req_i || (~fetch_start_i)); - valid_addr = 1'b0; - next_pc_addr = pc_addr_ff; - next_pc_buff = pc_buff_ff; - next_st = st_ff; - jump = fetch_req_i; - valid_txn_i = 1'b0; - - next_ot = ot_cnt_ff + (req_ff && addr_ready) - (data_valid && data_ready); + jump = fetch_req_i; case (st_ff) F_STP: begin - next_st = fetch_start_i ? F_REQ : F_STP; - - if (req_ff && ~addr_ready) begin - valid_addr = 1'b1; // Keep driving high to complete txn - valid_txn_i = 1'b0; + if (fetch_start_i) begin + next_st = F_REQ; + next_req = 1'b1; + next_fetch_addr = fetch_start_addr_i; end end F_REQ: begin - if (req_ff && ~addr_ready) begin - valid_addr = 1'b1; // Keep driving high to complete txn - valid_txn_i = 1'b1; + if (dp_ff && ahb_miso_i.hready) begin + write_instr = 1'b1; + next_dp = 1'b0; end - if (req_ff && addr_ready) begin - valid_txn_i = 1'b1; - next_pc_addr = pc_addr_ff + 'd4; + if (buffer_space < buffer_t'(L0_BUFFER_SIZE-1)) begin + next_req = 1'b1; + end + else begin + next_req = 1'b0; end - if ((req_ff && addr_ready) || ~req_ff) begin - // Next txn - if (next_ot < (buffer_t'(L0_BUFFER_SIZE))) begin - valid_addr = ~full_fifo; - end + if (req_ff && ahb_miso_i.hready) begin + next_fetch_addr = fetch_addr_ff + 'd4; + next_dp = 1'b1; end if (jump) begin - next_pc_addr = fetch_addr_i; - next_pc_buff = pc_addr_ff; - valid_txn_i = 1'b0; - - if ((req_ff && ~addr_ready) || (next_ot > 'd0)) begin - next_st = F_CLR; + clear_fifo = 1'b1; + + if (req_ff) begin + if (ahb_miso_i.hready) begin + next_fetch_addr = fetch_addr_i; + next_dp = 1'b0; + end + else begin + next_jmp = fetch_addr_i; + next_st = F_CLR; + end end - - if (req_ff && addr_ready) begin - valid_addr = 1'b0; + else if (~req_ff) begin + next_fetch_addr = fetch_addr_i; end end - - if (~fetch_start_i) begin - next_st = F_STP; - end end F_CLR: begin - // After a jump request: - // - Finish ongoing txn - valid_txn_i = 1'b0; - if (req_ff && ~addr_ready) begin - valid_addr = 1'b1; - end - else if (next_ot == '0) begin - next_st = F_REQ; - valid_addr = 1'b1; // Next txn is the jump + next_dp = 1'b0; + + if (ahb_miso_i.hready) begin + next_st = F_REQ; + next_fetch_addr = fetch_jmp_ff; + next_req = 1'b1; end end - default: valid_addr = 1'b0; + default: clear_fifo = 1'b1; endcase - - next_req = valid_addr; - instr_cb_mosi_o.rd_addr_valid = req_ff; - instr_cb_mosi_o.rd_addr = req_ff ? ((st_ff == F_CLR) ? pc_buff_ff : pc_addr_ff) : '0; - instr_cb_mosi_o.rd_size = req_ff ? cb_size_t'(CB_WORD) : cb_size_t'('0); - end : addr_chn_req - - always_comb begin : rd_chn - write_instr = 'b0; - data_ready = (st_ff == F_REQ) ? ~full_fifo : 'b1; - instr_cb_mosi_o.rd_ready = data_ready; - read_ot_fifo = ot_empty ? 1'b0 : (data_valid && data_ready); - // Only write in the FIFO if - // 1 - When there's no jump req - // 2 - When there's vld data phase (opposite means discarding) - // 3 - There valid data in the bus - // 4 - We don't have a full fifo - if (~fetch_req_i && ~ot_empty && valid_txn_o && data_valid && ~full_fifo) begin - write_instr = 'b1; - end - end : rd_chn + end always_comb begin : trap_control trap_info_o = s_trap_info_t'('0); - instr_access_fault = instr_cb_miso_i.rd_valid && - (instr_cb_miso_i.rd_resp != CB_OKAY); + instr_access_fault = (ahb_miso_i.hready == 1) && + (ahb_miso_i.hresp == 1); if (instr_access_fault) begin trap_info_o.active = 'b1; - trap_info_o.pc_addr = pc_addr_ff; - trap_info_o.mtval = pc_addr_ff; + trap_info_o.pc_addr = fetch_addr_ff - 'd4; + trap_info_o.mtval = fetch_addr_ff - 'd4; end end : trap_control - `CLK_PROC(clk, rst) begin - `RST_TYPE(rst) begin - pc_addr_ff <= cb_addr_t'(fetch_start_addr_i); - pc_buff_ff <= cb_addr_t'(fetch_start_addr_i); - st_ff <= F_STP; - req_ff <= 1'b0; - ot_cnt_ff <= buffer_t'('0); - end - else begin - pc_addr_ff <= next_pc_addr; - pc_buff_ff <= next_pc_buff; - st_ff <= next_st; - req_ff <= next_req; - ot_cnt_ff <= next_ot; - end - end - always_comb begin : fetch_proc_if fetch_valid_o = 'b0; fetch_instr_o = 'd0; @@ -201,7 +155,7 @@ module fetch // We assert valid instr if: // 1 - There's no req to fetch a new addr // 2 - There's data inside the FIFO - if (fetch_start_i && ~fetch_req_i && (buffer_space != 'd0)) begin + if (~fetch_req_i && (buffer_space != 'd0)) begin // We request to read the FIFO if: // 3 - The next stage is ready to receive fetch_valid_o = 'b1; @@ -210,22 +164,22 @@ module fetch end end : fetch_proc_if - fifo_nox #( - .SLOTS (L0_BUFFER_SIZE), - .WIDTH (1) - ) u_fifo_ot_rd ( - .clk (clk), - .rst (rst), - .clear_i (clear_fifo), - .write_i ((req_ff && addr_ready)), - .read_i (read_ot_fifo), - .data_i (valid_txn_i), - .data_o (valid_txn_o), - .error_o (), - .full_o (), - .empty_o (ot_empty), - .ocup_o () - ); + `CLK_PROC(clk, rst) begin + `RST_TYPE(rst) begin + fetch_addr_ff <= pc_t'('0); + st_ff <= F_STP; + req_ff <= 1'b0; + dp_ff <= 1'b0; + fetch_jmp_ff <= pc_t'('0); + end + else begin + fetch_addr_ff <= next_fetch_addr; + st_ff <= next_st; + req_ff <= next_req; + dp_ff <= next_dp; + fetch_jmp_ff <= next_jmp; + end + end fifo_nox #( .SLOTS (L0_BUFFER_SIZE), @@ -236,7 +190,7 @@ module fetch .clear_i (clear_fifo), .write_i (write_instr), .read_i (get_next_instr), - .data_i (instr_cb_miso_i.rd_data), + .data_i (ahb_miso_i.hrdata), .data_o (instr_buffer), .error_o (), .full_o (full_fifo), diff --git a/rtl/fetch_axi.sv b/rtl/fetch_axi.sv new file mode 100644 index 0000000..7403b89 --- /dev/null +++ b/rtl/fetch_axi.sv @@ -0,0 +1,252 @@ +/** +* File : fetch_axi.sv + * License : MIT license + * Author : Anderson Ignacio da Silva (aignacio) + * Date : 16.10.2021 + * Last Modified Date: 21.05.2024 + */ +module fetch_axi + import amba_axi_pkg::*; + import amba_ahb_pkg::*; + import nox_utils_pkg::*; +#( + parameter int SUPPORT_DEBUG = 1, + parameter int L0_BUFFER_SIZE = 2 // Max instrs locally stored +)( + input clk, + input rst, + // Core bus fetch I/F + output s_cb_mosi_t instr_cb_mosi_o, + input s_cb_miso_t instr_cb_miso_i, + // Start I/F + input fetch_start_i, + input pc_t fetch_start_addr_i, + // From EXEC stg + input fetch_req_i, + input pc_t fetch_addr_i, + // To DEC I/F + output valid_t fetch_valid_o, + input ready_t fetch_ready_i, + output instr_raw_t fetch_instr_o, + // Trap - Instruction access fault + output s_trap_info_t trap_info_o +); + typedef logic [$clog2(L0_BUFFER_SIZE):0] buffer_t; + + logic get_next_instr; + logic write_instr; + buffer_t buffer_space; + instr_raw_t instr_buffer; + logic full_fifo; + logic data_valid; + logic data_ready; + logic jump; + logic clear_fifo; + logic valid_addr; + logic read_ot_fifo; + logic ot_empty; + + cb_addr_t pc_addr_ff, next_pc_addr; + cb_addr_t pc_buff_ff, next_pc_buff; + logic req_ff, next_req; + logic valid_txn_i, valid_txn_o; + logic addr_ready; + logic instr_access_fault; + + typedef enum logic [1:0] { + F_STP, + F_REQ, + F_CLR + } fetch_st_t; + + fetch_st_t st_ff, next_st; + buffer_t ot_cnt_ff, next_ot; + + always_comb begin : addr_chn_req + instr_cb_mosi_o.wr_addr = cb_addr_t'('0); + instr_cb_mosi_o.wr_size = cb_size_t'('0); + instr_cb_mosi_o.wr_addr_valid = 1'b0; + instr_cb_mosi_o.wr_data = cb_data_t'('0); + instr_cb_mosi_o.wr_strobe = cb_strb_t'('0); + instr_cb_mosi_o.wr_data_valid = 1'b0; + instr_cb_mosi_o.wr_resp_ready = 1'b0; + + data_valid = instr_cb_miso_i.rd_valid; + addr_ready = instr_cb_miso_i.rd_addr_ready; + clear_fifo = (fetch_req_i || (~fetch_start_i)); + valid_addr = 1'b0; + next_pc_addr = pc_addr_ff; + next_pc_buff = pc_buff_ff; + next_st = st_ff; + jump = fetch_req_i; + valid_txn_i = 1'b0; + + next_ot = ot_cnt_ff + (req_ff && addr_ready) - (data_valid && data_ready); + + case (st_ff) + F_STP: begin + next_st = fetch_start_i ? F_REQ : F_STP; + + if (req_ff && ~addr_ready) begin + valid_addr = 1'b1; // Keep driving high to complete txn + valid_txn_i = 1'b0; + end + end + F_REQ: begin + if (req_ff && ~addr_ready) begin + valid_addr = 1'b1; // Keep driving high to complete txn + valid_txn_i = 1'b1; + end + + if (req_ff && addr_ready) begin + valid_txn_i = 1'b1; + next_pc_addr = pc_addr_ff + 'd4; + end + + if ((req_ff && addr_ready) || ~req_ff) begin + // Next txn + if (next_ot < (buffer_t'(L0_BUFFER_SIZE))) begin + valid_addr = ~full_fifo; + end + end + + if (jump) begin + next_pc_addr = fetch_addr_i; + next_pc_buff = pc_addr_ff; + valid_txn_i = 1'b0; + + if ((req_ff && ~addr_ready) || (next_ot > 'd0)) begin + next_st = F_CLR; + end + + if (req_ff && addr_ready) begin + valid_addr = 1'b0; + end + end + + if (~fetch_start_i) begin + next_st = F_STP; + end + end + F_CLR: begin + // After a jump request: + // - Finish ongoing txn + valid_txn_i = 1'b0; + if (req_ff && ~addr_ready) begin + valid_addr = 1'b1; + end + else if (next_ot == '0) begin + next_st = F_REQ; + valid_addr = 1'b1; // Next txn is the jump + end + end + default: valid_addr = 1'b0; + endcase + + next_req = valid_addr; + instr_cb_mosi_o.rd_addr_valid = req_ff; + instr_cb_mosi_o.rd_addr = req_ff ? ((st_ff == F_CLR) ? pc_buff_ff : pc_addr_ff) : '0; + instr_cb_mosi_o.rd_size = req_ff ? cb_size_t'(CB_WORD) : cb_size_t'('0); + end : addr_chn_req + + always_comb begin : rd_chn + write_instr = 'b0; + data_ready = (st_ff == F_REQ) ? ~full_fifo : 'b1; + instr_cb_mosi_o.rd_ready = data_ready; + read_ot_fifo = ot_empty ? 1'b0 : (data_valid && data_ready); + // Only write in the FIFO if + // 1 - When there's no jump req + // 2 - When there's vld data phase (opposite means discarding) + // 3 - There valid data in the bus + // 4 - We don't have a full fifo + if (~fetch_req_i && ~ot_empty && valid_txn_o && data_valid && ~full_fifo) begin + write_instr = 'b1; + end + end : rd_chn + + always_comb begin : trap_control + trap_info_o = s_trap_info_t'('0); + instr_access_fault = instr_cb_miso_i.rd_valid && + (instr_cb_miso_i.rd_resp != CB_OKAY); + + if (instr_access_fault) begin + trap_info_o.active = 'b1; + trap_info_o.pc_addr = pc_addr_ff; + trap_info_o.mtval = pc_addr_ff; + end + end : trap_control + + `CLK_PROC(clk, rst) begin + `RST_TYPE(rst) begin + pc_addr_ff <= cb_addr_t'(fetch_start_addr_i); + pc_buff_ff <= cb_addr_t'(fetch_start_addr_i); + st_ff <= F_STP; + req_ff <= 1'b0; + ot_cnt_ff <= buffer_t'('0); + end + else begin + pc_addr_ff <= next_pc_addr; + pc_buff_ff <= next_pc_buff; + st_ff <= next_st; + req_ff <= next_req; + ot_cnt_ff <= next_ot; + end + end + + always_comb begin : fetch_proc_if + fetch_valid_o = 'b0; + fetch_instr_o = 'd0; + get_next_instr = 'b0; + + // We assert valid instr if: + // 1 - There's no req to fetch a new addr + // 2 - There's data inside the FIFO + if (fetch_start_i && ~fetch_req_i && (buffer_space != 'd0)) begin + // We request to read the FIFO if: + // 3 - The next stage is ready to receive + fetch_valid_o = 'b1; + fetch_instr_o = instr_buffer; + get_next_instr = fetch_ready_i; + end + end : fetch_proc_if + + fifo_nox #( + .SLOTS (L0_BUFFER_SIZE), + .WIDTH (1) + ) u_fifo_ot_rd ( + .clk (clk), + .rst (rst), + .clear_i (clear_fifo), + .write_i ((req_ff && addr_ready)), + .read_i (read_ot_fifo), + .data_i (valid_txn_i), + .data_o (valid_txn_o), + .error_o (), + .full_o (), + .empty_o (ot_empty), + .ocup_o () + ); + + fifo_nox #( + .SLOTS (L0_BUFFER_SIZE), + .WIDTH (32) + ) u_fifo_l0 ( + .clk (clk), + .rst (rst), + .clear_i (clear_fifo), + .write_i (write_instr), + .read_i (get_next_instr), + .data_i (instr_cb_miso_i.rd_data), + .data_o (instr_buffer), + .error_o (), + .full_o (full_fifo), + .empty_o (), + .ocup_o (buffer_space) + ); + +`ifdef COCOTB_SIM + `ifdef XCELIUM + `DUMP_WAVES_XCELIUM + `endif +`endif +endmodule diff --git a/rtl/inc/nox_pkg.svh b/rtl/inc/nox_pkg.svh index 5f64789..a98a741 100644 --- a/rtl/inc/nox_pkg.svh +++ b/rtl/inc/nox_pkg.svh @@ -10,8 +10,8 @@ //`define TARGET_ASIC //`define EN_RTL_VERBOSE - `define TARGET_IF_AXI - //`define TARGET_IF_AHB + //`define TARGET_IF_AXI + `define TARGET_IF_AHB `ifdef TARGET_FPGA `define ACT_L_RESET diff --git a/rtl/nox.sv b/rtl/nox.sv index ad6db6c..43d9bd0 100644 --- a/rtl/nox.sv +++ b/rtl/nox.sv @@ -3,7 +3,7 @@ * License : MIT license * Author : Anderson Ignacio da Silva (aignacio) * Date : 16.10.2021 - * Last Modified Date: 02.07.2022 + * Last Modified Date: 21.05.2024 */ module nox import amba_axi_pkg::*; @@ -12,7 +12,7 @@ module nox #( parameter int SUPPORT_DEBUG = 1, parameter int MTVEC_DEFAULT_VAL = 'h1000, // 4KB - parameter int L0_BUFFER_SIZE = 2, // Max instrs locally stored + parameter int L0_BUFFER_SIZE = 4, // Max instrs locally stored parameter int TRAP_ON_MIS_LSU_ADDR = 1, // Trap in case of misaligned addr on LSU parameter int TRAP_ON_LSU_ERROR = 1, // Trap in case of LSU error parameter int FETCH_IF_ID = 0, @@ -82,18 +82,6 @@ module nox `endif `ifdef TARGET_IF_AXI - cb_to_axi #( - .AXI_ID (FETCH_IF_ID) - ) u_instr_cb_to_axi( - .clk (clk), - // Core bus Master I/F - .cb_mosi_i (instr_cb_mosi), - .cb_miso_o (instr_cb_miso), - // AXI Master I/F - .axi_mosi_o (instr_axi_mosi_o), - .axi_miso_i (instr_axi_miso_i) - ); - cb_to_axi #( .AXI_ID (LSU_IF_ID) ) u_lsu_cb_to_axi( @@ -106,16 +94,9 @@ module nox .axi_miso_i (lsu_axi_miso_i) ); `else - cb_to_ahb u_instr_cb_to_ahb( - // Core bus Master I/F - .cb_mosi_i (instr_cb_mosi), - .cb_miso_o (instr_cb_miso), - // AHB Master I/F - .ahb_mosi_o (instr_ahb_mosi_o), - .ahb_miso_i (instr_ahb_miso_i) - ); - cb_to_ahb u_lsu_cb_to_ahb( + .clk (clk), + .rst (rst), // Core bus Master I/F .cb_mosi_i (lsu_cb_mosi), .cb_miso_o (lsu_cb_miso), @@ -132,8 +113,8 @@ module nox .clk (clk), .rst (rst), // Core bus fetch I/F - .instr_cb_mosi_o (instr_cb_mosi), - .instr_cb_miso_i (instr_cb_miso), + .ahb_mosi_o (instr_ahb_mosi_o), + .ahb_miso_i (instr_ahb_miso_i), // Start I/F .fetch_start_i (start_fetch_i), .fetch_start_addr_i (start_addr_i), diff --git a/sw/hello_world/sections.ld b/sw/hello_world/sections.ld index ff772a6..09d3ad2 100755 --- a/sw/hello_world/sections.ld +++ b/sw/hello_world/sections.ld @@ -28,8 +28,8 @@ ENTRY( _start_reset ) MEMORY { - IRAM(rxai!w) : ORIGIN = 0x80000000, LENGTH = 16K - DRAM(wxa!ri) : ORIGIN = 0x10000000, LENGTH = 8K + IRAM(rxai!w) : ORIGIN = 0x00000000, LENGTH = 13K + DRAM(wxa!ri) : ORIGIN = 0x00040000, LENGTH = 8K } _min_stack = 0x100; diff --git a/sw/hello_world/src/main.c b/sw/hello_world/src/main.c index f712951..ac5c22e 100755 --- a/sw/hello_world/src/main.c +++ b/sw/hello_world/src/main.c @@ -12,7 +12,7 @@ volatile uint32_t* const addr_leds = (uint32_t*) LEDS_ADDR; volatile uint32_t* const addr_print = (uint32_t*) PRINT_ADDR; void _putchar(char character){ - *addr_print = character; + /**addr_print = character;*/ } void print_logo(void){ @@ -59,7 +59,7 @@ int main(void) { /*int time = rdtime();*/ /*printf("Hello_World Nox!");*/ - *addr_leds = leds_out; + /**addr_leds = leds_out;*/ print_logo(); set_csr(mstatus,MSTATUS_MIE); while(true){ @@ -94,7 +94,7 @@ int main(void) { else leds_out = leds_out << 1; - *addr_leds = leds_out; + /**addr_leds = leds_out;*/ } i++; test++; diff --git a/sw/soc_hello_world/sections.ld b/sw/soc_hello_world/sections.ld index de8638d..53269cc 100755 --- a/sw/soc_hello_world/sections.ld +++ b/sw/soc_hello_world/sections.ld @@ -28,8 +28,8 @@ ENTRY( _start_reset ) MEMORY { - IRAM(rxai!w) : ORIGIN = 0xA0000000, LENGTH = 24K - DRAM(wxa!ri) : ORIGIN = 0x10000000, LENGTH = 8K + IRAM(rxai!w) : ORIGIN = 0x00000000, LENGTH = 8K + DRAM(wxa!ri) : ORIGIN = 0x00020000, LENGTH = 8K } _min_stack = 0x100; diff --git a/sw/soc_hello_world/src/main.c b/sw/soc_hello_world/src/main.c index 72f92e6..8652cc9 100755 --- a/sw/soc_hello_world/src/main.c +++ b/sw/soc_hello_world/src/main.c @@ -10,7 +10,7 @@ #define BR_UART 115200 //#define REAL_UART -#define LCD_EN +/*#define LCD_EN*/ #define ERR_CFG 0xFFFF0000 #define PRINT_ADDR 0xD0000008 diff --git a/tb/cpp/testbench_soc.cpp b/tb/cpp/testbench_soc.cpp index 5008a7e..8e1efc9 100644 --- a/tb/cpp/testbench_soc.cpp +++ b/tb/cpp/testbench_soc.cpp @@ -67,9 +67,9 @@ template class testbench { } virtual void tick(void) { - if (core->nox_soc->u_axi_gpio->printfbufferReq()) { - printf("%c",core->nox_soc->u_axi_gpio->getbufferReq()); - } + //if (core->nox_soc->u_axi_gpio->printfbufferReq()) { + //printf("%c",core->nox_soc->u_axi_gpio->getbufferReq()); + //} core->clk_in = 0; core->eval(); diff --git a/verilator_config.vlt b/verilator_config.vlt index bed6df7..c41395c 100644 --- a/verilator_config.vlt +++ b/verilator_config.vlt @@ -17,3 +17,7 @@ lint_off -rule WIDTH -file "xlnx/rtl/verilog-axi/rtl/axi_crossbar_rd.v" lint_off -rule LITENDIAN -file "xlnx/rtl/verilog-axi/rtl/axi_crossbar_rd.v" lint_off -rule CASEINCOMPLETE -file "xlnx/rtl/verilog-axi/rtl/axi_crossbar_addr.v" lint_off -rule INITIALDLY -file "xlnx/rtl/verilog-axi/rtl/axi_crossbar_addr.v" +lint_off -rule UNSIGNED -file "xlnx/rtl/ahb_interconnect/nox_intcon_decM1_CPU_LSU.v" +lint_off -rule UNSIGNED -file "xlnx/rtl/ahb_interconnect/nox_intcon_decM2_CPU_FRONT_PORT.v" +lint_off -rule UNSIGNED -file "xlnx/rtl/ahb_interconnect/nox_intcon_decM0_CPU_FETCH.v" +lint_off -rule CMPCONST -file "xlnx/rtl/ahb_interconnect/nox_intcon_decM1_CPU_LSU.v" diff --git a/xlnx/rtl/ahb_interconnect/nox_intcon.v b/xlnx/rtl/ahb_interconnect/nox_intcon.v new file mode 100644 index 0000000..814b778 --- /dev/null +++ b/xlnx/rtl/ahb_interconnect/nox_intcon.v @@ -0,0 +1,1182 @@ +//----------------------------------------------------------------------------- +// The confidential and proprietary information contained in this file may +// only be used by a person authorised under and to the extent permitted +// by a subsisting licensing agreement from ARM Limited. +// +// (C) COPYRIGHT 2001-2013-2024 ARM Limited. +// ALL RIGHTS RESERVED +// +// This entire notice must be reproduced on all copies of this file +// and copies of this file may only be made by a person if such person is +// permitted to do so under the terms of a subsisting license agreement +// from ARM Limited. +// +// SVN Information +// +// Checked In : $Date: 2012-10-15 18:01:36 +0100 (Mon, 15 Oct 2012) $ +// +// Revision : $Revision: 225465 $ +// +// Release Information : Cortex-M System Design Kit-r1p0-01rel0 +// +//----------------------------------------------------------------------------- +// +//------------------------------------------------------------------------------ +// Abstract : BusMatrix is the top-level which connects together +// the required Input Stages, MatrixDecodes, Output +// Stages and Output Arbitration blocks. +// +// Supports the following configured options: +// +// - Architecture type 'ahb2', +// - 3 slave ports (connecting to masters), +// - 4 master ports (connecting to slaves), +// - Routing address width of 32 bits, +// - Routing data width of 32 bits, +// - xUSER signal width of 32 bits, +// - Arbiter type 'round', +// - Connectivity mapping: +// M0_CPU_FETCH -> S0_ROM, S1_IRAM, +// M1_CPU_LSU -> S0_ROM, S1_IRAM, S2_DRAM, S3_PERIPH, +// M2_CPU_FRONT_PORT -> S0_ROM, S1_IRAM, S2_DRAM, +// - Connectivity type 'sparse'. +// +//------------------------------------------------------------------------------ + +`timescale 1ns/1ps + +module nox_intcon ( + + // Common AHB signals + HCLK, + HRESETn, + + // System address remapping control + REMAP, + + // Input port SI0 (inputs from master 0) + HSELM0_CPU_FETCH, + HADDRM0_CPU_FETCH, + HTRANSM0_CPU_FETCH, + HWRITEM0_CPU_FETCH, + HSIZEM0_CPU_FETCH, + HBURSTM0_CPU_FETCH, + HPROTM0_CPU_FETCH, + HMASTERM0_CPU_FETCH, + HWDATAM0_CPU_FETCH, + HMASTLOCKM0_CPU_FETCH, + HREADYM0_CPU_FETCH, + HAUSERM0_CPU_FETCH, + HWUSERM0_CPU_FETCH, + + // Input port SI1 (inputs from master 1) + HSELM1_CPU_LSU, + HADDRM1_CPU_LSU, + HTRANSM1_CPU_LSU, + HWRITEM1_CPU_LSU, + HSIZEM1_CPU_LSU, + HBURSTM1_CPU_LSU, + HPROTM1_CPU_LSU, + HMASTERM1_CPU_LSU, + HWDATAM1_CPU_LSU, + HMASTLOCKM1_CPU_LSU, + HREADYM1_CPU_LSU, + HAUSERM1_CPU_LSU, + HWUSERM1_CPU_LSU, + + // Input port SI2 (inputs from master 2) + HSELM2_CPU_FRONT_PORT, + HADDRM2_CPU_FRONT_PORT, + HTRANSM2_CPU_FRONT_PORT, + HWRITEM2_CPU_FRONT_PORT, + HSIZEM2_CPU_FRONT_PORT, + HBURSTM2_CPU_FRONT_PORT, + HPROTM2_CPU_FRONT_PORT, + HMASTERM2_CPU_FRONT_PORT, + HWDATAM2_CPU_FRONT_PORT, + HMASTLOCKM2_CPU_FRONT_PORT, + HREADYM2_CPU_FRONT_PORT, + HAUSERM2_CPU_FRONT_PORT, + HWUSERM2_CPU_FRONT_PORT, + + // Output port MI0 (inputs from slave 0) + HRDATAS0_ROM, + HREADYOUTS0_ROM, + HRESPS0_ROM, + HRUSERS0_ROM, + + // Output port MI1 (inputs from slave 1) + HRDATAS1_IRAM, + HREADYOUTS1_IRAM, + HRESPS1_IRAM, + HRUSERS1_IRAM, + + // Output port MI2 (inputs from slave 2) + HRDATAS2_DRAM, + HREADYOUTS2_DRAM, + HRESPS2_DRAM, + HRUSERS2_DRAM, + + // Output port MI3 (inputs from slave 3) + HRDATAS3_PERIPH, + HREADYOUTS3_PERIPH, + HRESPS3_PERIPH, + HRUSERS3_PERIPH, + + // Scan test dummy signals; not connected until scan insertion + SCANENABLE, // Scan Test Mode Enable + SCANINHCLK, // Scan Chain Input + + + // Output port MI0 (outputs to slave 0) + HSELS0_ROM, + HADDRS0_ROM, + HTRANSS0_ROM, + HWRITES0_ROM, + HSIZES0_ROM, + HBURSTS0_ROM, + HPROTS0_ROM, + HMASTERS0_ROM, + HWDATAS0_ROM, + HMASTLOCKS0_ROM, + HREADYMUXS0_ROM, + HAUSERS0_ROM, + HWUSERS0_ROM, + + // Output port MI1 (outputs to slave 1) + HSELS1_IRAM, + HADDRS1_IRAM, + HTRANSS1_IRAM, + HWRITES1_IRAM, + HSIZES1_IRAM, + HBURSTS1_IRAM, + HPROTS1_IRAM, + HMASTERS1_IRAM, + HWDATAS1_IRAM, + HMASTLOCKS1_IRAM, + HREADYMUXS1_IRAM, + HAUSERS1_IRAM, + HWUSERS1_IRAM, + + // Output port MI2 (outputs to slave 2) + HSELS2_DRAM, + HADDRS2_DRAM, + HTRANSS2_DRAM, + HWRITES2_DRAM, + HSIZES2_DRAM, + HBURSTS2_DRAM, + HPROTS2_DRAM, + HMASTERS2_DRAM, + HWDATAS2_DRAM, + HMASTLOCKS2_DRAM, + HREADYMUXS2_DRAM, + HAUSERS2_DRAM, + HWUSERS2_DRAM, + + // Output port MI3 (outputs to slave 3) + HSELS3_PERIPH, + HADDRS3_PERIPH, + HTRANSS3_PERIPH, + HWRITES3_PERIPH, + HSIZES3_PERIPH, + HBURSTS3_PERIPH, + HPROTS3_PERIPH, + HMASTERS3_PERIPH, + HWDATAS3_PERIPH, + HMASTLOCKS3_PERIPH, + HREADYMUXS3_PERIPH, + HAUSERS3_PERIPH, + HWUSERS3_PERIPH, + + // Input port SI0 (outputs to master 0) + HRDATAM0_CPU_FETCH, + HREADYOUTM0_CPU_FETCH, + HRESPM0_CPU_FETCH, + HRUSERM0_CPU_FETCH, + + // Input port SI1 (outputs to master 1) + HRDATAM1_CPU_LSU, + HREADYOUTM1_CPU_LSU, + HRESPM1_CPU_LSU, + HRUSERM1_CPU_LSU, + + // Input port SI2 (outputs to master 2) + HRDATAM2_CPU_FRONT_PORT, + HREADYOUTM2_CPU_FRONT_PORT, + HRESPM2_CPU_FRONT_PORT, + HRUSERM2_CPU_FRONT_PORT, + + // Scan test dummy signals; not connected until scan insertion + SCANOUTHCLK // Scan Chain Output + + ); + + +// ----------------------------------------------------------------------------- +// Input and Output declarations +// ----------------------------------------------------------------------------- + + // Common AHB signals + input HCLK; // AHB System Clock + input HRESETn; // AHB System Reset + + // System address remapping control + input [3:0] REMAP; // REMAP input + + // Input port SI0 (inputs from master 0) + input HSELM0_CPU_FETCH; // Slave Select + input [31:0] HADDRM0_CPU_FETCH; // Address bus + input [1:0] HTRANSM0_CPU_FETCH; // Transfer type + input HWRITEM0_CPU_FETCH; // Transfer direction + input [2:0] HSIZEM0_CPU_FETCH; // Transfer size + input [2:0] HBURSTM0_CPU_FETCH; // Burst type + input [3:0] HPROTM0_CPU_FETCH; // Protection control + input [3:0] HMASTERM0_CPU_FETCH; // Master select + input [31:0] HWDATAM0_CPU_FETCH; // Write data + input HMASTLOCKM0_CPU_FETCH; // Locked Sequence + input HREADYM0_CPU_FETCH; // Transfer done + input [31:0] HAUSERM0_CPU_FETCH; // Address USER signals + input [31:0] HWUSERM0_CPU_FETCH; // Write-data USER signals + + // Input port SI1 (inputs from master 1) + input HSELM1_CPU_LSU; // Slave Select + input [31:0] HADDRM1_CPU_LSU; // Address bus + input [1:0] HTRANSM1_CPU_LSU; // Transfer type + input HWRITEM1_CPU_LSU; // Transfer direction + input [2:0] HSIZEM1_CPU_LSU; // Transfer size + input [2:0] HBURSTM1_CPU_LSU; // Burst type + input [3:0] HPROTM1_CPU_LSU; // Protection control + input [3:0] HMASTERM1_CPU_LSU; // Master select + input [31:0] HWDATAM1_CPU_LSU; // Write data + input HMASTLOCKM1_CPU_LSU; // Locked Sequence + input HREADYM1_CPU_LSU; // Transfer done + input [31:0] HAUSERM1_CPU_LSU; // Address USER signals + input [31:0] HWUSERM1_CPU_LSU; // Write-data USER signals + + // Input port SI2 (inputs from master 2) + input HSELM2_CPU_FRONT_PORT; // Slave Select + input [31:0] HADDRM2_CPU_FRONT_PORT; // Address bus + input [1:0] HTRANSM2_CPU_FRONT_PORT; // Transfer type + input HWRITEM2_CPU_FRONT_PORT; // Transfer direction + input [2:0] HSIZEM2_CPU_FRONT_PORT; // Transfer size + input [2:0] HBURSTM2_CPU_FRONT_PORT; // Burst type + input [3:0] HPROTM2_CPU_FRONT_PORT; // Protection control + input [3:0] HMASTERM2_CPU_FRONT_PORT; // Master select + input [31:0] HWDATAM2_CPU_FRONT_PORT; // Write data + input HMASTLOCKM2_CPU_FRONT_PORT; // Locked Sequence + input HREADYM2_CPU_FRONT_PORT; // Transfer done + input [31:0] HAUSERM2_CPU_FRONT_PORT; // Address USER signals + input [31:0] HWUSERM2_CPU_FRONT_PORT; // Write-data USER signals + + // Output port MI0 (inputs from slave 0) + input [31:0] HRDATAS0_ROM; // Read data bus + input HREADYOUTS0_ROM; // HREADY feedback + input [1:0] HRESPS0_ROM; // Transfer response + input [31:0] HRUSERS0_ROM; // Read-data USER signals + + // Output port MI1 (inputs from slave 1) + input [31:0] HRDATAS1_IRAM; // Read data bus + input HREADYOUTS1_IRAM; // HREADY feedback + input [1:0] HRESPS1_IRAM; // Transfer response + input [31:0] HRUSERS1_IRAM; // Read-data USER signals + + // Output port MI2 (inputs from slave 2) + input [31:0] HRDATAS2_DRAM; // Read data bus + input HREADYOUTS2_DRAM; // HREADY feedback + input [1:0] HRESPS2_DRAM; // Transfer response + input [31:0] HRUSERS2_DRAM; // Read-data USER signals + + // Output port MI3 (inputs from slave 3) + input [31:0] HRDATAS3_PERIPH; // Read data bus + input HREADYOUTS3_PERIPH; // HREADY feedback + input [1:0] HRESPS3_PERIPH; // Transfer response + input [31:0] HRUSERS3_PERIPH; // Read-data USER signals + + // Scan test dummy signals; not connected until scan insertion + input SCANENABLE; // Scan enable signal + input SCANINHCLK; // HCLK scan input + + + // Output port MI0 (outputs to slave 0) + output HSELS0_ROM; // Slave Select + output [31:0] HADDRS0_ROM; // Address bus + output [1:0] HTRANSS0_ROM; // Transfer type + output HWRITES0_ROM; // Transfer direction + output [2:0] HSIZES0_ROM; // Transfer size + output [2:0] HBURSTS0_ROM; // Burst type + output [3:0] HPROTS0_ROM; // Protection control + output [3:0] HMASTERS0_ROM; // Master select + output [31:0] HWDATAS0_ROM; // Write data + output HMASTLOCKS0_ROM; // Locked Sequence + output HREADYMUXS0_ROM; // Transfer done + output [31:0] HAUSERS0_ROM; // Address USER signals + output [31:0] HWUSERS0_ROM; // Write-data USER signals + + // Output port MI1 (outputs to slave 1) + output HSELS1_IRAM; // Slave Select + output [31:0] HADDRS1_IRAM; // Address bus + output [1:0] HTRANSS1_IRAM; // Transfer type + output HWRITES1_IRAM; // Transfer direction + output [2:0] HSIZES1_IRAM; // Transfer size + output [2:0] HBURSTS1_IRAM; // Burst type + output [3:0] HPROTS1_IRAM; // Protection control + output [3:0] HMASTERS1_IRAM; // Master select + output [31:0] HWDATAS1_IRAM; // Write data + output HMASTLOCKS1_IRAM; // Locked Sequence + output HREADYMUXS1_IRAM; // Transfer done + output [31:0] HAUSERS1_IRAM; // Address USER signals + output [31:0] HWUSERS1_IRAM; // Write-data USER signals + + // Output port MI2 (outputs to slave 2) + output HSELS2_DRAM; // Slave Select + output [31:0] HADDRS2_DRAM; // Address bus + output [1:0] HTRANSS2_DRAM; // Transfer type + output HWRITES2_DRAM; // Transfer direction + output [2:0] HSIZES2_DRAM; // Transfer size + output [2:0] HBURSTS2_DRAM; // Burst type + output [3:0] HPROTS2_DRAM; // Protection control + output [3:0] HMASTERS2_DRAM; // Master select + output [31:0] HWDATAS2_DRAM; // Write data + output HMASTLOCKS2_DRAM; // Locked Sequence + output HREADYMUXS2_DRAM; // Transfer done + output [31:0] HAUSERS2_DRAM; // Address USER signals + output [31:0] HWUSERS2_DRAM; // Write-data USER signals + + // Output port MI3 (outputs to slave 3) + output HSELS3_PERIPH; // Slave Select + output [31:0] HADDRS3_PERIPH; // Address bus + output [1:0] HTRANSS3_PERIPH; // Transfer type + output HWRITES3_PERIPH; // Transfer direction + output [2:0] HSIZES3_PERIPH; // Transfer size + output [2:0] HBURSTS3_PERIPH; // Burst type + output [3:0] HPROTS3_PERIPH; // Protection control + output [3:0] HMASTERS3_PERIPH; // Master select + output [31:0] HWDATAS3_PERIPH; // Write data + output HMASTLOCKS3_PERIPH; // Locked Sequence + output HREADYMUXS3_PERIPH; // Transfer done + output [31:0] HAUSERS3_PERIPH; // Address USER signals + output [31:0] HWUSERS3_PERIPH; // Write-data USER signals + + // Input port SI0 (outputs to master 0) + output [31:0] HRDATAM0_CPU_FETCH; // Read data bus + output HREADYOUTM0_CPU_FETCH; // HREADY feedback + output [1:0] HRESPM0_CPU_FETCH; // Transfer response + output [31:0] HRUSERM0_CPU_FETCH; // Read-data USER signals + + // Input port SI1 (outputs to master 1) + output [31:0] HRDATAM1_CPU_LSU; // Read data bus + output HREADYOUTM1_CPU_LSU; // HREADY feedback + output [1:0] HRESPM1_CPU_LSU; // Transfer response + output [31:0] HRUSERM1_CPU_LSU; // Read-data USER signals + + // Input port SI2 (outputs to master 2) + output [31:0] HRDATAM2_CPU_FRONT_PORT; // Read data bus + output HREADYOUTM2_CPU_FRONT_PORT; // HREADY feedback + output [1:0] HRESPM2_CPU_FRONT_PORT; // Transfer response + output [31:0] HRUSERM2_CPU_FRONT_PORT; // Read-data USER signals + + // Scan test dummy signals; not connected until scan insertion + output SCANOUTHCLK; // Scan Chain Output + + +// ----------------------------------------------------------------------------- +// Wire declarations +// ----------------------------------------------------------------------------- + + // Common AHB signals + wire HCLK; // AHB System Clock + wire HRESETn; // AHB System Reset + + // System address remapping control + wire [3:0] REMAP; // REMAP signal + + // Input Port SI0 + wire HSELM0_CPU_FETCH; // Slave Select + wire [31:0] HADDRM0_CPU_FETCH; // Address bus + wire [1:0] HTRANSM0_CPU_FETCH; // Transfer type + wire HWRITEM0_CPU_FETCH; // Transfer direction + wire [2:0] HSIZEM0_CPU_FETCH; // Transfer size + wire [2:0] HBURSTM0_CPU_FETCH; // Burst type + wire [3:0] HPROTM0_CPU_FETCH; // Protection control + wire [3:0] HMASTERM0_CPU_FETCH; // Master select + wire [31:0] HWDATAM0_CPU_FETCH; // Write data + wire HMASTLOCKM0_CPU_FETCH; // Locked Sequence + wire HREADYM0_CPU_FETCH; // Transfer done + + wire [31:0] HRDATAM0_CPU_FETCH; // Read data bus + wire HREADYOUTM0_CPU_FETCH; // HREADY feedback + wire [1:0] HRESPM0_CPU_FETCH; // Transfer response + wire [31:0] HAUSERM0_CPU_FETCH; // Address USER signals + wire [31:0] HWUSERM0_CPU_FETCH; // Write-data USER signals + wire [31:0] HRUSERM0_CPU_FETCH; // Read-data USER signals + + // Input Port SI1 + wire HSELM1_CPU_LSU; // Slave Select + wire [31:0] HADDRM1_CPU_LSU; // Address bus + wire [1:0] HTRANSM1_CPU_LSU; // Transfer type + wire HWRITEM1_CPU_LSU; // Transfer direction + wire [2:0] HSIZEM1_CPU_LSU; // Transfer size + wire [2:0] HBURSTM1_CPU_LSU; // Burst type + wire [3:0] HPROTM1_CPU_LSU; // Protection control + wire [3:0] HMASTERM1_CPU_LSU; // Master select + wire [31:0] HWDATAM1_CPU_LSU; // Write data + wire HMASTLOCKM1_CPU_LSU; // Locked Sequence + wire HREADYM1_CPU_LSU; // Transfer done + + wire [31:0] HRDATAM1_CPU_LSU; // Read data bus + wire HREADYOUTM1_CPU_LSU; // HREADY feedback + wire [1:0] HRESPM1_CPU_LSU; // Transfer response + wire [31:0] HAUSERM1_CPU_LSU; // Address USER signals + wire [31:0] HWUSERM1_CPU_LSU; // Write-data USER signals + wire [31:0] HRUSERM1_CPU_LSU; // Read-data USER signals + + // Input Port SI2 + wire HSELM2_CPU_FRONT_PORT; // Slave Select + wire [31:0] HADDRM2_CPU_FRONT_PORT; // Address bus + wire [1:0] HTRANSM2_CPU_FRONT_PORT; // Transfer type + wire HWRITEM2_CPU_FRONT_PORT; // Transfer direction + wire [2:0] HSIZEM2_CPU_FRONT_PORT; // Transfer size + wire [2:0] HBURSTM2_CPU_FRONT_PORT; // Burst type + wire [3:0] HPROTM2_CPU_FRONT_PORT; // Protection control + wire [3:0] HMASTERM2_CPU_FRONT_PORT; // Master select + wire [31:0] HWDATAM2_CPU_FRONT_PORT; // Write data + wire HMASTLOCKM2_CPU_FRONT_PORT; // Locked Sequence + wire HREADYM2_CPU_FRONT_PORT; // Transfer done + + wire [31:0] HRDATAM2_CPU_FRONT_PORT; // Read data bus + wire HREADYOUTM2_CPU_FRONT_PORT; // HREADY feedback + wire [1:0] HRESPM2_CPU_FRONT_PORT; // Transfer response + wire [31:0] HAUSERM2_CPU_FRONT_PORT; // Address USER signals + wire [31:0] HWUSERM2_CPU_FRONT_PORT; // Write-data USER signals + wire [31:0] HRUSERM2_CPU_FRONT_PORT; // Read-data USER signals + + // Output Port MI0 + wire HSELS0_ROM; // Slave Select + wire [31:0] HADDRS0_ROM; // Address bus + wire [1:0] HTRANSS0_ROM; // Transfer type + wire HWRITES0_ROM; // Transfer direction + wire [2:0] HSIZES0_ROM; // Transfer size + wire [2:0] HBURSTS0_ROM; // Burst type + wire [3:0] HPROTS0_ROM; // Protection control + wire [3:0] HMASTERS0_ROM; // Master select + wire [31:0] HWDATAS0_ROM; // Write data + wire HMASTLOCKS0_ROM; // Locked Sequence + wire HREADYMUXS0_ROM; // Transfer done + + wire [31:0] HRDATAS0_ROM; // Read data bus + wire HREADYOUTS0_ROM; // HREADY feedback + wire [1:0] HRESPS0_ROM; // Transfer response + wire [31:0] HAUSERS0_ROM; // Address USER signals + wire [31:0] HWUSERS0_ROM; // Write-data USER signals + wire [31:0] HRUSERS0_ROM; // Read-data USER signals + + // Output Port MI1 + wire HSELS1_IRAM; // Slave Select + wire [31:0] HADDRS1_IRAM; // Address bus + wire [1:0] HTRANSS1_IRAM; // Transfer type + wire HWRITES1_IRAM; // Transfer direction + wire [2:0] HSIZES1_IRAM; // Transfer size + wire [2:0] HBURSTS1_IRAM; // Burst type + wire [3:0] HPROTS1_IRAM; // Protection control + wire [3:0] HMASTERS1_IRAM; // Master select + wire [31:0] HWDATAS1_IRAM; // Write data + wire HMASTLOCKS1_IRAM; // Locked Sequence + wire HREADYMUXS1_IRAM; // Transfer done + + wire [31:0] HRDATAS1_IRAM; // Read data bus + wire HREADYOUTS1_IRAM; // HREADY feedback + wire [1:0] HRESPS1_IRAM; // Transfer response + wire [31:0] HAUSERS1_IRAM; // Address USER signals + wire [31:0] HWUSERS1_IRAM; // Write-data USER signals + wire [31:0] HRUSERS1_IRAM; // Read-data USER signals + + // Output Port MI2 + wire HSELS2_DRAM; // Slave Select + wire [31:0] HADDRS2_DRAM; // Address bus + wire [1:0] HTRANSS2_DRAM; // Transfer type + wire HWRITES2_DRAM; // Transfer direction + wire [2:0] HSIZES2_DRAM; // Transfer size + wire [2:0] HBURSTS2_DRAM; // Burst type + wire [3:0] HPROTS2_DRAM; // Protection control + wire [3:0] HMASTERS2_DRAM; // Master select + wire [31:0] HWDATAS2_DRAM; // Write data + wire HMASTLOCKS2_DRAM; // Locked Sequence + wire HREADYMUXS2_DRAM; // Transfer done + + wire [31:0] HRDATAS2_DRAM; // Read data bus + wire HREADYOUTS2_DRAM; // HREADY feedback + wire [1:0] HRESPS2_DRAM; // Transfer response + wire [31:0] HAUSERS2_DRAM; // Address USER signals + wire [31:0] HWUSERS2_DRAM; // Write-data USER signals + wire [31:0] HRUSERS2_DRAM; // Read-data USER signals + + // Output Port MI3 + wire HSELS3_PERIPH; // Slave Select + wire [31:0] HADDRS3_PERIPH; // Address bus + wire [1:0] HTRANSS3_PERIPH; // Transfer type + wire HWRITES3_PERIPH; // Transfer direction + wire [2:0] HSIZES3_PERIPH; // Transfer size + wire [2:0] HBURSTS3_PERIPH; // Burst type + wire [3:0] HPROTS3_PERIPH; // Protection control + wire [3:0] HMASTERS3_PERIPH; // Master select + wire [31:0] HWDATAS3_PERIPH; // Write data + wire HMASTLOCKS3_PERIPH; // Locked Sequence + wire HREADYMUXS3_PERIPH; // Transfer done + + wire [31:0] HRDATAS3_PERIPH; // Read data bus + wire HREADYOUTS3_PERIPH; // HREADY feedback + wire [1:0] HRESPS3_PERIPH; // Transfer response + wire [31:0] HAUSERS3_PERIPH; // Address USER signals + wire [31:0] HWUSERS3_PERIPH; // Write-data USER signals + wire [31:0] HRUSERS3_PERIPH; // Read-data USER signals + + +// ----------------------------------------------------------------------------- +// Signal declarations +// ----------------------------------------------------------------------------- + + // Bus-switch input SI0 + wire i_sel0; // HSEL signal + wire [31:0] i_addr0; // HADDR signal + wire [1:0] i_trans0; // HTRANS signal + wire i_write0; // HWRITE signal + wire [2:0] i_size0; // HSIZE signal + wire [2:0] i_burst0; // HBURST signal + wire [3:0] i_prot0; // HPROTS signal + wire [3:0] i_master0; // HMASTER signal + wire i_mastlock0; // HMASTLOCK signal + wire i_active0; // Active signal + wire i_held_tran0; // HeldTran signal + wire i_readyout0; // Readyout signal + wire [1:0] i_resp0; // Response signal + wire [31:0] i_auser0; // HAUSER signal + + // Bus-switch input SI1 + wire i_sel1; // HSEL signal + wire [31:0] i_addr1; // HADDR signal + wire [1:0] i_trans1; // HTRANS signal + wire i_write1; // HWRITE signal + wire [2:0] i_size1; // HSIZE signal + wire [2:0] i_burst1; // HBURST signal + wire [3:0] i_prot1; // HPROTS signal + wire [3:0] i_master1; // HMASTER signal + wire i_mastlock1; // HMASTLOCK signal + wire i_active1; // Active signal + wire i_held_tran1; // HeldTran signal + wire i_readyout1; // Readyout signal + wire [1:0] i_resp1; // Response signal + wire [31:0] i_auser1; // HAUSER signal + + // Bus-switch input SI2 + wire i_sel2; // HSEL signal + wire [31:0] i_addr2; // HADDR signal + wire [1:0] i_trans2; // HTRANS signal + wire i_write2; // HWRITE signal + wire [2:0] i_size2; // HSIZE signal + wire [2:0] i_burst2; // HBURST signal + wire [3:0] i_prot2; // HPROTS signal + wire [3:0] i_master2; // HMASTER signal + wire i_mastlock2; // HMASTLOCK signal + wire i_active2; // Active signal + wire i_held_tran2; // HeldTran signal + wire i_readyout2; // Readyout signal + wire [1:0] i_resp2; // Response signal + wire [31:0] i_auser2; // HAUSER signal + + // Bus-switch SI0 to MI0 signals + wire i_sel0to0; // Routing selection signal + wire i_active0to0; // Active signal + + // Bus-switch SI0 to MI1 signals + wire i_sel0to1; // Routing selection signal + wire i_active0to1; // Active signal + + // Bus-switch SI1 to MI0 signals + wire i_sel1to0; // Routing selection signal + wire i_active1to0; // Active signal + + // Bus-switch SI1 to MI1 signals + wire i_sel1to1; // Routing selection signal + wire i_active1to1; // Active signal + + // Bus-switch SI1 to MI2 signals + wire i_sel1to2; // Routing selection signal + wire i_active1to2; // Active signal + + // Bus-switch SI1 to MI3 signals + wire i_sel1to3; // Routing selection signal + wire i_active1to3; // Active signal + + // Bus-switch SI2 to MI0 signals + wire i_sel2to0; // Routing selection signal + wire i_active2to0; // Active signal + + // Bus-switch SI2 to MI1 signals + wire i_sel2to1; // Routing selection signal + wire i_active2to1; // Active signal + + // Bus-switch SI2 to MI2 signals + wire i_sel2to2; // Routing selection signal + wire i_active2to2; // Active signal + + wire i_hready_mux_s0_rom; // Internal HREADYMUXM for MI0 + wire i_hready_mux_s1_iram; // Internal HREADYMUXM for MI1 + wire i_hready_mux_s2_dram; // Internal HREADYMUXM for MI2 + wire i_hready_mux_s3_periph; // Internal HREADYMUXM for MI3 + + +// ----------------------------------------------------------------------------- +// Beginning of main code +// ----------------------------------------------------------------------------- + + // Input stage for SI0 + nox_intcon_in u_nox_intcon_in_0 ( + + // Common AHB signals + .HCLK (HCLK), + .HRESETn (HRESETn), + + // Input Port Address/Control Signals + .HSELS (HSELM0_CPU_FETCH), + .HADDRS (HADDRM0_CPU_FETCH), + .HTRANSS (HTRANSM0_CPU_FETCH), + .HWRITES (HWRITEM0_CPU_FETCH), + .HSIZES (HSIZEM0_CPU_FETCH), + .HBURSTS (HBURSTM0_CPU_FETCH), + .HPROTS (HPROTM0_CPU_FETCH), + .HMASTERS (HMASTERM0_CPU_FETCH), + .HMASTLOCKS (HMASTLOCKM0_CPU_FETCH), + .HREADYS (HREADYM0_CPU_FETCH), + .HAUSERS (HAUSERM0_CPU_FETCH), + + // Internal Response + .active_ip (i_active0), + .readyout_ip (i_readyout0), + .resp_ip (i_resp0), + + // Input Port Response + .HREADYOUTS (HREADYOUTM0_CPU_FETCH), + .HRESPS (HRESPM0_CPU_FETCH), + + // Internal Address/Control Signals + .sel_ip (i_sel0), + .addr_ip (i_addr0), + .auser_ip (i_auser0), + .trans_ip (i_trans0), + .write_ip (i_write0), + .size_ip (i_size0), + .burst_ip (i_burst0), + .prot_ip (i_prot0), + .master_ip (i_master0), + .mastlock_ip (i_mastlock0), + .held_tran_ip (i_held_tran0) + + ); + + + // Input stage for SI1 + nox_intcon_in u_nox_intcon_in_1 ( + + // Common AHB signals + .HCLK (HCLK), + .HRESETn (HRESETn), + + // Input Port Address/Control Signals + .HSELS (HSELM1_CPU_LSU), + .HADDRS (HADDRM1_CPU_LSU), + .HTRANSS (HTRANSM1_CPU_LSU), + .HWRITES (HWRITEM1_CPU_LSU), + .HSIZES (HSIZEM1_CPU_LSU), + .HBURSTS (HBURSTM1_CPU_LSU), + .HPROTS (HPROTM1_CPU_LSU), + .HMASTERS (HMASTERM1_CPU_LSU), + .HMASTLOCKS (HMASTLOCKM1_CPU_LSU), + .HREADYS (HREADYM1_CPU_LSU), + .HAUSERS (HAUSERM1_CPU_LSU), + + // Internal Response + .active_ip (i_active1), + .readyout_ip (i_readyout1), + .resp_ip (i_resp1), + + // Input Port Response + .HREADYOUTS (HREADYOUTM1_CPU_LSU), + .HRESPS (HRESPM1_CPU_LSU), + + // Internal Address/Control Signals + .sel_ip (i_sel1), + .addr_ip (i_addr1), + .auser_ip (i_auser1), + .trans_ip (i_trans1), + .write_ip (i_write1), + .size_ip (i_size1), + .burst_ip (i_burst1), + .prot_ip (i_prot1), + .master_ip (i_master1), + .mastlock_ip (i_mastlock1), + .held_tran_ip (i_held_tran1) + + ); + + + // Input stage for SI2 + nox_intcon_in u_nox_intcon_in_2 ( + + // Common AHB signals + .HCLK (HCLK), + .HRESETn (HRESETn), + + // Input Port Address/Control Signals + .HSELS (HSELM2_CPU_FRONT_PORT), + .HADDRS (HADDRM2_CPU_FRONT_PORT), + .HTRANSS (HTRANSM2_CPU_FRONT_PORT), + .HWRITES (HWRITEM2_CPU_FRONT_PORT), + .HSIZES (HSIZEM2_CPU_FRONT_PORT), + .HBURSTS (HBURSTM2_CPU_FRONT_PORT), + .HPROTS (HPROTM2_CPU_FRONT_PORT), + .HMASTERS (HMASTERM2_CPU_FRONT_PORT), + .HMASTLOCKS (HMASTLOCKM2_CPU_FRONT_PORT), + .HREADYS (HREADYM2_CPU_FRONT_PORT), + .HAUSERS (HAUSERM2_CPU_FRONT_PORT), + + // Internal Response + .active_ip (i_active2), + .readyout_ip (i_readyout2), + .resp_ip (i_resp2), + + // Input Port Response + .HREADYOUTS (HREADYOUTM2_CPU_FRONT_PORT), + .HRESPS (HRESPM2_CPU_FRONT_PORT), + + // Internal Address/Control Signals + .sel_ip (i_sel2), + .addr_ip (i_addr2), + .auser_ip (i_auser2), + .trans_ip (i_trans2), + .write_ip (i_write2), + .size_ip (i_size2), + .burst_ip (i_burst2), + .prot_ip (i_prot2), + .master_ip (i_master2), + .mastlock_ip (i_mastlock2), + .held_tran_ip (i_held_tran2) + + ); + + + // Matrix decoder for SI0 + nox_intcon_decM0_CPU_FETCH u_nox_intcon_decm0_cpu_fetch ( + + // Common AHB signals + .HCLK (HCLK), + .HRESETn (HRESETn), + + // Signals from Input stage SI0 + .HREADYS (HREADYM0_CPU_FETCH), + .sel_dec (i_sel0), + .decode_addr_dec (i_addr0[31:10]), // HADDR[9:0] is not decoded + .trans_dec (i_trans0), + + // Control/Response for Output Stage MI0 + .active_dec0 (i_active0to0), + .readyout_dec0 (i_hready_mux_s0_rom), + .resp_dec0 (HRESPS0_ROM), + .rdata_dec0 (HRDATAS0_ROM), + .ruser_dec0 (HRUSERS0_ROM), + + // Control/Response for Output Stage MI1 + .active_dec1 (i_active0to1), + .readyout_dec1 (i_hready_mux_s1_iram), + .resp_dec1 (HRESPS1_IRAM), + .rdata_dec1 (HRDATAS1_IRAM), + .ruser_dec1 (HRUSERS1_IRAM), + + .sel_dec0 (i_sel0to0), + .sel_dec1 (i_sel0to1), + + .active_dec (i_active0), + .HREADYOUTS (i_readyout0), + .HRESPS (i_resp0), + .HRUSERS (HRUSERM0_CPU_FETCH), + .HRDATAS (HRDATAM0_CPU_FETCH) + + ); + + + // Matrix decoder for SI1 + nox_intcon_decM1_CPU_LSU u_nox_intcon_decm1_cpu_lsu ( + + // Common AHB signals + .HCLK (HCLK), + .HRESETn (HRESETn), + + // Signals from Input stage SI1 + .HREADYS (HREADYM1_CPU_LSU), + .sel_dec (i_sel1), + .decode_addr_dec (i_addr1[31:10]), // HADDR[9:0] is not decoded + .trans_dec (i_trans1), + + // Control/Response for Output Stage MI0 + .active_dec0 (i_active1to0), + .readyout_dec0 (i_hready_mux_s0_rom), + .resp_dec0 (HRESPS0_ROM), + .rdata_dec0 (HRDATAS0_ROM), + .ruser_dec0 (HRUSERS0_ROM), + + // Control/Response for Output Stage MI1 + .active_dec1 (i_active1to1), + .readyout_dec1 (i_hready_mux_s1_iram), + .resp_dec1 (HRESPS1_IRAM), + .rdata_dec1 (HRDATAS1_IRAM), + .ruser_dec1 (HRUSERS1_IRAM), + + // Control/Response for Output Stage MI2 + .active_dec2 (i_active1to2), + .readyout_dec2 (i_hready_mux_s2_dram), + .resp_dec2 (HRESPS2_DRAM), + .rdata_dec2 (HRDATAS2_DRAM), + .ruser_dec2 (HRUSERS2_DRAM), + + // Control/Response for Output Stage MI3 + .active_dec3 (i_active1to3), + .readyout_dec3 (i_hready_mux_s3_periph), + .resp_dec3 (HRESPS3_PERIPH), + .rdata_dec3 (HRDATAS3_PERIPH), + .ruser_dec3 (HRUSERS3_PERIPH), + + .sel_dec0 (i_sel1to0), + .sel_dec1 (i_sel1to1), + .sel_dec2 (i_sel1to2), + .sel_dec3 (i_sel1to3), + + .active_dec (i_active1), + .HREADYOUTS (i_readyout1), + .HRESPS (i_resp1), + .HRUSERS (HRUSERM1_CPU_LSU), + .HRDATAS (HRDATAM1_CPU_LSU) + + ); + + + // Matrix decoder for SI2 + nox_intcon_decM2_CPU_FRONT_PORT u_nox_intcon_decm2_cpu_front_port ( + + // Common AHB signals + .HCLK (HCLK), + .HRESETn (HRESETn), + + // Signals from Input stage SI2 + .HREADYS (HREADYM2_CPU_FRONT_PORT), + .sel_dec (i_sel2), + .decode_addr_dec (i_addr2[31:10]), // HADDR[9:0] is not decoded + .trans_dec (i_trans2), + + // Control/Response for Output Stage MI0 + .active_dec0 (i_active2to0), + .readyout_dec0 (i_hready_mux_s0_rom), + .resp_dec0 (HRESPS0_ROM), + .rdata_dec0 (HRDATAS0_ROM), + .ruser_dec0 (HRUSERS0_ROM), + + // Control/Response for Output Stage MI1 + .active_dec1 (i_active2to1), + .readyout_dec1 (i_hready_mux_s1_iram), + .resp_dec1 (HRESPS1_IRAM), + .rdata_dec1 (HRDATAS1_IRAM), + .ruser_dec1 (HRUSERS1_IRAM), + + // Control/Response for Output Stage MI2 + .active_dec2 (i_active2to2), + .readyout_dec2 (i_hready_mux_s2_dram), + .resp_dec2 (HRESPS2_DRAM), + .rdata_dec2 (HRDATAS2_DRAM), + .ruser_dec2 (HRUSERS2_DRAM), + + .sel_dec0 (i_sel2to0), + .sel_dec1 (i_sel2to1), + .sel_dec2 (i_sel2to2), + + .active_dec (i_active2), + .HREADYOUTS (i_readyout2), + .HRESPS (i_resp2), + .HRUSERS (HRUSERM2_CPU_FRONT_PORT), + .HRDATAS (HRDATAM2_CPU_FRONT_PORT) + + ); + + + // Output stage for MI0 + nox_intcon_outS0_ROM u_nox_intcon_outs0_rom_0 ( + + // Common AHB signals + .HCLK (HCLK), + .HRESETn (HRESETn), + + // Port 0 Signals + .sel_op0 (i_sel0to0), + .addr_op0 (i_addr0), + .auser_op0 (i_auser0), + .trans_op0 (i_trans0), + .write_op0 (i_write0), + .size_op0 (i_size0), + .burst_op0 (i_burst0), + .prot_op0 (i_prot0), + .master_op0 (i_master0), + .mastlock_op0 (i_mastlock0), + .wdata_op0 (HWDATAM0_CPU_FETCH), + .wuser_op0 (HWUSERM0_CPU_FETCH), + .held_tran_op0 (i_held_tran0), + + // Port 1 Signals + .sel_op1 (i_sel1to0), + .addr_op1 (i_addr1), + .auser_op1 (i_auser1), + .trans_op1 (i_trans1), + .write_op1 (i_write1), + .size_op1 (i_size1), + .burst_op1 (i_burst1), + .prot_op1 (i_prot1), + .master_op1 (i_master1), + .mastlock_op1 (i_mastlock1), + .wdata_op1 (HWDATAM1_CPU_LSU), + .wuser_op1 (HWUSERM1_CPU_LSU), + .held_tran_op1 (i_held_tran1), + + // Port 2 Signals + .sel_op2 (i_sel2to0), + .addr_op2 (i_addr2), + .auser_op2 (i_auser2), + .trans_op2 (i_trans2), + .write_op2 (i_write2), + .size_op2 (i_size2), + .burst_op2 (i_burst2), + .prot_op2 (i_prot2), + .master_op2 (i_master2), + .mastlock_op2 (i_mastlock2), + .wdata_op2 (HWDATAM2_CPU_FRONT_PORT), + .wuser_op2 (HWUSERM2_CPU_FRONT_PORT), + .held_tran_op2 (i_held_tran2), + + // Slave read data and response + .HREADYOUTM (HREADYOUTS0_ROM), + + .active_op0 (i_active0to0), + .active_op1 (i_active1to0), + .active_op2 (i_active2to0), + + // Slave Address/Control Signals + .HSELM (HSELS0_ROM), + .HADDRM (HADDRS0_ROM), + .HAUSERM (HAUSERS0_ROM), + .HTRANSM (HTRANSS0_ROM), + .HWRITEM (HWRITES0_ROM), + .HSIZEM (HSIZES0_ROM), + .HBURSTM (HBURSTS0_ROM), + .HPROTM (HPROTS0_ROM), + .HMASTERM (HMASTERS0_ROM), + .HMASTLOCKM (HMASTLOCKS0_ROM), + .HREADYMUXM (i_hready_mux_s0_rom), + .HWUSERM (HWUSERS0_ROM), + .HWDATAM (HWDATAS0_ROM) + + ); + + // Drive output with internal version + assign HREADYMUXS0_ROM = i_hready_mux_s0_rom; + + + // Output stage for MI1 + nox_intcon_outS1_IRAM u_nox_intcon_outs1_iram_1 ( + + // Common AHB signals + .HCLK (HCLK), + .HRESETn (HRESETn), + + // Port 0 Signals + .sel_op0 (i_sel0to1), + .addr_op0 (i_addr0), + .auser_op0 (i_auser0), + .trans_op0 (i_trans0), + .write_op0 (i_write0), + .size_op0 (i_size0), + .burst_op0 (i_burst0), + .prot_op0 (i_prot0), + .master_op0 (i_master0), + .mastlock_op0 (i_mastlock0), + .wdata_op0 (HWDATAM0_CPU_FETCH), + .wuser_op0 (HWUSERM0_CPU_FETCH), + .held_tran_op0 (i_held_tran0), + + // Port 1 Signals + .sel_op1 (i_sel1to1), + .addr_op1 (i_addr1), + .auser_op1 (i_auser1), + .trans_op1 (i_trans1), + .write_op1 (i_write1), + .size_op1 (i_size1), + .burst_op1 (i_burst1), + .prot_op1 (i_prot1), + .master_op1 (i_master1), + .mastlock_op1 (i_mastlock1), + .wdata_op1 (HWDATAM1_CPU_LSU), + .wuser_op1 (HWUSERM1_CPU_LSU), + .held_tran_op1 (i_held_tran1), + + // Port 2 Signals + .sel_op2 (i_sel2to1), + .addr_op2 (i_addr2), + .auser_op2 (i_auser2), + .trans_op2 (i_trans2), + .write_op2 (i_write2), + .size_op2 (i_size2), + .burst_op2 (i_burst2), + .prot_op2 (i_prot2), + .master_op2 (i_master2), + .mastlock_op2 (i_mastlock2), + .wdata_op2 (HWDATAM2_CPU_FRONT_PORT), + .wuser_op2 (HWUSERM2_CPU_FRONT_PORT), + .held_tran_op2 (i_held_tran2), + + // Slave read data and response + .HREADYOUTM (HREADYOUTS1_IRAM), + + .active_op0 (i_active0to1), + .active_op1 (i_active1to1), + .active_op2 (i_active2to1), + + // Slave Address/Control Signals + .HSELM (HSELS1_IRAM), + .HADDRM (HADDRS1_IRAM), + .HAUSERM (HAUSERS1_IRAM), + .HTRANSM (HTRANSS1_IRAM), + .HWRITEM (HWRITES1_IRAM), + .HSIZEM (HSIZES1_IRAM), + .HBURSTM (HBURSTS1_IRAM), + .HPROTM (HPROTS1_IRAM), + .HMASTERM (HMASTERS1_IRAM), + .HMASTLOCKM (HMASTLOCKS1_IRAM), + .HREADYMUXM (i_hready_mux_s1_iram), + .HWUSERM (HWUSERS1_IRAM), + .HWDATAM (HWDATAS1_IRAM) + + ); + + // Drive output with internal version + assign HREADYMUXS1_IRAM = i_hready_mux_s1_iram; + + + // Output stage for MI2 + nox_intcon_outS2_DRAM u_nox_intcon_outs2_dram_2 ( + + // Common AHB signals + .HCLK (HCLK), + .HRESETn (HRESETn), + + // Port 1 Signals + .sel_op1 (i_sel1to2), + .addr_op1 (i_addr1), + .auser_op1 (i_auser1), + .trans_op1 (i_trans1), + .write_op1 (i_write1), + .size_op1 (i_size1), + .burst_op1 (i_burst1), + .prot_op1 (i_prot1), + .master_op1 (i_master1), + .mastlock_op1 (i_mastlock1), + .wdata_op1 (HWDATAM1_CPU_LSU), + .wuser_op1 (HWUSERM1_CPU_LSU), + .held_tran_op1 (i_held_tran1), + + // Port 2 Signals + .sel_op2 (i_sel2to2), + .addr_op2 (i_addr2), + .auser_op2 (i_auser2), + .trans_op2 (i_trans2), + .write_op2 (i_write2), + .size_op2 (i_size2), + .burst_op2 (i_burst2), + .prot_op2 (i_prot2), + .master_op2 (i_master2), + .mastlock_op2 (i_mastlock2), + .wdata_op2 (HWDATAM2_CPU_FRONT_PORT), + .wuser_op2 (HWUSERM2_CPU_FRONT_PORT), + .held_tran_op2 (i_held_tran2), + + // Slave read data and response + .HREADYOUTM (HREADYOUTS2_DRAM), + + .active_op1 (i_active1to2), + .active_op2 (i_active2to2), + + // Slave Address/Control Signals + .HSELM (HSELS2_DRAM), + .HADDRM (HADDRS2_DRAM), + .HAUSERM (HAUSERS2_DRAM), + .HTRANSM (HTRANSS2_DRAM), + .HWRITEM (HWRITES2_DRAM), + .HSIZEM (HSIZES2_DRAM), + .HBURSTM (HBURSTS2_DRAM), + .HPROTM (HPROTS2_DRAM), + .HMASTERM (HMASTERS2_DRAM), + .HMASTLOCKM (HMASTLOCKS2_DRAM), + .HREADYMUXM (i_hready_mux_s2_dram), + .HWUSERM (HWUSERS2_DRAM), + .HWDATAM (HWDATAS2_DRAM) + + ); + + // Drive output with internal version + assign HREADYMUXS2_DRAM = i_hready_mux_s2_dram; + + + // Output stage for MI3 + nox_intcon_outS3_PERIPH u_nox_intcon_outs3_periph_3 ( + + // Common AHB signals + .HCLK (HCLK), + .HRESETn (HRESETn), + + // Port 1 Signals + .sel_op1 (i_sel1to3), + .addr_op1 (i_addr1), + .auser_op1 (i_auser1), + .trans_op1 (i_trans1), + .write_op1 (i_write1), + .size_op1 (i_size1), + .burst_op1 (i_burst1), + .prot_op1 (i_prot1), + .master_op1 (i_master1), + .mastlock_op1 (i_mastlock1), + .wdata_op1 (HWDATAM1_CPU_LSU), + .wuser_op1 (HWUSERM1_CPU_LSU), + .held_tran_op1 (i_held_tran1), + + // Slave read data and response + .HREADYOUTM (HREADYOUTS3_PERIPH), + + .active_op1 (i_active1to3), + + // Slave Address/Control Signals + .HSELM (HSELS3_PERIPH), + .HADDRM (HADDRS3_PERIPH), + .HAUSERM (HAUSERS3_PERIPH), + .HTRANSM (HTRANSS3_PERIPH), + .HWRITEM (HWRITES3_PERIPH), + .HSIZEM (HSIZES3_PERIPH), + .HBURSTM (HBURSTS3_PERIPH), + .HPROTM (HPROTS3_PERIPH), + .HMASTERM (HMASTERS3_PERIPH), + .HMASTLOCKM (HMASTLOCKS3_PERIPH), + .HREADYMUXM (i_hready_mux_s3_periph), + .HWUSERM (HWUSERS3_PERIPH), + .HWDATAM (HWDATAS3_PERIPH) + + ); + + // Drive output with internal version + assign HREADYMUXS3_PERIPH = i_hready_mux_s3_periph; + + +endmodule + +// --================================= End ===================================-- diff --git a/xlnx/rtl/ahb_interconnect/nox_intcon.xml b/xlnx/rtl/ahb_interconnect/nox_intcon.xml new file mode 100644 index 0000000..4a2b472 --- /dev/null +++ b/xlnx/rtl/ahb_interconnect/nox_intcon.xml @@ -0,0 +1,51 @@ + + + + + ahb2 + round + 32 + 32 + 32 + + nox_intcon + nox_intcon_in + nox_intcon_dec + nox_intcon_arb + nox_intcon_out + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/xlnx/rtl/ahb_interconnect/nox_intcon_arbS0_ROM.v b/xlnx/rtl/ahb_interconnect/nox_intcon_arbS0_ROM.v new file mode 100644 index 0000000..e18d84d --- /dev/null +++ b/xlnx/rtl/ahb_interconnect/nox_intcon_arbS0_ROM.v @@ -0,0 +1,384 @@ +//----------------------------------------------------------------------------- +// The confidential and proprietary information contained in this file may +// only be used by a person authorised under and to the extent permitted +// by a subsisting licensing agreement from ARM Limited. +// +// (C) COPYRIGHT 2001-2013-2024 ARM Limited. +// ALL RIGHTS RESERVED +// +// This entire notice must be reproduced on all copies of this file +// and copies of this file may only be made by a person if such person is +// permitted to do so under the terms of a subsisting license agreement +// from ARM Limited. +// +// SVN Information +// +// Checked In : $Date: 2012-10-15 18:01:36 +0100 (Mon, 15 Oct 2012) $ +// +// Revision : $Revision: 225465 $ +// +// Release Information : Cortex-M System Design Kit-r1p0-01rel0 +// +//----------------------------------------------------------------------------- +// +//----------------------------------------------------------------------------- +// Abstract : The Output Arbitration is used to determine which +// of the input stages will be given access to the +// shared slave. +// +// Notes : The bus matrix has sparse connectivity. +// +//----------------------------------------------------------------------------- + +`timescale 1ns/1ps + +module nox_intcon_arbS0_ROM ( + + // Common AHB signals + HCLK , + HRESETn, + + // Input port request signals + req_port0, + req_port1, + req_port2, + + HREADYM, + HSELM, + HTRANSM, + HBURSTM, + HMASTLOCKM, + + // Arbiter outputs + addr_in_port, + no_port + + ); + + +// ----------------------------------------------------------------------------- +// Input and Output declarations +// ----------------------------------------------------------------------------- + + // Common AHB signals + input HCLK; // AHB system clock + input HRESETn; // AHB system reset + input req_port0; // Port 0 request signal + input req_port1; // Port 1 request signal + input req_port2; // Port 2 request signal + input HREADYM; // Transfer done + input HSELM; // Slave select line + input [1:0] HTRANSM; // Transfer type + input [2:0] HBURSTM; // Burst type + input HMASTLOCKM; // Locked transfer + output [1:0] addr_in_port; // Port address input + output no_port; // No port selected signal + + +// ----------------------------------------------------------------------------- +// Constant declarations +// ----------------------------------------------------------------------------- +// HTRANS transfer type signal encoding +`define TRN_IDLE 2'b00 // Idle transfer +`define TRN_BUSY 2'b01 // Busy transfer +`define TRN_NONSEQ 2'b10 // NonSequential transfer +`define TRN_SEQ 2'b11 // Sequential transfer + +// HBURST transfer type signal encoding +`define BUR_SINGLE 3'b000 // Single +`define BUR_INCR 3'b001 // Incremental +`define BUR_WRAP4 3'b010 // 4-beat wrap +`define BUR_INCR4 3'b011 // 4-beat Incr +`define BUR_WRAP8 3'b100 // 8-beat wrap +`define BUR_INCR8 3'b101 // 8-beat Incr +`define BUR_WRAP16 3'b110 // 16-beat Wrap +`define BUR_INCR16 3'b111 // 16-beat Incr + + +// ----------------------------------------------------------------------------- +// Wire declarations +// ----------------------------------------------------------------------------- + wire HCLK; // AHB system clock + wire HRESETn; // AHB system reset + wire req_port0; // Port 0 request signal + wire req_port1; // Port 1 request signal + wire req_port2; // Port 2 request signal + wire HREADYM; // Transfer done + wire HSELM; // Slave select line + wire [1:0] HTRANSM; // Transfer type + wire [2:0] HBURSTM; // Burst type + wire HMASTLOCKM; // Locked transfer + wire [1:0] addr_in_port; // Address input port + wire no_port; // No port selected signal + + +// ----------------------------------------------------------------------------- +// Signal declarations +// ----------------------------------------------------------------------------- + reg [1:0] next_addr_in_port; // D-input of addr_in_port + reg next_no_port; // D-input of no_port + reg [1:0] i_addr_in_port; // Internal version of addr_in_port + reg i_no_port; // Internal version of no_port + + // Burst counter logic + reg [3:0] next_burst_remain; // D-input of reg_burst_remain + reg [3:0] reg_burst_remain; // Burst counter + reg next_burst_hold; // D-input of reg_burst_hold + reg reg_burst_hold; // Burst hold signal + + // INCR burst logic + reg [1:0] reg_early_incr_count; // Counts number of INCR bursts terminated + // earlier than 4-beats + wire [1:0] next_early_incr_count; // D-input for reg_early_incr_count + + +// ----------------------------------------------------------------------------- +// Beginning of main code +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +// BURST TRANSFER COUNTER +// ----------------------------------------------------------------------------- +// +// The Burst counter is used to count down from the number of transfers the +// master should perform and when the counter reaches zero the bus may be +// passed to another master. +// +// reg_burst_remain indicates the number of transfers remaining in the +// current fixed length burst after the current transfer. +// reg_burst_hold is set when transfers remain in a burst and causes the arbitration +// to be held in the current cycle + + always @ (HTRANSM or HSELM or HBURSTM or reg_burst_remain or reg_burst_hold or + reg_early_incr_count) + begin : p_next_burst_remain_comb + // Force the Burst logic to reset if this port is de-selected. This would + // otherwise cause problems in several situations, e.g.: + // 1. The master performs 2 fixed-length bursts back-to-back, but the + // second is to an alternate output port + // 2. The master is performing a fixed-length burst but is de-granted mid- + // way by a local AHB Arbiter + if (~HSELM) + begin + next_burst_remain = 4'b0000; + next_burst_hold = 1'b0; + end + + // Burst logic is initialised on a NONSEQ transfer (i.e. start of burst) + // IDLE transfers cause the logic to reset + // BUSY transfers pause the decrementer + // SEQ transfers decrement the counter + else + case (HTRANSM) + + `TRN_NONSEQ : begin + case (HBURSTM) + `BUR_INCR16, `BUR_WRAP16 : begin + next_burst_remain = 4'b1110; + next_burst_hold = 1'b1; + end // case: BUR_INCR16 | BUR_WRAP16 + + `BUR_INCR8, `BUR_WRAP8 : begin + next_burst_remain = 4'b0110; + next_burst_hold = 1'b1; + end // case: BUR_INCR8 | BUR_WRAP8 + + `BUR_INCR4, `BUR_WRAP4 : begin + next_burst_remain = 4'b0010; + next_burst_hold = 1'b1; + end // case: BUR_INCR4 | BUR_WRAP4 + + `BUR_INCR : begin + if (reg_early_incr_count == 2'b01) + begin + next_burst_remain = 4'b0000; + next_burst_hold = 1'b0; + end + else + begin + next_burst_remain = 4'b0010; + next_burst_hold = 1'b1; + end + end // case: BUR_INCR + + `BUR_SINGLE : begin + next_burst_remain = 4'b0000; + next_burst_hold = 1'b0; + end // case: BUR_SINGLE | BUR_INCR + + default : begin + next_burst_remain = 4'bxxxx; + next_burst_hold = 1'bx; + end // case: default + + endcase // case(HBURSTM) + end // case: `TRN_NONSEQ + + `TRN_SEQ : begin + if (reg_burst_remain == 4'b0000) + begin + next_burst_hold = 1'b0; + next_burst_remain = 4'b0000; + end + else + begin + next_burst_hold = reg_burst_hold; + next_burst_remain = reg_burst_remain - 1'b1; + end + end // case: `TRN_SEQ + + `TRN_BUSY : begin + next_burst_remain = reg_burst_remain; + next_burst_hold = reg_burst_hold; + end // case: `TRN_BUSY + + `TRN_IDLE : begin + next_burst_remain = 4'b0000; + next_burst_hold = 1'b0; + end // case: `TRN_IDLE + + default : begin + next_burst_remain = 4'bxxxx; + next_burst_hold = 1'bx; + end // case: default + + endcase // case(HTRANSM) + end // block: p_next_burst_remain_comb + + + // reg_early_incr_count counts the number of bursts which have terminated + // earlier than the defined arbitration point: this is primarily + // intended to detect back-to-back INCR bursts which are less than 4 + // beats long. If such bursts are not counted then theoretically a + // sequence of e.g. 3-beat INCR bursts from a master would lock the + // arbitration scheme indefinitely. + + assign next_early_incr_count = (!next_burst_hold) ? 2'b00 : + (reg_burst_hold & (HTRANSM == `TRN_NONSEQ)) ? + reg_early_incr_count + 1'b1 : + reg_early_incr_count; + + // Sequential process + always @ (negedge HRESETn or posedge HCLK) + begin : p_burst_seq + if (~HRESETn) + begin + reg_burst_remain <= 4'b0000; + reg_burst_hold <= 1'b0; + reg_early_incr_count <= 2'b00; + end // if (HRESETn == 1'b0) + else + if (HREADYM) + begin + reg_burst_remain <= next_burst_remain; + reg_burst_hold <= next_burst_hold; + reg_early_incr_count <= next_early_incr_count; + end + end // block: p_burst_seq + + +// ----------------------------------------------------------------------------- +// Port Selection +// ----------------------------------------------------------------------------- +// The Output Arbitration function looks at all the requests to use the +// output port and determines which is the highest priority request. This +// version of the arbitration logic uses a round-robin scheme. +// For example if port 1 is currently in use then the arbiter will first check +// if port 2 requires access, then it checks port 3, then port 4 etc. When +// port 2 is currently in use it will check port 3 first then port 4 and +// all remaining ports, before finally checking port 1. +// If none of the input ports are requesting then the current port will +// remain active if it is performing IDLE transfers to the selected slave. If +// this is not the case then the no_port signal will be asserted which +// indicates that no input port should be selected. + + always @ ( + req_port0 or + req_port1 or + req_port2 or + HMASTLOCKM or next_burst_hold or HSELM or i_no_port or i_addr_in_port + ) + begin : p_sel_port_comb + // Default values are used for next_no_port and next_addr_in_port + next_no_port = 1'b0; + next_addr_in_port = i_addr_in_port; + + if ( HMASTLOCKM | next_burst_hold ) + next_addr_in_port = i_addr_in_port; + else if (i_no_port) + begin + if (req_port0) + next_addr_in_port = 2'b00; + else if (req_port1) + next_addr_in_port = 2'b01; + else if (req_port2) + next_addr_in_port = 2'b10; + else + next_no_port = 1'b1; + end + else + case (i_addr_in_port) + 2'b00 : begin + if (req_port1) + next_addr_in_port = 2'b01; + else if (req_port2) + next_addr_in_port = 2'b10; + else if (HSELM) + next_addr_in_port = 2'b00; + else + next_no_port = 1'b1; + end + + 2'b01 : begin + if (req_port2) + next_addr_in_port = 2'b10; + else if (req_port0) + next_addr_in_port = 2'b00; + else if (HSELM) + next_addr_in_port = 2'b01; + else + next_no_port = 1'b1; + end + + 2'b10 : begin + if (req_port0) + next_addr_in_port = 2'b00; + else if (req_port1) + next_addr_in_port = 2'b01; + else if (HSELM) + next_addr_in_port = 2'b10; + else + next_no_port = 1'b1; + end + + default : begin + next_addr_in_port = {2{1'bx}}; + next_no_port = 1'bx; + end + endcase + end + + // Sequential process + always @ (negedge HRESETn or posedge HCLK) + begin : p_addr_in_port_reg + if (~HRESETn) + begin + i_no_port <= 1'b1; + i_addr_in_port <= {2{1'b0}}; + end + else + if (HREADYM) + begin + i_no_port <= next_no_port; + i_addr_in_port <= next_addr_in_port; + end + end + + // Drive outputs with internal versions + assign addr_in_port = i_addr_in_port; + assign no_port = i_no_port; + + +endmodule + +// --================================= End ===================================-- diff --git a/xlnx/rtl/ahb_interconnect/nox_intcon_arbS1_IRAM.v b/xlnx/rtl/ahb_interconnect/nox_intcon_arbS1_IRAM.v new file mode 100644 index 0000000..0daf8c6 --- /dev/null +++ b/xlnx/rtl/ahb_interconnect/nox_intcon_arbS1_IRAM.v @@ -0,0 +1,384 @@ +//----------------------------------------------------------------------------- +// The confidential and proprietary information contained in this file may +// only be used by a person authorised under and to the extent permitted +// by a subsisting licensing agreement from ARM Limited. +// +// (C) COPYRIGHT 2001-2013-2024 ARM Limited. +// ALL RIGHTS RESERVED +// +// This entire notice must be reproduced on all copies of this file +// and copies of this file may only be made by a person if such person is +// permitted to do so under the terms of a subsisting license agreement +// from ARM Limited. +// +// SVN Information +// +// Checked In : $Date: 2012-10-15 18:01:36 +0100 (Mon, 15 Oct 2012) $ +// +// Revision : $Revision: 225465 $ +// +// Release Information : Cortex-M System Design Kit-r1p0-01rel0 +// +//----------------------------------------------------------------------------- +// +//----------------------------------------------------------------------------- +// Abstract : The Output Arbitration is used to determine which +// of the input stages will be given access to the +// shared slave. +// +// Notes : The bus matrix has sparse connectivity. +// +//----------------------------------------------------------------------------- + +`timescale 1ns/1ps + +module nox_intcon_arbS1_IRAM ( + + // Common AHB signals + HCLK , + HRESETn, + + // Input port request signals + req_port0, + req_port1, + req_port2, + + HREADYM, + HSELM, + HTRANSM, + HBURSTM, + HMASTLOCKM, + + // Arbiter outputs + addr_in_port, + no_port + + ); + + +// ----------------------------------------------------------------------------- +// Input and Output declarations +// ----------------------------------------------------------------------------- + + // Common AHB signals + input HCLK; // AHB system clock + input HRESETn; // AHB system reset + input req_port0; // Port 0 request signal + input req_port1; // Port 1 request signal + input req_port2; // Port 2 request signal + input HREADYM; // Transfer done + input HSELM; // Slave select line + input [1:0] HTRANSM; // Transfer type + input [2:0] HBURSTM; // Burst type + input HMASTLOCKM; // Locked transfer + output [1:0] addr_in_port; // Port address input + output no_port; // No port selected signal + + +// ----------------------------------------------------------------------------- +// Constant declarations +// ----------------------------------------------------------------------------- +// HTRANS transfer type signal encoding +`define TRN_IDLE 2'b00 // Idle transfer +`define TRN_BUSY 2'b01 // Busy transfer +`define TRN_NONSEQ 2'b10 // NonSequential transfer +`define TRN_SEQ 2'b11 // Sequential transfer + +// HBURST transfer type signal encoding +`define BUR_SINGLE 3'b000 // Single +`define BUR_INCR 3'b001 // Incremental +`define BUR_WRAP4 3'b010 // 4-beat wrap +`define BUR_INCR4 3'b011 // 4-beat Incr +`define BUR_WRAP8 3'b100 // 8-beat wrap +`define BUR_INCR8 3'b101 // 8-beat Incr +`define BUR_WRAP16 3'b110 // 16-beat Wrap +`define BUR_INCR16 3'b111 // 16-beat Incr + + +// ----------------------------------------------------------------------------- +// Wire declarations +// ----------------------------------------------------------------------------- + wire HCLK; // AHB system clock + wire HRESETn; // AHB system reset + wire req_port0; // Port 0 request signal + wire req_port1; // Port 1 request signal + wire req_port2; // Port 2 request signal + wire HREADYM; // Transfer done + wire HSELM; // Slave select line + wire [1:0] HTRANSM; // Transfer type + wire [2:0] HBURSTM; // Burst type + wire HMASTLOCKM; // Locked transfer + wire [1:0] addr_in_port; // Address input port + wire no_port; // No port selected signal + + +// ----------------------------------------------------------------------------- +// Signal declarations +// ----------------------------------------------------------------------------- + reg [1:0] next_addr_in_port; // D-input of addr_in_port + reg next_no_port; // D-input of no_port + reg [1:0] i_addr_in_port; // Internal version of addr_in_port + reg i_no_port; // Internal version of no_port + + // Burst counter logic + reg [3:0] next_burst_remain; // D-input of reg_burst_remain + reg [3:0] reg_burst_remain; // Burst counter + reg next_burst_hold; // D-input of reg_burst_hold + reg reg_burst_hold; // Burst hold signal + + // INCR burst logic + reg [1:0] reg_early_incr_count; // Counts number of INCR bursts terminated + // earlier than 4-beats + wire [1:0] next_early_incr_count; // D-input for reg_early_incr_count + + +// ----------------------------------------------------------------------------- +// Beginning of main code +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +// BURST TRANSFER COUNTER +// ----------------------------------------------------------------------------- +// +// The Burst counter is used to count down from the number of transfers the +// master should perform and when the counter reaches zero the bus may be +// passed to another master. +// +// reg_burst_remain indicates the number of transfers remaining in the +// current fixed length burst after the current transfer. +// reg_burst_hold is set when transfers remain in a burst and causes the arbitration +// to be held in the current cycle + + always @ (HTRANSM or HSELM or HBURSTM or reg_burst_remain or reg_burst_hold or + reg_early_incr_count) + begin : p_next_burst_remain_comb + // Force the Burst logic to reset if this port is de-selected. This would + // otherwise cause problems in several situations, e.g.: + // 1. The master performs 2 fixed-length bursts back-to-back, but the + // second is to an alternate output port + // 2. The master is performing a fixed-length burst but is de-granted mid- + // way by a local AHB Arbiter + if (~HSELM) + begin + next_burst_remain = 4'b0000; + next_burst_hold = 1'b0; + end + + // Burst logic is initialised on a NONSEQ transfer (i.e. start of burst) + // IDLE transfers cause the logic to reset + // BUSY transfers pause the decrementer + // SEQ transfers decrement the counter + else + case (HTRANSM) + + `TRN_NONSEQ : begin + case (HBURSTM) + `BUR_INCR16, `BUR_WRAP16 : begin + next_burst_remain = 4'b1110; + next_burst_hold = 1'b1; + end // case: BUR_INCR16 | BUR_WRAP16 + + `BUR_INCR8, `BUR_WRAP8 : begin + next_burst_remain = 4'b0110; + next_burst_hold = 1'b1; + end // case: BUR_INCR8 | BUR_WRAP8 + + `BUR_INCR4, `BUR_WRAP4 : begin + next_burst_remain = 4'b0010; + next_burst_hold = 1'b1; + end // case: BUR_INCR4 | BUR_WRAP4 + + `BUR_INCR : begin + if (reg_early_incr_count == 2'b01) + begin + next_burst_remain = 4'b0000; + next_burst_hold = 1'b0; + end + else + begin + next_burst_remain = 4'b0010; + next_burst_hold = 1'b1; + end + end // case: BUR_INCR + + `BUR_SINGLE : begin + next_burst_remain = 4'b0000; + next_burst_hold = 1'b0; + end // case: BUR_SINGLE | BUR_INCR + + default : begin + next_burst_remain = 4'bxxxx; + next_burst_hold = 1'bx; + end // case: default + + endcase // case(HBURSTM) + end // case: `TRN_NONSEQ + + `TRN_SEQ : begin + if (reg_burst_remain == 4'b0000) + begin + next_burst_hold = 1'b0; + next_burst_remain = 4'b0000; + end + else + begin + next_burst_hold = reg_burst_hold; + next_burst_remain = reg_burst_remain - 1'b1; + end + end // case: `TRN_SEQ + + `TRN_BUSY : begin + next_burst_remain = reg_burst_remain; + next_burst_hold = reg_burst_hold; + end // case: `TRN_BUSY + + `TRN_IDLE : begin + next_burst_remain = 4'b0000; + next_burst_hold = 1'b0; + end // case: `TRN_IDLE + + default : begin + next_burst_remain = 4'bxxxx; + next_burst_hold = 1'bx; + end // case: default + + endcase // case(HTRANSM) + end // block: p_next_burst_remain_comb + + + // reg_early_incr_count counts the number of bursts which have terminated + // earlier than the defined arbitration point: this is primarily + // intended to detect back-to-back INCR bursts which are less than 4 + // beats long. If such bursts are not counted then theoretically a + // sequence of e.g. 3-beat INCR bursts from a master would lock the + // arbitration scheme indefinitely. + + assign next_early_incr_count = (!next_burst_hold) ? 2'b00 : + (reg_burst_hold & (HTRANSM == `TRN_NONSEQ)) ? + reg_early_incr_count + 1'b1 : + reg_early_incr_count; + + // Sequential process + always @ (negedge HRESETn or posedge HCLK) + begin : p_burst_seq + if (~HRESETn) + begin + reg_burst_remain <= 4'b0000; + reg_burst_hold <= 1'b0; + reg_early_incr_count <= 2'b00; + end // if (HRESETn == 1'b0) + else + if (HREADYM) + begin + reg_burst_remain <= next_burst_remain; + reg_burst_hold <= next_burst_hold; + reg_early_incr_count <= next_early_incr_count; + end + end // block: p_burst_seq + + +// ----------------------------------------------------------------------------- +// Port Selection +// ----------------------------------------------------------------------------- +// The Output Arbitration function looks at all the requests to use the +// output port and determines which is the highest priority request. This +// version of the arbitration logic uses a round-robin scheme. +// For example if port 1 is currently in use then the arbiter will first check +// if port 2 requires access, then it checks port 3, then port 4 etc. When +// port 2 is currently in use it will check port 3 first then port 4 and +// all remaining ports, before finally checking port 1. +// If none of the input ports are requesting then the current port will +// remain active if it is performing IDLE transfers to the selected slave. If +// this is not the case then the no_port signal will be asserted which +// indicates that no input port should be selected. + + always @ ( + req_port0 or + req_port1 or + req_port2 or + HMASTLOCKM or next_burst_hold or HSELM or i_no_port or i_addr_in_port + ) + begin : p_sel_port_comb + // Default values are used for next_no_port and next_addr_in_port + next_no_port = 1'b0; + next_addr_in_port = i_addr_in_port; + + if ( HMASTLOCKM | next_burst_hold ) + next_addr_in_port = i_addr_in_port; + else if (i_no_port) + begin + if (req_port0) + next_addr_in_port = 2'b00; + else if (req_port1) + next_addr_in_port = 2'b01; + else if (req_port2) + next_addr_in_port = 2'b10; + else + next_no_port = 1'b1; + end + else + case (i_addr_in_port) + 2'b00 : begin + if (req_port1) + next_addr_in_port = 2'b01; + else if (req_port2) + next_addr_in_port = 2'b10; + else if (HSELM) + next_addr_in_port = 2'b00; + else + next_no_port = 1'b1; + end + + 2'b01 : begin + if (req_port2) + next_addr_in_port = 2'b10; + else if (req_port0) + next_addr_in_port = 2'b00; + else if (HSELM) + next_addr_in_port = 2'b01; + else + next_no_port = 1'b1; + end + + 2'b10 : begin + if (req_port0) + next_addr_in_port = 2'b00; + else if (req_port1) + next_addr_in_port = 2'b01; + else if (HSELM) + next_addr_in_port = 2'b10; + else + next_no_port = 1'b1; + end + + default : begin + next_addr_in_port = {2{1'bx}}; + next_no_port = 1'bx; + end + endcase + end + + // Sequential process + always @ (negedge HRESETn or posedge HCLK) + begin : p_addr_in_port_reg + if (~HRESETn) + begin + i_no_port <= 1'b1; + i_addr_in_port <= {2{1'b0}}; + end + else + if (HREADYM) + begin + i_no_port <= next_no_port; + i_addr_in_port <= next_addr_in_port; + end + end + + // Drive outputs with internal versions + assign addr_in_port = i_addr_in_port; + assign no_port = i_no_port; + + +endmodule + +// --================================= End ===================================-- diff --git a/xlnx/rtl/ahb_interconnect/nox_intcon_arbS2_DRAM.v b/xlnx/rtl/ahb_interconnect/nox_intcon_arbS2_DRAM.v new file mode 100644 index 0000000..84081ad --- /dev/null +++ b/xlnx/rtl/ahb_interconnect/nox_intcon_arbS2_DRAM.v @@ -0,0 +1,363 @@ +//----------------------------------------------------------------------------- +// The confidential and proprietary information contained in this file may +// only be used by a person authorised under and to the extent permitted +// by a subsisting licensing agreement from ARM Limited. +// +// (C) COPYRIGHT 2001-2013-2024 ARM Limited. +// ALL RIGHTS RESERVED +// +// This entire notice must be reproduced on all copies of this file +// and copies of this file may only be made by a person if such person is +// permitted to do so under the terms of a subsisting license agreement +// from ARM Limited. +// +// SVN Information +// +// Checked In : $Date: 2012-10-15 18:01:36 +0100 (Mon, 15 Oct 2012) $ +// +// Revision : $Revision: 225465 $ +// +// Release Information : Cortex-M System Design Kit-r1p0-01rel0 +// +//----------------------------------------------------------------------------- +// +//----------------------------------------------------------------------------- +// Abstract : The Output Arbitration is used to determine which +// of the input stages will be given access to the +// shared slave. +// +// Notes : The bus matrix has sparse connectivity. +// +//----------------------------------------------------------------------------- + +`timescale 1ns/1ps + +module nox_intcon_arbS2_DRAM ( + + // Common AHB signals + HCLK , + HRESETn, + + // Input port request signals + req_port1, + req_port2, + + HREADYM, + HSELM, + HTRANSM, + HBURSTM, + HMASTLOCKM, + + // Arbiter outputs + addr_in_port, + no_port + + ); + + +// ----------------------------------------------------------------------------- +// Input and Output declarations +// ----------------------------------------------------------------------------- + + // Common AHB signals + input HCLK; // AHB system clock + input HRESETn; // AHB system reset + input req_port1; // Port 1 request signal + input req_port2; // Port 2 request signal + input HREADYM; // Transfer done + input HSELM; // Slave select line + input [1:0] HTRANSM; // Transfer type + input [2:0] HBURSTM; // Burst type + input HMASTLOCKM; // Locked transfer + output [1:0] addr_in_port; // Port address input + output no_port; // No port selected signal + + +// ----------------------------------------------------------------------------- +// Constant declarations +// ----------------------------------------------------------------------------- +// HTRANS transfer type signal encoding +`define TRN_IDLE 2'b00 // Idle transfer +`define TRN_BUSY 2'b01 // Busy transfer +`define TRN_NONSEQ 2'b10 // NonSequential transfer +`define TRN_SEQ 2'b11 // Sequential transfer + +// HBURST transfer type signal encoding +`define BUR_SINGLE 3'b000 // Single +`define BUR_INCR 3'b001 // Incremental +`define BUR_WRAP4 3'b010 // 4-beat wrap +`define BUR_INCR4 3'b011 // 4-beat Incr +`define BUR_WRAP8 3'b100 // 8-beat wrap +`define BUR_INCR8 3'b101 // 8-beat Incr +`define BUR_WRAP16 3'b110 // 16-beat Wrap +`define BUR_INCR16 3'b111 // 16-beat Incr + + +// ----------------------------------------------------------------------------- +// Wire declarations +// ----------------------------------------------------------------------------- + wire HCLK; // AHB system clock + wire HRESETn; // AHB system reset + wire req_port1; // Port 1 request signal + wire req_port2; // Port 2 request signal + wire HREADYM; // Transfer done + wire HSELM; // Slave select line + wire [1:0] HTRANSM; // Transfer type + wire [2:0] HBURSTM; // Burst type + wire HMASTLOCKM; // Locked transfer + wire [1:0] addr_in_port; // Address input port + wire no_port; // No port selected signal + + +// ----------------------------------------------------------------------------- +// Signal declarations +// ----------------------------------------------------------------------------- + reg [1:0] next_addr_in_port; // D-input of addr_in_port + reg next_no_port; // D-input of no_port + reg [1:0] i_addr_in_port; // Internal version of addr_in_port + reg i_no_port; // Internal version of no_port + + // Burst counter logic + reg [3:0] next_burst_remain; // D-input of reg_burst_remain + reg [3:0] reg_burst_remain; // Burst counter + reg next_burst_hold; // D-input of reg_burst_hold + reg reg_burst_hold; // Burst hold signal + + // INCR burst logic + reg [1:0] reg_early_incr_count; // Counts number of INCR bursts terminated + // earlier than 4-beats + wire [1:0] next_early_incr_count; // D-input for reg_early_incr_count + + +// ----------------------------------------------------------------------------- +// Beginning of main code +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +// BURST TRANSFER COUNTER +// ----------------------------------------------------------------------------- +// +// The Burst counter is used to count down from the number of transfers the +// master should perform and when the counter reaches zero the bus may be +// passed to another master. +// +// reg_burst_remain indicates the number of transfers remaining in the +// current fixed length burst after the current transfer. +// reg_burst_hold is set when transfers remain in a burst and causes the arbitration +// to be held in the current cycle + + always @ (HTRANSM or HSELM or HBURSTM or reg_burst_remain or reg_burst_hold or + reg_early_incr_count) + begin : p_next_burst_remain_comb + // Force the Burst logic to reset if this port is de-selected. This would + // otherwise cause problems in several situations, e.g.: + // 1. The master performs 2 fixed-length bursts back-to-back, but the + // second is to an alternate output port + // 2. The master is performing a fixed-length burst but is de-granted mid- + // way by a local AHB Arbiter + if (~HSELM) + begin + next_burst_remain = 4'b0000; + next_burst_hold = 1'b0; + end + + // Burst logic is initialised on a NONSEQ transfer (i.e. start of burst) + // IDLE transfers cause the logic to reset + // BUSY transfers pause the decrementer + // SEQ transfers decrement the counter + else + case (HTRANSM) + + `TRN_NONSEQ : begin + case (HBURSTM) + `BUR_INCR16, `BUR_WRAP16 : begin + next_burst_remain = 4'b1110; + next_burst_hold = 1'b1; + end // case: BUR_INCR16 | BUR_WRAP16 + + `BUR_INCR8, `BUR_WRAP8 : begin + next_burst_remain = 4'b0110; + next_burst_hold = 1'b1; + end // case: BUR_INCR8 | BUR_WRAP8 + + `BUR_INCR4, `BUR_WRAP4 : begin + next_burst_remain = 4'b0010; + next_burst_hold = 1'b1; + end // case: BUR_INCR4 | BUR_WRAP4 + + `BUR_INCR : begin + if (reg_early_incr_count == 2'b01) + begin + next_burst_remain = 4'b0000; + next_burst_hold = 1'b0; + end + else + begin + next_burst_remain = 4'b0010; + next_burst_hold = 1'b1; + end + end // case: BUR_INCR + + `BUR_SINGLE : begin + next_burst_remain = 4'b0000; + next_burst_hold = 1'b0; + end // case: BUR_SINGLE | BUR_INCR + + default : begin + next_burst_remain = 4'bxxxx; + next_burst_hold = 1'bx; + end // case: default + + endcase // case(HBURSTM) + end // case: `TRN_NONSEQ + + `TRN_SEQ : begin + if (reg_burst_remain == 4'b0000) + begin + next_burst_hold = 1'b0; + next_burst_remain = 4'b0000; + end + else + begin + next_burst_hold = reg_burst_hold; + next_burst_remain = reg_burst_remain - 1'b1; + end + end // case: `TRN_SEQ + + `TRN_BUSY : begin + next_burst_remain = reg_burst_remain; + next_burst_hold = reg_burst_hold; + end // case: `TRN_BUSY + + `TRN_IDLE : begin + next_burst_remain = 4'b0000; + next_burst_hold = 1'b0; + end // case: `TRN_IDLE + + default : begin + next_burst_remain = 4'bxxxx; + next_burst_hold = 1'bx; + end // case: default + + endcase // case(HTRANSM) + end // block: p_next_burst_remain_comb + + + // reg_early_incr_count counts the number of bursts which have terminated + // earlier than the defined arbitration point: this is primarily + // intended to detect back-to-back INCR bursts which are less than 4 + // beats long. If such bursts are not counted then theoretically a + // sequence of e.g. 3-beat INCR bursts from a master would lock the + // arbitration scheme indefinitely. + + assign next_early_incr_count = (!next_burst_hold) ? 2'b00 : + (reg_burst_hold & (HTRANSM == `TRN_NONSEQ)) ? + reg_early_incr_count + 1'b1 : + reg_early_incr_count; + + // Sequential process + always @ (negedge HRESETn or posedge HCLK) + begin : p_burst_seq + if (~HRESETn) + begin + reg_burst_remain <= 4'b0000; + reg_burst_hold <= 1'b0; + reg_early_incr_count <= 2'b00; + end // if (HRESETn == 1'b0) + else + if (HREADYM) + begin + reg_burst_remain <= next_burst_remain; + reg_burst_hold <= next_burst_hold; + reg_early_incr_count <= next_early_incr_count; + end + end // block: p_burst_seq + + +// ----------------------------------------------------------------------------- +// Port Selection +// ----------------------------------------------------------------------------- +// The Output Arbitration function looks at all the requests to use the +// output port and determines which is the highest priority request. This +// version of the arbitration logic uses a round-robin scheme. +// For example if port 1 is currently in use then the arbiter will first check +// if port 2 requires access, then it checks port 3, then port 4 etc. When +// port 2 is currently in use it will check port 3 first then port 4 and +// all remaining ports, before finally checking port 1. +// If none of the input ports are requesting then the current port will +// remain active if it is performing IDLE transfers to the selected slave. If +// this is not the case then the no_port signal will be asserted which +// indicates that no input port should be selected. + + always @ ( + req_port1 or + req_port2 or + HMASTLOCKM or next_burst_hold or HSELM or i_no_port or i_addr_in_port + ) + begin : p_sel_port_comb + // Default values are used for next_no_port and next_addr_in_port + next_no_port = 1'b0; + next_addr_in_port = i_addr_in_port; + + if ( HMASTLOCKM | next_burst_hold ) + next_addr_in_port = i_addr_in_port; + else if (i_no_port) + begin + if (req_port1) + next_addr_in_port = 2'b01; + else if (req_port2) + next_addr_in_port = 2'b10; + else + next_no_port = 1'b1; + end + else + case (i_addr_in_port) + 2'b01 : begin + if (req_port2) + next_addr_in_port = 2'b10; + else if (HSELM) + next_addr_in_port = 2'b01; + else + next_no_port = 1'b1; + end + + 2'b10 : begin + if (req_port1) + next_addr_in_port = 2'b01; + else if (HSELM) + next_addr_in_port = 2'b10; + else + next_no_port = 1'b1; + end + + default : begin + next_addr_in_port = {2{1'bx}}; + next_no_port = 1'bx; + end + endcase + end + + // Sequential process + always @ (negedge HRESETn or posedge HCLK) + begin : p_addr_in_port_reg + if (~HRESETn) + begin + i_no_port <= 1'b1; + i_addr_in_port <= {2{1'b0}}; + end + else + if (HREADYM) + begin + i_no_port <= next_no_port; + i_addr_in_port <= next_addr_in_port; + end + end + + // Drive outputs with internal versions + assign addr_in_port = i_addr_in_port; + assign no_port = i_no_port; + + +endmodule + +// --================================= End ===================================-- diff --git a/xlnx/rtl/ahb_interconnect/nox_intcon_arbS3_PERIPH.v b/xlnx/rtl/ahb_interconnect/nox_intcon_arbS3_PERIPH.v new file mode 100644 index 0000000..a4255f7 --- /dev/null +++ b/xlnx/rtl/ahb_interconnect/nox_intcon_arbS3_PERIPH.v @@ -0,0 +1,144 @@ +//----------------------------------------------------------------------------- +// The confidential and proprietary information contained in this file may +// only be used by a person authorised under and to the extent permitted +// by a subsisting licensing agreement from ARM Limited. +// +// (C) COPYRIGHT 2001-2013-2024 ARM Limited. +// ALL RIGHTS RESERVED +// +// This entire notice must be reproduced on all copies of this file +// and copies of this file may only be made by a person if such person is +// permitted to do so under the terms of a subsisting license agreement +// from ARM Limited. +// +// SVN Information +// +// Checked In : $Date: 2012-10-15 18:01:36 +0100 (Mon, 15 Oct 2012) $ +// +// Revision : $Revision: 225465 $ +// +// Release Information : Cortex-M System Design Kit-r1p0-01rel0 +// +//----------------------------------------------------------------------------- +// +//------------------------------------------------------------------------------ +// Abstract : The Output Arbitration is normally used to determine +// which of the input stages will be given access to +// the shared slave. However, for this output port, only +// one sparse connection is declared and arbitration +// is simplified to a 'grant when requested' function. +// +// Notes : The bus matrix has sparse connectivity and the +// round arbiter scheme has been overridden for this +// instance only. +// +//----------------------------------------------------------------------------- + +`timescale 1ns/1ps + +module nox_intcon_arbS3_PERIPH ( + + // Common AHB signals + HCLK , + HRESETn, + + // Input port request signals + req_port1, + + HREADYM, + HSELM, + HTRANSM, + HBURSTM, + HMASTLOCKM, + + // Arbiter outputs + addr_in_port, + no_port + + ); + + +// ----------------------------------------------------------------------------- +// Input and Output declarations +// ----------------------------------------------------------------------------- + + // Common AHB signals + input HCLK; // AHB system clock + input HRESETn; // AHB system reset + + input req_port1; // Port 1 request signal + + input HREADYM; // Transfer done + input HSELM; // Slave select line + input [1:0] HTRANSM; // Transfer type + input [2:0] HBURSTM; // Burst type + input HMASTLOCKM; // Locked transfer + + output [1:0] addr_in_port; // Port address input + output no_port; // No port selected signal + + +// ----------------------------------------------------------------------------- +// Wire declarations +// ----------------------------------------------------------------------------- + wire HCLK; // AHB system clock + wire HRESETn; // AHB system reset + wire req_port1; // Port 1 request signal + wire HREADYM; // Transfer done + wire HSELM; // Slave select line + wire [1:0] HTRANSM; // Transfer type + wire HMASTLOCKM; // Locked transfer + wire [1:0] addr_in_port; // Port address input + reg no_port; // No port selected signal + + +// ----------------------------------------------------------------------------- +// Signal declarations +// ----------------------------------------------------------------------------- + wire [1:0] addr_in_port_next; // D-input of addr_in_port + reg [1:0] iaddr_in_port; // Internal version of addr_in_port + wire no_port_next; // D-input of no_port + wire request; // Slave port request + + +// ----------------------------------------------------------------------------- +// Beginning of main code +// ----------------------------------------------------------------------------- +//------------------------------------------------------------------------------ +// Port Selection +//------------------------------------------------------------------------------ +// The single output 'arbitration' function looks at the request to use the +// output port and grants it appropriately. The input port will remain granted +// if it is performing IDLE transfers to the selected slave. If this is not +// the case then the no_port signal will be asserted which indicates that the +// input port should be deselected. + + assign request = req_port1 | ( (iaddr_in_port == 2'b01) & HSELM & + (HTRANSM != 2'b00) ); + + assign no_port_next = ! ( HMASTLOCKM | request | HSELM ); + assign addr_in_port_next = ( request & !HMASTLOCKM ) ? 2'b01 : iaddr_in_port; + + // Sequential process + always @ (negedge HRESETn or posedge HCLK) + begin : p_addr_in_port_reg + if (~HRESETn) + begin + no_port <= 1'b1; + iaddr_in_port <= {2{1'b0}}; + end + else + if (HREADYM) + begin + no_port <= no_port_next; + iaddr_in_port <= addr_in_port_next; + end + end // block: p_addr_in_port_reg + + // Drive output with internal version + assign addr_in_port = iaddr_in_port; + + +endmodule + +// --================================= End ===================================-- diff --git a/xlnx/rtl/ahb_interconnect/nox_intcon_decM0_CPU_FETCH.v b/xlnx/rtl/ahb_interconnect/nox_intcon_decM0_CPU_FETCH.v new file mode 100644 index 0000000..7a0fa80 --- /dev/null +++ b/xlnx/rtl/ahb_interconnect/nox_intcon_decM0_CPU_FETCH.v @@ -0,0 +1,341 @@ +//----------------------------------------------------------------------------- +// The confidential and proprietary information contained in this file may +// only be used by a person authorised under and to the extent permitted +// by a subsisting licensing agreement from ARM Limited. +// +// (C) COPYRIGHT 2001-2013-2024 ARM Limited. +// ALL RIGHTS RESERVED +// +// This entire notice must be reproduced on all copies of this file +// and copies of this file may only be made by a person if such person is +// permitted to do so under the terms of a subsisting license agreement +// from ARM Limited. +// +// SVN Information +// +// Checked In : $Date: 2013-01-23 11:45:45 +0000 (Wed, 23 Jan 2013) $ +// +// Revision : $Revision: 234562 $ +// +// Release Information : Cortex-M System Design Kit-r1p0-01rel0 +// +//----------------------------------------------------------------------------- +// +//----------------------------------------------------------------------------- +// Abstract : The MatrixDecode is used to determine which output +// stage is required for a particular access. Addresses +// that do not map to an Output port are diverted to +// the local default slave. +// +// Notes : The bus matrix has sparse connectivity. +// +//----------------------------------------------------------------------------- + +`timescale 1ns/1ps + +module nox_intcon_decM0_CPU_FETCH ( + + // Common AHB signals + HCLK, + HRESETn, + + // Signals from the Input stage + HREADYS, + sel_dec, + decode_addr_dec, + trans_dec, + + // Bus-switch output 0 + active_dec0, + readyout_dec0, + resp_dec0, + rdata_dec0, + ruser_dec0, + + // Bus-switch output 1 + active_dec1, + readyout_dec1, + resp_dec1, + rdata_dec1, + ruser_dec1, + + // Output port selection signals + sel_dec0, + sel_dec1, + + // Selected Output port data and control signals + active_dec, + HREADYOUTS, + HRESPS, + HRUSERS, + HRDATAS + + ); + + +// ----------------------------------------------------------------------------- +// Input and Output declarations +// ----------------------------------------------------------------------------- + + // Common AHB signals + input HCLK; // AHB System Clock + input HRESETn; // AHB System Reset + + // Signals from the Input stage + input HREADYS; // Transfer done + input sel_dec; // HSEL input + input [31:10] decode_addr_dec; // HADDR decoder input + input [1:0] trans_dec; // Input port HTRANS signal + + // Bus-switch output MI0 + input active_dec0; // Output stage MI0 active_dec signal + input readyout_dec0; // HREADYOUT input + input [1:0] resp_dec0; // HRESP input + input [31:0] rdata_dec0; // HRDATA input + input [31:0] ruser_dec0; // HRUSER input + + // Bus-switch output MI1 + input active_dec1; // Output stage MI1 active_dec signal + input readyout_dec1; // HREADYOUT input + input [1:0] resp_dec1; // HRESP input + input [31:0] rdata_dec1; // HRDATA input + input [31:0] ruser_dec1; // HRUSER input + + // Output port selection signals + output sel_dec0; // HSEL output + output sel_dec1; // HSEL output + + // Selected Output port data and control signals + output active_dec; // Combinatorial active_dec O/P + output HREADYOUTS; // HREADY feedback output + output [1:0] HRESPS; // Transfer response + output [31:0] HRUSERS; // User read Data + output [31:0] HRDATAS; // Read Data + + +// ----------------------------------------------------------------------------- +// Wire declarations +// ----------------------------------------------------------------------------- + + // Common AHB signals + wire HCLK; // AHB System Clock + wire HRESETn; // AHB System Reset + + // Signals from the Input stage + wire HREADYS; // Transfer done + wire sel_dec; // HSEL input + wire [31:10] decode_addr_dec; // HADDR input + wire [1:0] trans_dec; // Input port HTRANS signal + + // Bus-switch output MI0 + wire active_dec0; // active_dec signal + wire readyout_dec0; // HREADYOUT input + wire [1:0] resp_dec0; // HRESP input + wire [31:0] rdata_dec0; // HRDATA input + wire [31:0] ruser_dec0; // HRUSER input + reg sel_dec0; // HSEL output + + // Bus-switch output MI1 + wire active_dec1; // active_dec signal + wire readyout_dec1; // HREADYOUT input + wire [1:0] resp_dec1; // HRESP input + wire [31:0] rdata_dec1; // HRDATA input + wire [31:0] ruser_dec1; // HRUSER input + reg sel_dec1; // HSEL output + + +// ----------------------------------------------------------------------------- +// Signal declarations +// ----------------------------------------------------------------------------- + + // Selected Output port data and control signals + reg active_dec; // Combinatorial active_dec O/P signal + reg HREADYOUTS; // Combinatorial HREADYOUT signal + reg [1:0] HRESPS; // Combinatorial HRESPS signal + reg [31:0] HRUSERS; + reg [31:0] HRDATAS; // Read data bus + + reg [2:0] addr_out_port; // Address output ports + reg [2:0] data_out_port; // Data output ports + + // Default slave signals + reg sel_dft_slv; // HSEL signal + wire readyout_dft_slv; // HREADYOUT signal + wire [1:0] resp_dft_slv; // Combinatorial HRESPS signal + + +// ----------------------------------------------------------------------------- +// Beginning of main code +// ----------------------------------------------------------------------------- + +//------------------------------------------------------------------------------ +// Default slave (accessed when HADDR is unmapped) +//------------------------------------------------------------------------------ + + nox_intcon_default_slave u_nox_intcon_default_slave ( + + // Common AHB signals + .HCLK (HCLK), + .HRESETn (HRESETn), + + // AHB Control signals + .HSEL (sel_dft_slv), + .HTRANS (trans_dec), + .HREADY (HREADYS), + .HREADYOUT (readyout_dft_slv), + .HRESP (resp_dft_slv) + + ); + + +//------------------------------------------------------------------------------ +// Address phase signals +//------------------------------------------------------------------------------ + +// The address decode is done in two stages. This is so that the address +// decode occurs in only one process, p_addr_out_portComb, and then the select +// signal is factored in. +// +// Note that the hexadecimal address values are reformatted to align with the +// lower bound of decode_addr_dec[31:10], which is not a hex character boundary + + always @ ( + decode_addr_dec or data_out_port or trans_dec + ) + begin : p_addr_out_port_comb + // Address region 0x00000000-0x0001ffff + if (((decode_addr_dec >= 22'h000000) & (decode_addr_dec <= 22'h00007f)) + | ((data_out_port == 3'b000) & (trans_dec == 2'b00))) + addr_out_port = 3'b000; // Select Output port MI0 + + // Address region 0x00020000-0x0003ffff + else if (((decode_addr_dec >= 22'h000080) & (decode_addr_dec <= 22'h0000ff)) + | ((data_out_port == 3'b001) & (trans_dec == 2'b00))) + addr_out_port = 3'b001; // Select Output port MI1 + + else + addr_out_port = 3'b100; // Select the default slave + end // block: p_addr_out_port_comb + + // Select signal decode + always @ (sel_dec or addr_out_port) + begin : p_sel_comb + sel_dec0 = 1'b0; + sel_dec1 = 1'b0; + sel_dft_slv = 1'b0; + + if (sel_dec) + case (addr_out_port) + 3'b000 : sel_dec0 = 1'b1; + 3'b001 : sel_dec1 = 1'b1; + 3'b100 : sel_dft_slv = 1'b1; // Select the default slave + default : begin + sel_dec0 = 1'bx; + sel_dec1 = 1'bx; + sel_dft_slv = 1'bx; + end + endcase // case(addr_out_port) + end // block: p_sel_comb + +// The decoder selects the appropriate active_dec signal depending on which +// output stage is required for the transfer. + always @ ( + active_dec0 or + active_dec1 or + addr_out_port + ) + begin : p_active_comb + case (addr_out_port) + 3'b000 : active_dec = active_dec0; + 3'b001 : active_dec = active_dec1; + 3'b100 : active_dec = 1'b1; // Select the default slave + default : active_dec = 1'bx; + endcase // case(addr_out_port) + end // block: p_active_comb + + +//------------------------------------------------------------------------------ +// Data phase signals +//------------------------------------------------------------------------------ + +// The data_out_port needs to be updated when HREADY from the input stage is high. +// Note: HREADY must be used, not HREADYOUT, because there are occaisions +// (namely when the holding register gets loaded) when HREADYOUT may be low +// but HREADY is high, and in this case it is important that the data_out_port +// gets updated. + + always @ (negedge HRESETn or posedge HCLK) + begin : p_data_out_port_seq + if (~HRESETn) + data_out_port <= {3{1'b0}}; + else + if (HREADYS) + data_out_port <= addr_out_port; + end // block: p_data_out_port_seq + + // HREADYOUTS output decode + always @ ( + readyout_dft_slv or + readyout_dec0 or + readyout_dec1 or + data_out_port + ) + begin : p_ready_comb + case (data_out_port) + 3'b000 : HREADYOUTS = readyout_dec0; + 3'b001 : HREADYOUTS = readyout_dec1; + 3'b100 : HREADYOUTS = readyout_dft_slv; // Select the default slave + default : HREADYOUTS = 1'bx; + endcase // case(data_out_port) + end // block: p_ready_comb + + // HRESPS output decode + always @ ( + resp_dft_slv or + resp_dec0 or + resp_dec1 or + data_out_port + ) + begin : p_resp_comb + case (data_out_port) + 3'b000 : HRESPS = resp_dec0; + 3'b001 : HRESPS = resp_dec1; + 3'b100 : HRESPS = resp_dft_slv; // Select the default slave + default : HRESPS = {2{1'bx}}; + endcase // case (data_out_port) + end // block: p_resp_comb + + // HRDATAS output decode + always @ ( + rdata_dec0 or + rdata_dec1 or + data_out_port + ) + begin : p_rdata_comb + case (data_out_port) + 3'b000 : HRDATAS = rdata_dec0; + 3'b001 : HRDATAS = rdata_dec1; + 3'b100 : HRDATAS = {32{1'b0}}; // Select the default slave + default : HRDATAS = {32{1'bx}}; + endcase // case (data_out_port) + end // block: p_rdata_comb + + // HRUSERS output decode + always @ ( + ruser_dec0 or + ruser_dec1 or + data_out_port + ) + begin : p_ruser_comb + case (data_out_port) + 3'b000 : HRUSERS = ruser_dec0; + 3'b001 : HRUSERS = ruser_dec1; + 3'b100 : HRUSERS = {32{1'b0}}; // Select the default slave + default : HRUSERS = {32{1'bx}}; + endcase // case (data_out_port) + end // block: p_ruser_comb + + +endmodule + +// --================================= End ===================================-- diff --git a/xlnx/rtl/ahb_interconnect/nox_intcon_decM1_CPU_LSU.v b/xlnx/rtl/ahb_interconnect/nox_intcon_decM1_CPU_LSU.v new file mode 100644 index 0000000..21cdf48 --- /dev/null +++ b/xlnx/rtl/ahb_interconnect/nox_intcon_decM1_CPU_LSU.v @@ -0,0 +1,425 @@ +//----------------------------------------------------------------------------- +// The confidential and proprietary information contained in this file may +// only be used by a person authorised under and to the extent permitted +// by a subsisting licensing agreement from ARM Limited. +// +// (C) COPYRIGHT 2001-2013-2024 ARM Limited. +// ALL RIGHTS RESERVED +// +// This entire notice must be reproduced on all copies of this file +// and copies of this file may only be made by a person if such person is +// permitted to do so under the terms of a subsisting license agreement +// from ARM Limited. +// +// SVN Information +// +// Checked In : $Date: 2013-01-23 11:45:45 +0000 (Wed, 23 Jan 2013) $ +// +// Revision : $Revision: 234562 $ +// +// Release Information : Cortex-M System Design Kit-r1p0-01rel0 +// +//----------------------------------------------------------------------------- +// +//----------------------------------------------------------------------------- +// Abstract : The MatrixDecode is used to determine which output +// stage is required for a particular access. Addresses +// that do not map to an Output port are diverted to +// the local default slave. +// +// Notes : The bus matrix has sparse connectivity. +// +//----------------------------------------------------------------------------- + +`timescale 1ns/1ps + +module nox_intcon_decM1_CPU_LSU ( + + // Common AHB signals + HCLK, + HRESETn, + + // Signals from the Input stage + HREADYS, + sel_dec, + decode_addr_dec, + trans_dec, + + // Bus-switch output 0 + active_dec0, + readyout_dec0, + resp_dec0, + rdata_dec0, + ruser_dec0, + + // Bus-switch output 1 + active_dec1, + readyout_dec1, + resp_dec1, + rdata_dec1, + ruser_dec1, + + // Bus-switch output 2 + active_dec2, + readyout_dec2, + resp_dec2, + rdata_dec2, + ruser_dec2, + + // Bus-switch output 3 + active_dec3, + readyout_dec3, + resp_dec3, + rdata_dec3, + ruser_dec3, + + // Output port selection signals + sel_dec0, + sel_dec1, + sel_dec2, + sel_dec3, + + // Selected Output port data and control signals + active_dec, + HREADYOUTS, + HRESPS, + HRUSERS, + HRDATAS + + ); + + +// ----------------------------------------------------------------------------- +// Input and Output declarations +// ----------------------------------------------------------------------------- + + // Common AHB signals + input HCLK; // AHB System Clock + input HRESETn; // AHB System Reset + + // Signals from the Input stage + input HREADYS; // Transfer done + input sel_dec; // HSEL input + input [31:10] decode_addr_dec; // HADDR decoder input + input [1:0] trans_dec; // Input port HTRANS signal + + // Bus-switch output MI0 + input active_dec0; // Output stage MI0 active_dec signal + input readyout_dec0; // HREADYOUT input + input [1:0] resp_dec0; // HRESP input + input [31:0] rdata_dec0; // HRDATA input + input [31:0] ruser_dec0; // HRUSER input + + // Bus-switch output MI1 + input active_dec1; // Output stage MI1 active_dec signal + input readyout_dec1; // HREADYOUT input + input [1:0] resp_dec1; // HRESP input + input [31:0] rdata_dec1; // HRDATA input + input [31:0] ruser_dec1; // HRUSER input + + // Bus-switch output MI2 + input active_dec2; // Output stage MI2 active_dec signal + input readyout_dec2; // HREADYOUT input + input [1:0] resp_dec2; // HRESP input + input [31:0] rdata_dec2; // HRDATA input + input [31:0] ruser_dec2; // HRUSER input + + // Bus-switch output MI3 + input active_dec3; // Output stage MI3 active_dec signal + input readyout_dec3; // HREADYOUT input + input [1:0] resp_dec3; // HRESP input + input [31:0] rdata_dec3; // HRDATA input + input [31:0] ruser_dec3; // HRUSER input + + // Output port selection signals + output sel_dec0; // HSEL output + output sel_dec1; // HSEL output + output sel_dec2; // HSEL output + output sel_dec3; // HSEL output + + // Selected Output port data and control signals + output active_dec; // Combinatorial active_dec O/P + output HREADYOUTS; // HREADY feedback output + output [1:0] HRESPS; // Transfer response + output [31:0] HRUSERS; // User read Data + output [31:0] HRDATAS; // Read Data + + +// ----------------------------------------------------------------------------- +// Wire declarations +// ----------------------------------------------------------------------------- + + // Common AHB signals + wire HCLK; // AHB System Clock + wire HRESETn; // AHB System Reset + + // Signals from the Input stage + wire HREADYS; // Transfer done + wire sel_dec; // HSEL input + wire [31:10] decode_addr_dec; // HADDR input + wire [1:0] trans_dec; // Input port HTRANS signal + + // Bus-switch output MI0 + wire active_dec0; // active_dec signal + wire readyout_dec0; // HREADYOUT input + wire [1:0] resp_dec0; // HRESP input + wire [31:0] rdata_dec0; // HRDATA input + wire [31:0] ruser_dec0; // HRUSER input + reg sel_dec0; // HSEL output + + // Bus-switch output MI1 + wire active_dec1; // active_dec signal + wire readyout_dec1; // HREADYOUT input + wire [1:0] resp_dec1; // HRESP input + wire [31:0] rdata_dec1; // HRDATA input + wire [31:0] ruser_dec1; // HRUSER input + reg sel_dec1; // HSEL output + + // Bus-switch output MI2 + wire active_dec2; // active_dec signal + wire readyout_dec2; // HREADYOUT input + wire [1:0] resp_dec2; // HRESP input + wire [31:0] rdata_dec2; // HRDATA input + wire [31:0] ruser_dec2; // HRUSER input + reg sel_dec2; // HSEL output + + // Bus-switch output MI3 + wire active_dec3; // active_dec signal + wire readyout_dec3; // HREADYOUT input + wire [1:0] resp_dec3; // HRESP input + wire [31:0] rdata_dec3; // HRDATA input + wire [31:0] ruser_dec3; // HRUSER input + reg sel_dec3; // HSEL output + + +// ----------------------------------------------------------------------------- +// Signal declarations +// ----------------------------------------------------------------------------- + + // Selected Output port data and control signals + reg active_dec; // Combinatorial active_dec O/P signal + reg HREADYOUTS; // Combinatorial HREADYOUT signal + reg [1:0] HRESPS; // Combinatorial HRESPS signal + reg [31:0] HRUSERS; + reg [31:0] HRDATAS; // Read data bus + + reg [2:0] addr_out_port; // Address output ports + reg [2:0] data_out_port; // Data output ports + + // Default slave signals + reg sel_dft_slv; // HSEL signal + wire readyout_dft_slv; // HREADYOUT signal + wire [1:0] resp_dft_slv; // Combinatorial HRESPS signal + + +// ----------------------------------------------------------------------------- +// Beginning of main code +// ----------------------------------------------------------------------------- + +//------------------------------------------------------------------------------ +// Default slave (accessed when HADDR is unmapped) +//------------------------------------------------------------------------------ + + nox_intcon_default_slave u_nox_intcon_default_slave ( + + // Common AHB signals + .HCLK (HCLK), + .HRESETn (HRESETn), + + // AHB Control signals + .HSEL (sel_dft_slv), + .HTRANS (trans_dec), + .HREADY (HREADYS), + .HREADYOUT (readyout_dft_slv), + .HRESP (resp_dft_slv) + + ); + + +//------------------------------------------------------------------------------ +// Address phase signals +//------------------------------------------------------------------------------ + +// The address decode is done in two stages. This is so that the address +// decode occurs in only one process, p_addr_out_portComb, and then the select +// signal is factored in. +// +// Note that the hexadecimal address values are reformatted to align with the +// lower bound of decode_addr_dec[31:10], which is not a hex character boundary + + always @ ( + decode_addr_dec or data_out_port or trans_dec + ) + begin : p_addr_out_port_comb + // Address region 0x00000000-0x0001ffff + if (((decode_addr_dec >= 22'h000000) & (decode_addr_dec <= 22'h00007f)) + | ((data_out_port == 3'b000) & (trans_dec == 2'b00))) + addr_out_port = 3'b000; // Select Output port MI0 + + // Address region 0x00020000-0x0003ffff + else if (((decode_addr_dec >= 22'h000080) & (decode_addr_dec <= 22'h0000ff)) + | ((data_out_port == 3'b001) & (trans_dec == 2'b00))) + addr_out_port = 3'b001; // Select Output port MI1 + + // Address region 0x00040000-0x0007ffff + else if (((decode_addr_dec >= 22'h000100) & (decode_addr_dec <= 22'h0001ff)) + | ((data_out_port == 3'b010) & (trans_dec == 2'b00))) + addr_out_port = 3'b010; // Select Output port MI2 + + // Address region 0x00080000-0xffffffff + else if (((decode_addr_dec >= 22'h000200) & (decode_addr_dec <= 22'h3fffff)) + | ((data_out_port == 3'b011) & (trans_dec == 2'b00))) + addr_out_port = 3'b011; // Select Output port MI3 + + else + addr_out_port = 3'b100; // Select the default slave + end // block: p_addr_out_port_comb + + // Select signal decode + always @ (sel_dec or addr_out_port) + begin : p_sel_comb + sel_dec0 = 1'b0; + sel_dec1 = 1'b0; + sel_dec2 = 1'b0; + sel_dec3 = 1'b0; + sel_dft_slv = 1'b0; + + if (sel_dec) + case (addr_out_port) + 3'b000 : sel_dec0 = 1'b1; + 3'b001 : sel_dec1 = 1'b1; + 3'b010 : sel_dec2 = 1'b1; + 3'b011 : sel_dec3 = 1'b1; + 3'b100 : sel_dft_slv = 1'b1; // Select the default slave + default : begin + sel_dec0 = 1'bx; + sel_dec1 = 1'bx; + sel_dec2 = 1'bx; + sel_dec3 = 1'bx; + sel_dft_slv = 1'bx; + end + endcase // case(addr_out_port) + end // block: p_sel_comb + +// The decoder selects the appropriate active_dec signal depending on which +// output stage is required for the transfer. + always @ ( + active_dec0 or + active_dec1 or + active_dec2 or + active_dec3 or + addr_out_port + ) + begin : p_active_comb + case (addr_out_port) + 3'b000 : active_dec = active_dec0; + 3'b001 : active_dec = active_dec1; + 3'b010 : active_dec = active_dec2; + 3'b011 : active_dec = active_dec3; + 3'b100 : active_dec = 1'b1; // Select the default slave + default : active_dec = 1'bx; + endcase // case(addr_out_port) + end // block: p_active_comb + + +//------------------------------------------------------------------------------ +// Data phase signals +//------------------------------------------------------------------------------ + +// The data_out_port needs to be updated when HREADY from the input stage is high. +// Note: HREADY must be used, not HREADYOUT, because there are occaisions +// (namely when the holding register gets loaded) when HREADYOUT may be low +// but HREADY is high, and in this case it is important that the data_out_port +// gets updated. + + always @ (negedge HRESETn or posedge HCLK) + begin : p_data_out_port_seq + if (~HRESETn) + data_out_port <= {3{1'b0}}; + else + if (HREADYS) + data_out_port <= addr_out_port; + end // block: p_data_out_port_seq + + // HREADYOUTS output decode + always @ ( + readyout_dft_slv or + readyout_dec0 or + readyout_dec1 or + readyout_dec2 or + readyout_dec3 or + data_out_port + ) + begin : p_ready_comb + case (data_out_port) + 3'b000 : HREADYOUTS = readyout_dec0; + 3'b001 : HREADYOUTS = readyout_dec1; + 3'b010 : HREADYOUTS = readyout_dec2; + 3'b011 : HREADYOUTS = readyout_dec3; + 3'b100 : HREADYOUTS = readyout_dft_slv; // Select the default slave + default : HREADYOUTS = 1'bx; + endcase // case(data_out_port) + end // block: p_ready_comb + + // HRESPS output decode + always @ ( + resp_dft_slv or + resp_dec0 or + resp_dec1 or + resp_dec2 or + resp_dec3 or + data_out_port + ) + begin : p_resp_comb + case (data_out_port) + 3'b000 : HRESPS = resp_dec0; + 3'b001 : HRESPS = resp_dec1; + 3'b010 : HRESPS = resp_dec2; + 3'b011 : HRESPS = resp_dec3; + 3'b100 : HRESPS = resp_dft_slv; // Select the default slave + default : HRESPS = {2{1'bx}}; + endcase // case (data_out_port) + end // block: p_resp_comb + + // HRDATAS output decode + always @ ( + rdata_dec0 or + rdata_dec1 or + rdata_dec2 or + rdata_dec3 or + data_out_port + ) + begin : p_rdata_comb + case (data_out_port) + 3'b000 : HRDATAS = rdata_dec0; + 3'b001 : HRDATAS = rdata_dec1; + 3'b010 : HRDATAS = rdata_dec2; + 3'b011 : HRDATAS = rdata_dec3; + 3'b100 : HRDATAS = {32{1'b0}}; // Select the default slave + default : HRDATAS = {32{1'bx}}; + endcase // case (data_out_port) + end // block: p_rdata_comb + + // HRUSERS output decode + always @ ( + ruser_dec0 or + ruser_dec1 or + ruser_dec2 or + ruser_dec3 or + data_out_port + ) + begin : p_ruser_comb + case (data_out_port) + 3'b000 : HRUSERS = ruser_dec0; + 3'b001 : HRUSERS = ruser_dec1; + 3'b010 : HRUSERS = ruser_dec2; + 3'b011 : HRUSERS = ruser_dec3; + 3'b100 : HRUSERS = {32{1'b0}}; // Select the default slave + default : HRUSERS = {32{1'bx}}; + endcase // case (data_out_port) + end // block: p_ruser_comb + + +endmodule + +// --================================= End ===================================-- diff --git a/xlnx/rtl/ahb_interconnect/nox_intcon_decM2_CPU_FRONT_PORT.v b/xlnx/rtl/ahb_interconnect/nox_intcon_decM2_CPU_FRONT_PORT.v new file mode 100644 index 0000000..80bdd42 --- /dev/null +++ b/xlnx/rtl/ahb_interconnect/nox_intcon_decM2_CPU_FRONT_PORT.v @@ -0,0 +1,383 @@ +//----------------------------------------------------------------------------- +// The confidential and proprietary information contained in this file may +// only be used by a person authorised under and to the extent permitted +// by a subsisting licensing agreement from ARM Limited. +// +// (C) COPYRIGHT 2001-2013-2024 ARM Limited. +// ALL RIGHTS RESERVED +// +// This entire notice must be reproduced on all copies of this file +// and copies of this file may only be made by a person if such person is +// permitted to do so under the terms of a subsisting license agreement +// from ARM Limited. +// +// SVN Information +// +// Checked In : $Date: 2013-01-23 11:45:45 +0000 (Wed, 23 Jan 2013) $ +// +// Revision : $Revision: 234562 $ +// +// Release Information : Cortex-M System Design Kit-r1p0-01rel0 +// +//----------------------------------------------------------------------------- +// +//----------------------------------------------------------------------------- +// Abstract : The MatrixDecode is used to determine which output +// stage is required for a particular access. Addresses +// that do not map to an Output port are diverted to +// the local default slave. +// +// Notes : The bus matrix has sparse connectivity. +// +//----------------------------------------------------------------------------- + +`timescale 1ns/1ps + +module nox_intcon_decM2_CPU_FRONT_PORT ( + + // Common AHB signals + HCLK, + HRESETn, + + // Signals from the Input stage + HREADYS, + sel_dec, + decode_addr_dec, + trans_dec, + + // Bus-switch output 0 + active_dec0, + readyout_dec0, + resp_dec0, + rdata_dec0, + ruser_dec0, + + // Bus-switch output 1 + active_dec1, + readyout_dec1, + resp_dec1, + rdata_dec1, + ruser_dec1, + + // Bus-switch output 2 + active_dec2, + readyout_dec2, + resp_dec2, + rdata_dec2, + ruser_dec2, + + // Output port selection signals + sel_dec0, + sel_dec1, + sel_dec2, + + // Selected Output port data and control signals + active_dec, + HREADYOUTS, + HRESPS, + HRUSERS, + HRDATAS + + ); + + +// ----------------------------------------------------------------------------- +// Input and Output declarations +// ----------------------------------------------------------------------------- + + // Common AHB signals + input HCLK; // AHB System Clock + input HRESETn; // AHB System Reset + + // Signals from the Input stage + input HREADYS; // Transfer done + input sel_dec; // HSEL input + input [31:10] decode_addr_dec; // HADDR decoder input + input [1:0] trans_dec; // Input port HTRANS signal + + // Bus-switch output MI0 + input active_dec0; // Output stage MI0 active_dec signal + input readyout_dec0; // HREADYOUT input + input [1:0] resp_dec0; // HRESP input + input [31:0] rdata_dec0; // HRDATA input + input [31:0] ruser_dec0; // HRUSER input + + // Bus-switch output MI1 + input active_dec1; // Output stage MI1 active_dec signal + input readyout_dec1; // HREADYOUT input + input [1:0] resp_dec1; // HRESP input + input [31:0] rdata_dec1; // HRDATA input + input [31:0] ruser_dec1; // HRUSER input + + // Bus-switch output MI2 + input active_dec2; // Output stage MI2 active_dec signal + input readyout_dec2; // HREADYOUT input + input [1:0] resp_dec2; // HRESP input + input [31:0] rdata_dec2; // HRDATA input + input [31:0] ruser_dec2; // HRUSER input + + // Output port selection signals + output sel_dec0; // HSEL output + output sel_dec1; // HSEL output + output sel_dec2; // HSEL output + + // Selected Output port data and control signals + output active_dec; // Combinatorial active_dec O/P + output HREADYOUTS; // HREADY feedback output + output [1:0] HRESPS; // Transfer response + output [31:0] HRUSERS; // User read Data + output [31:0] HRDATAS; // Read Data + + +// ----------------------------------------------------------------------------- +// Wire declarations +// ----------------------------------------------------------------------------- + + // Common AHB signals + wire HCLK; // AHB System Clock + wire HRESETn; // AHB System Reset + + // Signals from the Input stage + wire HREADYS; // Transfer done + wire sel_dec; // HSEL input + wire [31:10] decode_addr_dec; // HADDR input + wire [1:0] trans_dec; // Input port HTRANS signal + + // Bus-switch output MI0 + wire active_dec0; // active_dec signal + wire readyout_dec0; // HREADYOUT input + wire [1:0] resp_dec0; // HRESP input + wire [31:0] rdata_dec0; // HRDATA input + wire [31:0] ruser_dec0; // HRUSER input + reg sel_dec0; // HSEL output + + // Bus-switch output MI1 + wire active_dec1; // active_dec signal + wire readyout_dec1; // HREADYOUT input + wire [1:0] resp_dec1; // HRESP input + wire [31:0] rdata_dec1; // HRDATA input + wire [31:0] ruser_dec1; // HRUSER input + reg sel_dec1; // HSEL output + + // Bus-switch output MI2 + wire active_dec2; // active_dec signal + wire readyout_dec2; // HREADYOUT input + wire [1:0] resp_dec2; // HRESP input + wire [31:0] rdata_dec2; // HRDATA input + wire [31:0] ruser_dec2; // HRUSER input + reg sel_dec2; // HSEL output + + +// ----------------------------------------------------------------------------- +// Signal declarations +// ----------------------------------------------------------------------------- + + // Selected Output port data and control signals + reg active_dec; // Combinatorial active_dec O/P signal + reg HREADYOUTS; // Combinatorial HREADYOUT signal + reg [1:0] HRESPS; // Combinatorial HRESPS signal + reg [31:0] HRUSERS; + reg [31:0] HRDATAS; // Read data bus + + reg [2:0] addr_out_port; // Address output ports + reg [2:0] data_out_port; // Data output ports + + // Default slave signals + reg sel_dft_slv; // HSEL signal + wire readyout_dft_slv; // HREADYOUT signal + wire [1:0] resp_dft_slv; // Combinatorial HRESPS signal + + +// ----------------------------------------------------------------------------- +// Beginning of main code +// ----------------------------------------------------------------------------- + +//------------------------------------------------------------------------------ +// Default slave (accessed when HADDR is unmapped) +//------------------------------------------------------------------------------ + + nox_intcon_default_slave u_nox_intcon_default_slave ( + + // Common AHB signals + .HCLK (HCLK), + .HRESETn (HRESETn), + + // AHB Control signals + .HSEL (sel_dft_slv), + .HTRANS (trans_dec), + .HREADY (HREADYS), + .HREADYOUT (readyout_dft_slv), + .HRESP (resp_dft_slv) + + ); + + +//------------------------------------------------------------------------------ +// Address phase signals +//------------------------------------------------------------------------------ + +// The address decode is done in two stages. This is so that the address +// decode occurs in only one process, p_addr_out_portComb, and then the select +// signal is factored in. +// +// Note that the hexadecimal address values are reformatted to align with the +// lower bound of decode_addr_dec[31:10], which is not a hex character boundary + + always @ ( + decode_addr_dec or data_out_port or trans_dec + ) + begin : p_addr_out_port_comb + // Address region 0x00000000-0x0001ffff + if (((decode_addr_dec >= 22'h000000) & (decode_addr_dec <= 22'h00007f)) + | ((data_out_port == 3'b000) & (trans_dec == 2'b00))) + addr_out_port = 3'b000; // Select Output port MI0 + + // Address region 0x00020000-0x0003ffff + else if (((decode_addr_dec >= 22'h000080) & (decode_addr_dec <= 22'h0000ff)) + | ((data_out_port == 3'b001) & (trans_dec == 2'b00))) + addr_out_port = 3'b001; // Select Output port MI1 + + // Address region 0x00040000-0x0007ffff + else if (((decode_addr_dec >= 22'h000100) & (decode_addr_dec <= 22'h0001ff)) + | ((data_out_port == 3'b010) & (trans_dec == 2'b00))) + addr_out_port = 3'b010; // Select Output port MI2 + + else + addr_out_port = 3'b100; // Select the default slave + end // block: p_addr_out_port_comb + + // Select signal decode + always @ (sel_dec or addr_out_port) + begin : p_sel_comb + sel_dec0 = 1'b0; + sel_dec1 = 1'b0; + sel_dec2 = 1'b0; + sel_dft_slv = 1'b0; + + if (sel_dec) + case (addr_out_port) + 3'b000 : sel_dec0 = 1'b1; + 3'b001 : sel_dec1 = 1'b1; + 3'b010 : sel_dec2 = 1'b1; + 3'b100 : sel_dft_slv = 1'b1; // Select the default slave + default : begin + sel_dec0 = 1'bx; + sel_dec1 = 1'bx; + sel_dec2 = 1'bx; + sel_dft_slv = 1'bx; + end + endcase // case(addr_out_port) + end // block: p_sel_comb + +// The decoder selects the appropriate active_dec signal depending on which +// output stage is required for the transfer. + always @ ( + active_dec0 or + active_dec1 or + active_dec2 or + addr_out_port + ) + begin : p_active_comb + case (addr_out_port) + 3'b000 : active_dec = active_dec0; + 3'b001 : active_dec = active_dec1; + 3'b010 : active_dec = active_dec2; + 3'b100 : active_dec = 1'b1; // Select the default slave + default : active_dec = 1'bx; + endcase // case(addr_out_port) + end // block: p_active_comb + + +//------------------------------------------------------------------------------ +// Data phase signals +//------------------------------------------------------------------------------ + +// The data_out_port needs to be updated when HREADY from the input stage is high. +// Note: HREADY must be used, not HREADYOUT, because there are occaisions +// (namely when the holding register gets loaded) when HREADYOUT may be low +// but HREADY is high, and in this case it is important that the data_out_port +// gets updated. + + always @ (negedge HRESETn or posedge HCLK) + begin : p_data_out_port_seq + if (~HRESETn) + data_out_port <= {3{1'b0}}; + else + if (HREADYS) + data_out_port <= addr_out_port; + end // block: p_data_out_port_seq + + // HREADYOUTS output decode + always @ ( + readyout_dft_slv or + readyout_dec0 or + readyout_dec1 or + readyout_dec2 or + data_out_port + ) + begin : p_ready_comb + case (data_out_port) + 3'b000 : HREADYOUTS = readyout_dec0; + 3'b001 : HREADYOUTS = readyout_dec1; + 3'b010 : HREADYOUTS = readyout_dec2; + 3'b100 : HREADYOUTS = readyout_dft_slv; // Select the default slave + default : HREADYOUTS = 1'bx; + endcase // case(data_out_port) + end // block: p_ready_comb + + // HRESPS output decode + always @ ( + resp_dft_slv or + resp_dec0 or + resp_dec1 or + resp_dec2 or + data_out_port + ) + begin : p_resp_comb + case (data_out_port) + 3'b000 : HRESPS = resp_dec0; + 3'b001 : HRESPS = resp_dec1; + 3'b010 : HRESPS = resp_dec2; + 3'b100 : HRESPS = resp_dft_slv; // Select the default slave + default : HRESPS = {2{1'bx}}; + endcase // case (data_out_port) + end // block: p_resp_comb + + // HRDATAS output decode + always @ ( + rdata_dec0 or + rdata_dec1 or + rdata_dec2 or + data_out_port + ) + begin : p_rdata_comb + case (data_out_port) + 3'b000 : HRDATAS = rdata_dec0; + 3'b001 : HRDATAS = rdata_dec1; + 3'b010 : HRDATAS = rdata_dec2; + 3'b100 : HRDATAS = {32{1'b0}}; // Select the default slave + default : HRDATAS = {32{1'bx}}; + endcase // case (data_out_port) + end // block: p_rdata_comb + + // HRUSERS output decode + always @ ( + ruser_dec0 or + ruser_dec1 or + ruser_dec2 or + data_out_port + ) + begin : p_ruser_comb + case (data_out_port) + 3'b000 : HRUSERS = ruser_dec0; + 3'b001 : HRUSERS = ruser_dec1; + 3'b010 : HRUSERS = ruser_dec2; + 3'b100 : HRUSERS = {32{1'b0}}; // Select the default slave + default : HRUSERS = {32{1'bx}}; + endcase // case (data_out_port) + end // block: p_ruser_comb + + +endmodule + +// --================================= End ===================================-- diff --git a/xlnx/rtl/ahb_interconnect/nox_intcon_default_slave.v b/xlnx/rtl/ahb_interconnect/nox_intcon_default_slave.v new file mode 100644 index 0000000..6b50ecc --- /dev/null +++ b/xlnx/rtl/ahb_interconnect/nox_intcon_default_slave.v @@ -0,0 +1,138 @@ +//----------------------------------------------------------------------------- +// The confidential and proprietary information contained in this file may +// only be used by a person authorised under and to the extent permitted +// by a subsisting licensing agreement from ARM Limited. +// +// (C) COPYRIGHT 2001-2013-2024 ARM Limited. +// ALL RIGHTS RESERVED +// +// This entire notice must be reproduced on all copies of this file +// and copies of this file may only be made by a person if such person is +// permitted to do so under the terms of a subsisting license agreement +// from ARM Limited. +// +// SVN Information +// +// Checked In : $Date: 2013-01-23 11:45:45 +0000 (Wed, 23 Jan 2013) $ +// +// Revision : $Revision: 234562 $ +// +// Release Information : Cortex-M System Design Kit-r1p0-01rel0 +// +//----------------------------------------------------------------------------- +// +// ----------------------------------------------------------------------------- +// Abstract : Default slave used to drive the slave response signals +// when there are no other slaves selected. +//----------------------------------------------------------------------------- + +`timescale 1ns/1ps + +module nox_intcon_default_slave ( + + // Common AHB signals + HCLK, + HRESETn, + + // AHB control input signals + HSEL, + HTRANS, + HREADY, + + // AHB control output signals + HREADYOUT, + HRESP + + ); + + +// ----------------------------------------------------------------------------- +// Input and Output declarations +// ----------------------------------------------------------------------------- + + // Common AHB signals + input HCLK; // AHB System Clock + input HRESETn; // AHB System Reset + + // AHB control input signals + input HSEL; // Slave Select + input [1:0] HTRANS; // Transfer type + input HREADY; // Transfer done + + // AHB control output signals + output HREADYOUT; // HREADY feedback + output [1:0] HRESP; // Transfer response + + +// ----------------------------------------------------------------------------- +// Constant declarations +// ----------------------------------------------------------------------------- + +// HRESP transfer response signal encoding +`define RSP_OKAY 2'b00 // OKAY response +`define RSP_ERROR 2'b01 // ERROR response +`define RSP_RETRY 2'b10 // RETRY response +`define RSP_SPLIT 2'b11 // SPLIT response + + +// ----------------------------------------------------------------------------- +// Input and Output declarations +// ----------------------------------------------------------------------------- + + // Common AHB signals + wire HCLK; // AHB System Clock + wire HRESETn; // AHB System Reset + + // AHB control input signals + wire HSEL; // Slave Select + wire [1:0] HTRANS; // Transfer type + wire HREADY; // Transfer done + + // AHB control output signals + wire HREADYOUT; // HREADY feedback + wire [1:0] HRESP; // Transfer response + + +// ----------------------------------------------------------------------------- +// Signal declarations +// ----------------------------------------------------------------------------- + + wire invalid; // Set during invalid transfer + wire hready_next; // Controls generation of HREADYOUT output + reg i_hreadyout; // HREADYOUT register + wire [1:0] hresp_next; // Generated response + reg [1:0] i_hresp; // HRESP register + + +// ----------------------------------------------------------------------------- +// Beginning of main code +// ----------------------------------------------------------------------------- + + assign invalid = ( HREADY & HSEL & HTRANS[1] ); + assign hready_next = i_hreadyout ? ~invalid : 1'b1 ; + assign hresp_next = invalid ? `RSP_ERROR : `RSP_OKAY; + + always @(negedge HRESETn or posedge HCLK) + begin : p_resp_seq + if (~HRESETn) + begin + i_hreadyout <= 1'b1; + i_hresp <= `RSP_OKAY; + end + else + begin + i_hreadyout <= hready_next; + + if (i_hreadyout) + i_hresp <= hresp_next; + end + end + + // Drive outputs with internal versions + assign HREADYOUT = i_hreadyout; + assign HRESP = i_hresp; + + +endmodule + +// --================================= End ===================================-- diff --git a/xlnx/rtl/ahb_interconnect/nox_intcon_in.v b/xlnx/rtl/ahb_interconnect/nox_intcon_in.v new file mode 100644 index 0000000..c65920a --- /dev/null +++ b/xlnx/rtl/ahb_interconnect/nox_intcon_in.v @@ -0,0 +1,471 @@ +//----------------------------------------------------------------------------- +// The confidential and proprietary information contained in this file may +// only be used by a person authorised under and to the extent permitted +// by a subsisting licensing agreement from ARM Limited. +// +// (C) COPYRIGHT 2001-2013-2024 ARM Limited. +// ALL RIGHTS RESERVED +// +// This entire notice must be reproduced on all copies of this file +// and copies of this file may only be made by a person if such person is +// permitted to do so under the terms of a subsisting license agreement +// from ARM Limited. +// +// SVN Information +// +// Checked In : $Date: 2012-10-15 18:01:36 +0100 (Mon, 15 Oct 2012) $ +// +// Revision : $Revision: 225465 $ +// +// Release Information : Cortex-M System Design Kit-r1p0-01rel0 +// +//----------------------------------------------------------------------------- +// +//------------------------------------------------------------------------------ +// Abstract : The Input Stage is used to hold a pending transfer +// when the required output stage is not available. +// +//----------------------------------------------------------------------------- + +`timescale 1ns/1ps + +module nox_intcon_in ( + + // Common AHB signals + HCLK, + HRESETn, + + // Input Port Address/Control Signals + HSELS, + HADDRS, + HAUSERS, + HTRANSS, + HWRITES, + HSIZES, + HBURSTS, + HPROTS, + HMASTERS, + HMASTLOCKS, + HREADYS, + + // Internal Response + active_ip, + readyout_ip, + resp_ip, + + // Input Port Response + HREADYOUTS, + HRESPS, + + // Internal Address/Control Signals + sel_ip, + addr_ip, + auser_ip, + trans_ip, + write_ip, + size_ip, + burst_ip, + prot_ip, + master_ip, + mastlock_ip, + held_tran_ip + + ); + + +// ----------------------------------------------------------------------------- +// Input and Output declarations +// ----------------------------------------------------------------------------- + + input HCLK; // AHB System Clock + input HRESETn; // AHB System Reset + input HSELS; // Slave Select from AHB + input [31:0] HADDRS; // Address bus from AHB + input [31:0] HAUSERS; // Additional user adress bus + input [1:0] HTRANSS; // Transfer type from AHB + input HWRITES; // Transfer direction from AHB + input [2:0] HSIZES; // Transfer size from AHB + input [2:0] HBURSTS; // Burst type from AHB + input [3:0] HPROTS; // Protection control from AHB + input [3:0] HMASTERS; // Master number from AHB + input HMASTLOCKS; // Locked Sequence from AHB + input HREADYS; // Transfer done from AHB + input active_ip; // active_ip signal + input readyout_ip; // HREADYOUT input + input [1:0] resp_ip; // HRESP input + + output HREADYOUTS; // HREADY feedback to AHB + output [1:0] HRESPS; // Transfer response to AHB + output sel_ip; // HSEL output + output [31:0] addr_ip; // HADDR output + output [31:0] auser_ip; // HAUSER output + output [1:0] trans_ip; // HTRANS output + output write_ip; // HWRITE output + output [2:0] size_ip; // HSIZE output + output [2:0] burst_ip; // HBURST output + output [3:0] prot_ip; // HPROT output + output [3:0] master_ip; // HMASTER output + output mastlock_ip; // HMASTLOCK output + output held_tran_ip; // Holding register active flag + + +// ----------------------------------------------------------------------------- +// Constant declarations +// ----------------------------------------------------------------------------- + +// HTRANS transfer type signal encoding +`define TRN_IDLE 2'b00 // Idle Transfer +`define TRN_BUSY 2'b01 // Busy Transfer +`define TRN_NONSEQ 2'b10 // Nonsequential transfer +`define TRN_SEQ 2'b11 // Sequential transfer + +// HBURST transfer type signal encoding +`define BUR_SINGLE 3'b000 // Single BURST +`define BUR_INCR 3'b001 // Incremental BURSTS +`define BUR_WRAP4 3'b010 // 4-beat wrap +`define BUR_INCR4 3'b011 // 4-beat incr +`define BUR_WRAP8 3'b100 // 8-beat wrap +`define BUR_INCR8 3'b101 // 8-beat incr +`define BUR_WRAP16 3'b110 // 16-beat wrap +`define BUR_INCR16 3'b111 // 16-beat incr + +// HRESP signal encoding +`define RSP_OKAY 2'b00 // OKAY response +`define RSP_ERROR 2'b01 // ERROR response +`define RSP_RETRY 2'b10 // RETRY response +`define RSP_SPLIT 2'b11 // SPLIT response + + +// ----------------------------------------------------------------------------- +// Wire declarations +// ----------------------------------------------------------------------------- + + wire HCLK; // AHB System Clock + wire HRESETn; // AHB System Reset + wire HSELS; // Slave Select from AHB + wire [31:0] HADDRS; // Address bus from AHB + wire [31:0] HAUSERS; // Additional user adress bus + wire [1:0] HTRANSS; // Transfer type from AHB + wire HWRITES; // Transfer direction from AHB + wire [2:0] HSIZES; // Transfer size from AHB + wire [2:0] HBURSTS; // Burst type from AHB + wire [3:0] HPROTS; // Protection control from AHB + wire [3:0] HMASTERS; // Master number from AHB + wire HMASTLOCKS; // Locked Sequence from AHB + wire HREADYS; // Transfer done from AHB + reg HREADYOUTS; // HREADY feedback to AHB + reg [1:0] HRESPS; // Transfer response to AHB + reg sel_ip; // HSEL output + reg [31:0] addr_ip; // HADDR output + reg [31:0] auser_ip; // HAUSER output + wire [1:0] trans_ip; // HTRANS output + reg write_ip; // HWRITE output + reg [2:0] size_ip; // HSIZE output + wire [2:0] burst_ip; // HBURST output + reg [3:0] prot_ip; // HPROT output + reg [3:0] master_ip; // HMASTER output + reg mastlock_ip; // HMASTLOCK output + wire held_tran_ip; // Holding register active flag + wire active_ip; // active_ip signal + wire readyout_ip; // HREADYOUT input + wire [1:0] resp_ip; // HRESP input + + +// ----------------------------------------------------------------------------- +// Signal declarations +// ----------------------------------------------------------------------------- + + wire load_reg; // Holding register load flag + wire pend_tran; // An active transfer cannot complete + reg pend_tran_reg; // Registered version of pend_tran + wire addr_valid; // Indicates address phase of + // valid transfer + reg data_valid; // Indicates data phase of + // valid transfer + reg [1:0] reg_trans; // Registered HTRANSS + reg [31:0] reg_addr; // Registered HADDRS + reg [31:0] reg_auser; + reg reg_write; // Registered HWRITES + reg [2:0] reg_size; // Registered HSIZES + reg [2:0] reg_burst; // Registered HBURSTS + reg [3:0] reg_prot; // Registered HPROTS + reg [3:0] reg_master; // Registerd HMASTERS + reg reg_mastlock; // Registered HMASTLOCKS + reg [1:0] transb; // HTRANS output used for burst information + reg [1:0] trans_int; // HTRANS output + reg [2:0] burst_int; // HBURST output + reg [3:0] offset_addr; // Address offset for boundary logic + reg [3:0] check_addr; // Address check for wrapped bursts + reg burst_override; // Registered burst_override_next + wire burst_override_next; // Indicates burst has been over-ridden + reg bound; // Registered version of bound_next + wire bound_next; // Indicates boundary wrapping + wire bound_en; // Clock-enable for bound register + + +// ----------------------------------------------------------------------------- +// Beginning of main code +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +// Holding Registers +// ----------------------------------------------------------------------------- +// Each input port has a holding register associated with it and a mux to +// select between the register and the direct input path. The control of +// the mux is done simply by selecting the holding register when it is loaded +// with a pending transfer, otherwise the straight through path is used. + + always @ (negedge HRESETn or posedge HCLK) + begin : p_holding_reg_seq1 + if (~HRESETn) + begin + reg_trans <= 2'b00; + reg_addr <= {32{1'b0}}; + reg_auser <= {32{1'b0}}; + reg_write <= 1'b0 ; + reg_size <= 3'b000; + reg_burst <= 3'b000; + reg_prot <= {4{1'b0}}; + reg_master <= 4'b0000; + reg_mastlock <= 1'b0 ; + end + else + if (load_reg) + begin + reg_trans <= HTRANSS; + reg_addr <= HADDRS; + reg_auser <= HAUSERS; + reg_write <= HWRITES; + reg_size <= HSIZES; + reg_burst <= HBURSTS; + reg_prot <= HPROTS; + reg_master <= HMASTERS; + reg_mastlock <= HMASTLOCKS; + end + end + + // addr_valid indicates the address phase of an active (non-BUSY/IDLE) + // transfer to this slave port + assign addr_valid = ( HSELS & HTRANSS[1] ); + + // The holding register is loaded whenever there is a transfer on the input + // port which is validated by active HREADYS + assign load_reg = ( addr_valid & HREADYS ); + + // data_valid register + // addr_valid indicates the data phase of an active (non-BUSY/IDLE) + // transfer to this slave port. A valid response (HREADY, HRESP) must be + // generated + always @ (negedge HRESETn or posedge HCLK) + begin : p_data_valid + if (~HRESETn) + data_valid <= 1'b0; + else + if (HREADYS) + data_valid <= addr_valid; + end + +// ----------------------------------------------------------------------------- +// Generate HeldTran +// ----------------------------------------------------------------------------- +// The HeldTran signal is used to indicate when there is an active transfer +// being presented to the output stage, either passing straight through or from +// the holding register. + + // pend_tran indicates that an active transfer presented to this + // slave cannot complete immediately. It is always set after the + // load_reg signal has been active. When set, it is cleared when the + // transfer is being driven onto the selected slave (as indicated by + // active_ip being high) and HREADY from the selected slave is high. + assign pend_tran = (load_reg & (~active_ip)) ? 1'b1 : + (active_ip & readyout_ip) ? 1'b0 : pend_tran_reg; + + // pend_tran_reg indicates that an active transfer was accepted by the input + // stage,but not by the output stage, and so the holding registers should be + // used + always @ (negedge HRESETn or posedge HCLK) + begin : p_pend_tran_reg + if (~HRESETn) + pend_tran_reg <= 1'b0; + else + pend_tran_reg <= pend_tran; + end + + // held_tran_ip indicates an active transfer, and is held whilst that transfer is + // in the holding registers. It passes to the output stage where it acts as + // a request line to the arbitration scheme + assign held_tran_ip = (load_reg | pend_tran_reg); + + // The output from this stage is selected from the holding register when + // there is a held transfer. Otherwise the direct path is used. + + always @ ( pend_tran_reg or HSELS or HTRANSS or HADDRS or HWRITES or + HSIZES or HBURSTS or HPROTS or HMASTERS or HMASTLOCKS or + HAUSERS or reg_auser or + reg_addr or reg_write or reg_size or reg_burst or reg_prot or + reg_master or reg_mastlock + ) + begin : p_mux_comb + if (~pend_tran_reg) + begin + sel_ip = HSELS; + trans_int = HTRANSS; + addr_ip = HADDRS; + auser_ip = HAUSERS; + write_ip = HWRITES; + size_ip = HSIZES; + burst_int = HBURSTS; + prot_ip = HPROTS; + master_ip = HMASTERS; + mastlock_ip = HMASTLOCKS; + end + else + begin + sel_ip = 1'b1; + trans_int = `TRN_NONSEQ; + addr_ip = reg_addr; + auser_ip = reg_auser; + write_ip = reg_write; + size_ip = reg_size; + burst_int = reg_burst; + prot_ip = reg_prot; + master_ip = reg_master; + mastlock_ip = reg_mastlock; + end + end + + // The transb output is used to select the correct Burst value when completing + // an interrupted defined-lenght burst. + + always @ (pend_tran_reg or HTRANSS or reg_trans) + begin : p_transb_comb + if (~pend_tran_reg) + transb = HTRANSS; + else + transb = reg_trans; + end // block: p_transb_comb + + + // Convert SEQ->NONSEQ and BUSY->IDLE when an address boundary is crossed + // whilst the burst type is being over-ridden, i.e. when completing an + // interrupted wrapping burst. + assign trans_ip = (burst_override & bound) ? {trans_int[1], 1'b0} + : trans_int; + + assign burst_ip = (burst_override & (transb != `TRN_NONSEQ)) ? `BUR_INCR + : burst_int; + +// ----------------------------------------------------------------------------- +// HREADYOUT Generation +// ----------------------------------------------------------------------------- +// There are three possible sources for the HREADYOUT signal. +// - It is driven LOW when there is a held transfer. +// - It is driven HIGH when not Selected or for Idle/Busy transfers. +// - At all other times it is driven from the appropriate shared +// slave. + + always @ (data_valid or pend_tran_reg or readyout_ip or resp_ip) + begin : p_ready_comb + if (~data_valid) + begin + HREADYOUTS = 1'b1; + HRESPS = `RSP_OKAY; + end + else if (pend_tran_reg) + begin + HREADYOUTS = 1'b0; + HRESPS = `RSP_OKAY; + end + else + begin + HREADYOUTS = readyout_ip; + HRESPS = resp_ip; + end + end // block: p_ready_comb + +// ----------------------------------------------------------------------------- +// Early Burst Termination +// ----------------------------------------------------------------------------- +// There are times when the output stage will switch to another input port +// without allowing the current burst to complete. In these cases the HTRANS +// and HBURST signals need to be overriden to ensure that the transfers +// reaching the output port meet the AHB specification. + + assign burst_override_next = ( (HTRANSS == `TRN_NONSEQ) | + (HTRANSS == `TRN_IDLE) ) ? 1'b0 + : ( (HTRANSS ==`TRN_SEQ) & + load_reg & + (~active_ip) ) ? 1'b1 + : burst_override; + + // burst_override register + always @ (negedge HRESETn or posedge HCLK) + begin : p_burst_overrideseq + if (~HRESETn) + burst_override <= 1'b0; + else + if (HREADYS) + burst_override <= burst_override_next; + end // block: p_burst_overrideseq + +// ----------------------------------------------------------------------------- +// Boundary Checking Logic +// ----------------------------------------------------------------------------- + // offset_addr + always @ (HADDRS or HSIZES) + begin : p_offset_addr_comb + case (HSIZES) + 3'b000 : offset_addr = HADDRS[3:0]; + 3'b001 : offset_addr = HADDRS[4:1]; + 3'b010 : offset_addr = HADDRS[5:2]; + 3'b011 : offset_addr = HADDRS[6:3]; + + 3'b100, 3'b101, 3'b110, 3'b111 : + offset_addr = HADDRS[3:0]; // Sizes >= 128-bits are not supported + + default : offset_addr = 4'bxxxx; + endcase + end + + // check_addr + always @ (offset_addr or HBURSTS) + begin : p_check_addr_comb + case (HBURSTS) + `BUR_WRAP4 : begin + check_addr[1:0] = offset_addr[1:0]; + check_addr[3:2] = 2'b11; + end + + `BUR_WRAP8 : begin + check_addr[2:0] = offset_addr[2:0]; + check_addr[3] = 1'b1; + end + + `BUR_WRAP16 : + check_addr[3:0] = offset_addr[3:0]; + + `BUR_SINGLE, `BUR_INCR, `BUR_INCR4, `BUR_INCR8, `BUR_INCR16 : + check_addr[3:0] = 4'b0000; + + default : check_addr[3:0] = 4'bxxxx; + endcase + end + + assign bound_next = ( check_addr == 4'b1111 ); + + assign bound_en = ( HTRANSS[1] & HREADYS ); + + // bound register + always @ (negedge HRESETn or posedge HCLK) + begin : p_bound_seq + if (~HRESETn) + bound <= 1'b0; + else + if (bound_en) + bound <= bound_next; + end + + +endmodule + +// --================================= End ===================================-- diff --git a/xlnx/rtl/ahb_interconnect/nox_intcon_lite.v b/xlnx/rtl/ahb_interconnect/nox_intcon_lite.v new file mode 100644 index 0000000..2a7387f --- /dev/null +++ b/xlnx/rtl/ahb_interconnect/nox_intcon_lite.v @@ -0,0 +1,665 @@ +//----------------------------------------------------------------------------- +// The confidential and proprietary information contained in this file may +// only be used by a person authorised under and to the extent permitted +// by a subsisting licensing agreement from ARM Limited. +// +// (C) COPYRIGHT 2001-2013-2024 ARM Limited. +// ALL RIGHTS RESERVED +// +// This entire notice must be reproduced on all copies of this file +// and copies of this file may only be made by a person if such person is +// permitted to do so under the terms of a subsisting license agreement +// from ARM Limited. +// +// SVN Information +// +// Checked In : $Date: 2012-10-15 18:01:36 +0100 (Mon, 15 Oct 2012) $ +// +// Revision : $Revision: 225465 $ +// +// Release Information : Cortex-M System Design Kit-r1p0-01rel0 +// +//----------------------------------------------------------------------------- +// +//------------------------------------------------------------------------------ +// Abstract : BusMatrixLite is a wrapper module that wraps around +// the BusMatrix module to give AHB Lite compliant +// slave and master interfaces. +// +//----------------------------------------------------------------------------- + +`timescale 1ns/1ps + +module nox_intcon_lite ( + + // Common AHB signals + HCLK, + HRESETn, + + // System Address Remap control + REMAP, + + // Input port SI0 (inputs from master 0) + HADDRM0_CPU_FETCH, + HTRANSM0_CPU_FETCH, + HWRITEM0_CPU_FETCH, + HSIZEM0_CPU_FETCH, + HBURSTM0_CPU_FETCH, + HPROTM0_CPU_FETCH, + HWDATAM0_CPU_FETCH, + HMASTLOCKM0_CPU_FETCH, + HAUSERM0_CPU_FETCH, + HWUSERM0_CPU_FETCH, + + // Input port SI1 (inputs from master 1) + HADDRM1_CPU_LSU, + HTRANSM1_CPU_LSU, + HWRITEM1_CPU_LSU, + HSIZEM1_CPU_LSU, + HBURSTM1_CPU_LSU, + HPROTM1_CPU_LSU, + HWDATAM1_CPU_LSU, + HMASTLOCKM1_CPU_LSU, + HAUSERM1_CPU_LSU, + HWUSERM1_CPU_LSU, + + // Input port SI2 (inputs from master 2) + HADDRM2_CPU_FRONT_PORT, + HTRANSM2_CPU_FRONT_PORT, + HWRITEM2_CPU_FRONT_PORT, + HSIZEM2_CPU_FRONT_PORT, + HBURSTM2_CPU_FRONT_PORT, + HPROTM2_CPU_FRONT_PORT, + HWDATAM2_CPU_FRONT_PORT, + HMASTLOCKM2_CPU_FRONT_PORT, + HAUSERM2_CPU_FRONT_PORT, + HWUSERM2_CPU_FRONT_PORT, + + // Output port MI0 (inputs from slave 0) + HRDATAS0_ROM, + HREADYOUTS0_ROM, + HRESPS0_ROM, + HRUSERS0_ROM, + + // Output port MI1 (inputs from slave 1) + HRDATAS1_IRAM, + HREADYOUTS1_IRAM, + HRESPS1_IRAM, + HRUSERS1_IRAM, + + // Output port MI2 (inputs from slave 2) + HRDATAS2_DRAM, + HREADYOUTS2_DRAM, + HRESPS2_DRAM, + HRUSERS2_DRAM, + + // Output port MI3 (inputs from slave 3) + HRDATAS3_PERIPH, + HREADYOUTS3_PERIPH, + HRESPS3_PERIPH, + HRUSERS3_PERIPH, + + // Scan test dummy signals; not connected until scan insertion + SCANENABLE, // Scan Test Mode Enable + SCANINHCLK, // Scan Chain Input + + + // Output port MI0 (outputs to slave 0) + HSELS0_ROM, + HADDRS0_ROM, + HTRANSS0_ROM, + HWRITES0_ROM, + HSIZES0_ROM, + HBURSTS0_ROM, + HPROTS0_ROM, + HWDATAS0_ROM, + HMASTLOCKS0_ROM, + HREADYMUXS0_ROM, + HAUSERS0_ROM, + HWUSERS0_ROM, + + // Output port MI1 (outputs to slave 1) + HSELS1_IRAM, + HADDRS1_IRAM, + HTRANSS1_IRAM, + HWRITES1_IRAM, + HSIZES1_IRAM, + HBURSTS1_IRAM, + HPROTS1_IRAM, + HWDATAS1_IRAM, + HMASTLOCKS1_IRAM, + HREADYMUXS1_IRAM, + HAUSERS1_IRAM, + HWUSERS1_IRAM, + + // Output port MI2 (outputs to slave 2) + HSELS2_DRAM, + HADDRS2_DRAM, + HTRANSS2_DRAM, + HWRITES2_DRAM, + HSIZES2_DRAM, + HBURSTS2_DRAM, + HPROTS2_DRAM, + HWDATAS2_DRAM, + HMASTLOCKS2_DRAM, + HREADYMUXS2_DRAM, + HAUSERS2_DRAM, + HWUSERS2_DRAM, + + // Output port MI3 (outputs to slave 3) + HSELS3_PERIPH, + HADDRS3_PERIPH, + HTRANSS3_PERIPH, + HWRITES3_PERIPH, + HSIZES3_PERIPH, + HBURSTS3_PERIPH, + HPROTS3_PERIPH, + HWDATAS3_PERIPH, + HMASTLOCKS3_PERIPH, + HREADYMUXS3_PERIPH, + HAUSERS3_PERIPH, + HWUSERS3_PERIPH, + + // Input port SI0 (outputs to master 0) + HRDATAM0_CPU_FETCH, + HREADYM0_CPU_FETCH, + HRESPM0_CPU_FETCH, + HRUSERM0_CPU_FETCH, + + // Input port SI1 (outputs to master 1) + HRDATAM1_CPU_LSU, + HREADYM1_CPU_LSU, + HRESPM1_CPU_LSU, + HRUSERM1_CPU_LSU, + + // Input port SI2 (outputs to master 2) + HRDATAM2_CPU_FRONT_PORT, + HREADYM2_CPU_FRONT_PORT, + HRESPM2_CPU_FRONT_PORT, + HRUSERM2_CPU_FRONT_PORT, + + // Scan test dummy signals; not connected until scan insertion + SCANOUTHCLK // Scan Chain Output + + ); + +// ----------------------------------------------------------------------------- +// Input and Output declarations +// ----------------------------------------------------------------------------- + + // Common AHB signals + input HCLK; // AHB System Clock + input HRESETn; // AHB System Reset + + // System Address Remap control + input [3:0] REMAP; // System Address REMAP control + + // Input port SI0 (inputs from master 0) + input [31:0] HADDRM0_CPU_FETCH; // Address bus + input [1:0] HTRANSM0_CPU_FETCH; // Transfer type + input HWRITEM0_CPU_FETCH; // Transfer direction + input [2:0] HSIZEM0_CPU_FETCH; // Transfer size + input [2:0] HBURSTM0_CPU_FETCH; // Burst type + input [3:0] HPROTM0_CPU_FETCH; // Protection control + input [31:0] HWDATAM0_CPU_FETCH; // Write data + input HMASTLOCKM0_CPU_FETCH; // Locked Sequence + input [31:0] HAUSERM0_CPU_FETCH; // Address USER signals + input [31:0] HWUSERM0_CPU_FETCH; // Write-data USER signals + + // Input port SI1 (inputs from master 1) + input [31:0] HADDRM1_CPU_LSU; // Address bus + input [1:0] HTRANSM1_CPU_LSU; // Transfer type + input HWRITEM1_CPU_LSU; // Transfer direction + input [2:0] HSIZEM1_CPU_LSU; // Transfer size + input [2:0] HBURSTM1_CPU_LSU; // Burst type + input [3:0] HPROTM1_CPU_LSU; // Protection control + input [31:0] HWDATAM1_CPU_LSU; // Write data + input HMASTLOCKM1_CPU_LSU; // Locked Sequence + input [31:0] HAUSERM1_CPU_LSU; // Address USER signals + input [31:0] HWUSERM1_CPU_LSU; // Write-data USER signals + + // Input port SI2 (inputs from master 2) + input [31:0] HADDRM2_CPU_FRONT_PORT; // Address bus + input [1:0] HTRANSM2_CPU_FRONT_PORT; // Transfer type + input HWRITEM2_CPU_FRONT_PORT; // Transfer direction + input [2:0] HSIZEM2_CPU_FRONT_PORT; // Transfer size + input [2:0] HBURSTM2_CPU_FRONT_PORT; // Burst type + input [3:0] HPROTM2_CPU_FRONT_PORT; // Protection control + input [31:0] HWDATAM2_CPU_FRONT_PORT; // Write data + input HMASTLOCKM2_CPU_FRONT_PORT; // Locked Sequence + input [31:0] HAUSERM2_CPU_FRONT_PORT; // Address USER signals + input [31:0] HWUSERM2_CPU_FRONT_PORT; // Write-data USER signals + + // Output port MI0 (inputs from slave 0) + input [31:0] HRDATAS0_ROM; // Read data bus + input HREADYOUTS0_ROM; // HREADY feedback + input HRESPS0_ROM; // Transfer response + input [31:0] HRUSERS0_ROM; // Read-data USER signals + + // Output port MI1 (inputs from slave 1) + input [31:0] HRDATAS1_IRAM; // Read data bus + input HREADYOUTS1_IRAM; // HREADY feedback + input HRESPS1_IRAM; // Transfer response + input [31:0] HRUSERS1_IRAM; // Read-data USER signals + + // Output port MI2 (inputs from slave 2) + input [31:0] HRDATAS2_DRAM; // Read data bus + input HREADYOUTS2_DRAM; // HREADY feedback + input HRESPS2_DRAM; // Transfer response + input [31:0] HRUSERS2_DRAM; // Read-data USER signals + + // Output port MI3 (inputs from slave 3) + input [31:0] HRDATAS3_PERIPH; // Read data bus + input HREADYOUTS3_PERIPH; // HREADY feedback + input HRESPS3_PERIPH; // Transfer response + input [31:0] HRUSERS3_PERIPH; // Read-data USER signals + + // Scan test dummy signals; not connected until scan insertion + input SCANENABLE; // Scan enable signal + input SCANINHCLK; // HCLK scan input + + + // Output port MI0 (outputs to slave 0) + output HSELS0_ROM; // Slave Select + output [31:0] HADDRS0_ROM; // Address bus + output [1:0] HTRANSS0_ROM; // Transfer type + output HWRITES0_ROM; // Transfer direction + output [2:0] HSIZES0_ROM; // Transfer size + output [2:0] HBURSTS0_ROM; // Burst type + output [3:0] HPROTS0_ROM; // Protection control + output [31:0] HWDATAS0_ROM; // Write data + output HMASTLOCKS0_ROM; // Locked Sequence + output HREADYMUXS0_ROM; // Transfer done + output [31:0] HAUSERS0_ROM; // Address USER signals + output [31:0] HWUSERS0_ROM; // Write-data USER signals + + // Output port MI1 (outputs to slave 1) + output HSELS1_IRAM; // Slave Select + output [31:0] HADDRS1_IRAM; // Address bus + output [1:0] HTRANSS1_IRAM; // Transfer type + output HWRITES1_IRAM; // Transfer direction + output [2:0] HSIZES1_IRAM; // Transfer size + output [2:0] HBURSTS1_IRAM; // Burst type + output [3:0] HPROTS1_IRAM; // Protection control + output [31:0] HWDATAS1_IRAM; // Write data + output HMASTLOCKS1_IRAM; // Locked Sequence + output HREADYMUXS1_IRAM; // Transfer done + output [31:0] HAUSERS1_IRAM; // Address USER signals + output [31:0] HWUSERS1_IRAM; // Write-data USER signals + + // Output port MI2 (outputs to slave 2) + output HSELS2_DRAM; // Slave Select + output [31:0] HADDRS2_DRAM; // Address bus + output [1:0] HTRANSS2_DRAM; // Transfer type + output HWRITES2_DRAM; // Transfer direction + output [2:0] HSIZES2_DRAM; // Transfer size + output [2:0] HBURSTS2_DRAM; // Burst type + output [3:0] HPROTS2_DRAM; // Protection control + output [31:0] HWDATAS2_DRAM; // Write data + output HMASTLOCKS2_DRAM; // Locked Sequence + output HREADYMUXS2_DRAM; // Transfer done + output [31:0] HAUSERS2_DRAM; // Address USER signals + output [31:0] HWUSERS2_DRAM; // Write-data USER signals + + // Output port MI3 (outputs to slave 3) + output HSELS3_PERIPH; // Slave Select + output [31:0] HADDRS3_PERIPH; // Address bus + output [1:0] HTRANSS3_PERIPH; // Transfer type + output HWRITES3_PERIPH; // Transfer direction + output [2:0] HSIZES3_PERIPH; // Transfer size + output [2:0] HBURSTS3_PERIPH; // Burst type + output [3:0] HPROTS3_PERIPH; // Protection control + output [31:0] HWDATAS3_PERIPH; // Write data + output HMASTLOCKS3_PERIPH; // Locked Sequence + output HREADYMUXS3_PERIPH; // Transfer done + output [31:0] HAUSERS3_PERIPH; // Address USER signals + output [31:0] HWUSERS3_PERIPH; // Write-data USER signals + + // Input port SI0 (outputs to master 0) + output [31:0] HRDATAM0_CPU_FETCH; // Read data bus + output HREADYM0_CPU_FETCH; // HREADY feedback + output HRESPM0_CPU_FETCH; // Transfer response + output [31:0] HRUSERM0_CPU_FETCH; // Read-data USER signals + + // Input port SI1 (outputs to master 1) + output [31:0] HRDATAM1_CPU_LSU; // Read data bus + output HREADYM1_CPU_LSU; // HREADY feedback + output HRESPM1_CPU_LSU; // Transfer response + output [31:0] HRUSERM1_CPU_LSU; // Read-data USER signals + + // Input port SI2 (outputs to master 2) + output [31:0] HRDATAM2_CPU_FRONT_PORT; // Read data bus + output HREADYM2_CPU_FRONT_PORT; // HREADY feedback + output HRESPM2_CPU_FRONT_PORT; // Transfer response + output [31:0] HRUSERM2_CPU_FRONT_PORT; // Read-data USER signals + + // Scan test dummy signals; not connected until scan insertion + output SCANOUTHCLK; // Scan Chain Output + +// ----------------------------------------------------------------------------- +// Wire declarations +// ----------------------------------------------------------------------------- + + // Common AHB signals + wire HCLK; // AHB System Clock + wire HRESETn; // AHB System Reset + + // System Address Remap control + wire [3:0] REMAP; // System REMAP signal + + // Input Port SI0 + wire [31:0] HADDRM0_CPU_FETCH; // Address bus + wire [1:0] HTRANSM0_CPU_FETCH; // Transfer type + wire HWRITEM0_CPU_FETCH; // Transfer direction + wire [2:0] HSIZEM0_CPU_FETCH; // Transfer size + wire [2:0] HBURSTM0_CPU_FETCH; // Burst type + wire [3:0] HPROTM0_CPU_FETCH; // Protection control + wire [31:0] HWDATAM0_CPU_FETCH; // Write data + wire HMASTLOCKM0_CPU_FETCH; // Locked Sequence + + wire [31:0] HRDATAM0_CPU_FETCH; // Read data bus + wire HREADYM0_CPU_FETCH; // HREADY feedback + wire HRESPM0_CPU_FETCH; // Transfer response + wire [31:0] HAUSERM0_CPU_FETCH; // Address USER signals + wire [31:0] HWUSERM0_CPU_FETCH; // Write-data USER signals + wire [31:0] HRUSERM0_CPU_FETCH; // Read-data USER signals + + // Input Port SI1 + wire [31:0] HADDRM1_CPU_LSU; // Address bus + wire [1:0] HTRANSM1_CPU_LSU; // Transfer type + wire HWRITEM1_CPU_LSU; // Transfer direction + wire [2:0] HSIZEM1_CPU_LSU; // Transfer size + wire [2:0] HBURSTM1_CPU_LSU; // Burst type + wire [3:0] HPROTM1_CPU_LSU; // Protection control + wire [31:0] HWDATAM1_CPU_LSU; // Write data + wire HMASTLOCKM1_CPU_LSU; // Locked Sequence + + wire [31:0] HRDATAM1_CPU_LSU; // Read data bus + wire HREADYM1_CPU_LSU; // HREADY feedback + wire HRESPM1_CPU_LSU; // Transfer response + wire [31:0] HAUSERM1_CPU_LSU; // Address USER signals + wire [31:0] HWUSERM1_CPU_LSU; // Write-data USER signals + wire [31:0] HRUSERM1_CPU_LSU; // Read-data USER signals + + // Input Port SI2 + wire [31:0] HADDRM2_CPU_FRONT_PORT; // Address bus + wire [1:0] HTRANSM2_CPU_FRONT_PORT; // Transfer type + wire HWRITEM2_CPU_FRONT_PORT; // Transfer direction + wire [2:0] HSIZEM2_CPU_FRONT_PORT; // Transfer size + wire [2:0] HBURSTM2_CPU_FRONT_PORT; // Burst type + wire [3:0] HPROTM2_CPU_FRONT_PORT; // Protection control + wire [31:0] HWDATAM2_CPU_FRONT_PORT; // Write data + wire HMASTLOCKM2_CPU_FRONT_PORT; // Locked Sequence + + wire [31:0] HRDATAM2_CPU_FRONT_PORT; // Read data bus + wire HREADYM2_CPU_FRONT_PORT; // HREADY feedback + wire HRESPM2_CPU_FRONT_PORT; // Transfer response + wire [31:0] HAUSERM2_CPU_FRONT_PORT; // Address USER signals + wire [31:0] HWUSERM2_CPU_FRONT_PORT; // Write-data USER signals + wire [31:0] HRUSERM2_CPU_FRONT_PORT; // Read-data USER signals + + // Output Port MI0 + wire HSELS0_ROM; // Slave Select + wire [31:0] HADDRS0_ROM; // Address bus + wire [1:0] HTRANSS0_ROM; // Transfer type + wire HWRITES0_ROM; // Transfer direction + wire [2:0] HSIZES0_ROM; // Transfer size + wire [2:0] HBURSTS0_ROM; // Burst type + wire [3:0] HPROTS0_ROM; // Protection control + wire [31:0] HWDATAS0_ROM; // Write data + wire HMASTLOCKS0_ROM; // Locked Sequence + wire HREADYMUXS0_ROM; // Transfer done + + wire [31:0] HRDATAS0_ROM; // Read data bus + wire HREADYOUTS0_ROM; // HREADY feedback + wire HRESPS0_ROM; // Transfer response + wire [31:0] HAUSERS0_ROM; // Address USER signals + wire [31:0] HWUSERS0_ROM; // Write-data USER signals + wire [31:0] HRUSERS0_ROM; // Read-data USER signals + + // Output Port MI1 + wire HSELS1_IRAM; // Slave Select + wire [31:0] HADDRS1_IRAM; // Address bus + wire [1:0] HTRANSS1_IRAM; // Transfer type + wire HWRITES1_IRAM; // Transfer direction + wire [2:0] HSIZES1_IRAM; // Transfer size + wire [2:0] HBURSTS1_IRAM; // Burst type + wire [3:0] HPROTS1_IRAM; // Protection control + wire [31:0] HWDATAS1_IRAM; // Write data + wire HMASTLOCKS1_IRAM; // Locked Sequence + wire HREADYMUXS1_IRAM; // Transfer done + + wire [31:0] HRDATAS1_IRAM; // Read data bus + wire HREADYOUTS1_IRAM; // HREADY feedback + wire HRESPS1_IRAM; // Transfer response + wire [31:0] HAUSERS1_IRAM; // Address USER signals + wire [31:0] HWUSERS1_IRAM; // Write-data USER signals + wire [31:0] HRUSERS1_IRAM; // Read-data USER signals + + // Output Port MI2 + wire HSELS2_DRAM; // Slave Select + wire [31:0] HADDRS2_DRAM; // Address bus + wire [1:0] HTRANSS2_DRAM; // Transfer type + wire HWRITES2_DRAM; // Transfer direction + wire [2:0] HSIZES2_DRAM; // Transfer size + wire [2:0] HBURSTS2_DRAM; // Burst type + wire [3:0] HPROTS2_DRAM; // Protection control + wire [31:0] HWDATAS2_DRAM; // Write data + wire HMASTLOCKS2_DRAM; // Locked Sequence + wire HREADYMUXS2_DRAM; // Transfer done + + wire [31:0] HRDATAS2_DRAM; // Read data bus + wire HREADYOUTS2_DRAM; // HREADY feedback + wire HRESPS2_DRAM; // Transfer response + wire [31:0] HAUSERS2_DRAM; // Address USER signals + wire [31:0] HWUSERS2_DRAM; // Write-data USER signals + wire [31:0] HRUSERS2_DRAM; // Read-data USER signals + + // Output Port MI3 + wire HSELS3_PERIPH; // Slave Select + wire [31:0] HADDRS3_PERIPH; // Address bus + wire [1:0] HTRANSS3_PERIPH; // Transfer type + wire HWRITES3_PERIPH; // Transfer direction + wire [2:0] HSIZES3_PERIPH; // Transfer size + wire [2:0] HBURSTS3_PERIPH; // Burst type + wire [3:0] HPROTS3_PERIPH; // Protection control + wire [31:0] HWDATAS3_PERIPH; // Write data + wire HMASTLOCKS3_PERIPH; // Locked Sequence + wire HREADYMUXS3_PERIPH; // Transfer done + + wire [31:0] HRDATAS3_PERIPH; // Read data bus + wire HREADYOUTS3_PERIPH; // HREADY feedback + wire HRESPS3_PERIPH; // Transfer response + wire [31:0] HAUSERS3_PERIPH; // Address USER signals + wire [31:0] HWUSERS3_PERIPH; // Write-data USER signals + wire [31:0] HRUSERS3_PERIPH; // Read-data USER signals + + +// ----------------------------------------------------------------------------- +// Signal declarations +// ----------------------------------------------------------------------------- + wire [3:0] tie_hi_4; + wire tie_hi; + wire tie_low; + wire [1:0] i_hrespM0_CPU_FETCH; + wire [1:0] i_hrespM1_CPU_LSU; + wire [1:0] i_hrespM2_CPU_FRONT_PORT; + + wire [3:0] i_hmasterS0_ROM; + wire [1:0] i_hrespS0_ROM; + wire [3:0] i_hmasterS1_IRAM; + wire [1:0] i_hrespS1_IRAM; + wire [3:0] i_hmasterS2_DRAM; + wire [1:0] i_hrespS2_DRAM; + wire [3:0] i_hmasterS3_PERIPH; + wire [1:0] i_hrespS3_PERIPH; + +// ----------------------------------------------------------------------------- +// Beginning of main code +// ----------------------------------------------------------------------------- + + assign tie_hi = 1'b1; + assign tie_hi_4 = 4'b1111; + assign tie_low = 1'b0; + + + assign HRESPM0_CPU_FETCH = i_hrespM0_CPU_FETCH[0]; + + assign HRESPM1_CPU_LSU = i_hrespM1_CPU_LSU[0]; + + assign HRESPM2_CPU_FRONT_PORT = i_hrespM2_CPU_FRONT_PORT[0]; + + assign i_hrespS0_ROM = {tie_low, HRESPS0_ROM}; + assign i_hrespS1_IRAM = {tie_low, HRESPS1_IRAM}; + assign i_hrespS2_DRAM = {tie_low, HRESPS2_DRAM}; + assign i_hrespS3_PERIPH = {tie_low, HRESPS3_PERIPH}; + +// BusMatrix instance + nox_intcon unox_intcon ( + .HCLK (HCLK), + .HRESETn (HRESETn), + .REMAP (REMAP), + + // Input port SI0 signals + .HSELM0_CPU_FETCH (tie_hi), + .HADDRM0_CPU_FETCH (HADDRM0_CPU_FETCH), + .HTRANSM0_CPU_FETCH (HTRANSM0_CPU_FETCH), + .HWRITEM0_CPU_FETCH (HWRITEM0_CPU_FETCH), + .HSIZEM0_CPU_FETCH (HSIZEM0_CPU_FETCH), + .HBURSTM0_CPU_FETCH (HBURSTM0_CPU_FETCH), + .HPROTM0_CPU_FETCH (HPROTM0_CPU_FETCH), + .HWDATAM0_CPU_FETCH (HWDATAM0_CPU_FETCH), + .HMASTLOCKM0_CPU_FETCH (HMASTLOCKM0_CPU_FETCH), + .HMASTERM0_CPU_FETCH (tie_hi_4), + .HREADYM0_CPU_FETCH (HREADYM0_CPU_FETCH), + .HAUSERM0_CPU_FETCH (HAUSERM0_CPU_FETCH), + .HWUSERM0_CPU_FETCH (HWUSERM0_CPU_FETCH), + .HRDATAM0_CPU_FETCH (HRDATAM0_CPU_FETCH), + .HREADYOUTM0_CPU_FETCH (HREADYM0_CPU_FETCH), + .HRESPM0_CPU_FETCH (i_hrespM0_CPU_FETCH), + .HRUSERM0_CPU_FETCH (HRUSERM0_CPU_FETCH), + + // Input port SI1 signals + .HSELM1_CPU_LSU (tie_hi), + .HADDRM1_CPU_LSU (HADDRM1_CPU_LSU), + .HTRANSM1_CPU_LSU (HTRANSM1_CPU_LSU), + .HWRITEM1_CPU_LSU (HWRITEM1_CPU_LSU), + .HSIZEM1_CPU_LSU (HSIZEM1_CPU_LSU), + .HBURSTM1_CPU_LSU (HBURSTM1_CPU_LSU), + .HPROTM1_CPU_LSU (HPROTM1_CPU_LSU), + .HWDATAM1_CPU_LSU (HWDATAM1_CPU_LSU), + .HMASTLOCKM1_CPU_LSU (HMASTLOCKM1_CPU_LSU), + .HMASTERM1_CPU_LSU (tie_hi_4), + .HREADYM1_CPU_LSU (HREADYM1_CPU_LSU), + .HAUSERM1_CPU_LSU (HAUSERM1_CPU_LSU), + .HWUSERM1_CPU_LSU (HWUSERM1_CPU_LSU), + .HRDATAM1_CPU_LSU (HRDATAM1_CPU_LSU), + .HREADYOUTM1_CPU_LSU (HREADYM1_CPU_LSU), + .HRESPM1_CPU_LSU (i_hrespM1_CPU_LSU), + .HRUSERM1_CPU_LSU (HRUSERM1_CPU_LSU), + + // Input port SI2 signals + .HSELM2_CPU_FRONT_PORT (tie_hi), + .HADDRM2_CPU_FRONT_PORT (HADDRM2_CPU_FRONT_PORT), + .HTRANSM2_CPU_FRONT_PORT (HTRANSM2_CPU_FRONT_PORT), + .HWRITEM2_CPU_FRONT_PORT (HWRITEM2_CPU_FRONT_PORT), + .HSIZEM2_CPU_FRONT_PORT (HSIZEM2_CPU_FRONT_PORT), + .HBURSTM2_CPU_FRONT_PORT (HBURSTM2_CPU_FRONT_PORT), + .HPROTM2_CPU_FRONT_PORT (HPROTM2_CPU_FRONT_PORT), + .HWDATAM2_CPU_FRONT_PORT (HWDATAM2_CPU_FRONT_PORT), + .HMASTLOCKM2_CPU_FRONT_PORT (HMASTLOCKM2_CPU_FRONT_PORT), + .HMASTERM2_CPU_FRONT_PORT (tie_hi_4), + .HREADYM2_CPU_FRONT_PORT (HREADYM2_CPU_FRONT_PORT), + .HAUSERM2_CPU_FRONT_PORT (HAUSERM2_CPU_FRONT_PORT), + .HWUSERM2_CPU_FRONT_PORT (HWUSERM2_CPU_FRONT_PORT), + .HRDATAM2_CPU_FRONT_PORT (HRDATAM2_CPU_FRONT_PORT), + .HREADYOUTM2_CPU_FRONT_PORT (HREADYM2_CPU_FRONT_PORT), + .HRESPM2_CPU_FRONT_PORT (i_hrespM2_CPU_FRONT_PORT), + .HRUSERM2_CPU_FRONT_PORT (HRUSERM2_CPU_FRONT_PORT), + + + // Output port MI0 signals + .HSELS0_ROM (HSELS0_ROM), + .HADDRS0_ROM (HADDRS0_ROM), + .HTRANSS0_ROM (HTRANSS0_ROM), + .HWRITES0_ROM (HWRITES0_ROM), + .HSIZES0_ROM (HSIZES0_ROM), + .HBURSTS0_ROM (HBURSTS0_ROM), + .HPROTS0_ROM (HPROTS0_ROM), + .HWDATAS0_ROM (HWDATAS0_ROM), + .HMASTERS0_ROM (i_hmasterS0_ROM), + .HMASTLOCKS0_ROM (HMASTLOCKS0_ROM), + .HREADYMUXS0_ROM (HREADYMUXS0_ROM), + .HAUSERS0_ROM (HAUSERS0_ROM), + .HWUSERS0_ROM (HWUSERS0_ROM), + .HRDATAS0_ROM (HRDATAS0_ROM), + .HREADYOUTS0_ROM (HREADYOUTS0_ROM), + .HRESPS0_ROM (i_hrespS0_ROM), + .HRUSERS0_ROM (HRUSERS0_ROM), + + // Output port MI1 signals + .HSELS1_IRAM (HSELS1_IRAM), + .HADDRS1_IRAM (HADDRS1_IRAM), + .HTRANSS1_IRAM (HTRANSS1_IRAM), + .HWRITES1_IRAM (HWRITES1_IRAM), + .HSIZES1_IRAM (HSIZES1_IRAM), + .HBURSTS1_IRAM (HBURSTS1_IRAM), + .HPROTS1_IRAM (HPROTS1_IRAM), + .HWDATAS1_IRAM (HWDATAS1_IRAM), + .HMASTERS1_IRAM (i_hmasterS1_IRAM), + .HMASTLOCKS1_IRAM (HMASTLOCKS1_IRAM), + .HREADYMUXS1_IRAM (HREADYMUXS1_IRAM), + .HAUSERS1_IRAM (HAUSERS1_IRAM), + .HWUSERS1_IRAM (HWUSERS1_IRAM), + .HRDATAS1_IRAM (HRDATAS1_IRAM), + .HREADYOUTS1_IRAM (HREADYOUTS1_IRAM), + .HRESPS1_IRAM (i_hrespS1_IRAM), + .HRUSERS1_IRAM (HRUSERS1_IRAM), + + // Output port MI2 signals + .HSELS2_DRAM (HSELS2_DRAM), + .HADDRS2_DRAM (HADDRS2_DRAM), + .HTRANSS2_DRAM (HTRANSS2_DRAM), + .HWRITES2_DRAM (HWRITES2_DRAM), + .HSIZES2_DRAM (HSIZES2_DRAM), + .HBURSTS2_DRAM (HBURSTS2_DRAM), + .HPROTS2_DRAM (HPROTS2_DRAM), + .HWDATAS2_DRAM (HWDATAS2_DRAM), + .HMASTERS2_DRAM (i_hmasterS2_DRAM), + .HMASTLOCKS2_DRAM (HMASTLOCKS2_DRAM), + .HREADYMUXS2_DRAM (HREADYMUXS2_DRAM), + .HAUSERS2_DRAM (HAUSERS2_DRAM), + .HWUSERS2_DRAM (HWUSERS2_DRAM), + .HRDATAS2_DRAM (HRDATAS2_DRAM), + .HREADYOUTS2_DRAM (HREADYOUTS2_DRAM), + .HRESPS2_DRAM (i_hrespS2_DRAM), + .HRUSERS2_DRAM (HRUSERS2_DRAM), + + // Output port MI3 signals + .HSELS3_PERIPH (HSELS3_PERIPH), + .HADDRS3_PERIPH (HADDRS3_PERIPH), + .HTRANSS3_PERIPH (HTRANSS3_PERIPH), + .HWRITES3_PERIPH (HWRITES3_PERIPH), + .HSIZES3_PERIPH (HSIZES3_PERIPH), + .HBURSTS3_PERIPH (HBURSTS3_PERIPH), + .HPROTS3_PERIPH (HPROTS3_PERIPH), + .HWDATAS3_PERIPH (HWDATAS3_PERIPH), + .HMASTERS3_PERIPH (i_hmasterS3_PERIPH), + .HMASTLOCKS3_PERIPH (HMASTLOCKS3_PERIPH), + .HREADYMUXS3_PERIPH (HREADYMUXS3_PERIPH), + .HAUSERS3_PERIPH (HAUSERS3_PERIPH), + .HWUSERS3_PERIPH (HWUSERS3_PERIPH), + .HRDATAS3_PERIPH (HRDATAS3_PERIPH), + .HREADYOUTS3_PERIPH (HREADYOUTS3_PERIPH), + .HRESPS3_PERIPH (i_hrespS3_PERIPH), + .HRUSERS3_PERIPH (HRUSERS3_PERIPH), + + + // Scan test dummy signals; not connected until scan insertion + .SCANENABLE (SCANENABLE), + .SCANINHCLK (SCANINHCLK), + .SCANOUTHCLK (SCANOUTHCLK) + ); + + +endmodule diff --git a/xlnx/rtl/ahb_interconnect/nox_intcon_outS0_ROM.v b/xlnx/rtl/ahb_interconnect/nox_intcon_outS0_ROM.v new file mode 100644 index 0000000..4b1538f --- /dev/null +++ b/xlnx/rtl/ahb_interconnect/nox_intcon_outS0_ROM.v @@ -0,0 +1,533 @@ +//----------------------------------------------------------------------------- +// The confidential and proprietary information contained in this file may +// only be used by a person authorised under and to the extent permitted +// by a subsisting licensing agreement from ARM Limited. +// +// (C) COPYRIGHT 2001-2013-2024 ARM Limited. +// ALL RIGHTS RESERVED +// +// This entire notice must be reproduced on all copies of this file +// and copies of this file may only be made by a person if such person is +// permitted to do so under the terms of a subsisting license agreement +// from ARM Limited. +// +// SVN Information +// +// Checked In : $Date: 2012-10-15 18:01:36 +0100 (Mon, 15 Oct 2012) $ +// +// Revision : $Revision: 225465 $ +// +// Release Information : Cortex-M System Design Kit-r1p0-01rel0 +// +//----------------------------------------------------------------------------- +// +//----------------------------------------------------------------------------- +// Abstract : The Output Stage is used to route the required input +// stage to the shared slave output. +// +// Notes : The bus matrix has sparse connectivity, +// and has a round arbiter scheme. +// +//----------------------------------------------------------------------------- + +`timescale 1ns/1ps + +module nox_intcon_outS0_ROM ( + + // Common AHB signals + HCLK, + HRESETn, + + // Port 0 Signals + sel_op0, + addr_op0, + auser_op0, + trans_op0, + write_op0, + size_op0, + burst_op0, + prot_op0, + master_op0, + mastlock_op0, + wdata_op0, + wuser_op0, + held_tran_op0, + + // Port 1 Signals + sel_op1, + addr_op1, + auser_op1, + trans_op1, + write_op1, + size_op1, + burst_op1, + prot_op1, + master_op1, + mastlock_op1, + wdata_op1, + wuser_op1, + held_tran_op1, + + // Port 2 Signals + sel_op2, + addr_op2, + auser_op2, + trans_op2, + write_op2, + size_op2, + burst_op2, + prot_op2, + master_op2, + mastlock_op2, + wdata_op2, + wuser_op2, + held_tran_op2, + + // Slave read data and response + HREADYOUTM, + + active_op0, + active_op1, + active_op2, + + // Slave Address/Control Signals + HSELM, + HADDRM, + HAUSERM, + HTRANSM, + HWRITEM, + HSIZEM, + HBURSTM, + HPROTM, + HMASTERM, + HMASTLOCKM, + HREADYMUXM, + HWUSERM, + HWDATAM + + ); + + +// ----------------------------------------------------------------------------- +// Input and Output declarations +// ----------------------------------------------------------------------------- + + // Common AHB signals + input HCLK; // AHB system clock + input HRESETn; // AHB system reset + + // Bus-switch input 0 + input sel_op0; // Port 0 HSEL signal + input [31:0] addr_op0; // Port 0 HADDR signal + input [31:0] auser_op0; // Port 0 HAUSER signal + input [1:0] trans_op0; // Port 0 HTRANS signal + input write_op0; // Port 0 HWRITE signal + input [2:0] size_op0; // Port 0 HSIZE signal + input [2:0] burst_op0; // Port 0 HBURST signal + input [3:0] prot_op0; // Port 0 HPROT signal + input [3:0] master_op0; // Port 0 HMASTER signal + input mastlock_op0; // Port 0 HMASTLOCK signal + input [31:0] wdata_op0; // Port 0 HWDATA signal + input [31:0] wuser_op0; // Port 0 HWUSER signal + input held_tran_op0; // Port 0 HeldTran signal + + // Bus-switch input 1 + input sel_op1; // Port 1 HSEL signal + input [31:0] addr_op1; // Port 1 HADDR signal + input [31:0] auser_op1; // Port 1 HAUSER signal + input [1:0] trans_op1; // Port 1 HTRANS signal + input write_op1; // Port 1 HWRITE signal + input [2:0] size_op1; // Port 1 HSIZE signal + input [2:0] burst_op1; // Port 1 HBURST signal + input [3:0] prot_op1; // Port 1 HPROT signal + input [3:0] master_op1; // Port 1 HMASTER signal + input mastlock_op1; // Port 1 HMASTLOCK signal + input [31:0] wdata_op1; // Port 1 HWDATA signal + input [31:0] wuser_op1; // Port 1 HWUSER signal + input held_tran_op1; // Port 1 HeldTran signal + + // Bus-switch input 2 + input sel_op2; // Port 2 HSEL signal + input [31:0] addr_op2; // Port 2 HADDR signal + input [31:0] auser_op2; // Port 2 HAUSER signal + input [1:0] trans_op2; // Port 2 HTRANS signal + input write_op2; // Port 2 HWRITE signal + input [2:0] size_op2; // Port 2 HSIZE signal + input [2:0] burst_op2; // Port 2 HBURST signal + input [3:0] prot_op2; // Port 2 HPROT signal + input [3:0] master_op2; // Port 2 HMASTER signal + input mastlock_op2; // Port 2 HMASTLOCK signal + input [31:0] wdata_op2; // Port 2 HWDATA signal + input [31:0] wuser_op2; // Port 2 HWUSER signal + input held_tran_op2; // Port 2 HeldTran signal + + input HREADYOUTM; // HREADY feedback + + output active_op0; // Port 0 Active signal + output active_op1; // Port 1 Active signal + output active_op2; // Port 2 Active signal + + // Slave Address/Control Signals + output HSELM; // Slave select line + output [31:0] HADDRM; // Address + output [31:0] HAUSERM; // User Address bus + output [1:0] HTRANSM; // Transfer type + output HWRITEM; // Transfer direction + output [2:0] HSIZEM; // Transfer size + output [2:0] HBURSTM; // Burst type + output [3:0] HPROTM; // Protection control + output [3:0] HMASTERM; // Master ID + output HMASTLOCKM; // Locked transfer + output HREADYMUXM; // Transfer done + output [31:0] HWUSERM; // User data bus + output [31:0] HWDATAM; // Write data + + +// ----------------------------------------------------------------------------- +// Wire declarations +// ----------------------------------------------------------------------------- + wire HCLK; // AHB system clock + wire HRESETn; // AHB system reset + + // Bus-switch input 0 + wire sel_op0; // Port 0 HSEL signal + wire [31:0] addr_op0; // Port 0 HADDR signal + wire [31:0] auser_op0; // Port 0 HAUSER signal + wire [1:0] trans_op0; // Port 0 HTRANS signal + wire write_op0; // Port 0 HWRITE signal + wire [2:0] size_op0; // Port 0 HSIZE signal + wire [2:0] burst_op0; // Port 0 HBURST signal + wire [3:0] prot_op0; // Port 0 HPROT signal + wire [3:0] master_op0; // Port 0 HMASTER signal + wire mastlock_op0; // Port 0 HMASTLOCK signal + wire [31:0] wdata_op0; // Port 0 HWDATA signal + wire [31:0] wuser_op0; // Port 0 HWUSER signal + wire held_tran_op0; // Port 0 HeldTran signal + reg active_op0; // Port 0 Active signal + + // Bus-switch input 1 + wire sel_op1; // Port 1 HSEL signal + wire [31:0] addr_op1; // Port 1 HADDR signal + wire [31:0] auser_op1; // Port 1 HAUSER signal + wire [1:0] trans_op1; // Port 1 HTRANS signal + wire write_op1; // Port 1 HWRITE signal + wire [2:0] size_op1; // Port 1 HSIZE signal + wire [2:0] burst_op1; // Port 1 HBURST signal + wire [3:0] prot_op1; // Port 1 HPROT signal + wire [3:0] master_op1; // Port 1 HMASTER signal + wire mastlock_op1; // Port 1 HMASTLOCK signal + wire [31:0] wdata_op1; // Port 1 HWDATA signal + wire [31:0] wuser_op1; // Port 1 HWUSER signal + wire held_tran_op1; // Port 1 HeldTran signal + reg active_op1; // Port 1 Active signal + + // Bus-switch input 2 + wire sel_op2; // Port 2 HSEL signal + wire [31:0] addr_op2; // Port 2 HADDR signal + wire [31:0] auser_op2; // Port 2 HAUSER signal + wire [1:0] trans_op2; // Port 2 HTRANS signal + wire write_op2; // Port 2 HWRITE signal + wire [2:0] size_op2; // Port 2 HSIZE signal + wire [2:0] burst_op2; // Port 2 HBURST signal + wire [3:0] prot_op2; // Port 2 HPROT signal + wire [3:0] master_op2; // Port 2 HMASTER signal + wire mastlock_op2; // Port 2 HMASTLOCK signal + wire [31:0] wdata_op2; // Port 2 HWDATA signal + wire [31:0] wuser_op2; // Port 2 HWUSER signal + wire held_tran_op2; // Port 2 HeldTran signal + reg active_op2; // Port 2 Active signal + + // Slave Address/Control Signals + wire HSELM; // Slave select line + reg [31:0] HADDRM; // Address + reg [31:0] HAUSERM; // User Address bus + wire [1:0] HTRANSM; // Transfer type + reg HWRITEM; // Transfer direction + reg [2:0] HSIZEM; // Transfer size + wire [2:0] HBURSTM; // Burst type + reg [3:0] HPROTM; // Protection control + reg [3:0] HMASTERM; // Master ID + wire HMASTLOCKM; // Locked transfer + wire HREADYMUXM; // Transfer done + reg [31:0] HWUSERM; // User data bus + reg [31:0] HWDATAM; // Write data + wire HREADYOUTM; // HREADY feedback + + +// ----------------------------------------------------------------------------- +// Signal declarations +// ----------------------------------------------------------------------------- + wire req_port0; // Port 0 request signal + wire req_port1; // Port 1 request signal + wire req_port2; // Port 2 request signal + + wire [1:0] addr_in_port; // Address input port + reg [1:0] data_in_port; // Data input port + wire no_port; // No port selected signal + reg slave_sel; // Slave select signal + + reg hsel_lock; // Held HSELS during locked sequence + wire next_hsel_lock; // Pre-registered hsel_lock + wire hlock_arb; // HMASTLOCK modified by HSEL for arbitration + + reg i_hselm; // Internal HSELM + reg [1:0] i_htransm; // Internal HTRANSM + reg [2:0] i_hburstm; // Internal HBURSTM + wire i_hreadymuxm; // Internal HREADYMUXM + reg i_hmastlockm; // Internal HMASTLOCKM + + +// ----------------------------------------------------------------------------- +// Beginning of main code +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +// Port Selection +// ----------------------------------------------------------------------------- + + assign req_port0 = held_tran_op0 & sel_op0; + assign req_port1 = held_tran_op1 & sel_op1; + assign req_port2 = held_tran_op2 & sel_op2; + + // Arbiter instance for resolving requests to this output stage + nox_intcon_arbS0_ROM u_output_arb ( + + .HCLK (HCLK), + .HRESETn (HRESETn), + + .req_port0 (req_port0), + .req_port1 (req_port1), + .req_port2 (req_port2), + + .HREADYM (i_hreadymuxm), + .HSELM (i_hselm), + .HTRANSM (i_htransm), + .HBURSTM (i_hburstm), + .HMASTLOCKM (hlock_arb), + + .addr_in_port (addr_in_port), + .no_port (no_port) + + ); + + + // Active signal combinatorial decode + always @ (addr_in_port or no_port) + begin : p_active_comb + // Default value(s) + active_op0 = 1'b0; + active_op1 = 1'b0; + active_op2 = 1'b0; + + // Decode selection when enabled + if (~no_port) + case (addr_in_port) + 2'b00 : active_op0 = 1'b1; + 2'b01 : active_op1 = 1'b1; + 2'b10 : active_op2 = 1'b1; + default : begin + active_op0 = 1'bx; + active_op1 = 1'bx; + active_op2 = 1'bx; + end + endcase // case(addr_in_port) + end // block: p_active_comb + + + // Address/control output decode + always @ ( + sel_op0 or addr_op0 or trans_op0 or write_op0 or + size_op0 or burst_op0 or prot_op0 or + auser_op0 or + master_op0 or mastlock_op0 or + sel_op1 or addr_op1 or trans_op1 or write_op1 or + size_op1 or burst_op1 or prot_op1 or + auser_op1 or + master_op1 or mastlock_op1 or + sel_op2 or addr_op2 or trans_op2 or write_op2 or + size_op2 or burst_op2 or prot_op2 or + auser_op2 or + master_op2 or mastlock_op2 or + addr_in_port or no_port + ) + begin : p_addr_mux + // Default values + i_hselm = 1'b0; + HADDRM = {32{1'b0}}; + HAUSERM = {32{1'b0}}; + i_htransm = 2'b00; + HWRITEM = 1'b0; + HSIZEM = 3'b000; + i_hburstm = 3'b000; + HPROTM = {4{1'b0}}; + HMASTERM = 4'b0000; + i_hmastlockm= 1'b0; + + // Decode selection when enabled + if (~no_port) + case (addr_in_port) + // Bus-switch input 0 + 2'b00 : + begin + i_hselm = sel_op0; + HADDRM = addr_op0; + HAUSERM = auser_op0; + i_htransm = trans_op0; + HWRITEM = write_op0; + HSIZEM = size_op0; + i_hburstm = burst_op0; + HPROTM = prot_op0; + HMASTERM = master_op0; + i_hmastlockm= mastlock_op0; + end // case: 4'b00 + + // Bus-switch input 1 + 2'b01 : + begin + i_hselm = sel_op1; + HADDRM = addr_op1; + HAUSERM = auser_op1; + i_htransm = trans_op1; + HWRITEM = write_op1; + HSIZEM = size_op1; + i_hburstm = burst_op1; + HPROTM = prot_op1; + HMASTERM = master_op1; + i_hmastlockm= mastlock_op1; + end // case: 4'b01 + + // Bus-switch input 2 + 2'b10 : + begin + i_hselm = sel_op2; + HADDRM = addr_op2; + HAUSERM = auser_op2; + i_htransm = trans_op2; + HWRITEM = write_op2; + HSIZEM = size_op2; + i_hburstm = burst_op2; + HPROTM = prot_op2; + HMASTERM = master_op2; + i_hmastlockm= mastlock_op2; + end // case: 4'b10 + + default : + begin + i_hselm = 1'bx; + HADDRM = {32{1'bx}}; + HAUSERM = {32{1'bx}}; + i_htransm = 2'bxx; + HWRITEM = 1'bx; + HSIZEM = 3'bxxx; + i_hburstm = 3'bxxx; + HPROTM = {4{1'bx}}; + HMASTERM = 4'bxxxx; + i_hmastlockm= 1'bx; + end // case: default + endcase // case(addr_in_port) + end // block: p_addr_mux + + // hsel_lock provides support for AHB masters that address other + // slave regions in the middle of a locked sequence (i.e. HSEL is + // de-asserted during the locked sequence). Unless HMASTLOCK is + // held during these intermediate cycles, the OutputArb scheme will + // lose track of the locked sequence and may allow another input + // port to access the output port which should be locked + assign next_hsel_lock = (i_hselm & i_htransm[1] & i_hmastlockm) ? 1'b1 : + (i_hmastlockm == 1'b0) ? 1'b0 : + hsel_lock; + + // Register hsel_lock + always @ (negedge HRESETn or posedge HCLK) + begin : p_hsel_lock + if (~HRESETn) + hsel_lock <= 1'b0; + else + if (i_hreadymuxm) + hsel_lock <= next_hsel_lock; + end + + // Version of HMASTLOCK which is masked when not selected, unless a + // locked sequence has already begun through this port + assign hlock_arb = i_hmastlockm & (hsel_lock | i_hselm); + + assign HTRANSM = i_htransm; + assign HBURSTM = i_hburstm; + assign HSELM = i_hselm; + assign HMASTLOCKM = i_hmastlockm; + + // Dataport register + always @ (negedge HRESETn or posedge HCLK) + begin : p_data_in_port_reg + if (~HRESETn) + data_in_port <= {2{1'b0}}; + else + if (i_hreadymuxm) + data_in_port <= addr_in_port; + end + + // HWDATAM output decode + always @ ( + wdata_op0 or + wdata_op1 or + wdata_op2 or + data_in_port + ) + begin : p_data_mux + // Default value + HWDATAM = {32{1'b0}}; + + // Decode selection + case (data_in_port) + 2'b00 : HWDATAM = wdata_op0; + 2'b01 : HWDATAM = wdata_op1; + 2'b10 : HWDATAM = wdata_op2; + default : HWDATAM = {32{1'bx}}; + endcase // case(data_in_port) + end // block: p_data_mux + + // HWUSERM output decode + always @ ( + wuser_op0 or + wuser_op1 or + wuser_op2 or + data_in_port + ) + begin : p_wuser_mux + // Default value + HWUSERM = {32{1'b0}}; + + // Decode selection + case (data_in_port) + 2'b00 : HWUSERM = wuser_op0; + 2'b01 : HWUSERM = wuser_op1; + 2'b10 : HWUSERM = wuser_op2; + default : HWUSERM = {32{1'bx}}; + endcase // case(data_in_port) + end // block: p_wuser_mux + + // --------------------------------------------------------------------------- + // HREADYMUXM generation + // --------------------------------------------------------------------------- + // The HREADY signal on the shared slave is generated directly from + // the shared slave HREADYOUTS if the slave is selected, otherwise + // it mirrors the HREADY signal of the appropriate input port + always @ (negedge HRESETn or posedge HCLK) + begin : p_slave_sel_reg + if (~HRESETn) + slave_sel <= 1'b0; + else + if (i_hreadymuxm) + slave_sel <= i_hselm; + end + + // HREADYMUXM output selection + assign i_hreadymuxm = (slave_sel) ? HREADYOUTM : 1'b1; + + // Drive output with internal version of the signal + assign HREADYMUXM = i_hreadymuxm; + + +endmodule + +// --================================= End ===================================-- diff --git a/xlnx/rtl/ahb_interconnect/nox_intcon_outS1_IRAM.v b/xlnx/rtl/ahb_interconnect/nox_intcon_outS1_IRAM.v new file mode 100644 index 0000000..943e3ce --- /dev/null +++ b/xlnx/rtl/ahb_interconnect/nox_intcon_outS1_IRAM.v @@ -0,0 +1,533 @@ +//----------------------------------------------------------------------------- +// The confidential and proprietary information contained in this file may +// only be used by a person authorised under and to the extent permitted +// by a subsisting licensing agreement from ARM Limited. +// +// (C) COPYRIGHT 2001-2013-2024 ARM Limited. +// ALL RIGHTS RESERVED +// +// This entire notice must be reproduced on all copies of this file +// and copies of this file may only be made by a person if such person is +// permitted to do so under the terms of a subsisting license agreement +// from ARM Limited. +// +// SVN Information +// +// Checked In : $Date: 2012-10-15 18:01:36 +0100 (Mon, 15 Oct 2012) $ +// +// Revision : $Revision: 225465 $ +// +// Release Information : Cortex-M System Design Kit-r1p0-01rel0 +// +//----------------------------------------------------------------------------- +// +//----------------------------------------------------------------------------- +// Abstract : The Output Stage is used to route the required input +// stage to the shared slave output. +// +// Notes : The bus matrix has sparse connectivity, +// and has a round arbiter scheme. +// +//----------------------------------------------------------------------------- + +`timescale 1ns/1ps + +module nox_intcon_outS1_IRAM ( + + // Common AHB signals + HCLK, + HRESETn, + + // Port 0 Signals + sel_op0, + addr_op0, + auser_op0, + trans_op0, + write_op0, + size_op0, + burst_op0, + prot_op0, + master_op0, + mastlock_op0, + wdata_op0, + wuser_op0, + held_tran_op0, + + // Port 1 Signals + sel_op1, + addr_op1, + auser_op1, + trans_op1, + write_op1, + size_op1, + burst_op1, + prot_op1, + master_op1, + mastlock_op1, + wdata_op1, + wuser_op1, + held_tran_op1, + + // Port 2 Signals + sel_op2, + addr_op2, + auser_op2, + trans_op2, + write_op2, + size_op2, + burst_op2, + prot_op2, + master_op2, + mastlock_op2, + wdata_op2, + wuser_op2, + held_tran_op2, + + // Slave read data and response + HREADYOUTM, + + active_op0, + active_op1, + active_op2, + + // Slave Address/Control Signals + HSELM, + HADDRM, + HAUSERM, + HTRANSM, + HWRITEM, + HSIZEM, + HBURSTM, + HPROTM, + HMASTERM, + HMASTLOCKM, + HREADYMUXM, + HWUSERM, + HWDATAM + + ); + + +// ----------------------------------------------------------------------------- +// Input and Output declarations +// ----------------------------------------------------------------------------- + + // Common AHB signals + input HCLK; // AHB system clock + input HRESETn; // AHB system reset + + // Bus-switch input 0 + input sel_op0; // Port 0 HSEL signal + input [31:0] addr_op0; // Port 0 HADDR signal + input [31:0] auser_op0; // Port 0 HAUSER signal + input [1:0] trans_op0; // Port 0 HTRANS signal + input write_op0; // Port 0 HWRITE signal + input [2:0] size_op0; // Port 0 HSIZE signal + input [2:0] burst_op0; // Port 0 HBURST signal + input [3:0] prot_op0; // Port 0 HPROT signal + input [3:0] master_op0; // Port 0 HMASTER signal + input mastlock_op0; // Port 0 HMASTLOCK signal + input [31:0] wdata_op0; // Port 0 HWDATA signal + input [31:0] wuser_op0; // Port 0 HWUSER signal + input held_tran_op0; // Port 0 HeldTran signal + + // Bus-switch input 1 + input sel_op1; // Port 1 HSEL signal + input [31:0] addr_op1; // Port 1 HADDR signal + input [31:0] auser_op1; // Port 1 HAUSER signal + input [1:0] trans_op1; // Port 1 HTRANS signal + input write_op1; // Port 1 HWRITE signal + input [2:0] size_op1; // Port 1 HSIZE signal + input [2:0] burst_op1; // Port 1 HBURST signal + input [3:0] prot_op1; // Port 1 HPROT signal + input [3:0] master_op1; // Port 1 HMASTER signal + input mastlock_op1; // Port 1 HMASTLOCK signal + input [31:0] wdata_op1; // Port 1 HWDATA signal + input [31:0] wuser_op1; // Port 1 HWUSER signal + input held_tran_op1; // Port 1 HeldTran signal + + // Bus-switch input 2 + input sel_op2; // Port 2 HSEL signal + input [31:0] addr_op2; // Port 2 HADDR signal + input [31:0] auser_op2; // Port 2 HAUSER signal + input [1:0] trans_op2; // Port 2 HTRANS signal + input write_op2; // Port 2 HWRITE signal + input [2:0] size_op2; // Port 2 HSIZE signal + input [2:0] burst_op2; // Port 2 HBURST signal + input [3:0] prot_op2; // Port 2 HPROT signal + input [3:0] master_op2; // Port 2 HMASTER signal + input mastlock_op2; // Port 2 HMASTLOCK signal + input [31:0] wdata_op2; // Port 2 HWDATA signal + input [31:0] wuser_op2; // Port 2 HWUSER signal + input held_tran_op2; // Port 2 HeldTran signal + + input HREADYOUTM; // HREADY feedback + + output active_op0; // Port 0 Active signal + output active_op1; // Port 1 Active signal + output active_op2; // Port 2 Active signal + + // Slave Address/Control Signals + output HSELM; // Slave select line + output [31:0] HADDRM; // Address + output [31:0] HAUSERM; // User Address bus + output [1:0] HTRANSM; // Transfer type + output HWRITEM; // Transfer direction + output [2:0] HSIZEM; // Transfer size + output [2:0] HBURSTM; // Burst type + output [3:0] HPROTM; // Protection control + output [3:0] HMASTERM; // Master ID + output HMASTLOCKM; // Locked transfer + output HREADYMUXM; // Transfer done + output [31:0] HWUSERM; // User data bus + output [31:0] HWDATAM; // Write data + + +// ----------------------------------------------------------------------------- +// Wire declarations +// ----------------------------------------------------------------------------- + wire HCLK; // AHB system clock + wire HRESETn; // AHB system reset + + // Bus-switch input 0 + wire sel_op0; // Port 0 HSEL signal + wire [31:0] addr_op0; // Port 0 HADDR signal + wire [31:0] auser_op0; // Port 0 HAUSER signal + wire [1:0] trans_op0; // Port 0 HTRANS signal + wire write_op0; // Port 0 HWRITE signal + wire [2:0] size_op0; // Port 0 HSIZE signal + wire [2:0] burst_op0; // Port 0 HBURST signal + wire [3:0] prot_op0; // Port 0 HPROT signal + wire [3:0] master_op0; // Port 0 HMASTER signal + wire mastlock_op0; // Port 0 HMASTLOCK signal + wire [31:0] wdata_op0; // Port 0 HWDATA signal + wire [31:0] wuser_op0; // Port 0 HWUSER signal + wire held_tran_op0; // Port 0 HeldTran signal + reg active_op0; // Port 0 Active signal + + // Bus-switch input 1 + wire sel_op1; // Port 1 HSEL signal + wire [31:0] addr_op1; // Port 1 HADDR signal + wire [31:0] auser_op1; // Port 1 HAUSER signal + wire [1:0] trans_op1; // Port 1 HTRANS signal + wire write_op1; // Port 1 HWRITE signal + wire [2:0] size_op1; // Port 1 HSIZE signal + wire [2:0] burst_op1; // Port 1 HBURST signal + wire [3:0] prot_op1; // Port 1 HPROT signal + wire [3:0] master_op1; // Port 1 HMASTER signal + wire mastlock_op1; // Port 1 HMASTLOCK signal + wire [31:0] wdata_op1; // Port 1 HWDATA signal + wire [31:0] wuser_op1; // Port 1 HWUSER signal + wire held_tran_op1; // Port 1 HeldTran signal + reg active_op1; // Port 1 Active signal + + // Bus-switch input 2 + wire sel_op2; // Port 2 HSEL signal + wire [31:0] addr_op2; // Port 2 HADDR signal + wire [31:0] auser_op2; // Port 2 HAUSER signal + wire [1:0] trans_op2; // Port 2 HTRANS signal + wire write_op2; // Port 2 HWRITE signal + wire [2:0] size_op2; // Port 2 HSIZE signal + wire [2:0] burst_op2; // Port 2 HBURST signal + wire [3:0] prot_op2; // Port 2 HPROT signal + wire [3:0] master_op2; // Port 2 HMASTER signal + wire mastlock_op2; // Port 2 HMASTLOCK signal + wire [31:0] wdata_op2; // Port 2 HWDATA signal + wire [31:0] wuser_op2; // Port 2 HWUSER signal + wire held_tran_op2; // Port 2 HeldTran signal + reg active_op2; // Port 2 Active signal + + // Slave Address/Control Signals + wire HSELM; // Slave select line + reg [31:0] HADDRM; // Address + reg [31:0] HAUSERM; // User Address bus + wire [1:0] HTRANSM; // Transfer type + reg HWRITEM; // Transfer direction + reg [2:0] HSIZEM; // Transfer size + wire [2:0] HBURSTM; // Burst type + reg [3:0] HPROTM; // Protection control + reg [3:0] HMASTERM; // Master ID + wire HMASTLOCKM; // Locked transfer + wire HREADYMUXM; // Transfer done + reg [31:0] HWUSERM; // User data bus + reg [31:0] HWDATAM; // Write data + wire HREADYOUTM; // HREADY feedback + + +// ----------------------------------------------------------------------------- +// Signal declarations +// ----------------------------------------------------------------------------- + wire req_port0; // Port 0 request signal + wire req_port1; // Port 1 request signal + wire req_port2; // Port 2 request signal + + wire [1:0] addr_in_port; // Address input port + reg [1:0] data_in_port; // Data input port + wire no_port; // No port selected signal + reg slave_sel; // Slave select signal + + reg hsel_lock; // Held HSELS during locked sequence + wire next_hsel_lock; // Pre-registered hsel_lock + wire hlock_arb; // HMASTLOCK modified by HSEL for arbitration + + reg i_hselm; // Internal HSELM + reg [1:0] i_htransm; // Internal HTRANSM + reg [2:0] i_hburstm; // Internal HBURSTM + wire i_hreadymuxm; // Internal HREADYMUXM + reg i_hmastlockm; // Internal HMASTLOCKM + + +// ----------------------------------------------------------------------------- +// Beginning of main code +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +// Port Selection +// ----------------------------------------------------------------------------- + + assign req_port0 = held_tran_op0 & sel_op0; + assign req_port1 = held_tran_op1 & sel_op1; + assign req_port2 = held_tran_op2 & sel_op2; + + // Arbiter instance for resolving requests to this output stage + nox_intcon_arbS1_IRAM u_output_arb ( + + .HCLK (HCLK), + .HRESETn (HRESETn), + + .req_port0 (req_port0), + .req_port1 (req_port1), + .req_port2 (req_port2), + + .HREADYM (i_hreadymuxm), + .HSELM (i_hselm), + .HTRANSM (i_htransm), + .HBURSTM (i_hburstm), + .HMASTLOCKM (hlock_arb), + + .addr_in_port (addr_in_port), + .no_port (no_port) + + ); + + + // Active signal combinatorial decode + always @ (addr_in_port or no_port) + begin : p_active_comb + // Default value(s) + active_op0 = 1'b0; + active_op1 = 1'b0; + active_op2 = 1'b0; + + // Decode selection when enabled + if (~no_port) + case (addr_in_port) + 2'b00 : active_op0 = 1'b1; + 2'b01 : active_op1 = 1'b1; + 2'b10 : active_op2 = 1'b1; + default : begin + active_op0 = 1'bx; + active_op1 = 1'bx; + active_op2 = 1'bx; + end + endcase // case(addr_in_port) + end // block: p_active_comb + + + // Address/control output decode + always @ ( + sel_op0 or addr_op0 or trans_op0 or write_op0 or + size_op0 or burst_op0 or prot_op0 or + auser_op0 or + master_op0 or mastlock_op0 or + sel_op1 or addr_op1 or trans_op1 or write_op1 or + size_op1 or burst_op1 or prot_op1 or + auser_op1 or + master_op1 or mastlock_op1 or + sel_op2 or addr_op2 or trans_op2 or write_op2 or + size_op2 or burst_op2 or prot_op2 or + auser_op2 or + master_op2 or mastlock_op2 or + addr_in_port or no_port + ) + begin : p_addr_mux + // Default values + i_hselm = 1'b0; + HADDRM = {32{1'b0}}; + HAUSERM = {32{1'b0}}; + i_htransm = 2'b00; + HWRITEM = 1'b0; + HSIZEM = 3'b000; + i_hburstm = 3'b000; + HPROTM = {4{1'b0}}; + HMASTERM = 4'b0000; + i_hmastlockm= 1'b0; + + // Decode selection when enabled + if (~no_port) + case (addr_in_port) + // Bus-switch input 0 + 2'b00 : + begin + i_hselm = sel_op0; + HADDRM = addr_op0; + HAUSERM = auser_op0; + i_htransm = trans_op0; + HWRITEM = write_op0; + HSIZEM = size_op0; + i_hburstm = burst_op0; + HPROTM = prot_op0; + HMASTERM = master_op0; + i_hmastlockm= mastlock_op0; + end // case: 4'b00 + + // Bus-switch input 1 + 2'b01 : + begin + i_hselm = sel_op1; + HADDRM = addr_op1; + HAUSERM = auser_op1; + i_htransm = trans_op1; + HWRITEM = write_op1; + HSIZEM = size_op1; + i_hburstm = burst_op1; + HPROTM = prot_op1; + HMASTERM = master_op1; + i_hmastlockm= mastlock_op1; + end // case: 4'b01 + + // Bus-switch input 2 + 2'b10 : + begin + i_hselm = sel_op2; + HADDRM = addr_op2; + HAUSERM = auser_op2; + i_htransm = trans_op2; + HWRITEM = write_op2; + HSIZEM = size_op2; + i_hburstm = burst_op2; + HPROTM = prot_op2; + HMASTERM = master_op2; + i_hmastlockm= mastlock_op2; + end // case: 4'b10 + + default : + begin + i_hselm = 1'bx; + HADDRM = {32{1'bx}}; + HAUSERM = {32{1'bx}}; + i_htransm = 2'bxx; + HWRITEM = 1'bx; + HSIZEM = 3'bxxx; + i_hburstm = 3'bxxx; + HPROTM = {4{1'bx}}; + HMASTERM = 4'bxxxx; + i_hmastlockm= 1'bx; + end // case: default + endcase // case(addr_in_port) + end // block: p_addr_mux + + // hsel_lock provides support for AHB masters that address other + // slave regions in the middle of a locked sequence (i.e. HSEL is + // de-asserted during the locked sequence). Unless HMASTLOCK is + // held during these intermediate cycles, the OutputArb scheme will + // lose track of the locked sequence and may allow another input + // port to access the output port which should be locked + assign next_hsel_lock = (i_hselm & i_htransm[1] & i_hmastlockm) ? 1'b1 : + (i_hmastlockm == 1'b0) ? 1'b0 : + hsel_lock; + + // Register hsel_lock + always @ (negedge HRESETn or posedge HCLK) + begin : p_hsel_lock + if (~HRESETn) + hsel_lock <= 1'b0; + else + if (i_hreadymuxm) + hsel_lock <= next_hsel_lock; + end + + // Version of HMASTLOCK which is masked when not selected, unless a + // locked sequence has already begun through this port + assign hlock_arb = i_hmastlockm & (hsel_lock | i_hselm); + + assign HTRANSM = i_htransm; + assign HBURSTM = i_hburstm; + assign HSELM = i_hselm; + assign HMASTLOCKM = i_hmastlockm; + + // Dataport register + always @ (negedge HRESETn or posedge HCLK) + begin : p_data_in_port_reg + if (~HRESETn) + data_in_port <= {2{1'b0}}; + else + if (i_hreadymuxm) + data_in_port <= addr_in_port; + end + + // HWDATAM output decode + always @ ( + wdata_op0 or + wdata_op1 or + wdata_op2 or + data_in_port + ) + begin : p_data_mux + // Default value + HWDATAM = {32{1'b0}}; + + // Decode selection + case (data_in_port) + 2'b00 : HWDATAM = wdata_op0; + 2'b01 : HWDATAM = wdata_op1; + 2'b10 : HWDATAM = wdata_op2; + default : HWDATAM = {32{1'bx}}; + endcase // case(data_in_port) + end // block: p_data_mux + + // HWUSERM output decode + always @ ( + wuser_op0 or + wuser_op1 or + wuser_op2 or + data_in_port + ) + begin : p_wuser_mux + // Default value + HWUSERM = {32{1'b0}}; + + // Decode selection + case (data_in_port) + 2'b00 : HWUSERM = wuser_op0; + 2'b01 : HWUSERM = wuser_op1; + 2'b10 : HWUSERM = wuser_op2; + default : HWUSERM = {32{1'bx}}; + endcase // case(data_in_port) + end // block: p_wuser_mux + + // --------------------------------------------------------------------------- + // HREADYMUXM generation + // --------------------------------------------------------------------------- + // The HREADY signal on the shared slave is generated directly from + // the shared slave HREADYOUTS if the slave is selected, otherwise + // it mirrors the HREADY signal of the appropriate input port + always @ (negedge HRESETn or posedge HCLK) + begin : p_slave_sel_reg + if (~HRESETn) + slave_sel <= 1'b0; + else + if (i_hreadymuxm) + slave_sel <= i_hselm; + end + + // HREADYMUXM output selection + assign i_hreadymuxm = (slave_sel) ? HREADYOUTM : 1'b1; + + // Drive output with internal version of the signal + assign HREADYMUXM = i_hreadymuxm; + + +endmodule + +// --================================= End ===================================-- diff --git a/xlnx/rtl/ahb_interconnect/nox_intcon_outS2_DRAM.v b/xlnx/rtl/ahb_interconnect/nox_intcon_outS2_DRAM.v new file mode 100644 index 0000000..b02fa9e --- /dev/null +++ b/xlnx/rtl/ahb_interconnect/nox_intcon_outS2_DRAM.v @@ -0,0 +1,456 @@ +//----------------------------------------------------------------------------- +// The confidential and proprietary information contained in this file may +// only be used by a person authorised under and to the extent permitted +// by a subsisting licensing agreement from ARM Limited. +// +// (C) COPYRIGHT 2001-2013-2024 ARM Limited. +// ALL RIGHTS RESERVED +// +// This entire notice must be reproduced on all copies of this file +// and copies of this file may only be made by a person if such person is +// permitted to do so under the terms of a subsisting license agreement +// from ARM Limited. +// +// SVN Information +// +// Checked In : $Date: 2012-10-15 18:01:36 +0100 (Mon, 15 Oct 2012) $ +// +// Revision : $Revision: 225465 $ +// +// Release Information : Cortex-M System Design Kit-r1p0-01rel0 +// +//----------------------------------------------------------------------------- +// +//----------------------------------------------------------------------------- +// Abstract : The Output Stage is used to route the required input +// stage to the shared slave output. +// +// Notes : The bus matrix has sparse connectivity, +// and has a round arbiter scheme. +// +//----------------------------------------------------------------------------- + +`timescale 1ns/1ps + +module nox_intcon_outS2_DRAM ( + + // Common AHB signals + HCLK, + HRESETn, + + // Port 1 Signals + sel_op1, + addr_op1, + auser_op1, + trans_op1, + write_op1, + size_op1, + burst_op1, + prot_op1, + master_op1, + mastlock_op1, + wdata_op1, + wuser_op1, + held_tran_op1, + + // Port 2 Signals + sel_op2, + addr_op2, + auser_op2, + trans_op2, + write_op2, + size_op2, + burst_op2, + prot_op2, + master_op2, + mastlock_op2, + wdata_op2, + wuser_op2, + held_tran_op2, + + // Slave read data and response + HREADYOUTM, + + active_op1, + active_op2, + + // Slave Address/Control Signals + HSELM, + HADDRM, + HAUSERM, + HTRANSM, + HWRITEM, + HSIZEM, + HBURSTM, + HPROTM, + HMASTERM, + HMASTLOCKM, + HREADYMUXM, + HWUSERM, + HWDATAM + + ); + + +// ----------------------------------------------------------------------------- +// Input and Output declarations +// ----------------------------------------------------------------------------- + + // Common AHB signals + input HCLK; // AHB system clock + input HRESETn; // AHB system reset + + // Bus-switch input 1 + input sel_op1; // Port 1 HSEL signal + input [31:0] addr_op1; // Port 1 HADDR signal + input [31:0] auser_op1; // Port 1 HAUSER signal + input [1:0] trans_op1; // Port 1 HTRANS signal + input write_op1; // Port 1 HWRITE signal + input [2:0] size_op1; // Port 1 HSIZE signal + input [2:0] burst_op1; // Port 1 HBURST signal + input [3:0] prot_op1; // Port 1 HPROT signal + input [3:0] master_op1; // Port 1 HMASTER signal + input mastlock_op1; // Port 1 HMASTLOCK signal + input [31:0] wdata_op1; // Port 1 HWDATA signal + input [31:0] wuser_op1; // Port 1 HWUSER signal + input held_tran_op1; // Port 1 HeldTran signal + + // Bus-switch input 2 + input sel_op2; // Port 2 HSEL signal + input [31:0] addr_op2; // Port 2 HADDR signal + input [31:0] auser_op2; // Port 2 HAUSER signal + input [1:0] trans_op2; // Port 2 HTRANS signal + input write_op2; // Port 2 HWRITE signal + input [2:0] size_op2; // Port 2 HSIZE signal + input [2:0] burst_op2; // Port 2 HBURST signal + input [3:0] prot_op2; // Port 2 HPROT signal + input [3:0] master_op2; // Port 2 HMASTER signal + input mastlock_op2; // Port 2 HMASTLOCK signal + input [31:0] wdata_op2; // Port 2 HWDATA signal + input [31:0] wuser_op2; // Port 2 HWUSER signal + input held_tran_op2; // Port 2 HeldTran signal + + input HREADYOUTM; // HREADY feedback + + output active_op1; // Port 1 Active signal + output active_op2; // Port 2 Active signal + + // Slave Address/Control Signals + output HSELM; // Slave select line + output [31:0] HADDRM; // Address + output [31:0] HAUSERM; // User Address bus + output [1:0] HTRANSM; // Transfer type + output HWRITEM; // Transfer direction + output [2:0] HSIZEM; // Transfer size + output [2:0] HBURSTM; // Burst type + output [3:0] HPROTM; // Protection control + output [3:0] HMASTERM; // Master ID + output HMASTLOCKM; // Locked transfer + output HREADYMUXM; // Transfer done + output [31:0] HWUSERM; // User data bus + output [31:0] HWDATAM; // Write data + + +// ----------------------------------------------------------------------------- +// Wire declarations +// ----------------------------------------------------------------------------- + wire HCLK; // AHB system clock + wire HRESETn; // AHB system reset + + // Bus-switch input 1 + wire sel_op1; // Port 1 HSEL signal + wire [31:0] addr_op1; // Port 1 HADDR signal + wire [31:0] auser_op1; // Port 1 HAUSER signal + wire [1:0] trans_op1; // Port 1 HTRANS signal + wire write_op1; // Port 1 HWRITE signal + wire [2:0] size_op1; // Port 1 HSIZE signal + wire [2:0] burst_op1; // Port 1 HBURST signal + wire [3:0] prot_op1; // Port 1 HPROT signal + wire [3:0] master_op1; // Port 1 HMASTER signal + wire mastlock_op1; // Port 1 HMASTLOCK signal + wire [31:0] wdata_op1; // Port 1 HWDATA signal + wire [31:0] wuser_op1; // Port 1 HWUSER signal + wire held_tran_op1; // Port 1 HeldTran signal + reg active_op1; // Port 1 Active signal + + // Bus-switch input 2 + wire sel_op2; // Port 2 HSEL signal + wire [31:0] addr_op2; // Port 2 HADDR signal + wire [31:0] auser_op2; // Port 2 HAUSER signal + wire [1:0] trans_op2; // Port 2 HTRANS signal + wire write_op2; // Port 2 HWRITE signal + wire [2:0] size_op2; // Port 2 HSIZE signal + wire [2:0] burst_op2; // Port 2 HBURST signal + wire [3:0] prot_op2; // Port 2 HPROT signal + wire [3:0] master_op2; // Port 2 HMASTER signal + wire mastlock_op2; // Port 2 HMASTLOCK signal + wire [31:0] wdata_op2; // Port 2 HWDATA signal + wire [31:0] wuser_op2; // Port 2 HWUSER signal + wire held_tran_op2; // Port 2 HeldTran signal + reg active_op2; // Port 2 Active signal + + // Slave Address/Control Signals + wire HSELM; // Slave select line + reg [31:0] HADDRM; // Address + reg [31:0] HAUSERM; // User Address bus + wire [1:0] HTRANSM; // Transfer type + reg HWRITEM; // Transfer direction + reg [2:0] HSIZEM; // Transfer size + wire [2:0] HBURSTM; // Burst type + reg [3:0] HPROTM; // Protection control + reg [3:0] HMASTERM; // Master ID + wire HMASTLOCKM; // Locked transfer + wire HREADYMUXM; // Transfer done + reg [31:0] HWUSERM; // User data bus + reg [31:0] HWDATAM; // Write data + wire HREADYOUTM; // HREADY feedback + + +// ----------------------------------------------------------------------------- +// Signal declarations +// ----------------------------------------------------------------------------- + wire req_port1; // Port 1 request signal + wire req_port2; // Port 2 request signal + + wire [1:0] addr_in_port; // Address input port + reg [1:0] data_in_port; // Data input port + wire no_port; // No port selected signal + reg slave_sel; // Slave select signal + + reg hsel_lock; // Held HSELS during locked sequence + wire next_hsel_lock; // Pre-registered hsel_lock + wire hlock_arb; // HMASTLOCK modified by HSEL for arbitration + + reg i_hselm; // Internal HSELM + reg [1:0] i_htransm; // Internal HTRANSM + reg [2:0] i_hburstm; // Internal HBURSTM + wire i_hreadymuxm; // Internal HREADYMUXM + reg i_hmastlockm; // Internal HMASTLOCKM + + +// ----------------------------------------------------------------------------- +// Beginning of main code +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +// Port Selection +// ----------------------------------------------------------------------------- + + assign req_port1 = held_tran_op1 & sel_op1; + assign req_port2 = held_tran_op2 & sel_op2; + + // Arbiter instance for resolving requests to this output stage + nox_intcon_arbS2_DRAM u_output_arb ( + + .HCLK (HCLK), + .HRESETn (HRESETn), + + .req_port1 (req_port1), + .req_port2 (req_port2), + + .HREADYM (i_hreadymuxm), + .HSELM (i_hselm), + .HTRANSM (i_htransm), + .HBURSTM (i_hburstm), + .HMASTLOCKM (hlock_arb), + + .addr_in_port (addr_in_port), + .no_port (no_port) + + ); + + + // Active signal combinatorial decode + always @ (addr_in_port or no_port) + begin : p_active_comb + // Default value(s) + active_op1 = 1'b0; + active_op2 = 1'b0; + + // Decode selection when enabled + if (~no_port) + case (addr_in_port) + 2'b01 : active_op1 = 1'b1; + 2'b10 : active_op2 = 1'b1; + default : begin + active_op1 = 1'bx; + active_op2 = 1'bx; + end + endcase // case(addr_in_port) + end // block: p_active_comb + + + // Address/control output decode + always @ ( + sel_op1 or addr_op1 or trans_op1 or write_op1 or + size_op1 or burst_op1 or prot_op1 or + auser_op1 or + master_op1 or mastlock_op1 or + sel_op2 or addr_op2 or trans_op2 or write_op2 or + size_op2 or burst_op2 or prot_op2 or + auser_op2 or + master_op2 or mastlock_op2 or + addr_in_port or no_port + ) + begin : p_addr_mux + // Default values + i_hselm = 1'b0; + HADDRM = {32{1'b0}}; + HAUSERM = {32{1'b0}}; + i_htransm = 2'b00; + HWRITEM = 1'b0; + HSIZEM = 3'b000; + i_hburstm = 3'b000; + HPROTM = {4{1'b0}}; + HMASTERM = 4'b0000; + i_hmastlockm= 1'b0; + + // Decode selection when enabled + if (~no_port) + case (addr_in_port) + // Bus-switch input 1 + 2'b01 : + begin + i_hselm = sel_op1; + HADDRM = addr_op1; + HAUSERM = auser_op1; + i_htransm = trans_op1; + HWRITEM = write_op1; + HSIZEM = size_op1; + i_hburstm = burst_op1; + HPROTM = prot_op1; + HMASTERM = master_op1; + i_hmastlockm= mastlock_op1; + end // case: 4'b01 + + // Bus-switch input 2 + 2'b10 : + begin + i_hselm = sel_op2; + HADDRM = addr_op2; + HAUSERM = auser_op2; + i_htransm = trans_op2; + HWRITEM = write_op2; + HSIZEM = size_op2; + i_hburstm = burst_op2; + HPROTM = prot_op2; + HMASTERM = master_op2; + i_hmastlockm= mastlock_op2; + end // case: 4'b10 + + default : + begin + i_hselm = 1'bx; + HADDRM = {32{1'bx}}; + HAUSERM = {32{1'bx}}; + i_htransm = 2'bxx; + HWRITEM = 1'bx; + HSIZEM = 3'bxxx; + i_hburstm = 3'bxxx; + HPROTM = {4{1'bx}}; + HMASTERM = 4'bxxxx; + i_hmastlockm= 1'bx; + end // case: default + endcase // case(addr_in_port) + end // block: p_addr_mux + + // hsel_lock provides support for AHB masters that address other + // slave regions in the middle of a locked sequence (i.e. HSEL is + // de-asserted during the locked sequence). Unless HMASTLOCK is + // held during these intermediate cycles, the OutputArb scheme will + // lose track of the locked sequence and may allow another input + // port to access the output port which should be locked + assign next_hsel_lock = (i_hselm & i_htransm[1] & i_hmastlockm) ? 1'b1 : + (i_hmastlockm == 1'b0) ? 1'b0 : + hsel_lock; + + // Register hsel_lock + always @ (negedge HRESETn or posedge HCLK) + begin : p_hsel_lock + if (~HRESETn) + hsel_lock <= 1'b0; + else + if (i_hreadymuxm) + hsel_lock <= next_hsel_lock; + end + + // Version of HMASTLOCK which is masked when not selected, unless a + // locked sequence has already begun through this port + assign hlock_arb = i_hmastlockm & (hsel_lock | i_hselm); + + assign HTRANSM = i_htransm; + assign HBURSTM = i_hburstm; + assign HSELM = i_hselm; + assign HMASTLOCKM = i_hmastlockm; + + // Dataport register + always @ (negedge HRESETn or posedge HCLK) + begin : p_data_in_port_reg + if (~HRESETn) + data_in_port <= {2{1'b0}}; + else + if (i_hreadymuxm) + data_in_port <= addr_in_port; + end + + // HWDATAM output decode + always @ ( + wdata_op1 or + wdata_op2 or + data_in_port + ) + begin : p_data_mux + // Default value + HWDATAM = {32{1'b0}}; + + // Decode selection + case (data_in_port) + 2'b01 : HWDATAM = wdata_op1; + 2'b10 : HWDATAM = wdata_op2; + default : HWDATAM = {32{1'bx}}; + endcase // case(data_in_port) + end // block: p_data_mux + + // HWUSERM output decode + always @ ( + wuser_op1 or + wuser_op2 or + data_in_port + ) + begin : p_wuser_mux + // Default value + HWUSERM = {32{1'b0}}; + + // Decode selection + case (data_in_port) + 2'b01 : HWUSERM = wuser_op1; + 2'b10 : HWUSERM = wuser_op2; + default : HWUSERM = {32{1'bx}}; + endcase // case(data_in_port) + end // block: p_wuser_mux + + // --------------------------------------------------------------------------- + // HREADYMUXM generation + // --------------------------------------------------------------------------- + // The HREADY signal on the shared slave is generated directly from + // the shared slave HREADYOUTS if the slave is selected, otherwise + // it mirrors the HREADY signal of the appropriate input port + always @ (negedge HRESETn or posedge HCLK) + begin : p_slave_sel_reg + if (~HRESETn) + slave_sel <= 1'b0; + else + if (i_hreadymuxm) + slave_sel <= i_hselm; + end + + // HREADYMUXM output selection + assign i_hreadymuxm = (slave_sel) ? HREADYOUTM : 1'b1; + + // Drive output with internal version of the signal + assign HREADYMUXM = i_hreadymuxm; + + +endmodule + +// --================================= End ===================================-- diff --git a/xlnx/rtl/ahb_interconnect/nox_intcon_outS3_PERIPH.v b/xlnx/rtl/ahb_interconnect/nox_intcon_outS3_PERIPH.v new file mode 100644 index 0000000..5bd59e9 --- /dev/null +++ b/xlnx/rtl/ahb_interconnect/nox_intcon_outS3_PERIPH.v @@ -0,0 +1,299 @@ +//----------------------------------------------------------------------------- +// The confidential and proprietary information contained in this file may +// only be used by a person authorised under and to the extent permitted +// by a subsisting licensing agreement from ARM Limited. +// +// (C) COPYRIGHT 2001-2013-2024 ARM Limited. +// ALL RIGHTS RESERVED +// +// This entire notice must be reproduced on all copies of this file +// and copies of this file may only be made by a person if such person is +// permitted to do so under the terms of a subsisting license agreement +// from ARM Limited. +// +// SVN Information +// +// Checked In : $Date: 2012-10-15 18:01:36 +0100 (Mon, 15 Oct 2012) $ +// +// Revision : $Revision: 225465 $ +// +// Release Information : Cortex-M System Design Kit-r1p0-01rel0 +// +//----------------------------------------------------------------------------- +// +//----------------------------------------------------------------------------- +// Abstract : The Output Stage is used to route the required input +// stage to the shared slave output. However, for this +// output port, only one sparse connection is declared +// and muxing is simplified. +// +// Notes : The bus matrix has sparse connectivity and the +// standard output stage has been overridden for this +// instance only. +// +//----------------------------------------------------------------------------- + +`timescale 1ns/1ps + +module nox_intcon_outS3_PERIPH ( + + // Common AHB signals + HCLK, + HRESETn, + + // Port 1 Signals + sel_op1, + addr_op1, + auser_op1, + trans_op1, + write_op1, + size_op1, + burst_op1, + prot_op1, + master_op1, + mastlock_op1, + wdata_op1, + wuser_op1, + held_tran_op1, + + // Slave read data and response + HREADYOUTM, + + active_op1, + + // Slave addr_opess/Control Signals + HSELM, + HADDRM, + HAUSERM, + HTRANSM, + HWRITEM, + HSIZEM, + HBURSTM, + HPROTM, + HMASTERM, + HMASTLOCKM, + HREADYMUXM, + HWUSERM, + HWDATAM + + ); + + +// ----------------------------------------------------------------------------- +// Input and Output declarations +// ----------------------------------------------------------------------------- + + // Common AHB signals + input HCLK; // AHB system clock + input HRESETn; // AHB system reset + + // Bus-switch input 1 + input sel_op1; // Port 1 HSEL signal + input [31:0] addr_op1; // Port 1 HADDR signal + input [31:0] auser_op1; // Port 1 HAUSER signal + input [1:0] trans_op1; // Port 1 HTRANS signal + input write_op1; // Port 1 HWRITE signal + input [2:0] size_op1; // Port 1 HSIZE signal + input [2:0] burst_op1; // Port 1 HBURST signal + input [3:0] prot_op1; // Port 1 HPROT signal + input [3:0] master_op1; // Port 1 HMASTER signal + input mastlock_op1; // Port 1 HMASTLOCK signal + input [31:0] wdata_op1; // Port 1 HWDATA signal + input [31:0] wuser_op1; // Port 1 HWUSER signal + input held_tran_op1; // Port 1 held_tran_op signal + + input HREADYOUTM; // HREADY feedback + + output active_op1; // Port 1 active_op signal + + // Slave addr_opess/Control Signals + output HSELM; // Slave select line + output [31:0] HADDRM; // addr_opess + output [31:0] HAUSERM; // User addr_opess bus + output [1:0] HTRANSM; // trans_opfer type + output HWRITEM; // trans_opfer direction + output [2:0] HSIZEM; // trans_opfer size + output [2:0] HBURSTM; // burst_op type + output [3:0] HPROTM; // prot_opection control + output [3:0] HMASTERM; // master_op ID + output HMASTLOCKM; // Locked transfer + output HREADYMUXM; // trans_opfer done + output [31:0] HWUSERM; // User data bus + output [31:0] HWDATAM; // write_op data + + +// ----------------------------------------------------------------------------- +// Wire declarations +// ----------------------------------------------------------------------------- + wire HCLK; // AHB system clock + wire HRESETn; // AHB system reset + + // Bus-switch input 1 + wire sel_op1; // Port 1 HSEL signal + wire [31:0] addr_op1; // Port 1 HADDR signal + wire [31:0] auser_op1; // Port 1 HAUSER signal + wire [1:0] trans_op1; // Port 1 HTRANS signal + wire write_op1; // Port 1 HWRITE signal + wire [2:0] size_op1; // Port 1 HSIZE signal + wire [2:0] burst_op1; // Port 1 HBURST signal + wire [3:0] prot_op1; // Port 1 HPROT signal + wire [3:0] master_op1; // Port 1 HMASTER signal + wire mastlock_op1; // Port 1 HMASTLOCK signal + wire [31:0] wdata_op1; // Port 1 HWDATA signal + wire [31:0] wuser_op1; // Port 1 HWUSER signal + wire held_tran_op1; // Port 1 held_tran_op signal + wire active_op1; // Port 1 active_op signal + + // Slave addr_opess/Control Signals + wire HSELM; // Slave select line + wire [31:0] HADDRM; // addr_opess + wire [31:0] HAUSERM; // User addr_opess bus + wire [1:0] HTRANSM; // trans_opfer type + wire HWRITEM; // trans_opfer direction + wire [2:0] HSIZEM; // trans_opfer size + wire [2:0] HBURSTM; // burst_op type + wire [3:0] HPROTM; // prot_opection control + wire [3:0] HMASTERM; // master_op ID + wire HMASTLOCKM; // Locked transfer + wire HREADYMUXM; // trans_opfer done + wire [31:0] HWUSERM; // User data bus + wire [31:0] HWDATAM; // write_op data + wire HREADYOUTM; // HREADY feedback + + +// ----------------------------------------------------------------------------- +// Signal declarations +// ----------------------------------------------------------------------------- + wire req_port1; // Port 1 request signal + + wire [1:0] addr_in_port; // addr_opess input port + reg [1:0] data_in_port; // Data input port + wire no_port; // No port selected signal + reg slave_sel; // Slave select signal + + reg hsel_lock; // Held HSELS during locked sequence + wire next_hsel_lock; // Pre-registered hsel_lock + wire hlock_arb; // HMASTLOCK modified by HSEL for arbitration + + wire i_hselm; // Internal HSELM + wire [1:0] i_htransm; // Internal HTRANSM + wire [2:0] i_hburstm; // Internal HBURSTM + wire i_hreadymuxm; // Internal HREADYMUXM + wire i_hmastlockm; // Internal HMASTLOCKM + + +// ----------------------------------------------------------------------------- +// Beginning of main code +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +// Port sel_opection +// ----------------------------------------------------------------------------- + + assign req_port1 = held_tran_op1 & sel_op1; + + // Dummy arbiter instance for granting requests to this output stage + nox_intcon_arbS3_PERIPH u_output_arb ( + + .HCLK (HCLK), + .HRESETn (HRESETn), + + .req_port1 (req_port1), + + .HREADYM (i_hreadymuxm), + .HSELM (i_hselm), + .HTRANSM (i_htransm), + .HBURSTM (i_hburstm), + .HMASTLOCKM (hlock_arb), + + .addr_in_port (addr_in_port), + .no_port (no_port) + + ); + + + // active_op signal combinatorial decode + assign active_op1 = (addr_in_port == 2'b01) & !no_port; + + // addr_opess/control output decode + assign i_hselm = (addr_in_port == 2'b01) & sel_op1 & !no_port; + assign HADDRM = ( (addr_in_port == 2'b01) & !no_port ) ? addr_op1 : {32{1'b0}}; + assign HAUSERM = ( (addr_in_port == 2'b01) & !no_port ) ? auser_op1 : {32{1'b0}}; + assign i_htransm = ( (addr_in_port == 2'b01) & !no_port ) ? trans_op1 : 2'b00; + assign HWRITEM = (addr_in_port == 2'b01) & write_op1 & !no_port; + assign HSIZEM = ( (addr_in_port == 2'b01) & !no_port ) ? size_op1 : 3'b000; + assign i_hburstm = ( (addr_in_port == 2'b01) & !no_port ) ? burst_op1 : 3'b000; + assign HPROTM = ( (addr_in_port == 2'b01) & !no_port ) ? prot_op1 : {4{1'b0}}; + assign HMASTERM = ( (addr_in_port == 2'b01) & !no_port ) ? master_op1 : 4'b0000; + assign i_hmastlockm = (addr_in_port == 2'b01) & mastlock_op1 & !no_port; + + // hsel_lock provides support for AHB masters that address other + // slave regions in the middle of a locked sequence (i.e. HSEL is + // de-asserted during the locked sequence). Unless HMASTLOCK is + // held during these intermediate cycles, the OutputArb scheme will + // lose track of the locked sequence and may allow another input + // port to access the output port which should be locked + assign next_hsel_lock = (i_hselm & i_htransm[1] & i_hmastlockm) ? 1'b1 : + (i_hmastlockm == 1'b0) ? 1'b0 : + hsel_lock; + + // Register hsel_lock + always @ (negedge HRESETn or posedge HCLK) + begin : p_hsel_lock + if (!HRESETn) + hsel_lock <= 1'b0; + else + if (i_hreadymuxm) + hsel_lock <= next_hsel_lock; + end + + // Version of HMASTLOCK which is masked when not selected, unless a + // locked sequence has already begun through this port + assign hlock_arb = i_hmastlockm & (hsel_lock | i_hselm); + + assign HTRANSM = i_htransm; + assign HBURSTM = i_hburstm; + assign HSELM = i_hselm; + assign HMASTLOCKM = i_hmastlockm; + + // Dataport register + always @ (negedge HRESETn or posedge HCLK) + begin : p_data_in_port_reg + if (!HRESETn) + data_in_port <= {2{1'b0}}; + else + if (i_hreadymuxm) + data_in_port <= addr_in_port; + end + + // HWDATAM output decode + assign HWDATAM = ( data_in_port == 2'b01 ) ? wdata_op1 : {32{1'b0}}; + + // HWUSERM output decode + assign HWUSERM = ( data_in_port == 2'b01 ) ? wuser_op1 : {32{1'b0}}; + + // --------------------------------------------------------------------------- + // HREADYMUXM generation + // --------------------------------------------------------------------------- + // The HREADY signal on the shared slave is generated directly from + // the shared slave HREADYOUTS if the slave is selected, otherwise + // it mirrors the HREADY signal of the appropriate input port + always @ (negedge HRESETn or posedge HCLK) + begin : p_slave_sel_reg + if (!HRESETn) + slave_sel <= 1'b0; + else + if (i_hreadymuxm) + slave_sel <= i_hselm; + end + + // HREADYMUXM output selection + assign i_hreadymuxm = (slave_sel) ? HREADYOUTM : 1'b1; + + // Drive output with internal version of the signal + assign HREADYMUXM = i_hreadymuxm; + + +endmodule + +// --================================= End ===================================-- diff --git a/xlnx/rtl/ahb_interconnect/nox_intcon_wrapper.sv b/xlnx/rtl/ahb_interconnect/nox_intcon_wrapper.sv new file mode 100644 index 0000000..fcd2488 --- /dev/null +++ b/xlnx/rtl/ahb_interconnect/nox_intcon_wrapper.sv @@ -0,0 +1,190 @@ +/** + * File : nox_intcon_wrapper.sv + * Author : aignacio + * Date : 2024-05-15 21:12:25.103943 + * Description : AHB Interconnect wrapper - nox_intcon + * ------------------------------------------------- + * -- Design AUTO-GENERATED using AHB wrapper gen -- + * ------------------------------------------------- + + M0_CPU_FETCH: + - S0_ROM: from 0x00000000 to 0x0001ffff + - S1_IRAM: from 0x00020000 to 0x0003ffff + + M1_CPU_LSU: + - S0_ROM: from 0x00000000 to 0x0001ffff + - S1_IRAM: from 0x00020000 to 0x0003ffff + - S2_DRAM: from 0x00040000 to 0x0007ffff + - S3_PERIPH: from 0x00080000 to 0xffffffff + + M2_CPU_FRONT_PORT: + - S0_ROM: from 0x00000000 to 0x0001ffff + - S1_IRAM: from 0x00020000 to 0x0003ffff + - S2_DRAM: from 0x00040000 to 0x0007ffff + + **/ +module nox_intcon_wrapper + import amba_ahb_pkg::*; +( + + input clk, + input ares, + + // Slave I/F - From Masters + + input s_ahb_mosi_t m0_cpu_fetch_mosi, + output s_ahb_miso_t m0_cpu_fetch_miso, + + input s_ahb_mosi_t m1_cpu_lsu_mosi, + output s_ahb_miso_t m1_cpu_lsu_miso, + + input s_ahb_mosi_t m2_cpu_front_port_mosi, + output s_ahb_miso_t m2_cpu_front_port_miso, + + + // Master I/F - To Slaves + + output s_ahb_mosi_t s0_rom_mosi, + input s_ahb_miso_t s0_rom_miso, + + output s_ahb_mosi_t s2_dram_mosi, + input s_ahb_miso_t s2_dram_miso, + + output s_ahb_mosi_t s3_periph_mosi, + input s_ahb_miso_t s3_periph_miso, + + output s_ahb_mosi_t s1_iram_mosi, + input s_ahb_miso_t s1_iram_miso + +); + logic ares_n; + + assign ares_n = ~ares; + + nox_intcon_lite u_nox_intcon ( + .HCLK (clk), + .HRESETn (ares_n), + .REMAP ('0), + + // Slave I/F - From Masters + + .HADDRM0_CPU_FETCH(m0_cpu_fetch_mosi.haddr), + .HTRANSM0_CPU_FETCH(m0_cpu_fetch_mosi.htrans), + .HWRITEM0_CPU_FETCH(m0_cpu_fetch_mosi.hwrite), + .HSIZEM0_CPU_FETCH(m0_cpu_fetch_mosi.hsize), + .HBURSTM0_CPU_FETCH(m0_cpu_fetch_mosi.hburst), + .HPROTM0_CPU_FETCH(m0_cpu_fetch_mosi.hprot[3:0]), + .HWDATAM0_CPU_FETCH(m0_cpu_fetch_mosi.hwdata), + .HMASTLOCKM0_CPU_FETCH(m0_cpu_fetch_mosi.hmastlock), + .HAUSERM0_CPU_FETCH('0), + .HWUSERM0_CPU_FETCH('0), + .HRDATAM0_CPU_FETCH(m0_cpu_fetch_miso.hrdata), + .HREADYM0_CPU_FETCH(m0_cpu_fetch_miso.hready), + .HRESPM0_CPU_FETCH(m0_cpu_fetch_miso.hresp), + .HRUSERM0_CPU_FETCH(), + + .HADDRM1_CPU_LSU(m1_cpu_lsu_mosi.haddr), + .HTRANSM1_CPU_LSU(m1_cpu_lsu_mosi.htrans), + .HWRITEM1_CPU_LSU(m1_cpu_lsu_mosi.hwrite), + .HSIZEM1_CPU_LSU(m1_cpu_lsu_mosi.hsize), + .HBURSTM1_CPU_LSU(m1_cpu_lsu_mosi.hburst), + .HPROTM1_CPU_LSU(m1_cpu_lsu_mosi.hprot[3:0]), + .HWDATAM1_CPU_LSU(m1_cpu_lsu_mosi.hwdata), + .HMASTLOCKM1_CPU_LSU(m1_cpu_lsu_mosi.hmastlock), + .HAUSERM1_CPU_LSU('0), + .HWUSERM1_CPU_LSU('0), + .HRDATAM1_CPU_LSU(m1_cpu_lsu_miso.hrdata), + .HREADYM1_CPU_LSU(m1_cpu_lsu_miso.hready), + .HRESPM1_CPU_LSU(m1_cpu_lsu_miso.hresp), + .HRUSERM1_CPU_LSU(), + + .HADDRM2_CPU_FRONT_PORT(m2_cpu_front_port_mosi.haddr), + .HTRANSM2_CPU_FRONT_PORT(m2_cpu_front_port_mosi.htrans), + .HWRITEM2_CPU_FRONT_PORT(m2_cpu_front_port_mosi.hwrite), + .HSIZEM2_CPU_FRONT_PORT(m2_cpu_front_port_mosi.hsize), + .HBURSTM2_CPU_FRONT_PORT(m2_cpu_front_port_mosi.hburst), + .HPROTM2_CPU_FRONT_PORT(m2_cpu_front_port_mosi.hprot[3:0]), + .HWDATAM2_CPU_FRONT_PORT(m2_cpu_front_port_mosi.hwdata), + .HMASTLOCKM2_CPU_FRONT_PORT(m2_cpu_front_port_mosi.hmastlock), + .HAUSERM2_CPU_FRONT_PORT('0), + .HWUSERM2_CPU_FRONT_PORT('0), + .HRDATAM2_CPU_FRONT_PORT(m2_cpu_front_port_miso.hrdata), + .HREADYM2_CPU_FRONT_PORT(m2_cpu_front_port_miso.hready), + .HRESPM2_CPU_FRONT_PORT(m2_cpu_front_port_miso.hresp), + .HRUSERM2_CPU_FRONT_PORT(), + + // Master I/F - To Slaves + + .HSELS0_ROM(s0_rom_mosi.hsel), + .HADDRS0_ROM(s0_rom_mosi.haddr), + .HTRANSS0_ROM(s0_rom_mosi.htrans), + .HWRITES0_ROM(s0_rom_mosi.hwrite), + .HSIZES0_ROM(s0_rom_mosi.hsize), + .HBURSTS0_ROM(s0_rom_mosi.hburst), + .HPROTS0_ROM(s0_rom_mosi.hprot[3:0]), + .HWDATAS0_ROM(s0_rom_mosi.hwdata), + .HMASTLOCKS0_ROM(s0_rom_mosi.hmastlock), + .HREADYMUXS0_ROM(s0_rom_mosi.hready), + .HAUSERS0_ROM(), + .HWUSERS0_ROM(), + .HRDATAS0_ROM(s0_rom_miso.hrdata), + .HREADYOUTS0_ROM(s0_rom_miso.hready), + .HRESPS0_ROM(s0_rom_miso.hresp), + .HRUSERS0_ROM('0), + + .HSELS2_DRAM(s2_dram_mosi.hsel), + .HADDRS2_DRAM(s2_dram_mosi.haddr), + .HTRANSS2_DRAM(s2_dram_mosi.htrans), + .HWRITES2_DRAM(s2_dram_mosi.hwrite), + .HSIZES2_DRAM(s2_dram_mosi.hsize), + .HBURSTS2_DRAM(s2_dram_mosi.hburst), + .HPROTS2_DRAM(s2_dram_mosi.hprot[3:0]), + .HWDATAS2_DRAM(s2_dram_mosi.hwdata), + .HMASTLOCKS2_DRAM(s2_dram_mosi.hmastlock), + .HREADYMUXS2_DRAM(s2_dram_mosi.hready), + .HAUSERS2_DRAM(), + .HWUSERS2_DRAM(), + .HRDATAS2_DRAM(s2_dram_miso.hrdata), + .HREADYOUTS2_DRAM(s2_dram_miso.hready), + .HRESPS2_DRAM(s2_dram_miso.hresp), + .HRUSERS2_DRAM('0), + + .HSELS3_PERIPH(s3_periph_mosi.hsel), + .HADDRS3_PERIPH(s3_periph_mosi.haddr), + .HTRANSS3_PERIPH(s3_periph_mosi.htrans), + .HWRITES3_PERIPH(s3_periph_mosi.hwrite), + .HSIZES3_PERIPH(s3_periph_mosi.hsize), + .HBURSTS3_PERIPH(s3_periph_mosi.hburst), + .HPROTS3_PERIPH(s3_periph_mosi.hprot[3:0]), + .HWDATAS3_PERIPH(s3_periph_mosi.hwdata), + .HMASTLOCKS3_PERIPH(s3_periph_mosi.hmastlock), + .HREADYMUXS3_PERIPH(s3_periph_mosi.hready), + .HAUSERS3_PERIPH(), + .HWUSERS3_PERIPH(), + .HRDATAS3_PERIPH(s3_periph_miso.hrdata), + .HREADYOUTS3_PERIPH(s3_periph_miso.hready), + .HRESPS3_PERIPH(s3_periph_miso.hresp), + .HRUSERS3_PERIPH('0), + + .HSELS1_IRAM(s1_iram_mosi.hsel), + .HADDRS1_IRAM(s1_iram_mosi.haddr), + .HTRANSS1_IRAM(s1_iram_mosi.htrans), + .HWRITES1_IRAM(s1_iram_mosi.hwrite), + .HSIZES1_IRAM(s1_iram_mosi.hsize), + .HBURSTS1_IRAM(s1_iram_mosi.hburst), + .HPROTS1_IRAM(s1_iram_mosi.hprot[3:0]), + .HWDATAS1_IRAM(s1_iram_mosi.hwdata), + .HMASTLOCKS1_IRAM(s1_iram_mosi.hmastlock), + .HREADYMUXS1_IRAM(s1_iram_mosi.hready), + .HAUSERS1_IRAM(), + .HWUSERS1_IRAM(), + .HRDATAS1_IRAM(s1_iram_miso.hrdata), + .HREADYOUTS1_IRAM(s1_iram_miso.hready), + .HRESPS1_IRAM(s1_iram_miso.hresp), + .HRUSERS1_IRAM('0), + + .SCANENABLE('0), + .SCANINHCLK('0), + .SCANOUTHCLK() + ); +endmodule \ No newline at end of file diff --git a/xlnx/rtl/ahb_mem.sv b/xlnx/rtl/ahb_mem.sv new file mode 100644 index 0000000..d43c7a2 --- /dev/null +++ b/xlnx/rtl/ahb_mem.sv @@ -0,0 +1,18 @@ +/** + * File : ahb_mem.sv + * License : MIT license + * Author : Anderson I. da Silva (aignacio) + * Date : 01.04.2024 + * Last Modified Date: 01.04.2024 + */ +module ahb_mem + import amba_ahb_pkg::*; +( + input clk, + input ares, + + input s_ahb_mosi_t mem_mosi_i, + output s_ahb_miso_t mem_miso_o +); + +endmodule diff --git a/xlnx/rtl/cmsdk_ahb_to_sram.v b/xlnx/rtl/cmsdk_ahb_to_sram.v new file mode 100644 index 0000000..75f056d --- /dev/null +++ b/xlnx/rtl/cmsdk_ahb_to_sram.v @@ -0,0 +1,418 @@ +// ---------------------------------------------------------------------------- +// The confidential and proprietary information contained in this file may +// only be used by a person authorised under and to the extent permitted +// by a subsisting licensing agreement from ARM Limited. +// +// (C) COPYRIGHT 2010-2013 ARM Limited. +// ALL RIGHTS RESERVED +// +// This entire notice must be reproduced on all copies of this file +// and copies of this file may only be made by a person if such person is +// permitted to do so under the terms of a subsisting license agreement +// from ARM Limited. +// +// SVN Information +// +// Checked In : $Date: 2012-09-18 17:14:17 +0100 (Tue, 18 Sep 2012) $ +// +// Revision : $Revision: 223062 $ +// +// Release Information : Cortex-M System Design Kit-r1p0-00rel0 +// +// ---------------------------------------------------------------------------- +// Purpose : AHB OnChip RAM interface. Also suitable for FPGA RAM implmentation +// ---------------------------------------------------------------------------- + +module cmsdk_ahb_to_sram #( +// -------------------------------------------------------------------------- +// Parameter Declarations +// -------------------------------------------------------------------------- + parameter AW = 16) // Address width + ( +// -------------------------------------------------------------------------- +// Port Definitions +// -------------------------------------------------------------------------- + input wire HCLK, // system bus clock + input wire HRESETn, // system bus reset + input wire HSEL, // AHB peripheral select + input wire HREADY, // AHB ready input + input wire [1:0] HTRANS, // AHB transfer type + input wire [2:0] HSIZE, // AHB hsize + input wire HWRITE, // AHB hwrite + input wire [AW-1:0] HADDR, // AHB address bus + input wire [31:0] HWDATA, // AHB write data bus + output wire HREADYOUT, // AHB ready output to S->M mux + output wire HRESP, // AHB response + output wire [31:0] HRDATA, // AHB read data bus + + input wire [31:0] SRAMRDATA, // SRAM Read Data + output wire [AW-3:0] SRAMADDR, // SRAM address + output wire [3:0] SRAMWEN, // SRAM write enable (active high) + output wire [31:0] SRAMWDATA, // SRAM write data + output wire SRAMCS); // SRAM Chip Select (active high) + + // ---------------------------------------------------------- + // Internal state + // ---------------------------------------------------------- + reg [(AW-3):0] buf_addr; // Write address buffer + reg [ 3:0] buf_we; // Write enable buffer (data phase) + reg buf_hit; // High when AHB read address + // matches buffered address + reg [31:0] buf_data; // AHB write bus buffered + reg buf_pend; // Buffer write data valid + reg buf_data_en; // Data buffer write enable (data phase) + + // ---------------------------------------------------------- + // Read/write control logic + // ---------------------------------------------------------- + + wire ahb_access = HTRANS[1] & HSEL & HREADY; + wire ahb_write = ahb_access & HWRITE; + wire ahb_read = ahb_access & (~HWRITE); + + // Stored write data in pending state if new transfer is read + // buf_data_en indicate new write (data phase) + // ahb_read indicate new read (address phase) + // buf_pend is registered version of buf_pend_nxt + wire buf_pend_nxt = (buf_pend | buf_data_en) & ahb_read; + + // RAM write happens when + // - write pending (buf_pend), or + // - new AHB write seen (buf_data_en) at data phase, + // - and not reading (address phase) + wire ram_write = (buf_pend | buf_data_en) & (~ahb_read); // ahb_write + + // RAM WE is the buffered WE + assign SRAMWEN = {4{ram_write}} & buf_we[3:0]; + + // RAM address is the buffered address for RAM write otherwise HADDR + assign SRAMADDR = ahb_read ? HADDR[AW-1:2] : buf_addr; + + // RAM chip select during read or write + assign SRAMCS = ahb_read | ram_write; + + // ---------------------------------------------------------- + // Byte lane decoder and next state logic + // ---------------------------------------------------------- + + wire tx_byte = (~HSIZE[1]) & (~HSIZE[0]); + wire tx_half = (~HSIZE[1]) & HSIZE[0]; + wire tx_word = HSIZE[1]; + + wire byte_at_00 = tx_byte & (~HADDR[1]) & (~HADDR[0]); + wire byte_at_01 = tx_byte & (~HADDR[1]) & HADDR[0]; + wire byte_at_10 = tx_byte & HADDR[1] & (~HADDR[0]); + wire byte_at_11 = tx_byte & HADDR[1] & HADDR[0]; + + wire half_at_00 = tx_half & (~HADDR[1]); + wire half_at_10 = tx_half & HADDR[1]; + + wire word_at_00 = tx_word; + + wire byte_sel_0 = word_at_00 | half_at_00 | byte_at_00; + wire byte_sel_1 = word_at_00 | half_at_00 | byte_at_01; + wire byte_sel_2 = word_at_00 | half_at_10 | byte_at_10; + wire byte_sel_3 = word_at_00 | half_at_10 | byte_at_11; + + // Address phase byte lane strobe + wire [3:0] buf_we_nxt = { byte_sel_3 & ahb_write, + byte_sel_2 & ahb_write, + byte_sel_1 & ahb_write, + byte_sel_0 & ahb_write }; + + // ---------------------------------------------------------- + // Write buffer + // ---------------------------------------------------------- + + // buf_data_en is data phase write control + always @(posedge HCLK or negedge HRESETn) + if (~HRESETn) + buf_data_en <= 1'b0; + else + buf_data_en <= ahb_write; + + always @(posedge HCLK) + if(buf_we[3] & buf_data_en) + buf_data[31:24] <= HWDATA[31:24]; + + always @(posedge HCLK) + if(buf_we[2] & buf_data_en) + buf_data[23:16] <= HWDATA[23:16]; + + always @(posedge HCLK) + if(buf_we[1] & buf_data_en) + buf_data[15: 8] <= HWDATA[15: 8]; + + always @(posedge HCLK) + if(buf_we[0] & buf_data_en) + buf_data[ 7: 0] <= HWDATA[ 7: 0]; + + // buf_we keep the valid status of each byte (data phase) + always @(posedge HCLK or negedge HRESETn) + if (~HRESETn) + buf_we <= 4'b0000; + else if(ahb_write) + buf_we <= buf_we_nxt; + + always @(posedge HCLK or negedge HRESETn) + begin + if (~HRESETn) + buf_addr <= {(AW-2){1'b0}}; + else if (ahb_write) + buf_addr <= HADDR[(AW-1):2]; + end + // ---------------------------------------------------------- + // Buf_hit detection logic + // ---------------------------------------------------------- + + wire buf_hit_nxt = (HADDR[AW-1:2] == buf_addr[AW-3:0]); + + // ---------------------------------------------------------- + // Read data merge : This is for the case when there is a AHB + // write followed by AHB read to the same address. In this case + // the data is merged from the buffer as the RAM write to that + // address hasn't happened yet + // ---------------------------------------------------------- + + wire [ 3:0] merge1 = {4{buf_hit}} & buf_we; // data phase, buf_we indicates data is valid + + assign HRDATA = + { merge1[3] ? buf_data[31:24] : SRAMRDATA[31:24], + merge1[2] ? buf_data[23:16] : SRAMRDATA[23:16], + merge1[1] ? buf_data[15: 8] : SRAMRDATA[15: 8], + merge1[0] ? buf_data[ 7: 0] : SRAMRDATA[ 7: 0] }; + + // ---------------------------------------------------------- + // Synchronous state update + // ---------------------------------------------------------- + + always @(posedge HCLK or negedge HRESETn) + if (~HRESETn) + buf_hit <= 1'b0; + else if(ahb_read) + buf_hit <= buf_hit_nxt; + + always @(posedge HCLK or negedge HRESETn) + if (~HRESETn) + buf_pend <= 1'b0; + else + buf_pend <= buf_pend_nxt; + + // if there is an AHB write and valid data in the buffer, RAM write data + // comes from the buffer. otherwise comes from the HWDATA + assign SRAMWDATA = (buf_pend) ? buf_data : HWDATA[31:0]; + + // ---------------------------------------------------------- + // Assign outputs + // ---------------------------------------------------------- + assign HREADYOUT = 1'b1; + assign HRESP = 1'b0; + +`ifdef ARM_AHB_ASSERT_ON + + // ------------------------------------------------------------ + // Assertions + // ------------------------------------------------------------ + // +`include "std_ovl_defines.h" + + reg ovl_ahb_read_reg; // Last cycle has an AHB read in address phase + reg ovl_ahb_write_reg; // Last cycle has an AHB write in address phase + reg ovl_buf_pend_reg; // Value of buf_pend in the last cycle + + always @(posedge HCLK or negedge HRESETn) + begin + if (~HRESETn) + begin + ovl_ahb_read_reg <= 1'b0; + ovl_ahb_write_reg <= 1'b0; + ovl_buf_pend_reg <= 1'b0; + end + else + begin + ovl_ahb_read_reg <= ahb_read; + ovl_ahb_write_reg <= ahb_write; + ovl_buf_pend_reg <= buf_pend; + end + end + + // ----------------------------------------------------------------------------- + // OVLs for read operations + // ----------------------------------------------------------------------------- + + // Check during a read (address phase), SRAMADDR must match + // HADDR unless it is reading a word that is already inside the buffer. + // Note:This interface module still generate a read to the SRAM although + // strictly speaking it is not required. + + assert_never + #(`OVL_ERROR,`OVL_ASSERT, + "SRAMADDR read incorrect") + u_ovl_sramaddr_read_transfer_error + (.clk(HCLK), .reset_n(HRESETn), + .test_expr(HTRANS[1] & HSEL & HREADY & (~HWRITE) & (SRAMADDR != HADDR[(AW-1):2])) + ); + + // Check during a read (address phase), SRAMWEN must be low + assert_never + #(`OVL_ERROR,`OVL_ASSERT, + "SRAMWEN read incorrect") + u_ovl_sramwen_read_transfer_error + (.clk(HCLK), .reset_n(HRESETn), + .test_expr(HTRANS[1] & HSEL & HREADY & (~HWRITE) & (SRAMWEN!=4'b0000)) + ); + + // Check during a read (address phase), SRAMCS must be high + assert_never + #(`OVL_ERROR,`OVL_ASSERT, + "SRAMCS read incorrect") + u_ovl_sramcs_read_transfer_error + (.clk(HCLK), .reset_n(HRESETn), + .test_expr(HTRANS[1] & HSEL & HREADY & (~HWRITE) & (SRAMCS!=1'b1)) + ); + + // ----------------------------------------------------------------------------- + // OVLs for write operations + // ----------------------------------------------------------------------------- + + // Check during a write (data phase), if there is no read in address phase + // SRAMADDR should be same as buffered address + assert_implication + #(`OVL_ERROR,`OVL_ASSERT, + "SRAMADDR write incorrect") + u_ovl_sramaddr_wr_transfer_error + (.clk(HCLK), .reset_n(HRESETn), + .antecedent_expr(ovl_ahb_write_reg & // write data phase + (ahb_read==1'b0)), // no read + .consequent_expr(SRAMADDR==buf_addr) + ); + + // Check during a write (data phase), if there is no read in address phase + // SRAMCS should be high + assert_implication + #(`OVL_ERROR,`OVL_ASSERT, + "SRAMCS write incorrect") + u_ovl_sramcs_wr_transfer_error + (.clk(HCLK), .reset_n(HRESETn), + .antecedent_expr(ovl_ahb_write_reg & // write data phase + (ahb_read==1'b0)), // no read + .consequent_expr(SRAMCS) + ); + + // Check during a write (data phase), if there is no read in address phase + // SRAMWEN should be active + assert_implication + #(`OVL_ERROR,`OVL_ASSERT, + "SRAMWEN write incorrect") + u_ovl_sramwen_wr_transfer_error + (.clk(HCLK), .reset_n(HRESETn), + .antecedent_expr(ovl_ahb_write_reg & // write data phase + (ahb_read==1'b0)), // no read + .consequent_expr(SRAMWEN==buf_we) + ); + + // Check during a write (data phase), if there is no read in address phase + // SRAMWDATA should be same as HWDATA + assert_implication + #(`OVL_ERROR,`OVL_ASSERT, + "SRAMWDATA write incorrect") + u_ovl_sramwdata_wr_transfer_error + (.clk(HCLK), .reset_n(HRESETn), + .antecedent_expr(ovl_ahb_write_reg & // write data phase + (ahb_read==1'b0)), // no read + .consequent_expr(buf_pend == 1'b0) // Instead of checking SRAMWDATA and HWDATA + ); // which can be X, check buf_pend instead. Otherwise OVL_ERROR will be + // generated when write data is unknown. + + // ----------------------------------------------------------------------------- + // OVLs for buffered write operations + // ----------------------------------------------------------------------------- + + // Check during a write (address phase) or idle, if there is a buffered write + // SRAMADDR should be same as buffered address + assert_implication + #(`OVL_ERROR,`OVL_ASSERT, + "SRAMADDR buffer write incorrect") + u_ovl_sramaddr_bufwr_transfer_error + (.clk(HCLK), .reset_n(HRESETn), + .antecedent_expr(((~(HTRANS[1] & HSEL & HREADY))|(HWRITE)) & // Idle or write + (buf_pend==1'b1)), // buffered write pending + .consequent_expr(SRAMADDR==buf_addr) + ); + + // Check during a write (address phase) or idle, if there is a buffered write + // SRAMWDATA should be same as buffered write data + assert_implication + #(`OVL_ERROR,`OVL_ASSERT, + "SRAMWDATA buffer write incorrect") + u_ovl_sramwdata_bufwr_transfer_error + (.clk(HCLK), .reset_n(HRESETn), + .antecedent_expr(((~(HTRANS[1] & HSEL & HREADY))|(HWRITE)) & // Idle or write + (buf_pend==1'b1)), // buffered write pending + .consequent_expr(SRAMWDATA==buf_data) + ); + + // Check during a write (address phase) or idle, if there is a buffered write + // SRAMCS should be high + assert_implication + #(`OVL_ERROR,`OVL_ASSERT, + "SRAMWDATA buffer write incorrect") + u_ovl_sramcs_bufwr_transfer_error + (.clk(HCLK), .reset_n(HRESETn), + .antecedent_expr(((~(HTRANS[1] & HSEL & HREADY))|(HWRITE)) & // Idle or write + (buf_pend==1'b1)), // buffered write pending + .consequent_expr(SRAMCS) + ); + + // Check during a write (address phase) or idle, if there is a buffered write + // SRAMWEN should be high + assert_implication + #(`OVL_ERROR,`OVL_ASSERT, + "SRAMWEN buffer write incorrect") + u_ovl_sramwen_bufwr_transfer_error + (.clk(HCLK), .reset_n(HRESETn), + .antecedent_expr(((~(HTRANS[1] & HSEL & HREADY))|(HWRITE)) & // Idle or write + (buf_pend==1'b1)), // buffered write pending + .consequent_expr(SRAMWEN==buf_we) + ); + + // ----------------------------------------------------------------------------- + // OVLs for write buffer status + // ----------------------------------------------------------------------------- + + // Check if last cycle is an AHB write (address phase) and this cycle + // we have an AHB read, then buf_pend_nxt should be high + assert_implication + #(`OVL_ERROR,`OVL_ASSERT, + "buf_pend not staying high at read") + u_ovl_buf_pend_nxt_set_error + (.clk(HCLK), .reset_n(HRESETn), + .antecedent_expr(ovl_ahb_write_reg & ahb_read), + .consequent_expr(buf_pend_nxt) + ); + + // Check if last cycle is an AHB read and last buf_pend was high, then + // buf_pend should still be high this cycle + assert_implication + #(`OVL_ERROR,`OVL_ASSERT, + "buf_pend not staying high at read") + u_ovl_buf_pend_stay_error + (.clk(HCLK), .reset_n(HRESETn), + .antecedent_expr(ovl_ahb_read_reg & ovl_buf_pend_reg), + .consequent_expr(buf_pend) + ); + + // Check if last cycle is an AHB write (address phase) or idle, then + // buf_pend should be low this cycle + assert_implication + #(`OVL_ERROR,`OVL_ASSERT, + "buf_pend not clear") + u_ovl_buf_pend_clear_error + (.clk(HCLK), .reset_n(HRESETn), + .antecedent_expr(ovl_ahb_write_reg | (~ovl_ahb_read_reg)), + .consequent_expr(~buf_pend) + ); + +`endif + +endmodule diff --git a/xlnx/rtl/cmsdk_fpga_sram.v b/xlnx/rtl/cmsdk_fpga_sram.v new file mode 100644 index 0000000..d066bb2 --- /dev/null +++ b/xlnx/rtl/cmsdk_fpga_sram.v @@ -0,0 +1,90 @@ +//----------------------------------------------------------------------------- +// The confidential and proprietary information contained in this file may +// only be used by a person authorised under and to the extent permitted +// by a subsisting licensing agreement from ARM Limited. +// +// (C) COPYRIGHT 2010-2013 ARM Limited. +// ALL RIGHTS RESERVED +// +// This entire notice must be reproduced on all copies of this file +// and copies of this file may only be made by a person if such person is +// permitted to do so under the terms of a subsisting license agreement +// from ARM Limited. +// +// SVN Information +// +// Checked In : $Date: 2013-04-10 15:27:13 +0100 (Wed, 10 Apr 2013) $ +// +// Revision : $Revision: 243506 $ +// +// Release Information : Cortex-M System Design Kit-r1p0-00rel0 +// +// ---------------------------------------------------------------------------- +// Abstract : FPGA BlockRam/OnChip SRAM +// ---------------------------------------------------------------------------- +// The read operation is pipelined. Write operation is not pipelined. +//`include "fpga_options_defs.v" +module cmsdk_fpga_sram #( +// -------------------------------------------------------------------------- +// Parameters +// -------------------------------------------------------------------------- + parameter AW = 16, + parameter MEMFILE = "image.hex" + ) + ( + // Inputs + input wire CLK, + input wire [AW-1:0] ADDR, + input wire [31:0] WDATA, + input wire [3:0] WREN, + input wire CS, + + // Outputs + output wire [31:0] RDATA + ); + +// ----------------------------------------------------------------------------- +// Constant Declarations +// ----------------------------------------------------------------------------- +localparam AWT = ((1<<(AW-0))-1); + + // Memory Array + reg [7:0] BRAM0 [AWT:0]; + reg [7:0] BRAM1 [AWT:0]; + reg [7:0] BRAM2 [AWT:0]; + reg [7:0] BRAM3 [AWT:0]; + + // Internal signals + reg [AW-1:0] addr_q1; + wire [3:0] write_enable; + reg cs_reg; + wire [31:0] read_data; + + assign write_enable[3:0] = WREN[3:0] & {4{CS}}; + + always @ (posedge CLK) + begin + cs_reg <= CS; + end + + // Infer Block RAM - syntax is very specific. + always @ (posedge CLK) + begin + if (write_enable[0]) + BRAM0[ADDR] <= WDATA[7:0]; + if (write_enable[1]) + BRAM1[ADDR] <= WDATA[15:8]; + if (write_enable[2]) + BRAM2[ADDR] <= WDATA[23:16]; + if (write_enable[3]) + BRAM3[ADDR] <= WDATA[31:24]; + // do not use enable on read interface. + addr_q1 <= ADDR[AW-1:0]; + end + + assign read_data = {BRAM3[addr_q1],BRAM2[addr_q1],BRAM1[addr_q1],BRAM0[addr_q1]}; + + + assign RDATA = (cs_reg) ? read_data : {32{1'b0}}; + +endmodule diff --git a/xlnx/rtl/nox_ahb_ram.sv b/xlnx/rtl/nox_ahb_ram.sv new file mode 100644 index 0000000..65ebbf5 --- /dev/null +++ b/xlnx/rtl/nox_ahb_ram.sv @@ -0,0 +1,60 @@ +module nox_ahb_ram + import amba_ahb_pkg::*; +#( + parameter int MEM_KIB = 8 +)( + input clk, + input rstn, + input s_ahb_mosi_t mosi_i, + output s_ahb_miso_t miso_o +); + localparam AW = $clog2(MEM_KIB*1024); + + logic [31:0] SRAMRDATA; + logic [(AW-3):0] SRAMADDR; + logic [3:0] SRAMWEN; + logic [31:0] SRAMWDATA; + logic SRAMCS; + + cmsdk_ahb_to_sram #( + // -------------------------------------------------------------------------- + // Parameter Declarations + // -------------------------------------------------------------------------- + .AW (AW) + ) u_ahb_to_sram ( + // -------------------------------------------------------------------------- + // Port Definitions + // -------------------------------------------------------------------------- + .HCLK (clk), // system bus clock + .HRESETn (rstn), // system bus reset + .HSEL (mosi_i.hsel), // AHB peripheral select + .HREADY (mosi_i.hready), // AHB ready input + .HTRANS (mosi_i.htrans), // AHB transfer type + .HSIZE (mosi_i.hsize), // AHB hsize + .HWRITE (mosi_i.hwrite), // AHB hwrite + .HADDR (mosi_i.haddr[(AW-1):0]), // AHB address bus + .HWDATA (mosi_i.hwdata), // AHB write data bus + .HREADYOUT (miso_o.hready), // AHB ready output to S->M mux + .HRESP (miso_o.hresp), // AHB response + .HRDATA (miso_o.hrdata), // AHB read data bus + // AHB SRAM I/F + .SRAMRDATA (SRAMRDATA), // SRAM Read Data + .SRAMADDR (SRAMADDR), // SRAM address + .SRAMWEN (SRAMWEN), // SRAM write enable (active high) + .SRAMWDATA (SRAMWDATA), // SRAM write data + .SRAMCS (SRAMCS) + ); + + cmsdk_fpga_sram #( + .AW (AW-2) + ) u_sram ( + // Inputs + .CLK (clk), + .ADDR (SRAMADDR), + .WDATA (SRAMWDATA), + .WREN (SRAMWEN), + .CS (SRAMCS), + // Outputs + .RDATA (SRAMRDATA) + ); +endmodule diff --git a/xlnx/rtl/nox_soc_ahb.sv b/xlnx/rtl/nox_soc_ahb.sv new file mode 100644 index 0000000..9854124 --- /dev/null +++ b/xlnx/rtl/nox_soc_ahb.sv @@ -0,0 +1,190 @@ +/** + * File : nox_soc_ahb.sv + * License : MIT license + * Author : Anderson Ignacio da Silva (aignacio) + * Date : 12.03.2022 + * Last Modified Date: 29.04.2024 + */ + +`default_nettype wire + +module nox_soc + import amba_axi_pkg::*; + import amba_ahb_pkg::*; + import nox_utils_pkg::*; +( + input clk_in, + input rst_cpu, + input rst_clk, + input bootloader_i, + output logic [7:0] csr_out, + output logic clk_locked_o, + output logic uart_tx_o, + output logic uart_tx_mirror_o, + output logic uart_irq_o, + input uart_rx_i, + output spi_clk_o, + output spi_mosi_o, + input spi_miso_i, + output spi_csn_o, + output logic [9:0] spi_gpio_o +); + logic clk; + logic rst; + logic bootloader_int; + logic start_fetch; + logic [31:0] core_rst; + logic mtimer_irq; + logic uart_rx_irq; + + assign clk = clk_in; + assign rst = rst_cpu; + assign start_fetch = '1; + assign csr_out = '0; + assign uart_tx_o = '0; + assign uart_tx_mirror_o = '0; + assign uart_irq_o = '0; + + s_ahb_mosi_t [1:0] masters_ahb_mosi; + s_ahb_miso_t [1:0] masters_ahb_miso; + s_ahb_mosi_t [1:0] slaves_ahb_mosi; + s_ahb_miso_t [1:0] slaves_ahb_miso; + + s_axi_mosi_t masters_axi_mosi; + s_axi_miso_t masters_axi_miso; + s_axi_mosi_t [2:0] slaves_axi_mosi; + s_axi_miso_t [2:0] slaves_axi_miso; + + nox_wrapper u_nox_wrapper ( + .clk (clk), + .rst (rst), + .irq_i ({mtimer_irq,1'b0,uart_rx_irq}), + .start_fetch_i (start_fetch), + .start_addr_i (core_rst), + .instr_ahb_mosi_o (masters_ahb_mosi[0]), + .instr_ahb_miso_i (masters_ahb_miso[0]), + .lsu_ahb_mosi_o (masters_ahb_mosi[1]), + .lsu_ahb_miso_i (masters_ahb_miso[1]) + ); + + nox_intcon_wrapper u_nox_intcon_wrapper ( + .clk (clk), + .ares (~rst), + + // Slave I/F - From Masters + .m2_cpu_front_port_mosi ('0), + .m2_cpu_front_port_miso (), + + .m1_cpu_lsu_mosi (masters_ahb_mosi[1]), + .m1_cpu_lsu_miso (masters_ahb_miso[1]), + + .m0_cpu_fetch_mosi (masters_ahb_mosi[0]), + .m0_cpu_fetch_miso (masters_ahb_miso[0]), + + // Master I/F - To Slaves + .s3_periph_mosi (), + .s3_periph_miso ('0), + + .s2_dram_mosi (slaves_ahb_mosi[1]), + .s2_dram_miso (slaves_ahb_miso[1]), + + .s1_iram_mosi (), + .s1_iram_miso ('0), + + .s0_rom_mosi (slaves_ahb_mosi[0]), + .s0_rom_miso (slaves_ahb_miso[0]) + ); + + nox_ahb_ram #( + .MEM_KIB (8) + ) u_dram ( + .clk (clk), + .rstn (rst), + .mosi_i (slaves_ahb_mosi[1]), + .miso_o (slaves_ahb_miso[1]) + ); + + nox_ahb_ram #( + .MEM_KIB (13) + ) u_iram ( + .clk (clk), + .rstn (rst), + .mosi_i (slaves_ahb_mosi[0]), + .miso_o (slaves_ahb_miso[0]) + ); + + axi_crossbar_wrapper #( + .N_MASTERS (1), + .N_SLAVES (3), + .AXI_TID_WIDTH (8), + .M_BASE_ADDR ({32'hC000_0000, // MTIMER + 32'hB000_0000, // RST Ctrl + 32'hA000_0000}), // UART + .M_ADDR_WIDTH ({32'd17, + 32'd17, + 32'd17}) + ) u_axi_crossbar ( + .clk (clk), + .arst (rst), + .* + ); + + axi_uart_wrapper u_axi_uart ( + .clk (clk), + .rst (rst), + .axi_mosi (slaves_axi_mosi[0]), + .axi_miso (slaves_axi_miso[0]), + .uart_tx_o (uart_tx_o), + .uart_rx_i (uart_rx_i), + .uart_rx_irq_o (uart_rx_irq) + ); + + rst_ctrl u_rst_ctrl( + .clk (clk), + .rst (bootloader_int), + .axi_mosi (slaves_axi_mosi[1]), + .axi_miso (slaves_axi_miso[1]), + .rst_addr_o (core_rst) + ); + + axi_mtimer u_axi_mtimer ( + .clk (clk), + .rst (rst), + .axi_mosi (slaves_axi_mosi[2]), + .axi_miso (slaves_axi_miso[2]), + .mtimer_irq_o (mtimer_irq) + ); + + //// synthesis translate_off + function automatic void writeWordIRAM(addr_val, word_val); + /*verilator public*/ + logic [31:0] addr_val; + logic [31:0] word_val; + //u_imem.u_ram.mem[addr_val] = word_val; + //u_imem.mem_loading[addr_val] = word_val; + u_iram.u_sram.BRAM0[addr_val] = word_val[7:0]; + u_iram.u_sram.BRAM1[addr_val] = word_val[15:8]; + u_iram.u_sram.BRAM2[addr_val] = word_val[23:16]; + u_iram.u_sram.BRAM3[addr_val] = word_val[31:24]; + $display("Address = [%h] / Value = [%h]", addr_val, word_val); + endfunction + + function automatic void writeWordDRAM(addr_val, word_val); + /*verilator public*/ + logic [31:0] addr_val; + logic [31:0] word_val; + //u_dram.mem_loading[addr_val] = word_val; + u_dram.u_sram.BRAM0[addr_val] = word_val[7:0]; + u_dram.u_sram.BRAM1[addr_val] = word_val[15:8]; + u_dram.u_sram.BRAM2[addr_val] = word_val[23:16]; + u_dram.u_sram.BRAM3[addr_val] = word_val[31:24]; + $display("Address = [%h] / Value = [%h]", addr_val, word_val); + endfunction + + function automatic void writeRstAddr(rst_addr); + /*verilator public*/ + logic [31:0] rst_addr; + u_rst_ctrl.rst_loading = rst_addr; + endfunction + // synthesis translate_on +endmodule diff --git a/xlnx/rtl/nox_wrapper.sv b/xlnx/rtl/nox_wrapper.sv index a9db235..e29bd7b 100644 --- a/xlnx/rtl/nox_wrapper.sv +++ b/xlnx/rtl/nox_wrapper.sv @@ -3,7 +3,7 @@ * License : MIT license * Author : Anderson Ignacio da Silva (aignacio) * Date : 12.03.2022 - * Last Modified Date: 17.03.2022 + * Last Modified Date: 16.04.2024 */ module nox_wrapper import amba_axi_pkg::*; @@ -15,10 +15,10 @@ module nox_wrapper input [2:0] irq_i, input start_fetch_i, input [31:0] start_addr_i, - output s_axi_mosi_t instr_axi_mosi_o, - input s_axi_miso_t instr_axi_miso_i, - output s_axi_mosi_t lsu_axi_mosi_o, - input s_axi_miso_t lsu_axi_miso_i + output s_ahb_mosi_t instr_ahb_mosi_o, + input s_ahb_miso_t instr_ahb_miso_i, + output s_ahb_mosi_t lsu_ahb_mosi_o, + input s_ahb_miso_t lsu_ahb_miso_i ); s_irq_t irq_core; logic [2:0] irq_sync; @@ -47,9 +47,9 @@ module nox_wrapper .irq_i (irq_core), .start_fetch_i (start_fetch_i), .start_addr_i (start_addr_i), - .instr_axi_mosi_o (instr_axi_mosi_o), - .instr_axi_miso_i (instr_axi_miso_i), - .lsu_axi_mosi_o (lsu_axi_mosi_o), - .lsu_axi_miso_i (lsu_axi_miso_i) + .instr_ahb_mosi_o (instr_ahb_mosi_o), + .instr_ahb_miso_i (instr_ahb_miso_i), + .lsu_ahb_mosi_o (lsu_ahb_mosi_o), + .lsu_ahb_miso_i (lsu_ahb_miso_i) ); endmodule