diff --git a/src/runtime_src/xdp/profile/database/static_info/filetypes/aie_control_config_filetype.cpp b/src/runtime_src/xdp/profile/database/static_info/filetypes/aie_control_config_filetype.cpp index ec9913b0d9a..3331a759e9a 100644 --- a/src/runtime_src/xdp/profile/database/static_info/filetypes/aie_control_config_filetype.cpp +++ b/src/runtime_src/xdp/profile/database/static_info/filetypes/aie_control_config_filetype.cpp @@ -242,12 +242,12 @@ AIEControlConfigFiletype::getInterfaceTiles(const std::string& graphName, // Make sure it's desired polarity // NOTE: input = slave (data flowing from PLIO) // output = master (data flowing to PLIO) - if ((metricStr != "ports") - && ((isMaster && (metricStr.find("input") != std::string::npos - || metricStr.find("mm2s") != std::string::npos)) - || (!isMaster && (metricStr.find("output") != std::string::npos - || metricStr.find("s2mm") != std::string::npos)))) + if ((isMaster && (metricStr.find("output") == std::string::npos) + && (metricStr.find("s2mm") == std::string::npos)) + || (!isMaster && (metricStr.find("input") == std::string::npos) + && (metricStr.find("mm2s") == std::string::npos))) continue; + // Make sure column is within specified range (if specified) if (useColumn && !((minCol <= shimCol) && (shimCol <= maxCol))) continue; diff --git a/src/runtime_src/xdp/profile/plugin/aie_trace/aie_trace_metadata.h b/src/runtime_src/xdp/profile/plugin/aie_trace/aie_trace_metadata.h index 3f2ce3fc667..ad4f8307ba6 100644 --- a/src/runtime_src/xdp/profile/plugin/aie_trace/aie_trace_metadata.h +++ b/src/runtime_src/xdp/profile/plugin/aie_trace/aie_trace_metadata.h @@ -157,7 +157,9 @@ class AieTraceMetadata { "input_ports_details", "output_ports_details", "mm2s_ports", "s2mm_ports", "mm2s_ports_stalls", "s2mm_ports_stalls", - "mms2_ports_details", "s2mm_ports_details"} } + "mms2_ports_details", "s2mm_ports_details", + "input_output_ports", "mm2s_s2mm_ports", + "input_output_ports_stalls", "mm2s_s2mm_ports_stalls"} } }; void* handle; diff --git a/src/runtime_src/xdp/profile/plugin/aie_trace/client/aie_trace.cpp b/src/runtime_src/xdp/profile/plugin/aie_trace/client/aie_trace.cpp index 6d329af39e8..53d7735b538 100644 --- a/src/runtime_src/xdp/profile/plugin/aie_trace/client/aie_trace.cpp +++ b/src/runtime_src/xdp/profile/plugin/aie_trace/client/aie_trace.cpp @@ -91,7 +91,8 @@ namespace xdp { XAIE_EVENT_PORT_RUNNING_0_CORE, XAIE_EVENT_PORT_RUNNING_1_CORE}}, {"s2mm_channels", {XAIE_EVENT_INSTR_CALL_CORE, XAIE_EVENT_INSTR_RETURN_CORE, - XAIE_EVENT_PORT_RUNNING_0_CORE, XAIE_EVENT_PORT_RUNNING_1_CORE}}, + XAIE_EVENT_PORT_RUNNING_0_CORE, XAIE_EVENT_PORT_STALLED_0_CORE, + XAIE_EVENT_PORT_RUNNING_1_CORE, XAIE_EVENT_PORT_STALLED_1_CORE}}, {"s2mm_channels_stalls", {XAIE_EVENT_DMA_S2MM_0_START_TASK_MEM, XAIE_EVENT_DMA_S2MM_0_FINISHED_BD_MEM, XAIE_EVENT_DMA_S2MM_0_FINISHED_TASK_MEM, XAIE_EVENT_DMA_S2MM_0_STALLED_LOCK_MEM, @@ -156,27 +157,37 @@ namespace xdp { {"output_ports", {XAIE_EVENT_PORT_RUNNING_0_PL, XAIE_EVENT_PORT_RUNNING_1_PL, XAIE_EVENT_PORT_RUNNING_2_PL, XAIE_EVENT_PORT_RUNNING_3_PL}}, + {"input_output_ports", + {XAIE_EVENT_PORT_RUNNING_0_PL, XAIE_EVENT_PORT_RUNNING_1_PL, + XAIE_EVENT_PORT_RUNNING_2_PL, XAIE_EVENT_PORT_RUNNING_3_PL}}, {"input_ports_stalls", {XAIE_EVENT_PORT_RUNNING_0_PL, XAIE_EVENT_PORT_STALLED_0_PL, XAIE_EVENT_PORT_RUNNING_1_PL, XAIE_EVENT_PORT_STALLED_1_PL}}, {"output_ports_stalls", - {XAIE_EVENT_PORT_RUNNING_0_PL, XAIE_EVENT_PORT_STALLED_0_PL, - XAIE_EVENT_PORT_RUNNING_1_PL, XAIE_EVENT_PORT_STALLED_1_PL}}, + {XAIE_EVENT_PORT_RUNNING_0_PL, XAIE_EVENT_PORT_STALLED_0_PL, + XAIE_EVENT_PORT_RUNNING_1_PL, XAIE_EVENT_PORT_STALLED_1_PL}}, + {"input_output_ports_stalls", + {XAIE_EVENT_PORT_RUNNING_0_PL, XAIE_EVENT_PORT_STALLED_0_PL, + XAIE_EVENT_PORT_RUNNING_1_PL, XAIE_EVENT_PORT_STALLED_1_PL, + XAIE_EVENT_PORT_RUNNING_2_PL, XAIE_EVENT_PORT_STALLED_2_PL, + XAIE_EVENT_PORT_RUNNING_3_PL, XAIE_EVENT_PORT_STALLED_3_PL}}, {"input_ports_details", - {XAIE_EVENT_DMA_MM2S_0_START_TASK_PL, XAIE_EVENT_DMA_MM2S_0_FINISHED_BD_PL, - XAIE_EVENT_DMA_MM2S_0_FINISHED_TASK_PL, XAIE_EVENT_DMA_MM2S_0_STALLED_LOCK_PL, - XAIE_EVENT_DMA_MM2S_0_STREAM_BACKPRESSURE_PL, XAIE_EVENT_DMA_MM2S_0_MEMORY_STARVATION_PL}}, + {XAIE_EVENT_DMA_MM2S_0_START_TASK_PL, XAIE_EVENT_DMA_MM2S_0_FINISHED_BD_PL, + XAIE_EVENT_DMA_MM2S_0_FINISHED_TASK_PL, XAIE_EVENT_DMA_MM2S_0_STALLED_LOCK_PL, + XAIE_EVENT_DMA_MM2S_0_STREAM_BACKPRESSURE_PL, XAIE_EVENT_DMA_MM2S_0_MEMORY_STARVATION_PL}}, {"output_ports_details", - {XAIE_EVENT_DMA_S2MM_0_START_TASK_PL, XAIE_EVENT_DMA_S2MM_0_FINISHED_BD_PL, - XAIE_EVENT_DMA_S2MM_0_FINISHED_TASK_PL, XAIE_EVENT_DMA_S2MM_0_STALLED_LOCK_PL, - XAIE_EVENT_DMA_S2MM_0_STREAM_STARVATION_PL, XAIE_EVENT_DMA_S2MM_0_MEMORY_BACKPRESSURE_PL}} + {XAIE_EVENT_DMA_S2MM_0_START_TASK_PL, XAIE_EVENT_DMA_S2MM_0_FINISHED_BD_PL, + XAIE_EVENT_DMA_S2MM_0_FINISHED_TASK_PL, XAIE_EVENT_DMA_S2MM_0_STALLED_LOCK_PL, + XAIE_EVENT_DMA_S2MM_0_STREAM_STARVATION_PL, XAIE_EVENT_DMA_S2MM_0_MEMORY_BACKPRESSURE_PL}} }; - interfaceTileEventSets["mm2s_ports"] = interfaceTileEventSets["input_ports"]; - interfaceTileEventSets["s2mm_ports"] = interfaceTileEventSets["output_ports"]; - interfaceTileEventSets["mm2s_ports_stalls"] = interfaceTileEventSets["input_ports_stalls"]; - interfaceTileEventSets["s2mm_ports_stalls"] = interfaceTileEventSets["output_ports_stalls"]; - interfaceTileEventSets["mm2s_ports_details"] = interfaceTileEventSets["input_ports_details"]; - interfaceTileEventSets["s2mm_ports_details"] = interfaceTileEventSets["output_ports_details"]; + interfaceTileEventSets["mm2s_ports"] = interfaceTileEventSets["input_ports"]; + interfaceTileEventSets["s2mm_ports"] = interfaceTileEventSets["output_ports"]; + interfaceTileEventSets["mm2s_s2mm_ports"] = interfaceTileEventSets["input_output_ports"]; + interfaceTileEventSets["mm2s_ports_stalls"] = interfaceTileEventSets["input_ports_stalls"]; + interfaceTileEventSets["s2mm_ports_stalls"] = interfaceTileEventSets["output_ports_stalls"]; + interfaceTileEventSets["mm2s_s2mm_ports_stalls"] = interfaceTileEventSets["input_output_ports_stalls"]; + interfaceTileEventSets["mm2s_ports_details"] = interfaceTileEventSets["input_ports_details"]; + interfaceTileEventSets["s2mm_ports_details"] = interfaceTileEventSets["output_ports_details"]; // Interface tile trace is flushed at end of run interfaceTileTraceStartEvent = XAIE_EVENT_TRUE_PL; @@ -565,7 +576,7 @@ namespace xdp { XAie_EventSelectStrmPort(&aieDevInst, loc, portnum, slaveOrMaster, SOUTH, streamPortId); // Record for runtime config file - config.port_trace_ids[portnum] = streamPortId; + config.port_trace_ids[portnum] = ((portnum % 2) == 0) ? channel0 : channel1; config.port_trace_is_master[portnum] = (tile.is_master != 0); if (aie::isInputSet(type, metricSet)) { @@ -1076,11 +1087,17 @@ namespace xdp { break; { - uint8_t phyEvent = 0; - XAie_EventLogicalToPhysicalConv(&aieDevInst, loc, mod, traceStartEvent, &phyEvent); - cfgTile->memory_trace_config.start_event = phyEvent; - XAie_EventLogicalToPhysicalConv(&aieDevInst, loc, mod, traceEndEvent, &phyEvent); - cfgTile->memory_trace_config.stop_event = phyEvent; + uint8_t phyEvent1 = 0; + uint8_t phyEvent2 = 0; + XAie_EventLogicalToPhysicalConv(&aieDevInst, loc, mod, traceStartEvent, &phyEvent1); + XAie_EventLogicalToPhysicalConv(&aieDevInst, loc, mod, traceEndEvent, &phyEvent2); + if (type == module_type::core) { + cfgTile->memory_trace_config.start_event = phyEvent1; + cfgTile->memory_trace_config.stop_event = phyEvent2; + } else { + cfgTile->memory_tile_trace_config.start_event = phyEvent1; + cfgTile->memory_tile_trace_config.stop_event = phyEvent2; + } } // auto ret = memoryTrace->reserve();