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Circular dependency within source files #966

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yesilzeytin opened this issue Jan 11, 2024 · 0 comments
Open

Circular dependency within source files #966

yesilzeytin opened this issue Jan 11, 2024 · 0 comments

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@yesilzeytin
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Hello, firstly, I would like to say this is a great project both for the utilities it provides and the learning it provides. So, thanks a lot for sharing this awesome work.

I have been working on integrating the instruction cover group of this project into a custom core verification environment that I have been working on in order to make it sample through uvm_monitor alongside the DUT and also support other test suites and custom tests when I faced this issue. To get the riscv_instr_cover_group.sv file up and running, I created a dependency package that would include and import all the necessary data types and functions. However, during the implementation, I realized that even though this project works quite as described when built and run standalone, it had some dependency patterns that puzzled me.

As far as I know, in SystemVerilog, one cannot have circular dependencies (two different classes or packages depending on each other) within a project (i.e., Verification Academy discussion regarding it) However, when I started fiddling with the source files manually, I realized that in line 40 of riscv_instr_gen_config.sv, there is a type data_pattern_t used within the class riscv_instr_gen_config.

// Pattern of data section: RAND_DATA, ALL_ZERO, INCR_VAL
rand data_pattern_t data_page_pattern;

This type is defined in the riscv_instr_pkg.sv package, lines 1131-1135.

// Data pattern of the memory model
typedef enum bit [1:0] {
RAND_DATA = 0,
ALL_ZERO,
INCR_VAL
} data_pattern_t;

However, riscv_instr_pkg.sv also includes riscv_instr_gen_config.sv in line 1536, which makes these two dependent on each other:

`include "riscv_instr_gen_config.sv"

and I face a syntax error through VCS regarding the type here, as follows:

image

Even though the standalone master branch works fine, I thought that this could be a problem and wanted to report it. And possibly, if this is not an issue in this project, how could this work without any issues? Is there a specific methodology employed to overcome this?

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