AXI Lite

AXI

axi is a communication protocol that aims to suppurt high troughput, out of order transaction completion, burst data transfer.

transaction

a transaction is a complete sequence (we can think of it consisting of two phase: request and response) of meaningful information transfers between a manager (master) and a subordinate (slave). There are two types of transactinos in axi:

1. read transaction: manager transfers the adress (and other metadata for the read data) via ar (read request) channel. subordinate, then, sends the read data and the read response via r channel.
2. write transaction: manager transfers the write request (adress and metadata) and the data to be written to the subordinate via aw and w channels respectively. after those, subordinate sends the write response via b channel to the manager.

channel

a channel is the place where a piece of information is transfered in a transaction. a channel from a source to a destination consist of 3 signals:

1. valid: from source to destination. says if the information is valid it is not a garbage. it also implies that source wants to send information to the destination.
2. information: from source to destination. the actual piece of data that source wants to send to the destination.
3. ready: from destination to source. signals that the destination is available to receive information from the source.

handshake

on a channel, when both source and destination agrees on transfering some information, handshaking occurs. handshaking is the time that when both valid and ready signals (which are being watched by manager and subordinate to take neccessary action) are high. handshaking occurs, source knows that information is received for the destination, and destination knows that from know on, it is responsible to take the neccessary actions. (later, destination informs the source that it completed the neccessary actions and the result of the actions via another channel)

because of the requirements of the protocol, in a transfer, source is more restricted than destination, it must keep the valid high until the transfer completes. it cannot wait for the ready signal to be asserted (raised) to raise the valid signal (i.e. it should raise valid as soon as possible). destination has more freedom, it can wait to assert (raise) the ready signal until it sees the valid from source. and it doesn't have to keep the ready signal high until it sees a valid asserted.

my comment on the restriction on the source

I understand the purpose to load the restriction to the source is to