From f4d12cf2462e11e5ba8baf70e9c6cfca35a06d16 Mon Sep 17 00:00:00 2001 From: kxxt Date: Wed, 11 Oct 2023 15:20:24 +0800 Subject: [PATCH] upgpatch: chromium - Remove old v8 build fix. - Add new v8 build fix: https://chromium-review.googlesource.com/c/v8/v8/+/4837830 --- chromium/riscv-v8.patch | 244 ++++++++++++++++++++++------------------ chromium/riscv64.patch | 14 +-- 2 files changed, 140 insertions(+), 118 deletions(-) diff --git a/chromium/riscv-v8.patch b/chromium/riscv-v8.patch index 1b8064acb..56dc391e6 100644 --- a/chromium/riscv-v8.patch +++ b/chromium/riscv-v8.patch @@ -1,126 +1,148 @@ -From 994cbb58abfb61b04f589488a0743a275a714e06 Mon Sep 17 00:00:00 2001 +From 13192d6e10fa726858056e49fc9bca6201401171 Mon Sep 17 00:00:00 2001 From: Lu Yahan -Date: Tue, 08 Aug 2023 10:30:50 +0800 -Subject: [PATCH] [riscv] Skip case about Float Nan. +Date: Tue, 5 Sep 2023 09:31:56 +0800 +Subject: [PATCH] [riscv][tagged-ptr] Convert more Objects to Tagged<> -On RISC-V, except when otherwise stated, if the result of a floating-point operation is NaN, it is the canonical Nan. +Port commit 064b9a7903b793734b6c03a86ee53a2dc85f0f80 -If the input is f32, it will be converted into f64 js code. When f32 is Nan, the output is the canonical Nan, so these cases can't get the correct result. +Bug: v8:12710 -Also port commit 0dbea94dbdd950cbe5ff018a3e43a4bac18c6045 -[compiler] Generalize InstructionSelectorT for Turboshaft (part 10) - -Bug: v8:12783 - -Change-Id: I56188b5643b71d942d505b8ec009a0353d263aff -Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/4757761 -Commit-Queue: Yahan Lu -Reviewed-by: Andreas Haas +Change-Id: If076ca5cd9e9d175c20fc3611e03d39c0260404d +Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/4837830 +Reviewed-by: Ji Qiu +Commit-Queue: Ji Qiu Auto-Submit: Yahan Lu -Cr-Commit-Position: refs/heads/main@{#89423} +Cr-Commit-Position: refs/heads/main@{#89780} --- + src/builtins/riscv/builtins-riscv.cc | 2 +- + src/codegen/riscv/assembler-riscv-inl.h | 15 ++++++++------- + src/codegen/riscv/assembler-riscv.h | 2 +- + src/execution/riscv/simulator-riscv.cc | 8 ++++---- + src/regexp/riscv/regexp-macro-assembler-riscv.cc | 2 +- + 5 files changed, 15 insertions(+), 14 deletions(-) -diff --git a/src/compiler/backend/riscv/code-generator-riscv.cc b/src/compiler/backend/riscv/code-generator-riscv.cc -index 63e2d1d..3121489 100644 ---- a/src/compiler/backend/riscv/code-generator-riscv.cc -+++ b/src/compiler/backend/riscv/code-generator-riscv.cc -@@ -1540,31 +1540,11 @@ - __ FPUCanonicalizeNaN(i.OutputDoubleRegister(), i.InputDoubleRegister(0)); - break; - case kRiscvCvtSD: { -- Label done; -- __ feq_d(kScratchReg, i.InputDoubleRegister(0), i.InputDoubleRegister(0)); -- __ fmv_x_d(kScratchReg2, i.InputDoubleRegister(0)); - __ fcvt_s_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0)); -- __ Branch(&done, eq, kScratchReg, Operand(1)); -- __ And(kScratchReg2, kScratchReg2, Operand(0x8000000000000000)); -- __ srai(kScratchReg2, kScratchReg2, 32); -- __ fmv_d_x(kScratchDoubleReg, kScratchReg2); -- __ fsgnj_s(i.OutputDoubleRegister(), i.OutputDoubleRegister(), -- kScratchDoubleReg); -- __ bind(&done); - break; - } - case kRiscvCvtDS: { -- Label done; -- __ feq_s(kScratchReg, i.InputDoubleRegister(0), i.InputDoubleRegister(0)); -- __ fmv_x_d(kScratchReg2, i.InputDoubleRegister(0)); - __ fcvt_d_s(i.OutputDoubleRegister(), i.InputSingleRegister(0)); -- __ Branch(&done, eq, kScratchReg, Operand(1)); -- __ And(kScratchReg2, kScratchReg2, Operand(0x80000000)); -- __ slli(kScratchReg2, kScratchReg2, 32); -- __ fmv_d_x(kScratchDoubleReg, kScratchReg2); -- __ fsgnj_d(i.OutputDoubleRegister(), i.OutputDoubleRegister(), -- kScratchDoubleReg); -- __ bind(&done); - break; - } - case kRiscvCvtDW: { -diff --git a/src/compiler/backend/riscv/instruction-selector-riscv.h b/src/compiler/backend/riscv/instruction-selector-riscv.h -index 91e79b2..0e5d446 100644 ---- a/src/compiler/backend/riscv/instruction-selector-riscv.h -+++ b/src/compiler/backend/riscv/instruction-selector-riscv.h -@@ -277,15 +277,19 @@ - } +diff --git a/src/builtins/riscv/builtins-riscv.cc b/src/builtins/riscv/builtins-riscv.cc +index 326001fdd18..638001f9054 100644 +--- a/src/builtins/riscv/builtins-riscv.cc ++++ b/src/builtins/riscv/builtins-riscv.cc +@@ -1673,7 +1673,7 @@ static void Generate_InterpreterEnterBytecode(MacroAssembler* masm) { + // Set the return address to the correct point in the interpreter entry + // trampoline. + Label builtin_trampoline, trampoline_loaded; +- Smi interpreter_entry_return_pc_offset( ++ Tagged interpreter_entry_return_pc_offset( + masm->isolate()->heap()->interpreter_entry_return_pc_offset()); + DCHECK_NE(interpreter_entry_return_pc_offset, Smi::zero()); - template --void InstructionSelectorT::VisitStackSlot(Node* node) { -- StackSlotRepresentation rep = StackSlotRepresentationOf(node->op()); -- int alignment = rep.alignment(); -- int slot = frame_->AllocateSpillSlot(rep.size(), alignment); -- OperandGenerator g(this); -+void InstructionSelectorT::VisitStackSlot(node_t node) { -+ if constexpr (Adapter::IsTurboshaft) { -+ UNIMPLEMENTED(); -+ } else { -+ StackSlotRepresentation rep = StackSlotRepresentationOf(node->op()); -+ int alignment = rep.alignment(); -+ int slot = frame_->AllocateSpillSlot(rep.size(), alignment); -+ OperandGenerator g(this); - -- Emit(kArchStackSlot, g.DefineAsRegister(node), -- sequence()->AddImmediate(Constant(slot)), -- sequence()->AddImmediate(Constant(alignment)), 0, nullptr); -+ Emit(kArchStackSlot, g.DefineAsRegister(node), -+ sequence()->AddImmediate(Constant(slot)), -+ sequence()->AddImmediate(Constant(alignment)), 0, nullptr); -+ } +diff --git a/src/codegen/riscv/assembler-riscv-inl.h b/src/codegen/riscv/assembler-riscv-inl.h +index 773dc560da1..8abf4b3239f 100644 +--- a/src/codegen/riscv/assembler-riscv-inl.h ++++ b/src/codegen/riscv/assembler-riscv-inl.h +@@ -128,9 +128,9 @@ Handle Assembler::compressed_embedded_object_handle_at( } - template -diff --git a/src/compiler/backend/riscv/instruction-selector-riscv32.cc b/src/compiler/backend/riscv/instruction-selector-riscv32.cc -index 727605d..abafd91 100644 ---- a/src/compiler/backend/riscv/instruction-selector-riscv32.cc -+++ b/src/compiler/backend/riscv/instruction-selector-riscv32.cc -@@ -206,6 +206,7 @@ - case MachineRepresentation::kWord64: - case MachineRepresentation::kNone: - case MachineRepresentation::kSimd256: // Fall through. -+ case MachineRepresentation::kIndirectPointer: - UNREACHABLE(); - } - -@@ -283,6 +284,7 @@ - case MachineRepresentation::kNone: - case MachineRepresentation::kWord64: - case MachineRepresentation::kSimd256: // Fall through. -+ case MachineRepresentation::kIndirectPointer: - UNREACHABLE(); - } + void Assembler::deserialization_set_special_target_at( +- Address instruction_payload, Code code, Address target) { ++ Address instruction_payload, Tagged code, Address target) { + set_target_address_at(instruction_payload, +- !code.is_null() ? code.constant_pool() : kNullAddress, ++ !code.is_null() ? code->constant_pool() : kNullAddress, + target); + } -@@ -824,6 +826,7 @@ - case MachineRepresentation::kMapWord: // Fall through. - case MachineRepresentation::kWord64: - case MachineRepresentation::kNone: -+ case MachineRepresentation::kIndirectPointer: - UNREACHABLE(); +@@ -159,12 +159,13 @@ void Assembler::deserialization_set_target_internal_reference_at( } + } -@@ -879,6 +882,7 @@ - case MachineRepresentation::kMapWord: // Fall through. - case MachineRepresentation::kNone: - case MachineRepresentation::kWord64: -+ case MachineRepresentation::kIndirectPointer: - UNREACHABLE(); +-HeapObject RelocInfo::target_object(PtrComprCageBase cage_base) { ++Tagged RelocInfo::target_object(PtrComprCageBase cage_base) { + DCHECK(IsCodeTarget(rmode_) || IsEmbeddedObjectMode(rmode_)); + if (IsCompressedEmbeddedObject(rmode_)) { +- return HeapObject::cast(Object(V8HeapCompressionScheme::DecompressTagged( +- cage_base, +- Assembler::target_compressed_address_at(pc_, constant_pool_)))); ++ return HeapObject::cast( ++ Tagged(V8HeapCompressionScheme::DecompressTagged( ++ cage_base, ++ Assembler::target_compressed_address_at(pc_, constant_pool_)))); + } else { + return HeapObject::cast( + Object(Assembler::target_address_at(pc_, constant_pool_))); +@@ -186,7 +187,7 @@ Handle RelocInfo::target_object_handle(Assembler* origin) { } + } + +-void RelocInfo::set_target_object(HeapObject target, ++void RelocInfo::set_target_object(Tagged target, + ICacheFlushMode icache_flush_mode) { + DCHECK(IsCodeTarget(rmode_) || IsEmbeddedObjectMode(rmode_)); + if (IsCompressedEmbeddedObject(rmode_)) { +diff --git a/src/codegen/riscv/assembler-riscv.h b/src/codegen/riscv/assembler-riscv.h +index 65c317ad018..ced4dd8aee8 100644 +--- a/src/codegen/riscv/assembler-riscv.h ++++ b/src/codegen/riscv/assembler-riscv.h +@@ -288,7 +288,7 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase, + // This is for calls and branches within generated code. The serializer + // has already deserialized the lui/ori instructions etc. + inline static void deserialization_set_special_target_at(Address location, +- Code code, ++ Tagged code, + Address target); + // Get the size of the special target encoded at 'instruction_payload'. +diff --git a/src/execution/riscv/simulator-riscv.cc b/src/execution/riscv/simulator-riscv.cc +index 1baf9eb6c66..5b5411cb3e2 100644 +--- a/src/execution/riscv/simulator-riscv.cc ++++ b/src/execution/riscv/simulator-riscv.cc +@@ -1889,7 +1889,7 @@ void RiscvDebugger::Debug() { + sreg_t value; + StdoutStream os; + if (GetValue(arg1, &value)) { +- Object obj(value); ++ Tagged obj(value); + os << arg1 << ": \n"; + #ifdef DEBUG + Print(obj, os); +@@ -1938,7 +1938,7 @@ void RiscvDebugger::Debug() { + PrintF(" 0x%012" PRIxPTR " : 0x%016" REGIx_FORMAT + " %14" REGId_FORMAT " ", + reinterpret_cast(cur), *cur, *cur); +- Object obj(*cur); ++ Tagged obj(*cur); + Heap* current_heap = sim_->isolate_->heap(); + if (IsSmi(obj) || + IsValidHeapObject(current_heap, HeapObject::cast(obj))) { +@@ -4815,7 +4815,7 @@ bool Simulator::DecodeRvvVS() { + Builtin Simulator::LookUp(Address pc) { + for (Builtin builtin = Builtins::kFirst; builtin <= Builtins::kLast; + ++builtin) { +- if (builtins_.code(builtin).contains(isolate_, pc)) return builtin; ++ if (builtins_.code(builtin)->contains(isolate_, pc)) return builtin; + } + return Builtin::kNoBuiltinId; + } +@@ -4832,7 +4832,7 @@ void Simulator::DecodeRVIType() { + if (builtin != Builtin::kNoBuiltinId) { + auto code = builtins_.code(builtin); + if ((rs1_reg() != ra || imm12() != 0)) { +- if ((Address)get_pc() == code.instruction_start()) { ++ if ((Address)get_pc() == code->instruction_start()) { + sreg_t arg0 = get_register(a0); + sreg_t arg1 = get_register(a1); + sreg_t arg2 = get_register(a2); +diff --git a/src/regexp/riscv/regexp-macro-assembler-riscv.cc b/src/regexp/riscv/regexp-macro-assembler-riscv.cc +index 3b57e613eef..f60f03e5eee 100644 +--- a/src/regexp/riscv/regexp-macro-assembler-riscv.cc ++++ b/src/regexp/riscv/regexp-macro-assembler-riscv.cc +@@ -1216,7 +1216,7 @@ static T* frame_entry_address(Address re_frame, int frame_offset) { + int64_t RegExpMacroAssemblerRISCV::CheckStackGuardState(Address* return_address, + Address raw_code, + Address re_frame) { +- InstructionStream re_code = InstructionStream::cast(Object(raw_code)); ++ Tagged re_code = InstructionStream::cast(Object(raw_code)); + return NativeRegExpMacroAssembler::CheckStackGuardState( + frame_entry(re_frame, kIsolateOffset), + static_cast(frame_entry(re_frame, kStartIndexOffset)), +-- +2.42.0 + diff --git a/chromium/riscv64.patch b/chromium/riscv64.patch index e6361147b..f59c5fef8 100644 --- a/chromium/riscv64.patch +++ b/chromium/riscv64.patch @@ -1,6 +1,6 @@ --- PKGBUILD +++ PKGBUILD -@@ -68,7 +68,7 @@ declare -gA _system_libs=( +@@ -63,7 +63,7 @@ declare -gA _system_libs=( [libxml]=libxml2 [libxslt]=libxslt [opus]=opus @@ -9,7 +9,7 @@ [snappy]=snappy [woff2]=woff2 [zlib]=minizip -@@ -77,6 +77,16 @@ _unwanted_bundled_libs=( +@@ -72,6 +72,16 @@ _unwanted_bundled_libs=( $(printf "%s\n" ${!_system_libs[@]} | sed 's/^libjpeg$/&_turbo/') ) depends+=(${_system_libs[@]}) @@ -22,13 +22,13 @@ + '4b2dcfdeb8ab32130d220d9827f49a930cf748bf4d6c7aef97a7b36a98316430' + '8d52d4da703c8a86059418d1a4ed63d2d6bc1134e9dfe569695a830479a9afae' + 'aab631f5b6ea316b08bd290b52f60ed7715fceabd5c8de67535271fbbe2ae794' -+ '9d16fbb661cf972da5292bf810795352d2d358bdcd446d4114181a65980b943d') ++ '21505b7c6dc28b388da49a615cf70943293f081e573d66c1b77e5123625fdbd9') # Google API keys (see https://www.chromium.org/developers/how-tos/api-keys) # Note: These are for Arch Linux use ONLY. For your own distribution, please -@@ -123,6 +133,14 @@ prepare() { - patch -Np1 -i ../patches/chromium-114-ruy-include.patch - patch -Np1 -i ../patches/chromium-114-vk_mem_alloc-include.patch +@@ -118,6 +128,14 @@ prepare() { + patch -Np1 -i ../chromium-patches-*/chromium-118-LightweightDetector-include.patch + patch -Np1 -i ../chromium-patches-*/chromium-118-system-freetype.patch + patch -Np0 -i ../swiftshader-use-llvm16.patch + @@ -41,7 +41,7 @@ # Link to system tools required by the build mkdir -p third_party/node/linux/node-linux-x64/bin ln -s /usr/bin/node third_party/node/linux/node-linux-x64/bin/ -@@ -178,6 +196,10 @@ build() { +@@ -173,6 +191,10 @@ build() { 'enable_nacl=false' 'enable_rust=false' "google_api_key=\"$_google_api_key\""