Problem with Verilog export

[JackOfShadow]

Hi! I can't export XOR gate to the Verilog.

/*
 * Generated by Digital. Don't modify this file!
 * Any changes will be lost if this file is regenerated.
 */

module \xor  ( /*Why there is a "\"-symbol in the name? */
  input a,
  input b,
  output s
);
  assign s = (a ^ b); /* <- XOR expected*/
endmodule

[JackOfShadow]

Sorry guys. My fault. I just started learning Verilog and Boolean Algebra. So I thought "^" is a logical AND.