EEPROM: A zero at addr zero seemingly without WE

[Emmett81]

Hi, I was wondering if anyone else had run into the problem below or other problems regarding the EEPROM component. I didn't see it under issues and I'm having problems reproducing it reliably and in a simpler circuit.

Sometimes, not always, when I run my design (a 32bit oisc cpu) the value at addr 0 is replaced by 0 in the eeprom component. But the only clockcycle when the WE signal is high, is when it's writing it's result to the destination addr, and it does that correctly. Looking at the graph there is no moment before or after the WE cycle that addr (or data) is set to zero.

[Emmett81]

I discovered that ~WE is low for the very first gate level clock, well before the first clock it's stable. But writing is triggered on WE. It's the only possible culprit I could find. Basically failure to properly use pull resistors. That seems to have solved it.

I am just in awe a digital simulator would catch something like that. :)

[hneemann]

When the simulator starts, the gates stabilize in random order. During this process, various similar effects can occur, and sometimes they can always have different effects.
You can use the reset component to force a certain state during the stabilization phase.

[Emmett81]

Good to know, especially handy for hdl. This design is for implementation in 7400 with async sram so I feel using pull resistors instead of the reset component makes more sense.

I feel stupid for posting it tho. :) What a major oversight on my part.

[Emmett81]

And again I was wrong. I was thinking of the test component, didn't know the reset component is an initialize signal. Makes me feel double as stupid. :) Amazing work you've done.