Verilog Include Statement

[richardson1959]

How do I use an include statement in an external verilog module to pull in a separate module? It works when I run iverilog from the command line using the -I option to specify the directory containing the file to be included, but I can't seem to get it to work by passing the -I option to iverilog through a Digital verilog module. I get an error message saying it can't find the file. I've tried several different relative and absolute paths. I am using the MinGW version of Icarus Verilog on Windows, but usually I can resolve path issues (and I can get it to work from the command line). It seems as if Digital is munging the argument in some way when passing it to iverilog.

[hneemann]

Have you tried to put the verilog file and the *.dig files in the same folder?

[richardson1959]

Yes. I can't get it to work (with or without the -I option). It finds the top-level file, but I get an error message saying that it can't find the include file.

[hneemann]

Would you like to send/attach the project? Then I can have a closer look at it.

[richardson1959]

ver_chk.zip

I've attached the project. I've stripped things down to as simple as possible. The digital schematic includes one verilog component. The verilog component is linked to an external verilog file that includes another verilog file. iverilog compiles the top-level (top.v) file without problems from the command line, but when I try to simulate in digital I get an error message indicating that the file to be included can not be found. I've tried a variety of relative and absolute paths with the "-I" option in the digital verilog component advanced options.

I am running under windows, with the MinGW version of iverilog. The -I option seems to work fine from the command line even when the file to be included is in a different directory. I've got a Linux (virtual) machine I can try, but I don't have either Digital or iverilog installed there. I'll try to get them installed and test there to see if my problem is Windows related or not.

[richardson1959]

It works under Linux if I use an absolute path to the directory containing the include file with the -I option. It doesn't work (can't find the file) if I omit the -I option or with any of the relative paths that I've tried. This is with the digital verilog component, the external verilog file and the file to be included all in the same directory. It appears that the working directory of the iverilog process is not the same as the directory containing the verilog digital component. I'm not sure why I can't get the absolute path working under Windows.

[richardson1959]

OK. It works under Windows if I use an absolute Windows style path (c:/path) to the directory containing the file to be included. I was using a MinGW style path (/c/path). It would be nice to be able to use a relative path, but I can do what I want to do. Thanks!