Reporting SVD defects to NXP

[mciantyre]

The imxrt-ral is derived from patched SVD files. The patches correct defects in SVD files. See #5 for a few SVD defects we're patching.

These patches help our users, but we might help others if we report these defects to NXP. This issue tracks SVD defect reporting to NXP. I'll occasionally report a defect to NXP, and summarize the outcomes in comments. If you'd like to help out with defect reporting, let me know, and I might be able to add you to the NXP technical support channel.

[mciantyre]

Title: Incorrect USBCMD[ATDTW] bit offset in i.MX RT SVDs
Case: 00376594
Date opened: 2021-06-26

Report

i.MX RT System View Description (SVD) files have an incorrect bit offset for USBCMD[ATDTW]. This defect affects projects that generate library code from the SVD files. The defect results in incorrect usage of the USB device controller, since it will result in an invalid semaphore between software and hardware.

Affects the SVD files for the following processors (SVD version). As of this writing, these SVDs are available at developer.arm.com.

• MIMXRT1021DAG5A (version 1.0)
• MIMXRT1051DVL6B (version 1.0)
• MIMXRT1052DVL6B (version 1.0)
• MIMXRT1061DVL6A (version 1.0)
• MIMXRT1062DVL6A (version 1.0)
• MIMXRT1064DVL6A (version 1.0)

We would expect the bit offset to be 14, as documented in the reference manual. However, in the defective SVD files, the bit offset is 12, which is documented as a reserved bit in the reference manual.

Response

NXP technical support acknowledged the discrepancy. NXP also noted that the issue affects their SDK files (demonstrated in SDK headers, IDE GUIs).

NXP's internal applications team confirmed the defect, and emphasized that 14 is the correct offset. From the support team,

This change has already been requested to SDK team so they will update this in future releases. For the SVD files that are present in the arm website, we will try to update them as well.

Since NXP is tracking the issue internally, NXP and I closed the issue on 2021-07-08.

[mciantyre]

Title: Incorrect PIT[LDVALx] bit width in i.MX RT SVDs
Case: 00413572
Date opened: 2021-08-07

Report

Select i.MX RT System View Description (SVD) files have an incorrect bit width for PIT[LDVALx]. The defect affects projects that generate library code from the SVD files. A mask generated from this bit width will prevent full utilization of the field, which may affect timing.

The defect is present in SVD files for the following i.MX RT processors (SVD version). The defective SVD files are published at developer.arm.com.

• MIMXRT1015DAF5A (version 1.0)
• MIMXRT1021DAG5A (version 1.0)

These SVD files indicate that PIT[LDVALx] is 24 bits wide. However, we would expect the SVD files to indicate a bit width of 32 for PIT[LDVALx].

Response

NXP support acknowledges that this is a problem, and recommends direct writes to the register without using a bitmask. NXP support will report the problem to the software team.

Closed by NXP on 2021-08-17 without additional input.