diff --git a/EVB-2/.gitignore b/EVB-2/.gitignore new file mode 100644 index 000000000..eb2633975 --- /dev/null +++ b/EVB-2/.gitignore @@ -0,0 +1 @@ +buildinfo/ diff --git a/EVB-2/IS_EVB-2.atsln b/EVB-2/IS_EVB-2.atsln new file mode 100644 index 000000000..0fbc0e47f --- /dev/null +++ b/EVB-2/IS_EVB-2.atsln @@ -0,0 +1,22 @@ + +Microsoft Visual Studio Solution File, Format Version 12.00 +# Atmel Studio Solution File, Format Version 11.00 +VisualStudioVersion = 14.0.23107.0 +MinimumVisualStudioVersion = 10.0.40219.1 +Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "IS_EVB-2", "IS_EVB-2\IS_EVB-2.cppproj", "{925E765A-EF7D-44B9-BD30-D7973E606927}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|ARM = Debug|ARM + Release|ARM = Release|ARM + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {925E765A-EF7D-44B9-BD30-D7973E606927}.Debug|ARM.ActiveCfg = Debug|ARM + {925E765A-EF7D-44B9-BD30-D7973E606927}.Debug|ARM.Build.0 = Debug|ARM + {925E765A-EF7D-44B9-BD30-D7973E606927}.Release|ARM.ActiveCfg = Release|ARM + {925E765A-EF7D-44B9-BD30-D7973E606927}.Release|ARM.Build.0 = Release|ARM + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection +EndGlobal diff --git a/EVB-2/IS_EVB-2/IS_EVB-2.componentinfo.xml b/EVB-2/IS_EVB-2/IS_EVB-2.componentinfo.xml new file mode 100644 index 000000000..e27575522 --- /dev/null +++ b/EVB-2/IS_EVB-2/IS_EVB-2.componentinfo.xml @@ -0,0 +1,4 @@ + + + + \ No newline at end of file diff --git a/EVB-2/IS_EVB-2/IS_EVB-2.cppproj b/EVB-2/IS_EVB-2/IS_EVB-2.cppproj new file mode 100644 index 000000000..8f44fbff0 --- /dev/null +++ b/EVB-2/IS_EVB-2/IS_EVB-2.cppproj @@ -0,0 +1,2925 @@ + + + + 2.0 + 7.0 + com.Atmel.ARMGCC.CPP + {925e765a-ef7d-44b9-bd30-d7973e606927} + ATSAME70Q20B + same70 + Executable + CPP + $(MSBuildProjectName) + .elf + $(MSBuildProjectDirectory)\$(Configuration) + EVB-2 + IS_EVB-2 + EVB-2 + Native + true + false + false + true + 0x20000000 + + true + exception_table + 2 + 0 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + com.atmel.avrdbg.tool.atmelice + J41800082852 + 0xA1020C01 + SWD + + + + 2000000 + + SWD + + com.atmel.avrdbg.tool.edbg + ATML2637010000000000 + EDBG + + 2000000 + + + + 2000000 + + SWD + + custom + + + Custom Programming Tool + + + + + 2000000 + + SWD + + com.atmel.avrdbg.tool.atmelice + J41800082852 + Atmel-ICE + + + + + 0 + + SWD + + com.atmel.avrdbg.tool.samice + 980100526 + J-Link + + + + + + True + True + True + True + True + + + BOARD=USER_BOARD + ARM_MATH_CM7=true + __FREERTOS__ + scanf=iscanf + UDD_ENABLE + SD_MMC_ENABLE + ARM + __INERTIAL_SENSE_EVB_2__ + CONF_PERIPH + NDEBUG + __SAME70Q20B__ + + + + + ../src/ASF/thirdparty/freertos/freertos-10.0.0/Source/include + ../src/ASF/thirdparty/freertos/freertos-10.0.0/Source/portable/GCC/ARM_CM7/r0p1 + ../src/ASF/common/utils/stdio/stdio_serial + ../src/ASF/common/services/serial/sam_uart + ../src/ASF/common/services/serial + ../src/ASF/sam/drivers/uart + ../src/ASF/sam/drivers/usart + ../src/ASF/sam/boards/user_board + ../src + ../src/config + ../src/drivers + ../src/ASF/common/services/storage/ctrl_access + ../src/ASF/sam/drivers/mcan + ../src/ASF/sam/drivers/rtc + ../src/ASF/sam/drivers/tc + ../src/ASF/sam/drivers/twihs + ../src/ASF/sam/drivers/xdmac + ../src/ASF/thirdparty/fatfs/fatfs-r0.09/src + ../src/ASF/common/components/memory/sd_mmc + ../src/ASF/common/services/delay + ../src/ASF/common/services/sleepmgr + ../src/ASF/common/services/spi/sam_spi + ../src/ASF/common/services/spi + ../src/ASF/common/services/spi/sam_usart_spi + ../src/ASF/common/services/usb + ../src/ASF/common/services/usb/class/cdc + ../src/ASF/common/services/usb/class/cdc/device + ../src/ASF/common/services/usb/udc + ../src/ASF/sam/drivers/hsmci + ../src/ASF/sam/drivers/spi + ../src/ASF/sam/drivers/usbhs + ../src/ASF/thirdparty/fatfs/fatfs-port-r0.09/sam + ../../../src + ../../../hw-libs + ../src/ASF/sam/drivers/rtt + ../src/ASF/sam/boards + ../src/ASF/sam/utils/cmsis/same70/include + ../src/ASF/sam/utils/cmsis/same70/source/templates + ../src/ASF/common/boards + ../src/ASF/sam/utils + ../src/ASF/sam/utils/header_files + ../src/ASF/sam/utils/preprocessor + ../src/ASF/thirdparty/CMSIS/Include + ../src/ASF/thirdparty/CMSIS/Lib/GCC + ../src/ASF/sam/utils/fpu + ../src/ASF/common/utils + ../src/ASF/common/services/ioport + ../src/ASF/common/services/clock + ../src/ASF/sam/drivers/pmc + ../src/ASF/common/services/gpio + ../src/ASF/sam/drivers/pio + ../src/ASF/sam/drivers/mpu + ../src/ASF/common/components/wifi/winc3400/wifi_drv + ../src/ASF/sam/drivers/efc + ../src/ASF/sam/services/flash_efc + ../src/ASF/sam/drivers/wdt + ../src/ASF/sam/drivers/afec + + + Optimize most (-O3) + -fdata-sections + True + True + False + True + -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Wmissing-declarations -Wimplicit-function-declaration -Wpointer-arith -std=gnu11 -ffunction-sections -fdata-sections -Wchar-subscripts -Wimplicit-int -Wmain -Wsequence-point -Wreturn-type -Wtrigraphs -Wuninitialized -Wunknown-pragmas -Wundef -Wshadow -Wwrite-strings -Wsign-compare -Wmissing-declarations -Wmissing-format-attribute -Wpacked -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -mfloat-abi=softfp -mfpu=fpv5-sp-d16 -Wno-unused -Wno-unused-function -Wno-misleading-indentation -Wno-comment -Wno-int-conversion + + + BOARD=USER_BOARD + ARM_MATH_CM7=true + __FREERTOS__ + UDD_ENABLE + SD_MMC_ENABLE + ARM + __INERTIAL_SENSE_EVB_2__ + CONF_PERIPH + NDEBUG + __SAME70Q20B__ + + + + + ../src/ASF/common/services/clock + ../src/ASF/sam/drivers/pmc + ../src/ASF/sam/utils + ../src/ASF/sam/utils/header_files + ../src/ASF/sam/utils/preprocessor + ../src/ASF/thirdparty/CMSIS/Include + ../src/ASF/thirdparty/CMSIS/Lib/GCC + ../src/ASF/sam/utils/fpu + ../src/ASF/common/utils + ../src/ASF/sam/utils/cmsis/same70/include + ../src/ASF/sam/utils/cmsis/same70/source/templates + ../src/ASF/thirdparty/freertos/freertos-10.0.0/Source/include + ../src/ASF/thirdparty/freertos/freertos-10.0.0/Source/portable/GCC/ARM_CM7/r0p1 + ../src/ASF/common/utils/stdio/stdio_serial + ../src/ASF/common/services/serial/sam_uart + ../src/ASF/common/services/serial + ../src/ASF/sam/drivers/uart + ../src/ASF/sam/drivers/usart + ../src/ASF/sam/boards/user_board + ../src/ASF/sam/boards + ../src/ASF/common/boards + ../src/ASF/common/services/ioport + ../src/ASF/common/services/gpio + ../src/ASF/sam/drivers/pio + ../src/ASF/sam/drivers/mpu + ../src + ../src/config + ../src/ASF/common/services/storage/ctrl_access + ../src/ASF/sam/drivers/mcan + ../src/ASF/sam/drivers/rtc + ../src/ASF/sam/drivers/tc + ../src/ASF/sam/drivers/twihs + ../src/ASF/sam/drivers/xdmac + ../src/ASF/thirdparty/fatfs/fatfs-r0.09/src + ../src/ASF/common/components/memory/sd_mmc + ../src/ASF/common/services/delay + ../src/ASF/common/services/sleepmgr + ../src/ASF/common/services/spi/sam_spi + ../src/ASF/common/services/spi + ../src/ASF/common/services/spi/sam_usart_spi + ../src/ASF/common/services/usb + ../src/ASF/common/services/usb/class/cdc + ../src/ASF/common/services/usb/class/cdc/device + ../src/ASF/common/services/usb/udc + ../src/ASF/sam/drivers/hsmci + ../src/ASF/sam/drivers/spi + ../src/ASF/sam/drivers/usbhs + ../src/ASF/thirdparty/fatfs/fatfs-port-r0.09/sam + ../../../src + ../../../hw-libs + ../src/ASF/sam/drivers/rtt + ../src/ASF/common/components/wifi/winc3400/wifi_drv + ../src/ASF/sam/drivers/efc + ../src/ASF/sam/services/flash_efc + ../src/ASF/sam/drivers/wdt + ../src/ASF/sam/drivers/afec + ../src/drivers + + + Optimize most (-O3) + True + True + False + -std=gnu++11 -mfloat-abi=softfp -mfpu=fpv5-d16 -Wno-comment -Wno-switch -Wno-unused-function -Wno-parentheses + + + libarm_cortexM7lfsp_math_softfp + libm + + + + + ../src/ASF/thirdparty/CMSIS/Lib/GCC + + + True + + -Wl,--entry=Reset_Handler -Wl,--cref -mthumb -T../src/ASF/sam/utils/linker_scripts/same70/same70q21/gcc/flash.ld + + + ../src/ASF/thirdparty/freertos/freertos-10.0.0/Source/include + ../src/ASF/thirdparty/freertos/freertos-10.0.0/Source/portable/GCC/ARM_CM7/r0p1 + ../src/ASF/common/utils/stdio/stdio_serial + ../src/ASF/common/services/serial/sam_uart + ../src/ASF/common/services/serial + ../src/ASF/sam/drivers/uart + ../src/ASF/sam/drivers/usart + ../src/ASF/sam/boards/user_board + ../src + ../src/config + ../src/ASF/common/services/storage/ctrl_access + ../src/ASF/sam/drivers/mcan + ../src/ASF/sam/drivers/rtc + ../src/ASF/sam/drivers/tc + ../src/ASF/sam/drivers/twihs + ../src/ASF/sam/drivers/xdmac + ../src/ASF/thirdparty/fatfs/fatfs-r0.09/src + ../src/ASF/common/components/memory/sd_mmc + ../src/ASF/common/services/delay + ../src/ASF/common/services/sleepmgr + ../src/ASF/common/services/spi/sam_spi + ../src/ASF/common/services/spi + ../src/ASF/common/services/spi/sam_usart_spi + ../src/ASF/common/services/usb + ../src/ASF/common/services/usb/class/cdc + ../src/ASF/common/services/usb/class/cdc/device + ../src/ASF/common/services/usb/udc + ../src/ASF/sam/drivers/hsmci + ../src/ASF/sam/drivers/spi + ../src/ASF/sam/drivers/usbhs + ../src/ASF/thirdparty/fatfs/fatfs-port-r0.09/sam + ../../../src + ../../../hw-libs + ../src/ASF/sam/drivers/rtt + ../src/ASF/sam/boards + ../src/ASF/sam/utils/cmsis/same70/include + ../src/ASF/sam/utils/cmsis/same70/source/templates + ../src/ASF/common/boards + ../src/ASF/sam/utils + ../src/ASF/sam/utils/header_files + ../src/ASF/sam/utils/preprocessor + ../src/ASF/thirdparty/CMSIS/Include + ../src/ASF/thirdparty/CMSIS/Lib/GCC + ../src/ASF/sam/utils/fpu + ../src/ASF/common/utils + ../src/ASF/common/services/ioport + ../src/ASF/common/services/clock + ../src/ASF/sam/drivers/pmc + ../src/ASF/common/services/gpio + ../src/ASF/sam/drivers/pio + ../src/ASF/sam/drivers/mpu + ../src/ASF/common/components/wifi/winc3400/wifi_drv + ../src/ASF/sam/drivers/efc + ../src/ASF/sam/services/flash_efc + ../src/ASF/sam/drivers/wdt + ../src/ASF/sam/drivers/afec + + + -DARM_MATH_CM7=true -DBOARD=USER_BOARD -D__FREERTOS__ -D__SAME70Q20B__ -DUDD_ENABLE -DSD_MMC_ENABLE -D__SAME70Q21B__ -DBOARD=SAME70_XPLAINED -Dprintf=iprintf -Dscanf=iscanf -DCONF_PERIPH + + + ../src/ASF/thirdparty/freertos/freertos-10.0.0/Source/include + ../src/ASF/thirdparty/freertos/freertos-10.0.0/Source/portable/GCC/ARM_CM7/r0p1 + ../src/ASF/common/utils/stdio/stdio_serial + ../src/ASF/common/services/serial/sam_uart + ../src/ASF/common/services/serial + ../src/ASF/sam/drivers/uart + ../src/ASF/sam/drivers/usart + ../src/ASF/sam/boards/user_board + ../src + ../src/config + ../src/ASF/common/services/storage/ctrl_access + ../src/ASF/sam/drivers/mcan + ../src/ASF/sam/drivers/rtc + ../src/ASF/sam/drivers/tc + ../src/ASF/sam/drivers/twihs + ../src/ASF/sam/drivers/xdmac + ../src/ASF/thirdparty/fatfs/fatfs-r0.09/src + ../src/ASF/common/components/memory/sd_mmc + ../src/ASF/common/services/delay + ../src/ASF/common/services/sleepmgr + ../src/ASF/common/services/spi/sam_spi + ../src/ASF/common/services/spi + ../src/ASF/common/services/spi/sam_usart_spi + ../src/ASF/common/services/usb + ../src/ASF/common/services/usb/class/cdc + ../src/ASF/common/services/usb/class/cdc/device + ../src/ASF/common/services/usb/udc + ../src/ASF/sam/drivers/hsmci + ../src/ASF/sam/drivers/spi + ../src/ASF/sam/drivers/usbhs + ../src/ASF/thirdparty/fatfs/fatfs-port-r0.09/sam + ../../../src + ../../../hw-libs + ../src/ASF/sam/drivers/rtt + ../src/ASF/sam/boards + ../src/ASF/sam/utils/cmsis/same70/include + ../src/ASF/sam/utils/cmsis/same70/source/templates + ../src/ASF/common/boards + ../src/ASF/sam/utils + ../src/ASF/sam/utils/header_files + ../src/ASF/sam/utils/preprocessor + ../src/ASF/thirdparty/CMSIS/Include + ../src/ASF/thirdparty/CMSIS/Lib/GCC + ../src/ASF/sam/utils/fpu + ../src/ASF/common/utils + ../src/ASF/common/services/ioport + ../src/ASF/common/services/clock + ../src/ASF/sam/drivers/pmc + ../src/ASF/common/services/gpio + ../src/ASF/sam/drivers/pio + ../src/ASF/sam/drivers/mpu + ../src/ASF/common/components/wifi/winc3400/wifi_drv + ../src/ASF/sam/drivers/efc + ../src/ASF/sam/services/flash_efc + ../src/ASF/sam/drivers/wdt + ../src/ASF/sam/drivers/afec + + + + + ARM_MATH_CM7 + + + + + + + IS_EVB-2 + .elf + True + $(MSBuildProjectDirectory)\.. + all -j8 + clean + ..\Makefile + echo f | xcopy .\Release\IS_EVB-2.elf .\IS_EVB-2.elf /y + + + + + True + True + True + True + True + + + BOARD=USER_BOARD + ARM_MATH_CM7=true + __FREERTOS__ + scanf=iscanf + UDD_ENABLE + SD_MMC_ENABLE + ARM + __INERTIAL_SENSE_EVB_2__ + CONF_PERIPH + DEBUG + __SAME70Q2B__ + + + + + ../src/ASF/thirdparty/freertos/freertos-10.0.0/Source/include + ../src/ASF/thirdparty/freertos/freertos-10.0.0/Source/portable/GCC/ARM_CM7/r0p1 + ../src/ASF/common/utils/stdio/stdio_serial + ../src/ASF/common/services/serial/sam_uart + ../src/ASF/common/services/serial + ../src/ASF/sam/drivers/uart + ../src/ASF/sam/drivers/usart + ../src/ASF/sam/boards/user_board + ../src + ../src/config + ../src/drivers + ../src/ASF/common/services/storage/ctrl_access + ../src/ASF/sam/drivers/mcan + ../src/ASF/sam/drivers/rtc + ../src/ASF/sam/drivers/tc + ../src/ASF/sam/drivers/twihs + ../src/ASF/sam/drivers/xdmac + ../src/ASF/thirdparty/fatfs/fatfs-r0.09/src + ../src/ASF/common/components/memory/sd_mmc + ../src/ASF/common/services/delay + ../src/ASF/common/services/sleepmgr + ../src/ASF/common/services/spi/sam_spi + ../src/ASF/common/services/spi + ../src/ASF/common/services/spi/sam_usart_spi + ../src/ASF/common/services/usb + ../src/ASF/common/services/usb/class/cdc + ../src/ASF/common/services/usb/class/cdc/device + ../src/ASF/common/services/usb/udc + ../src/ASF/sam/drivers/hsmci + ../src/ASF/sam/drivers/spi + ../src/ASF/sam/drivers/usbhs + ../src/ASF/thirdparty/fatfs/fatfs-port-r0.09/sam + ../../../src + ../../../hw-libs + ../src/ASF/sam/drivers/rtt + ../src/ASF/sam/boards + ../src/ASF/sam/utils/cmsis/same70/include + ../src/ASF/sam/utils/cmsis/same70/source/templates + ../src/ASF/common/boards + ../src/ASF/sam/utils + ../src/ASF/sam/utils/header_files + ../src/ASF/sam/utils/preprocessor + ../src/ASF/thirdparty/CMSIS/Include + ../src/ASF/thirdparty/CMSIS/Lib/GCC + ../src/ASF/sam/utils/fpu + ../src/ASF/common/utils + ../src/ASF/common/services/ioport + ../src/ASF/common/services/clock + ../src/ASF/sam/drivers/pmc + ../src/ASF/common/services/gpio + ../src/ASF/sam/drivers/pio + ../src/ASF/sam/drivers/mpu + ../src/ASF/common/components/wifi/winc3400/wifi_drv + ../src/ASF/sam/drivers/efc + ../src/ASF/sam/services/flash_efc + ../../../hw-libs/drivers + ../src/ASF/sam/drivers/wdt + ../src/ASF/sam/drivers/afec + + + -fdata-sections + True + True + False + Maximum (-g3) + True + -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Wmissing-declarations -Wimplicit-function-declaration -Wpointer-arith -std=gnu11 -ffunction-sections -fdata-sections -Wchar-subscripts -Wimplicit-int -Wmain -Wsequence-point -Wreturn-type -Wtrigraphs -Wuninitialized -Wunknown-pragmas -Wundef -Wshadow -Wwrite-strings -Wsign-compare -Wmissing-declarations -Wmissing-format-attribute -Wpacked -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -mfloat-abi=softfp -mfpu=fpv5-sp-d16 -Wno-unused -Wno-unused-function -Wno-misleading-indentation -Wno-comment -Wno-int-conversion + + + BOARD=USER_BOARD + ARM_MATH_CM7=true + __FREERTOS__ + UDD_ENABLE + SD_MMC_ENABLE + ARM + __INERTIAL_SENSE_EVB_2__ + CONF_PERIPH + DEBUG + + + + + ../src/ASF/common/services/clock + ../src/ASF/sam/drivers/pmc + ../src/ASF/sam/utils + ../src/ASF/sam/utils/header_files + ../src/ASF/sam/utils/preprocessor + ../src/ASF/thirdparty/CMSIS/Include + ../src/ASF/thirdparty/CMSIS/Lib/GCC + ../src/ASF/sam/utils/fpu + ../src/ASF/common/utils + ../src/ASF/sam/utils/cmsis/same70/include + ../src/ASF/sam/utils/cmsis/same70/source/templates + ../src/ASF/thirdparty/freertos/freertos-10.0.0/Source/include + ../src/ASF/thirdparty/freertos/freertos-10.0.0/Source/portable/GCC/ARM_CM7/r0p1 + ../src/ASF/common/utils/stdio/stdio_serial + ../src/ASF/common/services/serial/sam_uart + ../src/ASF/common/services/serial + ../src/ASF/sam/drivers/uart + ../src/ASF/sam/drivers/usart + ../src/ASF/sam/boards/user_board + ../src/ASF/sam/boards + ../src/ASF/common/boards + ../src/ASF/common/services/ioport + ../src/ASF/common/services/gpio + ../src/ASF/sam/drivers/pio + ../src/ASF/sam/drivers/mpu + ../src + ../src/config + ../src/ASF/common/services/storage/ctrl_access + ../src/ASF/sam/drivers/mcan + ../src/ASF/sam/drivers/rtc + ../src/ASF/sam/drivers/tc + ../src/ASF/sam/drivers/twihs + ../src/ASF/sam/drivers/xdmac + ../src/ASF/thirdparty/fatfs/fatfs-r0.09/src + ../src/ASF/common/components/memory/sd_mmc + ../src/ASF/common/services/delay + ../src/ASF/common/services/sleepmgr + ../src/ASF/common/services/spi/sam_spi + ../src/ASF/common/services/spi + ../src/ASF/common/services/spi/sam_usart_spi + ../src/ASF/common/services/usb + ../src/ASF/common/services/usb/class/cdc + ../src/ASF/common/services/usb/class/cdc/device + ../src/ASF/common/services/usb/udc + ../src/ASF/sam/drivers/hsmci + ../src/ASF/sam/drivers/spi + ../src/ASF/sam/drivers/usbhs + ../src/ASF/thirdparty/fatfs/fatfs-port-r0.09/sam + ../../../src + ../../../hw-libs + ../src/ASF/sam/drivers/rtt + ../src/ASF/common/components/wifi/winc3400/wifi_drv + ../src/ASF/sam/drivers/efc + ../src/ASF/sam/services/flash_efc + ../src/drivers + ../../../hw-libs/drivers + ../src/ASF/sam/drivers/wdt + ../src/ASF/sam/drivers/afec + + + -fdata-sections + True + True + False + Maximum (-g3) + True + -std=gnu++11 -mfloat-abi=softfp -mfpu=fpv5-d16 -Wno-comment -Wno-switch -Wno-unused-function -Wno-parentheses + + + libarm_cortexM7lfsp_math_softfp + libm + + + + + ../src/ASF/thirdparty/CMSIS/Lib/GCC + + + True + + -Wl,--entry=Reset_Handler -Wl,--cref -mthumb -T../src/ASF/sam/utils/linker_scripts/same70/same70q21/gcc/flash.ld + + + ../src/ASF/thirdparty/freertos/freertos-10.0.0/Source/include + ../src/ASF/thirdparty/freertos/freertos-10.0.0/Source/portable/GCC/ARM_CM7/r0p1 + ../src/ASF/common/utils/stdio/stdio_serial + ../src/ASF/common/services/serial/sam_uart + ../src/ASF/common/services/serial + ../src/ASF/sam/drivers/uart + ../src/ASF/sam/drivers/usart + ../src/ASF/sam/boards/user_board + ../src + ../src/config + ../src/ASF/common/services/storage/ctrl_access + ../src/ASF/sam/drivers/mcan + ../src/ASF/sam/drivers/rtc + ../src/ASF/sam/drivers/tc + ../src/ASF/sam/drivers/twihs + ../src/ASF/sam/drivers/xdmac + ../src/ASF/thirdparty/fatfs/fatfs-r0.09/src + ../src/ASF/common/components/memory/sd_mmc + ../src/ASF/common/services/delay + ../src/ASF/common/services/sleepmgr + ../src/ASF/common/services/spi/sam_spi + ../src/ASF/common/services/spi + ../src/ASF/common/services/spi/sam_usart_spi + ../src/ASF/common/services/usb + ../src/ASF/common/services/usb/class/cdc + ../src/ASF/common/services/usb/class/cdc/device + ../src/ASF/common/services/usb/udc + ../src/ASF/sam/drivers/hsmci + ../src/ASF/sam/drivers/spi + ../src/ASF/sam/drivers/usbhs + ../src/ASF/thirdparty/fatfs/fatfs-port-r0.09/sam + ../../../src + ../../../hw-libs + ../src/ASF/sam/drivers/rtt + ../src/ASF/sam/boards + ../src/ASF/sam/utils/cmsis/same70/include + ../src/ASF/sam/utils/cmsis/same70/source/templates + ../src/ASF/common/boards + ../src/ASF/sam/utils + ../src/ASF/sam/utils/header_files + ../src/ASF/sam/utils/preprocessor + ../src/ASF/thirdparty/CMSIS/Include + ../src/ASF/thirdparty/CMSIS/Lib/GCC + ../src/ASF/sam/utils/fpu + ../src/ASF/common/utils + ../src/ASF/common/services/ioport + ../src/ASF/common/services/clock + ../src/ASF/sam/drivers/pmc + ../src/ASF/common/services/gpio + ../src/ASF/sam/drivers/pio + ../src/ASF/sam/drivers/mpu + ../src/ASF/common/components/wifi/winc3400/wifi_drv + ../src/ASF/sam/drivers/efc + ../src/ASF/sam/services/flash_efc + ../src/ASF/sam/drivers/wdt + ../src/ASF/sam/drivers/afec + + + Default (-g) + -DARM_MATH_CM7=true -DBOARD=USER_BOARD -D__FREERTOS__ -D__SAME70Q20B__ -DUDD_ENABLE -DSD_MMC_ENABLE -D__SAME70Q21B__ -DBOARD=SAME70_XPLAINED -Dprintf=iprintf -Dscanf=iscanf -DCONF_PERIPH + + + ../src/ASF/thirdparty/freertos/freertos-10.0.0/Source/include + ../src/ASF/thirdparty/freertos/freertos-10.0.0/Source/portable/GCC/ARM_CM7/r0p1 + ../src/ASF/common/utils/stdio/stdio_serial + ../src/ASF/common/services/serial/sam_uart + ../src/ASF/common/services/serial + ../src/ASF/sam/drivers/uart + ../src/ASF/sam/drivers/usart + ../src/ASF/sam/boards/user_board + ../src + ../src/config + ../src/ASF/common/services/storage/ctrl_access + ../src/ASF/sam/drivers/mcan + ../src/ASF/sam/drivers/rtc + ../src/ASF/sam/drivers/tc + ../src/ASF/sam/drivers/twihs + ../src/ASF/sam/drivers/xdmac + ../src/ASF/thirdparty/fatfs/fatfs-r0.09/src + ../src/ASF/common/components/memory/sd_mmc + ../src/ASF/common/services/delay + ../src/ASF/common/services/sleepmgr + ../src/ASF/common/services/spi/sam_spi + ../src/ASF/common/services/spi + ../src/ASF/common/services/spi/sam_usart_spi + ../src/ASF/common/services/usb + ../src/ASF/common/services/usb/class/cdc + ../src/ASF/common/services/usb/class/cdc/device + ../src/ASF/common/services/usb/udc + ../src/ASF/sam/drivers/hsmci + ../src/ASF/sam/drivers/spi + ../src/ASF/sam/drivers/usbhs + ../src/ASF/thirdparty/fatfs/fatfs-port-r0.09/sam + ../../../src + ../../../hw-libs + ../src/ASF/sam/drivers/rtt + ../src/ASF/sam/boards + ../src/ASF/sam/utils/cmsis/same70/include + ../src/ASF/sam/utils/cmsis/same70/source/templates + ../src/ASF/common/boards + ../src/ASF/sam/utils + ../src/ASF/sam/utils/header_files + ../src/ASF/sam/utils/preprocessor + ../src/ASF/thirdparty/CMSIS/Include + ../src/ASF/thirdparty/CMSIS/Lib/GCC + ../src/ASF/sam/utils/fpu + ../src/ASF/common/utils + ../src/ASF/common/services/ioport + ../src/ASF/common/services/clock + ../src/ASF/sam/drivers/pmc + ../src/ASF/common/services/gpio + ../src/ASF/sam/drivers/pio + ../src/ASF/sam/drivers/mpu + ../src/ASF/common/components/wifi/winc3400/wifi_drv + ../src/ASF/sam/drivers/efc + ../src/ASF/sam/services/flash_efc + ../src/ASF/sam/drivers/wdt + ../src/ASF/sam/drivers/afec + + + + + ARM_MATH_CM7 + + + Default (-Wa,-g) + + + + + True + $(MSBuildProjectDirectory)\.. + all -j8 DEBUG=GDB + clean DEBUG=GDB + ..\Makefile + echo f | xcopy .\Debug\IS_EVB-2.elf .\IS_EVB-2.elf /y + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + compile + src\inertial-sense-sdk\hw-libs\communications\CAN_comm.h + + + compile + src\inertial-sense-sdk\hw-libs\drivers\d_time.c + + + compile + src\inertial-sense-sdk\hw-libs\drivers\d_time.h + + + compile + src\inertial-sense-sdk\hw-libs\printf-master\printf.c + + + compile + src\inertial-sense-sdk\hw-libs\printf-master\printf.h + + + compile + src\inertial-sense-sdk\src\protocol_nmea.cpp + + + compile + src\inertial-sense-sdk\src\protocol_nmea.h + + + compile + src\inertial-sense-sdk\src\time_conversion.c + + + compile + src\inertial-sense-sdk\src\time_conversion.h + + + compile + + + compile + + + compile + + + compile + src\inertial-sense-sdk\src\com_manager.c + + + compile + src\inertial-sense-sdk\src\com_manager.h + + + compile + src\inertial-sense-sdk\src\DataCSV.cpp + + + compile + src\inertial-sense-sdk\src\DataCSV.h + + + compile + src\inertial-sense-sdk\src\data_sets.c + + + compile + src\inertial-sense-sdk\src\data_sets.h + + + compile + src\inertial-sense-sdk\src\DeviceLogRaw.cpp + + + compile + src\inertial-sense-sdk\src\DeviceLogSerial.cpp + + + compile + src\inertial-sense-sdk\src\ISComm.c + + + compile + src\inertial-sense-sdk\src\ISComm.h + + + compile + src\inertial-sense-sdk\src\ISDataMappings.cpp + + + compile + src\inertial-sense-sdk\src\ISFileManager.cpp + + + compile + src\inertial-sense-sdk\src\ISFileManager.h + + + compile + src\inertial-sense-sdk\src\ISLogger.cpp + + + compile + src\inertial-sense-sdk\src\ISLogger.h + + + compile + src\inertial-sense-sdk\src\ISLogStats.cpp + + + compile + src\inertial-sense-sdk\src\ISLogStats.h + + + compile + src\inertial-sense-sdk\src\DeviceLog.cpp + + + compile + src\inertial-sense-sdk\src\DeviceLogSerial.h + + + compile + src\inertial-sense-sdk\src\DataChunk.cpp + + + compile + src\inertial-sense-sdk\src\filters.cpp + + + compile + src\inertial-sense-sdk\src\ISDataMappings.h + + + compile + src\inertial-sense-sdk\src\convert_ins.h + + + compile + src\inertial-sense-sdk\src\ISConstants.h + + + compile + src\inertial-sense-sdk\src\ISMatrix.c + + + compile + src\inertial-sense-sdk\src\ISMatrix.h + + + compile + src\inertial-sense-sdk\src\ISPose.c + + + compile + src\inertial-sense-sdk\src\ISPose.h + + + compile + src\inertial-sense-sdk\src\ISEarth.c + + + compile + src\inertial-sense-sdk\src\ISEarth.h + + + compile + src\inertial-sense-sdk\src\ISUtilities.c + + + compile + src\inertial-sense-sdk\src\ISUtilities.h + + + compile + src\inertial-sense-sdk\hw-libs\drivers\CAN.c + + + compile + src\inertial-sense-sdk\hw-libs\drivers\CAN.h + + + compile + src\inertial-sense-sdk\hw-libs\drivers\d_dma.c + + + compile + src\inertial-sense-sdk\hw-libs\drivers\d_dma.h + + + compile + src\inertial-sense-sdk\hw-libs\drivers\d_flash.c + + + compile + src\inertial-sense-sdk\hw-libs\drivers\d_flash.h + + + compile + src\inertial-sense-sdk\hw-libs\drivers\d_i2c.c + + + compile + src\inertial-sense-sdk\hw-libs\drivers\d_i2c.h + + + compile + src\inertial-sense-sdk\hw-libs\drivers\d_usartDMA.c + + + compile + src\inertial-sense-sdk\hw-libs\drivers\d_usartDMA.h + + + compile + src\inertial-sense-sdk\hw-libs\FreeRTOS_new.cpp + + + compile + src\inertial-sense-sdk\hw-libs\misc\bootloaderApp.c + + + compile + src\inertial-sense-sdk\hw-libs\misc\bootloaderApp.h + + + compile + src\inertial-sense-sdk\hw-libs\misc\rtos.c + + + compile + src\inertial-sense-sdk\hw-libs\misc\rtos.h + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + 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compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + src\ASF\thirdparty\freertos\freertos-10.0.0\Source\portable\MemMang\heap_4.c + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + src\ISLogFileFatFs.cpp + + + compile + src\ISLogFileFatFs.h + + + compile + + + compile + + + compile + + + + \ No newline at end of file diff --git a/EVB-2/IS_EVB-2/SAMx70-FLASH.ld b/EVB-2/IS_EVB-2/SAMx70-FLASH.ld new file mode 100644 index 000000000..3cbf40ab0 --- /dev/null +++ b/EVB-2/IS_EVB-2/SAMx70-FLASH.ld @@ -0,0 +1,190 @@ +/** + * \file + * + * Copyright (c) 2015 Microchip Technology Inc. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAME70Q20 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00406000, LENGTH = 0x000EA000 + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000; +__ram_end__ = ORIGIN(ram) + LENGTH(ram) - 4; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x400; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + + /* SIGNATURE */ + BYTE(0x46); BYTE(0x0F); BYTE(0xF9); BYTE(0xA7); BYTE(0x17); BYTE(0x7D); BYTE(0x4E); BYTE(0x99); BYTE(0xDB); BYTE(0x53); BYTE(0xA2); BYTE(0x72); BYTE(0xE7); BYTE(0xC3); BYTE(0xE1); BYTE(0x52); + + /* REPEAT SIGNATURE TO INDICATE EXTENDED INFO AVAILABLE */ + /* BYTE(0x45); BYTE(0x0F); BYTE(0xF9); BYTE(0xA7); BYTE(0x17); BYTE(0x7D); BYTE(0x4E); BYTE(0x99); BYTE(0xDB); BYTE(0x53); BYTE(0xA2); BYTE(0x72); BYTE(0xE7); BYTE(0xC3); BYTE(0xE1); BYTE(0x51); */ + + /* + EXTENDED INFO - First four bytes are flags, followed by info + Flag 0x00000001 : Version info bit. Version is 32 bit unsigned integer, little endian. + */ + /* BYTE(0x00); BYTE(0x00); BYTE(0x00); BYTE(0x01); BYTE(0x00); BYTE(0x00); BYTE(0x00); BYTE(0x01); */ + + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + KEEP(*(.WMMData)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(MCAN MCAN.*) + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) -1 ; +} + diff --git a/EVB-2/IS_EVB-2/atmel_devices_cdc.cat b/EVB-2/IS_EVB-2/atmel_devices_cdc.cat new file mode 100644 index 000000000..09a0673b2 Binary files /dev/null and b/EVB-2/IS_EVB-2/atmel_devices_cdc.cat differ diff --git a/EVB-2/IS_EVB-2/atmel_devices_cdc.inf b/EVB-2/IS_EVB-2/atmel_devices_cdc.inf new file mode 100644 index 000000000..1d7b56238 --- /dev/null +++ b/EVB-2/IS_EVB-2/atmel_devices_cdc.inf @@ -0,0 +1,182 @@ +; Windows 2000, XP, Vista, 7 and 8 (x32 and x64) setup file for Atmel CDC Devices +; Copyright (c) 2000-2013 ATMEL, Inc. + +[Version] +Signature = "$Windows NT$" +Class = Ports +ClassGuid = {4D36E978-E325-11CE-BFC1-08002BE10318} + +Provider = %Manufacturer% +LayoutFile = layout.inf +CatalogFile = atmel_devices_cdc.cat +DriverVer = 01/08/2013,6.0.0.0 + +;---------------------------------------------------------- +; Targets +;---------------------------------------------------------- +[Manufacturer] +%Manufacturer%=DeviceList, NTAMD64, NTIA64, NT + +[DeviceList] +%ATMEL_CDC_XPLAINED%=DriverInstall, USB\VID_03EB&PID_2122 +%ATMEL_CDC_USB_ZIGBIT_Sub%=DriverInstall, USB\VID_03EB&PID_214B +%ATMEL_CDC_USB_ZIGBIT_2_4%=DriverInstall, USB\VID_03EB&PID_214A +%ATMEL_CDC_SFW_EXAMPLE%=DriverInstall, USB\VID_03EB&PID_2307 +%ATMEL_CDC_EVK1XXX%=DriverInstall, USB\VID_03EB&PID_2310 +%ATMEL_CDC_ASF_EXAMPLE%=DriverInstall, USB\VID_03EB&PID_2404 +%ATMEL_CDC_ASF_COMPOSITE_EXAMPLE2%=DriverInstall, USB\VID_03EB&PID_2421&MI_00 +%ATMEL_CDC_ASF_COMPOSITE_EXAMPLE4%=DriverInstall, USB\VID_03EB&PID_2424&MI_00 +%ATMEL_CDC_ASF_EXAMPLE2_COM1%=DriverInstall, USB\VID_03EB&PID_2425&MI_00 +%ATMEL_CDC_ASF_EXAMPLE2_COM2%=DriverInstall, USB\VID_03EB&PID_2425&MI_02 +%ATMEL_CDC_ASF_EXAMPLE3_COM1%=DriverInstall, USB\VID_03EB&PID_2426&MI_00 +%ATMEL_CDC_ASF_EXAMPLE3_COM2%=DriverInstall, USB\VID_03EB&PID_2426&MI_02 +%ATMEL_CDC_ASF_EXAMPLE3_COM3%=DriverInstall, USB\VID_03EB&PID_2426&MI_04 +%ATMEL_CDC_ASF_EXAMPLE3_COM4%=DriverInstall, USB\VID_03EB&PID_2426&MI_06 +%ATMEL_CDC_ASF_EXAMPLE3_COM5%=DriverInstall, USB\VID_03EB&PID_2426&MI_08 +%ATMEL_CDC_ASF_EXAMPLE3_COM6%=DriverInstall, USB\VID_03EB&PID_2426&MI_0A +%ATMEL_CDC_ASF_EXAMPLE3_COM7%=DriverInstall, USB\VID_03EB&PID_2426&MI_0C + +[DeviceList.NTAMD64] +%ATMEL_CDC_XPLAINED%=DriverInstall.NTamd64, USB\VID_03EB&PID_2122 +%ATMEL_CDC_USB_ZIGBIT_Sub%=DriverInstall.NTamd64, USB\VID_03EB&PID_214B +%ATMEL_CDC_USB_ZIGBIT_2_4%=DriverInstall.NTamd64, USB\VID_03EB&PID_214A +%ATMEL_CDC_SFW_EXAMPLE%=DriverInstall.NTamd64, USB\VID_03EB&PID_2307 +%ATMEL_CDC_EVK1XXX%=DriverInstall.NTamd64, USB\VID_03EB&PID_2310 +%ATMEL_CDC_ASF_EXAMPLE%=DriverInstall.NTamd64, USB\VID_03EB&PID_2404 +%ATMEL_CDC_ASF_COMPOSITE_EXAMPLE2%=DriverInstall.NTamd64, USB\VID_03EB&PID_2421&MI_00 +%ATMEL_CDC_ASF_COMPOSITE_EXAMPLE4%=DriverInstall.NTamd64, USB\VID_03EB&PID_2424&MI_00 +%ATMEL_CDC_ASF_EXAMPLE2_COM1%=DriverInstall.NTamd64, USB\VID_03EB&PID_2425&MI_00 +%ATMEL_CDC_ASF_EXAMPLE2_COM2%=DriverInstall.NTamd64, USB\VID_03EB&PID_2425&MI_02 +%ATMEL_CDC_ASF_EXAMPLE3_COM1%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_00 +%ATMEL_CDC_ASF_EXAMPLE3_COM2%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_02 +%ATMEL_CDC_ASF_EXAMPLE3_COM3%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_04 +%ATMEL_CDC_ASF_EXAMPLE3_COM4%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_06 +%ATMEL_CDC_ASF_EXAMPLE3_COM5%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_08 +%ATMEL_CDC_ASF_EXAMPLE3_COM6%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_0A +%ATMEL_CDC_ASF_EXAMPLE3_COM7%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_0C + +[DeviceList.NTIA64] +%ATMEL_CDC_XPLAINED%=DriverInstall.NTamd64, USB\VID_03EB&PID_2122 +%ATMEL_CDC_USB_ZIGBIT_Sub%=DriverInstall.NTamd64, USB\VID_03EB&PID_214B +%ATMEL_CDC_USB_ZIGBIT_2_4%=DriverInstall.NTamd64, USB\VID_03EB&PID_214A +%ATMEL_CDC_SFW_EXAMPLE%=DriverInstall.NTamd64, USB\VID_03EB&PID_2307 +%ATMEL_CDC_EVK1XXX%=DriverInstall.NTamd64, USB\VID_03EB&PID_2310 +%ATMEL_CDC_ASF_EXAMPLE%=DriverInstall.NTamd64, USB\VID_03EB&PID_2404 +%ATMEL_CDC_ASF_COMPOSITE_EXAMPLE2%=DriverInstall.NTamd64, USB\VID_03EB&PID_2421&MI_00 +%ATMEL_CDC_ASF_COMPOSITE_EXAMPLE4%=DriverInstall.NTamd64, USB\VID_03EB&PID_2424&MI_00 +%ATMEL_CDC_ASF_EXAMPLE2_COM1%=DriverInstall.NTamd64, USB\VID_03EB&PID_2425&MI_00 +%ATMEL_CDC_ASF_EXAMPLE2_COM2%=DriverInstall.NTamd64, USB\VID_03EB&PID_2425&MI_02 +%ATMEL_CDC_ASF_EXAMPLE3_COM1%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_00 +%ATMEL_CDC_ASF_EXAMPLE3_COM2%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_02 +%ATMEL_CDC_ASF_EXAMPLE3_COM3%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_04 +%ATMEL_CDC_ASF_EXAMPLE3_COM4%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_06 +%ATMEL_CDC_ASF_EXAMPLE3_COM5%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_08 +%ATMEL_CDC_ASF_EXAMPLE3_COM6%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_0A +%ATMEL_CDC_ASF_EXAMPLE3_COM7%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_0C + +[DeviceList.NT] +%ATMEL_CDC_XPLAINED%=DriverInstall.NT, USB\VID_03EB&PID_2122 +%ATMEL_CDC_USB_ZIGBIT_Sub%=DriverInstall.NT, USB\VID_03EB&PID_214B +%ATMEL_CDC_USB_ZIGBIT_2_4%=DriverInstall.NT, USB\VID_03EB&PID_214A +%ATMEL_CDC_SFW_EXAMPLE%=DriverInstall.NT, USB\VID_03EB&PID_2307 +%ATMEL_CDC_EVK1XXX%=DriverInstall.NT, USB\VID_03EB&PID_2310 +%ATMEL_CDC_ASF_EXAMPLE%=DriverInstall.NT, USB\VID_03EB&PID_2404 +%ATMEL_CDC_ASF_COMPOSITE_EXAMPLE2%=DriverInstall.NT, USB\VID_03EB&PID_2421&MI_00 +%ATMEL_CDC_ASF_COMPOSITE_EXAMPLE4%=DriverInstall.NT, USB\VID_03EB&PID_2424&MI_00 +%ATMEL_CDC_ASF_EXAMPLE2_COM1%=DriverInstall.NT, USB\VID_03EB&PID_2425&MI_00 +%ATMEL_CDC_ASF_EXAMPLE2_COM2%=DriverInstall.NT, USB\VID_03EB&PID_2425&MI_02 +%ATMEL_CDC_ASF_EXAMPLE3_COM1%=DriverInstall.NT, USB\VID_03EB&PID_2426&MI_00 +%ATMEL_CDC_ASF_EXAMPLE3_COM2%=DriverInstall.NT, USB\VID_03EB&PID_2426&MI_02 +%ATMEL_CDC_ASF_EXAMPLE3_COM3%=DriverInstall.NT, USB\VID_03EB&PID_2426&MI_04 +%ATMEL_CDC_ASF_EXAMPLE3_COM4%=DriverInstall.NT, USB\VID_03EB&PID_2426&MI_06 +%ATMEL_CDC_ASF_EXAMPLE3_COM5%=DriverInstall.NT, USB\VID_03EB&PID_2426&MI_08 +%ATMEL_CDC_ASF_EXAMPLE3_COM6%=DriverInstall.NT, USB\VID_03EB&PID_2426&MI_0A +%ATMEL_CDC_ASF_EXAMPLE3_COM7%=DriverInstall.NT, USB\VID_03EB&PID_2426&MI_0C + +;---------------------------------------------------------- +; Windows 2000, XP, Vista, Windows 7, Windows 8 - 32bit +;---------------------------------------------------------- +[Reader_Install.NTx86] + + +[DestinationDirs] +DefaultDestDir=12 +DriverInstall.NT.Copy=12 + +[DriverInstall.NT] +include=mdmcpq.inf +CopyFiles=DriverInstall.NT.Copy +AddReg=DriverInstall.NT.AddReg + +[DriverInstall.NT.Copy] +usbser.sys + +[DriverInstall.NT.AddReg] +HKR,,DevLoader,,*ntkern +HKR,,NTMPDriver,,usbser.sys +HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider" + +[DriverInstall.NT.Services] +AddService = usbser, 0x00000002, DriverService.NT + +[DriverService.NT] +DisplayName = %Serial.SvcDesc% +ServiceType = 1 ; SERVICE_KERNEL_DRIVER +StartType = 3 ; SERVICE_DEMAND_START +ErrorControl = 1 ; SERVICE_ERROR_NORMAL +ServiceBinary = %12%\usbser.sys +LoadOrderGroup = Base + +;---------------------------------------------------------- +; Windows XP, Vista, Windows 7, Windows 8 - 64bit +;---------------------------------------------------------- + +[DriverInstall.NTamd64] +include=mdmcpq.inf +CopyFiles=DriverCopyFiles.NTamd64 +AddReg=DriverInstall.NTamd64.AddReg + +[DriverCopyFiles.NTamd64] +usbser.sys,,,0x20 + +[DriverInstall.NTamd64.AddReg] +HKR,,DevLoader,,*ntkern +HKR,,NTMPDriver,,usbser.sys +HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider" + +[DriverInstall.NTamd64.Services] +AddService=usbser, 0x00000002, DriverService.NTamd64 + +[DriverService.NTamd64] +DisplayName=%Serial.SvcDesc% +ServiceType=1 +StartType=3 +ErrorControl=1 +ServiceBinary=%12%\usbser.sys + +;---------------------------------------------------------- +; String +;---------------------------------------------------------- + +[Strings] +Manufacturer = "Inertial Sense, Inc." +ATMEL_CDC_XPLAINED = "XPLAINED Virtual Com Port" +ATMEL_CDC_USB_ZIGBIT_Sub = "ZigBit SubGHz USBstick Com Port" +ATMEL_CDC_USB_ZIGBIT_2_4 = "ZigBit 2.4GHz USBstick Com Port" +ATMEL_CDC_SFW_EXAMPLE = "Communication Device Class SFW example" +ATMEL_CDC_EVK1XXX = "EVK1XXX Virtual Com Port" +ATMEL_CDC_ASF_EXAMPLE = "Communication Device Class - Inertial Sense" +ATMEL_CDC_ASF_COMPOSITE_EXAMPLE2 = "Communication Device Class ASF composite example 2" +ATMEL_CDC_ASF_COMPOSITE_EXAMPLE4 = "Communication Device Class ASF composite example 4" +ATMEL_CDC_ASF_EXAMPLE2_COM1 = "Communication Device Class ASF example2, COM1" +ATMEL_CDC_ASF_EXAMPLE2_COM2 = "Communication Device Class ASF example2, COM2" +ATMEL_CDC_ASF_EXAMPLE3_COM1 = "Communication Device Class ASF example3, COM1" +ATMEL_CDC_ASF_EXAMPLE3_COM2 = "Communication Device Class ASF example3, COM2" +ATMEL_CDC_ASF_EXAMPLE3_COM3 = "Communication Device Class ASF example3, COM3" +ATMEL_CDC_ASF_EXAMPLE3_COM4 = "Communication Device Class ASF example3, COM4" +ATMEL_CDC_ASF_EXAMPLE3_COM5 = "Communication Device Class ASF example3, COM5" +ATMEL_CDC_ASF_EXAMPLE3_COM6 = "Communication Device Class ASF example3, COM6" +ATMEL_CDC_ASF_EXAMPLE3_COM7 = "Communication Device Class ASF example3, COM7" + +Serial.SvcDesc = "USB Serial emulation driver" + diff --git a/EVB-2/IS_EVB-2/src/ISLogFileFatFs.cpp b/EVB-2/IS_EVB-2/src/ISLogFileFatFs.cpp new file mode 100644 index 000000000..4ad9387bb --- /dev/null +++ b/EVB-2/IS_EVB-2/src/ISLogFileFatFs.cpp @@ -0,0 +1,235 @@ +/* +MIT LICENSE + +Copyright 2014-2019 Inertial Sense, Inc. - http://inertialsense.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions : + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +#include "d_time.h" + +#include "ISLogFileFatFs.h" +#include "ISConstants.h" + +cISLogFileFatFs::cISLogFileFatFs() : m_file{}, m_opened(false), m_lastSync(0) +{ +} + +cISLogFileFatFs::cISLogFileFatFs(const std::string& filePath, const char* mode) : cISLogFileFatFs(filePath.c_str(), mode) +{ + +} + +cISLogFileFatFs::cISLogFileFatFs(const char* filePath, const char* mode) : cISLogFileFatFs() +{ + open(filePath, mode); +} + +cISLogFileFatFs::~cISLogFileFatFs() +{ + close(); +} + +bool cISLogFileFatFs::open(const char* filePath, const char* mode) +{ + CONST_EXPRESSION std::size_t MAX_MODE_LEN = 3; + CONST_EXPRESSION char DRIVE[] = "0:"; + BYTE flags = 0x00; + bool append = false; + char fullFilePath[256]; + strncpy(fullFilePath, DRIVE, sizeof(fullFilePath)); + strncat(fullFilePath, filePath, _MIN(strlen(fullFilePath), sizeof(fullFilePath))); + + if (strncmp(mode, "r", MAX_MODE_LEN) == 0) + { + flags = FA_READ; + } + else if (strncmp(mode, "r+", MAX_MODE_LEN) == 0) + { + flags = FA_READ | FA_WRITE; + } + else if (strncmp(mode, "w", MAX_MODE_LEN) == 0 || + strncmp(mode, "wb", MAX_MODE_LEN) == 0) + { + flags = FA_CREATE_ALWAYS | FA_WRITE; + } + else if (strncmp(mode, "w+", MAX_MODE_LEN) == 0 || + (strncmp(mode, "wb+", MAX_MODE_LEN) == 0)) + { + flags = FA_CREATE_ALWAYS | FA_WRITE | FA_READ; + } + else if (strncmp(mode, "a", MAX_MODE_LEN) == 0) + { + // FatFs 0.09 does not support append mode. + // If we upgrade, we can use instead of setting n append flag and seeking. + //flags = FA_OPEN_APPEND | FA_WRITE; + + flags = FA_WRITE; + append = true; + } + else if (strncmp(mode, "a+", MAX_MODE_LEN) == 0) + { + // FatFs 0.09 does not support append mode. + // If we upgrade, we can use instead of setting n append flag and seeking. + //flags = FA_OPEN_APPEND | FA_WRITE | FA_READ; + + flags = FA_WRITE | FA_READ; + append = true; + } + else if (strncmp(mode, "wx", MAX_MODE_LEN) == 0) + { + flags = FA_CREATE_NEW | FA_WRITE; + } + else if (strncmp(mode, "w+x", MAX_MODE_LEN) == 0) + { + flags = FA_CREATE_NEW | FA_WRITE | FA_READ; + } + else + { + while (1) {} // not supported, fix this + } + + FRESULT result = f_open(&m_file, filePath, flags); + + if (result != FR_OK) + { + return false; + } + + if (append) + { + /* Move to end of the file to append data */ + result = f_lseek(&m_file, f_size(&m_file)); + if (result != FR_OK) + { + close(); + return false; + } + } + + m_opened = true; + m_lastSync = time_msec(); + return true; +} + +bool cISLogFileFatFs::close() +{ + if (m_opened) + { + FRESULT result = f_close(&m_file); + if (result != FR_OK) + { + return false; + } + m_opened = false; + } + return true; +} + +bool cISLogFileFatFs::flush() +{ + bool result = (f_sync(&m_file) == FR_OK); + if (result) + { + m_lastSync = time_msec(); + } + return result; +} + +bool cISLogFileFatFs::good() +{ + return (f_error(&m_file) == FR_OK); +} + +bool cISLogFileFatFs::isOpened() +{ + return m_opened; +} + +int cISLogFileFatFs::putch(char ch) +{ + if (f_putc(ch, &m_file) == 1) + { + return static_cast(ch); + } + return EOF; +} + +int cISLogFileFatFs::puts(const char* str) +{ + return f_puts(str, &m_file); +} + +std::size_t cISLogFileFatFs::write(const void* bytes, std::size_t len) +{ + std::size_t bytes_written = 0; + f_write(&m_file, bytes, len, &bytes_written); + + // Indicate write to disk + extern int g_indicateFsWriteMs; + g_indicateFsWriteMs = 50; + + if (time_msec() - m_lastSync > SYNC_FREQ_MS) + { + flush(); + } + + + return bytes_written; +} + +int cISLogFileFatFs::lprintf(const char* format, ...) +{ + int result; + va_list args; + va_start(args, format); + result = vprintf(format, args); + va_end(args); + return result; +} + +int cISLogFileFatFs::vprintf(const char* format, va_list args) +{ + return f_vprintf(&m_file, format, args); +} + +int cISLogFileFatFs::getch() +{ + char buffer[1]; + CONST_EXPRESSION UINT bytesToRead = sizeof(buffer); + UINT bytesRead; + + if (f_read(&m_file, buffer, bytesToRead, &bytesRead) == FR_OK && bytesRead == bytesToRead) + { + return static_cast(buffer[0]); + } + return EOF; +} + +std::size_t cISLogFileFatFs::read(void* bytes, std::size_t len) +{ + std::size_t bytes_read = 0; + f_read(&m_file, bytes, len, &bytes_read); + return bytes_read; +} + +int cISLogFileFatFs::seek(long int offset, int origin) +{ + return f_lseek(&m_file, offset); +} + +long int cISLogFileFatFs::tell() +{ + return f_tell(&m_file); +} + +int cISLogFileFatFs::eof() +{ + return f_eof(&m_file); +} + + diff --git a/EVB-2/IS_EVB-2/src/ISLogFileFatFs.h b/EVB-2/IS_EVB-2/src/ISLogFileFatFs.h new file mode 100644 index 000000000..9109fdeb8 --- /dev/null +++ b/EVB-2/IS_EVB-2/src/ISLogFileFatFs.h @@ -0,0 +1,54 @@ +/* +MIT LICENSE + +Copyright 2014-2019 Inertial Sense, Inc. - http://inertialsense.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions : + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +#ifndef IS_FAT_FS_LOG_FILE_H_ +#define IS_FAT_FS_LOG_FILE_H_ + +#include "ISLogFileBase.h" +#include "ff.h" +#include + +class cISLogFileFatFs : public cISLogFileBase +{ +public: + cISLogFileFatFs(); + cISLogFileFatFs(const std::string& filePath, const char* mode); + cISLogFileFatFs(const char* filePath, const char* mode); + ~cISLogFileFatFs(); + + bool open(const char* filePath, const char* mode) OVERRIDE; + bool close() OVERRIDE; + bool flush() OVERRIDE; + bool good() OVERRIDE; + bool isOpened() OVERRIDE; + + int putch(char ch) OVERRIDE; + int puts(const char* str) OVERRIDE; + std::size_t write(const void* bytes, std::size_t len) OVERRIDE; + int lprintf(const char* format, ...) OVERRIDE; + int vprintf(const char* format, va_list args) OVERRIDE; + + int getch() OVERRIDE; + std::size_t read(void* bytes, std::size_t len) OVERRIDE; + int seek(long int offset, int origin) OVERRIDE; + long int tell() OVERRIDE; + int eof() OVERRIDE; + +private: + FIL m_file; + bool m_opened; + std::uint32_t m_lastSync; + CONST_EXPRESSION std::uint32_t SYNC_FREQ_MS = 1000; // sync every second +}; + + +#endif //IS_FAT_FS_LOG_FILE_H_ diff --git a/EVB-2/IS_EVB-2/src/asf.h b/EVB-2/IS_EVB-2/src/asf.h new file mode 100644 index 000000000..40bca26a5 --- /dev/null +++ b/EVB-2/IS_EVB-2/src/asf.h @@ -0,0 +1,201 @@ +/** + * \file + * + * \brief Autogenerated API include file for the Atmel Software Framework (ASF) + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef ASF_H +#define ASF_H + +/* + * This file includes all API header files for the selected drivers from ASF. + * Note: There might be duplicate includes required by more than one driver. + * + * The file is automatically generated and will be re-written when + * running the ASF driver selector tool. Any changes will be discarded. + */ + +// From module: AFEC - Analog-Front-End Controller +#include + +// From module: CAN - Control Area Network Controller +#include + +// From module: Common SAM compiler driver +#include +#include + +// From module: Delay routines +#include + +// From module: EEFC - Enhanced Embedded Flash Controller +#include + +// From module: FatFS file system +#include +#include +#include +#include + +// From module: Flash - SAM Flash Service API +#include + +// From module: FreeRTOS mini Real-Time Kernel +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// From module: GPIO - General purpose Input/Output +#include + +// From module: Generic board support +#include "ISBoards.h" + +// From module: High Speed Multimedia Card Interface +#include + +// From module: IOPORT - General purpose I/O service +#include + +// From module: Interrupt management - SAM implementation +#include + +// From module: MPU - Memory Protect Unit +#include + +// From module: Memory Control Access Interface +#include + +// From module: PIO - Parallel Input/Output Controller +#include + +// From module: PMC - Power Management Controller +#include +#include + +// From module: Part identification macros +#include + +// From module: RTC - Real Time Clock +#include + +// From module: RTT - Real Time Timer +#include + +// From module: SAM FPU driver +#include + +// From module: SAME70 XPLD LED support enabled +#include + +// From module: SD/MMC Memory Control Access - Enable +#include + +// From module: SD/MMC stack on Multimedia Card interface +#include + +// From module: SPI - SAM Implementation +#include +#include + +// From module: SPI - SAM implementation +#include +#include + +// From module: SPI - Serial Peripheral Interface +#include + +// From module: Sleep manager - SAM implementation +#include +#include + +// From module: Standard serial I/O (stdio) - SAM implementation +#include + +// From module: Supported ports of FatFS +#include + +// From module: System Clock Control - SAME70 implementation +#include + +// From module: TC - Timer Counter +#include + +// From module: TWI - Two-wire Interface High Speed +#include + +// From module: UART - Univ. Async Rec/Trans +#include + +// From module: USART - Serial interface - SAM implementation for devices with both UART and USART +#include + +// From module: USART - Univ. Syn Async Rec/Trans +#include + +// From module: USB CDC Protocol +#include + +// From module: USB Device CDC (Single Interface Device) +#include + +// From module: USB Device Stack Core (Common API) +#include +#include + +// From module: WDT - Watchdog Timer +#include + +// From module: XDMAC - XDMA Controller +#include + +// From module: pio_handler support enabled +#include + +#endif // ASF_H diff --git a/EVB-2/IS_EVB-2/src/communications.cpp b/EVB-2/IS_EVB-2/src/communications.cpp new file mode 100644 index 000000000..53fa7d449 --- /dev/null +++ b/EVB-2/IS_EVB-2/src/communications.cpp @@ -0,0 +1,1127 @@ +/* +MIT LICENSE + +Copyright 2014-2019 Inertial Sense, Inc. - http://inertialsense.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions : + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +#include +#include "CAN_comm.h" +#include "CAN.h" +#include "d_flash.h" +#include "bootloaderApp.h" +#include "../../../src/convert_ins.h" +#include "../../../src/filters.h" +#include "../../../src/ISEarth.h" +#include "../../../src/ISLogger.h" +#include "../../../src/ISUtilities.h" +#include "../drivers/d_quadEnc.h" +#include "../src/protocol_nmea.h" +#include "ISLogFileFatFs.h" +#include "xbee.h" +#include "wifi.h" +#include "sd_card_logger.h" +#include "user_interface.h" +#include "wheel_encoder.h" +#include "communications.h" + +typedef struct +{ + // Comm instances + is_comm_instance_t comm; + + // Comm instance data buffer + uint8_t comm_buffer[PKT_BUF_SIZE]; + +} comm_rx_port_t; + + +#define COM_RX_PORT_COUNT (EVB2_PORT_COUNT-1) // exclude CAN port +comm_rx_port_t g_comRxPort[COM_RX_PORT_COUNT] = {}; + +is_comm_instance_t g_commTx = {}; + +StreamBufferHandle_t g_xStreamBufferUINS; +StreamBufferHandle_t g_xStreamBufferWiFiRx; +StreamBufferHandle_t g_xStreamBufferWiFiTx; +static uint8_t s_xStreamBufferUINS_buf[ STREAM_BUFFER_SIZE ] __attribute__((aligned(4))); +static uint8_t s_xStreamBufferWiFiRx_buf[ STREAM_BUFFER_SIZE ] __attribute__((aligned(4))); +static uint8_t s_xStreamBufferWiFiTx_buf[ STREAM_BUFFER_SIZE ] __attribute__((aligned(4))); +static StaticStreamBuffer_t s_xStreamBufferUINS_struct; +static StaticStreamBuffer_t s_xStreamBufferWiFiRx_struct; +static StaticStreamBuffer_t s_xStreamBufferWiFiTx_struct; + +static pfnHandleUinsData s_pfnHandleUinsData = NULLPTR; +static pfnHandleHostData s_pfnHandleHostData = NULLPTR; +static pfnHandleBroadcst s_pfnHandleBroadcst = NULLPTR; +static pfnHandleDid2Ermc s_pfnHandleDid2Ermc = NULLPTR; + + +int comWrite(int serialNum, const unsigned char *buf, int size, uint32_t ledPin ) +{ + int len; + if (serialNum == EVB2_PORT_UINS1 && g_flashCfg->cbOptions&EVB2_CB_OPTIONS_SPI_ENABLE) + { + len = spiTouINS_serWrite(buf, size); + } + else + { + len = serWrite(serialNum, buf, size); + } + + if(len) + { + LED_ON(ledPin); + } + return len; +} + +int comRead(int serialNum, unsigned char *buf, int bufSize, uint32_t ledPin) +{ + int len = 0; + + if (serialNum == EVB2_PORT_UINS1 && g_flashCfg->cbOptions&EVB2_CB_OPTIONS_SPI_ENABLE) + { + len = spiTouINS_serRead(buf, bufSize); + } + else + { +#if 0 // Wait for end of data. Check Rx buffer has data and hasn't change over 1ms. + static int usedLast[EVB2_PORT_COUNT] = {0}; + int used = serRxUsed(serialNum); + if(used!=0 && used==usedLast[serialNum]) + { // Data in Rx buffer and amount hasn't changed. + len = serRead(serialNum, buf, bufSize, 0); + } + usedLast[serialNum] = used; +#else + // Normal read + len = serRead(serialNum, buf, bufSize); +#endif + } + + if(len) + { + LED_ON(ledPin); + } + return len; +} + +void callback_cdc_set_config(uint8_t port, usb_cdc_line_coding_t * cfg) +{ + UNUSED(port); +#if 0 + uint32_t stopbits, parity, databits; +// uint32_t imr; + + switch (cfg->bCharFormat) + { + case CDC_STOP_BITS_2: + stopbits = US_MR_NBSTOP_2_BIT; + break; + case CDC_STOP_BITS_1_5: + stopbits = US_MR_NBSTOP_1_5_BIT; + break; + case CDC_STOP_BITS_1: + default: + // Default stop bit = 1 stop bit + stopbits = US_MR_NBSTOP_1_BIT; + break; + } + + switch (cfg->bParityType) + { + case CDC_PAR_EVEN: + parity = US_MR_PAR_EVEN; + break; + case CDC_PAR_ODD: + parity = US_MR_PAR_ODD; + break; + case CDC_PAR_MARK: + parity = US_MR_PAR_MARK; + break; + case CDC_PAR_SPACE: + parity = US_MR_PAR_SPACE; + break; + default: + case CDC_PAR_NONE: + parity = US_MR_PAR_NO; + break; + } + + switch(cfg->bDataBits) + { + case 5: + case 6: + case 7: + databits = cfg->bDataBits - 5; + break; + default: + case 8: + databits = US_MR_CHRL_8_BIT; + break; + } + + // Options for USART. This gets called when USB is first connected AND each time the USB CDC serial port is opened by the host. + // sam_usart_opt_t usart_options; + // usart_options.baudrate = LE32_TO_CPU(cfg->dwDTERate); + // usart_options.char_length = databits; + // usart_options.parity_type = parity; + // usart_options.stop_bits = stopbits; + // usart_options.channel_mode = US_MR_CHMODE_NORMAL; +#endif + + uint32_t baudrate = LE32_TO_CPU(cfg->dwDTERate); + if (comManagerValidateBaudRate(baudrate)==0) + { + // Set baudrate based on USB CDC baudrate + if (g_flashCfg->cbf[EVB2_PORT_USB] & (1<cbf[EVB2_PORT_USB] & (1<cbOptions&EVB2_CB_OPTIONS_SPI_ENABLE)) + { + serSyncBaudRate(EVB2_PORT_UINS1, &baudrate); + } + } + + if (comManagerValidateBaudRate(baudrate)==0 || baudrate==9600) + { + // if(g_flashCfg->cbf[EVB2_PORT_USB] & (1<cbf[EVB2_PORT_USB] & (1<cbf[EVB2_PORT_USB] & (1<cbf[EVB2_PORT_USB] & (1<cbf[EVB2_PORT_USB] & (1<cbf[EVB2_PORT_USB] & (1<uinsComPort, buf, len, LED_INS_TXD_PIN); +} + +void uINS_stream_enable_std(void) +{ + int len; + uint8_t buf[64]; + + len = is_comm_get_data_to_buf(buf, sizeof(buf), &g_commTx, DID_INS_2, 0, 0, 10); // 20 x 4ms = 40ms + comWrite(g_flashCfg->uinsComPort, buf, len, LED_INS_TXD_PIN); + + len = is_comm_get_data_to_buf(buf, sizeof(buf), &g_commTx, DID_DEV_INFO, 0, 0, 500); // 500ms + comWrite(g_flashCfg->uinsComPort, buf, len, LED_INS_TXD_PIN); +} + +void uINS_stream_enable_PPD(void) +{ + rmc_t rmc; + rmc.bits = RMC_PRESET_PPD_GROUND_VEHICLE; + rmc.options = 0; + + uint8_t buf[64]; + int len = is_comm_data_to_buf(buf, sizeof(buf), &g_commTx, DID_RMC, sizeof(rmc_t), 0, (void*)&rmc); + + comWrite(g_flashCfg->uinsComPort, buf, len, LED_INS_TXD_PIN); + +// len = is_comm_get_data(buf, sizeof(buf) &comm, DID_INS_2, 0, 0, 1); // 1 x 4ms = 4ms +// comWrite(EVB2_PORT_UINS0, buf, len, LED_INS_TXD_PIN); +} + + +void time_sync_evb_from_IMX(uint32_t week, double timeOfWeek) +{ + g_towOffset = timeOfWeek - time_seclf(); + + g_status.week = week; + g_statusToWlocal = false; + g_status.timeOfWeekMs = (uint32_t)round(timeOfWeek*1000.0); + g_status.towOffset = g_towOffset; +} + + +void handle_data_from_IMX(p_data_hdr_t &dataHdr, uint8_t *data) +{ + uDatasets d = {0}; + + if( copyDataPToStructP2(&d, &dataHdr, data, sizeof(uDatasets)) ) + { // Invalid + return; + } + + // Save uINS data to global variables + switch(dataHdr.id) + { + case DID_DEV_INFO: + copyDataPToStructP2(&g_uins.uInsInfo, &dataHdr, data, sizeof(dev_info_t)); + break; + + case DID_INS_1: + if(dataHdr.size+dataHdr.offset > sizeof(ins_1_t)){ /* Invalid */ return; } + time_sync_evb_from_IMX(d.ins1.week, d.ins1.timeOfWeek); + g_uins.ins1 = d.ins1; + convertIns1ToIns2(&d.ins1, &g_uins.ins2); + g_insUpdateTimeMs = g_comm_time_ms; + break; + + case DID_INS_2: + if(dataHdr.size+dataHdr.offset > sizeof(ins_2_t)){ /* Invalid */ return; } + time_sync_evb_from_IMX(d.ins2.week, d.ins2.timeOfWeek); + g_uins.ins2 = d.ins2; + if(g_uins.refLlaValid) + { + convertIns2ToIns1(&d.ins2, &g_uins.ins1, g_uins.flashCfg.refLla); + } + else + { + convertIns2ToIns1(&d.ins2, &g_uins.ins1); + } + g_insUpdateTimeMs = g_comm_time_ms; + break; + + case DID_INS_3: + if(dataHdr.size+dataHdr.offset > sizeof(ins_3_t)){ /* Invalid */ return; } + time_sync_evb_from_IMX(d.ins3.week, d.ins3.timeOfWeek); + break; + + case DID_INS_4: + if(dataHdr.size+dataHdr.offset > sizeof(ins_4_t)){ /* Invalid */ return; } + time_sync_evb_from_IMX(d.ins4.week, d.ins4.timeOfWeek); + break; + + case DID_INL2_STATES: + if(dataHdr.size+dataHdr.offset > sizeof(inl2_states_t)){ /* Invalid */ return; } + g_uins.inl2States = d.inl2States; + break; + + case DID_PIMU: + if(dataHdr.size+dataHdr.offset > sizeof(pimu_t)){ /* Invalid */ return; } + g_uins.pImu = d.pImu; + preintegratedImuToIMU(&(g_imu), &(g_uins.pImu)); + sub_Vec3_Vec3(g_imu.I.pqr, g_imu.I.pqr, g_uins.inl2States.biasPqr); // Subtract EKF bias estimates + sub_Vec3_Vec3(g_imu.I.acc, g_imu.I.acc, g_uins.inl2States.biasAcc); + g_imuUpdateTimeMs = g_comm_time_ms; + break; + + case DID_FLASH_CONFIG: // uINS + if(dataHdr.size+dataHdr.offset > sizeof(nvm_flash_cfg_t)){ /* Invalid */ return; } + g_uins.flashCfg = d.flashCfg; + g_uins.refLlaValid = (bool)llaDegValid(g_uins.flashCfg.refLla); + break; + } + + // Pass to callback + if(s_pfnHandleUinsData) + { + s_pfnHandleUinsData(dataHdr, d); + } +} + + +// Convert DID to message out control mask +uint64_t evbDidToErmcBit(uint32_t dataId) +{ + switch (dataId) + { + case DID_EVB_DEV_INFO: return ERMC_BITS_DEV_INFO; + case DID_EVB_FLASH_CFG: return ERMC_BITS_FLASH_CFG; + case DID_EVB_STATUS: return ERMC_BITS_STATUS; + case DID_EVB_DEBUG_ARRAY: return ERMC_BITS_DEBUG_ARRAY; + case DID_WHEEL_ENCODER: return ERMC_BITS_WHEEL_ENCODER; + default: break; + } + + if (s_pfnHandleDid2Ermc) + { // Pass to callback + return s_pfnHandleDid2Ermc(dataId); + } + + return 0; +} + + +void broadcastRmcMessage(is_comm_instance_t *comm, uint32_t did, uint32_t size, void* data, uint32_t &time_ms, uint32_t didSendNow) +{ + if ((g_ermc.periodMultiple[did] && + g_ermc.bits & evbDidToErmcBit(did) && + (g_comm_time_ms-time_ms) > g_ermc.periodMultiple[did]) || + did == didSendNow) + { + time_ms = g_comm_time_ms; + is_comm_data(serWrite, EVB2_PORT_USB, comm, did, size, 0, data); + } +} + + +void step_broadcast_data(is_comm_instance_t *comm, uint32_t didSendNow) +{ + static uint32_t time_ms_dev_info; + static uint32_t time_ms_flash_cfg; + static uint32_t time_ms_rtos; + static uint32_t time_ms_status; + static uint32_t time_ms_debug; + + // Broadcast messages + broadcastRmcMessage(comm, DID_EVB_DEV_INFO, sizeof(dev_info_t), (void*)&g_evbDevInfo, time_ms_dev_info, didSendNow); + broadcastRmcMessage(comm, DID_EVB_FLASH_CFG, sizeof(evb_flash_cfg_t), (void*)g_flashCfg, time_ms_flash_cfg, didSendNow); + broadcastRmcMessage(comm, DID_EVB_RTOS_INFO, sizeof(evb_rtos_info_t), (void*)&g_rtos, time_ms_rtos, didSendNow); + broadcastRmcMessage(comm, DID_EVB_STATUS, sizeof(evb_status_t), (void*)&g_status, time_ms_status, didSendNow); + broadcastRmcMessage(comm, DID_EVB_DEBUG_ARRAY, sizeof(debug_array_t), (void*)&g_debug, time_ms_debug, didSendNow); + + switch (didSendNow) + { + case DID_EVB_RTOS_INFO: g_enRtosStats = true; break; + } + + if (s_pfnHandleBroadcst) + { // Pass to callback + s_pfnHandleBroadcst(comm, didSendNow); + } +} + + +void log_IMX_data(cISLogger &logger, is_comm_instance_t &comm) +{ + is_evb_log_stream stm = {}; + uint8_t data[MAX_DATASET_SIZE]; + p_data_hdr_t dataHdr = {}; + + while (xStreamBufferReceive(g_xStreamBufferUINS, (void*)&stm, sizeof(is_evb_log_stream), 0) == sizeof(is_evb_log_stream)) + { + if (stm.marker==DATA_CHUNK_MARKER) + { + switch (stm.ptype) + { + case _PTYPE_INERTIAL_SENSE_DATA: + if (xStreamBufferReceive(g_xStreamBufferUINS, (void*)&dataHdr, sizeof(p_data_hdr_t), 0) == sizeof(p_data_hdr_t)) + { + if (dataHdr.id < DID_COUNT && dataHdr.size < MAX_DATASET_SIZE) + { + if (xStreamBufferReceive(g_xStreamBufferUINS, (void*)data, dataHdr.size, 0) == dataHdr.size) + { + // Log Inertial Sense Binary data to SD Card + if(g_loggerEnabled) + { + logger.LogData(0, &dataHdr, data); + } + } + } + } + break; + + case _PTYPE_NMEA: + break; + + case _PTYPE_UBLOX: +#if UBLOX_LOG_ENABLE + if (xStreamBufferReceive(g_xStreamBufferUINS, (void*)&data, stm.size, 0) == stm.size) + { +extern void log_ublox_raw_to_SD(cISLogger& logger, uint8_t *dataPtr, uint32_t dataSize); + log_ublox_raw_to_SD(logger, data, stm.size); + } +#endif + break; + } + } + } +} + + +void update_flash_cfg(evb_flash_cfg_t &newCfg) +{ + if(error_check_evb_flash_cfg(&newCfg)) + { + return; + } + + // Data is identical, no changes. + if( !memcmp(&newCfg, g_flashCfg, sizeof(evb_flash_cfg_t)) ) + { + return; + } + + bool initCbPreset = false; + bool initIOconfig = false; + bool reinitXBee = false; + bool reinitWiFi = false; + bool reinitCAN = false; + bool reinitWheelEncoder = false; + + // Detect changes + if (newCfg.cbPreset != g_flashCfg->cbPreset || + newCfg.uinsComPort != g_flashCfg->uinsComPort) + { + initCbPreset = true; + initIOconfig = true; + } + if (newCfg.radioPID != g_flashCfg->radioPID || + newCfg.radioNID != g_flashCfg->radioNID || + newCfg.radioPowerLevel != g_flashCfg->radioPowerLevel) + { + reinitXBee = true; + } + if (EVB_CFG_BITS_IDX_WIFI(newCfg.bits) != EVB_CFG_BITS_IDX_WIFI(g_flashCfg->bits) || + EVB_CFG_BITS_IDX_SERVER(newCfg.bits) != EVB_CFG_BITS_IDX_SERVER(g_flashCfg->bits)) + { // WiFi or TCP server preset changed + reinitWiFi = true; + } + int i = EVB_CFG_BITS_IDX_WIFI(newCfg.bits); + if (strncmp((const char*)(newCfg.wifi[i].ssid), (const char*)(g_flashCfg->wifi[i].ssid), WIFI_SSID_PSK_SIZE)!=0 || + strncmp((const char*)(newCfg.wifi[i].psk), (const char*)(g_flashCfg->wifi[i].psk), WIFI_SSID_PSK_SIZE)!=0 || + newCfg.server[i].ipAddr.u32 != g_flashCfg->server[i].ipAddr.u32 || + newCfg.server[i].port != g_flashCfg->server[i].port) + { // WiFi or TCP settings changed + reinitWiFi = true; + } + i = EVB_CFG_BITS_IDX_SERVER(newCfg.bits); + if (newCfg.server[i].ipAddr.u32 != g_flashCfg->server[i].ipAddr.u32 || + newCfg.server[i].port != g_flashCfg->server[i].port) + { // TCP settings changed + reinitWiFi = true; + } + if ((newCfg.cbOptions&EVB2_CB_OPTIONS_XBEE_ENABLE) != (g_flashCfg->cbOptions&EVB2_CB_OPTIONS_XBEE_ENABLE) || + (newCfg.cbOptions&EVB2_CB_OPTIONS_WIFI_ENABLE) != (g_flashCfg->cbOptions&EVB2_CB_OPTIONS_WIFI_ENABLE) || + (newCfg.h3sp330BaudRate != g_flashCfg->h3sp330BaudRate) || + (newCfg.h4xRadioBaudRate != g_flashCfg->h4xRadioBaudRate) || + (newCfg.h8gpioBaudRate != g_flashCfg->h8gpioBaudRate) ) + { + initIOconfig = true; + } + if (g_flashCfg->CANbaud_kbps != newCfg.CANbaud_kbps) + { + g_flashCfg->CANbaud_kbps = newCfg.CANbaud_kbps; + reinitCAN = true; + } + if (g_flashCfg->can_receive_address != newCfg.can_receive_address) + { + g_flashCfg->can_receive_address = newCfg.can_receive_address; + reinitCAN = true; + } + if (g_flashCfg->wheelCfgBits != newCfg.wheelCfgBits) + { + reinitWheelEncoder = true; + initIOconfig = true; + } + + // Copy data from message to working location + *g_flashCfg = newCfg; + + // Apply changes + if(initCbPreset) + { + com_bridge_apply_preset(g_flashCfg); + } + if(initIOconfig) + { // Update EVB IO config + board_IO_config(); + } + if(reinitXBee) + { + xbee_init(); + } + if(reinitWiFi) + { + wifi_reinit(); + } + if (reinitCAN) + { + CAN_init(g_flashCfg->CANbaud_kbps*1000, g_flashCfg->can_receive_address); + } + if (reinitWheelEncoder) + { + init_wheel_encoder(); + } + evbUiRefreshLedCfg(); + + // Enable flash write + nvr_flash_config_write_needed(); + nvr_flash_config_write_enable(); +} + + +void send_nmea_dev_info(int portNum) +{ + char a[NMEA_BUFFER_SIZE]; + int n = nmea_dev_info(a, sizeof(a), g_evbDevInfo); + serWrite(portNum, (unsigned char*)a, n); +} + + +void handle_data_from_host(is_comm_instance_t *comm, protocol_type_t ptype, uint32_t srcPort) +{ + uint8_t *dataPtr = comm->rxPkt.data.ptr + comm->rxPkt.dataHdr.offset; + static uint8_t manfUnlock = false; + + switch(ptype) + { + case _PTYPE_INERTIAL_SENSE_DATA: + switch(comm->rxPkt.dataHdr.id) + { // From host to EVB + case DID_EVB_STATUS: + is_comm_copy_to_struct(&g_status, comm, sizeof(evb_status_t)); + + switch (g_status.sysCommand) + { + case SYS_CMD_SOFTWARE_RESET: // Reset processor + soft_reset_backup_register(SYS_FAULT_STATUS_USER_RESET); + break; + + case SYS_CMD_MANF_UNLOCK: // Unlock process for chip erase + manfUnlock = true; + g_status.evbStatus |= EVB_STATUS_MANF_UNLOCKED; + break; + + case SYS_CMD_MANF_ENABLE_ROM_BOOTLOADER: // reboot into ROM bootloader mode + if(manfUnlock) + { + // Set "stay_in_bootloader" signature to require app firmware update following bootloader update. + write_bootloader_signature_stay_in_bootloader_mode(); + + BEGIN_CRITICAL_SECTION + flash_rom_bootloader(); + while(1); + END_CRITICAL_SECTION + } + break; + + case SYS_CMD_MANF_CHIP_ERASE: // chip erase and reboot + if(manfUnlock) + { + BEGIN_CRITICAL_SECTION + flash_erase_chip(); + while(1); + END_CRITICAL_SECTION + } + break; + } + g_status.sysCommand = 0; + break; + + case DID_EVB_FLASH_CFG: + evb_flash_cfg_t newCfg; + newCfg = *g_flashCfg; + is_comm_copy_to_struct(&newCfg, comm, sizeof(evb_flash_cfg_t)); + + update_flash_cfg(newCfg); + break; + + case DID_EVB_DEBUG_ARRAY: + is_comm_copy_to_struct(&g_debug, comm, sizeof(debug_array_t)); + break; + } + + // Disable uINS bootloader if host sends IS binary data + g_imxBootloaderEnableTimeMs = 0; + break; + + case _PTYPE_INERTIAL_SENSE_CMD: + switch(comm->rxPkt.flags&PKT_TYPE_MASK) + { + case PKT_TYPE_GET_DATA: + { + p_data_get_t *get = (p_data_get_t*)(comm->rxPkt.data.ptr); + + // Set ERMC broadcast control bits + setErmcBroadcastBits(comm, srcPort, evbDidToErmcBit(get->id)); + + // Send data now + step_broadcast_data(comm, get->id); + } + + // Disable uINS bootloader mode if host sends IS binary command + g_imxBootloaderEnableTimeMs = 0; + break; // PID_GET_DATA + + // case PKT_TYPE_SET_DATA: + // if(comm->rxPkt.dataHdr.id == DID_RMC) + // { + // g_ermc.bits = *((uint64_t*)(comm->dataPtr)); // RMC is not the same as ERMC (EVB RMC). We may need to translate this if necessary. + // } + // break; + + case PKT_TYPE_STOP_BROADCASTS_ALL_PORTS: + case PKT_TYPE_STOP_DID_BROADCAST: + case PKT_TYPE_STOP_BROADCASTS_CURRENT_PORT: + // Disable EVB broadcasts + g_ermc.bits = 0; + break; + } + break; + + case _PTYPE_NMEA: + { + switch (getNmeaMsgId(dataPtr, comm->rxPkt.dataHdr.size)) + { + case NMEA_MSG_ID_BLEN: // Enable bootloader (IMX) + g_imxBootloaderEnableTimeMs = g_comm_time_ms; + + // Disable EVB broadcasts + g_ermc.bits = 0; + break; + + case NMEA_MSG_ID_EBLE: // Enable bootloader (EVB) + // Disable uINS bootloader if host enables EVB bootloader + g_imxBootloaderEnableTimeMs = 0; + + enable_bootloader(PORT_SEL_USB); + break; + + case NMEA_MSG_ID_INFO: + send_nmea_dev_info(srcPort); + break; + + case NMEA_MSG_ID_NELB: // SAM bootloader assistant (SAM-BA) enable + if (comm->rxPkt.dataHdr.size == 22 && +// (pHandle == EVB2_PORT_USB) && + strncmp((const char*)(&(comm->rxBuf.start[6])), "!!SAM-BA!!", 6) == 0) + { // 16 character commands (i.e. "$NELB,!!SAM-BA!!\0*58\r\n") + enable_rom_bootloader(); + } + break; + + case NMEA_MSG_ID_STPB: + case NMEA_MSG_ID_STPC: + // Disable EVB communications + g_ermc.bits = 0; + break; + + default: + // Disable IMX bootloader if host sends larger NMEA sentence + g_imxBootloaderEnableTimeMs = 0; + break; + } + } + break; + } + + if (s_pfnHandleHostData) + { // Pass to callback + s_pfnHandleHostData(comm, ptype, srcPort); + } +} + + +// Set ERMC broadcast control bits +void setErmcBroadcastBits(is_comm_instance_t *comm, uint32_t srcPort, uint64_t bits) +{ + uint32_t bc_period_multiple = *((int32_t*)(comm->rxPkt.data.ptr)); + if(bc_period_multiple) + { // Enable message + g_ermc.bits |= bits; + } + else + { // Disable message + g_ermc.bits &= ~bits; + bc_period_multiple = 0; + } + if (comm->rxPkt.dataHdr.id < sizeof(g_ermc.periodMultiple)) + { + g_ermc.periodMultiple[comm->rxPkt.dataHdr.id] = bc_period_multiple; + } +} + + +#define CAN_COM_PORT 1 +#define CAN_HDR 0xFC; +#define CAN_FTR 0xFE; + +void sendRadio(uint8_t *data, int dataSize, bool sendXbee, bool sendXrad) +{ + if(g_flashCfg->portOptions == EVB2_PORT_OPTIONS_RADIO_RTK_FILTER) + { // Filter RTK Base Messages + protocol_type_t ptype; + + static is_comm_instance_t comm = {}; + static uint8_t buffer[PKT_BUF_SIZE]; + if (comm.rxBuf.start == NULL) + { // Init buffer + is_comm_init(&comm, buffer, sizeof(buffer)); + } + + for(uint8_t *ptr=data; dataSize>0; ) + { + // Number of bytes to copy + int n = _MIN(dataSize, is_comm_free(&comm)); + + // Copy data into buffer + memcpy(comm.rxBuf.tail, ptr, n); + comm.rxBuf.tail += n; + dataSize -= n; + ptr += n; + + while((ptype = is_comm_parse_timeout(&comm, g_comm_time_ms)) != _PTYPE_NONE) + { + // Parse Data + switch(ptype) + { + case _PTYPE_UBLOX: + case _PTYPE_RTCM3: + case _PTYPE_NMEA: + if(sendXbee){ comWrite(EVB2_PORT_XBEE, comm.rxPkt.data.ptr, comm.rxPkt.dataHdr.size, LED_XBEE_TXD_PIN); } + if(sendXrad){ comWrite(EVB2_PORT_XRADIO, comm.rxPkt.data.ptr, comm.rxPkt.dataHdr.size, 0); } + break; + } + } + } + } + else + { + if(sendXbee){ comWrite(EVB2_PORT_XBEE, data, dataSize, LED_XBEE_TXD_PIN); } + if(sendXrad){ comWrite(EVB2_PORT_XRADIO, data, dataSize, 0); } + } +} + + +// This function only forwards data after complete valid packets are received +void com_bridge_smart_forward(uint32_t srcPort, uint32_t ledPin) +{ + if(srcPort>=COM_RX_PORT_COUNT) + { + return; + } + + is_comm_instance_t &comm = g_comRxPort[srcPort].comm; + + // Get available size of comm buffer + int n = is_comm_free(&comm); + + if ((n = comRead(srcPort, comm.rxBuf.tail, n, ledPin)) > 0) + { + if (g_flashCfg->cbPreset == EVB2_CB_PRESET_USB_HUB_RS422) + { + com_bridge_forward(srcPort, comm.rxBuf.head, n); + return; + } + if (g_imxBootloaderEnableTimeMs) + { // When IMX bootloader is enabled forwarding is disabled below is_comm_parse(), so forward bootloader data here. + switch (srcPort) + { + case EVB2_PORT_USB: comWrite(EVB2_PORT_UINS0, comm.rxBuf.tail, n, LED_INS_TXD_PIN); break; + case EVB2_PORT_UINS0: comWrite(EVB2_PORT_USB, comm.rxBuf.tail, n, 0); break; + } + } + + // Update comm buffer tail pointer + comm.rxBuf.tail += n; + + // Search comm buffer for valid packets + protocol_type_t ptype; + while((ptype = is_comm_parse_timeout(&comm, g_comm_time_ms)) != _PTYPE_NONE) + { + switch(srcPort) + { + case EVB2_PORT_USB: + case EVB2_PORT_XBEE: + case EVB2_PORT_SP330: + handle_data_from_host(&comm, ptype, srcPort); + break; + } + + if (ptype!=_PTYPE_NONE && + ptype!=_PTYPE_PARSE_ERROR && + g_imxBootloaderEnableTimeMs==0) + { // Forward data + uint32_t pktSize = _MIN(comm.rxPkt.size, PKT_BUF_SIZE); + com_bridge_forward(srcPort, comm.rxBuf.head-pktSize, pktSize); + + // Send uINS data to Logging task + if (srcPort == g_flashCfg->uinsComPort && pktSize > 0) + { + is_evb_log_stream stm; + stm.marker = DATA_CHUNK_MARKER; + stm.ptype = ptype; + switch (ptype) + { + case _PTYPE_INERTIAL_SENSE_DATA: + if (comm.rxPkt.dataHdr.size > 0) + { + handle_data_from_IMX(comm.rxPkt.dataHdr, comm.rxPkt.data.ptr); + + stm.size = sizeof(p_data_hdr_t) + comm.rxPkt.dataHdr.size; + xStreamBufferSend(g_xStreamBufferUINS, (void*)&(stm), sizeof(is_evb_log_stream), 0); + xStreamBufferSend(g_xStreamBufferUINS, (void*)&(comm.rxPkt.dataHdr), sizeof(p_data_hdr_t), 0); + xStreamBufferSend(g_xStreamBufferUINS, (void*)(comm.rxPkt.data.ptr), comm.rxPkt.dataHdr.size, 0); + } + break; + case _PTYPE_UBLOX: +#if UBLOX_LOG_ENABLE + stm.size = pktSize; + xStreamBufferSend(g_xStreamBufferUINS, (void*)&(stm), sizeof(is_evb_log_stream), 0); + xStreamBufferSend(g_xStreamBufferUINS, (void*)(comm.pktPtr), pktSize, 0); +#endif + break; + } + } + + } + } + } +} + + +void com_bridge_smart_forward_xstream(uint32_t srcPort, StreamBufferHandle_t xStreamBuffer); +void com_bridge_smart_forward_xstream(uint32_t srcPort, StreamBufferHandle_t xStreamBuffer) +{ + if(srcPort>=COM_RX_PORT_COUNT) + { + return; + } + + is_comm_instance_t &comm = g_comRxPort[srcPort].comm; + + // Get available size of comm buffer + int n = is_comm_free(&comm); + + if ((n = xStreamBufferReceive(xStreamBuffer, comm.rxBuf.tail, n, 0)) > 0) + { + // Update comm buffer tail pointer + comm.rxBuf.tail += n; + + // Search comm buffer for valid packets + protocol_type_t ptype; + while ((ptype = is_comm_parse_timeout(&comm, g_comm_time_ms)) != _PTYPE_NONE) + { + if (srcPort == EVB2_PORT_USB) + { + handle_data_from_host(&comm, ptype, srcPort); + } + + if (ptype!=_PTYPE_NONE && + ptype!=_PTYPE_PARSE_ERROR && + g_imxBootloaderEnableTimeMs==0) + { // Forward data + uint32_t pktSize = _MIN(comm.rxPkt.size, PKT_BUF_SIZE); + com_bridge_forward(srcPort, comm.rxPkt.data.ptr, pktSize); + } + } + } +} + + +void com_bridge_forward(uint32_t srcPort, uint8_t *buf, int len) +{ + uint32_t dstCbf = g_flashCfg->cbf[srcPort]; + + if(dstCbf == 0 || len==0) // None + { + return; + } + + if(dstCbf & (1<uinsComPort==EVB2_PORT_SP330?LED_INS_TXD_PIN:0); + } + + if(dstCbf & (1<uinsComPort==EVB2_PORT_GPIO_H8?LED_INS_TXD_PIN:0); + } + +#if 0 // Disabled when forwarding data directly in wifi task + if(dstCbf & (1<uinsComPort==EVB2_PORT_SP330?LED_INS_RXD_PIN:0); +#endif + +#ifdef CONF_BOARD_SERIAL_GPIO_H8 // H8 Header GPIO TTL Rx ======================================================= + com_bridge_smart_forward(EVB2_PORT_GPIO_H8, g_flashCfg->uinsComPort==EVB2_PORT_GPIO_H8?LED_INS_RXD_PIN:0); +#endif + +#ifdef CONF_BOARD_SPI_ATWINC_WIFI // WiFi Rx ======================================================= + com_bridge_smart_forward_xstream(EVB2_PORT_WIFI, g_xStreamBufferWiFiRx); +#endif + +#ifdef CONF_BOARD_CAN1 + //uint8_t can_rx_message[CONF_MCAN_ELEMENT_DATA_SIZE]; + //uint32_t id; + //uint8_t lenCAN; + //is_can_message msg; + //msg.startByte = CAN_HDR; + //msg.endByte = CAN_FTR; + //if((lenCAN = mcan_receive_message(&id, can_rx_message)) > 0)// && --timeout > 0)) + //{ + //msg.address = id; + //msg.payload = *(is_can_payload*)can_rx_message; + //msg.dlc = lenCAN; + //com_bridge_forward(EVB2_PORT_CAN,(uint8_t*)&msg, sizeof(is_can_message)); + //} + /*Test CAN*/ + //static uint8_t tx_message_1[8] = { 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87}; + //mcan_send_message(0x100000A5, tx_message_1, CONF_MCAN_ELEMENT_DATA_SIZE); +#endif +} + + +void comunications_set_uins_data_callback( pfnHandleUinsData pfn ) +{ + s_pfnHandleUinsData = pfn; +} + + +void comunications_set_host_data_callback( pfnHandleHostData pfn ) +{ + s_pfnHandleHostData = pfn; +} + + +void communications_init(pfnHandleBroadcst pfnBroadcst, pfnHandleDid2Ermc pfnDid2Ermc) +{ + const size_t xTriggerLevel = 1; + + g_xStreamBufferUINS = xStreamBufferCreateStatic(STREAM_BUFFER_SIZE, + xTriggerLevel, + s_xStreamBufferUINS_buf, + &s_xStreamBufferUINS_struct); + g_xStreamBufferWiFiRx = xStreamBufferCreateStatic(STREAM_BUFFER_SIZE, + xTriggerLevel, + s_xStreamBufferWiFiRx_buf, + &s_xStreamBufferWiFiRx_struct); + g_xStreamBufferWiFiTx = xStreamBufferCreateStatic(STREAM_BUFFER_SIZE, + xTriggerLevel, + s_xStreamBufferWiFiTx_buf, + &s_xStreamBufferWiFiTx_struct); + + for(int i=0; i +#include "globals.h" +#include "spiTouINS.h" +#include "../../../src/ISLogger.h" +#include "../hw-libs/communications/CAN_comm.h" + + +extern is_comm_instance_t g_commTx; +extern bool g_usb_cdc_open; + +typedef void(*pfnHandleUinsData)(p_data_hdr_t &dataHdr, uDatasets &data); +typedef void(*pfnHandleHostData)(is_comm_instance_t *comm, protocol_type_t ptype, uint32_t srcPort); +typedef void(*pfnHandleBroadcst)(is_comm_instance_t *comm, uint32_t didSendNow); +typedef uint64_t(*pfnHandleDid2Ermc)(uint32_t dataId); + +int comWrite(int serialNum, const unsigned char *buf, int size, uint32_t ledPin ); +int comRead(int serialNum, unsigned char *buf, int size, uint32_t ledPin); +int comRxUsed(int serialNum); + +void callback_cdc_set_config(uint8_t port, usb_cdc_line_coding_t * cfg); +void callback_cdc_disable(void); +void callback_cdc_set_dtr(uint8_t port, bool b_enable); + +void uINS_stream_stop_all(void); +void uINS_stream_enable_std(void); +void uINS_stream_enable_PPD(void); + +void broadcastRmcMessage(is_comm_instance_t *comm, uint32_t did, uint32_t size, void* data, uint32_t &time_ms, uint32_t didSendNow); +void step_broadcast_data(is_comm_instance_t *comm, uint32_t didSendNow=0); +void log_IMX_data(cISLogger &logger, is_comm_instance_t &comm); +void setErmcBroadcastBits(is_comm_instance_t *comm, uint32_t srcPort, uint64_t bits); + +void com_bridge_smart_forward(uint32_t srcPort, uint32_t ledPin); +void com_bridge_forward(uint32_t srcPort, uint8_t *buf, int len); +void step_com_bridge(is_comm_instance_t &comm); +void comunications_set_uins_data_callback( pfnHandleUinsData pfn ); +void comunications_set_host_data_callback( pfnHandleHostData pfn ); +void communications_init( pfnHandleBroadcst pfnHandleBroadcst = NULLPTR, pfnHandleDid2Ermc pfnDid2Ermc = NULLPTR ); + +/*CAN Message*/ +typedef struct PACKED +{ + uint8_t startByte; + uint32_t address; + uint8_t dlc; //Data Length + is_can_payload payload; + uint8_t endByte; + +} is_can_message; + +typedef struct PACKED +{ + uint32_t marker; + protocol_type_t ptype; + uint32_t size; +} is_evb_log_stream; + + +#endif // __COMMUNICATIONS_H_ diff --git a/EVB-2/IS_EVB-2/src/config/FreeRTOSConfig.h b/EVB-2/IS_EVB-2/src/config/FreeRTOSConfig.h new file mode 100644 index 000000000..af9f3e881 --- /dev/null +++ b/EVB-2/IS_EVB-2/src/config/FreeRTOSConfig.h @@ -0,0 +1,162 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +/* For definition of BOARD_MCK. */ +#include "ISBoards.h" +#include "sysclk.h" +#include "d_time.h" +#include "../../../../src/data_sets.h" + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#define configUSE_QUEUE_SETS 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +// #define configCPU_CLOCK_HZ ( BOARD_MCK << 1UL ) +#define configCPU_CLOCK_HZ ( sysclk_get_cpu_hz() ) +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 10 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 130 ) + +#ifndef configTOTAL_HEAP_SIZE +#define configTOTAL_HEAP_SIZE 250368 +#endif + +#define configMAX_TASK_NAME_LEN ( 10 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 8 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 1 +#define configSUPPORT_STATIC_ALLOCATION 1 + +/* The full demo always has tasks to run so the tick will never be turned off. +The blinky demo will use the default tickless idle implementation to turn the +tick off. */ +#define configUSE_TICKLESS_IDLE 0 + +/* Run time stats gathering definitions. */ +#define configGENERATE_RUN_TIME_STATS 1 /* http://www.freertos.org/rtos-run-time-stats.html */ +#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() // Don't double init d_time here +#define portGET_RUN_TIME_COUNTER_VALUE() ((uint32_t)time_ticks_u32()) +#define INCLUDE_uxTaskGetStackHighWaterMark 1 + + +/* This demo makes use of one or more example stats formatting functions. These +format the raw data provided by the uxTaskGetSystemState() function in to human +readable ASCII form. See the notes in the implementation of vTaskList() within +FreeRTOS/Source/tasks.c for limitations. */ +#define configUSE_STATS_FORMATTING_FUNCTIONS 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define configTIMER_QUEUE_LENGTH 5 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskGetIdleTaskHandle 1 + +extern evb_rtos_info_t g_rtos; +#define traceMALLOC(pvAddress, uiSize) g_rtos.mallocSize += uiSize +#define traceFREE(pvAddress, uiSize) g_rtos.freeSize += uiSize + +/* Cortex-M specific definitions. */ +#ifdef __NVIC_PRIO_BITS + /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ + #define configPRIO_BITS __NVIC_PRIO_BITS +#else + #define configPRIO_BITS 3 /* 7 priority levels */ +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x07 + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 4 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) + +/* Normal assert() semantics without relying on the provision of an assert.h +header file. */ +#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. Based on the architecture choosen, the below definitons may be needed*/ + +#define xPortPendSVHandler PendSV_Handler +#define vPortSVCHandler SVC_Handler +#define xPortSysTickHandler SysTick_Handler + +#endif /* FREERTOS_CONFIG_H */ + diff --git a/EVB-2/IS_EVB-2/src/config/board_opt.h b/EVB-2/IS_EVB-2/src/config/board_opt.h new file mode 100644 index 000000000..e70f8e0fc --- /dev/null +++ b/EVB-2/IS_EVB-2/src/config/board_opt.h @@ -0,0 +1,21 @@ +/* +MIT LICENSE + +Copyright 2014-2019 Inertial Sense, Inc. - http://inertialsense.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions : + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +#ifndef BOARD_OPT_H_ +#define BOARD_OPT_H_ + + // Set to 0 to disable DCache, TODO: Fix, this crashes the system currently in release and malloc failures in debug + +// #include "conf_board.h" +// #include "core_cm7_4p30.h" + +#endif /* BOARD_OPT_H_ */ \ No newline at end of file diff --git a/EVB-2/IS_EVB-2/src/config/conf_access.h b/EVB-2/IS_EVB-2/src/config/conf_access.h new file mode 100644 index 000000000..0bd98885f --- /dev/null +++ b/EVB-2/IS_EVB-2/src/config/conf_access.h @@ -0,0 +1,273 @@ +/***************************************************************************** + * + * \file + * + * \brief Memory access control configuration file. + * + * This file contains the possible external configuration of the memory access + * control. + * + * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + ******************************************************************************/ +/* + * Support and FAQ: visit Microchip Support + */ + + + //! Configuration of ctrl_access which is an abstraction layer for memory interfaces (common/services/storage/ctrl_access) + +#ifndef _CONF_ACCESS_H_ +#define _CONF_ACCESS_H_ + +#include "compiler.h" +#include "ISBoards.h" + + +/*! \name Activation of Logical Unit Numbers + */ +//! @{ +#ifdef VIRTUAL_MEMORY_ENABLE +#define LUN_0 ENABLE //!< Enable On-Chip Virtual Memory. +#else +#define LUN_0 DISABLE //!< Disable On-Chip Virtual Memory. +#endif + +#ifdef AT45DBX_ENABLE +#define LUN_1 ENABLE //!< Enable AT45DBX Data Flash. +#else +#define LUN_1 DISABLE //!< Disable AT45DBX Data Flash. +#endif + +//! New setting for SD/MMC stack in common folder +#ifdef SD_MMC_ENABLE +#define LUN_2 ENABLE //!< Enable common SD/MMC stack +#define LUN_3 ENABLE +#define ACCESS_MEM_TO_RAM_ENABLED +#else +#define LUN_2 DISABLE //!< Disable common SD/MMC stack +#define LUN_3 DISABLE +#endif + +//! Old setting for SD/MMC stack in AVR folder +#ifdef SD_MMC_SPI_ENABLE +#define LUN_4 ENABLE //!< Enable SD/MMC Card over SPI or SPI. +#else +#define LUN_4 DISABLE //!< Disable SD/MMC Card over SPI or SPI. +#endif + +//! Old setting for SD/MMC stack in AVR folder +#ifdef SD_MMC_MCI_ENABLE +#define LUN_5 ENABLE //!< Enable SD/MMC Card over MCI or MCI. +#else +#define LUN_5 DISABLE //!< Disable SD/MMC Card over MCI or MCI. +#endif + +#define LUN_6 DISABLE +#define LUN_7 DISABLE + +#ifdef USB_MASS_STORAGE_ENABLE +#define LUN_USB ENABLE //!< Enable Host Mass-Storage Memory. +#else +#define LUN_USB DISABLE //!< Disable Host Mass-Storage Memory. +#endif + +//! @} + +/*! \name LUN 0 Definitions + */ +//! @{ +#define VIRTUAL_MEM LUN_0 +#define LUN_ID_VIRTUAL_MEM LUN_ID_0 +#define LUN_0_INCLUDE "virtual_mem.h" +#define Lun_0_test_unit_ready virtual_test_unit_ready +#define Lun_0_read_capacity virtual_read_capacity +#define Lun_0_unload NULL /* Can not be unloaded */ +#define Lun_0_wr_protect virtual_wr_protect +#define Lun_0_removal virtual_removal +#define Lun_0_usb_read_10 virtual_usb_read_10 +#define Lun_0_usb_write_10 virtual_usb_write_10 +#define Lun_0_mem_2_ram virtual_mem_2_ram +#define Lun_0_ram_2_mem virtual_ram_2_mem +#define LUN_0_NAME "\"On-Chip Virtual Memory\"" +//! @} + +/*! \name LUN 1 Definitions + */ +//! @{ +#define AT45DBX_MEM LUN_1 +#define LUN_ID_AT45DBX_MEM LUN_ID_1 +#define LUN_1_INCLUDE "at45dbx_mem.h" +#define Lun_1_test_unit_ready at45dbx_test_unit_ready +#define Lun_1_read_capacity at45dbx_read_capacity +#define Lun_1_unload NULL /* Can not be unloaded */ +#define Lun_1_wr_protect at45dbx_wr_protect +#define Lun_1_removal at45dbx_removal +#define Lun_1_usb_read_10 at45dbx_usb_read_10 +#define Lun_1_usb_write_10 at45dbx_usb_write_10 +#define Lun_1_mem_2_ram at45dbx_df_2_ram +#define Lun_1_ram_2_mem at45dbx_ram_2_df +#define LUN_1_NAME "\"AT45DBX Data Flash\"" +//! @} + +/*! \name LUN 2 Definitions + */ +//! @{ +#define SD_MMC_0_MEM LUN_2 +#define LUN_ID_SD_MMC_0_MEM LUN_ID_2 +#define LUN_2_INCLUDE "sd_mmc_mem.h" +#define Lun_2_test_unit_ready sd_mmc_test_unit_ready_0 +#define Lun_2_read_capacity sd_mmc_read_capacity_0 +#define Lun_2_unload sd_mmc_unload_0 +#define Lun_2_wr_protect sd_mmc_wr_protect_0 +#define Lun_2_removal sd_mmc_removal_0 +#define Lun_2_usb_read_10 sd_mmc_usb_read_10_0 +#define Lun_2_usb_write_10 sd_mmc_usb_write_10_0 +#define Lun_2_mem_2_ram sd_mmc_mem_2_ram_0 +#define Lun_2_ram_2_mem sd_mmc_ram_2_mem_0 +#define LUN_2_NAME "\"SD/MMC Card Slot 0\"" +//! @} + +/*! \name LUN 3 Definitions + */ +//! @{ +#define SD_MMC_1_MEM LUN_3 +#define LUN_ID_SD_MMC_1_MEM LUN_ID_3 +#define LUN_3_INCLUDE "sd_mmc_mem.h" +#define Lun_3_test_unit_ready sd_mmc_test_unit_ready_1 +#define Lun_3_read_capacity sd_mmc_read_capacity_1 +#define Lun_3_unload sd_mmc_unload_1 +#define Lun_3_wr_protect sd_mmc_wr_protect_1 +#define Lun_3_removal sd_mmc_removal_1 +#define Lun_3_usb_read_10 sd_mmc_usb_read_10_1 +#define Lun_3_usb_write_10 sd_mmc_usb_write_10_1 +#define Lun_3_mem_2_ram sd_mmc_mem_2_ram_1 +#define Lun_3_ram_2_mem sd_mmc_ram_2_mem_1 +#define LUN_3_NAME "\"SD/MMC Card Slot 1\"" +//! @} + +/*! \name LUN 4 Definitions + */ +//! @{ +#define SD_MMC_SPI_MEM LUN_4 +#define LUN_ID_SD_MMC_SPI_MEM LUN_ID_4 +#define LUN_4_INCLUDE "sd_mmc_spi_mem.h" +#define Lun_4_test_unit_ready sd_mmc_spi_test_unit_ready +#define Lun_4_read_capacity sd_mmc_spi_read_capacity +#define Lun_4_unload NULL +#define Lun_4_wr_protect sd_mmc_spi_wr_protect +#define Lun_4_removal sd_mmc_spi_removal +#define Lun_4_usb_read_10 sd_mmc_spi_usb_read_10 +#define Lun_4_usb_write_10 sd_mmc_spi_usb_write_10 +#define Lun_4_mem_2_ram sd_mmc_spi_mem_2_ram +#define Lun_4_ram_2_mem sd_mmc_spi_ram_2_mem +#define LUN_4_NAME "\"SD/MMC Card over SPI\"" +//! @} + +/*! \name LUN 5 Definitions + */ +//! @{ +#define SD_MMC_MCI_0_MEM LUN_5 +#define LUN_ID_SD_MMC_MCI_0_MEM LUN_ID_5 +#define LUN_5_INCLUDE "sd_mmc_mci_mem.h" +#define Lun_5_test_unit_ready sd_mmc_mci_test_unit_ready_0 +#define Lun_5_read_capacity sd_mmc_mci_read_capacity_0 +#define Lun_5_unload NULL +#define Lun_5_wr_protect sd_mmc_mci_wr_protect_0 +#define Lun_5_removal sd_mmc_mci_removal_0 +#define Lun_5_usb_read_10 sd_mmc_mci_usb_read_10_0 +#define Lun_5_usb_write_10 sd_mmc_mci_usb_write_10_0 +#define Lun_5_mem_2_ram sd_mmc_mci_mem_2_ram_0 +#define Lun_5_ram_2_mem sd_mmc_mci_ram_2_mem_0 +#define LUN_5_NAME "\"SD/MMC Card over MCI Slot 0\"" +//! @} + +/*! \name USB LUNs Definitions + */ +//! @{ +#define MEM_USB LUN_USB +#define LUN_ID_MEM_USB LUN_ID_USB +#define LUN_USB_INCLUDE "uhi_msc_mem.h" +#define Lun_usb_get_lun() uhi_msc_mem_get_lun() +#define Lun_usb_test_unit_ready(lun) uhi_msc_mem_test_unit_ready(lun) +#define Lun_usb_read_capacity(lun, nb_sect) uhi_msc_mem_read_capacity(lun, nb_sect) +#define Lun_usb_read_sector_size(lun) uhi_msc_mem_read_sector_size(lun) +#define Lun_usb_unload NULL +#define Lun_usb_wr_protect(lun) uhi_msc_mem_wr_protect(lun) +#define Lun_usb_removal() uhi_msc_mem_removal() +#define Lun_usb_mem_2_ram(addr, ram) uhi_msc_mem_read_10_ram(addr, ram) +#define Lun_usb_ram_2_mem(addr, ram) uhi_msc_mem_write_10_ram(addr, ram) +#define LUN_USB_NAME "\"Host Mass-Storage Memory\"" +//! @} + +/*! \name Actions Associated with Memory Accesses + * + * Write here the action to associate with each memory access. + * + * \warning Be careful not to waste time in order not to disturb the functions. + */ +//! @{ +#define memory_start_read_action(nb_sectors) +#define memory_stop_read_action() +#define memory_start_write_action(nb_sectors) +#define memory_stop_write_action() +//! @} + +/*! \name Activation of Interface Features + */ +//! @{ +#ifdef ACCESS_USB_ENABLED +#define ACCESS_USB true //!< MEM <-> USB interface. +#else +#define ACCESS_USB false //!< MEM <-> USB interface. +#endif + +#ifdef ACCESS_MEM_TO_RAM_ENABLED +#define ACCESS_MEM_TO_RAM true //!< MEM <-> RAM interface. +#else +#define ACCESS_MEM_TO_RAM false //!< MEM <-> RAM interface. +#endif + +#define ACCESS_STREAM false //!< Streaming MEM <-> MEM interface. +#define ACCESS_STREAM_RECORD false //!< Streaming MEM <-> MEM interface in record mode. +#define ACCESS_MEM_TO_MEM false //!< MEM <-> MEM interface. +#define ACCESS_CODEC false //!< Codec interface. +//! @} + +/*! \name Specific Options for Access Control + */ +//! @{ +#define GLOBAL_WR_PROTECT false //!< Management of a global write protection. +//! @} + +/*! \name Sector size option for different storage media. + */ +//! @{ +#define SECTOR_SIZE 512 +//! @} + +#endif // _CONF_ACCESS_H_ diff --git a/EVB-2/IS_EVB-2/src/config/conf_board.h b/EVB-2/IS_EVB-2/src/config/conf_board.h new file mode 100644 index 000000000..adc4a200e --- /dev/null +++ b/EVB-2/IS_EVB-2/src/config/conf_board.h @@ -0,0 +1,118 @@ +/** + * \file + * + * \brief Board configuration. + * + * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef CONF_BOARD_H_INCLUDED +#define CONF_BOARD_H_INCLUDED + +#include "ISBoards.h" +#include "board_opt.h" + +#define CONF_BOARD_CONFIG_MPU_AT_INIT + +// Setup to use the Watchdog +#ifndef DEBUG // RELEASE +#define ENABLE_WDT +#endif // DEBUG + +#ifdef ENABLE_WDT + #define CONF_BOARD_KEEP_WATCHDOG_AT_INIT // Don't change WDT mode register in init.c +#endif + +/* Enable ICache and DCache */ +#if CONF_BOARD_ENABLE_DCACHE == 1 + #define CONF_BOARD_ENABLE_CACHE_AT_INIT +#endif + +/** Enable SD MMC interface pins through HSMCI */ +#define CONF_BOARD_SD_MMC_HSMCI +#define CONF_HSMCI_XDMAC_CHANNEL XDMAC_CHANNEL_HWID_HSMCI + +//! [tc_define_peripheral] +/* Use TC Peripheral 0. */ +#define TC TC0 +#define TC_PERIPHERAL 0 +//! [tc_define_peripheral] + +//! [tc_define_ch1] +/* Configure TC0 channel 1 as waveform output. */ +#define TC_CHANNEL_WAVEFORM 1 +#define ID_TC_WAVEFORM ID_TC1 +#define PIN_TC_WAVEFORM PIN_TC0_TIOA1 +#define PIN_TC_WAVEFORM_MUX PIN_TC0_TIOA1_MUX +//! [tc_define_ch1] + +//! [tc_define_ch2] +/* Configure TC0 channel 2 as capture input. */ +#define TC_CHANNEL_CAPTURE 2 +#define ID_TC_CAPTURE ID_TC2 +#define PIN_TC_CAPTURE PIN_TC0_TIOA2 +#define PIN_TC_CAPTURE_MUX PIN_TC0_TIOA2_MUX +//! [tc_define_ch2] + +//! [tc_define_irq_handler] +/* Use TC2_Handler for TC capture interrupt. */ +#define TC_Handler TC2_Handler +#define TC_IRQn TC2_IRQn +//! [tc_define_irq_handler] + +// Serial interfaces +#define CONF_BOARD_SERIAL_UINS_SER0 +#define CONF_BOARD_SERIAL_UINS_SER1 +#define CONF_BOARD_SERIAL_XBEE +// HACK: disable external radio to prevent right RK2K wheel from spinning. We need to move all I/O config into a central function that allows these features to be disabled. +// #define CONF_BOARD_SERIAL_EXT_RADIO +#define CONF_BOARD_SERIAL_ATWINC_BLE +#define CONF_BOARD_SERIAL_SP330 +#define CONF_BOARD_SERIAL_GPIO_H8 + +// SPI interfaces +#define CONF_BOARD_SPI_UINS +#define CONF_BOARD_SPI_ATWINC_WIFI + +// Encoder interfaces +#define CONF_BOARD_QUAD_ENCODER + +// I2C interface +// #define CONF_BOARD_I2C_UINS + +// CAN interface +#define CONF_BOARD_CAN1 + //#define CONF_BOARD_CAN_TEST + +// ADC interface +#define CONF_BOARD_ADC + +#endif /* CONF_BOARD_H_INCLUDED */ diff --git a/EVB-2/IS_EVB-2/src/config/conf_clock.h b/EVB-2/IS_EVB-2/src/config/conf_clock.h new file mode 100644 index 000000000..6bbfffad7 --- /dev/null +++ b/EVB-2/IS_EVB-2/src/config/conf_clock.h @@ -0,0 +1,104 @@ +/** + * \file + * + * \brief SAME70 clock configuration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef CONF_CLOCK_H_INCLUDED +#define CONF_CLOCK_H_INCLUDED + +// ===== System Clock (MCK) Source Options +//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_RC +//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_XTAL +//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_BYPASS +//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_4M_RC +//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_8M_RC +//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_12M_RC +//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_XTAL +//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_BYPASS +#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK +//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_UPLLCK + +// ===== Processor Clock (HCLK) Prescaler Options (Fhclk = Fsys / (SYSCLK_PRES)) +#define CONFIG_SYSCLK_PRES SYSCLK_PRES_1 +//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_2 +//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_4 +//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_8 +//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_16 +//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_32 +//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_64 +//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_3 + +// ===== System Clock (MCK) Division Options (Fmck = Fhclk / (SYSCLK_DIV)). MCK max freq is 150 MHz. +#define CONFIG_SYSCLK_DIV 2 + +#if 1 // HCLK: 300 MHz, MCK: 150 MHz +// ===== PLL0 (A) Options (Fpll = (Fclk * PLL_mul) / PLL_div) +// Use mul and div effective values here. +#define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_BYPASS +#define CONFIG_PLL0_MUL 25 +#define CONFIG_PLL0_DIV 1 + +#else // HCLK: 200 MHz, MCK: 100 MHz + +#define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL +#define CONFIG_PLL0_MUL 50 +#define CONFIG_PLL0_DIV 3 + +#endif + + +// ===== UPLL (UTMI) Hardware fixed at 480 MHz. + +// ===== USB Clock Source Options (Fusb = FpllX / USB_div) +// Use div effective value here. +//#define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0 +#define CONFIG_USBCLK_SOURCE USBCLK_SRC_UPLL +#define CONFIG_USBCLK_DIV 1 + +// ===== Target frequency (Processor clock) +// - XTAL frequency: 12MHz +// - System clock source: PLLA +// - System clock prescaler: 1 (divided by 1) +// - System clock divider: 2 (divided by 2) +// - PLLA source: XTAL +// - PLLA output: XTAL * 25 / 1 +// - Processor clock: 12 * 25 / 1 / 1 = 300MHz +// - System clock: 300 / 2 = 150MHz +// ===== Target frequency (USB Clock) +// - USB clock source: UPLL +// - USB clock divider: 1 (not divided) +// - UPLL frequency: 480MHz +// - USB clock: 480 / 1 = 480MHz + +#endif /* CONF_CLOCK_H_INCLUDED */ diff --git a/EVB-2/IS_EVB-2/src/config/conf_comm.h b/EVB-2/IS_EVB-2/src/config/conf_comm.h new file mode 100644 index 000000000..4aafaebe5 --- /dev/null +++ b/EVB-2/IS_EVB-2/src/config/conf_comm.h @@ -0,0 +1,40 @@ +/* +MIT LICENSE + +Copyright 2014-2019 Inertial Sense, Inc. - http://inertialsense.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions : + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +#ifndef CONF_COMM_H_ +#define CONF_COMM_H_ + +//Define what port number goes to which hardware UART/USART and some configuration +// UART/USART DMA TX Channel TX Buffer Size DMA RX Channel RX Buffer Size +#define PORT0_CONFIG ( UART1, DMA_CH_EVB_UART_UINS0_TX, 4096, DMA_CH_EVB_UART_UINS0_RX, 4096 ) +#define PORT1_CONFIG ( UART0, DMA_CH_EVB_UART_UINS1_TX, 4096, DMA_CH_EVB_UART_UINS1_RX, 4096 ) +#define PORT2_CONFIG ( USART0, DMA_CH_EVB_UART_XBEE_TX, 2048, DMA_CH_EVB_UART_XBEE_RX, 2048 ) +#define PORT3_CONFIG ( UART2, DMA_CH_EVB_UART_XRADIO_TX, 2048, DMA_CH_EVB_UART_XRADIO_RX, 2048 ) +#define PORT4_CONFIG ( USART2, DMA_CH_EVB_UART_WINC_BLE_TX, 2048, DMA_CH_EVB_UART_WINC_BLE_RX, 2048 ) +#define PORT5_CONFIG ( UART3, DMA_CH_EVB_UART_SP330_TX, 2048, DMA_CH_EVB_UART_SP330_RX, 2048 ) +#define PORT6_CONFIG ( USART1, DMA_CH_EVB_UART_GPIO_TTL_TX, 2048, DMA_CH_EVB_UART_GPIO_TTL_RX, 2048 ) +#define PORT7_CONFIG ( 0, 0, 2048, 0, 0 ) // USB port + +#define DEFAULT_BAUDRATE 115200 + +#define CONF_BOARD_USART_SPI 0 // Configure USART SPI pins +#define CONF_BOARD_USART_SPI_DATAREADY_ENABLE 0 //Enables the use of the data ready pin when in USART SPI mode + +#define CONF_LOOPBACK_PORT 0 // DEBUGGING: Select port 0 or 1 +#define ENABLE_COMM_LOOPBACK_DRIVER 0 // DEBUGGING: Forward serial port Rx onto Tx (Driver level) +#define ENABLE_COMM_LOOPBACK_RTOS 0 // DEBUGGING: Forward serial port Rx onto Tx (RTOS level). +#define MAX_NUMBER_SERIAL_PORTS 8 + +#define SER_INDICATE_TX() +#define SER_INDICATE_RX() + +#endif /* CONF_COMM_H_ */ diff --git a/EVB-2/IS_EVB-2/src/config/conf_d_i2c.h b/EVB-2/IS_EVB-2/src/config/conf_d_i2c.h new file mode 100644 index 000000000..c7c56f87f --- /dev/null +++ b/EVB-2/IS_EVB-2/src/config/conf_d_i2c.h @@ -0,0 +1,16 @@ +/* +MIT LICENSE + +Copyright 2014-2019 Inertial Sense, Inc. - http://inertialsense.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions : + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +#ifndef CONF_D_I2C_H_ +#define CONF_D_I2C_H_ + +#endif /* CONF_D_I2C_H_ */ \ No newline at end of file diff --git a/EVB-2/IS_EVB-2/src/config/conf_d_quadEnc.h b/EVB-2/IS_EVB-2/src/config/conf_d_quadEnc.h new file mode 100644 index 000000000..47a6eef91 --- /dev/null +++ b/EVB-2/IS_EVB-2/src/config/conf_d_quadEnc.h @@ -0,0 +1,136 @@ +/* +MIT LICENSE + +Copyright 2014-2019 Inertial Sense, Inc. - http://inertialsense.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions : + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + + +#ifndef CONF_D_QUADENC_H_ +#define CONF_D_QUADENC_H_ + +#if 1 + +/*********** Left Wheel Encoder ***********/ +/*** Position ***/ +// EVB H8-9: GPIO5 - QDEC2-A - TIOA6 - PC5 +// EVB H8-10: GPIO6 - QDEC2-B - TIOB6 - PC6 +#define QE0_POS TC2 +#define ID_QE0_POS ID_TC6 + +#define PIN_QE0_POS_PHA (PIO_PC5_IDX) //TC2 TIOA6 +#define PIN_QE0_POS_PHA_MUX (IOPORT_MODE_MUX_B) + +#define PIN_QE0_POS_PHB (PIO_PC6_IDX) //TC2 TIOB6 +#define PIN_QE0_POS_PHB_MUX (IOPORT_MODE_MUX_B) + +/*** Speed ***/ +#if 1 + // EVB H8-9: GPIO5 - TIOA5 - PC29 + #define TCCAP0_SPD TC1 + #define TCCAP0_SPD_CHANNEL 2 + #define ID_TCCAP0_SPD ID_TC5 + + #define PIN_TCCAP0_SPD (PIO_PC29_IDX) + #define PIN_TCCAP0_SPD_MUX (IOPORT_MODE_MUX_B) + + #define TCCAP0_SPD_Handler TC5_Handler + #define TCCAP0_SPD_IRQn TC5_IRQn +#else + // EVB H8-11: GPIO7 - TIOA10 - PE3 + #define TCCAP0_SPD TC3 + #define TCCAP0_SPD_CHANNEL 1 + #define ID_TCCAP0_SPD ID_TC10 + + #define PIN_TCCAP0_SPD (PIO_PE3_IDX) + #define PIN_TCCAP0_SPD_MUX (IOPORT_MODE_MUX_B) + + #define TCCAP0_SPD_Handler TC10_Handler + #define TCCAP0_SPD_IRQn TC10_IRQn +#endif + +/*********** Right Wheel Encoder ***********/ +/*** Position ***/ +// EVB H8-13: GPIO9 - QDEC3-A - TIOA9 - PE0 +// EVB H8-14: GPIO10 - QDEC3-B - TIOB9 - PE1 +#define QE1_POS TC3 +#define ID_QE1_POS ID_TC9 + +#define PIN_QE1_POS_PHA (PIO_PE0_IDX) //TC3 TIOA9 +#define PIN_QE1_POS_PHA_MUX (IOPORT_MODE_MUX_B) + +#define PIN_QE1_POS_PHB (PIO_PE1_IDX) //TC3 TIOB9 +#define PIN_QE1_POS_PHB_MUX (IOPORT_MODE_MUX_B) + +/*** Speed ***/ +// EVB H8-7: GPIO3 - TIOA0 - PA0 +#define TCCAP1_SPD TC0 +#define TCCAP1_SPD_CHANNEL 0 +#define ID_TCCAP1_SPD ID_TC0 + +#define PIN_TCCAP1_SPD (PIO_PA15_IDX) +#define PIN_TCCAP1_SPD_MUX (IOPORT_MODE_MUX_B) + +#define TCCAP1_SPD_Handler TC0_Handler +#define TCCAP1_SPD_IRQn TC0_IRQn + +#else +/*********** Use for testing with EVB-2 rev 2.0.0 *********/ + + /*** Position ***/ + // EVB H8-7: GPIO3 - QDEC0-A - TIOA0 - PA0 + // EVB H8-8: GPIO4 - QDEC0-B - TIOB0 - PA1 + #define QE0_POS TC0 + #define ID_QE0_POS ID_TC0 + + #define PIN_QE0_POS_PHA (PIO_PA0_IDX) //TC0 TIOA0 + #define PIN_QE0_POS_PHA_MUX (IOPORT_MODE_MUX_B) + + #define PIN_QE0_POS_PHB (PIO_PA1_IDX) //TC0 TIOB0 + #define PIN_QE0_POS_PHB_MUX (IOPORT_MODE_MUX_B) + + /*** Speed ***/ + // EVB H8-7: GPIO3 - QDEC0-A - TIOA0 - PA0 + #define TCCAP0_SPD TC0 + #define TCCAP0_SPD_CHANNEL 0 + #define ID_TCCAP0_SPD ID_TC0 + + #define PIN_TCCAP0_SPD (PIO_PA0_IDX) + #define PIN_TCCAP0_SPD_MUX (IOPORT_MODE_MUX_B) + + #define TCCAP0_SPD_Handler TC0_Handler + #define TCCAP0_SPD_IRQn TC0_IRQn + + /*********** Right Wheel Encoder ***********/ + /*** Position ***/ + // EVB H8-13: GPIO9 - QDEC3-A - TIOA9 - PE0 + // EVB H8-14: GPIO10 - QDEC3-B - TIOB9 - PE1 + #define QE1_POS TC3 + #define ID_QE1_POS ID_TC9 + + #define PIN_QE1_POS_PHA (PIO_PE0_IDX) //TC3 TIOA9 + #define PIN_QE1_POS_PHA_MUX (IOPORT_MODE_MUX_B) + + #define PIN_QE1_POS_PHB (PIO_PE1_IDX) //TC3 TIOB9 + #define PIN_QE1_POS_PHB_MUX (IOPORT_MODE_MUX_B) + + /*** Speed ***/ + // EVB H8-13: GPIO1 - TIOA9 - PE0 + #define TCCAP1_SPD TC3 + #define TCCAP1_SPD_CHANNEL 0 + #define ID_TCCAP1_SPD ID_TC9 + + #define PIN_TCCAP1_SPD (PIO_PE0_IDX) + #define PIN_TCCAP1_SPD_MUX (IOPORT_MODE_MUX_B) + + #define TCCAP1_SPD_Handler TC9_Handler + #define TCCAP1_SPD_IRQn TC9_IRQn + +#endif + +#endif /* CONF_D_QUADENC_H_ */ \ No newline at end of file diff --git a/EVB-2/IS_EVB-2/src/config/conf_debug.h b/EVB-2/IS_EVB-2/src/config/conf_debug.h new file mode 100644 index 000000000..682ccc54e --- /dev/null +++ b/EVB-2/IS_EVB-2/src/config/conf_debug.h @@ -0,0 +1,19 @@ +/* +MIT LICENSE + +Copyright 2014-2019 Inertial Sense, Inc. - http://inertialsense.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions : + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +#ifndef CONF_DEBUG_H_ +#define CONF_DEBUG_H_ + +#define DBG_TX_DCACHE_CLEAN_PIN 0 //GPIO_5_PIN +#define DBG_RX_DCACHE_CLEAN_PIN 0 //GPIO_8_PIN + +#endif /* CONF_DEBUG_H_ */ \ No newline at end of file diff --git a/EVB-2/IS_EVB-2/src/config/conf_fatfs.h b/EVB-2/IS_EVB-2/src/config/conf_fatfs.h new file mode 100644 index 000000000..1ebe23c8a --- /dev/null +++ b/EVB-2/IS_EVB-2/src/config/conf_fatfs.h @@ -0,0 +1,227 @@ +/** + * \file + * + * \brief FatFS configurations. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef CONF_FATFS_H_INCLUDED +#define CONF_FATFS_H_INCLUDED + +/*---------------------------------------------------------------------------/ +/ FatFs - FAT file system module configuration file R0.09 (C)ChaN, 2011 +/----------------------------------------------------------------------------/ +/ +/ CAUTION! Do not forget to make clean the project after any changes to +/ the configuration options. +/ +/----------------------------------------------------------------------------*/ + +#ifndef _FFCONF +#define _FFCONF 6502 /* Revision ID */ + + +/*---------------------------------------------------------------------------/ +/ Functions and Buffer Configurations +/----------------------------------------------------------------------------*/ + +#define _FS_TINY 1 /* 0:Normal or 1:Tiny */ +/* When _FS_TINY is set to 1, FatFs uses the sector buffer in the file system +/ object instead of the sector buffer in the individual file object for file +/ data transfer. This reduces memory consumption 512 bytes each file object. */ + + +#define _FS_READONLY 0 /* 0:Read/Write or 1:Read only */ +/* Setting _FS_READONLY to 1 defines read only configuration. This removes +/ writing functions, f_write, f_sync, f_unlink, f_mkdir, f_chmod, f_rename, +/ f_truncate and useless f_getfree. */ + + +#define _FS_MINIMIZE 0 /* 0 to 3 */ +/* The _FS_MINIMIZE option defines minimization level to remove some functions. +/ +/ 0: Full function. +/ 1: f_stat, f_getfree, f_unlink, f_mkdir, f_chmod, f_truncate and f_rename +/ are removed. +/ 2: f_opendir and f_readdir are removed in addition to 1. +/ 3: f_lseek is removed in addition to 2. */ + + +#define _USE_STRFUNC 1 /* 0:Disable or 1-2:Enable */ +/* To enable string functions, set _USE_STRFUNC to 1 or 2. */ + + +#define _USE_MKFS 1 /* 0:Disable or 1:Enable */ +/* To enable f_mkfs function, set _USE_MKFS to 1 and set _FS_READONLY to 0 */ + + +#define _USE_FORWARD 0 /* 0:Disable or 1:Enable */ +/* To enable f_forward function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */ + + +#define _USE_FASTSEEK 0 /* 0:Disable or 1:Enable */ +/* To enable fast seek feature, set _USE_FASTSEEK to 1. */ + + + +/*---------------------------------------------------------------------------/ +/ Locale and Namespace Configurations +/----------------------------------------------------------------------------*/ +#define _CODE_PAGE 850 +/* The _CODE_PAGE specifies the OEM code page to be used on the target system. +/ Incorrect setting of the code page can cause a file open failure. +/ +/ 932 - Japanese Shift-JIS (DBCS, OEM, Windows) +/ 936 - Simplified Chinese GBK (DBCS, OEM, Windows) +/ 949 - Korean (DBCS, OEM, Windows) +/ 950 - Traditional Chinese Big5 (DBCS, OEM, Windows) +/ 1250 - Central Europe (Windows) +/ 1251 - Cyrillic (Windows) +/ 1252 - Latin 1 (Windows) +/ 1253 - Greek (Windows) +/ 1254 - Turkish (Windows) +/ 1255 - Hebrew (Windows) +/ 1256 - Arabic (Windows) +/ 1257 - Baltic (Windows) +/ 1258 - Vietnam (OEM, Windows) +/ 437 - U.S. (OEM) +/ 720 - Arabic (OEM) +/ 737 - Greek (OEM) +/ 775 - Baltic (OEM) +/ 850 - Multilingual Latin 1 (OEM) +/ 858 - Multilingual Latin 1 + Euro (OEM) +/ 852 - Latin 2 (OEM) +/ 855 - Cyrillic (OEM) +/ 866 - Russian (OEM) +/ 857 - Turkish (OEM) +/ 862 - Hebrew (OEM) +/ 874 - Thai (OEM, Windows) +/ 1 - ASCII only (Valid for non LFN cfg.) +*/ + +#define _USE_LFN 2 /* 0 to 3 */ +#define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */ +/* The _USE_LFN option switches the LFN support. +/ +/ 0: Disable LFN feature. _MAX_LFN and _LFN_UNICODE have no effect. +/ 1: Enable LFN with static working buffer on the BSS. Always NOT reentrant. +/ 2: Enable LFN with dynamic working buffer on the STACK. +/ 3: Enable LFN with dynamic working buffer on the HEAP. +/ +/ The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. To enable LFN, +/ Unicode handling functions ff_convert() and ff_wtoupper() must be added +/ to the project. When enable to use heap, memory control functions +/ ff_memalloc() and ff_memfree() must be added to the project. */ + + +#define _LFN_UNICODE 0 /* 0:ANSI/OEM or 1:Unicode */ +/* To switch the character code set on FatFs API to Unicode, +/ enable LFN feature and set _LFN_UNICODE to 1. */ + + +#define _FS_RPATH 0 /* 0 to 2 */ +/* The _FS_RPATH option configures relative path feature. +/ +/ 0: Disable relative path feature and remove related functions. +/ 1: Enable relative path. f_chdrive() and f_chdir() are available. +/ 2: f_getcwd() is available in addition to 1. +/ +/ Note that output of the f_readdir fnction is affected by this option. */ + + + +/*---------------------------------------------------------------------------/ +/ Physical Drive Configurations +/----------------------------------------------------------------------------*/ + +#define _VOLUMES 8 +/* Number of volumes (logical drives) to be used. */ + + +#define _MAX_SS 512 /* 512, 1024, 2048 or 4096 */ +/* Maximum sector size to be handled. +/ Always set 512 for memory card and hard disk but a larger value may be +/ required for on-board flash memory, floppy disk and optical disk. +/ When _MAX_SS is larger than 512, it configures FatFs to variable sector size +/ and GET_SECTOR_SIZE command must be implemented to the disk_ioctl function. */ + + +#define _MULTI_PARTITION 0 /* 0:Single partition, 1/2:Enable multiple partition */ +/* When set to 0, each volume is bound to the same physical drive number and +/ it can mount only first primaly partition. When it is set to 1, each volume +/ is tied to the partitions listed in VolToPart[]. */ + + +#define _USE_ERASE 0 /* 0:Disable or 1:Enable */ +/* To enable sector erase feature, set _USE_ERASE to 1. CTRL_ERASE_SECTOR command +/ should be added to the disk_ioctl functio. */ + + + +/*---------------------------------------------------------------------------/ +/ System Configurations +/----------------------------------------------------------------------------*/ + +#define _WORD_ACCESS 0 /* 0 or 1 */ +/* Set 0 first and it is always compatible with all platforms. The _WORD_ACCESS +/ option defines which access method is used to the word data on the FAT volume. +/ +/ 0: Byte-by-byte access. +/ 1: Word access. Do not choose this unless following condition is met. +/ +/ When the byte order on the memory is big-endian or address miss-aligned word +/ access results incorrect behavior, the _WORD_ACCESS must be set to 0. +/ If it is not the case, the value can also be set to 1 to improve the +/ performance and code size. +*/ + + +/* A header file that defines sync object types on the O/S, such as +/ windows.h, ucos_ii.h and semphr.h, must be included prior to ff.h. */ + +#define _FS_REENTRANT 0 /* 0:Disable or 1:Enable */ +#define _FS_TIMEOUT 1000 /* Timeout period in unit of time ticks */ +#define _SYNC_t HANDLE /* O/S dependent type of sync object. e.g. HANDLE, OS_EVENT*, ID and etc.. */ + +/* The _FS_REENTRANT option switches the reentrancy (thread safe) of the FatFs module. +/ +/ 0: Disable reentrancy. _SYNC_t and _FS_TIMEOUT have no effect. +/ 1: Enable reentrancy. Also user provided synchronization handlers, +/ ff_req_grant, ff_rel_grant, ff_del_syncobj and ff_cre_syncobj +/ function must be added to the project. */ + + +#define _FS_SHARE 0 /* 0:Disable or >=1:Enable */ +/* To enable file shareing feature, set _FS_SHARE to 1 or greater. The value + defines how many files can be opened simultaneously. */ + + +#endif /* _FFCONFIG */ + +#endif /* CONF_FATFS_H_INCLUDED */ diff --git a/EVB-2/IS_EVB-2/src/config/conf_interrupts.h b/EVB-2/IS_EVB-2/src/config/conf_interrupts.h new file mode 100644 index 000000000..505ea2d23 --- /dev/null +++ b/EVB-2/IS_EVB-2/src/config/conf_interrupts.h @@ -0,0 +1,14 @@ +#ifndef _CONF_INTERRUPTS_H_ +#define _CONF_INTERRUPTS_H_ + +// see ARM Cortex-M7 documentation on NVIC IPR +// Each priority field holds a priority value, 0-255. +// The lower the value, the greater the priority of +// the corresponding interrupt. + +#define INT_PRIORITY_TC 1 +#define INT_PRIORITY_RTT 2 +#define INT_PRIORITY_DMA 3 + +#endif // _CONF_INTERRUPTS_H_ + diff --git a/EVB-2/IS_EVB-2/src/config/conf_mcan.h b/EVB-2/IS_EVB-2/src/config/conf_mcan.h new file mode 100644 index 000000000..d6e39773c --- /dev/null +++ b/EVB-2/IS_EVB-2/src/config/conf_mcan.h @@ -0,0 +1,109 @@ +/** + * \file + * + * \brief SAM Control Area Network Driver Configuration Header + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef CONF_MCAN_H_INCLUDED +#define CONF_MCAN_H_INCLUDED + +/* + * Below is the message RAM setting, it will be stored in the system RAM. + * Please adjust the message size according to your application. + */ +/** Range: 1..64 */ +#define CONF_MCAN0_RX_FIFO_0_NUM 16 +/** Range: 1..64 */ +#define CONF_MCAN0_RX_FIFO_1_NUM 16 +/** Range: 1..64 */ +#define CONF_MCAN0_RX_BUFFER_NUM 16 +/** Range: 1..16 */ +#define CONF_MCAN0_TX_BUFFER_NUM 4 +/** Range: 1..16 */ +#define CONF_MCAN0_TX_FIFO_QUEUE_NUM 4 +/** Range: 1..32 */ +#define CONF_MCAN0_TX_EVENT_FIFO 8 +/** Range: 1..128 */ +#define CONF_MCAN0_RX_STANDARD_ID_FILTER_NUM 32 +/** Range: 1..64 */ +#define CONF_MCAN0_RX_EXTENDED_ID_FILTER_NUM 16 +/** Range: 1..64 */ +#define CONF_MCAN1_RX_FIFO_0_NUM 16 +/** Range: 1..64 */ +#define CONF_MCAN1_RX_FIFO_1_NUM 16 +/** Range: 1..64 */ +#define CONF_MCAN1_RX_BUFFER_NUM 0 //16 +/** Range: 1..16 */ +#define CONF_MCAN1_TX_BUFFER_NUM 0 +/** Range: 1..16 */ +#define CONF_MCAN1_TX_FIFO_QUEUE_NUM 8 +/** Range: 1..32 */ +#define CONF_MCAN1_TX_EVENT_FIFO 8 +/** Range: 1..128 */ +#define CONF_MCAN1_RX_STANDARD_ID_FILTER_NUM 32 +/** Range: 1..64 */ +#define CONF_MCAN1_RX_EXTENDED_ID_FILTER_NUM 16 + +/** The value should be 8/12/16/20/24/32/48/64. */ +#define CONF_MCAN_ELEMENT_DATA_SIZE 8 + +/** + * The setting of the nominal bit rate is based on the PCK5 which is 480M which you can + * change in the conf_clock.h. Below is the default configuration. The + * time quanta is 20MHz / (1+1) = 10MHz. And each bit is (1 + NTSEG1 + 1 + NTSEG2 + 1) = 20 time + * quanta which means the bit rate is 10MHz/20=500KHz. + */ +/** Nominal bit Baud Rate Prescaler */ +#define CONF_MCAN_NBTP_NBRP_VALUE 1 +/** Nominal bit (Re)Synchronization Jump Width */ +#define CONF_MCAN_NBTP_NSJW_VALUE 3 +/** Nominal bit Time segment before sample point */ +#define CONF_MCAN_NBTP_NTSEG1_VALUE 10 +/** Nominal bit Time segment after sample point */ +#define CONF_MCAN_NBTP_NTSEG2_VALUE 7 + +/* + * The setting of the data bit rate is based on the GCLK_MCAN is 48M which you can + * change in the conf_clock.h. Below is the default configuration. The + * time quanta is 48MHz / (5+1) = 8MHz. And each bit is (1 + FTSEG1 + 1 + FTSEG2 + 1) = 16 time + * quanta which means the bit rate is 8MHz/16=500KHz. + */ +/** Data bit Baud Rate Prescaler */ +#define CONF_MCAN_FBTP_FBRP_VALUE 5 +/** Data bit (Re)Synchronization Jump Width */ +#define CONF_MCAN_FBTP_FSJW_VALUE 3 +/** Data bit Time segment before sample point */ +#define CONF_MCAN_FBTP_FTSEG1_VALUE 10 +/** Data bit Time segment after sample point */ +#define CONF_MCAN_FBTP_FTSEG2_VALUE 3 + +#endif diff --git a/EVB-2/IS_EVB-2/src/config/conf_sd_mmc.h b/EVB-2/IS_EVB-2/src/config/conf_sd_mmc.h new file mode 100644 index 000000000..ad47bd933 --- /dev/null +++ b/EVB-2/IS_EVB-2/src/config/conf_sd_mmc.h @@ -0,0 +1,55 @@ +/** + * \file + * + * \brief SD/MMC stack configuration file. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef CONF_SD_MMC_H_INCLUDED +#define CONF_SD_MMC_H_INCLUDED + +// Define to enable the SPI mode instead of Multimedia Card interface mode +//#define SD_MMC_SPI_MODE + +#define CONF_BOARD_SD_MMC_HSMCI + +// Define to enable the SDIO support +#define SDIO_SUPPORT_ENABLE + +#define CONF_BOARD_CONFIG_MPU_AT_INIT + +// Define it to enable the debug trace to the current standard output (stdio) +//#define SD_MMC_DEBUG +//#define HSMCI_DEBUG + +#endif /* CONF_SD_MMC_H_INCLUDED */ + diff --git a/EVB-2/IS_EVB-2/src/config/conf_sleepmgr.h b/EVB-2/IS_EVB-2/src/config/conf_sleepmgr.h new file mode 100644 index 000000000..cf01e2b63 --- /dev/null +++ b/EVB-2/IS_EVB-2/src/config/conf_sleepmgr.h @@ -0,0 +1,42 @@ +/** + * \file + * + * \brief Chip-specific sleep manager configuration + * + * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef CONF_SLEEPMGR_H +#define CONF_SLEEPMGR_H + +// Sleep manager options +#define CONFIG_SLEEPMGR_ENABLE + +#endif /* CONF_SLEEPMGR_H */ diff --git a/EVB-2/IS_EVB-2/src/config/conf_spi_master.h b/EVB-2/IS_EVB-2/src/config/conf_spi_master.h new file mode 100644 index 000000000..20d6fa495 --- /dev/null +++ b/EVB-2/IS_EVB-2/src/config/conf_spi_master.h @@ -0,0 +1,57 @@ +/** + * \file + * + * \brief Spi Master configuration. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef CONF_SPI_MASTER_H_INCLUDED +#define CONF_SPI_MASTER_H_INCLUDED + +/* Possibility to change low-level configurations here */ + +//! Default Config Spi Master Delay BCS +#define CONFIG_SPI_MASTER_DELAY_BCS 0 + +//! Default Config Spi Master Bits per Transfer Definition +#define CONFIG_SPI_MASTER_BITS_PER_TRANSFER 8 + +//! Default Config Spi Master Delay BCT +#define CONFIG_SPI_MASTER_DELAY_BCT 0 + +//! Default Config Spi Master Delay BS +#define CONFIG_SPI_MASTER_DELAY_BS 0 + +//! Default Config Spi Master Dummy Field +#define CONFIG_SPI_MASTER_DUMMY 0xFF + +#endif /* CONF_SPI_MASTER_H_INCLUDED */ diff --git a/EVB-2/IS_EVB-2/src/config/conf_uart_serial.h b/EVB-2/IS_EVB-2/src/config/conf_uart_serial.h new file mode 100644 index 000000000..191662d1f --- /dev/null +++ b/EVB-2/IS_EVB-2/src/config/conf_uart_serial.h @@ -0,0 +1,51 @@ +/** + * \file + * + * \brief USART Serial Configuration + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef CONF_USART_SERIAL_H +#define CONF_USART_SERIAL_H + +/** UART Interface */ +#define CONF_UART CONSOLE_UART +/** Baudrate setting */ +// #define CONF_UART_BAUDRATE (115200UL) +/** Character length setting */ +#define CONF_UART_CHAR_LENGTH US_MR_CHRL_8_BIT +/** Parity setting */ +#define CONF_UART_PARITY US_MR_PAR_NO +/** Stop bits setting */ +#define CONF_UART_STOP_BITS US_MR_NBSTOP_1_BIT + +#endif/* CONF_USART_SERIAL_H */ diff --git a/EVB-2/IS_EVB-2/src/config/conf_usart_spi.h b/EVB-2/IS_EVB-2/src/config/conf_usart_spi.h new file mode 100644 index 000000000..24ffcbfd6 --- /dev/null +++ b/EVB-2/IS_EVB-2/src/config/conf_usart_spi.h @@ -0,0 +1,40 @@ +/** + * \file + * + * \brief USART SPI Configuration. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef CONF_USART_SPI_H_INCLUDED +#define CONF_USART_SPI_H_INCLUDED + +#endif /* CONF_USART_SPI_H_INCLUDED */ diff --git a/EVB-2/IS_EVB-2/src/config/conf_usb.h b/EVB-2/IS_EVB-2/src/config/conf_usb.h new file mode 100644 index 000000000..4951cdd88 --- /dev/null +++ b/EVB-2/IS_EVB-2/src/config/conf_usb.h @@ -0,0 +1,168 @@ +/** + * \file + * + * \brief USB configuration file for CDC application + * + * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _CONF_USB_H_ +#define _CONF_USB_H_ +#if defined( __cplusplus ) +extern "C" { +#endif + +#include "compiler.h" +#include "usb_protocol_cdc.h" + +/** + * USB Device Configuration + * @{ + */ + +//! Device definition (mandatory) +#define USB_DEVICE_VENDOR_ID USB_VID_ATMEL +// #define USB_DEVICE_PRODUCT_ID USB_PID_ATMEL_ASF_CDC // "Communication Device Class ASF example" +#define USB_DEVICE_PRODUCT_ID 0x6124 // "Bossa Program Port" - This allows us to keep same serial port number when switching to SAM-BA mode +#define USB_DEVICE_MAJOR_VERSION 1 +#define USB_DEVICE_MINOR_VERSION 0 +#define USB_DEVICE_POWER 100 // Consumption on Vbus line (mA) +#define USB_DEVICE_ATTR \ + (USB_CONFIG_ATTR_SELF_POWERED) +// (USB_CONFIG_ATTR_BUS_POWERED) +// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_SELF_POWERED) +// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_BUS_POWERED) + +//! USB Device string definitions (Optional) +// #define USB_DEVICE_MANUFACTURE_NAME "Manufacture name" +// #define USB_DEVICE_PRODUCT_NAME "Product name" +// #define USB_DEVICE_SERIAL_NAME "12...EF" + + + +#if 0 // USB device low speed (1.5Mbit/s) +#define USB_DEVICE_LOW_SPEED +//#define USB_DEVICE_HS_SUPPORT +#elif 0 // USB device full speed (12Mbit/s) +//#define USB_DEVICE_LOW_SPEED +//#define USB_DEVICE_HS_SUPPORT +#else // USB device high speed (480Mbit/s) +//#define USB_DEVICE_LOW_SPEED +#define USB_DEVICE_HS_SUPPORT +#endif + + +/** + * USB Device Callbacks definitions (Optional) + * @{ + */ +// #define UDC_VBUS_EVENT(b_vbus_high) user_callback_vbus_action(b_vbus_high) +// extern void user_callback_vbus_action(bool b_vbus_high); +// #define UDC_SOF_EVENT() user_callback_sof_action() +// extern void user_callback_sof_action(void); +// #define UDC_SUSPEND_EVENT() user_callback_suspend_action() +// extern void user_callback_suspend_action(void); +// #define UDC_RESUME_EVENT() user_callback_resume_action() +// extern void user_callback_resume_action(void); +// Mandatory when USB_DEVICE_ATTR authorizes remote wakeup feature +// #define UDC_REMOTEWAKEUP_ENABLE() user_callback_remotewakeup_enable() +// extern void user_callback_remotewakeup_enable(void); +// #define UDC_REMOTEWAKEUP_DISABLE() user_callback_remotewakeup_disable() +// extern void user_callback_remotewakeup_disable(void); +// When a extra string descriptor must be supported +// other than manufacturer, product and serial string +// #define UDC_GET_EXTRA_STRING() +//@} + +//@} + + +/** + * USB Interface Configuration + * @{ + */ +/** + * Configuration of CDC interface + * @{ + */ + +//! Number of communication port used (1 to 3) +#define UDI_CDC_PORT_NB 1 + +//! Interface callback definition +#define UDI_CDC_ENABLE_EXT(port) true +// #define UDI_CDC_ENABLE_EXT(port) my_callback_cdc_enable() +// extern bool my_callback_cdc_enable(void); +//#define UDI_CDC_DISABLE_EXT(port) +#define UDI_CDC_DISABLE_EXT(port) d_usartDMA_callback_cdc_disable() +extern void d_usartDMA_callback_cdc_disable(void); +#define UDI_CDC_RX_NOTIFY(port) +// #define UDI_CDC_RX_NOTIFY(port) my_callback_rx_notify(port) +// extern void my_callback_rx_notify(uint8_t port); +#define UDI_CDC_TX_EMPTY_NOTIFY(port) +// #define UDI_CDC_TX_EMPTY_NOTIFY(port) my_callback_tx_empty_notify(port) +// extern void my_callback_tx_empty_notify(uint8_t port); +// #define UDI_CDC_SET_CODING_EXT(port,cfg) +#define UDI_CDC_SET_CODING_EXT(port,cfg) callback_cdc_set_config(port,cfg) +extern void callback_cdc_set_config(uint8_t port, usb_cdc_line_coding_t * cfg); +// #define UDI_CDC_SET_DTR_EXT(port,set) +#define UDI_CDC_SET_DTR_EXT(port,set) callback_cdc_set_dtr(port,set) +extern void callback_cdc_set_dtr(uint8_t port, bool b_enable); +#define UDI_CDC_SET_RTS_EXT(port,set) +// #define UDI_CDC_SET_RTS_EXT(port,set) callback_cdc_set_rts(port,set) +// extern void callback_cdc_set_rts(uint8_t port, bool b_enable); + +//! Define it when the transfer CDC Device to Host is a low rate (<512000 bauds) +//! to reduce CDC buffers size +//#define UDI_CDC_LOW_RATE + +//! Default configuration of communication port +#define UDI_CDC_DEFAULT_RATE 921600 +#define UDI_CDC_DEFAULT_STOPBITS CDC_STOP_BITS_1 +#define UDI_CDC_DEFAULT_PARITY CDC_PAR_NONE +#define UDI_CDC_DEFAULT_DATABITS 8 +//@} +//@} + + +/** + * USB Device Driver Configuration + * @{ + */ +//@} + +//! The includes of classes and other headers must be done at the end of this file to avoid compile error +#include "udi_cdc_conf.h" + +#if defined( __cplusplus ) +} +#endif +#endif // _CONF_USB_H_ diff --git a/EVB-2/IS_EVB-2/src/config/conf_winc.h b/EVB-2/IS_EVB-2/src/config/conf_winc.h new file mode 100644 index 000000000..c89a2a24e --- /dev/null +++ b/EVB-2/IS_EVB-2/src/config/conf_winc.h @@ -0,0 +1,108 @@ +/** + * + * \file + * + * \brief WINC3400 configuration. + * + * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef CONF_WINC_H_INCLUDED +#define CONF_WINC_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ISBoards.h" + +/** Settings for EVB-2. */ + +/* + --------------------------------- + ---------- PIN settings --------- + --------------------------------- +*/ + +#define CONF_WINC_PIN_RESET IOPORT_CREATE_PIN(PIOC, 21) +#define CONF_WINC_PIN_CHIP_ENABLE IOPORT_CREATE_PIN(PIOC, 22) +#define CONF_WINC_PIN_WAKE IOPORT_CREATE_PIN(PIOC, 31) //Not On Board + +/* + --------------------------------- + ---------- SPI settings --------- + --------------------------------- +*/ + +#define CONF_WINC_USE_SPI (1) + +/** SPI pin and instance settings. */ +#define CONF_WINC_SPI SPI1 +#define CONF_WINC_SPI_ID ID_SPI1 +#define CONF_WINC_SPI_MISO_GPIO PIO_PC26_IDX +#define CONF_WINC_SPI_MISO_FLAGS IOPORT_MODE_MUX_C +#define CONF_WINC_SPI_MOSI_GPIO PIO_PC27_IDX +#define CONF_WINC_SPI_MOSI_FLAGS IOPORT_MODE_MUX_C +#define CONF_WINC_SPI_CLK_GPIO PIO_PC24_IDX +#define CONF_WINC_SPI_CLK_FLAGS IOPORT_MODE_MUX_C +#define CONF_WINC_SPI_CS_GPIO PIO_PC25_IDX +#define CONF_WINC_SPI_CS_FLAGS IOPORT_MODE_MUX_C +#define CONF_WINC_SPI_NPCS (1) + +/** SPI delay before SPCK and between consecutive transfer. */ +#define CONF_WINC_SPI_DLYBS (0) +#define CONF_WINC_SPI_DLYBCT (0) + +/** SPI interrupt pin. */ +#define CONF_WINC_SPI_INT_PIN IOPORT_CREATE_PIN(PIOC, 23) +#define CONF_WINC_SPI_INT_PIO PIOC +#define CONF_WINC_SPI_INT_PIO_ID ID_PIOC +#define CONF_WINC_SPI_INT_MASK PIO_PC23 +#define CONF_WINC_SPI_INT_PRIORITY (0) + +/** Clock polarity & phase. */ +#define CONF_WINC_SPI_POL (0) +#define CONF_WINC_SPI_PHA (1) + +/** SPI clock: (sysclk_get_cpu_hz() / CONF_WINC_SPI_CLOCK). Beware of integer division. */ +#define CONF_WINC_SPI_CLOCK (48000000) + +/* + --------------------------------- + --------- Debug Options --------- + --------------------------------- +*/ + +#define CONF_WINC_DEBUG (0) +#define CONF_WINC_PRINTF //printf + +#ifdef __cplusplus +} +#endif + +#endif /* CONF_WINC_H_INCLUDED */ diff --git a/EVB-2/IS_EVB-2/src/drivers/d_adc.c b/EVB-2/IS_EVB-2/src/drivers/d_adc.c new file mode 100644 index 000000000..e5c1b2ad1 --- /dev/null +++ b/EVB-2/IS_EVB-2/src/drivers/d_adc.c @@ -0,0 +1,71 @@ +#include "asf.h" +#include "d_adc.h" + + +int afec0_init(void) +{ + static bool initialized = false; + if (initialized) + return 0; + //Configure AFEC unit + afec_enable(AFEC0); + struct afec_config afec_cfg; + afec_get_config_defaults(&afec_cfg); + afec_init(AFEC0, &afec_cfg); + afec_set_trigger(AFEC0, AFEC_TRIG_FREERUN); + initialized = true; + + return 0; +} + +int adc4_init(void) +{ + static bool initialized = false; + if (initialized) + return 0; + //Configure ADC channel + struct afec_ch_config afec_ch_cfg; + afec_ch_cfg.diff = false; + afec_ch_cfg.gain = AFEC_GAINVALUE_0; + afec_ch_set_config(AFEC0, AFEC_CHANNEL_4, &afec_ch_cfg); + afec_channel_set_analog_offset(AFEC0, AFEC_CHANNEL_4, 0x200); + afec_channel_enable(AFEC0, AFEC_CHANNEL_4); + + + //ioport_set_pin_input_mode(PIO_PE4_IDX, 0, 0); + //ioport_set_pin_input_mode(PIO_PD27_IDX, 0, 0); + ioport_set_pin_dir(PIO_PE4_IDX, IOPORT_DIR_INPUT); + + initialized = true; + + return 0; +} + +int adc1_init(void) +{ + static bool initialized = false; + if (initialized) + return 0; + + //Configure ADC channel + struct afec_ch_config afec_ch_cfg; + afec_ch_cfg.diff = false; + afec_ch_cfg.gain = AFEC_GAINVALUE_0; + afec_ch_set_config(AFEC0, AFEC_CHANNEL_1, &afec_ch_cfg); + afec_channel_set_analog_offset(AFEC0, AFEC_CHANNEL_1, 0x200); + afec_channel_enable(AFEC0, AFEC_CHANNEL_1); +// + //ioport_set_pin_input_mode(PIO_PA16_IDX, 0, 0); + //ioport_set_pin_input_mode(PIO_PA21_IDX, 0, 0); + ioport_set_pin_dir(PIO_PA21_IDX, IOPORT_DIR_INPUT); + + initialized = true; + + return 0; +} + +float adc_voltage(Afec *const afec, enum afec_channel_num afec_ch) +{ + volatile uint32_t data = afec_channel_get_value(afec, afec_ch); + return (float)data * ADC_VOLT_REF / ADC_MAX_DIGITAL / 1000.0f; +} diff --git a/EVB-2/IS_EVB-2/src/drivers/d_adc.h b/EVB-2/IS_EVB-2/src/drivers/d_adc.h new file mode 100644 index 000000000..cd6bae129 --- /dev/null +++ b/EVB-2/IS_EVB-2/src/drivers/d_adc.h @@ -0,0 +1,21 @@ +#ifndef D_ADC_H_ +#define D_ADC_H_ +#ifdef __cplusplus +extern "C" { +#endif + +// defines +#define ADC_VOLT_REF 3300 // reference voltage for AFEC in mV +#define ADC_MAX_DIGITAL 4096UL // the maximal digital value + +// prototypes +int afec0_init(void); +int adc4_init(void); +int adc1_init(void); + +float adc_voltage(Afec *const afec, enum afec_channel_num afec_ch); + +#ifdef __cplusplus +} +#endif +#endif // D_ADC_H_ diff --git a/EVB-2/IS_EVB-2/src/drivers/d_quadEnc.c b/EVB-2/IS_EVB-2/src/drivers/d_quadEnc.c new file mode 100644 index 000000000..c68c4696c --- /dev/null +++ b/EVB-2/IS_EVB-2/src/drivers/d_quadEnc.c @@ -0,0 +1,302 @@ +/* +MIT LICENSE + +Copyright 2014-2019 Inertial Sense, Inc. - http://inertialsense.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions : + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +#include +#include "d_quadEnc.h" +#include "conf_d_quadEnc.h" +#include "globals.h" + +//Use of index signal is not support at this time. Needs setup for pin and reading values +#define QDEC_USE_INDEX 0 + +static float s_tc2sec = 0.0f; +static bool s_direction_reverse_0 = 0; +static bool s_direction_reverse_1 = 0; + +static void quadEncSetModePosition(Tc *const timercounter, uint32_t ID_timercounter) +{ + //Enable the QDEC channel clocks + sysclk_enable_peripheral_clock(ID_timercounter); //Channel 0 +#if QDEC_USE_INDEX + sysclk_enable_peripheral_clock(ID_timercounter + 1); //Channel 1 +#endif + + //Init TC channel 0 to QDEC Position mode + tc_init(timercounter, 0, + TC_CMR_TCCLKS_XC0 + | TC_CMR_ETRGEDG_RISING /* To clear the counter on a rising edge of the TIOA signal*/ + | TC_CMR_ABETRG /* To select TIOA as a trigger for this channel 0 */ + ); + +#if QDEC_USE_INDEX + //Init TC channel 1 to QDEC Rotation mode + tc_init(timercounter, 1, + /* QDEC Clock Selection */ + TC_CMR_TCCLKS_XC0 + ); +#endif + + //Enable TC QDEC channel 0 in QDEC Position mode + tc_set_block_mode(timercounter, TC_BMR_QDEN /* QDEC mode enabled */ + | TC_BMR_POSEN /* Position measure is enabled */ + | TC_BMR_EDGPHA /* Detect quadrature on both PHA and PHB (4X decoding)*/ + | (0<< TC_BMR_MAXFILT_Pos) /* enable filter on input signal*/ + ); + + tc_start(timercounter, 0); //For position measurement +#if QDEC_USE_INDEX + tc_start(timercounter, 1); //For rotation measurement +#endif +} + +typedef struct +{ + uint32_t count; + uint32_t overflow; + uint32_t directionLast; + uint32_t running; + uint32_t timeMs; + uint32_t pulseCount; // Number of pulses accumulated in count + float period; +} capture_t; + +static capture_t capture[2] = {}; + +static void quadEncPeriodSetStopped(capture_t *c) +{ // Wheels are stationary or spinning very slowly + c->running = false; + c->count = 0; + c->pulseCount = 0; + c->period = 0.0f; +} + +// This wheel encoder works by +static inline void tc_encoder_handler(capture_t *c, Tc *p_tc, uint32_t ul_channel, uint32_t direction) +{ + uint32_t status = tc_get_status(p_tc, ul_channel); + + if (c->directionLast != direction) + { // Switched direction. Reset velocity measurements and indicate system is not running. + c->directionLast = direction; + quadEncPeriodSetStopped(c); + } + + if (status & TC_SR_COVFS) + { // Counter Overflow + c->overflow += 0x00010000; + } + + if (status & TC_SR_LDRAS) + { // RA Loading + uint32_t ra_count = tc_read_ra(p_tc, ul_channel); + if(c->running != 0) + { + c->count += c->overflow + ra_count; + c->pulseCount++; + } + else + { // First read after stopping is invalid + c->running = true; + c->count = 0; + c->pulseCount = 0; + } + + c->timeMs = time_msec(); + c->overflow = 0; + } +} + +void TCCAP0_SPD_Handler(void) +{ + tc_encoder_handler(&capture[0], TCCAP0_SPD, TCCAP0_SPD_CHANNEL, QE0_POS->TC_QISR & TC_QISR_DIR); +} + +void TCCAP1_SPD_Handler(void) +{ + tc_encoder_handler(&capture[1], TCCAP1_SPD, TCCAP1_SPD_CHANNEL, QE1_POS->TC_QISR & TC_QISR_DIR); +} + +static void quadEncSetModeSpeed(Tc *const timercounter, int timerchannel, int timerirq, uint32_t ID_timercounter, uint32_t pck6_pres) +{ + //Enable the TC channel clock + sysclk_enable_peripheral_clock(ID_timercounter); + + if(!pmc_is_pck_enabled(PMC_PCK_6)) + { + pmc_disable_pck(PMC_PCK_6); + pmc_switch_pck_to_mainck(PMC_PCK_6, PMC_PCK_PRES(pck6_pres)); + pmc_enable_pck(PMC_PCK_6); + } + + // Init TC to capture mode. + tc_init(timercounter, timerchannel, + TC_CMR_TCCLKS_TIMER_CLOCK1 /* Clock Selection */ + | TC_CMR_LDRA_RISING /* RA Loading: rising edge of TIOA */ + | TC_CMR_ABETRG /* External Trigger Source: TIOA */ + | TC_CMR_ETRGEDG_RISING /* External Trigger Edge: rising */ + ); + + // Setup capture and overflow interrupt + NVIC_DisableIRQ(timerirq); + NVIC_ClearPendingIRQ(timerirq); + NVIC_SetPriority(timerirq, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY-1); + NVIC_EnableIRQ(timerirq); + tc_enable_interrupt(timercounter, timerchannel, TC_IER_LDRAS | TC_IER_COVFS); + + tc_start(timercounter, timerchannel); +} + +void quadEncInit(uint32_t pck6_pres) +{ + /**** Configure pins ****/ + // Left Encoder - Position + ioport_set_pin_mode(PIN_QE0_POS_PHA, PIN_QE0_POS_PHA_MUX); + ioport_disable_pin(PIN_QE0_POS_PHA); + ioport_set_pin_mode(PIN_QE0_POS_PHB, PIN_QE0_POS_PHB_MUX); + ioport_disable_pin(PIN_QE0_POS_PHB); + + // Left Encoder - Speed + ioport_set_pin_mode(PIN_TCCAP0_SPD, PIN_TCCAP0_SPD_MUX); + ioport_disable_pin(PIN_TCCAP0_SPD); + + // Right Encoder - Position + ioport_set_pin_mode(PIN_QE1_POS_PHA, PIN_QE1_POS_PHA_MUX); + ioport_disable_pin(PIN_QE1_POS_PHA); + ioport_set_pin_mode(PIN_QE1_POS_PHB, PIN_QE1_POS_PHB_MUX); + ioport_disable_pin(PIN_QE1_POS_PHB); + + // Right Encoder - Speed + ioport_set_pin_mode(PIN_TCCAP1_SPD, PIN_TCCAP1_SPD_MUX); + ioport_disable_pin(PIN_TCCAP1_SPD); + + /**** Setup hardware ****/ + quadEncSetModePosition(QE0_POS, ID_QE0_POS); + quadEncSetModeSpeed(TCCAP0_SPD, TCCAP0_SPD_CHANNEL, TCCAP0_SPD_IRQn, ID_TCCAP0_SPD, pck6_pres); + + quadEncSetModePosition(QE1_POS, ID_QE1_POS); + quadEncSetModeSpeed(TCCAP1_SPD, TCCAP1_SPD_CHANNEL, TCCAP1_SPD_IRQn, ID_TCCAP1_SPD, pck6_pres); + + s_tc2sec = ((float)(pck6_pres+1)) / 12.0e6; +} + +void quadEncSetDirectionReverse( bool reverse_0, bool reverse_1 ) +{ + s_direction_reverse_0 = reverse_0; + s_direction_reverse_1 = reverse_1; +} + +void quadEncReadPositionAll(int *pos0, bool *dir0, int *pos1, bool *dir1) +{ + int16_t cv; + + taskENTER_CRITICAL(); + + cv = QE0_POS->TC_CHANNEL[0].TC_CV; + *pos0 = cv; + *dir0 = 0x1 && (QE0_POS->TC_QISR & TC_QISR_DIR); + + cv = QE1_POS->TC_CHANNEL[0].TC_CV; + *pos1 = cv; + *dir1 = 0x1 && (QE1_POS->TC_QISR & TC_QISR_DIR); + + // Reverse direction + if (s_direction_reverse_0) { *pos0 = -(*pos0); *dir0 = !(*dir0); } + if (s_direction_reverse_1) { *pos1 = -(*pos1); *dir1 = !(*dir1); } + + taskEXIT_CRITICAL(); +} + +static float quadEncReadPeriod(capture_t *c) +{ + if (c->running) + { + uint32_t dtMs = time_msec() - c->timeMs; + if (dtMs > 500) // 100ms timeout + // We might try scaling this timeout based on the minimum velocity and number of ticks per radian. We need to wait longer for lower resolution encoders. + // threshold = rad_per_tick * min_velocity * (125) Hoverbot ~500ms, ZT ~2ms + { + quadEncPeriodSetStopped(c); + } + } + + if (c->pulseCount) + { + c->period = s_tc2sec * (float)(c->count) / (float)(c->pulseCount); + c->count = 0; + c->pulseCount = 0; + } +// else +// { +// c->period = 0.0f; +// } + + return c->period; +} + +void quadEncReadPeriodAll(float *period0, float *period1) +{ + // g_debug.i[4] = capture[0].pulseCount; + // g_debug.i[5] = capture[1].pulseCount; + + taskENTER_CRITICAL(); + + *period0 = quadEncReadPeriod(&capture[0]); + *period1 = quadEncReadPeriod(&capture[1]); + + taskEXIT_CRITICAL(); + + // g_debug.i[0] = capture[0].count; + // g_debug.i[1] = capture[1].count; + // g_debug.i[2] = capture[0].overflow; + // g_debug.i[3] = capture[1].overflow; + // g_debug.f[0] = *period0 * 1000.0; + // g_debug.f[1] = *period1 * 1000.0; +} + +void test_quad_encoders(void) +{ +#if 0 //quadEnc testing + + udi_cdc_write_buf("Running\r\n", 9); + quadEncInit(239); + + while(1) + { + #define BUF_SIZE 100 + char str[BUF_SIZE]; + int chL, chR; + bool dirL, dirR; + float periodL, periodR; + + quadEncReadPositionAll(&chL, &dirL, &chR, &dirR); + quadEncReadPeriodAll(&periodL, &periodR); + + // Set velocity direction + if(dirL) + { + periodL = -periodL; + } + if(dirR) + { + periodR = -periodR; + } + + int len = SNPRINTF(str, BUF_SIZE, "ch0 %c %7d %7.4f ch1 %c %7d %7.4f\r\n", + dirL ? 'R':'F', chL, periodL, + dirR ? 'R':'F', chR, periodR); + udi_cdc_write_buf(str, len); + + vTaskDelay(200); + } + +#endif //END quadEnc testing +} diff --git a/EVB-2/IS_EVB-2/src/drivers/d_quadEnc.h b/EVB-2/IS_EVB-2/src/drivers/d_quadEnc.h new file mode 100644 index 000000000..dba396299 --- /dev/null +++ b/EVB-2/IS_EVB-2/src/drivers/d_quadEnc.h @@ -0,0 +1,46 @@ +/* +MIT LICENSE + +Copyright 2014-2019 Inertial Sense, Inc. - http://inertialsense.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions : + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + + +#ifndef D_QUADENC_H_ +#define D_QUADENC_H_ + +#define QE_LEFT_WHEEL 0 +#define QE_RIGHT_WHEEL 1 + +#ifdef __cplusplus + extern "C" { +#endif + +/** + * \brief Initialize quadrature encoder driver. + */ +void quadEncInit(uint32_t pck6_pres); + +/** + * \brief Apply a direction reversal to encoder output. + */ +void quadEncSetDirectionReverse( bool reverse_0, bool reverse_1 ); + +/** + * \brief Reads the current position of the encoders. + */ +void quadEncReadPositionAll(int *pos0, bool *dir0, int *pos1, bool *dir1); +void quadEncReadPeriodAll(float *period0, float *period1); + +void test_quad_encoders(void); + +#ifdef __cplusplus + } +#endif + +#endif /* D_QUADENC_H_ */ \ No newline at end of file diff --git a/EVB-2/IS_EVB-2/src/drivers/d_timer.c b/EVB-2/IS_EVB-2/src/drivers/d_timer.c new file mode 100644 index 000000000..c378a39fa --- /dev/null +++ b/EVB-2/IS_EVB-2/src/drivers/d_timer.c @@ -0,0 +1,344 @@ +#include +#include +#include "d_timer.h" +#ifdef ENABLE_TC_WAVEFORM_INTERRUPT +#include "conf_interrupts.h" +#endif // ENABLE_TC_WAVEFORM_INTERRUPT +// #include "globals.h" +#include "misc/debug_gpio.h" + +#ifdef DEBUG +//#define TIMER_DEBUG +//#define TIMER_IO_DEBUG +#endif // DEBUG + +#ifdef TIMER_IO_DEBUG +#define TIMER_PIN GPIO_8_PIN +#endif // TIMER_IO_DEBUG + +// source based on example acquired from: +// https://github.com/avrxml/asf/blob/master/sam/drivers/tc/tc_capture_waveform_example + + +//---------------------------------------- +// waveform mode +//---------------------------------------- +// The last one is meaningless +static const uint32_t g_divisors[5] = { 2, 8, 32, 128, 0 }; +static void (*g_wvf_callback)(void) = NULL; +static unsigned int g_wvf_channel; + +static void timer_io_enable(void) +{ +#ifdef TIMER_IO_DEBUG +//#if (BOARD == SAME70_XPLAINED) +// ioport_set_pin_mode(PIN_TC0_TIOA0, PIN_TC0_TIOA0_MUX); +// ioport_disable_pin(PIN_TC0_TIOA0); +//#endif // BOARD + ioport_set_pin_dir(TIMER_PIN, IOPORT_DIR_OUTPUT); + ioport_set_pin_level(TIMER_PIN, 0); +#endif // TIMER_IO_DEBUG +} + + +#ifdef ENABLE_TC_WAVEFORM_INTERRUPT +#ifdef TIMER_DEBUG +#include "d_time.h" +static uint32_t g_times[TC_SAMPLE_SENSORS_RATE_HZ+1]; + +static inline void timer_report(void) +{ + uint32_t k; + uint32_t sum = 0; + uint32_t diffs = 0; + uint32_t diff; + + for (k=1; k g_times[k-1]) + { + sum += g_times[k] - g_times[k-1]; + diffs++; + } + } + //printf("diffs=%04u sum=%u\r\n", (unsigned int)diffs, (unsigned int)sum); + printf("avg=%u us expected=%u us\r\n", + (unsigned int)((sum/TIME_TICKS_PER_US)/diffs), + (unsigned int)(1000000.0/(TC_SAMPLE_SENSORS_RATE_HZ*1.0))); + diff = g_times[TC_SAMPLE_SENSORS_RATE_HZ]-g_times[0]; + printf("t0=%u t%d=%u diff=%u\r\n", + (unsigned int)g_times[0], + TC_SAMPLE_SENSORS_RATE_HZ, + (unsigned int)g_times[TC_SAMPLE_SENSORS_RATE_HZ], + (unsigned int)diff); +} +#endif // TIMER_DEBUG + + +static void timer_register_callback(void (*func)(void)) +{ + g_wvf_callback = func; +} + + + +void TC_SAMPLE_SENSORS_HANDLER(void) +{ + if (tc_get_status(TC0, TC_SAMPLE_SENSORS_CHANNEL) & TC_IMR_CPCS) + { + tc_disable_interrupt(TC0, TC_SAMPLE_SENSORS_CHANNEL, TC_IDR_CPCS); + NVIC_DisableIRQ(TC_SAMPLE_SENSORS_IRQn); + NVIC_ClearPendingIRQ(TC_SAMPLE_SENSORS_IRQn); + if (g_wvf_callback) + (*g_wvf_callback)(); + NVIC_EnableIRQ(TC_SAMPLE_SENSORS_IRQn); + tc_enable_interrupt(TC0, TC_SAMPLE_SENSORS_CHANNEL, TC_IER_CPCS); + } +} +#endif // ENABLE_TC_WAVEFORM_INTERRUPT + + +void timer_waveform_init(unsigned int channel, void (*func)(void)) +{ + uint32_t ra, rc; + waveconfig_t wvf = {TC_CMR_TCCLKS_TIMER_CLOCK2, TC_SAMPLE_SENSORS_RATE_HZ, 50}; + + g_wvf_channel = channel; + g_wvf_callback = func; + + timer_io_enable(); + + // Configure the PMC to enable the TC module. + sysclk_enable_peripheral_clock(TC_SAMPLE_SENSORS_ID); + +#if SAMG55 + // Enable PCK output + pmc_disable_pck(PMC_PCK_3); + pmc_switch_pck_to_mck(PMC_PCK_3, PMC_PCK_PRES(0)); + pmc_enable_pck(PMC_PCK_3); +#endif // SAMG55 + + // Init TC to waveform mode. + tc_init(TC0, g_wvf_channel, + wvf.ul_intclock // Waveform Clock Selection + | TC_CMR_WAVE // Waveform mode is enabled + | TC_CMR_ACPA_SET // RA Compare Effect: set + | TC_CMR_ACPC_CLEAR // RC Compare Effect: clear + | TC_CMR_CPCTRG // UP mode with automatic trigger on RC Compare + ); + + // Configure waveform frequency and duty cycle. + rc = (sysclk_get_peripheral_bus_hz(TC0) / g_divisors[wvf.ul_intclock]) / wvf.us_frequency; + tc_write_rc(TC0, g_wvf_channel, rc); + ra = (100 - wvf.us_dutycycle) * rc / 100; + tc_write_ra(TC0, g_wvf_channel, ra); + +#ifdef ENABLE_TC_WAVEFORM_INTERRUPT + timer_register_callback(func); + tc_disable_interrupt(TC0, g_wvf_channel, TC_IDR_CPCS); + NVIC_DisableIRQ(TC_SAMPLE_SENSORS_IRQn); + NVIC_ClearPendingIRQ(TC_SAMPLE_SENSORS_IRQn); + NVIC_SetPriority(TC_SAMPLE_SENSORS_IRQn, INT_PRIORITY_TC); + NVIC_EnableIRQ(TC_SAMPLE_SENSORS_IRQn); + tc_enable_interrupt(TC0, g_wvf_channel, TC_IER_CPCS); +#endif // ENABLE_TC_WAVEFORM_INTERRUPT + +#ifdef TIMER_DEBUG + printf("rc: %u, ra: %u\r\n", (unsigned int)rc, (unsigned int)ra); + printf("Start waveform: Frequency = %d Hz,Duty Cycle = %2d%%\n\r", + wvf.us_frequency, wvf.us_dutycycle); +#endif // TIMER_DEBUG +} + + +//---------------------------------------- +// capture mode +//---------------------------------------- +static int g_capture_initialized; +#ifdef ENABLE_TC_CAPTURE_INTERRUPT +static uint32_t g_captured; +extern void gps_sync_int_handler(int index, int addTimeSinceTrigger); + + +void TC_TIME_SYNC_HANDLER(void) +{ + uint32_t status = tc_get_status(TC0, TC_TIME_SYNC_CHANNEL); + + if (status & TC_TIME_SYNC_IER_MASK) + { +#if 0 + if (TC_CAPTURE_IER_MASK & TC_IER_LDRAS) + g_captured = tc_read_ra(TC0, TC_CAPTURE_CHANNEL); + else + g_captured = tc_read_cv(TC0, TC_CAPTURE_CHANNEL); + + if (!(g_nvmFlashCfg->sysCfgBits & SYS_CFG_BITS_DISABLE_LEDS) && g_sysParams.hStatus&HDW_STATUS_GPS_SATELLITE_RX) + { + LEDS_GPS_PULSE(); + g_led.gps_timeMs = g_gpsTimeOfWeekMs; + } +#else + gps_sync_int_handler(0,1); +#endif // 0 + } +} +#endif // ENABLE_TC_CAPTURE_INTERRUPT + + +int timer_capture_enable(void) +{ + if (!g_capture_initialized) + return -1; + +#ifdef ENABLE_TC_CAPTURE_INTERRUPT + tc_enable_interrupt(TC0, TC_TIME_SYNC_CHANNEL, TC_TIME_SYNC_IER_MASK); +#endif // ENABLE_TC_CAPTURE_INTERRUPT + tc_start(TC0, TC_TIME_SYNC_CHANNEL); + + return 0; +} + + +int timer_capture_disable(void) +{ + if (!g_capture_initialized) + return -1; + +#ifdef ENABLE_TC_CAPTURE_INTERRUPT + tc_disable_interrupt(TC0, TC_TIME_SYNC_CHANNEL, TC_TIME_SYNC_IER_MASK); +#endif // ENABLE_TC_CAPTURE_INTERRUPT + tc_stop(TC0, TC_TIME_SYNC_CHANNEL); + + return 0; +} + + +void timer_capture_init(void) +{ + if (g_capture_initialized) + return; + + // Configure the PMC to enable the TC module. + sysclk_enable_peripheral_clock(TC_TIME_SYNC_ID); + +#if SAMG55 + // Enable PCK output + pmc_disable_pck(PMC_PCK_3); + pmc_switch_pck_to_mck(PMC_PCK_3, PMC_PCK_PRES(0)); + pmc_enable_pck(PMC_PCK_3); +#endif // SAMG55 + + // Init TC to capture mode. + tc_init(TC0, TC_TIME_SYNC_CHANNEL, + TC_CMR_TCCLKS_TIMER_CLOCK2 // Clock Selection + | TC_CMR_LDRA_RISING // RA Loading: rising edge of TIOA + | TC_CMR_ABETRG // External Trigger: TIOA + | TC_CMR_ETRGEDG_RISING // External Trigger Edge: Rising edge + ); + +#ifdef ENABLE_TC_CAPTURE_INTERRUPT + tc_disable_interrupt(TC0, TC_TIME_SYNC_CHANNEL, TC_TIME_SYNC_IER_MASK); + NVIC_DisableIRQ(TC_TIME_SYNC_IRQn); + NVIC_ClearPendingIRQ(TC_TIME_SYNC_IRQn); + NVIC_SetPriority(TC_TIME_SYNC_IRQn, INT_PRIORITY_TC); + NVIC_EnableIRQ(TC_TIME_SYNC_IRQn); + tc_enable_interrupt(TC0, TC_TIME_SYNC_CHANNEL, TC_TIME_SYNC_IER_MASK); +#endif // ENABLE_TC_CAPTURE_INTERRUPT + + tc_start(TC0, TC_TIME_SYNC_CHANNEL); + + g_capture_initialized = 1; +} + + +uint32_t timer_captured(void) +{ +#ifdef ENABLE_TC_CAPTURE_INTERRUPT + return g_captured; +#else + tc_stop(TC0, TC_TIME_SYNC_CHANNEL); + return tc_read_ra(TC0, TC_TIME_SYNC_CHANNEL); +#endif // ENABLE_TC_CAPTURE_INTERRUPT +} + + +//---------------------------------------- +// time timer +//---------------------------------------- +static uint16_t g_rollover = 0; + + +void TC_TIME_HANDLER(void) +{ + if (tc_get_status(TC3, TC_TIME_CHANNEL) & TC_IMR_CPCS) + { + g_rollover++; + } +} + + +volatile uint64_t time_cv(void) +{ + union + { + uint16_t u16[4]; + uint64_t u64; + } ticks; + + ticks.u16[3] = g_rollover; + ticks.u16[2] = (uint16_t) tc_read_cv(TC3, 2); + ticks.u16[1] = (uint16_t) tc_read_cv(TC3, 1); + ticks.u16[0] = (uint16_t) tc_read_cv(TC3, 0); + + return ticks.u64; +} + + +static void time_channel_init(uint32_t channel, uint32_t intclock) +{ + // Configure the PMC to enable the TC module. + sysclk_enable_peripheral_clock(TC_TIME_BASE_ID + channel); + + // Init TC to waveform mode. + tc_init(TC3, channel, + intclock // Waveform Clock Selection + | TC_CMR_WAVE // Waveform mode is enabled + | TC_CMR_WAVSEL_UP // WAVSEL = 00 without Trigger + | TC_CMR_ACPA_CLEAR // RA Compare Effect: clear + | TC_CMR_ACPC_SET // RC Compare Effect: set + | TC_CMR_CPCTRG // UP mode with automatic trigger on RC Compare + ); + + // Configure waveform frequency and duty cycle. + tc_write_ra(TC3, channel, 0xFF); + tc_write_rc(TC3, channel, 0xFFFF); +} + + +void timer_time_init(void) +{ +#ifdef ENABLE_TC_WAVEFORM_INTERRUPT + time_channel_init(0, TC_CMR_TCCLKS_TIMER_CLOCK2); + time_channel_init(1, TC_CMR_TCCLKS_XC1); + time_channel_init(2, TC_CMR_TCCLKS_XC2); + + tc_set_block_mode(TC3, + TC_BMR_TC1XC1S_TIOA0 | // select TIOA0 as external clock signal for channel 1 + TC_BMR_TC2XC2S_TIOA1); // select TIOA1 as external clock signal for channel 2 + + // the last channel will generate an interrupt for rollover + tc_disable_interrupt(TC3, TC_TIME_CHANNEL, TC_IDR_CPCS); + NVIC_DisableIRQ(TC_TIME_IRQn); + NVIC_ClearPendingIRQ(TC_TIME_IRQn); + NVIC_SetPriority(TC_TIME_IRQn, INT_PRIORITY_TC); + NVIC_EnableIRQ(TC_TIME_IRQn); + tc_enable_interrupt(TC3, TC_TIME_CHANNEL, TC_IER_CPCS); + + tc_start(TC3, 2); + tc_start(TC3, 1); + tc_start(TC3, 0); + + uint32_t previous_time = tc_read_cv(TC3, 0); + while (previous_time == tc_read_cv(TC3, 0)); +#endif +} diff --git a/EVB-2/IS_EVB-2/src/drivers/d_timer.h b/EVB-2/IS_EVB-2/src/drivers/d_timer.h new file mode 100644 index 000000000..3c97e8205 --- /dev/null +++ b/EVB-2/IS_EVB-2/src/drivers/d_timer.h @@ -0,0 +1,64 @@ +#ifndef _D_TIMER_H_ +#define _D_TIMER_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef NDEBUG + +// enable additional timer interrupts, release mode only, makes debugging impossible +#define ENABLE_TC_WAVEFORM_INTERRUPT +#define ENABLE_TC_CAPTURE_INTERRUPT + +#endif + +// NOTE: TC2_IRQn is the IRQ id for TC0 channel 2 not for TC2 +// see datasheet table on "peripheral identifiers" + +#define TC_SAMPLE_SENSORS_CHANNEL 0 +#define TC_SAMPLE_SENSORS_ID ID_TC0 +#define TC_SAMPLE_SENSORS_HANDLER TC0_Handler +#define TC_SAMPLE_SENSORS_IRQn TC0_IRQn +#define TC_SAMPLE_SENSORS_RATE_HZ 8000 + +// according to SAMS70 doc 46.5.1 +// PA15 & PA16 (GPS# TPULSE) are on channel 1 +#define TC_TIME_SYNC_CHANNEL 1 +#define TC_TIME_SYNC_ID ID_TC1 +#define TC_TIME_SYNC_HANDLER TC1_Handler +#define TC_TIME_SYNC_IRQn TC1_IRQn +#define TC_TIME_SYNC_IER_MASK TC_IER_LDRAS +//#define TC_TIME_SYNC_IER_MASK TC_IER_ETRGS + +//#define TC_TIME_SYNC_TICKS_TO_SEC (0.000030517578125) // 1/32768 based on SLCK +#define TC_TIME_SYNC_TICKS_TO_SEC (5.3333333333333333333333333333333e-8) // 8/150,000,000 based on MCK/8 + +#define TC_TIME_BASE_ID ID_TC9 +#define TC_TIME_CHANNEL 2 +#define TC_TIME_HANDLER TC9_Handler +#define TC_TIME_IRQn TC9_IRQn + +// typedefs +typedef struct +{ + /** Internal clock signals selection. */ + uint32_t ul_intclock; + /** Waveform frequency (in Hz). */ + uint32_t us_frequency; + /** Duty cycle in percent (positive).*/ + uint16_t us_dutycycle; +} waveconfig_t; + +// prototypes +void timer_waveform_init(unsigned int channel, void (*func)(void)); +void timer_capture_init(void); +int timer_capture_enable(void); +int timer_capture_disable(void); +uint32_t timer_captured(void); +void timer_time_init(void); +volatile uint64_t time_cv(void); + +#ifdef __cplusplus +} +#endif +#endif // _D_TIMER_H_ diff --git a/EVB-2/IS_EVB-2/src/evb_tasks.cpp b/EVB-2/IS_EVB-2/src/evb_tasks.cpp new file mode 100644 index 000000000..8c30fc494 --- /dev/null +++ b/EVB-2/IS_EVB-2/src/evb_tasks.cpp @@ -0,0 +1,261 @@ +/* +MIT LICENSE + +Copyright 2014-2019 Inertial Sense, Inc. - http://inertialsense.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions : + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +#include "evb_tasks.h" +#include "d_i2c.h" +#include "init.h" + +is_comm_instance_t& evbTaskCommInit(void *pvParameters) +{ + UNUSED(pvParameters); + static uint8_t comm_buffer[PKT_BUF_SIZE]; + is_comm_init(&g_commTx, comm_buffer, PKT_BUF_SIZE); + +#ifdef CONF_BOARD_CAN_TEST + //if(/*g_can_test == CAN_TEST_MASTER - or something like that*/ 1) + //mcan_test_master(); + if(/*g_can_test == CAN_TEST_SLAVE - or something like that*/ 1) + mcan_test_slave(); +#endif + + // Start USB CDC after everything is running +#ifdef USB_PORT_NUM + serInit(USB_PORT_NUM, 0, NULL); +#endif + + vTaskDelay(200); + evbUiRefreshLedCfg(); + + return g_commTx; +} + + +void evbTaskComm(rtos_task_t &task, is_comm_instance_t &comm) +{ + vTaskDelay(task.periodMs); + + g_comm_time = time_seclf(); + g_comm_time_ms = (uint32_t)round(g_comm_time * 1000.0); + + if (g_statusToWlocal) + { + g_status.timeOfWeekMs = g_comm_time_ms; + } + +#ifdef ENABLE_WDT + // Feed Watchdog to prevent reset + wdt_restart(WDT); +#endif + + // Turn off communications LEDs - first thing after vTaskDelay() + LED_OFF(LED_INS_RXD_PIN); + LED_OFF(LED_INS_TXD_PIN); + + // Forward data between communications ports + step_com_bridge(comm); + + // Sample wheel encoder output + step_wheel_encoder(comm); + + // Read buttons and update LEDs + step_user_interface(g_comm_time_ms); + + // Stream DIDs data sets + step_broadcast_data(&comm); +} + + +is_comm_instance_t& evbTaskLoggerInit(void *pvParameters) +{ + UNUSED(pvParameters); + static is_comm_instance_t comm; + static uint8_t comm_buffer[PKT_BUF_SIZE]; + is_comm_init(&comm, comm_buffer, PKT_BUF_SIZE); + + vTaskDelay(200); + LED_LOG_OFF(); + vTaskDelay(800); + +#if STREAM_INS_FOR_TIME_SYNC // Stream INS message on startup. Necessary to update EVB RTC for correct data log date and time. + //uINS_stream_stop_all(comm); + //uINS_stream_enable_std(comm); +#endif + + return comm; +} + + +void evbTaskLogger(rtos_task_t &task, is_comm_instance_t &comm) +{ + static cISLogger logger = {}; + + vTaskDelay(task.periodMs); + + step_logger_control(logger, comm); + + // Ready uINS data from com task. Log to file. + log_IMX_data(logger, comm); + + // Mount/unmount SD card + sd_card_maintenance(); + + evbUiRefreshLedLog(); +} + + +void evbTaskMaintInit(void *pvParameters) +{ + UNUSED(pvParameters); + + g_rtos.task[TASK_IDLE].handle = (uint32_t)xTaskGetIdleTaskHandle(); +} + +int evbTaskMaint(rtos_task_t &task) +{ + static uint32_t m2sPeriodMs = 0; + + vTaskDelay(task.periodMs); + + ////////////////////////////////////////////////////////////////////////// + // Fast Maintenance - 10ms period + evbUiRefreshLedCfg(); + evbUiRefreshLedLog(); + + ////////////////////////////////////////////////////////////////////////// + // Slow Maintenance - 1000ms period + if ((m2sPeriodMs += TASK_MAINT_PERIOD_MS) > TASK_MAINT_SLOW_SEC_PERIOD_MS && !g_loggerEnabled) + { + m2sPeriodMs = 0; + + // Sync local time from uINS + time_sync_from_uINS(); + + // Update RTOS stats + if (g_enRtosStats) + { + rtos_monitor(EVB_RTOS_NUM_TASKS); + } + + if (g_imxBootloaderEnableTimeMs) + { // uINS bootloader mode enabled + if ( (g_comm_time_ms-g_imxBootloaderEnableTimeMs) > 180000 ) + { // Automatically disable uINS after 3 minutes + g_imxBootloaderEnableTimeMs = 0; + } + } + + return 1; + } + + return 0; +} + + +void evbMainInitBoard(void) +{ + //XDMAC channel interrupt enables do not get cleared by a software reset. Clear them before they cause issues. + XDMAC->XDMAC_GID = 0xFFFFFFFF; + for(int i=0;iXDMAC_CHID[i].XDMAC_CID = 0xFFFFFFFF; + } + + // Force USB to disconnect. Helps to make sure the USB port starts up correctly when debugging. + udc_stop(); + + // Initialize the SAM system + board_init(); + + // Init globals and flash parameters + globals_init(); +} + + +void evbMainInitNvr(void) +{ + nvr_init(); +} + + +void evbMainInitIO(void) +{ + // Hold config while resetting + if(!ioport_get_pin_level(BUTTON_CFG_PIN)) + { + g_flashCfg->cbPreset = EVB2_CB_PRESET_DEFAULT; + } + + board_IO_config(); + + // Setup user interface buttons and leds + evbUiDefaults(); +} + + +void evbMainInitComm(void) +{ + // Init hardware I/O, SD card logger, and communications + sd_card_logger_init(); + communications_init(); + +#ifdef CONF_BOARD_ADC + if (g_flashCfg->bits&EVB_CFG_BITS_ENABLE_ADC4) + { + afec0_init(); + adc4_init(); + } + if (g_flashCfg->bits&EVB_CFG_BITS_ENABLE_ADC10) + { + afec0_init(); + adc1_init(); + } +#endif +} + + +void evbMainInitRTOS(pdTASK_CODE pxTaskComm, + pdTASK_CODE pxTaskLogg, + pdTASK_CODE pxTaskWifi, + pdTASK_CODE pxTaskMant ) +{ + // Create RTOS tasks + createTask(EVB_TASK_COMMUNICATIONS, pxTaskComm, "COMM", TASK_COMM_STACK_SIZE, NULL, TASK_COMM_PRIORITY, TASK_COMM_PERIOD_MS, TASK_COMM_PERIOD_MS); + createTask(EVB_TASK_LOGGER, pxTaskLogg, "LOGGER", TASK_LOGGER_STACK_SIZE, NULL, TASK_LOGGER_PRIORITY, TASK_LOGGER_PERIOD_MS, TASK_LOGGER_PERIOD_MS); +#ifdef CONF_BOARD_SPI_ATWINC_WIFI // ATWINC WIFI + createTask(EVB_TASK_WIFI, pxTaskWifi, "WIFI", TASK_WIFI_STACK_SIZE, NULL, TASK_WIFI_PRIORITY, TASK_WIFI_PERIOD_MS, TASK_WIFI_PERIOD_MS); +#endif + createTask(EVB_TASK_MAINTENANCE, pxTaskMant, "MAINT", TASK_MAINT_STACK_SIZE, NULL, TASK_MAINT_PRIORITY, TASK_MAINT_PERIOD_MS, TASK_MAINT_PERIOD_MS); + strncpy(g_rtos.task[EVB_TASK_IDLE].name, "IDLE", MAX_TASK_NAME_LEN); + strncpy(g_rtos.task[EVB_TASK_TIMER].name, "TIMER", MAX_TASK_NAME_LEN); + strncpy(g_rtos.task[EVB_TASK_SPI_UINS_COM].name, "INSSPI", MAX_TASK_NAME_LEN); + +#ifdef ENABLE_WDT + // Setup Watchdog + uint32_t timeout_value = wdt_get_timeout_value(1000000, BOARD_FREQ_SLCK_XTAL); //Timeout in us, configured for 1 second. + wdt_init(WDT, WDT_MR_WDRSTEN | WDT_MR_WDDBGHLT, timeout_value, timeout_value); +#endif +} + + +int evbMain(void) +{ + // Start the scheduler + printf("Starting FreeRTOS\n\r"); + vTaskStartScheduler(); + + // Will only get here if there was insufficient memory to create the idle task. + return 0; +} + + + + diff --git a/EVB-2/IS_EVB-2/src/evb_tasks.h b/EVB-2/IS_EVB-2/src/evb_tasks.h new file mode 100644 index 000000000..4358d08b0 --- /dev/null +++ b/EVB-2/IS_EVB-2/src/evb_tasks.h @@ -0,0 +1,59 @@ +#include +#include +#include +#include + +#include "sd_mmc_mem.h" +#include "wifi.h" +#include "xbee.h" +#include "globals.h" +#include "communications.h" +#include "user_interface.h" +#include "sd_card_logger.h" +#include "wheel_encoder.h" +#include "CAN.h" +#include "drivers/d_adc.h" + +// RTOS Task Configuration +#define TASK_COMM_PERIOD_MS 1 +#define TASK_LOGGER_PERIOD_MS 1 +#define TASK_WIFI_PERIOD_MS 10 +#define TASK_MAINT_PERIOD_MS 10 +#define TASK_MAINT_SLOW_SEC_PERIOD_MS 1000 + +// #define TASK_COMM_STACK_SIZE (4096/sizeof(portSTACK_TYPE)) +#define TASK_COMM_STACK_SIZE (8192/sizeof(portSTACK_TYPE)) +#define TASK_MAINT_STACK_SIZE (4096/sizeof(portSTACK_TYPE)) +// #define TASK_LOGGER_STACK_SIZE (4096/sizeof(portSTACK_TYPE)) +#define TASK_LOGGER_STACK_SIZE (8192/sizeof(portSTACK_TYPE)) +#define TASK_WIFI_STACK_SIZE (2048/sizeof(portSTACK_TYPE)) + +#define TASK_COMM_PRIORITY (tskIDLE_PRIORITY + 4) // Highest +#define TASK_LOGGER_PRIORITY (tskIDLE_PRIORITY + 3) +#define TASK_WIFI_PRIORITY (tskIDLE_PRIORITY + 2) +#define TASK_MAINT_PRIORITY (tskIDLE_PRIORITY + 1) + +#undef printf +#define printf(...) +#define printf_mutex(...) + + +is_comm_instance_t& evbTaskCommInit(void *pvParameters); +void evbTaskComm(rtos_task_t &task, is_comm_instance_t &comm); + +is_comm_instance_t& evbTaskLoggerInit(void *pvParameters); +void evbTaskLogger(rtos_task_t &task, is_comm_instance_t &comm); + +void evbTaskMaintInit(void *pvParameters); +int evbTaskMaint(rtos_task_t &task); + +void evbMainInitBoard(void); +void evbMainInitNvr(void); +void evbMainInitIO(void); +void evbMainInitComm(void); +void evbMainInitRTOS(pdTASK_CODE pxTaskComm, + pdTASK_CODE pxTaskLogg, + pdTASK_CODE pxTaskWifi, + pdTASK_CODE pxTaskMant ); + +int evbMain(void); \ No newline at end of file diff --git a/EVB-2/IS_EVB-2/src/globals.c b/EVB-2/IS_EVB-2/src/globals.c new file mode 100644 index 000000000..6788d56c2 --- /dev/null +++ b/EVB-2/IS_EVB-2/src/globals.c @@ -0,0 +1,618 @@ +/* +MIT LICENSE + +Copyright 2014-2019 Inertial Sense, Inc. - http://inertialsense.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions : + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +#include +#include "ASF/common/components/wifi/winc3400/wifi_drv/socket/include/socket.h" +#include "d_flash.h" +#include "version/version.h" +#include "version/repositoryInfo.h" +#include "version/buildInfo.h" +#include "globals.h" + + +dev_info_t g_evbDevInfo = {0}; +wheel_encoder_t g_wheelEncoder = {0}; +uint32_t g_wheelEncoderTimeMs = 0; +evb_status_t g_status = {0}; +bool g_statusToWlocal = true; +evb_flash_cfg_t* g_flashCfg; +nvr_manage_t g_nvr_manage_config; +nvm_config_t g_userPage = {0}; +uins_msg_t g_uins = {0}; +imu_t g_imu = {0}; +uint32_t g_insUpdateTimeMs = 0; +uint32_t g_imuUpdateTimeMs = 0; +debug_array_t g_debug = {0}; +evb_rtos_info_t g_rtos = {0}; +date_time_t g_gps_date_time = {0}; +//uint32_t g_CANbaud_kbps = 500; +//uint32 g_can_receive_address = 0; +bool g_gpsTimeSync = false; +uint32_t g_comm_time_ms = 0; +double g_comm_time = 0; +double g_towOffset = 0; +bool g_loggerEnabled = false; +uint32_t g_imxBootloaderEnableTimeMs = 0; // 0 = disabled +bool g_enRtosStats = 0; +ermc_t g_ermc = {0}; + + +void globals_init(void) +{ + // Init Device Info struct + g_evbDevInfo.hardwareType = IS_HARDWARE_TYPE_EVB; + g_evbDevInfo.hardwareVer[0] = 2; + switch(g_hdw_detect) + { + default: + g_evbDevInfo.hardwareVer[1] = 0; + break; + case HDW_DETECT_VER_EVB_2_1_0: + case HDW_DETECT_VER_EVB_2_1_1: + g_evbDevInfo.hardwareVer[1] = 1; + break; + case HDW_DETECT_VER_EVB_2_2_0: + g_evbDevInfo.hardwareVer[1] = 2; + break; + } + switch(g_hdw_detect) + { + default: + g_evbDevInfo.hardwareVer[2] = 0; + break; + case HDW_DETECT_VER_EVB_2_0_1: + case HDW_DETECT_VER_EVB_2_1_1: + g_evbDevInfo.hardwareVer[2] = 1; + break; + } + g_evbDevInfo.hardwareVer[3] = 0; + + g_evbDevInfo.firmwareVer[0] = FIRMWARE_VERSION_CHAR0; // Major + g_evbDevInfo.firmwareVer[1] = FIRMWARE_VERSION_CHAR1; // Minor + g_evbDevInfo.firmwareVer[2] = FIRMWARE_VERSION_CHAR2; // Revision + g_evbDevInfo.firmwareVer[3] = FIRMWARE_VERSION_CHAR3; // firmware specific revision + + g_evbDevInfo.protocolVer[0] = PROTOCOL_VERSION_CHAR0; // in com_manager.h + g_evbDevInfo.protocolVer[1] = PROTOCOL_VERSION_CHAR1; + g_evbDevInfo.protocolVer[2] = PROTOCOL_VERSION_CHAR2; // in data_sets.h + g_evbDevInfo.protocolVer[3] = PROTOCOL_VERSION_CHAR3; + + g_evbDevInfo.repoRevision = REPO_HEAD_COUNT; + g_evbDevInfo.buildNumber = BUILD_NUMBER; + +#if defined(DEBUG) + g_evbDevInfo.buildType = 'd'; // Debug +#else + g_evbDevInfo.buildType = 'r'; // Release +#endif + +#if 0 + setBuildDateTimeFromCompileTime(g_evbDevInfo.buildDate, g_evbDevInfo.buildTime); +#else + g_evbDevInfo.buildYear = BUILD_DATE_YEAR-2000; + g_evbDevInfo.buildMonth = BUILD_DATE_MONTH; + g_evbDevInfo.buildDay = BUILD_DATE_DAY; + + g_evbDevInfo.buildHour = BUILD_TIME_HOUR; + g_evbDevInfo.buildMinute = BUILD_TIME_MINUTE; + g_evbDevInfo.buildSecond = BUILD_TIME_SECOND; + g_evbDevInfo.buildMillisecond = (uint8_t)BUILD_TIME_MILLISECOND; +#endif + + strncpy(g_evbDevInfo.manufacturer, "Inertial Sense INC", DEVINFO_MANUFACTURER_STRLEN); +} + + +void com_bridge_apply_preset_uins_com(evb_flash_cfg_t* cfg, uint8_t uinsComPort); +void com_bridge_apply_preset_uins_com(evb_flash_cfg_t* cfg, uint8_t uinsComPort) +{ + if(uinsComPort >= EVB2_PORT_COUNT) + { + return; + } + + if(uinsComPort != EVB2_PORT_USB) + { + cfg->cbf[uinsComPort] |= (1<cbf[EVB2_PORT_USB] |= (1<cbf[uinsComPort] |= (1<cbf[EVB2_PORT_SP330] |= (1<uinsComPort == uinsAuxPort) +// { // Using UINS-AUX as primary communication link. Skip this section. +// return; +// } + + if (uinsAuxPort >= EVB2_PORT_COUNT) + { // Port disabled + return; + } + + // XRadio Forwarding + if (uinsAuxPort != EVB2_PORT_XRADIO) + { + switch(cfg->cbPreset) + { + case EVB2_CB_PRESET_RS232: + case EVB2_CB_PRESET_RS232_XBEE: + case EVB2_CB_PRESET_RS422_WIFI: + cfg->cbf[uinsAuxPort] |= (1<cbf[EVB2_PORT_XRADIO] |= (1<cbPreset == EVB2_CB_PRESET_RS232_XBEE)) + { + cfg->cbf[uinsAuxPort] |= (1<cbf[EVB2_PORT_XBEE] |= (1<cbPreset == EVB2_CB_PRESET_RS422_WIFI)) + { + cfg->cbf[uinsAuxPort] |= (1<cbf[EVB2_PORT_WIFI] |= (1<cbPreset==EVB2_CB_PRESET_NA) + { // Do nothing + return; + } + + // Comm Bridge + memset(cfg->cbf, 0, sizeof(cfg->cbf)); // Clear com bridge settings + switch(cfg->cbPreset) + { + case EVB2_CB_PRESET_RS232: + case EVB2_CB_PRESET_RS232_XBEE: + case EVB2_CB_PRESET_RS422_WIFI: + com_bridge_apply_preset_uins_com(cfg, cfg->uinsComPort); // UINS communication port used for SD logging. + com_bridge_apply_preset_uins_aux(cfg, cfg->uinsAuxPort); // UINS auxiliary port used for RTK corrections. + break; + + case EVB2_CB_PRESET_SPI_RS232: + // SPI mode must be on port UINS1 + cfg->cbf[EVB2_PORT_UINS1] |= (1<cbf[EVB2_PORT_USB] |= (1<cbf[EVB2_PORT_UINS1] |= (1<cbf[EVB2_PORT_SP330] |= (1<cbf[EVB2_PORT_USB] |= (1<cbf[EVB2_PORT_XBEE] |= (1<cbf[EVB2_PORT_USB] |= (1<cbf[EVB2_PORT_SP330] |= (1<cbf[EVB2_PORT_USB] |= (1<cbf[EVB2_PORT_GPIO_H8] |= (1<cbf[EVB2_PORT_USB] |= (1<cbf[EVB2_PORT_XRADIO] |= (1<cbf[EVB2_PORT_USB] |= (1<cbf[EVB2_PORT_SP330] |= (1<cbf[EVB2_PORT_USB] |= (1<cbf[EVB2_PORT_GPIO_H8] |= (1<cbf[EVB2_PORT_USB] |= (1<cbf[EVB2_PORT_XRADIO] |= (1<cbf[EVB2_PORT_USB] |= (1<cbf[EVB2_PORT_BLE] |= (1<cbf[EVB2_PORT_UINS0] |= (1<cbf[EVB2_PORT_UINS0] |= (1<cbf[EVB2_PORT_USB] |= (1<cbf[EVB2_PORT_SP330] |= (1<cbf[EVB2_PORT_UINS1] |= (1<cbf[EVB2_PORT_CAN] |= (1<cbOptions = 0; + + // Tri-state uINS + switch(cfg->cbPreset) + { + case EVB2_CB_PRESET_NA: + case EVB2_CB_PRESET_ALL_OFF: + case EVB2_CB_PRESET_USB_HUB_RS232: + case EVB2_CB_PRESET_USB_HUB_RS422: + case EVB2_CB_PRESET_COUNT: + cfg->cbOptions |= EVB2_CB_OPTIONS_TRISTATE_UINS_IO; + break; + } + + // SP330 Options + switch(cfg->cbPreset) + { + case EVB2_CB_PRESET_RS422_WIFI: + case EVB2_CB_PRESET_USB_HUB_RS422: + cfg->cbOptions |= EVB2_CB_OPTIONS_SP330_RS422; + break; + } + + // XBee and WiFi Power Options + switch(cfg->cbPreset) + { + case EVB2_CB_PRESET_RS232_XBEE: + case EVB2_CB_PRESET_USB_HUB_RS232: + cfg->cbOptions |= EVB2_CB_OPTIONS_XBEE_ENABLE; + break; + + case EVB2_CB_PRESET_RS422_WIFI: + cfg->cbOptions |= EVB2_CB_OPTIONS_WIFI_ENABLE; + break; + } + + // Enable SPI example +#ifdef CONF_BOARD_SPI_UINS + switch(cfg->cbPreset) + { + case EVB2_CB_PRESET_SPI_RS232: + cfg->cbOptions |= EVB2_CB_OPTIONS_SPI_ENABLE; + break; + } +#endif + + // Enable CAN +//#ifdef CONF_BOARD_CAN1 + //switch(cfg->cbPreset) + //{ + //case EVB2_CB_PRESET_CAN: + //cfg->cbOptions |= EVB2_CB_OPTIONS_CAN_ENABLE; + //break; + //} +//#endif +} + + +void concatStringWithSpace(char* buf, size_t bufLen, const char* concat) +{ + if (bufLen > 0) + { + size_t len = strnlen(buf, bufLen); + if (len != 0 && len < bufLen - 1) + { + buf[len++] = ' '; + buf[len] = '\0'; + } + strncat(buf, concat, bufLen - len - 1); + } +} + + +bool nvr_validate_config_integrity(evb_flash_cfg_t* cfg) +{ + evb_flash_cfg_t defaults; + memset(&defaults, 0, sizeof(evb_flash_cfg_t)); + reset_evb_flash_cfg_defaults(&defaults); + + bool valid = true; + if (cfg->checksum != flashChecksum32(cfg, sizeof(evb_flash_cfg_t)) || cfg->key != defaults.key) + { // checksum failure + valid = false; + } + + if (error_check_evb_flash_cfg(cfg)) + { // Values are outside valid ranges + valid = false; + } + + // Flash Config + if (!valid) + { // Reset to defaults + *cfg = defaults; + nvr_flash_config_write_needed(); + nvr_flash_config_write_enable(); + } + + // Disable cbPresets is necessary +#ifndef CONF_BOARD_SPI_ATWINC_WIFI + if (cfg->cbPreset == EVB2_CB_PRESET_RS422_WIFI){ cfg->cbPreset = EVB2_CB_PRESET_DEFAULT; } +#endif +#ifndef CONF_BOARD_SPI_UINS + if (cfg->cbPreset == EVB2_CB_PRESET_SPI_RS232){ cfg->cbPreset = EVB2_CB_PRESET_DEFAULT; } +#endif + + return valid; +} + + +void nvr_init(void) +{ + // Initialize flash: 6 wait states for flash writing + uint32_t rc = flash_init(FLASH_ACCESS_MODE_128, 6); + configASSERT(rc == FLASH_RC_OK); + + g_flashCfg = &(g_userPage.g0.m); + + // Update RAM from FLASH + memcpy(&g_userPage, (void*)BOOTLOADER_FLASH_CONFIG_BASE_ADDRESS, sizeof(g_userPage)); + + // Disable flash writes. We require the user to initiate each write with this option. + g_nvr_manage_config.flash_write_enable_timeMs = 0; + g_status.evbStatus &= ~EVB_STATUS_FLASH_WRITE_IN_PROGRESS; + + // Reset to defaults if checksum or keys don't match + nvr_validate_config_integrity(g_flashCfg); +} + + +bool nvr_slow_maintenance(void) +{ + if (g_nvr_manage_config.flash_write_enable_timeMs==0) + { + return false; + } + + uint32_t dtMs = time_msec() - g_nvr_manage_config.flash_write_enable_timeMs; + if (dtMs < 1000) + { // Wait 1 second following flash_write_enable_timeMs + return false; + } + + bool flash_write = false; + + if (g_nvr_manage_config.flash_write_needed) + { + // Ensure flash config isn't larger than block + STATIC_ASSERT(sizeof(nvm_config_t) <= BOOTLOADER_FLASH_BLOCK_SIZE); + +#if 0 + + // copy contents, set migration marker and re-calculate checksums inside critical section + BEGIN_CRITICAL_SECTION + + nvm_config_t* copyOfRam = (nvm_config_t*)MALLOC(BOOTLOADER_FLASH_BLOCK_SIZE); + + // Copy config data, zero pad, update checksum + memcpy(copyOfRam, &g_userPage, sizeof(g_userPage)); + memset((uint8_t*)copyOfRam + sizeof(g_userPage), 0, BOOTLOADER_FLASH_BLOCK_SIZE - sizeof(g_userPage)); + copyOfRam->g0.m.checksum = flashChecksum32(copyOfRam, sizeof(evb_flash_cfg_t)); + + // Update userPage config + memcpy(&g_userPage, copyOfRam, sizeof(g_userPage)); + + END_CRITICAL_SECTION + + uint32_t address = BOOTLOADER_FLASH_CONFIG_BASE_ADDRESS; + uint32_t memsize = BOOTLOADER_FLASH_BLOCK_SIZE; +// uint32_t memsize = IFLASH_PAGE_SIZE; + +#if 0 + + if (flash_unlock(address, address + memsize - 1, 0, 0) == FLASH_RC_OK) + { + if (flash_erase_page(address, IFLASH_ERASE_PAGES_16) == FLASH_RC_OK) + { + if (flash_write(address, ©OfRam, memsize, 0) == FLASH_RC_OK) + { + if( flash_lock(address, address + memsize - 1, 0, 0) == FLASH_RC_OK) + { // indicate attempted flash write + g_nvr_manage_config.flash_write_count++; + } + } + } + } + +#else + // write to primary location + if( flash_update_block(address, copyOfRam, BOOTLOADER_FLASH_BLOCK_SIZE, 0) != FLASH_RC_OK) + { + // error + int j=0; + j++; + } + +#endif + + FREE(copyOfRam); + +#else + + BEGIN_CRITICAL_SECTION + + // calculate checksum + g_userPage.g0.m.size = sizeof(evb_flash_cfg_t); + g_userPage.g0.m.checksum = flashChecksum32(&g_userPage.g0.m, sizeof(evb_flash_cfg_t)); + +// flash_update_block(BOOTLOADER_FLASH_CONFIG_BASE_ADDRESS, &g_userPage, sizeof(nvm_config_t), 0); + flash_update_block(BOOTLOADER_FLASH_CONFIG_BASE_ADDRESS, &g_userPage, BOOTLOADER_FLASH_BLOCK_SIZE, 0); + + END_CRITICAL_SECTION + +#endif + + g_nvr_manage_config.flash_write_count++; + g_nvr_manage_config.flash_write_needed = 0; + // Disable following each flash write. We require users to re-enable for each write. + g_nvr_manage_config.flash_write_enable_timeMs = 0; + g_status.evbStatus &= ~EVB_STATUS_FLASH_WRITE_IN_PROGRESS; + flash_write = false; + } + + return flash_write; +} + + +void nvr_flash_config_write_needed(void) +{ + g_nvr_manage_config.flash_write_needed++; +} + + +// Used to enabled flash writes at controlled times. The system may identify when a flash write is needed. +// However, this will not occur until flash is enabled (at time EKF can tolerate stutters in RTOS update). +void nvr_flash_config_write_enable(void) +{ + g_nvr_manage_config.flash_write_enable_timeMs = time_msec(); + g_status.evbStatus |= EVB_STATUS_FLASH_WRITE_IN_PROGRESS; +} + + +// Returns 0 on success +int error_check_evb_flash_cfg(evb_flash_cfg_t *cfg) +{ + if(cfg == NULLPTR) + { + return -1; + } + + int failure = 0; + + if (cfg->radioPID > 9 || + cfg->radioNID > 0x7FFF || + cfg->radioPowerLevel > 2 ) + { + failure = -1; + } + if(EVB_CFG_BITS_IDX_WIFI(cfg->bits) >= NUM_WIFI_PRESETS) + { + EVB_CFG_BITS_SET_IDX_WIFI(cfg->bits,0); + failure = -1; + } + if(EVB_CFG_BITS_IDX_SERVER(cfg->bits) >= NUM_WIFI_PRESETS) + { + EVB_CFG_BITS_SET_IDX_SERVER(cfg->bits,0); + failure = -1; + } + + return failure; +} + + +void reset_evb_flash_cfg_defaults( evb_flash_cfg_t *cfg ) +{ + if (cfg == NULL) + return; + + memset(cfg, 0, sizeof(evb_flash_cfg_t)); + cfg->size = sizeof(evb_flash_cfg_t); + cfg->key = 3; // increment key to force config to revert to defaults (overwrites customer's settings) + + cfg->cbPreset = EVB2_CB_PRESET_DEFAULT; + + cfg->uinsComPort = EVB2_PORT_UINS0; // Default port for uINS communications and SD card logging + cfg->uinsAuxPort = EVB2_PORT_UINS0; // Default port for RTK corrections and wireless interface + cfg->portOptions = EVB2_PORT_OPTIONS_DEFAULT; // Enable radio RTK filter + cfg->h3sp330BaudRate = 921600; + cfg->h4xRadioBaudRate = 115200; + cfg->h8gpioBaudRate = 921600; + + cfg->radioPID = 2; // 0x0 to 0x9 + cfg->radioNID = 72; // 0x0 to 0x7FFF + cfg->radioPowerLevel = 0; // 0=20dBm use low power so radio can run from USB supply. 1=27dBm and 2=30dBm are too powerful for USB supply. + + cfg->server[0].ipAddr.u32 = nmi_inet_addr((void*)"69.167.49.43"); + cfg->server[0].port = 7778; + cfg->server[1].ipAddr.u32 = nmi_inet_addr((void*)"192.168.1.144"); + cfg->server[1].port = 2000; +// cfg->encoderTickToWheelRad = 0.0359998f; // Husqvarna lawnmower + cfg->encoderTickToWheelRad = 0.108329996f; // Husqvarna lawnmower + // cfg->encoderTickToWheelRad = 0.00523598775598298873f; // = 2 Pi / (400 count encoder x 3 gear ratio), (ZT mower) + + cfg->velocityControlPeriodMs = 50; // 20 Hz + + com_bridge_apply_preset(cfg); + + cfg->checksum = flashChecksum32(cfg, sizeof(evb_flash_cfg_t)); +} + + +void setBuildDateTimeFromCompileTime(uint8_t buildDate[4], uint8_t buildTime[4]) +{ + char date[20] = __DATE__; // mmm dd yyyy (e.g. "Jan 14 2012") + int day=0, month=0, year=0, hour=0, minute=0, second=0; + if (date[0] == 'J' && + date[1] == 'a' && + date[2] == 'n'){ month = 1; } // month + else if(date[0] == 'F' && + date[1] == 'e' && + date[2] == 'b'){ month = 2; } + else if(date[0] == 'M' && + date[1] == 'a' && + date[2] == 'r'){ month = 3; } + else if(date[0] == 'A' && + date[1] == 'p' && + date[2] == 'r'){ month = 4; } + else if(date[0] == 'M' && + date[1] == 'a' && + date[2] == 'y'){ month = 5; } + else if(date[0] == 'J' && + date[1] == 'u' && + date[2] == 'n'){ month = 6; } + else if(date[0] == 'J' && + date[1] == 'u' && + date[2] == 'l'){ month = 7; } + else if(date[0] == 'A' && + date[1] == 'u' && + date[2] == 'g'){ month = 8; } + else if(date[0] == 'S' && + date[1] == 'e' && + date[2] == 'p'){ month = 9; } + else if(date[0] == 'O' && + date[1] == 'c' && + date[2] == 't'){ month = 10; } + else if(date[0] == 'N' && + date[1] == 'o' && + date[2] == 'v'){ month = 11; } + else if(date[0] == 'D' && + date[1] == 'e' && + date[2] == 'c'){ month = 12; } + day = atoi(&date[4]); // day + year = atoi(&date[7]); // year + + char time[20] = __TIME__; // hh:mm:ss in 24 hour time (e.g. "22:29:12") + hour = atoi(&time[0]); // hour + minute = atoi(&time[3]); // minute + second = atoi(&time[6]); // second + + buildDate[1] = year - 2000; + buildDate[2] = month; + buildDate[3] = day; + + buildTime[0] = hour; + buildTime[1] = minute; + buildTime[2] = second; + buildTime[3] = 0; +} diff --git a/EVB-2/IS_EVB-2/src/globals.h b/EVB-2/IS_EVB-2/src/globals.h new file mode 100644 index 000000000..14c3d03f7 --- /dev/null +++ b/EVB-2/IS_EVB-2/src/globals.h @@ -0,0 +1,156 @@ +/* +MIT LICENSE + +Copyright 2014-2019 Inertial Sense, Inc. - http://inertialsense.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions : + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +#ifndef __GLOBALS_H_ +#define __GLOBALS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "ISComm.h" +#include "data_sets.h" +#include "ISConstants.h" +#include "bootloaderShared.h" +#include "rtos.h" +#include "d_serial.h" +#include "d_time.h" +#include "conf_board.h" + +#define USE_RTC_DATE_TIME 1 // Use RTC for system data and time + +#define STREAM_INS_FOR_TIME_SYNC 1 +#define SKI_BOX_STATUS_LED_PIN GPIO_10_PIN +#define UBLOX_LOG_ENABLE 0 + +// EVB Realtime Message Controller (ERMC) - message broadcast mechanism. +#define ERMC_BITS_DEV_INFO 0x0000000000000001 +#define ERMC_BITS_FLASH_CFG 0x0000000000000002 +#define ERMC_BITS_STATUS 0x0000000000000004 +#define ERMC_BITS_WHEEL_ENCODER 0x0000000000000008 +#define ERMC_BITS_DEBUG_ARRAY 0x0000000000000100 + + +typedef void (*VoidFuncPtrVoid)(void); + +PUSH_PACK_1 + +typedef struct +{ + uint32_t year, month, day, week, hour, minute, second; +} date_time_t; + +typedef struct +{ + dev_info_t uInsInfo; + ins_1_t ins1; + ins_2_t ins2; + inl2_states_t inl2States; + pimu_t pImu; + nvm_flash_cfg_t flashCfg; + bool refLlaValid; +} uins_msg_t; + +typedef struct PACKED // Non-volatile memory state +{ + uint32_t flash_write_needed; // 0=No write; 1=config write needed; 2=config write needed without backup 0xFFFFFFFF=reset defaults + uint32_t flash_write_count; // Number of times flash is written to since reset + uint32_t flash_write_enable_timeMs; // Local time when enabled. Flash will happen 1-2 seconds after this enable time. Reset to zero following flash write. +} nvr_manage_t; + +typedef struct PACKED // +{ + uint64_t bits; + uint32_t options; + uint32_t periodMultiple[DID_COUNT]; +} ermc_t; + +// All Flash Parameters - config max size is 8K for ARM +typedef struct PACKED +{ + union + { // Standard EVB-2 + evb_flash_cfg_t m; + uint32_t padding[BOOTLOADER_FLASH_BLOCK_SIZE / 2 / sizeof(uint32_t)]; // 4096 bytes + } g0; + + union + { // Reserved for Luna + uint32_t padding[BOOTLOADER_FLASH_BLOCK_SIZE / 2 / sizeof(uint32_t)]; // 4096 bytes + } g1; + +} nvm_config_t; + +POP_PACK + +// Defined in init.c +void init_set_board_IO_config_callback(VoidFuncPtrVoid fpIoCfg); +void refresh_led_cfg(void); +void board_IO_config(void); +// + +#define STREAM_BUFFER_SIZE 4096 + +extern uint8_t g_hdw_detect; +extern dev_info_t g_evbDevInfo; +extern wheel_encoder_t g_wheelEncoder; +extern uint32_t g_wheelEncoderTimeMs; +extern evb_status_t g_status; +extern bool g_statusToWlocal; +extern evb_flash_cfg_t* g_flashCfg; +extern nvr_manage_t g_nvr_manage_config; +extern nvm_config_t g_userPage; +extern uins_msg_t g_uins; +extern imu_t g_imu; +extern uint32_t g_insUpdateTimeMs; +extern uint32_t g_imuUpdateTimeMs; +extern debug_array_t g_debug; +extern evb_rtos_info_t g_rtos; +extern date_time_t g_gps_date_time; +//extern uint32_t g_CANbaud_kbps; +//extern uint32_t g_can_receive_address; +extern bool g_gpsTimeSync; +extern uint32_t g_comm_time_ms; +extern double g_comm_time; +extern double g_towOffset; +extern bool g_loggerEnabled; +extern uint32_t g_imxBootloaderEnableTimeMs; +extern bool g_enRtosStats; +extern ermc_t g_ermc; + +void globals_init(void); +void com_bridge_apply_preset(evb_flash_cfg_t* cfg); +void reset_evb_flash_cfg_defaults(evb_flash_cfg_t* cfg); +int comWrite(int serialNum, const unsigned char *buf, int size, uint32_t ledPin ); +int comRead(int serialNum, unsigned char *buf, int size, uint32_t ledPin); +void com_bridge_forward(uint32_t srcPort, uint8_t *buf, int len); +void com_bridge_smart_forward(uint32_t srcPort, uint32_t ledPin); +void concatStringWithSpace(char* buf, size_t bufLen, const char* concat); + +bool nvr_validate_config_integrity(evb_flash_cfg_t* cfg); +void nvr_init(void); +bool nvr_slow_maintenance(void); +void nvr_flash_config_write_needed(void); +void nvr_flash_config_write_enable(void); + +int error_check_evb_flash_cfg(evb_flash_cfg_t *cfg); + +void setBuildDateTimeFromCompileTime(uint8_t buildDate[4], uint8_t buildTime[4]); + +#define FLASH_WRITE_IN_PROGRESS() (g_nvr_manage_config.flash_write_enable_timeMs) + +#ifdef __cplusplus +} +#endif + +#endif // __GLOBALS_H_ diff --git a/EVB-2/IS_EVB-2/src/main.cpp b/EVB-2/IS_EVB-2/src/main.cpp new file mode 100644 index 000000000..a92543e8c --- /dev/null +++ b/EVB-2/IS_EVB-2/src/main.cpp @@ -0,0 +1,112 @@ +/* +MIT LICENSE + +Copyright 2014-2019 Inertial Sense, Inc. - http://inertialsense.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions : + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +#include "evb_tasks.h" + + +static void vTaskComm(void *pvParameters) +{ + rtos_task_t &task = g_rtos.task[EVB_TASK_COMMUNICATIONS]; + is_comm_instance_t &comm = evbTaskCommInit(pvParameters); + + while(1) + { + // EVB communications task + evbTaskComm(task, comm); + + ////////////////////////////////////////////////////////////////////////// + // Suggested USER CODE Section + // Update period: 1ms (Adjust by changing TASK_COMM_PERIOD_MS) + // Priority: high + // + // Ensure code added here does not run longer than 1ms. Consider + // adding code to vTaskMaint if it runs longer than 1ms and does not + // require a high priority. + + // Add code here... + ////////////////////////////////////////////////////////////////////////// + } +} + + +/** + * \brief RTOS logger task. + */ +static void vTaskLogger(void *pvParameters) +{ + rtos_task_t &task = g_rtos.task[EVB_TASK_LOGGER]; + is_comm_instance_t &comm = evbTaskLoggerInit(pvParameters); + + while(1) + { + // EVB logger task + evbTaskLogger(task, comm); + } +} + + +/** + * \brief RTOS maintenance task. + */ +static void vTaskMaint(void *pvParameters) +{ + rtos_task_t &task = g_rtos.task[EVB_TASK_MAINTENANCE]; + evbTaskMaintInit(pvParameters); + + for (;;) + { + if(evbTaskMaint(task)) + { + nvr_slow_maintenance(); + + ////////////////////////////////////////////////////////////////////////// + // Slow Maintenance - 1000ms period - Suggested USER CODE Section + // Update period: 1000ms (Adjust by changing TASK_MAINT_SUB_TASK_PERIOD_MS) + // Priority: low + // + // Consider adding code to vTaskComm if it needs to run faster than every + // 10ms or requires a higher priority. + + // Add code here... + ////////////////////////////////////////////////////////////////////////// + + //Test code for ADC + // g_debug.f[0] = adc_voltage(); + } + + ////////////////////////////////////////////////////////////////////////// + // Fast Maintenance - 10ms period - Suggested USER CODE Section + // Update period: 10ms (Adjust by changing TASK_MAINT_PERIOD_MS) + // Priority: low + // + // Consider adding code to vTaskComm if it needs to run faster than every + // 10ms or requires a higher priority. + + // Add code here... + ////////////////////////////////////////////////////////////////////////// + } +} + + +int main(void) +{ + evbMainInitBoard(); + evbMainInitNvr(); + evbMainInitIO(); + evbMainInitComm(); + evbMainInitRTOS(vTaskComm, vTaskLogger, vTaskWiFi, vTaskMaint); + + int result = evbMain(); + + // Will only get here if there was insufficient memory to create the idle task. + return result; +} diff --git a/EVB-2/IS_EVB-2/src/misc/init.c b/EVB-2/IS_EVB-2/src/misc/init.c new file mode 100644 index 000000000..db36e18e3 --- /dev/null +++ b/EVB-2/IS_EVB-2/src/misc/init.c @@ -0,0 +1,919 @@ +/** + * \file + * + * \brief SAME70-XPLD board init. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "compiler.h" +#include "ISBoards.h" +#include "conf_board.h" +#include "ioport.h" +#include "pio.h" +#include "data_sets.h" +#include "d_serial.h" +#include "CAN.h" +#include "d_time.h" +#include "spiTouINS.h" +#include "xbee.h" +#include "wifi.h" +#include "globals.h" +#include "init.h" +#ifdef CONF_BOARD_CONFIG_MPU_AT_INIT +#include "mpu.h" +#endif + + +/** + * \brief Set input mode for one single IOPORT pin. + * It will configure port mode and disable pin mode (but enable peripheral). + * The "ioport_enable_pin(pin);" line is necessary to allow tristate. (whj) + * \param pin IOPORT pin to configure + * \param mode Mode masks to configure for the specified pin (\ref ioport_modes) + * \param sense Sense for interrupt detection (\ref ioport_sense) + */ +#undef ioport_set_pin_input_mode +#define ioport_set_pin_input_mode(pin, mode, sense) \ + do {\ + ioport_enable_pin((pin));\ + ioport_set_pin_dir((pin), IOPORT_DIR_INPUT);\ + ioport_set_pin_mode((pin), (mode));\ + ioport_set_pin_sense_mode((pin), (sense));\ + } while (0) + + +#ifdef CONF_BOARD_CONFIG_MPU_AT_INIT +/** + * Default memory map + * Address range Memory region Memory type Shareability Cache policy + * 0x00000000- 0x1FFFFFFF Code Normal Non-shareable WT + * 0x20000000- 0x3FFFFFFF SRAM Normal Non-shareable WBWA + * 0x40000000- 0x5FFFFFFF Peripheral Device Non-shareable - + * 0x60000000- 0x7FFFFFFF RAM Normal Non-shareable WBWA + * 0x80000000- 0x9FFFFFFF RAM Normal Non-shareable WT + * 0xA0000000- 0xBFFFFFFF Device Device Shareable + * 0xC0000000- 0xDFFFFFFF Device Device Non Shareable + * 0xE0000000- 0xFFFFFFFF System - - + */ + +uint8_t g_hdw_detect; // (see eEvbHdwDetectVersion) +static VoidFuncPtrVoid s_pfnHandleBoardIoCfg = NULLPTR; + + +/** + * \brief Set up a memory region. + */ +static void _setup_memory_region( void ) +{ + + uint32_t dw_region_base_addr; + uint32_t dw_region_attr; + + __DMB(); + +/** + * ITCM memory region --- Normal + * START_Addr:- 0x00000000UL + * END_Addr:- 0x00400000UL + */ + dw_region_base_addr = + ITCM_START_ADDRESS | + MPU_REGION_VALID | + MPU_DEFAULT_ITCM_REGION; + + dw_region_attr = + MPU_AP_PRIVILEGED_READ_WRITE | + mpu_cal_mpu_region_size(ITCM_END_ADDRESS - ITCM_START_ADDRESS) | MPU_REGION_ENABLE; + + mpu_set_region( dw_region_base_addr, dw_region_attr); + +/** + * Internal flash memory region --- Normal read-only + * (update to Strongly ordered in write accesses) + * START_Addr:- 0x00400000UL + * END_Addr:- 0x00600000UL + */ + + dw_region_base_addr = + IFLASH_START_ADDRESS | + MPU_REGION_VALID | + MPU_DEFAULT_IFLASH_REGION; + + dw_region_attr = +// MPU_AP_READONLY | + MPU_AP_FULL_ACCESS | + INNER_NORMAL_WB_NWA_TYPE( NON_SHAREABLE ) | + mpu_cal_mpu_region_size(IFLASH_END_ADDRESS - IFLASH_START_ADDRESS) | MPU_REGION_ENABLE; + + mpu_set_region( dw_region_base_addr, dw_region_attr); + +/** + * DTCM memory region --- Normal + * START_Addr:- 0x20000000L + * END_Addr:- 0x20400000UL + */ + + /* DTCM memory region */ + dw_region_base_addr = + DTCM_START_ADDRESS | + MPU_REGION_VALID | + MPU_DEFAULT_DTCM_REGION; + + dw_region_attr = + MPU_AP_PRIVILEGED_READ_WRITE | + mpu_cal_mpu_region_size(DTCM_END_ADDRESS - DTCM_START_ADDRESS) | MPU_REGION_ENABLE; + + mpu_set_region( dw_region_base_addr, dw_region_attr); + +/** + * SRAM Cacheable memory region --- Normal + * START_Addr:- 0x20400000UL + * END_Addr:- 0x2043FFFFUL + */ + /* SRAM memory region */ + dw_region_base_addr = + SRAM_FIRST_START_ADDRESS | + MPU_REGION_VALID | + MPU_DEFAULT_SRAM_REGION_1; + + dw_region_attr = + MPU_AP_FULL_ACCESS | + INNER_NORMAL_WB_NWA_TYPE( NON_SHAREABLE ) | + mpu_cal_mpu_region_size(SRAM_FIRST_END_ADDRESS - SRAM_FIRST_START_ADDRESS) | MPU_REGION_ENABLE; + + mpu_set_region( dw_region_base_addr, dw_region_attr); + + +/** + * Internal SRAM second partition memory region --- Normal + * START_Addr:- 0x20440000UL + * END_Addr:- 0x2045FFFFUL + */ + /* SRAM memory region */ + dw_region_base_addr = + SRAM_SECOND_START_ADDRESS | + MPU_REGION_VALID | + MPU_DEFAULT_SRAM_REGION_2; + + dw_region_attr = + MPU_AP_FULL_ACCESS | + INNER_NORMAL_WB_NWA_TYPE( NON_SHAREABLE ) | + mpu_cal_mpu_region_size(SRAM_SECOND_END_ADDRESS - SRAM_SECOND_START_ADDRESS) | MPU_REGION_ENABLE; + + mpu_set_region( dw_region_base_addr, dw_region_attr); + +#ifdef MPU_HAS_NOCACHE_REGION + dw_region_base_addr = + SRAM_NOCACHE_START_ADDRESS | + MPU_REGION_VALID | + MPU_NOCACHE_SRAM_REGION; + + dw_region_attr = + MPU_AP_FULL_ACCESS | + INNER_OUTER_NORMAL_NOCACHE_TYPE( SHAREABLE ) | + mpu_cal_mpu_region_size(NOCACHE_SRAM_REGION_SIZE) | MPU_REGION_ENABLE; + + mpu_set_region( dw_region_base_addr, dw_region_attr); +#endif + +/** + * Peripheral memory region --- DEVICE Shareable + * START_Addr:- 0x40000000UL + * END_Addr:- 0x5FFFFFFFUL + */ + dw_region_base_addr = + PERIPHERALS_START_ADDRESS | + MPU_REGION_VALID | + MPU_PERIPHERALS_REGION; + + dw_region_attr = MPU_AP_FULL_ACCESS | + MPU_REGION_EXECUTE_NEVER | + SHAREABLE_DEVICE_TYPE | + mpu_cal_mpu_region_size(PERIPHERALS_END_ADDRESS - PERIPHERALS_START_ADDRESS) | MPU_REGION_ENABLE; + + mpu_set_region( dw_region_base_addr, dw_region_attr); + + +/** + * External EBI memory memory region --- Strongly Ordered + * START_Addr:- 0x60000000UL + * END_Addr:- 0x6FFFFFFFUL + */ + dw_region_base_addr = + EXT_EBI_START_ADDRESS | + MPU_REGION_VALID | + MPU_EXT_EBI_REGION; + + dw_region_attr = + MPU_AP_FULL_ACCESS | + /* External memory Must be defined with 'Device' or 'Strongly Ordered' attribute for write accesses (AXI) */ + STRONGLY_ORDERED_SHAREABLE_TYPE | + mpu_cal_mpu_region_size(EXT_EBI_END_ADDRESS - EXT_EBI_START_ADDRESS) | MPU_REGION_ENABLE; + + mpu_set_region( dw_region_base_addr, dw_region_attr); + +/** + * SDRAM cacheable memory region --- Normal + * START_Addr:- 0x70000000UL + * END_Addr:- 0x7FFFFFFFUL + */ + dw_region_base_addr = + SDRAM_START_ADDRESS | + MPU_REGION_VALID | + MPU_DEFAULT_SDRAM_REGION; + + dw_region_attr = + MPU_AP_FULL_ACCESS | + INNER_NORMAL_WB_RWA_TYPE( SHAREABLE ) | + mpu_cal_mpu_region_size(SDRAM_END_ADDRESS - SDRAM_START_ADDRESS) | MPU_REGION_ENABLE; + + mpu_set_region( dw_region_base_addr, dw_region_attr); + +/** + * QSPI memory region --- Strongly ordered + * START_Addr:- 0x80000000UL + * END_Addr:- 0x9FFFFFFFUL + */ + dw_region_base_addr = + QSPI_START_ADDRESS | + MPU_REGION_VALID | + MPU_QSPIMEM_REGION; + + dw_region_attr = + MPU_AP_FULL_ACCESS | + STRONGLY_ORDERED_SHAREABLE_TYPE | + mpu_cal_mpu_region_size(QSPI_END_ADDRESS - QSPI_START_ADDRESS) | + MPU_REGION_ENABLE; + + mpu_set_region( dw_region_base_addr, dw_region_attr); + + +/** + * USB RAM Memory region --- Device + * START_Addr:- 0xA0100000UL + * END_Addr:- 0xA01FFFFFUL + */ + dw_region_base_addr = + USBHSRAM_START_ADDRESS | + MPU_REGION_VALID | + MPU_USBHSRAM_REGION; + + dw_region_attr = + MPU_AP_FULL_ACCESS | + MPU_REGION_EXECUTE_NEVER | + SHAREABLE_DEVICE_TYPE | + mpu_cal_mpu_region_size(USBHSRAM_END_ADDRESS - USBHSRAM_START_ADDRESS) | + MPU_REGION_ENABLE; + + mpu_set_region( dw_region_base_addr, dw_region_attr); + + + /* Enable the memory management fault , Bus Fault, Usage Fault exception */ + SCB->SHCSR |= (SCB_SHCSR_MEMFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk | SCB_SHCSR_USGFAULTENA_Msk); + + /* Enable the MPU region */ + mpu_enable( MPU_ENABLE | MPU_PRIVDEFENA); + + __DSB(); + __ISB(); +} +#endif + +#ifdef CONF_BOARD_ENABLE_TCM_AT_INIT +#if defined(__GNUC__) +extern char _itcm_lma, _sitcm, _eitcm; +#endif + +/** \brief TCM memory enable +* The function enables TCM memories +*/ +static inline void tcm_enable(void) +{ + + __DSB(); + __ISB(); + + SCB->ITCMCR = (SCB_ITCMCR_EN_Msk | SCB_ITCMCR_RMW_Msk | SCB_ITCMCR_RETEN_Msk); + SCB->DTCMCR = ( SCB_DTCMCR_EN_Msk | SCB_DTCMCR_RMW_Msk | SCB_DTCMCR_RETEN_Msk); + + __DSB(); + __ISB(); +} +#else +/** \brief TCM memory Disable + + The function enables TCM memories + */ +static inline void tcm_disable(void) +{ + + __DSB(); + __ISB(); + SCB->ITCMCR &= ~(uint32_t)(1UL); + SCB->DTCMCR &= ~(uint32_t)SCB_DTCMCR_EN_Msk; + __DSB(); + __ISB(); +} +#endif + +__attribute__((optimize("O0"))) +static void waitPinPullup(void) +{ + // wait a tiny bit for pins to pull + for (volatile int i = 0; i < 200000; i++) {} +} + + +void refresh_led_cfg(void) +{ + switch(g_flashCfg->cbPreset) + { + default: + case EVB2_CB_PRESET_ALL_OFF: LED_CFG_OFF(); break; + case EVB2_CB_PRESET_RS232: LED_CFG_GREEN(); break; + case EVB2_CB_PRESET_RS232_XBEE: LED_CFG_BLUE(); break; + case EVB2_CB_PRESET_RS422_WIFI: LED_CFG_PURPLE(); break; + case EVB2_CB_PRESET_SPI_RS232: LED_CFG_CYAN(); break; + case EVB2_CB_PRESET_USB_HUB_RS232: LED_CFG_YELLOW(); break; + case EVB2_CB_PRESET_USB_HUB_RS422: LED_CFG_WHITE(); break; + } +} + + +void init_set_board_IO_config_callback(VoidFuncPtrVoid fpIoCfg) +{ + s_pfnHandleBoardIoCfg = fpIoCfg; +} + +void board_IO_config(void) +{ + ////////////////////////////////////////////////////////////////////////// + // EVB uINS G1,G2 (CAN, Ser2, I2C) + // EVB-PA3 - SDA + // EVB-PA4 - SCL +#ifdef CONF_BOARD_I2C_UINS + if (!g_flashCfg->cbOptions&EVB2_CB_OPTIONS_TRISTATE_UINS_IO && + g_flashCfg->cbOptions&EVB2_CB_OPTIONS_I2C_ENABLE) + { + i2cInit(); + } + else + { // Disable pins + ioport_set_pin_input_mode(I2C_0_SDA_PIN, 0, 0); + ioport_set_pin_input_mode(I2C_0_SCL_PIN, 0, 0); + } +#endif + + ////////////////////////////////////////////////////////////////////////// + // uINS G3,G4 (Ser0) + // EVB-PA5,PA6 + if (g_flashCfg->cbOptions&EVB2_CB_OPTIONS_TRISTATE_UINS_IO || + (g_flashCfg->uinsComPort != EVB2_PORT_UINS0 && + g_flashCfg->uinsAuxPort != EVB2_PORT_UINS0)) + { // I/O tristate + ioport_set_pin_input_mode(UART_INS_SER0_TXD_PIN, 0, 0); + ioport_set_pin_input_mode(UART_INS_SER0_RXD_PIN, 0, 0); + } + else + { +#ifdef CONF_BOARD_SERIAL_UINS_SER0 + ioport_set_pin_peripheral_mode(UART_INS_SER0_RXD_PIN, UART_INS_SER0_RXD_FLAGS); + ioport_set_pin_peripheral_mode(UART_INS_SER0_TXD_PIN, UART_INS_SER0_TXD_FLAGS); + serInit(EVB2_PORT_UINS0, 921600, NULL); +#endif + } + + ///////////////////////////////////////////////////////////// + // uINS G6,G7 (Ser1, SPI, QDEC0) + // EVB-PA9,PA10 + if (g_flashCfg->cbOptions&EVB2_CB_OPTIONS_SPI_ENABLE) + { + #ifdef CONF_BOARD_SPI_UINS + ioport_set_pin_peripheral_mode(SPI_INS_MISO_PIN, SPI_INS_MISO_FLAGS); + ioport_set_pin_peripheral_mode(SPI_INS_MOSI_PIN, SPI_INS_MOSI_FLAGS); + ioport_set_pin_peripheral_mode(SPI_INS_SCLK_PIN, SPI_INS_SCLK_FLAGS); + + //CS will be handled by GPIO + ioport_set_pin_output_mode(SPI_INS_CS_PIN, IOPORT_PIN_LEVEL_HIGH); + ioport_enable_pin(SPI_INS_CS_PIN); + + //Indicate to uINS that SPI is requested + ioport_set_pin_output_mode(SPI_INS_EN, IOPORT_PIN_LEVEL_LOW); + ioport_enable_pin(SPI_INS_EN); + + //Setup data ready pin + ioport_set_pin_dir(INS_DATA_RDY_PIN_IDX, IOPORT_DIR_INPUT); + ioport_set_pin_mode(INS_DATA_RDY_PIN_IDX, IOPORT_MODE_PULLDOWN); + + spiTouINS_init(); + #endif + } + else if (g_flashCfg->cbOptions&EVB2_CB_OPTIONS_TRISTATE_UINS_IO || + (g_flashCfg->uinsComPort != EVB2_PORT_UINS1 && g_flashCfg->uinsAuxPort != EVB2_PORT_UINS1)) + { // I/O tristate - (Enable pin and set as input) + ioport_set_pin_input_mode(UART_INS_SER1_TXD_PIN, 0, 0); + ioport_set_pin_input_mode(UART_INS_SER1_RXD_PIN, 0, 0); + + ioport_set_pin_input_mode(SPI_INS_MISO_PIN, 0, 0); + ioport_set_pin_input_mode(SPI_INS_MOSI_PIN, 0, 0); + ioport_set_pin_input_mode(SPI_INS_SCLK_PIN, 0, 0); + ioport_set_pin_input_mode(SPI_INS_CS_PIN, 0, 0); + ioport_set_pin_input_mode(SPI_INS_EN, 0, 0); + } + else + { +#ifdef CONF_BOARD_SERIAL_UINS_SER1 + ioport_set_pin_peripheral_mode(UART_INS_SER1_TXD_PIN, UART_INS_SER1_TXD_FLAGS); + ioport_set_pin_peripheral_mode(UART_INS_SER1_RXD_PIN, UART_INS_SER1_RXD_FLAGS); + serInit(EVB2_PORT_UINS1, 921600, NULL); + ioport_set_pin_input_mode(SPI_INS_SCLK_PIN, 0, 0); + ioport_set_pin_input_mode(SPI_INS_CS_PIN, 0, 0); + ioport_set_pin_input_mode(SPI_INS_EN, 0, 0); +#endif + } + + ///////////////////////////////////////////////////////////// + // SP330 - RS232/RS485 interface +#ifdef CONF_BOARD_SERIAL_SP330 + if (g_flashCfg->cbOptions&EVB2_CB_OPTIONS_SP330_RS422) + { // RS422 mode + ioport_set_pin_output_mode(SP330_N485_RXEN_PIN, IOPORT_PIN_LEVEL_LOW); // Enable RS485 receiver + ioport_set_pin_output_mode(SP330_485_N232_PIN, IOPORT_PIN_LEVEL_HIGH); // Enable RS422/RS485 mode + } + else + { // RS232 mode + ioport_set_pin_output_mode(SP330_N485_RXEN_PIN, IOPORT_PIN_LEVEL_HIGH); // Disable RS485 receiver + ioport_set_pin_output_mode(SP330_485_N232_PIN, IOPORT_PIN_LEVEL_LOW); // Enable RS232 mode + } + serSyncBaudRate(EVB2_PORT_SP330, &(g_flashCfg->h3sp330BaudRate)); +#endif + + ////////////////////////////////////////////////////////////////////////// + // XBee +#ifdef CONF_BOARD_SERIAL_XBEE + if (g_flashCfg->cbOptions&EVB2_CB_OPTIONS_XBEE_ENABLE) + { // XBee enabled + ioport_set_pin_peripheral_mode(UART_XBEE_RXD_PIN, UART_XBEE_RXD_FLAGS); + ioport_set_pin_peripheral_mode(UART_XBEE_TXD_PIN, UART_XBEE_TXD_FLAGS); + ioport_set_pin_peripheral_mode(UART_XBEE_N_CTS_PIN, UART_XBEE_N_CTS_FLAGS); + serInit(EVB2_PORT_XBEE, 115200, NULL); +#if 0 + ioport_set_pin_peripheral_mode(UART_XBEE_N_RTS_PIN, UART_XBEE_N_RTS_FLAGS); + ioport_set_pin_peripheral_mode(UART_XBEE_DTR_PIN, UART_XBEE_DTR_FLAGS); +#else + ioport_set_pin_output_mode(UART_XBEE_N_DTR_PIN, IOPORT_PIN_LEVEL_LOW); // Low assert + ioport_set_pin_output_mode(UART_XBEE_N_RTS_PIN, IOPORT_PIN_LEVEL_LOW); // Low assert +#endif +// ioport_set_pin_output_mode(XBEE_VUSB_DISABLE_PIN, IOPORT_PIN_LEVEL_LOW); // Enable VBUS + ioport_set_pin_output_mode(XBEE_RST_PIN, IOPORT_PIN_LEVEL_HIGH); // Reset off (low asserted) + ioport_set_pin_output_mode(XBEE_SUPPLY_EN_PIN, IOPORT_PIN_LEVEL_HIGH); // Enable supply + g_status.evbStatus |= EVB_STATUS_XBEE_ENABLED; + } + else + { // XBee disabled + ioport_set_pin_input_mode(UART_XBEE_TXD_PIN, 0, 0); + ioport_set_pin_input_mode(UART_XBEE_RXD_PIN, 0, 0); + ioport_set_pin_input_mode(UART_XBEE_N_CTS_PIN, 0, 0); + ioport_set_pin_input_mode(UART_XBEE_N_DTR_PIN, 0, 0); + ioport_set_pin_input_mode(UART_XBEE_N_RTS_PIN, 0, 0); + ioport_set_pin_input_mode(XBEE_RST_PIN, 0, 0); + + ioport_set_pin_output_mode(XBEE_SUPPLY_EN_PIN, IOPORT_PIN_LEVEL_LOW); // Disable supply + g_status.evbStatus &= ~EVB_STATUS_XBEE_ENABLED; + + LED_OFF(LED_XBEE_RXD_PIN); + LED_OFF(LED_XBEE_TXD_PIN); + } + serSetBaudRate(EVB2_PORT_XBEE, 115200); + + switch(g_flashCfg->cbPreset) + { + case EVB2_CB_PRESET_RS232_XBEE: + case EVB2_CB_PRESET_USB_HUB_RS232: + xbee_init(); + + } +#endif + + ////////////////////////////////////////////////////////////////////////// + // WiFi +#ifdef CONF_BOARD_SPI_ATWINC_WIFI + if (g_flashCfg->cbOptions&EVB2_CB_OPTIONS_WIFI_ENABLE ) + { // WiFi enabled + wifi_enable(true); // power on wifi. Connect to hot spot and TCP socket + } + else + { // WiFi disabled + wifi_enable(false); // power off wifi + } +#else + LED_OFF(LED_WIFI_TXD_PIN); + LED_OFF(LED_WIFI_RXD_PIN); +#endif + + // Reset default baud rates + if (!(g_flashCfg->cbOptions&EVB2_CB_OPTIONS_TRISTATE_UINS_IO)) + { // I/O not tristate + serSetBaudRate(EVB2_PORT_UINS0, 921600); + if (!(g_flashCfg->cbOptions&EVB2_CB_OPTIONS_SPI_ENABLE)) + { + serSetBaudRate(EVB2_PORT_UINS1, 921600); + } + } + serSetBaudRate(EVB2_PORT_BLE, 115200); + serSyncBaudRate(EVB2_PORT_XRADIO, &(g_flashCfg->h4xRadioBaudRate)); + serSyncBaudRate(EVB2_PORT_GPIO_H8, &(g_flashCfg->h8gpioBaudRate)); + + ////////////////////////////////////////////////////////////////////////// + // CAN +#ifdef CONF_BOARD_CAN1 + if (g_flashCfg->cbOptions&EVB2_CB_OPTIONS_CAN_ENABLE) + { + serSetBaudRate(EVB2_PORT_UINS1, 921600); + CAN_init(g_flashCfg->CANbaud_kbps*1000, g_flashCfg->can_receive_address); + } +#endif + + ///////////////////////////////////////////////////////////////////////// + // Reset IMX for changes to take effect (SPI, etc.) + ioport_set_pin_output_mode(INS_RESET_PIN_PIN, IOPORT_PIN_LEVEL_LOW); + time_delay_msec(100); + ioport_set_pin_output_mode(INS_RESET_PIN_PIN, IOPORT_PIN_LEVEL_HIGH); + + if (s_pfnHandleBoardIoCfg) + { + s_pfnHandleBoardIoCfg(); + } +} + + + +void board_init() +{ + // Hardware Detection - PCB version + ioport_set_pin_dir(EVB_HDW_DETECT_0_GPIO, IOPORT_DIR_INPUT); + ioport_set_pin_dir(EVB_HDW_DETECT_1_GPIO, IOPORT_DIR_INPUT); + ioport_set_pin_dir(EVB_HDW_DETECT_2_GPIO, IOPORT_DIR_INPUT); + ioport_set_pin_mode(EVB_HDW_DETECT_0_GPIO, IOPORT_MODE_PULLUP); + ioport_set_pin_mode(EVB_HDW_DETECT_1_GPIO, IOPORT_MODE_PULLUP); + ioport_set_pin_mode(EVB_HDW_DETECT_2_GPIO, IOPORT_MODE_PULLUP); + waitPinPullup(); + + g_hdw_detect = ~(0xF8 | + ((ioport_get_pin_level(EVB_HDW_DETECT_0_GPIO)&0x1) <<0) | + ((ioport_get_pin_level(EVB_HDW_DETECT_1_GPIO)&0x1) <<1) | + ((ioport_get_pin_level(EVB_HDW_DETECT_2_GPIO)&0x1) <<2)); + + // Disable hardware detect pullup/pulldown (tri-state pins) + ioport_set_pin_input_mode(EVB_HDW_DETECT_0_GPIO, 0, 0); + ioport_set_pin_input_mode(EVB_HDW_DETECT_1_GPIO, 0, 0); + ioport_set_pin_input_mode(EVB_HDW_DETECT_2_GPIO, 0, 0); + + ////////////////////////////////////////////////////////////////////////// + // Init system clocks + // If running on PLL, disable it so second PLL initialization does not hang device + if((PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK) + { + pmc_switch_mck_to_mainck(0); + pll_disable(PLLA_ID); + } + + pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL); // set SLCK to use external 32kHz crystal rather than internal 32kHz RC oscillator. + sysclk_init(); + + +#ifndef CONF_BOARD_KEEP_WATCHDOG_AT_INIT + /* Disable the watchdog */ + WDT->WDT_MR = WDT_MR_WDDIS; +#endif + +#ifdef CONF_BOARD_CONFIG_MPU_AT_INIT + _setup_memory_region(); +#endif + + SCB_EnableICache(); + +#if CONF_BOARD_ENABLE_DCACHE == 1 + SCB_EnableDCache(); +#endif + +#ifdef CONF_BOARD_ENABLE_TCM_AT_INIT + /* TCM Configuration */ + EFC->EEFC_FCR = (EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FCMD_CGPB + | EEFC_FCR_FARG(8)); + EFC->EEFC_FCR = (EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FCMD_SGPB + | EEFC_FCR_FARG(7)); + tcm_enable(); +#if defined(__GNUC__) + volatile char *dst = &_sitcm; + volatile char *src = &_itcm_lma; + /* copy code_TCM from flash to ITCM */ + while(dst < &_eitcm){ + *dst++ = *src++; + } +#endif +#else + /* TCM Configuration */ + EFC->EEFC_FCR = (EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FCMD_CGPB + | EEFC_FCR_FARG(8)); + EFC->EEFC_FCR = (EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FCMD_CGPB + | EEFC_FCR_FARG(7)); + + tcm_disable(); +#endif + + // Real-time timer + time_init(); + time_delay_msec(1); // Delay to ensure time_msec() returns non-zero. + + /* Initialize IOPORTs */ + ioport_init(); + + ////////////////////////////////////////////////////////////////////////// + // LEDs - default to ALL on + ioport_set_pin_output_mode(LED_CFG_RED_PIN, IOPORT_PIN_LEVEL_LOW); + ioport_set_pin_output_mode(LED_CFG_GRN_PIN, IOPORT_PIN_LEVEL_LOW); + ioport_set_pin_output_mode(LED_CFG_BLU_PIN, IOPORT_PIN_LEVEL_LOW); + ioport_set_pin_output_mode(LED_LOG_RED_PIN, IOPORT_PIN_LEVEL_LOW); + ioport_set_pin_output_mode(LED_LOG_GRN_PIN, IOPORT_PIN_LEVEL_LOW); + ioport_set_pin_output_mode(LED_LOG_BLU_PIN, IOPORT_PIN_LEVEL_LOW); + + ioport_set_pin_output_mode(LED_INS_RXD_PIN, IOPORT_PIN_LEVEL_LOW); + ioport_set_pin_output_mode(LED_INS_TXD_PIN, IOPORT_PIN_LEVEL_LOW); + ioport_set_pin_output_mode(LED_XBEE_RXD_PIN, IOPORT_PIN_LEVEL_LOW); + ioport_set_pin_output_mode(LED_XBEE_TXD_PIN, IOPORT_PIN_LEVEL_LOW); + ioport_set_pin_output_mode(LED_WIFI_RXD_PIN, IOPORT_PIN_LEVEL_LOW); + ioport_set_pin_output_mode(LED_WIFI_TXD_PIN, IOPORT_PIN_LEVEL_LOW); + +#if 0 + // Turn off LEDs + LED_CFG_OFF(); + LED_LOG_OFF(); + + LED_OFF(LED_INS_RXD_PIN); + LED_OFF(LED_INS_TXD_PIN); + LED_OFF(LED_XBEE_RXD_PIN); + LED_OFF(LED_XBEE_TXD_PIN); + LED_OFF(LED_WIFI_RXD_PIN); + LED_OFF(LED_WIFI_TXD_PIN); +#endif + + ////////////////////////////////////////////////////////////////////////// + // Push Buttons + ioport_set_pin_input_mode(BUTTON_CFG_PIN, BUTTON_CFG_FLAGS, BUTTON_CFG_SENSE); + ioport_set_pin_input_mode(BUTTON_LOG_PIN, BUTTON_LOG_FLAGS, BUTTON_LOG_SENSE); + + ////////////////////////////////////////////////////////////////////////// + // Serial Ports + + // UINS ser0 and ser1 - In board_IO_init() in main.cpp + +#ifdef CONF_BOARD_SERIAL_EXT_RADIO // External Radio + ioport_set_pin_peripheral_mode(UART_EXT_RADIO_RXD_PIN, UART_EXT_RADIO_RXD_FLAGS); + ioport_set_pin_peripheral_mode(UART_EXT_RADIO_TXD_PIN, UART_EXT_RADIO_TXD_FLAGS); + serInitSyncBaudrate(EVB2_PORT_XRADIO, &(g_flashCfg->h4xRadioBaudRate), NULL); +// ioport_set_pin_dir(EXT_RADIO_RST, IOPORT_DIR_OUTPUT); +// ioport_set_pin_level(EXT_RADIO_RST, IOPORT_PIN_LEVEL_HIGH); // Low assert +#endif + +#ifdef CONF_BOARD_SERIAL_ATWINC_BLE // ATWINC3400 Bluetooth + ioport_set_pin_peripheral_mode(UART_BTLE_RXD_PIN, UART_BTLE_RXD_FLAGS); + ioport_set_pin_peripheral_mode(UART_BTLE_TXD_PIN, UART_BTLE_TXD_FLAGS); + ioport_set_pin_peripheral_mode(UART_BTLE_CTS_PIN, UART_XBEE_N_CTS_FLAGS); + ioport_set_pin_peripheral_mode(UART_BTLE_RTS_PIN, UART_XBEE_N_RTS_FLAGS); + serInit(EVB2_PORT_BLE, 115200, NULL); +#endif + +#ifdef CONF_BOARD_SERIAL_SP330 // RS232/RS422/RS485 converter + ioport_set_pin_peripheral_mode(UART_SP330_RXD_PIN, UART_SP330_RXD_FLAGS); + ioport_set_pin_peripheral_mode(UART_SP330_TXD_PIN, UART_SP330_TXD_FLAGS); + serInitSyncBaudrate(EVB2_PORT_SP330, &(g_flashCfg->h3sp330BaudRate), NULL); + ioport_set_pin_output_mode(SP330_NSLEW_PIN, IOPORT_PIN_LEVEL_HIGH); // Don't limit data rate to less than 250 Kbps + ioport_set_pin_output_mode(SP330_NFULL_DPLX_PIN, IOPORT_PIN_LEVEL_LOW); // RS485 full duplex (RS232 N/A) + ioport_set_pin_output_mode(SP330_NSHDN_PIN, IOPORT_PIN_LEVEL_HIGH); // Enable device +#endif + + ioport_set_pin_output_mode(GPIO_UART_INV_PIN, IOPORT_PIN_LEVEL_LOW); // Non-inverting +#ifdef CONF_BOARD_SERIAL_GPIO_H8 // GPIO TTL + ioport_set_pin_peripheral_mode(GPIO_H8_UART_RXD_PIN, GPIO_H8_UART_RXD_FLAGS); + MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO4; + ioport_set_pin_peripheral_mode(GPIO_H8_UART_TXD_PIN, GPIO_H8_UART_TXD_FLAGS); + serInitSyncBaudrate(EVB2_PORT_GPIO_H8, &(g_flashCfg->h8gpioBaudRate), NULL); +#endif + + ////////////////////////////////////////////////////////////////////////// + // SPI Interface +#ifdef CONF_BOARD_SPI_ATWINC_WIFI // ATWINC WIFI + ioport_set_pin_peripheral_mode(SPI_WIFI_MISO_PIN, SPI_WIFI_MISO_FLAGS); + ioport_set_pin_peripheral_mode(SPI_WIFI_MOSI_PIN, SPI_WIFI_MOSI_FLAGS); + ioport_set_pin_peripheral_mode(SPI_WIFI_SCLK_PIN, SPI_WIFI_SCLK_FLAGS); + ioport_set_pin_peripheral_mode(SPI_WIFI_CS_PIN, SPI_WIFI_CS_FLAGS); + ioport_set_pin_output_mode(WIFI_RST_PIN, IOPORT_PIN_LEVEL_LOW); + ioport_set_pin_output_mode(WIFI_CHIPEN_PIN, IOPORT_PIN_LEVEL_LOW); // Disable + ioport_set_pin_input_mode(WIFI_IRQN_PIN, 0, 0); +#else + ioport_set_pin_output_mode(WIFI_CHIPEN_PIN, IOPORT_PIN_LEVEL_LOW); // Disable +#endif + + ////////////////////////////////////////////////////////////////////////// + // I2C Interface +#ifdef CONF_BOARD_I2C_UINS // UINS I2C + ioport_set_pin_peripheral_mode(I2C_0_SCL_PIN, I2C_0_SCL_FLAGS); + ioport_set_pin_peripheral_mode(I2C_0_SDA_PIN, I2C_0_SDA_FLAGS); +#endif + +#ifdef CONF_BOARD_CAN1 + /* Configure the CAN1 TX and RX pin. */ + ioport_set_pin_peripheral_mode(CAN_RXD_PIN, CAN_RXD_FLAGS); + ioport_set_pin_peripheral_mode(CAN_TXD_PIN, CAN_TXD_FLAGS); +#endif + + ////////////////////////////////////////////////////////////////////////// + // SD Card Interface +#ifdef CONF_BOARD_SD_MMC_HSMCI + /* Configure HSMCI pins */ + ioport_set_pin_peripheral_mode(PIN_HSMCI_MCCDA_GPIO, PIN_HSMCI_MCCDA_FLAGS); + ioport_set_pin_peripheral_mode(PIN_HSMCI_MCCK_GPIO, PIN_HSMCI_MCCK_FLAGS); + ioport_set_pin_peripheral_mode(PIN_HSMCI_MCDA0_GPIO, PIN_HSMCI_MCDA0_FLAGS); + ioport_set_pin_peripheral_mode(PIN_HSMCI_MCDA1_GPIO, PIN_HSMCI_MCDA1_FLAGS); + ioport_set_pin_peripheral_mode(PIN_HSMCI_MCDA2_GPIO, PIN_HSMCI_MCDA2_FLAGS); + ioport_set_pin_peripheral_mode(PIN_HSMCI_MCDA3_GPIO, PIN_HSMCI_MCDA3_FLAGS); + + /* Configure SD/MMC card detect pin */ + ioport_set_pin_input_mode(SD_MMC_0_CD_GPIO, SD_MMC_0_CD_FLAGS, 0); +#endif + + + + ////////////////////////////////////////////////////////////////////////// + /// Unused / Future Use + ////////////////////////////////////////////////////////////////////////// + +#ifdef CONF_BOARD_TWIHS0 + ioport_set_pin_peripheral_mode(TWIHS0_DATA_GPIO, TWIHS0_DATA_FLAGS); + ioport_set_pin_peripheral_mode(TWIHS0_CLK_GPIO, TWIHS0_CLK_FLAGS); +#endif + +#ifdef CONF_BOARD_CAN0 + /* Configure the CAN0 TX and RX pins. */ + ioport_set_pin_peripheral_mode(PIN_CAN0_RX_IDX, PIN_CAN0_RX_FLAGS); + ioport_set_pin_peripheral_mode(PIN_CAN0_TX_IDX, PIN_CAN0_TX_FLAGS); + /* Configure the transiver0 RS & EN pins. */ + ioport_set_pin_dir(PIN_CAN0_TR_RS_IDX, IOPORT_DIR_OUTPUT); + ioport_set_pin_dir(PIN_CAN0_TR_EN_IDX, IOPORT_DIR_OUTPUT); +#endif + +#ifdef CONF_BOARD_SPI + ioport_set_pin_peripheral_mode(SPI0_MISO_GPIO, SPI0_MISO_FLAGS); + ioport_set_pin_peripheral_mode(SPI0_MOSI_GPIO, SPI0_MOSI_FLAGS); + ioport_set_pin_peripheral_mode(SPI0_SPCK_GPIO, SPI0_SPCK_FLAGS); + +#ifdef CONF_BOARD_SPI_NPCS0 + ioport_set_pin_peripheral_mode(SPI0_NPCS0_GPIO, SPI0_NPCS0_FLAGS); +#endif + +#ifdef CONF_BOARD_SPI_NPCS1 + ioport_set_pin_peripheral_mode(SPI0_NPCS1_GPIO, SPI0_NPCS1_FLAGS); +#endif +#endif + +#ifdef CONF_BOARD_QSPI + ioport_set_pin_peripheral_mode(QSPI_QSCK_GPIO, QSPI_QSCK_FLAGS); + ioport_set_pin_peripheral_mode(QSPI_QCS_GPIO, QSPI_QCS_FLAGS); + ioport_set_pin_peripheral_mode(QSPI_QIO0_GPIO, QSPI_QIO0_FLAGS); + ioport_set_pin_peripheral_mode(QSPI_QIO1_GPIO, QSPI_QIO1_FLAGS); + ioport_set_pin_peripheral_mode(QSPI_QIO2_GPIO, QSPI_QIO2_FLAGS); + ioport_set_pin_peripheral_mode(QSPI_QIO3_GPIO, QSPI_QIO3_FLAGS); +#endif + +#ifdef CONF_BOARD_PWM_LED0 + /* Configure PWM LED0 pin */ + ioport_set_pin_peripheral_mode(PIN_PWM_LED0_GPIO, PIN_PWM_LED0_FLAGS); +#endif + +#ifdef CONF_BOARD_PWM_LED1 + /* Configure PWM LED1 pin */ + ioport_set_pin_peripheral_mode(PIN_PWM_LED1_GPIO, PIN_PWM_LED1_FLAGS); +#endif + +#ifdef CONF_BOARD_USART_SCK + /* Configure USART synchronous communication SCK pin */ + ioport_set_pin_peripheral_mode(PIN_USART0_SCK_IDX,PIN_USART0_SCK_FLAGS); +#endif + +#ifdef CONF_BOARD_USART_CTS + /* Configure USART synchronous communication CTS pin */ + ioport_set_pin_peripheral_mode(PIN_USART0_CTS_IDX,PIN_USART0_CTS_FLAGS); +#endif + +#ifdef CONF_BOARD_USART_RTS + /* Configure USART RTS pin */ + ioport_set_pin_peripheral_mode(PIN_USART0_RTS_IDX, PIN_USART0_RTS_FLAGS); +#endif + +#ifdef CONF_BOARD_ILI9488 + /**LCD pin configure on EBI*/ + pio_configure(PIN_EBI_RESET_PIO, PIN_EBI_RESET_TYPE, PIN_EBI_RESET_MASK, PIN_EBI_RESET_ATTRI); + pio_configure(PIN_EBI_CDS_PIO, PIN_EBI_CDS_TYPE, PIN_EBI_CDS_MASK, PIN_EBI_CDS_ATTRI); + pio_configure(PIN_EBI_DATAL_PIO, PIN_EBI_DATAL_TYPE, PIN_EBI_DATAL_MASK, PIN_EBI_DATAL_ATTRI); + pio_configure(PIN_EBI_DATAH_0_PIO, PIN_EBI_DATAH_0_TYPE, PIN_EBI_DATAH_0_MASK, PIN_EBI_DATAH_0_ATTRI); + pio_configure(PIN_EBI_DATAH_1_PIO, PIN_EBI_DATAH_1_TYPE, PIN_EBI_DATAH_1_MASK, PIN_EBI_DATAH_1_ATTRI); + pio_configure(PIN_EBI_NWE_PIO, PIN_EBI_NWE_TYPE, PIN_EBI_NWE_MASK, PIN_EBI_NWE_ATTRI); + pio_configure(PIN_EBI_NRD_PIO, PIN_EBI_NRD_TYPE, PIN_EBI_NRD_MASK, PIN_EBI_NRD_ATTRI); + pio_configure(PIN_EBI_CS_PIO, PIN_EBI_CS_TYPE, PIN_EBI_CS_MASK, PIN_EBI_CS_ATTRI); + pio_configure(PIN_EBI_BACKLIGHT_PIO, PIN_EBI_BACKLIGHT_TYPE, PIN_EBI_BACKLIGHT_MASK, PIN_EBI_BACKLIGHT_ATTRI); + pio_set(PIN_EBI_BACKLIGHT_PIO, PIN_EBI_BACKLIGHT_MASK); +#endif + +#if (defined CONF_BOARD_USB_PORT) +# if defined(CONF_BOARD_USB_VBUS_DETECT) + ioport_set_pin_dir(USB_VBUS_PIN, IOPORT_DIR_INPUT); +# endif +# if defined(CONF_BOARD_USB_ID_DETECT) + ioport_set_pin_dir(USB_ID_PIN, IOPORT_DIR_INPUT); +# endif +#endif + +#ifdef CONF_BOARD_SDRAMC + pio_configure_pin(SDRAM_BA0_PIO, SDRAM_BA0_FLAGS); + pio_configure_pin(SDRAM_SDCK_PIO, SDRAM_SDCK_FLAGS); + pio_configure_pin(SDRAM_SDCKE_PIO, SDRAM_SDCKE_FLAGS); + pio_configure_pin(SDRAM_SDCS_PIO, SDRAM_SDCS_FLAGS); + pio_configure_pin(SDRAM_RAS_PIO, SDRAM_RAS_FLAGS); + pio_configure_pin(SDRAM_CAS_PIO, SDRAM_CAS_FLAGS); + pio_configure_pin(SDRAM_SDWE_PIO, SDRAM_SDWE_FLAGS); + pio_configure_pin(SDRAM_NBS0_PIO, SDRAM_NBS0_FLAGS); + pio_configure_pin(SDRAM_NBS1_PIO, SDRAM_NBS1_FLAGS); + pio_configure_pin(SDRAM_A2_PIO, SDRAM_A_FLAGS); + pio_configure_pin(SDRAM_A3_PIO, SDRAM_A_FLAGS); + pio_configure_pin(SDRAM_A4_PIO, SDRAM_A_FLAGS); + pio_configure_pin(SDRAM_A5_PIO, SDRAM_A_FLAGS); + pio_configure_pin(SDRAM_A6_PIO, SDRAM_A_FLAGS); + pio_configure_pin(SDRAM_A7_PIO, SDRAM_A_FLAGS); + pio_configure_pin(SDRAM_A8_PIO, SDRAM_A_FLAGS); + pio_configure_pin(SDRAM_A9_PIO, SDRAM_A_FLAGS); + pio_configure_pin(SDRAM_A10_PIO, SDRAM_A_FLAGS); + pio_configure_pin(SDRAM_A11_PIO, SDRAM_A_FLAGS); + pio_configure_pin(SDRAM_SDA10_PIO, SDRAM_SDA10_FLAGS); + pio_configure_pin(SDRAM_D0_PIO, SDRAM_D_FLAGS); + pio_configure_pin(SDRAM_D1_PIO, SDRAM_D_FLAGS); + pio_configure_pin(SDRAM_D2_PIO, SDRAM_D_FLAGS); + pio_configure_pin(SDRAM_D3_PIO, SDRAM_D_FLAGS); + pio_configure_pin(SDRAM_D4_PIO, SDRAM_D_FLAGS); + pio_configure_pin(SDRAM_D5_PIO, SDRAM_D_FLAGS); + pio_configure_pin(SDRAM_D6_PIO, SDRAM_D_FLAGS); + pio_configure_pin(SDRAM_D7_PIO, SDRAM_D_FLAGS); + pio_configure_pin(SDRAM_D8_PIO, SDRAM_D_FLAGS); + pio_configure_pin(SDRAM_D9_PIO, SDRAM_D_FLAGS); + pio_configure_pin(SDRAM_D10_PIO, SDRAM_D_FLAGS); + pio_configure_pin(SDRAM_D11_PIO, SDRAM_D_FLAGS); + pio_configure_pin(SDRAM_D12_PIO, SDRAM_D_FLAGS); + pio_configure_pin(SDRAM_D13_PIO, SDRAM_D_FLAGS); + pio_configure_pin(SDRAM_D14_PIO, SDRAM_D_FLAGS); + pio_configure_pin(SDRAM_D15_PIO, SDRAM_D_FLAGS); + + MATRIX->CCFG_SMCNFCS = CCFG_SMCNFCS_SDRAMEN; +#endif + +#ifdef CONF_BOARD_ILI9488 + /**LCD pin configure on SPI*/ + pio_configure_pin(LCD_SPI_MISO_PIO, LCD_SPI_MISO_FLAGS); + pio_configure_pin(LCD_SPI_MOSI_PIO, LCD_SPI_MOSI_FLAGS); + pio_configure_pin(LCD_SPI_SPCK_PIO, LCD_SPI_SPCK_FLAGS); + pio_configure_pin(LCD_SPI_NPCS_PIO, LCD_SPI_NPCS_FLAGS); + pio_configure_pin(LCD_SPI_RESET_PIO, LCD_SPI_RESET_FLAGS); + pio_configure_pin(LCD_SPI_CDS_PIO, LCD_SPI_CDS_FLAGS); + pio_configure_pin(LCD_SPI_BACKLIGHT_PIO, LCD_SPI_BACKLIGHT_FLAGS); + pio_set_pin_high(LCD_SPI_BACKLIGHT_PIO); + +#endif +} diff --git a/EVB-2/IS_EVB-2/src/misc/init.h b/EVB-2/IS_EVB-2/src/misc/init.h new file mode 100644 index 000000000..094a960a4 --- /dev/null +++ b/EVB-2/IS_EVB-2/src/misc/init.h @@ -0,0 +1,14 @@ +#ifndef __INIT_H_ +#define __INIT_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +void board_init(void); + +#ifdef __cplusplus +} +#endif + +#endif // __INIT_H_ diff --git a/EVB-2/IS_EVB-2/src/misc/led.h b/EVB-2/IS_EVB-2/src/misc/led.h new file mode 100644 index 000000000..ec3719c5a --- /dev/null +++ b/EVB-2/IS_EVB-2/src/misc/led.h @@ -0,0 +1,71 @@ +/** + * \file + * + * \brief SAME70-XPLD LEDs support package. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef LED_H_INCLUDED +#define LED_H_INCLUDED + +#include "compiler.h" +#include "ioport.h" + +/** + * \brief Turns off the specified LEDs. + * + * \param led LED to turn off (LEDx_GPIO). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +#define LED_Off(led) ioport_set_pin_level(led##_GPIO, led##_INACTIVE_LEVEL) + +/** + * \brief Turns on the specified LEDs. + * + * \param led LED to turn on (LEDx_GPIO). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +#define LED_On(led) ioport_set_pin_level(led##_GPIO, led##_ACTIVE_LEVEL) + +/** + * \brief Toggles the specified LEDs. + * + * \param led LED to toggle (LEDx_GPIO). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +#define LED_Toggle(led) ioport_toggle_pin_level(led##_GPIO) + + +#endif // LED_H_INCLUDED diff --git a/EVB-2/IS_EVB-2/src/sd_card_logger.cpp b/EVB-2/IS_EVB-2/src/sd_card_logger.cpp new file mode 100644 index 000000000..4d3a1d6ff --- /dev/null +++ b/EVB-2/IS_EVB-2/src/sd_card_logger.cpp @@ -0,0 +1,250 @@ +/* +MIT LICENSE + +Copyright 2014-2019 Inertial Sense, Inc. - http://inertialsense.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions : + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +#include +#include "../../../src/ISUtilities.h" +#include "../../../src/ISLogger.h" +#include "globals.h" +#include "ISLogFileFatFs.h" +#include "communications.h" +#include "user_interface.h" +#include "sd_mmc_mem.h" + +#include "sd_card_logger.h" + +#undef printf +#define printf(...) +#define printf_mutex(...) + +int g_indicateFsWriteMs=0; + +static FATFS s_fs; +static bool s_sd_card_ready=false; +static int s_enableLogger=0; // 1=enable, -1=disable + +#if UBLOX_LOG_ENABLE +static cISLogFileBase *s_ubloxLog = NULLPTR; +#endif + + +void refresh_led_log(void) +{ + if(s_sd_card_ready) + { // SD ready + + if(g_loggerEnabled) + { // Logging + if(g_indicateFsWriteMs > 0) + { // writing to disk + g_indicateFsWriteMs -= g_rtos.task[EVB_TASK_LOGGER].periodMs; + LED_LOG_YELLOW(); +// ioport_set_pin_level(SKI_BOX_STATUS_LED_PIN,IOPORT_PIN_LEVEL_HIGH); // LED ON + } + else + { // not writing to disk + LED_LOG_OFF(); +// ioport_set_pin_level(SKI_BOX_STATUS_LED_PIN,IOPORT_PIN_LEVEL_LOW); // LED OFF + } + } + else + { // Not logging + if(g_gpsTimeSync) + { // w/ GPS + LED_LOG_GREEN(); + } + else + { // No GPS + LED_LOG_BLUE(); + } + } + } + else + { // SD not ready + LED_LOG_OFF(); + } +} + + +static void start_logger(cISLogger& logger, is_comm_instance_t &comm) +{ + if( s_sd_card_ready==false ) + { + return; + } + + g_loggerEnabled = true; + g_status.evbStatus |= EVB_STATUS_SD_LOG_ENABLED; + evbUiRefreshLedLog(); + +//// logger.InitSave(LOGTYPE_DAT, cISLogger::g_emptyString, 1, 0.5f, 1024 * 1024 * 5, 131072); + logger.InitSave(cISLogger::LOGTYPE_DAT, "IS_logs", 0.5f, 1024 * 1024 * 5, 16384); + +//// logger.InitSave(); + // logger.SetDeviceInfo(&g_uins.uInsInfo); // set uINS serial number + logger.EnableLogging(true); +} + + +static void stop_logger(cISLogger& logger, is_comm_instance_t &comm) +{ + g_loggerEnabled = false; + g_status.evbStatus &= ~EVB_STATUS_SD_LOG_ENABLED; + evbUiRefreshLedLog(); + + logger.EnableLogging(false); + logger.CloseAllFiles(); + +#if UBLOX_LOG_ENABLE + if (s_ubloxLog != NULLPTR) + { + delete s_ubloxLog; + s_ubloxLog = NULLPTR; + } +#endif +} + + +void enable_logger(bool enable) +{ + if(enable) + { + s_enableLogger = 1; + } + else + { // Disable logger + s_enableLogger = -1; + } +} + + +void step_logger_control(cISLogger& logger, is_comm_instance_t &comm) +{ + switch(s_enableLogger) + { + case 1: // Enable logger + s_enableLogger = 0; + start_logger(logger, comm); + break; + case -1: // Disable logger + s_enableLogger = 0; + stop_logger(logger, comm); + } +} + + + +void log_ublox_raw_to_SD(cISLogger& logger, uint8_t *dataPtr, uint32_t dataSize) +{ +#if UBLOX_LOG_ENABLE + + if(g_loggerEnabled) + { // log raw u-blox, rtcm, etc. + if (s_ubloxLog == NULLPTR) + { + std::string ubloxFile = (logger.LogDirectory() + "/raw_ublox.ubx"); + s_ubloxLog = new cISLogFileFatFs(ubloxFile.c_str(), "wb"); + } + if (dataSize <= MAX_DATASET_SIZE) + { + s_ubloxLog->write(dataPtr, dataSize); + } + } + +#endif +} + + +void time_sync_from_uINS(void) +{ + static uint32_t timeOfWeekMsLast=0; + + // Real-time clock (RTC) time synchronization with uINS + if(g_status.week != 0 && g_status.timeOfWeekMs!=timeOfWeekMsLast) + { + timeOfWeekMsLast = g_status.timeOfWeekMs; + int32_t gpsSeconds = g_status.timeOfWeekMs/1000; + convertMjdToDate( convertGpsToMjd(g_uins.ins2.week, gpsSeconds), (int32_t*)&g_gps_date_time.year, (int32_t*)&g_gps_date_time.month, (int32_t*)&g_gps_date_time.day); + convertGpsToHMS( gpsSeconds, (int32_t*)&g_gps_date_time.hour, (int32_t*)&g_gps_date_time.minute, (int32_t*)&g_gps_date_time.second ); + +#if USE_RTC_DATE_TIME // use RTC + date_time_t rtc; + rtc_get_date(RTC, &rtc.year, &rtc.month, &rtc.day, &rtc.week); + rtc_get_time(RTC, &rtc.hour, &rtc.minute, &rtc.second); + + if( g_gps_date_time.year != rtc.year || + g_gps_date_time.month != rtc.month || + g_gps_date_time.day != rtc.day || + g_gps_date_time.hour != rtc.hour || + g_gps_date_time.minute != rtc.minute ) + { + g_gps_date_time.week = dateToWeekDay(g_gps_date_time.year, g_gps_date_time.month, g_gps_date_time.day); + + rtc_set_date(RTC, g_gps_date_time.year, g_gps_date_time.month, g_gps_date_time.day, g_gps_date_time.week); // year, month, day, day of week + rtc_set_time(RTC, g_gps_date_time.hour, g_gps_date_time.minute, g_gps_date_time.second); // hour, minute, second + } + else +#endif + { + g_gpsTimeSync = true; + } + } +} + + +void sd_card_maintenance(void) +{ + static Ctrl_status statusLast = CTRL_NO_PRESENT; + Ctrl_status status = sd_mmc_test_unit_ready(0); +// FRESULT res; + + if( status != statusLast ) + { // Event + statusLast = status; + + switch(status) + { + case CTRL_GOOD: // Card inserted and ready + s_sd_card_ready = true; + g_status.evbStatus |= EVB_STATUS_SD_CARD_READY; + break; + + case CTRL_NO_PRESENT: // Card removed + s_sd_card_ready = false; + g_status.evbStatus &= ~EVB_STATUS_SD_CARD_READY; + printf_mutex("Card removed\r\n"); + break; + } + } +} + + +void sd_card_logger_init(void) +{ + /* Initialize SD MMC stack */ + sd_mmc_init(); + + /* Initialize FatFs handle: g_fs */ + memset(&s_fs, 0, sizeof(FATFS)); + f_mount(LUN_ID_SD_MMC_0_MEM, &s_fs); + + /* Init real-time clock: RTC configuration, 24-hour mode */ + rtc_set_hour_mode(RTC, 0); + +#if USE_RTC_DATE_TIME + /* Init real-time clock */ + if((RTC->RTC_CR & (RTC_CR_UPDTIM | RTC_CR_UPDCAL)) != 0) //Make sure RTC is running + RTC->RTC_CR &= ~(RTC_CR_UPDTIM | RTC_CR_UPDCAL); + + rtc_set_time(RTC, 1, 1, 1); // hour, minute, second + rtc_set_date(RTC, 2018, 1, 1, dateToWeekDay(2018, 1, 1)); // year, month, day, week +#endif +} \ No newline at end of file diff --git a/EVB-2/IS_EVB-2/src/sd_card_logger.h b/EVB-2/IS_EVB-2/src/sd_card_logger.h new file mode 100644 index 000000000..1cae77061 --- /dev/null +++ b/EVB-2/IS_EVB-2/src/sd_card_logger.h @@ -0,0 +1,30 @@ +/* +MIT LICENSE + +Copyright 2014-2019 Inertial Sense, Inc. - http://inertialsense.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions : + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +#ifndef __SD_CARD_LOGGER_H_ +#define __SD_CARD_LOGGER_H_ + +#include "globals.h" +#include "../../../src/ISLogger.h" + +void refresh_led_log(void); + +void enable_logger(bool enable); +void step_logger_control(cISLogger& logger, is_comm_instance_t &comm); +void log_ublox_raw_to_SD(cISLogger& logger, uint8_t *dataPtr, uint32_t dataSize); + +void time_sync_from_uINS(void); + +void sd_card_maintenance(void); +void sd_card_logger_init(void); + +#endif // __SD_CARD_LOGGER_H_ \ No newline at end of file diff --git a/EVB-2/IS_EVB-2/src/spiTouINS.c b/EVB-2/IS_EVB-2/src/spiTouINS.c new file mode 100644 index 000000000..369e89214 --- /dev/null +++ b/EVB-2/IS_EVB-2/src/spiTouINS.c @@ -0,0 +1,694 @@ +/* +MIT LICENSE + +Copyright 2014-2019 Inertial Sense, Inc. - http://inertialsense.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions : + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +#include +#include "spiTouINS.h" +#include "ISBoards.h" +#include "d_dma.h" +#include "rtos.h" + +#define SPI_INS_BAUDRATE 10000000UL + +// SPI Channel +#define SPI_INS_BASE SPI0 +#define SPI_INS_CHIP_SEL 2 +#define SPI_spiTouINS_Handler SPI0_Handler +#define SPI_IRQn SPI0_IRQn +#define SPI_XDMAC_TX_CH_NUM 1 +#define SPI_XDMAC_RX_CH_NUM 2 + +// Clock polarity & phase. Set to mode 3. +#define SPI_INS_CLK_POLARITY 1 +#define SPI_INS_CLK_PHASE 0 + +// Delay before SPCK. +#define SPI_DLYBS 0x10 + +// Delay between consecutive transfers. +#define SPI_DLYBCT 0x03 + +#define TX_BUFFER_SIZE 512 +#define RX_BUFFER_SIZE 2048 //Needs to be a power of 2 (2^x) +#define RX_INT_BUFFER_SIZE 1024 //Needs to be a power of 2 (2^x) + +#define READ_SIZE 100 +#define READ_ADDITIONAL_SIZE 20 + +COMPILER_ALIGNED(32) static volatile uint8_t TxBuf[TX_BUFFER_SIZE]; +COMPILER_ALIGNED(32) static volatile uint8_t TxBlank[READ_SIZE]; +COMPILER_ALIGNED(32) static volatile uint8_t RxBuf[RX_BUFFER_SIZE]; +COMPILER_ALIGNED(32) static volatile uint8_t RxBufInternal[RX_INT_BUFFER_SIZE]; +static volatile uint32_t rxfptr = 0, rxbptr = 0, rxintptr = 0; +static volatile uint8_t *txfptr = TxBuf; + +//Pointers for the lld_view0 array +volatile uint32_t lld_fptr; +volatile uint32_t lld_bptr; + +// DMA linked list descriptor used for reload +#define DMA_LLD_COUNT 32 //Must be 2^x in size +#define DMA_LLD_MASK (DMA_LLD_COUNT - 1) +COMPILER_WORD_ALIGNED volatile lld_view0 lld[DMA_LLD_COUNT]; +COMPILER_WORD_ALIGNED volatile lld_view0 rx_lld; + +static void sendMoreData(int len); + +//Task stuff +#define TASK_SPI_TO_UINS_STACK_SIZE (512/sizeof(portSTACK_TYPE)) +#define TASK_SPI_TO_UINS_PRIORITY (configMAX_PRIORITIES - 2) // We want this to be the highest priority - Only timer task higher +#define TASK_SPI_TO_UINS_PERIOD_MS 1 +static TaskHandle_t xHandlingTask; + +void XDMAC_spiTouINS_Handler(void) +{ + if( (xdmac_channel_get_interrupt_status(XDMAC, DMA_CH_EVB_SPI_INS_TX) & XDMAC_CIS_BIS) && (xdmac_channel_get_interrupt_mask(XDMAC, DMA_CH_EVB_SPI_INS_TX) & XDMAC_CIE_BIE) ) + { + //Check to see if DMA is finished (as indicated by channel becoming disabled) + if ((XDMAC->XDMAC_GS & (XDMAC_GS_ST0 << DMA_CH_EVB_SPI_INS_TX)) == 0) + { + if(lld_bptr != lld_fptr) //Not equal means there is data ready to send + { + //Setup TX DMA + xdmac_channel_set_source_addr(XDMAC, DMA_CH_EVB_SPI_INS_TX, lld[lld_bptr].mbr_ta); + xdmac_channel_set_microblock_control(XDMAC, DMA_CH_EVB_SPI_INS_TX, lld[lld_bptr].mbr_ubc); + + //Move pointer + lld_bptr = (lld_bptr + 1) & DMA_LLD_MASK; + + //Enable - We don't need to clean cache as DMA data is already flushed to main memory + XDMAC->XDMAC_GE = (XDMAC_GE_EN0 << DMA_CH_EVB_SPI_INS_TX); + } + else + { + //We are done with the list + xdmac_channel_disable_interrupt(XDMAC, DMA_CH_EVB_SPI_INS_TX, XDMAC_CIE_BIE); + + //See if we need to receive more or lower CS line + if(ioport_get_pin_level(INS_DATA_RDY_PIN_IDX)) + { + //Keep receiving + sendMoreData(READ_ADDITIONAL_SIZE); + } + else + { + spi_enable_interrupt(SPI_INS_BASE, SPI_IER_TDRE); + } + } + + //Notify task to process data + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + xTaskNotifyFromISR(g_rtos.task[EVB_TASK_SPI_UINS_COM].handle, 1, eSetBits, &xHigherPriorityTaskWoken); + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); + } + } +} + +void SPI_spiTouINS_Handler(void) +{ + static volatile bool inDataPacket = false; + + uint32_t spi_statusReg; + +// PIOC->PIO_SODR = 1U << 20; + + if((SPI_INS_BASE->SPI_IMR & SPI_IMR_TDRE) && (SPI_INS_BASE->SPI_SR & SPI_SR_TXEMPTY)) + { + //Turn off interrupt as we are either done or sending more data + spi_disable_interrupt(SPI_INS_BASE, SPI_IER_TDRE); + + if(inDataPacket || ioport_get_pin_level(INS_DATA_RDY_PIN_IDX)) + { + //Keep receiving + sendMoreData(READ_ADDITIONAL_SIZE); + } + else + { + //Deactivate CS line + ioport_set_pin_level(SPI_INS_CS_PIN, IOPORT_PIN_LEVEL_HIGH); + + //Enable Data Ready interrupt + pio_get_interrupt_status(INS_DATA_RDY_PIN_PIO); + pio_enable_interrupt(INS_DATA_RDY_PIN_PIO, INS_DATA_RDY_PIN_MASK); + } + } + +// PIOC->PIO_CODR = 1U << 20; +} + +static void PIO_DataReady_Handler(uint32_t id, uint32_t mask) +{ + //Clear interrupt by reading status + pio_get_interrupt_status(INS_DATA_RDY_PIN_PIO); + + if (INS_DATA_RDY_PIN_ID == id && (INS_DATA_RDY_PIN_MASK & mask)) + { + pio_disable_interrupt(INS_DATA_RDY_PIN_PIO, INS_DATA_RDY_PIN_MASK); + + //Start transmission + sendMoreData(READ_SIZE); + } +} + +static void spiTouINS_task(void *pvParameters) +{ + UNUSED(pvParameters); + static volatile bool inDataPacket = false; + + while(1) + { +// PIOC->PIO_CODR = 1U << 20; + + //Wait to be notified by interrupt + xTaskNotifyWait( pdFALSE, 0xFFFFFFFFUL, 0, pdMS_TO_TICKS(1000)); + +// PIOC->PIO_SODR = 1U << 20; + + //Check and process any data in the internal buffer into the external buffer. + + //Flush FIFO, content of the FIFO is written to memory + xdmac_channel_software_flush_request(XDMAC, DMA_CH_EVB_SPI_INS_RX); + + //Find how much data we have + uint32_t bytesReady; + uint32_t curDmaAddr = (uint32_t)XDMAC->XDMAC_CHID[DMA_CH_EVB_SPI_INS_RX].XDMAC_CDA - (uint32_t)RxBufInternal; + if (curDmaAddr < rxintptr) + bytesReady = RX_INT_BUFFER_SIZE - rxintptr + curDmaAddr; + else + bytesReady = curDmaAddr - rxintptr; + + for(uint32_t i=0; iSPI_RDR); + cfg.mbr_da = (uint32_t)RxBufInternal; + cfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | + XDMAC_CC_MEMSET_NORMAL_MODE | + XDMAC_CC_DSYNC_PER2MEM | + XDMAC_CC_MBSIZE_SINGLE | + XDMAC_CC_DWIDTH_BYTE | + XDMAC_CC_SIF_AHB_IF1 | + XDMAC_CC_DIF_AHB_IF1 | + XDMAC_CC_SAM_FIXED_AM | + XDMAC_CC_DAM_INCREMENTED_AM | + XDMAC_CC_PERID(SPI_XDMAC_RX_CH_NUM); + cfg.mbr_ubc = RX_INT_BUFFER_SIZE; + xdmac_configure_transfer(XDMAC, DMA_CH_EVB_SPI_INS_RX, &cfg); + + // Configure linked list descriptor (only uses one) + rx_lld.mbr_ta = (uint32_t)RxBufInternal; + rx_lld.mbr_nda = (uint32_t)&rx_lld; // point to self + rx_lld.mbr_ubc = + XDMAC_UBC_NVIEW_NDV0 | + XDMAC_UBC_NDE_FETCH_EN | + XDMAC_UBC_NDEN_UPDATED | + RX_INT_BUFFER_SIZE; + + // Set initial descriptor control + xdmac_channel_set_descriptor_control(XDMAC, DMA_CH_EVB_SPI_INS_RX, //Updates CNDC register + XDMAC_CNDC_NDVIEW_NDV0 | + XDMAC_CNDC_NDE_DSCR_FETCH_EN | + XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED); + xdmac_channel_set_descriptor_addr(XDMAC, DMA_CH_EVB_SPI_INS_RX, (uint32_t)&rx_lld, 0); //Updates CNDA register + + rxintptr = 0; + SCB_CLEAN_DCACHE_BY_ADDR_32BYTE_ALIGNED(&rx_lld, sizeof(rx_lld)); + XDMAC->XDMAC_GE = (XDMAC_GE_EN0 << DMA_CH_EVB_SPI_INS_RX); + +//Configure task for processing incoming data + createTask(EVB_TASK_SPI_UINS_COM, spiTouINS_task, "SPI_UINS", TASK_SPI_TO_UINS_STACK_SIZE, NULL, TASK_SPI_TO_UINS_PRIORITY, TASK_SPI_TO_UINS_PERIOD_MS, TASK_SPI_TO_UINS_PERIOD_MS); + +//DMA for outgoing + cfg.mbr_sa = (uint32_t)TxBuf; + cfg.mbr_da = (uint32_t)&(SPI_INS_BASE->SPI_TDR); + cfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | + XDMAC_CC_MEMSET_NORMAL_MODE | + XDMAC_CC_DSYNC_MEM2PER | + XDMAC_CC_MBSIZE_SINGLE | + XDMAC_CC_CSIZE_CHK_1 | + XDMAC_CC_DWIDTH_BYTE | + XDMAC_CC_SIF_AHB_IF1 | + XDMAC_CC_DIF_AHB_IF1 | + XDMAC_CC_SAM_INCREMENTED_AM | + XDMAC_CC_DAM_FIXED_AM | + XDMAC_CC_PERID(SPI_XDMAC_TX_CH_NUM); + cfg.mbr_ubc = 0; + xdmac_configure_transfer(XDMAC, DMA_CH_EVB_SPI_INS_TX, &cfg); + + //Setup pointers to lld array + lld_fptr = 0; + lld_bptr = 0; + + //Setup interrupts for DMA for UART mode (gets multiple setups as this routine is called for multiple USARTs) + NVIC_ClearPendingIRQ(XDMAC_IRQn); + NVIC_SetPriority(XDMAC_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); //Must not be higher than RTOS allows + NVIC_EnableIRQ(XDMAC_IRQn); + +//Setup data ready pin + pio_handler_set(INS_DATA_RDY_PIN_PIO, INS_DATA_RDY_PIN_ID, INS_DATA_RDY_PIN_MASK, PIO_DEBOUNCE | PIO_IT_HIGH_LEVEL, PIO_DataReady_Handler); + NVIC_EnableIRQ((IRQn_Type)INS_DATA_RDY_PIN_ID); + + //Enable Data Ready interrupt + pio_handler_set_priority(INS_DATA_RDY_PIN_PIO, (IRQn_Type) INS_DATA_RDY_PIN_ID, 3); + pio_get_interrupt_status(INS_DATA_RDY_PIN_PIO); + pio_enable_interrupt(INS_DATA_RDY_PIN_PIO, INS_DATA_RDY_PIN_MASK); + + //Haven't figured out why, but the first packet out is garbage so send one now + //Maybe it has something to do with the mode we are in, because before we send the data/clock lines are not in their default states + spi_write_single(SPI_INS_BASE, 0); +} + +//This routine is called by interrupts to read data out of the uINS +//Don't use outside this module. +static void sendMoreData(int len) +{ + pio_disable_interrupt(INS_DATA_RDY_PIN_PIO, INS_DATA_RDY_PIN_MASK); + spi_disable_interrupt(SPI_INS_BASE, SPI_IER_TDRE); + + //Check for sending overflow + if(((lld_fptr + 1) & DMA_LLD_MASK) == lld_bptr ) + return; //This isn't great + + // Setup DMA to transfer some more data + lld[lld_fptr].mbr_ta = (uint32_t)TxBlank; + lld[lld_fptr].mbr_ubc = XDMAC_UBC_UBLEN(len); + + // Move to next lld + lld_fptr = (lld_fptr + 1) & DMA_LLD_MASK; + + //Block interrupt handler from running and causing a double configure + NVIC_DisableIRQ(XDMAC_IRQn); + + //Enable DMA if it isn't running + if((XDMAC->XDMAC_GS & (XDMAC_GS_ST0 << DMA_CH_EVB_SPI_INS_TX)) == 0) + { + if(lld_bptr != lld_fptr) + { + //Activate CS line + ioport_set_pin_level(SPI_INS_CS_PIN, IOPORT_PIN_LEVEL_LOW); + + //Setup TX DMA + xdmac_channel_set_source_addr(XDMAC, DMA_CH_EVB_SPI_INS_TX, lld[lld_bptr].mbr_ta); + xdmac_channel_set_microblock_control(XDMAC, DMA_CH_EVB_SPI_INS_TX, lld[lld_bptr].mbr_ubc); + + //Move pointer + lld_bptr = (lld_bptr + 1) & DMA_LLD_MASK; + + // Enable DMA interrupt + xdmac_enable_interrupt(XDMAC, DMA_CH_EVB_SPI_INS_TX); + spi_disable_interrupt(SPI_INS_BASE, SPI_IER_TDRE); + xdmac_channel_enable_interrupt(XDMAC, DMA_CH_EVB_SPI_INS_TX, XDMAC_CIE_BIE); + + //Enable - cache should have already been cleaned + XDMAC->XDMAC_GE = (XDMAC_GE_EN0 << DMA_CH_EVB_SPI_INS_TX); + } + } + + NVIC_EnableIRQ(XDMAC_IRQn); +} + +static uint32_t getTxFree(void) +{ + if ((XDMAC->XDMAC_GS & (XDMAC_GS_ST0 << DMA_CH_EVB_SPI_INS_TX)) == 0) + return TX_BUFFER_SIZE; + + uint8_t* curDmaAddr = XDMAC->XDMAC_CHID[DMA_CH_EVB_SPI_INS_TX].XDMAC_CDA; + + if (txfptr < curDmaAddr) + return (int)(curDmaAddr - txfptr); + else + return TX_BUFFER_SIZE - (int)(txfptr - curDmaAddr); +} + +int spiTouINS_serWrite(const unsigned char *buf, int size) +{ + if (size <= 0) return 0; + if (g_rtos.task[EVB_TASK_SPI_UINS_COM].handle == 0) return 0; //Block executing if we have not been configured + + //Disable interrupt so we don't get double writes + pio_disable_interrupt(INS_DATA_RDY_PIN_PIO, INS_DATA_RDY_PIN_MASK); + spi_disable_interrupt(SPI_INS_BASE, SPI_IER_TDRE); + + // Bytes free in DMA buffer + int dmaFreeBytes = getTxFree(); + + taskENTER_CRITICAL(); + + // Limit size + if (size > dmaFreeBytes || ((lld_fptr + 1) & DMA_LLD_MASK) == lld_bptr ) + return 0; + + ////////////////////////////////////////////////////////////////////////// + // Copy into DMA buffer + // Bytes before end of DMA buffer + int bytesToEnd = (TxBuf + TX_BUFFER_SIZE) - txfptr; + + // Add data to ring buffer + if (size <= bytesToEnd) + { + // Don't need to wrap + // Copy data into DMA buffer + MEMCPY_DCACHE_CLEAN(txfptr, buf, size); + + // Setup DMA + lld[lld_fptr].mbr_ta = (uint32_t)txfptr; + lld[lld_fptr].mbr_ubc = XDMAC_UBC_UBLEN(size); + + // Increment buffer pointer + txfptr += size; + + // Move to next lld + lld_fptr = (lld_fptr + 1) & DMA_LLD_MASK; + } + else // Need to wrap + { + // Bytes to write at buffer start + int bytesWrapped = size - bytesToEnd; + uint32_t bufptr = lld_fptr; + int count = 1; + + //Write out data needed to fill the end of the buffer + if (bytesToEnd) + { + // Not already at buffer end. Fill buffer to end. + // Copy data into DMA buffer & update transfer size + MEMCPY_DCACHE_CLEAN(txfptr, buf, bytesToEnd); + + // Setup DMA for end + lld[bufptr].mbr_ta = (uint32_t)txfptr; + lld[bufptr].mbr_ubc = XDMAC_UBC_UBLEN(bytesToEnd); + + // Move to next lld + bufptr = (bufptr + 1) & DMA_LLD_MASK; + count++; + } + + // Copy data into DMA buffer start & update pointer + MEMCPY_DCACHE_CLEAN(TxBuf, buf + bytesToEnd, bytesWrapped); + + // Setup DMA for beginning + lld[bufptr].mbr_ta = (uint32_t)TxBuf; + lld[bufptr].mbr_ubc = XDMAC_UBC_UBLEN(bytesWrapped); + + // Increment buffer pointer + txfptr = TxBuf + bytesWrapped; + + // Move to next lld + lld_fptr = (lld_fptr + count) & DMA_LLD_MASK; + } + + ////////////////////////////////////////////////////////////////////////// + // Transfer out of DMA buffer + + //Block interrupt handler from running and causing a double configure + NVIC_DisableIRQ(XDMAC_IRQn); + + //Enable DMA if it isn't running + if((XDMAC->XDMAC_GS & (XDMAC_GS_ST0 << DMA_CH_EVB_SPI_INS_TX)) == 0) + { + if(lld_bptr != lld_fptr) + { + //Activate CS line + ioport_set_pin_level(SPI_INS_CS_PIN, IOPORT_PIN_LEVEL_LOW); + + //Setup TX DMA + xdmac_channel_set_source_addr(XDMAC, DMA_CH_EVB_SPI_INS_TX, lld[lld_bptr].mbr_ta); + xdmac_channel_set_microblock_control(XDMAC, DMA_CH_EVB_SPI_INS_TX, lld[lld_bptr].mbr_ubc); + + //Move pointer + lld_bptr = (lld_bptr + 1) & DMA_LLD_MASK; + + // Enable DMA interrupt + xdmac_enable_interrupt(XDMAC, DMA_CH_EVB_SPI_INS_TX); + spi_disable_interrupt(SPI_INS_BASE, SPI_IER_TDRE); + xdmac_channel_enable_interrupt(XDMAC, DMA_CH_EVB_SPI_INS_TX, XDMAC_CIE_BIE); + + //Enable - cache should have already been cleaned + XDMAC->XDMAC_GE = (XDMAC_GE_EN0 << DMA_CH_EVB_SPI_INS_TX); + } + } + + NVIC_EnableIRQ(XDMAC_IRQn); + + taskEXIT_CRITICAL(); + + return size; +} + +int spiTouINS_dataReady(void) +{ + int dataAvail = rxfptr - rxbptr; + if(dataAvail < 0) + return RX_BUFFER_SIZE + dataAvail; + else + return dataAvail; +} + +int spiTouINS_serRead(unsigned char *buf, int size) +{ + if(rxfptr == rxbptr) //No data available. + return 0; + + int dataAvail = rxfptr - rxbptr; + + if(dataAvail < 0) //Take care of buffer wrap + { + // Limit to bytes available + size = Min(size, RX_BUFFER_SIZE + dataAvail); + int bytesToEnd = RX_BUFFER_SIZE - rxbptr; + + // Copy data + if(size <= bytesToEnd) + { + memcpy(buf, (const uint8_t*)&RxBuf[rxbptr], size); + } + else + { + memcpy(buf, (const uint8_t*)&RxBuf[rxbptr], bytesToEnd); + memcpy(&buf[bytesToEnd], (const uint8_t*)RxBuf, size - bytesToEnd); + } + } + else + { + // Limit to bytes available + size = Min(size, dataAvail); + + // Copy data + memcpy(buf, (const uint8_t*)&RxBuf[rxbptr], size); + } + + // Move pointer + rxbptr = (rxbptr + size) & (RX_BUFFER_SIZE - 1); + + return size; +} + + + +void test_spiTouINS(void) +{ +#if 0 + vTaskDelay(1000); + udi_cdc_write_buf("Testing\r\n", 9); + + //Clear uINS buffer + { + #define SIZE 500 + uint8_t buf[SIZE]; + buf[0] = 0xFF; + buf[1] = 0xFE; + for(int i=2; i= 100) + seed = 0; + total += tx_len; + + //Send data + spiTouINS_serWrite(tx_buf, tx_len); + + //Wait for TX/RX (with timeout) + volatile uint32_t j=20000; + while(spiTouINS_dataReady() < tx_len) + { + if(--j == 0) + break; + } + + //Read data + rx_len = spiTouINS_serRead(rx_buf, BUF_SIZE); + + if(tx_len != rx_len) + { + len = sprintf(str, "len %d %d %d\r\n", tx_len, rx_len, packet_count); + udi_cdc_write_buf(str, len); + } + + bool issue = false; + for(int i=0;iRTC_SR & RTC_SR_SEC) == RTC_SR_SEC) + { + RTC->RTC_SCCR = RTC_SCCR_SECCLR; + + if(++seconds >= 10) + { + len = sprintf(str, "Packets %d, failures %d, rate %.01f kB/s (each direction)\r\n", packet_count, failure, (float)(total / seconds) / 1000.0); + udi_cdc_write_buf(str, len); + + total = 0; + seconds = 0; + } + + } + } +#endif + +#if 0 + while(1) + { + #define BUF_SIZE 256 + uint8_t buf[BUF_SIZE]; + int len; + + //USB -> SPI + while(udi_cdc_is_rx_ready()) + { + len = udi_cdc_read_no_polling(buf, BUF_SIZE); + spiTouINS_serWrite(buf, len); + } + + //SPI -> USB + while((len = spiTouINS_serRead(buf, BUF_SIZE)) > 0) + { + if(g_usb_cdc_open && udi_cdc_is_tx_ready()) + { + udi_cdc_write_buf(buf, len); + } + } + + vTaskDelay(1); + } +#endif + +} diff --git a/EVB-2/IS_EVB-2/src/spiTouINS.h b/EVB-2/IS_EVB-2/src/spiTouINS.h new file mode 100644 index 000000000..2dbcca3fd --- /dev/null +++ b/EVB-2/IS_EVB-2/src/spiTouINS.h @@ -0,0 +1,31 @@ +/* +MIT LICENSE + +Copyright 2014-2019 Inertial Sense, Inc. - http://inertialsense.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions : + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +#ifndef SPITOUINS_H_ +#define SPITOUINS_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +void spiTouINS_init(void); +int spiTouINS_serWrite(const unsigned char *buf, int size); +int spiTouINS_serRead(unsigned char *buf, int size); +int spiTouINS_dataReady(void); +void XDMAC_spiTouINS_Handler(void); + +void test_spiTouINS(void); + +#ifdef __cplusplus + } +#endif +#endif /* SPITOUINS_H_ */ \ No newline at end of file diff --git a/EVB-2/IS_EVB-2/src/user_interface.cpp b/EVB-2/IS_EVB-2/src/user_interface.cpp new file mode 100644 index 000000000..aa8fd8176 --- /dev/null +++ b/EVB-2/IS_EVB-2/src/user_interface.cpp @@ -0,0 +1,249 @@ +/* +MIT LICENSE + +Copyright 2014-2019 Inertial Sense, Inc. - http://inertialsense.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions : + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +#include +#include "globals.h" +#include "sd_card_logger.h" +#include "communications.h" +#include "user_interface.h" + + +static VoidFuncPtrVoid s_funcPtrCfgButtonPressed = NULL; +static VoidFuncPtrVoid s_funcPtrCfgButtonRelease = NULL; +static VoidFuncPtrVoid s_funcPtrLogButtonPressed = NULL; +static VoidFuncPtrVoid s_funcPtrLogButtonRelease = NULL; +static VoidFuncPtrVoid s_funcPtrBothButtonsPressed = NULL; +static VoidFuncPtrVoid s_funcPtrBothButtonsRelease = NULL; + +static VoidFuncPtrVoid s_funcPtrRefreshLedCfg = NULL; +static VoidFuncPtrVoid s_funcPtrRefreshLedLog = NULL; + +bool logger_ready() +{ + return (g_status.evbStatus&EVB_STATUS_SD_CARD_READY) && !(g_status.evbStatus&EVB_STATUS_SD_ERR_CARD_MASK); +} + + +static void on_cfg_button_pressed() +{ + // Indicate button is pressed by turning off LED + LED_CFG_OFF(); +} + +static void on_cfg_button_release() +{ + // Increment config + g_flashCfg->cbPreset++; + + switch(g_flashCfg->cbPreset) + { // Skip these configs +#ifndef CONF_BOARD_SPI_ATWINC_WIFI + case EVB2_CB_PRESET_RS422_WIFI: +#endif +#ifndef CONF_BOARD_SPI_UINS + case EVB2_CB_PRESET_SPI_RS232: +#endif + g_flashCfg->cbPreset++; + } + + // Restart config + if(g_flashCfg->cbPreset >= EVB2_CB_PRESET_COUNT) + { + g_flashCfg->cbPreset = 1; + } + + com_bridge_apply_preset(g_flashCfg); + board_IO_config(); + nvr_flash_config_write_needed(); + nvr_flash_config_write_enable(); + evbUiRefreshLedCfg(); +} + +static void on_log_button_pressed() +{ + // Indicate button is pressed by turning off LED + LED_LOG_OFF(); +} + +static void on_log_button_release() +{ + if( logger_ready() ) + { + if (!(g_flashCfg->bits & EVB_CFG_BITS_NO_STREAM_PPD_ON_LOG_BUTTON)) + { + uINS_stream_enable_PPD(); + } + + // Toggle logger enable + enable_logger(!g_loggerEnabled); + } +} + +static void on_both_buttons_pressed() +{ // Reset uINS + ioport_set_pin_output_mode(INS_RESET_PIN_PIN, IOPORT_PIN_LEVEL_LOW); +} + +static void on_both_buttons_release() +{ // De-assert uINS reset + ioport_set_pin_input_mode(INS_RESET_PIN_PIN, 0, 0); + evbUiRefreshLedCfg(); +} + + +#define BUTTON_DEBOUNCE_TIME_MS 100 +void step_user_interface(uint32_t time_ms) +{ + bool cfgBtnDown = !ioport_get_pin_level(BUTTON_CFG_PIN); + bool logBtnDown = !ioport_get_pin_level(BUTTON_LOG_PIN); + static bool bothBtnsDown = false; + static bool cfgBtnDownLast = cfgBtnDown; + static bool logBtnDownLast = logBtnDown; + static bool bothBtnsDownLast = bothBtnsDown; + static uint32_t cfgBtnTimeMs = 0; // for button debouncing + static uint32_t logBtnTimeMs = 0; + static uint32_t bothBtnTimeMs = 0; + static bool ignoreEstopBtnRelease=false; + static bool ignorePauseBtnRelease=false; + + if (cfgBtnDownLast != cfgBtnDown && time_ms-cfgBtnTimeMs > BUTTON_DEBOUNCE_TIME_MS) + { // Button toggled + cfgBtnDownLast = cfgBtnDown; + cfgBtnTimeMs = time_ms; + if(cfgBtnDown) + { + if(s_funcPtrCfgButtonPressed){ s_funcPtrCfgButtonPressed(); } + } + else + { + if(!ignoreEstopBtnRelease) + { + if(s_funcPtrCfgButtonRelease){ s_funcPtrCfgButtonRelease(); } + } + ignoreEstopBtnRelease = false; + } + } + + if(logBtnDownLast != logBtnDown && time_ms-logBtnTimeMs > BUTTON_DEBOUNCE_TIME_MS) + { // Button toggled + logBtnDownLast = logBtnDown; + logBtnTimeMs = time_ms; + if(logBtnDown) + { + if(s_funcPtrLogButtonPressed){ s_funcPtrLogButtonPressed(); } + } + else + { + if(!ignorePauseBtnRelease) + { + if(s_funcPtrLogButtonRelease){ s_funcPtrLogButtonRelease(); } + } + ignorePauseBtnRelease = false; + } + } + + // Only toggle down on both down and up on both up. + if (bothBtnsDown) + { + if(!cfgBtnDown && !logBtnDown) + { + bothBtnsDown = false; + } + } + else + { + if(cfgBtnDown && logBtnDown) + { + bothBtnsDown = true; + } + } + + if(bothBtnsDownLast != bothBtnsDown && time_ms-bothBtnTimeMs > BUTTON_DEBOUNCE_TIME_MS) + { // Both buttons toggled + bothBtnsDownLast = bothBtnsDown; + bothBtnTimeMs = time_ms; + if(bothBtnsDown) + { + if(s_funcPtrBothButtonsPressed){ s_funcPtrBothButtonsPressed(); } + ignoreEstopBtnRelease = true; + ignorePauseBtnRelease = true; + } + else + { + if(s_funcPtrBothButtonsRelease){ s_funcPtrBothButtonsRelease(); } + } + } + + if( logger_ready() ) + { // Handle logger commands via g_status.loggerMode + if(g_status.loggerMode!=EVB2_LOG_NA) + { + switch(g_status.loggerMode) + { + case EVB2_LOG_CMD_START: enable_logger(true); break; + case EVB2_LOG_CMD_STOP: enable_logger(false); break; // disable logger + } + g_status.loggerMode = EVB2_LOG_NA; + } + } + else + { + if(g_loggerEnabled==1) + { // Disable logger + enable_logger(false); + } + } +} + + +void evbUiDefaults() +{ + s_funcPtrCfgButtonPressed = on_cfg_button_pressed; + s_funcPtrCfgButtonRelease = on_cfg_button_release; + s_funcPtrLogButtonPressed = on_log_button_pressed; + s_funcPtrLogButtonRelease = on_log_button_release; + s_funcPtrBothButtonsPressed = on_both_buttons_pressed; + s_funcPtrBothButtonsRelease = on_both_buttons_release; + + s_funcPtrRefreshLedCfg = refresh_led_cfg; + s_funcPtrRefreshLedLog = refresh_led_log; +} + +void evbUiButtonCallbacks( + VoidFuncPtrVoid fpCfgButtonPressed, VoidFuncPtrVoid fpCfgButtonRelease, + VoidFuncPtrVoid fpLogButtonPressed, VoidFuncPtrVoid fpLogButtonRelease, + VoidFuncPtrVoid fpBothButtonsPressed, VoidFuncPtrVoid fpBothButtonsRelease ) +{ + s_funcPtrCfgButtonPressed = fpCfgButtonPressed; + s_funcPtrCfgButtonRelease = fpCfgButtonRelease; + s_funcPtrLogButtonPressed = fpLogButtonPressed; + s_funcPtrLogButtonRelease = fpLogButtonRelease; + s_funcPtrBothButtonsPressed = fpBothButtonsPressed; + s_funcPtrBothButtonsRelease = fpBothButtonsRelease; +} + +void evbUiLedCallbacks(VoidFuncPtrVoid fpLedCfg, VoidFuncPtrVoid fpLedLog ) +{ + s_funcPtrRefreshLedCfg = fpLedCfg; + s_funcPtrRefreshLedLog = fpLedLog; +} + +void evbUiRefreshLedCfg() +{ + if(s_funcPtrRefreshLedCfg){ s_funcPtrRefreshLedCfg(); } +} + +void evbUiRefreshLedLog() +{ + if(s_funcPtrRefreshLedLog){ s_funcPtrRefreshLedLog(); } +} + diff --git a/EVB-2/IS_EVB-2/src/user_interface.h b/EVB-2/IS_EVB-2/src/user_interface.h new file mode 100644 index 000000000..c012ed050 --- /dev/null +++ b/EVB-2/IS_EVB-2/src/user_interface.h @@ -0,0 +1,32 @@ +/* +MIT LICENSE + +Copyright 2014-2019 Inertial Sense, Inc. - http://inertialsense.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions : + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +#ifndef __USER_INTERFACE_H_ +#define __USER_INTERFACE_H_ + +typedef void (*VoidFuncPtrVoid)(void); + +void step_user_interface(uint32_t time_ms); + +void evbUiDefaults(); +void evbUiButtonCallbacks( + VoidFuncPtrVoid fpCfgButtonPressed, VoidFuncPtrVoid fpCfgButtonRelease, + VoidFuncPtrVoid fpLogButtonPressed, VoidFuncPtrVoid fpLogButtonRelease, + VoidFuncPtrVoid fpBothButtonsPressed, VoidFuncPtrVoid fpBothButtonsRelease ); +void evbUiLedCallbacks(VoidFuncPtrVoid fpLedCfg, VoidFuncPtrVoid fpLedLog ); + +void evbUiRefreshLedCfg(); +void evbUiRefreshLedLog(); + + +#endif // __USER_INTERFACE_H_ + diff --git a/EVB-2/IS_EVB-2/src/version/buildInfo.h b/EVB-2/IS_EVB-2/src/version/buildInfo.h new file mode 100644 index 000000000..4954e058f --- /dev/null +++ b/EVB-2/IS_EVB-2/src/version/buildInfo.h @@ -0,0 +1,8 @@ +#define BUILD_NUMBER 72 +#define BUILD_DATE_YEAR 2024 +#define BUILD_DATE_MONTH 2 +#define BUILD_DATE_DAY 19 +#define BUILD_TIME_HOUR 15 +#define BUILD_TIME_MINUTE 06 +#define BUILD_TIME_SECOND 40 +#define BUILD_TIME_MILLISECOND 82 diff --git a/EVB-2/IS_EVB-2/src/version/repositoryInfo.h b/EVB-2/IS_EVB-2/src/version/repositoryInfo.h new file mode 100644 index 000000000..fa110a131 --- /dev/null +++ b/EVB-2/IS_EVB-2/src/version/repositoryInfo.h @@ -0,0 +1,5 @@ +#define REPO_DESCRIPTION "2.0.3" +#define REPO_VERSION_MAJOR 2 +#define REPO_VERSION_MINOR 0 +#define REPO_VERSION_REVIS 3 +#define REPO_HEAD_COUNT 1 diff --git a/EVB-2/IS_EVB-2/src/version/version.h b/EVB-2/IS_EVB-2/src/version/version.h new file mode 100644 index 000000000..e035ad17a --- /dev/null +++ b/EVB-2/IS_EVB-2/src/version/version.h @@ -0,0 +1,24 @@ +#ifndef VERSION_H +#define VERSION_H + +#include "repositoryInfo.h" +#include "buildInfo.h" +#include "ISBoards.h" + +#define HARDWARE_VERSION_CHAR0 2 +#define HARDWARE_VERSION_CHAR1 0 +#define HARDWARE_VERSION_CHAR2 (g_hdw_detect) +#define HARDWARE_VERSION_CHAR3 0 + +#define FIRMWARE_VERSION_CHAR0 REPO_VERSION_MAJOR +#define FIRMWARE_VERSION_CHAR1 REPO_VERSION_MINOR +#define FIRMWARE_VERSION_CHAR2 REPO_VERSION_REVIS +#define FIRMWARE_VERSION_CHAR3 0 // firmware specific revision + + +extern uint8_t g_hdw_detect; // (see eEvbHdwDetectVersion) + + + + +#endif // VERSION_H diff --git a/EVB-2/IS_EVB-2/src/wheel_encoder.cpp b/EVB-2/IS_EVB-2/src/wheel_encoder.cpp new file mode 100644 index 000000000..0fb587806 --- /dev/null +++ b/EVB-2/IS_EVB-2/src/wheel_encoder.cpp @@ -0,0 +1,133 @@ +/* +MIT LICENSE + +Copyright 2014-2019 Inertial Sense, Inc. - http://inertialsense.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions : + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +#include +#include "globals.h" +#include "arm_math.h" +#include "drivers/d_quadEnc.h" +#include "wheel_encoder.h" + + +void init_wheel_encoder(void) +{ +#ifdef CONF_BOARD_QUAD_ENCODER + if(g_flashCfg->wheelCfgBits&WHEEL_CFG_BITS_ENABLE_ENCODER) + { + quadEncInit(4); // Sensing range: ~27ms + quadEncSetDirectionReverse(g_flashCfg->wheelCfgBits&WHEEL_CFG_BITS_DIRECTION_REVERSE_LEFT, g_flashCfg->wheelCfgBits&WHEEL_CFG_BITS_DIRECTION_REVERSE_RIGHT); + } +#endif +} + + +void step_wheel_encoder(is_comm_instance_t &comm) +{ +#ifdef CONF_BOARD_QUAD_ENCODER // Encoder Rx ======================================================= + + if(!(g_flashCfg->wheelCfgBits&WHEEL_CFG_BITS_ENABLE_ENCODER)) + { // Wheel encoders disabled + return; + } + + if(g_flashCfg->wheelCfgBits&WHEEL_CFG_BITS_ENCODER_SOURCE) + { + return; // EVB is providing wheel encoders + } + + int chL, chR; + bool dirL, dirR; + int n=0; + float periodL, periodR; + static int encoderSendTimeMs=0; + static wheel_encoder_t wheelEncoderLast = {0}; + + ++encoderSendTimeMs; + if(encoderSendTimeMs >= (int)g_flashCfg->velocityControlPeriodMs) + { + encoderSendTimeMs = 0; + + // Call read encoders +#if WHEEL_ENCODER_TIME_FROM_TOW == 1 + g_wheelEncoder.timeOfWeek = g_comm_time + g_towOffset; +#else + g_wheelEncoder.timeOfWeek = g_comm_time; +#endif + + g_wheelEncoderTimeMs = (uint32_t)round(g_wheelEncoder.timeOfWeek*1000.0); + quadEncReadPositionAll(&chL, &dirL, &chR, &dirR); + quadEncReadPeriodAll(&periodL, &periodR); + + // Set velocity direction + if(dirL) + { + periodL = -periodL; + } + if(dirR) + { + periodR = -periodR; + } + + // Convert encoder ticks to radians. + g_wheelEncoder.theta_l = (chL * g_flashCfg->encoderTickToWheelRad) * 0.25; /* Division by 4 to account for 4x encoding */ + g_wheelEncoder.theta_r = (chR * g_flashCfg->encoderTickToWheelRad) * 0.25; + + // Convert TC pulse period to rad/sec. + if(periodL!=0.0f) + { + g_wheelEncoder.omega_l = g_flashCfg->encoderTickToWheelRad / periodL; + } + else + { + g_wheelEncoder.omega_l = 0.0f; + } + if(periodR!=0.0f) + { + g_wheelEncoder.omega_r = g_flashCfg->encoderTickToWheelRad / periodR; + } + else + { + g_wheelEncoder.omega_r = 0.0f; + } + + // Encoder Wrap count (currently counting revolutions) +// g_wheelEncoder.wrap_count_l = g_wheelEncoder.theta_l / (2*PI); +// g_wheelEncoder.wrap_count_r = g_wheelEncoder.theta_r / (2*PI); + + uint8_t txBuf[512]; + + if (g_ermc.bits & ERMC_BITS_WHEEL_ENCODER) + { + n = is_comm_data_to_buf(txBuf, sizeof(txBuf), &comm, DID_WHEEL_ENCODER, sizeof(wheel_encoder_t), 0, (void*)&(g_wheelEncoder)); + +#if 1 // Send to uINS + comWrite(EVB2_PORT_UINS0, txBuf, n, LED_INS_TXD_PIN); +#else // Send to Luna + comWrite(EVB2_PORT_USB, txBuf, n, 0); +#endif + } + +#if 0 + n = is_comm_data(txBuf, sizeof(txBuf), &comm, DID_EVB_DEBUG_ARRAY, sizeof(debug_array_t), 0, (void*)&(g_debug)); + comWrite(EVB2_PORT_USB, txBuf, n, 0); +#endif + +#if 0 + n = is_comm_data(txBuf, sizeof(txBuf), &comm, DID_EVB_DEBUG_ARRAY, sizeof(debug_array_t), 0, (void*)&(g_debug)); + comWrite(EVB2_PORT_USB, txBuf, n, 0); +#endif + + // Update history + wheelEncoderLast = g_wheelEncoder; + } + +#endif +} \ No newline at end of file diff --git a/EVB-2/IS_EVB-2/src/wheel_encoder.h b/EVB-2/IS_EVB-2/src/wheel_encoder.h new file mode 100644 index 000000000..5555058c8 --- /dev/null +++ b/EVB-2/IS_EVB-2/src/wheel_encoder.h @@ -0,0 +1,23 @@ +/* +MIT LICENSE + +Copyright 2014-2019 Inertial Sense, Inc. - http://inertialsense.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions : + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +#ifndef __WHEEL_ENCODER_H_ +#define __WHEEL_ENCODER_H_ + + +void init_wheel_encoder(void); + +void step_wheel_encoder(is_comm_instance_t &comm); + + +#endif // __WHEEL_ENCODER_H_ + diff --git a/EVB-2/IS_EVB-2/src/wifi.c b/EVB-2/IS_EVB-2/src/wifi.c new file mode 100644 index 000000000..f689e9139 --- /dev/null +++ b/EVB-2/IS_EVB-2/src/wifi.c @@ -0,0 +1,423 @@ +/* +MIT LICENSE + +Copyright 2014-2019 Inertial Sense, Inc. - http://inertialsense.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions : + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +// #define WIFI_AUTH M2M_WIFI_SEC_WPA_PSK +// #define WIFI_SSID "BobaMachine" +// #define WIFI_PSK "pineapple" + +// #define WIFI_AUTH M2M_WIFI_SEC_WPA_PSK +// #define WIFI_SSID "Walt Johnson's iPhone" +// #define WIFI_PSK "magicctech" + +#define WIFI_AUTH M2M_WIFI_SEC_WPA_PSK +#define MAIN_WIFI_M2M_PRODUCT_NAME "EVB-2" + +#include +#include +#include "wifi.h" +#include "driver/include/m2m_wifi.h" +#include "driver/source/nmasic.h" +#include "common/include/nm_common.h" +#include "socket/include/socket.h" +#include "globals.h" + +extern StreamBufferHandle_t g_xStreamBufferWiFiRx; +extern StreamBufferHandle_t g_xStreamBufferWiFiTx; + +/** Socket for client */ +static SOCKET tcp_client_socket = -1; +static int g_init_wifi = 0; // 1=enable, -1=disable +static uint8_t g_wifi_connected = 0; + +static struct sockaddr_in g_addr = {0}; + +/** Message format definitions. */ +typedef struct s_msg_wifi_product { + uint8_t name[20]; +} t_msg_wifi_product; + +static t_msg_wifi_product msg_wifi_product = { + .name = MAIN_WIFI_M2M_PRODUCT_NAME, +}; + +/** Receive buffer definition. */ +#define WIFI_BUFFER_SIZE 1460 +static uint8_t socketRxBuffer[WIFI_BUFFER_SIZE]; +static uint8_t socketTxBuffer[WIFI_BUFFER_SIZE]; +static int g_indicateWiFiRxMs=0; + + +/** + * \brief Callback to get the Wi-Fi status update. + * + * \param[in] u8MsgType type of Wi-Fi notification. Possible types are: + * - [M2M_WIFI_RESP_CURRENT_RSSI](@ref M2M_WIFI_RESP_CURRENT_RSSI) + * - [M2M_WIFI_RESP_CON_STATE_CHANGED](@ref M2M_WIFI_RESP_CON_STATE_CHANGED) + * - [M2M_WIFI_RESP_CONNTION_STATE](@ref M2M_WIFI_RESP_CONNTION_STATE) + * - [M2M_WIFI_RESP_SCAN_DONE](@ref M2M_WIFI_RESP_SCAN_DONE) + * - [M2M_WIFI_RESP_SCAN_RESULT](@ref M2M_WIFI_RESP_SCAN_RESULT) + * - [M2M_WIFI_REQ_WPS](@ref M2M_WIFI_REQ_WPS) + * - [M2M_WIFI_RESP_IP_CONFIGURED](@ref M2M_WIFI_RESP_IP_CONFIGURED) + * - [M2M_WIFI_RESP_IP_CONFLICT](@ref M2M_WIFI_RESP_IP_CONFLICT) + * - [M2M_WIFI_RESP_P2P](@ref M2M_WIFI_RESP_P2P) + * - [M2M_WIFI_RESP_AP](@ref M2M_WIFI_RESP_AP) + * - [M2M_WIFI_RESP_CLIENT_INFO](@ref M2M_WIFI_RESP_CLIENT_INFO) + * \param[in] pvMsg A pointer to a buffer containing the notification parameters + * (if any). It should be casted to the correct data type corresponding to the + * notification type. Existing types are: + * - tstrM2mWifiStateChanged + * - tstrM2MWPSInfo + * - tstrM2MP2pResp + * - tstrM2MAPResp + * - tstrM2mScanDone + * - tstrM2mWifiscanResult + */ +static void wifi_cb(uint8_t u8MsgType, void *pvMsg) +{ + switch (u8MsgType) + { + case M2M_WIFI_RESP_CON_STATE_CHANGED: + { + tstrM2mWifiStateChanged *pstrWifiState = (tstrM2mWifiStateChanged *)pvMsg; + if (pstrWifiState->u8CurrState == M2M_WIFI_CONNECTED) + { + g_wifi_connected = 1; + g_status.evbStatus |= EVB_STATUS_WIFI_CONNECTED; + m2m_wifi_request_dhcp_client(); + } else if (pstrWifiState->u8CurrState == M2M_WIFI_DISCONNECTED) + { + g_wifi_connected = 0; + g_status.evbStatus &= ~EVB_STATUS_WIFI_CONNECTED; + char* wifi_ssid = (char*)(g_flashCfg->wifi[EVB_CFG_BITS_IDX_WIFI(g_flashCfg->bits)].ssid); + char* wifi_psk = (char*)(g_flashCfg->wifi[EVB_CFG_BITS_IDX_WIFI(g_flashCfg->bits)].psk); + m2m_wifi_connect(wifi_ssid, strlen(wifi_ssid), WIFI_AUTH, wifi_psk, M2M_WIFI_CH_ALL); + } + + break; + } + + case M2M_WIFI_REQ_DHCP_CONF: + { +// uint8_t *pu8IPAddress = (uint8_t *)pvMsg; +// printf("wifi_cb: M2M_WIFI_REQ_DHCP_CONF: IP is %u.%u.%u.%u\r\n", pu8IPAddress[0], pu8IPAddress[1], pu8IPAddress[2], pu8IPAddress[3]); + g_status.wifiIpAddr = *(uint32_t *)pvMsg; + break; + } + + default: + { + break; + } + } +} + + +/** + * \brief Callback to get the Data from socket. + * + * \param[in] sock socket handler. + * \param[in] u8Msg socket event type. Possible values are: + * - SOCKET_MSG_BIND + * - SOCKET_MSG_LISTEN + * - SOCKET_MSG_ACCEPT + * - SOCKET_MSG_CONNECT + * - SOCKET_MSG_RECV + * - SOCKET_MSG_SEND + * - SOCKET_MSG_SENDTO + * - SOCKET_MSG_RECVFROM + * \param[in] pvMsg is a pointer to message structure. Existing types are: + * - tstrSocketBindMsg + * - tstrSocketListenMsg + * - tstrSocketAcceptMsg + * - tstrSocketConnectMsg + * - tstrSocketRecvMsg + */ +static void socket_cb(SOCKET sock, uint8_t u8Msg, void *pvMsg) +{ + switch (u8Msg) { + /* Socket connected */ + case SOCKET_MSG_CONNECT: + { + tstrSocketConnectMsg *pstrConnect = (tstrSocketConnectMsg *)pvMsg; + if (pstrConnect && pstrConnect->s8Error >= 0) + { + //socket_cb: connect success! + //Start receive process + recv(tcp_client_socket, socketRxBuffer, sizeof(socketRxBuffer), 0); +// send(tcp_client_socket, &msg_wifi_product, sizeof(t_msg_wifi_product), 0); + } + else + { + //socket_cb: connect error! + close(tcp_client_socket); + tcp_client_socket = -1; + } + } + break; + + /* Message send */ + case SOCKET_MSG_SEND: + { + //socket_cb: send success! + LED_ON(LED_WIFI_TXD_PIN); + } + break; + + /* Message receive */ + case SOCKET_MSG_RECV: + { + tstrSocketRecvMsg *pstrRecv = (tstrSocketRecvMsg *)pvMsg; + if (pstrRecv && pstrRecv->s16BufferSize > 0) { + //socket_cb: recv success! + g_indicateWiFiRxMs = 20; + + if(g_flashCfg->cbf[EVB2_PORT_WIFI] & (1<s16BufferSize, 0); +#else + BEGIN_CRITICAL_SECTION + comWrite(EVB2_PORT_UINS1, socketRxBuffer, pstrRecv->s16BufferSize, LED_INS_TXD_PIN); + END_CRITICAL_SECTION +#endif + } + + //Start new receive process + recv(tcp_client_socket, socketRxBuffer, sizeof(socketRxBuffer), 0); + } else { + //socket_cb: recv error! + close(tcp_client_socket); + tcp_client_socket = -1; + } + } + + break; + + default: + break; + } +} + + +static void init_tcp_socket(void) +{ + if(tcp_client_socket != -1) + { + close(tcp_client_socket); + tcp_client_socket = -1; + } + + /* Initialize socket module */ + socketInit(); + registerSocketCallback(socket_cb, NULL); +} + + +static void deinit_tcp_socket(void) +{ + if(tcp_client_socket != -1) + { + close(tcp_client_socket); + tcp_client_socket = -1; + socketDeinit(); + } +} + + +void wifi_enable(int enable) +{ + if(enable) + { // Init wifi ONLY if it was off + if(!(g_status.evbStatus&EVB_STATUS_WIFI_ENABLED)) + { + g_init_wifi = 1; + } + } + else + { // Turn off wifi + g_init_wifi = -1; + } +} + + +void wifi_reinit(void) +{ + g_init_wifi = 1; +} + + +static void init_wifi(void) +{ + g_wifi_connected = 0; + g_status.evbStatus &= ~EVB_STATUS_WIFI_CONNECTED; + g_status.evbStatus |= EVB_STATUS_WIFI_ENABLED; + + tstrWifiInitParam param; + int8_t ret; + + /* Initialize the BSP. */ + nm_bsp_init(); + + /* Initialize Wi-Fi parameters structure. */ + memset((uint8_t *)¶m, 0, sizeof(tstrWifiInitParam)); + + /* Initialize socket address structure. */ + g_addr.sin_family = AF_INET; + g_addr.sin_addr.s_addr = g_flashCfg->server[EVB_CFG_BITS_IDX_SERVER(g_flashCfg->bits)].ipAddr.u32; + g_addr.sin_port = _htons(g_flashCfg->server[EVB_CFG_BITS_IDX_SERVER(g_flashCfg->bits)].port); + + /* Initialize Wi-Fi driver with data and status callbacks. */ + param.pfAppWifiCb = wifi_cb; + ret = m2m_wifi_reinit(¶m); + if (M2M_SUCCESS != ret) + { + //m2m_wifi_init call error! + while (1) {} + } + + /* Initialize socket module */ + init_tcp_socket(); + + /* Connect to router. */ + char* wifi_ssid = (char*)(g_flashCfg->wifi[EVB_CFG_BITS_IDX_WIFI(g_flashCfg->bits)].ssid); + char* wifi_psk = (char*)(g_flashCfg->wifi[EVB_CFG_BITS_IDX_WIFI(g_flashCfg->bits)].psk); + m2m_wifi_connect(wifi_ssid, strlen(wifi_ssid), WIFI_AUTH, wifi_psk, M2M_WIFI_CH_ALL); +} + + +static void deinit_wifi(void) +{ + deinit_tcp_socket(); + m2m_wifi_deinit(NULLPTR); + + /* Power down the BSP. */ + nm_bsp_deinit(); + + g_wifi_connected = 0; + g_status.evbStatus &= ~EVB_STATUS_WIFI_CONNECTED; + g_status.evbStatus &= ~EVB_STATUS_WIFI_ENABLED; +} + + +static void update_wifi_leds(rtos_task_t * task) +{ + if(g_wifi_connected == M2M_WIFI_CONNECTED) + { + // Inverted LED. On shows hot spot connectivity and blink off shows data received. + if(g_indicateWiFiRxMs > 0) + { + g_indicateWiFiRxMs-=task->periodMs; + LED_OFF(LED_WIFI_RXD_PIN); + } + else + { + LED_ON(LED_WIFI_RXD_PIN); + } + } + else + { + LED_OFF(LED_WIFI_RXD_PIN); + } + + LED_OFF(LED_WIFI_TXD_PIN); +} + + +static void step_wifi(rtos_task_t * task) +{ + int8_t ret; + + /* Handle pending events from network controller. */ + m2m_wifi_handle_events(NULL); + + if (g_wifi_connected == M2M_WIFI_CONNECTED) + { + /* Open client socket. */ + if (tcp_client_socket < 0) // Open socket + { + if ((tcp_client_socket = socket(AF_INET, SOCK_STREAM, 0)) < 0) + { + //Failed to create TCP client socket error! + return; + } + + /* Connect server */ + ret = connect(tcp_client_socket, (struct sockaddr *)&g_addr, sizeof(struct sockaddr_in)); + + if (ret < 0) + { + close(tcp_client_socket); + tcp_client_socket = -1; + } + } + else // Socket open, process data + { + int len = 0; + + // Forward uINS Ser1 port data to WiFi socket + if(g_flashCfg->cbf[EVB2_PORT_UINS1] & (1< 0) + { + send(tcp_client_socket, socketTxBuffer, len, 1000); + LED_ON(LED_WIFI_TXD_PIN); + } + } + } + + // Cause loop to sleep a while + vTaskDelay(task->periodMs); + } + else + { // We are not connected, wait and try again + deinit_tcp_socket(); + vTaskDelay(500); + } +} + + +void vTaskWiFi(void *pvParameters) +{ + (void)pvParameters; + rtos_task_t *task = &g_rtos.task[EVB_TASK_WIFI]; + + LED_OFF(LED_WIFI_TXD_PIN); + LED_OFF(LED_WIFI_RXD_PIN); + + while (1) + { + switch(g_init_wifi) + { + case 1: + g_init_wifi = 0; + deinit_wifi(); + init_wifi(); + break; + + case -1: // Disabled wifi + g_init_wifi = 0; + deinit_wifi(); + break; + } + + step_wifi(task); + + update_wifi_leds(task); // Call right after step_wifi() (task delay) + } +} diff --git a/EVB-2/IS_EVB-2/src/wifi.h b/EVB-2/IS_EVB-2/src/wifi.h new file mode 100644 index 000000000..6abdd6c03 --- /dev/null +++ b/EVB-2/IS_EVB-2/src/wifi.h @@ -0,0 +1,31 @@ +/* +MIT LICENSE + +Copyright 2014-2019 Inertial Sense, Inc. - http://inertialsense.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions : + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + + +#ifndef WIFI_H_ +#define WIFI_H_ + +#include "asf.h" + +#ifdef __cplusplus + extern "C" { +#endif + +void wifi_enable(int enable); +void wifi_reinit(void); +void vTaskWiFi(void *pvParameters); + +#ifdef __cplusplus + } +#endif + +#endif /* WIFI_H_ */ \ No newline at end of file diff --git a/EVB-2/IS_EVB-2/src/xbee.cpp b/EVB-2/IS_EVB-2/src/xbee.cpp new file mode 100644 index 000000000..e13231c39 --- /dev/null +++ b/EVB-2/IS_EVB-2/src/xbee.cpp @@ -0,0 +1,369 @@ +/* +MIT LICENSE + +Copyright 2014-2019 Inertial Sense, Inc. - http://inertialsense.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions : + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +#include +#include +#include "conf_board.h" +#include "d_serial.h" +#include "globals.h" +#include "../../../src/ISComm.h" +#include "xbee.h" + +using namespace std; + + +enum xbee_frame_id +{ + AT_COMMAND_FRAME = 0x08, // AT Command frame + AT_COMMAND_QUEUE_FRAME = 0x09, // AT Command - Queue Parameter Value frame + TX_REQUEST_FRAME = 0x10, // Transmit Request frame + TX_EXPLICIT_REQUEST_FRAME = 0x11, // Explicit Addressing Command frame + AT_REMOTE_COMMAND_FRAME = 0x17, // Remote AT Command Request frame + AT_SECURE_REMOTE_COMMAND_FRAME = 0x18, // Secure Remote AT Command Request frame + AT_COMMAND_RESPONSE_FRAME = 0x88, // AT Command Response frame + RX_INDICATOR_FRAME = 0x90, // RX Indicator frame + RX_EXPLICIT_INDICATOR_FRAME = 0x91, // Explicit Rx Indicator frame + NODE_ID_FRAME = 0x95, // Node Identification Indicator frame + REMOTE_COMMAND_RESPONSE_FRAME = 0x97, // Remote Command Response frame +}; + +/** Special Commands */ +#define XBEE_APPLY_CHANGES "AC" +#define XBEE_SOFTWARE_RESET "FR" +#define XBEE_RESTORE_DEFAULTS "RE" +#define XBEE_WRITE_VALUES "WR" +#define XBEE_EXIT_COMMAND_MODE "CN" + +/** Settable parameters. Only list the ones that are different from the stock config. */ +#define XBEE_PREAMBLE_ID "HP" +#define XBEE_NETWORK_ID "ID" +#define XBEE_BCAST_MULTITX "MT" +#define XBEE_UCAST_RETRIES "RR" +#define XBEE_TRANSMIT_OPTIONS "TO" +#define XBEE_TX_POWER_LEVEL "PL" +#define XBEE_BAUD_RATE "BD" +#define XBEE_PACKETIZATION_TO "RO" +#define XBEE_API_ENABLE "AP" +#define XBEE_SLEEP_MODE "SM" + +/** Readable parameters. Only list the ones you want to read */ +#define XBEE_RSSI = "DB" + + +/** Settable parameters. Only list the ones that are different from the stock config. */ +struct xbee_diff_commands +{ + uint8_t preamble_id = 23; + uint16_t network_id = 45; + uint8_t bcast_multi_tx = 0; + uint8_t ucast_retries = 0; + uint8_t transmit_options = 0x40; // Point to point/multipoint + uint8_t tx_power_level = 2; // 2 = 30dBm (full power) + uint8_t baud_rate = 7; // 7 = 115,200 + uint8_t packetization_to = 0; + uint8_t api_enable = 1; + uint8_t sleep_options = 1; // Use I/O pin to sleep +}; + +/** Readable parameters. Only list the ones you want to read */ +struct xbee_read_commands +{ + uint8_t rssi; +}; + + +enum +{ + XSTATE_RUN_TIME_DEFAULT = 0, + XSTATE_START_CONFIG, + XSTATE_AT_CMD_MODE_START_1, + XSTATE_AT_CMD_MODE_START_2, + XSTATE_AT_CMD_MODE_CONFIG, + XSTATE_AT_CMD_MODE_FAILURE, + XSTATE_AT_CMD_MODE_FAILURE_DELAY, + XSTATE_AT_CMD_MODE_FINISH, + XSTATE_AT_CMD_MODE_FINISH_DELAY, +}; + +// #define BUF_SIZE 256 + +xbee_diff_commands xbee_diff; +xbee_read_commands xbee_read; + + +// uint8_t xbee_buf[BUF_SIZE]; +// static uint8_t s_last_api_command[3] = {0}; +static int s_at_command_idx = 0; + +static bool s_at_ok = 0; +static int s_timer_ms = 0; +static int s_baud_rate = 115200; +static int s_xstate = XSTATE_RUN_TIME_DEFAULT; + + + +static void send_at_command(string cmd) +{ + cmd = string("AT") + cmd + "\r"; + comWrite(EVB2_PORT_XBEE, (uint8_t *)(cmd.c_str()), cmd.size(), LED_XBEE_TXD_PIN); +} + + +static bool send_next_at_command() +{ + switch(s_at_command_idx++) + { + case 0: send_at_command( XBEE_RESTORE_DEFAULTS ); break; + case 1: send_at_command( XBEE_PREAMBLE_ID + to_string(g_flashCfg->radioPID) ); break; + case 2: send_at_command( XBEE_NETWORK_ID + to_string(g_flashCfg->radioNID) ); break; + case 3: send_at_command( XBEE_TRANSMIT_OPTIONS + string("0x40") ); break; + case 4: send_at_command( XBEE_TX_POWER_LEVEL + to_string(g_flashCfg->radioPowerLevel) ); break; + case 5: send_at_command( XBEE_BCAST_MULTITX + string("0") ); break; // sets multi-transmit to off + case 6: send_at_command( XBEE_UCAST_RETRIES + string("0") ); break; // sets retry to off + case 7: send_at_command( XBEE_BAUD_RATE + to_string(xbee_diff.baud_rate) ); break; // baud rate doesn't change until XBEE_EXIT_COMMAND_MODE is sent + case 8: + if(s_baud_rate!=115200) + { // Update flash IF baud is not at 115200 so next time it starts faster + send_at_command( XBEE_WRITE_VALUES ); + break; + } + else + { // Continue to next command + s_at_command_idx++; + } + // This must be the last command sent + case 9: send_at_command( XBEE_EXIT_COMMAND_MODE ); break; + +// case 3: send_at_command( XBEE_BCAST_MULTITX + to_string(xbee_diff.bcast_multitx_val) ); break; +// case 4: send_at_command( XBEE_UCAST_RETRIES + to_string(xbee_diff.ucast_retries_val) ); break; +// case 6: send_at_command( XBEE_PACKETIZATION_TO + to_string(xbee_diff.packetization_to) ); break; +// case 7: send_at_command( XBEE_API_ENABLE + to_string(xbee_diff.api_enable) ); break; +// case 8: send_at_command( XBEE_SLEEP_MODE + to_string(xbee_diff.sleep_options) ); break; +// case 10: send_at_command( XBEE_WRITE_VALUES ); break; + default: return true; // done + } + + // Not done + return false; +} + + +// uint8_t xbee_packetize(uint8_t *raw_buf, uint8_t len_raw_buf, uint8_t *pack_buf) { +// raw_buf[0] = 0x7E; // Start delimiter +// raw_buf[1] = 0x00; // MSB +// raw_buf[2] = len_raw_buf; // LSB +// +// uint32_t checksum; +// +// pack_buf = raw_buf - 3; +// +// for(size_t i = 0 ; i < len_raw_buf ; ++i ) { +// checksum += raw_buf[i]; +// } +// +// pack_buf[len_raw_buf+3] = 0xFF - (checksum & 0xFF); // Checksum calculation +// +// return len_raw_buf+3; // Length of packetized buffer +// } + +static void xbee_receive(is_comm_instance_t *comm) +{ + if( xbee_runtime_mode() +// || g_flashCfg->cbPreset == EVB2_CB_PRESET_USB_HUB_RS232 +// || g_flashCfg->cbPreset == EVB2_CB_PRESET_USB_HUB_RS422 + ) + { // Normal communications + com_bridge_smart_forward(EVB2_PORT_XBEE, LED_XBEE_RXD_PIN); + } + else + { // XBee configuration/command mode +#define BUF_SIZE 256 //USB CDC buffer size is 320 + uint8_t buf[BUF_SIZE]; + int len; + if((len = comRead(EVB2_PORT_XBEE, buf, BUF_SIZE, LED_XBEE_RXD_PIN)) <= 0) + { // No data + return; + } + + // Look for AT "OK\r" response + while(buf[0] == 0x4F && len < 3) + { // Ensure we have at lease 3 bytes + len += comRead(EVB2_PORT_XBEE, &buf[len], BUF_SIZE-len, LED_XBEE_RXD_PIN); //Read new com data into buffer after original data and update len value + } + if(memcmp(reinterpret_cast(buf), "OK\r", 3) == 0) + { // AT command mode + s_at_ok = 1; // Make sure to reset this when you go to the next command + } + +#if 0 + if(buf[0] == 0x7E) + { // API packet + uint8_t lsb = buf[2]; + + switch (buf[3]) + { + case AT_COMMAND_RESPONSE_FRAME: + s_last_api_command[0] = buf[5]; // First AT character + s_last_api_command[1] = buf[6]; // Second AT character + s_last_api_command[2] = buf[7]; // Command status + + if(buf[5] == ('D') && buf[6] == ('B')) + { + xbee_read.rssi = buf[8]; + } + break; + + case RX_INDICATOR_FRAME: + com_bridge_forward(EVB2_PORT_XBEE, buf + 15, lsb - 12); // Forward data into com bridge + break; + } + } + else +#endif + } +} + + +void xbee_init(void) +{ + s_baud_rate = 115200; + g_status.evbStatus &= (~EVB_STATUS_XBEE_CONFIGURED | ~EVB_STATUS_XBEE_CONFIG_FAILURE); + s_xstate = XSTATE_START_CONFIG; + LED_OFF(LED_XBEE_RXD_PIN); + LED_OFF(LED_XBEE_TXD_PIN); +} + + +void xbee_step(is_comm_instance_t *comm) +{ + if( !(g_status.evbStatus & EVB_STATUS_XBEE_ENABLED) ) + { // Don't run XBee if its disabled. Enabled inside board_IO_config(). + return; + } + + switch(s_xstate) + { + default: // XSTATE_RUN_TIME_DEFAULT + LED_OFF(LED_XBEE_RXD_PIN); + LED_OFF(LED_XBEE_TXD_PIN); + break; + + case XSTATE_START_CONFIG: + serSetBaudRate(EVB2_PORT_XBEE, s_baud_rate); + LED_OFF(LED_XBEE_RXD_PIN); // green off + LED_OFF(LED_XBEE_TXD_PIN); // red off + s_timer_ms = g_comm_time_ms; + s_xstate++; + break; + + case XSTATE_AT_CMD_MODE_START_1: + if((g_comm_time_ms - s_timer_ms) < 1500) + { + LED_OFF(LED_XBEE_RXD_PIN); // green off + LED_OFF(LED_XBEE_TXD_PIN); // red off + break; + } + + comWrite(EVB2_PORT_XBEE, (uint8_t *)"+++", 3, LED_XBEE_TXD_PIN); + LED_ON(LED_XBEE_RXD_PIN); // green on + LED_ON(LED_XBEE_TXD_PIN); // red on (orange) + s_timer_ms = g_comm_time_ms; + s_xstate++; + break; + + case XSTATE_AT_CMD_MODE_START_2: + if((g_comm_time_ms - s_timer_ms) < 1200) + { + break; // Wait + } + + if(s_at_ok) + { // Received OK + s_at_command_idx = 0; + s_timer_ms = g_comm_time_ms; + s_xstate = XSTATE_AT_CMD_MODE_CONFIG; + break; + } + if(s_baud_rate == 115200) + { // Retry config at 9600 baud + s_baud_rate = 9600; + s_xstate = XSTATE_START_CONFIG; + break; + } + s_xstate = XSTATE_AT_CMD_MODE_FAILURE; + break; + + case XSTATE_AT_CMD_MODE_CONFIG: + if(s_at_ok) + { // Last command OK. Send next. + s_at_ok = 0; + s_timer_ms = g_comm_time_ms; + if(send_next_at_command()) + { + s_xstate = XSTATE_AT_CMD_MODE_FINISH; + } + } + else + { + if((g_comm_time_ms - s_timer_ms) > 1000) + { // Timeout failure + s_xstate = XSTATE_AT_CMD_MODE_FAILURE; + } + } + break; + + case XSTATE_AT_CMD_MODE_FAILURE: + // Failure to enter AT command mode + serSetBaudRate(EVB2_PORT_XBEE, 115200); + g_status.evbStatus |= EVB_STATUS_XBEE_CONFIG_FAILURE; + s_timer_ms = g_comm_time_ms; + s_xstate = XSTATE_AT_CMD_MODE_FAILURE_DELAY; + break; + + case XSTATE_AT_CMD_MODE_FAILURE_DELAY: + if((g_comm_time_ms - s_timer_ms) > 1000) + { + s_xstate = XSTATE_RUN_TIME_DEFAULT; + } + LED_OFF(LED_XBEE_RXD_PIN); // green off + LED_ON(LED_XBEE_TXD_PIN); // red on + break; + + case XSTATE_AT_CMD_MODE_FINISH: + // Completed configuration! + serSetBaudRate(EVB2_PORT_XBEE, 115200); + g_status.evbStatus |= EVB_STATUS_XBEE_CONFIGURED; + s_timer_ms = g_comm_time_ms; + s_xstate = XSTATE_AT_CMD_MODE_FINISH_DELAY; + break; + + case XSTATE_AT_CMD_MODE_FINISH_DELAY: + if((g_comm_time_ms - s_timer_ms) > 1000) + { + s_xstate = XSTATE_RUN_TIME_DEFAULT; + } + LED_ON(LED_XBEE_RXD_PIN); // green on + LED_OFF(LED_XBEE_TXD_PIN); // red off + break; + } + + xbee_receive(comm); +} + + + +int xbee_runtime_mode(void) +{ + return s_xstate==XSTATE_RUN_TIME_DEFAULT; +} + + diff --git a/EVB-2/IS_EVB-2/src/xbee.h b/EVB-2/IS_EVB-2/src/xbee.h new file mode 100644 index 000000000..8f4a9d404 --- /dev/null +++ b/EVB-2/IS_EVB-2/src/xbee.h @@ -0,0 +1,36 @@ +/* +MIT LICENSE + +Copyright 2014-2019 Inertial Sense, Inc. - http://inertialsense.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions : + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + + +#ifndef __XBEE_H__ +#define __XBEE_H__ + +#include "../../../src/ISComm.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void xbee_init(void); + +void xbee_step(is_comm_instance_t *comm); + +int xbee_runtime_mode(void); + +// static uint8_t xbee_packetize(unsigned char *raw_buf, uint8_t len_raw_buf, unsigned char *pack_buf); +// static uint8_t xbee_depacketize(unsigned char *pack_buf, unsigned char *raw_buf); + +#ifdef __cplusplus +} +#endif + +#endif /* __XBEE_H__ */ \ No newline at end of file diff --git a/EVB-2/Makefile b/EVB-2/Makefile new file mode 100644 index 000000000..6b7292492 --- /dev/null +++ b/EVB-2/Makefile @@ -0,0 +1,420 @@ +# MIT LICENSE + +# Copyright 2014-2023 Inertial Sense, Inc. - http://inertialsense.com + +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions : + +# The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +TARGET ?= EVB-2 +IS_TARGET = $(addprefix IS_,$(TARGET)) + +DEBUG ?= + +################################# +# GNU ARM Embedded Toolchain +################################# + +ifeq ($(OS),Windows_NT) # Windows (any, not just NT) + +# Windows mkdir isn't same as linux +mkdir = mkdir $(subst /,\,$(1)) > nul 2>&1 || (exit 0) +rm = rmdir /Q /S $(subst /,\,$(1)) > nul 2>&1 || (exit 0) + +COMPILER_DIR := $(subst \,/,C:/Inertial_Sense/compilers/arm-none-eabi-stm32/tools/bin) +ifeq ("$(wildcard $(COMPILER_DIR)/*)","") +COMPILER_DIR := $(subst \,/,C:/PROGRA~2/Atmel/Studio/7.0/toolchain/arm/arm-gnu-toolchain/bin) +endif +ifeq ("$(wildcard $(COMPILER_DIR)/*)","") +$(error Windows: $(wildcard $(COMPILER_DIR)/*) compiler does not exist) +endif + +CC = $(addsuffix /arm-none-eabi-gcc.exe,$(COMPILER_DIR)) +CXX = $(addsuffix /arm-none-eabi-g++.exe,$(COMPILER_DIR)) +LD = $(addsuffix /arm-none-eabi-ld.exe,$(COMPILER_DIR)) +CP = $(addsuffix /arm-none-eabi-objcopy.exe,$(COMPILER_DIR)) +OD = $(addsuffix /arm-none-eabi-objdump.exe,$(COMPILER_DIR)) +SIZE = $(addsuffix /arm-none-eabi-size.exe,$(COMPILER_DIR)) + +else # Linux + +mkdir = mkdir -p $(1) +rm = rm -f -r $(1) + +# Detect if a compiler exists. +COMPILER_DIR := /opt/arm-none-eabi-uins3/bin +ifeq ("$(wildcard $(COMPILER_DIR)/*)","") +# Use the old arm-none-eabi from before we split arm-none-eabi-uins3/arm-none-eabi-stm32 +COMPILER_DIR = /opt/arm-none-eabi/bin +endif +ifeq ("$(wildcard $(COMPILER_DIR)/*)","") +$(error Linux: $(wildcard $(COMPILER_DIR)/*) compiler does not exist) +endif + +CC=$(COMPILER_DIR)/arm-none-eabi-gcc +CXX=$(COMPILER_DIR)/arm-none-eabi-g++ +LD=$(COMPILER_DIR)/arm-none-eabi-ld +AR=$(COMPILER_DIR)/arm-none-eabi-ar +AS=$(COMPILER_DIR)/arm-none-eabi-as +CP=$(COMPILER_DIR)/arm-none-eabi-objcopy +OD=$(COMPILER_DIR)/arm-none-eabi-objdump +NM=$(COMPILER_DIR)/arm-none-eabi-nm +SIZE=$(COMPILER_DIR)/arm-none-eabi-size +A2L=$(COMPILER_DIR)/arm-none-eabi-addr2line + +endif # OS + +################################# +# Working directories +################################# +ROOT = . +SRC_DIR = $(ROOT)/IS_EVB-2/src +SDK_DIR = .. +HW_LIBS_DIR = ../hw-libs +ASF_DIR = $(HW_LIBS_DIR)/drivers/SAMx70/ASF + +################################# +# Debug/Release selection +################################# +ifeq ($(DEBUG), GDB) +BUILD_MODE = debug +DEBUG_FLAGS = -g3 +OPT_FLAGS = -O0 +DEFS += -DDEBUG +OBJECT_DIR = Debug/cpp/hdw-src +BIN_DIR = Debug +else +BUILD_MODE = release +DEBUG_FLAGS = -g3 +OPT_FLAGS = -O3 +DEFS += -DNDEBUG +OBJECT_DIR = Release/cpp/hdw-src +BIN_DIR = Release +endif + +################################# +# Source Files +################################# + +C_SRCS += \ + $(SDK_DIR)/src/com_manager.c \ + $(SDK_DIR)/src/convert_ins.cpp \ + $(SDK_DIR)/src/data_sets.c \ + $(SDK_DIR)/src/DeviceLog.cpp \ + $(SDK_DIR)/src/DeviceLogRaw.cpp \ + $(SDK_DIR)/src/DeviceLogSerial.cpp \ + $(SDK_DIR)/src/DataChunk.cpp \ + $(SDK_DIR)/src/filters.cpp \ + $(SDK_DIR)/src/ISComm.c \ + $(SDK_DIR)/src/ISDataMappings.cpp \ + $(SDK_DIR)/src/ISEarth.c \ + $(SDK_DIR)/src/ISFileManager.cpp \ + $(SDK_DIR)/src/ISLogger.cpp \ + $(SDK_DIR)/src/ISLogStats.cpp \ + $(SDK_DIR)/src/ISMatrix.c \ + $(SDK_DIR)/src/ISPose.cpp \ + $(SDK_DIR)/src/ISUtilities.cpp \ + $(SDK_DIR)/src/message_stats.cpp \ + $(SDK_DIR)/src/protocol_nmea.cpp \ + $(ASF_DIR)/sam/utils/syscalls/gcc/syscalls.c \ + $(ASF_DIR)/common/components/memory/sd_mmc/sd_mmc.c \ + $(ASF_DIR)/common/components/memory/sd_mmc/sd_mmc_mem.c \ + $(ASF_DIR)/common/components/wifi/winc3400/wifi_drv/common/source/nm_common.c \ + $(ASF_DIR)/common/components/wifi/winc3400/wifi_drv/driver/source/m2m_wifi.c \ + $(ASF_DIR)/common/components/wifi/winc3400/wifi_drv/bsp/source/nm_bsp_same70.c \ + $(ASF_DIR)/common/components/wifi/winc3400/wifi_drv/socket/source/socket.c \ + $(ASF_DIR)/common/components/wifi/winc3400/wifi_drv/driver/source/m2m_hif.c \ + $(ASF_DIR)/common/components/wifi/winc3400/wifi_drv/driver/source/nmbus.c \ + $(ASF_DIR)/common/components/wifi/winc3400/wifi_drv/driver/source/nmspi.c \ + $(ASF_DIR)/common/components/wifi/winc3400/wifi_drv/bus_wrapper/source/nm_bus_wrapper_same70.c \ + $(ASF_DIR)/common/components/wifi/winc3400/wifi_drv/driver/source/nmasic.c \ + $(ASF_DIR)/common/components/wifi/winc3400/wifi_drv/driver/source/nmdrv.c \ + $(ASF_DIR)/common/services/clock/same70/sysclk.c \ + $(ASF_DIR)/common/services/delay/sam/cycle_counter.c \ + $(ASF_DIR)/common/services/serial/usart_serial.c \ + $(ASF_DIR)/common/services/sleepmgr/sam/sleepmgr.c \ + $(ASF_DIR)/common/services/spi/sam_spi/spi_master.c \ + $(ASF_DIR)/common/services/spi/sam_usart_spi/usart_spi.c \ + $(ASF_DIR)/common/services/storage/ctrl_access/ctrl_access.c \ + $(ASF_DIR)/common/services/usb/class/cdc/device/udi_cdc.c \ + $(ASF_DIR)/common/services/usb/class/cdc/device/udi_cdc_desc.c \ + $(ASF_DIR)/common/services/usb/udc/udc.c \ + $(ASF_DIR)/common/utils/interrupt/interrupt_sam_nvic.c \ + $(ASF_DIR)/common/utils/stdio/read.c \ + $(ASF_DIR)/common/utils/stdio/write.c \ + $(ASF_DIR)/sam/drivers/afec/afec.c \ + $(ASF_DIR)/sam/drivers/efc/efc.c \ + $(ASF_DIR)/sam/drivers/hsmci/hsmci.c \ + $(ASF_DIR)/sam/drivers/mcan/mcan.c \ + $(ASF_DIR)/sam/drivers/mpu/mpu.c \ + $(ASF_DIR)/sam/drivers/pio/pio.c \ + $(ASF_DIR)/sam/drivers/pio/pio_handler.c \ + $(ASF_DIR)/sam/drivers/pmc/pmc.c \ + $(ASF_DIR)/sam/drivers/pmc/sleep.c \ + $(ASF_DIR)/sam/drivers/pwm/pwm.c \ + $(ASF_DIR)/sam/drivers/rtc/rtc.c \ + $(ASF_DIR)/sam/drivers/rtt/rtt.c \ + $(ASF_DIR)/sam/drivers/spi/spi.c \ + $(ASF_DIR)/sam/drivers/tc/tc.c \ + $(ASF_DIR)/sam/drivers/twihs/twihs.c \ + $(ASF_DIR)/sam/drivers/uart/uart.c \ + $(ASF_DIR)/sam/drivers/usart/usart.c \ + $(ASF_DIR)/sam/drivers/usbhs/usbhs_device.c \ + $(ASF_DIR)/sam/drivers/wdt/wdt.c \ + $(ASF_DIR)/sam/drivers/xdmac/xdmac.c \ + $(ASF_DIR)/sam/services/flash_efc/flash_efc.c \ + $(ASF_DIR)/sam/utils/cmsis/same70/source/templates/gcc/startup_same70.c \ + $(ASF_DIR)/sam/utils/cmsis/same70/source/templates/system_same70.c \ + $(ASF_DIR)/thirdparty/fatfs/fatfs-port-r0.09/diskio.c \ + $(ASF_DIR)/thirdparty/fatfs/fatfs-port-r0.09/sam/fattime_rtc.c \ + $(ASF_DIR)/thirdparty/fatfs/fatfs-r0.09/src/ff.c \ + $(ASF_DIR)/thirdparty/fatfs/fatfs-r0.09/src/option/ccsbcs.c \ + $(HW_LIBS_DIR)/misc/new.cpp \ + $(HW_LIBS_DIR)/drivers/SAMx70/CAN.c \ + $(HW_LIBS_DIR)/drivers/SAMx70/d_dma.c \ + $(HW_LIBS_DIR)/drivers/SAMx70/d_flash.c \ + $(HW_LIBS_DIR)/drivers/SAMx70/d_i2c.c \ + $(HW_LIBS_DIR)/drivers/SAMx70/d_serial.c \ + $(HW_LIBS_DIR)/drivers/SAMx70/d_time.c \ + $(HW_LIBS_DIR)/bootloader/bootloaderApp.c \ + $(HW_LIBS_DIR)/misc/rtos.c \ + $(HW_LIBS_DIR)/printf/printf.c \ + $(HW_LIBS_DIR)/freertos/croutine.c \ + $(HW_LIBS_DIR)/freertos/event_groups.c \ + $(HW_LIBS_DIR)/freertos/portable/MemMang/heap_4.c \ + $(HW_LIBS_DIR)/freertos/list.c \ + $(HW_LIBS_DIR)/freertos/portable/GCC/ARM_CM7/r0p1/port.c \ + $(HW_LIBS_DIR)/freertos/queue.c \ + $(HW_LIBS_DIR)/freertos/tasks.c \ + $(HW_LIBS_DIR)/freertos/timers.c \ + $(HW_LIBS_DIR)/freertos/stream_buffer.c \ + $(SRC_DIR)/communications.cpp \ + $(SRC_DIR)/evb_tasks.cpp \ + $(SRC_DIR)/globals.c \ + $(SRC_DIR)/ISLogFileFatFs.cpp \ + $(SRC_DIR)/main.cpp \ + $(SRC_DIR)/sd_card_logger.cpp \ + $(SRC_DIR)/spiTouINS.c \ + $(SRC_DIR)/user_interface.cpp \ + $(SRC_DIR)/wheel_encoder.cpp \ + $(SRC_DIR)/wifi.c \ + $(SRC_DIR)/xbee.cpp \ + $(SRC_DIR)/drivers/d_quadEnc.c \ + $(SRC_DIR)/drivers/d_adc.c \ + $(SRC_DIR)/misc/init.c + +################################# +# Include Directories +################################# + +INCLUDES += \ + $(SRC_DIR) \ + $(SRC_DIR)/config \ + $(SRC_DIR)/drivers \ + $(SRC_DIR)/misc + +INCLUDES += $(SDK_DIR)/src + +INCLUDES += \ + $(HW_LIBS_DIR) \ + $(HW_LIBS_DIR)/boards \ + $(HW_LIBS_DIR)/bootloader \ + $(HW_LIBS_DIR)/communications \ + $(HW_LIBS_DIR)/freertos \ + $(HW_LIBS_DIR)/drivers/SAMx70 \ + $(HW_LIBS_DIR)/printf \ + $(HW_LIBS_DIR)/misc + +INCLUDES += \ + $(ASF_DIR)/common/boards \ + $(ASF_DIR)/common/components/memory/sd_mmc \ + $(ASF_DIR)/common/components/wifi/winc3400/wifi_drv \ + $(ASF_DIR)/common/services/clock \ + $(ASF_DIR)/common/services/delay \ + $(ASF_DIR)/common/services/gpio \ + $(ASF_DIR)/common/services/ioport \ + $(ASF_DIR)/common/services/serial/sam_uart \ + $(ASF_DIR)/common/services/serial \ + $(ASF_DIR)/common/services/sleepmgr \ + $(ASF_DIR)/common/services/spi/sam_spi \ + $(ASF_DIR)/common/services/spi/sam_usart_spi \ + $(ASF_DIR)/common/services/spi \ + $(ASF_DIR)/common/services/storage/ctrl_access \ + $(ASF_DIR)/common/services/usb/class/cdc/device \ + $(ASF_DIR)/common/services/usb/class/cdc \ + $(ASF_DIR)/common/services/usb/udc \ + $(ASF_DIR)/common/services/usb \ + $(ASF_DIR)/common/utils/stdio/stdio_serial \ + $(ASF_DIR)/common/utils \ + $(ASF_DIR)/sam/boards \ + $(ASF_DIR)/sam/drivers/efc \ + $(ASF_DIR)/sam/drivers/hsmci \ + $(ASF_DIR)/sam/drivers/mcan \ + $(ASF_DIR)/sam/drivers/mpu \ + $(ASF_DIR)/sam/drivers/pio \ + $(ASF_DIR)/sam/drivers/pmc \ + $(ASF_DIR)/sam/drivers/pwm \ + $(ASF_DIR)/sam/drivers/rtc \ + $(ASF_DIR)/sam/drivers/rtt \ + $(ASF_DIR)/sam/drivers/spi \ + $(ASF_DIR)/sam/drivers/tc \ + $(ASF_DIR)/sam/drivers/twihs \ + $(ASF_DIR)/sam/drivers/uart \ + $(ASF_DIR)/sam/drivers/usart \ + $(ASF_DIR)/sam/drivers/usbhs \ + $(ASF_DIR)/sam/drivers/wdt \ + $(ASF_DIR)/sam/drivers/afec \ + $(ASF_DIR)/sam/drivers/xdmac \ + $(ASF_DIR)/sam/services/flash_efc \ + $(ASF_DIR)/sam/utils/cmsis/same70/include \ + $(ASF_DIR)/sam/utils/cmsis/same70/include/component \ + $(ASF_DIR)/sam/utils/cmsis/same70/source/templates \ + $(ASF_DIR)/sam/utils/fpu \ + $(ASF_DIR)/sam/utils/header_files \ + $(ASF_DIR)/sam/utils/preprocessor \ + $(ASF_DIR)/sam/utils \ + $(ASF_DIR)/thirdparty/CMSIS/Include \ + $(ASF_DIR)/thirdparty/CMSIS/Lib/GCC \ + $(ASF_DIR)/thirdparty/fatfs/fatfs-port-r0.09/sam \ + $(ASF_DIR)/thirdparty/fatfs/fatfs-r0.09/src \ + $(HW_LIBS_DIR)/freertos/include \ + $(HW_LIBS_DIR)/freertos/portable/GCC/ARM_CM7/r0p1 \ + +LDSCRIPT=$(ROOT)/IS_EVB-2/SAMx70-FLASH.ld + +################################# +# Object List +################################# +OBJECTS+=$(addsuffix .o,$(addprefix $(OBJECT_DIR)/$(TARGET)/,$(basename $(C_SRCS)))) +DEPENDENCIES+=$(patsubst %.o,%.d,$(OBJECTS)) + +################################# +# Target Output Files +################################# +TARGET_ELF=$(BIN_DIR)/$(IS_TARGET).elf +TARGET_HEX=$(BIN_DIR)/$(IS_TARGET).hex +TARGET_BIN=$(BIN_DIR)/$(IS_TARGET).bin +TARGET_LSS=$(BIN_DIR)/$(IS_TARGET).lss +TARGET_MAP=$(BIN_DIR)/$(IS_TARGET).map + +################################# +# Flags +################################# + +DEFS += \ + -D__SAME70Q20B__ \ + -DARM_MATH_CM7=true \ + -D__FREERTOS__ \ + -DUDD_ENABLE \ + -DSD_MMC_ENABLE \ + -DARM \ + -D__INERTIAL_SENSE_EVB_2__ \ + -DCONF_PERIPH \ + -DEVB_2 \ + +# CPU type flags +CPU_FLAGS = \ + -mcpu=cortex-m7 \ + -mthumb \ + -mfloat-abi=softfp \ + -mfpu=fpv5-d16 \ + +# Dependency flags +DEP_FLAGS = -MD -MP -MF $(@:%.o=%.d) -MT$(@:%.o=%.d) -MT$(@:%.o=%.o) + +# C assorted flags +FLAGS_C = -x c -c -pipe -std=gnu11 -fdata-sections -ffunction-sections \ + -fno-strict-aliasing --param max-inline-insns-single=500 +# C defines, CPU flags +FLAGS_C += $(CPU_FLAGS) $(DEFS) -Dscanf=iscanf +# C includes +FLAGS_C += $(addprefix -I,$(INCLUDES)) +# C optimization and debug flags +FLAGS_C += $(OPT_FLAGS) $(DEBUG_FLAGS) +# C warning flags +FLAGS_C += \ + -Wall -Wstrict-prototypes -Wmissing-prototypes -Wmissing-declarations \ + -Wimplicit-function-declaration -Wpointer-arith -Wchar-subscripts -Wno-comment \ + -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type \ + -Wswitch -Wtrigraphs -Wuninitialized -Wunknown-pragmas -Wundef -Wshadow \ + -Wwrite-strings -Wsign-compare -Wmissing-declarations -Wformat -Wmissing-format-attribute \ + -Wpacked -Wunreachable-code -Wcast-align -Wno-unused -Wno-unused-function \ + -Wno-misleading-indentation -Wno-int-conversion +# C dependency flags +FLAGS_C += $(DEP_FLAGS) + +# C++ defines, CPU flags +FLAGS_CXX = $(CPU_FLAGS) $(DEFS) +# C++ includes +FLAGS_CXX += $(addprefix -I,$(INCLUDES)) +# C++ optimization and debug flags +FLAGS_CXX += $(OPT_FLAGS) $(DEBUG_FLAGS) +# C++ assorted flags +FLAGS_CXX += -fno-exceptions -fno-rtti -ffunction-sections -fdata-sections \ + -fno-rtti -fno-exceptions -c -std=gnu++11 +# C++ warning flags +FLAGS_CXX += -Wno-comment -Wno-switch -Wno-unused-function -Wno-parentheses -Wno-psabi +# C++ dependency flags +FLAGS_CXX += $(DEP_FLAGS) + +FLAGS_LD = \ + -mthumb -Wl,-Map="$(TARGET_MAP)" -Wl,--start-group -lm \ + -Wl,--end-group --specs=nano.specs -Wl,--gc-sections -Wl,--entry=Reset_Handler \ + -Wl,--cref -mthumb -T$(LDSCRIPT) $(CPU_FLAGS) -L"../src/ASF/thirdparty/CMSIS/Lib/GCC" + +FLAGS_HEX = -O ihex -R .eeprom -R .fuse -R .lock -R .signature + +################################# +# Recipes +################################# +.PHONY: all clean + +all: main-build + +pre-build: + @$(call update_info) + $(info Compiler found.) + $(info Using $(CC) as C compiler) + $(info Using $(CXX) as C++ compiler) + $(info Using $(LD) as linker) + $(info Building in $(BUILD_MODE) mode) + +main-build: pre-build + @$(MAKE) --no-print-directory $(TARGET_BIN) $(TARGET_HEX) + +clean: + $(info Cleaning project) + @$(call rm,$(BIN_DIR)) + +-include $(DEPENDENCIES) + +################################# +# Build +################################# + +$(TARGET_BIN): $(TARGET_ELF) + $(info Creating $@) + @$(CP) -O binary $< $@ + +$(TARGET_HEX): $(TARGET_ELF) + $(info Creating $@) + @$(CP) $(FLAGS_HEX) $< $@ + +$(TARGET_ELF): $(OBJECTS) + $(info Linking $@ in $(BUILD_MODE) mode...) + @$(CXX) -o $@ $(OBJECTS) $(FLAGS_LD) + @$(OD) -h -S $@ > $(TARGET_LSS) + $(info Program size table:) + @$(SIZE) $@ + +$(OBJECT_DIR)/$(TARGET)/%.o: %.cpp + @$(call mkdir,$(dir $@)) + $(info $(notdir $<)) + @$(CXX) $(FLAGS_CXX) -o $@ $< + +$(OBJECT_DIR)/$(TARGET)/%.o: %.c + @$(call mkdir,$(dir $@)) + $(info $(notdir $<)) + @$(CC) $(FLAGS_C) -o $@ $< diff --git a/EVB-2/README.md b/EVB-2/README.md new file mode 100644 index 000000000..1b119b8ce --- /dev/null +++ b/EVB-2/README.md @@ -0,0 +1,146 @@ +# EVB-2 + +## Hardware + +The Inertial Sense EVB 2.x is a development board which contains the Inertial Sense µINS, µAHRS, or µIMU module. The EVB 2.x builds on the foundation established by the EVB 1.x, but adds these and other new features: + +- 915MHz Xbee radio for RTK (real-time-kinematics) +- Wi-Fi and Bluetooth Low energy (BLE) for remote data viewing and logging operation +- Onboard logging to micro SD card. +- Dual antenna ports for GPS compassing +- Companion Microchip SAME70 processor that serves as a communication bridge between the µINS, µAHRS, or µIMU and all other interfaces. + +More details on the EVB-2 can be found in the [Inertial Sense online documentation]() + +## Firmware + +The EVB-2 project source code is open source and available in the inertial-sense-sdk. It serves as a dev kit example project for the following applications: + +- RTK positioning, base or rover with 900MHz radio and WiFi radios. +- RTK compassing, moving baseline RTK for a dual GNSS heading solution. +- External uBlox [ZED-F9P multi-frequency GNSS](https://docs.inertialsense.com/user-manual/gnss/multi_frequency_gnss/) for simultaneous RTK positioning and RTK compassing. +- [uINS SPI](https://docs.inertialsense.com/user-manual/hardware/EVB2/#spi) interface. +- [uINS CAN](https://docs.inertialsense.com/user-manual/com-protocol/CAN/) interface. + +Because the EVB-2 project is open source, itself can be customized by users to meet various needs. + +### Compiling EVB-2 Firmware + +##### Atmel Studio + +###### Install + +Installer link: https://www.microchip.com/avr-support/atmel-studio-7 +(Downloads are near the bottom of the page.) +Download the installer and take all of the default options during installation. + +###### Building + +1. Open SDK\EVB-2\IS_EVB-2.atsln +1. Click Build Menu -> Build Soution (F7) + a. If using JTAG programmer the firmware will be flashed to EVB-2. + +##### **Ubuntu** + +###### **Install toolchain** + +In order to build you need to install the gcc-arm embedded toolchain. You can install it with Microchip Studio, or the following commands: + +```bash +# Download toolchain version 6.3.1 6-2017-q2 +wget https://developer.arm.com/-/media/Files/downloads/gnu-rm/6-2017q2/gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 + +# Unzip file +tar -xf gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 + +# Move it to the opt directory +sudo mv gcc-arm-none-eabi-6-2017-q2-update /opt/ + +# Add the compiler to the path +echo "export PATH=\$PATH:/opt/gcc-arm-none-eabi-6-2017-q2-update/bin/" >> ~/.bashrc + +# Delete the downloaded file +rm -rf gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 + +# Re-source your .bashrc to get the updated $PATH +source ~/.bashrc + +# Print gcc toolchain version info +arm-none-eabi-gcc --version +``` + +###### **Building** + +Run `make` within the EVB-2 directory . + +### Loading Firmware onto EVB-2 + +The EVB USB port on the EVB-2 must be used to update the EVB-2 firmware. + +##### EvalTool + +1. Enter the Settings tab +2. Open the COM ports of the units that need to be updated + 1. If the units don't open up, the baud rate may need changed +3. Click, "Update Firmware" +4. Navigate to the directory where the newly built .hex file is located +5. Select it and press "Open" +6. Wait for the firmware to fully load + +##### CLTool + +Use the -b command line flag. See the cltool [help menu](). + +##### SDK + +Use the function bootloadFile() to load firmware onto the EVB-2. See [SDK Docs](). + +### Chip Erase Using Atmel-ICE + +The EVB-2 SAM-E70 can be chip erased using the Atmel-ICE JTAG (SWD) interface and Atmel Studio. The following steps describe how to erase the contents of the SAM-E70 and then reload the bootloader and firmware. + +1. Open the **Device Programming** dialog in Atmel Studio -> Tools -> Device Programming. +2. Select Tool: **Atmel-ICE**, Device: **ATSAME70Q20B**, Interface: **SWD** and click Apply. +3. Click the **Device Signature Read** button to ensure communication works properly. +4. Go to the Memories area and click Erase Chip - **Erase now** button. This will erase all of the contents on the processor. + +![chip erase](images/jtag_chip_erase.png) + +5. Go to the GPNVM Bits area and **uncheck** the GPNVMBITS.BOOT_MODE checkbox and click the program button. This will put the processor into bootloader update mode. + +![](images/jtag_gpnvmbits_boot_mode.png) + +6. Follow the standard bootloader and firmware update process, using either the [EvalTool](https://docs.inertialsense.com/user-manual/software/evaltool/#update-firmware) or [CLTool](https://docs.inertialsense.com/user-manual/software/cltool/#update-the-firmware). The bootloader must be loaded first followed by the firmware. + +## SPI + +SPI communication has been implemented between the EVB-2 communications hub and the uINS device to demonstrate how to properly communicate with a uINS using SPI. Details of the SPI communications protocol can be found in the [Inertial Sense Online Documentation](https://docs.inertialsense.com/user-manual/com-protocol/SPI/). + +SPI communication between the uINS and the EVB-2 processor is enabled by setting the appropriate bit of DID_EVB_FLASH_CFG.[cbOptions](https://docs.inertialsense.com/user-manual/com-protocol/DID-descriptions/#did_evb_flash_cfg). + +The main implementation of the SPI protocol exists in spiTouINS.c. + +## Updating ASF drivers in project + +If additional peripherals are needed in the project, you may need to add drivers using the Atmel Studio Framework (ASF). This can be done using Atmel Studio's ASF Wizard. Currently the EVB-2 project uses ASF version 3.44.1. + +1. Open ASF Wizard and select the project if needed. + + ![](images\ASF_project.png) + +2. Verify version is showing as 3.44.1 by clicking on the version tab. If the version is not showing correctly, see note below. + + ![](images\ASF_version.png) + +3. Return to the Extensions tab. For each item that needs added, select it and press add. + +4. Once everything is modified, click the apply button. + +5. Using a Git diff tool, discard the following two changes to the EVB-2/IS_EVB-2/src/asf.h file. + + ![](images\ASF_discard.png) + +6. The project will now be ready to use the new drivers. + +Note: Sometimes the project gets inconsistent ASF versions entered into the project file. If the ASF Wizard does not show the correct version, open the EVB-2/IS_EVB-2/IS_EVB-2.cppproj file with a text editor, locate versions that are not 3.44.1 and change them to 3.44.1. Typically there will only be a few that will be incorrect. + diff --git a/EVB-2/images/ASF_discard.png b/EVB-2/images/ASF_discard.png new file mode 100644 index 000000000..555a0dc68 Binary files /dev/null and b/EVB-2/images/ASF_discard.png differ diff --git a/EVB-2/images/ASF_project.png b/EVB-2/images/ASF_project.png new file mode 100644 index 000000000..270bfa42a Binary files /dev/null and b/EVB-2/images/ASF_project.png differ diff --git a/EVB-2/images/ASF_version.png b/EVB-2/images/ASF_version.png new file mode 100644 index 000000000..a228159e5 Binary files /dev/null and b/EVB-2/images/ASF_version.png differ diff --git a/EVB-2/images/jtag_chip_erase.png b/EVB-2/images/jtag_chip_erase.png new file mode 100644 index 000000000..f0e29dd99 Binary files /dev/null and b/EVB-2/images/jtag_chip_erase.png differ diff --git a/EVB-2/images/jtag_gpnvmbits_boot_mode.png b/EVB-2/images/jtag_gpnvmbits_boot_mode.png new file mode 100644 index 000000000..645a9f0d1 Binary files /dev/null and b/EVB-2/images/jtag_gpnvmbits_boot_mode.png differ diff --git a/hw-libs/boards/EVB-2.h b/hw-libs/boards/EVB-2.h new file mode 100644 index 000000000..40b4df1f1 --- /dev/null +++ b/hw-libs/boards/EVB-2.h @@ -0,0 +1,903 @@ +#ifndef __EVB_2_H +#define __EVB_2_H + +#ifdef LUNA_VEHICLE +#include "config/conf_luna.h" +#endif + +#define USE_FREERTOS 1 +#define USE_TIMER_DRIVER 0 + +#define CONF_BOARD_ENABLE_DCACHE 0 + +/** Board oscillator settings */ +#define BOARD_FREQ_SLCK_XTAL (32768U) +#define BOARD_FREQ_SLCK_BYPASS (32768U) +#define BOARD_FREQ_MAINCK_XTAL (12000000U) +#define BOARD_FREQ_MAINCK_BYPASS (12000000U) +#define BOARD_FREQ_CPU 3000000 // CPU target frequency + +#define TIM_CLK_FREQ BOARD_FREQ_SLCK_XTAL +#define TIM_PRESC 3 // finest allowed granularity + +/** Master clock frequency */ +#define BOARD_MCK CHIP_FREQ_CPU_MAX + +/** board main clock xtal statup time */ +// #define BOARD_OSC_STARTUP_US 15625 +#define BOARD_OSC_STARTUP_US 13000 +// #define BOARD_OSC_STARTUP_US 31250 + +/*----------------------------------------------------------------------------*/ +/** + * \page same70_xplained_info "SAME70-XPLD - Board informations" + * This page lists several definition related to the board description. + * + * \section Definitions + * - \ref BOARD_NAME + */ + +/** Name of the board */ +#define BOARD_NAME "IS_EVB-2" +/** Board definition */ +// #define same70xpld +/** Family definition (already defined) */ +#define same70 +/** Core definition */ +#define cortexm7 + +/*----------------------------------------------------------------------------*/ + + + +/*! \name Pin Assignments by General Name + */ +//! @{ + +// Hardware Versions +// SAMS70N20B <=IMX-3.1 +// SAME70Q20B >=IMX3.2 +// SAME70Q20B EVB-2 + +// EVB-2 Hardware Detection Pins +#define EVB_HDW_DETECT_0_GPIO (PIO_PC0_IDX) +#define EVB_HDW_DETECT_1_GPIO (PIO_PC1_IDX) +#define EVB_HDW_DETECT_2_GPIO (PIO_PC2_IDX) + +enum eEvbHdwDetectVersion +{ + HDW_DETECT_VER_EVB_2_0_0 = 0, + HDW_DETECT_VER_EVB_2_0_1 = 1, + HDW_DETECT_VER_EVB_2_1_0 = 2, + HDW_DETECT_VER_EVB_2_1_1 = 3, + HDW_DETECT_VER_EVB_2_2_0 = 4, +}; + +// uINS Ser0 UART +#define UART_INS_SER0_RXD_PIN (PIO_PA5_IDX) +#define UART_INS_SER0_RXD_FLAGS (IOPORT_MODE_MUX_C) +#define UART_INS_SER0_TXD_PIN (PIO_PA6_IDX) +#define UART_INS_SER0_TXD_FLAGS (IOPORT_MODE_MUX_C) +// uINS Ser1 UART Functionality +#define UART_INS_SER1_RXD_PIN (PIO_PA9_IDX) +#define UART_INS_SER1_RXD_FLAGS (IOPORT_MODE_MUX_A) +#define UART_INS_SER1_TXD_PIN (PIO_PA10_IDX) +#define UART_INS_SER1_TXD_FLAGS (IOPORT_MODE_MUX_A) +// uINS Ser1 SPI Functionality +#define SPI_INS_MISO_PIN (PIO_PD20_IDX) +#define SPI_INS_MISO_FLAGS (IOPORT_MODE_MUX_B) +#define SPI_INS_MOSI_PIN (PIO_PD21_IDX) +#define SPI_INS_MOSI_FLAGS (IOPORT_MODE_MUX_B) +#define SPI_INS_SCLK_PIN (PIO_PD22_IDX) +#define SPI_INS_SCLK_FLAGS (IOPORT_MODE_MUX_B) +#define SPI_INS_CS_PIN (PIO_PD12_IDX) +#define SPI_INS_CS_FLAGS (IOPORT_MODE_MUX_C) +#define SPI_INS_EN (PIO_PC20_IDX) + +// uINS Data Ready +#define INS_DATA_RDY_PIN_IDX (PIO_PD2_IDX) +#define INS_DATA_RDY_PIN_MASK (PIO_PD2) +#define INS_DATA_RDY_PIN_ID (ID_PIOD) +#define INS_DATA_RDY_PIN_PIO (PIOD) + +// uINS Reset +#define INS_RESET_PIN_PIN (PIO_PA2_IDX) + +// RS232/RS422/RS485 +#define UART_SP330_RXD_PIN (PIO_PD28_IDX) +#define UART_SP330_RXD_FLAGS (IOPORT_MODE_MUX_A) +#define UART_SP330_TXD_PIN (PIO_PD30_IDX) +#define UART_SP330_TXD_FLAGS (IOPORT_MODE_MUX_A) +#define SP330_NSLEW_PIN (PIO_PA18_IDX) // Data rate limit to 250 kbps when low +#define SP330_NSHDN_PIN (PIO_PA19_IDX) +#define SP330_N485_RXEN_PIN (PIO_PA20_IDX) // RS845 enable receiver when low +#define SP330_NFULL_DPLX_PIN (PIO_PC18_IDX) // RS485 full duplex when low +#define SP330_485_N232_PIN (PIO_PD4_IDX) // RS232 low / RS485 high + +// SD Card Interface +#define SD_CLK_PIN (PIO_PA25_IDX) +#define SD_CLK_FLAGS (IOPORT_MODE_MUX_D) +#define SD_CMD_PIN (PIO_PA28_IDX) +#define SD_CMD_FLAGS (IOPORT_MODE_MUX_C) +#define SD_D0_PIN (PIO_PA30_IDX) +#define SD_D0_FLAGS (IOPORT_MODE_MUX_C) +#define SD_D1_PIN (PIO_PA31_IDX) +#define SD_D1_FLAGS (IOPORT_MODE_MUX_C) +#define SD_D2_PIN (PIO_PA25_IDX) +#define SD_D2_FLAGS (IOPORT_MODE_MUX_C) +#define SD_D3_PIN (PIO_PA27_IDX) +#define SD_D3_FLAGS (IOPORT_MODE_MUX_C) +#define SD_DETECT (PIO_PC16_IDX) + +// ATWINC WiFi SPI Interface +#define SPI_WIFI_MISO_PIN (PIO_PC26_IDX) +#define SPI_WIFI_MISO_FLAGS (IOPORT_MODE_MUX_C) +#define SPI_WIFI_MOSI_PIN (PIO_PC27_IDX) +#define SPI_WIFI_MOSI_FLAGS (IOPORT_MODE_MUX_C) +#define SPI_WIFI_SCLK_PIN (PIO_PC24_IDX) +#define SPI_WIFI_SCLK_FLAGS (IOPORT_MODE_MUX_C) +#define SPI_WIFI_CS_PIN (PIO_PC25_IDX) +#define SPI_WIFI_CS_FLAGS (IOPORT_MODE_MUX_C) +#define WIFI_RST_PIN (PIO_PC21_IDX) +#define WIFI_CHIPEN_PIN (PIO_PC22_IDX) +#define WIFI_IRQN_PIN (PIO_PC23_IDX) + +// ATWINC BTLE UART Interface +#define UART_BTLE_RXD_PIN (PIO_PD15_IDX) +#define UART_BTLE_RXD_FLAGS (IOPORT_MODE_MUX_B) +#define UART_BTLE_TXD_PIN (PIO_PD16_IDX) +#define UART_BTLE_TXD_FLAGS (IOPORT_MODE_MUX_B) +#define UART_BTLE_RTS_PIN (PIO_PD18_IDX) +#define UART_BTLE_RTS_FLAGS (IOPORT_MODE_MUX_B) +#define UART_BTLE_CTS_PIN (PIO_PD19_IDX) +#define UART_BTLE_CTS_FLAGS (IOPORT_MODE_MUX_B) + +// External Radio UART +#define UART_EXT_RADIO_RXD_PIN (PIO_PD25_IDX) +#define UART_EXT_RADIO_RXD_FLAGS (IOPORT_MODE_MUX_C | IOPORT_MODE_PULLUP) +#define UART_EXT_RADIO_TXD_PIN (PIO_PD26_IDX) +#define UART_EXT_RADIO_TXD_FLAGS (IOPORT_MODE_MUX_C) +#define EXT_RADIO_RST (PIO_PD7_IDX) + +// Xbee UART +#define UART_XBEE_RXD_PIN (PIO_PB0_IDX) +#define UART_XBEE_RXD_FLAGS (IOPORT_MODE_MUX_C) +#define UART_XBEE_TXD_PIN (PIO_PB1_IDX) +#define UART_XBEE_TXD_FLAGS (IOPORT_MODE_MUX_C) +#if 0 // Normal (EVB-2.0.1) +#define UART_XBEE_N_CTS_PIN (PIO_PB2_IDX) +#define UART_XBEE_N_CTS_FLAGS (IOPORT_MODE_MUX_C) +#define UART_XBEE_N_RTS_PIN (PIO_PB3_IDX) +#define UART_XBEE_N_RTS_FLAGS (IOPORT_MODE_MUX_C) +#else // temporary fix (EVB-2.0.0) +#define UART_XBEE_N_CTS_PIN (PIO_PB3_IDX) +#define UART_XBEE_N_CTS_FLAGS (IOPORT_MODE_MUX_C) +#define UART_XBEE_N_RTS_PIN (PIO_PB2_IDX) +#define UART_XBEE_N_RTS_FLAGS (IOPORT_MODE_MUX_C) +#endif +#define UART_XBEE_N_DTR_PIN (PIO_PD1_IDX) +#define UART_XBEE_N_DTR_FLAGS (IOPORT_MODE_MUX_D) +#define XBEE_SUPPLY_EN_PIN (PIO_PD17_IDX) +#define XBEE_VUSB_DISABLE_PIN (PIO_PC3_IDX) +#define XBEE_RST_PIN (PIO_PA29_IDX) +#define XBEE_SLEEP_RQ_PIN (PIO_PD1_IDX) + +// USB +#define USB_PORT_NUM EVB2_PORT_USB + +// CAN Transceiver +#define CAN_RXD_PIN (PIO_PC12_IDX) +#define CAN_RXD_FLAGS (IOPORT_MODE_MUX_C) +#define CAN_TXD_PIN (PIO_PC14_IDX) +#define CAN_TXD_FLAGS (IOPORT_MODE_MUX_C) + +// I2C Bus +#define I2C_0_SDA_PIN (PIO_PA3_IDX) +#define I2C_0_SDA_FLAGS (IOPORT_MODE_MUX_A) +#define I2C_0_SCL_PIN (PIO_PA4_IDX) +#define I2C_0_SCL_FLAGS (IOPORT_MODE_MUX_A) + +// GPS Time Pulse Input +#define GPS_TP_PIN (PIO_PC9_IDX) + + +// H8 GPIO Pins - GPIO pins are all tied to multiple SAME70 pins. Below is just one of these pins. +#define GPIO_1_PIN (PIO_PB4_IDX) // (H8-5) PB4 +#define GPIO_2_PIN (PIO_PA16_IDX) // (H8-6) PA16 + PA21 +#define GPIO_3_PIN (PIO_PA23_IDX) // (H8-7) PA23 + PA0 + PE3 +#define GPIO_4_PIN (PIO_PA24_IDX) // (H8-8) PA24 + PA1 +#define GPIO_5_PIN (PIO_PB13_IDX) // (H8-9) PB13 + PC5 + PC29 +#define GPIO_6_PIN (PIO_PC6_IDX) // (H8-10) PC6 + PD0 +#define GPIO_7_PIN (PIO_PC9_IDX) // (H8-11) PC9 +#define GPIO_8_PIN (PIO_PD27_IDX) // (H8-12) PE4 + PD27 (PE4 does not work as an output pin) +#define GPIO_9_PIN (PIO_PE0_IDX) // (H8-13) PE0 + PA15 + PC13 +#define GPIO_10_PIN (PIO_PE1_IDX) // (H8-14) PE1 + PC15 +// GPIO Inverted UART Control +#define GPIO_UART_INV_PIN (PIO_PE2_IDX) + +// GPIO UART +#define GPIO_H8_UART_RXD_PIN (PIO_PA21_IDX) +#define GPIO_H8_UART_RXD_FLAGS (IOPORT_MODE_MUX_A | IOPORT_MODE_PULLUP) +// #define GPIO_H8_UART_RXD_FLAGS (IOPORT_MODE_MUX_A) +#define GPIO_H8_UART_TXD_PIN (PIO_PB4_IDX) +#define GPIO_H8_UART_TXD_FLAGS (IOPORT_MODE_MUX_D) + + +// USB ID +#define M_USB_ID_PIN (PIO_PA17_IDX) + +#define LED_OFF(led) ioport_set_pin_level(led,IOPORT_PIN_LEVEL_HIGH) +#define LED_ON(led) ioport_set_pin_level(led,IOPORT_PIN_LEVEL_LOW) +#define LED_TOGGLE(led) ioport_toggle_pin_level(led) +// EVB - LED - Config +#define LED_CFG_RED_PIN (PIO_PD6_IDX) +#define LED_CFG_GRN_PIN (PIO_PA13_IDX) +#define LED_CFG_BLU_PIN (PIO_PD3_IDX) +#define LED_CFG_RED() { LED_ON(LED_CFG_RED_PIN); LED_OFF(LED_CFG_GRN_PIN); LED_OFF(LED_CFG_BLU_PIN); } +#define LED_CFG_GREEN() { LED_OFF(LED_CFG_RED_PIN); LED_ON(LED_CFG_GRN_PIN); LED_OFF(LED_CFG_BLU_PIN); } +#define LED_CFG_BLUE() { LED_OFF(LED_CFG_RED_PIN); LED_OFF(LED_CFG_GRN_PIN); LED_ON(LED_CFG_BLU_PIN); } +#define LED_CFG_CYAN() { LED_OFF(LED_CFG_RED_PIN); LED_ON(LED_CFG_GRN_PIN); LED_ON(LED_CFG_BLU_PIN); } +#define LED_CFG_YELLOW() { LED_ON(LED_CFG_RED_PIN); LED_ON(LED_CFG_GRN_PIN); LED_OFF(LED_CFG_BLU_PIN); } +#define LED_CFG_PURPLE() { LED_ON(LED_CFG_RED_PIN); LED_OFF(LED_CFG_GRN_PIN); LED_ON(LED_CFG_BLU_PIN); } +#define LED_CFG_WHITE() { LED_ON(LED_CFG_RED_PIN); LED_ON(LED_CFG_GRN_PIN); LED_ON(LED_CFG_BLU_PIN); } +#define LED_CFG_OFF() { LED_OFF(LED_CFG_RED_PIN); LED_OFF(LED_CFG_GRN_PIN); LED_OFF(LED_CFG_BLU_PIN); } + +#define LED_COLOR_RED() LED_CFG_RED(); +#define LED_COLOR_GREEN() LED_CFG_GREEN(); +#define LED_COLOR_BLUE() LED_CFG_BLUE(); +#define LED_COLOR_CYAN() LED_CFG_CYAN(); +#define LED_COLOR_YELLOW() LED_CFG_YELLOW(); +#define LED_COLOR_PURPLE() LED_CFG_PURPLE(); +#define LED_COLOR_WHITE() LED_CFG_WHITE(); + +// EVB - LED - Logger +#define LED_LOG_RED_PIN (PIO_PA11_IDX) +#define LED_LOG_GRN_PIN (PIO_PD23_IDX) +#define LED_LOG_BLU_PIN (PIO_PA12_IDX) +#define LED_LOG_RED() { LED_ON(LED_LOG_RED_PIN); LED_OFF(LED_LOG_GRN_PIN); LED_OFF(LED_LOG_BLU_PIN); } +#define LED_LOG_GREEN() { LED_OFF(LED_LOG_RED_PIN); LED_ON(LED_LOG_GRN_PIN); LED_OFF(LED_LOG_BLU_PIN); } +#define LED_LOG_BLUE() { LED_OFF(LED_LOG_RED_PIN); LED_OFF(LED_LOG_GRN_PIN); LED_ON(LED_LOG_BLU_PIN); } +#define LED_LOG_CYAN() { LED_OFF(LED_LOG_RED_PIN); LED_ON(LED_LOG_GRN_PIN); LED_ON(LED_LOG_BLU_PIN); } +#define LED_LOG_YELLOW() { LED_ON(LED_LOG_RED_PIN); LED_ON(LED_LOG_GRN_PIN); LED_OFF(LED_LOG_BLU_PIN); } +#define LED_LOG_PURPLE() { LED_ON(LED_LOG_RED_PIN); LED_OFF(LED_LOG_GRN_PIN); LED_ON(LED_LOG_BLU_PIN); } +#define LED_LOG_WHITE() { LED_ON(LED_LOG_RED_PIN); LED_ON(LED_LOG_GRN_PIN); LED_ON(LED_LOG_BLU_PIN); } +#define LED_LOG_OFF() { LED_OFF(LED_LOG_RED_PIN); LED_OFF(LED_LOG_GRN_PIN); LED_OFF(LED_LOG_BLU_PIN); } + +#define LEDS_ALL_ON() { LED_ON(LED_LOG_RED_PIN); LED_ON(LED_LOG_GRN_PIN); LED_ON(LED_LOG_BLU_PIN); } +#define LEDS_ALL_OFF() { LED_OFF(LED_LOG_RED_PIN); LED_OFF(LED_LOG_GRN_PIN); LED_OFF(LED_LOG_BLU_PIN); } +#define LEDS_ALL_TOGGLE() { LED_TOGGLE(LED_LOG_RED_PIN); LED_TOGGLE(LED_LOG_GRN_PIN); LED_TOGGLE(LED_LOG_BLU_PIN); } + + + +// LED - INS Communications +#define LED_INS_RXD_PIN (PIO_PC8_IDX) // green +#define LED_INS_TXD_PIN (PIO_PC28_IDX) // red +// LED - Xbee Communications +#define LED_XBEE_RXD_PIN (PIO_PC10_IDX) // green +#define LED_XBEE_TXD_PIN (PIO_PC11_IDX) // red +// LED - Wifi Communications +#define LED_WIFI_RXD_PIN (PIO_PC17_IDX) // green +#define LED_WIFI_TXD_PIN (PIO_PD10_IDX) // red + +// Buttons +#define BUTTON_CFG_PIN (g_hdw_detect==0?PIO_PC5_IDX:PIO_PC3_IDX) // EVB 2.0.0 = PC5, all others are PC3 +#define BUTTON_CFG_FLAGS (IOPORT_MODE_PULLUP | IOPORT_MODE_DEBOUNCE) +#define BUTTON_CFG_SENSE (IOPORT_SENSE_LEVEL_LOW) +#define BUTTON_LOG_PIN (g_hdw_detect==0?PIO_PC6_IDX:PIO_PC7_IDX) // EVB 2.0.0 = PC6, all others are PC7 +#define BUTTON_LOG_FLAGS (IOPORT_MODE_PULLUP | IOPORT_MODE_DEBOUNCE) +#define BUTTON_LOG_SENSE (IOPORT_SENSE_LEVEL_LOW) + +#define JTAG_TMS_SWDIO_PIN (PIO_PB6_IDX) +#define JTAG_TCK_SWCLK_PIN (PIO_PB7_IDX) +#define JTAG_TDO_SWO_PIN (PIO_PB5_IDX) +#define JTAG_TDI_PIN (PIO_PB4_IDX) + + +// ioport helper macros below acquired from same70_xplained/init.c +#ifndef ioport_set_port_peripheral_mode +#define ioport_set_port_peripheral_mode(port, masks, mode) \ + do {\ + ioport_set_port_mode(port, masks, mode);\ + ioport_disable_port(port, masks);\ + } while (0) +#endif // ioport_set_port_peripheral_mode + +#ifndef ioport_set_pin_peripheral_mode +#define ioport_set_pin_peripheral_mode(pin, mode) \ + do {\ + ioport_set_pin_mode(pin, mode);\ + ioport_disable_pin(pin);\ + } while (0) +#endif // ioport_set_pin_peripheral_mode + +// The following "ioport_enable_pin(pin);" line is necessary to allow tristate. (whj) +#ifndef ioport_set_pin_input_mode +#define ioport_set_pin_input_mode(pin, mode, sense) \ + do {\ + ioport_enable_pin(pin);\ + ioport_set_pin_dir(pin, IOPORT_DIR_INPUT);\ + ioport_set_pin_mode(pin, mode);\ + ioport_set_pin_sense_mode(pin, (ioport_sense)sense);\ + } while (0) +#endif // ioport_set_pin_input_mode + +#ifndef ioport_set_pin_output_mode +#define ioport_set_pin_output_mode(pin, level) \ + do {\ + ioport_enable_pin(pin);\ + ioport_set_pin_level(pin, level);\ + ioport_set_pin_dir(pin, IOPORT_DIR_OUTPUT);\ + } while (0) +#endif // ioport_set_pin_output_mode + +////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////// +// START OF same70_xplained.h defaults +////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////// + +// #define CONSOLE_UART (USART1) +// #define CONSOLE_UART_ID (ID_USART1) +// /** USART1 pins definitions, PA21,PB4. */ +// #define USART1_RXD_GPIO (PIO_PA21_IDX) +// #define USART1_RXD_FLAGS (IOPORT_MODE_MUX_A | IOPORT_MODE_PULLUP) +// #define USART1_TXD_GPIO (PIO_PB4_IDX) +// #define USART1_TXD_FLAGS (IOPORT_MODE_MUX_D) + +// /** USART0 pins definitions, PB0,PB1. */ +// #define USART0_RXD_GPIO (PIO_PB0_IDX +// #define USART0_RXD_FLAGS (IOPORT_MODE_MUX_C | IOPORT_MODE_PULLUP) +// #define USART0_TXD_GPIO (PIO_PB1_IDX) +// #define USART0_TXD_FLAGS (IOPORT_MODE_MUX_C) + +#define PIN_USART0_SCK_IDX (PIO_PB13_IDX) +#define PIN_USART0_SCK_FLAGS (IOPORT_MODE_MUX_C) + +/** USART0 pin CTS */ +#define PIN_USART0_CTS_IDX (PIO_PB2_IDX) +#define PIN_USART0_CTS_FLAGS (IOPORT_MODE_MUX_C) + +/** USART0 pin RTS */ +#define PIN_USART0_RTS_IDX (PIO_PB3_IDX) +#define PIN_USART0_RTS_FLAGS (IOPORT_MODE_MUX_C) + +/** HSMCI pins definition. */ +/*! Number of slot connected on HSMCI interface */ +#define SD_MMC_HSMCI_MEM_CNT 1 +#define SD_MMC_HSMCI_SLOT_0_SIZE 4 +/** HSMCI MCCDA pin definition. */ +#define PIN_HSMCI_MCCDA_GPIO (PIO_PA28_IDX) +#define PIN_HSMCI_MCCDA_FLAGS (IOPORT_MODE_MUX_C) +/** HSMCI MCCK pin definition. */ +#define PIN_HSMCI_MCCK_GPIO (PIO_PA25_IDX) +#define PIN_HSMCI_MCCK_FLAGS (IOPORT_MODE_MUX_D) +/** HSMCI MCDA0 pin definition. */ +#define PIN_HSMCI_MCDA0_GPIO (PIO_PA30_IDX) +#define PIN_HSMCI_MCDA0_FLAGS (IOPORT_MODE_MUX_C) +/** HSMCI MCDA1 pin definition. */ +#define PIN_HSMCI_MCDA1_GPIO (PIO_PA31_IDX) +#define PIN_HSMCI_MCDA1_FLAGS (IOPORT_MODE_MUX_C) +/** HSMCI MCDA2 pin definition. */ +#define PIN_HSMCI_MCDA2_GPIO (PIO_PA26_IDX) +#define PIN_HSMCI_MCDA2_FLAGS (IOPORT_MODE_MUX_C) +/** HSMCI MCDA3 pin definition. */ +#define PIN_HSMCI_MCDA3_GPIO (PIO_PA27_IDX) +#define PIN_HSMCI_MCDA3_FLAGS (IOPORT_MODE_MUX_C) + +/** SD/MMC card detect pin definition. */ +#define PIN_HSMCI_CD {PIO_PC16, PIOD, ID_PIOD, PIO_INPUT, PIO_PULLUP} +#define SD_MMC_0_CD_GPIO (PIO_PC16_IDX) +#define SD_MMC_0_CD_PIO_ID ID_PIOD +#define SD_MMC_0_CD_FLAGS (IOPORT_MODE_PULLUP) +#define SD_MMC_0_CD_DETECT_VALUE 0 + + +//! \name SW0 definitions +//@{ +// #define SW0_PIN (PIO_PA11_IDX) +// #define SW0_ACTIVE (IOPORT_PIN_LEVEL_LOW) +// #define SW0_INACTIVE (!SW0_ACTIVE) +// #define SW0_SUPC_INPUT 2 + +/** + * Wrapper macros for SW0, to ensure common naming across all Xplained + * boards. + */ +// #define PIN_SW0 {PIO_PA11, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE} +// #define PIN_SW0_MASK PIO_PA11 +// #define PIN_SW0_PIO PIOA +// #define PIN_SW0_ID ID_PIOA +// #define PIN_SW0_TYPE PIO_INPUT +// #define PIN_SW0_ATTR (PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE) +//@} + +/** + * \name LED #0 definitions + * + * Wrapper macros for LED0, to ensure common naming across all Xplained + * boards. + */ +//@{ +// #define LED_0_NAME "LED0 (yellow)" +// #define LED_0_PIN LED0_GPIO +// #define LED_0_ACTIVE LED0_ACTIVE_LEVEL +// #define LED_0_INACTIVE LED0_INACTIVE_LEVEL + +// #define PIN_LED_0 {PIO_PC8, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} +// #define PIN_LED_0_MASK PIO_PC8 +// #define PIN_LED_0_PIO PIOC +// #define PIN_LED_0_ID ID_PIOC +// #define PIN_LED_0_TYPE PIO_OUTPUT_1 +// #define PIN_LED_0_ATTR PIO_DEFAULT +//@} + +/* TC-- Timer Count */ +// #define PIN_TC0_TIOA0 (PIO_PA0_IDX) +// #define PIN_TC0_TIOA0_MUX (IOPORT_MODE_MUX_B) +// #define PIN_TC0_TIOA0_FLAGS (IOPORT_MODE_MUX_B) +// +// #define PIN_TC0_TIOA0_PIO PIOA +// #define PIN_TC0_TIOA0_MASK PIO_PA0 +// #define PIN_TC0_TIOA0_ID ID_PIOA +// #define PIN_TC0_TIOA0_TYPE PIO_PERIPH_B +// #define PIN_TC0_TIOA0_ATTR PIO_DEFAULT +// +// #define PIN_TC3_TIOA11 (PIO_PD21_IDX) +// #define PIN_TC3_TIOA11_MUX (IOPORT_MODE_MUX_C) +// #define PIN_TC3_TIOA11_FLAGS (IOPORT_MODE_MUX_C) +// +// #define PIN_TC3_TIOA11_PIO PIOD +// #define PIN_TC3_TIOA11_MASK PIO_PD21 +// #define PIN_TC3_TIOA11_ID ID_PIOD +// #define PIN_TC3_TIOA11_TYPE PIO_PERIPH_C +// #define PIN_TC3_TIOA11_ATTR PIO_DEFAULT +// +// //! Number of on-board LEDs +// #define BOARD_NUM_OF_LED 1 + +/** + * Push button #0 definition. Attributes = pull-up + debounce + interrupt on + * rising edge. + */ +// #define BUTTON_0_NAME "SW0" +// #define BUTTON_0_PIN SW0_PIN +// #define BUTTON_0_ACTIVE SW0_ACTIVE +// #define BUTTON_0_INACTIVE SW0_INACTIVE +// #define BUTTON_0_SUPC_INPUT SW0_SUPC_INPUT +// #define GPIO_PUSH_BUTTON_0 BUTTON_0_PIN +// +// #define PUSHBUTTON_1_NAME "SW0" +// #define PUSHBUTTON_1_WKUP_LINE (2) +// #define PUSHBUTTON_1_WKUP_FSTT (PMC_FSMR_FSTT2) +// #define GPIO_PUSH_BUTTON_1 (PIO_PA11_IDX) +// #define GPIO_PUSH_BUTTON_1_FLAGS (IOPORT_MODE_PULLUP | IOPORT_MODE_DEBOUNCE) +// #define GPIO_PUSH_BUTTON_1_SENSE (IOPORT_SENSE_RISING) +// +// #define PIN_PUSHBUTTON_1 {PIO_PA11, PIOA, ID_PIOA, PIO_INPUT, \ +// PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE} +// #define PIN_PUSHBUTTON_1_MASK PIO_PA11 +// #define PIN_PUSHBUTTON_1_PIO PIOA +// #define PIN_PUSHBUTTON_1_ID ID_PIOA +// #define PIN_PUSHBUTTON_1_TYPE PIO_INPUT +// #define PIN_PUSHBUTTON_1_ATTR (PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE) +// #define PIN_PUSHBUTTON_1_IRQn PIOA_IRQn +// +// /** List of all push button definitions. */ +// #define PINS_PUSHBUTTONS {PIN_PUSHBUTTON_1} + +// //! \name Extension header #1 pin definitions +// //@{ +// #define EXT1_PIN_3 PIO_PC31_IDX +// #define EXT1_PIN_4 PIO_PA19_IDX +// #define EXT1_PIN_5 PIO_PB3_IDX +// #define EXT1_PIN_6 PIO_PB2_IDX +// #define EXT1_PIN_7 PIO_PA0_IDX +// #define EXT1_PIN_8 PIO_PC30_IDX +// #define EXT1_PIN_9 PIO_PD28_IDX +// #define EXT1_PIN_10 PIO_PC17_IDX +// #define EXT1_PIN_11 PIO_PA3_IDX +// #define EXT1_PIN_12 PIO_PA4_IDX +// #define EXT1_PIN_13 PIO_PB0_IDX +// #define EXT1_PIN_14 PIO_PB1_IDX +// #define EXT1_PIN_15 PIO_PD25_IDX +// #define EXT1_PIN_16 PIO_PD21_IDX +// #define EXT1_PIN_17 PIO_PD20_IDX +// #define EXT1_PIN_18 PIO_PD22_IDX +// //@} +// +// //! \name Extension header #1 pin definitions by function +// //@{ +// #define EXT1_PIN_ADC_0 EXT1_PIN_3 +// #define EXT1_PIN_ADC_1 EXT1_PIN_4 +// #define EXT1_PIN_GPIO_0 EXT1_PIN_5 +// #define EXT1_PIN_GPIO_1 EXT1_PIN_6 +// #define EXT1_PIN_PWM_0 EXT1_PIN_7 +// #define EXT1_PIN_PWM_1 EXT1_PIN_8 +// #define EXT1_PIN_IRQ EXT1_PIN_9 +// #define EXT1_PIN_TWI_SDA EXT1_PIN_11 +// #define EXT1_PIN_TWI_SCL EXT1_PIN_12 +// #define EXT1_PIN_UART_RX EXT1_PIN_13 +// #define EXT1_PIN_UART_TX EXT1_PIN_14 +// #define EXT1_PIN_SPI_SS_1 EXT1_PIN_10 +// #define EXT1_PIN_SPI_SS_0 EXT1_PIN_15 +// #define EXT1_PIN_SPI_MOSI EXT1_PIN_16 +// #define EXT1_PIN_SPI_MISO EXT1_PIN_17 +// #define EXT1_PIN_SPI_SCK EXT1_PIN_18 +// //@} +// +// //! \name Extension header #2 pin definitions +// //@{ +// #define EXT2_PIN_3 PIO_PD30_IDX +// #define EXT2_PIN_4 PIO_PC13_IDX +// #define EXT2_PIN_5 PIO_PA6_IDX +// #define EXT2_PIN_6 PIO_PD11_IDX +// #define EXT2_PIN_7 PIO_PC19_IDX +// #define EXT2_PIN_8 PIO_PD26_IDX +// #define EXT2_PIN_9 PIO_PA2_IDX +// #define EXT2_PIN_10 PIO_PA24_IDX +// #define EXT2_PIN_11 PIO_PA3_IDX +// #define EXT2_PIN_12 PIO_PA4_IDX +// #define EXT2_PIN_13 PIO_PA21_IDX +// #define EXT2_PIN_14 PIO_PB4_IDX +// #define EXT2_PIN_15 PIO_PD27_IDX +// #define EXT2_PIN_16 PIO_PD21_IDX +// #define EXT2_PIN_17 PIO_PD20_IDX +// #define EXT2_PIN_18 PIO_PD22_IDX +// //@} +// +// //! \name Extension header #2 pin definitions by function +// //@{ +// #define EXT2_PIN_ADC_0 EXT2_PIN_3 +// #define EXT2_PIN_ADC_1 EXT2_PIN_4 +// #define EXT2_PIN_GPIO_0 EXT2_PIN_5 +// #define EXT2_PIN_GPIO_1 EXT2_PIN_6 +// #define EXT2_PIN_PWM_0 EXT2_PIN_7 +// #define EXT2_PIN_PWM_1 EXT2_PIN_8 +// #define EXT2_PIN_IRQ EXT2_PIN_9 +// #define EXT2_PIN_TWI_SDA EXT2_PIN_11 +// #define EXT2_PIN_TWI_SCL EXT2_PIN_12 +// #define EXT2_PIN_UART_RX EXT2_PIN_13 +// #define EXT2_PIN_UART_TX EXT2_PIN_14 +// #define EXT2_PIN_SPI_SS_1 EXT2_PIN_10 +// #define EXT2_PIN_SPI_SS_0 EXT2_PIN_15 +// #define EXT2_PIN_SPI_MOSI EXT2_PIN_16 +// #define EXT2_PIN_SPI_MISO EXT2_PIN_17 +// #define EXT2_PIN_SPI_SCK EXT2_PIN_18 +// //@} + +// /** PCK0 pin definition (PA6) */ +// #define PIN_PCK0 (PIO_PA6_IDX) +// #define PIN_PCK0_MUX (IOPORT_MODE_MUX_B) +// #define PIN_PCK0_FLAGS (IOPORT_MODE_MUX_B) +// #define PIN_PCK0_PORT IOPORT_PIOA +// #define PIN_PCK0_MASK PIO_PA6B_PCK0 +// #define PIN_PCK0_PIO PIOA +// #define PIN_PCK0_ID ID_PIOA +// #define PIN_PCK0_TYPE PIO_PERIPH_B +// #define PIN_PCK0_ATTR PIO_DEFAULT +// +// +// /** TWI0 pins definition */ +// #define TWIHS0_DATA_GPIO PIO_PA3_IDX +// #define TWIHS0_DATA_FLAGS (IOPORT_MODE_MUX_A) +// #define TWIHS0_CLK_GPIO PIO_PA4_IDX +// #define TWIHS0_CLK_FLAGS (IOPORT_MODE_MUX_A) +// +// /** SPI0 pins definition */ +// #define SPI0_MISO_GPIO PIO_PD20_IDX +// #define SPI0_MISO_FLAGS (IOPORT_MODE_MUX_B) +// #define SPI0_MOSI_GPIO PIO_PD21_IDX +// #define SPI0_MOSI_FLAGS (IOPORT_MODE_MUX_B) +// #define SPI0_NPCS0_GPIO PIO_PB2_IDX +// #define SPI0_NPCS0_FLAGS (IOPORT_MODE_MUX_D) +// #define SPI0_NPCS1_GPIO PIO_PD25_IDX +// #define SPI0_NPCS1_FLAGS (IOPORT_MODE_MUX_B) +// #define SPI0_NPCS2_GPIO PIO_PD12_IDX +// #define SPI0_NPCS2_FLAGS (IOPORT_MODE_MUX_C) +// #define SPI0_NPCS3_GPIO PIO_PD27_IDX +// #define SPI0_NPCS3_FLAGS (IOPORT_MODE_MUX_B) +// #define SPI0_SPCK_GPIO PIO_PD22_IDX +// #define SPI0_SPCK_FLAGS (IOPORT_MODE_MUX_B) + +// /** QSPI pins definition */ +// #define QSPI_QSCK_GPIO PIO_PA14_IDX +// #define QSPI_QSCK_FLAGS (IOPORT_MODE_MUX_A) +// #define QSPI_QCS_GPIO PIO_PA11_IDX +// #define QSPI_QCS_FLAGS (IOPORT_MODE_MUX_A) +// #define QSPI_QIO0_GPIO PIO_PA13_IDX +// #define QSPI_QIO0_FLAGS (IOPORT_MODE_MUX_A) +// #define QSPI_QIO1_GPIO PIO_PA12_IDX +// #define QSPI_QIO1_FLAGS (IOPORT_MODE_MUX_A) +// #define QSPI_QIO2_GPIO PIO_PA17_IDX +// #define QSPI_QIO2_FLAGS (IOPORT_MODE_MUX_A) +// #define QSPI_QIO3_GPIO PIO_PD31_IDX +// #define QSPI_QIO3_FLAGS (IOPORT_MODE_MUX_A) + +// /** AFEC channel for potentiometer */ +// #define AFEC_CHANNEL_POTENTIOMETER AFEC_CHANNEL_0 +// +// #define MCAN_MODULE MCAN1 +/*----------------------------------------------------------------------------*/ +/** + * \page same70_xpld_CAN "SAME70-XPLD - CAN" + * This page lists definitions related to CAN0 and CAN1. + * + * CAN + * - \ref PIN_CAN0_TRANSCEIVER_RXEN + * - \ref PIN_CAN0_TRANSCEIVER_RS + * - \ref PIN_CAN0_TXD + * - \ref PIN_CAN0_RXD + * - \ref PINS_CAN0 + * + * - \ref PIN_CAN1_TRANSCEIVER_RXEN + * - \ref PIN_CAN1_TRANSCEIVER_RS + * - \ref PIN_CAN1_TXD + * - \ref PIN_CAN1_RXD + * - \ref PINS_CAN1 + */ +// /** CAN0 transceiver PIN RS. */ +// #define PIN_CAN0_TR_RS_IDX PIO_PE0_IDX +// #define PIN_CAN0_TR_RS_FLAGS IOPORT_DIR_OUTPUT +// +// /** CAN0 transceiver PIN EN. */ +// #define PIN_CAN0_TR_EN_IDX PIO_PE1_IDX +// #define PIN_CAN0_TR_EN_FLAGS IOPORT_DIR_OUTPUT +// +// /** CAN0 PIN RX. */ +// #define PIN_CAN0_RX_IDX PIO_PB3_IDX +// #define PIN_CAN0_RX_FLAGS IOPORT_MODE_MUX_A +// +// /** CAN0 PIN TX. */ +// #define PIN_CAN0_TX_IDX PIO_PB2_IDX +// #define PIN_CAN0_TX_FLAGS IOPORT_MODE_MUX_A +// +// /** CAN1 transceiver PIN RS. */ +// #define PIN_CAN1_TR_RS_IDX PIO_PE2_IDX +// #define PIN_CAN1_TR_RS_FLAGS IOPORT_DIR_OUTPUT +// +// /** CAN1 transceiver PIN EN. */ +// #define PIN_CAN1_TR_EN_IDX PIO_PE3_IDX +// #define PIN_CAN1_TR_EN_FLAGS IOPORT_DIR_OUTPUT +// +// /** CAN1 PIN RX. */ +// #define PIN_CAN1_RX_IDX PIO_PC12_IDX +// #define PIN_CAN1_RX_FLAGS IOPORT_MODE_MUX_C +// +// /** CAN1 PIN TX. */ +// #define PIN_CAN1_TX_IDX PIO_PC14_IDX +// #define PIN_CAN1_TX_FLAGS IOPORT_MODE_MUX_C +// +// /** PWM LED0 pin definitions. */ +// #define PIN_PWM_LED0_GPIO PIO_PA23_IDX +// #define PIN_PWM_LED0_FLAGS (IOPORT_MODE_MUX_B) +// #define PIN_PWM_LED0_CHANNEL PWM_CHANNEL_0 +// +// /** PWM LED1 pin definitions. */ +// #define PIN_PWM_LED1_GPIO PIO_PA24_IDX +// #define PIN_PWM_LED1_FLAGS (IOPORT_MODE_MUX_B) +// #define PIN_PWM_LED1_CHANNEL PWM_CHANNEL_1 + +/*----------------------------------------------------------------------------*/ +// /** GMAC HW configurations */ +// #define BOARD_GMAC_PHY_ADDR 0 +// +// #define PIN_GMAC_RESET_MASK PIO_PC10 +// #define PIN_GMAC_RESET_PIO PIOC +// #define PIN_GMAC_INT_MASK PIO_PA14 +// #define PIN_GMAC_INT_PIO PIOA +// #define PIN_GMAC_PERIPH PIO_PERIPH_A +// #define PIN_GMAC_PIO PIOD +// #define PIN_GMAC_MASK (PIO_PD0A_GTXCK | PIO_PD1A_GTXEN | PIO_PD2A_GTX0 | \ +// PIO_PD3A_GTX1 | PIO_PD4A_GRXDV | PIO_PD5A_GRX0 | \ +// PIO_PD6A_GRX1 | PIO_PD7A_GRXER | PIO_PD8A_GMDC | \ +// PIO_PD9A_GMDIO) +// +// /** Board configuration of the AT24MAC EEPROM */ +// #define BOARD_AT24MAC_TWIHS TWIHS0 +// //#define BOARD_AT24MAC_ADDRESS (0xBE >> 1) +// #define BOARD_AT24MAC_TWIHS_CLK (400000UL) +// #define BOARD_AT24MAC_PAGE_SIZE 16 +// #define BOARD_AT24MAC_TWIHS_INSTANCE TWIHS0 +// #define BOARD_AT24MAC_ADDRESS (0xAE >> 1) +// #define BOARD_CLK_TWIHS_EEPROM PIO_PA4 + +// /** EBI pins configuration for LCD */ +// /** LCD reset pin */ +// #define PIN_EBI_RESET_MASK PIO_PC13 +// #define PIN_EBI_RESET_PIO PIOC +// #define PIN_EBI_RESET_TYPE PIO_OUTPUT_1 +// #define PIN_EBI_RESET_ATTRI PIO_DEFAULT +// +// /** LCD command/data select pin */ +// #define PIN_EBI_CDS_MASK PIO_PC30 +// #define PIN_EBI_CDS_PIO PIOC +// #define PIN_EBI_CDS_TYPE PIO_OUTPUT_1 +// #define PIN_EBI_CDS_ATTRI PIO_DEFAULT +// +// /** LCD data pin */ +// #define PIN_EBI_DATAL_MASK 0xFF +// #define PIN_EBI_DATAL_PIO PIOC +// #define PIN_EBI_DATAL_TYPE PIO_PERIPH_A +// #define PIN_EBI_DATAL_ATTRI PIO_PULLUP +// +// #define PIN_EBI_DATAH_0_MASK 0x3F +// #define PIN_EBI_DATAH_0_PIO PIOE +// #define PIN_EBI_DATAH_0_TYPE PIO_PERIPH_A +// #define PIN_EBI_DATAH_0_ATTRI PIO_PULLUP +// +// #define PIN_EBI_DATAH_1_MASK (PIO_PA15A_D14|PIO_PA16A_D15) +// #define PIN_EBI_DATAH_1_PIO PIOA +// #define PIN_EBI_DATAH_1_TYPE PIO_PERIPH_A +// #define PIN_EBI_DATAH_1_ATTRI PIO_PULLUP +// +// /** LCD WE pin */ +// #define PIN_EBI_NWE_MASK PIO_PC8A_NWE +// #define PIN_EBI_NWE_PIO PIOC +// #define PIN_EBI_NWE_TYPE PIO_PERIPH_A +// #define PIN_EBI_NWE_ATTRI PIO_PULLUP +// +// /** LCD RD pin */ +// #define PIN_EBI_NRD_MASK PIO_PC11A_NRD +// #define PIN_EBI_NRD_PIO PIOC +// #define PIN_EBI_NRD_TYPE PIO_PERIPH_A +// #define PIN_EBI_NRD_ATTRI PIO_PULLUP +// +// /** LCD CS pin (NCS3) */ +// #define PIN_EBI_CS_MASK PIO_PD19A_NCS3 +// #define PIN_EBI_CS_PIO PIOD +// #define PIN_EBI_CS_TYPE PIO_PERIPH_A +// #define PIN_EBI_CS_ATTRI PIO_PULLUP +// +// /** Back-light pin definition. */ +// #define PIN_EBI_BACKLIGHT_MASK PIO_PC9B_TIOB7 +// #define PIN_EBI_BACKLIGHT_PIO PIOC +// #define PIN_EBI_BACKLIGHT_TYPE PIO_PERIPH_B +// #define PIN_EBI_BACKLIGHT_ATTRI PIO_DEFAULT + +// /*! \name GPIO Connections of VBUS monitoring +// */ +// //! @{ +// #define USB_VBUS_FLAGS (PIO_INPUT | PIO_PULLUP) +// #define USB_VBUS_PIN PIO_PC9_IDX /* As IO pin input */ +// #define USB_VBUS_PIN_IRQn ( PIOC_IRQn) +// #define USB_VBUS_PIO_ID ID_PIOC +// #define USB_VBUS_PIO_MASK PIO_PC9 +// //! @} +// +// /*! \name GPIO Connections of ID detecting +// */ +// //! @{ +// #define USB_ID_FLAGS (PIO_INPUT | PIO_PULLUP) +// #define USB_ID_PIN PIO_PC16_IDX /* As IO pin input */ +// #define USB_ID_PIN_IRQn (PIOC_IRQn) +// #define USB_ID_PIO_ID ID_PIOC +// #define USB_ID_PIO_MASK PIO_PC16 +// //! @} + +// /** WM8904 Slave address */ +// #define WM8904_SLAVE_ADDRESS (0x34 >> 1) +// +// /** TWI interface for WM8904 */ +// #define WM8904_TWIHS TWIHS0 +// +// /** WM8904 pins definition */ +// #define WM8904_TK_PIO PIO_PB1_IDX +// #define WM8904_TK_FLAGS PIO_PERIPH_D +// #define WM8904_TF_PIO PIO_PB0_IDX +// #define WM8904_TF_FLAGS PIO_PERIPH_D +// #define WM8904_TD_PIO PIO_PD26_IDX +// #define WM8904_TD_FLAGS PIO_PERIPH_B +// #define WM8904_RK_PIO PIO_PA22_IDX +// #define WM8904_RK_FLAGS PIO_PERIPH_A +// #define WM8904_RF_PIO PIO_PD24_IDX +// #define WM8904_RF_FLAGS PIO_PERIPH_B +// #define WM8904_RD_PIO PIO_PA10_IDX +// #define WM8904_RD_FLAGS PIO_PERIPH_C +// #define WM8904_PCK2_PIO PIO_PA18_IDX +// #define WM8904_PCK2_FLAGS PIO_PERIPH_B + +// /** Board SDRAM size for MT48LC16M16A2 */ +// #define BOARD_SDRAM_SIZE (2 * 1024 * 1024) +// +// /** Address for transferring command bytes to the SDRAM. */ +// #define BOARD_SDRAM_ADDR 0x70000000 +// +// /** SDRAM pins definitions */ +// #define SDRAM_BA0_PIO PIO_PA20_IDX +// #define SDRAM_SDCK_PIO PIO_PD23_IDX +// #define SDRAM_SDCKE_PIO PIO_PD14_IDX +// #define SDRAM_SDCS_PIO PIO_PC15_IDX +// #define SDRAM_RAS_PIO PIO_PD16_IDX +// #define SDRAM_CAS_PIO PIO_PD17_IDX +// #define SDRAM_SDWE_PIO PIO_PD29_IDX +// #define SDRAM_NBS0_PIO PIO_PC18_IDX +// #define SDRAM_NBS1_PIO PIO_PD15_IDX +// #define SDRAM_A2_PIO PIO_PC20_IDX +// #define SDRAM_A3_PIO PIO_PC21_IDX +// #define SDRAM_A4_PIO PIO_PC22_IDX +// #define SDRAM_A5_PIO PIO_PC23_IDX +// #define SDRAM_A6_PIO PIO_PC24_IDX +// #define SDRAM_A7_PIO PIO_PC25_IDX +// #define SDRAM_A8_PIO PIO_PC26_IDX +// #define SDRAM_A9_PIO PIO_PC27_IDX +// #define SDRAM_A10_PIO PIO_PC28_IDX +// #define SDRAM_A11_PIO PIO_PC29_IDX +// #define SDRAM_SDA10_PIO PIO_PD13_IDX +// #define SDRAM_D0_PIO PIO_PC0_IDX +// #define SDRAM_D1_PIO PIO_PC1_IDX +// #define SDRAM_D2_PIO PIO_PC2_IDX +// #define SDRAM_D3_PIO PIO_PC3_IDX +// #define SDRAM_D4_PIO PIO_PC4_IDX +// #define SDRAM_D5_PIO PIO_PC5_IDX +// #define SDRAM_D6_PIO PIO_PC6_IDX +// #define SDRAM_D7_PIO PIO_PC7_IDX +// #define SDRAM_D8_PIO PIO_PE0_IDX +// #define SDRAM_D9_PIO PIO_PE1_IDX +// #define SDRAM_D10_PIO PIO_PE2_IDX +// #define SDRAM_D11_PIO PIO_PE3_IDX +// #define SDRAM_D12_PIO PIO_PE4_IDX +// #define SDRAM_D13_PIO PIO_PE5_IDX +// #define SDRAM_D14_PIO PIO_PA15_IDX +// #define SDRAM_D15_PIO PIO_PA16_IDX +// +// #define SDRAM_BA0_FLAGS PIO_PERIPH_C +// #define SDRAM_SDCK_FLAGS PIO_PERIPH_C +// #define SDRAM_SDCKE_FLAGS PIO_PERIPH_C +// #define SDRAM_SDCS_FLAGS PIO_PERIPH_A +// #define SDRAM_RAS_FLAGS PIO_PERIPH_C +// #define SDRAM_CAS_FLAGS PIO_PERIPH_C +// #define SDRAM_SDWE_FLAGS PIO_PERIPH_C +// #define SDRAM_NBS0_FLAGS PIO_PERIPH_A +// #define SDRAM_NBS1_FLAGS PIO_PERIPH_C +// #define SDRAM_A_FLAGS PIO_PERIPH_A +// #define SDRAM_SDA10_FLAGS PIO_PERIPH_C +// #define SDRAM_D_FLAGS PIO_PERIPH_A + +// /** LCD SPI configuration */ +// #define BOARD_ILI9488_SPI SPI0 +// #define BOARD_ILI9488_SPI_IRQN SPI0_IRQn +// #define BOARD_ILI9488_SPI_NPCS 3 +// +// /** LCD SPI pins definition */ +// #define LCD_SPI_MISO_PIO PIO_PD20_IDX +// #define LCD_SPI_MISO_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) +// #define LCD_SPI_MOSI_PIO PIO_PD21_IDX +// #define LCD_SPI_MOSI_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) +// #define LCD_SPI_SPCK_PIO PIO_PD22_IDX +// #define LCD_SPI_SPCK_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) +// #define LCD_SPI_NPCS_PIO PIO_PD27_IDX +// #define LCD_SPI_NPCS_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) +// +// #define LCD_SPI_RESET_PIO PIO_PA24_IDX +// #define LCD_SPI_RESET_FLAGS (PIO_OUTPUT_1 | PIO_DEFAULT) +// #define LCD_SPI_CDS_PIO PIO_PA6_IDX +// #define LCD_SPI_CDS_FLAGS (PIO_OUTPUT_1 | PIO_DEFAULT) +// #define LCD_SPI_BACKLIGHT_PIO PIO_PC19_IDX +// #define LCD_SPI_BACKLIGHT_FLAGS (PIO_OUTPUT_1 | PIO_DEFAULT) + + +// /** TWI interface for maXTouch XPRO */ +// #define MAXTOUCH_XPRO_TWIHS TWIHS0 +// +// #define MAXTOUCH_XPRO_CHG_PIO PIO_PA2_IDX +// +// /** BNO055 external interrupt pin definition */ +// #define PIN_BNO055_EXT_INIERRUPT {PIO_PD28, PIOD, ID_PIOD, PIO_INPUT, \ +// PIO_DEFAULT | PIO_IT_RISE_EDGE} +// #define PIN_BNO055_EXT_INIERRUPT_MASK PIO_PD28 +// #define PIN_BNO055_EXT_INIERRUPT_PIO PIOD +// #define PIN_BNO055_EXT_INIERRUPT_ID ID_PIOD +// #define PIN_BNO055_EXT_INIERRUPT_TYPE PIO_INPUT +// #define PIN_BNO055_EXT_INIERRUPT_ATTR (PIO_DEFAULT | PIO_IT_RISE_EDGE) +// #define PIN_BNO055_EXT_INIERRUPT_IRQn PIOD_IRQn +// +// #define BOARD_BNO055_TWIHS TWIHS0 +// #define BOARD_BNO055_ID_TWIHS ID_TWIHS0 +// +// /** TWIHS ID for simulated EEPROM application to use */ +// #define BOARD_AT30TSE_ID_TWIHS ID_TWIHS0 +// /** TWIHS Base for simulated TWI EEPROM application to use */ +// #define BOARD_AT30TSE_TWIHS TWIHS0 + +/*----------------------------------------------------------------------------*/ +#endif // __EVB_2_H diff --git a/hw-libs/boards/ISBoards.h b/hw-libs/boards/ISBoards.h new file mode 100644 index 000000000..bc64c01f1 --- /dev/null +++ b/hw-libs/boards/ISBoards.h @@ -0,0 +1,18 @@ +#ifndef _ISBOARDS_H +#define _ISBOARDS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(__INERTIAL_SENSE_EVB_2__) +#include "EVB-2.h" +#else +#include "ISBoardsInternal.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _UINS_H */ diff --git a/hw-libs/communications/CAN_comm.h b/hw-libs/communications/CAN_comm.h new file mode 100644 index 000000000..c1ee0c698 --- /dev/null +++ b/hw-libs/communications/CAN_comm.h @@ -0,0 +1,286 @@ +/* +MIT LICENSE + +Copyright 2014-2019 Inertial Sense, Inc. - http://inertialsense.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions : + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +#ifndef CAN_COMM_H_ +#define CAN_COMM_H_ +#ifdef __cplusplus +extern "C" { +#endif + + +PUSH_PACK_1 + +/*GMT information*/ +typedef struct PACKED +{ + /** Weeks since January 6th, 1980 */ + uint32_t week; //4 bytes + + /** Time of week (since Sunday morning) in milliseconds, GMT */ + float timeOfWeekMs; //4 bytes + +} is_can_time; + +/*Status Information*/ +typedef struct PACKED +{ + /** INS status flags (eInsStatusFlags). Copy of DID_SYS_PARAMS.insStatus */ + uint32_t insStatus; //4 bytes + + /** Hardware status flags (eHdwStatusFlags). Copy of DID_SYS_PARAMS.hdwStatus */ + uint32_t hdwStatus; //4 bytes + +} is_can_ins_status; + +/*Euler Angles*/ +typedef struct PACKED +{ + /** Euler angles: roll, pitch, yaw in radians with respect to NED (scaled by 10000)*/ + int16_t theta1; //2 bytes (4 decimal places precision) + int16_t theta2; //2 bytes + int16_t theta3; //2 bytes + //int16_t reserved; +} is_can_ins_euler; + +/*Quaternion*/ +typedef struct PACKED +{ + /** Quaternion body rotation with respect to NED: W, X, Y, Z (scaled by 10000)*/ + int16_t qn2b1; //2 bytes (4 decimal places precision) + int16_t qn2b2; //2 bytes + int16_t qn2b3; //2 bytes + int16_t qn2b4; //2 bytes +} is_can_ins_quatn2b; + +/*Quaternion*/ +typedef struct PACKED +{ + /** Quaternion body rotation with respect to ECEF: W, X, Y, Z (scaled by 10000)*/ + int16_t qe2b1; //2 bytes (4 decimal places precision) + int16_t qe2b2; //2 bytes + int16_t qe2b3; //2 bytes + int16_t qe2b4; //2 bytes +} is_can_ins_quate2b; + +/*velocity in body frame*/ +typedef struct PACKED +{ + /** Velocity U, V, W in meters per second (scaled by 100). Convert to NED velocity using "vectorBodyToReference( uvw, theta, vel_ned )". */ + int16_t uvw1; //2 bytes (2 decimal places precision, max absolute value 327.67) + int16_t uvw2; //2 bytes + int16_t uvw3; //2 bytes +} is_can_uvw; + +/** Velocity in ECEF */ +typedef struct PACKED +{ + /** Velocity in ECEF (earth-centered earth-fixed) (scaled by 100) frame in meters per second */ + int16_t ve1; //2 bytes (2 decimal places precision, max absolute value 327.67) + int16_t ve2; //2 bytes + int16_t ve3; //2 bytes + +} is_can_ve; + +/** WGS84 latitude (degrees) */ +typedef struct PACKED +{ + /** WGS84 latitude (degrees) */ + double lat; //8 bytes (more than 8 decimal places precision) + +} is_can_ins_lat; + +/** WGS84 longitude (degrees) */ +typedef struct PACKED +{ + /** WGS84 longitude (degrees) */ + double lon; //8 bytes (more than 8 decimal places precision) +} is_can_ins_lon; + +/** WGS84 height above ellipsoid (meters) */ +typedef struct PACKED +{ + /** WGS84 height above ellipsoid (meters) */ + float alt; //4 bytes (more than 8 decimal places precision) + /** (see eGpsStatus) GPS status: [0x000000xx] number of satellites used, [0x0000xx00] fix type, [0x00xx0000] status flags */ + uint32_t status; +} is_can_ins_alt; + +/** North offset from reference LLA */ +typedef struct PACKED +{ + /** North offset from reference latitude, longitude, and altitude to current latitude, longitude, and altitude */ + float ned1; //4 bytes + /** East offset from reference latitude, longitude, and altitude to current latitude, longitude, and altitude */ + float ned2; //4 bytes + +} is_can_north_east; + +/** Down offset from reference LLA */ +typedef struct PACKED +{ + /** Down offset from reference latitude, longitude, and altitude to current latitude, longitude, and altitude */ + float ned3; //4 bytes + /** INS status flags (eInsStatusFlags). Copy of DID_SYS_PARAMS.insStatus */ + uint32_t insStatus; //4 bytes + +} is_can_down; + +/** X Position in ECEF (earth-centered earth-fixed) frame in meters */ +typedef struct PACKED +{ + /** X Position in ECEF (earth-centered earth-fixed) frame in meters */ + double ecef1; //8 bytes + +} is_can_ecef_x; + +/** Y Position in ECEF (earth-centered earth-fixed) frame in meters */ +typedef struct PACKED +{ + /** Y Position in ECEF (earth-centered earth-fixed) frame in meters */ + double ecef2; //8 bytes + +} is_can_ecef_y; + +/** Z Position in ECEF (earth-centered earth-fixed) frame in meters */ +typedef struct PACKED +{ + /** Z Position in ECEF (earth-centered earth-fixed) frame in meters */ + double ecef3; //8 bytes + +} is_can_ecef_z; + +/** Height above Mean Sea Level */ +typedef struct PACKED +{ + /** Height above mean sea level (MSL) in meters */ + float msl; //4 bytes +} is_can_msl; + +/**Preintegrated IMU values delta theta and delta velocity (X axis), and Integral period in body/IMU frame of accelerometer 0.**/ +typedef struct PACKED +{ + int16_t theta0; //2 bytes (scaled by 1000 3 decimal places precision) + int16_t vel0; //2 bytes (scaled by 100 2 decimal places precision) + /** Integral period in seconds for delta theta and delta velocity (scaled by 1000).*/ + uint16_t dt; //2 bytes +} is_can_preint_imu_px; + +/**Preintegrated IMU values delta theta and delta velocity (Y axis), and Integral period in body/IMU frame of accelerometer 0.**/ +typedef struct PACKED +{ + int16_t theta1; //2 bytes (scaled by 1000 3 decimal places precision) + int16_t vel1; //2 bytes (scaled by 100 2 decimal places precision) + /** Integral period in seconds for delta theta and delta velocity (scaled by 1000).*/ + uint16_t dt; //2 bytes + +} is_can_preint_imu_qy; + +/**Preintegrated IMU values delta theta and delta velocity (Z axis), and Integral period in body/IMU frame of accelerometer 0.**/ +typedef struct PACKED +{ + int16_t theta2; //2 bytes (scaled by 1000 3 decimal places precision) + int16_t vel2; //2 bytes (scaled by 100 2 decimal places precision) + /** Integral period in seconds for delta theta and delta velocity (scaled by 1000).*/ + uint16_t dt; //2 bytes +} is_can_preint_imu_rz; + +typedef struct PACKED +{ + int16_t theta0; //2 bytes (scaled by 1000 3 decimal places precision) + int16_t vel0; //2 bytes (scaled by 100 2 decimal places precision) + /** IMU Status (eImuStatus) */ + uint32_t status; //4 bytes +} is_can_dual_imu_px; + +typedef struct PACKED +{ + int16_t theta1; //2 bytes (scaled by 1000 3 decimal places precision) + int16_t vel1; //2 bytes (scaled by 100 2 decimal places precision) + /** IMU Status (eImuStatus) */ + uint32_t status; //4 bytes + +} is_can_dual_imu_qy; + +typedef struct PACKED +{ + int16_t theta2; //2 bytes (scaled by 1000 3 decimal places precision) + int16_t vel2; //2 bytes (scaled by 100 2 decimal places precision) + /** IMU Status (eImuStatus) */ + uint32_t status; //4 bytes +} is_can_dual_imu_rz; + +typedef struct PACKED +{ + /** (see eGpsStatus) GPS status: [0x000000xx] number of satellites used, [0x0000xx00] fix type, [0x00xx0000] status flags */ + uint32_t status; //4 bytes + /** Average of all satellite carrier to noise ratios (signal strengths) that non-zero in dBHz */ + uint32_t cnoMean; //4 byte +} is_can_gps_pos_status; + +typedef struct PACKED +{ + /** Ambiguity resolution ratio factor for validation */ + uint8_t arRatio; //1 byte + /** Age of differential (seconds) */ + uint8_t differentialAge; //1 byte + /** Distance to Base (m) */ + float distanceToBase; //4 bytes + /** Angle from north to vectorToBase in local tangent plane. (rad) */ + int16_t headingToBase; //2 bytes (scaled by 1000 3 decimal places precision) +} is_can_gps_rtk_rel; + +typedef struct PACKED +{ + /** Euler roll, roll rates from each IMU(DID_IMU)**/ + int16_t insRoll; //2 bytes (scaled by 10000 4 decimal places precision) + int16_t pImu1; //2 bytes (scaled by 1000 3 decimal places precision) + int16_t pImu2; //2 bytes (scaled by 1000 3 decimal places precision) + +} is_can_roll_rollRate; + +typedef union PACKED +{ + is_can_time time; + is_can_ins_status insstatus; + is_can_ins_euler euler; + is_can_ins_quatn2b quatn2b; + is_can_ins_quate2b quate2b; + is_can_uvw uvw; + is_can_ve ve; + is_can_ins_lat lat; + is_can_ins_lon lon; + is_can_ins_alt alt; + is_can_north_east ne; + is_can_down down; + is_can_ecef_x ecefx; + is_can_ecef_y ecefy; + is_can_ecef_z ecefz; + is_can_msl msl; + is_can_preint_imu_px pimupx; + is_can_preint_imu_qy pimuqy; + is_can_preint_imu_rz pimurz; + is_can_dual_imu_px dimupx; + is_can_dual_imu_qy dimuqy; + is_can_dual_imu_rz dimurz; + is_can_gps_pos_status gpspos; + is_can_gps_rtk_rel rtkrel; + is_can_roll_rollRate rollrollrate; +} is_can_payload; + + +POP_PACK + +#ifdef __cplusplus +} +#endif + +#endif // CAN_COMM_H_ diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/memory/sd_mmc/sd_mmc.c b/hw-libs/drivers/SAMx70/ASF/common/components/memory/sd_mmc/sd_mmc.c new file mode 100644 index 000000000..c524f644f --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/memory/sd_mmc/sd_mmc.c @@ -0,0 +1,2128 @@ +/** + * \file + * + * \brief Common SD/MMC stack + * + * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include +#include "conf_board.h" +#include "ISBoards.h" +#include "conf_sd_mmc.h" +#include "sd_mmc_protocol.h" +#include "sd_mmc.h" +#include "delay.h" +#include "ioport.h" + +#ifdef FREERTOS_USED +#include "FreeRTOS.h" +#include "task.h" +#include "portmacro.h" +#include "projdefs.h" +#endif + +/** + * \ingroup sd_mmc_stack + * \defgroup sd_mmc_stack_internal Implementation of SD/MMC/SDIO Stack + * @{ + */ + +// Enable debug information for SD/MMC module +#ifdef SD_MMC_DEBUG +# include +# define sd_mmc_debug(...) printf(__VA_ARGS__) +#else +# define sd_mmc_debug(...) +#endif + +#ifndef SD_MMC_SPI_MEM_CNT +# define SD_MMC_SPI_MEM_CNT 0 +#endif +#ifndef SD_MMC_MCI_MEM_CNT +# define SD_MMC_MCI_MEM_CNT 0 +#endif +#ifndef SD_MMC_HSMCI_MEM_CNT +# define SD_MMC_HSMCI_MEM_CNT 0 +#endif + +// Macros to switch SD MMC stack to the correct driver (MCI or SPI) +#ifdef SD_MMC_SPI_MODE +# if (SD_MMC_SPI_MEM_CNT != 0) +# include "sd_mmc_spi.h" +# define driver sd_mmc_spi +# define SD_MMC_MEM_CNT SD_MMC_SPI_MEM_CNT +# define sd_mmc_is_spi() true +# else +# error No SPI interface is defined for SD MMC stack. \ + SD_MMC_SPI_MEM_CNT must be added in board.h file. +# endif +#else +# if (SD_MMC_HSMCI_MEM_CNT != 0) +# include "hsmci.h" +# define driver hsmci +# define SD_MMC_MEM_CNT SD_MMC_HSMCI_MEM_CNT +# define sd_mmc_is_spi() false +# elif (SD_MMC_MCI_MEM_CNT != 0) +# include "mci.h" +# define driver mci +# define SD_MMC_MEM_CNT SD_MMC_MCI_MEM_CNT +# define sd_mmc_is_spi() false +# else +# error No MCI or HSMCI interfaces are defined for SD MMC stack. \ + SD_MMC_MCI_MEM_CNT or SD_MMC_HSMCI_MEM_CNT must be added in board.h file. +# endif +#endif + + +#define driver_init ATPASTE2(driver, _init) +#define driver_select_device ATPASTE2(driver, _select_device) +#define driver_deselect_device ATPASTE2(driver, _deselect_device) +#define driver_get_bus_width ATPASTE2(driver, _get_bus_width) +#define driver_is_high_speed_capable ATPASTE2(driver, _is_high_speed_capable) +#define driver_send_clock ATPASTE2(driver, _send_clock) +#define driver_send_cmd ATPASTE2(driver, _send_cmd) +#define driver_get_response ATPASTE2(driver, _get_response) +#define driver_get_response_128 ATPASTE2(driver, _get_response_128) +#define driver_adtc_start ATPASTE2(driver, _adtc_start) +#define driver_adtc_stop ATPASTE2(driver, _send_cmd) +#define driver_read_word ATPASTE2(driver, _read_word) +#define driver_write_word ATPASTE2(driver, _write_word) +#define driver_start_read_blocks ATPASTE2(driver, _start_read_blocks) +#define driver_wait_end_of_read_blocks ATPASTE2(driver, _wait_end_of_read_blocks) +#define driver_start_write_blocks ATPASTE2(driver, _start_write_blocks) +#define driver_wait_end_of_write_blocks ATPASTE2(driver, _wait_end_of_write_blocks) + + +#if (!defined SD_MMC_0_CD_GPIO) || (!defined SD_MMC_0_CD_DETECT_VALUE) +# warning No pin for card detection has been defined in board.h. \ + The define SD_MMC_0_CD_GPIO, SD_MMC_0_CD_DETECT_VALUE must be added in board.h file. +#endif + +#ifdef SDIO_SUPPORT_ENABLE +# define IS_SDIO() (sd_mmc_card->type & CARD_TYPE_SDIO) +#else +# define IS_SDIO() false +#endif + +#define sd_mmc_is_mci() (!sd_mmc_is_spi()) + +//! This SD MMC stack supports only the high voltage +#define SD_MMC_VOLTAGE_SUPPORT \ + (OCR_VDD_27_28 | OCR_VDD_28_29 | \ + OCR_VDD_29_30 | OCR_VDD_30_31 | \ + OCR_VDD_31_32 | OCR_VDD_32_33) + +//! SD/MMC card states +enum card_state { + SD_MMC_CARD_STATE_READY = 0, //!< Ready to use + SD_MMC_CARD_STATE_DEBOUNCE = 1, //!< Debounce on going + SD_MMC_CARD_STATE_INIT = 2, //!< Initialization on going + SD_MMC_CARD_STATE_UNUSABLE = 3, //!< Unusable card + SD_MMC_CARD_STATE_NO_CARD = 4, //!< No SD/MMC card inserted +}; + +//! SD/MMC card information structure +struct sd_mmc_card { + uint32_t clock; //!< Card access clock + uint32_t capacity; //!< Card capacity in KBytes +#if (defined SD_MMC_0_CD_GPIO) + uint32_t cd_gpio; //!< Card detect GPIO +# if (defined SD_MMC_0_WP_GPIO) + uint32_t wp_gpio; //!< Card write protection GPIO +# endif +#endif + uint16_t rca; //!< Relative card address + enum card_state state; //!< Card state + card_type_t type; //!< Card type + card_version_t version; //!< Card version + uint8_t bus_width; //!< Number of DATA lin on bus (MCI only) + uint8_t csd[CSD_REG_BSIZE];//!< CSD register + uint8_t high_speed; //!< High speed card (1) +}; + +//! SD/MMC card list +//! Note: Initialize card detect pin fields if present +static struct sd_mmc_card sd_mmc_cards[SD_MMC_MEM_CNT] +#if (defined SD_MMC_0_CD_GPIO) && (defined SD_MMC_0_WP_GPIO) + = { +# define SD_MMC_CD_WP(slot, unused) \ + {.cd_gpio = SD_MMC_##slot##_CD_GPIO, \ + .wp_gpio = SD_MMC_##slot##_WP_GPIO}, + MREPEAT(SD_MMC_MEM_CNT, SD_MMC_CD_WP, ~) +# undef SD_MMC_CD_WP +} +#elif (defined SD_MMC_0_CD_GPIO) + = { +# define SD_MMC_CD(slot, unused) \ + {.cd_gpio = SD_MMC_##slot##_CD_GPIO}, + MREPEAT(SD_MMC_MEM_CNT, SD_MMC_CD, ~) +# undef SD_MMC_CD +} +#endif +; + +//! Index of current slot configurated +static uint8_t sd_mmc_slot_sel; +//! Pointer on current slot configurated +static struct sd_mmc_card *sd_mmc_card; +//! Number of block to read or write on the current transfer +static uint16_t sd_mmc_nb_block_to_tranfer = 0; +//! Number of block remaining to read or write on the current transfer +static uint16_t sd_mmc_nb_block_remaining = 0; + +//! SD/MMC transfer rate unit codes (10K) list +const uint32_t sd_mmc_trans_units[7] = { + 10, 100, 1000, 10000, 0, 0, 0 +}; +//! SD transfer multiplier factor codes (1/10) list +const uint32_t sd_trans_multipliers[16] = { + 0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80 +}; +//! MMC transfer multiplier factor codes (1/10) list +const uint32_t mmc_trans_multipliers[16] = { + 0, 10, 12, 13, 15, 20, 26, 30, 35, 40, 45, 52, 55, 60, 70, 80 +}; + +//! \name MMC, SD and SDIO commands process +//! @{ +static bool mmc_spi_op_cond(void); +static bool mmc_mci_op_cond(void); +static bool sd_spi_op_cond(uint8_t v2); +static bool sd_mci_op_cond(uint8_t v2); +static bool sdio_op_cond(void); +static bool sdio_get_max_speed(void); +static bool sdio_cmd52_set_bus_width(void); +static bool sdio_cmd52_set_high_speed(void); +static bool sd_cm6_set_high_speed(void); +static bool mmc_cmd6_set_bus_width(uint8_t bus_width); +static bool mmc_cmd6_set_high_speed(void); +static bool sd_cmd8(uint8_t * v2); +static bool mmc_cmd8(uint8_t *b_authorize_high_speed); +static bool sd_mmc_cmd9_spi(void); +static bool sd_mmc_cmd9_mci(void); +static void mmc_decode_csd(void); +static void sd_decode_csd(void); +static bool sd_mmc_cmd13(void); +#ifdef SDIO_SUPPORT_ENABLE +static bool sdio_cmd52(uint8_t rw_flag, uint8_t func_nb, + uint32_t reg_addr, uint8_t rd_after_wr, uint8_t *io_data); +static bool sdio_cmd53(uint8_t rw_flag, uint8_t func_nb, uint32_t reg_addr, + uint8_t inc_addr, uint32_t size, bool access_block); +#endif // SDIO_SUPPORT_ENABLE +static bool sd_acmd6(void); +static bool sd_acmd51(void); +//! @} + +//! \name Internal function to process the initialization and install +//! @{ +static sd_mmc_err_t sd_mmc_select_slot(uint8_t slot); +static void sd_mmc_configure_slot(void); +static void sd_mmc_deselect_slot(void); +static bool sd_mmc_spi_card_init(void); +static bool sd_mmc_mci_card_init(void); +static bool sd_mmc_spi_install_mmc(void); +static bool sd_mmc_mci_install_mmc(void); +//! @} + + +//! \name Internal functions to manage a large timeout after a card insertion +//! @{ +#define SD_MMC_DEBOUNCE_TIMEOUT 1000 // Unit ms + +#if XMEGA +# define SD_MMC_START_TIMEOUT() delay_ms(SD_MMC_DEBOUNCE_TIMEOUT) +# define SD_MMC_IS_TIMEOUT() true +# define SD_MMC_STOP_TIMEOUT() +#endif + +#if UC3 +static t_cpu_time timer; +# define SD_MMC_START_TIMEOUT() \ + cpu_set_timeout(cpu_ms_2_cy(SD_MMC_DEBOUNCE_TIMEOUT, sysclk_get_cpu_hz()), &timer) +# define SD_MMC_IS_TIMEOUT() \ + cpu_is_timeout(&timer) +# define SD_MMC_STOP_TIMEOUT() +#endif + +#if SAM +static bool sd_mmc_sam_systick_used; +# ifdef FREERTOS_USED + static xTimeOutType xTimeOut; +#endif + +static inline void SD_MMC_START_TIMEOUT(void) +{ + if (!SysTick->CTRL) { + sd_mmc_sam_systick_used = true; + SysTick->LOAD = (sysclk_get_cpu_hz() / (8 * 1000)) + * SD_MMC_DEBOUNCE_TIMEOUT; + SysTick->CTRL = SysTick_CTRL_ENABLE_Msk; + } else { + sd_mmc_sam_systick_used = false; +#ifdef FREERTOS_USED + // Note: the define INCLUDE_vTaskDelay must be set to one + // in FreeRTOSConfig.h file. + vTaskSetTimeOutState(&xTimeOut); +#else + delay_ms(SD_MMC_DEBOUNCE_TIMEOUT); +#endif + } +} + +static inline bool SD_MMC_IS_TIMEOUT(void) +{ + if (!sd_mmc_sam_systick_used) { +#ifdef FREERTOS_USED + portTickType xTicksToWait = + SD_MMC_DEBOUNCE_TIMEOUT / portTICK_RATE_MS; + return (xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdTRUE); +#else + return true; +#endif + } + if (SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) { + SysTick->CTRL = 0; + return true; + } + return false; +} + +static inline void SD_MMC_STOP_TIMEOUT(void) +{ + if (sd_mmc_sam_systick_used) { + SysTick->CTRL = 0; + } +} +#endif +//! @} + +/** + * \brief Sends operation condition command and read OCR (SPI only) + * - CMD1 sends operation condition command + * - CMD58 reads OCR + * + * \return true if success, otherwise false + */ +static bool mmc_spi_op_cond(void) +{ + uint32_t retry, resp; + + /* + * Timeout 1s = 400KHz / ((6+1)*8) cylces = 7150 retry + * 6 = cmd byte size + * 1 = response byte size + */ + retry = 7150; + do { + if (!driver_send_cmd(MMC_SPI_CMD1_SEND_OP_COND, 0)) { + sd_mmc_debug("%s: CMD1 SPI Fail - Busy retry %d\n\r", + __func__, (int)(7150 - retry)); + return false; + } + // Check busy flag + resp = driver_get_response(); + if (!(resp & R1_SPI_IDLE)) { + break; + } + if (retry-- == 0) { + sd_mmc_debug("%s: CMD1 Timeout on busy\n\r", __func__); + return false; + } + } while (1); + + // Read OCR for SPI mode + if (!driver_send_cmd(SDMMC_SPI_CMD58_READ_OCR, 0)) { + sd_mmc_debug("%s: CMD58 Fail\n\r", __func__); + return false; + } + // Check OCR value + if ((driver_get_response() & OCR_ACCESS_MODE_MASK) + == OCR_ACCESS_MODE_SECTOR) { + sd_mmc_card->type |= CARD_TYPE_HC; + } + return true; +} + +/** + * \brief Sends operation condition command and read OCR (MCI only) + * - CMD1 sends operation condition command + * - CMD1 reads OCR + * + * \return true if success, otherwise false + */ +static bool mmc_mci_op_cond(void) +{ + uint32_t retry, resp; + + /* + * Timeout 1s = 400KHz / ((6+6)*8) cylces = 4200 retry + * 6 = cmd byte size + * 6 = response byte size + */ + retry = 4200; + do { + if (!driver_send_cmd(MMC_MCI_CMD1_SEND_OP_COND, + SD_MMC_VOLTAGE_SUPPORT | OCR_ACCESS_MODE_SECTOR)) { + sd_mmc_debug("%s: CMD1 MCI Fail - Busy retry %d\n\r", + __func__, (int)(4200 - retry)); + return false; + } + // Check busy flag + resp = driver_get_response(); + if (resp & OCR_POWER_UP_BUSY) { + // Check OCR value + if ((resp & OCR_ACCESS_MODE_MASK) + == OCR_ACCESS_MODE_SECTOR) { + sd_mmc_card->type |= CARD_TYPE_HC; + } + break; + } + if (retry-- == 0) { + sd_mmc_debug("%s: CMD1 Timeout on busy\n\r", __func__); + return false; + } + } while (1); + return true; +} + +/** + * \brief Ask to all cards to send their operations conditions (SPI only). + * - ACMD41 sends operation condition command. + * - CMD58 reads OCR + * + * \param v2 Shall be 1 if it is a SD card V2 + * + * \return true if success, otherwise false + */ +static bool sd_spi_op_cond(uint8_t v2) +{ + uint32_t arg, retry, resp; + + /* + * Timeout 1s = 400KHz / ((6+1)*8) cylces = 7150 retry + * 6 = cmd byte size + * 1 = response byte size + */ + retry = 7150; + do { + // CMD55 - Indicate to the card that the next command is an + // application specific command rather than a standard command. + if (!driver_send_cmd(SDMMC_CMD55_APP_CMD, 0)) { + sd_mmc_debug("%s: CMD55 Fail\n\r", __func__); + return false; + } + + // (ACMD41) Sends host OCR register + arg = 0; + if (v2) { + arg |= SD_ACMD41_HCS; + } + // Check response + if (!driver_send_cmd(SD_SPI_ACMD41_SD_SEND_OP_COND, arg)) { + sd_mmc_debug("%s: ACMD41 Fail\n\r", __func__); + return false; + } + resp = driver_get_response(); + if (!(resp & R1_SPI_IDLE)) { + // Card is ready + break; + } + if (retry-- == 0) { + sd_mmc_debug("%s: ACMD41 Timeout on busy, resp32 0x%08x \n\r", + __func__, resp); + return false; + } + } while (1); + + // Read OCR for SPI mode + if (!driver_send_cmd(SDMMC_SPI_CMD58_READ_OCR, 0)) { + sd_mmc_debug("%s: CMD58 Fail\n\r", __func__); + return false; + } + if ((driver_get_response() & OCR_CCS) != 0) { + sd_mmc_card->type |= CARD_TYPE_HC; + } + return true; +} + +/** + * \brief Ask to all cards to send their operations conditions (MCI only). + * - ACMD41 sends operation condition command. + * - ACMD41 reads OCR + * + * \param v2 Shall be 1 if it is a SD card V2 + * + * \return true if success, otherwise false + */ +static bool sd_mci_op_cond(uint8_t v2) +{ + uint32_t arg, retry, resp; + + /* + * Timeout 1s = 400KHz / ((6+6+6+6)*8) cylces = 2100 retry + * 6 = cmd byte size + * 6 = response byte size + * 6 = cmd byte size + * 6 = response byte size + */ + retry = 2100; + do { + // CMD55 - Indicate to the card that the next command is an + // application specific command rather than a standard command. + if (!driver_send_cmd(SDMMC_CMD55_APP_CMD, 0)) { + sd_mmc_debug("%s: CMD55 Fail\n\r", __func__); + return false; + } + + // (ACMD41) Sends host OCR register + arg = SD_MMC_VOLTAGE_SUPPORT; + if (v2) { + arg |= SD_ACMD41_HCS; + } + // Check response + if (!driver_send_cmd(SD_MCI_ACMD41_SD_SEND_OP_COND, arg)) { + sd_mmc_debug("%s: ACMD41 Fail\n\r", __func__); + return false; + } + resp = driver_get_response(); + if (resp & OCR_POWER_UP_BUSY) { + // Card is ready + if ((resp & OCR_CCS) != 0) { + sd_mmc_card->type |= CARD_TYPE_HC; + } + break; + } + if (retry-- == 0) { + sd_mmc_debug("%s: ACMD41 Timeout on busy, resp32 0x%08x \n\r", + __func__, resp); + return false; + } + } while (1); + return true; +} + +#ifdef SDIO_SUPPORT_ENABLE +/** + * \brief Try to get the SDIO card's operating condition + * - CMD5 to read OCR NF field + * - CMD5 to wait OCR power up busy + * - CMD5 to read OCR MP field + * sd_mmc_card->type is updated + * + * \return true if success, otherwise false + */ +static bool sdio_op_cond(void) +{ + uint32_t resp; + + // CMD5 - SDIO send operation condition (OCR) command. + if (!driver_send_cmd(SDIO_CMD5_SEND_OP_COND, 0)) { + sd_mmc_debug("%s: CMD5 Fail\n\r", __func__); + return true; // No error but card type not updated + } + resp = driver_get_response(); + if ((resp & OCR_SDIO_NF) == 0) { + return true; // No error but card type not updated + } + + /* + * Wait card ready + * Timeout 1s = 400KHz / ((6+4)*8) cylces = 5000 retry + * 6 = cmd byte size + * 4(SPI) 6(MCI) = response byte size + */ + uint32_t cmd5_retry = 5000; + while (1) { + // CMD5 - SDIO send operation condition (OCR) command. + if (!driver_send_cmd(SDIO_CMD5_SEND_OP_COND, + resp & SD_MMC_VOLTAGE_SUPPORT)) { + sd_mmc_debug("%s: CMD5 Fail\n\r", __func__); + return false; + } + resp = driver_get_response(); + if ((resp & OCR_POWER_UP_BUSY) == OCR_POWER_UP_BUSY) { + break; + } + if (cmd5_retry-- == 0) { + sd_mmc_debug("%s: CMD5 Timeout on busy\n\r", __func__); + return false; + } + } + // Update card type at the end of busy + if ((resp & OCR_SDIO_MP) > 0) { + sd_mmc_card->type = CARD_TYPE_SD_COMBO; + } else { + sd_mmc_card->type = CARD_TYPE_SDIO; + } + return true; // No error and card type updated with SDIO type +} + +/** + * \brief Get SDIO max transfer speed in Hz. + * - CMD53 reads CIS area address in CCCR area. + * - Nx CMD53 search Fun0 tuple in CIS area + * - CMD53 reads TPLFE_MAX_TRAN_SPEED in Fun0 tuple + * - Compute maximum speed of SDIO + * and update sd_mmc_card->clock + * + * \return true if success, otherwise false + */ +static bool sdio_get_max_speed(void) +{ + uint32_t addr_new, addr_old; + uint8_t buf[6]; + uint32_t unit; + uint32_t mul; + uint8_t tplfe_max_tran_speed, i; + uint8_t addr_cis[4]; + + /* Read CIS area address in CCCR area */ + addr_old = SDIO_CCCR_CIS_PTR; + for(i = 0; i < 4; i++) { + sdio_cmd52(SDIO_CMD52_READ_FLAG, SDIO_CIA, addr_old, 0, &addr_cis[i]); + addr_old++; + } + addr_old = addr_cis[0] + (addr_cis[1] << 8) + \ + (addr_cis[2] << 16) + (addr_cis[3] << 24); + addr_new = addr_old; + + while (1) { + /* Read a sample of CIA area */ + for(i=0; i<3; i++) { + sdio_cmd52(SDIO_CMD52_READ_FLAG, SDIO_CIA, addr_new, 0, &buf[i]); + addr_new++; + } + if (buf[0] == SDIO_CISTPL_END) { + return false; /* Tuple error */ + } + if (buf[0] == SDIO_CISTPL_FUNCE && buf[2] == 0x00) { + break; /* Fun0 tuple found */ + } + if (buf[1] == 0) { + return false; /* Tuple error */ + } + /* Next address */ + addr_new += buf[1]-1; + if (addr_new > (addr_old + 256)) { + return false; /* Outoff CIS area */ + } + } + + /* Read all Fun0 tuple fields: fn0_blk_siz & max_tran_speed */ + addr_new -= 3; + for(i = 0; i < 6; i++) { + sdio_cmd52(SDIO_CMD52_READ_FLAG, SDIO_CIA, addr_new, 0, &buf[i]); + addr_new++; + } + + tplfe_max_tran_speed = buf[5]; + if (tplfe_max_tran_speed > 0x32) { + /* Error on SDIO register, the high speed is not activated + * and the clock can not be more than 25MHz. + * This error is present on specific SDIO card + * (H&D wireless card - HDG104 WiFi SIP). + */ + tplfe_max_tran_speed = 0x32; /* 25Mhz */ + } + + /* Decode transfer speed in Hz.*/ + unit = sd_mmc_trans_units[tplfe_max_tran_speed & 0x7]; + mul = sd_trans_multipliers[(tplfe_max_tran_speed >> 3) & 0xF]; + sd_mmc_card->clock = unit * mul * 1000; + /** + * Note: A combo card shall be a Full-Speed SDIO card + * which supports upto 25MHz. + * A SDIO card alone can be: + * - a Low-Speed SDIO card which supports 400Khz minimum + * - a Full-Speed SDIO card which supports upto 25MHz + */ + return true; +} + +/** + * \brief CMD52 for SDIO - Switches the bus width mode to 4 + * + * \note sd_mmc_card->bus_width is updated. + * + * \return true if success, otherwise false + */ +static bool sdio_cmd52_set_bus_width(void) +{ + /** + * A SD memory card always supports bus 4bit + * A SD COMBO card always supports bus 4bit + * A SDIO Full-Speed alone always supports 4bit + * A SDIO Low-Speed alone can supports 4bit (Optional) + */ + uint8_t u8_value; + + // Check 4bit support in 4BLS of "Card Capability" register + if (!sdio_cmd52(SDIO_CMD52_READ_FLAG, SDIO_CIA, SDIO_CCCR_CAP, + 0, &u8_value)) { + return false; + } + if ((u8_value & SDIO_CAP_4BLS) != SDIO_CAP_4BLS) { + // No supported, it is not a protocol error + return true; + } + // HS mode possible, then enable + u8_value = SDIO_BUSWIDTH_4B; + if (!sdio_cmd52(SDIO_CMD52_WRITE_FLAG, SDIO_CIA, SDIO_CCCR_BUS_CTRL, + 1, &u8_value)) { + return false; + } + sd_mmc_card->bus_width = 4; + sd_mmc_debug("%d-bit bus width enabled.\n\r", (int)sd_mmc_card->bus_width); + return true; +} + +/** + * \brief CMD52 for SDIO - Enable the high speed mode + * + * \note sd_mmc_card->high_speed is updated. + * \note sd_mmc_card->clock is updated. + * + * \return true if success, otherwise false + */ +static bool sdio_cmd52_set_high_speed(void) +{ + uint8_t u8_value; + + // Check CIA.HS + if (!sdio_cmd52(SDIO_CMD52_READ_FLAG, SDIO_CIA, SDIO_CCCR_HS, 0, &u8_value)) { + return false; + } + if ((u8_value & SDIO_SHS) != SDIO_SHS) { + // No supported, it is not a protocol error + return true; + } + // HS mode possible, then enable + u8_value = SDIO_EHS; + if (!sdio_cmd52(SDIO_CMD52_WRITE_FLAG, SDIO_CIA, SDIO_CCCR_HS, + 1, &u8_value)) { + return false; + } + sd_mmc_card->high_speed = 1; + sd_mmc_card->clock *= 2; + return true; +} + +#else +static bool sdio_op_cond(void) +{ + return true; // No error but card type not updated +} +static bool sdio_get_max_speed(void) +{ + return false; +} +static bool sdio_cmd52_set_bus_width(void) +{ + return false; +} +static bool sdio_cmd52_set_high_speed(void) +{ + return false; +} +#endif // SDIO_SUPPORT_ENABLE + +/** + * \brief CMD6 for SD - Switch card in high speed mode + * + * \note CMD6 for SD is valid under the "trans" state. + * \note sd_mmc_card->high_speed is updated. + * \note sd_mmc_card->clock is updated. + * + * \return true if success, otherwise false + */ +static bool sd_cm6_set_high_speed(void) +{ + uint8_t switch_status[SD_SW_STATUS_BSIZE] = {0}; + + if (!driver_adtc_start(SD_CMD6_SWITCH_FUNC, + SD_CMD6_MODE_SWITCH + | SD_CMD6_GRP6_NO_INFLUENCE + | SD_CMD6_GRP5_NO_INFLUENCE + | SD_CMD6_GRP4_NO_INFLUENCE + | SD_CMD6_GRP3_NO_INFLUENCE + | SD_CMD6_GRP2_DEFAULT + | SD_CMD6_GRP1_HIGH_SPEED, + SD_SW_STATUS_BSIZE, 1, true)) { + return false; + } + if (!driver_start_read_blocks(switch_status, 1)) { + return false; + } + if (!driver_wait_end_of_read_blocks()) { + return false; + } + + if (driver_get_response() & CARD_STATUS_SWITCH_ERROR) { + sd_mmc_debug("%s: CMD6 CARD_STATUS_SWITCH_ERROR\n\r", __func__); + return false; + } + if (SD_SW_STATUS_FUN_GRP1_RC(switch_status) + == SD_SW_STATUS_FUN_GRP_RC_ERROR) { + // No supported, it is not a protocol error + return true; + } + if (SD_SW_STATUS_FUN_GRP1_BUSY(switch_status)) { + sd_mmc_debug("%s: CMD6 SD_SW_STATUS_FUN_GRP1_BUSY\n\r", __func__); + return false; + } + // CMD6 function switching period is within 8 clocks + // after the end bit of status data. + driver_send_clock(); + sd_mmc_card->high_speed = 1; + sd_mmc_card->clock *= 2; + return true; +} + +/** + * \brief CMD6 for MMC - Switches the bus width mode + * + * \note CMD6 is valid under the "trans" state. + * \note sd_mmc_card->bus_width is updated. + * + * \param bus_width Bus width to set + * + * \return true if success, otherwise false + */ +static bool mmc_cmd6_set_bus_width(uint8_t bus_width) +{ + uint32_t arg; + + switch (bus_width) { + case 8: + arg = MMC_CMD6_ACCESS_SET_BITS + | MMC_CMD6_INDEX_BUS_WIDTH + | MMC_CMD6_VALUE_BUS_WIDTH_8BIT; + break; + case 4: + arg = MMC_CMD6_ACCESS_SET_BITS + | MMC_CMD6_INDEX_BUS_WIDTH + | MMC_CMD6_VALUE_BUS_WIDTH_4BIT; + break; + default: + arg = MMC_CMD6_ACCESS_SET_BITS + | MMC_CMD6_INDEX_BUS_WIDTH + | MMC_CMD6_VALUE_BUS_WIDTH_1BIT; + break; + } + if (!driver_send_cmd(MMC_CMD6_SWITCH, arg)) { + return false; + } + if (driver_get_response() & CARD_STATUS_SWITCH_ERROR) { + // No supported, it is not a protocol error + sd_mmc_debug("%s: CMD6 CARD_STATUS_SWITCH_ERROR\n\r", __func__); + return false; + } + sd_mmc_card->bus_width = bus_width; + sd_mmc_debug("%d-bit bus width enabled.\n\r", (int)sd_mmc_card->bus_width); + return true; +} + +/** + * \brief CMD6 for MMC - Switches in high speed mode + * + * \note CMD6 is valid under the "trans" state. + * \note sd_mmc_card->high_speed is updated. + * \note sd_mmc_card->clock is updated. + * + * \return true if success, otherwise false + */ +static bool mmc_cmd6_set_high_speed(void) +{ + if (!driver_send_cmd(MMC_CMD6_SWITCH, + MMC_CMD6_ACCESS_WRITE_BYTE + | MMC_CMD6_INDEX_HS_TIMING + | MMC_CMD6_VALUE_HS_TIMING_ENABLE)) { + return false; + } + if (driver_get_response() & CARD_STATUS_SWITCH_ERROR) { + // No supported, it is not a protocol error + sd_mmc_debug("%s: CMD6 CARD_STATUS_SWITCH_ERROR\n\r", __func__); + return false; + } + sd_mmc_card->high_speed = 1; + sd_mmc_card->clock = 52000000lu; + return true; +} + +/** + * \brief CMD8 for SD card - Send Interface Condition Command. + * + * \note + * Send SD Memory Card interface condition, which includes host supply + * voltage information and asks the card whether card supports voltage. + * Should be performed at initialization time to detect the card type. + * + * \param v2 Pointer to v2 flag to update + * + * \return true if success, otherwise false + * with a update of \ref sd_mmc_err. + */ +static bool sd_cmd8(uint8_t * v2) +{ + uint32_t resp; + + *v2 = 0; + // Test for SD version 2 + if (!driver_send_cmd(SD_CMD8_SEND_IF_COND, + SD_CMD8_PATTERN | SD_CMD8_HIGH_VOLTAGE)) { + return true; // It is not a V2 + } + // Check R7 response + resp = driver_get_response(); + if (resp == 0xFFFFFFFF) { + // No compliance R7 value + return true; // It is not a V2 + } + if ((resp & (SD_CMD8_MASK_PATTERN | SD_CMD8_MASK_VOLTAGE)) + != (SD_CMD8_PATTERN | SD_CMD8_HIGH_VOLTAGE)) { + sd_mmc_debug("%s: CMD8 resp32 0x%08x UNUSABLE CARD\n\r", + __func__, resp); + return false; + } + sd_mmc_debug("SD card V2\n\r"); + *v2 = 1; + return true; +} + +/** + * \brief CMD8 - The card sends its EXT_CSD register as a block of data. + * + * \param b_authorize_high_speed Pointer to update with the high speed + * support information + * + * \return true if success, otherwise false + */ +static bool mmc_cmd8(uint8_t *b_authorize_high_speed) +{ + uint16_t i; + uint32_t ext_csd; + uint32_t sec_count; + + if (!driver_adtc_start(MMC_CMD8_SEND_EXT_CSD, 0, + EXT_CSD_BSIZE, 1, false)) { + return false; + } + //** Read and decode Extended Extended CSD + // Note: The read access is done in byte to avoid a buffer + // of EXT_CSD_BSIZE Byte in stack. + + // Read card type + for (i = 0; i < (EXT_CSD_CARD_TYPE_INDEX + 4) / 4; i++) { + if (!driver_read_word(&ext_csd)) { + return false; + } + } + *b_authorize_high_speed = (ext_csd >> ((EXT_CSD_CARD_TYPE_INDEX % 4) * 8)) + & MMC_CTYPE_52MHZ; + + if (MMC_CSD_C_SIZE(sd_mmc_card->csd) == 0xFFF) { + // For high capacity SD/MMC card, + // memory capacity = SEC_COUNT * 512 byte + for (; i <(EXT_CSD_SEC_COUNT_INDEX + 4) / 4; i++) { + if (!driver_read_word(&sec_count)) { + return false; + } + } + sd_mmc_card->capacity = sec_count / 2; + } + for (; i < EXT_CSD_BSIZE / 4; i++) { + if (!driver_read_word(&sec_count)) { + return false; + } + } + return true; +} + +/** + * \brief CMD9: Addressed card sends its card-specific + * data (CSD) on the CMD line spi. + * + * \return true if success, otherwise false + */ +static bool sd_mmc_cmd9_spi(void) +{ + if (!driver_adtc_start(SDMMC_SPI_CMD9_SEND_CSD, (uint32_t)sd_mmc_card->rca << 16, + CSD_REG_BSIZE, 1, true)) { + return false; + } + if (!driver_start_read_blocks(sd_mmc_card->csd, 1)) { + return false; + } + return driver_wait_end_of_read_blocks(); +} + +/** + * \brief CMD9: Addressed card sends its card-specific + * data (CSD) on the CMD line mci. + * + * \return true if success, otherwise false + */ +static bool sd_mmc_cmd9_mci(void) +{ + if (!driver_send_cmd(SDMMC_MCI_CMD9_SEND_CSD, (uint32_t)sd_mmc_card->rca << 16)) { + return false; + } + driver_get_response_128(sd_mmc_card->csd); + return true; +} + +/** + * \brief Decodes MMC CSD register + */ +static void mmc_decode_csd(void) +{ + uint32_t unit; + uint32_t mul; + uint32_t tran_speed; + + // Get MMC System Specification version supported by the card + switch (MMC_CSD_SPEC_VERS(sd_mmc_card->csd)) { + default: + case 0: + sd_mmc_card->version = CARD_VER_MMC_1_2; + break; + + case 1: + sd_mmc_card->version = CARD_VER_MMC_1_4; + break; + + case 2: + sd_mmc_card->version = CARD_VER_MMC_2_2; + break; + + case 3: + sd_mmc_card->version = CARD_VER_MMC_3; + break; + + case 4: + sd_mmc_card->version = CARD_VER_MMC_4; + break; + } + + // Get MMC memory max transfer speed in Hz. + tran_speed = CSD_TRAN_SPEED(sd_mmc_card->csd); + unit = sd_mmc_trans_units[tran_speed & 0x7]; + mul = mmc_trans_multipliers[(tran_speed >> 3) & 0xF]; + sd_mmc_card->clock = unit * mul * 1000; + + /* + * Get card capacity. + * ---------------------------------------------------- + * For normal SD/MMC card: + * memory capacity = BLOCKNR * BLOCK_LEN + * Where + * BLOCKNR = (C_SIZE+1) * MULT + * MULT = 2 ^ (C_SIZE_MULT+2) (C_SIZE_MULT < 8) + * BLOCK_LEN = 2 ^ READ_BL_LEN (READ_BL_LEN < 12) + * ---------------------------------------------------- + * For high capacity SD/MMC card: + * memory capacity = SEC_COUNT * 512 byte + */ + if (MMC_CSD_C_SIZE(sd_mmc_card->csd) != 0xFFF) { + uint32_t blocknr = ((MMC_CSD_C_SIZE(sd_mmc_card->csd) + 1) * + (1 << (MMC_CSD_C_SIZE_MULT(sd_mmc_card->csd) + 2))); + sd_mmc_card->capacity = blocknr * + (1 << MMC_CSD_READ_BL_LEN(sd_mmc_card->csd)) / 1024; + } +} + +/** + * \brief Decodes SD CSD register + */ +static void sd_decode_csd(void) +{ + uint32_t unit; + uint32_t mul; + uint32_t tran_speed; + + // Get SD memory maximum transfer speed in Hz. + tran_speed = CSD_TRAN_SPEED(sd_mmc_card->csd); + unit = sd_mmc_trans_units[tran_speed & 0x7]; + mul = sd_trans_multipliers[(tran_speed >> 3) & 0xF]; + sd_mmc_card->clock = unit * mul * 1000; + + /* + * Get card capacity. + * ---------------------------------------------------- + * For normal SD/MMC card: + * memory capacity = BLOCKNR * BLOCK_LEN + * Where + * BLOCKNR = (C_SIZE+1) * MULT + * MULT = 2 ^ (C_SIZE_MULT+2) (C_SIZE_MULT < 8) + * BLOCK_LEN = 2 ^ READ_BL_LEN (READ_BL_LEN < 12) + * ---------------------------------------------------- + * For high capacity SD card: + * memory capacity = (C_SIZE+1) * 512K byte + */ + if (CSD_STRUCTURE_VERSION(sd_mmc_card->csd) >= SD_CSD_VER_2_0) { + sd_mmc_card->capacity = + (SD_CSD_2_0_C_SIZE(sd_mmc_card->csd) + 1) + * 512; + } else { + uint32_t blocknr = ((SD_CSD_1_0_C_SIZE(sd_mmc_card->csd) + 1) * + (1 << (SD_CSD_1_0_C_SIZE_MULT(sd_mmc_card->csd) + 2))); + sd_mmc_card->capacity = blocknr * + (1 << SD_CSD_1_0_READ_BL_LEN(sd_mmc_card->csd)) + / 1024; + } +} + +/** + * \brief CMD13 - Addressed card sends its status register. + * This function waits the clear of the busy flag + * + * \return true if success, otherwise false + */ +static bool sd_mmc_cmd13(void) +{ + uint32_t nec_timeout; + + /* Wait for data ready status. + * Nec timing: 0 to unlimited + * However a timeout is used. + * 200 000 * 8 cycles + */ + nec_timeout = 200000; + do { + if (sd_mmc_is_spi()) { + if (!driver_send_cmd(SDMMC_SPI_CMD13_SEND_STATUS, 0)) { + return false; + } + // Check busy flag + if (!(driver_get_response() & 0xFF)) { + break; + } + } else { + if (!driver_send_cmd(SDMMC_MCI_CMD13_SEND_STATUS, + (uint32_t)sd_mmc_card->rca << 16)) { + return false; + } + // Check busy flag + if (driver_get_response() & CARD_STATUS_READY_FOR_DATA) { + break; + } + } + if (nec_timeout-- == 0) { + sd_mmc_debug("%s: CMD13 Busy timeout\n\r", __func__); + return false; + } + } while (1); + + return true; +} + +#ifdef SDIO_SUPPORT_ENABLE +/** + * \brief CMD52 - SDIO IO_RW_DIRECT command + * + * \param rw_flag Direction, 1:write, 0:read. + * \param func_nb Number of the function. + * \param rd_after_wr Read after Write flag. + * \param reg_addr register address. + * \param io_data Pointer to input argument and response buffer. + * + * \return true if success, otherwise false + */ +#if defined(__GNUC__) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wmaybe-uninitialized" +#endif + +static bool sdio_cmd52(uint8_t rw_flag, uint8_t func_nb, + uint32_t reg_addr, uint8_t rd_after_wr, uint8_t *io_data) +{ + Assert(io_data != NULL); + if (!driver_send_cmd(SDIO_CMD52_IO_RW_DIRECT, + ((uint32_t)*io_data << SDIO_CMD52_WR_DATA) + | ((uint32_t)rw_flag << SDIO_CMD52_RW_FLAG) + | ((uint32_t)func_nb << SDIO_CMD52_FUNCTION_NUM) + | ((uint32_t)rd_after_wr << SDIO_CMD52_RAW_FLAG) + | ((uint32_t)reg_addr << SDIO_CMD52_REG_ADRR))) { + return false; + } + *io_data = driver_get_response() & 0xFF; + return true; +} + +#if defined(__GNUC__) +#pragma GCC diagnostic pop +#endif + +/** + * \brief CMD53 - SDIO IO_RW_EXTENDED command + * This implementation support only the SDIO multi-byte transfer mode which is + * similar to the single block transfer on memory. + * Note: The SDIO block transfer mode is optional for SDIO card. + * + * \param rw_flag Direction, 1:write, 0:read. + * \param func_nb Number of the function. + * \param reg_addr Register address. + * \param inc_addr 1:Incrementing address, 0: fixed. + * \param size Transfer data size. + * \param access_block true, if the block access (DMA) is used + * + * \return true if success, otherwise false + */ +static bool sdio_cmd53(uint8_t rw_flag, uint8_t func_nb, uint32_t reg_addr, + uint8_t inc_addr, uint32_t size, bool access_block) +{ + Assert(size != 0); + Assert(size <= 512); + + return driver_adtc_start((rw_flag == SDIO_CMD53_READ_FLAG)? + SDIO_CMD53_IO_R_BYTE_EXTENDED : + SDIO_CMD53_IO_W_BYTE_EXTENDED, + ((size % 512) << SDIO_CMD53_COUNT) + | ((uint32_t)reg_addr << SDIO_CMD53_REG_ADDR) + | ((uint32_t)inc_addr << SDIO_CMD53_OP_CODE) + | ((uint32_t)0 << SDIO_CMD53_BLOCK_MODE) + | ((uint32_t)func_nb << SDIO_CMD53_FUNCTION_NUM) + | ((uint32_t)rw_flag << SDIO_CMD53_RW_FLAG), + size, 1, access_block); +} +#endif // SDIO_SUPPORT_ENABLE + +/** + * \brief ACMD6 - Define the data bus width to 4 bits bus + * + * \return true if success, otherwise false + */ +static bool sd_acmd6(void) +{ + // CMD55 - Indicate to the card that the next command is an + // application specific command rather than a standard command. + if (!driver_send_cmd(SDMMC_CMD55_APP_CMD, (uint32_t)sd_mmc_card->rca << 16)) { + return false; + } + // 10b = 4 bits bus + if (!driver_send_cmd(SD_ACMD6_SET_BUS_WIDTH, 0x2)) { + return false; + } + sd_mmc_card->bus_width = 4; + sd_mmc_debug("%d-bit bus width enabled.\n\r", (int)sd_mmc_card->bus_width); + return true; +} + +/** + * \brief ACMD51 - Read the SD Configuration Register. + * + * \note + * SD Card Configuration Register (SCR) provides information on the SD Memory + * Card's special features that were configured into the given card. The size + * of SCR register is 64 bits. + * + * + * \return true if success, otherwise false + */ +static bool sd_acmd51(void) +{ + uint8_t scr[SD_SCR_REG_BSIZE]; + + // CMD55 - Indicate to the card that the next command is an + // application specific command rather than a standard command. + if (!driver_send_cmd(SDMMC_CMD55_APP_CMD, (uint32_t)sd_mmc_card->rca << 16)) { + return false; + } + if (!driver_adtc_start(SD_ACMD51_SEND_SCR, 0, + SD_SCR_REG_BSIZE, 1, true)) { + return false; + } + if (!driver_start_read_blocks(scr, 1)) { + return false; + } + if (!driver_wait_end_of_read_blocks()) { + return false; + } + + // Get SD Memory Card - Spec. Version + switch (SD_SCR_SD_SPEC(scr)) { + case SD_SCR_SD_SPEC_1_0_01: + sd_mmc_card->version = CARD_VER_SD_1_0; + break; + + case SD_SCR_SD_SPEC_1_10: + sd_mmc_card->version = CARD_VER_SD_1_10; + break; + + case SD_SCR_SD_SPEC_2_00: + if (SD_SCR_SD_SPEC3(scr) == SD_SCR_SD_SPEC_3_00) { + sd_mmc_card->version = CARD_VER_SD_3_0; + } else { + sd_mmc_card->version = CARD_VER_SD_2_0; + } + break; + + default: + sd_mmc_card->version = CARD_VER_SD_1_0; + break; + } + return true; +} + +/** + * \brief Select a card slot and initialize the associated driver + * + * \param slot Card slot number + * + * \retval SD_MMC_ERR_SLOT Wrong slot number + * \retval SD_MMC_ERR_NO_CARD No card present on slot + * \retval SD_MMC_ERR_UNUSABLE Unusable card + * \retval SD_MMC_INIT_ONGOING Card initialization requested + * \retval SD_MMC_OK Card present + */ +static sd_mmc_err_t sd_mmc_select_slot(uint8_t slot) +{ + if (slot >= SD_MMC_MEM_CNT) { + return SD_MMC_ERR_SLOT; + } + Assert(sd_mmc_nb_block_remaining == 0); + +#if (defined SD_MMC_0_CD_GPIO) + //! Card Detect pins + if (ioport_get_pin_level(sd_mmc_cards[slot].cd_gpio) + != SD_MMC_0_CD_DETECT_VALUE) { + if (sd_mmc_cards[slot].state == SD_MMC_CARD_STATE_DEBOUNCE) { + SD_MMC_STOP_TIMEOUT(); + } + sd_mmc_cards[slot].state = SD_MMC_CARD_STATE_NO_CARD; + return SD_MMC_ERR_NO_CARD; + } + if (sd_mmc_cards[slot].state == SD_MMC_CARD_STATE_NO_CARD) { + // A card plug on going, but this is not initialized + sd_mmc_cards[slot].state = SD_MMC_CARD_STATE_DEBOUNCE; + // Debounce + Power On Setup + SD_MMC_START_TIMEOUT(); + return SD_MMC_ERR_NO_CARD; + } + if (sd_mmc_cards[slot].state == SD_MMC_CARD_STATE_DEBOUNCE) { + if (!SD_MMC_IS_TIMEOUT()) { + // Debounce on going + return SD_MMC_ERR_NO_CARD; + } + // Card is not initialized + sd_mmc_cards[slot].state = SD_MMC_CARD_STATE_INIT; + // Set 1-bit bus width and low clock for initialization + sd_mmc_cards[slot].clock = SDMMC_CLOCK_INIT; + sd_mmc_cards[slot].bus_width = 1; + sd_mmc_cards[slot].high_speed = 0; + } + if (sd_mmc_cards[slot].state == SD_MMC_CARD_STATE_UNUSABLE) { + return SD_MMC_ERR_UNUSABLE; + } +#else + // No pin card detection, then always try to install it + if ((sd_mmc_cards[slot].state == SD_MMC_CARD_STATE_NO_CARD) + || (sd_mmc_cards[slot].state == SD_MMC_CARD_STATE_UNUSABLE)) { + // Card is not initialized + sd_mmc_cards[slot].state = SD_MMC_CARD_STATE_INIT; + // Set 1-bit bus width and low clock for initialization + sd_mmc_cards[slot].clock = SDMMC_CLOCK_INIT; + sd_mmc_cards[slot].bus_width = 1; + sd_mmc_cards[slot].high_speed = 0; + } +#endif + + // Initialize interface + sd_mmc_slot_sel = slot; + sd_mmc_card = &sd_mmc_cards[slot]; + sd_mmc_configure_slot(); + return (sd_mmc_cards[slot].state == SD_MMC_CARD_STATE_INIT) ? + SD_MMC_INIT_ONGOING : SD_MMC_OK; +} + +/** + * \brief Configures the driver with the selected card configuration + */ +static void sd_mmc_configure_slot(void) +{ + driver_select_device(sd_mmc_slot_sel, sd_mmc_card->clock, + sd_mmc_card->bus_width, sd_mmc_card->high_speed); +} + +/** + * \brief Deselect the current card slot + */ +static void sd_mmc_deselect_slot(void) +{ + if (sd_mmc_slot_sel < SD_MMC_MEM_CNT) { + driver_deselect_device(sd_mmc_slot_sel); + } +} + +/** + * \brief Initialize the SD card in SPI mode. + * + * \note + * This function runs the initialization procedure and the identification + * process, then it sets the SD/MMC card in transfer state. + * At last, it will automaticly enable maximum bus width and transfer speed. + * + * \return true if success, otherwise false + */ +static bool sd_mmc_spi_card_init(void) +{ + uint8_t v2 = 0; + + // In first, try to install SD/SDIO card + sd_mmc_card->type = CARD_TYPE_SD; + sd_mmc_card->version = CARD_VER_UNKNOWN; + sd_mmc_card->rca = 0; + sd_mmc_debug("Start SD card install\n\r"); + + // Card need of 74 cycles clock minimum to start + driver_send_clock(); + + // CMD0 - Reset all cards to idle state. + if (!driver_send_cmd(SDMMC_SPI_CMD0_GO_IDLE_STATE, 0)) { + return false; + } + if (!sd_cmd8(&v2)) { + return false; + } + // Try to get the SDIO card's operating condition + if (!sdio_op_cond()) { + return false; + } + + if (sd_mmc_card->type & CARD_TYPE_SD) { + // Try to get the SD card's operating condition + if (!sd_spi_op_cond(v2)) { + // It is not a SD card + sd_mmc_debug("Start MMC Install\n\r"); + sd_mmc_card->type = CARD_TYPE_MMC; + return sd_mmc_spi_install_mmc(); + } + + /* The CRC on card is disabled by default. + * However, to be sure, the CRC OFF command is send. + * Unfortunately, specific SDIO card does not support it + * (H&D wireless card - HDG104 WiFi SIP) + * and the command is send only on SD card. + */ + if (!driver_send_cmd(SDMMC_SPI_CMD59_CRC_ON_OFF, 0)) { + return false; + } + } + // SD MEMORY + if (sd_mmc_card->type & CARD_TYPE_SD) { + // Get the Card-Specific Data + if (!sd_mmc_cmd9_spi()) { + return false; + } + sd_decode_csd(); + // Read the SCR to get card version + if (!sd_acmd51()) { + return false; + } + } + if (IS_SDIO()) { + if (!sdio_get_max_speed()) { + return false; + } + } + // SD MEMORY not HC, Set default block size + if ((sd_mmc_card->type & CARD_TYPE_SD) && + (0 == (sd_mmc_card->type & CARD_TYPE_HC))) { + if (!driver_send_cmd(SDMMC_CMD16_SET_BLOCKLEN, SD_MMC_BLOCK_SIZE)) { + return false; + } + } + // Check communication + if (sd_mmc_card->type & CARD_TYPE_SD) { + if (!sd_mmc_cmd13()) { + return false; + } + } + // Reinitialize the slot with the new speed + sd_mmc_configure_slot(); + return true; +} + +/** + * \brief Initialize the SD card in MCI mode. + * + * \note + * This function runs the initialization procedure and the identification + * process, then it sets the SD/MMC card in transfer state. + * At last, it will automaticly enable maximum bus width and transfer speed. + * + * \return true if success, otherwise false + */ +static bool sd_mmc_mci_card_init(void) +{ + uint8_t v2 = 0; +#ifdef SDIO_SUPPORT_ENABLE + uint8_t data = 0x08; +#endif + + // In first, try to install SD/SDIO card + sd_mmc_card->type = CARD_TYPE_SD; + sd_mmc_card->version = CARD_VER_UNKNOWN; + sd_mmc_card->rca = 0; + sd_mmc_debug("Start SD card install\n\r"); + + // Card need of 74 cycles clock minimum to start + driver_send_clock(); + +#ifdef SDIO_SUPPORT_ENABLE + /* CMD52 Reset SDIO */ + sdio_cmd52(SDIO_CMD52_WRITE_FLAG, SDIO_CIA,SDIO_CCCR_IOA, 0, &data); +#endif + + // CMD0 - Reset all cards to idle state. + if (!driver_send_cmd(SDMMC_MCI_CMD0_GO_IDLE_STATE, 0)) { + return false; + } + if (!sd_cmd8(&v2)) { + return false; + } + // Try to get the SDIO card's operating condition + if (!sdio_op_cond()) { + return false; + } + + if (sd_mmc_card->type & CARD_TYPE_SD) { + // Try to get the SD card's operating condition + if (!sd_mci_op_cond(v2)) { + // It is not a SD card + sd_mmc_debug("Start MMC Install\n\r"); + sd_mmc_card->type = CARD_TYPE_MMC; + return sd_mmc_mci_install_mmc(); + } + } + + if (sd_mmc_card->type & CARD_TYPE_SD) { + // SD MEMORY, Put the Card in Identify Mode + // Note: The CID is not used in this stack + if (!driver_send_cmd(SDMMC_CMD2_ALL_SEND_CID, 0)) { + return false; + } + } + // Ask the card to publish a new relative address (RCA). + if (!driver_send_cmd(SD_CMD3_SEND_RELATIVE_ADDR, 0)) { + return false; + } + sd_mmc_card->rca = (driver_get_response() >> 16) & 0xFFFF; + + // SD MEMORY, Get the Card-Specific Data + if (sd_mmc_card->type & CARD_TYPE_SD) { + if (!sd_mmc_cmd9_mci()) { + return false; + } + sd_decode_csd(); + } + // Select the and put it into Transfer Mode + if (!driver_send_cmd(SDMMC_CMD7_SELECT_CARD_CMD, + (uint32_t)sd_mmc_card->rca << 16)) { + return false; + } + // SD MEMORY, Read the SCR to get card version + if (sd_mmc_card->type & CARD_TYPE_SD) { + if (!sd_acmd51()) { + return false; + } + } + if (IS_SDIO()) { + if (!sdio_get_max_speed()) { + return false; + } + } + if ((4 <= driver_get_bus_width(sd_mmc_slot_sel))) { + // TRY to enable 4-bit mode + if (IS_SDIO()) { + if (!sdio_cmd52_set_bus_width()) { + return false; + } + } + if (sd_mmc_card->type & CARD_TYPE_SD) { + if (!sd_acmd6()) { + return false; + } + } + // Switch to selected bus mode + sd_mmc_configure_slot(); + } + if (driver_is_high_speed_capable()) { + // TRY to enable High-Speed Mode + if (IS_SDIO()) { + if (!sdio_cmd52_set_high_speed()) { + return false; + } + } + if (sd_mmc_card->type & CARD_TYPE_SD) { + if (sd_mmc_card->version > CARD_VER_SD_1_0) { + if (!sd_cm6_set_high_speed()) { + return false; + } + } + } + // Valid new configuration + sd_mmc_configure_slot(); + } + // SD MEMORY, Set default block size + if (sd_mmc_card->type & CARD_TYPE_SD) { + if (!driver_send_cmd(SDMMC_CMD16_SET_BLOCKLEN, SD_MMC_BLOCK_SIZE)) { + return false; + } + } + return true; +} + +/** + * \brief Initialize the MMC card in SPI mode. + * + * \note + * This function runs the initialization procedure and the identification + * process, then it sets the SD/MMC card in transfer state. + * At last, it will automaticly enable maximum bus width and transfer speed. + * + * \return true if success, otherwise false + */ +static bool sd_mmc_spi_install_mmc(void) +{ + uint8_t b_authorize_high_speed; + + // CMD0 - Reset all cards to idle state. + if (!driver_send_cmd(SDMMC_SPI_CMD0_GO_IDLE_STATE, 0)) { + return false; + } + + if (!mmc_spi_op_cond()) { + return false; + } + + // Disable CRC check for SPI mode + if (!driver_send_cmd(SDMMC_SPI_CMD59_CRC_ON_OFF, 0)) { + return false; + } + // Get the Card-Specific Data + if (!sd_mmc_cmd9_spi()) { + return false; + } + mmc_decode_csd(); + // For MMC 4.0 Higher version + if (sd_mmc_card->version >= CARD_VER_MMC_4) { + // Get EXT_CSD + if (!mmc_cmd8(&b_authorize_high_speed)) { + return false; + } + } + // Set default block size + if (!driver_send_cmd(SDMMC_CMD16_SET_BLOCKLEN, SD_MMC_BLOCK_SIZE)) { + return false; + } + // Check communication + if (!sd_mmc_cmd13()) { + return false; + } + // Reinitialize the slot with the new speed + sd_mmc_configure_slot(); + return true; +} + + +/** + * \brief Initialize the MMC card in MCI mode. + * + * \note + * This function runs the initialization procedure and the identification + * process, then it sets the SD/MMC card in transfer state. + * At last, it will automaticly enable maximum bus width and transfer speed. + * + * \return true if success, otherwise false + */ +static bool sd_mmc_mci_install_mmc(void) +{ + uint8_t b_authorize_high_speed; + + // CMD0 - Reset all cards to idle state. + if (!driver_send_cmd(SDMMC_MCI_CMD0_GO_IDLE_STATE, 0)) { + return false; + } + + if (!mmc_mci_op_cond()) { + return false; + } + + // Put the Card in Identify Mode + // Note: The CID is not used in this stack + if (!driver_send_cmd(SDMMC_CMD2_ALL_SEND_CID, 0)) { + return false; + } + // Assign relative address to the card. + sd_mmc_card->rca = 1; + if (!driver_send_cmd(MMC_CMD3_SET_RELATIVE_ADDR, + (uint32_t)sd_mmc_card->rca << 16)) { + return false; + } + // Get the Card-Specific Data + if (!sd_mmc_cmd9_mci()) { + return false; + } + mmc_decode_csd(); + // Select the and put it into Transfer Mode + if (!driver_send_cmd(SDMMC_CMD7_SELECT_CARD_CMD, + (uint32_t)sd_mmc_card->rca << 16)) { + return false; + } + if (sd_mmc_card->version >= CARD_VER_MMC_4) { + // For MMC 4.0 Higher version + // Get EXT_CSD + if (!mmc_cmd8(&b_authorize_high_speed)) { + return false; + } + if (4 <= driver_get_bus_width(sd_mmc_slot_sel)) { + // Enable more bus width + if (!mmc_cmd6_set_bus_width(driver_get_bus_width(sd_mmc_slot_sel))) { + return false; + } + // Reinitialize the slot with the bus width + sd_mmc_configure_slot(); + } + if (driver_is_high_speed_capable() && b_authorize_high_speed) { + // Enable HS + if (!mmc_cmd6_set_high_speed()) { + return false; + } + // Reinitialize the slot with the new speed + sd_mmc_configure_slot(); + } + } else { + // Reinitialize the slot with the new speed + sd_mmc_configure_slot(); + } + + uint8_t retry = 10; + while (retry--) { + // Retry is a WORKAROUND for no compliance card (Atmel Internal ref. MMC19): + // These cards seem not ready immediatly + // after the end of busy of mmc_cmd6_set_high_speed() + + // Set default block size + if (driver_send_cmd(SDMMC_CMD16_SET_BLOCKLEN, SD_MMC_BLOCK_SIZE)) { + return true; + } + } + return false; +} + +//------------------------------------------------------------------- +//--------------------- PUBLIC FUNCTIONS ---------------------------- + +void sd_mmc_init(void) +{ + //! Enable the PMC clock for the card detect pins +#if (defined SD_MMC_0_CD_GPIO) && (SAM) && (!SAM4L) +# include "pmc.h" +# define SD_MMC_ENABLE_CD_PIN(slot, unused) \ + pmc_enable_periph_clk(SD_MMC_##slot##_CD_PIO_ID); + MREPEAT(SD_MMC_MEM_CNT, SD_MMC_ENABLE_CD_PIN, ~) +# undef SD_MMC_ENABLE_CD_PIN +#endif + //! Enable the PMC clock for the card write protection pins +#if (defined SD_MMC_0_WP_GPIO) && (SAM) && (!SAM4L) +# include "pmc.h" +# define SD_MMC_ENABLE_WP_PIN(slot, unused) \ + pmc_enable_periph_clk(SD_MMC_##slot##_WP_PIO_ID); + MREPEAT(SD_MMC_MEM_CNT, SD_MMC_ENABLE_WP_PIN, ~) +# undef SD_MMC_ENABLE_WP_PIN +#endif + for (uint8_t slot = 0; slot < SD_MMC_MEM_CNT; slot++) { + sd_mmc_cards[slot].state = SD_MMC_CARD_STATE_NO_CARD; + } + sd_mmc_slot_sel = 0xFF; // No slot configurated + driver_init(); +} + +uint8_t sd_mmc_nb_slot(void) +{ + return SD_MMC_MEM_CNT; +} + +sd_mmc_err_t sd_mmc_check(uint8_t slot) +{ + sd_mmc_err_t sd_mmc_err; + + sd_mmc_err = sd_mmc_select_slot(slot); + if (sd_mmc_err != SD_MMC_INIT_ONGOING) { + sd_mmc_deselect_slot(); + return sd_mmc_err; + } + + // Initialization of the card requested + if (sd_mmc_is_spi()? sd_mmc_spi_card_init() + : sd_mmc_mci_card_init()) { + sd_mmc_debug("SD/MMC card ready\n\r"); + sd_mmc_card->state = SD_MMC_CARD_STATE_READY; + sd_mmc_deselect_slot(); + // To notify that the card has been just initialized + // It is necessary for USB Device MSC + return SD_MMC_INIT_ONGOING; + } + sd_mmc_debug("SD/MMC card initialization failed\n\r"); + sd_mmc_card->state = SD_MMC_CARD_STATE_UNUSABLE; + sd_mmc_deselect_slot(); + return SD_MMC_ERR_UNUSABLE; +} + +card_type_t sd_mmc_get_type(uint8_t slot) +{ + if (SD_MMC_OK != sd_mmc_select_slot(slot)) { + return CARD_TYPE_UNKNOWN; + } + sd_mmc_deselect_slot(); + return sd_mmc_card->type; +} + +card_version_t sd_mmc_get_version(uint8_t slot) +{ + if (SD_MMC_OK != sd_mmc_select_slot(slot)) { + return CARD_VER_UNKNOWN; + } + sd_mmc_deselect_slot(); + return sd_mmc_card->version; +} + +uint32_t sd_mmc_get_capacity(uint8_t slot) +{ + if (SD_MMC_OK != sd_mmc_select_slot(slot)) { + return 0; + } + sd_mmc_deselect_slot(); + return sd_mmc_card->capacity; +} + +bool sd_mmc_is_write_protected(uint8_t slot) +{ + UNUSED(slot); +#if (defined SD_MMC_0_WP_GPIO) + //! Card Detect pins + if (ioport_get_pin_level(sd_mmc_cards[slot].wp_gpio) + == SD_MMC_0_WP_DETECT_VALUE) { + return true; + } +#endif + return false; +} + +sd_mmc_err_t sd_mmc_init_read_blocks(uint8_t slot, uint32_t start, + uint16_t nb_block) +{ + sd_mmc_err_t sd_mmc_err; + uint32_t cmd, arg, resp; + + sd_mmc_err = sd_mmc_select_slot(slot); + if (sd_mmc_err != SD_MMC_OK) { + return sd_mmc_err; + } + + // Wait for data ready status + if (!sd_mmc_cmd13()) { + sd_mmc_deselect_slot(); + return SD_MMC_ERR_COMM; + } + + if (nb_block > 1) { + cmd = SDMMC_CMD18_READ_MULTIPLE_BLOCK; + } else { + cmd = SDMMC_CMD17_READ_SINGLE_BLOCK; + } + /* + * SDSC Card (CCS=0) uses byte unit address, + * SDHC and SDXC Cards (CCS=1) use block unit address (512 Bytes unit). + */ + if (sd_mmc_card->type & CARD_TYPE_HC) { + arg = start; + } else { + arg = (start * SD_MMC_BLOCK_SIZE); + } + + if (!driver_adtc_start(cmd, arg, SD_MMC_BLOCK_SIZE, nb_block, true)) { + sd_mmc_deselect_slot(); + return SD_MMC_ERR_COMM; + } + // Check response + if (sd_mmc_is_mci()) { + resp = driver_get_response(); + if (resp & CARD_STATUS_ERR_RD_WR) { + sd_mmc_debug("%s: Read blocks %02d resp32 0x%08x CARD_STATUS_ERR_RD_WR\n\r", + __func__, (int)SDMMC_CMD_GET_INDEX(cmd), resp); + sd_mmc_deselect_slot(); + return SD_MMC_ERR_COMM; + } + } + sd_mmc_nb_block_remaining = nb_block; + sd_mmc_nb_block_to_tranfer = nb_block; + return SD_MMC_OK; +} + +sd_mmc_err_t sd_mmc_start_read_blocks(void *dest, uint16_t nb_block) +{ + Assert(sd_mmc_nb_block_remaining >= nb_block); + + if (!driver_start_read_blocks(dest, nb_block)) { + sd_mmc_nb_block_remaining = 0; + return SD_MMC_ERR_COMM; + } + sd_mmc_nb_block_remaining -= nb_block; + return SD_MMC_OK; +} + +sd_mmc_err_t sd_mmc_wait_end_of_read_blocks(bool abort) +{ + if (!driver_wait_end_of_read_blocks()) { + return SD_MMC_ERR_COMM; + } + if (abort) { + sd_mmc_nb_block_remaining = 0; + } else if (sd_mmc_nb_block_remaining) { + return SD_MMC_OK; + } + + // All blocks are transfered then stop read operation + if (sd_mmc_nb_block_to_tranfer == 1) { + // Single block transfer, then nothing to do + sd_mmc_deselect_slot(); + return SD_MMC_OK; + } + // WORKAROUND for no compliance card (Atmel Internal ref. !MMC7 !SD19): + // The errors on this command must be ignored + // and one retry can be necessary in SPI mode for no compliance card. + if (!driver_adtc_stop(SDMMC_CMD12_STOP_TRANSMISSION, 0)) { + driver_adtc_stop(SDMMC_CMD12_STOP_TRANSMISSION, 0); + } + sd_mmc_deselect_slot(); + return SD_MMC_OK; +} + +sd_mmc_err_t sd_mmc_init_write_blocks(uint8_t slot, uint32_t start, + uint16_t nb_block) +{ + sd_mmc_err_t sd_mmc_err; + uint32_t cmd, arg, resp; + + sd_mmc_err = sd_mmc_select_slot(slot); + if (sd_mmc_err != SD_MMC_OK) { + return sd_mmc_err; + } + if (sd_mmc_is_write_protected(slot)) { + sd_mmc_deselect_slot(); + return SD_MMC_ERR_WP; + } + + if (nb_block > 1) { + cmd = SDMMC_CMD25_WRITE_MULTIPLE_BLOCK; + } else { + cmd = SDMMC_CMD24_WRITE_BLOCK; + } + /* + * SDSC Card (CCS=0) uses byte unit address, + * SDHC and SDXC Cards (CCS=1) use block unit address (512 Bytes unit). + */ + if (sd_mmc_card->type & CARD_TYPE_HC) { + arg = start; + } else { + arg = (start * SD_MMC_BLOCK_SIZE); + } + if (!driver_adtc_start(cmd, arg, SD_MMC_BLOCK_SIZE, nb_block, true)) { + sd_mmc_deselect_slot(); + return SD_MMC_ERR_COMM; + } + // Check response + if (sd_mmc_is_mci()) { + resp = driver_get_response(); + if (resp & CARD_STATUS_ERR_RD_WR) { + sd_mmc_debug("%s: Write blocks %02d r1 0x%08x CARD_STATUS_ERR_RD_WR\n\r", + __func__, (int)SDMMC_CMD_GET_INDEX(cmd), resp); + sd_mmc_deselect_slot(); + return SD_MMC_ERR_COMM; + } + } + sd_mmc_nb_block_remaining = nb_block; + sd_mmc_nb_block_to_tranfer = nb_block; + return SD_MMC_OK; +} + +sd_mmc_err_t sd_mmc_start_write_blocks(const void *src, uint16_t nb_block) +{ + Assert(sd_mmc_nb_block_remaining >= nb_block); + if (!driver_start_write_blocks(src, nb_block)) { + sd_mmc_nb_block_remaining = 0; + return SD_MMC_ERR_COMM; + } + sd_mmc_nb_block_remaining -= nb_block; + return SD_MMC_OK; +} + +sd_mmc_err_t sd_mmc_wait_end_of_write_blocks(bool abort) +{ + if (!driver_wait_end_of_write_blocks()) { + return SD_MMC_ERR_COMM; + } + if (abort) { + sd_mmc_nb_block_remaining = 0; + } else if (sd_mmc_nb_block_remaining) { + return SD_MMC_OK; + } + + // All blocks are transfered then stop write operation + if (sd_mmc_nb_block_to_tranfer == 1) { + // Single block transfer, then nothing to do + sd_mmc_deselect_slot(); + return SD_MMC_OK; + } + + if (sd_mmc_is_mci()) { + // Note: SPI multiblock writes terminate using a special + // token, not a STOP_TRANSMISSION request. + if (!driver_adtc_stop(SDMMC_CMD12_STOP_TRANSMISSION, 0)) { + sd_mmc_deselect_slot(); + return SD_MMC_ERR_COMM; + } + } + sd_mmc_deselect_slot(); + return SD_MMC_OK; +} + +#ifdef SDIO_SUPPORT_ENABLE +sd_mmc_err_t sdio_read_direct(uint8_t slot, uint8_t func_num, uint32_t addr, + uint8_t *dest) +{ + sd_mmc_err_t sd_mmc_err; + + if (dest == NULL) { + return SD_MMC_ERR_PARAM; + } + + sd_mmc_err = sd_mmc_select_slot(slot); + if (sd_mmc_err != SD_MMC_OK) { + return sd_mmc_err; + } + + if (!sdio_cmd52(SDIO_CMD52_READ_FLAG, func_num, addr, 0, dest)) { + sd_mmc_deselect_slot(); + return SD_MMC_ERR_COMM; + } + sd_mmc_deselect_slot(); + return SD_MMC_OK; +} + +sd_mmc_err_t sdio_write_direct(uint8_t slot, uint8_t func_num, uint32_t addr, + uint8_t data) +{ + sd_mmc_err_t sd_mmc_err; + + sd_mmc_err = sd_mmc_select_slot(slot); + if (sd_mmc_err != SD_MMC_OK) { + return sd_mmc_err; + } + + if (!sdio_cmd52(SDIO_CMD52_WRITE_FLAG, func_num, addr, 0, &data)) { + sd_mmc_deselect_slot(); + return SD_MMC_ERR_COMM; + } + + sd_mmc_deselect_slot(); + return SD_MMC_OK; +} + +sd_mmc_err_t sdio_read_extended(uint8_t slot, uint8_t func_num, uint32_t addr, + uint8_t inc_addr, uint8_t *dest, uint16_t size) +{ + sd_mmc_err_t sd_mmc_err; + + if ((size == 0) || (size > 512)) { + return SD_MMC_ERR_PARAM; + } + + sd_mmc_err = sd_mmc_select_slot(slot); + if (sd_mmc_err != SD_MMC_OK) { + return sd_mmc_err; + } + + if (!sdio_cmd53(SDIO_CMD53_READ_FLAG, func_num, addr, inc_addr, + size, true)) { + sd_mmc_deselect_slot(); + return SD_MMC_ERR_COMM; + } + if (!driver_start_read_blocks(dest, 1)) { + sd_mmc_deselect_slot(); + return SD_MMC_ERR_COMM; + } + if (!driver_wait_end_of_read_blocks()) { + sd_mmc_deselect_slot(); + return SD_MMC_ERR_COMM; + } + + sd_mmc_deselect_slot(); + return SD_MMC_OK; +} + +sd_mmc_err_t sdio_write_extended(uint8_t slot, uint8_t func_num, uint32_t addr, + uint8_t inc_addr, uint8_t *src, uint16_t size) +{ + sd_mmc_err_t sd_mmc_err; + + if ((size == 0) || (size > 512)) { + return SD_MMC_ERR_PARAM; + } + + sd_mmc_err = sd_mmc_select_slot(slot); + if (sd_mmc_err != SD_MMC_OK) { + return sd_mmc_err; + } + + if (!sdio_cmd53(SDIO_CMD53_WRITE_FLAG, func_num, addr, inc_addr, + size, true)) { + sd_mmc_deselect_slot(); + return SD_MMC_ERR_COMM; + } + if (!driver_start_write_blocks(src, 1)) { + sd_mmc_deselect_slot(); + return SD_MMC_ERR_COMM; + } + if (!driver_wait_end_of_write_blocks()) { + sd_mmc_deselect_slot(); + return SD_MMC_ERR_COMM; + } + + sd_mmc_deselect_slot(); + return SD_MMC_OK; +} +#endif // SDIO_SUPPORT_ENABLE + +//! @} diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/memory/sd_mmc/sd_mmc.h b/hw-libs/drivers/SAMx70/ASF/common/components/memory/sd_mmc/sd_mmc.h new file mode 100644 index 000000000..8c71c51b3 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/memory/sd_mmc/sd_mmc.h @@ -0,0 +1,303 @@ +/** + * \file + * + * \brief Common SD/MMC stack header file + * + * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef SD_MMC_H_INCLUDED +#define SD_MMC_H_INCLUDED + +#include "compiler.h" +#include "conf_sd_mmc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \ingroup common_memory + * \defgroup sd_mmc_stack_group SD/MMC/SDIO common stack + * + * SD/MMC/SDIO basic APIs used by SD/MMC/SDIO memory + * APIs (\ref sd_mmc_stack_mem_group). + * Also, it can be used by application which use the SDIO card + * or specific application which does not need of File System. + * + * For usual application which use the SD/MMC card in + * memory mode with a file system, please refer to + * \ref sd_mmc_stack_mem_group. + * @{ + */ + +typedef uint8_t sd_mmc_err_t; //!< Type of return error code + +//! \name Return error codes +//! @{ +#define SD_MMC_OK 0 //! No error +#define SD_MMC_INIT_ONGOING 1 //! Card not initialized +#define SD_MMC_ERR_NO_CARD 2 //! No SD/MMC card inserted +#define SD_MMC_ERR_UNUSABLE 3 //! Unusable card +#define SD_MMC_ERR_SLOT 4 //! Slot unknow +#define SD_MMC_ERR_COMM 5 //! General communication error +#define SD_MMC_ERR_PARAM 6 //! Illeage input parameter +#define SD_MMC_ERR_WP 7 //! Card write protected +//! @} + +typedef uint8_t card_type_t; //!< Type of card type + +//! \name Card Types +//! @{ +#define CARD_TYPE_UNKNOWN (0) //!< Unknown type card +#define CARD_TYPE_SD (1 << 0) //!< SD card +#define CARD_TYPE_MMC (1 << 1) //!< MMC card +#define CARD_TYPE_SDIO (1 << 2) //!< SDIO card +#define CARD_TYPE_HC (1 << 3) //!< High capacity card +//! SD combo card (io + memory) +#define CARD_TYPE_SD_COMBO (CARD_TYPE_SD | CARD_TYPE_SDIO) +//! @} + +typedef uint8_t card_version_t; //!< Type of card version + +//! \name Card Versions +//! @{ +#define CARD_VER_UNKNOWN (0) //! Unknown card version +#define CARD_VER_SD_1_0 (0x10) //! SD version 1.0 and 1.01 +#define CARD_VER_SD_1_10 (0x1A) //! SD version 1.10 +#define CARD_VER_SD_2_0 (0X20) //! SD version 2.00 +#define CARD_VER_SD_3_0 (0X30) //! SD version 3.0X +#define CARD_VER_MMC_1_2 (0x12) //! MMC version 1.2 +#define CARD_VER_MMC_1_4 (0x14) //! MMC version 1.4 +#define CARD_VER_MMC_2_2 (0x22) //! MMC version 2.2 +#define CARD_VER_MMC_3 (0x30) //! MMC version 3 +#define CARD_VER_MMC_4 (0x40) //! MMC version 4 +//! @} + +//! This SD MMC stack uses the maximum block size autorized (512 bytes) +#define SD_MMC_BLOCK_SIZE 512 + +/** + * \brief Initialize the SD/MMC stack and low level driver required + */ +void sd_mmc_init(void); + +/** \brief Return the number of slot available + * + * \return Number of card slot available + */ +uint8_t sd_mmc_nb_slot(void); + +/** \brief Performs a card checks + * + * \param slot Card slot to use + * + * \retval SD_MMC_OK Card ready + * \retval SD_MMC_INIT_ONGOING Initialization on going + * \retval SD_MMC_ERR_NO_CARD Card not present in slot + * \retval Other value for error cases, see \ref sd_mmc_err_t + */ +sd_mmc_err_t sd_mmc_check(uint8_t slot); + +/** \brief Get the card type + * + * \param slot Card slot + * + * \return Card type (\ref card_type_t) + */ +card_type_t sd_mmc_get_type(uint8_t slot); + +/** \brief Get the card version + * + * \param slot Card slot + * + * \return Card version (\ref card_version_t) + */ +card_version_t sd_mmc_get_version(uint8_t slot); + +/** \brief Get the memory capacity + * + * \param slot Card slot + * + * \return Capacity (unit KB) + */ +uint32_t sd_mmc_get_capacity(uint8_t slot); + +/** \brief Get the card write protection status + * + * \param slot Card slot + * + * \return true, if write portected + */ +bool sd_mmc_is_write_protected(uint8_t slot); + +/** + * \brief Initialize the read blocks of data from the card. + * + * \param slot Card slot to use + * \param start Start block number to to read. + * \param nb_block Total number of blocks to be read. + * + * \return return SD_MMC_OK if success, + * otherwise return an error code (\ref sd_mmc_err_t). + */ +sd_mmc_err_t sd_mmc_init_read_blocks(uint8_t slot, uint32_t start, + uint16_t nb_block); + +/** + * \brief Start the read blocks of data from the card. + * + * \param dest Pointer to read buffer. + * \param nb_block Number of blocks to be read. + * + * \return return SD_MMC_OK if started, + * otherwise return an error code (\ref sd_mmc_err_t). + */ +sd_mmc_err_t sd_mmc_start_read_blocks(void *dest, uint16_t nb_block); + +/** + * \brief Wait the end of read blocks of data from the card. + * + * \param abort Abort reading process initialized by + * \ref sd_mmc_init_read_blocks() after the reading issued by + * \ref sd_mmc_start_read_blocks() is done + * + * \return return SD_MMC_OK if success, + * otherwise return an error code (\ref sd_mmc_err_t). + */ +sd_mmc_err_t sd_mmc_wait_end_of_read_blocks(bool abort); + +/** + * \brief Initialize the write blocks of data + * + * \param slot Card slot to use + * \param start Start block number to be written. + * \param nb_block Total number of blocks to be written. + * + * \return return SD_MMC_OK if success, + * otherwise return an error code (\ref sd_mmc_err_t). + */ +sd_mmc_err_t sd_mmc_init_write_blocks(uint8_t slot, uint32_t start, + uint16_t nb_block); + +/** + * \brief Start the write blocks of data + * + * \param src Pointer to write buffer. + * \param nb_block Number of blocks to be written. + * + * \return return SD_MMC_OK if started, + * otherwise return an error code (\ref sd_mmc_err_t). + */ +sd_mmc_err_t sd_mmc_start_write_blocks(const void *src, uint16_t nb_block); + +/** + * \brief Wait the end of write blocks of data + * + * \param abort Abort writing process initialized by + * \ref sd_mmc_init_write_blocks() after the writing issued by + * \ref sd_mmc_start_write_blocks() is done + * + * \return return SD_MMC_OK if success, + * otherwise return an error code (\ref sd_mmc_err_t). + */ +sd_mmc_err_t sd_mmc_wait_end_of_write_blocks(bool abort); + +#ifdef SDIO_SUPPORT_ENABLE +/** + * \brief Read one byte from SDIO using RW_DIRECT command. + * + * \param slot Card slot to use + * \param func_num Function number. + * \param addr Register address to read from. + * \param dest Pointer to read buffer. + * + * \return return SD_MMC_OK if success, + * otherwise return an error code (\ref sd_mmc_err_t). + */ +sd_mmc_err_t sdio_read_direct(uint8_t slot, uint8_t func_num, uint32_t addr, + uint8_t *dest); +/** + * \brief Write one byte to SDIO using RW_DIRECT command. + * + * \param slot Card slot to use + * \param func_num Function number. + * \param addr Register address to read from. + * \param data Data to be written. + * + * \return return SD_MMC_OK if success, + * otherwise return an error code (\ref sd_mmc_err_t). + */ +sd_mmc_err_t sdio_write_direct(uint8_t slot, uint8_t func_num, uint32_t addr, + uint8_t data); + +/** + * \brief Read bytes from SDIO using RW_EXTENDED command. + * + * \param slot Card slot to use + * \param func_num Function number. + * \param addr First register address to read from. + * \param inc_addr 0 - The data address is fixed. + * 1 - The data address increase automatically. + * \param dest Pointer to read buffer. + * \param size Number of bytes to read (1 ~ 512). + * + * \return return SD_MMC_OK if success, + * otherwise return an error code (\ref sd_mmc_err_t). + */ +sd_mmc_err_t sdio_read_extended(uint8_t slot, uint8_t func_num, uint32_t addr, + uint8_t inc_addr, uint8_t *dest, uint16_t size); + +/** + * \brief Write bytes to SDIO using RW_EXTENDED command. + * + * \param slot Card slot to use + * \param func_num Function number. + * \param addr First register address to write to. + * \param inc_addr 0 - The data address is fixed. + * 1 - The data address increase automatically. + * \param src Pointer to write buffer. + * \param size Number of bytes to read (1 ~ 512). + * + * \return return SD_MMC_OK if success, + * otherwise return an error code (\ref sd_mmc_err_t). + */ +sd_mmc_err_t sdio_write_extended(uint8_t slot, uint8_t func_num, uint32_t addr, + uint8_t inc_addr, uint8_t *src, uint16_t size); +#endif // SDIO_SUPPORT_ENABLE + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* SD_MMC_H_INCLUDED */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/memory/sd_mmc/sd_mmc_mem.c b/hw-libs/drivers/SAMx70/ASF/common/components/memory/sd_mmc/sd_mmc_mem.c new file mode 100644 index 000000000..c445fb88a --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/memory/sd_mmc/sd_mmc_mem.c @@ -0,0 +1,359 @@ +/** + * \file + * + * \brief CTRL_ACCESS interface for common SD/MMC stack + * + * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "conf_access.h" + +#if (SD_MMC_0_MEM == ENABLE) || (SD_MMC_1_MEM == ENABLE) + +#include "conf_sd_mmc.h" +#include "sd_mmc.h" +#include "sd_mmc_mem.h" + +/** + * \ingroup sd_mmc_stack_mem + * \defgroup sd_mmc_stack_mem_internal Implementation of SD/MMC Memory + * @{ + */ + +/** + * \name Control Interface + * @{ + */ + +static bool sd_mmc_ejected[2] = {false, false}; + +Ctrl_status sd_mmc_test_unit_ready(uint8_t slot) +{ + switch (sd_mmc_check(slot)) + { + case SD_MMC_OK: + if (sd_mmc_ejected[slot]) { + return CTRL_NO_PRESENT; + } + if (sd_mmc_get_type(slot) & (CARD_TYPE_SD | CARD_TYPE_MMC)) { + return CTRL_GOOD; + } + // It is not a memory card + return CTRL_NO_PRESENT; + + case SD_MMC_INIT_ONGOING: + return CTRL_BUSY; + + case SD_MMC_ERR_NO_CARD: + sd_mmc_ejected[slot] = false; + return CTRL_NO_PRESENT; + + default: + return CTRL_FAIL; + } +} + +Ctrl_status sd_mmc_test_unit_ready_0(void) +{ + return sd_mmc_test_unit_ready(0); +} + + +Ctrl_status sd_mmc_test_unit_ready_1(void) +{ + return sd_mmc_test_unit_ready(1); +} + +Ctrl_status sd_mmc_read_capacity(uint8_t slot, uint32_t *nb_sector) +{ + // Return last sector address (-1) + *nb_sector = (sd_mmc_get_capacity(slot) * 2) - 1; + return sd_mmc_test_unit_ready(slot); +} + +Ctrl_status sd_mmc_read_capacity_0(uint32_t *nb_sector) +{ + return sd_mmc_read_capacity(0, nb_sector); +} + +Ctrl_status sd_mmc_read_capacity_1(uint32_t *nb_sector) +{ + return sd_mmc_read_capacity(1, nb_sector); +} + +bool sd_mmc_unload(uint8_t slot, bool unload) +{ + sd_mmc_ejected[slot] = unload; + return true; +} + +bool sd_mmc_unload_0(bool unload) +{ + return sd_mmc_unload(0, unload); +} + +bool sd_mmc_unload_1(bool unload) +{ + return sd_mmc_unload(1, unload); +} + +bool sd_mmc_wr_protect(uint8_t slot) +{ + return sd_mmc_is_write_protected(slot); +} + +bool sd_mmc_wr_protect_0(void) +{ + return sd_mmc_wr_protect(0); +} + +bool sd_mmc_wr_protect_1(void) +{ + return sd_mmc_wr_protect(1); +} + +bool sd_mmc_removal(uint8_t slot) +{ + UNUSED(slot); + return true; +} + +bool sd_mmc_removal_0(void) +{ + return sd_mmc_removal(0); +} + +bool sd_mmc_removal_1(void) +{ + return sd_mmc_removal(1); +} +//! @} + +#if ACCESS_USB == true +/** + * \name MEM <-> USB Interface + * @{ + */ + +#include "udi_msc.h" + +COMPILER_WORD_ALIGNED +uint8_t sector_buf_0[SD_MMC_BLOCK_SIZE]; + +COMPILER_WORD_ALIGNED +uint8_t sector_buf_1[SD_MMC_BLOCK_SIZE]; + +Ctrl_status sd_mmc_usb_read_10(uint8_t slot, uint32_t addr, uint16_t nb_sector) +{ + bool b_first_step = true; + uint16_t nb_step; + + switch (sd_mmc_init_read_blocks(slot, addr, nb_sector)) { + case SD_MMC_OK: + break; + case SD_MMC_ERR_NO_CARD: + return CTRL_NO_PRESENT; + default: + return CTRL_FAIL; + } + // Pipeline the 2 transfer in order to speed-up the performances + nb_step = nb_sector + 1; + while (nb_step--) { + if (nb_step) { // Skip last step + // MCI -> RAM + if (SD_MMC_OK != sd_mmc_start_read_blocks(((nb_step % 2) == 0) ? + sector_buf_0 : sector_buf_1, 1)) { + return CTRL_FAIL; + } + } + if (!b_first_step) { // Skip first step + // RAM -> USB + if (!udi_msc_trans_block(true, + ((nb_step % 2) == 0) ? + sector_buf_1 : sector_buf_0, + SD_MMC_BLOCK_SIZE, + NULL)) { + if (!b_first_step) { + sd_mmc_wait_end_of_read_blocks(true); + } + return CTRL_FAIL; + } + } else { + b_first_step = false; + } + if (nb_step) { // Skip last step + if (SD_MMC_OK != sd_mmc_wait_end_of_read_blocks(false)) { + return CTRL_FAIL; + } + } + b_first_step = false; + } + return CTRL_GOOD; +} + +Ctrl_status sd_mmc_usb_read_10_0(uint32_t addr, uint16_t nb_sector) +{ + return sd_mmc_usb_read_10(0, addr, nb_sector); +} + +Ctrl_status sd_mmc_usb_read_10_1(uint32_t addr, uint16_t nb_sector) +{ + return sd_mmc_usb_read_10(1, addr, nb_sector); +} + +Ctrl_status sd_mmc_usb_write_10(uint8_t slot, uint32_t addr, uint16_t nb_sector) +{ + bool b_first_step = true; + uint16_t nb_step; + + switch (sd_mmc_init_write_blocks(slot, addr, nb_sector)) { + case SD_MMC_OK: + break; + case SD_MMC_ERR_NO_CARD: + return CTRL_NO_PRESENT; + default: + return CTRL_FAIL; + } + // Pipeline the 2 transfer in order to speed-up the performances + nb_step = nb_sector + 1; + while (nb_step--) { + if (!b_first_step) { // Skip first step + // RAM -> MCI + if (SD_MMC_OK != sd_mmc_start_write_blocks(((nb_step % 2) == 0) ? + sector_buf_0 : sector_buf_1, 1)) { + return CTRL_FAIL; + } + } + if (nb_step) { // Skip last step + // USB -> RAM + if (!udi_msc_trans_block(false, + ((nb_step % 2) == 0) ? + sector_buf_1 : sector_buf_0, + SD_MMC_BLOCK_SIZE, + NULL)) { + if (!b_first_step) { + sd_mmc_wait_end_of_write_blocks(true); + } + return CTRL_FAIL; + } + } + if (!b_first_step) { // Skip first step + if (SD_MMC_OK != sd_mmc_wait_end_of_write_blocks(false)) { + return CTRL_FAIL; + } + } else { + b_first_step = false; + } + } + return CTRL_GOOD; +} + +Ctrl_status sd_mmc_usb_write_10_0(uint32_t addr, uint16_t nb_sector) +{ + return sd_mmc_usb_write_10(0, addr, nb_sector); +} + +Ctrl_status sd_mmc_usb_write_10_1(uint32_t addr, uint16_t nb_sector) +{ + return sd_mmc_usb_write_10(1, addr, nb_sector); +} +//! @} +#endif // ACCESS_USB == true + + +#if ACCESS_MEM_TO_RAM == true +/** + * \name MEM <-> RAM Interface + * @{ + */ +Ctrl_status sd_mmc_mem_2_ram(uint8_t slot, uint32_t addr, void *ram) +{ + switch (sd_mmc_init_read_blocks(slot, addr, 1)) { + case SD_MMC_OK: + break; + case SD_MMC_ERR_NO_CARD: + return CTRL_NO_PRESENT; + default: + return CTRL_FAIL; + } + if (SD_MMC_OK != sd_mmc_start_read_blocks(ram, 1)) { + return CTRL_FAIL; + } + if (SD_MMC_OK != sd_mmc_wait_end_of_read_blocks(false)) { + return CTRL_FAIL; + } + return CTRL_GOOD; +} + +Ctrl_status sd_mmc_mem_2_ram_0(uint32_t addr, void *ram) +{ + return sd_mmc_mem_2_ram(0, addr, ram); +} + +Ctrl_status sd_mmc_mem_2_ram_1(uint32_t addr, void *ram) +{ + return sd_mmc_mem_2_ram(1, addr, ram); +} + +Ctrl_status sd_mmc_ram_2_mem(uint8_t slot, uint32_t addr, const void *ram) +{ + switch (sd_mmc_init_write_blocks(slot, addr, 1)) { + case SD_MMC_OK: + break; + case SD_MMC_ERR_NO_CARD: + return CTRL_NO_PRESENT; + default: + return CTRL_FAIL; + } + if (SD_MMC_OK != sd_mmc_start_write_blocks(ram, 1)) { + return CTRL_FAIL; + } + if (SD_MMC_OK != sd_mmc_wait_end_of_write_blocks(false)) { + return CTRL_FAIL; + } + return CTRL_GOOD; +} + +Ctrl_status sd_mmc_ram_2_mem_0(uint32_t addr, const void *ram) +{ + return sd_mmc_ram_2_mem(0, addr, ram); +} + +Ctrl_status sd_mmc_ram_2_mem_1(uint32_t addr, const void *ram) +{ + return sd_mmc_ram_2_mem(1, addr, ram); +} +//! @} + +//! @} +#endif // ACCESS_MEM_TO_RAM == true + +#endif // SD_MMC_0_MEM == ENABLE || SD_MMC_1_MEM == ENABLE diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/memory/sd_mmc/sd_mmc_mem.h b/hw-libs/drivers/SAMx70/ASF/common/components/memory/sd_mmc/sd_mmc_mem.h new file mode 100644 index 000000000..1dc809a68 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/memory/sd_mmc/sd_mmc_mem.h @@ -0,0 +1,218 @@ +/** + * \file + * + * \brief CTRL_ACCESS interface for common SD/MMC stack + * + * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SD_MMC_MEM_H_ +#define _SD_MMC_MEM_H_ + +/** + * \ingroup sd_mmc_stack_group + * \defgroup sd_mmc_stack_mem SD/MMC Memory + * + * SD/MMC memory APIs required by CTRL_ACCESS module + * (\ref group_common_services_storage_ctrl_access). + * + * For usual application which use the SD/MMC card in + * memory mode through a file system or a USB device MSC, + * only a call of \ref sd_mmc_init() function is required in the startup. + * + * @{ + */ + +#include "conf_access.h" +#include "ctrl_access.h" + +#if (SD_MMC_0_MEM == ENABLE) || (SD_MMC_1_MEM == ENABLE) + +/*! \name Control Interface + */ +//! @{ + +/*! \brief Tests the memory state and initializes the memory if required. + * + * The TEST UNIT READY SCSI primary command allows an application client to poll + * a LUN until it is ready without having to allocate memory for returned data. + * + * This command may be used to check the media status of LUNs with removable + * media. + * + * \param slot SD/MMC Slot Card Selected. + * + * \return Status. + */ +extern Ctrl_status sd_mmc_test_unit_ready(uint8_t slot); +//! Instance Declaration for sd_mmc_test_unit_ready Slot O +extern Ctrl_status sd_mmc_test_unit_ready_0(void); +//! Instance Declaration for sd_mmc_test_unit_ready Slot 1 +extern Ctrl_status sd_mmc_test_unit_ready_1(void); + +/*! \brief Returns the address of the last valid sector in the memory. + * + * \param slot SD/MMC Slot Card Selected. + * \param u32_nb_sector Pointer to the address of the last valid sector. + * + * \return Status. + */ +extern Ctrl_status sd_mmc_read_capacity(uint8_t slot,uint32_t *u32_nb_sector); +//! Instance Declaration for sd_mmc_read_capacity Slot O +extern Ctrl_status sd_mmc_read_capacity_0(uint32_t *u32_nb_sector); +//! Instance Declaration for sd_mmc_read_capacity Slot 1 +extern Ctrl_status sd_mmc_read_capacity_1(uint32_t *u32_nb_sector); + +/*! \brief Unload/Load the SD/MMC card selected + * + * The START STOP UNIT SCSI optional command allows an application client to + * eject the removable medium on a LUN. + * + * \param slot SD/MMC Slot Card Selected. + * \param unload \c true to unload the medium, \c false to load the medium. + * + * \return \c true if unload/load done success. + */ +extern bool sd_mmc_unload(uint8_t slot, bool unload); +//! Instance Declaration for sd_mmc_unload Slot O +extern bool sd_mmc_unload_0(bool unload); +//! Instance Declaration for sd_mmc_unload Slot 1 +extern bool sd_mmc_unload_1(bool unload); + +/*! \brief Returns the write-protection state of the memory. + * +* \param slot SD/MMC Slot Card Selected. + * \return \c true if the memory is write-protected, else \c false. + * + * \note Only used by removable memories with hardware-specific write + * protection. + */ +extern bool sd_mmc_wr_protect(uint8_t slot); +//! Instance Declaration for sd_mmc_wr_protect Slot O +extern bool sd_mmc_wr_protect_0(void); +//! Instance Declaration for sd_mmc_wr_protect Slot 1 +extern bool sd_mmc_wr_protect_1(void); + +/*! \brief Tells whether the memory is removable. + * + * \param slot SD/MMC Slot Card Selected. + * \return \c true if the memory is removable, else \c false. + */ +extern bool sd_mmc_removal(uint8_t slot); +//! Instance Declaration for sd_mmc_removal Slot O +extern bool sd_mmc_removal_0(void); +//! Instance Declaration for sd_mmc_removal Slot 1 +extern bool sd_mmc_removal_1(void); + +//! @} + + +#if ACCESS_USB == true + +/*! \name MEM <-> USB Interface + */ +//! @{ + +/*! \brief Transfers data from the memory to USB. + * + * \param slot SD/MMC Slot Card Selected. + * \param addr Address of first memory sector to read. + * \param nb_sector Number of sectors to transfer. + * + * \return Status. + */ +extern Ctrl_status sd_mmc_usb_read_10(uint8_t slot,uint32_t addr, uint16_t nb_sector); +//! Instance Declaration for sd_mmc_usb_read_10 Slot O +extern Ctrl_status sd_mmc_usb_read_10_0(uint32_t addr, uint16_t nb_sector); +//! Instance Declaration for sd_mmc_usb_read_10 Slot 1 +extern Ctrl_status sd_mmc_usb_read_10_1(uint32_t addr, uint16_t nb_sector); + +/*! \brief Transfers data from USB to the memory. + * + * \param slot SD/MMC Slot Card Selected. + * \param addr Address of first memory sector to write. + * \param nb_sector Number of sectors to transfer. + * + * \return Status. + */ +extern Ctrl_status sd_mmc_usb_write_10(uint8_t slot,uint32_t addr, uint16_t nb_sector); +//! Instance Declaration for sd_mmc_usb_write_10 Slot O +extern Ctrl_status sd_mmc_usb_write_10_0(uint32_t addr, uint16_t nb_sector); +//! Instance Declaration for sd_mmc_usb_write_10 Slot 1 +extern Ctrl_status sd_mmc_usb_write_10_1(uint32_t addr, uint16_t nb_sector); + +//! @} + +#endif + + +#if ACCESS_MEM_TO_RAM == true + +/*! \name MEM <-> RAM Interface + */ +//! @{ + +/*! \brief Copies 1 data sector from the memory to RAM. + * + * \param slot SD/MMC Slot Card Selected. + * \param addr Address of first memory sector to read. + * \param ram Pointer to RAM buffer to write. + * + * \return Status. + */ +extern Ctrl_status sd_mmc_mem_2_ram(uint8_t slot, uint32_t addr, void *ram); +//! Instance Declaration for sd_mmc_mem_2_ram Slot O +extern Ctrl_status sd_mmc_mem_2_ram_0(uint32_t addr, void *ram); +//! Instance Declaration for sd_mmc_mem_2_ram Slot 1 +extern Ctrl_status sd_mmc_mem_2_ram_1(uint32_t addr, void *ram); + +/*! \brief Copies 1 data sector from RAM to the memory. + * + * \param slot SD/MMC Slot Card Selected. + * \param addr Address of first memory sector to write. + * \param ram Pointer to RAM buffer to read. + * + * \return Status. + */ +extern Ctrl_status sd_mmc_ram_2_mem(uint8_t slot, uint32_t addr, const void *ram); +//! Instance Declaration for sd_mmc_mem_2_ram Slot O +extern Ctrl_status sd_mmc_ram_2_mem_0(uint32_t addr, const void *ram); +//! Instance Declaration for sd_mmc_mem_2_ram Slot 1 +extern Ctrl_status sd_mmc_ram_2_mem_1(uint32_t addr, const void *ram); + +//! @} + +#endif +#endif + +//! @} + +#endif // _SD_MMC_MEM_H_ diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/memory/sd_mmc/sd_mmc_protocol.h b/hw-libs/drivers/SAMx70/ASF/common/components/memory/sd_mmc/sd_mmc_protocol.h new file mode 100644 index 000000000..0cea2084b --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/memory/sd_mmc/sd_mmc_protocol.h @@ -0,0 +1,997 @@ +/** + * \file + * + * \brief SD/MMC protocol definitions. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef SD_MMC_PROTOCOL_H_INCLUDED +#define SD_MMC_PROTOCOL_H_INCLUDED + +#include "compiler.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup sd_mmc_protocol SD/MMC Protocol Definition + * \ingroup sd_mmc_stack_group + * @{ + */ + +// SD/MMC/SDIO default clock frequency for initialization (400KHz) +#define SDMMC_CLOCK_INIT 400000 + + +/** + * \name Macros for command definition + * + * Commands types: + * - broadcast commands (bc), no response + * - broadcast commands with response (bcr) (Note: No open drain on SD card) + * - addressed (point-to-point) commands (ac), no data transfer on DAT lines + * - addressed (point-to-point) data transfer commands (adtc), data transfer + * on DAT lines + * + * Specific MMC norms: + * CMD1, CMD2 & CMD3 are processed in the open-drain mode. + * The CMD line is driven with push-pull drivers. + * + * Specific SD norms: + * There is no open drain mode in SD memory card. + * + *************************************** + * Responses types: + * + * R1, R3, R4 & R5 use a 48 bits response protected by a 7bit CRC checksum + * - R1 receiv data not specified + * - R3 receiv OCR + * - R4, R5 RCA management (MMC only) + * - R6, R7 RCA management (SD only) + * + * R1b assert the BUSY signal and respond with R1. + * If the busy signal is asserted, it is done two clock cycles (Nsr time) + * after the end bit of the command. The DAT0 line is driven low. + * DAT1-DAT7 lines are driven by the card though their values are not relevant. + * + * R2 use a 136 bits response protected by a 7bit CRC checksum + * The content is CID or CSD + * + * Specific MMC norms: + * - R4 (Fast I/O) return RCA + * - R5 (interrupt request) return RCA null + * + * Specific SD norms: + * - R6 (Published RCA) return RCA + * - R7 (Card interface condition) return RCA null + * + * @{ + */ + +//! Value to define a SD/MMC/SDIO command +typedef uint32_t sdmmc_cmd_def_t; + +//! \name Flags used to define a SD/MMC/SDIO command +//! @{ +#define SDMMC_CMD_GET_INDEX(cmd) (cmd & 0x3F) +//! Have response (MCI only) +#define SDMMC_RESP_PRESENT (1lu << 8) +//! 8 bit response (SPI only) +#define SDMMC_RESP_8 (1lu << 9) +//! 32 bit response (SPI only) +#define SDMMC_RESP_32 (1lu << 10) +//! 136 bit response (MCI only) +#define SDMMC_RESP_136 (1lu << 11) +//! Expect valid crc (MCI only) +#define SDMMC_RESP_CRC (1lu << 12) +//! Card may send busy +#define SDMMC_RESP_BUSY (1lu << 13) +// Open drain for a braodcast command (bc) +// or to enter in inactive state (MCI only) +#define SDMMC_CMD_OPENDRAIN (1lu << 14) +//! To signal a data write operation +#define SDMMC_CMD_WRITE (1lu << 15) +//! To signal a SDIO tranfer in multi byte mode +#define SDMMC_CMD_SDIO_BYTE (1lu << 16) +//! To signal a SDIO tranfer in block mode +#define SDMMC_CMD_SDIO_BLOCK (1lu << 17) +//! To signal a data transfer in stream mode +#define SDMMC_CMD_STREAM (1lu << 18) +//! To signal a data transfer in single block mode +#define SDMMC_CMD_SINGLE_BLOCK (1lu << 19) +//! To signal a data transfer in multi block mode +#define SDMMC_CMD_MULTI_BLOCK (1lu << 20) +//! @} + +//! \name Set of flags to define a reponse type +//! @{ +#define SDMMC_CMD_NO_RESP (0) +#define SDMMC_CMD_R1 (SDMMC_RESP_PRESENT | SDMMC_RESP_CRC) +#define SDMMC_CMD_R1B (SDMMC_RESP_PRESENT | SDMMC_RESP_CRC | SDMMC_RESP_BUSY) +#define SDMMC_CMD_R2 (SDMMC_RESP_PRESENT | SDMMC_RESP_8 | SDMMC_RESP_136 | SDMMC_RESP_CRC) +#define SDMMC_CMD_R3 (SDMMC_RESP_PRESENT | SDMMC_RESP_32) +#define SDMMC_CMD_R4 (SDMMC_RESP_PRESENT | SDMMC_RESP_32) +#define SDMMC_CMD_R5 (SDMMC_RESP_PRESENT | SDMMC_RESP_8 | SDMMC_RESP_CRC) +#define SDMMC_CMD_R6 (SDMMC_RESP_PRESENT | SDMMC_RESP_CRC) +#define SDMMC_CMD_R7 (SDMMC_RESP_PRESENT | SDMMC_RESP_32 | SDMMC_RESP_CRC) +//! @} + +//! \name SD/MMC/SDIO command definitions +//! SDMMC_CMDx are include in SD and MMC norms +//! MMC_CMDx are include in MMC norms only +//! SD_CMDx are include in SD norms only +//! SDIO_CMDx are include in SDIO norms only +//! @{ + +/* + * --- Basic commands and read-stream command (class 0 and class 1) --- + */ + +/** Cmd0(bc): Reset all cards to idle state */ +#define SDMMC_SPI_CMD0_GO_IDLE_STATE (0 | SDMMC_CMD_R1) +#define SDMMC_MCI_CMD0_GO_IDLE_STATE (0 | SDMMC_CMD_NO_RESP | SDMMC_CMD_OPENDRAIN) +/** MMC Cmd1(bcr, R3): Ask the card to send its Operating Conditions */ +#define MMC_SPI_CMD1_SEND_OP_COND (1 | SDMMC_CMD_R1) +#define MMC_MCI_CMD1_SEND_OP_COND (1 | SDMMC_CMD_R3 | SDMMC_CMD_OPENDRAIN) +/** Cmd2(bcr, R2): Ask the card to send its CID number (stuff but arg 0 used) */ +#define SDMMC_CMD2_ALL_SEND_CID (2 | SDMMC_CMD_R2 | SDMMC_CMD_OPENDRAIN) +/** SD Cmd3(bcr, R6): Ask the card to publish a new relative address (RCA) */ +#define SD_CMD3_SEND_RELATIVE_ADDR (3 | SDMMC_CMD_R6 | SDMMC_CMD_OPENDRAIN) +/** MMC Cmd3(ac, R1): Assigns relative address to the card */ +#define MMC_CMD3_SET_RELATIVE_ADDR (3 | SDMMC_CMD_R1) +/** Cmd4(bc): Program the DSR of all cards (MCI only) */ +#define SDMMC_CMD4_SET_DSR (4 | SDMMC_CMD_NO_RESP) +/** MMC Cmd5(ac, R1b): Toggle the card between Sleep state and Standby state. */ +#define MMC_CMD5_SLEEP_AWAKE (5 | SDMMC_CMD_R1B) +/** Cmd7(ac, R1/R1b): Select/Deselect card + * For SD: R1b only from the selected card. + * For MMC: R1 while selecting from Stand-By State to Transfer State; + * R1b while selecting from Disconnected State to Programming State. + */ +#define SDMMC_CMD7_SELECT_CARD_CMD (7 | SDMMC_CMD_R1B) +#define SDMMC_CMD7_DESELECT_CARD_CMD (7 | SDMMC_CMD_R1) +/** MMC Cmd8(adtc, R1): Send EXT_CSD register as a block of data */ +#define MMC_CMD8_SEND_EXT_CSD (8 | SDMMC_CMD_R1 | SDMMC_CMD_SINGLE_BLOCK) +/** SD Cmd8(bcr, R7) : Send SD Memory Card interface condition */ +#define SD_CMD8_SEND_IF_COND (8 | SDMMC_CMD_R7 | SDMMC_CMD_OPENDRAIN) +/** Cmd9 SPI (R1): Addressed card sends its card-specific data (CSD) */ +#define SDMMC_SPI_CMD9_SEND_CSD (9 | SDMMC_CMD_R1 | SDMMC_CMD_SINGLE_BLOCK) +/** Cmd9 MCI (ac, R2): Addressed card sends its card-specific data (CSD) */ +#define SDMMC_MCI_CMD9_SEND_CSD (9 | SDMMC_CMD_R2) +/** Cmd10(ac, R2): Addressed card sends its card identification (CID) */ +#define SDMMC_CMD10_SEND_CID (10 | SDMMC_CMD_R2) +/** + * MMC Cmd11(adtc, R1): Read data stream from the card, starting at the given + * address, until a STOP_TRANSMISSION follows. + */ +#define MMC_CMD11_READ_DAT_UNTIL_STOP (11 | SDMMC_CMD_R1) +/* SD Cmd11 MCI (ac, R1): Voltage switching */ +#define SD_CMD11_READ_DAT_UNTIL_STOP (11 | SDMMC_CMD_R1) +/** Cmd12(ac, R1b): Force the card to stop transmission */ +#define SDMMC_CMD12_STOP_TRANSMISSION (12 | SDMMC_CMD_R1B) +/** Cmd13(R2): Addressed card sends its status register. */ +#define SDMMC_SPI_CMD13_SEND_STATUS (13 | SDMMC_CMD_R2) +/** Cmd13(ac, R1): Addressed card sends its status register. */ +#define SDMMC_MCI_CMD13_SEND_STATUS (13 | SDMMC_CMD_R1) +/** MMC Cmd14(adtc, R1): Read the reversed bus testing data pattern from a card. */ +#define MMC_CMD14_BUSTEST_R (14 | SDMMC_CMD_R1) +/** Cmd15(ac): Send an addressed card into the Inactive State. */ +// Note: It is a ac cmd, but it must be send like bc cmd to open drain +#define SDMMC_CMD15_GO_INACTIVE_STATE (15 | SDMMC_CMD_NO_RESP | SDMMC_CMD_OPENDRAIN) +/** MMC Cmd19(adtc, R1): Send the bus test data pattern */ +#define MMC_CMD19_BUSTEST_W (19 | SDMMC_CMD_R1) +/** Cmd58(R3): Reads the OCR register of a card */ +#define SDMMC_SPI_CMD58_READ_OCR (58 | SDMMC_CMD_R3) +/** Cmd59(R1): Turns the CRC option on or off */ +#define SDMMC_SPI_CMD59_CRC_ON_OFF (59 | SDMMC_CMD_R1) + +/* + * --- Block-oriented read commands (class 2) --- + */ +/** Cmd16(ac, R1): Set the block length (in bytes) */ +#define SDMMC_CMD16_SET_BLOCKLEN (16 | SDMMC_CMD_R1) +/** Cmd17(adtc, R1): Read single block */ +#define SDMMC_CMD17_READ_SINGLE_BLOCK (17 | SDMMC_CMD_R1 | SDMMC_CMD_SINGLE_BLOCK) +/** Cmd18(adtc, R1): Read multiple block */ +#define SDMMC_CMD18_READ_MULTIPLE_BLOCK (18 | SDMMC_CMD_R1 | SDMMC_CMD_MULTI_BLOCK) + +/* + * --- Sequential write commands (class 3) --- + */ + +/** + * MMC Cmd20(adtc, R1): Write a data stream from the host, starting at the + * given address, until a STOP_TRANSMISSION follows. + */ +#define MMC_CMD20_WRITE_DAT_UNTIL_STOP (20 | SDMMC_CMD_R1) + +/* + * --- Block-oriented write commands (class 4) --- + */ +/** MMC Cmd23(ac, R1): Set block count */ +#define MMC_CMD23_SET_BLOCK_COUNT (23 | SDMMC_CMD_R1) +/** Cmd24(adtc, R1): Write block */ +#define SDMMC_CMD24_WRITE_BLOCK (24 | SDMMC_CMD_R1 | SDMMC_CMD_WRITE | SDMMC_CMD_SINGLE_BLOCK) +/** Cmd25(adtc, R1): Write multiple block */ +#define SDMMC_CMD25_WRITE_MULTIPLE_BLOCK (25 | SDMMC_CMD_R1 | SDMMC_CMD_WRITE | SDMMC_CMD_MULTI_BLOCK) +/** MMC Cmd26(adtc, R1): Programming of the card identification register. */ +#define MMC_CMD26_PROGRAM_CID (26 | SDMMC_CMD_R1) +/** Cmd27(adtc, R1): Programming of the programmable bits of the CSD. */ +#define SDMMC_CMD27_PROGRAM_CSD (27 | SDMMC_CMD_R1) + +/* + * --- Erase commands (class 5) --- + */ +/** SD Cmd32(ac, R1): */ +#define SD_CMD32_ERASE_WR_BLK_START (32 | SDMMC_CMD_R1) +/** SD Cmd33(ac, R1): */ +#define SD_CMD33_ERASE_WR_BLK_END (33 | SDMMC_CMD_R1) +/** MMC Cmd35(ac, R1): */ +#define MMC_CMD35_ERASE_GROUP_START (35 | SDMMC_CMD_R1) +/** MMC Cmd36(ac, R1): */ +#define MMC_CMD36_ERASE_GROUP_END (36 | SDMMC_CMD_R1) +/** Cmd38(ac, R1B): */ +#define SDMMC_CMD38_ERASE (38 | SDMMC_CMD_R1B) + +/* + * --- Block Oriented Write Protection Commands (class 6) --- + */ +/** Cmd28(ac, R1b): Set write protection */ +#define SDMMC_CMD28_SET_WRITE_PROT (28 | SDMMC_CMD_R1B) +/** Cmd29(ac, R1b): Clr write protection */ +#define SDMMC_CMD29_CLR_WRITE_PROT (29 | SDMMC_CMD_R1B) +/** Cmd30(adtc, R1b): Send write protection */ +#define SDMMC_CMD30_SEND_WRITE_PROT (30 | SDMMC_CMD_R1) + +/* + * --- Lock Card (class 7) --- + */ +/** Cmd42(adtc, R1): Used to set/reset the password or lock/unlock the card. */ +#define SDMMC_CMD42_LOCK_UNLOCK (42 | SDMMC_CMD_R1) + +/* + * --- Application-specific commands (class 8) --- + */ +/** + * Cmd55(ac, R1): Indicate to the card that the next command is an application + * specific command rather than a standard command. + */ +#define SDMMC_CMD55_APP_CMD (55 | SDMMC_CMD_R1) +/** + * Cmd 56(adtc, R1): Used either to transfer a data block to the card or to get + * a data block from the card for general purpose/application specific commands. + */ +#define SDMMC_CMD56_GEN_CMD (56 | SDMMC_CMD_R1) + +/** + * MMC Cmd6(ac, R1b) : Switche the mode of operation of the selected card + * or modifies the EXT_CSD registers. + */ +#define MMC_CMD6_SWITCH (6 | SDMMC_CMD_R1B) +/** + * SD Cmd6(adtc, R1) : Check switchable function (mode 0) + * and switch card function (mode 1). + */ +#define SD_CMD6_SWITCH_FUNC (6 | SDMMC_CMD_R1 | SDMMC_CMD_SINGLE_BLOCK) +/** ACMD6(ac, R1): Define the data bus width */ +#define SD_ACMD6_SET_BUS_WIDTH (6 | SDMMC_CMD_R1) +/** ACMD13(adtc, R1): Send the SD Status. */ +#define SD_ACMD13_SD_STATUS (13 | SDMMC_CMD_R1) +/** + * ACMD22(adtc, R1): Send the number of the written (with-out errors) write + * blocks. + */ +#define SD_ACMD22_SEND_NUM_WR_BLOCKS (22 | SDMMC_CMD_R1) +/** + * ACMD23(ac, R1): Set the number of write blocks to be pre-erased before + * writing + */ +#define SD_ACMD23_SET_WR_BLK_ERASE_COUNT (23 | SDMMC_CMD_R1) +/** + * ACMD41(bcr, R3): Send host capacity support information (HCS) and asks the + * accessed card to send its operating condition register (OCR) content + * in the response + */ +#define SD_MCI_ACMD41_SD_SEND_OP_COND (41 | SDMMC_CMD_R3 | SDMMC_CMD_OPENDRAIN) +/** + * ACMD41(R1): Send host capacity support information (HCS) and activates the + * card's initilization process + */ +#define SD_SPI_ACMD41_SD_SEND_OP_COND (41 | SDMMC_CMD_R1) +/** + * ACMD42(ac, R1): Connect[1]/Disconnect[0] the 50 KOhm pull-up resistor on + * CD/DAT3 (pin 1) of the card. + */ +#define SD_ACMD42_SET_CLR_CARD_DETECT (42 | SDMMC_CMD_R1) +/** ACMD51(adtc, R1): Read the SD Configuration Register (SCR). */ +#define SD_ACMD51_SEND_SCR (51 | SDMMC_CMD_R1 | SDMMC_CMD_SINGLE_BLOCK) + +/* + * --- I/O mode commands (class 9) --- + */ +/** MMC Cmd39(ac, R4): Used to write and read 8 bit (register) data fields. */ +#define MMC_CMD39_FAST_IO (39 | SDMMC_CMD_R4) +/** MMC Cmd40(bcr, R5): Set the system into interrupt mode */ +#define MMC_CMD40_GO_IRQ_STATE (40 | SDMMC_CMD_R5 | SDMMC_CMD_OPENDRAIN) +/** SDIO Cmd5(R4): Send operation condition */ +#define SDIO_CMD5_SEND_OP_COND (5 | SDMMC_CMD_R4 | SDMMC_CMD_OPENDRAIN) +/** SDIO CMD52(R5): Direct IO read/write */ +#define SDIO_CMD52_IO_RW_DIRECT (52 | SDMMC_CMD_R5) +/** SDIO CMD53(R5): Extended IO read/write */ +#define SDIO_CMD53_IO_R_BYTE_EXTENDED (53 | SDMMC_CMD_R5 | SDMMC_CMD_SDIO_BYTE) +#define SDIO_CMD53_IO_W_BYTE_EXTENDED (53 | SDMMC_CMD_R5 | SDMMC_CMD_SDIO_BYTE | SDMMC_CMD_WRITE) +#define SDIO_CMD53_IO_R_BLOCK_EXTENDED (53 | SDMMC_CMD_R5 | SDMMC_CMD_SDIO_BLOCK) +#define SDIO_CMD53_IO_W_BLOCK_EXTENDED (53 | SDMMC_CMD_R5 | SDMMC_CMD_SDIO_BLOCK | SDMMC_CMD_WRITE) +//! @} +//! @} + + +//! \name Macros for command argument definition +//! @{ + + //! \name MMC CMD6 argument structure + //! @{ +//! [31:26] Set to 0 +//! [25:24] Access +#define MMC_CMD6_ACCESS_COMMAND_SET (0lu << 24) +#define MMC_CMD6_ACCESS_SET_BITS (1lu << 24) +#define MMC_CMD6_ACCESS_CLEAR_BITS (2lu << 24) +#define MMC_CMD6_ACCESS_WRITE_BYTE (3lu << 24) +//! [23:16] Index for Mode Segment +#define MMC_CMD6_INDEX_CMD_SET (EXT_CSD_CMD_SET_INDEX << 16) +#define MMC_CMD6_INDEX_CMD_SET_REV (EXT_CSD_CMD_SET_REV_INDEX << 16) +#define MMC_CMD6_INDEX_POWER_CLASS (EXT_CSD_POWER_CLASS_INDEX << 16) +#define MMC_CMD6_INDEX_HS_TIMING (EXT_CSD_HS_TIMING_INDEX << 16) +#define MMC_CMD6_INDEX_BUS_WIDTH (EXT_CSD_BUS_WIDTH_INDEX << 16) +#define MMC_CMD6_INDEX_ERASED_MEM_CONT (EXT_CSD_ERASED_MEM_CONT_INDEX << 16) +#define MMC_CMD6_INDEX_BOOT_CONFIG (EXT_CSD_BOOT_CONFIG_INDEX << 16) +#define MMC_CMD6_INDEX_BOOT_BUS_WIDTH (EXT_CSD_BOOT_BUS_WIDTH_INDEX << 16) +#define MMC_CMD6_INDEX_ERASE_GROUP_DEF (EXT_CSD_ERASE_GROUP_DEF_INDEX << 16) +//! [15:8] Value +#define MMC_CMD6_VALUE_BUS_WIDTH_1BIT (0x0lu << 8) +#define MMC_CMD6_VALUE_BUS_WIDTH_4BIT (0x1lu << 8) +#define MMC_CMD6_VALUE_BUS_WIDTH_8BIT (0x2lu << 8) +#define MMC_CMD6_VALUE_HS_TIMING_ENABLE (0x1lu << 8) +#define MMC_CMD6_VALUE_HS_TIMING_DISABLE (0x0lu << 8) +//! [7:3] Set to 0 +//! [2:0] Cmd Set + //! @} + + //! \name SD CMD6 argument structure + //! @{ +//! CMD6 arg[ 3: 0] function group 1, access mode +#define SD_CMD6_GRP1_HIGH_SPEED (0x1lu << 0) +#define SD_CMD6_GRP1_DEFAULT (0x0lu << 0) +//! CMD6 arg[ 7: 4] function group 2, command system +#define SD_CMD6_GRP2_NO_INFLUENCE (0xFlu << 4) +#define SD_CMD6_GRP2_DEFAULT (0x0lu << 4) +//! CMD6 arg[11: 8] function group 3, 0xF or 0x0 +#define SD_CMD6_GRP3_NO_INFLUENCE (0xFlu << 8) +#define SD_CMD6_GRP3_DEFAULT (0x0lu << 8) +//! CMD6 arg[15:12] function group 4, 0xF or 0x0 +#define SD_CMD6_GRP4_NO_INFLUENCE (0xFlu << 12) +#define SD_CMD6_GRP4_DEFAULT (0x0lu << 12) +//! CMD6 arg[19:16] function group 5, 0xF or 0x0 +#define SD_CMD6_GRP5_NO_INFLUENCE (0xFlu << 16) +#define SD_CMD6_GRP5_DEFAULT (0x0lu << 16) +//! CMD6 arg[23:20] function group 6, 0xF or 0x0 +#define SD_CMD6_GRP6_NO_INFLUENCE (0xFlu << 20) +#define SD_CMD6_GRP6_DEFAULT (0x0lu << 20) +//! CMD6 arg[30:24] reserved 0 +//! CMD6 arg[31 ] Mode, 0: Check, 1: Switch +#define SD_CMD6_MODE_CHECK (0lu << 31) +#define SD_CMD6_MODE_SWITCH (1lu << 31) + //! @} + + //! \name SD CMD8 argument structure + //! @{ +#define SD_CMD8_PATTERN 0xAA +#define SD_CMD8_MASK_PATTERN 0xFF +#define SD_CMD8_HIGH_VOLTAGE 0x100 +#define SD_CMD8_MASK_VOLTAGE 0xF00 + //! @} + + //! \name SD ACMD41 arguments + //! @{ +#define SD_ACMD41_HCS (1lu << 30) //!< (SD) Host Capacity Support + //! @} +//! @} + + +//! \name SDIO definitions +//! @{ + + //! \name SDIO state (in R5) + //! @{ +#define SDIO_R5_COM_CRC_ERROR (1lu << 15) /**< CRC check error */ +#define SDIO_R5_ILLEGAL_COMMAND (1lu << 14) /**< Illegal command */ +#define SDIO_R5_STATE (3lu << 12) /**< SDIO R5 state mask */ +#define SDIO_R5_STATE_DIS (0lu << 12) /**< Disabled */ +#define SDIO_R5_STATE_CMD (1lu << 12) /**< DAT lines free */ +#define SDIO_R5_STATE_TRN (2lu << 12) /**< Transfer */ +#define SDIO_R5_STATE_RFU (3lu << 12) /**< Reserved */ +#define SDIO_R5_ERROR (1lu << 11) /**< General error */ +#define SDIO_R5_FUNC_NUM (1lu << 9) /**< Invalid function number */ +#define SDIO_R5_OUT_OF_RANGE (1lu << 8) /**< Argument out of range */ +#define SDIO_R5_STATUS_ERR (SDIO_R5_ERROR | SDIO_R5_FUNC_NUM \ + | SDIO_R5_OUT_OF_RANGE) //!< Errro status bits mask + //! @} + + //! \name SDIO state (in R6) + //! @{ +/** The CRC check of the previous command failed. */ +#define SDIO_R6_COM_CRC_ERROR (1lu << 15) +/** Command not legal for the card state. */ +#define SDIO_R6_ILLEGAL_COMMAND (1lu << 14) +/** A general or an unknown error occurred during the operation. */ +#define SDIO_R6_ERROR (1lu << 13) +/** Status bits mask for SDIO R6 */ +#define SDIO_STATUS_R6 (SDIO_R6_COM_CRC_ERROR \ + | SDIO_R6_ILLEGAL_COMMAND | SDIO_R6_ERROR) + //! @} + + //! \name SDIO CMD52 argument bit offset + //! @{ +//! CMD52 arg[ 7: 0] Write data or stuff bits +#define SDIO_CMD52_WR_DATA 0 +//! CMD52 arg[ 8] Reserved +#define SDIO_CMD52_STUFF0 8 +//! CMD52 arg[25: 9] Register address +#define SDIO_CMD52_REG_ADRR 9 +//! CMD52 arg[ 26] Reserved +#define SDIO_CMD52_STUFF1 26 +//! CMD52 arg[ 27] Read after Write flag +#define SDIO_CMD52_RAW_FLAG 27 +//! CMD52 arg[30:28] Number of the function +#define SDIO_CMD52_FUNCTION_NUM 28 +//! CMD52 arg[ 31] Direction, 1:write, 0:read. +#define SDIO_CMD52_RW_FLAG 31 +# define SDIO_CMD52_READ_FLAG 0 +# define SDIO_CMD52_WRITE_FLAG 1 + //! @} + + //! \name SDIO CMD53 argument structure + //! @{ +/** + * [ 8: 0] Byte mode: number of bytes to transfer, + * 0 cause 512 bytes transfer. + * Block mode: number of blocks to transfer, + * 0 set count to infinite. + */ +#define SDIO_CMD53_COUNT 0 +//! CMD53 arg[25: 9] Start Address I/O register +#define SDIO_CMD53_REG_ADDR 9 +//! CMD53 arg[ 26] 1:Incrementing address, 0: fixed +#define SDIO_CMD53_OP_CODE 26 +//! CMD53 arg[ 27] (Optional) 1:block mode +#define SDIO_CMD53_BLOCK_MODE 27 +//! CMD53 arg[30:28] Number of the function +#define SDIO_CMD53_FUNCTION_NUM 28 +//! CMD53 arg[ 31] Direction, 1:WR, 0:RD +#define SDIO_CMD53_RW_FLAG 31 +# define SDIO_CMD53_READ_FLAG 0 +# define SDIO_CMD53_WRITE_FLAG 1 + //! @} + + //! \name SDIO Functions + //! @{ +#define SDIO_CIA 0 /**< SDIO Function 0 (CIA) */ +#define SDIO_FN0 0 /**< SDIO Function 0 */ +#define SDIO_FN1 1 /**< SDIO Function 1 */ +#define SDIO_FN2 2 /**< SDIO Function 2 */ +#define SDIO_FN3 3 /**< SDIO Function 3 */ +#define SDIO_FN4 4 /**< SDIO Function 4 */ +#define SDIO_FN5 5 /**< SDIO Function 5 */ +#define SDIO_FN6 6 /**< SDIO Function 6 */ +#define SDIO_FN7 7 /**< SDIO Function 7 */ + //! @} + + //! \name SDIO Card Common Control Registers (CCCR) + //! @{ +#define SDIO_CCCR_SDIO_REV 0x00 /**< CCCR/SDIO revision (RO) */ +#define SDIO_CCCR_REV_1_00 (0x0lu << 0) /**< CCCR/FBR Version 1.00 */ +#define SDIO_CCCR_REV_1_10 (0x1lu << 0) /**< CCCR/FBR Version 1.10 */ +#define SDIO_CCCR_REV_2_00 (0x2lu << 0) /**< CCCR/FBR Version 2.00 */ +#define SDIO_CCCR_REV_3_00 (0x3lu << 0) /**< CCCR/FBR Version 3.00 */ +#define SDIO_SDIO_REV_1_00 (0x0lu << 4) /**< SDIO Spec 1.00 */ +#define SDIO_SDIO_REV_1_10 (0x1lu << 4) /**< SDIO Spec 1.10 */ +#define SDIO_SDIO_REV_1_20 (0x2lu << 4) /**< SDIO Spec 1.20(unreleased) */ +#define SDIO_SDIO_REV_2_00 (0x3lu << 4) /**< SDIO Spec Version 2.00 */ +#define SDIO_SDIO_REV_3_00 (0x4lu << 4) /**< SDIO Spec Version 3.00 */ +#define SDIO_CCCR_SD_REV 0x01 /**< SD Spec Revision (RO) */ +#define SDIO_SD_REV_1_01 (0x0lu << 0) /**< SD 1.01 (Mar 2000) */ +#define SDIO_SD_REV_1_10 (0x1lu << 0) /**< SD 1.10 (Oct 2004) */ +#define SDIO_SD_REV_2_00 (0x2lu << 0) /**< SD 2.00 (May 2006) */ +#define SDIO_SD_REV_3_00 (0x3lu << 0) /**< SD 3.00 */ +#define SDIO_CCCR_IOE 0x02 /**< I/O Enable (R/W) */ +#define SDIO_IOE_FN1 (0x1lu << 1) /**< Function 1 Enable/Disable */ +#define SDIO_IOE_FN2 (0x1lu << 2) /**< Function 2 Enable/Disable */ +#define SDIO_IOE_FN3 (0x1lu << 3) /**< Function 3 Enable/Disable */ +#define SDIO_IOE_FN4 (0x1lu << 4) /**< Function 4 Enable/Disable */ +#define SDIO_IOE_FN5 (0x1lu << 5) /**< Function 5 Enable/Disable */ +#define SDIO_IOE_FN6 (0x1lu << 6) /**< Function 6 Enable/Disable */ +#define SDIO_IOE_FN7 (0x1lu << 7) /**< Function 7 Enable/Disable */ +#define SDIO_CCCR_IOR 0x03 /**< I/O Ready (RO) */ +#define SDIO_IOR_FN1 (0x1lu << 1) /**< Function 1 ready */ +#define SDIO_IOR_FN2 (0x1lu << 2) /**< Function 2 ready */ +#define SDIO_IOR_FN3 (0x1lu << 3) /**< Function 3 ready */ +#define SDIO_IOR_FN4 (0x1lu << 4) /**< Function 4 ready */ +#define SDIO_IOR_FN5 (0x1lu << 5) /**< Function 5 ready */ +#define SDIO_IOR_FN6 (0x1lu << 6) /**< Function 6 ready */ +#define SDIO_IOR_FN7 (0x1lu << 7) /**< Function 7 ready */ +#define SDIO_CCCR_IEN 0x04 /**< Int Enable */ +#define SDIO_IENM (0x1lu << 0) /**< Int Enable Master (R/W) */ +#define SDIO_IEN_FN1 (0x1lu << 1) /**< Function 1 Int Enable */ +#define SDIO_IEN_FN2 (0x1lu << 2) /**< Function 2 Int Enable */ +#define SDIO_IEN_FN3 (0x1lu << 3) /**< Function 3 Int Enable */ +#define SDIO_IEN_FN4 (0x1lu << 4) /**< Function 4 Int Enable */ +#define SDIO_IEN_FN5 (0x1lu << 5) /**< Function 5 Int Enable */ +#define SDIO_IEN_FN6 (0x1lu << 6) /**< Function 6 Int Enable */ +#define SDIO_IEN_FN7 (0x1lu << 7) /**< Function 7 Int Enable */ +#define SDIO_CCCR_INT 0x05 /**< Int Pending */ +#define SDIO_INT_FN1 (0x1lu << 1) /**< Function 1 Int pending */ +#define SDIO_INT_FN2 (0x1lu << 2) /**< Function 2 Int pending */ +#define SDIO_INT_FN3 (0x1lu << 3) /**< Function 3 Int pending */ +#define SDIO_INT_FN4 (0x1lu << 4) /**< Function 4 Int pending */ +#define SDIO_INT_FN5 (0x1lu << 5) /**< Function 5 Int pending */ +#define SDIO_INT_FN6 (0x1lu << 6) /**< Function 6 Int pending */ +#define SDIO_INT_FN7 (0x1lu << 7) /**< Function 7 Int pending */ +#define SDIO_CCCR_IOA 0x06 /**< I/O Abort */ +#define SDIO_AS_FN1 (0x1lu << 0) /**< Abort function 1 IO */ +#define SDIO_AS_FN2 (0x2lu << 0) /**< Abort function 2 IO */ +#define SDIO_AS_FN3 (0x3lu << 0) /**< Abort function 3 IO */ +#define SDIO_AS_FN4 (0x4lu << 0) /**< Abort function 4 IO */ +#define SDIO_AS_FN5 (0x5lu << 0) /**< Abort function 5 IO */ +#define SDIO_AS_FN6 (0x6lu << 0) /**< Abort function 6 IO */ +#define SDIO_AS_FN7 (0x7lu << 0) /**< Abort function 7 IO */ +#define SDIO_RES (0x1lu << 3) /**< IO CARD RESET (WO) */ +#define SDIO_CCCR_BUS_CTRL 0x07 /**< Bus Interface Control */ +#define SDIO_BUSWIDTH_1B (0x0lu << 0) /**< 1-bit data bus */ +#define SDIO_BUSWIDTH_4B (0x2lu << 0) /**< 4-bit data bus */ +/** Enable Continuous SPI interrupt (R/W) */ +#define SDIO_BUS_ECSI (0x1lu << 5) +/** Support Continuous SPI interrupt (RO) */ +#define SDIO_BUS_SCSI (0x1lu << 6) +/** Connect(0)/Disconnect(1) pull-up on CD/DAT[3] (R/W) */ +#define SDIO_BUS_CD_DISABLE (0x1lu << 7) +#define SDIO_CCCR_CAP 0x08 /**< Card Capability */ +/** Support Direct Commands during data transfer (RO) */ +#define SDIO_CAP_SDC (0x1lu << 0) +/** Support Multi-Block (RO) */ +#define SDIO_CAP_SMB (0x1lu << 1) +/** Support Read Wait (RO) */ +#define SDIO_CAP_SRW (0x1lu << 2) +/** Support Suspend/Resume (RO) */ +#define SDIO_CAP_SBS (0x1lu << 3) +/** Support interrupt between blocks of data in 4-bit SD mode (RO) */ +#define SDIO_CAP_S4MI (0x1lu << 4) +/** Enable interrupt between blocks of data in 4-bit SD mode (R/W) */ +#define SDIO_CAP_E4MI (0x1lu << 5) +/** Low-Speed Card (RO) */ +#define SDIO_CAP_LSC (0x1lu << 6) +/** 4-bit support for Low-Speed Card (RO) */ +#define SDIO_CAP_4BLS (0x1lu << 7) +/** Pointer to CIS (3B, LSB first) */ +#define SDIO_CCCR_CIS_PTR 0x09 +/** Bus Suspend */ +#define SDIO_CCCR_BUS_SUSPEND 0x0C +/** Bus Status (transfer on DAT[x] lines) (RO) */ +#define SDIO_BS (0x1lu << 0) +/** Bus Release Request/Status (R/W) */ +#define SDIO_BR (0x1lu << 1) +#define SDIO_CCCR_FUN_SEL 0x0D /**< Function select */ +#define SDIO_DF (0x1lu << 7) /**< Resume Data Flag (RO) */ +#define SDIO_FS_CIA (0x0lu << 0) /**< Select CIA (function 0) */ +#define SDIO_FS_FN1 (0x1lu << 0) /**< Select Function 1 */ +#define SDIO_FS_FN2 (0x2lu << 0) /**< Select Function 2 */ +#define SDIO_FS_FN3 (0x3lu << 0) /**< Select Function 3 */ +#define SDIO_FS_FN4 (0x4lu << 0) /**< Select Function 4 */ +#define SDIO_FS_FN5 (0x5lu << 0) /**< Select Function 5 */ +#define SDIO_FS_FN6 (0x6lu << 0) /**< Select Function 6 */ +#define SDIO_FS_FN7 (0x7lu << 0) /**< Select Function 7 */ +#define SDIO_FS_MEM (0x8lu << 0) /**< Select memory in combo card */ +#define SDIO_CCCR_EXEC 0x0E /**< Exec Flags (RO) */ +#define SDIO_EXM (0x1lu << 0) /**< Executing status of memory */ +#define SDIO_EX_FN1 (0x1lu << 1) /**< Executing status of func 1 */ +#define SDIO_EX_FN2 (0x1lu << 2) /**< Executing status of func 2 */ +#define SDIO_EX_FN3 (0x1lu << 3) /**< Executing status of func 3 */ +#define SDIO_EX_FN4 (0x1lu << 4) /**< Executing status of func 4 */ +#define SDIO_EX_FN5 (0x1lu << 5) /**< Executing status of func 5 */ +#define SDIO_EX_FN6 (0x1lu << 6) /**< Executing status of func 6 */ +#define SDIO_EX_FN7 (0x1lu << 7) /**< Executing status of func 7 */ +#define SDIO_CCCR_READY 0x0F /**< Ready Flags (RO) */ +#define SDIO_RFM (0x1lu << 0) /**< Ready Flag for memory */ +#define SDIO_RF_FN1 (0x1lu << 1) /**< Ready Flag for function 1 */ +#define SDIO_RF_FN2 (0x1lu << 2) /**< Ready Flag for function 2 */ +#define SDIO_RF_FN3 (0x1lu << 3) /**< Ready Flag for function 3 */ +#define SDIO_RF_FN4 (0x1lu << 4) /**< Ready Flag for function 4 */ +#define SDIO_RF_FN5 (0x1lu << 5) /**< Ready Flag for function 5 */ +#define SDIO_RF_FN6 (0x1lu << 6) /**< Ready Flag for function 6 */ +#define SDIO_RF_FN7 (0x1lu << 7) /**< Ready Flag for function 7 */ +#define SDIO_CCCR_FN0_BLKSIZ 0x10 /**< FN0 Block Size (2B, LSB first) (R/W) */ +#define SDIO_CCCR_POWER 0x12 /**< Power Control */ +#define SDIO_POWER_SMPC (0x1lu << 0) /**< Support Master Power Control*/ +#define SDIO_POWER_EMPC (0x1lu << 1) /**< Enable Master Power Control */ +#define SDIO_CCCR_HS 0x13 /**< High-Speed */ +#define SDIO_SHS (0x1lu << 0) /**< Support High-Speed (RO) */ +#define SDIO_EHS (0x1lu << 1) /**< Enable High-Speed (R/W) */ + //! @} + + //! \name SDIO Card Metaformat + //! @{ +/** Null tuple (PCMCIA 3.1.9) */ +#define SDIO_CISTPL_NULL 0x00 +/** Device tuple (PCMCIA 3.2.2) */ +#define SDIO_CISTPL_DEVICE 0x01 +/** Checksum control (PCMCIA 3.1.1) */ +#define SDIO_CISTPL_CHECKSUM 0x10 +/** Level 1 version (PCMCIA 3.2.10) */ +#define SDIO_CISTPL_VERS_1 0x15 +/** Alternate Language String (PCMCIA 3.2.1) */ +#define SDIO_CISTPL_ALTSTR 0x16 +/** Manufacturer Identification String (PCMCIA 3.2.9) */ +#define SDIO_CISTPL_MANFID 0x20 +/** Function Identification (PCMCIA 3.2.7) */ +#define SDIO_CISTPL_FUNCID 0x21 +/** Function Extensions (PCMCIA 3.2.6) */ +#define SDIO_CISTPL_FUNCE 0x22 +/** Additional information for SDIO (PCMCIA 6.1.2) */ +#define SDIO_CISTPL_SDIO_STD 0x91 +/** Reserved for future SDIO (PCMCIA 6.1.3) */ +#define SDIO_CISTPL_SDIO_EXT 0x92 +/** The End-of-chain Tuple (PCMCIA 3.1.2) */ +#define SDIO_CISTPL_END 0xFF + //! @} + +//! @} + +//! \name CSD, OCR, SCR, Switch status, extend CSD definitions +//! @{ + +/** + * \brief Macro function to extract a bits field from a large SD MMC register + * Used by : CSD, SCR, Switch status + */ +static inline uint32_t SDMMC_UNSTUFF_BITS(uint8_t *reg, uint16_t reg_size, + uint16_t pos, uint8_t size) +{ + uint32_t value; + value = reg[((reg_size - pos + 7) / 8) - 1] >> (pos % 8); + if (((pos % 8) + size) > 8) { + value |= (uint32_t)reg[((reg_size - pos + 7) / 8) - 2] << (8 - (pos % 8)); + } + if (((pos % 8) + size) > 16) { + value |= (uint32_t)reg[((reg_size - pos + 7) / 8) - 3] << (16 - (pos % 8)); + } + if (((pos % 8) + size) > 16) { + value |= (uint32_t)reg[((reg_size - pos + 7) / 8) - 3] << (16 - (pos % 8)); + } + value &= ((uint32_t)1 << size) - 1; + return value; +} + + //! \name CSD Fields + //! @{ +#define CSD_REG_BIT_SIZE 128 //!< 128 bits +#define CSD_REG_BSIZE (CSD_REG_BIT_SIZE / 8) //!< 16 bytes +#define CSD_STRUCTURE(csd, pos, size) \ + SDMMC_UNSTUFF_BITS(csd, CSD_REG_BIT_SIZE, pos, size) +#define CSD_STRUCTURE_VERSION(csd) CSD_STRUCTURE(csd, 126, 2) +#define SD_CSD_VER_1_0 0 +#define SD_CSD_VER_2_0 1 +#define MMC_CSD_VER_1_0 0 +#define MMC_CSD_VER_1_1 1 +#define MMC_CSD_VER_1_2 2 +#define CSD_TRAN_SPEED(csd) CSD_STRUCTURE(csd, 96, 8) +#define SD_CSD_1_0_C_SIZE(csd) CSD_STRUCTURE(csd, 62, 12) +#define SD_CSD_1_0_C_SIZE_MULT(csd) CSD_STRUCTURE(csd, 47, 3) +#define SD_CSD_1_0_READ_BL_LEN(csd) CSD_STRUCTURE(csd, 80, 4) +#define SD_CSD_2_0_C_SIZE(csd) CSD_STRUCTURE(csd, 48, 22) +#define MMC_CSD_C_SIZE(csd) CSD_STRUCTURE(csd, 62, 12) +#define MMC_CSD_C_SIZE_MULT(csd) CSD_STRUCTURE(csd, 47, 3) +#define MMC_CSD_READ_BL_LEN(csd) CSD_STRUCTURE(csd, 80, 4) +#define MMC_CSD_SPEC_VERS(csd) CSD_STRUCTURE(csd, 122, 4) + //! @} + + //! \name OCR Register Fields + //! @{ +#define OCR_REG_BSIZE (32 / 8) /**< 32 bits, 4 bytes */ +#define OCR_VDD_170_195 (1lu << 7) +#define OCR_VDD_20_21 (1lu << 8) +#define OCR_VDD_21_22 (1lu << 9) +#define OCR_VDD_22_23 (1lu << 10) +#define OCR_VDD_23_24 (1lu << 11) +#define OCR_VDD_24_25 (1lu << 12) +#define OCR_VDD_25_26 (1lu << 13) +#define OCR_VDD_26_27 (1lu << 14) +#define OCR_VDD_27_28 (1lu << 15) +#define OCR_VDD_28_29 (1lu << 16) +#define OCR_VDD_29_30 (1lu << 17) +#define OCR_VDD_30_31 (1lu << 18) +#define OCR_VDD_31_32 (1lu << 19) +#define OCR_VDD_32_33 (1lu << 20) +#define OCR_VDD_33_34 (1lu << 21) +#define OCR_VDD_34_35 (1lu << 22) +#define OCR_VDD_35_36 (1lu << 23) +#define OCR_SDIO_S18R (1lu << 24) /**< Switching to 1.8V Accepted */ +#define OCR_SDIO_MP (1lu << 27) /**< Memory Present */ +#define OCR_SDIO_NF (7lu << 28) /**< Number of I/O Functions */ +#define OCR_ACCESS_MODE_MASK (3lu << 29) /**< (MMC) Access mode mask */ +#define OCR_ACCESS_MODE_BYTE (0lu << 29) /**< (MMC) Byte access mode */ +#define OCR_ACCESS_MODE_SECTOR (2lu << 29) /**< (MMC) Sector access mode */ +#define OCR_CCS (1lu << 30) /**< (SD) Card Capacity Status */ +#define OCR_POWER_UP_BUSY (1lu << 31) /**< Card power up status bit */ + //! @} + + //! \name SD SCR Register Fields + //! @{ +#define SD_SCR_REG_BIT_SIZE 64 //!< 64 bits +#define SD_SCR_REG_BSIZE (SD_SCR_REG_BIT_SIZE / 8) //!< 8 bytes +#define SD_SCR_STRUCTURE(scr, pos, size) \ + SDMMC_UNSTUFF_BITS(scr, SD_SCR_REG_BIT_SIZE, pos, size) +#define SD_SCR_SCR_STRUCTURE(scr) SD_SCR_STRUCTURE(scr, 60, 4) +#define SD_SCR_SCR_STRUCTURE_1_0 0 +#define SD_SCR_SD_SPEC(scr) SD_SCR_STRUCTURE(scr, 56, 4) +#define SD_SCR_SD_SPEC_1_0_01 0 +#define SD_SCR_SD_SPEC_1_10 1 +#define SD_SCR_SD_SPEC_2_00 2 +#define SD_SCR_DATA_STATUS_AFTER_ERASE(scr) SD_SCR_STRUCTURE(scr, 55, 1) +#define SD_SCR_SD_SECURITY(scr) SD_SCR_STRUCTURE(scr, 52, 3) +#define SD_SCR_SD_SECURITY_NO 0 +#define SD_SCR_SD_SECURITY_NOTUSED 1 +#define SD_SCR_SD_SECURITY_1_01 2 +#define SD_SCR_SD_SECURITY_2_00 3 +#define SD_SCR_SD_SECURITY_3_00 4 +#define SD_SCR_SD_BUS_WIDTHS(scr) SD_SCR_STRUCTURE(scr, 48, 4) +#define SD_SCR_SD_BUS_WIDTH_1BITS (1lu << 0) +#define SD_SCR_SD_BUS_WIDTH_4BITS (1lu << 2) +#define SD_SCR_SD_SPEC3(scr) SD_SCR_STRUCTURE(scr, 47, 1) +#define SD_SCR_SD_SPEC_3_00 1 +#define SD_SCR_SD_EX_SECURITY(scr) SD_SCR_STRUCTURE(scr, 43, 4) +#define SD_SCR_SD_CMD_SUPPORT(scr) SD_SCR_STRUCTURE(scr, 32, 2) + //! @} + + //! \name SD Switch Status Fields + //! @{ +#define SD_SW_STATUS_BIT_SIZE 512 //!< 512 bits +#define SD_SW_STATUS_BSIZE (SD_SW_STATUS_BIT_SIZE / 8) //!< 64 bytes +#define SD_SW_STATUS_STRUCTURE(sd_sw_status, pos, size) \ + SDMMC_UNSTUFF_BITS(sd_sw_status, SD_SW_STATUS_BIT_SIZE, pos, size) +#define SD_SW_STATUS_MAX_CURRENT_CONSUMPTION(status) \ + SD_SW_STATUS_STRUCTURE(status, 496, 16) +#define SD_SW_STATUS_FUN_GRP6_INFO(status) \ + SD_SW_STATUS_STRUCTURE(status, 480, 16) +#define SD_SW_STATUS_FUN_GRP5_INFO(status) \ + SD_SW_STATUS_STRUCTURE(status, 464, 16) +#define SD_SW_STATUS_FUN_GRP4_INFO(status) \ + SD_SW_STATUS_STRUCTURE(status, 448, 16) +#define SD_SW_STATUS_FUN_GRP3_INFO(status) \ + SD_SW_STATUS_STRUCTURE(status, 432, 16) +#define SD_SW_STATUS_FUN_GRP2_INFO(status) \ + SD_SW_STATUS_STRUCTURE(status, 416, 16) +#define SD_SW_STATUS_FUN_GRP1_INFO(status) \ + SD_SW_STATUS_STRUCTURE(status, 400, 16) +#define SD_SW_STATUS_FUN_GRP6_RC(status) \ + SD_SW_STATUS_STRUCTURE(status, 396, 4) +#define SD_SW_STATUS_FUN_GRP5_RC(status) \ + SD_SW_STATUS_STRUCTURE(status, 392, 4) +#define SD_SW_STATUS_FUN_GRP4_RC(status) \ + SD_SW_STATUS_STRUCTURE(status, 388, 4) +#define SD_SW_STATUS_FUN_GRP3_RC(status) \ + SD_SW_STATUS_STRUCTURE(status, 384, 4) +#define SD_SW_STATUS_FUN_GRP2_RC(status) \ + SD_SW_STATUS_STRUCTURE(status, 380, 4) +#define SD_SW_STATUS_FUN_GRP1_RC(status) \ + SD_SW_STATUS_STRUCTURE(status, 376, 4) +#define SD_SW_STATUS_FUN_GRP_RC_ERROR 0xFU +#define SD_SW_STATUS_DATA_STRUCT_VER(status) \ + SD_SW_STATUS_STRUCTURE(status, 368, 8) +#define SD_SW_STATUS_FUN_GRP6_BUSY(status) \ + SD_SW_STATUS_STRUCTURE(status, 352, 16) +#define SD_SW_STATUS_FUN_GRP5_BUSY(status) \ + SD_SW_STATUS_STRUCTURE(status, 336, 16) +#define SD_SW_STATUS_FUN_GRP4_BUSY(status) \ + SD_SW_STATUS_STRUCTURE(status, 320, 16) +#define SD_SW_STATUS_FUN_GRP3_BUSY(status) \ + SD_SW_STATUS_STRUCTURE(status, 304, 16) +#define SD_SW_STATUS_FUN_GRP2_BUSY(status) \ + SD_SW_STATUS_STRUCTURE(status, 288, 16) +#define SD_SW_STATUS_FUN_GRP1_BUSY(status) \ + SD_SW_STATUS_STRUCTURE(status, 272, 16) + //! @} + + //! \name Card Status Fields + //! @{ +#define CARD_STATUS_APP_CMD (1lu << 5) +#define CARD_STATUS_SWITCH_ERROR (1lu << 7) +#define CARD_STATUS_READY_FOR_DATA (1lu << 8) +#define CARD_STATUS_STATE_IDLE (0lu << 9) +#define CARD_STATUS_STATE_READY (1lu << 9) +#define CARD_STATUS_STATE_IDENT (2lu << 9) +#define CARD_STATUS_STATE_STBY (3lu << 9) +#define CARD_STATUS_STATE_TRAN (4lu << 9) +#define CARD_STATUS_STATE_DATA (5lu << 9) +#define CARD_STATUS_STATE_RCV (6lu << 9) +#define CARD_STATUS_STATE_PRG (7lu << 9) +#define CARD_STATUS_STATE_DIS (8lu << 9) +#define CARD_STATUS_STATE (0xFlu << 9) +#define CARD_STATUS_ERASE_RESET (1lu << 13) +#define CARD_STATUS_WP_ERASE_SKIP (1lu << 15) +#define CARD_STATUS_CIDCSD_OVERWRITE (1lu << 16) +#define CARD_STATUS_OVERRUN (1lu << 17) +#define CARD_STATUS_UNERRUN (1lu << 18) +#define CARD_STATUS_ERROR (1lu << 19) +#define CARD_STATUS_CC_ERROR (1lu << 20) +#define CARD_STATUS_CARD_ECC_FAILED (1lu << 21) +#define CARD_STATUS_ILLEGAL_COMMAND (1lu << 22) +#define CARD_STATUS_COM_CRC_ERROR (1lu << 23) +#define CARD_STATUS_UNLOCK_FAILED (1lu << 24) +#define CARD_STATUS_CARD_IS_LOCKED (1lu << 25) +#define CARD_STATUS_WP_VIOLATION (1lu << 26) +#define CARD_STATUS_ERASE_PARAM (1lu << 27) +#define CARD_STATUS_ERASE_SEQ_ERROR (1lu << 28) +#define CARD_STATUS_BLOCK_LEN_ERROR (1lu << 29) +#define CARD_STATUS_ADDRESS_MISALIGN (1lu << 30) +#define CARD_STATUS_ADDR_OUT_OF_RANGE (1lu << 31) + +#define CARD_STATUS_ERR_RD_WR (CARD_STATUS_ADDR_OUT_OF_RANGE \ + | CARD_STATUS_ADDRESS_MISALIGN \ + | CARD_STATUS_BLOCK_LEN_ERROR \ + | CARD_STATUS_WP_VIOLATION \ + | CARD_STATUS_ILLEGAL_COMMAND \ + | CARD_STATUS_CC_ERROR \ + | CARD_STATUS_ERROR) + //! @} + + //! \name SD Status Field + //! @{ +#define SD_STATUS_BSIZE (512 / 8) /**< 512 bits, 64bytes */ + //! @} + + //! \name MMC Extended CSD Register Field + //! @{ +#define EXT_CSD_BSIZE 512 /**< 512 bytes. */ +/* Below belongs to Properties Segment */ +#define EXT_CSD_S_CMD_SET_INDEX 504lu +#define EXT_CSD_BOOT_INFO_INDEX 228lu +#define EXT_CSD_BOOT_SIZE_MULTI_INDEX 226lu +#define EXT_CSD_ACC_SIZE_INDEX 225lu +#define EXT_CSD_HC_ERASE_GRP_SIZE_INDEX 224lu +#define EXT_CSD_ERASE_TIMEOUT_MULT_INDEX 223lu +#define EXT_CSD_REL_WR_SEC_C_INDEX 222lu +#define EXT_CSD_HC_WP_GRP_SIZE_INDEX 221lu +#define EXT_CSD_S_C_VCC_INDEX 220lu +#define EXT_CSD_S_C_VCCQ_INDEX 219lu +#define EXT_CSD_S_A_TIMEOUT_INDEX 217lu +#define EXT_CSD_SEC_COUNT_INDEX 212lu +#define EXT_CSD_MIN_PERF_W_8_52_INDEX 210lu +#define EXT_CSD_MIN_PERF_R_8_52_INDEX 209lu +#define EXT_CSD_MIN_PERF_W_8_26_4_52_INDEX 208lu +#define EXT_CSD_MIN_PERF_R_8_26_4_52_INDEX 207lu +#define EXT_CSD_MIN_PERF_W_4_26_INDEX 206lu +#define EXT_CSD_MIN_PERF_R_4_26_INDEX 205lu +#define EXT_CSD_PWR_CL_26_360_INDEX 203lu +#define EXT_CSD_PWR_CL_52_360_INDEX 202lu +#define EXT_CSD_PWR_CL_26_195_INDEX 201lu +#define EXT_CSD_PWR_CL_52_195_INDEX 200lu +#define EXT_CSD_CARD_TYPE_INDEX 196lu +/* MMC card type */ +# define MMC_CTYPE_26MHZ 0x1 +# define MMC_CTYPE_52MHZ 0x2 +#define EXT_CSD_CSD_STRUCTURE_INDEX 194lu +#define EXT_CSD_EXT_CSD_REV_INDEX 192lu + +/* Below belongs to Mode Segment */ +#define EXT_CSD_CMD_SET_INDEX 191lu +#define EXT_CSD_CMD_SET_REV_INDEX 189lu +#define EXT_CSD_POWER_CLASS_INDEX 187lu +#define EXT_CSD_HS_TIMING_INDEX 185lu +#define EXT_CSD_BUS_WIDTH_INDEX 183lu +#define EXT_CSD_ERASED_MEM_CONT_INDEX 181lu +#define EXT_CSD_BOOT_CONFIG_INDEX 179lu +#define EXT_CSD_BOOT_BUS_WIDTH_INDEX 177lu +#define EXT_CSD_ERASE_GROUP_DEF_INDEX 175lu + //! @} +//! @} + + +//! \name Definition for SPI mode only +//! @{ + +//! SPI commands start with a start bit "0" and a transmit bit "1" +#define SPI_CMD_ENCODE(x) (0x40 | (x & 0x3F)) + +//! \name Register R1 definition for SPI mode +//! The R1 register is always send after a command. +//! @{ +#define R1_SPI_IDLE (1lu << 0) +#define R1_SPI_ERASE_RESET (1lu << 1) +#define R1_SPI_ILLEGAL_COMMAND (1lu << 2) +#define R1_SPI_COM_CRC (1lu << 3) +#define R1_SPI_ERASE_SEQ (1lu << 4) +#define R1_SPI_ADDRESS (1lu << 5) +#define R1_SPI_PARAMETER (1lu << 6) +// R1 bit 7 is always zero, reuse this bit for error +#define R1_SPI_ERROR (1lu << 7) +//! @} + +//! \name Register R2 definition for SPI mode +//! The R2 register can be send after R1 register. +//! @{ +#define R2_SPI_CARD_LOCKED (1lu << 0) +#define R2_SPI_WP_ERASE_SKIP (1lu << 1) +#define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP +#define R2_SPI_ERROR (1lu << 2) +#define R2_SPI_CC_ERROR (1lu << 3) +#define R2_SPI_CARD_ECC_ERROR (1lu << 4) +#define R2_SPI_WP_VIOLATION (1lu << 5) +#define R2_SPI_ERASE_PARAM (1lu << 6) +#define R2_SPI_OUT_OF_RANGE (1lu << 7) +#define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE +//! @} + +//! \name Control Tokens in SPI Mode +//! @{ + //! \name Tokens used for a read operation + //! @{ +#define SPI_TOKEN_SINGLE_MULTI_READ 0xFE +#define SPI_TOKEN_DATA_ERROR_VALID(token) (((token) & 0xF0) == 0) +#define SPI_TOKEN_DATA_ERROR_ERRORS (0x0F) +#define SPI_TOKEN_DATA_ERROR_ERROR (1lu << 0) +#define SPI_TOKEN_DATA_ERROR_CC_ERROR (1lu << 1) +#define SPI_TOKEN_DATA_ERROR_ECC_ERROR (1lu << 2) +#define SPI_TOKEN_DATA_ERROR_OUT_RANGE (1lu << 3) + //! @} + //! \name Tokens used for a write operation + //! @{ +#define SPI_TOKEN_SINGLE_WRITE 0xFE +#define SPI_TOKEN_MULTI_WRITE 0xFC +#define SPI_TOKEN_STOP_TRAN 0xFD +#define SPI_TOKEN_DATA_RESP_VALID(token) \ + ((((token) & (1 << 4)) == 0) && (((token) & (1 << 0)) == 1)) +#define SPI_TOKEN_DATA_RESP_CODE(token) ((token) & 0x1E) +#define SPI_TOKEN_DATA_RESP_ACCEPTED (2lu << 1) +#define SPI_TOKEN_DATA_RESP_CRC_ERR (5lu << 1) +#define SPI_TOKEN_DATA_RESP_WRITE_ERR (6lu << 1) + //! @} +//! @} +//! @} + + +//! @} end of sd_mmc_protocol + +#ifdef __cplusplus +} +#endif + +#endif /* SD_MMC_PROTOCOL_H_INCLUDED */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/WINC3400_IoT_SW_APIs.chm b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/WINC3400_IoT_SW_APIs.chm new file mode 100644 index 000000000..1cc90f788 Binary files /dev/null and b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/WINC3400_IoT_SW_APIs.chm differ diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/bsp/include/nm_bsp.h b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/bsp/include/nm_bsp.h new file mode 100644 index 000000000..9649f1928 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/bsp/include/nm_bsp.h @@ -0,0 +1,246 @@ +/** + * + * \file + * + * \brief This module contains WINC3400 BSP APIs declarations. + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +/**@defgroup nm_bsp BSP + */ + +/**@defgroup BSPDefine Defines + * @ingroup nm_bsp + * @{ + */ +#ifndef _NM_BSP_H_ +#define _NM_BSP_H_ + +#define NMI_API +/*!< +* Attribute used to define memory section to map Functions in host memory. +*/ +#define CONST const + +#ifndef NULL +#define NULL ((void*)0) +#endif +/*!< +* Void Pointer to '0' in case of NULL is not defined. +*/ + + +#define BSP_MIN(x,y) ((x)>(y)?(y):(x)) +/*!< +* Computes the minimum of \b x and \b y. +*/ + + //@} + +/**@defgroup DataT Enumeration/Typedefs + * @ingroup nm_bsp + * @{ + */ + + /*! +* Used for code portability. +*/ + +/*! + * @typedef void (*tpfNmBspIsr) (void); + * @brief Pointer to function.\n + * Used as a data type of ISR function registered by \ref nm_bsp_register_isr + * @return None + */ +typedef void (*tpfNmBspIsr)(void); + + /*! + * @ingroup DataTypes + * @typedef unsigned char uint8; + * @brief Range of values between 0 to 255 + */ +typedef unsigned char uint8; + + /*! + * @ingroup DataTypes + * @typedef unsigned short uint16; + * @brief Range of values between 0 to 65535 + */ +typedef unsigned short uint16; + + /*! + * @ingroup Data Types + * @typedef unsigned long uint32; + * @brief Range of values between 0 to 4294967295 + */ +typedef unsigned long uint32; + + + /*! + * @ingroup Data Types + * @typedef signed char sint8; + * @brief Range of values between -128 to 127 + */ +typedef signed char sint8; + + /*! + * @ingroup DataTypes + * @typedef signed short sint16; + * @brief Range of values between -32768 to 32767 + */ +typedef signed short sint16; + + /*! + * @ingroup DataTypes + * @typedef signed long sint32; + * @brief Range of values between -2147483648 to 2147483647 + */ + +typedef signed long sint32; + //@} + +#ifndef CORTUS_APP + + +#ifdef __cplusplus +extern "C"{ +#endif + +/** \defgroup BSPAPI Functions + * @ingroup nm_bsp + * @{ + */ + +/*! + * @fn sint8 nm_bsp_init(void); + * Initialization for BSP such as Reset and Chip Enable Pins for WINC, delays, register ISR, enable/disable IRQ for WINC, ...etc. You must use this function in the head of your application to + * enable WINC and Host Driver to communicate with each other. + * @note Implementation of this function is host dependent. + * @warning Omission will lead to unavailability of host communication.\n + * + * @return The function returns @ref M2M_SUCCESS for successful operations and a negative value otherwise. + + */ +sint8 nm_bsp_init(void); +/*! + * @fn sint8 nm_bsp_deinit(void); + * De-initialization for BSP (\e Board \e Support \e Package) + * @pre Initialize \ref nm_bsp_init first + * @note Implementation of this function is host dependent. + * @warning Omission may lead to unknown behavior in case of soft reset.\n + * @see nm_bsp_init + * @return The function returns @ref M2M_SUCCESS for successful operations and a negative value otherwise. + + */ +sint8 nm_bsp_deinit(void); + /*! + * @fn void nm_bsp_reset(void); + * Resetting NMC1500 SoC by setting CHIP_EN and RESET_N signals low, then after specific delay the function will put CHIP_EN high then RESET_N high, + * for the timing between signals please review the WINC data-sheet + * @pre Initialize \ref nm_bsp_init first + * @note Implementation of this function is host dependent and called by HIF layer. + * @see nm_bsp_init + * @return None + + */ +void nm_bsp_reset(void); +/*! + * @fn void nm_bsp_sleep(uint32); + * Sleep in units of milliseconds.\n + * This function is used by HIF Layer as required in various situations. + * @brief + * @param [in] u32TimeMsec + * Time unit in milliseconds + * @pre Initialize \ref nm_bsp_init first + * @warning Maximum value must nor exceed 4294967295 milliseconds which is equal to 4294967.295 seconds.\n + * @note Implementation of this function is host dependent. + * @see nm_bsp_init + * @return None + */ +void nm_bsp_sleep(uint32 u32TimeMsec); +/*! + * @fn void nm_bsp_register_isr(tpfNmBspIsr); + * Register ISR (Interrupt Service Routine) in the initialization of HIF (Host Interface) Layer. + * When the interrupt trigger the BSP layer should call the pfisr function once inside the interrupt. + * @param [in] pfIsr + * Pointer to ISR handler in HIF + * @warning Make sure that ISR for IRQ pin for WINC is disabled by default in your implementation. + * @note Implementation of this function is host dependent and called by HIF layer. + * @see tpfNmBspIsr + * @return None + + */ +void nm_bsp_register_isr(tpfNmBspIsr pfIsr); +/*! + * @fn void nm_bsp_interrupt_ctrl(uint8); + * Synchronous enable/disable interrupts function + * @brief Enable/Disable interrupts + * @param [in] u8Enable + * '0' disable interrupts. '1' enable interrupts + * @see tpfNmBspIsr + * @note Implementation of this function is host dependent and called by HIF layer. + * @return None + + */ +void nm_bsp_interrupt_ctrl(uint8 u8Enable); + /**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif + +/** + * @addtogroup BSPDefine + * @{ + */ + +#ifdef _NM_BSP_BIG_END +/*! Switch endianness of 32bit word (In the case that Host is BE) */ +#define NM_BSP_B_L_32(x) \ +((((x) & 0x000000FF) << 24) + \ +(((x) & 0x0000FF00) << 8) + \ +(((x) & 0x00FF0000) >> 8) + \ +(((x) & 0xFF000000) >> 24)) +/*! Switch endianness of 16bit word (In the case that Host is BE) */ +#define NM_BSP_B_L_16(x) \ +((((x) & 0x00FF) << 8) + \ +(((x) & 0xFF00) >> 8)) +#else +/*! Retain endianness of 32bit word (In the case that Host is LE) */ +#define NM_BSP_B_L_32(x) (x) +/*! Retain endianness of 16bit word (In the case that Host is LE) */ +#define NM_BSP_B_L_16(x) (x) +#endif + +/**@} + */ + +#endif /*_NM_BSP_H_*/ diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/bsp/include/nm_bsp_internal.h b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/bsp/include/nm_bsp_internal.h new file mode 100644 index 000000000..aa7692bee --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/bsp/include/nm_bsp_internal.h @@ -0,0 +1,100 @@ +/** + * + * \file + * + * \brief This module contains WINC3400 BSP APIs declarations. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/**@defgroup BSPDefine Defines + * @ingroup nm_bsp + * @{ + */ +#ifndef _NM_BSP_INTERNAL_H_ +#define _NM_BSP_INTERNAL_H_ + + + +#ifdef WIN32 +#include "nm_bsp_win32.h" +#endif + +#ifdef __K20D50M__ +#include "nm_bsp_k20d50m.h" +#endif + +#ifdef __MSP430FR5739__ +#include "bsp_msp430fr5739.h" +#endif + +#ifdef _FREESCALE_MCF51CN128_ +#include "bsp/include/nm_bsp_mcf51cn128.h" +#endif + +#ifdef __MCF964548__ +#include "bsp/include/nm_bsp_mc96f4548.h" +#endif + +#ifdef __APP_APS3_CORTUS__ +#include "nm_bsp_aps3_cortus.h" +#endif + +#if (defined __SAMD21J18A__) || (defined __SAMD21G18A__) +#include "bsp/include/nm_bsp_samd21.h" +#endif + +#if (defined __SAM4S16C__) || (defined __SAM4SD32C__) +#include "bsp/include/nm_bsp_sam4s.h" +#endif + +#ifdef __SAMG55J19__ +#include "bsp/include/nm_bsp_samg55.h" +#endif + +#ifdef __SAMG53N19__ +#include "bsp/include/nm_bsp_samg53.h" +#endif + +#if (defined __SAME70Q21__) || (defined __SAME70Q20B__) || (defined __SAME70Q21B__) +#include "bsp/include/nm_bsp_same70.h" +#endif + +#ifdef CORTUS_APP +#include "crt_iface.h" +#endif + +#ifdef NRF51 +#include "nm_bsp_nrf51822.h" +#endif + +#ifdef _ARDUINO_UNO_ +#include "bsp/include/nm_bsp_arduino_uno.h" +#endif + + +#endif //_NM_BSP_INTERNAL_H_ \ No newline at end of file diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/bsp/include/nm_bsp_same70.h b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/bsp/include/nm_bsp_same70.h new file mode 100644 index 000000000..5ec80987c --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/bsp/include/nm_bsp_same70.h @@ -0,0 +1,45 @@ +/** + * + * \file + * + * \brief This module contains SAME70 BSP APIs declarations. + * + * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _NM_BSP_SAME70_H_ +#define _NM_BSP_SAME70_H_ + +#include "conf_winc.h" + +#define NM_EDGE_INTERRUPT (1) + +#define NM_DEBUG CONF_WINC_DEBUG +#define NM_BSP_PRINTF CONF_WINC_PRINTF + +#endif /* _NM_BSP_SAME70_H_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/bsp/source/nm_bsp_same70.c b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/bsp/source/nm_bsp_same70.c new file mode 100644 index 000000000..54d0c3e18 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/bsp/source/nm_bsp_same70.c @@ -0,0 +1,164 @@ +/** + * + * \file + * + * \brief This module contains SAME70 BSP APIs implementation. + * + * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "bsp/include/nm_bsp.h" +#include "common/include/nm_common.h" +#include "asf.h" +#include "conf_winc.h" + +static tpfNmBspIsr gpfIsr; + +static void chip_isr(uint32_t id, uint32_t mask) +{ + if ((id == CONF_WINC_SPI_INT_PIO_ID) && (mask == CONF_WINC_SPI_INT_MASK)) { + if (gpfIsr) { + gpfIsr(); + } + } +} + +/* + * @fn init_chip_pins + * @brief Initialize reset, chip enable and wake pin + */ +static void init_chip_pins(void) +{ + ioport_init(); + ioport_set_pin_dir(CONF_WINC_PIN_RESET, IOPORT_DIR_OUTPUT); + ioport_set_pin_level(CONF_WINC_PIN_RESET, IOPORT_PIN_LEVEL_HIGH); + ioport_set_pin_dir(CONF_WINC_PIN_CHIP_ENABLE, IOPORT_DIR_OUTPUT); + ioport_set_pin_level(CONF_WINC_PIN_CHIP_ENABLE, IOPORT_PIN_LEVEL_HIGH); + ioport_set_pin_dir(CONF_WINC_PIN_WAKE, IOPORT_DIR_OUTPUT); + ioport_set_pin_level(CONF_WINC_PIN_WAKE, IOPORT_PIN_LEVEL_HIGH); +} + +/* +* @fn nm_bsp_init +* @brief Initialize BSP +* @return 0 in case of success and -1 in case of failure +*/ +sint8 nm_bsp_init(void) +{ + gpfIsr = NULL; + + /* Initialize chip IOs. */ + init_chip_pins(); + + /* Perform chip reset. */ + nm_bsp_reset(); + + return 0; +} + +/** +* @fn nm_bsp_deinit +* @brief De-iInitialize BSP +* @return 0 in case of success and -1 in case of failure +*/ +sint8 nm_bsp_deinit(void) +{ + ioport_set_pin_level(CONF_WINC_PIN_CHIP_ENABLE, IOPORT_PIN_LEVEL_LOW); + ioport_set_pin_level(CONF_WINC_PIN_RESET, IOPORT_PIN_LEVEL_LOW); + return M2M_SUCCESS; +} + +/** + * @fn nm_bsp_reset + * @brief Reset WINC1500 SoC by setting CHIP_EN and RESET_N signals low, + * CHIP_EN high then RESET_N high + */ +void nm_bsp_reset(void) +{ + ioport_set_pin_level(CONF_WINC_PIN_CHIP_ENABLE, IOPORT_PIN_LEVEL_LOW); + ioport_set_pin_level(CONF_WINC_PIN_RESET, IOPORT_PIN_LEVEL_LOW); + nm_bsp_sleep(1); + ioport_set_pin_level(CONF_WINC_PIN_CHIP_ENABLE, IOPORT_PIN_LEVEL_HIGH); + nm_bsp_sleep(10); + ioport_set_pin_level(CONF_WINC_PIN_RESET, IOPORT_PIN_LEVEL_HIGH); +} + +/* +* @fn nm_bsp_sleep +* @brief Sleep in units of mSec +* @param[IN] u32TimeMsec +* Time in milliseconds +*/ +void nm_bsp_sleep(uint32 u32TimeMsec) +{ + while(u32TimeMsec--) { + delay_ms(4); + } +} + +/* +* @fn nm_bsp_register_isr +* @brief Register interrupt service routine +* @param[IN] pfIsr +* Pointer to ISR handler +*/ +void nm_bsp_register_isr(tpfNmBspIsr pfIsr) +{ + gpfIsr = pfIsr; + + /* Configure PGIO pin for interrupt from SPI slave, used when slave has data to send. */ + pmc_enable_periph_clk(CONF_WINC_SPI_INT_PIO_ID); + pio_configure_pin(CONF_WINC_SPI_INT_PIN, PIO_TYPE_PIO_INPUT); + pio_pull_up(CONF_WINC_SPI_INT_PIO, CONF_WINC_SPI_INT_MASK, PIO_PULLUP); + /*Interrupt on falling edge*/ + pio_handler_set(CONF_WINC_SPI_INT_PIO, CONF_WINC_SPI_INT_PIO_ID, + CONF_WINC_SPI_INT_MASK, PIO_PULLUP | PIO_IT_FALL_EDGE, chip_isr); + pio_get_interrupt_status(CONF_WINC_SPI_INT_PIO); + pio_enable_interrupt(CONF_WINC_SPI_INT_PIO, CONF_WINC_SPI_INT_MASK); + NVIC_EnableIRQ((IRQn_Type) CONF_WINC_SPI_INT_PIO_ID); + pio_handler_set_priority(CONF_WINC_SPI_INT_PIO, (IRQn_Type)CONF_WINC_SPI_INT_PIO_ID, + CONF_WINC_SPI_INT_PRIORITY); +} + +/* +* @fn nm_bsp_interrupt_ctrl +* @brief Enable/Disable interrupts +* @param[IN] u8Enable +* '0' disable interrupts. '1' enable interrupts +*/ +void nm_bsp_interrupt_ctrl(uint8 u8Enable) +{ + if (u8Enable) { + pio_get_interrupt_status(CONF_WINC_SPI_INT_PIO); + pio_enable_interrupt(CONF_WINC_SPI_INT_PIO, CONF_WINC_SPI_INT_MASK); + } + else { + pio_disable_interrupt(CONF_WINC_SPI_INT_PIO, CONF_WINC_SPI_INT_MASK); + } +} + diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/bus_wrapper/include/nm_bus_wrapper.h b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/bus_wrapper/include/nm_bus_wrapper.h new file mode 100644 index 000000000..6c680e4d3 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/bus_wrapper/include/nm_bus_wrapper.h @@ -0,0 +1,189 @@ +/** + * + * \file + * + * \brief This module contains WINC3400 bus wrapper APIs declarations. + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _NM_BUS_WRAPPER_H_ +#define _NM_BUS_WRAPPER_H_ + +#include "common/include/nm_common.h" + +/** + BUS Type +**/ +#define NM_BUS_TYPE_I2C ((uint8)0) +#define NM_BUS_TYPE_SPI ((uint8)1) +#define NM_BUS_TYPE_UART ((uint8)2) +/** + IOCTL commands +**/ +#define NM_BUS_IOCTL_R ((uint8)0) /*!< Read only ==> I2C/UART. Parameter:tstrNmI2cDefault/tstrNmUartDefault */ +#define NM_BUS_IOCTL_W ((uint8)1) /*!< Write only ==> I2C/UART. Parameter type tstrNmI2cDefault/tstrNmUartDefault*/ +#define NM_BUS_IOCTL_W_SPECIAL ((uint8)2) /*!< Write two buffers within the same transaction + (same start/stop conditions) ==> I2C only. Parameter:tstrNmI2cSpecial */ +#define NM_BUS_IOCTL_RW ((uint8)3) /*!< Read/Write at the same time ==> SPI only. Parameter:tstrNmSpiRw */ + +#define NM_BUS_IOCTL_WR_RESTART ((uint8)4) /*!< Write buffer then made restart condition then read ==> I2C only. parameter:tstrNmI2cSpecial */ +/** +* @struct tstrNmBusCapabilities +* @brief Structure holding bus capabilities information +* @sa NM_BUS_TYPE_I2C, NM_BUS_TYPE_SPI +*/ +typedef struct +{ + uint16 u16MaxTrxSz; /*!< Maximum transfer size. Must be >= 16 bytes*/ +} tstrNmBusCapabilities; + +/** +* @struct tstrNmI2cDefault +* @brief Structure holding I2C default operation parameters +* @sa NM_BUS_IOCTL_R, NM_BUS_IOCTL_W +*/ +typedef struct +{ + uint8 u8SlaveAdr; + uint8 *pu8Buf; /*!< Operation buffer */ + uint16 u16Sz; /*!< Operation size */ +} tstrNmI2cDefault; + +/** +* @struct tstrNmI2cSpecial +* @brief Structure holding I2C special operation parameters +* @sa NM_BUS_IOCTL_W_SPECIAL +*/ +typedef struct +{ + uint8 u8SlaveAdr; + uint8 *pu8Buf1; /*!< pointer to the 1st buffer */ + uint8 *pu8Buf2; /*!< pointer to the 2nd buffer */ + uint16 u16Sz1; /*!< 1st buffer size */ + uint16 u16Sz2; /*!< 2nd buffer size */ +} tstrNmI2cSpecial; + +/** +* @struct tstrNmSpiRw +* @brief Structure holding SPI R/W parameters +* @sa NM_BUS_IOCTL_RW +*/ +typedef struct +{ + uint8 *pu8InBuf; /*!< pointer to input buffer. + Can be set to null and in this case zeros should be sent at MOSI */ + uint8 *pu8OutBuf; /*!< pointer to output buffer. + Can be set to null and in this case data from MISO can be ignored */ + uint16 u16Sz; /*!< Transfere size */ +} tstrNmSpiRw; + + +/** +* @struct tstrNmUartDefault +* @brief Structure holding UART default operation parameters +* @sa NM_BUS_IOCTL_R, NM_BUS_IOCTL_W +*/ +typedef struct +{ + uint8 *pu8Buf; /*!< Operation buffer */ + uint16 u16Sz; /*!< Operation size */ +} tstrNmUartDefault; +/*!< Bus capabilities. This structure must be declared at platform specific bus wrapper */ +extern tstrNmBusCapabilities egstrNmBusCapabilities; + + +#ifdef __cplusplus + extern "C" { + #endif +/** +* @fn nm_bus_init +* @brief Initialize the bus wrapper +* @param [in] req_com_port +* Used to choose com port assigned to device like edbg +* @param [in] req_serial_number +* Used to choose peripheral, eg if 2 aardvark's are connected to pc. +* Pass 0 to select first/only or if using UART. +* @return ZERO in case of success and M2M_ERR_BUS_FAIL in case of failure +*/ +sint8 nm_bus_init(uint8 *req_com_port, uint32 req_serial_number); + +/** +* @fn nm_bus_ioctl +* @brief send/receive from the bus +* @param [in] u8Cmd +* IOCTL command for the operation +* @param [in] pvParameter +* Arbitrary parameter depending on IOCTL +* @return ZERO in case of success and M2M_ERR_BUS_FAIL in case of failure +* @note For SPI only, it's important to be able to send/receive at the same time +*/ +sint8 nm_bus_ioctl(uint8 u8Cmd, void* pvParameter); + +/** +* @fn nm_bus_deinit +* @brief De-initialize the bus wrapper +* @return ZERO in case of success and M2M_ERR_BUS_FAIL in case of failure +*/ +sint8 nm_bus_deinit(void); + +/* +* @fn nm_bus_reinit +* @brief re-initialize the bus wrapper +* @param [in] void *config +* re-init configuration data +* @return ZERO in case of success and M2M_ERR_BUS_FAIL in case of failure +*/ +sint8 nm_bus_reinit(void *); +/* +* @fn nm_bus_get_chip_type +* @brief get chip type +* @return ZERO in case of success and M2M_ERR_BUS_FAIL in case of failure +*/ +#ifdef CONF_WINC_USE_UART +uint8 nm_bus_get_chip_type(void); +uint8 nm_bus_get_sb_type(void); +#endif + +/* +* @fn spi_rw +* @brief Process SPI Read/Write operation +* @param pu8Mosi TX Data buffer +* @param pu8Miso RX Data buffer +* @param u16Sz Transfer length +* @return ZERO in case of success and M2M_ERR_BUS_FAIL in case of failure +*/ +#ifdef CONF_WINC_USE_SPI +sint8 nm_spi_rw(uint8* pu8Mosi, uint8* pu8Miso, uint16 u16Sz); +#endif + +#ifdef __cplusplus + } + #endif + +#endif /*_NM_BUS_WRAPPER_H_*/ diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/bus_wrapper/source/nm_bus_wrapper_same70.c b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/bus_wrapper/source/nm_bus_wrapper_same70.c new file mode 100644 index 000000000..441acfd57 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/bus_wrapper/source/nm_bus_wrapper_same70.c @@ -0,0 +1,341 @@ +/** + * + * \file + * + * \brief This module contains NMC1000 bus wrapper APIs implementation. + * + * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include "bsp/include/nm_bsp.h" +#include "common/include/nm_common.h" +#include "bus_wrapper/include/nm_bus_wrapper.h" +#include "asf.h" +#include "conf_winc.h" + +#define xSPI_ASSERT_CS() {gpio_set_pin_low(CONF_WINC_SPI_CS_GPIO);} +#define xSPI_DEASSERT_CS() {gpio_set_pin_high(CONF_WINC_SPI_CS_GPIO);} + +#define SPI_ASSERT_CS() do {p_pio->PIO_CODR = 1 << (CONF_WINC_SPI_CS_GPIO & 0x1F);}while(0) +#define SPI_DEASSERT_CS() do {p_pio->PIO_SODR = 1 << (CONF_WINC_SPI_CS_GPIO & 0x1F);}while(0) + + +#define NM_BUS_MAX_TRX_SZ 4096 + +tstrNmBusCapabilities egstrNmBusCapabilities = +{ + NM_BUS_MAX_TRX_SZ +}; + +#ifdef CONF_WINC_USE_I2C +#define SLAVE_ADDRESS 0x60 + +/** Number of times to try to send packet if failed. */ +#define I2C_TIMEOUT 100 + +static sint8 nm_i2c_write(uint8 *b, uint16 sz) +{ + sint8 result = M2M_ERR_BUS_FAIL; + return result; +} + +static sint8 nm_i2c_read(uint8 *rb, uint16 sz) +{ + sint8 result = M2M_ERR_BUS_FAIL; + return result; +} + +static sint8 nm_i2c_write_special(uint8 *wb1, uint16 sz1, uint8 *wb2, uint16 sz2) +{ + static uint8 tmp[NM_BUS_MAX_TRX_SZ]; + m2m_memcpy(tmp, wb1, sz1); + m2m_memcpy(&tmp[sz1], wb2, sz2); + return nm_i2c_write(tmp, sz1+sz2); +} +#endif + +#ifdef CONF_WINC_USE_SPI +/** PIO instance used by CS. */ +Pio *p_pio_cs; + +/** Fast CS macro. */ +#undef SPI_ASSERT_CS +#define SPI_ASSERT_CS() do {p_pio_cs->PIO_CODR = 1 << (CONF_WINC_SPI_CS_GPIO & 0x1F);} while(0) +#undef SPI_DEASSERT_CS +#define SPI_DEASSERT_CS() do {p_pio_cs->PIO_SODR = 1 << (CONF_WINC_SPI_CS_GPIO & 0x1F);} while(0) + +static sint8 spi_rw(uint8 *pu8Mosi, uint8 *pu8Miso, uint16 u16Sz) +{ +#ifdef DMA_SPI + pdc_packet_t pdc_spi_tx_packet,pdc_spi_rx_packet; + + p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (CONF_WINC_SPI_CS_GPIO >> 5))); + + pdc_spi_tx_packet.ul_addr = NULL; + pdc_spi_rx_packet.ul_addr = NULL; + pdc_spi_tx_packet.ul_size = u16Sz; + pdc_spi_rx_packet.ul_size = u16Sz; + + if (pu8Mosi) { + pdc_spi_tx_packet.ul_addr = (uint32_t)pu8Mosi; + } + + if(pu8Miso) { + pdc_spi_rx_packet.ul_addr = (uint32_t)pu8Miso; + } + + pdc_tx_init(g_p_spim_pdc, &pdc_spi_tx_packet, NULL); + pdc_rx_init(g_p_spim_pdc, &pdc_spi_rx_packet, NULL); + + /*Assert CS*/ + SPI_ASSERT_CS(); + /* Enable the RX and TX PDC transfer requests */ + g_p_spim_pdc->PERIPH_PTCR = PERIPH_PTCR_RXTEN|PERIPH_PTCR_TXTEN; + + /* Waiting transfer done*/ + while((CONF_WINC_SPI->SPI_SR & SPI_SR_RXBUFF) == 0); + + /*DEASSERT CS*/ + SPI_DEASSERT_CS(); + + /* Disable the RX and TX PDC transfer requests */ + g_p_spim_pdc->PERIPH_PTCR = PERIPH_PTCR_TXTDIS|PERIPH_PTCR_RXTDIS; + + + return M2M_SUCCESS; + +#elif (defined LOW_DELAY) + + +uint8 u8Dummy = 0; +uint8 u8SkipMosi = 0, u8SkipMiso = 0; + +p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (CONF_WINC_SPI_CS_GPIO >> 5))); + +if (!pu8Mosi) { + pu8Mosi = &u8Dummy; + u8SkipMosi = 1; +} +else if(!pu8Miso) { + /*RX must be zero*/ + pu8Miso = &u8Dummy; + u8SkipMiso = 1; +} +else { + return M2M_ERR_BUS_FAIL; +} + +/*TX path*/ +if(!u8SkipMosi) +{ + SPI_ASSERT_CS(); + while (u16Sz--) + { + CONF_WINC_SPI->SPI_TDR = SPI_TDR_TD((uint16)*pu8Mosi); + while (!(CONF_WINC_SPI->SPI_SR & SPI_SR_TDRE)); + pu8Mosi++; + } + SPI_DEASSERT_CS(); +} +/*RX path*/ +if(!u8SkipMiso) +{ + SPI_ASSERT_CS(); + while (u16Sz--) + { + + CONF_WINC_SPI->SPI_TDR = SPI_TDR_TD((uint16)*pu8Mosi); + while (!(CONF_WINC_SPI->SPI_SR & SPI_SR_TDRE)); + while (!(CONF_WINC_SPI->SPI_SR & (SPI_SR_RDRF))); + *pu8Miso = (uint16_t) ((CONF_WINC_SPI->SPI_RDR) & SPI_RDR_RD_Msk); + pu8Miso++; + } + SPI_DEASSERT_CS(); +} +return M2M_SUCCESS; + +#else + uint8 u8Dummy = 0; + uint8 u8SkipMosi = 0, u8SkipMiso = 0; + uint16_t txd_data = 0; + uint16_t rxd_data = 0; + uint8_t uc_pcs; + + if (!pu8Mosi) { + pu8Mosi = &u8Dummy; + u8SkipMosi = 1; + } + else if(!pu8Miso) { + pu8Miso = &u8Dummy; + u8SkipMiso = 1; + } + else { + return M2M_ERR_BUS_FAIL; + } + SPI_ASSERT_CS(); + while (u16Sz) { + txd_data = *pu8Mosi; + + spi_write(CONF_WINC_SPI, txd_data, 0, 0); + spi_read(CONF_WINC_SPI, &rxd_data, &uc_pcs); + + *pu8Miso = rxd_data; + + u16Sz--; + if (!u8SkipMiso) + pu8Miso++; + if (!u8SkipMosi) + pu8Mosi++; + } + SPI_DEASSERT_CS(); + + return M2M_SUCCESS; + #endif + +} +#endif + +/* +* @fn nm_bus_init +* @brief Initialize the bus wrapper +* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure +*/ +sint8 nm_bus_init(uint8_t *pvinit, uint32 req_serial_number) +{ + sint8 result = M2M_SUCCESS; +#ifdef CONF_WINC_USE_I2C + +#elif defined CONF_WINC_USE_SPI + /* Configure SPI pins. */ + ioport_set_pin_mode(CONF_WINC_SPI_MISO_GPIO, CONF_WINC_SPI_MISO_FLAGS); + ioport_set_pin_mode(CONF_WINC_SPI_MOSI_GPIO, CONF_WINC_SPI_MOSI_FLAGS); + ioport_set_pin_mode(CONF_WINC_SPI_CLK_GPIO, CONF_WINC_SPI_CLK_FLAGS); + ioport_set_pin_mode(CONF_WINC_SPI_CS_GPIO, CONF_WINC_SPI_CS_FLAGS); + ioport_disable_pin(CONF_WINC_SPI_MISO_GPIO); + ioport_disable_pin(CONF_WINC_SPI_MOSI_GPIO); + ioport_disable_pin(CONF_WINC_SPI_CLK_GPIO); + + /* Configure CS for manual (GPIO) control. */ + p_pio_cs = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (CONF_WINC_SPI_CS_GPIO >> 5))); + SPI_DEASSERT_CS(); + ioport_set_pin_dir(CONF_WINC_SPI_CS_GPIO, IOPORT_DIR_OUTPUT); + ioport_enable_pin(CONF_WINC_SPI_CS_GPIO); + + spi_enable_clock(CONF_WINC_SPI); + spi_disable(CONF_WINC_SPI); + spi_reset(CONF_WINC_SPI); + spi_set_master_mode(CONF_WINC_SPI); + spi_disable_mode_fault_detect(CONF_WINC_SPI); + spi_set_peripheral_chip_select_value(CONF_WINC_SPI, CONF_WINC_SPI_NPCS); + spi_set_clock_polarity(CONF_WINC_SPI, + CONF_WINC_SPI_NPCS, CONF_WINC_SPI_POL); + + spi_set_clock_phase(CONF_WINC_SPI, CONF_WINC_SPI_NPCS, CONF_WINC_SPI_PHA); + + spi_set_bits_per_transfer(CONF_WINC_SPI, CONF_WINC_SPI_NPCS, SPI_CSR_BITS_8_BIT); + + //printf("sys clk %d\r\n",sysclk_get_cpu_hz()); + spi_set_baudrate_div(CONF_WINC_SPI, CONF_WINC_SPI_NPCS, + (sysclk_get_peripheral_hz() / CONF_WINC_SPI_CLOCK)); + spi_set_transfer_delay(CONF_WINC_SPI, CONF_WINC_SPI_NPCS, CONF_WINC_SPI_DLYBS, + CONF_WINC_SPI_DLYBCT); + spi_enable(CONF_WINC_SPI); + + nm_bsp_reset(); +#endif + return result; +} + +/* +* @fn nm_bus_ioctl +* @brief send/receive from the bus +* @param[IN] u8Cmd +* IOCTL command for the operation +* @param[IN] pvParameter +* Arbitrary parameter depenging on IOCTL +* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure +* @note For SPI only, it's important to be able to send/receive at the same time +*/ +sint8 nm_bus_ioctl(uint8 u8Cmd, void* pvParameter) +{ + sint8 s8Ret = 0; + switch(u8Cmd) + { +#ifdef CONF_WINC_USE_I2C + case NM_BUS_IOCTL_R: { + tstrNmI2cDefault *pstrParam = (tstrNmI2cDefault *)pvParameter; + s8Ret = nm_i2c_read(pstrParam->pu8Buf, pstrParam->u16Sz); + } + break; + case NM_BUS_IOCTL_W: { + tstrNmI2cDefault *pstrParam = (tstrNmI2cDefault *)pvParameter; + s8Ret = nm_i2c_write(pstrParam->pu8Buf, pstrParam->u16Sz); + } + break; + case NM_BUS_IOCTL_W_SPECIAL: { + tstrNmI2cSpecial *pstrParam = (tstrNmI2cSpecial *)pvParameter; + s8Ret = nm_i2c_write_special(pstrParam->pu8Buf1, pstrParam->u16Sz1, pstrParam->pu8Buf2, pstrParam->u16Sz2); + } + break; +#elif defined CONF_WINC_USE_SPI + case NM_BUS_IOCTL_RW: { + tstrNmSpiRw *pstrParam = (tstrNmSpiRw *)pvParameter; + s8Ret = spi_rw(pstrParam->pu8InBuf, pstrParam->pu8OutBuf, pstrParam->u16Sz); + } + break; +#endif + default: + s8Ret = -1; + M2M_ERR("invalide ioclt cmd\n"); + break; + } + + return s8Ret; +} + +/* +* @fn nm_bus_deinit +* @brief De-initialize the bus wrapper +*/ +sint8 nm_bus_deinit(void) +{ + sint8 result = M2M_SUCCESS; + +#ifdef CONF_WINC_USE_I2C + //TODO: +#endif /* CONF_WINC_USE_I2C */ +#ifdef CONF_WINC_USE_SPI + spi_disable(CONF_WINC_SPI); + ioport_set_pin_dir(CONF_WINC_SPI_MOSI_GPIO, IOPORT_DIR_INPUT); + ioport_set_pin_dir(CONF_WINC_SPI_MISO_GPIO, IOPORT_DIR_INPUT); + ioport_set_pin_dir(CONF_WINC_SPI_CLK_GPIO, IOPORT_DIR_INPUT); + ioport_set_pin_dir(CONF_WINC_SPI_CS_GPIO, IOPORT_DIR_INPUT); +#endif /* CONF_WINC_USE_SPI */ + return result; +} diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/common/include/nm_common.h b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/common/include/nm_common.h new file mode 100644 index 000000000..cd3bf547b --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/common/include/nm_common.h @@ -0,0 +1,242 @@ +/** + * + * \file + * + * \brief This module contains common APIs declarations. + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +/**@defgroup COMMON COMMON +*/ + +#ifndef _NM_COMMON_H_ +#define _NM_COMMON_H_ + +#include "bsp/include/nm_bsp.h" +#include "common/include/nm_debug.h" + +/**@defgroup COMMONDEF Defines + * @ingroup COMMON + */ +/**@{*/ +#define M2M_TIME_OUT_DELAY 10000 + +/*states*/ +#define M2M_SUCCESS ((sint8)0) +#define M2M_ERR_SEND ((sint8)-1) +#define M2M_ERR_RCV ((sint8)-2) +#define M2M_ERR_MEM_ALLOC ((sint8)-3) +#define M2M_ERR_TIME_OUT ((sint8)-4) +#define M2M_ERR_INIT ((sint8)-5) +#define M2M_ERR_BUS_FAIL ((sint8)-6) +#define M2M_NOT_YET ((sint8)-7) +#define M2M_ERR_FIRMWARE ((sint8)-8) +#define M2M_SPI_FAIL ((sint8)-9) +#define M2M_ERR_FIRMWARE_bURN ((sint8)-10) +#define M2M_ACK ((sint8)-11) +#define M2M_ERR_FAIL ((sint8)-12) +#define M2M_ERR_FW_VER_MISMATCH ((sint8)-13) +#define M2M_ERR_SCAN_IN_PROGRESS ((sint8)-14) +/* +Invalid argument +*/ +#define M2M_ERR_INVALID_ARG ((sint8)-15) + +/*i2c MAASTER ERR*/ +#define I2C_ERR_LARGE_ADDRESS 0xE1UL /*!< the address exceed the max addressing mode in i2c flash*/ +#define I2C_ERR_TX_ABRT 0xE2UL /*!< NO ACK from slave*/ +#define I2C_ERR_OVER_SIZE 0xE3UL /**/ +#define ERR_PREFIX_NMIS 0xE4UL /*!< wrong first four byte in flash NMIS*/ +#define ERR_FIRMEWARE_EXCEED_SIZE 0xE5UL /*!< Total size of firmware exceed the max size 256k*/ +/**/ +#define PROGRAM_START 0x26961735UL +#define BOOT_SUCCESS 0x10add09eUL +#define BOOT_START 0x12345678UL + + +#define NBIT31 (0x80000000) +#define NBIT30 (0x40000000) +#define NBIT29 (0x20000000) +#define NBIT28 (0x10000000) +#define NBIT27 (0x08000000) +#define NBIT26 (0x04000000) +#define NBIT25 (0x02000000) +#define NBIT24 (0x01000000) +#define NBIT23 (0x00800000) +#define NBIT22 (0x00400000) +#define NBIT21 (0x00200000) +#define NBIT20 (0x00100000) +#define NBIT19 (0x00080000) +#define NBIT18 (0x00040000) +#define NBIT17 (0x00020000) +#define NBIT16 (0x00010000) +#define NBIT15 (0x00008000) +#define NBIT14 (0x00004000) +#define NBIT13 (0x00002000) +#define NBIT12 (0x00001000) +#define NBIT11 (0x00000800) +#define NBIT10 (0x00000400) +#define NBIT9 (0x00000200) +#define NBIT8 (0x00000100) +#define NBIT7 (0x00000080) +#define NBIT6 (0x00000040) +#define NBIT5 (0x00000020) +#define NBIT4 (0x00000010) +#define NBIT3 (0x00000008) +#define NBIT2 (0x00000004) +#define NBIT1 (0x00000002) +#define NBIT0 (0x00000001) + +/*! Maximum of two values */ +#define M2M_MAX(A,B) ((A) > (B) ? (A) : (B)) +/*! Choose one of three values */ +#define M2M_SEL(x,m1,m2,m3) ((x>1)?((x>2)?(m3):(m2)):(m1)) +/*! Align to next multiple of 4 */ +#define WORD_ALIGN(val) (((val) & 0x03) ? ((val) + 4 - ((val) & 0x03)) : (val)) + + + +#define DATA_PKT_OFFSET 4 + +#ifndef BIG_ENDIAN +/*! Most significant byte of 32bit word (LE) */ +#define BYTE_0(word) ((uint8)(((word) >> 0 ) & 0x000000FFUL)) +/*! Second most significant byte of 32bit word (LE) */ +#define BYTE_1(word) ((uint8)(((word) >> 8 ) & 0x000000FFUL)) +/*! Third most significant byte of 32bit word (LE) */ +#define BYTE_2(word) ((uint8)(((word) >> 16) & 0x000000FFUL)) +/*! Least significant byte of 32bit word (LE) */ +#define BYTE_3(word) ((uint8)(((word) >> 24) & 0x000000FFUL)) +#else +/*! Most significant byte of 32bit word (BE) */ +#define BYTE_0(word) ((uint8)(((word) >> 24) & 0x000000FFUL)) +/*! Second most significant byte of 32bit word (BE) */ +#define BYTE_1(word) ((uint8)(((word) >> 16) & 0x000000FFUL)) +/*! Third most significant byte of 32bit word (BE) */ +#define BYTE_2(word) ((uint8)(((word) >> 8 ) & 0x000000FFUL)) +/*! Least significant byte of 32bit word (BE) */ +#define BYTE_3(word) ((uint8)(((word) >> 0 ) & 0x000000FFUL)) +#endif +/**@}*/ + +#ifdef __cplusplus + extern "C" { + #endif +/**@defgroup COMMONAPI Functions + * @ingroup COMMON + */ +/**@{*/ + +/*! + * @fn void m2m_memcpy(uint8* pDst,uint8* pSrc,uint32 sz); + * @brief Copy specified number of bytes from source buffer to destination buffer + * @param [in] sz + * number of data bytes to copy + * @param [in] pSrc + * source buffer + * @param [out] pDst + * destination buffer +* @return None + */ +NMI_API void m2m_memcpy(uint8* pDst,uint8* pSrc,uint32 sz); +/*! + * @fn void m2m_memset(uint8* pBuf,uint8 val,uint32 sz); + * @brief Set specified number of data bytes in specified data buffer to specified value + * @param [in] sz + * number of data bytes (in specified data buffer whose values are to be set to the specified value) + * @param [in] val + * the specified value (to which data bytes in data buffer will be set) + * @param [out] pBuf + * the specified data buffer (whose data bytes will be set to the specified value) + * @return None + */ +NMI_API void m2m_memset(uint8* pBuf,uint8 val,uint32 sz); +/*! + * @fn uint16 m2m_strlen(uint8 * pcStr); + * @brief Returns the string length of a null terminated string buffer + * @param [in] pcStr + * null terminated string buffer + * @return length of the string in the specified string buffer + */ +NMI_API uint16 m2m_strlen(uint8 * pcStr); +/*! + * @fn sint8 m2m_memcmp(uint8 *pu8Buff1,uint8 *pu8Buff2 ,uint32 u32Size); + * @brief Compare specified number of data bytes in pu8Buff1 and pu8Buff2 and decide if they all match. + * @param [in] u32Size + * number of data bytes to compare + * @param [in] pu8Buff1 + * one of two data buffers for the comparison + * @param [in] pu8Buff2 + * one of two data buffers for the comparison + * @return zero if matched, one if not matched + */ +NMI_API sint8 m2m_memcmp(uint8 *pu8Buff1,uint8 *pu8Buff2 ,uint32 u32Size); +/*! + * @fn uint8 m2m_strncmp(uint8 *pcS1, uint8 *pcS2, uint16 u16Len); + * @brief Compare specified number of data bytes in string buffers pcS1 and pcS2 + * @param [in] u16Len + * Number of data bytes to compare + * @param [in] pcS1 + * first of two string buffers for the comparison + * @param [in] pcS2 + * second of two string buffers for the comparison + * @return 0 if matched, -1 if the first non-matching byte in pcS1 is smaller than that in pcS2, +1 if it is bigger + */ +NMI_API uint8 m2m_strncmp(uint8 *pcS1, uint8 *pcS2, uint16 u16Len); +/*! + * @fn uint8 * m2m_strstr(uint8 *pcIn, uint8 *pcStr); + * @brief Find the occurrence of pcStr string in pcIn string + * @param [in] pcStr + * one of two string buffers + * @param [in] pcIn + * one of two string buffers + * @return If pcStr string is part of pcIn string return a valid pointer to the start of pcStr within pcIn. If not a NULL Pointer is returned + */ +NMI_API uint8 * m2m_strstr(uint8 *pcIn, uint8 *pcStr); +/*! + * @fn uint8 m2m_checksum(uint8* buf, int sz); + * @brief calculates checksum for the specified number of data bytes in specified data buffer + * @param [in] sz + * number of data bytes used in the checksum calculation + * @param [in] buf + * the specified data buffer (whose data bytes will be used to calculate the checksum) + * @return the calculated checksum + */ +NMI_API uint8 m2m_checksum(uint8* buf, int sz); + +/*! + * @fn void (*at_sb_printf)(const char *_format, ...); + * @brief chooses which function to use in order to output debug + */ +// NMI_API void (*at_sb_printf)(const char *_format, ...); +/**@}*/ +#ifdef __cplusplus +} + #endif +#endif /*_NM_COMMON_H_*/ diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/common/include/nm_debug.h b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/common/include/nm_debug.h new file mode 100644 index 000000000..45a47b3bb --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/common/include/nm_debug.h @@ -0,0 +1,111 @@ +/** + * + * \file + * + * \brief This module contains debug APIs declarations. + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _NM_DEBUG_H_ +#define _NM_DEBUG_H_ + +#include "bsp/include/nm_bsp.h" +#include "bsp/include/nm_bsp_internal.h" + +#define M2M_LOG_NONE 0 +#define M2M_LOG_ERROR 1 +#define M2M_LOG_INFO 2 +#define M2M_LOG_REQ 3 +#define M2M_LOG_DBG 4 + +#if (defined __APP_APS3_CORTUS__) +#define M2M_LOG_LEVEL M2M_LOG_ERROR +#else +#define M2M_LOG_LEVEL M2M_LOG_REQ +#endif + +/**/ +#if !((defined __MSP430FR5739)||(defined __MCF964548__)) + +#define M2M_ERR(...) +#define M2M_INFO(...) +#define M2M_REQ(...) +#define M2M_DBG(...) + +#if (CONF_WINC_DEBUG == 1) +#define M2M_PRINT(...) do{CONF_WINC_PRINTF(__VA_ARGS__);}while(0) +#if (M2M_LOG_LEVEL >= M2M_LOG_ERROR) +#undef M2M_ERR +#define M2M_ERR(...) do{CONF_WINC_PRINTF("(APP)(ERR)[%s][%d]",__FUNCTION__,__LINE__); CONF_WINC_PRINTF(__VA_ARGS__);CONF_WINC_PRINTF("\r");}while(0) +#if (M2M_LOG_LEVEL >= M2M_LOG_INFO) +#undef M2M_INFO +#define M2M_INFO(...) do{CONF_WINC_PRINTF("(APP)(INFO)"); CONF_WINC_PRINTF(__VA_ARGS__);CONF_WINC_PRINTF("\r");}while(0) +#if (M2M_LOG_LEVEL >= M2M_LOG_REQ) +#undef M2M_REQ +#define M2M_REQ(...) do{CONF_WINC_PRINTF("(APP)(R)"); CONF_WINC_PRINTF(__VA_ARGS__);CONF_WINC_PRINTF("\r");}while(0) +#if (M2M_LOG_LEVEL >= M2M_LOG_DBG) +#undef M2M_DBG +#define M2M_DBG(...) do{CONF_WINC_PRINTF("(APP)(DBG)[%s][%d]",__FUNCTION__,__LINE__); CONF_WINC_PRINTF(__VA_ARGS__);CONF_WINC_PRINTF("\r");}while(0) +#endif +#endif +#endif +#endif +#else +#define M2M_ERR(...) +#define M2M_DBG(...) +#define M2M_REQ(...) +#define M2M_INFO(...) +#define M2M_PRINT(...) +#endif +#else +#if (!defined __MCF964548__)||(!defined __SAMD21J18A__) +static void M2M_ERR(const char *_format, ...) //__attribute__ ((__format__ (M2M_ERR, 1, 2))) +{ +} +static void M2M_DBG(const char *_format, ...) //__attribute__ ((__format__ (M2M_DBG, 1, 2))) +{ +} +static void M2M_REQ(const char *_format, ...) //__attribute__ ((__format__ (M2M_DBG, 1, 2))) +{ +} +static void M2M_INFO(const char *_format, ...) // __attribute__ ((__format__ (M2M_INFO, 1, 2))) +{ + +} +static void M2M_PRINT(const char *_format, ...) // __attribute__ ((__format__ (M2M_INFO, 1, 2))) +{ + +} +static void CONF_WINC_PRINTF(const char *_format, ...) +{ +} +#endif +#endif + +#endif /* _NM_DEBUG_H_ */ \ No newline at end of file diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/common/source/nm_common.c b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/common/source/nm_common.c new file mode 100644 index 000000000..6c3e99f47 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/common/source/nm_common.c @@ -0,0 +1,129 @@ +/** + * + * \file + * + * \brief This module contains common APIs declarations. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include "common/include/nm_common.h" + +void m2m_memcpy(uint8* pDst,uint8* pSrc,uint32 sz) +{ + if(sz == 0) return; + do + { + *pDst = *pSrc; + pDst++; + pSrc++; + }while(--sz); +} +uint8 m2m_checksum(uint8* buf, int sz) +{ + uint8 cs = 0; + while(--sz) + { + cs ^= *buf; + buf++; + } + + return cs; +} + +void m2m_memset(uint8* pBuf,uint8 val,uint32 sz) +{ + if(sz == 0) return; + do + { + *pBuf = val; + pBuf++; + }while(--sz); +} + +uint16 m2m_strlen(uint8 * pcStr) +{ + uint16 u16StrLen = 0; + while(*pcStr) + { + u16StrLen ++; + pcStr++; + } + return u16StrLen; +} + +uint8 m2m_strncmp(uint8 *pcS1, uint8 *pcS2, uint16 u16Len) +{ + for ( ; u16Len > 0; pcS1++, pcS2++, --u16Len) + if (*pcS1 != *pcS2) + return ((*(uint8 *)pcS1 < *(uint8 *)pcS2) ? -1 : +1); + else if (*pcS1 == '\0') + return 0; + return 0; +} + +/* Finds the occurance of pcStr in pcIn. +If pcStr is part of pcIn it returns a valid pointer to the start of pcStr within pcIn. +Otherwise a NULL Pointer is returned. +*/ +uint8 * m2m_strstr(uint8 *pcIn, uint8 *pcStr) +{ + uint8 u8c; + uint16 u16StrLen; + + u8c = *pcStr++; + if (!u8c) + return (uint8 *) pcIn; // Trivial empty string case + + u16StrLen = m2m_strlen(pcStr); + do { + uint8 u8Sc; + + do { + u8Sc = *pcIn++; + if (!u8Sc) + return (uint8 *) 0; + } while (u8Sc != u8c); + } while (m2m_strncmp(pcIn, pcStr, u16StrLen) != 0); + + return (uint8 *) (pcIn - 1); +} + +sint8 m2m_memcmp(uint8 *pu8Buff1,uint8 *pu8Buff2 ,uint32 u32Size) +{ + uint32 i; + sint8 s8Result = 0; + for(i = 0 ; i < u32Size ; i++) + { + if(pu8Buff1[i] != pu8Buff2[i]) + { + s8Result = 1; + break; + } + } + return s8Result; +} diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/include/m2m_ate_mode.h b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/include/m2m_ate_mode.h new file mode 100644 index 000000000..a68e14d77 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/include/m2m_ate_mode.h @@ -0,0 +1,580 @@ +/** + * + * \file + * + * \brief WINC3400 Peripherals Application Interface. + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _M2M_ATE_FW_ + +#ifndef _M2M_ATE_MODE_H_ +#define _M2M_ATE_MODE_H_ + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +INCLUDES +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ +#include "common/include/nm_common.h" +#include "driver/include/m2m_types.h" + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +MACROS +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ +#define M2M_ATE_MAX_NUM_OF_RATES (20) +/*!< Maximum number of all rates (b,g and n) + */ +#define M2M_ATE_MAX_FRAME_LENGTH (1024) +/*!< Maximum number of length for each frame + */ +#define M2M_ATE_MIN_FRAME_LENGTH (1) +/*!< Minimum number of length for each frame + */ + + +#define M2M_ATE_SUCCESS (M2M_SUCCESS) +/*!< No Error and operation has been completed successfully. +*/ +#define M2M_ATE_ERR_VALIDATE (M2M_ERR_FAIL) +/*!< Error in parameters passed to functions. + */ +#define M2M_ATE_ERR_TX_ALREADY_RUNNING (-1) +/*!< This means that TX case is already running and RX or even TX can't start without stopping it first. + */ +#define M2M_ATE_ERR_RX_ALREADY_RUNNING (-2) +/*!< This means that RX case is already running and TX or even RX can't start without stopping it first. + */ +#define M2M_ATE_ERR_UNHANDLED_CASE (-3) +/*!< Invalid case. + */ +#define M2M_ATE_RX_DISABLE_DA 0x0 +#define M2M_ATE_RX_ENABLE_DA 0x1 + +#define M2M_ATE_RX_DISABLE_SA 0x0 +#define M2M_ATE_RX_ENABLE_SA 0x1 + +#define M2M_ATE_DISABLE_SELF_MACADDR 0x0 +#define M2M_ATE_SET_SELF_MACADDR 0x1 +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +DATA TYPES +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ +/*! + *@enum tenuM2mAteFwState + *@brief Enumeration used for change ATE firmware state + */ +typedef enum { + M2M_ATE_FW_STATE_STOP = 0x00, + /*!< State to stop ATE firmware + */ + M2M_ATE_FW_STATE_RUN = 0x01, + /*!< State to run ATE firmware + */ +}tenuM2mAteFwState; + +/*! + *@enum tenuM2mAteTxRates + *@brief Used to get value of rate referenced by this index + */ +typedef enum { + M2M_ATE_TX_RATE_1_Mbps_INDEX = 0x00, + M2M_ATE_TX_RATE_2_Mbps_INDEX = 0x01, + M2M_ATE_TX_RATE_55_Mbps_INDEX = 0x02, + M2M_ATE_TX_RATE_11_Mbps_INDEX = 0x03, + /*!< B-Rates + */ + M2M_ATE_TX_RATE_6_Mbps_INDEX = 0x04, + M2M_ATE_TX_RATE_9_Mbps_INDEX = 0x05, + M2M_ATE_TX_RATE_12_Mbps_INDEX = 0x06, + M2M_ATE_TX_RATE_18_Mbps_INDEX = 0x07, + M2M_ATE_TX_RATE_24_Mbps_INDEX = 0x08, + M2M_ATE_TX_RATE_36_Mbps_INDEX = 0x09, + M2M_ATE_TX_RATE_48_Mbps_INDEX = 0x0A, + M2M_ATE_TX_RATE_54_Mbps_INDEX = 0x0B, + /*!< G-Rates + */ + M2M_ATE_TX_RATE_MCS_0_INDEX = 0x0C, + M2M_ATE_TX_RATE_MCS_1_INDEX = 0x0D, + M2M_ATE_TX_RATE_MCS_2_INDEX = 0x0E, + M2M_ATE_TX_RATE_MCS_3_INDEX = 0x0F, + M2M_ATE_TX_RATE_MCS_4_INDEX = 0x10, + M2M_ATE_TX_RATE_MCS_5_INDEX = 0x11, + M2M_ATE_TX_RATE_MCS_6_INDEX = 0x12, + M2M_ATE_TX_RATE_MCS_7_INDEX = 0x13, + /*!< N-Rates + */ +}tenuM2mAteTxIndexOfRates; + +/*! + *@enum tenuM2mAteTxDutyCycle + *@brief Values of duty cycle + */ +typedef enum { + M2M_ATE_TX_DUTY_1 = 0x01, + M2M_ATE_TX_DUTY_2 = 0x02, + M2M_ATE_TX_DUTY_3 = 0x03, + M2M_ATE_TX_DUTY_4 = 0x04, + M2M_ATE_TX_DUTY_5 = 0x05, + M2M_ATE_TX_DUTY_6 = 0x06, + M2M_ATE_TX_DUTY_7 = 0x07, + M2M_ATE_TX_DUTY_8 = 0x08, + M2M_ATE_TX_DUTY_9 = 0x09, + M2M_ATE_TX_DUTY_10 = 0xA0, +}tenuM2mAteTxDutyCycle; + + +#define M2M_ATE_TX_DUTY_MAX_VALUE M2M_ATE_TX_DUTY_1 +/*!< The maximum value of duty cycle +*/ +#define M2M_ATE_TX_DUTY_MIN_VALUE M2M_ATE_TX_DUTY_10 +/*!< The minimum value of duty cycle +*/ + +/*! + *@enum tenuM2mAteTxDpdControl + *@brief Allowed values for DPD control + */ +typedef enum { + M2M_ATE_TX_DPD_DYNAMIC = 0x00, + M2M_ATE_TX_DPD_BYPASS = 0x01, + M2M_ATE_TX_DPD_ENABLED = 0x02, +}tenuM2mAteTxDpdControl; + +/*! + *@enum tenuM2mAteTxGainSetting + *@brief Options for TX gain selection mode + */ +typedef enum { + M2M_ATE_TX_GAIN_DYNAMIC = 0x00, + M2M_ATE_TX_GAIN_BYPASS = 0x01, + M2M_ATE_TX_GAIN_FCC = 0x02, + M2M_ATE_TX_GAIN_TELEC = 0x03, +}tenuM2mAteTxGainSetting; + +/*! + *@enum tenuM2mAtePMUSetting + *@brief Used to Enable PMU or disable it + */ +typedef enum { + M2M_ATE_PMU_DISBLE = 0x00, + M2M_ATE_PMU_ENABLE = 0x01, +}tenuM2mAtePMUSetting; + +/*! + *@enum tenuM2mAteTxSource + *@brief Used to define if enable PHY continues mode or MAC + */ +typedef enum { + M2M_ATE_TX_SRC_MAC = 0x00, + M2M_ATE_TX_SRC_PHY = 0x01, +}tenuM2mAteTxSource; + +/*! + *@enum tenuM2mAteTxMode + *@brief Used to define type of TX mode either normal or CW(Continuous Wave) TX sequence + */ +typedef enum { + M2M_ATE_TX_MODE_NORM = 0x00, + M2M_ATE_TX_MODE_CW = 0x01, +}tenuM2mAteTxMode; + +/*! + *@enum tenuM2mAteChannels + *@brief Available channels for TX and RX + */ +typedef enum { + M2M_ATE_CHANNEL_1 = 0x01, + M2M_ATE_CHANNEL_2 = 0x02, + M2M_ATE_CHANNEL_3 = 0x03, + M2M_ATE_CHANNEL_4 = 0x04, + M2M_ATE_CHANNEL_5 = 0x05, + M2M_ATE_CHANNEL_6 = 0x06, + M2M_ATE_CHANNEL_7 = 0x07, + M2M_ATE_CHANNEL_8 = 0x08, + M2M_ATE_CHANNEL_9 = 0x09, + M2M_ATE_CHANNEL_10 = 0x0A, + M2M_ATE_CHANNEL_11 = 0x0B, + M2M_ATE_CHANNEL_12 = 0x0C, + M2M_ATE_CHANNEL_13 = 0x0D, + M2M_ATE_CHANNEL_14 = 0x0E, +}tenuM2mAteChannels; + +/*! + *@struct tstrM2mAteRxStatus + *@brief Used to save statistics of RX case + */ +typedef struct { + uint32 num_rx_pkts; + /*!< Number of total RX packet + */ + uint32 num_err_pkts; + /*!< Number of RX failed packets + */ + uint32 num_good_pkts; + /*!< Number of RX packets actually received + */ +} tstrM2mAteRxStatus; + +/*! + *@struct tstrM2mAteTx + *@brief Used as data source in case of enabling TX test case + */ +typedef struct { + uint32 num_frames; + /*!< Number of frames to be sent where maximum number allowed is 4294967295 ul, and ZERO means infinite number of frames + */ + uint32 data_rate; + /*!< Rate to sent packets over to select rate use value of \ref tenuM2mAteTxIndexOfRates and pass it to \ref m2m_ate_get_tx_rate + */ + uint8 channel_num; + /*!< Channel number \ref tenuM2mAteChannels + */ + uint8 duty_cycle; + /*!< Duty cycle value between from 1 to 10, where maximum = 1, minimum = 10 \ref tenuM2mAteTxDutyCycle + */ + uint16 frame_len; + /*!< Use \ref M2M_ATE_MAX_FRAME_LENGTH (1024) as the maximum value while \ref M2M_ATE_MIN_FRAME_LENGTH (1) is the minimum value + */ + uint8 tx_gain_sel; + /*!< TX gain mode selection value \ref tenuM2mAteTxGainSetting + */ + uint8 dpd_ctrl; + /*!< DPD mode value\ref tenuM2mAteTxDpdControl + */ + uint8 use_pmu; + /*!< This is 0 if PMU is not used otherwise it must be be 1 \ref tenuM2mAtePMUSetting + */ + uint8 phy_burst_tx; + /*!< Source of Burst TX either PHY or MAC\ref tenuM2mAteTxSource + */ + uint8 cw_tx; + /*!< Mode of Burst TX either normal TX sequence or CW(Continuous Wave) TX sequence \ref tenuM2mAteTxMode + */ + uint32 xo_offset_x1000; + /*!< Signed XO offset value in PPM (Part Per Million) multiplied by 1000. + */ + uint8 use_efuse_xo_offset; + /*!< Set to 0 to use the XO offset provided in xo_offset_x1000. Set to 1 to use XO offset programmed on WINC efuse. + */ + uint8 peer_mac_addr[6]; + /*!< Set peer address to send directed frames to a certain address. + */ +} tstrM2mAteTx; + +/*! + *@struct tstrM2mAteRx + *@brief Used as data source in case of enabling RX test case + */ +typedef struct { + uint8 channel_num; + /*!< Channel number \ref tenuM2mAteChannels + */ + uint8 use_pmu; + /*!< This is 0 if PMU is not used otherwise it must be be 1 \ref tenuM2mAtePMUSetting + */ + uint32 xo_offset_x1000; + /*!< Signed XO offset value in PPM (Part Per Million) multiplied by 1000. + */ + uint8 use_efuse_xo_offset; + /*!< Set to 0 to use the XO offset provided in xo_offset_x1000. Set to 1 to use XO offset programmed on WINC efuse. + */ + uint8 self_mac_addr[6]; + /*!< Set to the self mac address required to be overriden. + */ + uint8 sa_mac_addr[6]; + /*!< Set to the source mac address expected to filter frames from. + */ + uint8 mac_filter_en_da; + /*!< Flag set to enable or disable reception with destination address as a filter. + */ + uint8 mac_filter_en_sa; + /*!< Flag set to enable or disable reception with source address as a filter. + */ + uint8 override_self_mac_addr; + /*!< Flag set to enable or disable self mac address feature. + */ +} tstrM2mAteRx; + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +FUNCTION PROTOTYPES +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ +#ifdef __cplusplus + extern "C" { +#endif + +/*! +@fn \ + sint8 m2m_ate_init(void); + +@brief + This function used to download ATE firmware from flash and start it + +@return + The function SHALL return 0 for success and a negative value otherwise. +*/ +sint8 m2m_ate_init(uint32 req_serial_number); + +/*! +@fn \ + sint8 m2m_ate_deinit(void); + +@brief + De-Initialization of ATE firmware mode + +@return + The function SHALL return 0 for success and a negative value otherwise. +*/ +sint8 m2m_ate_deinit(void); + +/*! +@fn \ + sint8 m2m_ate_set_fw_state(uint8); + +@brief + This function used to change ATE firmware status from running to stopped or vice versa. + +@param [in] u8State + Required state of ATE firmware, one of \ref tenuM2mAteFwState enumeration values. +@return + The function SHALL return 0 for success and a negative value otherwise. +\sa + m2m_ate_init +*/ +sint8 m2m_ate_set_fw_state(uint8); + +/*! +@fn \ + sint8 m2m_ate_get_fw_state(uint8); + +@brief + This function used to return status of ATE firmware. + +@return + The function SHALL return status of ATE firmware, one of \ref tenuM2mAteFwState enumeration values. +\sa + m2m_ate_init, m2m_ate_set_fw_state +*/ +sint8 m2m_ate_get_fw_state(void); + +/*! +@fn \ + uint32 m2m_ate_get_tx_rate(uint8); + +@brief + This function used to return value of TX rate required by application developer. + +@param [in] u8Index + Index of required rate , one of \ref tenuM2mAteTxIndexOfRates enumeration values. +@return + The function SHALL return 0 for in case of failure otherwise selected rate value. +\sa + tenuM2mAteTxIndexOfRates +*/ +uint32 m2m_ate_get_tx_rate(uint8); + +/*! +@fn \ + sint8 m2m_ate_get_tx_status(void); + +@brief + This function used to return status of TX test case either running or stopped. + +@return + The function SHALL return status of ATE firmware, 1 if TX is running otherwise 0. +\sa + m2m_ate_start_tx, m2m_ate_stop_tx +*/ +sint8 m2m_ate_get_tx_status(void); + +/*! +@fn \ + sint8 m2m_ate_start_tx(tstrM2mAteTx *) + +@brief + This function used to start TX test case. + +@param [in] strM2mAteTx + Type of \ref tstrM2mAteTx, with the values required to enable TX test case. You must use \ref m2m_ate_init first. +@return + The function SHALL return 0 for success and a negative value otherwise. +\sa + m2m_ate_init, m2m_ate_stop_tx, m2m_ate_get_tx_status +*/ +sint8 m2m_ate_start_tx(tstrM2mAteTx *); + +/*! +@fn \ + sint8 m2m_ate_stop_tx(void) + +@brief + This function used to stop TX test case. + +@return + The function SHALL return 0 for success and a negative value otherwise. +\sa + m2m_ate_init, m2m_ate_start_tx, m2m_ate_get_tx_status +*/ +sint8 m2m_ate_stop_tx(void); + +/*! +@fn \ + sint8 m2m_ate_get_rx_status(uint8); + +@brief + This function used to return status of RX test case either running or stopped. + +@return + The function SHALL return status of ATE firmware, 1 if RX is running otherwise 0. +\sa + m2m_ate_start_rx, m2m_ate_stop_rx +*/ +sint8 m2m_ate_get_rx_status(void); + +/*! +@fn \ + sint8 m2m_ate_start_rx(tstrM2mAteRx *) + +@brief + This function used to start RX test case. + +@param [in] strM2mAteRx + Type of \ref tstrM2mAteRx, with the values required to enable RX test case. You must use \ref m2m_ate_init first. +@return + The function SHALL return 0 for success and a negative value otherwise. +\sa + m2m_ate_init, m2m_ate_stop_rx, m2m_ate_get_rx_status +*/ +sint8 m2m_ate_start_rx(tstrM2mAteRx *); + +/*! +@fn \ + sint8 m2m_ate_stop_rx(void) + +@brief + This function used to stop RX test case. + +@return + The function SHALL return 0 for success and a negative value otherwise. +\sa + m2m_ate_init, m2m_ate_start_rx, m2m_ate_get_rx_status +*/ +sint8 m2m_ate_stop_rx(void); + +/*! +@fn \ + sint8 m2m_ate_read_rx_status(tstrM2mAteRxStatus *) + +@brief + This function used to read RX statistics from ATE firmware. + +@param [out] strM2mAteRxStatus + Type of \ref tstrM2mAteRxStatus used to save statistics of RX test case. You must use \ref m2m_ate_start_rx first. +@return + The function SHALL return 0 for success and a negative value otherwise. +\sa + m2m_ate_init, m2m_ate_start_rx +*/ +sint8 m2m_ate_read_rx_status(tstrM2mAteRxStatus *); + +/*! +@fn \ + sint8 m2m_ate_set_dig_gain(double dGaindB) + +@brief + This function is used to set the digital gain + +@param [in] double dGaindB + The digital gain value required to be set. +@return + The function SHALL return 0 for success and a negative value otherwise. +*/ +sint8 m2m_ate_set_dig_gain(double dGaindB); + +/*! +@fn \ + sint8 m2m_ate_get_dig_gain(double * pdGaindB) + +@brief + This function is used to get the digital gain + +@param [out] double * pdGaindB + The retrieved digital gain value obtained from HW registers. +@return + The function SHALL return 0 for success and a negative value otherwise. +*/ +sint8 m2m_ate_get_dig_gain(double * pdGaindB); + +/*! +@fn \ + sint8 m2m_ate_get_pa_gain(uint32 *paGain) + +@brief + This function is used to get the pa gain + +@param [out] uint32 *paGain + The retrieved pa gain value obtained from HW registers. +@return + The function SHALL return 0 for success and a negative value otherwise. +*/ +sint8 m2m_ate_get_pa_gain(uint32 * paGain); + +/*! +@fn \ + sint8 m2m_ate_get_ppa_gain(uint32 * ppaGain) + +@brief + This function is used to get the ppa gain + +@param [out] uint32 * ppaGain + The retrieved ppa gain value obtained from HW registers. +@return + The function SHALL return 0 for success and a negative value otherwise. +*/ +sint8 m2m_ate_get_ppa_gain(uint32 * ppaGain); + +/*! +@fn \ + sint8 m2m_ate_get_tot_gain(double * pTotGaindB) + +@brief + This function is used to get the total gain + +@param [out] double * pTotGaindB + The retrieved total gain value obtained from calculations made based on the digital gain, pa and ppa gain values. +@return + The function SHALL return 0 for success and a negative value otherwise. +*/ +sint8 m2m_ate_get_tot_gain(double * pTotGaindB); + + +#ifdef __cplusplus +} +#endif + +#endif /* _M2M_CONFIG_MODE_H_ */ + +#endif //_M2M_ATE_FW_ \ No newline at end of file diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/include/m2m_crypto.h b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/include/m2m_crypto.h new file mode 100644 index 000000000..f173e0d0d --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/include/m2m_crypto.h @@ -0,0 +1,212 @@ +/** + * + * \file + * + * \brief WINC3400 Crypto API + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef __M2M_CRYPTO_H__ +#define __M2M_CRYPTO_H__ + + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +INCLUDES +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ + + +#include "common/include/nm_common.h" +#include "driver/include/m2m_types.h" + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +MACROS +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ +#define M2M_SHA256_CONTEXT_BUFF_LEN 128 +#define M2M_SHA256_DIGEST_LEN 32 +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +DATA TYPES +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ + +/*! +@struct \ + tstrM2mSha256Ctxt + +@brief + SHA256 context data +*/ +typedef struct sha256ctxt{ + uint32 au32Sha256CtxtBuff[M2M_SHA256_CONTEXT_BUFF_LEN/sizeof(uint32)]; +} tstrM2mSha256Ctxt; + + +/*! +@enum \ + tenuRsaSignStatus + +@brief + RSA Signature status: pass or fail. +*/ +typedef enum{ + M2M_RSA_SIGN_OK, + M2M_RSA_SIGN_FAIL +} tenuRsaSignStatus; + + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +FUNCTION PROTOTYPES +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ + + +#ifdef __cplusplus + extern "C" { +#endif + +/*! +@fn \ + sint8 m2m_sha256_hash_init(tstrM2mSha256Ctxt *psha256Ctxt); + +@brief SHA256 hash initialization + +@param[in] psha256Ctxt + Pointer to a sha256 context allocated by the caller. +*/ +sint8 m2m_sha256_hash_init(tstrM2mSha256Ctxt *psha256Ctxt); + + +/*! +@fn \ + sint8 m2m_sha256_hash_update(tstrM2mSha256Ctxt *psha256Ctxt, uint8 *pu8Data, uint16 u16DataLength); + +@brief SHA256 hash update + +@param [in] psha256Ctxt + Pointer to the sha256 context. + +@param [in] pu8Data + Buffer holding the data submitted to the hash. + +@param [in] u16DataLength + Size of the data bufefr in bytes. +*/ +sint8 m2m_sha256_hash_update(tstrM2mSha256Ctxt *psha256Ctxt, uint8 *pu8Data, uint16 u16DataLength); + + +/*! +@fn \ + sint8 m2m_sha256_hash_finish(tstrM2mSha256Ctxt *psha256Ctxt, uint8 *pu8Sha256Digest); + +@brief SHA256 hash finalization + +@param[in] psha256Ctxt + Pointer to a sha256 context allocated by the caller. + +@param [in] pu8Sha256Digest + Buffer allocated by the caller which will hold the resultant SHA256 Digest. It must be allocated no less than M2M_SHA256_DIGEST_LEN. +*/ +sint8 m2m_sha256_hash_finish(tstrM2mSha256Ctxt *psha256Ctxt, uint8 *pu8Sha256Digest); + + + + +/*! +@fn \ + sint8 m2m_rsa_sign_verify(uint8 *pu8N, uint16 u16NSize, uint8 *pu8E, uint16 u16ESize, uint8 *pu8SignedMsgHash, \ + uint16 u16HashLength, uint8 *pu8RsaSignature); + +@brief RSA Signature Verification + + The function shall request the RSA Signature verification from the WINC Firmware for the given message. The signed message shall be + compressed to the corresponding hash algorithm before calling this function. + The hash type is identified by the given hash length. For example, if the hash length is 32 bytes, then it is SHA256. + +@param[in] pu8N + RSA Key modulus n. + +@param[in] u16NSize + Size of the RSA modulus n in bytes. + +@param[in] pu8E + RSA public exponent. + +@param[in] u16ESize + Size of the RSA public exponent in bytes. + +@param[in] pu8SignedMsgHash + The hash digest of the signed message. + +@param[in] u16HashLength + The length of the hash digest. + +@param[out] pu8RsaSignature + Signature value to be verified. +*/ +sint8 m2m_rsa_sign_verify(uint8 *pu8N, uint16 u16NSize, uint8 *pu8E, uint16 u16ESize, uint8 *pu8SignedMsgHash, + uint16 u16HashLength, uint8 *pu8RsaSignature); + + +/*! +@fn \ + sint8 m2m_rsa_sign_gen(uint8 *pu8N, uint16 u16NSize, uint8 *pu8d, uint16 u16dSize, uint8 *pu8SignedMsgHash, \ + uint16 u16HashLength, uint8 *pu8RsaSignature); + +@brief RSA Signature Generation + + The function shall request the RSA Signature generation from the WINC Firmware for the given message. The signed message shall be + compressed to the corresponding hash algorithm before calling this function. + The hash type is identified by the given hash length. For example, if the hash length is 32 bytes, then it is SHA256. + +@param[in] pu8N + RSA Key modulus n. + +@param[in] u16NSize + Size of the RSA modulus n in bytes. + +@param[in] pu8d + RSA private exponent. + +@param[in] u16dSize + Size of the RSA private exponent in bytes. + +@param[in] pu8SignedMsgHash + The hash digest of the signed message. + +@param[in] u16HashLength + The length of the hash digest. + +@param[out] pu8RsaSignature + Pointer to a user buffer allocated by teh caller shall hold the generated signature. +*/ +sint8 m2m_rsa_sign_gen(uint8 *pu8N, uint16 u16NSize, uint8 *pu8d, uint16 u16dSize, uint8 *pu8SignedMsgHash, + uint16 u16HashLength, uint8 *pu8RsaSignature); +#ifdef __cplusplus +} +#endif + + +#endif /* __M2M_CRYPTO_H__ */ \ No newline at end of file diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/include/m2m_flash.h b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/include/m2m_flash.h new file mode 100644 index 000000000..258664c9a --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/include/m2m_flash.h @@ -0,0 +1,511 @@ +/** + * + * \file + * + * \brief WINC3400 Flash Interface. + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +/**@defgroup FLASHAPI FLASH +*/ + +#ifndef __M2M_FLASH_H__ +#define __M2M_FLASH_H__ + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +INCLUDES +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ +#include "common/include/nm_common.h" +#include "driver/include/m2m_types.h" + +/**@defgroup FlashDefs Defines + * @ingroup FLASHAPI + * @{*/ + + +/*! Bit 0 of u8Options parameter of @ref m2m_flash_updateimage.\n + * Request to write new firmware image to WINC inactive partition. */ +#define FLASH_UPDATEIMAGE_OPTION_UPDATE NBIT0 +/*! Bit 1 of u8Options parameter of @ref m2m_flash_updateimage.\n + * Request to mark image in WINC inactive partition as valid. If set along with + * @ref FLASH_UPDATEIMAGE_OPTION_UPDATE, the image is not marked valid if the writing fails. */ +#define FLASH_UPDATEIMAGE_OPTION_VALIDATE NBIT1 +/*! Bit 2 of u8Options parameter of @ref m2m_flash_updateimage.\n + * Request to switch the WINC active/inactive partitions. Use this to switch to a new image or to + * revert to an old one. The switch only succeeds if the image has been marked valid. */ +#define FLASH_UPDATEIMAGE_OPTION_SWITCH NBIT2 + +/*! Return success, transfer succeeded. */ +#define FLASH_SUCCESS 0 +/*! Return error. The parameters provided by the MCU application failed sanity checks. */ +#define FLASH_ERR_PARAM (-1) +/*! Return error. An MCU application function of type @ref tpfDataAccessFn returned failure. */ +#define FLASH_ERR_LOCAL_ACCESS (-2) +/*! Return error. There was an error while accessing WINC flash, or contents of WINC flash were not as expected. */ +#define FLASH_ERR_WINC_ACCESS (-3) +/*! Return error. The transfer destination location was too small for the size of data to be transferred. */ +#define FLASH_ERR_SIZE (-4) +/*! Return error. The data provided by the MCU application caused a failure. For example:\n + * - An item could not be added to a WINC flash store because the identifier matched an existing item. + * - An item could not be read or removed from a WINC flash store because the identifier did not match an existing item. + * - A firmware image could not be written to WINC flash because it did not match the format of WINC firmware images. */ +#define FLASH_ERR_WINC_CONFLICT (-5) +/*! Return error. The MCU application did not call @ref m2m_flash_init during Wi-Fi initialization. */ +#define FLASH_ERR_UNINIT (-6) +/*! Return error. The module hit an internal error, such as insufficient heap memory. */ +#define FLASH_ERR_INTERNAL (-7) + + /**@} + */ +/**@defgroup FlashEnums Enumeration/Typedefs + * @ingroup FLASHAPI + * @{*/ + +/*! +@enum tenuFlashDataFnCtl + +@brief Control parameter for @ref tpfDataAccessFn. + */ +typedef enum { + /*! Data access about to start. Check and save parameters as required, ready for subsequent + * data accesses. */ + FLASH_DATA_FN_INITIALIZE, + /*! Sequential data access, using parameters previously provided by FLASH_DATA_FN_INITIALIZE. */ + FLASH_DATA_FN_DATA, + /*! Data access aborted. Did not complete and will not be continued. */ + FLASH_DATA_FN_TERMINATE, + /*! Data access complete. */ + FLASH_DATA_FN_COMPLETE +}tenuFlashDataFnCtl; + +/*! +@enum tenuDataFnRW + +@brief Indicates whether data is to be read or written + */ +typedef enum { + /*! Read data from application memory. */ + FLASH_DATA_FN_READ, + /*! Write data to application memory. */ + FLASH_DATA_FN_WRITE +}tenuDataFnRW; + +/*! +@enum tenuImageId + +@brief Indicates which image to access in WINC flash + */ +typedef enum { + /*! Access the image in the inactive partition. */ + FLASH_IMAGE_INACTIVE, + /*! Access the image in the active partition. */ + FLASH_IMAGE_ACTIVE +}tenuImageId; + + +/*! +@typedef \ + tpfDataAccessFn + +@brief + A function of this type is used for local data access. It can be implemented to handle simple + RAM access with pointer/length, or it can be implemented to handle access to external memory. + Functions of this type are provided to the module via various function APIs. +@see m2m_flash_rootcert_add +@see m2m_flash_rootcert_read +@see m2m_flash_rootcert_readidx +@see m2m_flash_updateimage +@see m2m_flash_readimage + +@param [in] enuCtl + Control parameter. +@param [in] pvStr + Generic pointer to structure. The structure type depends on enuCtl: + - @ref tstrDataAccessInitParamsApp if enuCtl is @ref FLASH_DATA_FN_INITIALIZE. + - @ref tstrDataAccessParamsApp if enuCtl is @ref FLASH_DATA_FN_DATA. + - @ref NULL if enuCtl is @ref FLASH_DATA_FN_TERMINATE or @ref FLASH_DATA_FN_COMPLETE. + +@note The function is typically called by the module multiple times during a data transfer: + Once with @ref FLASH_DATA_FN_INITIALIZE, then multiple times with @ref FLASH_DATA_FN_DATA, then + once with @ref FLASH_DATA_FN_COMPLETE. + +@return Zero for success. Non-zero otherwise. + +\section FlashExample1 Example +This example illustrates an implementation of a function of type @ref tpfDataAccessFn. \n +This example assumes the application's data buffer is in RAM, so we can use memcpy. Alternatively +memcpy can be replaced by dedicated functions which read/write the application buffer. + +gpu8DataLocation is a pointer to the data buffer in RAM, set by the application. \n +gu32DataSize is the size of the data buffer, set by the application. + +@code{.c} +sint8 data_access_ptr(tenuFlashDataFnCtl enuCtl, void *pvStr) +{ + // Return value. + sint8 s8Ret = -1; + // Fixed variables, set in case FLASH_DATA_FN_INITIALIZE, reset in case FLASH_DATA_FN_COMPLETE. + static tenuDataFnRW enuRW; + static uint8 *pu8Location = NULL; + static uint32 u32BytesRemaining = 0; + + switch (enuCtl) + { + case FLASH_DATA_FN_INITIALIZE: + if (pvStr != NULL) + { + tstrDataAccessInitParamsApp *init_params = (tstrDataAccessInitParamsApp*)pvStr; + if (init_params->u32TotalSize > gu32DataSize) + break; + // Set fixed variables. + enuRW = init_params->enuRW; + pu8Location = gpu8DataLocation; + u32BytesRemaining = init_params->u32TotalSize; + s8Ret = 0; + } + break; + case FLASH_DATA_FN_DATA: + if ((pvStr != NULL) && (pu8Location != NULL)) + { + tstrDataAccessParamsApp *params = (tstrDataAccessParamsApp*)pvStr; + // Some sanity checks which should never fail. + if (u32BytesRemaining < params->u32DataSize) + break; + if (params->pu8Data == NULL) + break; + switch (enuRW) + { + case FLASH_DATA_FN_WRITE: + memcpy(pu8Location, params->pu8Data, params->u32DataSize); + s8Ret = 0; + break; + case FLASH_DATA_FN_READ: + memcpy(params->pu8Data, pu8Location, params->u32DataSize); + s8Ret = 0; + break; + } + // Update fixed variables for sequential access. + pu8Location += params->u32DataSize; + u32BytesRemaining -= params->u32DataSize; + } + break; + case FLASH_DATA_FN_TERMINATE: + case FLASH_DATA_FN_COMPLETE: + // Reset fixed variables. + pu8Location = NULL; + u32BytesRemaining = 0; + s8Ret = 0; + break; + } + return s8Ret; +} +@endcode +*/ +typedef sint8 (*tpfDataAccessFn) (tenuFlashDataFnCtl enuCtl, void *pvStr); + +/*! +@struct \ + tstrDataAccessInitParamsApp +@brief + This structure contains parameters for initializing a local data access (read or write). + +@see tpfDataAccessFn. + */ +typedef struct { + /*! Total size of data to be accessed in data location. */ + uint32 u32TotalSize; + /*! Flags indicating type of data access (read or write). */ + tenuDataFnRW enuRW; +}tstrDataAccessInitParamsApp; + +/*! +@struct \ + tstrDataAccessParamsApp +@brief + This structure contains data for local data access (read or write). +@see tpfDataAccessFn. + */ +typedef struct { + /*! Buffer to be written from or read to. */ + uint8 *pu8Data; + /*! Size of data to be written or read. */ + uint32 u32DataSize; +}tstrDataAccessParamsApp; + +/*! +@struct \ + tstrFlashState +@brief + This structure contains information about an attempted transfer. +@see m2m_flash_init + */ +typedef struct { + /*! Last access attempt. Identifier provided by MCU application. 0 if info not available. */ + uint16 u16LastAccessId; + /*! Was the last access attempt successful? */ + uint8 u8Success; + /*! Did the last access attempt result in modified WINC flash? */ + uint8 u8Changed; + /*! Has the module been initialized? */ + uint8 u8Init; + /*! Has the module been initialized more recently than the module last reset the WINC? */ + uint8 u8Reset; +}tstrFlashState; + +/**@} +*/ + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +FUNCTION PROTOTYPES +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ +/** \defgroup FLASHFUNCTIONS Functions +* @ingroup FLASHAPI +*/ + +/**@{*/ +/*! +@fn \ + sint8 m2m_flash_updateimage(uint8 u8Options, uint16 u16Id, tpfDataAccessFn pfSourceFn, uint32 u32SourceSize); + +@brief Write/validate/switch a WINC firmware image. + +@param [in] u8Options + Flags indicating the required combination of write / validate / switch. +@param [in] u16Id + Transfer identifier, not interpreted by this module. +@param [in] pfSourceFn + Function for the module to call to obtain the image from the MCU application. +@param [in] u32SourceSize + Size of the image being provided by the MCU application. + +@see FLASH_UPDATEIMAGE_OPTION_UPDATE +@see FLASH_UPDATEIMAGE_OPTION_VALIDATE +@see FLASH_UPDATEIMAGE_OPTION_SWITCH + +@return Zero indicates success. + Negative values indicate failure. +*/ +sint8 m2m_flash_updateimage(uint8 u8Options, uint16 u16Id, tpfDataAccessFn pfSourceFn, uint32 u32SourceSize); +/*! +@fn \ + sint8 m2m_flash_readimage(tenuImageId enuImageId, uint16 u16Id, tpfDataAccessFn pfDestFn, uint32 u32DestSize); + +@brief Read a WINC firmware image. + +@param [in] enuImageId + Which partition to read image from. +@param [in] u16Id + Transfer identifier, not interpreted by this module. +@param [in] pfDestFn + Function for the module to call to send the image to the MCU application. +@param [in] u32DestSize + Size of the memory available to the MCU application for storing the image. + +@return Zero indicates success. + Negative values indicate failure. +*/ +sint8 m2m_flash_readimage(tenuImageId enuImageId, uint16 u16Id, tpfDataAccessFn pfDestFn, uint32 u32DestSize); +/*! +@fn \ +sint8 m2m_flash_rootcert_add(uint16 u16Id, tpfDataAccessFn pfSourceFn, uint32 u32SourceSize); + +@brief Add an entry to the WINC TLS root certificate store. + +@param [in] u16Id + Transfer identifier, not interpreted by this module. +@param [in] pfSourceFn + Function for the module to call to obtain the certificate entry from the MCU application. +@param [in] u32SourceSize + Size of the certificate entry being provided by the MCU application. + +@note The data location to be accessed via pfSourceFn + contains the entry to be added. The format of a TLS root certificate entry is: + @code{.c} + Name Offset Length Contents + Header 0 36 tstrRootCertEntryHeader + Key 36 KeyLength Public key and padding + Padding 36+KeyLength PadLength 0xFF + @endcode + For RSA public keys, the format of Key is: + @code{.c} + Name Offset Length + Modulus 36 ModLength RSA modulus, with leading 0s stripped off + Exponent 36+ModLength ExpLength Public exponent, with leading 0s stripped off + @endcode + In this case PadLength is the amount of padding that would be required for 4-byte alignment of Modulus + plus the amount of padding that would be required for 4-byte alignment of Exponent.\n + For ECDSA public keys, the format of Key is: + @code{.c} + Name Offset Length + X Coord 36 CoordLength Public key X-coordinate + Y Coord 36+CoordLength CoordLength Public key Y-coordinate + @endcode + In this case PadLength is the amount of padding that would be required for 4-byte alignment of X Coord + plus the amount of padding that would be required for 4-byte alignment of Y Coord. + +@return Zero indicates success. + Negative values indicate failure. +*/ +sint8 m2m_flash_rootcert_add(uint16 u16Id, tpfDataAccessFn pfFn, uint32 u32Size); + +/*! +@fn \ +sint8 m2m_flash_rootcert_remove(uint16 u16Id, uint8 *pu8Identifier, uint32 u32IdentifierSz); + +@brief Remove an entry from the WINC TLS root certificate store. + +@param [in] u16Id + Transfer identifier, not interpreted by this module. +@param [in] pu8Identifier + Identifier for the entry to be removed. This is the SHA1 digest of the certificate issuer name. +@param [in] u32IdentifierSz + Size of the identifier (20). + +@return Zero indicates success. + Negative values indicate failure. +*/ +sint8 m2m_flash_rootcert_remove(uint16 u16Id, uint8 *pu8Identifier, uint32 u32IdentifierSz); +/*! +@fn \ + sint8 m2m_flash_rootcert_read(uint16 u16Id, tpfDataAccessFn pfDestFn, uint32 u32DestSize, uint8 *pu8Identifier, uint32 u32IdentifierSz); + +@brief Read an entry from the WINC TLS root certificate store, referenced by entry identifier. + +@param [in] u16Id + Transfer identifier, not interpreted by this module. +@param [in] pfDestFn + Function for the module to call to send the certificate entry to the MCU application. +@param [in] u32DestSize + Size of the memory available to the MCU application for storing the entry. +@param [in] pu8Identifier + Identifier for the entry to be read. This is the SHA1 digest of the certificate issuer name. +@param [in] u32IdentifierSz + Size of the identifier (20). + +@return Zero indicates success. + Negative values indicate failure. +*/ +sint8 m2m_flash_rootcert_read(uint16 u16Id, tpfDataAccessFn pfDestFn, uint32 u32DestSize, uint8 *pu8Identifier, uint32 u32IdentifierSz); +/*! +@fn \ + sint8 m2m_flash_rootcert_readidx(uint16 u16Id, tpfDataAccessFn pfDestFn, uint32 u32DestSize, uint8 u8Index); + +@brief Read an entry from the WINC TLS root certificate store, referenced by entry index. + +@param [in] u16Id + Transfer identifier, not interpreted by this module. +@param [in] pfDestFn + Function for the module to call to send the certificate entry to the MCU application. +@param [in] u32DestSize + Size of the memory available to the MCU application for storing the entry. +@param [in] u8Index + Zero-based index of the entry to be read. + +@return Zero indicates success. + Negative values indicate failure. +*/ +sint8 m2m_flash_rootcert_readidx(uint16 u16Id, tpfDataAccessFn pfDestFn, uint32 u32DestSize, uint8 u8Index); + +/*! +@fn \ + void m2m_flash_get_state(tstrFlashState *pstrState); + +@brief Get information about the module current state and about the most recent access attempt. + +@param [out] pstrState + Module state and most recent access attempt info. + +@return None. +*/ +void m2m_flash_get_state(tstrFlashState *pstrState); + + +/*! +@fn \ + sint8 m2m_flash_init(void); + +@brief Initialize the module. + +@warning This API must be called at a particular point during MCU application initialization. + +@see m2m_wifi_init +@see m2m_wifi_init_hold +@see m2m_wifi_init_start + +\section FlashExample2 Example +This example demonstrates how to add @ref m2m_flash_init and @ref m2m_flash_get_state +to MCU application initialization code. + +Original code: +@code{.c} +{ + tstrWifiInitParam param = {...} + sint8 status = 0; + + status = m2m_wifi_init(param); + if (status != 0) + { + // Wifi init failed. + } +} +@endcode +New code: +@code{.c} +{ + tstrWifiInitParam param = {...} + sint8 status = 0; + + status = m2m_wifi_init_hold(); + if (status == 0) + { + tstrFlashState strFlashState; + + m2m_flash_get_state(&strFlashState); + printf("FlashAccess:%x:%d%d\n", strFlashState.u16LastAccessId, strFlashState.u8Success, strFlashState.u8Changed); + + switch (strFlashState.u16LastAccessId) + { + // Application code dependent on meaning of u16LastAccessId. + } + m2m_flash_init(); + status = m2m_wifi_init_start(param); + } + if (status != 0) + { + // Wifi init failed. + } +} +@endcode + +@return Zero for successful initialization of module. Negative value otherwise. +*/ +sint8 m2m_flash_init(void); + + /**@}*/ +#endif /* __M2M_FLASH_H__ */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/include/m2m_ota.h b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/include/m2m_ota.h new file mode 100644 index 000000000..f53202491 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/include/m2m_ota.h @@ -0,0 +1,383 @@ +/** + * + * \file + * + * \brief WINC3400 IoT OTA Interface. + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +/**@defgroup OTAAPI OTA +*/ + +#ifndef __M2M_OTA_H__ +#define __M2M_OTA_H__ + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +INCLUDES +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ + +#include "common/include/nm_common.h" +#include "driver/include/m2m_types.h" +#include "driver/source/nmdrv.h" + +/** +* @addtogroup OTATYPEDEF +*/ +/**@{*/ + +/*! +@typedef \ + void (*tpfOtaNotifCb) (tstrOtaUpdateInfo *); + +@brief A callback to get notification about a potential OTA update. + +@param[in] pstrOtaUpdateInfo A structure to provide notification payload. + +@sa + tstrOtaUpdateInfo +@warning + The notification is not supported (Not implemented yet) + +*/ +typedef void (*tpfOtaNotifCb) (tstrOtaUpdateInfo * pstrOtaUpdateInfo); + + +/*! +@typedef \ + void (*tpfOtaUpdateCb) (uint8 u8OtaUpdateStatusType ,uint8 u8OtaUpdateStatus); + +@brief + A callback to get OTA status update, the callback provides the download status, + the switch to the downloaded firmware status and roll-back status. + +@param[in] u8OtaUpdateStatusType Possible values are listed in \ref tenuOtaUpdateStatusType. Possible types are: +- [DL_STATUS](@ref DL_STATUS) +- [SW_STATUS](@ref SW_STATUS) +- [RB_STATUS](@ref RB_STATUS) + +@param[in] u8OtaUpdateStatus Possible values are listed in \ref tenuOtaUpdateStatus. + +@see + tenuOtaUpdateStatusType + tenuOtaUpdateStatus + */ +typedef void (*tpfOtaUpdateCb) (uint8 u8OtaUpdateStatusType ,uint8 u8OtaUpdateStatus); + /**@} + */ +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +FUNCTION PROTOTYPES +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ +/** \defgroup OTAFUNCTIONS Functions + * @ingroup OTAAPI + */ +#ifdef __cplusplus + extern "C" { +#endif + + /**@{*/ +/*! +@fn \ + NMI_API sint8 m2m_ota_init(tpfOtaUpdateCb pfOtaUpdateCb,tpfOtaNotifCb pfOtaNotifCb); + * Synchronous initialization function for the OTA layer by registering the update callback. + * The notification callback is not supported at the current version. Calling this API is a + * prerequisite for all other OTA API's. +@param [in] pfOtaUpdateCb + OTA Update callback function + +@param [in] pfOtaNotifCb + OTA notify callback function + +@return + The function returns @ref M2M_SUCCESS for successful operations and a negative value otherwise. +*/ +NMI_API sint8 m2m_ota_init(tpfOtaUpdateCb pfOtaUpdateCb,tpfOtaNotifCb pfOtaNotifCb); +/*! +@fn \ + NMI_API sint8 m2m_ota_notif_set_url(uint8 * u8Url); + * Set the OTA notification server URL, the functions need to be called before any check for update. + * This functionality is not supported by WINC firmware. + +@param [in] u8Url + Set the OTA notification server URL, the functions need to be called before any check for update. +@warning + This functionality is not supported by WINC firmware. + +@see + m2m_ota_init +@return + The function returns @ref M2M_SUCCESS for successful operations and a negative value otherwise. +*/ +NMI_API sint8 m2m_ota_notif_set_url(uint8 * u8Url); +/*! +@fn \ + NMI_API sint8 m2m_ota_notif_check_for_update(void); + * Synchronous function to check for the OTA update using the Notification Server + * URL. This functionality is not supported by WINC firmware. +@warning + This functionality is not supported by WINC firmware. + +@sa + m2m_ota_init + m2m_ota_notif_set_url +@return + The function returns @ref M2M_SUCCESS for successful operations and a negative value otherwise. +*/ +NMI_API sint8 m2m_ota_notif_check_for_update(void); +/*! +@fn \ + NMI_API sint8 m2m_ota_notif_sched(uint32 u32Period); +* Schedule OTA notification Server check for update request after specific number of days. +* This functionality is not supported by WINC firmware. + +@param [in] u32Period + Period in days + +@warning + This functionality is not supported by WINC firmware. + +@sa + m2m_ota_init + m2m_ota_notif_check_for_update + m2m_ota_notif_set_url +@return + The function returns @ref M2M_SUCCESS for successful operations and a negative value otherwise. +*/ +NMI_API sint8 m2m_ota_notif_sched(uint32 u32Period); +/*! +@fn \ + NMI_API sint8 m2m_ota_start_update(uint8 * u8DownloadUrl); + Request OTA start update using the downloaded URL. + The firmware OTA module will download the OTA image, ensure integrity of the image, and update the validity of the image in + the control structure. + On completion, a callback of type @ref tpfOtaUpdateCb is called (callback previously provided via @ref m2m_ota_init()). + Switching to the updated image additionally requires completion of @ref m2m_ota_switch_firmware(), and system_reset(). + +@param [in] u8DownloadUrl + The download firmware URL, according to the application server. + +@warning + Calling this API does not guarantee OTA WINC image update; it depends on the connection with the download server and the validity + of the image. + Calling this API invalidates the previous rollback image. The current image will become the rollback image after + @ref m2m_ota_switch_firmware(). + +@pre + @ref m2m_ota_init() must have been called before using @ref m2m_ota_start_update(). +@sa + @ref m2m_ota_init() + @ref m2m_ota_switch_firmware() + @ref tpfOtaUpdateCb + +@return + The function returns @ref M2M_SUCCESS for successful operations and a negative value otherwise. + Note that successful operation in this context means the OTA update request has reached the firmware OTA module. It does not + indicate whether or not the image update succeeded. + +\section OTAExample Example + This example shows how an OTA image update and switch is carried out. + It demonstrates use of the following OTA APIs: + @ref m2m_ota_init() + @ref tpfOtaUpdateCb + @ref m2m_ota_start_update() + @ref m2m_ota_switch_firmware() + @ref m2m_ota_rollback() + It also makes use of @ref m2m_wifi_check_ota_rb() in order to inform OTA decisions. + +@code +static void OtaUpdateCb(uint8 u8OtaUpdateStatusType ,uint8 u8OtaUpdateStatus) +{ + sint8 s8tmp; + tstrM2mRev strtmp; + + M2M_INFO("%d %d\n", u8OtaUpdateStatusType, u8OtaUpdateStatus); + + switch(u8OtaUpdateStatusType) { + case DL_STATUS: + if(u8OtaUpdateStatus == OTA_STATUS_SUCSESS) { + M2M_INFO("OTA download succeeded\n"); + s8tmp = m2m_wifi_check_ota_rb(); + if(s8tmp == M2M_ERR_FW_VER_MISMATCH) { + // In this case the application SHOULD update the host driver before calling + // @ref m2m_ota_switch_firmware(). Switching firmware image and resetting without updating host + // driver would lead to severely limited functionality (i.e. OTA rollback only). + } + else if(s8tmp == M2M_SUCCESS) { + // In this case the application MAY WANT TO update the host driver before calling + // @ref m2m_ota_switch_firmware(). Switching firmware image and resetting without updating host + // driver may lead to suboptimal functionality. + } + else { + M2M_INFO("Cannot recognize downloaded image\n"); + // In this case the application MUST NOT update the host driver if such an update would change the + // driver HIF Major field. Firmware switch @ref using m2m_ota_switch_firmware() is blocked. + break; + } + M2M_INFO("Now switching active partition...\n"); + s8tmp = m2m_ota_switch_firmware(); + } + break; + case SW_STATUS: + case RB_STATUS: + if(u8OtaUpdateStatus == OTA_STATUS_SUCSESS) { + M2M_INFO("Switch/Rollback succeeded\n"); + M2M_INFO("Now resetting the system...\n"); + system_reset(); + } + break; + } +} +static void wifi_event_cb(uint8 u8WiFiEvent, void * pvMsg) +{ + // ... + case M2M_WIFI_REQ_DHCP_CONF: + { + //After successful connection, start the OTA upgrade. + m2m_ota_start_update(OTA_URL); + } + break; + // ... +} +int main (void) +{ + sint8 ret = M2M_SUCCESS; + tstrWifiInitParam param; + bool rollback_required = FALSE; + + // ... system init etc here ... + + //Initialize the WINC Driver. + m2m_memset((uint8*)¶m, 0, sizeof(param)); + param.pfAppWifiCb = wifi_event_cb; + + ret = m2m_wifi_init(¶m); + if(ret == M2M_ERR_FW_VER_MISMATCH) { + ret = m2m_wifi_check_ota_rb(); + if(ret == M2M_SUCCESS) { + // In this case the image in the inactive partition has compatible HIF. We will switch/rollback to it + // after initializing the OTA module. + rollback_required = TRUE; + } + } + if(ret != M2M_SUCCESS) { + M2M_ERR("Driver Init Failed <%d>\n",ret); + while(1); + } + + //Initialize the OTA module. + m2m_ota_init(OtaUpdateCb, NULL); + + if(rollback_required) { + // We need to call either @ref m2m_ota_rollback() or @ref m2m_ota_switch_firmware() (functionally equivalent). + m2m_ota_rollback(); + } else { + // Connect to AP that provides connection to the OTA server + m2m_wifi_default_connect(); + } + + while(1) { + // Handle the app state machine plus the WINC event handler. + while(m2m_wifi_handle_events(NULL) != M2M_SUCCESS) { + } + } +} +@endcode + +*/ +NMI_API sint8 m2m_ota_start_update(uint8 * u8DownloadUrl); +/*! +@fn \ + NMI_API sint8 m2m_ota_rollback(void); + Request rollback to the old (inactive) WINC image. The WINC firmware will check the validity of + the inactive image and activate it if it is valid. + On completion, a callback of type @ref tpfOtaUpdateCb is called (application must previously + have provided the callback via @ref m2m_ota_init()). + If the callback indicates successful activation, the newly-activated image will start running + after next system reset. + +@warning + If rollback will necessitate a host driver update in order to maintain HIF compatibility (HIF + major value change), then it is recommended to update the host driver prior to calling this + API. + In the event of system reset with incompatible driver/firmware, compatibility can be recovered + by calling @ref m2m_ota_rollback or @ref m2m_ota_switch_firmware. See @ref OTAExample. + +@sa + m2m_ota_init + m2m_ota_start_update + +@return + The function returns @ref M2M_SUCCESS for successful operations and a negative value otherwise. +*/ +NMI_API sint8 m2m_ota_rollback(void); +/*! +@fn \ + NMI_API sint8 m2m_ota_abort(void); + Abort an ota in progress (eg if server has stalled) and clean up +@sa + m2m_ota_init + m2m_ota_start_update + +@return + The function returns @ref M2M_SUCCESS for successful operations and a negative value otherwise. +*/ +NMI_API sint8 m2m_ota_abort(void); +/*! +@fn \ + NMI_API sint8 m2m_ota_switch_firmware(void); + Request switch to the updated WINC image. The WINC firmware will check the validity of the + inactive image and activate it if it is valid. + On completion, a callback of type @ref tpfOtaUpdateCb is called (application must previously + have provided the callback via @ref m2m_ota_init()). + If the callback indicates successful activation, the newly-activated image will start running + after next system reset. + +@warning + If switch will necessitate a host driver update in order to maintain HIF compatibility (HIF + major value change), then it is recommended to update the host driver prior to calling this + API. + In the event of system reset with incompatible driver/firmware, compatibility can be recovered + by calling @ref m2m_ota_rollback or @ref m2m_ota_switch_firmware. See @ref OTAExample. + +@sa + m2m_ota_init + m2m_ota_start_update + +@return + The function returns @ref M2M_SUCCESS for successful operations and a negative value otherwise. +*/ +NMI_API sint8 m2m_ota_switch_firmware(void); + +#if 0 +NMI_API sint8 m2m_ota_test(void); +#endif + /**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* __M2M_OTA_H__ */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/include/m2m_periph.h b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/include/m2m_periph.h new file mode 100644 index 000000000..d6730b7fc --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/include/m2m_periph.h @@ -0,0 +1,308 @@ +/** + * + * \file + * + * \brief WINC3400 Peripherals Application Interface. + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _M2M_PERIPH_H_ +#define _M2M_PERIPH_H_ + + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +INCLUDES +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ + + +#include "common/include/nm_common.h" +#include "driver/include/m2m_types.h" + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +MACROS +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +DATA TYPES +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ + +/*! +@struct \ + tstrPerphInitParam + +@brief + Peripheral module initialization parameters. +*/ +typedef struct { + void * arg; +} tstrPerphInitParam; + + +/*! +@enum \ + tenuGpioNum + +@brief + A list of GPIO numbers configurable through the m2m_periph module. +*/ +typedef enum { + M2M_PERIPH_GPIO15, /*!< GPIO15 pad */ + M2M_PERIPH_GPIO16, /*!< GPIO16 pad */ + M2M_PERIPH_GPIO18, /*!< GPIO18 pad */ + M2M_PERIPH_GPIO_MAX +} tenuGpioNum; + + +/*! +@enum \ + tenuI2cMasterSclMuxOpt + +@brief + Allowed pin multiplexing options for I2C master SCL signal. +*/ +typedef enum { + M2M_PERIPH_I2C_MASTER_SCL_MUX_OPT_HOST_WAKEUP, /*!< I2C master SCL is avaiable on HOST_WAKEUP. */ + M2M_PERIPH_I2C_MASTER_SCL_MUX_OPT_SD_DAT3, /*!< I2C master SCL is avaiable on SD_DAT3 (GPIO 7). */ + M2M_PERIPH_I2C_MASTER_SCL_MUX_OPT_GPIO13, /*!< I2C master SCL is avaiable on GPIO 13. */ + M2M_PERIPH_I2C_MASTER_SCL_MUX_OPT_GPIO4, /*!< I2C master SCL is avaiable on GPIO 4.*/ + M2M_PERIPH_I2C_MASTER_SCL_MUX_OPT_I2C_SCL, /*!< I2C master SCL is avaiable on I2C slave SCL. */ + M2M_PERIPH_I2C_MASTER_SCL_MUX_OPT_NUM +} tenuI2cMasterSclMuxOpt; + +/*! +@enum \ + tenuI2cMasterSdaMuxOpt + +@brief + Allowed pin multiplexing options for I2C master SDA signal. +*/ +typedef enum { + M2M_PERIPH_I2C_MASTER_SDA_MUX_OPT_RTC_CLK , /*!< I2C master SDA is avaiable on RTC_CLK. */ + M2M_PERIPH_I2C_MASTER_SDA_MUX_OPT_SD_CLK, /*!< I2C master SDA is avaiable on SD_CLK (GPIO 8). */ + M2M_PERIPH_I2C_MASTER_SDA_MUX_OPT_GPIO14, /*!< I2C master SDA is avaiable on GPIO 14. */ + M2M_PERIPH_I2C_MASTER_SDA_MUX_OPT_GPIO6, /*!< I2C master SDA is avaiable on GPIO 6.*/ + M2M_PERIPH_I2C_MASTER_SDA_MUX_OPT_I2C_SDA, /*!< I2C master SDA is avaiable on I2C slave SDA. */ + M2M_PERIPH_I2C_MASTER_SDA_MUX_OPT_NUM +} tenuI2cMasterSdaMuxOpt; + + +/*! +@struct \ + tstrI2cMasterInitParam + +@brief + I2C master configuration parameters. +@sa + tenuI2cMasterSclMuxOpt + tenuI2cMasterSdaMuxOpt +*/ +typedef struct { + uint8 enuSclMuxOpt; /*!< SCL multiplexing option. Allowed value are defined in tenuI2cMasterSclMuxOpt */ + uint8 enuSdaMuxOpt; /*!< SDA multiplexing option. Allowed value are defined in tenuI2cMasterSdaMuxOpt */ + uint8 u8ClkSpeedKHz; /*!< I2C master clock speed in KHz. */ +} tstrI2cMasterInitParam; + +/*! +@enum \ + tenuI2cMasterFlags + +@brief + Bitwise-ORed flags for use in m2m_periph_i2c_master_write and m2m_periph_i2c_master_read +@sa + m2m_periph_i2c_master_write + m2m_periph_i2c_master_read +*/ +typedef enum { + I2C_MASTER_NO_FLAGS = 0x00, + /*!< No flags. */ + I2C_MASTER_NO_STOP = 0x01, + /*!< No stop bit after this transaction. Useful for scattered buffer read/write operations. */ + I2C_MASTER_NO_START = 0x02, + /*!< No start bit at the beginning of this transaction. Useful for scattered buffer read/write operations.*/ +} tenuI2cMasterFlags; + +/*! +@enum \ + tenuPullupMask + +@brief + Bitwise-ORed flags for use in m2m_perph_pullup_ctrl. +@sa + m2m_periph_pullup_ctrl + +*/ +typedef enum { + M2M_PERIPH_PULLUP_DIS_HOST_WAKEUP = (1ul << 0), + M2M_PERIPH_PULLUP_DIS_RTC_CLK = (1ul << 1), + M2M_PERIPH_PULLUP_DIS_IRQN = (1ul << 2), + M2M_PERIPH_PULLUP_DIS_GPIO_3 = (1ul << 3), + M2M_PERIPH_PULLUP_DIS_GPIO_4 = (1ul << 4), + M2M_PERIPH_PULLUP_DIS_GPIO_5 = (1ul << 5), + M2M_PERIPH_PULLUP_DIS_GPIO_6 = (1ul << 6), + M2M_PERIPH_PULLUP_DIS_SD_CLK = (1ul << 7), + M2M_PERIPH_PULLUP_DIS_SD_CMD_SPI_SCK = (1ul << 8), + M2M_PERIPH_PULLUP_DIS_SD_DAT0_SPI_TXD = (1ul << 9), + M2M_PERIPH_PULLUP_DIS_SD_DAT1_SPI_SSN = (1ul << 10), + M2M_PERIPH_PULLUP_DIS_SD_DAT1_SPI_RXD = (1ul << 11), + M2M_PERIPH_PULLUP_DIS_SD_DAT3 = (1ul << 12), +} tenuPullupEnable1Mask; +typedef enum { + M2M_PERIPH_PULLUP_DIS_GPIO_13 = (1ul << 0), + M2M_PERIPH_PULLUP_DIS_GPIO_14 = (1ul << 1), + M2M_PERIPH_PULLUP_DIS_GPIO_15 = (1ul << 2), + M2M_PERIPH_PULLUP_DIS_GPIO_16 = (1ul << 3), + M2M_PERIPH_PULLUP_DIS_GPIO_17 = (1ul << 4), + M2M_PERIPH_PULLUP_DIS_GPIO_18 = (1ul << 5), + M2M_PERIPH_PULLUP_DIS_GPIO_19 = (1ul << 6), + M2M_PERIPH_PULLUP_DIS_GPIO_20 = (1ul << 7), + M2M_PERIPH_PULLUP_DIS_GPIO_22 = (1ul << 9), + M2M_PERIPH_PULLUP_DIS_GPIO_23 = (1ul << 10), + M2M_PERIPH_PULLUP_DIS_GPIO_38 = (1ul << 25), + M2M_PERIPH_PULLUP_DIS_GPIO_39 = (1ul << 26), + M2M_PERIPH_PULLUP_DIS_GPIO_40 = (1ul << 27), + M2M_PERIPH_PULLUP_DIS_GPIO_42 = (1ul << 29), +} tenuPullupEnable2Mask; +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +FUNCTION PROTOTYPES +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ + + +#ifdef __cplusplus + extern "C" { +#endif + +/*! +@fn \ + NMI_API sint8 m2m_periph_init(tstrPerphInitParam * param); + +@brief + Initialize the NMC1500 peripheral driver module. + +@param [in] param + Peripheral module initialization structure. See members of tstrPerphInitParam. + +@return + The function SHALL return 0 for success and a negative value otherwise. + +@sa + tstrPerphInitParam +*/ +NMI_API sint8 m2m_periph_init(tstrPerphInitParam * param); + +/*! +@fn \ + NMI_API sint8 m2m_periph_gpio_set_dir(uint8 u8GpioNum, uint8 u8GpioDir); + +@brief + Configure a specific NMC1500 pad as a GPIO and sets its direction (input or output). + +@param [in] u8GpioNum + GPIO number. Allowed values are defined in tenuGpioNum. + +@param [in] u8GpioDir + GPIO direction: Zero = input. Non-zero = output. + +@return + The function SHALL return 0 for success and a negative value otherwise. + +@sa + tenuGpioNum +*/ +NMI_API sint8 m2m_periph_gpio_set_dir(uint8 u8GpioNum, uint8 u8GpioDir); + +/*! +@fn \ + NMI_API sint8 m2m_periph_gpio_set_val(uint8 u8GpioNum, uint8 u8GpioVal); + +@brief + Set an NMC1500 GPIO output level high or low. + +@param [in] u8GpioNum + GPIO number. Allowed values are defined in tenuGpioNum. + +@param [in] u8GpioVal + GPIO output value. Zero = low, non-zero = high. + +@return + The function SHALL return 0 for success and a negative value otherwise. + +@sa + tenuGpioNum +*/ +NMI_API sint8 m2m_periph_gpio_set_val(uint8 u8GpioNum, uint8 u8GpioVal); + +/*! +@fn \ + NMI_API sint8 m2m_periph_gpio_get_val(uint8 u8GpioNum, uint8 * pu8GpioVal); + +@brief + Read an NMC1500 GPIO input level. + +@param [in] u8GpioNum + GPIO number. Allowed values are defined in tenuGpioNum. + +@param [out] pu8GpioVal + GPIO input value. Zero = low, non-zero = high. + +@return + The function SHALL return 0 for success and a negative value otherwise. + +@sa + tenuGpioNum +*/ +NMI_API sint8 m2m_periph_gpio_get_val(uint8 u8GpioNum, uint8 * pu8GpioVal); + +/*! +@fn \ + NMI_API sint8 m2m_periph_pullup_ctrl(uint32 pinmask, uint8 enable); + +@brief + Control the programmable pull-up resistor on the chip pads . + + +@param [in] pinmask + Write operation bitwise-ORed mask for which pads to control. Allowed values are defined in tenuPullupMask. + +@param [in] enable + Set to 0 to disable pull-up resistor. Non-zero will enable the pull-up. + +@return + The function SHALL return 0 for success and a negative value otherwise. + +@sa + tenuPullupMask +*/ +NMI_API sint8 m2m_periph_pullup_ctrl(uint32 pinmask, uint8 enable); + +#ifdef __cplusplus +} +#endif + + +#endif /* _M2M_PERIPH_H_ */ \ No newline at end of file diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/include/m2m_types.h b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/include/m2m_types.h new file mode 100644 index 000000000..3655a5b9a --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/include/m2m_types.h @@ -0,0 +1,2214 @@ +/** + * + * \file + * + * \brief WINC3400 IoT Application Interface Internal Types. + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef __M2M_WIFI_TYPES_H__ +#define __M2M_WIFI_TYPES_H__ + + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +INCLUDES +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ + +#ifndef _BOOT_ +#ifndef _FIRMWARE_ +#include "common/include/nm_common.h" +#else +#include "m2m_common.h" +#endif +#endif + + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +MACROS +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ +/**@defgroup VERSION VERSION + */ +/**@defgroup VERSIONDEF Defines + @ingroup VERSION + */ + +/**@{*/ + +/* + Layout of HIF_LEVEL fields + | x x x x x x | x x x x x x x x | + | 13:8 | 7:0 | + | HIF_MAJOR | HIF_MINOR | + | HIF_LEVEL | + + HIF compatibility (checked by driver after wifi boot). + + Check Firmware HIF_MAJOR + |___ + | Does not match Driver - Recommend either: + | > checking compatibility of Cortus image stored in inactive partition + | (m2m_wifi_check_ota_rb()) then swapping to it using OTA rollback or switch. + | > updating Host with out of band method. + |___ + Matches Driver - All APIs can be attempted. + | - Cortus image can be updated (OTA download) + | - New Host image can be retrieved (socket recv) + | + Check Firmware HIF_MINOR + |___ + | Less than Driver - Driver may refuse to execute some APIs (API would return M2M_ERR_SEND). + | - Recommend updating Cortus image using OTA download to use newer Firmware. + |___ + | Equal to Driver - Driver supports all APIs. + |___ + Greater than Driver - Driver supports all APIs. + - Recommend reviewing potential benefit of updating Host to use newer Driver. + + When an OTA update involving HIF_MAJOR change is required, the following order is recommended: + 1. m2m_ota_start_update() to store new Cortus image in inactive partition. + 2. Socket recv() to retrieve new Host image (including new WINC Driver). + 3. Application code to make Host image available in host flash. + 4. m2m_ota_switch_firmware() to switch active/inactive partition (will take effect after system_reset()). + 5. system_reset() to restart with new WINC Driver / Firmware. + Note that in the event of (unintentional) system reset after step (3), the remaining steps (4) and (5) should still be + run after the reset. +*/ +/* Selection of HIF_INFO +*/ +#define M2M_HIF_INFO_SHIFT (0) +#define M2M_HIF_INFO_MASK (0xffff) +/* Subdivision of HIF_INFO +*/ +#define M2M_HIF_BLOCK_SHIFT (14) +#define M2M_HIF_BLOCK_MASK (0x3) +#define M2M_HIF_LEVEL_SHIFT (0) +#define M2M_HIF_LEVEL_MASK (0x3fff) +/* Subdivision of HIF_LEVEL +*/ +#define M2M_HIF_MAJOR_SHIFT (8) +#define M2M_HIF_MAJOR_MASK (0x3f) +#define M2M_HIF_MINOR_SHIFT (0) +#define M2M_HIF_MINOR_MASK (0xff) + +#define M2M_GET_HIF_INFO(hif_ver) ((uint16)(((hif_ver) >> M2M_HIF_INFO_SHIFT) & M2M_HIF_INFO_MASK)) +#define M2M_GET_HIF_BLOCK(hif_info) ((uint8)(((hif_info) >> M2M_HIF_BLOCK_SHIFT) & M2M_HIF_BLOCK_MASK)) +#define M2M_GET_HIF_LEVEL(hif_info) ((uint16)(((hif_info) >> M2M_HIF_LEVEL_SHIFT) & M2M_HIF_LEVEL_MASK)) +#define M2M_GET_HIF_MAJOR(hif_info) ((uint8)(((hif_info) >> M2M_HIF_MAJOR_SHIFT) & M2M_HIF_MAJOR_MASK)) +#define M2M_GET_HIF_MINOR(hif_info) ((uint8)(((hif_info) >> M2M_HIF_MINOR_SHIFT) & M2M_HIF_MINOR_MASK)) + +#define M2M_MAKE_HIF_INFO(hif_level) ( \ + (((uint16)(hif_level) & M2M_HIF_LEVEL_MASK) << M2M_HIF_LEVEL_SHIFT) | \ + (((uint16)M2M_HIF_BLOCK_VALUE & M2M_HIF_BLOCK_MASK) << M2M_HIF_BLOCK_SHIFT) ) + +/*======*======*======*======* + HIF LEVEL + *======*======*======*======*/ + +#define M2M_HIF_BLOCK_VALUE (2) +/*!< Drv/Fw blocking compatibility check. + */ +#define M2M_HIF_MAJOR_VALUE (1) +/*!< Drv/Fw major compatibility check. +*/ +#define M2M_HIF_MINOR_VALUE (3) +/*!< Drv/Fw minor compatibility check. +*/ +#define M2M_HIF_LEVEL ( \ + ((M2M_HIF_MAJOR_VALUE & M2M_HIF_MAJOR_MASK) << M2M_HIF_MAJOR_SHIFT) | \ + ((M2M_HIF_MINOR_VALUE & M2M_HIF_MINOR_MASK) << M2M_HIF_MINOR_SHIFT) \ + ) +/*!< HIF Level (Major/Minor) for Drv/Fw compatibility. +*/ + +/*======*======*======*======* + DRIVER VERSION NO INFO + *======*======*======*======*/ + +#define M2M_DRIVER_VERSION_MAJOR_NO (1) +/*!< Driver Major release version number. +*/ +#define M2M_DRIVER_VERSION_MINOR_NO (0) +/*!< Driver Minor release version number. +*/ +#define M2M_DRIVER_VERSION_PATCH_NO (8) +/*!< Driver patch release version number. +*/ + +/**@}*/ + +/**@defgroup WLANDefines Defines + * @ingroup m2m_wifi + */ +/**@{*/ + +#define M2M_BUFFER_MAX_SIZE (1600UL - 4) +/*!< Maximum size for the shared packet buffer. + */ + + +#define M2M_MAC_ADDRES_LEN 6 +/*!< Size of the MAC address. + */ + +#define M2M_ETHERNET_HDR_OFFSET 34 +/*!< Offset of the ethernet header within the WLAN Tx Buffer. + */ + + +#define M2M_ETHERNET_HDR_LEN 14 +/*!< Length of the ethernet header in bytes. +*/ + + +#define M2M_MAX_SSID_LEN 33 +/*!< Maximum size for the Wi-Fi SSID including the NULL termination. + */ + + +#define M2M_MAX_PSK_LEN 65 +/*!< Maximum size for the WPA PSK including the NULL termination. + */ + +#define M2M_DEVICE_NAME_MAX 48 +/*!< Maximum Size for the device name including the NULL termination. + */ + + +#define M2M_LISTEN_INTERVAL 1 +/*!< The STA uses the Listen Interval parameter to indicate to the AP how + many beacon intervals it shall sleep before it retrieves the queued frames + from the AP. +*/ + + +#define M2M_1X_USR_NAME_MAX 21 +/*!< The maximum size of the user name including the NULL termination. + It is used for RADIUS authentication in case of connecting the device to + an AP secured with WPA-Enterprise. +*/ + + +#define M2M_1X_PWD_MAX 41 +/*!< The maximum size of the password including the NULL termination. + It is used for RADIUS authentication in case of connecting the device to + an AP secured with WPA-Enterprise. +*/ + +#define M2M_CUST_IE_LEN_MAX 252 +/*!< Maximum size for the Information Element. +*/ + + +#define M2M_CONFIG_CMD_BASE 1 +/*!< The base value of all the Host configuration commands opcodes. +*/ +#define M2M_STA_CMD_BASE 40 +/*!< The base value of all the Station mode host commands opcodes. +*/ +#define M2M_AP_CMD_BASE 70 +/*!< The base value of all the Access Point mode host commands opcodes. +*/ +#define M2M_P2P_CMD_BASE 90 +/*!< The base value of all the P2P mode host commands opcodes. +*/ +#define M2M_OTA_CMD_BASE 100 +/*!< The base value of all the OTA mode host commands opcodes. +*/ +#define M2M_SERVER_CMD_BASE 120 +/*!< The base value of all the Power Save mode host commands codes. +*/ + + +#define WEP_40_KEY_STRING_SIZE ((uint8)10) +/*!< Indicates the WEP key size for the 40 bit string passphrase. +*/ + +#define WEP_104_KEY_STRING_SIZE ((uint8)26) +/*!< Indicates the WEP key size for the 104 bit string passphrase. +*/ +#define WEP_KEY_MAX_INDEX ((uint8)4) +/*!< Indicates the maximum key index value for WEP authentication. +*/ +#define M2M_SCAN_DEFAULT_NUM_SLOTS (2) +/*!< The default number of scan slots used by the WINC board. +*/ +#define M2M_SCAN_DEFAULT_SLOT_TIME (20) +/*!< The active scan slot default duration in ms. +*/ +#define M2M_SCAN_DEFAULT_PASSIVE_SLOT_TIME (300) +/*!< The passive scan slot default duration in ms. +*/ +#define M2M_SCAN_DEFAULT_NUM_PROBE (2) +/*!< The default number of probes per slot. +*/ +#define M2M_FASTCONNECT_DEFAULT_RSSI_THRESH (-45) +/*!< The default threshold RSSI for fast reconnection to an AP. +*/ +#define M2M_SCAN_FAIL ((uint8)1) +/*!< Indicates the WINC board has failed to perform the scan operation. +*/ +#define M2M_JOIN_FAIL ((uint8)2) +/*!< Indicates the WINC board has failed to join the BSS. +*/ +#define M2M_AUTH_FAIL ((uint8)3) +/*!< Indicates the WINC board has failed to authenticate with the AP. +*/ +#define M2M_ASSOC_FAIL ((uint8)4) +/*!< Indicates the WINC board has failed to associate with the AP. +*/ + +#define M2M_SCAN_ERR_WIFI ((sint8)-2) +/*!< Currently not used. +*/ +#define M2M_SCAN_ERR_IP ((sint8)-3) +/*!< Currently not used. +*/ +#define M2M_SCAN_ERR_AP ((sint8)-4) +/*!< Currently not used. +*/ +#define M2M_SCAN_ERR_P2P ((sint8)-5) +/*!< Currently not used. +*/ +#define M2M_SCAN_ERR_WPS ((sint8)-6) +/*!< Currently not used. +*/ + +/*======*======*======*======* + MONTIORING MODE DEFINITIONS + *======*======*======*======*/ + +#define M2M_WIFI_FRAME_TYPE_ANY 0xFF +/*!< Receive any frame type when configured as Monitor Mode. +*/ +#define M2M_WIFI_FRAME_SUB_TYPE_ANY 0xFF +/*!< Receive frames with any sub type when configured as Monitor Mode. +*/ + +/*======*======*======*======* + TLS DEFINITIONS + *======*======*======*======*/ +#define TLS_FILE_NAME_MAX 48 +/*!< Maximum length for each TLS certificate file name. +*/ +#define TLS_SRV_SEC_MAX_FILES 8 +/*!< Maximum number of certificates allowed in TLS_SRV section. +*/ +#define TLS_SRV_SEC_START_PATTERN_LEN 8 +/*!< Length of certificate struct start pattern. +*/ + +/**@}*/ + +/**@defgroup OTADEFINE Defines + * @ingroup OTAAPI + */ + /* @{ */ + +/*======*======*======*======* + OTA DEFINITIONS + *======*======*======*======*/ + +#define OTA_STATUS_VALID (0x12526285) +/*!< + Magic value in the control structure for a valid image after ROLLBACK. +*/ +#define OTA_STATUS_INVALID (0x23987718) +/*!< + Magic value in the control structure for a invalid image after ROLLBACK. +*/ +#define OTA_MAGIC_VALUE (0x1ABCDEF9) +/*!< + Magic value set at the beginning of the OTA image header. +*/ +#define OTA_SHA256_DIGEST_SIZE (32) +/*!< + SHA256 digest size in the OTA image. + The SHA256 digest is set at the beginning of image before the OTA header. +*/ + +#define OTA_SUCCESS (0) +/*!< + OTA success status. +*/ +#define OTA_ERR_WORKING_IMAGE_LOAD_FAIL ((sint8)-1) +/*!< + Failure to load the firmware image. +*/ +#define OTA_ERR_INVAILD_CONTROL_SEC ((sint8)-2) +/*!< + Control structure is being corrupted. +*/ +#define M2M_ERR_OTA_SWITCH_FAIL ((sint8)-3) +/*!< + Failure to switch to the updated image, due to this being invalid. +*/ +#define M2M_ERR_OTA_START_UPDATE_FAIL ((sint8)-4) +/*!< + Failure to start the OTA update. + This could be due to a connection failure or a problem with the integrity of the image. +*/ +#define M2M_ERR_OTA_ROLLBACK_FAIL ((sint8)-5) +/*!< + Invalid roll-back image. +*/ +#define M2M_ERR_OTA_INVAILD_FLASH_SIZE ((sint8)-6) +/*!< + The OTA Support requires 8MB flash size. This error indicates the current flash is less than 8M. +*/ +#define M2M_ERR_OTA_INVAILD_ARG ((sint8)-7) +/*!< + Invalid argument in any OTA Function +*/ +/**@}*/ + +/** +* @addtogroup WlanEnums +*/ + /**@{*/ + +/*! +@enum \ + tenuM2mReqGroup + +@brief +*/ +typedef enum{ + M2M_REQ_GROUP_MAIN = 0, + M2M_REQ_GROUP_WIFI, + M2M_REQ_GROUP_IP, + M2M_REQ_GROUP_HIF, + M2M_REQ_GROUP_OTA, + M2M_REQ_GROUP_SSL, + M2M_REQ_GROUP_SIGMA +}tenuM2mReqGroup; + +/*! +@enum \ + tenuM2mReqpkt + +@brief +*/ +typedef enum{ + M2M_REQ_CONFIG_PKT, + M2M_REQ_DATA_PKT = 0x80 /*BIT7*/ +}tenuM2mReqpkt; + +/*! +@enum \ + tenuM2mWepKeyIndex + +@brief + +*/ +typedef enum { + M2M_WIFI_WEP_KEY_INDEX_1 = ((uint8) 1), + /*!< Index 1 for WEP key Authentication */ + M2M_WIFI_WEP_KEY_INDEX_2, + /*!< Index 2 for WEP key Authentication */ + M2M_WIFI_WEP_KEY_INDEX_3, + /*!< Index 3 for WEP key Authentication */ + M2M_WIFI_WEP_KEY_INDEX_4, + /*!< Index 4 for WEP key Authentication */ +}tenuM2mWepKeyIndex; + +/*! +@enum \ + tenuM2mDefaultConnErrcode + +@brief + +*/ +typedef enum { + M2M_DEFAULT_CONN_INPROGRESS = ((sint8)-23), + /*!< Failure response due to another connection being already in progress */ + M2M_DEFAULT_CONN_FAIL, + /*!< Failure to connect to the cached network */ + M2M_DEFAULT_CONN_SCAN_MISMATCH, + /*!< Failure to find any of the cached networks in the scan results. */ + M2M_DEFAULT_CONN_EMPTY_LIST + /*!< Failure due to empty network list. */ +}tenuM2mDefaultConnErrcode; + + +/*! +@enum \ + tenuM2mConnChangedErrcode + +@brief + +*/ +typedef enum { + M2M_ERR_SCAN_FAIL = ((uint8)1), + /*!< Failure to perform the scan operation. */ + M2M_ERR_JOIN_FAIL, + /*!< Failure to join the BSS. */ + M2M_ERR_AUTH_FAIL, + /*!< Failure to authenticate with the AP. */ + M2M_ERR_ASSOC_FAIL, + /*!< Failure to associate with the AP. */ + M2M_ERR_CONN_INPROGRESS, + /*!< Failure due to another connection being in progress. */ +}tenuM2mConnChangedErrcode; + + +/*! +@enum \ + tenuM2mSetGainsErrcode + +@brief + +*/ +typedef enum { + M2M_ERR_GAIN_TABLE_INVALID = ((sint8)-10), + /*!< Failure response due to trying to use an invalid table */ + M2M_ERR_READ_GAIN_TABLE, + /*!< Failure to read gains from flash */ +}tenuM2mSetGainsErrcode; + +/*! +@enum \ + tenuM2mPwrMode + +@brief + +*/ +typedef enum { + PWR_AUTO = ((uint8) 1), + /*!< Automatic power mode. */ + PWR_LOW1, + /*!< Low power mode #1. RX current 60mA.*/ + PWR_LOW2, + /*!< Low power mode #2, RX current 55mA, sensitivity is less by 3dBm*/ + PWR_HIGH, + /*!< High power mode: RX current 100mA.*/ +}tenuM2mPwrMode; + +/*! +@enum \ + tenuM2mTxPwrLevel + +@brief + +*/ +typedef enum { + TX_PWR_HIGH = ((uint8) 1), + /*!< PPA Gain 6dbm PA Gain 18dbm */ + TX_PWR_MED, + /*!< PPA Gain 6dbm PA Gain 12dbm */ + TX_PWR_LOW, + /*!< PPA Gain 6dbm PA Gain 6dbm */ +}tenuM2mTxPwrLevel; + +/*! +@enum \ + tenuM2mConfigCmd + +@brief + This enum contains all the host commands used to configure the WINC board. + +*/ +typedef enum { + M2M_WIFI_REQ_RESTART = M2M_CONFIG_CMD_BASE, + /*!< Restart the WINC MAC layer, it's doesn't restart the IP layer. */ + M2M_WIFI_REQ_SET_MAC_ADDRESS, + /*!< Set the WINC mac address (not possible for production effused boards). */ + M2M_WIFI_REQ_CURRENT_RSSI, + /*!< Request the current connected AP RSSI. */ + M2M_WIFI_RESP_CURRENT_RSSI, + /*!< Response to M2M_WIFI_REQ_CURRENT_RSSI with the RSSI value. */ + M2M_WIFI_REQ_RESTRICT_BLE, + /*!< Request restrict ble. */ + M2M_WIFI_REQ_UNRESTRICT_BLE, + /*!< Request unrestrict ble. */ + M2M_WIFI_REQ_GET_CONN_INFO, + /*!< Request connection information. */ + M2M_WIFI_RESP_CONN_INFO, + /*!< Response to M2M_WIFI_REQ_GET_CONN_INFO with the connection information. */ + M2M_WIFI_REQ_SET_DEVICE_NAME, + /*!< Request to set WINC device name property. */ + M2M_WIFI_REQ_START_PROVISION_MODE, + /*!< Request to start provisioning mode. */ + M2M_WIFI_RESP_PROVISION_INFO, + /*!< Response to the host with the provisioning information.*/ + M2M_WIFI_REQ_STOP_PROVISION_MODE, + /*!< Request to stop provision mode. */ + M2M_WIFI_REQ_SET_SYS_TIME, + /*!< Request to set system time. */ + M2M_WIFI_REQ_ENABLE_SNTP_CLIENT, + /*!< Request to enable the simple network time protocol to get the + time from the Internet. This is required for security purposes. */ + M2M_WIFI_REQ_DISABLE_SNTP_CLIENT, + /*!< Request to disable the simple network time protocol for applications that + do not need it. */ + M2M_WIFI_RESP_MEMORY_RECOVER, + /*!< Reserved for debuging */ + M2M_WIFI_REQ_CUST_INFO_ELEMENT, + /*!< Request to add custom information to the Beacons IE. */ + M2M_WIFI_REQ_SCAN, + /*!< Request scan command. */ + M2M_WIFI_RESP_SCAN_DONE, + /*!< Response to notify scan complete. */ + M2M_WIFI_REQ_SCAN_RESULT, + /*!< Request for scan results. */ + M2M_WIFI_RESP_SCAN_RESULT, + /*!< Response to provide the scan results. */ + M2M_WIFI_REQ_SET_SCAN_OPTION, + /*!< Request to set scan options "slot time, slot number .. etc". */ + M2M_WIFI_REQ_SET_SCAN_REGION, + /*!< Request to set scan region. */ + M2M_WIFI_REQ_SET_POWER_PROFILE, + /*!< Request to set the Power Profile. */ + M2M_WIFI_REQ_SET_TX_POWER, + /*!< Request to set the TX Power. */ + M2M_WIFI_REQ_SET_BATTERY_VOLTAGE, + /*!< Request to set the Battery Voltage. */ + M2M_WIFI_REQ_SET_ENABLE_LOGS, + /*!< Request to enable logs. */ + M2M_WIFI_REQ_GET_SYS_TIME, + /*!< Request to get system time. */ + M2M_WIFI_RESP_GET_SYS_TIME, + /*!< Response to retrieve the system time. */ + M2M_WIFI_REQ_SEND_ETHERNET_PACKET, + /*!< Request to send Ethernet packet in bypass mode. */ + M2M_WIFI_RESP_ETHERNET_RX_PACKET, + /*!< Response to receive an Ethernet packet in bypass mode. */ + M2M_WIFI_REQ_SET_MAC_MCAST, + /*!< Request to set multicast filters. */ + M2M_WIFI_REQ_BLE_API_SEND, + /*!< Request to send an Encapsulated BLE API MSG */ + M2M_WIFI_RESP_BLE_API_RECV, + /*!< Response to receive an Encapsulated BLE API MSG */ + M2M_WIFI_REQ_SET_GAIN_TABLE, + /*!< Request to use Gain table from Flash */ + M2M_WIFI_RESP_SET_GAIN_TABLE, + /*!< Response to fail to use Gain table from Flash */ + M2M_WIFI_REQ_PASSIVE_SCAN, + /*!< Request a passive scan. + */ + M2M_WIFI_MAX_CONFIG_ALL +}tenuM2mConfigCmd; + +/*! +@enum \ + tenuM2mStaCmd + +@brief + This enum contains all the WINC commands while in Station mode. +*/ +typedef enum { + M2M_WIFI_REQ_CONNECT = M2M_STA_CMD_BASE, + /*!< Request to connect with an specified AP. */ + M2M_WIFI_REQ_DEFAULT_CONNECT, + /*!< Request to connect with a cached AP. */ + M2M_WIFI_RESP_DEFAULT_CONNECT, + /*!< Response for the default connect.*/ + M2M_WIFI_REQ_DISCONNECT, + /*!< Request to disconnect from the AP. */ + M2M_WIFI_RESP_CON_STATE_CHANGED, + /*!< Response to indicate a change in the connection state. */ + M2M_WIFI_REQ_SLEEP, + /*!< Request to sleep. */ + M2M_WIFI_REQ_WPS_SCAN, + /*!< Request to WPS scan. */ + M2M_WIFI_REQ_WPS, + /*!< Request to start WPS. */ + M2M_WIFI_REQ_START_WPS, + /*!< This command is for internal use by the WINC and + should not be used by the host driver. */ + M2M_WIFI_REQ_DISABLE_WPS, + /*!< Request to disable WPS. */ + M2M_WIFI_REQ_DHCP_CONF, + /*!< Response to indicate the obtained IP address.*/ + M2M_WIFI_RESP_IP_CONFIGURED, + /*!< This command is for internal use by the WINC and + should not be used by the host driver. */ + M2M_WIFI_RESP_IP_CONFLICT, + /*!< Response to indicate a conflict in obtained IP address. + The user should re attempt the DHCP request. */ + M2M_WIFI_REQ_ENABLE_MONITORING, + /*!< Request to enable monitor mode. */ + M2M_WIFI_REQ_DISABLE_MONITORING, + /*!< Request to disable monitor mode. */ + M2M_WIFI_RESP_WIFI_RX_PACKET, + /*!< Response to indicate a packet was received in monitor mode. */ + M2M_WIFI_REQ_SEND_WIFI_PACKET, + /*!< Request to send a packet in monitor mode. */ + M2M_WIFI_REQ_LSN_INT, + /*!< Request to set the listen interval. */ + M2M_WIFI_REQ_DOZE, + /*!< Request to doze */ + M2M_WIFI_REQ_GET_PRNG, + /*!< Request PRNG. */ + M2M_WIFI_RESP_GET_PRNG, + /*!< Response for PRNG. */ + M2M_WIFI_MAX_STA_ALL, +} tenuM2mStaCmd; + +/*! +@enum \ + tenuM2mApCmd + +@brief + This enum contains all the WINC commands while in AP mode. +*/ +typedef enum { + M2M_WIFI_REQ_ENABLE_AP = M2M_AP_CMD_BASE, + /*!< Request to enable AP mode. */ + M2M_WIFI_REQ_DISABLE_AP, + /*!< Request to disable AP mode. */ + M2M_WIFI_MAX_AP_ALL, +}tenuM2mApCmd; + +/*! +@enum \ + tenuM2mP2pCmd + +@brief + This enum contains all the WINC commands while in P2P mode. +*/ +typedef enum { + M2M_WIFI_REQ_P2P_INT_CONNECT = M2M_P2P_CMD_BASE, + /*!< This command is for internal use by the WINC and + should not be used by the host driver. */ + M2M_WIFI_REQ_ENABLE_P2P, + /*!< Request to enable P2P mode.*/ + M2M_WIFI_REQ_DISABLE_P2P, + /*!< Request to disable P2P mode. */ + M2M_WIFI_REQ_P2P_REPOST, + /*!< This command is for internal use by the WINC and + should not be used by the host driver. + */ + M2M_WIFI_MAX_P2P_ALL, +}tenuM2mP2pCmd; + + +/*! +@enum \ + tenuM2mServerCmd + +@brief + These commands are currently not supported. +*/ +typedef enum { + M2M_WIFI_REQ_CLIENT_CTRL = M2M_SERVER_CMD_BASE, + /*!< Currently not supported.*/ + M2M_WIFI_RESP_CLIENT_INFO, + /*!< Currently not supported.*/ + M2M_WIFI_REQ_SERVER_INIT, + /*!< Currently not supported.*/ + M2M_WIFI_MAX_SERVER_ALL +}tenuM2mServerCmd; + + + + +/*! +@enum \ + tenuM2mIpCmd + +@brief + This enum contains all the WINC commands related to IP. +*/ +typedef enum { + M2M_IP_REQ_STATIC_IP_CONF = ((uint8) 10), + /*!< Request to set static IP.*/ + M2M_IP_REQ_ENABLE_DHCP, + /*!< Request to enable DHCP.*/ + M2M_IP_REQ_DISABLE_DHCP + /*!< Request to disable DHCP.*/ +} tenuM2mIpCmd; + +/*! +@enum \ + tenuM2mSigmaCmd + +@brief + This enum contains all the WINC commands related to Sigma. +*/ +typedef enum { + M2M_SIGMA_ENABLE = ((uint8) 3), + /*!< Enable Sigma.*/ + M2M_SIGMA_TA_START, + /*!< Start the traffic agent.*/ + M2M_SIGMA_TA_STATS, + /*!< Get traffic stadistics.*/ + M2M_SIGMA_TA_RECEIVE_STOP, + /*!< Stop receiving from the traffic agent.*/ + M2M_SIGMA_ICMP_ARP, + /*!< Send ARP.*/ + M2M_SIGMA_ICMP_RX, + /*!< Receive ICMP.*/ + M2M_SIGMA_ICMP_TX, + /*!< Transmit ICMP.*/ + M2M_SIGMA_UDP_TX, + /*!< Transmit UDP.*/ + M2M_SIGMA_UDP_TX_DEFER, + /*!< Transmit UDP defer.*/ + M2M_SIGMA_SECURITY_POLICY, + /*!< Set security policy.*/ + M2M_SIGMA_SET_SYSTIME + /*!< Set system time.*/ +} tenuM2mSigmaCmd; + +/*! +@enum \ + tenuM2mSslCmd + +@brief + This enum contains WINC commands related to TLS handshake. +*/ +typedef enum{ + M2M_SSL_REQ_CERT_VERIF, + M2M_SSL_REQ_ECC, + M2M_SSL_RESP_ECC, + M2M_SSL_RSV, + M2M_SSL_REQ_WRITE_OWN_CERTS, + M2M_SSL_REQ_SET_CS_LIST, + M2M_SSL_RESP_SET_CS_LIST, + M2M_SSL_RESP_WRITE_OWN_CERTS +}tenuM2mSslCmd; + + +/*! +@enum \ + tenuM2mConnState + +@brief + This enum contains all the Wi-Fi connection states. +*/ +typedef enum { + M2M_WIFI_DISCONNECTED = 0, + /*!< Wi-Fi state is disconnected. */ + M2M_WIFI_CONNECTED, + /*!< Wi-Fi state is connected. */ + M2M_WIFI_UNDEF = 0xff + /*!< Undefined Wi-Fi State. */ +}tenuM2mConnState; + +/*! +@enum \ + tenuM2mSecType + +@brief + This enum contains all the supported Wi-Fi security types. +*/ +typedef enum { + M2M_WIFI_SEC_INVALID = 0, + /*!< Invalid security type. */ + M2M_WIFI_SEC_OPEN, + /*!< Wi-Fi network is not secured. */ + M2M_WIFI_SEC_WPA_PSK, + /*!< Wi-Fi network is secured with WPA/WPA2 personal(PSK). */ + M2M_WIFI_SEC_WEP, + /*!< Security type WEP (40 or 104) OPEN OR SHARED. */ + M2M_WIFI_SEC_802_1X + /*!< Wi-Fi network is secured with WPA/WPA2 Enterprise.IEEE802.1x user-name/password authentication. */ +}tenuM2mSecType; + + +/*! +@enum \ + tenuM2mSecType + +@brief + This enum contains all the supported Wi-Fi SSID types. +*/ +typedef enum { + SSID_MODE_VISIBLE = 0, + /*!< SSID is visible to others. */ + SSID_MODE_HIDDEN + /*!< SSID is hidden. */ +}tenuM2mSsidMode; + +/*! +@enum \ + tenuM2mScanCh + +@brief + This enum contains all the Wi-Fi RF channels. +*/ +typedef enum { + M2M_WIFI_CH_1 = ((uint8) 1), + /*!< Channel 1. */ + M2M_WIFI_CH_2, + /*!< Channel 2. */ + M2M_WIFI_CH_3, + /*!< Channel 3. */ + M2M_WIFI_CH_4, + /*!< Channel 4. */ + M2M_WIFI_CH_5, + /*!< Channel 5. */ + M2M_WIFI_CH_6, + /*!< Channel 6. */ + M2M_WIFI_CH_7, + /*!< Channel 7. */ + M2M_WIFI_CH_8, + /*!< Channel 8. */ + M2M_WIFI_CH_9, + /*!< Channel 9. */ + M2M_WIFI_CH_10, + /*!< Channel 10. */ + M2M_WIFI_CH_11, + /*!< Channel 11. */ + M2M_WIFI_CH_12, + /*!< Channel 12. */ + M2M_WIFI_CH_13, + /*!< Channel 13. */ + M2M_WIFI_CH_14, + /*!< Channel 14. */ + M2M_WIFI_CH_ALL = ((uint8) 255) +}tenuM2mScanCh; + +/*! +@enum \ + tenuM2mScanRegion + +@brief + This enum contains all the Wi-Fi channel regions. +*/ +typedef enum { + REG_CH_1 = ((uint16) 1 << 0), + /*!< Region channel 1. */ + REG_CH_2 = ((uint16) 1 << 1), + /*!< Region channel 2. */ + REG_CH_3 = ((uint16) 1 << 2), + /*!< Region channel 3. */ + REG_CH_4 = ((uint16) 1 << 3), + /*!< Region channel 4. */ + REG_CH_5 = ((uint16) 1 << 4), + /*!< Region channel 5. */ + REG_CH_6 = ((uint16) 1 << 5), + /*!< Region channel 6. */ + REG_CH_7 = ((uint16) 1 << 6), + /*!< Region channel 7. */ + REG_CH_8 = ((uint16) 1 << 7), + /*!< Region channel 8. */ + REG_CH_9 = ((uint16) 1 << 8), + /*!< Region channel 9. */ + REG_CH_10 = ((uint16) 1 << 9), + /*!< Region channel 10. */ + REG_CH_11 = ((uint16) 1 << 10), + /*!< Region channel 11. */ + REG_CH_12 = ((uint16) 1 << 11), + /*!< Region channel 12. */ + REG_CH_13 = ((uint16) 1 << 12), + /*!< Region channel 13. */ + REG_CH_14 = ((uint16) 1 << 13), + /*!< Region channel 14. */ + REG_CH_ALL = ((uint16) 0x3FFF), + /*!< Region for all channels. */ + NORTH_AMERICA = ((uint16) 0x7FF), + /*!< North America region with 11 channels*/ + EUROPE = ((uint16) 0x1FFF), + /*!u8Status == M2M_SUCCESS) + { + m2m_wifi_connect((char*)pstrProvInfo->au8SSID, (uint8)strlen(pstrProvInfo->au8SSID), pstrProvInfo->u8SecType, + pstrProvInfo->au8Password, M2M_WIFI_CH_ALL); + + printf("PROV SSID : %s\n",pstrProvInfo->au8SSID); + printf("PROV PSK : %s\n",pstrProvInfo->au8Password); + } + else + { + printf("(ERR) Provisioning Failed\n"); + } + } + break; + + default: + break; + } + } + + int main() + { + tstrWifiInitParam param; + + param.pfAppWifiCb = wifi_event_cb; + if(!m2m_wifi_init(¶m)) + { + tstrM2MAPConfig apConfig; + uint8 bEnableRedirect = 1; + + strcpy(apConfig.au8SSID, "WINC_SSID"); + apConfig.u8ListenChannel = 1; + apConfig.u8SecType = M2M_WIFI_SEC_OPEN; + apConfig.u8SsidHide = 0; + + // IP Address + apConfig.au8DHCPServerIP[0] = 192; + apConfig.au8DHCPServerIP[1] = 168; + apConfig.au8DHCPServerIP[2] = 1; + apConfig.au8DHCPServerIP[0] = 1; + + m2m_wifi_start_provision_mode(&apConfig, "atmelwincconf.com", bEnableRedirect); + + while(1) + { + m2m_wifi_handle_events(NULL); + } + } + } +@endcode +*/ +NMI_API sint8 m2m_wifi_start_provision_mode(tstrM2MAPConfig *pstrAPConfig, char *pcHttpServerDomainName, uint8 bEnableHttpRedirect); + +/*! +@fn \ + sint8 m2m_wifi_stop_provision_mode(void); + +@brief + Synchronous API for terminating provisioning mode on the WINC IC. + +@details + This function will terminate any currently active provisioning mode on the WINC IC, returning the + IC to idle. + +@return + The function returns ZERO for success and a negative value otherwise. + +@pre + An active provisioning session must be active before it is terminated through this function. +@see + m2m_wifi_start_provision_mode +*/ +NMI_API sint8 m2m_wifi_stop_provision_mode(void); + +/*! +@fn \ + sint8 m2m_wifi_get_connection_info(void); + +@brief + Asynchronous API for retrieving the WINC IC's connection status. + +@details + Requests the connection status from the WINC IC including information regarding any access + point to which it is currently connected, or any non-AP station that is connected to the WINC. + All information will be returned to the application via the Wi-Fi notifiction callback and the + event @ref M2M_WIFI_RESP_CONN_INFO. + + The connection info can be retrieved using the structure @ref tstrM2MConnInfo which contains: + - Connection Security + - Connection RSSI + - Remote MAC address + - Remote IP address + - SSID of the network (in cases where the WINC is in non-AP mode) + +@return + The function returns @ref M2M_SUCCESS if the command has been successfully queued to the WINC, + and a negative value otherwise. + +@pre + - A Wi-Fi notification callback of type @ref tpfAppWifiCb MUST be implemented and registered at + startup. Registering the callback is done through passing it to the initialization + @ref m2m_wifi_init function. + - The event @ref M2M_WIFI_RESP_CONN_INFO must be handled in the callback to receive the + requested connection info. + +@warning + - In case of WINC AP mode or P2P mode, the SSID field shall be a NULL string. + +@see + M2M_WIFI_RESP_CONN_INFO, + tstrM2MConnInfo +\section WIFIExample2 Example + The code snippet shows an example of how wi-fi connection information is retrieved . +@code + #include "m2m_wifi.h" + #include "m2m_types.h" + + void wifi_event_cb(uint8 u8WiFiEvent, void * pvMsg) + { + switch(u8WiFiEvent) + { + case M2M_WIFI_RESP_CONN_INFO: + { + tstrM2MConnInfo *pstrConnInfo = (tstrM2MConnInfo*)pvMsg; + + printf("CONNECTED AP INFO\n"); + printf("SSID : %s\n",pstrConnInfo->acSSID); + printf("SEC TYPE : %d\n",pstrConnInfo->u8SecType); + printf("Signal Strength : %d\n", pstrConnInfo->s8RSSI); + printf("Local IP Address : %d.%d.%d.%d\n", + pstrConnInfo->au8IPAddr[0] , pstrConnInfo->au8IPAddr[1], pstrConnInfo->au8IPAddr[2], pstrConnInfo->au8IPAddr[3]); + } + break; + + case M2M_WIFI_REQ_DHCP_CONF: + { + // Get the current AP information. + m2m_wifi_get_connection_info(); + } + break; + default: + break; + } + } + + int main() + { + tstrWifiInitParam param; + + param.pfAppWifiCb = wifi_event_cb; + if(!m2m_wifi_init(¶m)) + { + // connect to the default AP + m2m_wifi_default_connect(); + + while(1) + { + m2m_wifi_handle_events(NULL); + } + } + } +@endcode +*/ +NMI_API sint8 m2m_wifi_get_connection_info(void); + +/*! +@fn \ + NMI_API sint8 m2m_wifi_set_mac_address(uint8 au8MacAddress[6]); + +@brief + Synchronous API for assigning a MAC address to the WINC IC. + +@details + This function is intended to allow non-production software to assign a MAC address to the WINC IC. + +@param [in] au8MacAddress + MAC Address to be provisioned to the WINC. + +@return + The function returns @ref M2M_SUCCESS if the command has been successfully queued to the WINC, + and a negative value otherwise. + +@warning + This function is intended for development use only and not for use in production software. +*/ +NMI_API sint8 m2m_wifi_set_mac_address(uint8 au8MacAddress[6]); + +/*! +@fn \ + NMI_API sint8 m2m_wifi_wps(uint8 u8TriggerType,const char * pcPinNumber); + +@brief + Asynchronous API to engage the WINC IC's Wi-Fi Protected Setup (enrolee) function. + +@details + This function can be called to make the WINC enter WPS (Wi-Fi Protected Setup) mode. The result + is passed to the Wi-Fi notification callback with the event @ref M2M_WIFI_REQ_WPS. + +@param [in] u8TriggerType + WPS Trigger method. This may be: + - [WPS_PIN_TRIGGER](@ref WPS_PIN_TRIGGER) Push button method + - [WPS_PBC_TRIGGER](@ref WPS_PBC_TRIGGER) Pin method + +@param [in] pcPinNumber + Valid only if the u8TriggerType is WPS_PIN_TRIGGER, this parameter contains the PIN number. + The number must follow the format as given in the WSC1.0 specification. + +@return + The function returns @ref M2M_SUCCESS if the command has been successfully queued to the WINC, + and a negative value otherwise. + +@warning + This function is not supported in AP or P2P modes. + +@pre + - A Wi-Fi notification callback of type (@ref tpfAppWifiCb MUST be implemented and registered at + startup. Registering the callback is done through passing it to the + [m2m_wifi_init](@ref m2m_wifi_init). + - The event [M2M_WIFI_REQ_WPS](@ref M2M_WIFI_REQ_WPS) must be handled in the callback to receive + the WPS status. + - The WINC device MUST be in IDLE or STA mode. If AP or P2P mode is active, the WPS will not be + performed. + - The [m2m_wifi_handle_events](@ref m2m_wifi_handle_events) MUST be called to receive the responses + in the callback. + +@see + tpfAppWifiCb + m2m_wifi_init + M2M_WIFI_REQ_WPS + tenuWPSTrigger + tstrM2MWPSInfo + +\section WIFIExample3 Example + The code snippet shows an example of how wifi WPS is triggered . +@code + #include "m2m_wifi.h" + #include "m2m_types.h" + + void wifi_event_cb(uint8 u8WiFiEvent, void * pvMsg) + { + switch(u8WiFiEvent) + { + case M2M_WIFI_REQ_WPS: + { + tstrM2MWPSInfo *pstrWPS = (tstrM2MWPSInfo*)pvMsg; + if(pstrWPS->u8AuthType != 0) + { + printf("WPS SSID : %s\n",pstrWPS->au8SSID); + printf("WPS PSK : %s\n",pstrWPS->au8PSK); + printf("WPS SSID Auth Type : %s\n",pstrWPS->u8AuthType == M2M_WIFI_SEC_OPEN ? "OPEN" : "WPA/WPA2"); + printf("WPS Channel : %d\n",pstrWPS->u8Ch + 1); + + // establish Wi-Fi connection + m2m_wifi_connect((char*)pstrWPS->au8SSID, (uint8)m2m_strlen(pstrWPS->au8SSID), + pstrWPS->u8AuthType, pstrWPS->au8PSK, pstrWPS->u8Ch); + } + else + { + printf("(ERR) WPS Is not enabled OR Timed out\n"); + } + } + break; + + default: + break; + } + } + + int main() + { + tstrWifiInitParam param; + + param.pfAppWifiCb = wifi_event_cb; + if(!m2m_wifi_init(¶m)) + { + // Trigger WPS in Push button mode. + m2m_wifi_wps(WPS_PBC_TRIGGER, NULL); + + while(1) + { + m2m_wifi_handle_events(NULL); + } + } + } +@endcode +*/ + + +NMI_API sint8 m2m_wifi_ble_set_gain_table(uint8 table_idx); +/*! +@fn \ + NMI_API sint8 m2m_wifi_ble_set_gain_table(uint8 table_idx); + +@brief + Asynchronous API that notifies the WINC with the Gain Table index from Flash that should use to configure the WiFi and BLE gains. + +@return + The function returns @ref M2M_SUCCESS if the command has been successfully queued to the WINC, + and a negative value otherwise. +*/ + +NMI_API sint8 m2m_wifi_wps(uint8 u8TriggerType,const char *pcPinNumber); + +/*! +@fn \ + NMI_API sint8 m2m_wifi_wps_disable(void); + +@brief + Synchronous API that disables Wi-Fi Protected Setup mode in the WINC IC. + +@return + The function returns @ref M2M_SUCCESS if the command has been successfully queued to the WINC, + and a negative value otherwise. +*/ +NMI_API sint8 m2m_wifi_wps_disable(void); + +/*! +@fn \ + NMI_API sint8 m2m_wifi_p2p(uint8 u8Channel); + +@brief + Asynchronous API for enabling Wi-Fi Direct (P2P) mode in the WINC IC. + +@param [in] u8Channel + P2P Listen RF channel. + +@return + The function returns @ref M2M_SUCCESS if the command has been successfully queued to the WINC, + and a negative value otherwise. + +@pre + - A Wi-Fi notification callback of type @ref tpfAppWifiCb MUST be implemented and registered at + initialization. Registering the callback + is done through passing it to the @ref m2m_wifi_init. + - The events @ref M2M_WIFI_RESP_CON_STATE_CHANGED and @ref M2M_WIFI_REQ_DHCP_CONF + must be handled in the callback. + - The @ref m2m_wifi_handle_events MUST be called to receive the responses in the callback. + +@warning + - This function is not available in the WINC 3400 + - This function is not allowed in AP or STA modes. + +@see + tpfAppWifiCb + m2m_wifi_init + M2M_WIFI_RESP_CON_STATE_CHANGED + M2M_WIFI_REQ_DHCP_CONF + tstrM2mWifiStateChanged + +\section WIFIExample4 Example + The code snippet shows an example of how the p2p mode operates. +@code + #include "m2m_wifi.h" + #include "m2m_types.h" + + void wifi_event_cb(uint8 u8WiFiEvent, void * pvMsg) + { + switch(u8WiFiEvent) + { + case M2M_WIFI_RESP_CON_STATE_CHANGED: + { + tstrM2mWifiStateChanged *pstrWifiState = (tstrM2mWifiStateChanged*)pvMsg; + M2M_INFO("Wifi State :: %s :: ErrCode %d\n", pstrWifiState->u8CurrState? "CONNECTED":"DISCONNECTED",pstrWifiState->u8ErrCode); + + // Do something + } + break; + + case M2M_WIFI_REQ_DHCP_CONF: + { + uint8 *pu8IPAddress = (uint8*)pvMsg; + + printf("P2P IP Address \"%u.%u.%u.%u\"\n",pu8IPAddress[0],pu8IPAddress[1],pu8IPAddress[2],pu8IPAddress[3]); + } + break; + + default: + break; + } + } + + int main() + { + tstrWifiInitParam param; + + param.pfAppWifiCb = wifi_event_cb; + if(!m2m_wifi_init(¶m)) + { + // Trigger P2P + m2m_wifi_p2p(M2M_WIFI_CH_1); + + while(1) + { + m2m_wifi_handle_events(NULL); + } + } + } + +@endcode + +*/ +NMI_API sint8 m2m_wifi_p2p(uint8 u8Channel); + +/*! +@fn \ + NMI_API sint8 m2m_wifi_p2p_disconnect(void); + +@brief + Synchronous API to disable Wi-Fi Direct (P2P) Mode on the WINC IC. + +@return + The function returns @ref M2M_SUCCESS if the command has been successfully queued to the WINC, + and a negative value otherwise. + +@see + m2m_wifi_p2p +*/ +NMI_API sint8 m2m_wifi_p2p_disconnect(void); + +/*! +@fn \ + NMI_API sint8 m2m_wifi_enable_ap(CONST tstrM2MAPConfig* pstrM2MAPConfig); + +@brief + Asynchronous API to enable access point (AKA "hot-spot") mode on the WINC IC + +@details + The WINC IC supports the ability to operate as an access point with the limitation that: + - only 1 station may be associated at any one time + - open system and WEP are the only security suites supported. + +@param [in] pstrM2MAPConfig + A structure holding the AP configurations. + +@return + The function returns @ref M2M_SUCCESS if the command has been successfully queued to the WINC, + and a negative value otherwise. + +@warning + This function is not allowed in P2P or STA modes. + +@pre + - A Wi-Fi notification callback of type @ref tpfAppWifiCb MUST be implemented and registered at initialization. Registering the callback + is done through passing it to the [m2m_wifi_init](@ref m2m_wifi_init). + - The event @ref M2M_WIFI_REQ_DHCP_CONF must be handled in the callback. + - The @ref m2m_wifi_handle_events MUST be called to receive the responses in the callback. + +@see + tpfAppWifiCb + tenuM2mSecType + m2m_wifi_init + M2M_WIFI_REQ_DHCP_CONF + tstrM2mWifiStateChanged + tstrM2MAPConfig + +\section WIFIExample5 Example + The code snippet demonstrates how the AP mode is enabled after the driver is initialized in the application's main function and the handling + of the event @ref M2M_WIFI_REQ_DHCP_CONF, to indicate successful connection. +@code + #include "m2m_wifi.h" + #include "m2m_types.h" + + void wifi_event_cb(uint8 u8WiFiEvent, void * pvMsg) + { + switch(u8WiFiEvent) + { + case M2M_WIFI_REQ_DHCP_CONF: + { + uint8 *pu8IPAddress = (uint8*)pvMsg; + + printf("Associated STA has IP Address \"%u.%u.%u.%u\"\n",pu8IPAddress[0],pu8IPAddress[1],pu8IPAddress[2],pu8IPAddress[3]); + } + break; + + default: + break; + } + } + + int main() + { + tstrWifiInitParam param; + + param.pfAppWifiCb = wifi_event_cb; + if(!m2m_wifi_init(¶m)) + { + tstrM2MAPConfig apConfig; + + strcpy(apConfig.au8SSID, "WINC_SSID"); + apConfig.u8ListenChannel = 1; + apConfig.u8SecType = M2M_WIFI_SEC_OPEN; + apConfig.u8SsidHide = 0; + + // IP Address + apConfig.au8DHCPServerIP[0] = 192; + apConfig.au8DHCPServerIP[1] = 168; + apConfig.au8DHCPServerIP[2] = 1; + apConfig.au8DHCPServerIP[0] = 1; + + // Trigger AP + m2m_wifi_enable_ap(&apConfig); + + while(1) + { + m2m_wifi_handle_events(NULL); + } + } + } + +@endcode + +*/ +NMI_API sint8 m2m_wifi_enable_ap(CONST tstrM2MAPConfig* pstrM2MAPConfig); + +/*! +@fn \ + NMI_API sint8 m2m_wifi_disable_ap(void); + +@brief + Synchronous API to disable access point mode on the WINC IC. + +@return + The function returns @ref M2M_SUCCESS if the command has been successfully queued to the WINC, + and a negative value otherwise. + +@see + m2m_wifi_enable_ap +*/ +NMI_API sint8 m2m_wifi_disable_ap(void); + +/*! +@fn \ + NMI_API sint8 m2m_wifi_set_static_ip(tstrM2MIPConfig * pstrStaticIPConf); + +@brief + Synchronous API to manually assign a (static) IP address to the WINC IC. + +@details + Typically an infrastructure access point will be able to provide an IP address to all clients + after they associate. The WINC will request configuration via DHCP automatically after + successfully connecting to an access point. This function should only be called in the event + that the network has no DHCP server and the application knows the specifics of the network. + +@param [in] pstrStaticIPConf + Pointer to a structure holding the static IP Configurations (IP, Gateway, subnet mask and + DNS address). + +@return + The function returns @ref M2M_SUCCESS if the command has been successfully queued to the WINC, + and a negative value otherwise. + +@pre + The application must first call @ref m2m_wifi_enable_dhcp to request that DHCP functionality is + disabled prior to calling this function. + +@warning + Exercise caution using this function. DHCP is the preferred method for configuring IP addresses. + +@see + tstrM2MIPConfig +*/ +NMI_API sint8 m2m_wifi_set_static_ip(tstrM2MIPConfig * pstrStaticIPConf); + +/*! +@fn \ + NMI_API sint8 m2m_wifi_request_dhcp_client(void); + +@brief + Legacy (deprecated) Asynchronous API for starting a DHCP client on the WINC IC. + +@details + This is a legacy API and is no longer supported. Calls to this API will not result in any + changes being made to the state of the WINC IC. + +@return + This function always returns @ref M2M_SUCCESS. + +@warning + - This function has been deprecated. DHCP is used automatically when the WINC IC connects. +*/ +NMI_API sint8 m2m_wifi_request_dhcp_client(void); + +/*! +@fn \ + NMI_API sint8 m2m_wifi_request_dhcp_server(uint8* addr); + +@brief + Legacy (deprecated) Asynchronous function to start a DHCP client on the WINC IC. + +@details + This is a legacy API and is no longer supported. Calls to this API will not result in any + changes being made to the state of the WINC IC. + +@param [in] addr The address to issue to a connected client (only one client is supported) + +@return + This function always returns @ref M2M_SUCCESS. + +@warning + - This function has been deprecated. DHCP is used automatically when the WINC IC connects. +*/ +NMI_API sint8 m2m_wifi_request_dhcp_server(uint8* addr); + +/*! +@fn \ + NMI_API sint8 m2m_wifi_enable_dhcp(uint8 u8DhcpEn ); + +@brief + Asynchronous function to control the DHCP client functionality within the WINC IC. + +@details + This function allows the application to control the behaviour of the DHCP client function within + the WINC IC once it has associated with an access point. DHCP client functionality is enabled by + default. + +@param [in] u8DhcpEn + The state of the DHCP client feature after successful association with an access point: + - 0: DHCP client will be disabled after connection. + - 1: DHCP client will be enabled after connection. + +@return + The function SHALL return 0 for success and a negative value otherwise. + +@warning + - DHCP client is enabled by default + - This Function should be called to disable DHCP client operation before using @ref m2m_wifi_set_static_ip + +@see + m2m_wifi_set_static_ip() +*/ +NMI_API sint8 m2m_wifi_enable_dhcp(uint8 u8DhcpEn ); + + +/*! +@fn \ + sint8 m2m_wifi_set_scan_options(tstrM2MScanOption* ptstrM2MScanOption) + +@brief + Synchronous API for configuring the behaviour of the WINC IC's network scanning functions. + +@details + This function allows the application to tune the scanning behaviour of the WINC IC using the + parameters described in @ref tstrM2MScanOption. + +@param [in] ptstrM2MScanOption; + Pointer to the structure holding the Scan Parameters. + +@return + The function returns @ref M2M_SUCCESS if the command has been successfully queued to the WINC, + and a negative value otherwise. + +@see + tenuM2mScanCh + m2m_wifi_request_scan + tstrM2MScanOption +*/ +NMI_API sint8 m2m_wifi_set_scan_options(tstrM2MScanOption* ptstrM2MScanOption); + +/*! +@fn \ + sint8 m2m_wifi_set_scan_region(uint16 ScanRegion) + +@brief + Synchronous API for configuring the regulatory restrictions that may affect the WINC ICs + scanning behaviour. + +@details + This function sets a property called the scan region, a parameter that affects the range of + channels that the WINC IC may legally scan given a geographic region. + +@param [in] ScanRegion + +@return + The function returns @ref M2M_SUCCESS if the command has been successfully queued to the WINC, + and a negative value otherwise. + +@see + tenuM2mScanRegion + m2m_wifi_request_scan + +*/ +NMI_API sint8 m2m_wifi_set_scan_region(uint16 ScanRegion); + +/*! +@fn \ + NMI_API sint8 m2m_wifi_request_scan(uint8 ch); + +@brief + Asynchronous API to request the WINC IC perform a scan for networks. + +@details + Scan statuses are delivered to the application via the Wi-Fi event callback (@ref tpfAppWifiCb) in + three stages. The first step involves the event @ref M2M_WIFI_RESP_SCAN_DONE which, if successful, + provides the number of detected networks (access points). The application must then read the list + of access points via multiple calls to the asynchronous @ref m2m_wifi_req_scan_result API. For + each call to this function, the application will receive (step three) the event + @ref M2M_WIFI_RESP_SCAN_RESULT. + +@param [in] ch + RF Channel ID for SCAN operation. It should be set according to tenuM2mScanCh, with a + value of @ref M2M_WIFI_CH_ALL to scan all channels. + +@return + The function returns @ref M2M_SUCCESS if the command has been successfully queued to the WINC, + and a negative value otherwise. + +@warning + This API is valid only for STA mode, it may be called regardless of connection state (connected + or disconnected). + +@pre + - A Wi-Fi notification callback of type @ref tpfAppWifiCb MUST be implemented and registered at + initialization. Registration of the callback is done via @ref m2m_wifi_init. + - The events @ref M2M_WIFI_RESP_SCAN_DONE and @ref M2M_WIFI_RESP_SCAN_RESULT must be handled in + the (tpfAppWifiCb) callback. + - The @ref m2m_wifi_handle_events function must be called to receive the responses in the + callback. + +@see M2M_WIFI_RESP_SCAN_DONE +@see M2M_WIFI_RESP_SCAN_RESULT +@see tpfAppWifiCb +@see tstrM2mWifiscanResult +@see tenuM2mScanCh +@see m2m_wifi_init +@see m2m_wifi_handle_events +@see m2m_wifi_req_scan_result + +\section WIFIExample6 Example + The code snippet demonstrates an example of how the scan request is called from the application's main function and the handling of + the events received in response. +@code + + #include "m2m_wifi.h" + #include "m2m_types.h" + + void wifi_event_cb(uint8 u8WiFiEvent, void * pvMsg) + { + static uint8 u8ScanResultIdx = 0; + + switch(u8WiFiEvent) + { + case M2M_WIFI_RESP_SCAN_DONE: + { + tstrM2mScanDone *pstrInfo = (tstrM2mScanDone*)pvMsg; + + printf("Num of AP found %d\n",pstrInfo->u8NumofCh); + if(pstrInfo->s8ScanState == M2M_SUCCESS) + { + u8ScanResultIdx = 0; + if(pstrInfo->u8NumofCh >= 1) + { + m2m_wifi_req_scan_result(u8ScanResultIdx); + u8ScanResultIdx ++; + } + else + { + printf("No AP Found Rescan\n"); + m2m_wifi_request_scan(M2M_WIFI_CH_ALL); + } + } + else + { + printf("(ERR) Scan fail with error <%d>\n",pstrInfo->s8ScanState); + } + } + break; + + case M2M_WIFI_RESP_SCAN_RESULT: + { + tstrM2mWifiscanResult *pstrScanResult =(tstrM2mWifiscanResult*)pvMsg; + uint8 u8NumFoundAPs = m2m_wifi_get_num_ap_found(); + + printf(">>%02d RI %d SEC %s CH %02d BSSID %02X:%02X:%02X:%02X:%02X:%02X SSID %s\n", + pstrScanResult->u8index,pstrScanResult->s8rssi, + pstrScanResult->u8AuthType, + pstrScanResult->u8ch, + pstrScanResult->au8BSSID[0], pstrScanResult->au8BSSID[1], pstrScanResult->au8BSSID[2], + pstrScanResult->au8BSSID[3], pstrScanResult->au8BSSID[4], pstrScanResult->au8BSSID[5], + pstrScanResult->au8SSID); + + if(u8ScanResultIdx < u8NumFoundAPs) + { + // Read the next scan result + m2m_wifi_req_scan_result(index); + u8ScanResultIdx ++; + } + } + break; + default: + break; + } + } + + int main() + { + tstrWifiInitParam param; + + param.pfAppWifiCb = wifi_event_cb; + if(!m2m_wifi_init(¶m)) + { + // Scan all channels + m2m_wifi_request_scan(M2M_WIFI_CH_ALL); + + while(1) + { + m2m_wifi_handle_events(NULL); + } + } + } + +@endcode +*/ +NMI_API sint8 m2m_wifi_request_scan(uint8 ch); + +/*! +@fn \ + sint8 m2m_wifi_request_scan_passive(uint8 ch); + +@param [in] ch + RF Channel ID for SCAN operation. It should be set according to tenuM2mScanCh, with a + value of @ref M2M_WIFI_CH_ALL to scan all channels. + +@warning + This function is not allowed in P2P or AP modes. It works only for STA mode (both connected or disconnected states). + +@pre + - A Wi-Fi notification callback of type @ref tpfAppWifiCb MUST be implemented and registered at initialization. Registering the callback + is done through passing it to the @ref m2m_wifi_init. + - The events @ref M2M_WIFI_RESP_SCAN_DONE and @ref M2M_WIFI_RESP_SCAN_RESULT. + must be handled in the callback. + - The @ref m2m_wifi_handle_events function MUST be called to receive the responses in the callback. + +@see m2m_wifi_request_scan +@see M2M_WIFI_RESP_SCAN_DONE +@see M2M_WIFI_RESP_SCAN_RESULT +@see tpfAppWifiCb +@see tstrM2MScanOption +@see tstrM2mWifiscanResult +@see tenuM2mScanCh +@see m2m_wifi_init +@see m2m_wifi_handle_events +@see m2m_wifi_req_scan_result + +@return + The function returns @ref M2M_SUCCESS for successful operations and a negative value otherwise. +*/ +sint8 m2m_wifi_request_scan_passive(uint8 ch); + +/*! +@fn NMI_API uint8 m2m_wifi_get_num_ap_found(void); + +@brief + Synchronous API to retrieve the number of AP's found during the last scan operation. + +@details + This function allows the application to recover the number of access points discovered during + the most recent scan activity. This is achieved via a global variable in the WINC driver that + is populated when receiving the M2M_WIFI_RESP_SCAN_DONE event. + +@return + Return the number of AP's found in the last Scan Request. + +@see + m2m_wifi_request_scan + M2M_WIFI_RESP_SCAN_DONE + M2M_WIFI_RESP_SCAN_RESULT + +@pre + - m2m_wifi_request_scan must be called first to ensure up to date results are available. + +@warning + - This function must be called only in the wi-fi callback function when the events + @ref M2M_WIFI_RESP_SCAN_DONE or @ref M2M_WIFI_RESP_SCAN_RESULT are received. Calling this + function in any other place may result in undefined/outdated numbers. + +\section WIFIExample7 Example + The code snippet demonstrates an example of how the scan request is called from the application's main function and the handling of + the events received in response. +@code + #include "m2m_wifi.h" + #include "m2m_types.h" + + void wifi_event_cb(uint8 u8WiFiEvent, void * pvMsg) + { + static uint8 u8ScanResultIdx = 0; + + switch(u8WiFiEvent) + { + case M2M_WIFI_RESP_SCAN_DONE: + { + tstrM2mScanDone *pstrInfo = (tstrM2mScanDone*)pvMsg; + + printf("Num of AP found %d\n",pstrInfo->u8NumofCh); + if(pstrInfo->s8ScanState == M2M_SUCCESS) + { + u8ScanResultIdx = 0; + if(pstrInfo->u8NumofCh >= 1) + { + m2m_wifi_req_scan_result(u8ScanResultIdx); + u8ScanResultIdx ++; + } + else + { + printf("No AP Found Rescan\n"); + m2m_wifi_request_scan(M2M_WIFI_CH_ALL); + } + } + else + { + printf("(ERR) Scan fail with error <%d>\n",pstrInfo->s8ScanState); + } + } + break; + + case M2M_WIFI_RESP_SCAN_RESULT: + { + tstrM2mWifiscanResult *pstrScanResult =(tstrM2mWifiscanResult*)pvMsg; + uint8 u8NumFoundAPs = m2m_wifi_get_num_ap_found(); + + printf(">>%02d RI %d SEC %s CH %02d BSSID %02X:%02X:%02X:%02X:%02X:%02X SSID %s\n", + pstrScanResult->u8index,pstrScanResult->s8rssi, + pstrScanResult->u8AuthType, + pstrScanResult->u8ch, + pstrScanResult->au8BSSID[0], pstrScanResult->au8BSSID[1], pstrScanResult->au8BSSID[2], + pstrScanResult->au8BSSID[3], pstrScanResult->au8BSSID[4], pstrScanResult->au8BSSID[5], + pstrScanResult->au8SSID); + + if(u8ScanResultIdx < u8NumFoundAPs) + { + // Read the next scan result + m2m_wifi_req_scan_result(index); + u8ScanResultIdx ++; + } + } + break; + default: + break; + } + } + + int main() + { + tstrWifiInitParam param; + + param.pfAppWifiCb = wifi_event_cb; + if(!m2m_wifi_init(¶m)) + { + // Scan all channels + m2m_wifi_request_scan(M2M_WIFI_CH_ALL); + + while(1) + { + m2m_wifi_handle_events(NULL); + } + } + } +@endcode +*/ +NMI_API uint8 m2m_wifi_get_num_ap_found(void); + +/*! +@fn NMI_API sint8 m2m_wifi_req_scan_result(uint8 index); + +@brief + Asynchronous API to request the information of an access point discovered via scanning. + +@details + This function allows the information of any discovered access point to be retrieved. When a + scan is completed, the application is informed of the number of networks (access points) + discovered. Calling this function with an index, N, will return the information for the Nth + access point. The information will be returned to the application via a + @ref M2M_WIFI_RESP_SCAN_RESULT event, and the response data may be obtained through casting + the pointer (pvMsg) to @ref tstrM2mWifiscanResult. + +@param [in] index + Index for the requested result, the index range start from 0 till number of AP's found + +@return + The function returns @ref M2M_SUCCESS if the command has been successfully queued to the WINC, + and a negative value otherwise. + +@see + tstrM2mWifiscanResult + m2m_wifi_get_num_ap_found + m2m_wifi_request_scan + +@pre + - @ref m2m_wifi_request_scan must be called first to ensure up to date results are available. + - A Wi-Fi notification callback of type @ref tpfAppWifiCb must be implemented and registered + in order to receive scan data after calling this function. Registration of the callback + is done via the @ref m2m_wifi_init function. + - The event @ref M2M_WIFI_RESP_SCAN_RESULT must be handled in the callback to receive the + requested connection information. + +@warning + - This API is valid only for STA mode, it may be called regardless of connection state (connected + or disconnected). + - Calling this function without first issuing a scan request may lead to stale data being + recovered. + - Application code should refrain from introducing significant delays between issuing the scan + request and scan result requests. + +\section WIFIExample8 Example + The code snippet demonstrates an example of how the scan request is called from the application's main function and the handling of + the events received in response. +@code + #include "m2m_wifi.h" + #include "m2m_types.h" + + void wifi_event_cb(uint8 u8WiFiEvent, void * pvMsg) + { + static uint8 u8ScanResultIdx = 0; + + switch(u8WiFiEvent) + { + case M2M_WIFI_RESP_SCAN_DONE: + { + tstrM2mScanDone *pstrInfo = (tstrM2mScanDone*)pvMsg; + + printf("Num of AP found %d\n",pstrInfo->u8NumofCh); + if(pstrInfo->s8ScanState == M2M_SUCCESS) + { + u8ScanResultIdx = 0; + if(pstrInfo->u8NumofCh >= 1) + { + m2m_wifi_req_scan_result(u8ScanResultIdx); + u8ScanResultIdx ++; + } + else + { + printf("No AP Found Rescan\n"); + m2m_wifi_request_scan(M2M_WIFI_CH_ALL); + } + } + else + { + printf("(ERR) Scan fail with error <%d>\n",pstrInfo->s8ScanState); + } + } + break; + + case M2M_WIFI_RESP_SCAN_RESULT: + { + tstrM2mWifiscanResult *pstrScanResult =(tstrM2mWifiscanResult*)pvMsg; + uint8 u8NumFoundAPs = m2m_wifi_get_num_ap_found(); + + printf(">>%02d RI %d SEC %s CH %02d BSSID %02X:%02X:%02X:%02X:%02X:%02X SSID %s\n", + pstrScanResult->u8index,pstrScanResult->s8rssi, + pstrScanResult->u8AuthType, + pstrScanResult->u8ch, + pstrScanResult->au8BSSID[0], pstrScanResult->au8BSSID[1], pstrScanResult->au8BSSID[2], + pstrScanResult->au8BSSID[3], pstrScanResult->au8BSSID[4], pstrScanResult->au8BSSID[5], + pstrScanResult->au8SSID); + + if(u8ScanResultIdx < u8NumFoundAPs) + { + // Read the next scan result + m2m_wifi_req_scan_result(index); + u8ScanResultIdx ++; + } + } + break; + default: + break; + } + } + + int main() + { + tstrWifiInitParam param; + + param.pfAppWifiCb = wifi_event_cb; + if(!m2m_wifi_init(¶m)) + { + // Scan all channels + m2m_wifi_request_scan(M2M_WIFI_CH_ALL); + + while(1) + { + m2m_wifi_handle_events(NULL); + } + } + } + +@endcode +*/ +NMI_API sint8 m2m_wifi_req_scan_result(uint8 index); + +/*! +@fn NMI_API sint8 m2m_wifi_req_curr_rssi(void); + +@brief + Asynchronous API to request the current Receive Signal Strength (RSSI) of the current connection. + +@details + This function will result in the application receiving the RSSI via a + @ref M2M_WIFI_RESP_CURRENT_RSSI event. + +@return + The function returns @ref M2M_SUCCESS if the command has been successfully queued to the WINC, + and a negative value otherwise. + +@pre + - A Wi-Fi notification callback of type @ref tpfAppWifiCb MUST be implemented and registered + during initialization. Registration of the callback is done via the + [m2m_wifi_init](@ref m2m_wifi_init) API. + - The event @ref M2M_WIFI_RESP_CURRENT_RSSI must be handled in the callback. + +\section WIFIExample9 Example + The code snippet demonstrates how the RSSI request is called in the application's main function and the handling of event received in the callback. +@code + #include "m2m_wifi.h" + #include "m2m_types.h" + + void wifi_event_cb(uint8 u8WiFiEvent, void * pvMsg) + { + static uint8 u8ScanResultIdx = 0; + + switch(u8WiFiEvent) + { + case M2M_WIFI_RESP_CURRENT_RSSI: + { + sint8 *rssi = (sint8*)pvMsg; + M2M_INFO("ch rssi %d\n",*rssi); + } + break; + default: + break; + } + } + + int main() + { + tstrWifiInitParam param; + + param.pfAppWifiCb = wifi_event_cb; + if(!m2m_wifi_init(¶m)) + { + // Scan all channels + m2m_wifi_req_curr_rssi(); + + while(1) + { + m2m_wifi_handle_events(NULL); + } + } + } + +@endcode +*/ +NMI_API sint8 m2m_wifi_req_curr_rssi(void); + +/*! +@fn NMI_API sint8 m2m_wifi_req_restrict_ble(void); + +@brief + Asynchronous API to request restricting of BLE functionality by placing the BLE processor in a low power state. + It is recommended to do this if it is know that BLE functionality will not be used for any significant length of time. + +@return + The function returns @ref M2M_SUCCESS if the command has been successfully queued to the WINC, + and a negative value otherwise. + +@pre + - A Wi-Fi notification callback of type @ref tpfAppWifiCb MUST be implemented and registered + during initialization. Registration of the callback is done via the + [m2m_wifi_init](@ref m2m_wifi_init) API. + +*/ +NMI_API sint8 m2m_wifi_req_restrict_ble(void); + +/*! +@fn NMI_API sint8 m2m_wifi_req_unrestrict_ble(void); + +@brief + Asynchronous API to request un-restricting of BLE functionality by reverting the BLE processor to full power mode. + +@return + The function returns @ref M2M_SUCCESS if the command has been successfully queued to the WINC, + and a negative value otherwise. + +@pre + - A Wi-Fi notification callback of type @ref tpfAppWifiCb MUST be implemented and registered + during initialization. Registration of the callback is done via the + [m2m_wifi_init](@ref m2m_wifi_init) API. + +*/ +NMI_API sint8 m2m_wifi_req_unrestrict_ble(void); + +/*! +@fn NMI_API sint8 m2m_wifi_get_otp_mac_address(uint8 *pu8MacAddr, uint8 * pu8IsValid); + +@brief + Synchronous API to query the MAC address programmed into the WINC ICs OTP memory + +@details + This function attempts to read the device's MAC address from the One Time Programmable (OTP) + memory on the IC. The presence (yes or no) of a MAC address in the OTP memory and, in the case + of it being present, its value are returned via RAM pointed to by the input arguments. + +@param [out] pu8MacAddr + Output MAC address buffer 6 bytes in size. This is valid only if *pu8Valid equals 1. + +@param [out] pu8IsValid + A boolean value set by the callee to indicate the validity of pu8MacAddr in OTP. If no MAC has + been programmed in the OTP the value of this parameter will be zero; otherwise it will be + non-zero. + +@return + The function returns @ref M2M_SUCCESS for success and a negative value otherwise. + +@see + m2m_wifi_get_mac_address + +*/ +NMI_API sint8 m2m_wifi_get_otp_mac_address(uint8 *pu8MacAddr, uint8 * pu8IsValid); + +/*! +@fn NMI_API sint8 m2m_wifi_get_mac_address(uint8 *pu8MacAddr) + +@brief + Synchronous API to retrieve the MAC address currently in use on the device. + +@details + This function obtains the MAC address that is currently in use by the device. If the function + returns with @ref M2M_SUCCESS then the content of the memory referenced by pu8MacAddr will be + populated with the 6 byte MAC address; otherwise, that memory will be left unchanged. + +@param [out] pu8MacAddr + Pointer to a buffer in memory containing a 6-byte MAC address (provided function returns + MEM_SUCCESS) + +@return + The function returns @ref M2M_SUCCESS for successful operation and a negative value otherwise. + +@see + m2m_wifi_get_otp_mac_address +*/ +NMI_API sint8 m2m_wifi_get_mac_address(uint8 *pu8MacAddr); + +/*! +@fn NMI_API sint8 m2m_wifi_set_sleep_mode(uint8 PsTyp, uint8 BcastEn); + +@brief + Synchronous API to set the power-save mode of the WINC IC. + +@param [in] PsTyp + Desired power saving mode. Supported types are defined in @ref tenuPowerSaveModes. + +@param [in] BcastEn + Broadcast reception enable flag. + - If set to 1, the WINC IC will wake for each DTIM beacon to ensure broadcast traffic can be + received. + - If set to 0, the WINC IC will not wakeup at the DTIM beacon, instead it will wake every N + beacon periods as per the negotiated Listen Interval. + +@return + The function returns @ref M2M_SUCCESS for successful operation and a negative value otherwise. + +@see + tenuPowerSaveModes + m2m_wifi_get_sleep_mode +*/ +NMI_API sint8 m2m_wifi_set_sleep_mode(uint8 PsTyp, uint8 BcastEn); + +/*! +@fn NMI_API sint8 m2m_wifi_request_sleep(uint32 u32SlpReqTime); + +@brief + Asynchronous API to place the WINC IC into sleep mode for a specified period of time. + +@details + This function allows a WINC IC that is running in M2M_PS_MANUAL mode to be placed into sleep + state for a specified period of time (measured in milliseconds). + +@param [in] u32SlpReqTime + The time in ms that the WINC IC should sleep for + +@return + The function returns @ref M2M_SUCCESS for successful operation and a negative value otherwise. + +@warning + - This API is currently unsupported on the WINC3400 + +@see + tenuPowerSaveModes + m2m_wifi_set_sleep_mode +*/ +NMI_API sint8 m2m_wifi_request_sleep(uint32 u32SlpReqTime); + +/*! +@fn NMI_API uint8 m2m_wifi_get_sleep_mode(void); + +@brief + Synchronous API to retrieve the current power save mode of the WINC IC. + +@return + The current operating power saving mode. The value will be one of those from the enumerated type + @ref tenuPowerSaveModes. + +@see + tenuPowerSaveModes + m2m_wifi_set_sleep_mode +*/ +NMI_API uint8 m2m_wifi_get_sleep_mode(void); + +#if 0 +/* + * These two functions are for a mode in which two WINC ICs communicate with each other + * via probe request and probe response frames. This mode is not supported in WINC fw. + */ +NMI_API sint8 m2m_wifi_req_client_ctrl(uint8 cmd); +NMI_API sint8 m2m_wifi_req_server_init(uint8 ch); +#endif + +/*! +@fn NMI_API sint8 m2m_wifi_set_device_name(uint8 *pu8DeviceName, uint8 u8DeviceNameLength); + +@brief + Asynchronous API to set the Wi-Fi Direct "Device Name" of the WINC IC + +@param [in] pu8DeviceName + Buffer holding the device name. + +@param [in] u8DeviceNameLength + Length of the device name. Should not exceed the maximum device name's length M2M_DEVICE_NAME_MAX. + +@return + The function returns @ref M2M_SUCCESS if the command has been successfully queued to the WINC, + and a negative value otherwise. +*/ +NMI_API sint8 m2m_wifi_set_device_name(uint8 *pu8DeviceName, uint8 u8DeviceNameLength); + +/*! +@fn NMI_API sint8 m2m_wifi_set_lsn_int(tstrM2mLsnInt * pstrM2mLsnInt); + +@brief + Asynchronous API to set Wi-Fi listen interval for power save operation. + +@param [in] pstrM2mLsnInt + Structure holding the listen interval configurations. + +@return + The function returns @ref M2M_SUCCESS if the command has been successfully queued to the WINC, + and a negative value otherwise. + +@pre + The function @ref m2m_wifi_set_sleep_mode shall be called first + +@see + - tstrM2mLsnInt + - m2m_wifi_set_sleep_mode +*/ +NMI_API sint8 m2m_wifi_set_lsn_int(tstrM2mLsnInt *pstrM2mLsnInt); + +/*! +@fn NMI_API sint8 m2m_wifi_enable_monitoring_mode(tstrM2MWifiMonitorModeCtrl *, uint8 *, uint16 , uint16); + +@brief + Asynchronous call to enable Wi-Fi monitoring (promiscuous receive) mode. + +@details + This function places the reciver into a mode where all frames (or those matching a set of filter + criteria) received on air are passed to the application. + + A dedicated callback function, @ref tpfAppMonCb, must be registered to handle frames received in + promiscuous mode. This is done via an instance of a @ref tstrWifiInitParam structure and a call to + the @ref m2m_wifi_init function. + +@param [in] pstrMtrCtrl + Pointer to @ref tstrM2MWifiMonitorModeCtrl structure holding the Filtering parameters. + +@param [in] pu8PayloadBuffer + Pointer to a Buffer allocated by the application. The buffer SHALL hold the Data field of + the WIFI RX Packet (Or a part from it). If it is set to NULL, the WIFI data payload will + be discarded by the monitoring driver. + +@param [in] u16BufferSize + The total size of the pu8PayloadBuffer in bytes. + +@param [in] u16DataOffset + Starting offset in the DATA FIELD of the received WIFI packet. The application may be interested + in reading specific information from the received packet. It must assign the offset to the starting + position of it relative to the DATA payload start.\n + \e Example, \e if \e the \e SSID \e is \e needed \e to \e be \e read \e from \e a \e PROBE \e REQ + \e packet, \e the \e u16Offset \e MUST \e be \e set \e to \e 0. + +@return + The function returns @ref M2M_SUCCESS if the command has been successfully queued to the WINC, + and a negative value otherwise. + +@warning + This mode available as sniffer ONLY, you can not be connected in any modes (Station, Access Point, + or P2P). + + @see + - tstrM2MWifiMonitorModeCtrl + - tstrM2MWifiRxPacketInfo + - tstrWifiInitParam + - tenuM2mScanCh + - m2m_wifi_disable_monitoring_mode + +\section WIFIExample10 Example + The example demonstrates the main function where-by the monitoring enable function is called after + the initialization of the driver and the packets are handled in the callback function. + +@code + #include "m2m_wifi.h" + #include "m2m_types.h" + + //Declare receive buffer + uint8 gmgmt[1600]; + + //Callback functions + void wifi_cb(uint8 u8WiFiEvent, void * pvMsg) + { + ; + } + + void wifi_monitoring_cb(tstrM2MWifiRxPacketInfo *pstrWifiRxPacket, uint8 *pu8Payload, uint16 u16PayloadSize) + { + if((NULL != pstrWifiRxPacket) && (0 != u16PayloadSize)) { + if(MANAGEMENT == pstrWifiRxPacket->u8FrameType) { + M2M_INFO("***# MGMT PACKET #***\n"); + } else if(DATA_BASICTYPE == pstrWifiRxPacket->u8FrameType) { + M2M_INFO("***# DATA PACKET #***\n"); + } else if(CONTROL == pstrWifiRxPacket->u8FrameType) { + M2M_INFO("***# CONTROL PACKET #***\n"); + } + } + } + + int main() + { + //Register wifi_monitoring_cb + tstrWifiInitParam param; + param.pfAppWifiCb = wifi_cb; + param.pfAppMonCb = wifi_monitoring_cb; + + nm_bsp_init(); + + if(!m2m_wifi_init(¶m)) { + //Enable Monitor Mode with filter to receive all data frames on channel 1 + tstrM2MWifiMonitorModeCtrl strMonitorCtrl = {0}; + strMonitorCtrl.u8ChannelID = M2M_WIFI_CH_1; + strMonitorCtrl.u8FrameType = DATA_BASICTYPE; + strMonitorCtrl.u8FrameSubtype = M2M_WIFI_FRAME_SUB_TYPE_ANY; //Receive any subtype of data frame + m2m_wifi_enable_monitoring_mode(&strMonitorCtrl, gmgmt, sizeof(gmgmt), 0); + + while(1) { + m2m_wifi_handle_events(NULL); + } + } + return 0; + } +@endcode +*/ +NMI_API sint8 m2m_wifi_enable_monitoring_mode(tstrM2MWifiMonitorModeCtrl *pstrMtrCtrl, uint8 *pu8PayloadBuffer, + uint16 u16BufferSize, uint16 u16DataOffset); + +/*! +@fn NMI_API sint8 m2m_wifi_disable_monitoring_mode(void); + +@brief + Asynchronous API to disable Wi-Fi monitoring (promiscuous receive) mode. + +@return + The function returns @ref M2M_SUCCESS if the command has been successfully queued to the WINC, + and a negative value otherwise. + +@see + m2m_wifi_enable_monitoring_mode + */ +NMI_API sint8 m2m_wifi_disable_monitoring_mode(void); + +/*! +@fn NMI_API sint8 m2m_wifi_send_wlan_pkt(uint8 *, uint16, uint16); + +@brief + Asynchronous API to queue a raw Wi-Fi packet for transmission by the WINC IC. + +@param [in] pu8WlanPacket + Pointer to a buffer holding the whole WIFI frame. + +@param [in] u16WlanHeaderLength + The size of the WIFI packet header ONLY. + +@param [in] u16WlanPktSize + The size of the whole bytes in packet. + +@return + The function returns @ref M2M_SUCCESS if the command has been successfully queued to the WINC, + and a negative value otherwise. + +@see + - m2m_wifi_enable_monitoring_mode + - m2m_wifi_disable_monitoring_mode + +@warning + This function is only available in builds supporting monitoring mode. +*/ +NMI_API sint8 m2m_wifi_send_wlan_pkt(uint8 *pu8WlanPacket, uint16 u16WlanHeaderLength, uint16 u16WlanPktSize); + +/*! +@fn NMI_API sint8 m2m_wifi_send_ethernet_pkt(uint8* pu8Packet,uint16 u16PacketSize) + +@brief + Asynchronous API to queue an Ethernet packet for transmission by the WINC IC. + +@param [in] pu8Packet + Pointer to a buffer holding the whole Ethernet frame. + +@param [in] u16PacketSize + The size of the whole bytes in packet. + +@return + The function returns @ref M2M_SUCCESS if the command has been successfully queued to the WINC, + and a negative value otherwise. + +@see + - m2m_wifi_enable_monitoring_mode + - m2m_wifi_disable_monitoring_mode + +@warning + This function is only available in builds supporting monitoring mode. +*/ +NMI_API sint8 m2m_wifi_send_ethernet_pkt(uint8* pu8Packet,uint16 u16PacketSize); + +/*! +@fn NMI_API sint8 m2m_wifi_enable_sntp(uint8); + +@brief + Asynchronous API to enable or disable the SNTP client running on the WINC IC. + +@details + The SNTP client is enabled by default during chip initialisation. This function can be used to + disable or subsequently re-enable the service. + + The service is capable of syncrhonising the WINC's system clock to the UTC time from a well-known + (and trusted) time server, for example "time.nist.gov". By default the SNTP client will update the + system time once every 24 hours. The ability to track the time accurately is important for various + applications such as checking expiry of X509 certificates during TLS session establishment. + + It is highly recommended to leave SNTP enabled if there is no alternative source of timing + information. For systems including an RTC device, SNTP may not be needed and the WINC IC's time + may be set using the @ref m2m_wifi_set_sytem_time function. + +@param [in] bEnable + Enables or disables the SNTP service + - '0' : disable SNTP + - '1' : enable SNTP + +@return + The function returns @ref M2M_SUCCESS if the command has been successfully queued to the WINC, + and a negative value otherwise. + +@see m2m_wifi_set_sytem_time + */ +NMI_API sint8 m2m_wifi_enable_sntp(uint8 bEnable); + +/*! +@fn NMI_API sint8 m2m_wifi_set_sytem_time(uint32); + +@brief + Asynchronous function for setting the system time within the WINC IC. + +@param [in] u32UTCSeconds + UTC value in seconds. + +@return + The function returns @ref M2M_SUCCESS if the command has been successfully queued to the WINC, + and a negative value otherwise. + +@see + - m2m_wifi_enable_sntp + - tstrSystemTime + +@note + If there is an RTC on the host MCU, the SNTP may be disabled and the host may set the system + time within the firmware using the API @ref m2m_wifi_set_sytem_time. + */ +NMI_API sint8 m2m_wifi_set_sytem_time(uint32 u32UTCSeconds); + +/*! +@fn NMI_API sint8 m2m_wifi_get_sytem_time(void); + +@brief + Asynchronous API to obtain the system time in use by the WINC IC. + +@details + This function will request that the WINC IC send it's current system time to the application. The + information will arrive at the application via the @ref tpfAppWifiCb and event @ref + M2M_WIFI_RESP_GET_SYS_TIME. + +@return + The function returns @ref M2M_SUCCESS if the command has been successfully queued to the WINC, + and a negative value otherwise. + +@pre + - A Wi-Fi notification callback of type @ref tpfAppWifiCb MUST be implemented and registered + during initialization. Registration of the callback is done via the + [m2m_wifi_init](@ref m2m_wifi_init) API. + - The event @ref M2M_WIFI_RESP_GET_SYS_TIME must be handled in the callback. + +@see + - m2m_wifi_enable_sntp + - tstrSystemTime + */ +NMI_API sint8 m2m_wifi_get_sytem_time(void); + +/*! +@fn NMI_API sint8 m2m_wifi_set_cust_InfoElement(uint8*); + +@brief + Asynchronous API to add or remove a user-defined Information Element + +@details + This function allows the application to provide a custom Information Element to the WINC IC that will + be included in all beacon and probe response frames. + +@param [in] pau8M2mCustInfoElement + Pointer to Buffer containing the IE to be used. If null, this removes any current custom IE. If + non-null, the pointer must reference data in the following format: + +@verbatim + --------------- ---------- ---------- ------------------- -------- -------- ----------- ---------------------- + | Byte[0] | Byte[1] | Byte[2] | Byte[3:length1+2] | ..... | Byte[n] | Byte[n+1] | Byte[n+2:lengthx+2] | + |---------------|----------|----------|-------------------|-------- --------|-----------|------------------| + | #of all Bytes | IE1 ID | Length1 | Data1(Hex Coded) | ..... | IEx ID | Lengthx | Datax(Hex Coded) | + --------------- ---------- ---------- ------------------- -------- -------- ----------- ---------------------- +@endverbatim + +@return + The function returns @ref M2M_SUCCESS if the command has been successfully queued to the WINC, + and a negative value otherwise. + +@warning + - Size of All elements combined must not exceed 255 byte.\n + - Used in Access Point Mode \n + +\section WIFIExample11 Example + The example demonstrates how the information elements are set using this function. +@code + char elementData[21]; + static char state = 0; // To Add, Append, and Delete + if(0 == state) { //Add 3 IEs + state = 1; + //Total Number of Bytes + elementData[0]=12; + //First IE + elementData[1]=200; elementData[2]=1; elementData[3]='A'; + //Second IE + elementData[4]=201; elementData[5]=2; elementData[6]='B'; elementData[7]='C'; + //Third IE + elementData[8]=202; elementData[9]=3; elementData[10]='D'; elementData[11]=0; elementData[12]='F'; + } else if(1 == state) { + //Append 2 IEs to others, Notice that we keep old data in array starting with\n + //element 13 and total number of bytes increased to 20 + state = 2; + //Total Number of Bytes + elementData[0]=20; + //Fourth IE + elementData[13]=203; elementData[14]=1; elementData[15]='G'; + //Fifth IE + elementData[16]=204; elementData[17]=3; elementData[18]='X'; elementData[19]=5; elementData[20]='Z'; + } else if(2 == state) { //Delete All IEs + state = 0; + //Total Number of Bytes + elementData[0]=0; + } + m2m_wifi_set_cust_InfoElement(elementData); +@endcode + */ +NMI_API sint8 m2m_wifi_set_cust_InfoElement(uint8* pau8M2mCustInfoElement); + +/*! +@fn NMI_API sint8 m2m_wifi_set_power_profile(uint8 u8PwrMode); + +@brief Change the power profile mode + +@param [in] u8PwrMode + Change the WINC power profile to one of the modes: PWR_LOW1, PWR_LOW2, PWR_HIGH, PWR_AUTO. + +@return + The function SHALL return @ref M2M_SUCCESS for success and a negative value otherwise. + +@see + tenuM2mPwrMode + +@warning + May only be called after initialization, before any connection request, and may not be used to change + the power mode thereafter. +*/ +sint8 m2m_wifi_set_power_profile(uint8 u8PwrMode); + +/*! +@fn NMI_API sint8 m2m_wifi_set_tx_power(uint8 u8TxPwrLevel); + +@brief set the TX power tenuM2mTxPwrLevel + +@param [in] u8TxPwrLevel + change the TX power tenuM2mTxPwrLevel + +@return + The function SHALL return @ref M2M_SUCCESS for success and a negative value otherwise. + +@sa tenuM2mTxPwrLevel +*/ +sint8 m2m_wifi_set_tx_power(uint8 u8TxPwrLevel); + +/*! +@fn NMI_API sint8 m2m_wifi_enable_firmware_logs(uint8 u8Enable); + +@brief + Enable or Disable logs in run time (Disable Firmware logs will enhance the firmware start-up time + and performance) + +@param [in] u8Enable + Set 1 to enable the logs 0 for disable + +@return + The function SHALL return @ref M2M_SUCCESS for success and a negative value otherwise. + +@see + __DISABLE_FIRMWARE_LOGS__ (build option to disable logs from initializations) +*/ +sint8 m2m_wifi_enable_firmware_logs(uint8 u8Enable); +/*! +@fn NMI_API sint8 m2m_wifi_set_battery_voltage(uint8 u8BattVolt) + +@brief + Set the battery voltage to update the firmware calculations + +@param [in] dbBattVolt + Battery Voltage + +@return + The function SHALL return @ref M2M_SUCCESS for success and a negative value otherwise. +*/ +sint8 m2m_wifi_set_battery_voltage(uint16 u16BattVoltx100); + +/*! +@fn NMI_API sint8 m2m_wifi_ble_api_send(const uint8* const msg, const uint32 len); + +@brief + Asynchronous API to send an encapsulated Atmel BLE message over the Wifi Host Interface + +@param [in] msg + Pointer to the start of the BLE message to transfer down to the WINC + +@param [in] len + The length of the message in octets + +@return + The function returns @ref M2M_SUCCESS if the command has been successfully queued to the WINC, + and a negative value otherwise. + */ +NMI_API sint8 m2m_wifi_ble_api_send(uint8* msg, uint32 len); + + +/*! +@fn NMI_API sint8 m2m_wifi_enable_mac_mcast(uint8 *, uint8); + +@brief + Asynchronous API to add or remove MAC addresses in the multicast filter + +@details + This function allows the application to configure the capability of the WINC IC to receive multicast + packets when operating in bypass mode. + +@param [in] pu8MulticastMacAddress + Pointer to MAC address + +@param [in] u8AddRemove + A flag to add or remove the MAC ADDRESS, based on the following values: + - 0 : remove MAC address + - 1 : add MAC address + +@return + The function returns @ref M2M_SUCCESS if the command has been successfully queued to the WINC, + and a negative value otherwise. + +@note + Maximum number of MAC addresses that could be added is 8. + +@warning + This functionality is not supported by current WINC firmware. + */ +NMI_API sint8 m2m_wifi_enable_mac_mcast(uint8* pu8MulticastMacAddress, uint8 u8AddRemove); + +/*! +@fn NMI_API sint8 m2m_wifi_set_receive_buffer(void *, uint16); + +@brief + Asynchronous API to set or change the size of the WINC IC's receive buffer + +@param [in] pvBuffer + Pointer to Buffer to receive data. A NULL pointer causes a negative error @ref M2M_ERR_FAIL. + +@param [in] u16BufferLen + Length of data to be received. Maximum length of data should not exceed the size defined by TCP/IP + defined as @ref SOCKET_BUFFER_MAX_LENGTH + +@return + The function returns @ref M2M_SUCCESS if the command has been successfully queued to the WINC, + and a negative value otherwise. + +@warning + This functionality is not supported by current WINC firmware. +*/ +NMI_API sint8 m2m_wifi_set_receive_buffer(void* pvBuffer,uint16 u16BufferLen); + +/**@}*/ + +/**@defgroup VERSIONAPI Functions + @ingroup VERSION + */ +/**@{*/ + + +/*! +@fn uint32 m2m_wifi_get_chipId(void) + +@brief + Synchronous API to obtain the firmware WINC chip ID + +@return + The function SHALL return chipID > 0 or 0 for failure. +*/ +uint32 m2m_wifi_get_chipId(void); +/*! +@fn sint8 m2m_wifi_check_ota_rb(void); + +@brief + Synchronous API to check presence and compatibility of the WINC image that is stored in the inactive flash partition. + This is the image that would run on the WINC IC if @ref m2m_ota_switch_firmware or @ref m2m_ota_rollback were called, + followed by a reset of the WINC IC. + +@return + The function SHALL return @ref M2M_SUCCESS for compatible image and a negative value otherwise. +*/ +sint8 m2m_wifi_check_ota_rb(void); +/*! +@fn sint8 m2m_wifi_get_firmware_version(tstrM2mRev* pstrRev) + +@brief + Synchronous API to obtain the firmware version currently running on the WINC IC + +@param [out] pstrRev + pointer holds address of structure "tstrM2mRev" that contains the firmware version parameters + +@return + The function SHALL return @ref M2M_SUCCESS for success and a negative value otherwise. +*/ +sint8 m2m_wifi_get_firmware_version(tstrM2mRev *pstrRev); + +/*! +@fn \ + NMI_API sint8 m2m_ota_get_firmware_version(tstrM2mRev *pstrRev); + +@brief + Synchronous API to obtain the firmware version of the WINC image that is stored in the inactive flash partition. + This is the image that would run on the WINC IC if @ref m2m_ota_switch_firmware or @ref m2m_ota_rollback were called, + followed by a reset of the WINC IC. + +@param [out] pstrRev + pointer holds address of structure "tstrM2mRev" that contains the ota fw version parameters + +@return + The function SHALL return @ref M2M_SUCCESS for success and a negative value otherwise. +*/ +NMI_API sint8 m2m_ota_get_firmware_version(tstrM2mRev *pstrRev); + +/**@}*/ + +/*! + * @fn sint8 m2m_wifi_prng_get_random_bytes(uint8 * pu8PRNGBuff,uint16 u16PRNGSize) + * @param [in] pu8PrngBuff + * Pointer to Buffer to receive data. + * Size greater than the maximum specified (@ref M2M_BUFFER_MAX_SIZE - sizeof(tstrPrng)) + * causes a negative error @ref M2M_ERR_FAIL. + * @param [in] u16PrngSize + request size in bytes + * @return The function returns @ref M2M_SUCCESS for successful operations and a negative value otherwise. + */ +sint8 m2m_wifi_prng_get_random_bytes(uint8 * pu8PrngBuff,uint16 u16PrngSize); + +#ifdef __cplusplus +} +#endif +#endif /* __M2M_WIFI_H__ */ + diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/m2m_ate_mode.c b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/m2m_ate_mode.c new file mode 100644 index 000000000..0f2964aa9 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/m2m_ate_mode.c @@ -0,0 +1,771 @@ +/** + * + * \file + * + * \brief WINC3400 Peripherials Application Interface. + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _M2M_ATE_FW_ +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +INCLUDES +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ +#include "driver/include/m2m_ate_mode.h" +#include "driver/source/nmasic.h" +#include "driver/source/nmdrv.h" +#include "m2m_hif.h" +#include "driver/source/nmbus.h" +#include "bsp/include/nm_bsp.h" + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +MACROS +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ +#define rInterrupt_CORTUS_0 (0x10a8) +#define rInterrupt_CORTUS_1 (0x10ac) +#define rInterrupt_CORTUS_2 (0x10b0) + +#define rBurstTx_NMI_TX_RATE (0x161d00) +#define rBurstTx_NMI_NUM_TX_FRAMES (0x161d04) +#define rBurstTx_NMI_TX_FRAME_LEN (0x161d08) +#define rBurstTx_NMI_TX_CW_PARAM (0x161d0c) +#define rBurstTx_NMI_TX_GAIN (0x161d10) +#define rBurstTx_NMI_TX_DPD_CTRL (0x161d14) +#define rBurstTx_NMI_USE_PMU (0x161d18) +#define rBurstTx_NMI_TEST_CH (0x161d1c) +#define rBurstTx_NMI_TX_PHY_CONT (0x161d20) +#define rBurstTx_NMI_TX_CW_MODE (0x161d24) +#define rBurstTx_NMI_TEST_XO_OFF (0x161d28) +#define rBurstTx_NMI_USE_EFUSE_XO_OFF (0x161d2c) + +#define rBurstTx_NMI_MAC_FILTER_ENABLE_DA (0x161d30) +#define rBurstTx_NMI_MAC_ADDR_LO_PEER (0x161d34) +#define rBurstTx_NMI_MAC_ADDR_LO_SELF (0x161d38) +#define rBurstTx_NMI_MAC_ADDR_HI_PEER (0x161d3c) +#define rBurstTx_NMI_MAC_ADDR_HI_SELF (0x161d40) +#define rBurstTx_NMI_RX_PKT_CNT_SUCCESS (0x161d44) +#define rBurstTx_NMI_RX_PKT_CNT_FAIL (0x161d48) +#define rBurstTx_NMI_SET_SELF_MAC_ADDR (0x161d4c) +#define rBurstTx_NMI_MAC_ADDR_LO_SA (0x161d50) +#define rBurstTx_NMI_MAC_ADDR_HI_SA (0x161d54) +#define rBurstTx_NMI_MAC_FILTER_ENABLE_SA (0x161d58) + +#define rBurstRx_NMI_RX_ALL_PKTS_CONT (0x9898) +#define rBurstRx_NMI_RX_ERR_PKTS_CONT (0x988c) + +#define TX_DGAIN_MAX_NUM_REGS (4) +#define TX_DGAIN_REG_BASE_ADDRESS (0x1240) +#define TX_GAIN_CODE_MAX_NUM_REGS (3) +#define TX_GAIN_CODE_BASE_ADDRESS (0x1250) +#define TX_PA_MAX_NUM_REGS (3) +#define TX_PA_BASE_ADDRESS (0x1e58) +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +VARIABLES +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ +volatile static uint8 gu8AteIsRunning = 0; /*!< ATE firmware status, 1 means ATE is running otherwise stopped */ +volatile static uint8 gu8RxState = 0; /*!< RX status, 1 means Rx is running otherwise stopped */ +volatile static uint8 gu8TxState = 0; /*!< TX status, 1 means Tx is running otherwise stopped */ +volatile static uint32 gaAteFwTxRates[M2M_ATE_MAX_NUM_OF_RATES] = +{ + 0x01, 0x02, 0x05, 0x0B, /*B-Rats*/ + 0x06, 0x09, 0x0C, 0x12, 0x18, 0x24, 0x30, 0x36, /*G-Rats*/ + 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87 /*N-Rats*/ +}; + + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +STATIC FUNCTIONS +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ +static void m2m_ate_set_rx_status(uint8 u8Value) +{ + gu8RxState = u8Value; +} + +static void m2m_ate_set_tx_status(uint8 u8Value) +{ + gu8TxState = u8Value; +} + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +FUNCTION IMPLEMENTATION +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ +/*! +@fn \ + sint8 m2m_ate_init(void); + +@brief + This function used to download ATE firmware from flash and start it + +@return + The function SHALL return 0 for success and a negative value otherwise. +*/ +sint8 m2m_ate_init(uint32 req_serial_number) +{ + sint8 s8Ret = M2M_SUCCESS; + uint8 u8WifiMode = M2M_WIFI_MODE_CONFIG; + + s8Ret = nm_drv_init(&u8WifiMode, req_serial_number); + + return s8Ret; +} + +/*! +@fn \ + sint8 m2m_ate_deinit(void); + +@brief + De-Initialization of ATE firmware mode + +@return + The function SHALL return 0 for success and a negative value otherwise. +*/ +sint8 m2m_ate_deinit(void) +{ + return nm_drv_deinit(NULL); +} + +/*! +@fn \ + sint8 m2m_ate_set_fw_state(uint8); + +@brief + This function used to change ATE firmware status from running to stopped or vice versa. + +@param [in] u8State + Required state of ATE firmware, one of \ref tenuM2mAteFwState enumeration values. +@return + The function SHALL return 0 for success and a negative value otherwise. +\sa + m2m_ate_init +*/ +sint8 m2m_ate_set_fw_state(uint8 u8State) +{ + sint8 s8Ret = M2M_SUCCESS; + uint32_t u32Val = 0; + + if((M2M_ATE_FW_STATE_STOP == u8State) && (M2M_ATE_FW_STATE_STOP != gu8AteIsRunning)) + { + u32Val = nm_read_reg(rNMI_GLB_RESET); + u32Val &= ~(1 << 10); + s8Ret = nm_write_reg(rNMI_GLB_RESET, u32Val); + gu8AteIsRunning = M2M_ATE_FW_STATE_STOP; + } + else if((M2M_ATE_FW_STATE_RUN == u8State) && (M2M_ATE_FW_STATE_RUN != gu8AteIsRunning)) + { + /* 0x1118[0]=0 at power-on-reset: pad-based control. */ + /* Switch cortus reset register to register control. 0x1118[0]=1. */ + u32Val = nm_read_reg(rNMI_BOOT_RESET_MUX); + u32Val |= (1 << 0); + s8Ret = nm_write_reg(rNMI_BOOT_RESET_MUX, u32Val); + if(M2M_SUCCESS != s8Ret) + { + goto __EXIT; + } + /** + Write the firmware download complete magic value 0x10ADD09E at + location 0xFFFF000C (Cortus map) or C000C (AHB map). + This will let the boot-rom code execute from RAM. + **/ + s8Ret = nm_write_reg(0xc0000, 0x71); + if(M2M_SUCCESS != s8Ret) + { + goto __EXIT; + } + + u32Val = nm_read_reg(rNMI_GLB_RESET); + if((u32Val & (1ul << 10)) == (1ul << 10)) + { + u32Val &= ~(1ul << 10); + s8Ret = nm_write_reg(rNMI_GLB_RESET, u32Val); + if(M2M_SUCCESS != s8Ret) + { + goto __EXIT; + } + } + + u32Val |= (1ul << 10); + s8Ret = nm_write_reg(rNMI_GLB_RESET, u32Val); + if(M2M_SUCCESS != s8Ret) + { + goto __EXIT; + } + gu8AteIsRunning = M2M_ATE_FW_STATE_RUN; + } + else + { + s8Ret = M2M_ATE_ERR_UNHANDLED_CASE; + } + +__EXIT: + if((M2M_SUCCESS == s8Ret) && (M2M_ATE_FW_STATE_RUN == gu8AteIsRunning)) + { + nm_bsp_sleep(500); /*wait for ATE firmware start up*/ + } + return s8Ret; +} + +/*! +@fn \ + sint8 m2m_ate_get_fw_state(uint8); + +@brief + This function used to return status of ATE firmware. + +@return + The function SHALL return status of ATE firmware, one of \ref tenuM2mAteFwState enumeration values. +\sa + m2m_ate_init, m2m_ate_set_fw_state +*/ +sint8 m2m_ate_get_fw_state(void) +{ + return gu8AteIsRunning; +} + +/*! +@fn \ + uint32 m2m_ate_get_tx_rate(uint8); + +@brief + This function used to return value of TX rate required by application developer. + +@param [in] u8Index + Index of required rate , one of \ref tenuM2mAteTxIndexOfRates enumeration values. +@return + The function SHALL return 0 for in case of failure otherwise selected rate value. +\sa + tenuM2mAteTxIndexOfRates +*/ +uint32 m2m_ate_get_tx_rate(uint8 u8Index) +{ + if(M2M_ATE_MAX_NUM_OF_RATES <= u8Index) + { + return 0; + } + return gaAteFwTxRates[u8Index]; +} + +/*! +@fn \ + sint8 m2m_ate_get_tx_status(void); + +@brief + This function used to return status of TX test case either running or stopped. + +@return + The function SHALL return status of ATE firmware, 1 if TX is running otherwise 0. +\sa + m2m_ate_start_tx, m2m_ate_stop_tx +*/ +sint8 m2m_ate_get_tx_status(void) +{ + return gu8TxState; +} + +/*! +@fn \ + sint8 m2m_ate_start_tx(tstrM2mAteTx *) + +@brief + This function used to start TX test case. + +@param [in] strM2mAteTx + Type of \ref tstrM2mAteTx, with the values required to enable TX test case. You must use \ref m2m_ate_init first. +@return + The function SHALL return 0 for success and a negative value otherwise. +\sa + m2m_ate_init, m2m_ate_stop_tx, m2m_ate_get_tx_status +*/ +sint8 m2m_ate_start_tx(tstrM2mAteTx * strM2mAteTx) +{ + sint8 s8Ret = M2M_SUCCESS; + uint8 u8LoopCntr = 0; + uint32_t val32; + + + if(NULL == strM2mAteTx) + { + s8Ret = M2M_ATE_ERR_VALIDATE; + goto __EXIT; + } + + if(0 != m2m_ate_get_tx_status()) + { + s8Ret = M2M_ATE_ERR_TX_ALREADY_RUNNING; + goto __EXIT; + } + + if(0 != m2m_ate_get_rx_status()) + { + s8Ret = M2M_ATE_ERR_RX_ALREADY_RUNNING; + goto __EXIT; + } + + if( (strM2mAteTx->channel_num < M2M_ATE_CHANNEL_1) || + (strM2mAteTx->channel_num > M2M_ATE_CHANNEL_14) || + (strM2mAteTx->tx_gain_sel < M2M_ATE_TX_GAIN_DYNAMIC) || + (strM2mAteTx->tx_gain_sel > M2M_ATE_TX_GAIN_TELEC) || + (strM2mAteTx->frame_len > M2M_ATE_MAX_FRAME_LENGTH) || + (strM2mAteTx->frame_len < M2M_ATE_MIN_FRAME_LENGTH) + ) + { + s8Ret = M2M_ATE_ERR_VALIDATE; + goto __EXIT; + } + + if( (strM2mAteTx->duty_cycle < M2M_ATE_TX_DUTY_MAX_VALUE /*1*/) || + (strM2mAteTx->duty_cycle > M2M_ATE_TX_DUTY_MIN_VALUE /*10*/ ) || + (strM2mAteTx->dpd_ctrl < M2M_ATE_TX_DPD_DYNAMIC) || + (strM2mAteTx->dpd_ctrl > M2M_ATE_TX_DPD_ENABLED) || + (strM2mAteTx->use_pmu < M2M_ATE_PMU_DISBLE) || + (strM2mAteTx->use_pmu > M2M_ATE_PMU_ENABLE) || + (strM2mAteTx->phy_burst_tx < M2M_ATE_TX_SRC_MAC) || + (strM2mAteTx->phy_burst_tx > M2M_ATE_TX_SRC_PHY) || + (strM2mAteTx->cw_tx < M2M_ATE_TX_MODE_NORM) || + (strM2mAteTx->cw_tx > M2M_ATE_TX_MODE_CW) + ) + { + s8Ret = M2M_ATE_ERR_VALIDATE; + goto __EXIT; + } + + for(u8LoopCntr=0; u8LoopCntrdata_rate) + { + break; + } + } + + if(M2M_ATE_MAX_NUM_OF_RATES == u8LoopCntr) + { + s8Ret = M2M_ATE_ERR_VALIDATE; + goto __EXIT; + } + + + + s8Ret += nm_write_reg(rBurstTx_NMI_USE_PMU, strM2mAteTx->use_pmu); + s8Ret += nm_write_reg(rBurstTx_NMI_TX_PHY_CONT, strM2mAteTx->phy_burst_tx); + s8Ret += nm_write_reg(rBurstTx_NMI_NUM_TX_FRAMES, strM2mAteTx->num_frames); + s8Ret += nm_write_reg(rBurstTx_NMI_TX_GAIN, strM2mAteTx->tx_gain_sel); + s8Ret += nm_write_reg(rBurstTx_NMI_TEST_CH, strM2mAteTx->channel_num); + s8Ret += nm_write_reg(rBurstTx_NMI_TX_FRAME_LEN, strM2mAteTx->frame_len); + s8Ret += nm_write_reg(rBurstTx_NMI_TX_CW_PARAM, strM2mAteTx->duty_cycle); + s8Ret += nm_write_reg(rBurstTx_NMI_TX_DPD_CTRL, strM2mAteTx->dpd_ctrl); + s8Ret += nm_write_reg(rBurstTx_NMI_TX_RATE, strM2mAteTx->data_rate); + s8Ret += nm_write_reg(rBurstTx_NMI_TX_CW_MODE, strM2mAteTx->cw_tx); + s8Ret += nm_write_reg(rBurstTx_NMI_TEST_XO_OFF, strM2mAteTx->xo_offset_x1000); + s8Ret += nm_write_reg(rBurstTx_NMI_USE_EFUSE_XO_OFF, strM2mAteTx->use_efuse_xo_offset); + + val32 = strM2mAteTx->peer_mac_addr[5] << 0; + val32 |= strM2mAteTx->peer_mac_addr[4] << 8; + val32 |= strM2mAteTx->peer_mac_addr[3] << 16; + nm_write_reg(rBurstTx_NMI_MAC_ADDR_LO_PEER, val32 ); + + val32 = strM2mAteTx->peer_mac_addr[2] << 0; + val32 |= strM2mAteTx->peer_mac_addr[1] << 8; + val32 |= strM2mAteTx->peer_mac_addr[0] << 16; + nm_write_reg(rBurstTx_NMI_MAC_ADDR_HI_PEER, val32 ); + + if(M2M_SUCCESS == s8Ret) + { + s8Ret += nm_write_reg(rInterrupt_CORTUS_0, 1); /*Interrupt Cortus*/ + m2m_ate_set_tx_status(1); + nm_bsp_sleep(200); /*Recommended*/ + } + +__EXIT: + return s8Ret; +} + +/*! +@fn \ + sint8 m2m_ate_stop_tx(void) + +@brief + This function used to stop TX test case. + +@return + The function SHALL return 0 for success and a negative value otherwise. +\sa + m2m_ate_init, m2m_ate_start_tx, m2m_ate_get_tx_status +*/ +sint8 m2m_ate_stop_tx(void) +{ + sint8 s8Ret = M2M_SUCCESS; + + s8Ret = nm_write_reg(rInterrupt_CORTUS_1, 1); + if(M2M_SUCCESS == s8Ret) + { + m2m_ate_set_tx_status(0); + } + + return s8Ret; +} + +/*! +@fn \ + sint8 m2m_ate_get_rx_status(uint8); + +@brief + This function used to return status of RX test case either running or stopped. + +@return + The function SHALL return status of ATE firmware, 1 if RX is running otherwise 0. +\sa + m2m_ate_start_rx, m2m_ate_stop_rx +*/ +sint8 m2m_ate_get_rx_status(void) +{ + return gu8RxState; +} + +/*! +@fn \ + sint8 m2m_ate_start_rx(tstrM2mAteRx *) + +@brief + This function used to start RX test case. + +@param [in] strM2mAteRx + Type of \ref tstrM2mAteRx, with the values required to enable RX test case. You must use \ref m2m_ate_init first. +@return + The function SHALL return 0 for success and a negative value otherwise. +\sa + m2m_ate_init, m2m_ate_stop_rx, m2m_ate_get_rx_status +*/ +sint8 m2m_ate_start_rx(tstrM2mAteRx * strM2mAteRxStr) +{ + sint8 s8Ret = M2M_SUCCESS; + uint32 val32; + if(NULL == strM2mAteRxStr) + { + s8Ret = M2M_ATE_ERR_VALIDATE; + goto __EXIT; + } + + if(0 != m2m_ate_get_tx_status()) + { + s8Ret = M2M_ATE_ERR_TX_ALREADY_RUNNING; + goto __EXIT; + } + + if(0 != m2m_ate_get_rx_status()) + { + s8Ret = M2M_ATE_ERR_RX_ALREADY_RUNNING; + goto __EXIT; + } + + if( (strM2mAteRxStr->channel_num < M2M_ATE_CHANNEL_1) || + (strM2mAteRxStr->channel_num > M2M_ATE_CHANNEL_14)|| + (strM2mAteRxStr->use_pmu < M2M_ATE_PMU_DISBLE) || + (strM2mAteRxStr->use_pmu > M2M_ATE_PMU_ENABLE) + ) + { + s8Ret = M2M_ATE_ERR_VALIDATE; + goto __EXIT; + } + + s8Ret += nm_write_reg(rBurstTx_NMI_TEST_CH, strM2mAteRxStr->channel_num); + s8Ret += nm_write_reg(rBurstTx_NMI_USE_PMU, strM2mAteRxStr->use_pmu); + s8Ret += nm_write_reg(rBurstTx_NMI_TEST_XO_OFF, strM2mAteRxStr->xo_offset_x1000); + s8Ret += nm_write_reg(rBurstTx_NMI_USE_EFUSE_XO_OFF, strM2mAteRxStr->use_efuse_xo_offset); + + if(strM2mAteRxStr->override_self_mac_addr) + { + val32 = strM2mAteRxStr->self_mac_addr[5] << 0; + val32 |= strM2mAteRxStr->self_mac_addr[4] << 8; + val32 |= strM2mAteRxStr->self_mac_addr[3] << 16; + nm_write_reg(rBurstTx_NMI_MAC_ADDR_LO_SELF, val32 ); + + val32 = strM2mAteRxStr->self_mac_addr[2] << 0; + val32 |= strM2mAteRxStr->self_mac_addr[1] << 8; + val32 |= strM2mAteRxStr->self_mac_addr[0] << 16; + nm_write_reg(rBurstTx_NMI_MAC_ADDR_HI_SELF, val32 ); + } + + if(strM2mAteRxStr->mac_filter_en_sa) + { + val32 = strM2mAteRxStr->sa_mac_addr[5] << 0; + val32 |= strM2mAteRxStr->sa_mac_addr[4] << 8; + val32 |= strM2mAteRxStr->sa_mac_addr[3] << 16; + nm_write_reg(rBurstTx_NMI_MAC_ADDR_LO_SA, val32 ); + + val32 = strM2mAteRxStr->sa_mac_addr[2] << 0; + val32 |= strM2mAteRxStr->sa_mac_addr[1] << 8; + val32 |= strM2mAteRxStr->sa_mac_addr[0] << 16; + nm_write_reg(rBurstTx_NMI_MAC_ADDR_HI_SA, val32 ); + } + + nm_write_reg(rBurstTx_NMI_MAC_FILTER_ENABLE_DA, strM2mAteRxStr->mac_filter_en_da); + nm_write_reg(rBurstTx_NMI_MAC_FILTER_ENABLE_SA, strM2mAteRxStr->mac_filter_en_sa); + nm_write_reg(rBurstTx_NMI_SET_SELF_MAC_ADDR, strM2mAteRxStr->override_self_mac_addr); + + if(M2M_SUCCESS == s8Ret) + { + s8Ret += nm_write_reg(rInterrupt_CORTUS_2, 1); /*Interrupt Cortus*/ + m2m_ate_set_rx_status(1); + nm_bsp_sleep(10); /*Recommended*/ + } + +__EXIT: + return s8Ret; +} + +/*! +@fn \ + sint8 m2m_ate_stop_rx(void) + +@brief + This function used to stop RX test case. + +@return + The function SHALL return 0 for success and a negative value otherwise. +\sa + m2m_ate_init, m2m_ate_start_rx, m2m_ate_get_rx_status +*/ +sint8 m2m_ate_stop_rx(void) +{ + m2m_ate_set_rx_status(0); + nm_bsp_sleep(200); /*Recommended*/ + return M2M_SUCCESS; +} + +/*! +@fn \ + sint8 m2m_ate_read_rx_status(tstrM2mAteRxStatus *) + +@brief + This function used to read RX statistics from ATE firmware. + +@param [out] strM2mAteRxStatus + Type of \ref tstrM2mAteRxStatus used to save statistics of RX test case. You must use \ref m2m_ate_start_rx first. +@return + The function SHALL return 0 for success and a negative value otherwise. +\sa + m2m_ate_init, m2m_ate_start_rx +*/ +sint8 m2m_ate_read_rx_status(tstrM2mAteRxStatus *strM2mAteRxStatus) +{ + sint8 s8Ret = M2M_SUCCESS; + + if(NULL == strM2mAteRxStatus) + { + s8Ret = M2M_ATE_ERR_VALIDATE; + goto __EXIT; + } + + if(0 != m2m_ate_get_tx_status()) + { + s8Ret = M2M_ATE_ERR_TX_ALREADY_RUNNING; + goto __EXIT; + } + + if (nm_read_reg(rBurstTx_NMI_MAC_FILTER_ENABLE_DA) || nm_read_reg(rBurstTx_NMI_MAC_FILTER_ENABLE_SA)) + { + strM2mAteRxStatus->num_rx_pkts = nm_read_reg(rBurstTx_NMI_RX_PKT_CNT_SUCCESS) + nm_read_reg(rBurstTx_NMI_RX_PKT_CNT_FAIL); + strM2mAteRxStatus->num_good_pkts = nm_read_reg(rBurstTx_NMI_RX_PKT_CNT_SUCCESS); + strM2mAteRxStatus->num_err_pkts = nm_read_reg(rBurstTx_NMI_RX_PKT_CNT_FAIL); + } + else + { + strM2mAteRxStatus->num_rx_pkts = nm_read_reg(rBurstRx_NMI_RX_ALL_PKTS_CONT) + nm_read_reg(0x989c); + strM2mAteRxStatus->num_err_pkts = nm_read_reg(rBurstRx_NMI_RX_ERR_PKTS_CONT); + strM2mAteRxStatus->num_good_pkts = strM2mAteRxStatus->num_rx_pkts - strM2mAteRxStatus->num_err_pkts; + } + +__EXIT: + return s8Ret; +} +/*! +@fn \ + sint8 m2m_ate_set_dig_gain(double dGaindB) + +@brief + This function is used to set the digital gain + +@param [in] double dGaindB + The digital gain value required to be set. +@return + The function SHALL return 0 for success and a negative value otherwise. +*/ +sint8 m2m_ate_set_dig_gain(double dGaindB) +{ + uint32_t dGain, val32; + dGain = (uint32_t)(pow(10, dGaindB/20.0) * 1024.0); + + val32 = nm_read_reg(0x160cd0); + val32 &= ~(0x1ffful << 0); + val32 |= (((uint32_t)dGain) << 0); + nm_write_reg(0x160cd0, val32); + return M2M_SUCCESS; +} +/*! +@fn \ + sint8 m2m_ate_get_dig_gain(double * pdGaindB) + +@brief + This function is used to get the digital gain + +@param [out] double * pdGaindB + The retrieved digital gain value obtained from HW registers. +@return + The function SHALL return 0 for success and a negative value otherwise. +*/ +sint8 m2m_ate_get_dig_gain(double * pdGaindB) +{ + uint32 dGain, val32; + + if(!pdGaindB) return M2M_ERR_INVALID_ARG; + + val32 = nm_read_reg(0x160cd0); + + dGain = (val32 >> 0) & 0x1ffful; + *pdGaindB = 20.0*log10((double)dGain / 1024.0); + + return M2M_SUCCESS; +} +/*! +@fn \ + sint8 m2m_ate_get_pa_gain(uint32 *paGain) + +@brief + This function is used to get the pa gain + +@param [out] uint32 *paGain + The retrieved pa gain value obtained from HW registers. +@return + The function SHALL return 0 for success and a negative value otherwise. +*/ +sint8 m2m_ate_get_pa_gain(uint32 *paGain) +{ + uint32 val32; + + if(!paGain) + return M2M_ERR_INVALID_ARG; + + val32 = nm_read_reg(0x1e9c); + + * paGain = (val32 >> 8) & 0x3f; + + return M2M_SUCCESS; +} +/*! +@fn \ + sint8 m2m_ate_get_ppa_gain(uint32 * ppaGain) + +@brief + This function is used to get the ppa gain + +@param [out] uint32 * ppaGain + The retrieved ppa gain value obtained from HW registers. +@return + The function SHALL return 0 for success and a negative value otherwise. +*/ +sint8 m2m_ate_get_ppa_gain(uint32 * ppaGain) +{ + uint32 val32; + + if(!ppaGain) return M2M_ERR_INVALID_ARG; + + val32 = nm_read_reg(0x1ea0); + + * ppaGain = (val32 >> 5) & 0x7; + + return M2M_SUCCESS; +} +/*! +@fn \ + sint8 m2m_ate_get_tot_gain(double * pTotGaindB) + +@brief + This function is used to calculate the total gain + +@param [out] double * pTotGaindB + The retrieved total gain value obtained from calculations made based on the digital gain, pa and ppa gain values. +@return + The function SHALL return 0 for success and a negative value otherwise. +*/ +sint8 m2m_ate_get_tot_gain(double * pTotGaindB) +{ + double totGaindB, dGaindB; + uint32 paGain,ppaGain,m_cmbPAGainStep,m_cmbPPAGainStep; + + + m2m_ate_get_pa_gain(&paGain); + m2m_ate_get_ppa_gain(&ppaGain); + m2m_ate_get_dig_gain(&dGaindB); + + switch(paGain){ + case 0x1: + m_cmbPAGainStep = 5; + break; + case 0x3: + m_cmbPAGainStep = 4; + break; + case 0x7: + m_cmbPAGainStep = 3; + break; + case 0xf: + m_cmbPAGainStep = 2; + break; + case 0x1f: + m_cmbPAGainStep = 1; + break; + case 0x3f: + m_cmbPAGainStep = 0; + break; + default: + m_cmbPAGainStep = 0; + break; + } + + + switch(ppaGain){ + case 0x1: + m_cmbPPAGainStep = 2; + break; + case 0x3: + m_cmbPPAGainStep = 1; + break; + case 0x7: + m_cmbPPAGainStep = 0; + break; + default: + m_cmbPPAGainStep = 3; + break; + } + + totGaindB = dGaindB + 18 - m_cmbPAGainStep*3; + totGaindB += 9 - m_cmbPPAGainStep*3; + + *pTotGaindB = totGaindB; + + return M2M_SUCCESS; +} +#endif //_M2M_ATE_FW_ \ No newline at end of file diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/m2m_crypto.c b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/m2m_crypto.c new file mode 100644 index 000000000..620d6ee99 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/m2m_crypto.c @@ -0,0 +1,686 @@ +/** + * + * \file m2m_crypto.c + * + * \brief WINC Crypto module. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +INCLUDES +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ + +#include "driver/include/m2m_crypto.h" +#include "driver/source/nmbus.h" +#include "driver/source/nmasic.h" + +#ifdef CONF_CRYPTO + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +MACROS +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ + +/*======*======*======*======*======*=======* +* WINC SHA256 HW Engine Register Definition * +*======*======*======*======*======*========*/ + +#define SHA_BLOCK_SIZE (64) + +#define SHARED_MEM_BASE (0xd0000) + + +#define SHA256_MEM_BASE (0x180000UL) +#define SHA256_ENGINE_ADDR (0x180000ul) + +/* SHA256 Registers */ +#define SHA256_CTRL (SHA256_MEM_BASE+0x00) +#define SHA256_CTRL_START_CALC_MASK (NBIT0) +#define SHA256_CTRL_START_CALC_SHIFT (0) +#define SHA256_CTRL_PREPROCESS_MASK (NBIT1) +#define SHA256_CTRL_PREPROCESS_SHIFT (1) +#define SHA256_CTRL_HASH_HASH_MASK (NBIT2) +#define SHA256_CTRL_HASH_HASH_SHIFT (2) +#define SHA256_CTRL_INIT_SHA256_STATE_MASK (NBIT3) +#define SHA256_CTRL_INIT_SHA256_STATE_SHIFT (3) +#define SHA256_CTRL_WR_BACK_HASH_VALUE_MASK (NBIT4) +#define SHA256_CTRL_WR_BACK_HASH_VALUE_SHIFT (4) +#define SHA256_CTRL_FORCE_SHA256_QUIT_MASK (NBIT5) +#define SHA256_CTRL_FORCE_SHA256_QUIT_SHIFT (5) + +#define SHA256_REGS_SHA256_CTRL_AHB_BYTE_REV_EN (NBIT6) +#define SHA256_REGS_SHA256_CTRL_RESERVED (NBIT7) +#define SHA256_REGS_SHA256_CTRL_CORE_TO_AHB_CLK_RATIO (NBIT8+ NBIT9+ NBIT10) +#define SHA256_REGS_SHA256_CTRL_CORE_TO_AHB_CLK_RATIO_MASK (NBIT2+ NBIT1+ NBIT0) +#define SHA256_REGS_SHA256_CTRL_CORE_TO_AHB_CLK_RATIO_SHIFT (8) +#define SHA256_REGS_SHA256_CTRL_RESERVED_11 (NBIT11) +#define SHA256_REGS_SHA256_CTRL_SHA1_CALC (NBIT12) +#define SHA256_REGS_SHA256_CTRL_PBKDF2_SHA1_CALC (NBIT13) + + +#define SHA256_START_RD_ADDR (SHA256_MEM_BASE+0x04UL) +#define SHA256_DATA_LENGTH (SHA256_MEM_BASE+0x08UL) +#define SHA256_START_WR_ADDR (SHA256_MEM_BASE+0x0cUL) +#define SHA256_COND_CHK_CTRL (SHA256_MEM_BASE+0x10) +#define SHA256_COND_CHK_CTRL_HASH_VAL_COND_CHK_MASK (NBIT1 | NBIT0) +#define SHA256_COND_CHK_CTRL_HASH_VAL_COND_CHK_SHIFT (0) +#define SHA256_COND_CHK_CTRL_STEP_VAL_MASK (NBIT6 | NBIT5 | NBIT4 | NBIT3 | NBIT2) +#define SHA256_COND_CHK_CTRL_STEP_VAL_SHIFT (2) +#define SHA256_COND_CHK_CTRL_COND_CHK_RESULT_MASK (NBIT7) +#define SHA256_COND_CHK_CTRL_COND_CHK_RESULT_SHIFT (7) + +#define SHA256_MOD_DATA_RANGE (SHA256_MEM_BASE+0x14) +#define SHA256_MOD_DATA_RANGE_ST_BYTE_2_ADD_STP_MASK (NBIT24-1) +#define SHA256_MOD_DATA_RANGE_ST_BYTE_2_ADD_STP_SHIFT (0) +#define SHA256_MOD_DATA_RANGE_MOD_DATA_LEN_MASK (NBIT24 | NBIT25| NBIT26) +#define SHA256_MOD_DATA_RANGE_MOD_DATA_LEN_SHIFT (24) + + +#define SHA256_COND_CHK_STS_1 (SHA256_MEM_BASE+0x18) +#define SHA256_COND_CHK_STS_2 (SHA256_MEM_BASE+0x1c) +#define SHA256_DONE_INTR_ENABLE (SHA256_MEM_BASE+0x20) +#define SHA256_DONE_INTR_STS (SHA256_MEM_BASE+0x24) +#define SHA256_TARGET_HASH_H1 (SHA256_MEM_BASE+0x28) +#define SHA256_TARGET_HASH_H2 (SHA256_MEM_BASE+0x2c) +#define SHA256_TARGET_HASH_H3 (SHA256_MEM_BASE+0x30) +#define SHA256_TARGET_HASH_H4 (SHA256_MEM_BASE+0x34) +#define SHA256_TARGET_HASH_H5 (SHA256_MEM_BASE+0x38) +#define SHA256_TARGET_HASH_H6 (SHA256_MEM_BASE+0x3c) +#define SHA256_TARGET_HASH_H7 (SHA256_MEM_BASE+0x40) +#define SHA256_TARGET_HASH_H8 (SHA256_MEM_BASE+0x44) + +/*======*======*======*======*======*=======* +* WINC BIGINT HW Engine Register Definition * +*======*======*======*======*======*========*/ + + +#define BIGINT_ENGINE_ADDR (0x180080ul) +#define BIGINT_VERSION (BIGINT_ENGINE_ADDR + 0x00) + +#define BIGINT_MISC_CTRL (BIGINT_ENGINE_ADDR + 0x04) +#define BIGINT_MISC_CTRL_CTL_START (NBIT0) +#define BIGINT_MISC_CTRL_CTL_RESET (NBIT1) +#define BIGINT_MISC_CTRL_CTL_MSW_FIRST (NBIT2) +#define BIGINT_MISC_CTRL_CTL_SWAP_BYTE_ORDER (NBIT3) +#define BIGINT_MISC_CTRL_CTL_FORCE_BARRETT (NBIT4) +#define BIGINT_MISC_CTRL_CTL_M_PRIME_VALID (NBIT5) + +#define BIGINT_M_PRIME (BIGINT_ENGINE_ADDR + 0x08) + +#define BIGINT_STATUS (BIGINT_ENGINE_ADDR + 0x0C) +#define BIGINT_STATUS_STS_DONE (NBIT0) + +#define BIGINT_CLK_COUNT (BIGINT_ENGINE_ADDR + 0x10) +#define BIGINT_ADDR_X (BIGINT_ENGINE_ADDR + 0x14) +#define BIGINT_ADDR_E (BIGINT_ENGINE_ADDR + 0x18) +#define BIGINT_ADDR_M (BIGINT_ENGINE_ADDR + 0x1C) +#define BIGINT_ADDR_R (BIGINT_ENGINE_ADDR + 0x20) +#define BIGINT_LENGTH (BIGINT_ENGINE_ADDR + 0x24) + +#define BIGINT_IRQ_STS (BIGINT_ENGINE_ADDR + 0x28) +#define BIGINT_IRQ_STS_DONE (NBIT0) +#define BIGINT_IRQ_STS_CHOOSE_MONT (NBIT1) +#define BIGINT_IRQ_STS_M_READ (NBIT2) +#define BIGINT_IRQ_STS_X_READ (NBIT3) +#define BIGINT_IRQ_STS_START (NBIT4) +#define BIGINT_IRQ_STS_PRECOMP_FINISH (NBIT5) + +#define BIGINT_IRQ_MASK (BIGINT_ENGINE_ADDR + 0x2C) +#define BIGINT_IRQ_MASK_CTL_IRQ_MASK_START (NBIT4) + +#define ENABLE_FLIPPING 1 + + + + +#define GET_UINT32(BUF,OFFSET) (((uint32)((BUF)[OFFSET])) | ((uint32)(((BUF)[OFFSET + 1]) << 8)) | \ +((uint32)(((BUF)[OFFSET + 2]) << 16)) | ((uint32)(((BUF)[OFFSET + 3]) << 24))) + +#define PUTU32(VAL32,BUF,OFFSET) \ +do \ +{ \ + (BUF)[OFFSET ] = BYTE_3((VAL32)); \ + (BUF)[OFFSET +1 ] = BYTE_2((VAL32)); \ + (BUF)[OFFSET +2 ] = BYTE_1((VAL32)); \ + (BUF)[OFFSET +3 ] = BYTE_0((VAL32)); \ +}while(0) + + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +DATA TYPES +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ + +/*! +@struct \ + tstrHashContext + +@brief +*/ +typedef struct{ + uint32 au32HashState[M2M_SHA256_DIGEST_LEN/4]; + uint8 au8CurrentBlock[64]; + uint32 u32TotalLength; + uint8 u8InitHashFlag; +}tstrSHA256HashCtxt; + + + +/*======*======*======*======*======*=======* +* SHA256 IMPLEMENTATION * +*======*======*======*======*======*========*/ + +sint8 m2m_sha256_hash_init(tstrM2mSha256Ctxt *pstrSha256Ctxt) +{ + tstrSHA256HashCtxt *pstrSHA256 = (tstrSHA256HashCtxt*)pstrSha256Ctxt; + if(pstrSHA256 != NULL) + { + m2m_memset((uint8*)pstrSha256Ctxt, 0, sizeof(tstrM2mSha256Ctxt)); + pstrSHA256->u8InitHashFlag = 1; + } + return 0; +} + +sint8 m2m_sha256_hash_update(tstrM2mSha256Ctxt *pstrSha256Ctxt, uint8 *pu8Data, uint16 u16DataLength) +{ + sint8 s8Ret = M2M_ERR_FAIL; + tstrSHA256HashCtxt *pstrSHA256 = (tstrSHA256HashCtxt*)pstrSha256Ctxt; + if(pstrSHA256 != NULL) + { + uint32 u32ReadAddr; + uint32 u32WriteAddr = SHARED_MEM_BASE; + uint32 u32Addr = u32WriteAddr; + uint32 u32ResidualBytes; + uint32 u32NBlocks; + uint32 u32Offset; + uint32 u32CurrentBlock = 0; + uint8 u8IsDone = 0; + + /* Get the remaining bytes from the previous update (if the length is not block aligned). */ + u32ResidualBytes = pstrSHA256->u32TotalLength % SHA_BLOCK_SIZE; + + /* Update the total data length. */ + pstrSHA256->u32TotalLength += u16DataLength; + + if(u32ResidualBytes != 0) + { + if((u32ResidualBytes + u16DataLength) >= SHA_BLOCK_SIZE) + { + u32Offset = SHA_BLOCK_SIZE - u32ResidualBytes; + m2m_memcpy(&pstrSHA256->au8CurrentBlock[u32ResidualBytes], pu8Data, u32Offset); + pu8Data += u32Offset; + u16DataLength -= u32Offset; + + nm_write_block(u32Addr, pstrSHA256->au8CurrentBlock, SHA_BLOCK_SIZE); + u32Addr += SHA_BLOCK_SIZE; + u32CurrentBlock = 1; + } + else + { + m2m_memcpy(&pstrSHA256->au8CurrentBlock[u32ResidualBytes], pu8Data, u16DataLength); + u16DataLength = 0; + } + } + + /* Get the number of HASH BLOCKs and the residual bytes. */ + u32NBlocks = u16DataLength / SHA_BLOCK_SIZE; + u32ResidualBytes = u16DataLength % SHA_BLOCK_SIZE; + + if(u32NBlocks != 0) + { + nm_write_block(u32Addr, pu8Data, (uint16)(u32NBlocks * SHA_BLOCK_SIZE)); + pu8Data += (u32NBlocks * SHA_BLOCK_SIZE); + } + + u32NBlocks += u32CurrentBlock; + if(u32NBlocks != 0) + { + uint32 u32RegVal = 0; + + nm_write_reg(SHA256_CTRL, u32RegVal); + u32RegVal |= SHA256_CTRL_FORCE_SHA256_QUIT_MASK; + nm_write_reg(SHA256_CTRL, u32RegVal); + + if(pstrSHA256->u8InitHashFlag) + { + pstrSHA256->u8InitHashFlag = 0; + u32RegVal |= SHA256_CTRL_INIT_SHA256_STATE_MASK; + } + + u32ReadAddr = u32WriteAddr + (u32NBlocks * SHA_BLOCK_SIZE); + nm_write_reg(SHA256_DATA_LENGTH, (u32NBlocks * SHA_BLOCK_SIZE)); + nm_write_reg(SHA256_START_RD_ADDR, u32WriteAddr); + nm_write_reg(SHA256_START_WR_ADDR, u32ReadAddr); + + u32RegVal |= SHA256_CTRL_START_CALC_MASK; + + u32RegVal &= ~(0x7 << 8); + u32RegVal |= (2 << 8); + + nm_write_reg(SHA256_CTRL, u32RegVal); + + /* 5. Wait for done_intr */ + while(!u8IsDone) + { + u32RegVal = nm_read_reg(SHA256_DONE_INTR_STS); + u8IsDone = u32RegVal & NBIT0; + } + } + if(u32ResidualBytes != 0) + { + m2m_memcpy(pstrSHA256->au8CurrentBlock, pu8Data, u32ResidualBytes); + } + s8Ret = M2M_SUCCESS; + } + return s8Ret; +} + + +sint8 m2m_sha256_hash_finish(tstrM2mSha256Ctxt *pstrSha256Ctxt, uint8 *pu8Sha256Digest) +{ + sint8 s8Ret = M2M_ERR_FAIL; + tstrSHA256HashCtxt *pstrSHA256 = (tstrSHA256HashCtxt*)pstrSha256Ctxt; + if(pstrSHA256 != NULL) + { + uint32 u32ReadAddr; + uint32 u32WriteAddr = SHARED_MEM_BASE; + uint32 u32Addr = u32WriteAddr; + uint16 u16Offset; + uint16 u16PaddingLength; + uint16 u16NBlocks = 1; + uint32 u32RegVal = 0; + uint32 u32Idx,u32ByteIdx; + uint32 au32Digest[M2M_SHA256_DIGEST_LEN / 4]; + uint8 u8IsDone = 0; + + nm_write_reg(SHA256_CTRL,u32RegVal); + u32RegVal |= SHA256_CTRL_FORCE_SHA256_QUIT_MASK; + nm_write_reg(SHA256_CTRL,u32RegVal); + + if(pstrSHA256->u8InitHashFlag) + { + pstrSHA256->u8InitHashFlag = 0; + u32RegVal |= SHA256_CTRL_INIT_SHA256_STATE_MASK; + } + + /* Calculate the offset of the last data byte in the current block. */ + u16Offset = (uint16)(pstrSHA256->u32TotalLength % SHA_BLOCK_SIZE); + + /* Add the padding byte 0x80. */ + pstrSHA256->au8CurrentBlock[u16Offset ++] = 0x80; + + /* Calculate the required padding to complete + one Hash Block Size. + */ + u16PaddingLength = SHA_BLOCK_SIZE - u16Offset; + m2m_memset(&pstrSHA256->au8CurrentBlock[u16Offset], 0, u16PaddingLength); + + /* If the padding count is not enough to hold 64-bit representation of + the total input message length, one padding block is required. + */ + if(u16PaddingLength < 8) + { + nm_write_block(u32Addr, pstrSHA256->au8CurrentBlock, SHA_BLOCK_SIZE); + u32Addr += SHA_BLOCK_SIZE; + m2m_memset(pstrSHA256->au8CurrentBlock, 0, SHA_BLOCK_SIZE); + u16NBlocks ++; + } + + /* pack the length at the end of the padding block */ + PUTU32(pstrSHA256->u32TotalLength << 3, pstrSHA256->au8CurrentBlock, (SHA_BLOCK_SIZE - 4)); + + u32ReadAddr = u32WriteAddr + (u16NBlocks * SHA_BLOCK_SIZE); + nm_write_block(u32Addr, pstrSHA256->au8CurrentBlock, SHA_BLOCK_SIZE); + nm_write_reg(SHA256_DATA_LENGTH, (u16NBlocks * SHA_BLOCK_SIZE)); + nm_write_reg(SHA256_START_RD_ADDR, u32WriteAddr); + nm_write_reg(SHA256_START_WR_ADDR, u32ReadAddr); + + u32RegVal |= SHA256_CTRL_START_CALC_MASK; + u32RegVal |= SHA256_CTRL_WR_BACK_HASH_VALUE_MASK; + u32RegVal &= ~(0x7UL << 8); + u32RegVal |= (0x2UL << 8); + + nm_write_reg(SHA256_CTRL,u32RegVal); + + + /* 5. Wait for done_intr */ + while(!u8IsDone) + { + u32RegVal = nm_read_reg(SHA256_DONE_INTR_STS); + u8IsDone = u32RegVal & NBIT0; + } + nm_read_block(u32ReadAddr, (uint8*)au32Digest, 32); + + /* Convert the output words to an array of bytes. + */ + u32ByteIdx = 0; + for(u32Idx = 0; u32Idx < (M2M_SHA256_DIGEST_LEN / 4); u32Idx ++) + { + pu8Sha256Digest[u32ByteIdx ++] = BYTE_3(au32Digest[u32Idx]); + pu8Sha256Digest[u32ByteIdx ++] = BYTE_2(au32Digest[u32Idx]); + pu8Sha256Digest[u32ByteIdx ++] = BYTE_1(au32Digest[u32Idx]); + pu8Sha256Digest[u32ByteIdx ++] = BYTE_0(au32Digest[u32Idx]); + } + s8Ret = M2M_SUCCESS; + } + return s8Ret; +} + + +/*======*======*======*======*======*=======* +* RSA IMPLEMENTATION * +*======*======*======*======*======*========*/ + +static void FlipBuffer(uint8 *pu8InBuffer, uint8 *pu8OutBuffer, uint16 u16BufferSize) +{ + uint16 u16Idx; + for(u16Idx = 0; u16Idx < u16BufferSize; u16Idx ++) + { +#if ENABLE_FLIPPING == 1 + pu8OutBuffer[u16Idx] = pu8InBuffer[u16BufferSize - u16Idx - 1]; +#else + pu8OutBuffer[u16Idx] = pu8InBuffer[u16Idx]; +#endif + } +} + +void BigInt_ModExp +( + uint8 *pu8X, uint16 u16XSize, + uint8 *pu8E, uint16 u16ESize, + uint8 *pu8M, uint16 u16MSize, + uint8 *pu8R, uint16 u16RSize + ) +{ + uint32 u32Reg; + uint8 au8Tmp[780] = {0}; + uint32 u32XAddr = SHARED_MEM_BASE; + uint32 u32MAddr; + uint32 u32EAddr; + uint32 u32RAddr; + uint8 u8EMswBits = 32; + uint32 u32Mprime = 0x7F; + uint16 u16XSizeWords,u16ESizeWords; + uint32 u32Exponent; + + u16XSizeWords = (u16XSize + 3) / 4; + u16ESizeWords = (u16ESize + 3) / 4; + + u32MAddr = u32XAddr + (u16XSizeWords * 4); + u32EAddr = u32MAddr + (u16XSizeWords * 4); + u32RAddr = u32EAddr + (u16ESizeWords * 4); + + /* Reset the core. + */ + u32Reg = 0; + u32Reg |= BIGINT_MISC_CTRL_CTL_RESET; + u32Reg = nm_read_reg(BIGINT_MISC_CTRL); + u32Reg &= ~BIGINT_MISC_CTRL_CTL_RESET; + u32Reg = nm_read_reg(BIGINT_MISC_CTRL); + + nm_write_block(u32RAddr,au8Tmp, u16RSize); + + /* Write Input Operands to Chip Memory. + */ + /*------- X -------*/ + FlipBuffer(pu8X,au8Tmp,u16XSize); + nm_write_block(u32XAddr,au8Tmp,u16XSizeWords * 4); + + /*------- E -------*/ + m2m_memset(au8Tmp, 0, sizeof(au8Tmp)); + FlipBuffer(pu8E, au8Tmp, u16ESize); + nm_write_block(u32EAddr, au8Tmp, u16ESizeWords * 4); + u32Exponent = GET_UINT32(au8Tmp, (u16ESizeWords * 4) - 4); + while((u32Exponent & NBIT31)== 0) + { + u32Exponent <<= 1; + u8EMswBits --; + } + + /*------- M -------*/ + m2m_memset(au8Tmp, 0, sizeof(au8Tmp)); + FlipBuffer(pu8M, au8Tmp, u16XSize); + nm_write_block(u32MAddr, au8Tmp, u16XSizeWords * 4); + + /* Program the addresses of the input operands. + */ + nm_write_reg(BIGINT_ADDR_X, u32XAddr); + nm_write_reg(BIGINT_ADDR_E, u32EAddr); + nm_write_reg(BIGINT_ADDR_M, u32MAddr); + nm_write_reg(BIGINT_ADDR_R, u32RAddr); + + /* Mprime. + */ + nm_write_reg(BIGINT_M_PRIME,u32Mprime); + + /* Length. + */ + u32Reg = (u16XSizeWords & 0xFF); + u32Reg += ((u16ESizeWords & 0xFF) << 8); + u32Reg += (u8EMswBits << 16); + nm_write_reg(BIGINT_LENGTH,u32Reg); + + /* CTRL Register. + */ + u32Reg = nm_read_reg(BIGINT_MISC_CTRL); + u32Reg ^= BIGINT_MISC_CTRL_CTL_START; + u32Reg |= BIGINT_MISC_CTRL_CTL_FORCE_BARRETT; + //u32Reg |= BIGINT_MISC_CTRL_CTL_M_PRIME_VALID; +#if ENABLE_FLIPPING == 0 + u32Reg |= BIGINT_MISC_CTRL_CTL_MSW_FIRST; +#endif + nm_write_reg(BIGINT_MISC_CTRL,u32Reg); + + /* Wait for computation to complete. */ + while(1) + { + u32Reg = nm_read_reg(BIGINT_IRQ_STS); + if(u32Reg & BIGINT_IRQ_STS_DONE) + { + break; + } + } + nm_write_reg(BIGINT_IRQ_STS,0); + m2m_memset(au8Tmp, 0, sizeof(au8Tmp)); + nm_read_block(u32RAddr, au8Tmp, u16RSize); + FlipBuffer(au8Tmp, pu8R, u16RSize); +} + + + +#define MD5_DIGEST_SIZE (16) +#define SHA1_DIGEST_SIZE (20) + +static const uint8 au8TEncodingMD5[] = +{ + 0x30, 0x20, 0x30, 0x0C, 0x06, 0x08, 0x2A, 0x86, + 0x48, 0x86, 0xF7, 0x0D, 0x02, 0x05, 0x05, 0x00, + 0x04 +}; +/*!< Fixed part of the Encoding T for the MD5 hash algorithm. +*/ + + +static const uint8 au8TEncodingSHA1[] = +{ + 0x30, 0x21, 0x30, 0x09, 0x06, 0x05, 0x2B, 0x0E, + 0x03, 0x02, 0x1A, 0x05, 0x00, 0x04 +}; +/*!< Fixed part of the Encoding T for the SHA-1 hash algorithm. +*/ + + +static const uint8 au8TEncodingSHA2[] = +{ + 0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, + 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, + 0x00, 0x04 +}; +/*!< Fixed part of the Encoding T for the SHA-2 hash algorithm. +*/ + + +sint8 m2m_rsa_sign_verify(uint8 *pu8N, uint16 u16NSize, uint8 *pu8E, uint16 u16ESize, uint8 *pu8SignedMsgHash, + uint16 u16HashLength, uint8 *pu8RsaSignature) +{ + sint8 s8Ret = M2M_RSA_SIGN_FAIL; + + if((pu8N != NULL) && (pu8E != NULL) && (pu8RsaSignature != NULL) && (pu8SignedMsgHash != NULL)) + { + uint16 u16TLength, u16TEncodingLength; + uint8 *pu8T; + uint8 au8EM[512]; + + /* Selection of correct T Encoding based on the hash size. + */ + if(u16HashLength == MD5_DIGEST_SIZE) + { + pu8T = (uint8*)au8TEncodingMD5; + u16TEncodingLength = sizeof(au8TEncodingMD5); + } + else if(u16HashLength == SHA1_DIGEST_SIZE) + { + pu8T = (uint8*)au8TEncodingSHA1; + u16TEncodingLength = sizeof(au8TEncodingSHA1); + } + else + { + pu8T = (uint8*)au8TEncodingSHA2; + u16TEncodingLength = sizeof(au8TEncodingSHA2); + } + u16TLength = u16TEncodingLength + 1 + u16HashLength; + + /* If emLen < tLen + 11. + */ + if(u16NSize >= (u16TLength + 11)) + { + uint32 u32PSLength,u32Idx = 0; + + /* + RSA verification + */ + BigInt_ModExp(pu8RsaSignature, u16NSize, pu8E, u16ESize, pu8N, u16NSize, au8EM, u16NSize); + + u32PSLength = u16NSize - u16TLength - 3; + + /* + The calculated EM must match the following pattern. + *======*======*======*======*======* + * 0x00 || 0x01 || PS || 0x00 || T * + *======*======*======*======*======* + Where PS is all 0xFF + T is defined based on the hash algorithm. + */ + if((au8EM[0] == 0x00) && (au8EM[1] == 0x01)) + { + for(u32Idx = 2; au8EM[u32Idx] == 0xFF; u32Idx ++); + if(u32Idx == (u32PSLength + 2)) + { + if(au8EM[u32Idx ++] == 0x00) + { + if(!m2m_memcmp(&au8EM[u32Idx], pu8T, u16TEncodingLength)) + { + u32Idx += u16TEncodingLength; + if(au8EM[u32Idx ++] == u16HashLength) + s8Ret = m2m_memcmp(&au8EM[u32Idx], pu8SignedMsgHash, u16HashLength); + } + } + } + } + } + } + return s8Ret; +} + + +sint8 m2m_rsa_sign_gen(uint8 *pu8N, uint16 u16NSize, uint8 *pu8d, uint16 u16dSize, uint8 *pu8SignedMsgHash, + uint16 u16HashLength, uint8 *pu8RsaSignature) +{ + sint8 s8Ret = M2M_RSA_SIGN_FAIL; + + if((pu8N != NULL) && (pu8d != NULL) && (pu8RsaSignature != NULL) && (pu8SignedMsgHash != NULL)) + { + uint16 u16TLength, u16TEncodingLength; + uint8 *pu8T; + uint8 au8EM[512]; + + /* Selection of correct T Encoding based on the hash size. + */ + if(u16HashLength == MD5_DIGEST_SIZE) + { + pu8T = (uint8*)au8TEncodingMD5; + u16TEncodingLength = sizeof(au8TEncodingMD5); + } + else if(u16HashLength == SHA1_DIGEST_SIZE) + { + pu8T = (uint8*)au8TEncodingSHA1; + u16TEncodingLength = sizeof(au8TEncodingSHA1); + } + else + { + pu8T = (uint8*)au8TEncodingSHA2; + u16TEncodingLength = sizeof(au8TEncodingSHA2); + } + u16TLength = u16TEncodingLength + 1 + u16HashLength; + + /* If emLen < tLen + 11. + */ + if(u16NSize >= (u16TLength + 11)) + { + uint16 u16PSLength = 0; + uint16 u16Offset = 0; + + /* + The calculated EM must match the following pattern. + *======*======*======*======*======* + * 0x00 || 0x01 || PS || 0x00 || T * + *======*======*======*======*======* + Where PS is all 0xFF + T is defined based on the hash algorithm. + */ + au8EM[u16Offset ++] = 0; + au8EM[u16Offset ++] = 1; + u16PSLength = u16NSize - u16TLength - 3; + m2m_memset(&au8EM[u16Offset], 0xFF, u16PSLength); + u16Offset += u16PSLength; + au8EM[u16Offset ++] = 0; + m2m_memcpy(&au8EM[u16Offset], pu8T, u16TEncodingLength); + u16Offset += u16TEncodingLength; + au8EM[u16Offset ++] = u16HashLength; + m2m_memcpy(&au8EM[u16Offset], pu8SignedMsgHash, u16HashLength); + + /* + RSA Signature Generation + */ + BigInt_ModExp(au8EM, u16NSize, pu8d, u16dSize, pu8N, u16NSize, pu8RsaSignature, u16NSize); + s8Ret = M2M_RSA_SIGN_OK; + } + } + return s8Ret; +} + +#endif /* CONF_CRYPTO */ \ No newline at end of file diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/m2m_flash.c b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/m2m_flash.c new file mode 100644 index 000000000..263571312 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/m2m_flash.c @@ -0,0 +1,553 @@ +/** + * + * \file + * + * \brief WINC Flash Interface. + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + + + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +INCLUDES +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ +#include "driver/include/m2m_flash.h" +#include "driver/include/m2m_wifi.h" +#include "driver/source/nmflash.h" +#include "driver/source/m2m_hif.h" +#include "spi_flash/include/spi_flash.h" +#include "nmdrv.h" + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +GLOBALS +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ +static tpfDataAccessFn gpfAppFn = NULL; +static uint8 gau8ItemIdentifier[20] = {0}; + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +FUNCTIONS +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ +#include "ISConstants.h" +#define malloc MALLOC +#define free FREE + +static sint8 transfer_init(void) +{ + sint8 ret = FLASH_RETURN_OK; + + /* Check module was initialized. */ + if (gu8Init == 0) + ret = FLASH_ERR_UNINIT; + return ret; +} +static sint8 init_access(void) +{ + sint8 ret = FLASH_RETURN_OK; + + gu8Reset = 0; + if (m2m_wifi_reinit_hold() != M2M_SUCCESS) + ret = FLASH_ERR_WINC_ACCESS; + + return ret; +} +static sint8 commit_access(tstrFlashAccess *pstrFlashAccess) +{ + sint8 ret = FLASH_RETURN_OK; + sint8 status = M2M_ERR_FAIL; + tstrFlashAccessPersistent *pstrPersistentInfo = &pstrFlashAccess->strPersistentInfo; + + /* + * To begin with, flash is unchanged. Later, when first flash erase/write occurs, this flag + * will be cleared. + */ + pstrPersistentInfo->u8ModeFlags |= FLASH_MODE_FLAGS_UNCHANGED; + if (pstrPersistentInfo->u8ModeFlags & FLASH_MODE_FLAGS_CS_SWITCH) + { + uint8 target = 0; + if (image_get_target(&target) != M2M_SUCCESS) + { + ret = FLASH_ERR_WINC_ACCESS; + goto ERR; + } + if (target > 0) + pstrPersistentInfo->u8ModeFlags |= FLASH_MODE_FLAGS_CS_SWITCH_TARGET; + } + + status = spi_flash_read((uint8*)pstrPersistentInfo, HOST_CONTROL_FLASH_OFFSET, FLASH_SIG_STA_SZ); + if (status == M2M_SUCCESS) + { + if ((pstrPersistentInfo->u32Signature != FLASH_SIGNATURE) || (pstrPersistentInfo->enuTransferStatus != FLASH_STATUS_EMPTY)) + status = spi_flash_erase(HOST_CONTROL_FLASH_OFFSET, HOST_CONTROL_FLASH_SZ); + } + if (status == M2M_SUCCESS) + { + pstrPersistentInfo->u32Signature = FLASH_SIGNATURE; + pstrPersistentInfo->enuTransferStatus = FLASH_STATUS_NOT_ACTIVE; + status = winc_flash_write_verify((uint8*)pstrPersistentInfo, HOST_CONTROL_FLASH_OFFSET, FLASH_SIG_STA_SZ); + if (status == M2M_SUCCESS) + { + status = winc_flash_write_verify((uint8*)pstrPersistentInfo, HOST_CONTROL_FLASH_OFFSET, sizeof(tstrFlashAccessPersistent)); + if (status == M2M_SUCCESS) + { + pstrPersistentInfo->enuTransferStatus = FLASH_STATUS_ACTIVE; + status = winc_flash_write_verify((uint8*)pstrPersistentInfo, HOST_CONTROL_FLASH_OFFSET, FLASH_SIG_STA_SZ); + gu16LastAccessId = pstrPersistentInfo->u16AppId; + gu8Success = 0; + gu8Changed = 0; + } + } + } + if (status != M2M_SUCCESS) + { + ret = FLASH_ERR_WINC_ACCESS; + goto ERR; + } + ret = transfer_run(pstrFlashAccess); +ERR: + return ret; +} +static sint8 register_app_fn(tpfDataAccessFn pfFn) +{ + sint8 ret = FLASH_RETURN_OK; + if (pfFn == NULL) + ret = FLASH_ERR_PARAM; + gpfAppFn = pfFn; + return ret; +} +static sint8 app_data_access(tenuFlashDataFnCtl enuCtl, void *pvStr) +{ + tstrDataAccessInitParamsApp init_params_app; + tstrDataAccessParamsApp params_app; + switch (enuCtl) + { + case FLASH_DATA_FN_INITIALIZE: + { + tstrDataAccessInitParams *init_params = (tstrDataAccessInitParams*)pvStr; + init_params_app.u32TotalSize = init_params->u32TotalSize; + if (init_params->u8Flags & FLASH_FN_FLAGS_READ) + init_params_app.enuRW = FLASH_DATA_FN_READ; + else if (init_params->u8Flags & FLASH_FN_FLAGS_WRITE) + init_params_app.enuRW = FLASH_DATA_FN_WRITE; + pvStr = &init_params_app; + } + break; + case FLASH_DATA_FN_DATA: + { + tstrDataAccessParams *params = (tstrDataAccessParams*)pvStr; + params_app.pu8Data = params->pu8Buf + params->u32DataOffset; + params_app.u32DataSize = params->u32DataSize; + pvStr = ¶ms_app; + } + break; + case FLASH_DATA_FN_COMPLETE: + case FLASH_DATA_FN_TERMINATE: + break; + } + return gpfAppFn(enuCtl, pvStr); +} +sint8 m2m_flash_readimage(uint8 enuImageId, uint16 u16Id, tpfDataAccessFn pfDestFn, uint32 u32DestSize) +{ + sint8 ret = FLASH_RETURN_OK; + + M2M_INFO("FA RdImage %d\n", enuImageId); + ret = transfer_init(); + if (ret < 0) + goto ERR; + ret = register_app_fn(pfDestFn); + if (ret < 0) + goto ERR; + if (u32DestSize < OTA_IMAGE_SIZE) + { + ret = FLASH_ERR_SIZE; + goto ERR; + } + if (enuImageId > FLASH_IMAGE_INACTIVE) + { + ret = FLASH_ERR_PARAM; + goto ERR; + } + + ret = init_access(); + if (ret == FLASH_RETURN_OK) + { + /* Set parameters for whole transfer. */ + tstrFlashAccess strFlashAccess; + m2m_memset((uint8*)&strFlashAccess, 0, sizeof(tstrFlashAccess)); + + strFlashAccess.strPersistentInfo.u16AppId = u16Id; + + strFlashAccess.pfDestinationFn = app_data_access; + switch (enuImageId) + { + case FLASH_IMAGE_ACTIVE: + set_internal_info(&strFlashAccess.pfSourceFn, MEM_ID_WINC_ACTIVE); + break; + case FLASH_IMAGE_INACTIVE: + set_internal_info(&strFlashAccess.pfSourceFn, MEM_ID_WINC_INACTIVE); + break; + } + strFlashAccess.u32Size = OTA_IMAGE_SIZE; + + ret = commit_access(&strFlashAccess); + } +ERR: + M2M_INFO("FAState:%d\n", ret); + return ret; +} + +sint8 m2m_flash_updateimage(uint8 u8Options, uint16 u16Id, tpfDataAccessFn pfSourceFn, uint32 u32SourceSize) +{ + sint8 ret = FLASH_RETURN_OK; + + M2M_INFO("FA Image %d\n", u8Options); + ret = transfer_init(); + if (ret < 0) + goto ERR; + if (u8Options & FLASH_UPDATEIMAGE_OPTION_UPDATE) + { + uint8 au8ImageStart[4]; + uint8 au8ImageCheck[] = {'N','M','I','S'}; + tstrDataAccessInitParams init_params = {sizeof(au8ImageStart), FLASH_FN_FLAGS_READ}; + sint8 status = M2M_SUCCESS; + + /* Check input parameters. */ + ret = register_app_fn(pfSourceFn); + if (ret < 0) + goto ERR; + if (u32SourceSize != OTA_IMAGE_SIZE) + { + ret = FLASH_ERR_PARAM; + goto ERR; + } + status = app_data_access(FLASH_DATA_FN_INITIALIZE, &init_params); + if (status == M2M_SUCCESS) + { + tstrDataAccessParams params = {au8ImageStart, sizeof(au8ImageStart), 0, sizeof(au8ImageStart)}; + status = app_data_access(FLASH_DATA_FN_DATA, ¶ms); + } + if (status != M2M_SUCCESS) + { + ret = FLASH_ERR_LOCAL_ACCESS; + goto ERR; + } + if (m2m_memcmp(au8ImageStart, au8ImageCheck, sizeof(au8ImageStart))) + { + ret = FLASH_ERR_WINC_CONFLICT; + goto ERR; + } + } + + ret = init_access(); + if (ret == FLASH_RETURN_OK) + { + /* Set parameters for whole transfer. */ + tstrFlashAccess strFlashAccess; + m2m_memset((uint8*)&strFlashAccess, 0, sizeof(tstrFlashAccess)); + + strFlashAccess.strPersistentInfo.u16AppId = u16Id; + if (u8Options & FLASH_UPDATEIMAGE_OPTION_UPDATE) + { + strFlashAccess.strPersistentInfo.u8AccessFlags = FLASH_ACCESS_WINC_MASK | FLASH_ACCESS_OPTION_ERASE_FIRST; + + strFlashAccess.pfSourceFn = app_data_access; + set_internal_info(&strFlashAccess.pfDestinationFn, MEM_ID_WINC_INACTIVE); + strFlashAccess.u32Size = OTA_IMAGE_SIZE; + } + else + strFlashAccess.u32Size = 0; + if (u8Options & FLASH_UPDATEIMAGE_OPTION_VALIDATE) + strFlashAccess.strPersistentInfo.u8ModeFlags |= FLASH_MODE_FLAGS_CS_VALIDATE_IMAGE; + if (u8Options & FLASH_UPDATEIMAGE_OPTION_SWITCH) + strFlashAccess.strPersistentInfo.u8ModeFlags |= FLASH_MODE_FLAGS_CS_SWITCH; + strFlashAccess.strPersistentInfo.u8ModeFlags |= FLASH_MODE_FLAGS_CS; + + ret = commit_access(&strFlashAccess); + } +ERR: + M2M_INFO("FAState:%d\n", ret); + return ret; +} + +static sint8 m2m_flash_rootcert_access(tenuFlashAccessItemMode enuMode, uint8 u8ModeOptions, uint8 u8AccessOptions, uint16 u16Id, tpfDataAccessFn pfFn, uint32 u32Size) +{ + sint8 ret = FLASH_RETURN_OK; + tstrRootCertEntryHeader strRootCertEntry; + uint16 u16EntrySz = 0; + + M2M_INFO("FA Rootcert %d\n", enuMode); + ret = transfer_init(); + if (ret < 0) + goto ERR; + + switch (enuMode) + { + case FLASH_ITEM_ADD: + { + sint8 status = M2M_SUCCESS; + tstrDataAccessInitParams init_params = {sizeof(strRootCertEntry), FLASH_FN_FLAGS_READ}; + + // Read the entry header + if (u32Size < sizeof(strRootCertEntry)) + { + ret = FLASH_ERR_PARAM; + goto ERR; + } + status = pfFn(FLASH_DATA_FN_INITIALIZE, &init_params); + if (status == M2M_SUCCESS) + { + tstrDataAccessParams params = {(uint8*)&strRootCertEntry, sizeof(strRootCertEntry), 0, sizeof(strRootCertEntry)}; + status = pfFn(FLASH_DATA_FN_DATA, ¶ms); + } + if (status != M2M_SUCCESS) + { + ret = FLASH_ERR_LOCAL_ACCESS; + goto ERR; + } + // Check source size matches size calculated from entry header. + status = rootcert_get_size(&strRootCertEntry, &u16EntrySz); + if ((status != M2M_SUCCESS) || (u32Size != u16EntrySz)) + { + ret = FLASH_ERR_PARAM; + goto ERR; + } + } + break; + case FLASH_ITEM_READ: + case FLASH_ITEM_REMOVE: + m2m_memcpy(strRootCertEntry.au8SHA1NameHash, gau8ItemIdentifier, sizeof(gau8ItemIdentifier)); + m2m_memset(gau8ItemIdentifier, 0, sizeof(gau8ItemIdentifier)); + break; + case FLASH_ITEM_READIDX: + // Hack strRootCertEntry to carry the index from u8ModeOptions. + *(uint32*)&strRootCertEntry = u8ModeOptions; + break; + default: + /* No other item modes supported. */ + ret = FLASH_ERR_PARAM; + goto ERR; + break; + } + + ret = init_access(); + if (ret == FLASH_RETURN_OK) + { + /* Now we can access the items in flash. */ + uint8 *pu8Buff = malloc(M2M_TLS_ROOTCER_FLASH_SZ); + uint32 u32Offset = 0; + if (pu8Buff == NULL) + { + ret = FLASH_ERR_INTERNAL; + goto ERR; + } + ret = rootcert_access(enuMode, &strRootCertEntry, &u16EntrySz, pu8Buff, &u32Offset); + if (ret == FLASH_RETURN_OK) + { + /* Set parameters for whole transfer, according to enuMode. */ + sint8 status = M2M_SUCCESS; + tstrDataAccessInitParams init_params = {u16EntrySz, 0}; + tstrDataAccessParams data_params = {pu8Buff + u32Offset, u16EntrySz, 0, u16EntrySz}; + tstrFlashAccess strFlashAccess; + + m2m_memset((uint8*)&strFlashAccess, 0, sizeof(tstrFlashAccess)); + strFlashAccess.strPersistentInfo.u16AppId = u16Id; + strFlashAccess.strPersistentInfo.u8AccessFlags = u8AccessOptions; + + switch (enuMode) + { + case FLASH_ITEM_ADD: + init_params.u8Flags = FLASH_FN_FLAGS_READ; + status = pfFn(FLASH_DATA_FN_INITIALIZE, &init_params); + if (status == M2M_SUCCESS) + status = pfFn(FLASH_DATA_FN_DATA, &data_params); + if (status != M2M_SUCCESS) + { + ret = FLASH_ERR_LOCAL_ACCESS; + pfFn(FLASH_DATA_FN_TERMINATE, NULL); + break; + } + u32Offset += u16EntrySz; + // intentional fallthrough. + case FLASH_ITEM_REMOVE: + status = spi_flash_erase(M2M_BACKUP_FLASH_OFFSET, M2M_BACKUP_FLASH_SZ); + if (status == M2M_SUCCESS) + status = winc_flash_write_verify(pu8Buff, M2M_BACKUP_FLASH_OFFSET, u32Offset); + if (status != M2M_SUCCESS) + { + ret = FLASH_ERR_WINC_ACCESS; + break; + } + set_internal_info(NULL, M2M_TLS_ROOTCER_FLASH_OFFSET); + strFlashAccess.strPersistentInfo.u8ModeFlags |= FLASH_MODE_FLAGS_DATA_IN_BACKUP; + break; + case FLASH_ITEM_READ: + case FLASH_ITEM_READIDX: + // Check source size is sufficient for reading entry. + if (u32Size < u16EntrySz) + { + ret = FLASH_ERR_SIZE; + break; + } + init_params.u8Flags = FLASH_FN_FLAGS_WRITE; + status = pfFn(FLASH_DATA_FN_INITIALIZE, &init_params); + if (status == M2M_SUCCESS) + status = pfFn(FLASH_DATA_FN_DATA, &data_params); + if (status != M2M_SUCCESS) + { + ret = FLASH_ERR_LOCAL_ACCESS; + pfFn(FLASH_DATA_FN_TERMINATE, NULL); + break; + } + break; + } + if (ret == 0) + { + ret = commit_access(&strFlashAccess); + if (enuMode != FLASH_ITEM_REMOVE) + pfFn(FLASH_DATA_FN_COMPLETE, NULL); + } + } + free(pu8Buff); + } +ERR: + M2M_INFO("FAState:%d\n", ret); + return ret; +} +sint8 m2m_flash_rootcert_add(uint16 u16Id, tpfDataAccessFn pfSourceFn, uint32 u32SourceSize) +{ + sint8 ret = FLASH_RETURN_OK; + + ret = register_app_fn(pfSourceFn); + if (ret == FLASH_RETURN_OK) + ret = m2m_flash_rootcert_access(FLASH_ITEM_ADD, 0, FLASH_ACCESS_OPTION_COMPARE_AFTER, u16Id, app_data_access, u32SourceSize); + return ret; +} +sint8 m2m_flash_rootcert_remove(uint16 u16Id, uint8 *pu8Identifier, uint32 u32IdentifierSz) +{ + sint8 ret = FLASH_ERR_PARAM; + + if ((pu8Identifier != NULL) && (u32IdentifierSz == 20)) + { + m2m_memcpy(gau8ItemIdentifier, pu8Identifier, u32IdentifierSz); + ret = m2m_flash_rootcert_access(FLASH_ITEM_REMOVE, 0, FLASH_ACCESS_OPTION_COMPARE_AFTER, u16Id, NULL, 0); + } + return ret; +} +sint8 m2m_flash_rootcert_read(uint16 u16Id, tpfDataAccessFn pfDestFn, uint32 u32DestSize, uint8 *pu8Identifier, uint32 u32IdentifierSz) +{ + sint8 ret = FLASH_RETURN_OK; + + ret = register_app_fn(pfDestFn); + if (ret == FLASH_RETURN_OK) + { + ret = FLASH_ERR_PARAM; + if ((pu8Identifier != NULL) && (u32IdentifierSz == 20)) + { + m2m_memcpy(gau8ItemIdentifier, pu8Identifier, u32IdentifierSz); + ret = m2m_flash_rootcert_access(FLASH_ITEM_READ, 0, 0, u16Id, app_data_access, u32DestSize); + } + } + return ret; +} +sint8 m2m_flash_rootcert_readidx(uint16 u16Id, tpfDataAccessFn pfDestFn, uint32 u32DestSize, uint8 u8Index) +{ + sint8 ret = FLASH_RETURN_OK; + + ret = register_app_fn(pfDestFn); + if (ret == FLASH_RETURN_OK) + ret = m2m_flash_rootcert_access(FLASH_ITEM_READIDX, u8Index, 0, u16Id, app_data_access, u32DestSize); + return ret; +} + +void m2m_flash_get_state(tstrFlashState *pstrState) +{ + if (gu8Reset == 0) + { + sint8 status = M2M_ERR_FAIL; + tstrFlashAccessPersistent strSavedFlashAccess; + + status = spi_flash_read((uint8*)&strSavedFlashAccess, HOST_CONTROL_FLASH_OFFSET, sizeof(tstrFlashAccessPersistent)); + if ((status == M2M_SUCCESS) && (strSavedFlashAccess.u32Signature == FLASH_SIGNATURE)) + { + switch (strSavedFlashAccess.enuTransferStatus) + { + case FLASH_STATUS_ACTIVE: + if (strSavedFlashAccess.u8ModeFlags & FLASH_MODE_FLAGS_CS_SWITCH) + { + // Check to see if switch happened before we were interrupted. If so we had actually completed. + uint8 target; + if (image_get_target(&target) == M2M_SUCCESS) + { + if ((target == 0) && (strSavedFlashAccess.u8ModeFlags & FLASH_MODE_FLAGS_CS_SWITCH_TARGET)) + gu8Success = 1; + if ((target > 0) && !(strSavedFlashAccess.u8ModeFlags & FLASH_MODE_FLAGS_CS_SWITCH_TARGET)) + gu8Success = 1; + } + } + gu16LastAccessId = strSavedFlashAccess.u16AppId; + gu8Changed = !(strSavedFlashAccess.u8ModeFlags & FLASH_MODE_FLAGS_UNCHANGED); + if (gu8Success == 1) + { + strSavedFlashAccess.enuTransferStatus = FLASH_STATUS_DONE; + winc_flash_write_verify((uint8*)&strSavedFlashAccess, HOST_CONTROL_FLASH_OFFSET, FLASH_SIG_STA_SZ); + } + break; + case FLASH_STATUS_DONE: + gu16LastAccessId = strSavedFlashAccess.u16AppId; + gu8Changed = !(strSavedFlashAccess.u8ModeFlags & FLASH_MODE_FLAGS_UNCHANGED); + gu8Success = 1; + break; + default: + break; + } + } + } + m2m_memset((uint8*)pstrState, 0, sizeof(tstrFlashState)); + if (gu16LastAccessId) + { + pstrState->u16LastAccessId = gu16LastAccessId; + pstrState->u8Success = gu8Success; + pstrState->u8Changed = gu8Changed; + } + pstrState->u8Init = gu8Init; + pstrState->u8Reset = gu8Reset; +} +sint8 m2m_flash_init(void) +{ + if (gu8Reset == 0) + { + // WINC backup recovery may be needed. + if (recover_backup() == FLASH_RETURN_OK) + { + gu8Init = 1; + gu8Reset = 1; + return M2M_SUCCESS; + } + } + return M2M_ERR_FAIL; +} diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/m2m_hif.c b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/m2m_hif.c new file mode 100644 index 000000000..592584d8c --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/m2m_hif.c @@ -0,0 +1,870 @@ +/** + * + * \file + * + * \brief This module contains M2M host interface APIs implementation. + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "common/include/nm_common.h" +#include "driver/source/nmbus.h" +#include "driver/source/nmdrv.h" +#include "bsp/include/nm_bsp.h" +#include "m2m_hif.h" +#include "driver/include/m2m_types.h" +#include "driver/source/nmasic.h" +#include "driver/include/m2m_periph.h" + +#if (defined NM_EDGE_INTERRUPT)&&(defined NM_LEVEL_INTERRUPT) +#error "only one type of interrupt NM_EDGE_INTERRUPT,NM_LEVEL_INTERRUPT" +#endif + +#if !((defined NM_EDGE_INTERRUPT)||(defined NM_LEVEL_INTERRUPT)) +#error "define interrupt type NM_EDGE_INTERRUPT,NM_LEVEL_INTERRUPT" +#endif + +#ifndef CORTUS_APP +#define NMI_AHB_DATA_MEM_BASE 0x30000 +#define NMI_AHB_SHARE_MEM_BASE 0xd0000 + +#define WIFI_HOST_RCV_CTRL_0 (0x1070) +#define WIFI_HOST_RCV_CTRL_1 (0x1084) +#define WIFI_HOST_RCV_CTRL_2 (0x1078) +#define WIFI_HOST_RCV_CTRL_3 (0x106c) +#define WAKE_VALUE (0x5678) +#define SLEEP_VALUE (0x4321) +#define WAKE_REG (0x1074) + +#define INTERRUPT_CORTUS_0_3000D0 (0x10a8) +#define INTERRUPT_CORTUS_1_3000D0 (0x10ac) +#define INTERRUPT_CORTUS_2_3000D0 (0x10b0) +#define INTERRUPT_CORTUS_3_3000D0 (0x10b4) + + +static volatile uint8 gu8ChipMode = 0; +static volatile uint8 gu8ChipSleep = 0; +static volatile uint8 gu8HifSizeDone = 0; +static volatile uint8 gu8Interrupt = 0; +static volatile uint8 gu8Yield = 0; + +/* + Special codes for managing HIF restriction to OTA rollback/switch only +*/ +#define HIF_OTA_RB_ONLY 0xFFFF +#define HIFCODE_OTA_RB ((M2M_REQ_GROUP_OTA << 8) | M2M_OTA_REQ_ROLLBACK) +#define HIFCODE_OTA_SW ((M2M_REQ_GROUP_OTA << 8) | M2M_OTA_REQ_SWITCH_FIRMWARE) +#define HIFCODE_SSL_WRITECERT ((M2M_REQ_GROUP_SSL << 8) | M2M_SSL_REQ_WRITE_OWN_CERTS) +#define HIFCODE_WIFI_PASSIVESCAN ((M2M_REQ_GROUP_WIFI << 8) | M2M_WIFI_REQ_PASSIVE_SCAN) +/* + List of new HIF messages (since last HIF major increase) + Each entry is formed of ((GroupId << 8) | OpCode) + Additionally, entry 0 used to indicate OTA RB/SW only. +*/ +#define NEW_HIF_LIST HIF_OTA_RB_ONLY, HIFCODE_SSL_WRITECERT, HIFCODE_WIFI_PASSIVESCAN +/* + Array of HIF messages which are not supported by Firmware. + During hif_init() this array is rebased using an offset determined by Firmware HIF level. +*/ +static uint16 gau16HifBlacklist[] = {NEW_HIF_LIST}; +#define HIF_BLACKLIST_SZ (sizeof(gau16HifBlacklist)/sizeof(gau16HifBlacklist[0])) +static uint8 gu8HifBlOffset = 0; + +tpfHifCallBack pfWifiCb = NULL; /*!< pointer to Wi-Fi call back function */ +tpfHifCallBack pfIpCb = NULL; /*!< pointer to Socket call back function */ +tpfHifCallBack pfOtaCb = NULL; /*!< pointer to OTA call back function */ +tpfHifCallBack pfSigmaCb = NULL; +tpfHifCallBack pfHifCb = NULL; +tpfHifCallBack pfSSLCb = NULL; + +static void isr(void) +{ + gu8Interrupt++; +#ifdef NM_LEVEL_INTERRUPT + nm_bsp_interrupt_ctrl(0); +#endif +} + +static sint8 hif_set_rx_done(void) +{ + uint32 reg; + sint8 ret = M2M_SUCCESS; +#ifdef NM_EDGE_INTERRUPT + nm_bsp_interrupt_ctrl(1); +#endif + + + if (ISNMC3400(nmi_get_chipid())) { + ret = nm_write_reg(INTERRUPT_CORTUS_0_3000D0,1); + if(ret != M2M_SUCCESS)goto ERR1; + } else { + ret = nm_read_reg_with_ret(WIFI_HOST_RCV_CTRL_0,®); + if(ret != M2M_SUCCESS)goto ERR1; + //reg &= ~(1<<0); + + /* Set RX Done */ + reg |= (1<<1); + ret = nm_write_reg(WIFI_HOST_RCV_CTRL_0,reg); + if(ret != M2M_SUCCESS)goto ERR1; + } + +#ifdef NM_LEVEL_INTERRUPT + nm_bsp_interrupt_ctrl(1); +#endif +ERR1: + return ret; + +} +/** +* @fn static void m2m_hif_cb(uint8 u8OpCode, uint16 u16DataSize, uint32 u32Addr) +* @brief WiFi call back function +* @param [in] u8OpCode +* HIF Opcode type. +* @param [in] u16DataSize +* HIF data length. +* @param [in] u32Addr +* HIF address. +* @author +* @date +* @version 1.0 +*/ +static void m2m_hif_cb(uint8 u8OpCode, uint16 u16DataSize, uint32 u32Addr) +{ + + +} +/** +* @fn NMI_API sint8 hif_chip_wake(void); +* @brief To Wakeup the chip. +* @return The function shall return ZERO for successful operation and a negative value otherwise. +*/ + +sint8 hif_chip_wake(void) +{ + sint8 ret = M2M_SUCCESS; + if(gu8ChipSleep == 0) + { + if((gu8ChipMode == M2M_PS_DEEP_AUTOMATIC)||(gu8ChipMode == M2M_PS_MANUAL)) + { + ret = nm_clkless_wake(); + if(ret != M2M_SUCCESS)goto ERR1; + ret = nm_write_reg(WAKE_REG, WAKE_VALUE); + if(ret != M2M_SUCCESS)goto ERR1; + } + else + { + } + } + gu8ChipSleep++; +ERR1: + return ret; +} +/*! +@fn \ + NMI_API void hif_set_sleep_mode(uint8 u8Pstype); + +@brief + Set the sleep mode of the HIF layer. + +@param [in] u8Pstype + Sleep mode. + +@return + The function SHALL return 0 for success and a negative value otherwise. +*/ + +void hif_set_sleep_mode(uint8 u8Pstype) +{ + gu8ChipMode = u8Pstype; +} +/*! +@fn \ + NMI_API uint8 hif_get_sleep_mode(void); + +@brief + Get the sleep mode of the HIF layer. + +@return + The function SHALL return the sleep mode of the HIF layer. +*/ + +uint8 hif_get_sleep_mode(void) +{ + return gu8ChipMode; +} +/** +* @fn NMI_API sint8 hif_chip_sleep(void); +* @brief To make the chip sleep. +* @return The function shall return ZERO for successful operation and a negative value otherwise. +*/ + +sint8 hif_chip_sleep(void) +{ + sint8 ret = M2M_SUCCESS; + + if(gu8ChipSleep >= 1) + { + gu8ChipSleep--; + } + + if(gu8ChipSleep == 0) + { + if((gu8ChipMode == M2M_PS_DEEP_AUTOMATIC)||(gu8ChipMode == M2M_PS_MANUAL)) + { + uint32 reg = 0; + ret = nm_write_reg(WAKE_REG, SLEEP_VALUE); + if(ret != M2M_SUCCESS)goto ERR1; + /* Clear bit 1 */ + ret = nm_read_reg_with_ret(0x1, ®); + if(ret != M2M_SUCCESS)goto ERR1; + if(reg&0x2) + { + reg &=~(1 << 1); + ret = nm_write_reg(0x1, reg); + } + } + else + { + } + } +ERR1: + return ret; +} +/** +* @fn NMI_API sint8 hif_init(void * arg); +* @brief To initialize HIF layer. +* @param [in] arg +* Pointer to the arguments. +* @return The function shall return ZERO for successful operation and a negative value otherwise. +*/ + +sint8 hif_init(void * arg) +{ + pfWifiCb = NULL; + pfIpCb = NULL; + + gu8ChipSleep = 0; + gu8ChipMode = M2M_NO_PS; + + gu8Interrupt = 0; + nm_bsp_register_isr(isr); + + gu8HifBlOffset = 0; + hif_register_cb(M2M_REQ_GROUP_HIF,m2m_hif_cb); + + return M2M_SUCCESS; +} +/** +* @fn NMI_API sint8 hif_deinit(void * arg); +* @brief To Deinitialize HIF layer. +* @param [in] arg +* Pointer to the arguments. +* @return The function shall return ZERO for successful operation and a negative value otherwise. +*/ +sint8 hif_deinit(void * arg) +{ + sint8 ret = M2M_SUCCESS; +#if 0 + uint32 reg = 0, cnt=0; + while (reg != M2M_DISABLE_PS) + { + nm_bsp_sleep(1); + reg = nm_read_reg(STATE_REG); + if(++cnt > 1000) + { + M2M_DBG("failed to stop power save\n"); + break; + } + } +#endif + ret = hif_chip_wake(); + + gu8ChipMode = 0; + gu8ChipSleep = 0; + gu8HifSizeDone = 0; + gu8Interrupt = 0; + + pfWifiCb = NULL; + pfIpCb = NULL; + pfOtaCb = NULL; + pfHifCb = NULL; + + return ret; +} +/** +* @fn sint8 hif_check_compatibility(uint16 u16HifInfo); +* @brief +* To check the compatibility of an image with the current driver. +* @param [in] u16HifInfo +* HIF info of image to be checked. +* @return The function shall return ZERO for compatible image and a negative value otherwise. +*/ +sint8 hif_check_compatibility(uint16 u16HifInfo) +{ + sint8 ret = M2M_ERR_FW_VER_MISMATCH; + if((M2M_GET_HIF_BLOCK(u16HifInfo) == M2M_HIF_BLOCK_VALUE) && (M2M_GET_HIF_MAJOR(u16HifInfo) == M2M_HIF_MAJOR_VALUE)) + { + ret = M2M_SUCCESS; + } + return ret; +} +/** +* @fn sint8 hif_enable_access(void); +* @brief +* To enable access to HIF layer, based on HIF level of Firmware. +* This function reads HIF level directly from a register written by Firmware. +* @return The function shall return ZERO for full match operation and a negative value if operation is restricted. +*/ +sint8 hif_enable_access(void) +{ + sint8 ret = M2M_SUCCESS; + uint16 fw_hif_info = 0; + + ret = nm_get_hif_info(&fw_hif_info, NULL); + if(ret == M2M_SUCCESS) + { + ret = hif_check_compatibility(fw_hif_info); + if(ret == M2M_SUCCESS) + { + switch(M2M_GET_HIF_MINOR(fw_hif_info)) + { + case 0: + gu8HifBlOffset = 1; + break; + case 1: + gu8HifBlOffset = 2; + break; + case 2: + gu8HifBlOffset = 2; + break; + case 3: + gu8HifBlOffset = 3; + break; + // Additional case to be added each time hif minor increments. + // All additional cases to be removed in the event of a hif major increment. + // Default catches all cases in which hif minor is greater in Firmware than in Driver. + default: + gu8HifBlOffset = HIF_BLACKLIST_SZ; + break; + } + } + else + { + gu8HifBlOffset = 0; + M2M_ERR("HIF access limited to OTA Switch/Rollback only\n"); + } + } + return ret; +} +/** +* @fn sint8 hif_check_code(uint8 u8Gid, uint8 u8OpCode); +* @brief +* To check that a particular hif message is supported with the current driver/firmware pair. +* @param [in] u8Gid +* Group ID. +* @param [in] u8Opcode +* Operation ID. +* @return The function shall return ZERO for support and a negative value otherwise. +*/ +sint8 hif_check_code(uint8 u8Gid, uint8 u8OpCode) +{ + uint8 u8BlId; + uint16 u16HifCode = ((uint16)u8Gid<<8) | u8OpCode; + if((u16HifCode == HIFCODE_OTA_RB) || (u16HifCode == HIFCODE_OTA_SW)) + { + return M2M_SUCCESS; + } + if(gu8HifBlOffset == 0) + { + M2M_ERR("HIF OTA rb/sw only\n"); + return M2M_ERR_SEND; + } + for(u8BlId = gu8HifBlOffset; u8BlId < HIF_BLACKLIST_SZ; u8BlId++) + { + if(u16HifCode == gau16HifBlacklist[u8BlId]) + { + M2M_ERR("HIF message unsupported\n"); + return M2M_ERR_SEND; + } + } + return M2M_SUCCESS; +} +/** +* @fn NMI_API sint8 hif_send(uint8 u8Gid,uint8 u8Opcode,uint8 *pu8CtrlBuf,uint16 u16CtrlBufSize, + uint8 *pu8DataBuf,uint16 u16DataSize, uint16 u16DataOffset) +* @brief Send packet using host interface. + +* @param [in] u8Gid +* Group ID. +* @param [in] u8Opcode +* Operation ID. +* @param [in] pu8CtrlBuf +* Pointer to the Control buffer. +* @param [in] u16CtrlBufSize + Control buffer size. +* @param [in] u16DataOffset + Packet Data offset. +* @param [in] pu8DataBuf +* Packet buffer Allocated by the caller. +* @param [in] u16DataSize + Packet buffer size (including the HIF header). +* @return The function shall return ZERO for successful operation and a negative value otherwise. +*/ + +sint8 hif_send(uint8 u8Gid,uint8 u8Opcode,uint8 *pu8CtrlBuf,uint16 u16CtrlBufSize, + uint8 *pu8DataBuf,uint16 u16DataSize, uint16 u16DataOffset) +{ + sint8 ret = M2M_ERR_SEND; + volatile tstrHifHdr strHif; + + strHif.u8Opcode = u8Opcode&(~NBIT7); + strHif.u8Gid = u8Gid; + strHif.u16Length = M2M_HIF_HDR_OFFSET; + if(pu8DataBuf != NULL) + { + strHif.u16Length += u16DataOffset + u16DataSize; + } + else + { + strHif.u16Length += u16CtrlBufSize; + } + + ret = hif_check_code(strHif.u8Gid, strHif.u8Opcode); + if(ret != M2M_SUCCESS) + { + goto ERR1; + } + + ret = hif_chip_wake(); + if(ret == M2M_SUCCESS) + { + volatile uint32 reg, dma_addr = 0; + volatile uint16 cnt = 0; + + reg = 0UL; + reg |= (uint32)u8Gid; + reg |= ((uint32)u8Opcode<<8); + reg |= ((uint32)strHif.u16Length<<16); + ret = nm_write_reg(NMI_STATE_REG,reg); + if(M2M_SUCCESS != ret) goto ERR1; + + reg = 0; + reg |= (1<<1); + ret = nm_write_reg(WIFI_HOST_RCV_CTRL_2, reg); + if(M2M_SUCCESS != ret) goto ERR1; + + + if (ISNMC3400(nmi_get_chipid())) { + + ret = nm_write_reg(INTERRUPT_CORTUS_1_3000D0, 1); + if(M2M_SUCCESS != ret) goto ERR1; + } + + dma_addr = 0; + + //nm_bsp_interrupt_ctrl(0); + + for(cnt = 0; cnt < 1000*5; cnt ++) + { + ret = nm_read_reg_with_ret(WIFI_HOST_RCV_CTRL_2,(uint32 *)®); + if(ret != M2M_SUCCESS) break; + + if (!(reg & 0x2)) + { + ret = nm_read_reg_with_ret(0x150400,(uint32 *)&dma_addr); + if(ret != M2M_SUCCESS) { + /*in case of read error clear the dma address and return error*/ + dma_addr = 0; + } + /*in case of success break */ + break; + } + //If we are struggling to get a response, start waiting longer + if (cnt>=1000) + nm_bsp_sleep(5); + } + //nm_bsp_interrupt_ctrl(1); + + if (dma_addr != 0) + { + volatile uint32 u32CurrAddr; + u32CurrAddr = dma_addr; + strHif.u16Length=NM_BSP_B_L_16(strHif.u16Length); + M2M_DBG("Writing into %lx %ld\n", dma_addr, strHif.u16Length); + ret = nm_write_block(u32CurrAddr, (uint8*)&strHif, M2M_HIF_HDR_OFFSET); + if(M2M_SUCCESS != ret) goto ERR1; + u32CurrAddr += M2M_HIF_HDR_OFFSET; + if(pu8CtrlBuf != NULL) + { + ret = nm_write_block(u32CurrAddr, pu8CtrlBuf, u16CtrlBufSize); + if(M2M_SUCCESS != ret) goto ERR1; + u32CurrAddr += u16CtrlBufSize; + } + if(pu8DataBuf != NULL) + { + u32CurrAddr += (u16DataOffset - u16CtrlBufSize); + ret = nm_write_block(u32CurrAddr, pu8DataBuf, u16DataSize); + if(M2M_SUCCESS != ret) goto ERR1; + u32CurrAddr += u16DataSize; + } + + reg = dma_addr << 2; + + /* MERGEBUG: TODO: Following line of code is to generate the interrupt which + is not needed for 3400, need to check if there are any side effects of keeping it + */ + reg |= (1 << 1); + ret = nm_write_reg(WIFI_HOST_RCV_CTRL_3, reg); + if(M2M_SUCCESS != ret) goto ERR1; + + if (ISNMC3400(nmi_get_chipid())) { + ret = nm_write_reg(INTERRUPT_CORTUS_2_3000D0, 1); + if(M2M_SUCCESS != ret) goto ERR1; + } + } + else + { + M2M_DBG("Failed to alloc rx size\n"); + ret = M2M_ERR_MEM_ALLOC; + goto ERR1; + } + + } + else + { + M2M_ERR("(HIF)Fail to wakup the chip\n"); + goto ERR1; + } + ret = hif_chip_sleep(); + +ERR1: + return ret; +} +/** +* @fn hif_isr +* @brief Host interface interrupt service routine +* @author M. Abdelmawla +* @date 15 July 2012 +* @return 1 in case of interrupt received else 0 will be returned +* @version 1.0 +*/ +static sint8 hif_isr(void) +{ + sint8 ret = M2M_SUCCESS; + uint32 reg; + volatile tstrHifHdr strHif; + + + //if(ret == M2M_SUCCESS) + { + ret = nm_read_reg_with_ret(0x1070, ®); + if(M2M_SUCCESS == ret) + { + if(reg & 0x1) /* New interrupt has been received */ + { + uint16 size; + + nm_bsp_interrupt_ctrl(0); + /*Clearing RX interrupt*/ + ret = nm_read_reg_with_ret(WIFI_HOST_RCV_CTRL_0,®); + if(ret != M2M_SUCCESS)goto ERR1; + reg &= ~(1<<0); + ret = nm_write_reg(WIFI_HOST_RCV_CTRL_0,reg); + if(ret != M2M_SUCCESS)goto ERR1; + /* read the rx size */ + ret = nm_read_reg_with_ret(WIFI_HOST_RCV_CTRL_0, ®); + if(M2M_SUCCESS != ret) + { + M2M_ERR("(hif) WIFI_HOST_RCV_CTRL_0 bus fail\n"); + nm_bsp_interrupt_ctrl(1); + goto ERR1; + } + gu8HifSizeDone = 0; + size = (uint16)((reg >> 2) & 0xfff); + if (size > 0) { + uint32 address = 0; + /** + start bus transfer + **/ + ret = nm_read_reg_with_ret(WIFI_HOST_RCV_CTRL_1, &address); + if(M2M_SUCCESS != ret) + { + M2M_ERR("(hif) WIFI_HOST_RCV_CTRL_1 bus fail\n"); + nm_bsp_interrupt_ctrl(1); + goto ERR1; + } + ret = nm_read_block(address, (uint8*)&strHif, sizeof(tstrHifHdr)); + strHif.u16Length = NM_BSP_B_L_16(strHif.u16Length); + if(M2M_SUCCESS != ret) + { + M2M_ERR("(hif) address bus fail\n"); + nm_bsp_interrupt_ctrl(1); + goto ERR1; + } + if(strHif.u16Length != size) + { + if((size - strHif.u16Length) > 4) + { + M2M_ERR("(hif) Corrupted packet Size = %u \n", + size, strHif.u16Length, strHif.u8Gid, strHif.u8Opcode); + nm_bsp_interrupt_ctrl(1); + ret = M2M_ERR_BUS_FAIL; + goto ERR1; + } + } + + if(M2M_REQ_GROUP_WIFI == strHif.u8Gid) + { + if(pfWifiCb) + pfWifiCb(strHif.u8Opcode,strHif.u16Length - M2M_HIF_HDR_OFFSET, address + M2M_HIF_HDR_OFFSET); + + } + else if(M2M_REQ_GROUP_IP == strHif.u8Gid) + { + if(pfIpCb) + pfIpCb(strHif.u8Opcode,strHif.u16Length - M2M_HIF_HDR_OFFSET, address + M2M_HIF_HDR_OFFSET); + } + else if(M2M_REQ_GROUP_OTA == strHif.u8Gid) + { + if(pfOtaCb) + pfOtaCb(strHif.u8Opcode,strHif.u16Length - M2M_HIF_HDR_OFFSET, address + M2M_HIF_HDR_OFFSET); + } + else if(M2M_REQ_GROUP_SIGMA == strHif.u8Gid) + { + if(pfSigmaCb) + pfSigmaCb(strHif.u8Opcode,strHif.u16Length - M2M_HIF_HDR_OFFSET, address + M2M_HIF_HDR_OFFSET); + } + else if(M2M_REQ_GROUP_SSL == strHif.u8Gid) + { + if(pfSSLCb) + pfSSLCb(strHif.u8Opcode,strHif.u16Length - M2M_HIF_HDR_OFFSET, address + M2M_HIF_HDR_OFFSET); + } + else + { + M2M_ERR("(hif) invalid group ID\n"); + ret = M2M_ERR_BUS_FAIL; + goto ERR1; + } + #ifndef ENABLE_UNO_BOARD + if(!gu8HifSizeDone) + { + M2M_ERR("(hif) host app didn't set RX Done\n"); + ret = hif_set_rx_done(); + } + #endif + } + else + { + ret = M2M_ERR_RCV; + M2M_ERR("(hif) Wrong Size\n"); + goto ERR1; + } + } + else + { +#ifndef WIN32 + M2M_ERR("(hif) False interrupt %lx",reg); +#endif + } + } + else + { + M2M_ERR("(hif) Fail to Read interrupt reg\n"); + } + } + +ERR1: + return ret; +} + +/** +* @fn hif_handle_isr(void) +* @brief Handle interrupt received from NMC1500 firmware. +* @return The function SHALL return 0 for success and a negative value otherwise. +*/ + +void hif_yield(void) +{ + gu8Yield = 1; +} + +sint8 hif_handle_isr(void) +{ + sint8 ret = M2M_SUCCESS; + + if (gu8Interrupt) { + ret = hif_chip_wake(); + if(ret == M2M_SUCCESS) + { + gu8Yield = 0; + while (gu8Interrupt && !gu8Yield) { + /*must be at that place because of the race of interrupt increment and that decrement*/ + /*when the interrupt enabled*/ + gu8Interrupt--; + while(1) + { + ret = hif_isr(); + if(ret == M2M_SUCCESS) { + /*we will try forever until we get that interrupt*/ + /*Fail return errors here due to bus errors (reading expected values)*/ + break; + } else { + M2M_ERR("(HIF) Fail to handle interrupt %d try Again..\n",ret); + } + } + } + ret = hif_chip_sleep(); + } + else { + M2M_ERR("(hif) FAIL to wakeup the chip\n"); + } + } + return ret; +} +/* +* @fn hif_receive +* @brief Host interface interrupt service routine +* @param [in] u32Addr +* Receive start address +* @param [out] pu8Buf +* Pointer to receive buffer. Allocated by the caller +* @param [in] u16Sz +* Receive buffer size +* @param [in] isDone +* If you don't need any more packets send True otherwise send false +* @return The function shall return ZERO for successful operation and a negative value otherwise. +*/ +sint8 hif_receive(uint32 u32Addr, uint8 *pu8Buf, uint16 u16Sz, uint8 isDone) +{ + uint32 address, reg; + uint16 size; + sint8 ret = M2M_SUCCESS; + + if(u32Addr == 0 || pu8Buf == NULL || u16Sz == 0) + { + if(isDone) + { + gu8HifSizeDone = 1; + + /* set RX done */ + ret = hif_set_rx_done(); + + if((u32Addr == 0) && (pu8Buf == NULL) && (u16Sz == 0)) + return M2M_SUCCESS; + } + + ret = M2M_ERR_FAIL; + M2M_ERR(" hif_receive: Invalid argument\n"); + goto ERR1; + } + + ret = nm_read_reg_with_ret(WIFI_HOST_RCV_CTRL_0,®); + if(ret != M2M_SUCCESS)goto ERR1; + + + size = (uint16)((reg >> 2) & 0xfff); + ret = nm_read_reg_with_ret(WIFI_HOST_RCV_CTRL_1,&address); + if(ret != M2M_SUCCESS)goto ERR1; + + /* Receive the payload */ + ret = nm_read_block(u32Addr, pu8Buf, u16Sz); + if(ret != M2M_SUCCESS)goto ERR1; + + if(u16Sz > size) + { + ret = M2M_ERR_FAIL; + M2M_ERR("APP Requested Size is larger than the recived buffer size <%d><%d>\n",u16Sz, size); + goto ERR1; + } + if((u32Addr < address)||((u32Addr + u16Sz)>(address+size))) + { + ret = M2M_ERR_FAIL; + M2M_ERR("APP Requested Address beyond the recived buffer address and length\n"); + goto ERR1; + } + + /* check if this is the last packet */ + if(isDone || (((address+size) - (u32Addr+u16Sz)) == 0) || + ((4 - ((u32Addr+u16Sz) & 3)) == ((address+size) - (u32Addr+u16Sz)))) /* Length in the RCV CTRL 0 register is rounded off to 4 by the firmware, + but length inside the HIF header is not, Hence consider done if number + of rounding bytes equal to length left to read */ + { + gu8HifSizeDone = 1; + + /* set RX done */ + ret = hif_set_rx_done(); + } + + + +ERR1: + return ret; +} + +/** +* @fn hif_register_cb +* @brief To set Callback function for every component +* @param [in] u8Grp +* Group to which the Callback function should be set. +* @param [in] fn +* function to be set +* @return The function shall return ZERO for successful operation and a negative value otherwise. +*/ + +sint8 hif_register_cb(uint8 u8Grp,tpfHifCallBack fn) +{ + sint8 ret = M2M_SUCCESS; + switch(u8Grp) + { + case M2M_REQ_GROUP_IP: + pfIpCb = fn; + break; + case M2M_REQ_GROUP_WIFI: + pfWifiCb = fn; + break; + case M2M_REQ_GROUP_OTA: + pfOtaCb = fn; + break; + case M2M_REQ_GROUP_HIF: + pfHifCb = fn; + break; + case M2M_REQ_GROUP_SIGMA: + pfSigmaCb = fn; + break; + case M2M_REQ_GROUP_SSL: + pfSSLCb = fn; + break; + default: + M2M_ERR("GRp ? %d\n",u8Grp); + ret = M2M_ERR_FAIL; + break; + } + return ret; +} + +#endif diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/m2m_hif.h b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/m2m_hif.h new file mode 100644 index 000000000..509500588 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/m2m_hif.h @@ -0,0 +1,270 @@ +/** + * + * \file + * + * \brief This module contains M2M host interface APIs implementation. + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _M2M_HIF_ +#define _M2M_HIF_ + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +INCLUDES +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ + +#include "common/include/nm_common.h" +/*!< Include depends on UNO Board is used or not*/ +#ifdef ENABLE_UNO_BOARD +#include "m2m_uno_hif.h" +#endif + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +MACROS +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ + +#define M2M_HIF_MAX_PACKET_SIZE (1600 - 4) +/*!< Maximum size of the buffer could be transferred between Host and Firmware. +*/ + +#define M2M_HIF_HDR_OFFSET (sizeof(tstrHifHdr) + 4) + + +/** +* @struct tstrHifHdr +* @brief Structure to hold HIF header +*/ +typedef struct +{ + uint8 u8Gid; /*!< Group ID */ + uint8 u8Opcode; /*!< OP code */ + uint16 u16Length; /*!< Payload length */ +}tstrHifHdr; + +#ifdef __cplusplus + extern "C" { +#endif + +/*! +@typedef typedef void (*tpfHifCallBack)(uint8 u8OpCode, uint16 u16DataSize, uint32 u32Addr); +@brief used to point to Wi-Fi call back function depend on Arduino project or other projects. +@param [in] u8OpCode + HIF Opcode type. +@param [in] u16DataSize + HIF data length. +@param [in] u32Addr + HIF address. +@param [in] grp + HIF group type. +*/ +typedef void (*tpfHifCallBack)(uint8 u8OpCode, uint16 u16DataSize, uint32 u32Addr); +/** +* @fn NMI_API sint8 hif_init(void * arg); +* @brief + To initialize HIF layer. +* @param [in] arg +* Pointer to the arguments. +* @return + The function shall return ZERO for successful operation and a negative value otherwise. +*/ +NMI_API sint8 hif_init(void * arg); +/** +* @fn NMI_API sint8 hif_deinit(void * arg); +* @brief + To Deinitialize HIF layer. +* @param [in] arg +* Pointer to the arguments. +* @return + The function shall return ZERO for successful operation and a negative value otherwise. +*/ +NMI_API sint8 hif_deinit(void * arg); +/** +* @fn sint8 hif_check_compatibility(uint16 u16HifInfo); +* @brief +* To check the compatibility of an image with the current driver. +* @param [in] u16HifInfo +* HIF info of image to be checked. +* @return The function shall return ZERO for compatible image and a negative value otherwise. +*/ +sint8 hif_check_compatibility(uint16 u16HifInfo); +/** +* @fn sint8 hif_enable_access(void); +* @brief +* To enable access to HIF layer, based on HIF level of Firmware. +* This function reads HIF level directly from a register written by Firmware. +* @return The function shall return ZERO for full match operation and a negative value if operation is restricted. +*/ +sint8 hif_enable_access(void); +/** +* @fn sint8 hif_check_code(uint8 u8Gid, uint8 u8OpCode); +* @brief +* To check that a particular hif message is supported with the current driver/firmware pair. +* @param [in] u8Gid +* Group ID. +* @param [in] u8Opcode +* Operation ID. +* @return The function shall return ZERO for support and a negative value otherwise. +*/ +sint8 hif_check_code(uint8 u8Gid, uint8 u8OpCode); +/** +* @fn NMI_API sint8 hif_send(uint8 u8Gid,uint8 u8Opcode,uint8 *pu8CtrlBuf,uint16 u16CtrlBufSize, + uint8 *pu8DataBuf,uint16 u16DataSize, uint16 u16DataOffset) +* @brief Send packet using host interface. + +* @param [in] u8Gid +* Group ID. +* @param [in] u8Opcode +* Operation ID. +* @param [in] pu8CtrlBuf +* Pointer to the Control buffer. +* @param [in] u16CtrlBufSize + Control buffer size. +* @param [in] u16DataOffset + Packet Data offset. +* @param [in] pu8DataBuf +* Packet buffer Allocated by the caller. +* @param [in] u16DataSize + Packet buffer size (including the HIF header). +* @return The function shall return ZERO for successful operation and a negative value otherwise. +*/ +NMI_API sint8 hif_send(uint8 u8Gid,uint8 u8Opcode,uint8 *pu8CtrlBuf,uint16 u16CtrlBufSize, + uint8 *pu8DataBuf,uint16 u16DataSize, uint16 u16DataOffset); +/** +* @fn hif_receive +* @brief Host interface interrupt serviece routine +* @param [in] u32Addr +* Receive start address +* @param [out] pu8Buf +* Pointer to receive buffer. Allocated by the caller +* @param [in] u16Sz +* Receive buffer size +* @param [in] isDone +* If you don't need any more packets send True otherwise send false +* @return + The function shall return ZERO for successful operation and a negative value otherwise. +*/ + +NMI_API sint8 hif_receive(uint32 u32Addr, uint8 *pu8Buf, uint16 u16Sz, uint8 isDone); +/** +* @fn hif_register_cb +* @brief + To set Callback function for every Component. + +* @param [in] u8Grp +* Group to which the Callback function should be set. + +* @param [in] fn +* function to be set to the specified group. +* @return + The function shall return ZERO for successful operation and a negative value otherwise. +*/ +NMI_API sint8 hif_register_cb(uint8 u8Grp,tpfHifCallBack fn); +/** +* @fn NMI_API sint8 hif_chip_sleep(void); +* @brief + To make the chip sleep. +* @return + The function shall return ZERO for successful operation and a negative value otherwise. +*/ +NMI_API sint8 hif_chip_sleep(void); +/** +* @fn NMI_API sint8 hif_chip_wake(void); +* @brief + To Wakeup the chip. +* @return + The function shall return ZERO for successful operation and a negative value otherwise. +*/ + +NMI_API sint8 hif_chip_wake(void); +/*! +@fn \ + NMI_API void hif_set_sleep_mode(uint8 u8Pstype); + +@brief + Set the sleep mode of the HIF layer. + +@param [in] u8Pstype + Sleep mode. + +@return + The function SHALL return 0 for success and a negative value otherwise. +*/ + +NMI_API void hif_set_sleep_mode(uint8 u8Pstype); +/*! +@fn \ + NMI_API uint8 hif_get_sleep_mode(void); + +@brief + Get the sleep mode of the HIF layer. + +@return + The function SHALL return the sleep mode of the HIF layer. +*/ + +NMI_API uint8 hif_get_sleep_mode(void); + +#ifdef CORTUS_APP +/** +* @fn hif_Resp_handler(uint8 *pu8Buffer, uint16 u16BufferSize) +* @brief + Response handler for HIF layer. + +* @param [in] pu8Buffer + Pointer to the buffer. + +* @param [in] u16BufferSize + Buffer size. + +* @return + The function SHALL return 0 for success and a negative value otherwise. +*/ +NMI_API sint8 hif_Resp_handler(uint8 *pu8Buffer, uint16 u16BufferSize); +#endif + +/** +* @fn hif_yield(void) +* @brief + Yields control from interrupt event handler. +*/ +NMI_API void hif_yield(void); + +/** +* @fn hif_handle_isr(void) +* @brief + Handle interrupt received from NMC1500 firmware. +* @return + The function SHALL return 0 for success and a negative value otherwise. +*/ +NMI_API sint8 hif_handle_isr(void); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/m2m_ota.c b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/m2m_ota.c new file mode 100644 index 000000000..d9f0b0ab6 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/m2m_ota.c @@ -0,0 +1,357 @@ +/** + * + * \file + * + * \brief WINC3400 IoT OTA Interface. + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + + + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +INCLUDES +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ +#include "common/include/nm_common.h" +#include "driver/include/m2m_types.h" +#include "driver/include/m2m_ota.h" +#include "driver/include/m2m_wifi.h" +#include "driver/source/m2m_hif.h" +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +MACROS +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +DATA TYPES +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ +static tpfOtaUpdateCb gpfOtaUpdateCb = NULL; +static tpfOtaNotifCb gpfOtaNotifCb = NULL; + + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +FUNCTION PROTOTYPES +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ +/** +* @fn m2m_wifi_cb(uint8 u8OpCode, uint16 u16DataSize, uint32 u32Addr, uint8 grp) +* @brief WiFi call back function +* @param [in] u8OpCode +* HIF Opcode type. +* @param [in] u16DataSize +* HIF data length. +* @param [in] u32Addr +* HIF address. +* @param [in] grp +* HIF group type. +* @author +* @date +* @version 1.0 +*/ +static void m2m_ota_cb(uint8 u8OpCode, uint16 u16DataSize, uint32 u32Addr) +{ + sint8 ret = M2M_SUCCESS; + if(u8OpCode == M2M_OTA_RESP_NOTIF_UPDATE_INFO) + { + tstrOtaUpdateInfo strOtaUpdateInfo; + m2m_memset((uint8*)&strOtaUpdateInfo,0,sizeof(tstrOtaUpdateInfo)); + ret = hif_receive(u32Addr,(uint8*)&strOtaUpdateInfo,sizeof(tstrOtaUpdateInfo),0); + if(ret == M2M_SUCCESS) + { + if(gpfOtaNotifCb) + gpfOtaNotifCb(&strOtaUpdateInfo); + } + } + else if (u8OpCode == M2M_OTA_RESP_UPDATE_STATUS) + { + tstrOtaUpdateStatusResp strOtaUpdateStatusResp; + m2m_memset((uint8*)&strOtaUpdateStatusResp,0,sizeof(tstrOtaUpdateStatusResp)); + ret = hif_receive(u32Addr, (uint8*) &strOtaUpdateStatusResp,sizeof(tstrOtaUpdateStatusResp), 0); + if(ret == M2M_SUCCESS) + { + if(gpfOtaUpdateCb) + gpfOtaUpdateCb(strOtaUpdateStatusResp.u8OtaUpdateStatusType,strOtaUpdateStatusResp.u8OtaUpdateStatus); + } + } + else + { + M2M_ERR("Invaild OTA resp %d ?\n",u8OpCode); + } + +} +/*! +@fn \ + NMI_API sint8 m2m_ota_init(tpfOtaUpdateCb pfOtaUpdateCb, tpfOtaNotifCb pfOtaNotifCb); + +@brief + Initialize the OTA layer. + +@param [in] pfOtaUpdateCb + OTA Update callback function + +@param [in] pfOtaNotifCb + OTA notify callback function + +@return + The function SHALL return 0 for success and a negative value otherwise. +*/ +NMI_API sint8 m2m_ota_init(tpfOtaUpdateCb pfOtaUpdateCb, tpfOtaNotifCb pfOtaNotifCb) +{ + sint8 ret = M2M_SUCCESS; + + if(pfOtaUpdateCb){ + gpfOtaUpdateCb = pfOtaUpdateCb; + }else{ + M2M_ERR("Invaild Ota update cb\n"); + } + if(pfOtaNotifCb){ + gpfOtaNotifCb = pfOtaNotifCb; + }else{ + M2M_ERR("Invaild Ota notify cb\n"); + } + + hif_register_cb(M2M_REQ_GROUP_OTA,m2m_ota_cb); + + return ret; +} +/*! +@fn \ + NMI_API sint8 m2m_ota_notif_set_url(uint8 * u8Url); + +@brief + Set the OTA url + +@param [in] u8Url + The url server address + +@return + The function SHALL return 0 for success and a negative value otherwise. +*/ +NMI_API sint8 m2m_ota_notif_set_url(uint8 * u8Url) +{ + sint8 ret = M2M_SUCCESS; + uint16 u16UrlSize = m2m_strlen(u8Url) + 1; + /*Todo: we may change it to data pkt but we need to give it higer priority + but the priorty is not implemnted yet in data pkt + */ + ret = hif_send(M2M_REQ_GROUP_OTA,M2M_OTA_REQ_START_UPDATE,u8Url,u16UrlSize,NULL,0,0); + return ret; + +} + +/*! +@fn \ + NMI_API sint8 m2m_ota_notif_check_for_update(void); + +@brief + check for ota update + +@return + The function SHALL return 0 for success and a negative value otherwise. +*/ +NMI_API sint8 m2m_ota_notif_check_for_update(void) +{ + sint8 ret = M2M_SUCCESS; + ret = hif_send(M2M_REQ_GROUP_OTA,M2M_OTA_REQ_NOTIF_CHECK_FOR_UPDATE,NULL,0,NULL,0,0); + return ret; +} + +/*! +@fn \ + NMI_API sint8 m2m_ota_notif_sched(uint32 u32Period); + +@brief + Schedule OTA update + +@param [in] u32Period + Period in days + +@return + The function SHALL return 0 for success and a negative value otherwise. +*/ +NMI_API sint8 m2m_ota_notif_sched(uint32 u32Period) +{ + sint8 ret = M2M_SUCCESS; + ret = hif_send(M2M_REQ_GROUP_OTA,M2M_OTA_REQ_NOTIF_CHECK_FOR_UPDATE,NULL,0,NULL,0,0); + return ret; +} + +/*! +@fn \ + NMI_API sint8 m2m_ota_start_update(uint8 * u8DownloadUrl); + +@brief + Request OTA start update using the downloaded url + +@param [in] u8DownloadUrl + The download firmware url, you get it from device info + +@return + The function SHALL return 0 for success and a negative value otherwise. + +*/ +NMI_API sint8 m2m_ota_start_update(uint8 * u8DownloadUrl) +{ + sint8 ret = M2M_SUCCESS; + uint16 u16DurlSize = m2m_strlen(u8DownloadUrl) + 1; + /*Todo: we may change it to data pkt but we need to give it higer priority + but the priorty is not implemnted yet in data pkt + */ + ret = hif_send(M2M_REQ_GROUP_OTA,M2M_OTA_REQ_START_UPDATE,u8DownloadUrl,u16DurlSize,NULL,0,0); + return ret; +} + + +/*! +@fn \ + NMI_API sint8 m2m_ota_rollback(void); + +@brief + Request OTA Rollback image + +@return + The function SHALL return 0 for success and a negative value otherwise. +*/ +NMI_API sint8 m2m_ota_rollback(void) +{ + sint8 ret = M2M_SUCCESS; + tstrM2mRev strRev; + + ret = m2m_ota_get_firmware_version(&strRev); + if(ret == M2M_SUCCESS) + { + if(M2M_GET_HIF_BLOCK(strRev.u16FirmwareHifInfo) == M2M_HIF_BLOCK_VALUE) + { + ret = hif_send(M2M_REQ_GROUP_OTA,M2M_OTA_REQ_ROLLBACK,NULL,0,NULL,0,0); + } + else + { + ret = M2M_ERR_FAIL; + } + } + return ret; +} + + +/*! +@fn \ + NMI_API sint8 m2m_ota_abort(void); + +@brief + Request OTA Abort + +@return + The function SHALL return 0 for success and a negative value otherwise. +*/ +NMI_API sint8 m2m_ota_abort(void) +{ + sint8 ret = M2M_SUCCESS; + ret = hif_send(M2M_REQ_GROUP_OTA,M2M_OTA_REQ_ABORT,NULL,0,NULL,0,0); + return ret; +} + + +/*! +@fn \ + NMI_API sint8 m2m_ota_switch_firmware(void); + +@brief + Switch to the upgraded Firmware + +@return + The function SHALL return 0 for success and a negative value otherwise. +*/ +NMI_API sint8 m2m_ota_switch_firmware(void) +{ + sint8 ret = M2M_SUCCESS; + tstrM2mRev strRev; + + ret = m2m_ota_get_firmware_version(&strRev); + if(ret == M2M_SUCCESS) + { + if(M2M_GET_HIF_BLOCK(strRev.u16FirmwareHifInfo) == M2M_HIF_BLOCK_VALUE) + { + ret = hif_send(M2M_REQ_GROUP_OTA,M2M_OTA_REQ_SWITCH_FIRMWARE,NULL,0,NULL,0,0); + } + else + { + ret = M2M_ERR_FAIL; + } + } + return ret; +} +#if 0 +#define M2M_OTA_FILE "../../../m2m_ota.dat" +NMI_API sint8 m2m_ota_test(void) +{ + uint32 page = 0; + uint8 buffer[1500]; + uint32 u32Sz = 0; + sint8 ret = M2M_SUCCESS; + FILE *fp =NULL; + fp = fopen(M2M_OTA_FILE,"rb"); + if(fp) + { + fseek(fp, 0L, SEEK_END); + u32Sz = ftell(fp); + fseek(fp, 0L, SEEK_SET); + + while(u32Sz > 0) + { + { + page = (rand()%1400); + + if((page<100)||(page>1400)) page = 1400; + } + + if(u32Sz>page) + { + u32Sz-=page; + } + else + { + page = u32Sz; + u32Sz = 0; + } + printf("page %d\n", (int)page); + fread(buffer,page,1,fp); + ret = hif_send(M2M_REQ_GROUP_OTA,M2M_OTA_REQ_TEST|M2M_REQ_DATA_PKT,NULL,0,(uint8*)&buffer,page,0); + if(ret != M2M_SUCCESS) + { + M2M_ERR("\n"); + } + nm_bsp_sleep(1); + } + + } + else + { + M2M_ERR("nO err\n"); + } + return ret; +} +#endif + diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/m2m_periph.c b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/m2m_periph.c new file mode 100644 index 000000000..d5c046664 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/m2m_periph.c @@ -0,0 +1,125 @@ +/** + * + * \file + * + * \brief WINC3400 Peripherials Application Interface. + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +INCLUDES +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ + +#include "driver/include/m2m_periph.h" +#include "driver/source/nmasic.h" +#include "m2m_hif.h" + +#ifdef CONF_PERIPH + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +MACROS +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ +#define GPIO_OP_DIR 0 +#define GPIO_OP_SET 1 +#define GPIO_OP_GET 2 +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +DATA TYPES +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +STATIC FUNCTIONS +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ +static sint8 get_gpio_idx(uint8 u8GpioNum) +{ + if(u8GpioNum >= M2M_PERIPH_GPIO_MAX) return -1; + if(u8GpioNum == M2M_PERIPH_GPIO15) { return 15; + } else if(u8GpioNum == M2M_PERIPH_GPIO16) { return 16; + } else if(u8GpioNum == M2M_PERIPH_GPIO18) { return 18; + } else { + return -2; + } +} +/* + * GPIO read/write skeleton with wakeup/sleep capability. + */ +static sint8 gpio_ioctl(uint8 op, uint8 u8GpioNum, uint8 u8InVal, uint8 * pu8OutVal) +{ + sint8 ret, gpio; + + ret = hif_chip_wake(); + if(ret != M2M_SUCCESS) goto _EXIT; + + gpio = get_gpio_idx(u8GpioNum); + if(gpio < 0) goto _EXIT1; + + if(op == GPIO_OP_DIR) { + ret = set_gpio_dir((uint8)gpio, u8InVal); + } else if(op == GPIO_OP_SET) { + ret = set_gpio_val((uint8)gpio, u8InVal); + } else if(op == GPIO_OP_GET) { + ret = get_gpio_val((uint8)gpio, pu8OutVal); + } + if(ret != M2M_SUCCESS) goto _EXIT1; + +_EXIT1: + ret = hif_chip_sleep(); +_EXIT: + return ret; +} +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +FUNCTION IMPLEMENTATION +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ + + +sint8 m2m_periph_init(tstrPerphInitParam * param) +{ + return M2M_SUCCESS; +} + +sint8 m2m_periph_gpio_set_dir(uint8 u8GpioNum, uint8 u8GpioDir) +{ + return gpio_ioctl(GPIO_OP_DIR, u8GpioNum, u8GpioDir, NULL); +} + +sint8 m2m_periph_gpio_set_val(uint8 u8GpioNum, uint8 u8GpioVal) +{ + return gpio_ioctl(GPIO_OP_SET, u8GpioNum, u8GpioVal, NULL); +} + +sint8 m2m_periph_gpio_get_val(uint8 u8GpioNum, uint8 * pu8GpioVal) +{ + return gpio_ioctl(GPIO_OP_GET, u8GpioNum, 0, pu8GpioVal); +} + +sint8 m2m_periph_pullup_ctrl(uint32 pinmask, uint8 enable) +{ + return pullup_ctrl(pinmask, enable); +} +#endif /* CONF_PERIPH */ \ No newline at end of file diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/m2m_wifi.c b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/m2m_wifi.c new file mode 100644 index 000000000..9e86a4538 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/m2m_wifi.c @@ -0,0 +1,1485 @@ +/** + * + * \file + * + * \brief This module contains M2M Wi-Fi APIs implementation. + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "driver/include/m2m_wifi.h" +#include "driver/source/m2m_hif.h" +#include "driver/source/nmasic.h" + +#include "ISConstants.h" +#define malloc MALLOC +#define free FREE + +static volatile uint8 gu8ChNum; +static tpfAppWifiCb gpfAppWifiCb = NULL; + + +#ifdef ETH_MODE +static tpfAppEthCb gpfAppEthCb = NULL; +static uint8* gau8ethRcvBuf=NULL; +static uint16 gu16ethRcvBufSize ; +#endif + +//#define CONF_MGMT + +#ifdef CONF_MGMT +static tpfAppMonCb gpfAppMonCb = NULL; +static struct _tstrMgmtCtrl +{ + uint8* pu8Buf; + uint16 u16Offset; + uint16 u16Sz; +} +gstrMgmtCtrl = {NULL, 0 , 0}; +#endif +/** +* @fn m2m_wifi_cb(uint8 u8OpCode, uint16 u16DataSize, uint32 u32Addr, uint8 grp) +* @brief WiFi call back function +* @param [in] u8OpCode +* HIF Opcode type. +* @param [in] u16DataSize +* HIF data length. +* @param [in] u32Addr +* HIF address. +* @param [in] grp +* HIF group type. +* @author +* @date +* @version 1.0 +*/ +static void m2m_wifi_cb(uint8 u8OpCode, uint16 u16DataSize, uint32 u32Addr) +{ + uint8 rx_buf[8]; + if (u8OpCode == M2M_WIFI_RESP_CON_STATE_CHANGED) + { + tstrM2mWifiStateChanged strState; + if (hif_receive(u32Addr, (uint8*) &strState,sizeof(tstrM2mWifiStateChanged), 0) == M2M_SUCCESS) + { + if (gpfAppWifiCb) + gpfAppWifiCb(M2M_WIFI_RESP_CON_STATE_CHANGED, &strState); + } + } + else if (u8OpCode == M2M_WIFI_RESP_GET_SYS_TIME) + { + tstrSystemTime strSysTime; + if (hif_receive(u32Addr, (uint8*) &strSysTime,sizeof(tstrSystemTime), 0) == M2M_SUCCESS) + { + if (gpfAppWifiCb) + gpfAppWifiCb(M2M_WIFI_RESP_GET_SYS_TIME, &strSysTime); + } + } + else if(u8OpCode == M2M_WIFI_RESP_CONN_INFO) + { + tstrM2MConnInfo strConnInfo; + if(hif_receive(u32Addr, (uint8*)&strConnInfo, sizeof(tstrM2MConnInfo), 1) == M2M_SUCCESS) + { + if(gpfAppWifiCb) + gpfAppWifiCb(M2M_WIFI_RESP_CONN_INFO, &strConnInfo); + } + } + else if (u8OpCode == M2M_WIFI_RESP_MEMORY_RECOVER) + { +#if 0 + if (hif_receive(u32Addr, rx_buf, 4, 1) == M2M_SUCCESS) + { + tstrM2mWifiStateChanged strState; + m2m_memcpy((uint8*) &strState, rx_buf,sizeof(tstrM2mWifiStateChanged)); + if (app_wifi_recover_cb) + app_wifi_recover_cb(strState.u8CurrState); + } +#endif + } + else if (u8OpCode == M2M_WIFI_REQ_DHCP_CONF) + { + tstrM2MIPConfig strIpConfig; + if (hif_receive(u32Addr, (uint8 *)&strIpConfig, sizeof(tstrM2MIPConfig), 0) == M2M_SUCCESS) + { + if (gpfAppWifiCb) + gpfAppWifiCb(M2M_WIFI_REQ_DHCP_CONF, (uint8 *)&strIpConfig); + } + } + else if (u8OpCode == M2M_WIFI_REQ_WPS) + { + tstrM2MWPSInfo strWps; + m2m_memset((uint8*)&strWps,0,sizeof(tstrM2MWPSInfo)); + if(hif_receive(u32Addr, (uint8*)&strWps, sizeof(tstrM2MWPSInfo), 0) == M2M_SUCCESS) + { + if (gpfAppWifiCb) + gpfAppWifiCb(M2M_WIFI_REQ_WPS, &strWps); + } + } + else if (u8OpCode == M2M_WIFI_RESP_IP_CONFLICT) + { + uint32 u32ConflictedIP; + if(hif_receive(u32Addr, (uint8 *)&u32ConflictedIP, sizeof(u32ConflictedIP), 0) == M2M_SUCCESS) + { + M2M_INFO("Conflicted IP \" %u.%u.%u.%u \" \n", + BYTE_0(u32ConflictedIP),BYTE_1(u32ConflictedIP),BYTE_2(u32ConflictedIP),BYTE_3(u32ConflictedIP)); + if (gpfAppWifiCb) + gpfAppWifiCb(M2M_WIFI_RESP_IP_CONFLICT, NULL); + + } + } + else if (u8OpCode == M2M_WIFI_RESP_SCAN_DONE) + { + tstrM2mScanDone strState; + if(hif_receive(u32Addr, (uint8*)&strState, sizeof(tstrM2mScanDone), 0) == M2M_SUCCESS) + { + gu8ChNum = strState.u8NumofCh; + if (gpfAppWifiCb) + gpfAppWifiCb(M2M_WIFI_RESP_SCAN_DONE, &strState); + } + } + else if (u8OpCode == M2M_WIFI_RESP_SCAN_RESULT) + { + tstrM2mWifiscanResult strScanResult; + if(hif_receive(u32Addr, (uint8*)&strScanResult, sizeof(tstrM2mWifiscanResult), 0) == M2M_SUCCESS) + { + if (gpfAppWifiCb) + gpfAppWifiCb(M2M_WIFI_RESP_SCAN_RESULT, &strScanResult); + } + } + else if (u8OpCode == M2M_WIFI_RESP_CURRENT_RSSI) + { + if (hif_receive(u32Addr, rx_buf, 4, 0) == M2M_SUCCESS) + { + if (gpfAppWifiCb) + gpfAppWifiCb(M2M_WIFI_RESP_CURRENT_RSSI, rx_buf); + } + } + else if (u8OpCode == M2M_WIFI_RESP_CLIENT_INFO) + { + if (hif_receive(u32Addr, rx_buf, 4, 0) == M2M_SUCCESS) + { + if (gpfAppWifiCb) + gpfAppWifiCb(M2M_WIFI_RESP_CLIENT_INFO, rx_buf); + } + } + else if(u8OpCode == M2M_WIFI_RESP_PROVISION_INFO) + { + tstrM2MProvisionInfo strProvInfo; + if(hif_receive(u32Addr, (uint8*)&strProvInfo, sizeof(tstrM2MProvisionInfo), 1) == M2M_SUCCESS) + { + if(gpfAppWifiCb) + gpfAppWifiCb(M2M_WIFI_RESP_PROVISION_INFO, &strProvInfo); + } + } + else if(u8OpCode == M2M_WIFI_RESP_DEFAULT_CONNECT) + { + tstrM2MDefaultConnResp strResp; + if(hif_receive(u32Addr, (uint8*)&strResp, sizeof(tstrM2MDefaultConnResp), 1) == M2M_SUCCESS) + { + if(gpfAppWifiCb) + gpfAppWifiCb(M2M_WIFI_RESP_DEFAULT_CONNECT, &strResp); + } + } + else if (u8OpCode == M2M_WIFI_RESP_BLE_API_RECV) + { + //Read the length + if(hif_receive(u32Addr, rx_buf, 2, 0) == M2M_SUCCESS) + { + uint16 u16BleMsgLen = (rx_buf[1] << 8) + rx_buf[0]; + tstrM2mBleApiMsg* bleRx = (tstrM2mBleApiMsg*)malloc(u16BleMsgLen + sizeof(tstrM2mBleApiMsg)); + + if(bleRx != NULL) + { + bleRx->u16Len = u16BleMsgLen; + + //Read the rest of the message + if (hif_receive(u32Addr+2, bleRx->data, bleRx->u16Len, 1)== M2M_SUCCESS) + { + if(gpfAppWifiCb) + gpfAppWifiCb(M2M_WIFI_RESP_BLE_API_RECV, bleRx); + } + free(bleRx); + } + } + } + else if(u8OpCode == M2M_WIFI_RESP_GET_PRNG) + { + tstrPrng strPrng; + if(hif_receive(u32Addr, (uint8*)&strPrng,sizeof(tstrPrng), 0) == M2M_SUCCESS) + { + if(hif_receive(u32Addr + sizeof(tstrPrng),strPrng.pu8RngBuff,strPrng.u16PrngSize, 1) == M2M_SUCCESS) + { + if(gpfAppWifiCb) { + gpfAppWifiCb(M2M_WIFI_RESP_GET_PRNG,&strPrng); + } + } + } + } + else if (u8OpCode == M2M_WIFI_RESP_SET_GAIN_TABLE) + { + tstrM2MGainTableRsp strGainRsp; + if (hif_receive(u32Addr, (uint8*) &strGainRsp,sizeof(tstrM2MGainTableRsp), 0) == M2M_SUCCESS) + { + if (gpfAppWifiCb) + gpfAppWifiCb(M2M_WIFI_RESP_SET_GAIN_TABLE, &strGainRsp); + } + } +#ifdef ETH_MODE + else if(u8OpCode == M2M_WIFI_RESP_ETHERNET_RX_PACKET) + { + if(hif_receive(u32Addr, rx_buf ,sizeof(tstrM2mIpRsvdPkt), 0) == M2M_SUCCESS) + { + tstrM2mIpRsvdPkt * pstrM2MIpRxPkt = (tstrM2mIpRsvdPkt*)rx_buf; + tstrM2mIpCtrlBuf strM2mIpCtrlBuf; + uint16 u16Offset = pstrM2MIpRxPkt->u16PktOffset; + + strM2mIpCtrlBuf.u16RemainigDataSize = pstrM2MIpRxPkt->u16PktSz; + if((gpfAppEthCb) &&(gau8ethRcvBuf)&& (gu16ethRcvBufSize > 0)) + { + while (strM2mIpCtrlBuf.u16RemainigDataSize > 0) + { + if(strM2mIpCtrlBuf.u16RemainigDataSize > gu16ethRcvBufSize) + { + strM2mIpCtrlBuf.u16DataSize = gu16ethRcvBufSize ; + } + else + { + strM2mIpCtrlBuf.u16DataSize = strM2mIpCtrlBuf.u16RemainigDataSize; + } + if(hif_receive(u32Addr+u16Offset, gau8ethRcvBuf, strM2mIpCtrlBuf.u16DataSize, 0) == M2M_SUCCESS) + { + strM2mIpCtrlBuf.u16RemainigDataSize -= strM2mIpCtrlBuf.u16DataSize; + u16Offset += strM2mIpCtrlBuf.u16DataSize; + gpfAppEthCb(M2M_WIFI_RESP_ETHERNET_RX_PACKET, gau8ethRcvBuf, &(strM2mIpCtrlBuf)); + } + else + { + break; + } + } + } + } + } +#endif + +#ifdef CONF_MGMT + else if(u8OpCode == M2M_WIFI_RESP_WIFI_RX_PACKET) + { + tstrM2MWifiRxPacketInfo strRxPacketInfo; + if(u16DataSize >= sizeof(tstrM2MWifiRxPacketInfo)) { + if(hif_receive(u32Addr, (uint8*)&strRxPacketInfo, sizeof(tstrM2MWifiRxPacketInfo), 0) == M2M_SUCCESS) + { + u16DataSize -= sizeof(tstrM2MWifiRxPacketInfo); + if(u16DataSize > 0 && gstrMgmtCtrl.pu8Buf != NULL) + { + if(u16DataSize > (gstrMgmtCtrl.u16Sz + gstrMgmtCtrl.u16Offset)) + { + u16DataSize = gstrMgmtCtrl.u16Sz; + } + u32Addr += sizeof(tstrM2MWifiRxPacketInfo) + gstrMgmtCtrl.u16Offset; + if(hif_receive(u32Addr , gstrMgmtCtrl.pu8Buf, u16DataSize, 1) != M2M_SUCCESS) + { + u16DataSize = 0; + } + } + if(gpfAppMonCb) + gpfAppMonCb(&strRxPacketInfo, gstrMgmtCtrl.pu8Buf,u16DataSize); + } + } else { + M2M_ERR("Incorrect mon data size %u\n", u16DataSize); + } + } +#endif + else + { + M2M_ERR("REQ Not defined %d\n",u8OpCode); + } +} + +sint8 m2m_wifi_download_mode() +{ + sint8 ret = M2M_SUCCESS; + /* Apply device specific initialization. */ + ret = nm_drv_init_download_mode(0); + if(ret != M2M_SUCCESS) goto _EXIT0; + + + + enable_interrupts(); + +_EXIT0: + return ret; +} + +static sint8 m2m_validate_ap_parameters(CONST tstrM2MAPConfig* pstrM2MAPConfig) +{ + sint8 s8Ret = M2M_SUCCESS; + /* Check for incoming pointer */ + if(pstrM2MAPConfig == NULL) + { + M2M_ERR("INVALID POINTER\n"); + s8Ret = M2M_ERR_FAIL; + goto ERR1; + } + /* Check for SSID */ + if((m2m_strlen((uint8 *)pstrM2MAPConfig->au8SSID) <= 0) || (m2m_strlen((uint8 *)pstrM2MAPConfig->au8SSID) >= M2M_MAX_SSID_LEN)) + { + M2M_ERR("INVALID SSID\n"); + s8Ret = M2M_ERR_FAIL; + goto ERR1; + } + /* Check for Channel */ + if(pstrM2MAPConfig->u8ListenChannel > M2M_WIFI_CH_14 || pstrM2MAPConfig->u8ListenChannel < M2M_WIFI_CH_1) + { + M2M_ERR("INVALID CH\n"); + s8Ret = M2M_ERR_FAIL; + goto ERR1; + } + /* Check for DHCP Server IP address */ + if(!(pstrM2MAPConfig->au8DHCPServerIP[0] || pstrM2MAPConfig->au8DHCPServerIP[1])) + { + if(!(pstrM2MAPConfig->au8DHCPServerIP[2])) + { + M2M_ERR("INVALID DHCP SERVER IP\n"); + s8Ret = M2M_ERR_FAIL; + goto ERR1; + } + } + /* Check for Security */ + if(pstrM2MAPConfig->u8SecType == M2M_WIFI_SEC_OPEN) + { + goto ERR1; + } + else if(pstrM2MAPConfig->u8SecType == M2M_WIFI_SEC_WEP) + { + /* Check for WEP Key index */ + if((pstrM2MAPConfig->u8KeyIndx <= 0) || (pstrM2MAPConfig->u8KeyIndx > WEP_KEY_MAX_INDEX)) + { + M2M_ERR("INVALID KEY INDEX\n"); + s8Ret = M2M_ERR_FAIL; + goto ERR1; + } + /* Check for WEP Key size */ + if( (pstrM2MAPConfig->u8KeySz != WEP_40_KEY_STRING_SIZE) && + (pstrM2MAPConfig->u8KeySz != WEP_104_KEY_STRING_SIZE) + ) + { + M2M_ERR("INVALID KEY SIZE\n"); + s8Ret = M2M_ERR_FAIL; + goto ERR1; + } + /* Check for WEP Key */ + if((pstrM2MAPConfig->au8WepKey == NULL) || (m2m_strlen((uint8 *)pstrM2MAPConfig->au8WepKey) <= 0) || (m2m_strlen((uint8 *)pstrM2MAPConfig->au8WepKey) > WEP_104_KEY_STRING_SIZE)) + { + M2M_ERR("INVALID WEP KEY\n"); + s8Ret = M2M_ERR_FAIL; + goto ERR1; + } + } + else + { + M2M_ERR("INVALID AUTHENTICATION MODE\n"); + s8Ret = M2M_ERR_FAIL; + goto ERR1; + } + +ERR1: + return s8Ret; +} +static sint8 m2m_validate_scan_options(tstrM2MScanOption* ptstrM2MScanOption) +{ + sint8 s8Ret = M2M_SUCCESS; + /* Check for incoming pointer */ + if(ptstrM2MScanOption == NULL) + { + M2M_ERR("INVALID POINTER\n"); + s8Ret = M2M_ERR_FAIL; + } + else + { + /* Check for valid No of slots */ + if(ptstrM2MScanOption->u8NumOfSlot == 0) + { + M2M_ERR("INVALID No of scan slots!\n"); + s8Ret = M2M_ERR_FAIL; + } + /* Check for valid time of slots */ + if((ptstrM2MScanOption->u8SlotTime < 10) || (ptstrM2MScanOption->u8SlotTime > 250)) + { + M2M_ERR("INVALID scan slot time!\n"); + s8Ret = M2M_ERR_FAIL; + } + /* Check for valid No of probe requests per slot */ + if((ptstrM2MScanOption->u8ProbesPerSlot == 0) || (ptstrM2MScanOption->u8ProbesPerSlot > M2M_SCAN_DEFAULT_NUM_PROBE)) + { + M2M_ERR("INVALID No of probe requests per scan slot\n"); + s8Ret = M2M_ERR_FAIL; + } + /* Check for valid RSSI threshold */ + if(ptstrM2MScanOption->s8RssiThresh >= 0) + { + M2M_ERR("INVALID RSSI threshold %d \n",ptstrM2MScanOption->s8RssiThresh); + s8Ret = M2M_ERR_FAIL; + } + } + return s8Ret; +} + +NMI_API sint8 m2m_wifi_ble_set_gain_table(uint8 table_idx) +{ + sint8 s8Ret = M2M_ERR_FAIL; + tstrM2MGainTable strGainTable = {0}; + + strGainTable.u8GainTable = table_idx; + + s8Ret = hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_SET_GAIN_TABLE, (uint8 *)&strGainTable, sizeof(tstrM2MGainTable), NULL, 0, 0); + return s8Ret; +} + + +sint8 m2m_wifi_init_hold(void) +{ + sint8 ret = M2M_ERR_FAIL; + + /* Apply device specific initialization. */ + ret = nm_drv_init_hold(0); + + return ret; +} +sint8 m2m_wifi_init_start(tstrWifiInitParam * param) +{ + tstrM2mRev strtmp; + sint8 ret = M2M_SUCCESS; + + if(param == NULL) { + ret = M2M_ERR_FAIL; + goto _EXIT0; + } + + gpfAppWifiCb = param->pfAppWifiCb; + +#ifdef ETH_MODE + gpfAppEthCb = param->strEthInitParam.pfAppEthCb; + gau8ethRcvBuf = param->strEthInitParam.au8ethRcvBuf; + gu16ethRcvBufSize = param->strEthInitParam.u16ethRcvBufSize; +#endif + +#ifdef CONF_MGMT + gpfAppMonCb = param->pfAppMonCb; +#endif + + /* Apply device specific initialization. */ + ret = nm_drv_init_start(NULL); + if(ret != M2M_SUCCESS) goto _EXIT0; + /* Initialize host interface module */ + ret = hif_init(NULL); + if(ret != M2M_SUCCESS) goto _EXIT1; + + hif_register_cb(M2M_REQ_GROUP_WIFI,m2m_wifi_cb); + + M2M_INFO("Curr driver ver: %u.%u.%u\n", M2M_DRIVER_VERSION_MAJOR_NO, M2M_DRIVER_VERSION_MINOR_NO, M2M_DRIVER_VERSION_PATCH_NO); + M2M_INFO("Curr driver HIF Level: (%u) %u.%u\n", M2M_HIF_BLOCK_VALUE, M2M_HIF_MAJOR_VALUE, M2M_HIF_MINOR_VALUE); + ret = m2m_wifi_get_firmware_version(&strtmp); + m2m_ota_get_firmware_version(&strtmp); + + if(ret == M2M_SUCCESS) + { + ret = hif_enable_access(); + if(ret == M2M_SUCCESS) + { + m2m_wifi_ble_set_gain_table(param->GainTableIndex); + } + } + goto _EXIT0; + +_EXIT1: + nm_drv_deinit(NULL); +_EXIT0: + return ret; +} +sint8 m2m_wifi_init(tstrWifiInitParam * param) +{ + sint8 ret = M2M_SUCCESS; + + ret = m2m_wifi_init_hold(); + if (ret == M2M_SUCCESS) + { + ret = m2m_wifi_init_start(param); + } + return ret; +} +sint8 m2m_wifi_deinit(void * arg) +{ + + hif_deinit(NULL); + + nm_drv_deinit(NULL); + + return M2M_SUCCESS; +} +sint8 m2m_wifi_reinit_hold(void) +{ + m2m_wifi_deinit(NULL); + return m2m_wifi_init_hold(); +} +sint8 m2m_wifi_reinit_start(tstrWifiInitParam * param) +{ + return m2m_wifi_init_start(param); +} +sint8 m2m_wifi_reinit(tstrWifiInitParam * param) +{ + sint8 ret = M2M_ERR_FAIL; + ret = m2m_wifi_reinit_hold(); + if(ret == M2M_SUCCESS) { + ret = m2m_wifi_reinit_start(param); + } + return ret; +} + +void m2m_wifi_yield(void) +{ + hif_yield(); +} + +sint8 m2m_wifi_handle_events(void * arg) +{ + return hif_handle_isr(); +} + +sint8 m2m_wifi_default_connect(void) +{ + return hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_DEFAULT_CONNECT, NULL, 0,NULL, 0,0); +} + +sint8 m2m_wifi_connect(char *pcSsid, uint8 u8SsidLen, uint8 u8SecType, void *pvAuthInfo, uint16 u16Ch) +{ + return m2m_wifi_connect_sc(pcSsid, u8SsidLen, u8SecType, pvAuthInfo, u16Ch,0); +} +sint8 m2m_wifi_connect_sc(char *pcSsid, uint8 u8SsidLen, uint8 u8SecType, void *pvAuthInfo, uint16 u16Ch, uint8 u8NoSaveCred) +{ + sint8 ret = M2M_SUCCESS; + tstrM2mWifiConnect strConnect; + tstrM2MWifiSecInfo *pstrAuthInfo; + + if(u8SecType != M2M_WIFI_SEC_OPEN) + { + if(pvAuthInfo == NULL) + { + M2M_ERR("Key is not valid\n"); + ret = M2M_ERR_FAIL; + goto ERR1; + } + if((u8SecType == M2M_WIFI_SEC_WPA_PSK) && (m2m_strlen(pvAuthInfo) == (M2M_MAX_PSK_LEN-1))) + { + uint8 i = 0; + uint8* pu8Psk = (uint8*)pvAuthInfo; + while(i < (M2M_MAX_PSK_LEN-1)) + { + if(pu8Psk[i]<'0' || (pu8Psk[i]>'9' && pu8Psk[i] < 'A')|| (pu8Psk[i]>'F' && pu8Psk[i] < 'a') || pu8Psk[i] > 'f') + { + M2M_ERR("Invalid Key\n"); + ret = M2M_ERR_FAIL; + goto ERR1; + } + i++; + } + } + } + if((u8SsidLen<=0)||(u8SsidLen>=M2M_MAX_SSID_LEN)) + { + M2M_ERR("SSID LEN INVALID\n"); + ret = M2M_ERR_FAIL; + goto ERR1; + } + + if(u16Ch < M2M_WIFI_CH_1 || u16Ch > M2M_WIFI_CH_14) + { + if(u16Ch!=M2M_WIFI_CH_ALL) + { + M2M_ERR("CH INVALID\n"); + ret = M2M_ERR_FAIL; + goto ERR1; + } + } + + m2m_memcpy(strConnect.au8SSID, (uint8*)pcSsid, u8SsidLen); + strConnect.au8SSID[u8SsidLen] = 0; + strConnect.u16Ch = NM_BSP_B_L_16(u16Ch); + /* Credentials will be Not be saved if u8NoSaveCred is set */ + strConnect.u8NoSaveCred = u8NoSaveCred ? 1:0; + pstrAuthInfo = &strConnect.strSec; + pstrAuthInfo->u8SecType = u8SecType; + + if(u8SecType == M2M_WIFI_SEC_WEP) + { + tstrM2mWifiWepParams * pstrWepParams = (tstrM2mWifiWepParams*)pvAuthInfo; + tstrM2mWifiWepParams *pstrWep = &pstrAuthInfo->uniAuth.strWepInfo; + pstrWep->u8KeyIndx =pstrWepParams->u8KeyIndx-1; + + if(pstrWep->u8KeyIndx >= WEP_KEY_MAX_INDEX) + { + M2M_ERR("Invalid Wep key index %d\n", pstrWep->u8KeyIndx); + ret = M2M_ERR_FAIL; + goto ERR1; + } + pstrWep->u8KeySz = pstrWepParams->u8KeySz-1; + if ((pstrWep->u8KeySz != WEP_40_KEY_STRING_SIZE)&& (pstrWep->u8KeySz != WEP_104_KEY_STRING_SIZE)) + { + M2M_ERR("Invalid Wep key length %d\n", pstrWep->u8KeySz); + ret = M2M_ERR_FAIL; + goto ERR1; + } + m2m_memcpy((uint8*)pstrWep->au8WepKey,(uint8*)pstrWepParams->au8WepKey, pstrWepParams->u8KeySz); + pstrWep->au8WepKey[pstrWepParams->u8KeySz] = 0; + + } + + + else if(u8SecType == M2M_WIFI_SEC_WPA_PSK) + { + uint16 u16KeyLen = m2m_strlen((uint8*)pvAuthInfo); + if((u16KeyLen <= 0)||(u16KeyLen >= M2M_MAX_PSK_LEN)) + { + M2M_ERR("Incorrect PSK key length\n"); + ret = M2M_ERR_FAIL; + goto ERR1; + } + m2m_memcpy(pstrAuthInfo->uniAuth.au8PSK, (uint8*)pvAuthInfo, u16KeyLen + 1); + } + else if(u8SecType == M2M_WIFI_SEC_802_1X) + { + m2m_memcpy((uint8*)&pstrAuthInfo->uniAuth.strCred1x, (uint8*)pvAuthInfo, sizeof(tstr1xAuthCredentials)); + } + else if(u8SecType == M2M_WIFI_SEC_OPEN) + { + + } + else + { + M2M_ERR("undefined sec type\n"); + ret = M2M_ERR_FAIL; + goto ERR1; + } + + ret = hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_CONNECT, (uint8*)&strConnect, sizeof(tstrM2mWifiConnect),NULL, 0,0); + +ERR1: + return ret; +} + +sint8 m2m_wifi_disconnect(void) +{ + return hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_DISCONNECT, NULL, 0, NULL, 0,0); +} +sint8 m2m_wifi_set_mac_address(uint8 au8MacAddress[6]) +{ + tstrM2mSetMacAddress strTmp; + m2m_memcpy((uint8*) strTmp.au8Mac, (uint8*) au8MacAddress, 6); + return hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_SET_MAC_ADDRESS, + (uint8*) &strTmp, sizeof(tstrM2mSetMacAddress), NULL, 0,0); +} + +sint8 m2m_wifi_set_static_ip(tstrM2MIPConfig * pstrStaticIPConf) +{ + pstrStaticIPConf->u32DNS = NM_BSP_B_L_32(pstrStaticIPConf->u32DNS); + pstrStaticIPConf->u32Gateway = NM_BSP_B_L_32(pstrStaticIPConf->u32Gateway); + pstrStaticIPConf->u32StaticIP = NM_BSP_B_L_32( + pstrStaticIPConf->u32StaticIP); + pstrStaticIPConf->u32SubnetMask = NM_BSP_B_L_32( + pstrStaticIPConf->u32SubnetMask); + return hif_send(M2M_REQ_GROUP_IP, M2M_IP_REQ_STATIC_IP_CONF, + (uint8*) pstrStaticIPConf, sizeof(tstrM2MIPConfig), NULL, 0,0); +} + +sint8 m2m_wifi_request_dhcp_client(void) +{ + /*legacy API should be removed */ + return 0; +} +sint8 m2m_wifi_request_dhcp_server(uint8* addr) +{ + /*legacy API should be removed */ + return 0; +} +/*! +@fn NMI_API sint8 m2m_wifi_set_lsn_int(tstrM2mLsnInt * pstrM2mLsnInt); +@brief Set the Wi-Fi listen interval for power save operation. It is represented in units + of AP Beacon periods. +@param [in] pstrM2mLsnInt + Structure holding the listen interval configurations. +@return The function SHALL return 0 for success and a negative value otherwise. +@sa tstrM2mLsnInt , m2m_wifi_set_sleep_mode +@pre m2m_wifi_set_sleep_mode shall be called first +@warning The Function called once after initialization. +*/ +sint8 m2m_wifi_enable_dhcp(uint8 u8DhcpEn ) +{ + + uint8 u8Req; + u8Req = u8DhcpEn ? M2M_IP_REQ_ENABLE_DHCP : M2M_IP_REQ_DISABLE_DHCP; + return hif_send(M2M_REQ_GROUP_IP, u8Req, NULL, 0, NULL, 0, 0); + + +} + +sint8 m2m_wifi_set_lsn_int(tstrM2mLsnInt* pstrM2mLsnInt) +{ + return hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_LSN_INT, (uint8*)pstrM2mLsnInt, sizeof(tstrM2mLsnInt), NULL, 0, 0); +} + +sint8 m2m_wifi_set_cust_InfoElement(uint8* pau8M2mCustInfoElement) +{ + return hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_CUST_INFO_ELEMENT, (uint8*)pau8M2mCustInfoElement, pau8M2mCustInfoElement[0]+1, NULL, 0, 0); +} + +sint8 m2m_wifi_set_scan_options(tstrM2MScanOption* ptstrM2MScanOption) +{ + sint8 s8Ret = M2M_ERR_FAIL; + if(m2m_validate_scan_options (ptstrM2MScanOption) == M2M_SUCCESS) + { + s8Ret = hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_SET_SCAN_OPTION, (uint8*)ptstrM2MScanOption, sizeof(tstrM2MScanOption),NULL, 0,0); + } + return s8Ret; +} +sint8 m2m_wifi_set_scan_region(uint16 ScanRegion) +{ + sint8 s8Ret = M2M_ERR_FAIL; + tstrM2MScanRegion strScanRegion; + strScanRegion.u16ScanRegion = ScanRegion; + s8Ret = hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_SET_SCAN_REGION, (uint8*)&strScanRegion, sizeof(tstrM2MScanRegion),NULL, 0,0); + return s8Ret; +} +sint8 m2m_wifi_request_scan(uint8 ch) +{ + sint8 s8Ret = M2M_SUCCESS; + + if(((ch >= M2M_WIFI_CH_1) && (ch <= M2M_WIFI_CH_14)) || (ch == M2M_WIFI_CH_ALL)) + { + tstrM2MScan strtmp; + strtmp.u8ChNum = ch; + s8Ret = hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_SCAN, (uint8*)&strtmp, sizeof(tstrM2MScan),NULL, 0,0); + } + else + { + s8Ret = M2M_ERR_INVALID_ARG; + } + return s8Ret; +} + +sint8 m2m_wifi_request_scan_passive(uint8 ch) +{ + sint8 s8Ret = M2M_SUCCESS; + + if(((ch >= M2M_WIFI_CH_1) && (ch <= M2M_WIFI_CH_14)) || (ch == M2M_WIFI_CH_ALL)) + { + tstrM2MScan strtmp; + strtmp.u8ChNum = ch; + + s8Ret = hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_PASSIVE_SCAN, (uint8*)&strtmp, sizeof(tstrM2MScan),NULL, 0,0); + } + else + { + s8Ret = M2M_ERR_INVALID_ARG; + } + return s8Ret; +} +sint8 m2m_wifi_wps(uint8 u8TriggerType,const char *pcPinNumber) +{ + tstrM2MWPSConnect strtmp; + + strtmp.u8TriggerType = u8TriggerType; + /*If WPS is using PIN METHOD*/ + if (u8TriggerType == WPS_PIN_TRIGGER) + m2m_memcpy ((uint8*)strtmp.acPinNumber,(uint8*) pcPinNumber,8); + return hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_WPS, (uint8*)&strtmp,sizeof(tstrM2MWPSConnect), NULL, 0,0); +} + +sint8 m2m_wifi_wps_disable(void) +{ + sint8 ret = M2M_SUCCESS; + ret = hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_DISABLE_WPS, NULL,0, NULL, 0, 0); + return ret; +} + +#if 0 +/* + * These two functions m2m_wifi_req_client_ctrl and m2m_wifi_req_server_init are for a mode in which two WINC ICs + * communicate with each other via probe request and probe response frames. This mode is not supported in WINC fw. + */ +sint8 m2m_wifi_req_client_ctrl(uint8 u8Cmd) +{ + + sint8 ret = M2M_SUCCESS; +#ifdef _PS_SERVER_ + tstrM2Mservercmd strCmd; + strCmd.u8cmd = u8Cmd; + ret = hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_CLIENT_CTRL, (uint8*)&strCmd, sizeof(tstrM2Mservercmd), NULL, 0, 0); +#else + M2M_ERR("_PS_SERVER_ is not defined\n"); +#endif + return ret; +} +sint8 m2m_wifi_req_server_init(uint8 ch) +{ + sint8 ret = M2M_SUCCESS; +#ifdef _PS_SERVER_ + tstrM2mServerInit strServer; + strServer.u8Channel = ch; + ret = hif_send(M2M_REQ_GROUP_WIFI,M2M_WIFI_REQ_SERVER_INIT, (uint8*)&strServer, sizeof(tstrM2mServerInit), NULL, 0, 0); +#else + M2M_ERR("_PS_SERVER_ is not defined\n"); +#endif + return ret; +} +#endif + +sint8 m2m_wifi_p2p(uint8 u8Channel) +{ + sint8 ret = M2M_SUCCESS; + if((u8Channel == M2M_WIFI_CH_1) || (u8Channel == M2M_WIFI_CH_6) || (u8Channel == M2M_WIFI_CH_11)) + { + tstrM2MP2PConnect strtmp; + strtmp.u8ListenChannel = u8Channel; + ret = hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_ENABLE_P2P, (uint8*)&strtmp, sizeof(tstrM2MP2PConnect), NULL, 0,0); + } + else + { + M2M_ERR("Listen channel should only be 1, 6 or 11\n"); + ret = M2M_ERR_FAIL; + } + return ret; +} +sint8 m2m_wifi_p2p_disconnect(void) +{ + sint8 ret = M2M_SUCCESS; + ret = hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_DISABLE_P2P, NULL, 0, NULL, 0, 0); + return ret; +} +sint8 m2m_wifi_enable_ap(CONST tstrM2MAPConfig* pstrM2MAPConfig) +{ + sint8 ret = M2M_ERR_FAIL; + if(M2M_SUCCESS == m2m_validate_ap_parameters(pstrM2MAPConfig)) + { + ret = hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_ENABLE_AP, (uint8 *)pstrM2MAPConfig, sizeof(tstrM2MAPConfig), NULL, 0, 0); + } + return ret; +} +sint8 m2m_wifi_disable_ap(void) +{ + sint8 ret = M2M_SUCCESS; + ret = hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_DISABLE_AP, NULL, 0, NULL, 0, 0); + return ret; +} +/*! +@fn NMI_API sint8 m2m_wifi_req_curr_rssi(void); +@brief Request the current RSSI for the current connected AP, + the response received in wifi_cb M2M_WIFI_RESP_CURRENT_RSSI +@sa M2M_WIFI_RESP_CURRENT_RSSI +@return The function shall return M2M_SUCCESS for success and a negative value otherwise. +*/ +sint8 m2m_wifi_req_curr_rssi(void) +{ + sint8 ret = M2M_SUCCESS; + ret = hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_CURRENT_RSSI, NULL, 0, NULL,0, 0); + return ret; +} + +sint8 m2m_wifi_req_restrict_ble(void) +{ + sint8 ret = M2M_SUCCESS; + ret = hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_RESTRICT_BLE,NULL, 0, NULL, 0, 0); + return ret; +} + +sint8 m2m_wifi_req_unrestrict_ble(void) +{ + sint8 ret = M2M_SUCCESS; + ret = hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_UNRESTRICT_BLE,NULL, 0, NULL, 0, 0); + return ret; +} + +sint8 m2m_wifi_send_ethernet_pkt(uint8* pu8Packet,uint16 u16PacketSize) +{ + sint8 s8Ret = -1; + if((pu8Packet != NULL)&&(u16PacketSize>0)) + { + tstrM2MWifiTxPacketInfo strTxPkt; + + strTxPkt.u16PacketSize = u16PacketSize; + strTxPkt.u16HeaderLength = M2M_ETHERNET_HDR_LEN; + s8Ret = hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_SEND_ETHERNET_PACKET | M2M_REQ_DATA_PKT, + (uint8*)&strTxPkt, sizeof(tstrM2MWifiTxPacketInfo), pu8Packet, u16PacketSize, M2M_ETHERNET_HDR_OFFSET - M2M_HIF_HDR_OFFSET); + } + return s8Ret; +} +/*! +@fn NMI_API sint8 m2m_wifi_get_otp_mac_address(uint8 *pu8MacAddr, uint8 * pu8IsValid); +@brief Request the MAC address stored on the OTP (one time programmable) memory of the device. + (the function is Blocking until response received) +@param [out] pu8MacAddr + Output MAC address buffer of 6 bytes size. Valid only if *pu8Valid=1. +@param [out] pu8IsValid + A output boolean value to indicate the validity of pu8MacAddr in OTP. + Output zero if the OTP memory is not programmed, non-zero otherwise. +@return The function shall return M2M_SUCCESS for success and a negative value otherwise. +@sa m2m_wifi_get_mac_address +@pre m2m_wifi_init required to call any WIFI/socket function +*/ +sint8 m2m_wifi_get_otp_mac_address(uint8 *pu8MacAddr, uint8* pu8IsValid) +{ + sint8 ret = M2M_SUCCESS; + ret = hif_chip_wake(); + if(ret == M2M_SUCCESS) + { + ret = nmi_get_otp_mac_address(pu8MacAddr, pu8IsValid); + if(ret == M2M_SUCCESS) + { + ret = hif_chip_sleep(); + } + } + return ret; +} +/*! +@fn NMI_API sint8 m2m_wifi_get_mac_address(uint8 *pu8MacAddr) +@brief Request the current MAC address of the device (the working mac address). + (the function is Blocking until response received) +@param [out] pu8MacAddr + Output MAC address buffer of 6 bytes size. +@return The function shall return M2M_SUCCESS for success and a negative value otherwise. +@sa m2m_wifi_get_otp_mac_address +@pre m2m_wifi_init required to call any WIFI/socket function +*/ +sint8 m2m_wifi_get_mac_address(uint8 *pu8MacAddr) +{ + sint8 ret = M2M_SUCCESS; + ret = hif_chip_wake(); + if(ret == M2M_SUCCESS) + { + ret = nmi_get_mac_address(pu8MacAddr); + if(ret == M2M_SUCCESS) + { + ret = hif_chip_sleep(); + } + } + + return ret; +} +/*! +@fn NMI_API sint8 m2m_wifi_req_scan_result(uint8 index); +@brief Reads the AP information from the Scan Result list with the given index, + the response received in wifi_cb M2M_WIFI_RESP_SCAN_RESULT, + the response pointer should be casted with tstrM2mWifiscanResult structure +@param [in] index + Index for the requested result, the index range start from 0 till number of AP's found +@sa tstrM2mWifiscanResult,m2m_wifi_get_num_ap_found,m2m_wifi_request_scan +@return The function shall return @ref M2M_SUCCESS for success and a negative value otherwise +@pre m2m_wifi_request_scan need to be called first, then m2m_wifi_get_num_ap_found + to get the number of AP's found +@warning Function used only in STA mode only. the scan result updated only if scan request called, + else it will be cashed in firmware for the host scan request result, + which mean if large delay occur between the scan request and the scan result request, + the result will not be up-to-date +*/ + +sint8 m2m_wifi_req_scan_result(uint8 index) +{ + sint8 ret = M2M_SUCCESS; + tstrM2mReqScanResult strReqScanRlt; + strReqScanRlt.u8Index = index; + ret = hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_SCAN_RESULT, (uint8*) &strReqScanRlt, sizeof(tstrM2mReqScanResult), NULL, 0, 0); + return ret; +} +/*! +@fn NMI_API uint8 m2m_wifi_get_num_ap_found(void); +@brief Reads the number of AP's found in the last Scan Request, + The function read the number of AP's from global variable which updated in the + wifi_cb in M2M_WIFI_RESP_SCAN_DONE. +@sa m2m_wifi_request_scan +@return Return the number of AP's found in the last Scan Request. +@pre m2m_wifi_request_scan need to be called first +@warning That function need to be called in the wifi_cb in M2M_WIFI_RESP_SCAN_DONE, + calling that function in any other place will return undefined/undated numbers. + Function used only in STA mode only. +*/ +uint8 m2m_wifi_get_num_ap_found(void) +{ + return gu8ChNum; +} +/*! +@fn NMI_API uint8 m2m_wifi_get_sleep_mode(void); +@brief Get the current Power save mode. +@return The current operating power saving mode. +@sa tenuPowerSaveModes , m2m_wifi_set_sleep_mode +*/ +uint8 m2m_wifi_get_sleep_mode(void) +{ + return hif_get_sleep_mode(); +} +/*! +@fn NMI_API sint8 m2m_wifi_set_sleep_mode(uint8 PsTyp, uint8 BcastEn); +@brief Set the power saving mode for the WINC3400. +@param [in] PsTyp + Desired power saving mode. Supported types are defined in tenuPowerSaveModes. +@param [in] BcastEn + Broadcast reception enable flag. + If it is 1, the WINC3400 must be awake each DTIM Beacon for receiving Broadcast traffic. + If it is 0, the WINC3400 will not wakeup at the DTIM Beacon, but its wakeup depends only + on the the configured Listen Interval. +@return The function SHALL return 0 for success and a negative value otherwise. +@sa tenuPowerSaveModes +@warning The function called once after initialization. +*/ +sint8 m2m_wifi_set_sleep_mode(uint8 PsTyp, uint8 BcastEn) +{ + sint8 ret = M2M_SUCCESS; + tstrM2mPsType strPs; + strPs.u8PsType = PsTyp; + strPs.u8BcastEn = BcastEn; + ret = hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_SLEEP, (uint8*) &strPs,sizeof(tstrM2mPsType), NULL, 0, 0); + M2M_INFO("POWER SAVE %d\n",PsTyp); + hif_set_sleep_mode(PsTyp); + return ret; +} +/*! +@fn NMI_API sint8 m2m_wifi_request_sleep(void) +@brief Request from WINC3400 device to Sleep for specific time in the M2M_PS_MANUAL Power save mode (only). +@param [in] u32SlpReqTime + Request Sleep in ms +@return The function SHALL return M2M_SUCCESS for success and a negative value otherwise. +@sa tenuPowerSaveModes , m2m_wifi_set_sleep_mode +@warning This API is currently unsupported on the WINC3400 +*/ +sint8 m2m_wifi_request_sleep(uint32 u32SlpReqTime) +{ + sint8 ret = M2M_SUCCESS; + uint8 psType; + psType = hif_get_sleep_mode(); + if(psType == M2M_PS_MANUAL) + { + tstrM2mSlpReqTime strPs; + strPs.u32SleepTime = u32SlpReqTime; + ret = hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_DOZE, (uint8*) &strPs,sizeof(tstrM2mSlpReqTime), NULL, 0, 0); + } + return ret; +} +/*! +@fn NMI_API sint8 m2m_wifi_set_device_name(uint8 *pu8DeviceName, uint8 u8DeviceNameLength); +@brief Set the WINC3400 device name which is used as P2P device name. +@param [in] pu8DeviceName + Buffer holding the device name. +@param [in] u8DeviceNameLength + Length of the device name. +@return The function SHALL return M2M_SUCCESS for success and a negative value otherwise. +@warning The Function called once after initialization. +*/ +sint8 m2m_wifi_set_device_name(uint8 *pu8DeviceName, uint8 u8DeviceNameLength) +{ + tstrM2MDeviceNameConfig strDeviceName; + if(u8DeviceNameLength >= M2M_DEVICE_NAME_MAX) + { + u8DeviceNameLength = M2M_DEVICE_NAME_MAX; + } + //pu8DeviceName[u8DeviceNameLength] = '\0'; + u8DeviceNameLength ++; + m2m_memcpy(strDeviceName.au8DeviceName, pu8DeviceName, u8DeviceNameLength); + return hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_SET_DEVICE_NAME, + (uint8*)&strDeviceName, sizeof(tstrM2MDeviceNameConfig), NULL, 0,0); +} +/*! +@fn \ + uint32 m2m_wifi_get_chipId(void) + +@brief + Get the WINC Chip ID. + +@return + The function SHALL return chipID >0 or 0 for failure. +*/ +uint32 m2m_wifi_get_chipId(void) +{ + return nmi_get_chipid(); +} +/*! +@fn sint8 m2m_wifi_get_firmware_version(tstrM2mRev* pstrRev) + +@brief + Synchronous API to obtain the firmware version currently running on the WINC IC + +@param [out] pstrRev + pointer holds address of structure "tstrM2mRev" that contains the firmware version parameters + +@return + The function SHALL return @ref M2M_SUCCESS for success and a negative value otherwise. +*/ +sint8 m2m_wifi_get_firmware_version(tstrM2mRev *pstrRev) +{ + sint8 ret = M2M_SUCCESS; + ret = hif_chip_wake(); + if(ret == M2M_SUCCESS) + { + ret = nm_get_firmware_full_info(pstrRev); + hif_chip_sleep(); + } + return ret; +} +/*! +@fn sint8 m2m_wifi_check_ota_rb(void); + +@brief + Synchronous API to check presence and compatibility of the WINC image that is stored in the inactive flash partition. + This is the image that would run on the WINC IC if @ref m2m_ota_switch_firmware or @ref m2m_ota_rollback were called, + followed by a reset of the WINC IC. + +@return + The function SHALL return @ref M2M_SUCCESS for compatible image and a negative value otherwise. +*/ +sint8 m2m_wifi_check_ota_rb(void) +{ + sint8 ret = M2M_SUCCESS; + uint16 ota_hif_info = 0; + + ret = nm_get_hif_info(NULL, &ota_hif_info); + if(ret == M2M_SUCCESS) + { + ret = hif_check_compatibility(ota_hif_info); + } + return ret; +} +/*! +@fn \ + NMI_API sint8 m2m_ota_get_firmware_version(tstrM2mRev *pstrRev); + +@brief + Synchronous API to obtain the firmware version of the WINC image that is stored in the inactive flash partition. + This is the image that would run on the WINC IC if @ref m2m_ota_switch_firmware or @ref m2m_ota_rollback were called, + followed by a reset of the WINC IC. + +@param [out] pstrRev + pointer holds address of structure "tstrM2mRev" that contains the ota fw version parameters + +@return + The function SHALL return @ref M2M_SUCCESS for success and a negative value otherwise. +*/ +NMI_API sint8 m2m_ota_get_firmware_version(tstrM2mRev * pstrRev) +{ + sint8 ret = M2M_SUCCESS; + ret = hif_chip_wake(); + if(ret == M2M_SUCCESS) + { + ret = nm_get_ota_firmware_info(pstrRev); + hif_chip_sleep(); + } + return ret; +} +#ifdef CONF_MGMT +sint8 m2m_wifi_enable_monitoring_mode(tstrM2MWifiMonitorModeCtrl *pstrMtrCtrl, uint8 *pu8PayloadBuffer, + uint16 u16BufferSize, uint16 u16DataOffset) +{ + sint8 s8Ret = -1; + if((pstrMtrCtrl->u8ChannelID >= M2M_WIFI_CH_1) && (pstrMtrCtrl->u8ChannelID <= M2M_WIFI_CH_14)) + { + gstrMgmtCtrl.pu8Buf = pu8PayloadBuffer; + gstrMgmtCtrl.u16Sz = u16BufferSize; + gstrMgmtCtrl.u16Offset = u16DataOffset; + s8Ret = hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_ENABLE_MONITORING, + (uint8*)pstrMtrCtrl, sizeof(tstrM2MWifiMonitorModeCtrl), NULL, 0,0); + } + return s8Ret; +} +sint8 m2m_wifi_disable_monitoring_mode(void) +{ + return hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_DISABLE_MONITORING, NULL, 0, NULL, 0,0); +} + +sint8 m2m_wifi_send_wlan_pkt(uint8 *pu8WlanPacket, uint16 u16WlanHeaderLength, uint16 u16WlanPktSize) +{ + sint8 s8Ret = -1; + if(pu8WlanPacket != NULL) + { + tstrM2MWifiTxPacketInfo strTxPkt; + + strTxPkt.u16PacketSize = u16WlanPktSize; + strTxPkt.u16HeaderLength = u16WlanHeaderLength; + s8Ret = hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_SEND_WIFI_PACKET | M2M_REQ_DATA_PKT, + (uint8*)&strTxPkt, sizeof(tstrM2MWifiTxPacketInfo), pu8WlanPacket, u16WlanPktSize, sizeof(tstrM2MWifiTxPacketInfo)); + } + return s8Ret; +} +#endif + +sint8 m2m_wifi_start_provision_mode(tstrM2MAPConfig *pstrAPConfig, char *pcHttpServerDomainName, uint8 bEnableHttpRedirect) +{ + sint8 s8Ret = M2M_ERR_FAIL; + + if((pstrAPConfig != NULL)) + { + tstrM2MProvisionModeConfig strProvConfig; + if(M2M_SUCCESS == m2m_validate_ap_parameters(pstrAPConfig)) + { + m2m_memcpy((uint8*)&strProvConfig.strApConfig, (uint8*)pstrAPConfig, sizeof(tstrM2MAPConfig)); + if((m2m_strlen((uint8 *)pcHttpServerDomainName) <= 0) || (NULL == pcHttpServerDomainName)) + { + M2M_ERR("INVALID DOMAIN NAME\n"); + goto ERR1; + } + m2m_memcpy((uint8*)strProvConfig.acHttpServerDomainName, (uint8*)pcHttpServerDomainName, 64); + strProvConfig.u8EnableRedirect = bEnableHttpRedirect; + + s8Ret = hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_START_PROVISION_MODE | M2M_REQ_DATA_PKT, + (uint8*)&strProvConfig, sizeof(tstrM2MProvisionModeConfig), NULL, 0, 0); + } + else + { + /*goto ERR1;*/ + } + } +ERR1: + return s8Ret; +} + +sint8 m2m_wifi_stop_provision_mode(void) +{ + return hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_STOP_PROVISION_MODE, NULL, 0, NULL, 0, 0); +} + +sint8 m2m_wifi_get_connection_info(void) +{ + return hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_GET_CONN_INFO, NULL, 0, NULL, 0, 0); +} + +sint8 m2m_wifi_set_sytem_time(uint32 u32UTCSeconds) +{ + return hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_SET_SYS_TIME, (uint8*)&u32UTCSeconds, sizeof(tstrSystemTime), NULL, 0, 0); +} +/*! + * @fn NMI_API sint8 m2m_wifi_get_sytem_time(void); + * @see m2m_wifi_enable_sntp + tstrSystemTime + * @note get the system time from the sntp client + * using the API \ref m2m_wifi_get_sytem_time. + * @return The function returns @ref M2M_SUCCESS for successful operations and a negative value otherwise. + */ +sint8 m2m_wifi_get_sytem_time(void) +{ + return hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_GET_SYS_TIME, NULL,0, NULL, 0, 0); +} + +sint8 m2m_wifi_enable_sntp(uint8 bEnable) +{ + uint8 u8Req; + + u8Req = bEnable ? M2M_WIFI_REQ_ENABLE_SNTP_CLIENT : M2M_WIFI_REQ_DISABLE_SNTP_CLIENT; + return hif_send(M2M_REQ_GROUP_WIFI, u8Req, NULL, 0, NULL, 0, 0); +} +/*! +@fn NMI_API sint8 m2m_wifi_set_power_profile(uint8 u8PwrMode); +@brief Change the power profile mode +@param [in] u8PwrMode + Change the WINC power profile to different mode + PWR_LOW1/PWR_LOW2/PWR_HIGH/PWR_AUTO (tenuM2mPwrMode) +@return The function SHALL return @ref M2M_SUCCESS for success and a negative value otherwise. +@sa tenuM2mPwrMode +@pre m2m_wifi_init +@warning must be called after the initializations and before any connection request and can't be changed in run time, +*/ +sint8 m2m_wifi_set_power_profile(uint8 u8PwrMode) +{ + sint8 ret = M2M_SUCCESS; + tstrM2mPwrMode strM2mPwrMode; + strM2mPwrMode.u8PwrMode = u8PwrMode; + ret = hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_SET_POWER_PROFILE, (uint8*)&strM2mPwrMode,sizeof(tstrM2mPwrMode), NULL, 0, 0); + return ret; +} +/*! +@fn NMI_API sint8 m2m_wifi_set_tx_power(uint8 u8TxPwrLevel); +@brief set the TX power tenuM2mTxPwrLevel +@param [in] u8TxPwrLevel + change the TX power tenuM2mTxPwrLevel +@return The function SHALL return @ref M2M_SUCCESS for success and a negative value otherwise. +@sa tenuM2mTxPwrLevel +@pre m2m_wifi_init +@warning +*/ +sint8 m2m_wifi_set_tx_power(uint8 u8TxPwrLevel) +{ + sint8 ret = M2M_SUCCESS; + tstrM2mTxPwrLevel strM2mTxPwrLevel; + strM2mTxPwrLevel.u8TxPwrLevel = u8TxPwrLevel; + ret = hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_SET_TX_POWER, (uint8*)&strM2mTxPwrLevel,sizeof(tstrM2mTxPwrLevel), NULL, 0, 0); + return ret; +} + +/*! +@fn NMI_API sint8 m2m_wifi_enable_firmware_logs(uint8 u8Enable); +@brief Enable or Disable logs in run time (Disable Firmware logs will + enhance the firmware start-up time and performance) +@param [in] u8Enable + Set 1 to enable the logs 0 for disable +@return The function SHALL return @ref M2M_SUCCESS for success and a negative value otherwise. +@sa __DISABLE_FIRMWARE_LOGS__ (build option to disable logs from initializations) +@pre m2m_wifi_init +@warning +*/ +sint8 m2m_wifi_enable_firmware_logs(uint8 u8Enable) +{ + sint8 ret = M2M_SUCCESS; + tstrM2mEnableLogs strM2mEnableLogs; + strM2mEnableLogs.u8Enable = u8Enable; + ret = hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_SET_ENABLE_LOGS, (uint8*)&strM2mEnableLogs,sizeof(tstrM2mEnableLogs), NULL, 0, 0); + return ret; +} + +/*! +@fn NMI_API sint8 m2m_wifi_set_battery_voltage(uint16 u16BattVoltx100); +@brief Enable or Disable logs in run time (Disable Firmware logs will + enhance the firmware start-up time and performance) +@param [in] u16BattVoltx100 + battery voltage multiplied by 100 +@return The function SHALL return @ref M2M_SUCCESS for success and a negative value otherwise. +@sa __DISABLE_FIRMWARE_LOGS__ (build option to disable logs from initializations) +@pre m2m_wifi_init +@warning +*/ +sint8 m2m_wifi_set_battery_voltage(uint16 u16BattVoltx100) +{ + sint8 ret = M2M_SUCCESS; + tstrM2mBatteryVoltage strM2mBattVol = {0}; + strM2mBattVol.u16BattVolt = u16BattVoltx100; + ret = hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_SET_BATTERY_VOLTAGE, (uint8*)&strM2mBattVol,sizeof(tstrM2mBatteryVoltage), NULL, 0, 0); + return ret; +} +/*! +@fn sint8 m2m_wifi_prng_get_random_bytes(uint8 * pu8PrngBuff,uint16 u16PrngSize) +@brief Get random bytes using the PRNG bytes. +@param [in] u16PrngSize + Size of the required random bytes to be generated. +@param [in] pu8PrngBuff + Pointer to user allocated buffer. +@return The function SHALL return M2M_SUCCESE for success and a negative value otherwise. +*/ +sint8 m2m_wifi_prng_get_random_bytes(uint8 * pu8PrngBuff,uint16 u16PrngSize) +{ + sint8 ret = M2M_ERR_FAIL; + tstrPrng strRng = {0}; + if((u16PrngSize < (M2M_BUFFER_MAX_SIZE - sizeof(tstrPrng)))&&(pu8PrngBuff != NULL)) + { + strRng.u16PrngSize = u16PrngSize; + strRng.pu8RngBuff = pu8PrngBuff; + ret = hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_GET_PRNG|M2M_REQ_DATA_PKT,(uint8 *)&strRng, sizeof(tstrPrng),NULL,0, 0); + } + else + { + M2M_ERR("PRNG Buffer exceeded maximum size %d or NULL Buffer\n",u16PrngSize); + } + return ret; +} +#ifdef ETH_MODE +/*! +@fn \ + NMI_API sint8 m2m_wifi_enable_mac_mcast(uint8* pu8MulticastMacAddress, uint8 u8AddRemove) + +@brief + Add MAC filter to receive Multicast packets. + +@param [in] pu8MulticastMacAddress + Pointer to the MAC address. +@param [in] u8AddRemove + Flag to Add/Remove MAC address. +@return + The function SHALL return 0 for success and a negative value otherwise. +*/ + +NMI_API sint8 m2m_wifi_enable_mac_mcast(uint8* pu8MulticastMacAddress, uint8 u8AddRemove) +{ + sint8 s8ret = M2M_ERR_FAIL; + tstrM2MMulticastMac strMulticastMac; + + if(pu8MulticastMacAddress != NULL ) + { + strMulticastMac.u8AddRemove = u8AddRemove; + m2m_memcpy(strMulticastMac.au8macaddress,pu8MulticastMacAddress,M2M_MAC_ADDRES_LEN); + M2M_DBG("mac multicast: %x:%x:%x:%x:%x:%x\r\n",strMulticastMac.au8macaddress[0],strMulticastMac.au8macaddress[1],strMulticastMac.au8macaddress[2],strMulticastMac.au8macaddress[3],strMulticastMac.au8macaddress[4],strMulticastMac.au8macaddress[5]); + s8ret = hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_SET_MAC_MCAST, (uint8 *)&strMulticastMac,sizeof(tstrM2MMulticastMac),NULL,0,0); + } + + return s8ret; + +} + +/*! +@fn \ + NMI_API sint8 m2m_wifi_set_receive_buffer(void* pvBuffer,uint16 u16BufferLen); + +@brief + set the ethernet receive buffer, should be called in the receive call back. + +@param [in] pvBuffer + Pointer to the ethernet receive buffer. +@param [in] u16BufferLen + Length of the buffer. + +@return + The function SHALL return 0 for success and a negative value otherwise. +*/ +NMI_API sint8 m2m_wifi_set_receive_buffer(void* pvBuffer,uint16 u16BufferLen) +{ + sint8 s8ret = M2M_SUCCESS; + if(pvBuffer != NULL) + { + gau8ethRcvBuf = pvBuffer; + gu16ethRcvBufSize= u16BufferLen; + } + else + { + s8ret = M2M_ERR_FAIL; + M2M_ERR("Buffer NULL pointer\r\n"); + } + return s8ret; +} +#endif + +/*! +@fn \ + NMI_API sint8 m2m_wifi_ble_api_send(const uint8* const msg, const uint32 len); + +@brief + Send an encapsulated Atmel BLE API message + +@param [in] msg + Pointer to the Atmel BLE API message raw bytes +@param [in] len + Length of the msg + +@return + The function SHALL return 0 for success and a negative value otherwise. +*/ +NMI_API sint8 m2m_wifi_ble_api_send(uint8* msg, uint32 len) +{ + tstrM2mBleApiMsg bleTx; + bleTx.u16Len = len; + return hif_send(M2M_REQ_GROUP_WIFI, M2M_WIFI_REQ_BLE_API_SEND | M2M_REQ_DATA_PKT, + (uint8*)&bleTx, sizeof(tstrM2mBleApiMsg), msg, len, sizeof(tstrM2mBleApiMsg)); +} diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmasic.c b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmasic.c new file mode 100644 index 000000000..7a6c4a69c --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmasic.c @@ -0,0 +1,741 @@ +/** + * + * \file + * + * \brief This module contains WINC3400 ASIC specific internal APIs. + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "common/include/nm_common.h" +#include "driver/source/nmbus.h" +#include "bsp/include/nm_bsp.h" +#include "driver/source/nmasic.h" + +#define NMI_GLB_RESET_0 (NMI_PERIPH_REG_BASE + 0x400) +#define NMI_INTR_REG_BASE (NMI_PERIPH_REG_BASE + 0xa00) +#define NMI_PIN_MUX_0 (NMI_PERIPH_REG_BASE + 0x408) +#define NMI_INTR_ENABLE (NMI_INTR_REG_BASE) +#define GET_UINT32(X,Y) (X[0+Y] + ((uint32)X[1+Y]<<8) + ((uint32)X[2+Y]<<16) +((uint32)X[3+Y]<<24)) + + + + +#define TIMEOUT (2000) +#define M2M_DISABLE_PS 0xD0UL + +/* Assume initially we're dealing with D0 - we will try other addresses if this + * fails - the addresses are as follows: + * 0x13 - for D0 + * 0x0F - for B0 + * 0x0E - for A0 + */ +static uint32 clk_status_reg_adr = 0x13; + +sint8 chip_apply_conf(uint32 u32Conf) +{ + sint8 ret = M2M_SUCCESS; + uint32 val32 = u32Conf; + +#ifdef __ENABLE_PMU__ + val32 |= rHAVE_USE_PMU_BIT; +#endif +#ifdef __ENABLE_SLEEP_CLK_SRC_RTC__ + val32 |= rHAVE_SLEEP_CLK_SRC_RTC_BIT; +#elif defined __ENABLE_SLEEP_CLK_SRC_XO__ + val32 |= rHAVE_SLEEP_CLK_SRC_XO_BIT; +#endif +#ifdef __ENABLE_EXT_PA_INV_TX_RX__ + val32 |= rHAVE_EXT_PA_INV_TX_RX; +#endif +#ifdef __ENABLE_LEGACY_RF_SETTINGS__ + val32 |= rHAVE_LEGACY_RF_SETTINGS; +#endif +#ifdef __DISABLE_FIRMWARE_LOGS__ + val32 |= rHAVE_LOGS_DISABLED_BIT; +#endif + do { + nm_write_reg(rNMI_GP_REG_1, val32); + if(val32 != 0) { + uint32 reg = 0; + ret = nm_read_reg_with_ret(rNMI_GP_REG_1, ®); + if(ret == M2M_SUCCESS) { + if(reg == val32) + break; + } + } else { + break; + } + } while(1); + + return M2M_SUCCESS; +} +/** +* @fn nm_clkless_wake +* @brief Wakeup the chip using clockless registers +* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure +* @author Samer Sarhan +* @date 06 June 2014 +* @version 1.0 +*/ +sint8 nm_clkless_wake(void) +{ + sint8 ret = M2M_SUCCESS; + uint32 reg, clk_status_reg,trials = 0; + uint32 keeptrying = 200; + /* wait 1ms, spi data read */ + nm_bsp_sleep(1); + ret = nm_read_reg_with_ret(0x1, ®); + if(ret != M2M_SUCCESS) { + M2M_ERR("Bus error (1). Wake up failed\n"); + return ret; + } + + /* + * At this point, I am not sure whether it is B0 or A0 + * If B0, then clks_enabled bit exists in register 0xf + * If A0, then clks_enabled bit exists in register 0xe + */ + do + { + /* Set bit 1 */ + nm_write_reg(0x1, reg | (1 << 1)); + + // Search for the correct (clock status) register address + do + { + if (keeptrying) --keeptrying; + + /* wait 1ms, spi data read */ + nm_bsp_sleep(1); + ret = nm_read_reg_with_ret(clk_status_reg_adr, &clk_status_reg); + if (ret != M2M_SUCCESS || (ret == M2M_SUCCESS && clk_status_reg == 0)) { + switch (clk_status_reg_adr) { + case 0x13: clk_status_reg_adr = 0x0F; break; + case 0x0F: clk_status_reg_adr = 0x0E; break; + default: clk_status_reg_adr = 0x00; break; + } + } + else + break; // we have found the correct register, break out of the search + } while (clk_status_reg_adr && keeptrying); + + if (0 == clk_status_reg_adr) { + M2M_ERR("Bus error (2). Wake up failed\n"); + return ret; + } + + // in case of clocks off, wait 2ms, and check it again. + // if still off, wait for another 2ms, for a total wait of 6ms. + // If still off, redo the wake up sequence + trials = 0; + while( ((clk_status_reg & 0x4) == 0) && (((++trials) %3) == 0) && keeptrying) + { + --keeptrying; + + /* Wait for the chip to stabilize*/ + nm_bsp_sleep(2); + + // Make sure chip is awake. This is an extra step that can be removed + // later to avoid the bus access overhead + nm_read_reg_with_ret(clk_status_reg_adr, &clk_status_reg); + + if ((clk_status_reg & 0x4) == 0) + { + M2M_ERR("clocks still OFF. Wake up failed\n"); + } + } + // in case of failure, Reset the wakeup bit to introduce a new edge on the next loop + if((clk_status_reg & 0x4) == 0) + { + // Reset bit 0 + nm_write_reg(0x1, reg | (1 << 1)); + } + } while((clk_status_reg & 0x4) == 0 && keeptrying); + + if (!keeptrying) + { + M2M_ERR("Wake up failed - out of retries\n"); + ret = M2M_ERR_INIT; + } + + return ret; +} +void chip_idle(void) +{ + uint32 reg =0; + nm_read_reg_with_ret(0x1, ®); + if(reg&0x2) + { + reg &=~(1 << 1); + nm_write_reg(0x1, reg); + } +} + +void enable_rf_blocks(void) +{ + nm_write_reg(0x6, 0xdb); + nm_write_reg(0x7, 0x6); + nm_bsp_sleep(10); + nm_write_reg(0x1480, 0); + nm_write_reg(0x1484, 0); + nm_bsp_sleep(10); + + nm_write_reg(0x6, 0x0); + nm_write_reg(0x7, 0x0); +} + +sint8 enable_interrupts(void) +{ + uint32 reg; + sint8 ret; + /** + interrupt pin mux select + **/ + ret = nm_read_reg_with_ret(NMI_PIN_MUX_0, ®); + if (M2M_SUCCESS != ret) { + return M2M_ERR_BUS_FAIL; + } + reg |= ((uint32) 1 << 8); + ret = nm_write_reg(NMI_PIN_MUX_0, reg); + if (M2M_SUCCESS != ret) { + return M2M_ERR_BUS_FAIL; + } + /** + interrupt enable + **/ + ret = nm_read_reg_with_ret(NMI_INTR_ENABLE, ®); + if (M2M_SUCCESS != ret) { + return M2M_ERR_BUS_FAIL; + } + reg |= ((uint32) 1 << 16); + ret = nm_write_reg(NMI_INTR_ENABLE, reg); + if (M2M_SUCCESS != ret) { + return M2M_ERR_BUS_FAIL; + } + return M2M_SUCCESS; +} + +sint8 cpu_start(void) { + uint32 reg; + sint8 ret; + + /** + reset regs + */ + nm_write_reg(BOOTROM_REG,0); + nm_write_reg(NMI_STATE_REG,0); + nm_write_reg(NMI_REV_REG,0); + + /** + Go... + **/ + ret = nm_read_reg_with_ret(0x1118, ®); + if (M2M_SUCCESS != ret) { + ret = M2M_ERR_BUS_FAIL; + M2M_ERR("[nmi start]: fail read reg 0x1118 ...\n"); + } + reg |= (1 << 0); + ret = nm_write_reg(0x1118, reg); + ret = nm_write_reg(0x150014, 0x1); + ret += nm_read_reg_with_ret(NMI_GLB_RESET_0, ®); + if ((reg & (1ul << 10)) == (1ul << 10)) { + reg &= ~(1ul << 10); + ret += nm_write_reg(NMI_GLB_RESET_0, reg); + } + + reg |= (1ul << 10); + ret += nm_write_reg(NMI_GLB_RESET_0, reg); + nm_bsp_sleep(1); /* TODO: Why bus error if this delay is not here. */ + return ret; +} + +uint32 nmi_get_chipid(void) +{ + static uint32 chipid = 0; + + if (chipid == 0) { + uint32 rfrevid; + + if((nm_read_reg_with_ret(0x1000, &chipid)) != M2M_SUCCESS) { + chipid = 0; + return 0; + } + if((nm_read_reg_with_ret(0x13f4, &rfrevid)) != M2M_SUCCESS) { + chipid = 0; + return 0; + } + + if(chipid == 0x1002a0) { + if (rfrevid == 0x1) { /* 1002A0 */ + } else /* if (rfrevid == 0x2) */ { /* 1002A1 */ + chipid = 0x1002a1; + } + } else if(chipid == 0x1002b0) { + if(rfrevid == 3) { /* 1002B0 */ + } else if(rfrevid == 4) { /* 1002B1 */ + chipid = 0x1002b1; + } else /* if(rfrevid == 5) */ { /* 1002B2 */ + chipid = 0x1002b2; + } + } else if(chipid == 0x1000f0) { + /* For 3400, the WiFi chip ID register reads 0x1000f0. + * Therefore using BT chip ID register here which should read 0x3000D0 + */ +#define rBT_CHIP_ID_REG (0x3b0000) + if((nm_read_reg_with_ret(rBT_CHIP_ID_REG, &chipid)) != M2M_SUCCESS) { + chipid = 0; + return 0; + } + if(chipid == 0x3000d0) { + if(rfrevid == 6) { + chipid = 0x3000d1; + } + else if(rfrevid == 2) { + chipid = 0x3000d2; + } + } + } +//#define PROBE_FLASH +#ifdef PROBE_FLASH + if(chipid) { + UWORD32 flashid; + + flashid = probe_spi_flash(); + if((chipid & 0xf00000) == 0x300000) { + if(flashid == 0x1440ef) { + chipid &= ~(0x0f0000); + chipid |= 0x040000; + } + } else { + if(flashid == 0x1230ef) { + chipid &= ~(0x0f0000); + chipid |= 0x050000; + } + if(flashid == 0xc21320c2) { + chipid &= ~(0x0f0000); + chipid |= 0x050000; + } + } + } +#else + /*M2M is by default have SPI flash*/ + if((chipid & 0xf00000) == 0x300000) { + chipid &= ~(0x0f0000); + chipid |= 0x040000; + } else { + chipid &= ~(0x0f0000); + chipid |= 0x050000; + } +#endif /* PROBE_FLASH */ + } + return chipid; +} + +uint32 nmi_get_rfrevid(void) +{ + uint32 rfrevid; + if((nm_read_reg_with_ret(0x13f4, &rfrevid)) != M2M_SUCCESS) { + rfrevid = 0; + return 0; + } + return rfrevid; +} + +void restore_pmu_settings_after_global_reset(void) +{ + /* + * Must restore PMU register value after + * global reset if PMU toggle is done at + * least once since the last hard reset. + */ + if(REV(nmi_get_chipid()) >= REV_2B0) { + nm_write_reg(0x1e48, 0xb78469ce); + } +} + +void nmi_update_pll(void) +{ + uint32 pll; + + pll = nm_read_reg(0x1428); + pll &= ~0x1ul; + nm_write_reg(0x1428, pll); + pll |= 0x1ul; + nm_write_reg(0x1428, pll); + +} +void nmi_set_sys_clk_src_to_xo(void) +{ + uint32 val32; + + /* Switch system clock source to XO. This will take effect after nmi_update_pll(). */ + val32 = nm_read_reg(0x141c); + val32 |= (1 << 2); + nm_write_reg(0x141c, val32); + + /* Do PLL update */ + nmi_update_pll(); +} +sint8 chip_wake(void) +{ + sint8 ret = M2M_SUCCESS; + + ret = nm_clkless_wake(); + if(ret != M2M_SUCCESS) return ret; + +// enable_rf_blocks(); MERGEBUG: TEMPORARILY DISABLING + + return ret; +} +sint8 chip_reset_and_cpu_halt(void) +{ + sint8 ret = M2M_SUCCESS; + uint32 reg = 0; + + ret = chip_wake(); + if(ret != M2M_SUCCESS) { + return ret; + } + chip_reset(); + ret = nm_read_reg_with_ret(0x1118, ®); + if (M2M_SUCCESS != ret) { + ret = M2M_ERR_BUS_FAIL; + M2M_ERR("[nmi start]: fail read reg 0x1118 ...\n"); + } + reg |= (1 << 0); + ret = nm_write_reg(0x1118, reg); + ret += nm_read_reg_with_ret(NMI_GLB_RESET_0, ®); + if ((reg & (1ul << 10)) == (1ul << 10)) { + reg &= ~(1ul << 10); + ret += nm_write_reg(NMI_GLB_RESET_0, reg); + ret += nm_read_reg_with_ret(NMI_GLB_RESET_0, ®); + } +#if 0 + reg |= (1ul << 10); + ret += nm_write_reg(NMI_GLB_RESET_0, reg); + ret += nm_read_reg_with_ret(NMI_GLB_RESET_0, ®); +#endif + nm_write_reg(BOOTROM_REG,0); + nm_write_reg(NMI_STATE_REG,0); + nm_write_reg(NMI_REV_REG,0); + nm_write_reg(NMI_PIN_MUX_0, 0x11111000); + return ret; +} +sint8 chip_reset(void) +{ + sint8 ret = M2M_SUCCESS; + +#if 0 + // MERGEBUG: TODO: This causes serial trace from the chip to be garbled - investigate +#ifndef CONF_WINC_USE_UART + nmi_set_sys_clk_src_to_xo(); +#endif +#endif + + ret += nm_write_reg(NMI_GLB_RESET_0, 0); + nm_bsp_sleep(50); +#ifndef CONF_WINC_USE_UART + restore_pmu_settings_after_global_reset(); +#endif + return ret; +} + +sint8 wait_for_bootrom(uint8 arg) +{ + sint8 ret = M2M_SUCCESS; + uint32 reg = 0, cnt = 0; + + reg = 0; + while(1) { + reg = nm_read_reg(0x1014); /* wait for efuse loading done */ + if (reg & 0x80000000) { + break; + } + nm_bsp_sleep(1); /* TODO: Why bus error if this delay is not here. */ + } + reg = nm_read_reg(M2M_WAIT_FOR_HOST_REG); + reg &= 0x1; + + /* check if waiting for the host will be skipped or not */ + if(reg == 0) + { + reg = 0; + while(reg != M2M_FINISH_BOOT_ROM) + { + nm_bsp_sleep(1); + reg = nm_read_reg(BOOTROM_REG); + + if(++cnt > TIMEOUT) + { + M2M_DBG("failed to load firmware from flash.\n"); + ret = M2M_ERR_INIT; + goto ERR2; + } + } + } + + if(2 == arg) { + nm_write_reg(NMI_REV_REG, M2M_ATE_FW_START_VALUE); + } else { + /*bypass this step*/ + } + + if(REV(nmi_get_chipid()) == REV_3A0) + { + chip_apply_conf(rHAVE_USE_PMU_BIT); + } + else + { + chip_apply_conf(0); + } + + nm_write_reg(BOOTROM_REG,M2M_START_FIRMWARE); + +#ifdef __ROM_TEST__ + rom_test(); +#endif /* __ROM_TEST__ */ + +ERR2: + return ret; +} + +sint8 wait_for_firmware_start(uint8 arg) +{ + sint8 ret = M2M_SUCCESS; + uint32 reg = 0, cnt = 0; + volatile uint32 regAddress = NMI_STATE_REG; + volatile uint32 checkValue = M2M_FINISH_INIT_STATE; + + if(2 == arg) { + regAddress = NMI_REV_REG; + checkValue = M2M_ATE_FW_IS_UP_VALUE; + } else { + /*bypass this step*/ + } + + while (checkValue != reg) + { + nm_bsp_sleep(2); /* TODO: Why bus error if this delay is not here. */ + M2M_DBG("%x %x %x\n",(unsigned int)nm_read_reg(0x108c),(unsigned int)nm_read_reg(0x108c),(unsigned int)nm_read_reg(0x14A0)); + if (nm_read_reg_with_ret(regAddress, ®) != M2M_SUCCESS) + { + // ensure reg != checkValue + reg = !checkValue; + } + if(++cnt > TIMEOUT) + { + M2M_DBG("Time out for wait firmware Run\n"); + ret = M2M_ERR_INIT; + goto ERR; + } + } + if(M2M_FINISH_INIT_STATE == checkValue) + { + nm_write_reg(NMI_STATE_REG, 0); + } +ERR: + return ret; +} + +sint8 chip_deinit(void) +{ + uint32 reg = 0; + sint8 ret; + uint8 timeout = 10; + + /** + stop the firmware, need a re-download + **/ + ret = nm_read_reg_with_ret(NMI_GLB_RESET_0, ®); + if (ret != M2M_SUCCESS) { + M2M_ERR("failed to de-initialize\n"); + } + reg &= ~(1 << 10); + ret = nm_write_reg(NMI_GLB_RESET_0, reg); + + if (ret != M2M_SUCCESS) { + M2M_ERR("Error while writing reg\n"); + return ret; + } + + do { + ret = nm_read_reg_with_ret(NMI_GLB_RESET_0, ®); + if (ret != M2M_SUCCESS) { + M2M_ERR("Error while reading reg\n"); + return ret; + } + /*Workaround to ensure that the chip is actually reset*/ + if ((reg & (1 << 10))) { + M2M_DBG("Bit 10 not reset retry %d\n", timeout); + reg &= ~(1 << 10); + ret = nm_write_reg(NMI_GLB_RESET_0, reg); + timeout--; + } else { + break; + } + + } while (timeout); + + return ret; +} + +#ifdef CONF_PERIPH + +sint8 set_gpio_dir(uint8 gpio, uint8 dir) +{ + uint32 val32; + sint8 ret; + + ret = nm_read_reg_with_ret(0x20108, &val32); + if(ret != M2M_SUCCESS) goto _EXIT; + + if(dir) { + val32 |= (1ul << gpio); + } else { + val32 &= ~(1ul << gpio); + } + + ret = nm_write_reg(0x20108, val32); + +_EXIT: + return ret; +} +sint8 set_gpio_val(uint8 gpio, uint8 val) +{ + uint32 val32; + sint8 ret; + + ret = nm_read_reg_with_ret(0x20100, &val32); + if(ret != M2M_SUCCESS) goto _EXIT; + + if(val) { + val32 |= (1ul << gpio); + } else { + val32 &= ~(1ul << gpio); + } + + ret = nm_write_reg(0x20100, val32); + +_EXIT: + return ret; +} + +sint8 get_gpio_val(uint8 gpio, uint8* val) +{ + uint32 val32; + sint8 ret; + + ret = nm_read_reg_with_ret(0x20104, &val32); + if(ret != M2M_SUCCESS) goto _EXIT; + + *val = (uint8)((val32 >> gpio) & 0x01); + +_EXIT: + return ret; +} + +sint8 pullup_ctrl(uint32 pinmask, uint8 enable) +{ + sint8 s8Ret; + uint32 val32; + s8Ret = nm_read_reg_with_ret(0x142c, &val32); + if(s8Ret != M2M_SUCCESS) { + M2M_ERR("[pullup_ctrl]: failed to read\n"); + goto _EXIT; + } + if(enable) { + val32 &= ~pinmask; + } else { + val32 |= pinmask; + } + s8Ret = nm_write_reg(0x142c, val32); + if(s8Ret != M2M_SUCCESS) { + M2M_ERR("[pullup_ctrl]: failed to write\n"); + goto _EXIT; + } +_EXIT: + return s8Ret; +} +#endif /* CONF_PERIPH */ + +sint8 nmi_get_otp_mac_address(uint8 *pu8MacAddr, uint8 * pu8IsValid) +{ + sint8 ret; + uint32 u32RegValue; + uint8 mac[6]; + tstrGpRegs strgp = {0}; + + ret = nm_read_reg_with_ret(rNMI_GP_REG_0, &u32RegValue); + if(ret != M2M_SUCCESS) goto _EXIT_ERR; + + ret = nm_read_block(u32RegValue|0x30000,(uint8*)&strgp,sizeof(tstrGpRegs)); + if(ret != M2M_SUCCESS) goto _EXIT_ERR; + u32RegValue = strgp.u32Mac_efuse_mib; + + if(!EFUSED_MAC(u32RegValue)) { + M2M_DBG("Default MAC\n"); + m2m_memset(pu8MacAddr, 0, 6); + goto _EXIT_ERR; + } + + M2M_DBG("OTP MAC\n"); + u32RegValue >>=16; + ret = nm_read_block(u32RegValue|0x30000, mac, 6); + m2m_memcpy(pu8MacAddr,mac,6); + if(pu8IsValid) *pu8IsValid = 1; + return ret; + +_EXIT_ERR: + if(pu8IsValid) *pu8IsValid = 0; + return ret; +} + +sint8 nmi_get_mac_address(uint8 *pu8MacAddr) +{ + sint8 ret; + uint32 u32RegValue; + uint8 mac[6]; + tstrGpRegs strgp = {0}; + + ret = nm_read_reg_with_ret(rNMI_GP_REG_0, &u32RegValue); + if(ret != M2M_SUCCESS) goto _EXIT_ERR; + + ret = nm_read_block(u32RegValue|0x30000,(uint8*)&strgp,sizeof(tstrGpRegs)); + if(ret != M2M_SUCCESS) goto _EXIT_ERR; + u32RegValue = strgp.u32Mac_efuse_mib; + + u32RegValue &=0x0000ffff; + ret = nm_read_block(u32RegValue|0x30000, mac, 6); + m2m_memcpy(pu8MacAddr, mac, 6); + + return ret; + +_EXIT_ERR: + return ret; +} diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmasic.h b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmasic.h new file mode 100644 index 000000000..ca32b3a04 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmasic.h @@ -0,0 +1,141 @@ +/** + * + * \file + * + * \brief This module contains WINC3400 ASIC specific internal APIs. + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _NMASIC_H_ +#define _NMASIC_H_ + +#include "common/include/nm_common.h" + +#define NMI_PERIPH_REG_BASE 0x1000 +#define NMI_CHIPID (NMI_PERIPH_REG_BASE) +#define rNMI_GP_REG_0 (0x149c) +#define rNMI_GP_REG_1 (0x14A0) +#define rNMI_GLB_RESET (0x1400) +#define rNMI_BOOT_RESET_MUX (0x1118) +#define NMI_STATE_REG (0x108c) +#define BOOTROM_REG (0xc000c) +#define NMI_REV_REG (0x207ac) /*Also, Used to load ATE firmware from SPI Flash and to ensure that it is running too*/ +#define M2M_WAIT_FOR_HOST_REG (0x207bc) +#define M2M_FINISH_INIT_STATE 0x02532636UL +#define M2M_FINISH_BOOT_ROM 0x10add09eUL +#define M2M_START_FIRMWARE 0xef522f61UL +#define M2M_START_PS_FIRMWARE 0x94992610UL + +#define M2M_ATE_FW_START_VALUE (0x3C1CD57D) /*Also, Change this value in boot_firmware if it will be changed here*/ +#define M2M_ATE_FW_IS_UP_VALUE (0xD75DC1C3) /*Also, Change this value in ATE (Burst) firmware if it will be changed here*/ + +#define REV_2B0 (0x2B0) +#define REV_B0 (0x2B0) +#define REV_3A0 (0x3A0) +#define CHIP_ID_3000D (0x3000D0) + +#define GET_CHIPID() nmi_get_chipid() +#define ISNMC1000(id) (((id & 0xfffff000) == 0x100000) ? 1 : 0) +#define ISNMC1500(id) (((id & 0xfffff000) == 0x150000) ? 1 : 0) +#define ISNMC3400(id) (((id & 0xfff0f000) == 0x300000) ? 1 : 0) +#define REV(id) ( ((id) & 0x00000fff ) ) +#define EFUSED_MAC(value) (value & 0xffff0000) + +#define rHAVE_SDIO_IRQ_GPIO_BIT (NBIT0) +#define rHAVE_USE_PMU_BIT (NBIT1) +#define rHAVE_SLEEP_CLK_SRC_RTC_BIT (NBIT2) +#define rHAVE_SLEEP_CLK_SRC_XO_BIT (NBIT3) +#define rHAVE_EXT_PA_INV_TX_RX (NBIT4) +#define rHAVE_LEGACY_RF_SETTINGS (NBIT5) +#define rHAVE_LOGS_DISABLED_BIT (NBIT6) + +typedef struct{ + uint32 u32Mac_efuse_mib; + uint32 u32Firmware_Ota_rev; +}tstrGpRegs; + +#ifdef __cplusplus + extern "C" { + #endif +/** +* @fn nm_clkless_wake +* @brief Wakeup the chip using clockless registers +* @return ZERO in case of success and M2M_ERR_BUS_FAIL in case of failure +* @author Samer Sarhan +*/ +sint8 nm_clkless_wake(void); + +sint8 chip_wake(void); + +void chip_idle(void); + +void enable_rf_blocks(void); + +sint8 enable_interrupts(void); + +sint8 cpu_start(void); + +uint32 nmi_get_chipid(void); + +uint32 nmi_get_rfrevid(void); + +void restore_pmu_settings_after_global_reset(void); + +void nmi_update_pll(void); + +void nmi_set_sys_clk_src_to_xo(void); + +sint8 chip_reset(void); + +sint8 wait_for_bootrom(uint8); + +sint8 wait_for_firmware_start(uint8); + +sint8 chip_deinit(void); + +sint8 chip_reset_and_cpu_halt(void); + +sint8 set_gpio_dir(uint8 gpio, uint8 dir); + +sint8 set_gpio_val(uint8 gpio, uint8 val); + +sint8 get_gpio_val(uint8 gpio, uint8* val); + +sint8 pullup_ctrl(uint32 pinmask, uint8 enable); + +sint8 nmi_get_otp_mac_address(uint8 *pu8MacAddr, uint8 * pu8IsValid); + +sint8 nmi_get_mac_address(uint8 *pu8MacAddr); + +sint8 chip_apply_conf(uint32 u32conf); + +#ifdef __cplusplus + } + #endif + +#endif /*_NMASIC_H_*/ diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmbus.c b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmbus.c new file mode 100644 index 000000000..fbecaac0c --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmbus.c @@ -0,0 +1,275 @@ +/** + * + * \file + * + * \brief This module contains WINC3400 bus APIs implementation. + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef CORTUS_APP + +#include "nmbus.h" +#include "nmi2c.h" +#include "nmspi.h" +#include "nmuart.h" + +#define MAX_TRX_CFG_SZ 8 + +/** +* @fn nm_bus_iface_init +* @brief Initialize bus interface +* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure +* @author M. Abdelmawla +* @date 11 July 2012 +* @version 1.0 +*/ +sint8 nm_bus_iface_init(uint8 *pvInitVal, uint32 req_serial_number) +{ + sint8 ret = M2M_SUCCESS; + ret = nm_bus_init(pvInitVal, req_serial_number); + + return ret; +} + +/** +* @fn nm_bus_iface_deinit +* @brief Deinitialize bus interface +* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure +* @author Samer Sarhan +* @date 07 April 2014 +* @version 1.0 +*/ +sint8 nm_bus_iface_deinit(void) +{ + sint8 ret = M2M_SUCCESS; + ret = nm_bus_deinit(); + + return ret; +} + +/** +* @fn nm_bus_iface_reconfigure +* @brief reconfigure bus interface +* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure +* @author Viswanathan Murugesan +* @date 22 Oct 2014 +* @version 1.0 +*/ +sint8 nm_bus_iface_reconfigure(void *ptr) +{ + sint8 ret = M2M_SUCCESS; +#ifdef CONF_WINC_USE_UART + if(ptr) + ret = nm_uart_reconfigure(ptr); + else + ret = M2M_ERR_BUS_FAIL; +#endif + return ret; +} +/* +* @fn nm_read_reg +* @brief Read register +* @param [in] u32Addr +* Register address +* @return Register value +* @author M. Abdelmawla +* @date 11 July 2012 +* @version 1.0 +*/ +uint32 nm_read_reg(uint32 u32Addr) +{ +#ifdef CONF_WINC_USE_UART + return nm_uart_read_reg(u32Addr); +#elif defined (CONF_WINC_USE_SPI) + return nm_spi_read_reg(u32Addr); +#elif defined (CONF_WINC_USE_I2C) + return nm_i2c_read_reg(u32Addr); +#else +#error "Plesae define bus usage" +#endif + +} + +/* +* @fn nm_read_reg_with_ret +* @brief Read register with error code return +* @param [in] u32Addr +* Register address +* @param [out] pu32RetVal +* Pointer to u32 variable used to return the read value +* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure +* @author M. Abdelmawla +* @date 11 July 2012 +* @version 1.0 +*/ +sint8 nm_read_reg_with_ret(uint32 u32Addr, uint32* pu32RetVal) +{ +#ifdef CONF_WINC_USE_UART + return nm_uart_read_reg_with_ret(u32Addr,pu32RetVal); +#elif defined (CONF_WINC_USE_SPI) + return nm_spi_read_reg_with_ret(u32Addr,pu32RetVal); +#elif defined (CONF_WINC_USE_I2C) + return nm_i2c_read_reg_with_ret(u32Addr,pu32RetVal); +#else +#error "Plesae define bus usage" +#endif +} + +/* +* @fn nm_write_reg +* @brief write register +* @param [in] u32Addr +* Register address +* @param [in] u32Val +* Value to be written to the register +* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure +* @author M. Abdelmawla +* @date 11 July 2012 +* @version 1.0 +*/ +sint8 nm_write_reg(uint32 u32Addr, uint32 u32Val) +{ +#ifdef CONF_WINC_USE_UART + return nm_uart_write_reg(u32Addr,u32Val); +#elif defined (CONF_WINC_USE_SPI) + return nm_spi_write_reg(u32Addr,u32Val); +#elif defined (CONF_WINC_USE_I2C) + return nm_i2c_write_reg(u32Addr,u32Val); +#else +#error "Plesae define bus usage" +#endif +} + +static inline sint8 p_nm_read_block(uint32 u32Addr, uint8 *puBuf, uint16 u16Sz) +{ +#ifdef CONF_WINC_USE_UART + return nm_uart_read_block(u32Addr,puBuf,u16Sz); +#elif defined (CONF_WINC_USE_SPI) + return nm_spi_read_block(u32Addr,puBuf,u16Sz); +#elif defined (CONF_WINC_USE_I2C) + return nm_i2c_read_block(u32Addr,puBuf,u16Sz); +#else +#error "Plesae define bus usage" +#endif + +} +/* +* @fn nm_read_block +* @brief Read block of data +* @param [in] u32Addr +* Start address +* @param [out] puBuf +* Pointer to a buffer used to return the read data +* @param [in] u32Sz +* Number of bytes to read. The buffer size must be >= u32Sz +* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure +* @author M. Abdelmawla +* @date 11 July 2012 +* @version 1.0 +*/ +sint8 nm_read_block(uint32 u32Addr, uint8 *puBuf, uint32 u32Sz) +{ + uint16 u16MaxTrxSz = egstrNmBusCapabilities.u16MaxTrxSz - MAX_TRX_CFG_SZ; + uint32 off = 0; + sint8 s8Ret = M2M_SUCCESS; + + for(;;) + { + if(u32Sz <= u16MaxTrxSz) + { + s8Ret += p_nm_read_block(u32Addr, &puBuf[off], (uint16)u32Sz); + break; + } + else + { + s8Ret += p_nm_read_block(u32Addr, &puBuf[off], u16MaxTrxSz); + if(M2M_SUCCESS != s8Ret) break; + u32Sz -= u16MaxTrxSz; + off += u16MaxTrxSz; + u32Addr += u16MaxTrxSz; + } + } + + return s8Ret; +} + +static inline sint8 p_nm_write_block(uint32 u32Addr, uint8 *puBuf, uint16 u16Sz) +{ +#ifdef CONF_WINC_USE_UART + return nm_uart_write_block(u32Addr,puBuf,u16Sz); +#elif defined (CONF_WINC_USE_SPI) + return nm_spi_write_block(u32Addr,puBuf,u16Sz); +#elif defined (CONF_WINC_USE_I2C) + return nm_i2c_write_block(u32Addr,puBuf,u16Sz); +#else +#error "Plesae define bus usage" +#endif + +} +/** +* @fn nm_write_block +* @brief Write block of data +* @param [in] u32Addr +* Start address +* @param [in] puBuf +* Pointer to the buffer holding the data to be written +* @param [in] u32Sz +* Number of bytes to write. The buffer size must be >= u32Sz +* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure +* @author M. Abdelmawla +* @date 11 July 2012 +* @version 1.0 +*/ +sint8 nm_write_block(uint32 u32Addr, uint8 *puBuf, uint32 u32Sz) +{ + uint16 u16MaxTrxSz = egstrNmBusCapabilities.u16MaxTrxSz - MAX_TRX_CFG_SZ; + uint32 off = 0; + sint8 s8Ret = M2M_SUCCESS; + + for(;;) + { + if(u32Sz <= u16MaxTrxSz) + { + s8Ret += p_nm_write_block(u32Addr, &puBuf[off], (uint16)u32Sz); + break; + } + else + { + s8Ret += p_nm_write_block(u32Addr, &puBuf[off], u16MaxTrxSz); + if(M2M_SUCCESS != s8Ret) break; + u32Sz -= u16MaxTrxSz; + off += u16MaxTrxSz; + u32Addr += u16MaxTrxSz; + } + } + + return s8Ret; +} + +#endif + diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmbus.h b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmbus.h new file mode 100644 index 000000000..44d115934 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmbus.h @@ -0,0 +1,132 @@ +/** + * + * \file + * + * \brief This module contains WINC3400 bus APIs implementation. + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _NMBUS_H_ +#define _NMBUS_H_ + +#include "common/include/nm_common.h" +#include "bus_wrapper/include/nm_bus_wrapper.h" + + + +#ifdef __cplusplus +extern "C"{ +#endif +/** +* @fn nm_bus_iface_init +* @brief Initialize bus interface +* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure +*/ +sint8 nm_bus_iface_init(uint8 *pvInitVal, uint32 req_serial_number); + + +/** +* @fn nm_bus_iface_deinit +* @brief Deinitialize bus interface +* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure +*/ +sint8 nm_bus_iface_deinit(void); + +/** +* @fn nm_bus_iface_reconfigure +* @brief reconfigure bus interface +* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure +*/ +sint8 nm_bus_iface_reconfigure(void *ptr); + +/** +* @fn nm_read_reg +* @brief Read register +* @param [in] u32Addr +* Register address +* @return Register value +*/ +uint32 nm_read_reg(uint32 u32Addr); + +/** +* @fn nm_read_reg_with_ret +* @brief Read register with error code return +* @param [in] u32Addr +* Register address +* @param [out] pu32RetVal +* Pointer to u32 variable used to return the read value +* @return ZERO in case of success and M2M_ERR_BUS_FAIL in case of failure +*/ +sint8 nm_read_reg_with_ret(uint32 u32Addr, uint32* pu32RetVal); + +/** +* @fn nm_write_reg +* @brief write register +* @param [in] u32Addr +* Register address +* @param [in] u32Val +* Value to be written to the register +* @return ZERO in case of success and M2M_ERR_BUS_FAIL in case of failure +*/ +sint8 nm_write_reg(uint32 u32Addr, uint32 u32Val); + +/** +* @fn nm_read_block +* @brief Read block of data +* @param [in] u32Addr +* Start address +* @param [out] puBuf +* Pointer to a buffer used to return the read data +* @param [in] u32Sz +* Number of bytes to read. The buffer size must be >= u32Sz +* @return ZERO in case of success and M2M_ERR_BUS_FAIL in case of failure +*/ +sint8 nm_read_block(uint32 u32Addr, uint8 *puBuf, uint32 u32Sz); + +/** +* @fn nm_write_block +* @brief Write block of data +* @param [in] u32Addr +* Start address +* @param [in] puBuf +* Pointer to the buffer holding the data to be written +* @param [in] u32Sz +* Number of bytes to write. The buffer size must be >= u32Sz +* @return ZERO in case of success and M2M_ERR_BUS_FAIL in case of failure +*/ +sint8 nm_write_block(uint32 u32Addr, uint8 *puBuf, uint32 u32Sz); + + + + +#ifdef __cplusplus +} +#endif + +#endif /* _NMBUS_H_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmdrv.c b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmdrv.c new file mode 100644 index 000000000..a4de41d4c --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmdrv.c @@ -0,0 +1,407 @@ +/** + * + * \file + * + * \brief This module contains WINC3400 M2M driver APIs implementation. + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "common/include/nm_common.h" +#include "driver/source/nmbus.h" +#include "bsp/include/nm_bsp.h" +#include "driver/source/nmdrv.h" +#include "driver/source/nmasic.h" +#include "driver/include/m2m_types.h" + +#ifdef CONF_WINC_USE_SPI +#include "driver/source/nmspi.h" +#endif + +/** +* @fn nm_get_hif_info(uint16 *pu16FwHifInfo, uint16 *pu16OtaHifInfo); +* @brief Get Hif info of images in both partitions (Firmware and Ota). +* @param [out] pu16FwHifInfo +* Pointer holding Hif info of image in the active partition. +* @param [out] pu16OtaHifInfo +* Pointer holding Hif info of image in the inactive partition. +* @return ZERO in case of success and Negative error code in case of failure +*/ +sint8 nm_get_hif_info(uint16 *pu16FwHifInfo, uint16 *pu16OtaHifInfo) +{ + sint8 ret = M2M_SUCCESS; + uint32 reg = 0; + + ret = nm_read_reg_with_ret(NMI_REV_REG, ®); + if(ret == M2M_SUCCESS) + { + if(pu16FwHifInfo != NULL) + { + *pu16FwHifInfo = (uint16)reg; + } + if(pu16OtaHifInfo) + { + *pu16OtaHifInfo = (uint16)(reg>>16); + } + } + return ret; +} +/** +* @fn nm_get_firmware_full_info(tstrM2mRev* M2mRev) +* @brief Get Firmware version info +* @param [out] M2mRev +* pointer holds address of structure "tstrM2mRev" that contains the firmware version parameters +* @version 1.0 +*/ +sint8 nm_get_firmware_full_info(tstrM2mRev* pstrRev) +{ + uint16 fw_hif_info = 0; + uint32 reg = 0; + sint8 ret = M2M_SUCCESS; + tstrGpRegs strgp = {0}; + + m2m_memset((uint8*)pstrRev,0,sizeof(tstrM2mRev)); + nm_get_hif_info(&fw_hif_info, NULL); + + M2M_INFO("Fw HIF: %04x\n", fw_hif_info); + if(M2M_GET_HIF_BLOCK(fw_hif_info) == M2M_HIF_BLOCK_VALUE) + { + ret = nm_read_reg_with_ret(rNMI_GP_REG_0, ®); + if(ret == M2M_SUCCESS) + { + if(reg != 0) + { + ret = nm_read_block(reg|0x30000,(uint8*)&strgp,sizeof(tstrGpRegs)); + if(ret == M2M_SUCCESS) + { + reg = strgp.u32Firmware_Ota_rev; + reg &= 0x0000ffff; + if(reg != 0) + { + ret = nm_read_block(reg|0x30000,(uint8*)pstrRev,sizeof(tstrM2mRev)); + if(ret == M2M_SUCCESS) + { + M2M_INFO("Firmware HIF (%u) : %u.%u \n", M2M_GET_HIF_BLOCK(pstrRev->u16FirmwareHifInfo), M2M_GET_HIF_MAJOR(pstrRev->u16FirmwareHifInfo), M2M_GET_HIF_MINOR(pstrRev->u16FirmwareHifInfo)); + M2M_INFO("Firmware ver : %u.%u.%u \n", pstrRev->u8FirmwareMajor, pstrRev->u8FirmwareMinor, pstrRev->u8FirmwarePatch); + M2M_INFO("Firmware Build %s Time %s\n", pstrRev->BuildDate, pstrRev->BuildTime); + + /* Check Hif info is consistent */ + if(fw_hif_info != pstrRev->u16FirmwareHifInfo) + { + ret = M2M_ERR_FAIL; + M2M_ERR("Inconsistent Firmware Version\n"); + } + } + } + else + { + ret = M2M_ERR_FAIL; + } + } + } + else + { + ret = M2M_ERR_FAIL; + } + } + } + else + { + ret = M2M_ERR_FAIL; + } + if(ret != M2M_SUCCESS) + { + M2M_ERR("Unknown Firmware Version\n"); + } + return ret; +} +/** +* @fn nm_get_ota_firmware_info(tstrM2mRev* pstrRev) +* @brief Get Firmware version info +* @param [out] M2mRev +* pointer holds address of structure "tstrM2mRev" that contains the firmware version parameters + +* @version 1.0 +*/ +sint8 nm_get_ota_firmware_info(tstrM2mRev* pstrRev) +{ + uint16 ota_hif_info = 0; + uint32 reg = 0; + sint8 ret = M2M_SUCCESS; + tstrGpRegs strgp = {0}; + + m2m_memset((uint8*)pstrRev,0,sizeof(tstrM2mRev)); + nm_get_hif_info(NULL, &ota_hif_info); + + M2M_INFO("Ota HIF: %04x\n", ota_hif_info); + if(M2M_GET_HIF_BLOCK(ota_hif_info) == M2M_HIF_BLOCK_VALUE) + { + ret = nm_read_reg_with_ret(rNMI_GP_REG_0, ®); + if(ret == M2M_SUCCESS) + { + if(reg != 0) + { + ret = nm_read_block(reg|0x30000,(uint8*)&strgp,sizeof(tstrGpRegs)); + if(ret == M2M_SUCCESS) + { + reg = strgp.u32Firmware_Ota_rev; + reg >>= 16; + if(reg != 0) + { + ret = nm_read_block(reg|0x30000,(uint8*)pstrRev,sizeof(tstrM2mRev)); + if(ret == M2M_SUCCESS) + { + M2M_INFO("OTA HIF (%u) : %u.%u \n", M2M_GET_HIF_BLOCK(pstrRev->u16FirmwareHifInfo), M2M_GET_HIF_MAJOR(pstrRev->u16FirmwareHifInfo), M2M_GET_HIF_MINOR(pstrRev->u16FirmwareHifInfo)); + M2M_INFO("OTA ver : %u.%u.%u \n", pstrRev->u8FirmwareMajor, pstrRev->u8FirmwareMinor, pstrRev->u8FirmwarePatch); + M2M_INFO("OTA Build %s Time %s\n", pstrRev->BuildDate, pstrRev->BuildTime); + + /* Check Hif info is consistent */ + if(ota_hif_info != pstrRev->u16FirmwareHifInfo) + { + ret = M2M_ERR_FAIL; + M2M_ERR("Inconsistent OTA Version\n"); + } + } + } + else + { + ret = M2M_ERR_FAIL; + } + } + } + else + { + ret = M2M_ERR_FAIL; + } + } + } + else + { + ret = M2M_ERR_FAIL; + } + if(ret != M2M_SUCCESS) + { + M2M_INFO("No valid Ota image\n"); + } + return ret; +} + +/* +* @fn nm_drv_init_download_mode +* @brief Initialize NMC1000 driver +* @return M2M_SUCCESS in case of success and Negative error code in case of failure +* @param [in] arg +* Generic argument +* @author Viswanathan Murugesan +* @date 10 Oct 2014 +* @version 1.0 +*/ +sint8 nm_drv_init_download_mode(uint32 req_serial_number) +{ + sint8 ret = M2M_SUCCESS; + + ret = nm_bus_iface_init(NULL, req_serial_number); + if (M2M_SUCCESS != ret) { + M2M_ERR("[nmi start]: fail init bus\n"); + goto ERR1; + } + + +#ifdef CONF_WINC_USE_SPI + /* Must do this after global reset to set SPI data packet size. */ + nm_spi_init(); +#endif + + M2M_INFO("Chip ID %lx\n", nmi_get_chipid()); + + /*disable all interrupt in ROM (to disable uart) in 2b0 chip*/ + nm_write_reg(0x20300,0); + +ERR1: + return ret; +} + +sint8 nm_drv_init_hold(uint32 req_serial_number) +{ + sint8 ret = M2M_SUCCESS; + + ret = nm_bus_iface_init(NULL, req_serial_number); + if (M2M_SUCCESS != ret) { + M2M_ERR("[nmi start]: fail init bus\n"); + goto ERR1; + } + +#ifdef BUS_ONLY + return; +#endif + + ret = chip_wake(); + nm_bsp_sleep(10); + if (M2M_SUCCESS != ret) { + M2M_ERR("[nmi start]: fail chip_wakeup\n"); + goto ERR2; + } + /** + Go... + **/ + ret = chip_reset(); + if (M2M_SUCCESS != ret) { + goto ERR2; + } + M2M_INFO("Chip ID %lx\n", nmi_get_chipid()); +#ifdef CONF_WINC_USE_SPI + /* Must do this after global reset to set SPI data packet size. */ + nm_spi_init(); +#endif + /*return power save to default value*/ + chip_idle(); + + return ret; +ERR2: + nm_bus_iface_deinit(); +ERR1: + return ret; +} + +sint8 nm_drv_init_start(void * arg) +{ + sint8 ret = M2M_SUCCESS; + uint8 u8Mode = M2M_WIFI_MODE_NORMAL; + + if(NULL != arg) { + if(M2M_WIFI_MODE_CONFIG == *((uint8 *)arg)) { + u8Mode = M2M_WIFI_MODE_CONFIG; + } else { + /*continue running*/ + } + } else { + /*continue running*/ + } + + ret = cpu_start(); + if (M2M_SUCCESS != ret) { + goto ERR2; + } + ret = wait_for_bootrom(u8Mode); + if (M2M_SUCCESS != ret) { + goto ERR2; + } + + ret = wait_for_firmware_start(u8Mode); + if (M2M_SUCCESS != ret) { + goto ERR2; + } + + if(M2M_WIFI_MODE_CONFIG == u8Mode) { + goto ERR1; + } else { + /*continue running*/ + } + + ret = enable_interrupts(); + if (M2M_SUCCESS != ret) { + M2M_ERR("failed to enable interrupts..\n"); + goto ERR2; + } + + return ret; +ERR2: + nm_bus_iface_deinit(); +#ifdef CONF_WINC_USE_SPI + nm_spi_deinit(); +#endif +ERR1: + return ret; +} + +/* +* @fn nm_drv_init +* @brief Initialize NMC1000 driver +* @return M2M_SUCCESS in case of success and Negative error code in case of failure +* @param [in] arg - Generic argument passed on to nm_drv_init_start +* @author M. Abdelmawla +* @date 15 July 2012 +* @version 1.0 +*/ +sint8 nm_drv_init(void * arg, uint32 req_serial_number) +{ + sint8 ret = M2M_SUCCESS; + + ret = nm_drv_init_hold(req_serial_number); + + if(ret == M2M_SUCCESS) + ret = nm_drv_init_start(arg); + + return ret; +} + +/* +* @fn nm_drv_deinit +* @brief Deinitialize NMC1000 driver +* @author M. Abdelmawla +* @date 17 July 2012 +* @version 1.0 +*/ +sint8 nm_drv_deinit(void * arg) +{ + sint8 ret; + + ret = chip_deinit(); + if (M2M_SUCCESS != ret) { + M2M_ERR("[nmi stop]: chip_deinit fail\n"); + goto ERR1; + } + + ret = nm_bus_iface_deinit(); + if (M2M_SUCCESS != ret) { + M2M_ERR("[nmi stop]: fail init bus\n"); + goto ERR1; + } +#ifdef CONF_WINC_USE_SPI + /* Must do this after global reset to set SPI data packet size. */ + nm_spi_deinit(); +#endif + +ERR1: + return ret; +} + + +/** +* @fn nm_cpu_start(void) +* @brief Start CPU from the WINC module +* @return ZERO in case of success and Negative error code in case of failure +*/ + +sint8 nm_cpu_start(void) +{ + sint8 ret; + + ret = cpu_start(); + return ret; +} \ No newline at end of file diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmdrv.h b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmdrv.h new file mode 100644 index 000000000..089c2227f --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmdrv.h @@ -0,0 +1,147 @@ +/** + * + * \file + * + * \brief This module contains WINC3400 M2M driver APIs declarations. + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _NMDRV_H_ +#define _NMDRV_H_ + +#include "common/include/nm_common.h" + +/** +* @struct tstrM2mRev +* @brief Structure holding firmware version parameters and build date/time +*/ +typedef struct { + uint16 u16FirmwareHifInfo; /* Fw HIF Info */ + uint8 u8FirmwareMajor; /* Version Major Number */ + uint8 u8FirmwareRsvd; /* Reserved */ + uint8 u8FirmwareMinor; /* Version Minor */ + uint8 u8FirmwarePatch; /* Patch Number */ + uint8 BuildDate[sizeof(__DATE__)]; // 12 bytes + uint8 BuildTime[sizeof(__TIME__)]; // 9 bytes +} tstrM2mRev; + +#ifdef __cplusplus + extern "C" { + #endif +/** +* @fn nm_get_hif_info(uint16 *pu16FwHifInfo, uint16 *pu16OtaHifInfo); +* @brief Get Hif info of images in both partitions (Firmware and Ota). +* @param [out] pu16FwHifInfo +* Pointer holding Hif info of image in the active partition. +* @param [out] pu16OtaHifInfo +* Pointer holding Hif info of image in the inactive partition. +* @return ZERO in case of success and Negative error code in case of failure +*/ +sint8 nm_get_hif_info(uint16 *pu16FwHifInfo, uint16 *pu16OtaHifInfo); +/** +* @fn nm_get_firmware_full_info(tstrM2mRev* pstrRev) +* @brief Get Firmware version info +* @param [out] pstrRev +* Pointer holds address of structure @ref tstrM2mRev that contains the version parameters +* of image in the active partition. +* @return ZERO in case of success and Negative error code in case of failure +*/ +sint8 nm_get_firmware_full_info(tstrM2mRev* pstrRev); +/** +* @fn nm_get_ota_firmware_info(tstrM2mRev* pstrRev) +* @brief Get Firmware version info +* @param [out] pstrRev +* Pointer holds address of structure @ref tstrM2mRev that contains the version parameters +* of image in the inactive partition. +* @return ZERO in case of success and Negative error code in case of failure +*/ +sint8 nm_get_ota_firmware_info(tstrM2mRev* pstrRev); +/* +* @fn nm_drv_init +* @brief Initialize NMC1000 driver +* @return ZERO in case of success and Negative error code in case of failure +*/ +sint8 nm_drv_init_download_mode(uint32 req_serial_number); + +/* +* @fn nm_drv_init +* @brief Initialize NMC1000 driver +* @return M2M_SUCCESS in case of success and Negative error code in case of failure +* @param [in] arg - Generic argument passed on to nm_drv_init_start +* @param [in] req_serial_number +* @return ZERO in case of success and Negative error code in case of failure +*/ +sint8 nm_drv_init(void * arg, uint32 req_serial_number); + +/* +* @fn nm_drv_init_hold +* @brief First part of nm_drv_init, up to the point of initializing spi for flash access. +* @see nm_drv_init +* @return M2M_SUCCESS in case of success and Negative error code in case of failure +* @param [in] req_serial_number +* Parameter inherited from nm_drv_init +* @return ZERO in case of success and Negative error code in case of failure +*/ +sint8 nm_drv_init_hold(uint32 req_serial_number); + +/* +* @fn nm_drv_init_start +* @brief Second part of nm_drv_init, continuing from where nm_drv_init_hold left off. +* @see nm_drv_init +* @return M2M_SUCCESS in case of success and Negative error code in case of failure +* @param [in] arg +* Parameter inherited from nm_drv_init +* @return ZERO in case of success and Negative error code in case of failure +*/ +sint8 nm_drv_init_start(void * arg); + +/** +* @fn nm_drv_deinit +* @brief Deinitialize NMC1000 driver +* @author M. Abdelmawla +* @param [in] arg - Generic argument unused. +* @return ZERO in case of success and Negative error code in case of failure +*/ +sint8 nm_drv_deinit(void * arg); + +/** +* @fn nm_cpu_start(void) +* @brief Start CPU from the WINC module +* @return ZERO in case of success and Negative error code in case of failure +*/ + +sint8 nm_cpu_start(void); + +#ifdef __cplusplus + } + #endif + +#endif /*_NMDRV_H_*/ + + diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmflash.c b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmflash.c new file mode 100644 index 000000000..6a2a16ff9 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmflash.c @@ -0,0 +1,878 @@ +/** + * + * \file + * + * \brief WINC Flash Interface. + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + + + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +INCLUDES +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ +#include "driver/include/m2m_flash.h" +#include "driver/source/nmflash.h" +#include "spi_flash/include/spi_flash.h" +#include "nmdrv.h" +//#include "main.h" + +#include "ISConstants.h" +//#include "compiler.h" +#define malloc MALLOC +#define free FREE + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +GLOBALS +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ +static uint32 gu32LocationId = MEM_ID_NONE; +static uint8 *gpu8Location = NULL; + +uint16 gu16LastAccessId = 0; +uint8 gu8Success = 0; +uint8 gu8Changed = 0; +uint8 gu8Init = 0; +uint8 gu8Reset = 0; + + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +FUNCTIONS +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ + +static sint8 winc_flash_compare(uint8 *pu8Buf, uint32 u32Offset, uint32 u32Size) +{ + sint8 ret = M2M_SUCCESS; + uint8 buf[128]; + uint32 offset = 0; + + while (offset < u32Size) + { + uint32 chunk_sz = sizeof(buf); + if (chunk_sz > u32Size - offset) + chunk_sz = u32Size - offset; + ret = spi_flash_read(buf, u32Offset + offset, chunk_sz); + if (ret != M2M_SUCCESS) + break; + ret = m2m_memcmp(buf, pu8Buf + offset, chunk_sz); + if (ret != 0) + break; + offset += chunk_sz; + } + return ret; +} + +sint8 winc_flash_write_verify(uint8 *pu8Buf, uint32 u32Offset, uint32 u32Size) +{ + sint8 ret = M2M_ERR_FAIL; + uint8 count = 20; + + while ((ret != M2M_SUCCESS) && (count-- > 0)) + { + ret = spi_flash_write(pu8Buf, u32Offset, u32Size); + if (ret == M2M_SUCCESS) + ret = winc_flash_compare(pu8Buf, u32Offset, u32Size); + } + return ret; +} +static sint8 set_changed_flag(tstrFlashAccessPersistent *pstrPersistentInfo) +{ + sint8 ret = FLASH_RETURN_OK; + if (pstrPersistentInfo->u8ModeFlags & FLASH_MODE_FLAGS_UNCHANGED) + { + pstrPersistentInfo->u8ModeFlags &= ~FLASH_MODE_FLAGS_UNCHANGED; + if (winc_flash_write_verify((uint8*)pstrPersistentInfo, HOST_CONTROL_FLASH_OFFSET, sizeof(tstrFlashAccessPersistent)) == M2M_SUCCESS) + gu8Changed = 1; + else + ret = FLASH_ERR_WINC_ACCESS; + } + return ret; +} + +static uint8 crc7(uint8 crc, const uint8 *buff, uint16 len) +{ + uint8 reg = crc; + uint16 i; + for(i = 0; i < len; i++) + { + uint16 g; + for(g = 0; g < 8; g++) + { + uint8 inv = (((buff[i] << g) & 0x80) >> 7) ^ ((reg >> 6) & 1); + reg = ((reg << 1) & 0x7f) ^ (9 * inv); + } + } + return reg; +} +static sint8 read_control_sector(tstrOtaControlSec *pstrControlSec, uint32 u32Offset) +{ + sint8 s8Ret = spi_flash_read((uint8*)pstrControlSec, u32Offset, sizeof(tstrOtaControlSec)); + if (s8Ret == M2M_SUCCESS) + { + if (pstrControlSec->u32OtaMagicValue != OTA_MAGIC_VALUE) + s8Ret = M2M_ERR_FAIL; + if (pstrControlSec->u32OtaControlSecCrc != crc7(0x7f, (uint8*)pstrControlSec, sizeof(tstrOtaControlSec) - 4)) + s8Ret = M2M_ERR_FAIL; + } + return s8Ret; +} +static sint8 update_control_sector(tstrOtaControlSec *pstrControlSec) +{ + sint8 ret = M2M_ERR_FAIL; + + ret = spi_flash_erase(M2M_BACKUP_FLASH_OFFSET, M2M_BACKUP_FLASH_SZ); + if (ret == M2M_SUCCESS) + { + pstrControlSec->u32OtaSequenceNumber++; + pstrControlSec->u32OtaControlSecCrc = crc7(0x7f, (uint8*)pstrControlSec, sizeof(tstrOtaControlSec) - 4); + ret = winc_flash_write_verify((uint8*)pstrControlSec, M2M_BACKUP_FLASH_OFFSET, sizeof(tstrOtaControlSec)); + if (ret == M2M_SUCCESS) + { + ret = spi_flash_erase(M2M_CONTROL_FLASH_OFFSET, M2M_CONTROL_FLASH_SZ); + if (ret == M2M_SUCCESS) + { + pstrControlSec->u32OtaSequenceNumber++; + pstrControlSec->u32OtaControlSecCrc = crc7(0x7f, (uint8*)pstrControlSec, sizeof(tstrOtaControlSec) - 4); + ret = winc_flash_write_verify((uint8*)pstrControlSec, M2M_CONTROL_FLASH_OFFSET, sizeof(tstrOtaControlSec)); + } + } + } + return ret; +} +static sint8 access_control_sector(tenuCSOp enuOp, uint32 *param) +{ + static tstrOtaControlSec strControlSec = {0}; + sint8 s8Ret = M2M_SUCCESS; + uint8 bUpdate = false; + + if ((enuOp != CS_INITIALIZE) && (strControlSec.u32OtaMagicValue != OTA_MAGIC_VALUE)) + { + if (param != NULL) + *param = 0; + return M2M_ERR_FAIL; + } + + switch (enuOp) + { + case CS_INITIALIZE: + s8Ret = read_control_sector(&strControlSec, M2M_CONTROL_FLASH_OFFSET); + if (s8Ret != M2M_SUCCESS) + { + s8Ret = read_control_sector(&strControlSec, M2M_BACKUP_FLASH_OFFSET); + if (s8Ret == M2M_SUCCESS) + { + /* + * Reinstate the control sector from backup. + */ + s8Ret = spi_flash_erase(M2M_CONTROL_FLASH_OFFSET, M2M_CONTROL_FLASH_SZ); + if (s8Ret == M2M_SUCCESS) + s8Ret = winc_flash_write_verify((uint8*)&strControlSec, M2M_CONTROL_FLASH_OFFSET, sizeof(tstrOtaControlSec)); + } + } + break; + case CS_INVALIDATE_RB: + // Update trashes the backup sector, so we need to avoid unnecessary updates. + if (strControlSec.u32OtaRollbackImageValidStatus != OTA_STATUS_INVALID) + { + strControlSec.u32OtaRollbackImageValidStatus = OTA_STATUS_INVALID; + bUpdate = true; + } + break; + case CS_VALIDATE_RB: + // Update trashes the backup sector, so we need to avoid unnecessary updates. + if (strControlSec.u32OtaRollbackImageValidStatus != OTA_STATUS_VALID) + { + strControlSec.u32OtaRollbackImageValidStatus = OTA_STATUS_VALID; + bUpdate = true; + } + break; + case CS_VALIDATE_SWITCH: + strControlSec.u32OtaRollbackImageValidStatus = OTA_STATUS_VALID; + // intentional fallthrough. + case CS_SWITCH: + if (strControlSec.u32OtaRollbackImageValidStatus == OTA_STATUS_VALID) + { + uint32 tmp = strControlSec.u32OtaCurrentworkingImagOffset; + strControlSec.u32OtaCurrentworkingImagOffset = strControlSec.u32OtaRollbackImageOffset; + strControlSec.u32OtaRollbackImageOffset = tmp; + bUpdate = true; + } + else + s8Ret = M2M_ERR_FAIL; + break; + case CS_GET_ACTIVE: + if (param == NULL) + s8Ret = M2M_ERR_FAIL; + else + *param = strControlSec.u32OtaCurrentworkingImagOffset; + break; + case CS_GET_INACTIVE: + if (param == NULL) + s8Ret = M2M_ERR_FAIL; + else + *param = strControlSec.u32OtaRollbackImageOffset; + break; + case CS_DEINITIALIZE: + m2m_memset((uint8*)&strControlSec, 0, sizeof(tstrOtaControlSec)); + break; + default: + s8Ret = M2M_ERR_FAIL; + } + if (bUpdate) + { + s8Ret = update_control_sector(&strControlSec); + M2M_INFO("CS update:%d %s\n", enuOp, (s8Ret==M2M_SUCCESS)?"":"Failed"); + } + return s8Ret; +} +static sint8 local_access_ptr(tenuFlashDataFnCtl enuCtl, void *pvStr) +{ + sint8 s8Ret = M2M_ERR_FAIL; + static uint8 *pu8Location = NULL; + static uint8 u8Flags = 0; + + switch (enuCtl) + { + case FLASH_DATA_FN_INITIALIZE: + { + tstrDataAccessInitParams *init_params = (tstrDataAccessInitParams*)pvStr; + u8Flags = init_params->u8Flags; + pu8Location = gpu8Location; + s8Ret = M2M_SUCCESS; + } + break; + case FLASH_DATA_FN_DATA: + if (pu8Location != NULL) + { + tstrDataAccessParams *params = (tstrDataAccessParams*)pvStr; + if (u8Flags & FLASH_FN_FLAGS_WRITE) + m2m_memcpy(pu8Location, params->pu8Buf + params->u32DataOffset, params->u32DataSize); + if (u8Flags & FLASH_FN_FLAGS_READ) + m2m_memcpy(params->pu8Buf + params->u32DataOffset, pu8Location, params->u32DataSize); + pu8Location += params->u32DataSize; + s8Ret = M2M_SUCCESS; + } + break; + case FLASH_DATA_FN_TERMINATE: + case FLASH_DATA_FN_COMPLETE: + u8Flags = 0; + pu8Location = NULL; + s8Ret = M2M_SUCCESS; + break; + } + return s8Ret; +} +static sint8 winc_flash_access(tenuFlashDataFnCtl enuCtl, void *pvStr) +{ + sint8 s8Ret = M2M_ERR_FAIL; + static uint32 u32CurrentAddr = 0; + static uint8 u8Flags = 0; + + switch (enuCtl) + { + case FLASH_DATA_FN_INITIALIZE: + { + tstrDataAccessInitParams *init_params = (tstrDataAccessInitParams*)pvStr; + printf("FA Init: 0x%lx Fg 0x%02x Sz 0x%lx \n", gu32LocationId, init_params->u8Flags, init_params->u32TotalSize); + u8Flags = init_params->u8Flags; + switch (gu32LocationId) + { + case MEM_ID_WINC_FLASH: + u32CurrentAddr = 0; + break; + case MEM_ID_WINC_ACTIVE: + s8Ret = access_control_sector(CS_GET_ACTIVE, &u32CurrentAddr); + break; + case MEM_ID_WINC_INACTIVE: + s8Ret = access_control_sector(CS_GET_INACTIVE, &u32CurrentAddr); + /* If we're about to write to the inactive partition, mark it as invalid. */ + if ((s8Ret == M2M_SUCCESS) && (u8Flags & (FLASH_FN_FLAGS_WRITE | FLASH_FN_FLAGS_ERASE))) + s8Ret = access_control_sector(CS_INVALIDATE_RB, NULL); + break; + case MEM_ID_NONE: + s8Ret = M2M_ERR_FAIL; + break; + default: + u32CurrentAddr = gu32LocationId; + break; + } + if (u8Flags & FLASH_FN_FLAGS_READ_SURROUNDING) + { + init_params->u32AlignmentSize = FLASH_SECTOR_SZ; + init_params->u32StartAlignment = u32CurrentAddr & (FLASH_SECTOR_SZ - 1); + } + s8Ret = M2M_SUCCESS; + } + break; + case FLASH_DATA_FN_DATA: + { + tstrDataAccessParams *params = (tstrDataAccessParams*)pvStr; + if (u8Flags & FLASH_FN_FLAGS_COMPARE_BEFORE) + { + printf("c-"); + // If contents match already, return success + s8Ret = winc_flash_compare(params->pu8Buf + params->u32DataOffset, u32CurrentAddr, params->u32DataSize); + if (s8Ret == M2M_SUCCESS) + goto END; + } + if (u8Flags & FLASH_FN_FLAGS_READ_SURROUNDING) + { + uint32 prefill_sz = params->u32DataOffset; + uint32 postfill_sz = params->u32BufSize - (params->u32DataOffset + params->u32DataSize); + if (prefill_sz > 0) + { + printf("r-"); + s8Ret = spi_flash_read(params->pu8Buf, u32CurrentAddr - prefill_sz, prefill_sz); + if (s8Ret != M2M_SUCCESS) + goto END; + } + if (postfill_sz > 0) + { + printf("-r"); + s8Ret = spi_flash_read(params->pu8Buf + params->u32BufSize - postfill_sz, u32CurrentAddr + params->u32DataSize, postfill_sz); + if (s8Ret != M2M_SUCCESS) + goto END; + } + } + if (u8Flags & FLASH_FN_FLAGS_BACKUP) + { + if (params->u32BufSize > params->u32DataSize) + { + printf("b"); + s8Ret = winc_flash_write_verify(params->pu8Buf, M2M_BACKUP_FLASH_OFFSET, params->u32BufSize); + if (s8Ret == M2M_SUCCESS) + s8Ret = prepare_backup(u32CurrentAddr - params->u32DataOffset); + if (s8Ret != M2M_SUCCESS) + goto END; + } + } + if (u8Flags & FLASH_FN_FLAGS_ERASE) + { + printf("e"); + s8Ret = spi_flash_erase(u32CurrentAddr, params->u32DataSize); + if (s8Ret != M2M_SUCCESS) + goto END; + } + if (u8Flags & FLASH_FN_FLAGS_WRITE) + { + printf("W"); + if (u8Flags & FLASH_FN_FLAGS_READ_SURROUNDING) + s8Ret = spi_flash_write(params->pu8Buf, u32CurrentAddr - params->u32DataOffset, params->u32BufSize); + else + s8Ret = spi_flash_write(params->pu8Buf + params->u32DataOffset, u32CurrentAddr, params->u32DataSize); + if (s8Ret != M2M_SUCCESS) + goto END; + } + if (u8Flags & FLASH_FN_FLAGS_COMPARE_AFTER) + { + printf("-c"); + // If contents do not match, return failure + if (u8Flags & FLASH_FN_FLAGS_READ_SURROUNDING) + s8Ret = winc_flash_compare(params->pu8Buf, u32CurrentAddr - params->u32DataOffset, params->u32BufSize); + else + s8Ret = winc_flash_compare(params->pu8Buf + params->u32DataOffset, u32CurrentAddr, params->u32DataSize); + if (s8Ret != M2M_SUCCESS) + goto END; + } + if (u8Flags & FLASH_FN_FLAGS_READ) + { + printf("R"); + s8Ret = spi_flash_read(params->pu8Buf + params->u32DataOffset, u32CurrentAddr, params->u32DataSize); + if (s8Ret != M2M_SUCCESS) + goto END; + } +END: + u32CurrentAddr += params->u32DataSize; + } + break; + case FLASH_DATA_FN_TERMINATE: + case FLASH_DATA_FN_COMPLETE: + printf(" FA End 0x%lx\n", u32CurrentAddr); + u8Flags = 0; + u32CurrentAddr = 0; + s8Ret = M2M_SUCCESS; + break; + } + return s8Ret; +} + +void set_internal_info_ptr(tpfDataAccessFn *ppfFn, uint8 *pu8Ptr) +{ + if (ppfFn != NULL) + *ppfFn = local_access_ptr; + gpu8Location = pu8Ptr; +} +void set_internal_info(tpfDataAccessFn *ppfFn, uint32 u32LocationId) +{ + if (ppfFn != NULL) + *ppfFn = winc_flash_access; + gu32LocationId = u32LocationId; +} +uint8 is_internal_info(tpfDataAccessFn pfFn) +{ + if (pfFn == winc_flash_access) + return true; + return false; +} +sint8 recover_backup(void) +{ + sint8 ret = FLASH_RETURN_OK; + uint32 u32BackupAddr = FLASH_BACKUP_STORE_OFFSET; + tstrBackup strBackup; + + while (u32BackupAddr < FLASH_BACKUP_STORE_OFFSET + FLASH_BACKUP_STORE_SZ) + { + sint8 status = spi_flash_read((uint8*)&strBackup, u32BackupAddr, sizeof(tstrBackup)); + if ((status == M2M_SUCCESS) && (strBackup.enuTransferStatus == BACKUP_STATUS_ACTIVE)) + { + uint8 *pu8Buff = malloc(strBackup.u32Size); + if (pu8Buff == NULL) + { + ret = FLASH_ERR_INTERNAL; + goto ERR; + } + status = spi_flash_read(pu8Buff, strBackup.u32SourceAddr, strBackup.u32Size); + if (status == M2M_SUCCESS) + { + status = spi_flash_erase(strBackup.u32DestinationAddr, strBackup.u32Size); + if (status == M2M_SUCCESS) + { + status = winc_flash_write_verify(pu8Buff, strBackup.u32DestinationAddr, strBackup.u32Size); + if (status == M2M_SUCCESS) + { + strBackup.enuTransferStatus = BACKUP_STATUS_DONE; + status = winc_flash_write_verify((uint8*)&strBackup.enuTransferStatus, u32BackupAddr, FLASH_BACKUP_STA_SZ); + } + } + } + free(pu8Buff); + } + if (status != M2M_SUCCESS) + { + ret = FLASH_ERR_WINC_ACCESS; + goto ERR; + } + u32BackupAddr += sizeof(tstrBackup); + } +ERR: + return ret; +} +sint8 prepare_backup(uint32 u32Target) +{ + sint8 s8Ret = M2M_ERR_FAIL; + uint32 u32BackupAddr = FLASH_BACKUP_STORE_OFFSET; + tenuBackupStatus enuStatus = BACKUP_STATUS_EMPTY; + + s8Ret = spi_flash_read((uint8*)&enuStatus, u32BackupAddr, sizeof(enuStatus)); + if ((s8Ret != M2M_SUCCESS) || (enuStatus != BACKUP_STATUS_EMPTY)) + { + u32BackupAddr += sizeof(tstrBackup); + s8Ret = spi_flash_read((uint8*)&enuStatus, u32BackupAddr, sizeof(enuStatus)); + if ((s8Ret == M2M_SUCCESS) && (enuStatus != BACKUP_STATUS_EMPTY)) + s8Ret = M2M_ERR_FAIL; + } + if (s8Ret == M2M_SUCCESS) + { + tstrBackup strBackup = {BACKUP_STATUS_NOT_ACTIVE, u32Target, M2M_BACKUP_FLASH_OFFSET, M2M_BACKUP_FLASH_SZ}; + s8Ret = winc_flash_write_verify((uint8*)&strBackup.enuTransferStatus, u32BackupAddr, FLASH_BACKUP_STA_SZ); + if (s8Ret == M2M_SUCCESS) + { + s8Ret = winc_flash_write_verify((uint8*)&strBackup, u32BackupAddr, sizeof(strBackup)); + if (s8Ret == M2M_SUCCESS) + { + strBackup.enuTransferStatus = BACKUP_STATUS_ACTIVE; + s8Ret = winc_flash_write_verify((uint8*)&strBackup.enuTransferStatus, u32BackupAddr, FLASH_BACKUP_STA_SZ); + } + } + } + return s8Ret; +} +sint8 image_get_target(uint8 *pu8Target) +{ + sint8 s8Ret = M2M_ERR_FAIL; + uint32 u32OffsetActive = 0; + uint32 u32OffsetInactive = 0; + + s8Ret = access_control_sector(CS_INITIALIZE, NULL); + if (s8Ret == M2M_SUCCESS) + { + s8Ret = access_control_sector(CS_GET_ACTIVE, &u32OffsetActive); + if (s8Ret == M2M_SUCCESS) + { + s8Ret = access_control_sector(CS_GET_INACTIVE, &u32OffsetInactive); + if (s8Ret == M2M_SUCCESS) + *pu8Target = (u32OffsetInactive > u32OffsetActive) ? 1 : 0; + } + access_control_sector(CS_DEINITIALIZE, NULL); + } + return s8Ret; +} +sint8 rootcert_get_size(tstrRootCertEntryHeader *pstrHdr, uint16 *pu16Size) +{ + sint8 s8Ret = M2M_ERR_FAIL; + if ((pstrHdr == NULL) || (pu16Size == NULL)) + goto ERR; + + /* Set default size out to maximum. */ + *pu16Size = 0xFFFF; + switch (pstrHdr->strPubKey.u32PubKeyType) + { + case ROOT_CERT_PUBKEY_RSA: + if (pstrHdr->strPubKey.strRsaKeyInfo.u16NSz > M2M_TLS_ROOTCER_FLASH_SZ) + goto ERR; + if (pstrHdr->strPubKey.strRsaKeyInfo.u16ESz > M2M_TLS_ROOTCER_FLASH_SZ) + goto ERR; + *pu16Size = sizeof(tstrRootCertEntryHeader) + ((pstrHdr->strPubKey.strRsaKeyInfo.u16NSz + 0x3) & ~0x3) + ((pstrHdr->strPubKey.strRsaKeyInfo.u16ESz + 0x3) & ~0x3); + s8Ret = M2M_SUCCESS; + break; + case ROOT_CERT_PUBKEY_ECDSA: + if (pstrHdr->strPubKey.strEcsdaKeyInfo.u16KeySz > M2M_TLS_ROOTCER_FLASH_SZ) + goto ERR; + *pu16Size = sizeof(tstrRootCertEntryHeader) + ((pstrHdr->strPubKey.strEcsdaKeyInfo.u16KeySz + 0x3) & ~0x3) * 2; + s8Ret = M2M_SUCCESS; + break; + case 0xFFFFFFFF: + // Invalid. May indicate end of list. Fail with size set to 0. + *pu16Size = 0; + break; + default: + // Corrupt header. + break; + } +ERR: + return s8Ret; +} +sint8 rootcert_access(tenuFlashAccessItemMode enuMode, tstrRootCertEntryHeader *pstrReferenceHdr, uint16 *pu16EntrySize, uint8 *pu8Buff, uint32 *pu32Offset) +{ + sint8 ret = FLASH_RETURN_OK; + sint8 status = M2M_SUCCESS; + uint8 au8RootCertSig[] = M2M_TLS_ROOTCER_FLASH_SIG; + tstrRootCertEntryHeader strEntryHeader; + /* Previous version used 0-identifiers to indicate removed entries. Use last 20 bytes of pu8Buff to help us check for them. */ + uint8 *pu8Zero = pu8Buff + M2M_TLS_ROOTCER_FLASH_SZ - sizeof(pstrReferenceHdr->au8SHA1NameHash); + uint32 u32StoreOffset = 0; + uint32 u32Entries = 0; + + m2m_memset(pu8Zero, 0, sizeof(pstrReferenceHdr->au8SHA1NameHash)); + /* Use pu8SectionBuffer to read signature. */ + status = spi_flash_read(pu8Buff, M2M_TLS_ROOTCER_FLASH_OFFSET, sizeof(au8RootCertSig)); + if ((status != M2M_SUCCESS) || m2m_memcmp(pu8Buff, au8RootCertSig, sizeof(au8RootCertSig))) + { + /* + * Root certificate section is not initialized. We could try to initialize it + * here, but for now just fail. + */ + ret = FLASH_ERR_WINC_ACCESS; + goto ERR; + } + + /* + * By default assume we'll get to the end of the flash store without finding what we need + * (matching entry or space to add new entry). If we break while loop before reaching end of + * store then we'll change ret accordingly. */ + if (enuMode == FLASH_ITEM_ADD) + ret = FLASH_ERR_SIZE; + else + ret = FLASH_ERR_WINC_CONFLICT; + + u32StoreOffset = *pu32Offset = sizeof(tstrRootCertFlashHeader); + while (u32StoreOffset + sizeof(tstrRootCertEntryHeader) < M2M_TLS_ROOTCER_FLASH_SZ) + { + uint16 u16EntrySize = 0; + status = spi_flash_read((uint8*)&strEntryHeader, M2M_TLS_ROOTCER_FLASH_OFFSET + u32StoreOffset, sizeof(tstrRootCertEntryHeader)); + if (status != M2M_SUCCESS) + { + ret = FLASH_ERR_WINC_ACCESS; + break; + } + status = rootcert_get_size(&strEntryHeader, &u16EntrySize); + if (status != M2M_SUCCESS) + { + // Found the end of the list. We are done. If we are adding an entry, check the space here. + if ((enuMode == FLASH_ITEM_ADD) && ((*pu32Offset + *pu16EntrySize) <= M2M_TLS_ROOTCER_FLASH_SZ)) + { + u32Entries++; + ret = FLASH_RETURN_OK; + } + break; + } + + // If we are here we know that u32EntrySize is sane. + if (m2m_memcmp(pu8Zero, (uint8*)pstrReferenceHdr, sizeof(strEntryHeader.au8SHA1NameHash))) + { + // Entry is not empty. + status = spi_flash_read(pu8Buff + *pu32Offset, M2M_TLS_ROOTCER_FLASH_OFFSET + u32StoreOffset, u16EntrySize); + if (status != M2M_SUCCESS) + { + ret = FLASH_ERR_WINC_ACCESS; + break; + } + if (enuMode == FLASH_ITEM_READIDX) + { + if (u32Entries == *(uint32*)pstrReferenceHdr) + { + // Found entry. pu16EntrySize is used to output size. + *pu16EntrySize = u16EntrySize; + ret = FLASH_RETURN_OK; + break; + } + } + else if (!m2m_memcmp(strEntryHeader.au8SHA1NameHash, (uint8*)pstrReferenceHdr, sizeof(strEntryHeader.au8SHA1NameHash))) + { + if (enuMode == FLASH_ITEM_ADD) + { + // Found a match. Cannot add. + ret = FLASH_ERR_WINC_CONFLICT; + break; + } + if (enuMode == FLASH_ITEM_READ) + { + // Found a match. pu16EntrySize is used to output size. + *pu16EntrySize = u16EntrySize; + ret = FLASH_RETURN_OK; + break; + } + if (enuMode == FLASH_ITEM_REMOVE) + { + // Found a match. Continue, to complete entry count. + ret = FLASH_RETURN_OK; + // Cancel out increment of u32BuffOffset. + *pu32Offset -= u16EntrySize; + } + } + *pu32Offset += u16EntrySize; + u32Entries++; + } + u32StoreOffset += u16EntrySize; + } + if (ret == FLASH_RETURN_OK) + ((tstrRootCertFlashHeader*)(void*)pu8Buff)->u32nCerts = u32Entries; +ERR: + return ret; +} + +sint8 transfer_run(tstrFlashAccess *pstrFlashAccess) +{ + /* + * Errors before start of first transfer will be reported as parameter errors. + * This means the information is insufficient to allow us to begin. + */ + sint8 ret = FLASH_RETURN_OK; + sint8 status = M2M_ERR_FAIL; + + tpfDataAccessFn pfWriteFn = pstrFlashAccess->pfDestinationFn; + tpfDataAccessFn pfReadFn = pstrFlashAccess->pfSourceFn; + tstrDataAccessInitParams read_init_params = {pstrFlashAccess->u32Size, FLASH_FN_FLAGS_READ, 0, 0}; + tstrDataAccessInitParams write_init_params = {pstrFlashAccess->u32Size, FLASH_FN_FLAGS_WRITE, 0, 0}; + uint32 u32BytesTransferred = 0; + uint32 u32BytesRemaining = pstrFlashAccess->u32Size; + uint8 *pu8Buff = NULL; + + if (pstrFlashAccess->strPersistentInfo.u8AccessFlags & FLASH_ACCESS_OPTION_COMPARE_BEFORE) + write_init_params.u8Flags |= FLASH_FN_FLAGS_COMPARE_BEFORE; + if (pstrFlashAccess->strPersistentInfo.u8AccessFlags & FLASH_ACCESS_OPTION_ERASE_FIRST) + { + write_init_params.u8Flags |= FLASH_FN_FLAGS_ERASE; + if (pstrFlashAccess->strPersistentInfo.u8AccessFlags & FLASH_ACCESS_OPTION_KEEP_SURROUNDING) + { + write_init_params.u8Flags |= FLASH_FN_FLAGS_READ_SURROUNDING; + if (pstrFlashAccess->strPersistentInfo.u8AccessFlags & FLASH_ACCESS_OPTION_USE_BACKUP) + write_init_params.u8Flags |= FLASH_FN_FLAGS_BACKUP; + } + } + if (pstrFlashAccess->strPersistentInfo.u8AccessFlags & FLASH_ACCESS_OPTION_COMPARE_AFTER) + write_init_params.u8Flags |= FLASH_FN_FLAGS_COMPARE_AFTER; + + if (pstrFlashAccess->strPersistentInfo.u8ModeFlags & FLASH_MODE_FLAGS_DATA_IN_BACKUP) + { + if (prepare_backup(gu32LocationId) != M2M_SUCCESS) + { + ret = FLASH_ERR_WINC_ACCESS; + goto ERR; + } + set_changed_flag(&pstrFlashAccess->strPersistentInfo); + ret = recover_backup(); + if (ret < 0) + goto ERR; + } + /* + * Initialize control sector. Even if we don't need to access it, this at + * least ensures that the control sector is not relying on the flash backup sector. + */ + status = access_control_sector(CS_INITIALIZE, NULL); + if (status != M2M_SUCCESS && (pstrFlashAccess->strPersistentInfo.u8ModeFlags & FLASH_MODE_FLAGS_CS)) + { + ret = FLASH_ERR_WINC_ACCESS; + goto ERR; + } + + if (pfReadFn != NULL) + { + /* Prepare for read. */ + + status = pfReadFn(FLASH_DATA_FN_INITIALIZE, &read_init_params); + if (status != M2M_SUCCESS) + { + if (is_internal_info(pfReadFn)) + ret = FLASH_ERR_WINC_ACCESS; + else + ret = FLASH_ERR_LOCAL_ACCESS; + pfReadFn(FLASH_DATA_FN_TERMINATE, NULL); + goto ERR; + } + } + if (pfWriteFn != NULL) + { + /* Prepare for write. */ + status = pfWriteFn(FLASH_DATA_FN_INITIALIZE, &write_init_params); + if (status != M2M_SUCCESS) + { + if (is_internal_info(pfWriteFn)) + ret = FLASH_ERR_WINC_ACCESS; + else + ret = FLASH_ERR_LOCAL_ACCESS; + goto TERMINATE; + } + } + if (u32BytesRemaining > 0) + { + if (u32BytesRemaining > FLASH_SECTOR_SIZE) + pu8Buff = malloc(FLASH_SECTOR_SIZE); + else if (write_init_params.u32AlignmentSize > 1) + pu8Buff = malloc(write_init_params.u32AlignmentSize); + else + pu8Buff = malloc(u32BytesRemaining); + if (pu8Buff == NULL) + { + ret = FLASH_ERR_INTERNAL; + goto TERMINATE; + } + } + + while (u32BytesRemaining > 0) + { + tstrDataAccessParams params = {pu8Buff, FLASH_SECTOR_SIZE, 0, FLASH_SECTOR_SIZE}; + + if (u32BytesTransferred > 0) + write_init_params.u32StartAlignment = 0; + if (write_init_params.u32AlignmentSize > 1) + { + params.u32DataOffset = write_init_params.u32StartAlignment & (write_init_params.u32AlignmentSize-1); + params.u32DataSize = write_init_params.u32AlignmentSize - params.u32DataOffset; + } + + if (params.u32DataSize > u32BytesRemaining) + params.u32DataSize = u32BytesRemaining; + + /* Read. */ + if (pfReadFn != NULL) + { + status = pfReadFn(FLASH_DATA_FN_DATA, ¶ms); + if (status != M2M_SUCCESS) + { + if (is_internal_info(pfReadFn)) + ret = FLASH_ERR_WINC_ACCESS; + else + ret = FLASH_ERR_LOCAL_ACCESS; + break; + } + } + + /* Write. */ + if (pfWriteFn != NULL) + { + if (is_internal_info(pfWriteFn)) + { + ret = set_changed_flag(&pstrFlashAccess->strPersistentInfo); + if (ret < 0) + break; + } + status = pfWriteFn(FLASH_DATA_FN_DATA, ¶ms); + if (status != M2M_SUCCESS) + { + if (is_internal_info(pfWriteFn)) + ret = FLASH_ERR_WINC_ACCESS; + else + ret = FLASH_ERR_LOCAL_ACCESS; + break; + } + } + + u32BytesTransferred += params.u32DataSize; + u32BytesRemaining -= params.u32DataSize; + } + + if (u32BytesRemaining > 0) + { +TERMINATE: + if (pfReadFn != NULL) + pfReadFn(FLASH_DATA_FN_TERMINATE, NULL); + if (pfWriteFn != NULL) + pfWriteFn(FLASH_DATA_FN_TERMINATE, NULL); + goto ERR; + } + else + { + if (pfReadFn != NULL) + pfReadFn(FLASH_DATA_FN_COMPLETE, NULL); + if (pfWriteFn != NULL) + pfWriteFn(FLASH_DATA_FN_COMPLETE, NULL); + } + + if (pstrFlashAccess->strPersistentInfo.u8ModeFlags & (FLASH_MODE_FLAGS_CS_VALIDATE_IMAGE | FLASH_MODE_FLAGS_CS_SWITCH)) + { + tenuCSOp enuOp; + ret = set_changed_flag(&pstrFlashAccess->strPersistentInfo); + if (ret < 0) + goto ERR; + if (pstrFlashAccess->strPersistentInfo.u8ModeFlags & FLASH_MODE_FLAGS_CS_VALIDATE_IMAGE) + { + if (pstrFlashAccess->strPersistentInfo.u8ModeFlags & FLASH_MODE_FLAGS_CS_SWITCH) + enuOp = CS_VALIDATE_SWITCH; + else + enuOp = CS_VALIDATE_RB; + } + else + enuOp = CS_SWITCH; + status = access_control_sector(enuOp, NULL); + if (status != M2M_SUCCESS) + { + ret = FLASH_ERR_WINC_ACCESS; + goto ERR; + } + } + + pstrFlashAccess->strPersistentInfo.enuTransferStatus = FLASH_STATUS_DONE; + status = winc_flash_write_verify((uint8*)pstrFlashAccess, HOST_CONTROL_FLASH_OFFSET, sizeof(tstrFlashAccessPersistent)); + gu8Success = 1; +ERR: + if (pu8Buff != NULL) + free(pu8Buff); + access_control_sector(CS_DEINITIALIZE, NULL); + return ret; +} diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmflash.h b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmflash.h new file mode 100644 index 000000000..8dceaf904 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmflash.h @@ -0,0 +1,284 @@ +/** + * + * \file + * + * \brief WINC Flash Interface. + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + + +#ifndef __NM_FLASH_H__ +#define __NM_FLASH_H__ + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +INCLUDES +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ +#include "common/include/nm_common.h" +#include "driver/include/m2m_types.h" + +#define FLASH_RETURN_OK 0 +#define FLASH_SECTOR_SIZE FLASH_SECTOR_SZ +#define FLASH_SIGNATURE HOST_CONTROL_FLASH_SIG +#define BACKUP_SIGNATURE 0x424b5550 + +#define FLASH_MODE_FLAGS_CS NBIT0 +#define FLASH_MODE_FLAGS_CS_SWITCH NBIT1 +#define FLASH_MODE_FLAGS_CS_SWITCH_TARGET NBIT2 +#define FLASH_MODE_FLAGS_CS_VALIDATE_IMAGE NBIT3 +#define FLASH_MODE_FLAGS_UNCHANGED NBIT4 +#define FLASH_MODE_FLAGS_DATA_IN_BACKUP NBIT5 + +/*! Bit 0 of u8Flags parameter of @ref tpfDataAccessFn.\n + * Compare buffer against existing data, to avoid unnecessary operation. */ +#define FLASH_FN_FLAGS_COMPARE_BEFORE NBIT0 +/*! Bit 1 of u8Flags parameter of @ref tpfDataAccessFn.\n + * Fill uninitialized portion of buffer with existing data to avoid losing it in subsequent erase. + * Typically not set unless @ref FLASH_FN_FLAGS_ERASE is set. */ +#define FLASH_FN_FLAGS_READ_SURROUNDING NBIT1 +/*! Bit 2 of u8Flags parameter of @ref tpfDataAccessFn.\n + * Save buffer to a backup persistent location in case of power loss after subsequent erase. + * A (persistent) record of the backup status must also be kept. + * Typically not set unless @ref FLASH_FN_FLAGS_READ_SURROUNDING and @ref FLASH_FN_FLAGS_ERASE are both set. */ +#define FLASH_FN_FLAGS_BACKUP NBIT2 +/*! Bit 3 of u8Flags parameter of @ref tpfDataAccessFn.\n + * Erase existing data before writing. */ +#define FLASH_FN_FLAGS_ERASE NBIT3 +/*! Bit 4 of u8Flags parameter of @ref tpfDataAccessFn.\n + * Write buffer. */ +#define FLASH_FN_FLAGS_WRITE NBIT4 +/*! Bit 5 of u8Flags parameter of @ref tpfDataAccessFn.\n + * Compare buffer against written data, to provide verification. + * Typically not set unless @ref FLASH_FN_FLAGS_WRITE is set. */ +#define FLASH_FN_FLAGS_COMPARE_AFTER NBIT5 +/*! Bit 6 of u8Flags parameter of @ref tpfDataAccessFn.\n + * Read data to buffer. Typically this would be the only flag set, meaning read the existing data. + * However, if other flags are set, the read should be performed at the end. */ +#define FLASH_FN_FLAGS_READ NBIT6 + +/*! Bit 0 of u8AccessOptions parameter of various function APIs.\n + * Request to erase existing data before writing.\n + * Only applies when module is providing data to the MCU application.\n + * If set, @ref FLASH_FN_FLAGS_ERASE will be set in subsequent call to function of type + * @ref tpfDataAccessFn. */ +#define FLASH_ACCESS_OPTION_ERASE_FIRST NBIT0 +/*! Bit 1 of u8AccessOptions parameter of various function APIs.\n + * When set with @ref FLASH_ACCESS_OPTION_ERASE_FIRST, this is a request to do + * read-modify-erase-write (eg if MCU application is storing received data in flash).\n + * Only applies when module is providing data to the MCU application.\n + * If set, @ref FLASH_FN_FLAGS_READ_SURROUNDING may be set in subsequent call to function of type + * @ref tpfDataAccessFn. */ +#define FLASH_ACCESS_OPTION_KEEP_SURROUNDING NBIT1 +/*! Bit 2 of u8AccessOptions parameter of various function APIs.\n + * When set with @ref FLASH_ACCESS_OPTION_ERASE_FIRST and @ref FLASH_ACCESS_OPTION_KEEP_SURROUNDING, + * this is a request to keep a persistent backup of modified contents during read-modify-erase-write.\n + * Only applies when module is providing data to the MCU application.\n + * If set, @ref FLASH_FN_FLAGS_BACKUP may be set in subsequent call to function of type + * @ref tpfDataAccessFn. */ +#define FLASH_ACCESS_OPTION_USE_BACKUP NBIT2 +/*! Bit 3 of u8AccessOptions parameter of various function APIs.\n + * Request to compare new data against existing data before erasing/writing, to avoid unnecessary operations.\n + * Applies to data transfer in either direction.\n + * If set, @ref FLASH_FN_FLAGS_COMPARE_BEFORE will be set in subsequent call to function of type + * @ref tpfDataAccessFn. */ +#define FLASH_ACCESS_OPTION_COMPARE_BEFORE NBIT3 +/*! Bit 4 of u8AccessOptions parameter of various function APIs.\n + * Request for byte-wise verification of write.\n + * Applies to data transfer in either direction.\n + * If set, @ref FLASH_FN_FLAGS_COMPARE_AFTER will be set in subsequent call to function of type + * @ref tpfDataAccessFn. */ +#define FLASH_ACCESS_OPTION_COMPARE_AFTER NBIT4 +/*! When modifying WINC flash contents, the module determines most options internally. Only two + * options are taken from the u8AccessOptions parameter.\n + * When providing data to the MCU application, the module takes all options from the + * u8AccessOptions parameter. */ +#define FLASH_ACCESS_WINC_MASK (FLASH_ACCESS_OPTION_COMPARE_BEFORE | FLASH_ACCESS_OPTION_COMPARE_AFTER) + + +typedef enum { + CS_INITIALIZE, + CS_INVALIDATE_RB, + CS_VALIDATE_RB, + CS_SWITCH, + CS_VALIDATE_SWITCH, + CS_GET_ACTIVE, + CS_GET_INACTIVE, + CS_DEINITIALIZE +}tenuCSOp; + +typedef enum { + /* + * Status values arranged so that status can be updated without any erase operation. + */ + FLASH_STATUS_EMPTY = 0xFFFFFFFF, + FLASH_STATUS_NOT_ACTIVE = 0xFFFFFF00, + FLASH_STATUS_ACTIVE = 0xFFFF0000, + FLASH_STATUS_DONE = 0xFF000000 +}tenuFlashAccessStatus; + +typedef enum { + /* + * Status values arranged so that status can be updated without any erase operation. + */ + BACKUP_STATUS_EMPTY = 0xFFFFFFFF, + BACKUP_STATUS_NOT_ACTIVE = BACKUP_SIGNATURE | 0xFFFFFF00, + BACKUP_STATUS_ACTIVE = BACKUP_SIGNATURE, + BACKUP_STATUS_DONE = 0x00000000 +}tenuBackupStatus; + +typedef enum { + /* + * Special location ID values. If top bit is not set, the location ID is interpreted as flash address. + */ + MEM_ID_WINC_FLASH = 0x80000000, + MEM_ID_WINC_ACTIVE, + MEM_ID_WINC_INACTIVE, + MEM_ID_NONE = 0xFFFFFFFF +}tenuMemId; + +/*! +@enum tenuFlashAccessItemMode + +@brief Transfer modes available for accessing items in WINC flash stores such as TLS root + certificate store. +@see m2m_flash_rootcert_access + */ +typedef enum { + /*! Add an item to the relevant WINC flash store. */ + FLASH_ITEM_ADD, + /*! Remove an item from the relevant WINC flash store. */ + FLASH_ITEM_REMOVE, + /*! Read an item from the relevant WINC flash store, using an identifier. */ + FLASH_ITEM_READ, + /*! Read an item from the relevant WINC flash store, using an index. */ + FLASH_ITEM_READIDX +}tenuFlashAccessItemMode; + + +typedef struct { + uint32 u32Signature; + tenuFlashAccessStatus enuTransferStatus; + uint16 u16AppId; + uint8 u8AccessFlags; // These correspond bitwise to application access options. + uint8 u8ModeFlags; // These are set internally, with reference to application mode options. +}tstrFlashAccessPersistent; +#define FLASH_SIG_SZ (sizeof(uint32)) +#define FLASH_STA_SZ (sizeof(tenuFlashAccessStatus)) +#define FLASH_SIG_STA_SZ (FLASH_SIG_SZ+FLASH_STA_SZ) + +typedef struct { + tstrFlashAccessPersistent strPersistentInfo; + tpfDataAccessFn pfDestinationFn; + tpfDataAccessFn pfSourceFn; + uint32 u32Size; +}tstrFlashAccess; + +typedef struct { + tenuBackupStatus enuTransferStatus; + uint32 u32DestinationAddr; + uint32 u32SourceAddr; + uint32 u32Size; +}tstrBackup; +#define FLASH_BACKUP_STA_SZ sizeof(tenuBackupStatus) +#define FLASH_BACKUP_STORE_SZ (2*sizeof(tstrBackup)) +#define FLASH_BACKUP_STORE_OFFSET (HOST_CONTROL_FLASH_OFFSET + HOST_CONTROL_FLASH_SZ - FLASH_BACKUP_STORE_SZ) + +/*! +@struct \ + tstrDataAccessInitParams +@brief + This structure contains parameters for initializing a local data access (read, erase or write). + +@see tpfDataAccessFn. +@see FLASH_FN_FLAGS_COMPARE_BEFORE +@see FLASH_FN_FLAGS_READ_SURROUNDING +@see FLASH_FN_FLAGS_BACKUP +@see FLASH_FN_FLAGS_ERASE +@see FLASH_FN_FLAGS_WRITE +@see FLASH_FN_FLAGS_COMPARE_AFTER +@see FLASH_FN_FLAGS_READ + */ +typedef struct { + /*! Total size of data to be accessed in data location. \n + * This field is set by the module in a call to @ref tpfDataAccessFn. */ + uint32 u32TotalSize; + /*! Flags indicating type of data access. \n + * This field is set by the module in a call to @ref tpfDataAccessFn. */ + uint8 u8Flags; + /*! Block size, to assist with alignment. \n + * This field can be set by the local memory access function @ref tpfDataAccessFn. Defaults to 0 if not set. + * Recommended values are:\n + * - 4096 if accessing flash memory with erase block size <= 4096.\n + * - 0 if accessing normal memory. */ + uint32 u32AlignmentSize; + /*! Offset of access start address, relative to u32AlignmentSize. \n + * This field can be set by the local memory access function @ref tpfDataAccessFn. The field is ignored if u32AlignmentSize < 2. */ + uint32 u32StartAlignment; +}tstrDataAccessInitParams; + +/*! +@struct \ + tstrDataAccessParams +@brief + This structure contains data for local data access (read, erase or write). +@see tpfDataAccessFn. + */ +typedef struct { + /*! Buffer to be written to or read from. */ + uint8 *pu8Buf; + /*! Total size of the buffer. */ + uint32 u32BufSize; + /* Offset of data within the buffer. */ + uint32 u32DataOffset; + /* Size of data to be written or read. */ + uint32 u32DataSize; +}tstrDataAccessParams; + +extern uint16 gu16LastAccessId; +extern uint8 gu8Success; +extern uint8 gu8Changed; +extern uint8 gu8Init; +extern uint8 gu8Reset; + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +FUNCTION PROTOTYPES +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ + +sint8 winc_flash_write_verify(uint8 *pu8Buf, uint32 u32Offset, uint32 u32Size); +void set_internal_info(tpfDataAccessFn *ppfFn, uint32 u32LocationId); +void set_internal_info_ptr(tpfDataAccessFn *ppfFn, uint8 *pu8Ptr); +uint8 is_internal_info(tpfDataAccessFn pfFn); +sint8 recover_backup(void); +sint8 prepare_backup(uint32 u32Target); +sint8 image_get_target(uint8 *pu8Target); +sint8 rootcert_get_size(tstrRootCertEntryHeader *pstrHdr, uint16 *pu16Size); +sint8 rootcert_access(tenuFlashAccessItemMode enuMode, tstrRootCertEntryHeader *pstrReferenceHdr, uint16 *pu16EntrySize, uint8 *pu8Buff, uint32 *pu32Offset); +sint8 transfer_run(tstrFlashAccess *pstrFlashAccess); + + +#endif /* __NM_FLASH_H__ */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmi2c.c b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmi2c.c new file mode 100644 index 000000000..dcde7ae76 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmi2c.c @@ -0,0 +1,262 @@ +/** + * + * \file + * + * \brief This module contains WINC3400 I2C protocol bus APIs implementation. + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "common/include/nm_common.h" + +#ifdef CONF_WINC_USE_I2C + +#include "nmi2c.h" +#include "bus_wrapper/include/nm_bus_wrapper.h" + + +/* +* @fn nm_i2c_read_reg_with_ret +* @brief Read register with error code return +* @param [in] u32Addr +* Register address +* @param [out] pu32RetVal +* Pointer to u32 variable used to return the read value +* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure +* @author M. Abdelmawla +* @date 11 July 2012 +* @version 1.0 +*/ + sint8 nm_i2c_read_reg_with_ret(uint32 u32Addr, uint32* pu32RetVal) +{ + uint8 b[6]; + uint8 rsz; + tstrNmI2cDefault strI2c; + sint8 s8Ret = M2M_SUCCESS; + + if(u32Addr < 0xff) { /* clockless i2c */ + b[0] = 0x09; + b[1] = (uint8)(u32Addr); + rsz = 1; + strI2c.u16Sz = 2; + } else { + b[0] = 0x80; + b[1] = (uint8)(u32Addr >> 24); + b[2] = (uint8)(u32Addr >> 16); + b[3] = (uint8)(u32Addr >> 8); + b[4] = (uint8)(u32Addr); + b[5] = 0x04; + rsz = 4; + strI2c.u16Sz = 6; + } + + strI2c.pu8Buf = b; + + if(M2M_SUCCESS == nm_bus_ioctl(NM_BUS_IOCTL_W, &strI2c)) + { + strI2c.u16Sz = rsz; + if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strI2c)) + { + //M2M_ERR("read error\n"); + s8Ret = M2M_ERR_BUS_FAIL; + } + } + else + { + M2M_ERR("failed to send cfg bytes\n"); + s8Ret = M2M_ERR_BUS_FAIL; + } + + if (rsz == 1) { + *pu32RetVal = b[0]; + } else { + *pu32RetVal = b[0] | ((uint32)b[1] << 8) | ((uint32)b[2] << 16) | ((uint32)b[3] << 24); + } + return s8Ret; +} + +/* +* @fn nm_i2c_read_reg +* @brief Read register +* @param [in] u32Addr +* Register address +* @return Register value +* @author M. Abdelmawla +* @date 11 July 2012 +* @version 1.0 +*/ +uint32 nm_i2c_read_reg(uint32 u32Addr) +{ + uint32 val; + nm_i2c_read_reg_with_ret(u32Addr, &val); + return val; +} + +/* +* @fn nm_i2c_write_reg +* @brief write register +* @param [in] u32Addr +* Register address +* @param [in] u32Val +* Value to be written to the register +* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure +* @author M. Abdelmawla +* @date 11 July 2012 +* @version 1.0 +*/ +sint8 nm_i2c_write_reg(uint32 u32Addr, uint32 u32Val) +{ + tstrNmI2cDefault strI2c; + uint8 b[16]; + sint8 s8Ret = M2M_SUCCESS; + + if(u32Addr < 0xff) { /* clockless i2c */ + b[0] = 0x19; + b[1] = (uint8)(u32Addr); + b[2] = (uint8)(u32Val); + strI2c.u16Sz = 3; + } else { + b[0] = 0x90; + b[1] = (uint8)(u32Addr >> 24); + b[2] = (uint8)(u32Addr >> 16); + b[3] = (uint8)(u32Addr >> 8); + b[4] = (uint8)u32Addr; + b[5] = 0x04; + b[6] = (uint8)u32Val; + b[7] = (uint8)(u32Val >> 8); + b[8] = (uint8)(u32Val >> 16); + b[9] = (uint8)(u32Val >> 24); + strI2c.u16Sz = 10; + } + + strI2c.pu8Buf = b; + + if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_W, &strI2c)) + { + M2M_ERR("write error\n"); + s8Ret = M2M_ERR_BUS_FAIL; + } + + return s8Ret; +} + +/* +* @fn nm_i2c_read_block +* @brief Read block of data +* @param [in] u32Addr +* Start address +* @param [out] puBuf +* Pointer to a buffer used to return the read data +* @param [in] u16Sz +* Number of bytes to read. The buffer size must be >= u16Sz +* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure +* @author M. Abdelmawla +* @date 11 July 2012 +* @version 1.0 +*/ +sint8 nm_i2c_read_block(uint32 u32Addr, uint8 *pu8Buf, uint16 u16Sz) +{ + tstrNmI2cDefault strI2c; + uint8 au8Buf[7]; + sint8 s8Ret = M2M_SUCCESS; + + au8Buf[0] = 0x02; + au8Buf[1] = (uint8)(u32Addr >> 24); + au8Buf[2] = (uint8)(u32Addr >> 16); + au8Buf[3] = (uint8)(u32Addr >> 8); + au8Buf[4] = (uint8)(u32Addr >> 0); + au8Buf[5] = (uint8)(u16Sz >> 8); + au8Buf[6] = (uint8)(u16Sz); + + strI2c.pu8Buf = au8Buf; + strI2c.u16Sz = sizeof(au8Buf); + + if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_W, &strI2c)) + { + M2M_ERR("write error\n"); + s8Ret = M2M_ERR_BUS_FAIL; + } + else + { + strI2c.pu8Buf = pu8Buf; + strI2c.u16Sz = u16Sz; + + if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strI2c)) + { + M2M_ERR("read error\n"); + s8Ret = M2M_ERR_BUS_FAIL; + } + } + + return s8Ret; +} + +/* +* @fn nm_i2c_write_block +* @brief Write block of data +* @param [in] u32Addr +* Start address +* @param [in] puBuf +* Pointer to the buffer holding the data to be written +* @param [in] u16Sz +* Number of bytes to write. The buffer size must be >= u16Sz +* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure +* @author M. Abdelmawla +* @date 11 July 2012 +* @version 1.0 +*/ +sint8 nm_i2c_write_block(uint32 u32Addr, uint8 *pu8Buf, uint16 u16Sz) +{ + uint8 au8Buf[7]; + tstrNmI2cSpecial strI2c; + sint8 s8Ret = M2M_SUCCESS; + + au8Buf[0] = 0x12; + au8Buf[1] = (uint8)(u32Addr >> 24); + au8Buf[2] = (uint8)(u32Addr >> 16); + au8Buf[3] = (uint8)(u32Addr >> 8); + au8Buf[4] = (uint8)(u32Addr); + au8Buf[5] = (uint8)(u16Sz >> 8); + au8Buf[6] = (uint8)(u16Sz); + + strI2c.pu8Buf1 = au8Buf; + strI2c.pu8Buf2 = pu8Buf; + strI2c.u16Sz1 = sizeof(au8Buf); + strI2c.u16Sz2 = u16Sz; + + if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_W_SPECIAL, &strI2c)) + { + M2M_ERR("write error\n"); + s8Ret = M2M_ERR_BUS_FAIL; + } + + return s8Ret; +} + +#endif +/* EOF */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmi2c.h b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmi2c.h new file mode 100644 index 000000000..a9048cc5b --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmi2c.h @@ -0,0 +1,97 @@ +/** + * + * \file + * + * \brief This module contains WINC3400 I2C protocol bus APIs implementation. + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _NMI2C_H_ +#define _NMI2C_H_ + +#include "common/include/nm_common.h" + +/** +* @fn nm_i2c_read_reg +* @brief Read register +* @param [in] u32Addr +* Register address +* @return Register value +*/ +uint32 nm_i2c_read_reg(uint32 u32Addr); + +/** +* @fn nm_i2c_read_reg_with_ret +* @brief Read register with error code return +* @param [in] u32Addr +* Register address +* @param [out] pu32RetVal +* Pointer to u32 variable used to return the read value +* @return ZERO in case of success and M2M_ERR_BUS_FAIL in case of failure +*/ +sint8 nm_i2c_read_reg_with_ret(uint32 u32Addr, uint32* pu32RetVal); + +/** +* @fn nm_i2c_write_reg +* @brief write register +* @param [in] u32Addr +* Register address +* @param [in] u32Val +* Value to be written to the register +* @return ZERO in case of success and M2M_ERR_BUS_FAIL in case of failure +*/ +sint8 nm_i2c_write_reg(uint32 u32Addr, uint32 u32Val); + +/** +* @fn nm_i2c_read_block +* @brief Read block of data +* @param [in] u32Addr +* Start address +* @param [out] puBuf +* Pointer to a buffer used to return the read data +* @param [in] u16Sz +* Number of bytes to read. The buffer size must be >= u16Sz +* @return ZERO in case of success and M2M_ERR_BUS_FAIL in case of failure +*/ +sint8 nm_i2c_read_block(uint32 u32Addr, uint8 *puBuf, uint16 u16Sz); + +/** +* @fn nm_i2c_write_block +* @brief Write block of data +* @param [in] u32Addr +* Start address +* @param [in] puBuf +* Pointer to the buffer holding the data to be written +* @param [in] u16Sz +* Number of bytes to write. The buffer size must be >= u16Sz +* @return ZERO in case of success and M2M_ERR_BUS_FAIL in case of failure +*/ +sint8 nm_i2c_write_block(uint32 u32Addr, uint8 *puBuf, uint16 u16Sz); + +#endif /* _NMI2C_H_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmspi.c b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmspi.c new file mode 100644 index 000000000..823f50fae --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmspi.c @@ -0,0 +1,910 @@ +/** + * + * \file + * + * \brief This module contains WINC3400 SPI protocol bus APIs implementation. + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include "common/include/nm_common.h" + +#ifdef CONF_WINC_USE_SPI + +#define USE_OLD_SPI_SW + +#include "bus_wrapper/include/nm_bus_wrapper.h" +#include "nmspi.h" + +#define NMI_PERIPH_REG_BASE 0x1000 +#define NMI_INTR_REG_BASE (NMI_PERIPH_REG_BASE+0xa00) +#define NMI_CHIPID (NMI_PERIPH_REG_BASE) +#define NMI_PIN_MUX_0 (NMI_PERIPH_REG_BASE + 0x408) +#define NMI_INTR_ENABLE (NMI_INTR_REG_BASE) + +#define NMI_SPI_REG_BASE 0xe800 +#define NMI_SPI_CTL (NMI_SPI_REG_BASE) +#define NMI_SPI_MASTER_DMA_ADDR (NMI_SPI_REG_BASE+0x4) +#define NMI_SPI_MASTER_DMA_COUNT (NMI_SPI_REG_BASE+0x8) +#define NMI_SPI_SLAVE_DMA_ADDR (NMI_SPI_REG_BASE+0xc) +#define NMI_SPI_SLAVE_DMA_COUNT (NMI_SPI_REG_BASE+0x10) +#define NMI_SPI_TX_MODE (NMI_SPI_REG_BASE+0x20) +#define NMI_SPI_PROTOCOL_CONFIG (NMI_SPI_REG_BASE+0x24) +#define NMI_SPI_INTR_CTL (NMI_SPI_REG_BASE+0x2c) + +#define NMI_SPI_PROTOCOL_OFFSET (NMI_SPI_PROTOCOL_CONFIG-NMI_SPI_REG_BASE) + +#define SPI_BASE NMI_SPI_REG_BASE + +//#define CMD_DMA_WRITE 0xc1 +//#define CMD_DMA_READ 0xc2 +#define CMD_INTERNAL_WRITE 0xc3 +#define CMD_INTERNAL_READ 0xc4 +//#define CMD_TERMINATE 0xc5 +//#define CMD_REPEAT 0xc6 +#define CMD_DMA_EXT_WRITE 0xc7 +#define CMD_DMA_EXT_READ 0xc8 +#define CMD_SINGLE_WRITE 0xc9 +#define CMD_SINGLE_READ 0xca +#define CMD_RESET 0xcf + +#define N_OK 0 +#define N_FAIL -1 +#define N_RESET -2 +#define N_RETRY -3 + + +#define DATA_PKT_SZ_256 256 +#define DATA_PKT_SZ_512 512 +#define DATA_PKT_SZ_1K 1024 +#define DATA_PKT_SZ_4K (4 * 1024) +#define DATA_PKT_SZ_8K (8 * 1024) +#define DATA_PKT_SZ DATA_PKT_SZ_8K + +static uint8 gu8Crc_off = 0; +#if (defined __SAMG55J19__) || (defined __SAM4SD32C__) || (defined __SAME70Q21__) || (defined __SAME70Q20B__) || (defined __SAME70Q21B__) +static sint8 nmi_spi_read(uint8* b, uint16 sz) +{ + tstrNmSpiRw spi; + spi.pu8InBuf = NULL; + spi.pu8OutBuf = b; + spi.u16Sz = sz; + return nm_bus_ioctl(NM_BUS_IOCTL_RW, &spi); +} + +static sint8 nmi_spi_write(uint8* b, uint16 sz) +{ + tstrNmSpiRw spi; + spi.pu8InBuf = b; + spi.pu8OutBuf = NULL; + spi.u16Sz = sz; + return nm_bus_ioctl(NM_BUS_IOCTL_RW, &spi); +} + +static sint8 nmi_spi_writeread(uint8* bw, uint8* br, uint16 sz) +{ + nmi_spi_write(bw, sz); + return nmi_spi_read(br, sz); +} +#else +static inline sint8 nmi_spi_read(uint8* b, uint16 sz) +{ + return nm_spi_rw(NULL, b, sz); +} +static inline sint8 nmi_spi_write(uint8* b, uint16 sz) +{ + return nm_spi_rw(b, NULL, sz); +} +static sint8 nmi_spi_writeread(uint8* bw, uint8* br, uint16 sz) +{ + return nm_spi_rw(bw, br, sz); +} +#endif +/******************************************** + + Crc7 + +********************************************/ + +static const uint8 crc7_syndrome_table[256] = { + 0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f, + 0x48, 0x41, 0x5a, 0x53, 0x6c, 0x65, 0x7e, 0x77, + 0x19, 0x10, 0x0b, 0x02, 0x3d, 0x34, 0x2f, 0x26, + 0x51, 0x58, 0x43, 0x4a, 0x75, 0x7c, 0x67, 0x6e, + 0x32, 0x3b, 0x20, 0x29, 0x16, 0x1f, 0x04, 0x0d, + 0x7a, 0x73, 0x68, 0x61, 0x5e, 0x57, 0x4c, 0x45, + 0x2b, 0x22, 0x39, 0x30, 0x0f, 0x06, 0x1d, 0x14, + 0x63, 0x6a, 0x71, 0x78, 0x47, 0x4e, 0x55, 0x5c, + 0x64, 0x6d, 0x76, 0x7f, 0x40, 0x49, 0x52, 0x5b, + 0x2c, 0x25, 0x3e, 0x37, 0x08, 0x01, 0x1a, 0x13, + 0x7d, 0x74, 0x6f, 0x66, 0x59, 0x50, 0x4b, 0x42, + 0x35, 0x3c, 0x27, 0x2e, 0x11, 0x18, 0x03, 0x0a, + 0x56, 0x5f, 0x44, 0x4d, 0x72, 0x7b, 0x60, 0x69, + 0x1e, 0x17, 0x0c, 0x05, 0x3a, 0x33, 0x28, 0x21, + 0x4f, 0x46, 0x5d, 0x54, 0x6b, 0x62, 0x79, 0x70, + 0x07, 0x0e, 0x15, 0x1c, 0x23, 0x2a, 0x31, 0x38, + 0x41, 0x48, 0x53, 0x5a, 0x65, 0x6c, 0x77, 0x7e, + 0x09, 0x00, 0x1b, 0x12, 0x2d, 0x24, 0x3f, 0x36, + 0x58, 0x51, 0x4a, 0x43, 0x7c, 0x75, 0x6e, 0x67, + 0x10, 0x19, 0x02, 0x0b, 0x34, 0x3d, 0x26, 0x2f, + 0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c, + 0x3b, 0x32, 0x29, 0x20, 0x1f, 0x16, 0x0d, 0x04, + 0x6a, 0x63, 0x78, 0x71, 0x4e, 0x47, 0x5c, 0x55, + 0x22, 0x2b, 0x30, 0x39, 0x06, 0x0f, 0x14, 0x1d, + 0x25, 0x2c, 0x37, 0x3e, 0x01, 0x08, 0x13, 0x1a, + 0x6d, 0x64, 0x7f, 0x76, 0x49, 0x40, 0x5b, 0x52, + 0x3c, 0x35, 0x2e, 0x27, 0x18, 0x11, 0x0a, 0x03, + 0x74, 0x7d, 0x66, 0x6f, 0x50, 0x59, 0x42, 0x4b, + 0x17, 0x1e, 0x05, 0x0c, 0x33, 0x3a, 0x21, 0x28, + 0x5f, 0x56, 0x4d, 0x44, 0x7b, 0x72, 0x69, 0x60, + 0x0e, 0x07, 0x1c, 0x15, 0x2a, 0x23, 0x38, 0x31, + 0x46, 0x4f, 0x54, 0x5d, 0x62, 0x6b, 0x70, 0x79 +}; + + +static inline uint8 crc7_byte(uint8 crc, uint8 data) +{ + return crc7_syndrome_table[(crc << 1) ^ data]; +} + +static inline uint8 crc7(uint8 crc, const uint8 *buffer, uint32 len) +{ + while (len--) + crc = crc7_byte(crc, *buffer++); + return crc; +} + +/******************************************** + + Spi protocol Function + +********************************************/ + +static sint8 spi_cmd(uint8 cmd, uint32 adr, uint32 u32data, uint32 sz,uint8 clockless) +{ + uint8 bc[9]; + uint8 len = 5; + sint8 result = N_OK; + + bc[0] = cmd; + switch (cmd) { + case CMD_SINGLE_READ: /* single word (4 bytes) read */ + bc[1] = (uint8)(adr >> 16); + bc[2] = (uint8)(adr >> 8); + bc[3] = (uint8)adr; + len = 5; + break; + case CMD_INTERNAL_READ: /* internal register read */ + bc[1] = (uint8)(adr >> 8); + if(clockless) bc[1] |= (1 << 7); + bc[2] = (uint8)adr; + bc[3] = 0x00; + len = 5; + break; +#if defined(CMD_TERMINATE) + case CMD_TERMINATE: /* termination */ + bc[1] = 0x00; + bc[2] = 0x00; + bc[3] = 0x00; + len = 5; + break; +#endif +#if defined(CMD_REPEAT) + case CMD_REPEAT: /* repeat */ + bc[1] = 0x00; + bc[2] = 0x00; + bc[3] = 0x00; + len = 5; + break; +#endif + case CMD_RESET: /* reset */ + bc[1] = 0xff; + bc[2] = 0xff; + bc[3] = 0xff; + len = 5; + break; +#if defined(CMD_DMA_WRITE) || defined(CMD_DMA_READ) + case CMD_DMA_WRITE: /* dma write */ + case CMD_DMA_READ: /* dma read */ + bc[1] = (uint8)(adr >> 16); + bc[2] = (uint8)(adr >> 8); + bc[3] = (uint8)adr; + bc[4] = (uint8)(sz >> 8); + bc[5] = (uint8)(sz); + len = 7; + break; +#endif + case CMD_DMA_EXT_WRITE: /* dma extended write */ + case CMD_DMA_EXT_READ: /* dma extended read */ + bc[1] = (uint8)(adr >> 16); + bc[2] = (uint8)(adr >> 8); + bc[3] = (uint8)adr; + bc[4] = (uint8)(sz >> 16); + bc[5] = (uint8)(sz >> 8); + bc[6] = (uint8)(sz); + len = 8; + break; + case CMD_INTERNAL_WRITE: /* internal register write */ + bc[1] = (uint8)(adr >> 8); + if(clockless) bc[1] |= (1 << 7); + bc[2] = (uint8)(adr); + bc[3] = (uint8)(u32data >> 24); + bc[4] = (uint8)(u32data >> 16); + bc[5] = (uint8)(u32data >> 8); + bc[6] = (uint8)(u32data); + len = 8; + break; + case CMD_SINGLE_WRITE: /* single word write */ + bc[1] = (uint8)(adr >> 16); + bc[2] = (uint8)(adr >> 8); + bc[3] = (uint8)(adr); + bc[4] = (uint8)(u32data >> 24); + bc[5] = (uint8)(u32data >> 16); + bc[6] = (uint8)(u32data >> 8); + bc[7] = (uint8)(u32data); + len = 9; + break; + default: + result = N_FAIL; + break; + } + + if (result == N_OK) { + if (!gu8Crc_off) + bc[len-1] = (crc7(0x7f, (const uint8 *)&bc[0], len-1)) << 1; + else + len-=1; + + if (M2M_SUCCESS != nmi_spi_write(bc, len)) { + M2M_ERR("[nmi spi]: Failed cmd write, bus error...\n"); + result = N_FAIL; + } + } + + return result; +} + +static sint8 spi_cmd_rsp(uint8 cmd) +{ + uint8 rsp; + sint8 result = N_OK; + sint8 s8RetryCnt; + + /** + Command/Control response + **/ +#if defined(CMD_TERMINATE) + if (cmd == CMD_TERMINATE) { + if (M2M_SUCCESS != nmi_spi_read(&rsp, 1)) { + result = N_FAIL; + goto _fail_; + } + } +#endif +#if defined(CMD_REPEAT) + if (cmd == CMD_REPEAT) { + if (M2M_SUCCESS != nmi_spi_read(&rsp, 1)) { + result = N_FAIL; + goto _fail_; + } + } +#endif + + /* wait for response */ + s8RetryCnt = 10; + do + { + if (M2M_SUCCESS != nmi_spi_read(&rsp, 1)) { + M2M_ERR("[nmi spi]: Failed cmd response read, bus error...\n"); + result = N_FAIL; + goto _fail_; + } + } while((rsp != cmd) && (s8RetryCnt-- >0)); + if (s8RetryCnt < 0) + { + M2M_ERR("[nmi spi]: Failed cmd response read\n"); + result = N_FAIL; + goto _fail_; + } + /** + State response + **/ + /* wait for response */ + s8RetryCnt = 10; + do + { + if (M2M_SUCCESS != nmi_spi_read(&rsp, 1)) { + M2M_ERR("[nmi spi]: Failed cmd response read, bus error...\n"); + result = N_FAIL; + goto _fail_; + } + } while((rsp != 0x00) && (s8RetryCnt-- >0)); + if (s8RetryCnt < 0) + { + M2M_ERR("[nmi spi]: Failed cmd response read\n"); + result = N_FAIL; + goto _fail_; + } +_fail_: + + return result; +} + +static sint8 spi_reset(void) +{ + M2M_INFO("Reset Spi\n"); + spi_cmd(CMD_RESET, 0, 0, 0, 0); + + if (spi_cmd_rsp(CMD_RESET) != N_OK) { + // Reset command failed, need to send repeated 1's until reset occurs + // TODO This catchall reset code has not yet been tested. + uint8 w_buf[8] = {0xFF}; + uint8 r_buf[8]; + M2M_ERR("[nmi spi]: Failed rst cmd response\n"); + nmi_spi_writeread(w_buf, r_buf, 8); + if (r_buf[7] != 0xFF) + { + M2M_ERR("[nmi spi]: Failed repeated reset\n"); + return N_FAIL; + } + } + // TODO: May need to call spi_init() here + return N_OK; +} + +static sint8 spi_data_read(uint8 *b, uint16 sz,uint8 clockless) +{ + sint16 retry, ix, nbytes; + sint8 result = N_OK; + uint8 crc[2]; + uint8 rsp; + + /** + Data + **/ + ix = 0; + do { + if (sz <= DATA_PKT_SZ) + nbytes = sz; + else + nbytes = DATA_PKT_SZ; + + /** + Data Response header + **/ + retry = 10; + do { + if (M2M_SUCCESS != nmi_spi_read(&rsp, 1)) { + M2M_ERR("[nmi spi]: Failed data response read, bus error...\n"); + result = N_FAIL; + break; + } + //if (((rsp >> 4) & 0xf) == 0xf) + if ((rsp & 0xf0) == 0xf0) + break; + } while (retry--); + + if (result == N_FAIL) + break; + + if (retry <= 0) { + M2M_ERR("[nmi spi]: Failed data response read...(%02x)\n", rsp); + result = N_FAIL; + break; + } + + /** + Read bytes + **/ + if (M2M_SUCCESS != nmi_spi_read(&b[ix], nbytes)) { + M2M_ERR("[nmi spi]: Failed data block read, bus error...\n"); + result = N_FAIL; + break; + } + if(!clockless) + { + /** + Read Crc + **/ + if (!gu8Crc_off) { + if (M2M_SUCCESS != nmi_spi_read(crc, 2)) { + M2M_ERR("[nmi spi]: Failed data block crc read, bus error...\n"); + result = N_FAIL; + break; + } + } + } + ix += nbytes; + sz -= nbytes; + + } while (sz); + + return result; +} + +static sint8 spi_data_write(uint8 *b, uint16 sz) +{ + sint16 ix = 0; + uint16 nbytes; + sint8 result = N_OK; + uint8 cmd, order, crc[2] = {0}; + //uint8 rsp; + + /** + Data + **/ + do { + if (sz <= DATA_PKT_SZ) + nbytes = sz; + else + nbytes = DATA_PKT_SZ; + + /** + Write command + **/ + cmd = 0xf0; + if (ix == 0) { + if (sz <= DATA_PKT_SZ) + order = 0x3; + else + order = 0x1; + } else { + if (sz <= DATA_PKT_SZ) + order = 0x3; + else + order = 0x2; + } + cmd |= order; + if (M2M_SUCCESS != nmi_spi_write(&cmd, 1)) { + M2M_ERR("[nmi spi]: Failed data block cmd write, bus error...\n"); + result = N_FAIL; + break; + } + + /** + Write data + **/ + if (M2M_SUCCESS != nmi_spi_write(&b[ix], nbytes)) { + M2M_ERR("[nmi spi]: Failed data block write, bus error...\n"); + result = N_FAIL; + break; + } + + /** + Write Crc + **/ + if (!gu8Crc_off) { + if (M2M_SUCCESS != nmi_spi_write(crc, 2)) { + M2M_ERR("[nmi spi]: Failed data block crc write, bus error...\n"); + result = N_FAIL; + break; + } + } + + ix += nbytes; + sz -= nbytes; + } while (sz); + + + return result; +} + +/******************************************** + + Spi Internal Read/Write Function + +********************************************/ + +/******************************************** + + Spi interfaces + +********************************************/ + +/* +* @fn nm_spi_write_reg +* @brief write register +* @param [in] u32Addr +* Register address +* @param [in] u32Val +* Value to be written to the register +* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure +* @author M. Abdelmawla +* @date 11 July 2012 +* @version 1.0 +*/ +sint8 nm_spi_write_reg(uint32 addr, uint32 u32data) +{ + sint8 result = N_OK; + uint8 cmd = CMD_SINGLE_WRITE; + uint8 clockless = 0; + if (addr <= 0x30) + { + /** + NMC1000 clockless registers. + **/ + cmd = CMD_INTERNAL_WRITE; + clockless = 1; + } + //else + //{ + // cmd = CMD_SINGLE_WRITE; + // clockless = 0; + //} + +#if defined USE_OLD_SPI_SW + result = spi_cmd(cmd, addr, u32data, 4, clockless); + if (result != N_OK) { + M2M_ERR("[nmi spi]: Failed cmd, write reg (%08x)...\n", (unsigned int)addr); + return N_FAIL; + } + + result = spi_cmd_rsp(cmd); + if (result != N_OK) { + M2M_ERR("[nmi spi]: Failed cmd response, write reg (%08x)...\n", (unsigned int)addr); + spi_reset(); + return N_FAIL; + } + + return N_OK; +#else + + result = spi_cmd_complete(cmd, addr, (uint8*)&u32data, 4, clockless); + if (result != N_OK) { + M2M_ERR( "[nmi spi]: Failed cmd, write reg (%08x)...\n", addr); + } + + return result; + +#endif +} + + +/* +* @fn nm_spi_write_block +* @brief Write block of data +* @param [in] u32Addr +* Start address +* @param [in] puBuf +* Pointer to the buffer holding the data to be written +* @param [in] u16Sz +* Number of bytes to write. The buffer size must be >= u16Sz +* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure +* @author M. Abdelmawla +* @date 11 July 2012 +* @version 1.0 +*/ +sint8 nm_spi_write_block(uint32 addr, uint8 *buf, uint16 size) +{ + sint8 result; + uint8 cmd = CMD_DMA_EXT_WRITE; + + + /** + Command + **/ +#if defined USE_OLD_SPI_SW + + //Workaround hardware problem with single byte transfers over SPI bus + if (size == 1) + size = 2; + + result = spi_cmd(cmd, addr, 0, size,0); + if (result != N_OK) { + M2M_ERR("[nmi spi]: Failed cmd, write block (%08x)...\n", (unsigned int)addr); + return N_FAIL; + } + + result = spi_cmd_rsp(cmd); + if (result != N_OK) { + M2M_ERR("[nmi spi ]: Failed cmd response, write block (%08x)...\n", (unsigned int)addr); + spi_reset(); + return N_FAIL; + } +#else + result = spi_cmd_complete(cmd, addr, NULL, size, 0); + if (result != N_OK) { + M2M_ERR( "[nmi spi]: Failed cmd, write block (%08x)...\n", addr); + return N_FAIL; + } +#endif + + /** + Data + **/ + result = spi_data_write(buf, size); + if (result != N_OK) { + M2M_ERR("[nmi spi]: Failed block data write...\n"); + spi_reset(); + return N_FAIL; + } + + return N_OK; +} + +/* +* @fn nm_spi_read_reg_with_ret +* @brief Read register with error code return +* @param [in] u32Addr +* Register address +* @param [out] pu32RetVal +* Pointer to u32 variable used to return the read value +* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure +* @author M. Abdelmawla +* @date 11 July 2012 +* @version 1.0 +*/ +sint8 nm_spi_read_reg_with_ret(uint32 addr, uint32 *u32data) +{ + sint8 result = N_OK; + uint8 cmd = CMD_SINGLE_READ; + uint8 tmp[4]; + uint8 clockless = 0; + + if (addr <= 0xff) + { + /** + NMC1000 clockless registers. + **/ + cmd = CMD_INTERNAL_READ; + clockless = 1; + } + //else + //{ + // cmd = CMD_SINGLE_READ; + // clockless = 0; + //} + +#if defined USE_OLD_SPI_SW + result = spi_cmd(cmd, addr, 0, 4, clockless); + if (result != N_OK) { + M2M_ERR("[nmi spi]: Failed cmd, read reg (%08x)...\n", (unsigned int)addr); + return N_FAIL; + } + + result = spi_cmd_rsp(cmd); + if (result != N_OK) { + M2M_ERR("[nmi spi]: Failed cmd response, read reg (%08x)...\n", (unsigned int)addr); + spi_reset(); + return N_FAIL; + } + + /* to avoid endianess issues */ + result = spi_data_read(tmp, 4, clockless); + if (result != N_OK) { + M2M_ERR("[nmi spi]: Failed data read...\n"); + spi_reset(); + return N_FAIL; + } +#else + result = spi_cmd_complete(cmd, addr, (uint8*)&tmp[0], 4, clockless); + if (result != N_OK) { + M2M_ERR( "[nmi spi]: Failed cmd, read reg (%08x)...\n", addr); + return N_FAIL; + } + +#endif + + *u32data = tmp[0] | + ((uint32)tmp[1] << 8) | + ((uint32)tmp[2] << 16) | + ((uint32)tmp[3] << 24); + + return N_OK; +} + +/* +* @fn nm_spi_read_block +* @brief Read block of data +* @param [in] u32Addr +* Start address +* @param [out] puBuf +* Pointer to a buffer used to return the read data +* @param [in] u16Sz +* Number of bytes to read. The buffer size must be >= u16Sz +* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure +* @author M. Abdelmawla +* @date 11 July 2012 +* @version 1.0 +*/ +sint8 nm_spi_read_block(uint32 addr, uint8 *buf, uint16 size) +{ + uint8 cmd = CMD_DMA_EXT_READ; + sint8 result; + +#if defined USE_OLD_SPI_SW + uint8 tmp[2]; + uint8 single_byte_workaround = 0; +#endif + + /** + Command + **/ +#if defined USE_OLD_SPI_SW + if (size == 1) + { + //Workaround hardware problem with single byte transfers over SPI bus + size = 2; + single_byte_workaround = 1; + } + result = spi_cmd(cmd, addr, 0, size,0); + if (result != N_OK) { + M2M_ERR("[nmi spi]: Failed cmd, read block (%08x)...\n", (unsigned int)addr); + return N_FAIL; + } + + result = spi_cmd_rsp(cmd); + if (result != N_OK) { + M2M_ERR("[nmi spi]: Failed cmd response, read block (%08x)...\n", (unsigned int)addr); + spi_reset(); + return N_FAIL; + } + + /** + Data + **/ + if (single_byte_workaround) + { + result = spi_data_read(tmp, size,0); + buf[0] = tmp[0]; + } + else + result = spi_data_read(buf, size,0); + if (result != N_OK) { + M2M_ERR("[nmi spi]: Failed block data read...\n"); + spi_reset(); + return N_FAIL; + } +#else + result = spi_cmd_complete(cmd, addr, buf, size, 0); + if (result != N_OK) { + M2M_ERR("[nmi spi]: Failed cmd, read block (%08x)...\n", addr); + return N_FAIL; + } +#endif + + return N_OK; +} + +/******************************************** + + Bus interfaces + +********************************************/ + +static void spi_init_pkt_sz(void) +{ + uint32 val32; + + /* Make sure SPI max. packet size fits the defined DATA_PKT_SZ. */ + val32 = nm_spi_read_reg(SPI_BASE+0x24); + val32 &= ~(0x7 << 4); + switch(DATA_PKT_SZ) + { + case 256: val32 |= (0 << 4); break; + case 512: val32 |= (1 << 4); break; + case 1024: val32 |= (2 << 4); break; + case 2048: val32 |= (3 << 4); break; + case 4096: val32 |= (4 << 4); break; + case 8192: val32 |= (5 << 4); break; + + } + nm_spi_write_reg(SPI_BASE+0x24, val32); +} + +/* +* @fn nm_spi_init +* @brief Initialize the SPI +* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure +* @author M. Abdelmawla +* @date 11 July 2012 +* @version 1.0 +*/ +sint8 nm_spi_init(void) +{ + uint32 chipid; + uint32 reg =0; + + /** + configure protocol + **/ + gu8Crc_off = 0; + + // TODO: We can remove the CRC trials if there is a definite way to reset + // the SPI to it's initial value. + if (nm_spi_read_reg_with_ret(NMI_SPI_PROTOCOL_CONFIG, ®) != M2M_SUCCESS) { + /* Read failed. Try with CRC off. This might happen when module + is removed but chip isn't reset*/ + gu8Crc_off = 1; + M2M_ERR("[nmi spi]: Failed internal read protocol with CRC on, retyring with CRC off...\n"); + if (nm_spi_read_reg_with_ret(NMI_SPI_PROTOCOL_CONFIG, ®) != M2M_SUCCESS){ + // Read failed with both CRC on and off, something went bad + M2M_ERR( "[nmi spi]: Failed internal read protocol...\n"); + return M2M_ERR_BUS_FAIL; + } + } + if(gu8Crc_off == 0) + { + reg &= ~0xc; /* disable crc checking */ + reg &= ~0x70; + reg |= (0x5 << 4); + if (nm_spi_write_reg(NMI_SPI_PROTOCOL_CONFIG, reg) != M2M_SUCCESS) { + M2M_ERR( "[nmi spi]: Failed internal write protocol reg...\n"); + return M2M_ERR_BUS_FAIL; + } + gu8Crc_off = 1; + } + + /** + make sure can read back chip id correctly + **/ + if (nm_spi_read_reg_with_ret(0x1000, &chipid) != M2M_SUCCESS) { + M2M_ERR("[nmi spi]: Fail cmd read chip id...\n"); + return M2M_ERR_BUS_FAIL; + } + + M2M_DBG("[nmi spi]: chipid (%08x)\n", (unsigned int)chipid); + spi_init_pkt_sz(); + + + return M2M_SUCCESS; +} + +/* +* @fn nm_spi_init +* @brief DeInitialize the SPI +* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure +* @author Samer Sarhan +* @date 27 Feb 2015 +* @version 1.0 +*/ +sint8 nm_spi_deinit(void) +{ + gu8Crc_off = 0; + return M2M_SUCCESS; +} + +/* +* @fn nm_spi_read_reg +* @brief Read register +* @param [in] u32Addr +* Register address +* @return Register value +* @author M. Abdelmawla +* @date 11 July 2012 +* @version 1.0 +*/ +uint32 nm_spi_read_reg(uint32 u32Addr) +{ + uint32 u32Val=0; + + nm_spi_read_reg_with_ret(u32Addr, &u32Val); + + return u32Val; +} + +#endif diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmspi.h b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmspi.h new file mode 100644 index 000000000..740f581ca --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmspi.h @@ -0,0 +1,119 @@ +/** + * + * \file + * + * \brief This module contains WINC3400 SPI protocol bus APIs implementation. + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _NMSPI_H_ +#define _NMSPI_H_ + +#include "common/include/nm_common.h" + +#ifdef __cplusplus + extern "C" { +#endif + +/** +* @fn nm_spi_init +* @brief Initialize the SPI +* @return ZERO in case of success and M2M_ERR_BUS_FAIL in case of failure +*/ +sint8 nm_spi_init(void); + +/** +* @fn nm_spi_deinit +* @brief DeInitialize the SPI +* @return ZERO in case of success and M2M_ERR_BUS_FAIL in case of failure +*/ +sint8 nm_spi_deinit(void); + +/** +* @fn nm_spi_read_reg +* @brief Read register +* @param [in] u32Addr +* Register address +* @return Register value +*/ +uint32 nm_spi_read_reg(uint32 u32Addr); + +/** +* @fn nm_spi_read_reg_with_ret +* @brief Read register with error code return +* @param [in] u32Addr +* Register address +* @param [out] pu32RetVal +* Pointer to u32 variable used to return the read value +* @return ZERO in case of success and M2M_ERR_BUS_FAIL in case of failure +*/ +sint8 nm_spi_read_reg_with_ret(uint32 u32Addr, uint32* pu32RetVal); + +/** +* @fn nm_spi_write_reg +* @brief write register +* @param [in] u32Addr +* Register address +* @param [in] u32Val +* Value to be written to the register +* @return ZERO in case of success and M2M_ERR_BUS_FAIL in case of failure +*/ +sint8 nm_spi_write_reg(uint32 u32Addr, uint32 u32Val); + +/** +* @fn nm_spi_read_block +* @brief Read block of data +* @param [in] u32Addr +* Start address +* @param [out] puBuf +* Pointer to a buffer used to return the read data +* @param [in] u16Sz +* Number of bytes to read. The buffer size must be >= u16Sz +* @return ZERO in case of success and M2M_ERR_BUS_FAIL in case of failure +*/ +sint8 nm_spi_read_block(uint32 u32Addr, uint8 *puBuf, uint16 u16Sz); + +/** +* @fn nm_spi_write_block +* @brief Write block of data +* @param [in] u32Addr +* Start address +* @param [in] puBuf +* Pointer to the buffer holding the data to be written +* @param [in] u16Sz +* Number of bytes to write. The buffer size must be >= u16Sz +* @return ZERO in case of success and M2M_ERR_BUS_FAIL in case of failure +*/ +sint8 nm_spi_write_block(uint32 u32Addr, uint8 *puBuf, uint16 u16Sz); + +#ifdef __cplusplus + } +#endif + +#endif /* _NMSPI_H_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmuart.c b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmuart.c new file mode 100644 index 000000000..48ed61326 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmuart.c @@ -0,0 +1,585 @@ +/** + * + * \file + * + * \brief This module contains WINC3400 UART protocol bus APIs implementation. + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "common/include/nm_common.h" + +#ifdef CONF_WINC_USE_UART + +#include "driver/source/nmuart.h" +#include "bus_wrapper/include/nm_bus_wrapper.h" + +#define HDR_SZ 12 + +static uint8 get_cs(uint8* b, uint8 sz){ + int i; + uint8 cs = 0; + for(i = 0; i < sz; i++) + cs ^= b[i]; + return cs; +} + +/* +* @fn nm_uart_sync_cmd +* @brief Check COM Port +* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure +* @author Dina El Sissy +* @date 13 AUG 2012 +* @version 1.0 +*/ +sint8 nm_uart_sync_cmd(void) +{ + tstrNmUartDefault strUart; + sint8 s8Ret = M2M_ERR_BUS_FAIL; + uint8 b [HDR_SZ+1]; + uint8 onchip = 0; + int escape = 3; + + // send query char up to 3 times + while (escape-- && (s8Ret != M2M_SUCCESS)) + { + b[0] = 0x12; + strUart.pu8Buf = b; + strUart.u16Sz = 1; + + // then read back all chars in the buffer if any, is last char what we are looking for + s8Ret = nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart); + if (M2M_SUCCESS == s8Ret) + { + uint8 lastchar; + + // drain buffer + while (M2M_SUCCESS == s8Ret) + { + lastchar = b[0]; + s8Ret = nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart); + } + + switch (lastchar) + { + case 0x5a: + onchip = 1; + M2M_INFO("Built-in WINCxx00 UART Found\n"); + s8Ret = M2M_SUCCESS; + break; + case 0x5b: + onchip = 0; + M2M_INFO("WINCxx00 Serial Bridge Found\n"); + s8Ret = M2M_SUCCESS; + break; + case 0x5c: + onchip = 2; + M2M_INFO("WINCxx00 Serial Bridge + AT CMD app Found\n"); + s8Ret = M2M_SUCCESS; + break; + case 0x12: + M2M_INFO("failed to read Serial Bridge ID response\n"); + s8Ret = M2M_ERR_BUS_FAIL; + break; + default: + M2M_INFO("Non Serial Bridge Found\n"); + s8Ret = M2M_ERR_BUS_FAIL; + break; + } + } + else + { + M2M_ERR("failed to send Serial Bridge ID Query\n"); + } + } + + if(s8Ret == M2M_SUCCESS) + s8Ret = (sint8)onchip; + + return s8Ret; +} + +/* +* @fn nm_uart_reboot_cmd +* @brief Sends a command to the MCU to force reboot +* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure +* @version 1.0 +*/ + +sint8 nm_uart_reboot_cmd(void) +{ + tstrNmUartDefault strUart; + sint8 s8Ret = M2M_SUCCESS; + uint8 b[HDR_SZ + 1]; + uint8 rsz; + uint8 onchip = 0; + + /*read reg*/ + b[0] = 0x13; + + rsz = 1; + strUart.pu8Buf = b; + strUart.u16Sz = 1; + + if (M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart)) + { + M2M_ERR("failed to send reboot cmd\n"); + s8Ret = M2M_ERR_BUS_FAIL; + } + return s8Ret; +} + + + sint8 nm_uart_read_reg_with_ret(uint32 u32Addr, uint32* pu32RetVal) +{ + tstrNmUartDefault strUart; + sint8 s8Ret = M2M_SUCCESS; + uint8 b [HDR_SZ+1]; + uint8 rsz; + + /*read reg*/ + b[0] = 0xa5; + b[1] = 0; + b[2] = 0; + b[3] = 0; + b[4] = 0; + b[5] = (uint8)(u32Addr & 0x000000ff); + b[6] = (uint8)((u32Addr & 0x0000ff00)>>8); + b[7] = (uint8)((u32Addr & 0x00ff0000)>>16); + b[8] = (uint8)((u32Addr & 0xff000000)>>24); + b[9] = 0; + b[10] = 0; + b[11] = 0; + b[12] = 0; + + b[2] = get_cs(&b[1],HDR_SZ); + + rsz = 4; + strUart.pu8Buf = b; + strUart.u16Sz = sizeof(b); + + if(M2M_SUCCESS == nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart)) + { + if(!nm_bus_get_chip_type()) + { + strUart.u16Sz = 1; + if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart)) + { + s8Ret = M2M_ERR_BUS_FAIL; + } + if(b[0] == 0xAC) + { + M2M_DBG("Successfully sent the command\n"); + strUart.u16Sz = rsz; + if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart)) + { + s8Ret = M2M_ERR_BUS_FAIL; + } + } + else + { + s8Ret = M2M_ERR_BUS_FAIL; + } + } + else + { + strUart.u16Sz = rsz; + if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart)) + { + s8Ret = M2M_ERR_BUS_FAIL; + } + } + } + else + { + M2M_ERR("failed to send cfg bytes\n"); + s8Ret = M2M_ERR_BUS_FAIL; + } + + *pu32RetVal = ((uint32)b[0] << 24) | ((uint32)b[1] << 16) | ((uint32)b[2] << 8) | b[3]; + + return s8Ret; +} + +/* +* @fn nm_uart_read_reg +* @brief Read register +* @param [in] u32Addr +* Register address +* @return Register value +* @author Dina El Sissy +* @date 13 AUG 2012 +* @version 1.0 +*/ +uint32 nm_uart_read_reg(uint32 u32Addr) +{ + uint32 val; + nm_uart_read_reg_with_ret(u32Addr , &val); + return val; +} + +/* +* @fn nm_uart_write_reg +* @brief write register +* @param [in] u32Addr +* Register address +* @param [in] u32Val +* Value to be written to the register +* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure +* @author Dina El Sissy +* @date 13 AUG 2012 +* @version 1.0 +*/ +sint8 nm_uart_write_reg(uint32 u32Addr, uint32 u32Val) +{ + tstrNmUartDefault strUart; + sint8 s8Ret = M2M_SUCCESS; + uint8 b[HDR_SZ+1]; + + /*write reg*/ + b[0] = 0xa5; + b[1] = 1; + b[2] = 0; + b[3] = 0; + b[4] = 0; + b[5] = (uint8)(u32Addr & 0x000000ff); + b[6] = (uint8)((u32Addr & 0x0000ff00)>>8); + b[7] = (uint8)((u32Addr & 0x00ff0000)>>16); + b[8] = (uint8)((u32Addr & 0xff000000)>>24); + b[9] = (uint8)(u32Val & 0x000000ff); + b[10] = (uint8)((u32Val & 0x0000ff00)>>8); + b[11] = (uint8)((u32Val & 0x00ff0000)>>16); + b[12] = (uint8)((u32Val & 0xff000000)>>24); + + b[2] = get_cs(&b[1],HDR_SZ); + + get_cs(&b[1],HDR_SZ); + + strUart.pu8Buf = b; + strUart.u16Sz = sizeof(b); + + if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart)) + { + M2M_ERR("write error\n"); + s8Ret = M2M_ERR_BUS_FAIL; + } + else + { + if(!nm_bus_get_chip_type()) + { + //check for the ack from the SAMD21 for the packet reception. + strUart.u16Sz = 1; + if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart)) + { + s8Ret = M2M_ERR_BUS_FAIL; + } + if(b[0] == 0xAC) + { + M2M_DBG("Successfully sent the reg write command\n"); + } + else + { + M2M_ERR("write error\n"); + s8Ret = M2M_ERR_BUS_FAIL; + } + } + } + + return s8Ret; +} + + +/** +* @fn nm_uart_read_block +* @brief Read block of data +* @param [in] u32Addr +* Start address +* @param [out] puBuf +* Pointer to a buffer used to return the read data +* @param [in] u16Sz +* Number of bytes to read. The buffer size must be >= u16Sz +* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure +* @author Dina El Sissy +* @date 13 AUG 2012 +* @version 1.0 +*/ +sint8 nm_uart_read_block(uint32 u32Addr, uint8 *pu8Buf, uint16 u16Sz) +{ + tstrNmUartDefault strUart; + sint8 s8Ret = M2M_SUCCESS; + uint8 au8Buf[HDR_SZ+1]; + + au8Buf[0] = 0xa5; + au8Buf[1] = 2; + au8Buf[2] = 0; + au8Buf[3] = (uint8)(u16Sz & 0x00ff); + au8Buf[4] = (uint8)((u16Sz & 0xff00)>>8); + au8Buf[5] = (uint8)(u32Addr & 0x000000ff); + au8Buf[6] = (uint8)((u32Addr & 0x0000ff00)>>8); + au8Buf[7] = (uint8)((u32Addr & 0x00ff0000)>>16); + au8Buf[8] = (uint8)((u32Addr & 0xff000000)>>24); + au8Buf[9] = 0; + au8Buf[10] = 0; + au8Buf[11] = 0; + au8Buf[12] = 0; + + au8Buf[2] = get_cs(&au8Buf[1],HDR_SZ); + + strUart.pu8Buf = au8Buf; + strUart.u16Sz = sizeof(au8Buf); + + if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart)) + { + M2M_ERR("write error\n"); + s8Ret = M2M_ERR_BUS_FAIL; + } + else + { + if(!nm_bus_get_chip_type()) + { + //check for the ack from the SAMD21 for the packet reception. + strUart.u16Sz = 1; + if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart)) + { + s8Ret = M2M_ERR_BUS_FAIL; + } + if(au8Buf[0] == 0xAC) + { + M2M_DBG("Successfully sent the block read command\n"); + strUart.pu8Buf = pu8Buf; + strUart.u16Sz = u16Sz; + + if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart)) + { + M2M_ERR("read error\n"); + s8Ret = M2M_ERR_BUS_FAIL; + } + } + else + { + M2M_ERR("write error (Error sending the block read command)\n"); + s8Ret = M2M_ERR_BUS_FAIL; + } + } + else + { + strUart.pu8Buf = pu8Buf; + strUart.u16Sz = u16Sz; + + if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart)) + { + M2M_ERR("read error\n"); + s8Ret = M2M_ERR_BUS_FAIL; + } + } + } + + return s8Ret; +} + +/** +* @fn nm_uart_write_block +* @brief Write block of data +* @param [in] u32Addr +* Start address +* @param [in] puBuf +* Pointer to the buffer holding the data to be written +* @param [in] u16Sz +* Number of bytes to write. The buffer size must be >= u16Sz +* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure +* @author Dina El Sissy +* @date 13 AUG 2012 +* @version 1.0 +*/ +sint8 nm_uart_write_block(uint32 u32Addr, uint8 *puBuf, uint16 u16Sz) +{ + tstrNmUartDefault strUart; + sint8 s8Ret = M2M_SUCCESS; + static uint8 au8Buf[HDR_SZ+1]; + + au8Buf[0] = 0xa5; + au8Buf[1] = 3; + au8Buf[2] = 0; + au8Buf[3] = (uint8)(u16Sz & 0x00ff); + au8Buf[4] = (uint8)((u16Sz & 0xff00)>>8); + au8Buf[5] = (uint8)(u32Addr & 0x000000ff); + au8Buf[6] = (uint8)((u32Addr & 0x0000ff00)>>8); + au8Buf[7] = (uint8)((u32Addr & 0x00ff0000)>>16); + au8Buf[8] = (uint8)((u32Addr & 0xff000000)>>24); + au8Buf[9] = 0; + au8Buf[10] = 0; + au8Buf[11] = 0; + au8Buf[12] = 0; + + au8Buf[2] = get_cs(&au8Buf[1],HDR_SZ); + + strUart.pu8Buf = au8Buf; + strUart.u16Sz = sizeof(au8Buf); + + if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart)) + { + M2M_ERR("write error\n"); + s8Ret = M2M_ERR_BUS_FAIL; + } + else + { + if(!nm_bus_get_chip_type()) + { + //check for the ack from the SAMD21 for the packet reception. + strUart.u16Sz = 1; + if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart)) + { + s8Ret = M2M_ERR_BUS_FAIL; + } + if(au8Buf[0] == 0xAC) + { + M2M_DBG("Successfully sent the block Write command\n"); + strUart.pu8Buf = puBuf; + strUart.u16Sz = u16Sz; + + if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart)) + { + M2M_ERR("write error\n"); + s8Ret = M2M_ERR_BUS_FAIL; + } + else + { + //check for the ack from the SAMD21 for the payload reception. + strUart.pu8Buf = au8Buf; + strUart.u16Sz = 1; + if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart)) + { + s8Ret = M2M_ERR_BUS_FAIL; + } + if(au8Buf[0] == 0xAC) + { + M2M_DBG("Successfully sent the data payload\n"); + } + else + { + M2M_ERR("write error\n"); + s8Ret = M2M_ERR_BUS_FAIL; + } + } + } + else + { + M2M_ERR("write error (Error sending the block write command)\n"); + s8Ret = M2M_ERR_BUS_FAIL; + } + } + else + { + strUart.pu8Buf = puBuf; + strUart.u16Sz = u16Sz; + + if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart)) + { + M2M_ERR("write error\n"); + s8Ret = M2M_ERR_BUS_FAIL; + } + } + } + return s8Ret; +} + +/** +* @fn nm_uart_reconfigure +* @brief Reconfigures the UART interface +* @param [in] ptr +* Pointer to a DWORD containing baudrate at this moment. +* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure +* @author Viswanathan Murugesan +* @date 22 OCT 2014 +* @version 1.0 +*/ +sint8 nm_uart_reconfigure(void *ptr) +{ + tstrNmUartDefault strUart; + sint8 s8Ret = M2M_SUCCESS; + uint8 b[HDR_SZ+1]; + + if (ptr == NULL) + { + M2M_ERR("port not open\n"); + return M2M_ERR_BUS_FAIL; + } + + /*write reg*/ + b[0] = 0xa5; + b[1] = 5; + b[2] = 0; + b[3] = 0; + b[4] = 0; + b[5] = 0; + b[6] = 0; + b[7] = 0; + b[8] = 0; + b[9] = (uint8)((*(unsigned long *)ptr) & 0x000000ff); + b[10] = (uint8)(((*(unsigned long *)ptr) & 0x0000ff00)>>8); + b[11] = (uint8)(((*(unsigned long *)ptr) & 0x00ff0000)>>16); + b[12] = (uint8)(((*(unsigned long *)ptr) & 0xff000000)>>24); + + b[2] = get_cs(&b[1],HDR_SZ); + + get_cs(&b[1],HDR_SZ); + + strUart.pu8Buf = b; + strUart.u16Sz = sizeof(b); + + if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart)) + { + M2M_ERR("write error\n"); + s8Ret = M2M_ERR_BUS_FAIL; + } + else + { + if(!nm_bus_get_chip_type()) + { + //check for the ack from the SAMD21 for the packet reception. + strUart.u16Sz = 1; + if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart)) + { + s8Ret = M2M_ERR_BUS_FAIL; + } + if(b[0] == 0xAC) + { + M2M_DBG("Successfully sent the UART reconfigure command\n"); + } + else + { + M2M_ERR("write error\n"); + s8Ret = M2M_ERR_BUS_FAIL; + } + } + } + + return s8Ret; +} +#endif +/* EOF */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmuart.h b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmuart.h new file mode 100644 index 000000000..2fdf9e56c --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/driver/source/nmuart.h @@ -0,0 +1,119 @@ +/** + * + * \file + * + * \brief This module contains WINC3400 UART protocol bus APIs implementation. + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _NMUART_H_ +#define _NMUART_H_ + +#include "common/include/nm_common.h" + +/* +* @fn nm_uart_sync_cmd +* @brief Check COM Port +* @return ZERO in case of success and M2M_ERR_BUS_FAIL in case of failure +*/ +sint8 nm_uart_sync_cmd(void); +/** +* @fn nm_uart_read_reg +* @brief Read register +* @param [in] u32Addr +* Register address +* @return Register value +*/ +uint32 nm_uart_read_reg(uint32 u32Addr); + +/** +* @fn nm_uart_reboot_cmd +* @brief Sends a command to the MCU to force the reboot of the WINC +* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure +* @version 1.0 +*/ +sint8 nm_uart_reboot_cmd(void); + +/** +* @fn nm_uart_read_reg_with_ret +* @brief Read register with error code return +* @param [in] u32Addr +* Register address +* @param [out] pu32RetVal +* Pointer to u32 variable used to return the read value +* @return ZERO in case of success and M2M_ERR_BUS_FAIL in case of failure +*/ +sint8 nm_uart_read_reg_with_ret(uint32 u32Addr, uint32* pu32RetVal); + +/** +* @fn nm_uart_write_reg +* @brief write register +* @param [in] u32Addr +* Register address +* @param [in] u32Val +* Value to be written to the register +* @return ZERO in case of success and M2M_ERR_BUS_FAIL in case of failure +*/ +sint8 nm_uart_write_reg(uint32 u32Addr, uint32 u32Val); + +/** +* @fn nm_uart_read_block +* @brief Read block of data +* @param [in] u32Addr +* Start address +* @param [out] puBuf +* Pointer to a buffer used to return the read data +* @param [in] u16Sz +* Number of bytes to read. The buffer size must be >= u16Sz +* @return ZERO in case of success and M2M_ERR_BUS_FAIL in case of failure +*/ +sint8 nm_uart_read_block(uint32 u32Addr, uint8 *puBuf, uint16 u16Sz); + +/** +* @fn nm_uart_write_block +* @brief Write block of data +* @param [in] u32Addr +* Start address +* @param [in] puBuf +* Pointer to the buffer holding the data to be written +* @param [in] u16Sz +* Number of bytes to write. The buffer size must be >= u16Sz +* @return ZERO in case of success and M2M_ERR_BUS_FAIL in case of failure +*/ +sint8 nm_uart_write_block(uint32 u32Addr, uint8 *puBuf, uint16 u16Sz); + +/** +* @fn nm_uart_reconfigure +* @brief Reconfigures the UART interface +* @param [in] ptr +* Pointer to a DWORD containing baudrate at this moment. +* @return ZERO in case of success and M2M_ERR_BUS_FAIL in case of failure +*/ +sint8 nm_uart_reconfigure(void *ptr); +#endif /* _NMI2C_H_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/programmer/programmer.h b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/programmer/programmer.h new file mode 100644 index 000000000..cbde6f718 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/programmer/programmer.h @@ -0,0 +1,53 @@ +/** + * + * \file + * + * \brief Programmer. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef IMAGE_DOWNLOADER_H_ +#define IMAGE_DOWNLOADER_H_ + +/** +* Include +*/ +#include "spi_flash_map.h" +#include "spi_flash/include/spi_flash.h" +#include "programmer_apis.h" + +#define ROOT_CERT_SIZE M2M_TLS_ROOTCER_FLASH_SZ + +#define programmer_get_flash_size() (((spi_flash_get_size()*1024)/8)*1024) +#define programmer_write(pu8Buf, u32Offset, u32Sz) spi_flash_write(pu8Buf, u32Offset, u32Sz) +#define programmer_erase(u32Offset, u32Sz) spi_flash_erase(u32Offset, u32Sz) +#define programmer_eraseall() programmer_erase(0, programmer_get_flash_size()) +#define programmer_read(pu8Buf, u32Offset, u32Sz) spi_flash_read(pu8Buf, u32Offset, u32Sz) + +#endif /* IMAGE_DOWNLOADER_H_ */ \ No newline at end of file diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/socket/include/m2m_socket_host_if.h b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/socket/include/m2m_socket_host_if.h new file mode 100644 index 000000000..1da993087 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/socket/include/m2m_socket_host_if.h @@ -0,0 +1,412 @@ +/** + * + * \file + * + * \brief BSD compatible socket interface internal types. + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef __M2M_SOCKET_HOST_IF_H__ +#define __M2M_SOCKET_HOST_IF_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +INCLUDES +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ + +#ifndef _BOOT_ +#ifndef _FIRMWARE_ +#include "socket/include/socket.h" +#else +#include "driver/include/m2m_types.h" +#endif +#endif + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +MACROS +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ + +#ifdef _FIRMWARE_ +#define HOSTNAME_MAX_SIZE (100) +#endif + +#define SSL_MAX_OPT_LEN HOSTNAME_MAX_SIZE + + + +#define SOCKET_CMD_INVALID 0x00 +/*!< + Invlaid Socket command value. +*/ + + +#define SOCKET_CMD_BIND 0x41 +/*!< + Socket Binding command value. +*/ + + +#define SOCKET_CMD_LISTEN 0x42 +/*!< + Socket Listening command value. +*/ + + +#define SOCKET_CMD_ACCEPT 0x43 +/*!< + Socket Accepting command value. +*/ + + +#define SOCKET_CMD_CONNECT 0x44 +/*!< + Socket Connecting command value. +*/ + + +#define SOCKET_CMD_SEND 0x45 +/*!< + Socket send command value. +*/ + + +#define SOCKET_CMD_RECV 0x46 +/*!< + Socket Recieve command value. +*/ + + +#define SOCKET_CMD_SENDTO 0x47 +/*!< + Socket sendTo command value. +*/ + + +#define SOCKET_CMD_RECVFROM 0x48 +/*!< + Socket RecieveFrom command value. +*/ + + +#define SOCKET_CMD_CLOSE 0x49 +/*!< + Socket Close command value. +*/ + + +#define SOCKET_CMD_DNS_RESOLVE 0x4A +/*!< + Socket DNS Resolve command value. +*/ + + +#define SOCKET_CMD_SSL_CONNECT 0x4B +/*!< + SSL-Socket Connect command value. +*/ + + +#define SOCKET_CMD_SSL_SEND 0x4C +/*!< + SSL-Socket Send command value. +*/ + + +#define SOCKET_CMD_SSL_RECV 0x4D +/*!< + SSL-Socket Recieve command value. +*/ + + +#define SOCKET_CMD_SSL_CLOSE 0x4E +/*!< + SSL-Socket Close command value. +*/ + + +#define SOCKET_CMD_SET_SOCKET_OPTION 0x4F +/*!< + Set Socket Option command value. +*/ + + +#define SOCKET_CMD_SSL_CREATE 0x50 +/*!< +*/ + + +#define SOCKET_CMD_SSL_SET_SOCK_OPT 0x51 + + +#define SOCKET_CMD_PING 0x52 + + + + + +#define PING_ERR_SUCCESS 0 +#define PING_ERR_DEST_UNREACH 1 +#define PING_ERR_TIMEOUT 2 + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +DATA TYPES +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ + + +/*! +* @brief +*/ +typedef struct{ + uint16 u16Family; + uint16 u16Port; + uint32 u32IPAddr; +}tstrSockAddr; + + +typedef sint8 SOCKET; +typedef tstrSockAddr tstrUIPSockAddr; + + + +/*! +@struct \ + tstrDnsReply + +@brief + DNS Reply, contains hostName and HostIP. +*/ +typedef struct{ + char acHostName[HOSTNAME_MAX_SIZE]; + uint32 u32HostIP; +}tstrDnsReply; + + +/*! +@brief +*/ +typedef struct{ + tstrSockAddr strAddr; + SOCKET sock; + uint8 u8Void; + uint16 u16SessionID; +}tstrBindCmd; + + +/*! +@brief +*/ +typedef struct{ + SOCKET sock; + sint8 s8Status; + uint16 u16SessionID; +}tstrBindReply; + + +/*! +* @brief +*/ +typedef struct{ + SOCKET sock; + uint8 u8BackLog; + uint16 u16SessionID; +}tstrListenCmd; + + +/*! +@struct \ + tstrSocketRecvMsg + +@brief Socket recv status. + + It is passed to the APPSocketEventHandler with SOCKET_MSG_RECV or SOCKET_MSG_RECVFROM message type + in a response to a user call to the recv or recvfrom. + If the received data from the remote peer is larger than the USER Buffer size (given at recv call), the data is + delivered to the user in a number of consecutive chunks according to the USER Buffer size. +*/ +typedef struct{ + SOCKET sock; + sint8 s8Status; + uint16 u16SessionID; +}tstrListenReply; + + +/*! +* @brief +*/ +typedef struct{ + tstrSockAddr strAddr; + SOCKET sListenSock; + SOCKET sConnectedSock; + uint16 u16Void; +}tstrAcceptReply; + + +/*! +* @brief +*/ +typedef struct{ + tstrSockAddr strAddr; + SOCKET sock; + uint8 u8SslFlags; + uint16 u16SessionID; +}tstrConnectCmd; + + +/*! +@struct \ + tstrConnectReply + +@brief + Connect Reply, contains sock number and error value +*/ +typedef struct{ + SOCKET sock; + sint8 s8Error; + uint16 u16AppDataOffset; + /*!< + In further packet send requests the host interface should put the user application + data at this offset in the allocated shared data packet. + */ +}tstrConnectReply; + + +/*! +@brief +*/ +typedef struct{ + SOCKET sock; + uint8 u8Void; + uint16 u16DataSize; + tstrSockAddr strAddr; + uint16 u16SessionID; + uint16 u16Void; +}tstrSendCmd; + + +/*! +@struct \ + tstrSendReply + +@brief + Send Reply, contains socket number and number of sent bytes. +*/ +typedef struct{ + SOCKET sock; + uint8 u8Void; + sint16 s16SentBytes; + uint16 u16SessionID; + uint16 u16Void; +}tstrSendReply; + + +/*! +* @brief +*/ +typedef struct{ + uint32 u32Timeoutmsec; + SOCKET sock; + uint8 u8Void; + uint16 u16SessionID; + uint16 u16BufLen; +}tstrRecvCmd; + + +/*! +@struct \ + tstrRecvReply +@brief +*/ +typedef struct{ + tstrSockAddr strRemoteAddr; + sint16 s16RecvStatus; + uint16 u16DataOffset; + SOCKET sock; + uint8 u8Void; + uint16 u16SessionID; +}tstrRecvReply; + + +/*! +* @brief +*/ +typedef struct{ + uint32 u32OptionValue; + SOCKET sock; + uint8 u8Option; + uint16 u16SessionID; +}tstrSetSocketOptCmd; + + +typedef struct{ + SOCKET sslSock; + uint8 __PAD24__[3]; +}tstrSSLSocketCreateCmd; + + +/*! +* @brief +*/ +typedef struct{ + SOCKET sock; + uint8 u8Option; + uint16 u16SessionID; + uint32 u32OptLen; + uint8 au8OptVal[SSL_MAX_OPT_LEN]; +}tstrSSLSetSockOptCmd; + + +/*! +*/ +typedef struct{ + uint32 u32DestIPAddr; + uint32 u32CmdPrivate; + uint16 u16PingCount; + uint8 u8TTL; + uint8 __PAD8__; +}tstrPingCmd; + + +typedef struct{ + uint32 u32IPAddr; + uint32 u32CmdPrivate; + uint32 u32RTT; + uint16 u16Success; + uint16 u16Fail; + uint8 u8ErrorCode; + uint8 __PAD24__[3]; +}tstrPingReply; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __M2M_SOCKET_HOST_IF_H__ */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/socket/include/socket.h b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/socket/include/socket.h new file mode 100644 index 000000000..6463d94f3 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/socket/include/socket.h @@ -0,0 +1,1740 @@ +/** + * + * \file + * + * \brief BSD compatible socket interface. + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +/**@defgroup SOCKETAPI SOCKET + */ + +#ifndef __SOCKET_H__ +#define __SOCKET_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +INCLUDES +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ + +#include "driver/include/m2m_types.h" + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +MACROS +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ +/**@defgroup SOCKETDEF Defines + * @ingroup SOCKETAPI + * The following list of macros are used to define constants used throughout the socket layer, and SSL Socket options. + * @{ */ + +#define HOSTNAME_MAX_SIZE 100 +/*!< + Maximum allowed size for a host domain name passed to the function gethostbyname @ref gethostbyname. + command value. Used with the setsocketopt function. + +*/ + +#define SOCKET_BUFFER_MAX_LENGTH 1400 +/*!< + Maximum allowed size for a socket data buffer. Used with @ref send socket + function to ensure that the buffer sent is within the allowed range. +*/ + +#define AF_INET 2 +/*!< + The AF_INET is the address family used for IPv4. An IPv4 transport address is specified with the @ref sockaddr_in structure. + (It is the only supported type for the current implementation.) +*/ + + +#define SOCK_STREAM 1 +/*!< + One of the IPv4 supported socket types for reliable connection-oriented stream connection. + Passed to the @ref socket function for the socket creation operation. +*/ + +#define SOCK_DGRAM 2 +/*!< + One of the IPv4 supported socket types for unreliable connectionless datagram connection. + Passed to the @ref socket function for the socket creation operation. +*/ + + +#define SOCKET_FLAGS_SSL 0x01 +/*!< + This flag shall be passed to the socket API for SSL session. +*/ + +#define TCP_SOCK_MAX (7) +/*!< + Maximum number of simultaneous TCP sockets. +*/ + +#define UDP_SOCK_MAX 4 +/*!< + Maximum number of simultaneous UDP sockets. +*/ + +#define MAX_SOCKET (TCP_SOCK_MAX + UDP_SOCK_MAX) +/*!< + Maximum number of simultaneous sockets. +*/ + +#define SOL_SOCKET 1 +/*!< + Socket option. + Used with the @ref setsockopt function +*/ + +#define SO_SET_UDP_SEND_CALLBACK 0x00 +/*!< + Socket option used by the application to enable/disable + the use of UDP send callbacks. + Used with the @ref setsockopt function. +*/ + +#define IP_ADD_MEMBERSHIP 0x01 +/*!< + Set Socket Option Add Membership command value. + Used with the @ref setsockopt function. +*/ + + +#define IP_DROP_MEMBERSHIP 0x02 +/*!< + Set Socket Option Drop Membership command value. + Used with the @ref setsockopt function. +*/ + + +// SSL Socket options + +#define SOL_SSL_SOCKET 2 +/*!< + SSL Socket option level. + Used with the @ref setsockopt function +*/ + + +#define SO_SSL_BYPASS_X509_VERIF 0x01 +/*!< + Allow an opened SSL socket to bypass the X509 certificate + verification process. + It is highly recommended NOT to use this socket option in production + software applications. It is intended for debugging and testing + purposes only.\n + The option value should be cast to int type and it is handled + as a boolean flag. +*/ + + +#define SO_SSL_SNI 0x02 +/*!< + Set the Server Name Indicator (SNI) for an SSL socket. The + SNI is a NULL terminated string containing the server name + associated with the connection. It must not exceed the size + of HOSTNAME_MAX_SIZE. If the SNI is not a null string, then + TLS Client Hello messages will include the SNI extension. +*/ + + +#define SO_SSL_ENABLE_SESSION_CACHING 0x03 +/*!< + Allow the TLS to cache the session information for fast + TLS session establishment in future connections using the + TLS Protocol session resume features.\n + The option value should be cast to int type and it is handled + as a boolean flag. + +*/ + +#define SO_SSL_ENABLE_CERTNAME_VALIDATION 0x04 +/*!< + Enable internal validation of server name against the server's + certificate subject common name. If there is no server name + provided (via the SO_SSL_SNI option), setting this option does + nothing.\n + The option value should be cast to int type and it is handled + as a boolean flag. +*/ + +#define SO_SSL_ENABLE_SNI_VALIDATION 0x04 +/*!< + Legacy name for @ref SO_SSL_ENABLE_CERTNAME_VALIDATION.\n + The option value should be cast to int type and it is handled + as a boolean flag. +*/ + //@} + +/** @defgroup SSLCipherSuiteID TLS Cipher Suite IDs + * @ingroup TLSDefines + * The following list of macros defined the list of supported TLS Cipher suites. + * Each MACRO defines a single Cipher suite. + * @sa m2m_ssl_set_active_ciphersuites + * @{ + */ + +#define SSL_CIPHER_RSA_WITH_AES_128_CBC_SHA NBIT0 +#define SSL_CIPHER_RSA_WITH_AES_128_CBC_SHA256 NBIT1 +#define SSL_CIPHER_DHE_RSA_WITH_AES_128_CBC_SHA NBIT2 +#define SSL_CIPHER_DHE_RSA_WITH_AES_128_CBC_SHA256 NBIT3 +#define SSL_CIPHER_RSA_WITH_AES_128_GCM_SHA256 NBIT4 +#define SSL_CIPHER_DHE_RSA_WITH_AES_128_GCM_SHA256 NBIT5 +#define SSL_CIPHER_RSA_WITH_AES_256_CBC_SHA NBIT6 +#define SSL_CIPHER_RSA_WITH_AES_256_CBC_SHA256 NBIT7 +#define SSL_CIPHER_DHE_RSA_WITH_AES_256_CBC_SHA NBIT8 +#define SSL_CIPHER_DHE_RSA_WITH_AES_256_CBC_SHA256 NBIT9 +#define SSL_CIPHER_ECDHE_RSA_WITH_AES_128_CBC_SHA NBIT10 +#define SSL_CIPHER_ECDHE_RSA_WITH_AES_256_CBC_SHA NBIT11 +#define SSL_CIPHER_ECDHE_RSA_WITH_AES_128_CBC_SHA256 NBIT12 +#define SSL_CIPHER_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 NBIT13 +#define SSL_CIPHER_ECDHE_RSA_WITH_AES_128_GCM_SHA256 NBIT14 +#define SSL_CIPHER_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 NBIT15 + + +#define SSL_ECC_ONLY_CIPHERS \ +(\ + SSL_CIPHER_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 | \ + SSL_CIPHER_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 \ +) +/*!< + All supported ECC Ciphers. These ciphers are turned off by default at startup. + The application may enable them if it has an ECC math engine (like ATECC508). +*/ + + +#define SSL_DEFAULT_CIPHERS \ +(\ + SSL_CIPHER_RSA_WITH_AES_128_CBC_SHA | \ + SSL_CIPHER_RSA_WITH_AES_128_CBC_SHA256 | \ + SSL_CIPHER_DHE_RSA_WITH_AES_128_CBC_SHA | \ + SSL_CIPHER_DHE_RSA_WITH_AES_128_CBC_SHA256 | \ + SSL_CIPHER_RSA_WITH_AES_128_GCM_SHA256 | \ + SSL_CIPHER_DHE_RSA_WITH_AES_128_GCM_SHA256 | \ + SSL_CIPHER_RSA_WITH_AES_256_CBC_SHA | \ + SSL_CIPHER_RSA_WITH_AES_256_CBC_SHA256 | \ + SSL_CIPHER_DHE_RSA_WITH_AES_256_CBC_SHA | \ + SSL_CIPHER_DHE_RSA_WITH_AES_256_CBC_SHA256 \ +) +/*!< + All supported Non-ECC Ciphers. This is the default active group after startup. + Note that firmware may support only a subset of these. +*/ + //@} + +/**@defgroup SOCKETBYTEORDER Byte Order + * @ingroup SOCKETAPI + * The following list of macros are used to convert between host representation and network byte order. + * @{ */ +#ifdef _NM_BSP_BIG_END +#define _htonl(m) (m) +/*!< + Convert a 4-byte integer from the Host representation to Network byte order (Host is BE). +*/ +#define _htons(A) (A) +/*!< + Convert a 2-byte integer (short) from Host representation to Network byte order (Host is BE). +*/ +#else +#define _htonl(m) \ + (uint32)(((uint32)(m << 24)) | ((uint32)((m & 0x0000FF00) << 8)) | ((uint32)((m & 0x00FF0000) >> 8)) | ((uint32)(((uint32)m) >> 24))) +/*!< + Convert a 4-byte integer from Host representation to Network byte order (Host is LE). +*/ + +#define _htons(A) (uint16)((((uint16) (A)) << 8) | (((uint16) (A)) >> 8)) +/*!< + Convert a 2-byte integer (short) from Host representation to Network byte order (Host is LE). +*/ +#endif + + +#define _ntohl _htonl +/*!< + Convert a 4-byte integer from Network byte order to Host representation. +*/ + + +#define _ntohs _htons +/*!< + Convert a 2-byte integer from Network byte order to Host representation. +*/ + //@} + +/************** +Socket Errors +**************/ +/**@defgroup SocketErrorCode Error Codes + * @ingroup SOCKETAPI + * The following list of macros are used to define the possible error codes. + * Errors are listed in numerical order with the error macro name. + * @{ + */ +#define SOCK_ERR_NO_ERROR 0 +/*!< + Successful socket operation. This code is also used with event @ref SOCKET_MSG_RECV if a socket connection is closed. + In that case, the application should call @ref close(). +*/ + + +#define SOCK_ERR_INVALID_ADDRESS -1 +/*!< + Socket address is invalid. The socket operation cannot be completed successfully without specifying a valid address + For example: bind is called without specifying a port number +*/ + + +#define SOCK_ERR_ADDR_ALREADY_IN_USE -2 +/*!< + Socket operation cannot bind on the given address. Only one IP address per socket, and one socket per IP address is permitted - + any attempt for a new socket to bind with an IP address already bound to another open socket will return the following error code. +*/ + + +#define SOCK_ERR_MAX_TCP_SOCK -3 +/*!< + Exceeded the maximum number of TCP sockets. A maximum number of TCP sockets opened simultaneously is defined through TCP_SOCK_MAX. + It is not permitted to exceed that number at socket creation. Identifies that @ref socket operation failed. +*/ + + +#define SOCK_ERR_MAX_UDP_SOCK -4 +/*!< + Exceeded the maximum number of UDP sockets. A maximum number of UDP sockets opened simultaneously is defined through UDP_SOCK_MAX. + It is not permitted to exceed that number at socket creation. Identifies that @ref socket operation failed +*/ + + +#define SOCK_ERR_INVALID_ARG -6 +/*!< + An invalid argument is passed to a socket function. Identifies that @ref socket operation failed +*/ + + +#define SOCK_ERR_MAX_LISTEN_SOCK -7 +/*!< + Exceeded the maximum number of TCP passive listening sockets. + Identifies that @ref listen operation failed. +*/ + + +#define SOCK_ERR_INVALID -9 +/*!< + The requested socket operation is not valid in the current socket state. + For example: @ref accept is called on a TCP socket before @ref bind or @ref listen. +*/ + + +#define SOCK_ERR_ADDR_IS_REQUIRED -11 +/*!< + Destination address is required. Failure to provide the socket address required for the socket operation to be completed. + The @ref sendto function requires a destination address to send data. +*/ + + +#define SOCK_ERR_CONN_ABORTED -12 +/*!< + The socket is closed (reset) by the peer. If this error is received, the application should call @ref close(). +*/ + + +#define SOCK_ERR_TIMEOUT -13 +/*!< + The socket pending operation has timed out. The socket remains open. +*/ + + +#define SOCK_ERR_BUFFER_FULL -14 +/*!< + No buffer space available to be used for the requested socket operation. +*/ + + //@} + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +DATA TYPES +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ + +/** @defgroup SocketEnums Enumeration/Typedefs + * @ingroup SOCKETAPI + * Specific Enumeration-typedefs used for socket operations + * @{ */ +/*! +@typedef \ + SOCKET + +@brief + Definition for socket handler data type. + Socket ID,used with all socket operations to uniquely identify the socket handler. + The ID is uniquely assigned at socket creation when calling @ref socket operation. +*/ +typedef sint8 SOCKET; + //@} + +/*! +@struct \ + in_addr + +@brief + IPv4 address representation. + + This structure is used as a placeholder for IPV4 address in other structures. +@see + sockaddr_in +*/ +typedef struct{ + uint32 s_addr; + /*!< + Network Byte Order representation of the IPv4 address. For example, + the address "192.168.0.10" is represented as 0x0A00A8C0. + */ +}in_addr; + + +/*! +@struct \ + sockaddr + +@brief + Generic socket address structure. + +@see \ + sockaddr_in +*/ +struct sockaddr{ + uint16 sa_family; + /*!< +Socket address family. + */ + uint8 sa_data[14]; + /*!< + Maximum size of all the different socket address structures. + */ +}; + +/*! +@struct \ + sockaddr_in + +@brief + Socket address structure for IPV4 addresses. Used to specify socket address information to connect to. + Can be cast to @ref sockaddr structure. +*/ +struct sockaddr_in{ + uint16 sin_family; + /*!< + Specifies the address family(AF). + Members of AF_INET address family are IPv4 addresses. + Hence,the only supported value for this is AF_INET. + */ + uint16 sin_port; + /*!< + Port number of the socket. + Network sockets are identified by a pair of IP addresses and port number. + Must be set in the Network Byte Order format , @ref _htons (e.g. _htons(80)). + Can NOT have zero value. + */ + in_addr sin_addr; + /*!< + IP Address of the socket. + The IP address is of type @ref in_addr structure. + Can be set to "0" to accept any IP address for server operation. + */ + uint8 sin_zero[8]; + /*!< + Padding to make structure the same size as @ref sockaddr. + */ +}; + +/**@addtogroup SocketEnums + * @{ */ +/*! +@enum \ + tenuSocketCallbackMsgType + +@brief + Asynchronous APIs make use of callback functions in-order to return back the results once the corresponding socket operation is completed. + Hence resuming the normal execution of the application code while the socket operation returns the results. + Callback functions expect event messages to be passed in, in-order to identify the operation they're returning the results for. + The following enum identifies the type of events that are received in the callback function. + + Application Use: + In order for application developers to handle the pending events from the network controller through the callback functions, + a function call must be made to the function @ref m2m_wifi_handle_events at least once for each socket operation. + +@see bind +@see listen +@see accept +@see connect +@see send +@see recv + +*/ +typedef enum{ + SOCKET_MSG_BIND = 1, + /*!< + Bind socket event. + */ + SOCKET_MSG_LISTEN, + /*!< + Listen socket event. + */ + SOCKET_MSG_DNS_RESOLVE, + /*!< + DNS Resolution event. + */ + SOCKET_MSG_ACCEPT, + /*!< + Accept socket event. + */ + SOCKET_MSG_CONNECT, + /*!< + Connect socket event. + */ + SOCKET_MSG_RECV, + /*!< + Receive socket event. + */ + SOCKET_MSG_SEND, + /*!< + Send socket event. + */ + SOCKET_MSG_SENDTO, + /*!< + Sendto socket event. + */ + SOCKET_MSG_RECVFROM + /*!< + Recvfrom socket event. + */ +}tenuSocketCallbackMsgType; +// @} + + +/*! +@struct \ + tstrSocketBindMsg + +@brief Socket bind status. + + An asynchronous call to the @ref bind socket operation, returns information through this structure in response. + This structure together with the event @ref SOCKET_MSG_BIND are passed in parameters to the callback function. +@see + bind + +*/ +typedef struct{ + sint8 status; + /*!< + The result of the bind operation. + Holding a value of ZERO for a successful bind or otherwise a negative + error code corresponding to @ref SocketErrorCode. + */ +}tstrSocketBindMsg; + + +/*! +@struct \ + tstrSocketListenMsg + +@brief Socket listen status. + + Socket listen information is returned through this structure in response to the asynchronous call to the @ref listen function. + This structure together with the event @ref SOCKET_MSG_LISTEN are passed-in parameters to the callback function. +@see + listen +*/ +typedef struct{ + sint8 status; + /*!< + Holding a value of ZERO for a successful listen or otherwise a negative + error code corresponding to @ref SocketErrorCode. + */ +}tstrSocketListenMsg; + + + +/*! +@struct \ + tstrSocketAcceptMsg + +@brief Socket accept status. + + Socket accept information is returned through this structure in response to the asynchronous call to the @ref accept function. + This structure together with the event @ref SOCKET_MSG_ACCEPT are passed-in parameters to the callback function. +*/ +typedef struct{ + SOCKET sock; + /*!< + On a successful @ref accept operation, the return information is the socket ID for the accepted connection with the remote peer. + Otherwise a negative error code is returned to indicate failure of the accept operation. + */ + struct sockaddr_in strAddr; + /*!< + Socket address structure for the remote peer. + */ +}tstrSocketAcceptMsg; + + +/*! +@struct \ + tstrSocketConnectMsg + +@brief Socket connect status. + + Socket connect information is returned through this structure in response to the asynchronous call to the @ref connect socket function. + This structure together with the event @ref SOCKET_MSG_CONNECT are passed-in parameters to the callback function. + If the application receives this structure with a negative value in s8Error, the application should call @ref close(). +*/ +typedef struct{ + SOCKET sock; + /*!< + Socket ID referring to the socket passed to the connect function call. + */ + sint8 s8Error; + /*!< + Connect error code. + Holding a value of ZERO for a successful connect or otherwise a negative + error code corresponding to the type of error. + */ +}tstrSocketConnectMsg; + + +/*! +@struct \ + tstrSocketRecvMsg + +@brief Socket recv status. + + Socket receive information is returned through this structure in response to the asynchronous call to the recv or recvfrom socket functions. + This structure together with the events @ref SOCKET_MSG_RECV or @ref SOCKET_MSG_RECVFROM are passed-in parameters to the callback function. +@remark + In case the received data from the remote peer is larger than the USER buffer size defined during the asynchronous call to the @ref recv function, + only data up to the buffer size is delivered to the user. The user must call @ref recv again in order to receive the remaining data. + A negative or zero buffer size indicates an error with the following code: + @ref SOCK_ERR_NO_ERROR : Socket connection closed. The application should now call @ref close(). + @ref SOCK_ERR_CONN_ABORTED : Socket connection aborted. The application should now call @ref close(). + @ref SOCK_ERR_TIMEOUT : Socket receive timed out. The socket connection remains open. +*/ +typedef struct{ + uint8 *pu8Buffer; + /*!< + Pointer to the USER buffer (passed to @ref recv and @ref recvfrom function) containing the received data chunk. + */ + sint16 s16BufferSize; + /*!< + The received data chunk size. + Holds a negative value if there is a receive error or ZERO on success upon reception of close socket message. + */ + uint16 u16RemainingSize; + /*!< + The number of bytes remaining in the current @ref recv operation. + */ + struct sockaddr_in strRemoteAddr; + /*!< + Socket address structure for the remote peer. It is valid for @ref SOCKET_MSG_RECVFROM event. + */ +}tstrSocketRecvMsg; + +/**@addtogroup SocketEnums + * @{ */ +/*! +@typedef \ + tpfAppSocketCb + +@brief + The main socket application callback function. Applications register their main socket application callback through this function by calling @ref registerSocketCallback. + In response to events received, the following callback function is called to handle the corresponding asynchronous function called. Example: @ref bind, @ref connect,...etc. + +@param [in] sock + Socket ID for the callback. + + The socket callback function is called whenever a new event is received in response + to socket operations. + +@param [in] u8Msg + Socket event type. Possible values are: + - @ref SOCKET_MSG_BIND + - @ref SOCKET_MSG_LISTEN + - @ref SOCKET_MSG_ACCEPT + - @ref SOCKET_MSG_CONNECT + - @ref SOCKET_MSG_RECV + - @ref SOCKET_MSG_SEND + - @ref SOCKET_MSG_SENDTO + - @ref SOCKET_MSG_RECVFROM + +@param [in] pvMsg + Pointer to message structure. Existing types are: + - tstrSocketBindMsg + - tstrSocketListenMsg + - tstrSocketAcceptMsg + - tstrSocketConnectMsg + - tstrSocketRecvMsg + +@see + tenuSocketCallbackMsgType + tstrSocketRecvMsg + tstrSocketConnectMsg + tstrSocketAcceptMsg + tstrSocketListenMsg + tstrSocketBindMsg +*/ +typedef void (*tpfAppSocketCb) (SOCKET sock, uint8 u8Msg, void * pvMsg); + + +/*! +@typedef \ + tpfAppResolveCb + +@brief + DNS resolution callback function. + Applications requiring DNS resolution should register their callback through this function by calling @ref registerSocketCallback. + The following callback is triggered in response to an asynchronous call to the @ref gethostbyname function (DNS Resolution callback). + +@param [in] pu8DomainName + Domain name of the host. + +@param [in] u32ServerIP + Server IPv4 address encoded in Network byte order format. If it is Zero, then the DNS resolution failed. +*/ +typedef void (*tpfAppResolveCb) (uint8* pu8DomainName, uint32 u32ServerIP); + +/*! +@typedef \ + tpfPingCb + +@brief PING Callback + + The function delivers the ping statistics for the sent ping triggered by calling + @ref m2m_ping_req. + +@param [in] u32IPAddr + Destination IP. + +@param [in] u32RTT + Round Trip Time. + +@param [in] u8ErrorCode + Ping error code. It may be one of: + - PING_ERR_SUCCESS + - PING_ERR_DEST_UNREACH + - PING_ERR_TIMEOUT +*/ +typedef void (*tpfPingCb)(uint32 u32IPAddr, uint32 u32RTT, uint8 u8ErrorCode); + + /**@}*/ +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +FUNCTION PROTOTYPES +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ +/** \defgroup SocketAPI Functions + * @ingroup SOCKETAPI + */ + + /**@{*/ +/*! +@fn \ + NMI_API void socketInit(void); + The function performs the necessary initialization for the socket library through the following steps: + - A check made by the global variable gbSocketInit, ensuring that initialization for sockets is performed only once, + in-order to prevent reseting the socket instances already created in the global socket array (gastrSockets). + - Zero initializations to the global socket array (gastrSockets), which holds the list of TCP sockets. + - Registers the socket (Host Interface)hif callback function through the call to the hif_register_cb function. + This facilitates handling all of the socket related functions received through interrupts from the firmware. + +@return void + +@remarks + This initialization function must be invoked before any socket operation is performed. + No error codes from this initialization function since the socket array is statically allocated based on the maximum number of + sockets @ref MAX_SOCKET which is tuned to the systems capability. +\section SocketExample1 Example +This example demonstrates the use of the socketInit for socket initialization for an mqtt chat application. + \code + tstrWifiInitParam param; + int8_t ret; + char topic[strlen(MAIN_CHAT_TOPIC) + MAIN_CHAT_USER_NAME_SIZE + 1]; + + //Initialize the board. + system_init(); + + //Initialize the UART console. + configure_console(); + + // Initialize the BSP. + nm_bsp_init(); + + ---------- + + // Initialize socket interface. + socketInit(); + registerSocketCallback(socket_event_handler, socket_resolve_handler); + + // Connect to router. + m2m_wifi_connect((char *)DEFAULT_SSID, sizeof(DEFAULT_SSID), + DEFAULT_AUTH, (char *)DEFAULT_KEY, M2M_WIFI_CH_ALL); + +\endcode +*/ +NMI_API void socketInit(void); + +/*! +@fn \ + NMI_API void socketDeinit(void); + +@brief Socket Layer De-initialization + + The function performs the necessary cleanup for the socket library static data + It must be invoked only after all desired socket operations have been performed on any active sockets. +*/ +NMI_API void socketDeinit(void); +/*! +@fn \ + NMI_API void registerSocketCallback(tpfAppSocketCb socket_cb, tpfAppResolveCb resolve_cb); + Register two callback functions one for asynchronous socket events and the other one for DNS callback registering function. + The registered callback functions are used to retrieve information in response to the asynchronous socket functions called. +@param [in] socket_cb + Assignment of callback function to the global callback @ref tpfAppSocketCb gpfAppSocketCb. Delivers + socket messages to the host application. In response to the asynchronous function calls, such as @ref bind + @ref listen @ref accept @ref connect + +@param [in] resolve_cb + Assignment of callback function to the global callback @ref tpfAppResolveCb gpfAppResolveCb. + Used for DNS resolving functionality. The DNS resolving technique is determined by the application + registering the callback. + NULL is assigned when DNS resolution is not required. + +@return void +@remarks + If any of the socket functionality is not to be used, NULL is passed in as a parameter. + It must be invoked after @ref socketInit and before other socket layer operations. + +\section SocketExample2 Example + This example demonstrates the use of the registerSocketCallback to register a socket callback function with DNS resolution CB set to null + for a simple UDP server example. + \code + tstrWifiInitParam param; + int8_t ret; + struct sockaddr_in addr; + + // Initialize the board + system_init(); + + //Initialize the UART console. + configure_console(); + + // Initialize the BSP. + nm_bsp_init(); + + // Initialize socket address structure. + addr.sin_family = AF_INET; + addr.sin_port = _htons(MAIN_WIFI_M2M_SERVER_PORT); + addr.sin_addr.s_addr = _htonl(MAIN_WIFI_M2M_SERVER_IP); + + // Initialize Wi-Fi parameters structure. + memset((uint8_t *)¶m, 0, sizeof(tstrWifiInitParam)); + + // Initialize Wi-Fi driver with data and status callbacks. + param.pfAppWifiCb = wifi_cb; + ret = m2m_wifi_init(¶m); + if (M2M_SUCCESS != ret) { + printf("main: m2m_wifi_init call error!(%d)\r\n", ret); + while (1) { + } + } + + // Initialize socket module + socketInit(); + registerSocketCallback(socket_cb, NULL); + + // Connect to router. + m2m_wifi_connect((char *)DEFAULT_SSID, sizeof(DEFAULT_SSID), DEFAULT_AUTH, (char *)DEFAULT_KEY, M2M_WIFI_CH_ALL); + \endcode +*/ +NMI_API void registerSocketCallback(tpfAppSocketCb socket_cb, tpfAppResolveCb resolve_cb); +/*! +@fn \ + NMI_API SOCKET socket(uint16 u16Domain, uint8 u8Type, uint8 u8Flags); + Synchronous socket allocation function based on the specified socket type. Created sockets are non-blocking and their possible types are either TCP or a UDP sockets. + The maximum allowed number of TCP sockets is @ref TCP_SOCK_MAX sockets while the maximum number of UDP sockets that can be created simultaneously is @ref UDP_SOCK_MAX sockets. + +@param [in] u16Domain + Socket family. The only allowed value is AF_INET (IPv4.0) for TCP/UDP sockets. + +@param [in] u8Type + Socket type. Allowed values are: + - [SOCK_STREAM](@ref SOCK_STREAM) + - [SOCK_DGRAM](@ref SOCK_DGRAM) + +@param [in] u8Flags + Used to specify the socket creation flags. It shall be set to zero for normal TCP/UDP sockets, + or [SOCKET_FLAGS_SSL](@ref SOCKET_FLAGS_SSL) if the socket is used for SSL session. The use of the flag + [SOCKET_FLAGS_SSL](@ref SOCKET_FLAGS_SSL) has no meaning in case of UDP sockets. + +@pre + The @ref socketInit function must be called once at the beginning of the application to initialize the socket handler. + before any call to the socket function can be made. + +@see + connect + bind + listen + accept + recv + recvfrom + send + sendto + close + setsockopt + getsockopt + +@return + On successful socket creation, a non-blocking socket type is created and a socket ID is returned + In case of failure the function returns a negative value, identifying one of the socket error codes defined. + For example: @ref SOCK_ERR_INVALID for invalid argument or + @ref SOCK_ERR_MAX_TCP_SOCK if the number of TCP allocated sockets exceeds the number of available sockets. + +@remarks + The socket function must be called before any other related socket functions "e.g. send, recv, close ..etc" +\section SocketExample3 Example + This example demonstrates the use of the socket function to allocate the socket, returning the socket handler to be used for other +socket operations. Socket creation is dependent on the socket type. +\subsection sub1 UDP example +@code + SOCKET UdpServerSocket = -1; + + UdpServerSocket = socket(AF_INET, SOCK_DGRAM, 0); + +@endcode +\subsection sub2 TCP example +@code + static SOCKET tcp_client_socket = -1; + + tcp_client_socket = socket(AF_INET, SOCK_STREAM, 0)); +@endcode +*/ +NMI_API SOCKET socket(uint16 u16Domain, uint8 u8Type, uint8 u8Flags); +/*! +\fn \ + NMI_API sint8 bind(SOCKET sock, struct sockaddr *pstrAddr, uint8 u8AddrLen); + Asynchronous bind function associates the provided address and local port to the socket. + The function can be used with both TCP and UDP sockets. It is mandatory to call the @ref bind function before starting any UDP or TCP server operation. + Upon socket bind completion, the application will receive a @ref SOCKET_MSG_BIND message in the socket callback. +@param [in] sock + Socket ID, must hold a non negative value. + A negative value will return a socket error @ref SOCK_ERR_INVALID_ARG. Indicating that an invalid argument is passed in. + +@param [in] pstrAddr + Pointer to socket address structure "sockaddr_in" + [sockaddr_in](@ref sockaddr_in) + + +@param [in] u8AddrLen + Size of the given socket address structure in bytes. + +@pre + The socket function must be called to allocate a socket before passing the socket ID to the bind function. + +@see socket +@see connect +@see listen +@see accept +@see recv +@see recvfrom +@see send +@see sendto + +@return + The function returns ZERO for successful operations and a negative value otherwise. + The possible error values are: + - [SOCK_ERR_NO_ERROR](@ref SOCK_ERR_NO_ERROR) + Indicating that the operation was successful. + + - [SOCK_ERR_INVALID_ARG](@ref SOCK_ERR_INVALID_ARG) + Indicating passing invalid arguments such as negative socket ID or NULL socket address structure. + + - [SOCK_ERR_INVALID](@ref SOCK_ERR_INVALID) + Indicate socket bind failure. +\section SocketExample4 Example + This example demonstrates the call of the bind socket operation after a successful socket operation. +@code + struct sockaddr_in addr; + SOCKET udpServerSocket =-1; + int ret = -1; + + if(udpServerSocket == -1) + { + udpServerSocket = socket(AF_INET,SOCK_DGRAM,0); + if(udpServerSocket >= 0) + { + addr.sin_family = AF_INET; + addr.sin_port = _htons(UDP_SERVER_PORT); + addr.sin_addr.s_addr = 0; + ret = bind(udpServerSocket,(struct sockaddr*)&addr,sizeof(addr)); + + if(ret == 0) + printf("Bind success!\n"); + else + { + printf("Bind Failed. Error code = %d\n",ret); + close(udpServerSocket); + } + else + { + printf("UDP Server Socket Creation Failed\n"); + return; + } + } +@endcode +*/ +NMI_API sint8 bind(SOCKET sock, struct sockaddr *pstrAddr, uint8 u8AddrLen); +/*! +@fn \ + NMI_API sint8 listen(SOCKET sock, uint8 backlog); + + After successfully binding a socket to an IP address and port on the system, start listening passively for incoming connections. + The socket must be bound on a local port or the listen operation fails. + Upon the call to the asynchronous listen function, response is received through the event @ref SOCKET_MSG_LISTEN + in the socket callback. + + A successful listen means the TCP server operation is active. If a connection is accepted, then the application socket callback function is + notified with the new connected socket through the event @ref SOCKET_MSG_ACCEPT. Hence there is no need to call the @ref accept function + after calling @ref listen. + + After a connection is accepted, the user is then required to call @ref recv to receive any packets transmitted by the remote host or to recieve notification of socket connection + termination. +@param [in] sock + Socket ID, must hold a non negative value. + A negative value will return a socket error @ref SOCK_ERR_INVALID_ARG. Indicating that an invalid argument is passed in. + +@param [in] backlog + Not used by the current implementation. + +@pre + The bind function must be called to assign the port number and IP address to the socket before the listen operation. + +@see bind +@see accept +@see recv +@see recvfrom +@see send +@see sendto + +@return + The function returns ZERO for successful operations and a negative value otherwise. + The possible error values are: + - [SOCK_ERR_NO_ERROR](@ref SOCK_ERR_NO_ERROR) + Indicating that the operation was successful. + + - [SOCK_ERR_INVALID_ARG](@ref SOCK_ERR_INVALID_ARG) + Indicating invalid arguments were passed, such as negative socket ID. + + - [SOCK_ERR_INVALID](@ref SOCK_ERR_INVALID) + Indicate socket listen failure. +\section SocketExample5 Example +This example demonstrates the call of the listen socket operation after a successful socket operation. +@code + static void TCP_Socketcallback(SOCKET sock, uint8 u8Msg, void * pvMsg) + { + int ret =-1; + + switch(u8Msg) + { + case SOCKET_MSG_BIND: + { + tstrSocketBindMsg *pstrBind = (tstrSocketBindMsg*)pvMsg; + if(pstrBind != NULL) + { + if(pstrBind->status == 0) + { + ret = listen(sock, 0); + + if(ret <0) + printf("Listen failure! Error = %d\n",ret); + } + else + { + M2M_ERR("bind Failure!\n"); + close(sock); + } + } + } + break; + + case SOCKET_MSG_LISTEN: + { + + tstrSocketListenMsg *pstrListen = (tstrSocketListenMsg*)pvMsg; + if(pstrListen != NULL) + { + if(pstrListen->status == 0) + { + ret = accept(sock,NULL,0); + } + else + { + M2M_ERR("listen Failure!\n"); + close(sock); + } + } + } + break; + + case SOCKET_MSG_ACCEPT: + { + tstrSocketAcceptMsg *pstrAccept = (tstrSocketAcceptMsg*)pvMsg; + + if(pstrAccept->sock >= 0) + { + TcpNotificationSocket = pstrAccept->sock; + recv(pstrAccept->sock,gau8RxBuffer,sizeof(gau8RxBuffer),TEST_RECV_TIMEOUT); + } + else + { + M2M_ERR("accept failure\n"); + } + } + break; + + default: + break; + } + } + +@endcode +*/ +NMI_API sint8 listen(SOCKET sock, uint8 backlog); +/*! +@fn \ + NMI_API sint8 accept(SOCKET sock, struct sockaddr *addr, uint8 *addrlen); + The function has no current implementation. An empty deceleration is used to prevent errors when legacy application code is used. + As it has no effect, it can be safely removed from any application using it. +@param [in] sock + Socket ID, must hold a non negative value. + A negative value will return a socket error @ref SOCK_ERR_INVALID_ARG. Indicating that an invalid argument is passed in. +@param [in] addr + Not used in the current implementation. + +@param [in] addrlen + Not used in the current implementation. + +@return + The function returns ZERO for successful operations and a negative value otherwise. + The possible error values are: + - [SOCK_ERR_NO_ERROR](@ref SOCK_ERR_NO_ERROR) + Indicating that the operation was successful. + + - [SOCK_ERR_INVALID_ARG](@ref SOCK_ERR_INVALID_ARG) + Indicating passing invalid arguments such as negative socket ID. +*/ +NMI_API sint8 accept(SOCKET sock, struct sockaddr *addr, uint8 *addrlen); +/*! +@fn \ + NMI_API sint8 connect(SOCKET sock, struct sockaddr *pstrAddr, uint8 u8AddrLen); + Establishes a TCP connection with a remote server. + The asynchronous connect function must be called after receiving a valid socket ID from the @ref socket function. + The application socket callback function is notified of the result of the connection attempt through the event @ref SOCKET_MSG_CONNECT, + along with a structure @ref tstrSocketConnectMsg. + If socket connection fails, the application should call @ref close(). + A successful connect means the TCP session is active. The application is then required to make a call to the @ref recv function + to receive any packets transmitted by the remote server, unless the application is interrupted by a notification of socket connection + termination. +@param [in] sock + Socket ID, must hold a non negative value. + A negative value will return a socket error @ref SOCK_ERR_INVALID_ARG. Indicating that an invalid argument is passed in. + +@param [in] pstrAddr + Address of the remote server. + +@param [in] u8AddrLen + Size of the given socket address structure in bytes. + Not currently used, implemented for BSD compatibility only. +@pre + The socket function must be called to allocate a TCP socket before passing the socket ID to the bind function. + If the socket is not bound, you do NOT have to call bind before the "connect" function. + +@see + socket + recv + send + close + +@return + The function returns ZERO for successful operations and a negative value otherwise. + The possible error values are: + - [SOCK_ERR_NO_ERROR](@ref SOCK_ERR_NO_ERROR) + Indicating that the operation was successful. + + - [SOCK_ERR_INVALID_ARG](@ref SOCK_ERR_INVALID_ARG) + Indicating passing invalid arguments such as negative socket ID or NULL socket address structure. + + - [SOCK_ERR_INVALID](@ref SOCK_ERR_INVALID) + Indicate socket connect failure. +\section SocketExample6 Example + The example demonstrates a TCP application, showing how the asynchronous call to the connect function is made through the main function and how the + callback function handles the @ref SOCKET_MSG_CONNECT event. +\subsection sub3 Main Function +@code + struct sockaddr_in Serv_Addr; + SOCKET TcpClientSocket =-1; + int ret = -1 + + TcpClientSocket = socket(AF_INET,SOCK_STREAM,0); + Serv_Addr.sin_family = AF_INET; + Serv_Addr.sin_port = _htons(1234); + Serv_Addr.sin_addr.s_addr = inet_addr(SERVER); + printf("Connected to server via socket %u\n",TcpClientSocket); + + do + { + ret = connect(TcpClientSocket,(sockaddr_in*)&Serv_Addr,sizeof(Serv_Addr)); + if(ret != 0) + { + printf("Connection Error\n"); + } + else + { + printf("Connection successful.\n"); + break; + } + }while(1) +@endcode +\subsection sub4 Socket Callback +@code + if(u8Msg == SOCKET_MSG_CONNECT) + { + tstrSocketConnectMsg *pstrConnect = (tstrSocketConnectMsg*)pvMsg; + if(pstrConnect->s8Error == 0) + { + uint8 acBuffer[GROWL_MSG_SIZE]; + uint16 u16MsgSize; + + printf("Connect success!\n"); + + u16MsgSize = FormatMsg(u8ClientID, acBuffer); + send(sock, acBuffer, u16MsgSize, 0); + recv(pstrNotification->Socket, (void*)au8Msg,GROWL_DESCRIPTION_MAX_LENGTH, GROWL_RX_TIMEOUT); + u8Retry = GROWL_CONNECT_RETRY; + } + else + { + M2M_DBG("Connection Failed, Error: %d\n",pstrConnect->s8Error"); + close(pstrNotification->Socket); + } + } +@endcode +*/ +NMI_API sint8 connect(SOCKET sock, struct sockaddr *pstrAddr, uint8 u8AddrLen); +/*! +@fn \ + NMI_API sint16 recv(SOCKET sock, void *pvRecvBuf, uint16 u16BufLen, uint32 u32Timeoutmsec); + + An asynchrnonous receive function, used to retrieve data from a TCP stream. + Before calling the recv function, a successful socket connection status must have been received through any of the two socket events + [SOCKET_MSG_CONNECT] or [SOCKET_MSG_ACCEPT], from the socket callback. Hence, indicating that the socket is already connected to a remote + host. + The application receives the required data in response to this asynchronous call through the reception of the event @ref SOCKET_MSG_RECV in the + socket callback. + + Receiving the SOCKET_MSG_RECV message in the callback with zero or negative buffer length indicates the following: + - @ref SOCK_ERR_NO_ERROR : Socket connection closed. The application should now call @ref close(). + - @ref SOCK_ERR_CONN_ABORTED : Socket connection aborted. The application should now call @ref close(). + - @ref SOCK_ERR_TIMEOUT : Socket receive timed out. The socket connection remains open. + +@param [in] sock + Socket ID, must hold a non negative value. + A negative value will return a socket error @ref SOCK_ERR_INVALID_ARG. Indicating that an invalid argument is passed in. + + +@param [in] pvRecvBuf + Pointer to a buffer that will hold the received data. The buffer is used + in the recv callback to deliver the received data to the caller. The buffer must + be resident in memory (heap or global buffer). + +@param [in] u16BufLen + The buffer size in bytes. + +@param [in] u32Timeoutmsec + Timeout for the recv function in milli-seconds. If the value is set to ZERO, the timeout + will be set to infinite (the recv function waits forever). If the timeout period is + elapsed with no data received, the socket will get a timeout error. +@pre + - The socket function must be called to allocate a TCP socket before passing the socket ID to the recv function. + - The socket in a connected state is expected to receive data through the socket interface. + +@see socket +@see connect +@see bind +@see listen +@see recvfrom +@see close + +@return + The function returns ZERO for successful operations and a negative value otherwise. + The possible error values are: + - [SOCK_ERR_NO_ERROR](@ref SOCK_ERR_NO_ERROR) + Indicating that the operation was successful. + + - [SOCK_ERR_INVALID_ARG](@ref SOCK_ERR_INVALID_ARG) + Indicating passing invalid arguments such as negative socket ID or NULL Recieve buffer. + + - [SOCK_ERR_BUFFER_FULL](@ref SOCK_ERR_BUFFER_FULL) + Indicate socket recieve failure. +\section SocketExample7 Example + The example demonstrates a code snippet for the calling of the recv function in the socket callback upon notification of the accept or connect events, and the parsing of the + received data when the SOCKET_MSG_RECV event is received. +@code + + switch(u8Msg) + { + + case SOCKET_MSG_ACCEPT: + { + tstrSocketAcceptMsg *pstrAccept = (tstrSocketAcceptMsg*)pvMsg; + + if(pstrAccept->sock >= 0) + { + recv(pstrAccept->sock,gau8RxBuffer,sizeof(gau8RxBuffer),TEST_RECV_TIMEOUT); + } + else + { + M2M_ERR("accept\n"); + } + } + break; + + + case SOCKET_MSG_RECV: + { + tstrSocketRecvMsg *pstrRx = (tstrSocketRecvMsg*)pvMsg; + + if(pstrRx->s16BufferSize > 0) + { + + recv(sock,gau8RxBuffer,sizeof(gau8RxBuffer),TEST_RECV_TIMEOUT); + } + else + { + printf("Socet recv Error: %d\n",pstrRx->s16BufferSize); + close(sock); + } + } + break; + + default: + break; + } +@endcode +*/ +NMI_API sint16 recv(SOCKET sock, void *pvRecvBuf, uint16 u16BufLen, uint32 u32Timeoutmsec); +/*! +@fn \ + NMI_API sint16 recvfrom(SOCKET sock, void *pvRecvBuf, uint16 u16BufLen, uint32 u32TimeoutSeconds); + Receives data from a UDP Scoket. + + The asynchronous recvfrom function is used to retrieve data from a UDP socket. The socket must already be bound to + a local port before a call to the recvfrom function is made (i.e message @ref SOCKET_MSG_BIND is received + with successful status in the socket callback). + + Upon calling the recvfrom function with a successful return code, the application is expected to receive a notification + in the socket callback whenever a message is received through the @ref SOCKET_MSG_RECVFROM event. + + Receiving the SOCKET_MSG_RECVFROM message in the callback with zero, indicates that the socket is closed. + Whereby a negative buffer length indicates one of the socket error codes such as socket timeout error @ref SOCK_ERR_TIMEOUT + + The recvfrom callback can also be used to show the IP address of the remote host that sent the frame by + using the "strRemoteAddr" element in the @ref tstrSocketRecvMsg structure. (refer to the code example) +@param [in] sock + Socket ID, must hold a non negative value. + A negative value will return a socket error @ref SOCK_ERR_INVALID_ARG. Indicating that an invalid argument is passed in. + +@param [in] pvRecvBuf + Pointer to a buffer that will hold the received data. The buffer shall be used + in the recv callback to deliver the received data to the caller. The buffer must + be resident in memory (heap or global buffer). + +@param [in] u16BufLen + The buffer size in bytes. + +@param [in] u32TimeoutSeconds + Timeout for the recv function in milli-seconds. If the value is set to ZERO, the timeout + will be set to infinite (the recv function waits forever). + +@pre + - The socket function must be called to allocate a TCP socket before passing the socket ID to the recv function. + - The socket corresponding to the socket ID must be successfully bound to a local port through the call to a @ref bind function. + +@see + socket + bind + close + +@return + The function returns ZERO for successful operations and a negative value otherwise. + The possible error values are: + - [SOCK_ERR_NO_ERROR](@ref SOCK_ERR_NO_ERROR) + Indicating that the operation was successful. + + - [SOCK_ERR_INVALID_ARG](@ref SOCK_ERR_INVALID_ARG) + Indicating passing invalid arguments such as negative socket ID or NULL Receive buffer. + + - [SOCK_ERR_BUFFER_FULL](@ref SOCK_ERR_BUFFER_FULL) + Indicate socket receive failure. +\section SocketExample8 Example + The example demonstrates a code snippet for the calling of the recvfrom function in the socket callback upon notification of a successful bind event, and the parsing of the + received data when the SOCKET_MSG_RECVFROM event is received. +@code + switch(u8Msg) + { + + case SOCKET_MSG_BIND: + { + tstrSocketBindMsg *pstrBind = (tstrSocketBindMsg*)pvMsg; + + if(pstrBind != NULL) + { + if(pstrBind->status == 0) + { + recvfrom(sock, gau8SocketTestBuffer, TEST_BUFFER_SIZE, 0); + } + else + { + M2M_ERR("bind\n"); + } + } + } + break; + + + case SOCKET_MSG_RECVFROM: + { + tstrSocketRecvMsg *pstrRx = (tstrSocketRecvMsg*)pvMsg; + + if(pstrRx->s16BufferSize > 0) + { + //get the remote host address and port number + uint16 u16port = pstrRx->strRemoteAddr.sin_port; + uint32 strRemoteHostAddr = pstrRx->strRemoteAddr.sin_addr.s_addr; + + printf("Received frame with size = %d.\tHost address=%x, Port number = %d\n\n",pstrRx->s16BufferSize,strRemoteHostAddr, u16port); + + ret = recvfrom(sock,gau8SocketTestBuffer,sizeof(gau8SocketTestBuffer),TEST_RECV_TIMEOUT); + } + else + { + printf("Socket recv Error: %d\n",pstrRx->s16BufferSize); + ret = close(sock); + } + } + break; + + default: + break; + } +@endcode +*/ +NMI_API sint16 recvfrom(SOCKET sock, void *pvRecvBuf, uint16 u16BufLen, uint32 u32Timeoutmsec); +/*! +@fn \ + NMI_API sint16 send(SOCKET sock, void *pvSendBuffer, uint16 u16SendLength, uint16 u16Flags); + Asynchronous sending function, used to send data on a TCP/UDP socket. + + Called by the application code when there is outgoing data available required to be sent on a specific socket handler. + The only difference between this function and the similar @ref sendto function, is the type of socket the data is sent on and the parameters passed in. + @ref send function is most commonly called for sockets in a connected state. + After the data is sent, the socket callback function registered using registerSocketCallback(), is expected to receive an event of type + @ref SOCKET_MSG_SEND holding information containing the number of data bytes sent. +@param [in] sock + Socket ID, must hold a non negative value. + A negative value will return a socket error @ref SOCK_ERR_INVALID_ARG. Indicating that an invalid argument is passed in. + +@param [in] pvSendBuffer + Pointer to a buffer holding data to be transmitted. + +@param [in] u16SendLength + The buffer size in bytes. + +@param [in] u16Flags + Not used in the current implementation. + +@pre + Sockets must be initialized using socketInit. \n + + For TCP Socket:\n + Must use a successfully connected Socket (so that the intended recipient address is known ahead of sending the data). + Hence this function is expected to be called after a successful socket connect operation(in client case or accept in the + the server case).\n + + For UDP Socket:\n + UDP sockets most commonly use @ref sendto function, where the destination address is defined. However, in-order to send outgoing data + using the @ref send function, at least one successful call must be made to the @ref sendto function before consecutive calls to the @ref send function, + to ensure that the destination address is saved in the firmware. + +@see + socketInit + recv + sendto + socket + connect + accept + sendto + +@warning + u16SendLength must not exceed @ref SOCKET_BUFFER_MAX_LENGTH. \n + Use a valid socket identifer through the aprior call to the @ref socket function. + Must use a valid buffer pointer. + Successful completion of a call to send() does not guarantee delivery of the message, + A negative return value indicates only locally-detected errors + + +@return + The function shall return @ref SOCK_ERR_NO_ERROR for successful operation and a negative value (indicating the error) otherwise. +*/ +NMI_API sint16 send(SOCKET sock, void *pvSendBuffer, uint16 u16SendLength, uint16 u16Flags); +/*! +@fn \ + NMI_API sint16 sendto(SOCKET sock, void *pvSendBuffer, uint16 u16SendLength, uint16 flags, struct sockaddr *pstrDestAddr, uint8 u8AddrLen); + + Asynchronous sending function, used to send data on a UDP socket. + Called by the application code when there is data required to be sent on a UDP socket. + The application code is expected to receive data from a successfully bound socket node. + The only difference between this function and the similar @ref send function, is the type of socket the data is received on. This function works + only with UDP sockets. + After the data is sent, the socket callback function registered using @ref registerSocketCallback(), is expected to receive an event of type + @ref SOCKET_MSG_SENDTO. + +@param [in] sock + Socket ID, must hold a non negative value. + A negative value will return a socket error @ref SOCK_ERR_INVALID_ARG. Indicating that an invalid argument is passed in. + +@param [in] pvSendBuffer + Pointer to a buffer holding data to be transmitted. + A NULL value will return a socket error @ref SOCK_ERR_INVALID_ARG. Indicating that an invalid argument is passed in. + +@param [in] u16SendLength + The buffer size in bytes. It must not exceed @ref SOCKET_BUFFER_MAX_LENGTH. + +@param [in] flags + Not used in the current implementation + +@param [in] pstrDestAddr + The destination address. + +@param [in] u8AddrLen + Destination address length in bytes. + Not used in the current implementation, only included for BSD compatibility. +@pre + Sockets must be initialized using socketInit. + +@see + socketInit + recvfrom + sendto + socket + connect + accept + send + +@warning + u16SendLength must not exceed @ref SOCKET_BUFFER_MAX_LENGTH. \n + Use a valid socket (returned from socket ). + A valid buffer pointer must be used (not NULL). \n + Successful completion of a call to sendto() does not guarantee delivery of the message, + A negative return value indicates only locally-detected errors + +@return + The function returns @ref SOCK_ERR_NO_ERROR for successful operation and a negative value (indicating the error) otherwise. +*/ +NMI_API sint16 sendto(SOCKET sock, void *pvSendBuffer, uint16 u16SendLength, uint16 flags, struct sockaddr *pstrDestAddr, uint8 u8AddrLen); +/*! +@fn \ + NMI_API sint8 close(SOCKET sock); + + Synchronous close function, releases all the socket assigned resources. + +@param [in] sock + Socket ID, must hold a non negative value. + A negative value will return a socket error @ref SOCK_ERR_INVALID_ARG. Indicating that an invalid argument is passed in. + +@pre + Sockets must be initialized through the call of the socketInit function. + @ref close is called only for valid socket identifiers created through the @ref socket function. + +@warning + If @ref close is called while there are still pending messages (sent or received ) they will be discarded. + +@see + socketInit + socket + +@return + The function returned @ref SOCK_ERR_NO_ERROR for successful operation and a negative value (indicating the error) otherwise. +*/ +NMI_API sint8 close(SOCKET sock); +/*! +@fn \ + NMI_API uint32 nmi_inet_addr(char *pcIpAddr); + + Synchronous function which returns a BSD socket compliant Internet Protocol (IPv4) socket address. + This IPv4 address in the input string parameter could either be specified as a hostname, or as a numeric string representation like n.n.n.n known as the IPv4 dotted-decimal format + (i.e. "192.168.10.1"). + This function is used whenever an ip address needs to be set in the proper format + (i.e. for the @ref tstrM2MIPConfig structure). + +@param [in] pcIpAddr + A null terminated string containing the IP address in IPv4 dotted-decimal address. + +@return + Unsigned 32-bit integer representing the IP address in Network byte order + (eg. "192.168.10.1" will be expressed as 0x010AA8C0). + +*/ +NMI_API uint32 nmi_inet_addr(char *pcIpAddr); +/*! +@fn \ + NMI_API sint8 gethostbyname(uint8 * pcHostName); + Asynchronous DNS resolving function. This function uses DNS to resolve a domain name to the corresponding IP address. + A call to this function will cause a DNS request to be sent and the response will be delivered to the DNS callback function registered using registerSocketCallback() + +@param [in] pcHostName + NULL terminated string containing the domain name for the remote host. + Its size must not exceed [HOSTNAME_MAX_SIZE](@ref HOSTNAME_MAX_SIZE). + +@see + registerSocketCallback + +@warning + Successful completion of a call to gethostbyname() does not guarantee success of the DNS request, + a negative return value indicates only locally-detected errors + +@return + - [SOCK_ERR_NO_ERROR](@ref SOCK_ERR_NO_ERROR) + - [SOCK_ERR_INVALID_ARG](@ref SOCK_ERR_INVALID_ARG) +*/ +NMI_API sint8 gethostbyname(uint8 * pcHostName); + +/*! +@fn \ + NMI_API sint8 setsockopt(SOCKET socket, uint8 u8Level, uint8 option_name, + const void *option_value, uint16 u16OptionLen); + + The setsockopt() function shall set the option specified by the option_name + argument, at the protocol level specified by the level argument, to the value + pointed to by the option_value argument for the socke specified by the socket argument. + + Possible Options: + SO_SET_UDP_SEND_CALLBACK: + Enable/Disable callback messages for sendto().Since UDP is unreliable by default the user maybe interested (or not) + in receiving a message of /ref SOCKET_MSG_SENDTO for each call of sendto(). + Enabled if option_value equals /ref BTRUE Disabled otherwise. + IP_ADD_MEMBERSHIP: + valid for UDP sockets,this option is used to receive frames sent to a multicast group. + option_value shall be a pointer to Unsigned 32 bit integer containing the Multicast ipv4 address. + IP_DROP_MEMBERSHIP: + valid for UDP sockets,this option is used to Stop receiving frames sent to a multicast group. + option_value shall be a pointer to Unsigned 32 bit integer containing the Multicast ipv4 address. + + Possible values for s32Level: + This argument is ignored. + +@param [in] socket + Socket handler. + +@param [in] u8Level + protocol level. always SOL_SOCKET for now. + +@param [in] option_name + option to be set. + +@param [in] option_value + pointer to user provided value. + +@param [in] u16OptionLen + length of the option value. +@warning + -Note that sending IGMP packets to Join/Leave multicast groups is not currently implemented. \n + Calling this function will Pass/Filter packets sent to the Multicast address provided in the option_value +@return + The function shall return \ref SOCK_ERR_NO_ERROR for successful operation + and a negative value (indicating the error) otherwise. +*/ +NMI_API sint8 setsockopt(SOCKET socket, uint8 u8Level, uint8 option_name, + const void *option_value, uint16 u16OptionLen); +/*! +@fn \ + sint8 getsockopt(SOCKET sock, uint8 u8Level, uint8 u8OptName, const void *pvOptValue, uint8 * pu8OptLen); + Get socket options retrieves + This Function isn't implemented yet but this is the form that will be released later. +@brief + + +@param [in] sock + Socket Identifie. +@param [in] u8Level + The protocol level of the option. +@param [in] u8OptName + The u8OptName argument specifies a single option to get. +@param [out] pvOptValue + The pvOptValue argument contains pointer to a buffer containing the option value. +@param [out] pu8OptLen + Option value buffer length. +@return + The function shall return ZERO for successful operation and a negative value otherwise. +*/ +NMI_API sint8 getsockopt(SOCKET sock, uint8 u8Level, uint8 u8OptName, const void *pvOptValue, uint8* pu8OptLen); +/*! + * @fn NMI_API sint8 m2m_ping_req(uint32 u32DstIP, uint8 u8TTL, tpfPingCb fpPingCb); + * The function request to send ping request to the given IP Address. + * + * @param [in] u32DstIP + * Target Destination IP Address for the ping request. It must be represented in Network + * byte order. + * The function nmi_inet_addr could be used to translate the dotted decimal notation IP + * to its Network bytes order integer represntative. + * + * @param [in] u8TTL + * IP TTL value for the ping request. If set to ZERO, the default value SHALL be used. + * + * @param [in] fpPingCb + * Callback will be called to deliver the ping statistics. + * + * @see nmi_inet_addr + * @return The function returns @ref M2M_SUCCESS for successful operations and a negative value otherwise. + */ +NMI_API sint8 m2m_ping_req(uint32 u32DstIP, uint8 u8TTL, tpfPingCb fpPingCb); +/**@}*/ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __SOCKET_H__ */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/socket/source/socket.c b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/socket/source/socket.c new file mode 100644 index 000000000..e6371a9f9 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/socket/source/socket.c @@ -0,0 +1,1266 @@ +/** + * + * \file + * + * \brief BSD compatible socket interface. + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +INCLUDES +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ + +#include "bsp/include/nm_bsp.h" +#include "socket/include/socket.h" +#include "driver/source/m2m_hif.h" +#include "socket/source/socket_internal.h" + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +MACROS +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ + + +#define TLS_RECORD_HEADER_LENGTH (5) +#define ETHERNET_HEADER_OFFSET (34) +#define ETHERNET_HEADER_LENGTH (14) +#define TCP_IP_HEADER_LENGTH (40) +#define UDP_IP_HEADER_LENGTH (28) + +#define IP_PACKET_OFFSET (ETHERNET_HEADER_LENGTH + ETHERNET_HEADER_OFFSET - M2M_HIF_HDR_OFFSET) + +#define TCP_TX_PACKET_OFFSET (IP_PACKET_OFFSET + TCP_IP_HEADER_LENGTH) +#define UDP_TX_PACKET_OFFSET (IP_PACKET_OFFSET + UDP_IP_HEADER_LENGTH) +#define SSL_TX_PACKET_OFFSET (TCP_TX_PACKET_OFFSET + TLS_RECORD_HEADER_LENGTH) + +#define SOCKET_REQUEST(reqID, reqArgs, reqSize, reqPayload, reqPayloadSize, reqPayloadOffset) \ + hif_send(M2M_REQ_GROUP_IP, reqID, reqArgs, reqSize, reqPayload, reqPayloadSize, reqPayloadOffset) + + +#define SSL_FLAGS_ACTIVE NBIT0 +#define SSL_FLAGS_BYPASS_X509 NBIT1 +#define SSL_FLAGS_CACHE_SESSION NBIT4 +#define SSL_FLAGS_CHECK_CERTNAME NBIT6 + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +PRIVATE DATA TYPES +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ + + +/*! +* @brief +*/ +typedef struct{ + SOCKET sock; + uint8 u8Dummy; + uint16 u16SessionID; +}tstrCloseCmd; + + +/*! +* @brief +*/ +typedef struct{ + uint8 *pu8UserBuffer; + uint16 u16UserBufferSize; + uint16 u16SessionID; + uint16 u16DataOffset; + uint8 bIsUsed; + uint8 u8SSLFlags; + uint8 bIsRecvPending; +}tstrSocket; + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +GLOBALS +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ + +volatile sint8 gsockerrno; +volatile tstrSocket gastrSockets[MAX_SOCKET]; +volatile uint8 gu8OpCode; +volatile uint16 gu16BufferSize; +volatile uint16 gu16SessionID = 0; + +volatile tpfAppSocketCb gpfAppSocketCb; +volatile tpfAppResolveCb gpfAppResolveCb; +volatile uint8 gbSocketInit = 0; +volatile tpfPingCb gfpPingCb; + +/********************************************************************* +Function + Socket_ReadSocketData + +Description + Callback function used by the NMC1500 driver to deliver messages + for socket layer. + +Return + None. + +Author + Ahmed Ezzat + +Version + 1.0 + +Date + 17 July 2012 +*********************************************************************/ +NMI_API void Socket_ReadSocketData(SOCKET sock, tstrSocketRecvMsg *pstrRecv,uint8 u8SocketMsg, + uint32 u32StartAddress,uint16 u16ReadCount) +{ + uint32 u32Address = u32StartAddress; + uint16 u16Read; + sint16 s16Diff; + + pstrRecv->u16RemainingSize = u16ReadCount; + if((u16ReadCount > 0) && (gastrSockets[sock].pu8UserBuffer != NULL) && (gastrSockets[sock].u16UserBufferSize > 0) && (gastrSockets[sock].bIsUsed == 1)) + { + u16Read = u16ReadCount; + s16Diff = u16Read - gastrSockets[sock].u16UserBufferSize; + if(s16Diff > 0) + u16Read = gastrSockets[sock].u16UserBufferSize; + + if(hif_receive(u32Address, gastrSockets[sock].pu8UserBuffer, u16Read, 1) == M2M_SUCCESS) + { + pstrRecv->pu8Buffer = gastrSockets[sock].pu8UserBuffer; + pstrRecv->s16BufferSize = u16Read; + pstrRecv->u16RemainingSize -= u16Read; + + gastrSockets[sock].u16UserBufferSize -= u16Read; + if(gastrSockets[sock].u16UserBufferSize == 0) + gastrSockets[sock].pu8UserBuffer = NULL; + + if (gpfAppSocketCb) + gpfAppSocketCb(sock,u8SocketMsg, pstrRecv); + } + else + { + M2M_INFO("(ERRR)Current <%d>\n", u16ReadCount); + } + } +} +/********************************************************************* +Function + m2m_ip_cb + +Description + Callback function used by the NMC1000 driver to deliver messages + for socket layer. + +Return + None. + +Author + Ahmed Ezzat + +Version + 1.0 + +Date + 17 July 2012 +*********************************************************************/ +static void m2m_ip_cb(uint8 u8OpCode, uint16 u16BufferSize,uint32 u32Address) +{ + if(u8OpCode == SOCKET_CMD_BIND) + { + tstrBindReply strBindReply; + tstrSocketBindMsg strBind; + + if(hif_receive(u32Address, (uint8*)&strBindReply, sizeof(tstrBindReply), 0) == M2M_SUCCESS) + { + strBind.status = strBindReply.s8Status; + if(gpfAppSocketCb) + gpfAppSocketCb(strBindReply.sock,SOCKET_MSG_BIND,&strBind); + } + } + else if(u8OpCode == SOCKET_CMD_LISTEN) + { + tstrListenReply strListenReply; + tstrSocketListenMsg strListen; + if(hif_receive(u32Address, (uint8*)&strListenReply, sizeof(tstrListenReply), 0) == M2M_SUCCESS) + { + strListen.status = strListenReply.s8Status; + if(gpfAppSocketCb) + gpfAppSocketCb(strListenReply.sock,SOCKET_MSG_LISTEN, &strListen); + } + } + else if(u8OpCode == SOCKET_CMD_ACCEPT) + { + tstrAcceptReply strAcceptReply; + tstrSocketAcceptMsg strAccept; + if(hif_receive(u32Address, (uint8*)&strAcceptReply, sizeof(tstrAcceptReply), 0) == M2M_SUCCESS) + { + if(strAcceptReply.sConnectedSock >= 0) + { + gastrSockets[strAcceptReply.sConnectedSock].u8SSLFlags = 0; + gastrSockets[strAcceptReply.sConnectedSock].bIsUsed = 1; + + /* The session ID is used to distinguish different socket connections + by comparing the assigned session ID to the one reported by the firmware*/ + ++gu16SessionID; + if(gu16SessionID == 0) + ++gu16SessionID; + + gastrSockets[strAcceptReply.sConnectedSock].u16SessionID = gu16SessionID; + M2M_DBG("Socket %d session ID = %d\r\n",strAcceptReply.sConnectedSock , gu16SessionID ); + } + strAccept.sock = strAcceptReply.sConnectedSock; + strAccept.strAddr.sin_family = AF_INET; + strAccept.strAddr.sin_port = strAcceptReply.strAddr.u16Port; + strAccept.strAddr.sin_addr.s_addr = strAcceptReply.strAddr.u32IPAddr; + if(gpfAppSocketCb) + gpfAppSocketCb(strAcceptReply.sListenSock, SOCKET_MSG_ACCEPT, &strAccept); + } + } + else if((u8OpCode == SOCKET_CMD_CONNECT) || (u8OpCode == SOCKET_CMD_SSL_CONNECT)) + { + tstrConnectReply strConnectReply; + tstrSocketConnectMsg strConnMsg; + if(hif_receive(u32Address, (uint8*)&strConnectReply, sizeof(tstrConnectReply), 0) == M2M_SUCCESS) + { + strConnMsg.sock = strConnectReply.sock; + strConnMsg.s8Error = strConnectReply.s8Error; + if(strConnectReply.s8Error == SOCK_ERR_NO_ERROR) + { + gastrSockets[strConnectReply.sock].u16DataOffset = strConnectReply.u16AppDataOffset - M2M_HIF_HDR_OFFSET; + } + if(gpfAppSocketCb) + gpfAppSocketCb(strConnectReply.sock,SOCKET_MSG_CONNECT, &strConnMsg); + } + } + else if(u8OpCode == SOCKET_CMD_DNS_RESOLVE) + { + tstrDnsReply strDnsReply; + if(hif_receive(u32Address, (uint8*)&strDnsReply, sizeof(tstrDnsReply), 0) == M2M_SUCCESS) + { + strDnsReply.u32HostIP = strDnsReply.u32HostIP; + if(gpfAppResolveCb) + gpfAppResolveCb((uint8*)strDnsReply.acHostName, strDnsReply.u32HostIP); + } + } + else if((u8OpCode == SOCKET_CMD_RECV) || (u8OpCode == SOCKET_CMD_RECVFROM) || (u8OpCode == SOCKET_CMD_SSL_RECV)) + { + SOCKET sock; + sint16 s16RecvStatus; + tstrRecvReply strRecvReply; + uint16 u16ReadSize; + tstrSocketRecvMsg strRecvMsg; + uint8 u8CallbackMsgID = SOCKET_MSG_RECV; + uint16 u16DataOffset; + + if(u8OpCode == SOCKET_CMD_RECVFROM) + u8CallbackMsgID = SOCKET_MSG_RECVFROM; + + /* Read RECV REPLY data structure. + */ + u16ReadSize = sizeof(tstrRecvReply); + if(hif_receive(u32Address, (uint8*)&strRecvReply, u16ReadSize, 0) == M2M_SUCCESS) + { + uint16 u16SessionID = 0; + + sock = strRecvReply.sock; + u16SessionID = strRecvReply.u16SessionID; + M2M_DBG("recv callback session ID = %d\r\n",u16SessionID); + + /* Reset the Socket RX Pending Flag. + */ + gastrSockets[sock].bIsRecvPending = 0; + + s16RecvStatus = NM_BSP_B_L_16(strRecvReply.s16RecvStatus); + u16DataOffset = NM_BSP_B_L_16(strRecvReply.u16DataOffset); + strRecvMsg.strRemoteAddr.sin_port = strRecvReply.strRemoteAddr.u16Port; + strRecvMsg.strRemoteAddr.sin_addr.s_addr = strRecvReply.strRemoteAddr.u32IPAddr; + + if(u16SessionID == gastrSockets[sock].u16SessionID) + { + if((s16RecvStatus > 0) && (s16RecvStatus < u16BufferSize)) + { + /* Skip incoming bytes until reaching the Start of Application Data. + */ + u32Address += u16DataOffset; + + /* Read the Application data and deliver it to the application callback in + the given application buffer. If the buffer is smaller than the received data, + the data is passed to the application in chunks according to its buffer size. + */ + u16ReadSize = (uint16)s16RecvStatus; + Socket_ReadSocketData(sock, &strRecvMsg, u8CallbackMsgID, u32Address, u16ReadSize); + } + else + { + /* Don't tidy up here. Application must call close(). + */ + strRecvMsg.s16BufferSize = s16RecvStatus; + strRecvMsg.pu8Buffer = NULL; + if(gpfAppSocketCb) + gpfAppSocketCb(sock,u8CallbackMsgID, &strRecvMsg); + } + } + else + { + M2M_DBG("Discard recv callback %d %d \r\n",u16SessionID , gastrSockets[sock].u16SessionID); + if(u16ReadSize < u16BufferSize) + hif_receive(0, NULL, 0, 1); + } + } + } + else if((u8OpCode == SOCKET_CMD_SEND) || (u8OpCode == SOCKET_CMD_SENDTO) || (u8OpCode == SOCKET_CMD_SSL_SEND)) + { + SOCKET sock; + sint16 s16Rcvd; + tstrSendReply strReply; + uint8 u8CallbackMsgID = SOCKET_MSG_SEND; + + if(u8OpCode == SOCKET_CMD_SENDTO) + u8CallbackMsgID = SOCKET_MSG_SENDTO; + + if(hif_receive(u32Address, (uint8*)&strReply, sizeof(tstrSendReply), 0) == M2M_SUCCESS) + { + uint16 u16SessionID = 0; + + sock = strReply.sock; + u16SessionID = strReply.u16SessionID; + M2M_DBG("send callback session ID = %d\r\n",u16SessionID); + + s16Rcvd = NM_BSP_B_L_16(strReply.s16SentBytes); + + if(u16SessionID == gastrSockets[sock].u16SessionID) + { + if(gpfAppSocketCb) + gpfAppSocketCb(sock,u8CallbackMsgID, &s16Rcvd); + } + else + { + M2M_DBG("Discard send callback %d %d \r\n",u16SessionID , gastrSockets[sock].u16SessionID); + } + } + } + else if(u8OpCode == SOCKET_CMD_PING) + { + tstrPingReply strPingReply; + if(hif_receive(u32Address, (uint8*)&strPingReply, sizeof(tstrPingReply), 1) == M2M_SUCCESS) + { + gfpPingCb = (void (*)(uint32 , uint32 , uint8))strPingReply.u32CmdPrivate; + if(gfpPingCb != NULL) + { + gfpPingCb(strPingReply.u32IPAddr, strPingReply.u32RTT, strPingReply.u8ErrorCode); +} + } + } +} +/********************************************************************* +Function + socketInit + +Description + +Return + None. + +Author + Ahmed Ezzat + +Version + 1.0 + +Date + 4 June 2012 +*********************************************************************/ +void socketInit(void) +{ + if(gbSocketInit==0) + { + m2m_memset((uint8*)gastrSockets, 0, MAX_SOCKET * sizeof(tstrSocket)); + hif_register_cb(M2M_REQ_GROUP_IP,m2m_ip_cb); + gbSocketInit=1; + gu16SessionID = 0; + } +} + +/********************************************************************* +Function + socketDeinit + +Description + +Return + None. + +Author + Samer Sarhan + +Version + 1.0 + +Date + 27 Feb 2015 +*********************************************************************/ +void socketDeinit(void) +{ + m2m_memset((uint8*)gastrSockets, 0, MAX_SOCKET * sizeof(tstrSocket)); + hif_register_cb(M2M_REQ_GROUP_IP, NULL); + gpfAppSocketCb = NULL; + gpfAppResolveCb = NULL; + gbSocketInit = 0; +} + + +/********************************************************************* +Function + registerSocketCallback + +Description + +Return + None. + +Author + Ahmed Ezzat + +Versio + 1.0 + +Date + 4 June 2012 +*********************************************************************/ +void registerSocketCallback(tpfAppSocketCb pfAppSocketCb, tpfAppResolveCb pfAppResolveCb) +{ + gpfAppSocketCb = pfAppSocketCb; + gpfAppResolveCb = pfAppResolveCb; +} + +/********************************************************************* +Function + socket + +Description + Creates a socket. + +Return + - Negative value for error. + - ZERO or positive value as a socket ID if successful. + +Author + Ahmed Ezzat + +Version + 1.0 + +Date + 4 June 2012 +*********************************************************************/ +SOCKET socket(uint16 u16Domain, uint8 u8Type, uint8 u8Flags) +{ + SOCKET sock = -1; + uint8 u8SockID; + uint8 u8Count; + volatile tstrSocket *pstrSock; + static volatile uint8 u8NextTcpSock = 0; + static volatile uint8 u8NextUdpSock = 0; + + /* The only supported family is the AF_INET for UDP and TCP transport layer protocols. */ + if(u16Domain == AF_INET) + { + if(u8Type == SOCK_STREAM) + { + for(u8Count = 0; u8Count < TCP_SOCK_MAX; u8Count ++) + { + u8SockID = u8NextTcpSock; + pstrSock = &gastrSockets[u8NextTcpSock]; + u8NextTcpSock = (u8NextTcpSock + 1) % TCP_SOCK_MAX; + if(!pstrSock->bIsUsed) + { + sock = (SOCKET)u8SockID; + break; + } + } + } + else if(u8Type == SOCK_DGRAM) + { + volatile tstrSocket *pastrUDPSockets = &gastrSockets[TCP_SOCK_MAX]; + for(u8Count = 0; u8Count < UDP_SOCK_MAX; u8Count ++) + { + u8SockID = u8NextUdpSock; + pstrSock = &pastrUDPSockets[u8NextUdpSock]; + u8NextUdpSock = (u8NextUdpSock + 1) % UDP_SOCK_MAX; + if(!pstrSock->bIsUsed) + { + sock = (SOCKET)(u8SockID + TCP_SOCK_MAX); + break; + } + } + } + + if(sock >= 0) + { + m2m_memset((uint8*)pstrSock, 0, sizeof(tstrSocket)); + pstrSock->bIsUsed = 1; + + /* The session ID is used to distinguish different socket connections + by comparing the assigned session ID to the one reported by the firmware*/ + ++gu16SessionID; + if(gu16SessionID == 0) + ++gu16SessionID; + + pstrSock->u16SessionID = gu16SessionID; + M2M_INFO("Socket %d session ID = %d\r\n",sock, gu16SessionID ); + + if(u8Flags & SOCKET_FLAGS_SSL) + { + tstrSSLSocketCreateCmd strSSLCreate; + strSSLCreate.sslSock = sock; + pstrSock->u8SSLFlags = SSL_FLAGS_ACTIVE; + SOCKET_REQUEST(SOCKET_CMD_SSL_CREATE, (uint8*)&strSSLCreate, sizeof(tstrSSLSocketCreateCmd), 0, 0, 0); + } + } + } + return sock; +} +/********************************************************************* +Function + bind + +Description + Request to bind a socket on a local address. + +Return + + +Author + Ahmed Ezzat + +Version + 1.0 + +Date + 5 June 2012 +*********************************************************************/ +sint8 bind(SOCKET sock, struct sockaddr *pstrAddr, uint8 u8AddrLen) +{ + sint8 s8Ret = SOCK_ERR_INVALID_ARG; + if((pstrAddr != NULL) && (sock >= 0) && (gastrSockets[sock].bIsUsed == 1) && (u8AddrLen != 0)) + { + tstrBindCmd strBind; + + /* Build the bind request. */ + strBind.sock = sock; + m2m_memcpy((uint8 *)&strBind.strAddr, (uint8 *)pstrAddr, sizeof(tstrSockAddr)); + + strBind.strAddr.u16Family = strBind.strAddr.u16Family; + strBind.strAddr.u16Port = strBind.strAddr.u16Port; + strBind.strAddr.u32IPAddr = strBind.strAddr.u32IPAddr; + strBind.u16SessionID = gastrSockets[sock].u16SessionID; + + /* Send the request. */ + s8Ret = SOCKET_REQUEST(SOCKET_CMD_BIND, (uint8*)&strBind,sizeof(tstrBindCmd) , NULL , 0, 0); + if(s8Ret != SOCK_ERR_NO_ERROR) + { + s8Ret = SOCK_ERR_INVALID; + } + } + return s8Ret; +} +/********************************************************************* +Function + listen + +Description + + +Return + + +Author + Ahmed Ezzat + +Version + 1.0 + +Date + 5 June 2012 +*********************************************************************/ +sint8 listen(SOCKET sock, uint8 backlog) +{ + sint8 s8Ret = SOCK_ERR_INVALID_ARG; + + if(sock >= 0 && (gastrSockets[sock].bIsUsed == 1)) + { + tstrListenCmd strListen; + + strListen.sock = sock; + strListen.u8BackLog = backlog; + strListen.u16SessionID = gastrSockets[sock].u16SessionID; + + s8Ret = SOCKET_REQUEST(SOCKET_CMD_LISTEN, (uint8*)&strListen, sizeof(tstrListenCmd), NULL, 0, 0); + if(s8Ret != SOCK_ERR_NO_ERROR) + { + s8Ret = SOCK_ERR_INVALID; + } + } + return s8Ret; +} +/********************************************************************* +Function + accept + +Description + +Return + + +Author + Ahmed Ezzat + +Version + 1.0 + +Date + 5 June 2012 +*********************************************************************/ +sint8 accept(SOCKET sock, struct sockaddr *addr, uint8 *addrlen) +{ + sint8 s8Ret = SOCK_ERR_INVALID_ARG; + + if(sock >= 0 && (gastrSockets[sock].bIsUsed == 1) ) + { + s8Ret = SOCK_ERR_NO_ERROR; + } + return s8Ret; +} +/********************************************************************* +Function + connect + +Description + Connect to a remote TCP Server. + +Return + + +Author + Ahmed Ezzat + +Version + 1.0 + +Date + 5 June 2012 +*********************************************************************/ +sint8 connect(SOCKET sock, struct sockaddr *pstrAddr, uint8 u8AddrLen) +{ + sint8 s8Ret = SOCK_ERR_INVALID_ARG; + if((sock >= 0) && (pstrAddr != NULL) && (gastrSockets[sock].bIsUsed == 1) && (u8AddrLen != 0)) + { + tstrConnectCmd strConnect; + uint8 u8Cmd = SOCKET_CMD_CONNECT; + if((gastrSockets[sock].u8SSLFlags) & SSL_FLAGS_ACTIVE) + { + u8Cmd = SOCKET_CMD_SSL_CONNECT; + strConnect.u8SslFlags = gastrSockets[sock].u8SSLFlags; + } + strConnect.sock = sock; + m2m_memcpy((uint8 *)&strConnect.strAddr, (uint8 *)pstrAddr, sizeof(tstrSockAddr)); + + strConnect.u16SessionID = gastrSockets[sock].u16SessionID; + s8Ret = SOCKET_REQUEST(u8Cmd, (uint8*)&strConnect,sizeof(tstrConnectCmd), NULL, 0, 0); + if(s8Ret != SOCK_ERR_NO_ERROR) + { + s8Ret = SOCK_ERR_INVALID; + } + } + return s8Ret; +} +/********************************************************************* +Function + send + +Description + +Return + +Author + Ahmed Ezzat + +Version + 1.0 + +Date + 5 June 2012 +*********************************************************************/ +sint16 send(SOCKET sock, void *pvSendBuffer, uint16 u16SendLength, uint16 flags) +{ + sint16 s16Ret = SOCK_ERR_INVALID_ARG; + + if((sock >= 0) && (pvSendBuffer != NULL) && (u16SendLength <= SOCKET_BUFFER_MAX_LENGTH) && (gastrSockets[sock].bIsUsed == 1)) + { + uint16 u16DataOffset; + tstrSendCmd strSend; + uint8 u8Cmd; + + u8Cmd = SOCKET_CMD_SEND; + u16DataOffset = TCP_TX_PACKET_OFFSET; + + strSend.sock = sock; + strSend.u16DataSize = NM_BSP_B_L_16(u16SendLength); + strSend.u16SessionID = gastrSockets[sock].u16SessionID; + + if(sock >= TCP_SOCK_MAX) + { + u16DataOffset = UDP_TX_PACKET_OFFSET; + } + if(gastrSockets[sock].u8SSLFlags & SSL_FLAGS_ACTIVE) + { + u8Cmd = SOCKET_CMD_SSL_SEND; + u16DataOffset = gastrSockets[sock].u16DataOffset; + } + + s16Ret = SOCKET_REQUEST(u8Cmd|M2M_REQ_DATA_PKT, (uint8*)&strSend, sizeof(tstrSendCmd), pvSendBuffer, u16SendLength, u16DataOffset); + if(s16Ret != SOCK_ERR_NO_ERROR) + { + s16Ret = SOCK_ERR_BUFFER_FULL; + } + } + return s16Ret; +} +/********************************************************************* +Function + sendto + +Description + +Return + +Author + Ahmed Ezzat + +Version + 1.0 + +Date + 4 June 2012 +*********************************************************************/ +sint16 sendto(SOCKET sock, void *pvSendBuffer, uint16 u16SendLength, uint16 flags, struct sockaddr *pstrDestAddr, uint8 u8AddrLen) +{ + sint16 s16Ret = SOCK_ERR_INVALID_ARG; + + if((sock >= 0) && (pvSendBuffer != NULL) && (u16SendLength <= SOCKET_BUFFER_MAX_LENGTH) && (gastrSockets[sock].bIsUsed == 1)) + { + if(gastrSockets[sock].bIsUsed) + { + tstrSendCmd strSendTo; + + m2m_memset((uint8*)&strSendTo, 0, sizeof(tstrSendCmd)); + + strSendTo.sock = sock; + strSendTo.u16DataSize = NM_BSP_B_L_16(u16SendLength); + strSendTo.u16SessionID = gastrSockets[sock].u16SessionID; + + if(pstrDestAddr != NULL) + { + struct sockaddr_in *pstrAddr; + pstrAddr = (void*)pstrDestAddr; + + strSendTo.strAddr.u16Family = pstrAddr->sin_family; + strSendTo.strAddr.u16Port = pstrAddr->sin_port; + strSendTo.strAddr.u32IPAddr = pstrAddr->sin_addr.s_addr; + } + s16Ret = SOCKET_REQUEST(SOCKET_CMD_SENDTO|M2M_REQ_DATA_PKT, (uint8*)&strSendTo, sizeof(tstrSendCmd), + pvSendBuffer, u16SendLength, UDP_TX_PACKET_OFFSET); + + if(s16Ret != SOCK_ERR_NO_ERROR) + { + s16Ret = SOCK_ERR_BUFFER_FULL; + } + } + } + return s16Ret; +} +/********************************************************************* +Function + recv + +Description + +Return + + +Author + Ahmed Ezzat + +Version + 1.0 + 2.0 9 April 2013 --> Add timeout for recv operation. + +Date + 5 June 2012 +*********************************************************************/ +sint16 recv(SOCKET sock, void *pvRecvBuf, uint16 u16BufLen, uint32 u32Timeoutmsec) +{ + sint16 s16Ret = SOCK_ERR_INVALID_ARG; + + if((sock >= 0) && (pvRecvBuf != NULL) && (u16BufLen != 0) && (gastrSockets[sock].bIsUsed == 1)) + { + s16Ret = SOCK_ERR_NO_ERROR; + gastrSockets[sock].pu8UserBuffer = (uint8*)pvRecvBuf; + gastrSockets[sock].u16UserBufferSize = u16BufLen; + + if(!gastrSockets[sock].bIsRecvPending) + { + tstrRecvCmd strRecv; + uint8 u8Cmd = SOCKET_CMD_RECV; + + gastrSockets[sock].bIsRecvPending = 1; + if(gastrSockets[sock].u8SSLFlags & SSL_FLAGS_ACTIVE) + { + u8Cmd = SOCKET_CMD_SSL_RECV; + } + + /* Check the timeout value. */ + if(u32Timeoutmsec == 0) + strRecv.u32Timeoutmsec = 0xFFFFFFFF; + else + strRecv.u32Timeoutmsec = NM_BSP_B_L_32(u32Timeoutmsec); + strRecv.sock = sock; + strRecv.u16SessionID = gastrSockets[sock].u16SessionID; + strRecv.u16BufLen = u16BufLen; + + s16Ret = SOCKET_REQUEST(u8Cmd, (uint8*)&strRecv, sizeof(tstrRecvCmd), NULL , 0, 0); + if(s16Ret != SOCK_ERR_NO_ERROR) + { + s16Ret = SOCK_ERR_BUFFER_FULL; + } + } + } + return s16Ret; +} +/********************************************************************* +Function + close + +Description + +Return + None. + +Author + Ahmed Ezzat + +Version + 1.0 + +Date + 4 June 2012 +*********************************************************************/ +sint8 close(SOCKET sock) +{ + sint8 s8Ret = SOCK_ERR_INVALID_ARG; + + M2M_INFO("Sock to delete <%d>\n", sock); + + if(sock >= 0 && (gastrSockets[sock].bIsUsed == 1)) + { + uint8 u8Cmd = SOCKET_CMD_CLOSE; + tstrCloseCmd strclose; + strclose.sock = sock; + strclose.u16SessionID = gastrSockets[sock].u16SessionID; + + if(gastrSockets[sock].u8SSLFlags & SSL_FLAGS_ACTIVE) + { + u8Cmd = SOCKET_CMD_SSL_CLOSE; + } + s8Ret = SOCKET_REQUEST(u8Cmd, (uint8*)&strclose, sizeof(tstrCloseCmd), NULL,0, 0); + if(s8Ret != SOCK_ERR_NO_ERROR) + { + s8Ret = SOCK_ERR_INVALID; + } + m2m_memset((uint8*)&gastrSockets[sock], 0, sizeof(tstrSocket)); + } + return s8Ret; +} +/********************************************************************* +Function + recvfrom + +Description + +Return + + +Author + Ahmed Ezzat + +Version + 1.0 + 2.0 9 April 2013 --> Add timeout for recv operation. + +Date + 5 June 2012 +*********************************************************************/ +sint16 recvfrom(SOCKET sock, void *pvRecvBuf, uint16 u16BufLen, uint32 u32Timeoutmsec) +{ + sint16 s16Ret = SOCK_ERR_NO_ERROR; + if((sock >= 0) && (pvRecvBuf != NULL) && (u16BufLen != 0) && (gastrSockets[sock].bIsUsed == 1)) + { + if(gastrSockets[sock].bIsUsed) + { + s16Ret = SOCK_ERR_NO_ERROR; + gastrSockets[sock].pu8UserBuffer = (uint8*)pvRecvBuf; + gastrSockets[sock].u16UserBufferSize = u16BufLen; + + if(!gastrSockets[sock].bIsRecvPending) + { + tstrRecvCmd strRecv; + + gastrSockets[sock].bIsRecvPending = 1; + + /* Check the timeout value. */ + if(u32Timeoutmsec == 0) + strRecv.u32Timeoutmsec = 0xFFFFFFFF; + else + strRecv.u32Timeoutmsec = NM_BSP_B_L_32(u32Timeoutmsec); + strRecv.sock = sock; + strRecv.u16SessionID = gastrSockets[sock].u16SessionID; + strRecv.u16BufLen = u16BufLen; + + s16Ret = SOCKET_REQUEST(SOCKET_CMD_RECVFROM, (uint8*)&strRecv, sizeof(tstrRecvCmd), NULL , 0, 0); + if(s16Ret != SOCK_ERR_NO_ERROR) + { + s16Ret = SOCK_ERR_BUFFER_FULL; + } + } + } + } + else + { + s16Ret = SOCK_ERR_INVALID_ARG; + } + return s16Ret; +} +/********************************************************************* +Function + nmi_inet_addr + +Description + +Return + Unsigned 32-bit integer representing the IP address in Network + byte order. + +Author + Ahmed Ezzat + +Version + 1.0 + +Date + 4 June 2012 +*********************************************************************/ +uint32 nmi_inet_addr(char *pcIpAddr) +{ + uint8 tmp; + uint32 u32IP = 0; + uint8 au8IP[4]; + uint8 c; + uint8 i, j; + + tmp = 0; + + for(i = 0; i < 4; ++i) + { + j = 0; + do + { + c = *pcIpAddr; + ++j; + if(j > 4) + { + return 0; + } + if(c == '.' || c == 0) + { + au8IP[i] = tmp; + tmp = 0; + } + else if(c >= '0' && c <= '9') + { + tmp = (tmp * 10) + (c - '0'); + } + else + { + return 0; + } + ++pcIpAddr; + } while(c != '.' && c != 0); + } + m2m_memcpy((uint8*)&u32IP, au8IP, 4); + return u32IP; +} +/********************************************************************* +Function + gethostbyname + +Description + +Return + None. + +Author + Ahmed Ezzat + +Version + 1.0 + +Date + 4 June 2012 +*********************************************************************/ +sint8 gethostbyname(uint8 * pcHostName) +{ + sint8 s8Err = SOCK_ERR_INVALID_ARG; + uint8 u8HostNameSize = (uint8)m2m_strlen(pcHostName); + if(u8HostNameSize <= HOSTNAME_MAX_SIZE) + { + s8Err = SOCKET_REQUEST(SOCKET_CMD_DNS_RESOLVE|M2M_REQ_DATA_PKT, (uint8*)pcHostName, u8HostNameSize + 1, NULL,0, 0); + if(s8Err != SOCK_ERR_NO_ERROR) + { + s8Err = SOCK_ERR_INVALID; + } + } + return s8Err; +} +/********************************************************************* +Function + setsockopt + +Description + +Return + None. + +Author + Abdelrahman Diab + +Version + 1.0 + +Date + 9 September 2014 +*********************************************************************/ +static sint8 sslSetSockOpt(SOCKET sock, uint8 u8Opt, const void *pvOptVal, uint16 u16OptLen) +{ + sint8 s8Ret = SOCK_ERR_INVALID_ARG; + if(sock < TCP_SOCK_MAX) + { + if(gastrSockets[sock].u8SSLFlags & SSL_FLAGS_ACTIVE) + { + if(u8Opt == SO_SSL_BYPASS_X509_VERIF) + { + int optVal = *((int*)pvOptVal); + if(optVal) + { + gastrSockets[sock].u8SSLFlags |= SSL_FLAGS_BYPASS_X509; + } + else + { + gastrSockets[sock].u8SSLFlags &= ~SSL_FLAGS_BYPASS_X509; + } + s8Ret = SOCK_ERR_NO_ERROR; + } + else if(u8Opt == SO_SSL_ENABLE_SESSION_CACHING) + { + int optVal = *((int*)pvOptVal); + if(optVal) + { + gastrSockets[sock].u8SSLFlags |= SSL_FLAGS_CACHE_SESSION; + } + else + { + gastrSockets[sock].u8SSLFlags &= ~SSL_FLAGS_CACHE_SESSION; + } + s8Ret = SOCK_ERR_NO_ERROR; + } + else if(u8Opt == SO_SSL_ENABLE_CERTNAME_VALIDATION) + { + int optVal = *((int*)pvOptVal); + if(optVal) + { + gastrSockets[sock].u8SSLFlags |= SSL_FLAGS_CHECK_CERTNAME; + } + else + { + gastrSockets[sock].u8SSLFlags &= ~SSL_FLAGS_CHECK_CERTNAME; + } + s8Ret = SOCK_ERR_NO_ERROR; + } + else if(u8Opt == SO_SSL_SNI) + { + if(u16OptLen < HOSTNAME_MAX_SIZE) + { + uint8 *pu8SNI = (uint8*)pvOptVal; + tstrSSLSetSockOptCmd strCmd; + + strCmd.sock = sock; + strCmd.u16SessionID = gastrSockets[sock].u16SessionID; + strCmd.u8Option = u8Opt; + strCmd.u32OptLen = u16OptLen; + m2m_memcpy(strCmd.au8OptVal, pu8SNI, HOSTNAME_MAX_SIZE); + + if(SOCKET_REQUEST(SOCKET_CMD_SSL_SET_SOCK_OPT, (uint8*)&strCmd, sizeof(tstrSSLSetSockOptCmd), + 0, 0, 0) == M2M_ERR_MEM_ALLOC) + { + s8Ret = SOCKET_REQUEST(SOCKET_CMD_SSL_SET_SOCK_OPT | M2M_REQ_DATA_PKT, + (uint8*)&strCmd, sizeof(tstrSSLSetSockOptCmd), 0, 0, 0); + } + s8Ret = SOCK_ERR_NO_ERROR; + } + else + { + M2M_ERR("SNI Exceeds Max Length\n"); + } + } + else + { + M2M_ERR("Unknown SSL Socket Option %d\n",u8Opt); + } + } + else + { + M2M_ERR("Not SSL Socket\n"); + } + } + return s8Ret; +} +/********************************************************************* +Function + setsockopt + +Description + +Return + None. + +Author + Abdelrahman Diab + +Version + 1.0 + +Date + 9 September 2014 +*********************************************************************/ +sint8 setsockopt(SOCKET sock, uint8 u8Level, uint8 option_name, + const void *option_value, uint16 u16OptionLen) +{ + sint8 s8Ret = SOCK_ERR_INVALID_ARG; + if((sock >= 0) && (option_value != NULL) && (gastrSockets[sock].bIsUsed == 1)) + { + if(u8Level == SOL_SSL_SOCKET) + { + if((option_name == SO_SSL_SNI) || (u16OptionLen == sizeof(int))) + { + s8Ret = sslSetSockOpt(sock, option_name, option_value, u16OptionLen); + } + } + else + { + if(u16OptionLen == sizeof(uint32)) + { + uint8 u8Cmd = SOCKET_CMD_SET_SOCKET_OPTION; + tstrSetSocketOptCmd strSetSockOpt; + strSetSockOpt.u8Option=option_name; + strSetSockOpt.sock = sock; + strSetSockOpt.u32OptionValue = *(uint32*)option_value; + strSetSockOpt.u16SessionID = gastrSockets[sock].u16SessionID; + + s8Ret = SOCKET_REQUEST(u8Cmd, (uint8*)&strSetSockOpt, sizeof(tstrSetSocketOptCmd), NULL,0, 0); + if(s8Ret != SOCK_ERR_NO_ERROR) + { + s8Ret = SOCK_ERR_INVALID; + } + } + } + } + return s8Ret; +} +/********************************************************************* +Function + getsockopt + +Description + +Return + None. + +Author + Ahmed Ezzat + +Version + 1.0 + +Date + 24 August 2014 +*********************************************************************/ +sint8 getsockopt(SOCKET sock, uint8 u8Level, uint8 u8OptName, const void *pvOptValue, uint8* pu8OptLen) +{ + // This is not implemented so return a value that will cause failure should this be used. + return SOCK_ERR_INVALID_ARG; +} +/********************************************************************* +Function + m2m_ping_req + +Description + Send Ping request. + +Return + +Author + Ahmed Ezzat + +Version + 1.0 + +Date + 4 June 2015 +*********************************************************************/ +sint8 m2m_ping_req(uint32 u32DstIP, uint8 u8TTL, tpfPingCb fpPingCb) +{ + sint8 s8Ret = M2M_ERR_INVALID_ARG; + + if((u32DstIP != 0) && (fpPingCb != NULL)) + { + tstrPingCmd strPingCmd; + + strPingCmd.u16PingCount = 1; + strPingCmd.u32DestIPAddr = u32DstIP; + strPingCmd.u32CmdPrivate = (uint32)fpPingCb; + strPingCmd.u8TTL = u8TTL; + + s8Ret = SOCKET_REQUEST(SOCKET_CMD_PING, (uint8*)&strPingCmd, sizeof(tstrPingCmd), NULL, 0, 0); + } + return s8Ret; +} diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/socket/source/socket_internal.h b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/socket/source/socket_internal.h new file mode 100644 index 000000000..e5c18961a --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/socket/source/socket_internal.h @@ -0,0 +1,61 @@ +/** + * + * \file + * + * \brief BSD compatible socket interface internal types. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef __SOCKET_INTERNAL_H__ +#define __SOCKET_INTERNAL_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +INCLUDES +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ + +#include "socket/include/socket.h" +#include "socket/include/m2m_socket_host_if.h" + + +/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=* +FUNCTION PROTOTYPES +*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ + +NMI_API void Socket_ReadSocketData(SOCKET sock, tstrSocketRecvMsg *pstrRecv,uint8 u8SocketMsg, + uint32 u32StartAddress,uint16 u16ReadCount); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __SOCKET_H__ */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/spi_flash/include/spi_flash.h b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/spi_flash/include/spi_flash.h new file mode 100644 index 000000000..44c360a84 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/spi_flash/include/spi_flash.h @@ -0,0 +1,192 @@ +/** + * + * \file + * + * \brief SPI Flash. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +/** @defgroup SPIFLASHAPI SPI FLASH + */ + +#ifndef __SPI_FLASH_H__ +#define __SPI_FLASH_H__ +#include "common/include/nm_common.h" +#include "bus_wrapper/include/nm_bus_wrapper.h" +#include "driver/source/nmbus.h" +#include "spi_flash_map.h" + +/** @defgroup SPIFLASHFUNCTIONS Functions + * @ingroup SPIFLASHAPI + */ + + /**@{*/ +/*! + * @fn uint32 spi_flash_get_size(void); + * @brief Returns with \ref uint32 value which is total flash size\n + * @note Returned value in Mb (Mega Bit). + * @return SPI flash size in case of success and a ZERO value in case of failure. + */ +uint32 spi_flash_get_size(void); + +/*! + * @fn sint8 spi_flash_read(uint8 *, uint32, uint32); + * @brief Read a specified portion of data from SPI Flash.\n + * @param [out] pu8Buf + * Pointer to data buffer which will be filled with data in case of successful operation. + * @param [in] u32Addr + * Address (Offset) to read from at the SPI flash. + * @param [in] u32Sz + * Total size of data to be read in bytes + * @warning + * - Address (offset) plus size of data must not exceed flash size.\n + * - No firmware is required for reading from SPI flash.\n + * - In case of there is a running firmware, it is required to pause your firmware first + * before any trial to access SPI flash to avoid any racing between host and running firmware on bus using + * @ref m2m_wifi_download_mode + * @note + * - It is blocking function\n + * @sa m2m_wifi_download_mode, spi_flash_get_size + * @return The function returns @ref M2M_SUCCESS for successful operations and a negative value otherwise. + */ +sint8 spi_flash_read(uint8 *pu8Buf, uint32 u32Addr, uint32 u32Sz); + +/*! + * @fn sint8 spi_flash_write(uint8 *, uint32, uint32); + * @brief Write a specified portion of data to SPI Flash.\n + * @param [in] pu8Buf + * Pointer to data buffer which contains the data to be written. + * @param [in] u32Offset + * Address (Offset) to write at the SPI flash. + * @param [in] u32Sz + * Total number of size of data bytes + * @note + * - It is blocking function\n + * - It is user's responsibility to verify that data has been written successfully + * by reading data again and comparing it with the original. + * @warning + * - Address (offset) plus size of data must not exceed flash size.\n + * - No firmware is required for writing to SPI flash.\n + * - In case of there is a running firmware, it is required to pause your firmware first + * before any trial to access SPI flash to avoid any racing between host and running firmware on bus using + * @ref m2m_wifi_download_mode. + * - Before writing to any section, it is required to erase that section first. + * @sa m2m_wifi_download_mode, spi_flash_get_size, spi_flash_erase + * @return The function returns @ref M2M_SUCCESS for successful operations and a negative value otherwise. + + */ +sint8 spi_flash_write(uint8* pu8Buf, uint32 u32Offset, uint32 u32Sz); + +/*! + * @fn sint8 spi_flash_erase(uint32, uint32); + * @brief Erase a specified portion of SPI Flash.\n + * @param [in] u32Offset + * Address (Offset) to erase from the SPI flash. + * @param [in] u32Sz + * Total number of bytes required to be erased. + * @note It is blocking function \n +* @warning +* - Address (offset) plus size of data must not exceed flash size.\n +* - No firmware is required for writing to SPI flash.\n + * - In case of there is a running firmware, it is required to pause your firmware first + * before any trial to access SPI flash to avoid any racing between host and running firmware on bus using + * @ref m2m_wifi_download_mode + * @sa m2m_wifi_download_mode, spi_flash_get_size + * @return The function returns @ref M2M_SUCCESS for successful operations and a negative value otherwise. + * \section SPIFLASHExample Example + * @code{.c} + * #include "spi_flash/include/spi_flash.h" + * + * #define DATA_TO_REPLACE "THIS IS A NEW SECTOR IN FLASH" + * + * int main() + * { + * uint8 au8FlashContent[FLASH_SECTOR_SZ] = {0}; + * uint32 u32FlashTotalSize = 0; + * uint32 u32FlashOffset = 0; + * + * ret = m2m_wifi_download_mode(); + * if(M2M_SUCCESS != ret) + * { + * printf("Unable to enter download mode\r\n"); + * } + * else + * { + * u32FlashTotalSize = spi_flash_get_size(); + * } + * + * while((u32FlashTotalSize > u32FlashOffset) && (M2M_SUCCESS == ret)) + * { + * ret = spi_flash_read(au8FlashContent, u32FlashOffset, FLASH_SECTOR_SZ); + * if(M2M_SUCCESS != ret) + * { + * printf("Unable to read SPI sector\r\n"); + * break; + * } + * memcpy(au8FlashContent, DATA_TO_REPLACE, strlen(DATA_TO_REPLACE)); + * + * ret = spi_flash_erase(u32FlashOffset, FLASH_SECTOR_SZ); + * if(M2M_SUCCESS != ret) + * { + * printf("Unable to erase SPI sector\r\n"); + * break; + * } + * + * ret = spi_flash_write(au8FlashContent, u32FlashOffset, FLASH_SECTOR_SZ); + * if(M2M_SUCCESS != ret) + * { + * printf("Unable to write SPI sector\r\n"); + * break; + * } + * u32FlashOffset += FLASH_SECTOR_SZ; + * } + * + * if(M2M_SUCCESS == ret) + * { + * printf("Successful operations\r\n"); + * } + * else + * { + * printf("Failed operations\r\n"); + * } + * + * while(1); + * return M2M_SUCCESS; + * } + * @endcode + */ + +sint8 spi_flash_erase(uint32 u32Offset, uint32 u32Sz); + + +/**@} + */ + + +#endif //__SPI_FLASH_H__ \ No newline at end of file diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/spi_flash/include/spi_flash_map.h b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/spi_flash/include/spi_flash_map.h new file mode 100644 index 000000000..40ea38d6c --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/spi_flash/include/spi_flash_map.h @@ -0,0 +1,267 @@ +/** + * + * \file + * + * \brief SPI Flash. + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef __SPI_FLASH_MAP_H__ +#define __SPI_FLASH_MAP_H__ + +//#define DOWNLOAD_ROLLBACK +//#define OTA_GEN +#define _PROGRAM_POWER_SAVE_ +#define BT_IMAGE_PRESENT + +/* =======*=======*=======*=======*======= + * General Sizes for Flash Memory + * =======*=======*=======*=======*======= + */ + +#define FLASH_START_ADDR (0UL) +/*! M2M_OTA_IMAGE2_OFFSET) +#error "Exceed Flash Size" +#endif /* ((FLASH_COMMON_SZ + OTA_IMAGE_SIZE + HOST_CONTROL_FLASH_SZ) > M2M_OTA_IMAGE2_OFFSET) */ +#if ((M2M_OTA_IMAGE2_OFFSET + OTA_IMAGE_SIZE) > FLASH_8M_TOTAL_SZ) +#error "OTA Exceed Flash Size" +#endif /* ((M2M_OTA_IMAGE2_OFFSET + OTA_IMAGE_SIZE) > FLASH_8M_TOTAL_SZ) */ + +#endif /* __SPI_FLASH_MAP_H__ */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/spi_flash/source/spi_flash.c b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/spi_flash/source/spi_flash.c new file mode 100644 index 000000000..ad91e04a6 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/components/wifi/winc3400/wifi_drv/spi_flash/source/spi_flash.c @@ -0,0 +1,677 @@ +/** + * + * \file + * + * \brief SPI Flash. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef PROFILING +#include "windows.h" +#endif +#include "spi_flash/include/spi_flash.h" +#define DUMMY_REGISTER (0x1084) + +#define TIMEOUT (-1) /*MS*/ + +//#define DISABLE_UNSED_FLASH_FUNCTIONS + +#define HOST_SHARE_MEM_BASE (0xd0000UL) +#define CORTUS_SHARE_MEM_BASE (0x60000000UL) +#define NMI_SPI_FLASH_ADDR (0x111c) +/*********************************************************** +SPI Flash DMA +***********************************************************/ +#define GET_UINT32(X,Y) (X[0+Y] + ((uint32)X[1+Y]<<8) + ((uint32)X[2+Y]<<16) +((uint32)X[3+Y]<<24)) +#define SPI_FLASH_BASE (0x10200) +#define SPI_FLASH_MODE (SPI_FLASH_BASE + 0x00) +#define SPI_FLASH_CMD_CNT (SPI_FLASH_BASE + 0x04) +#define SPI_FLASH_DATA_CNT (SPI_FLASH_BASE + 0x08) +#define SPI_FLASH_BUF1 (SPI_FLASH_BASE + 0x0c) +#define SPI_FLASH_BUF2 (SPI_FLASH_BASE + 0x10) +#define SPI_FLASH_BUF_DIR (SPI_FLASH_BASE + 0x14) +#define SPI_FLASH_TR_DONE (SPI_FLASH_BASE + 0x18) +#define SPI_FLASH_DMA_ADDR (SPI_FLASH_BASE + 0x1c) +#define SPI_FLASH_MSB_CTL (SPI_FLASH_BASE + 0x20) +#define SPI_FLASH_TX_CTL (SPI_FLASH_BASE + 0x24) + +/*********************************************/ +/* STATIC FUNCTIONS */ +/*********************************************/ + +/** +* @fn spi_flash_read_status_reg +* @brief Read status register +* @param[OUT] val + value of status reg +* @return Status of execution +* @note Compatible with MX25L6465E +* @author M. Abdelmawla +* @version 1.0 +*/ +static sint8 spi_flash_read_status_reg(uint8 * val) +{ + sint8 ret = M2M_SUCCESS; + uint8 cmd[1]; + uint32 reg; + + cmd[0] = 0x05; + + ret += nm_write_reg(SPI_FLASH_DATA_CNT, 4); + ret += nm_write_reg(SPI_FLASH_BUF1, cmd[0]); + ret += nm_write_reg(SPI_FLASH_BUF_DIR, 0x01); + ret += nm_write_reg(SPI_FLASH_DMA_ADDR, DUMMY_REGISTER); + ret += nm_write_reg(SPI_FLASH_CMD_CNT, 1 | (1<<7)); + do + { + ret += nm_read_reg_with_ret(SPI_FLASH_TR_DONE, (uint32 *)®); + if(M2M_SUCCESS != ret) break; + } + while(reg != 1); + + reg = (M2M_SUCCESS == ret)?(nm_read_reg(DUMMY_REGISTER)):(0); + *val = reg & 0xff; + return ret; +} + +#ifdef DISABLE_UNSED_FLASH_FUNCTIONS +/** +* @fn spi_flash_read_security_reg +* @brief Read security register +* @return Security register value +* @note Compatible with MX25L6465E +* @author M. Abdelmawla +* @version 1.0 +*/ +static uint8 spi_flash_read_security_reg(void) +{ + uint8 cmd[1]; + uint32 reg; + sint8 ret = M2M_SUCCESS; + + cmd[0] = 0x2b; + + ret += nm_write_reg(SPI_FLASH_DATA_CNT, 1); + ret += nm_write_reg(SPI_FLASH_BUF1, cmd[0]); + ret += nm_write_reg(SPI_FLASH_BUF_DIR, 0x01); + ret += nm_write_reg(SPI_FLASH_DMA_ADDR, DUMMY_REGISTER); + ret += nm_write_reg(SPI_FLASH_CMD_CNT, 1 | (1<<7)); + do + { + ret += nm_read_reg_with_ret(SPI_FLASH_TR_DONE, (uint32 *)®); + if(M2M_SUCCESS != ret) break; + } + while(reg != 1); + reg = (M2M_SUCCESS == ret)?(nm_read_reg(DUMMY_REGISTER)):(0); + + return (sint8)reg & 0xff; +} + +/** +* @fn spi_flash_gang_unblock +* @brief Unblock all flash area +* @note Compatible with MX25L6465E +* @author M. Abdelmawla +* @version 1.0 +*/ +static sint8 spi_flash_gang_unblock(void) +{ + uint8 cmd[1]; + uint32 val = 0; + sint8 ret = M2M_SUCCESS; + + cmd[0] = 0x98; + + ret += nm_write_reg(SPI_FLASH_DATA_CNT, 0); + ret += nm_write_reg(SPI_FLASH_BUF1, cmd[0]); + ret += nm_write_reg(SPI_FLASH_BUF_DIR, 0x01); + ret += nm_write_reg(SPI_FLASH_DMA_ADDR, 0); + ret += nm_write_reg(SPI_FLASH_CMD_CNT, 1 | (1<<7)); + do + { + ret += nm_read_reg_with_ret(SPI_FLASH_TR_DONE, (uint32 *)&val); + if(M2M_SUCCESS != ret) break; + } + while(val != 1); + + return ret; +} + +/** +* @fn spi_flash_clear_security_flags +* @brief Clear all security flags +* @note Compatible with MX25L6465E +* @author M. Abdelmawla +* @version 1.0 +*/ +static sint8 spi_flash_clear_security_flags(void) +{ + uint8 cmd[1]; + uint32 val = 0; + sint8 ret = M2M_SUCCESS; + + cmd[0] = 0x30; + + ret += nm_write_reg(SPI_FLASH_DATA_CNT, 0); + ret += nm_write_reg(SPI_FLASH_BUF1, cmd[0]); + ret += nm_write_reg(SPI_FLASH_BUF_DIR, 0x01); + ret += nm_write_reg(SPI_FLASH_DMA_ADDR, 0); + ret += nm_write_reg(SPI_FLASH_CMD_CNT, 1 | (1<<7)); + do + { + ret += nm_read_reg_with_ret(SPI_FLASH_TR_DONE, (uint32 *)&val); + if(M2M_SUCCESS != ret) break; + } + while(val != 1); + + return ret; +} +#endif + +/** +* @fn spi_flash_load_to_cortus_mem +* @brief Load data from SPI flash into cortus memory +* @param[IN] u32MemAdr +* Cortus load address. It must be set to its AHB access address +* @param[IN] u32FlashAdr +* Address to read from at the SPI flash +* @param[IN] u32Sz +* Data size +* @return Status of execution +* @note Compatible with MX25L6465E and should be working with other types +* @author M. Abdelmawla +* @version 1.0 +*/ +static sint8 spi_flash_load_to_cortus_mem(uint32 u32MemAdr, uint32 u32FlashAdr, uint32 u32Sz) +{ + uint8 cmd[5]; + uint32 val = 0; + sint8 ret = M2M_SUCCESS; + + cmd[0] = 0x0b; + cmd[1] = (uint8)(u32FlashAdr >> 16); + cmd[2] = (uint8)(u32FlashAdr >> 8); + cmd[3] = (uint8)(u32FlashAdr); + cmd[4] = 0xA5; + + ret += nm_write_reg(SPI_FLASH_DATA_CNT, u32Sz); + ret += nm_write_reg(SPI_FLASH_BUF1, cmd[0]|(cmd[1]<<8)|(cmd[2]<<16)|(cmd[3]<<24)); + ret += nm_write_reg(SPI_FLASH_BUF2, cmd[4]); + ret += nm_write_reg(SPI_FLASH_BUF_DIR, 0x1f); + ret += nm_write_reg(SPI_FLASH_DMA_ADDR, u32MemAdr); + ret += nm_write_reg(SPI_FLASH_CMD_CNT, 5 | (1<<7)); + do + { + ret += nm_read_reg_with_ret(SPI_FLASH_TR_DONE, (uint32 *)&val); + if(M2M_SUCCESS != ret) break; + } + while(val != 1); + + return ret; +} + +/** +* @fn spi_flash_sector_erase +* @brief Erase sector (4KB) +* @param[IN] u32FlashAdr +* Any memory address within the sector +* @return Status of execution +* @note Compatible with MX25L6465E and should be working with other types +* @author M. Abdelmawla +* @version 1.0 +*/ +static sint8 spi_flash_sector_erase(uint32 u32FlashAdr) +{ + uint8 cmd[4]; + uint32 val = 0; + sint8 ret = M2M_SUCCESS; + + cmd[0] = 0x20; + cmd[1] = (uint8)(u32FlashAdr >> 16); + cmd[2] = (uint8)(u32FlashAdr >> 8); + cmd[3] = (uint8)(u32FlashAdr); + + ret += nm_write_reg(SPI_FLASH_DATA_CNT, 0); + ret += nm_write_reg(SPI_FLASH_BUF1, cmd[0]|(cmd[1]<<8)|(cmd[2]<<16)|(cmd[3]<<24)); + ret += nm_write_reg(SPI_FLASH_BUF_DIR, 0x0f); + ret += nm_write_reg(SPI_FLASH_DMA_ADDR, 0); + ret += nm_write_reg(SPI_FLASH_CMD_CNT, 4 | (1<<7)); + do + { + ret += nm_read_reg_with_ret(SPI_FLASH_TR_DONE, (uint32 *)&val); + if(M2M_SUCCESS != ret) break; + } + while(val != 1); + + return ret; +} + +/** +* @fn spi_flash_write_enable +* @brief Send write enable command to SPI flash +* @return Status of execution +* @note Compatible with MX25L6465E and should be working with other types +* @author M. Abdelmawla +* @version 1.0 +*/ +static sint8 spi_flash_write_enable(void) +{ + uint8 cmd[1]; + uint32 val = 0; + sint8 ret = M2M_SUCCESS; + + cmd[0] = 0x06; + + ret += nm_write_reg(SPI_FLASH_DATA_CNT, 0); + ret += nm_write_reg(SPI_FLASH_BUF1, cmd[0]); + ret += nm_write_reg(SPI_FLASH_BUF_DIR, 0x01); + ret += nm_write_reg(SPI_FLASH_DMA_ADDR, 0); + ret += nm_write_reg(SPI_FLASH_CMD_CNT, 1 | (1<<7)); + do + { + ret += nm_read_reg_with_ret(SPI_FLASH_TR_DONE, (uint32 *)&val); + if(M2M_SUCCESS != ret) break; + } + while(val != 1); + + return ret; +} + +/** +* @fn spi_flash_write_disable +* @brief Send write disable command to SPI flash +* @note Compatible with MX25L6465E and should be working with other types +* @author M. Abdelmawla +* @version 1.0 +*/ +static sint8 spi_flash_write_disable(void) +{ + uint8 cmd[1]; + uint32 val = 0; + sint8 ret = M2M_SUCCESS; + cmd[0] = 0x04; + + ret += nm_write_reg(SPI_FLASH_DATA_CNT, 0); + ret += nm_write_reg(SPI_FLASH_BUF1, cmd[0]); + ret += nm_write_reg(SPI_FLASH_BUF_DIR, 0x01); + ret += nm_write_reg(SPI_FLASH_DMA_ADDR, 0); + ret += nm_write_reg(SPI_FLASH_CMD_CNT, 1 | (1<<7)); + do + { + ret += nm_read_reg_with_ret(SPI_FLASH_TR_DONE, (uint32 *)&val); + if(M2M_SUCCESS != ret) break; + } + while(val != 1); + + return ret; +} + +/** +* @fn spi_flash_page_program +* @brief Write data (less than page size) from cortus memory to SPI flash +* @param[IN] u32MemAdr +* Cortus data address. It must be set to its AHB access address +* @param[IN] u32FlashAdr +* Address to write to at the SPI flash +* @param[IN] u32Sz +* Data size +* @note Compatible with MX25L6465E and should be working with other types +* @author M. Abdelmawla +* @version 1.0 +*/ +static sint8 spi_flash_page_program(uint32 u32MemAdr, uint32 u32FlashAdr, uint32 u32Sz) +{ + uint8 cmd[4]; + uint32 val = 0; + sint8 ret = M2M_SUCCESS; + + cmd[0] = 0x02; + cmd[1] = (uint8)(u32FlashAdr >> 16); + cmd[2] = (uint8)(u32FlashAdr >> 8); + cmd[3] = (uint8)(u32FlashAdr); + + ret += nm_write_reg(SPI_FLASH_DATA_CNT, 0); + ret += nm_write_reg(SPI_FLASH_BUF1, cmd[0]|(cmd[1]<<8)|(cmd[2]<<16)|(cmd[3]<<24)); + ret += nm_write_reg(SPI_FLASH_BUF_DIR, 0x0f); + ret += nm_write_reg(SPI_FLASH_DMA_ADDR, u32MemAdr); + ret += nm_write_reg(SPI_FLASH_CMD_CNT, 4 | (1<<7) | ((u32Sz & 0xfffff) << 8)); + do + { + ret += nm_read_reg_with_ret(SPI_FLASH_TR_DONE, (uint32 *)&val); + if(M2M_SUCCESS != ret) break; + } + while(val != 1); + + return ret; +} + +/** +* @fn spi_flash_read_internal +* @brief Read from data from SPI flash +* @param[OUT] pu8Buf +* Pointer to data buffer +* @param[IN] u32Addr +* Address to read from at the SPI flash +* @param[IN] u32Sz +* Data size +* @note Data size must be < 64KB (limitation imposed by the bus wrapper) +* @author M. Abdelmawla +* @version 1.0 +*/ +static sint8 spi_flash_read_internal(uint8 *pu8Buf, uint32 u32Addr, uint32 u32Sz) +{ + sint8 ret = M2M_SUCCESS; + /* read size must be < 64KB */ + ret = spi_flash_load_to_cortus_mem(HOST_SHARE_MEM_BASE, u32Addr, u32Sz); + if(M2M_SUCCESS != ret) goto ERR; + ret = nm_read_block(HOST_SHARE_MEM_BASE, pu8Buf, u32Sz); +ERR: + return ret; +} + +/** +* @fn spi_flash_pp +* @brief Program data of size less than a page (256 bytes) at the SPI flash +* @param[IN] u32Offset +* Address to write to at the SPI flash +* @param[IN] pu8Buf +* Pointer to data buffer +* @param[IN] u32Sz +* Data size +* @return Status of execution +* @author M. Abdelmawla +* @version 1.0 +*/ +static sint8 spi_flash_pp(uint32 u32Offset, uint8 *pu8Buf, uint16 u16Sz) +{ + sint8 ret = M2M_SUCCESS; + uint8 tmp; + spi_flash_write_enable(); + /* use shared packet memory as temp mem */ + ret += nm_write_block(HOST_SHARE_MEM_BASE, pu8Buf, u16Sz); + ret += spi_flash_page_program(HOST_SHARE_MEM_BASE, u32Offset, u16Sz); + do + { + if(ret != M2M_SUCCESS) goto ERR; + ret += spi_flash_read_status_reg(&tmp); + } + while(tmp & 0x01); + ret += spi_flash_write_disable(); +ERR: + return ret; +} + +/** +* @fn spi_flash_rdid +* @brief Read SPI Flash ID +* @return SPI FLash ID +* @author M.S.M +* @version 1.0 +*/ +static uint32 spi_flash_rdid(void) +{ + unsigned char cmd[1]; + uint32 reg = 0; + uint32 cnt = 0; + sint8 ret = M2M_SUCCESS; + + cmd[0] = 0x9f; + + ret += nm_write_reg(SPI_FLASH_DATA_CNT, 4); + ret += nm_write_reg(SPI_FLASH_BUF1, cmd[0]); + ret += nm_write_reg(SPI_FLASH_BUF_DIR, 0x1); + ret += nm_write_reg(SPI_FLASH_DMA_ADDR, DUMMY_REGISTER); + ret += nm_write_reg(SPI_FLASH_CMD_CNT, 1 | (1<<7)); + do + { + ret += nm_read_reg_with_ret(SPI_FLASH_TR_DONE, (uint32 *)®); + if(M2M_SUCCESS != ret) break; + if(++cnt > 500) + { + ret = M2M_ERR_INIT; + break; + } + } + while(reg != 1); + reg = (M2M_SUCCESS == ret)?(nm_read_reg(DUMMY_REGISTER)):(0); + M2M_PRINT("Flash ID %x \n",(unsigned int)reg); + return reg; +} + +/** +* @fn spi_flash_unlock +* @brief Unlock SPI Flash +* @author M.S.M +* @version 1.0 +*/ +#if 0 +static void spi_flash_unlock(void) +{ + uint8 tmp; + tmp = spi_flash_read_security_reg(); + spi_flash_clear_security_flags(); + if(tmp & 0x80) + { + spi_flash_write_enable(); + spi_flash_gang_unblock(); + } +} +#endif + +/*********************************************/ +/* GLOBAL FUNCTIONS */ +/*********************************************/ + +/** +* @fn spi_flash_read +* @brief Read from data from SPI flash +* @param[OUT] pu8Buf +* Pointer to data buffer +* @param[IN] u32offset +* Address to read from at the SPI flash +* @param[IN] u32Sz +* Data size +* @return Status of execution +* @note Data size is limited by the SPI flash size only +* @author M. Abdelmawla +* @version 1.0 +*/ +sint8 spi_flash_read(uint8 *pu8Buf, uint32 u32offset, uint32 u32Sz) +{ + sint8 ret = M2M_SUCCESS; + if(u32Sz > FLASH_BLOCK_SIZE) + { + do + { + ret = spi_flash_read_internal(pu8Buf, u32offset, FLASH_BLOCK_SIZE); + if(M2M_SUCCESS != ret) goto ERR; + u32Sz -= FLASH_BLOCK_SIZE; + u32offset += FLASH_BLOCK_SIZE; + pu8Buf += FLASH_BLOCK_SIZE; + } while(u32Sz > FLASH_BLOCK_SIZE); + } + + ret = spi_flash_read_internal(pu8Buf, u32offset, u32Sz); + +ERR: + return ret; +} + +/** +* @fn spi_flash_write +* @brief Proram SPI flash +* @param[IN] pu8Buf +* Pointer to data buffer +* @param[IN] u32Offset +* Address to write to at the SPI flash +* @param[IN] u32Sz +* Data size +* @return Status of execution +* @author M. Abdelmawla +* @version 1.0 +*/ +sint8 spi_flash_write(uint8* pu8Buf, uint32 u32Offset, uint32 u32Sz) +{ +#ifdef PROFILING + unsigned long long t1 = 0; + uint32 percent =0; + uint32 tpercent =0; +#endif + sint8 ret = M2M_SUCCESS; + uint32 u32wsz; + uint32 u32off; + uint32 u32Blksz; + u32Blksz = FLASH_PAGE_SZ; + u32off = u32Offset % u32Blksz; +#ifdef PROFILING + tpercent = (u32Sz/u32Blksz)+((u32Sz%u32Blksz)>0); + t1 = GetTickCount64(); + M2M_PRINT(">Start programming...\r\n"); +#endif + if(u32Sz<=0) + { + M2M_ERR("Data size = %d",(int)u32Sz); + ret = M2M_ERR_FAIL; + goto ERR; + } + + if (u32off)/*first part of data in the address page*/ + { + u32wsz = u32Blksz - u32off; + if(spi_flash_pp(u32Offset, pu8Buf, (uint16)BSP_MIN(u32Sz, u32wsz))!=M2M_SUCCESS) + { + ret = M2M_ERR_FAIL; + goto ERR; + } + if (u32Sz < u32wsz) goto EXIT; + pu8Buf += u32wsz; + u32Offset += u32wsz; + u32Sz -= u32wsz; + } + while (u32Sz > 0) + { + u32wsz = BSP_MIN(u32Sz, u32Blksz); + + /*write complete page or the remaining data*/ + if(spi_flash_pp(u32Offset, pu8Buf, (uint16)u32wsz)!=M2M_SUCCESS) + { + ret = M2M_ERR_FAIL; + goto ERR; + } + pu8Buf += u32wsz; + u32Offset += u32wsz; + u32Sz -= u32wsz; +#ifdef PROFILING + percent++; + printf("\r>Complete Percentage = %d%%.\r",((percent*100)/tpercent)); +#endif + } +EXIT: +#ifdef PROFILING + M2M_PRINT("\rDone\t\t\t\t\t\t"); + M2M_PRINT("\n#Programming time = %f sec\n\r",(GetTickCount64() - t1)/1000.0); +#endif +ERR: + return ret; +} + +/** +* @fn spi_flash_erase +* @brief Erase from data from SPI flash +* @param[IN] u32Offset +* Address to write to at the SPI flash +* @param[IN] u32Sz +* Data size +* @return Status of execution +* @note Data size is limited by the SPI flash size only +* @author M. Abdelmawla +* @version 1.0 +*/ +sint8 spi_flash_erase(uint32 u32Offset, uint32 u32Sz) +{ + uint32 i = 0; + sint8 ret = M2M_SUCCESS; + uint8 tmp = 0; +#ifdef PROFILING + unsigned long long t; + t = GetTickCount64(); +#endif + M2M_DBG("\r\n>Start erasing...\r\n"); + for(i = u32Offset; i < (u32Sz +u32Offset); i += (16*FLASH_PAGE_SZ)) + { + ret += spi_flash_write_enable(); + ret += spi_flash_read_status_reg(&tmp); + ret += spi_flash_sector_erase(i); + ret += spi_flash_read_status_reg(&tmp); + do + { + if(ret != M2M_SUCCESS) goto ERR; + ret += spi_flash_read_status_reg(&tmp); + }while(tmp & 0x01); + + } + M2M_DBG("Done\r\n"); +#ifdef PROFILING + M2M_PRINT("#Erase time = %f sec\n", (GetTickCount64()-t)/1000.0); +#endif +ERR: + return ret; +} + +/** +* @fn spi_flash_get_size +* @brief Get size of SPI Flash +* @return Size of Flash +* @author M.S.M +* @version 1.0 +*/ +uint32 spi_flash_get_size(void) +{ + uint32 u32FlashId = 0, u32FlashPwr = 0; + static uint32 gu32InernalFlashSize= 0; + + if(!gu32InernalFlashSize) + { + u32FlashId = spi_flash_rdid();//spi_flash_probe(); + if(u32FlashId != 0xffffffff) + { + /*flash size is the third byte from the FLASH RDID*/ + u32FlashPwr = ((u32FlashId>>16)&0xff) - 0x11; /*2MBIT is the min*/ + /*That number power 2 to get the flash size*/ + gu32InernalFlashSize = 1<Microchip Support + */ +#ifndef CLK_GENCLK_H_INCLUDED +#define CLK_GENCLK_H_INCLUDED + +#include "parts.h" + +#if SAM3S +# include "sam3s/genclk.h" +#elif SAM3U +# include "sam3u/genclk.h" +#elif SAM3N +# include "sam3n/genclk.h" +#elif SAM3XA +# include "sam3x/genclk.h" +#elif SAM4S +# include "sam4s/genclk.h" +#elif SAM4L +# include "sam4l/genclk.h" +#elif SAM4E +# include "sam4e/genclk.h" +#elif SAM4N +# include "sam4n/genclk.h" +#elif SAM4C +# include "sam4c/genclk.h" +#elif SAM4CM +# include "sam4cm/genclk.h" +#elif SAM4CP +# include "sam4cp/genclk.h" +#elif SAMG +# include "samg/genclk.h" +#elif SAMV71 +# include "samv71/genclk.h" +#elif SAMV70 +# include "samv70/genclk.h" +#elif SAME70 +# include "same70/genclk.h" +#elif SAMS70 +# include "sams70/genclk.h" +#elif (UC3A0 || UC3A1) +# include "uc3a0_a1/genclk.h" +#elif UC3A3 +# include "uc3a3_a4/genclk.h" +#elif UC3B +# include "uc3b0_b1/genclk.h" +#elif UC3C +# include "uc3c/genclk.h" +#elif UC3D +# include "uc3d/genclk.h" +#elif UC3L +# include "uc3l/genclk.h" +#else +# error Unsupported chip type +#endif + +/** + * \ingroup clk_group + * \defgroup genclk_group Generic Clock Management + * + * Generic clocks are configurable clocks which run outside the system + * clock domain. They are often connected to peripherals which have an + * asynchronous component running independently of the bus clock, e.g. + * USB controllers, low-power timers and RTCs, etc. + * + * Note that not all platforms have support for generic clocks; on such + * platforms, this API will not be available. + * + * @{ + */ + +/** + * \def GENCLK_DIV_MAX + * \brief Maximum divider supported by the generic clock implementation + */ +/** + * \enum genclk_source + * \brief Generic clock source ID + * + * Each generic clock may be generated from a different clock source. + * These are the available alternatives provided by the chip. + */ + +//! \name Generic clock configuration +//@{ +/** + * \struct genclk_config + * \brief Hardware representation of a set of generic clock parameters + */ +/** + * \fn void genclk_config_defaults(struct genclk_config *cfg, + * unsigned int id) + * \brief Initialize \a cfg to the default configuration for the clock + * identified by \a id. + */ +/** + * \fn void genclk_config_read(struct genclk_config *cfg, unsigned int id) + * \brief Read the currently active configuration of the clock + * identified by \a id into \a cfg. + */ +/** + * \fn void genclk_config_write(const struct genclk_config *cfg, + * unsigned int id) + * \brief Activate the configuration \a cfg on the clock identified by + * \a id. + */ +/** + * \fn void genclk_config_set_source(struct genclk_config *cfg, + * enum genclk_source src) + * \brief Select a new source clock \a src in configuration \a cfg. + */ +/** + * \fn void genclk_config_set_divider(struct genclk_config *cfg, + * unsigned int divider) + * \brief Set a new \a divider in configuration \a cfg. + */ +/** + * \fn void genclk_enable_source(enum genclk_source src) + * \brief Enable the source clock \a src used by a generic clock. + */ + //@} + +//! \name Enabling and disabling Generic Clocks +//@{ +/** + * \fn void genclk_enable(const struct genclk_config *cfg, unsigned int id) + * \brief Activate the configuration \a cfg on the clock identified by + * \a id and enable it. + */ +/** + * \fn void genclk_disable(unsigned int id) + * \brief Disable the generic clock identified by \a id. + */ +//@} + +/** + * \brief Enable the configuration defined by \a src and \a divider + * for the generic clock identified by \a id. + * + * \param id The ID of the generic clock. + * \param src The source clock of the generic clock. + * \param divider The divider used to generate the generic clock. + */ +static inline void genclk_enable_config(unsigned int id, enum genclk_source src, unsigned int divider) +{ + struct genclk_config gcfg; + + genclk_config_defaults(&gcfg, id); + genclk_enable_source(src); + genclk_config_set_source(&gcfg, src); + genclk_config_set_divider(&gcfg, divider); + genclk_enable(&gcfg, id); +} + +//! @} + +#endif /* CLK_GENCLK_H_INCLUDED */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/clock/osc.h b/hw-libs/drivers/SAMx70/ASF/common/services/clock/osc.h new file mode 100644 index 000000000..265cddc85 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/clock/osc.h @@ -0,0 +1,175 @@ +/** + * \file + * + * \brief Oscillator management + * + * Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef OSC_H_INCLUDED +#define OSC_H_INCLUDED + +#include "parts.h" +#include "ISBoards.h" + +#if SAM3S +# include "sam3s/osc.h" +#elif SAM3XA +# include "sam3x/osc.h" +#elif SAM3U +# include "sam3u/osc.h" +#elif SAM3N +# include "sam3n/osc.h" +#elif SAM4S +# include "sam4s/osc.h" +#elif SAM4E +# include "sam4e/osc.h" +#elif SAM4C +# include "sam4c/osc.h" +#elif SAM4CM +# include "sam4cm/osc.h" +#elif SAM4CP +# include "sam4cp/osc.h" +#elif SAM4L +# include "sam4l/osc.h" +#elif SAM4N +# include "sam4n/osc.h" +#elif SAMG +# include "samg/osc.h" +#elif SAMV71 +# include "samv71/osc.h" +#elif SAMV70 +# include "samv70/osc.h" +#elif SAME70 +# include "same70/osc.h" +#elif SAMS70 +# include "sams70/osc.h" +#elif (UC3A0 || UC3A1) +# include "uc3a0_a1/osc.h" +#elif UC3A3 +# include "uc3a3_a4/osc.h" +#elif UC3B +# include "uc3b0_b1/osc.h" +#elif UC3C +# include "uc3c/osc.h" +#elif UC3D +# include "uc3d/osc.h" +#elif UC3L +# include "uc3l/osc.h" +#elif XMEGA +# include "xmega/osc.h" +#else +# error Unsupported chip type +#endif + +/** + * \ingroup clk_group + * \defgroup osc_group Oscillator Management + * + * This group contains functions and definitions related to configuring + * and enabling/disabling on-chip oscillators. Internal RC-oscillators, + * external crystal oscillators and external clock generators are + * supported by this module. What all of these have in common is that + * they swing at a fixed, nominal frequency which is normally not + * adjustable. + * + * \par Example: Enabling an oscillator + * + * The following example demonstrates how to enable the external + * oscillator on XMEGA A and wait for it to be ready to use. The + * oscillator identifiers are platform-specific, so while the same + * procedure is used on all platforms, the parameter to osc_enable() + * will be different from device to device. + * \code + osc_enable(OSC_ID_XOSC); + osc_wait_ready(OSC_ID_XOSC); \endcode + * + * \section osc_group_board Board-specific Definitions + * If external oscillators are used, the board code must provide the + * following definitions for each of those: + * - \b BOARD__HZ: The nominal frequency of the oscillator. + * - \b BOARD__STARTUP_US: The startup time of the + * oscillator in microseconds. + * - \b BOARD__TYPE: The type of oscillator connected, i.e. + * whether it's a crystal or external clock, and sometimes what kind + * of crystal it is. The meaning of this value is platform-specific. + * + * @{ + */ + +//! \name Oscillator Management +//@{ +/** + * \fn void osc_enable(uint8_t id) + * \brief Enable oscillator \a id + * + * The startup time and mode value is automatically determined based on + * definitions in the board code. + */ +/** + * \fn void osc_disable(uint8_t id) + * \brief Disable oscillator \a id + */ +/** + * \fn osc_is_ready(uint8_t id) + * \brief Determine whether oscillator \a id is ready. + * \retval true Oscillator \a id is running and ready to use as a clock + * source. + * \retval false Oscillator \a id is not running. + */ +/** + * \fn uint32_t osc_get_rate(uint8_t id) + * \brief Return the frequency of oscillator \a id in Hz + */ + +#ifndef __ASSEMBLY__ + +/** + * \brief Wait until the oscillator identified by \a id is ready + * + * This function will busy-wait for the oscillator identified by \a id + * to become stable and ready to use as a clock source. + * + * \param id A number identifying the oscillator to wait for. + */ +static inline void osc_wait_ready(uint8_t id) +{ + while (!osc_is_ready(id)) { + /* Do nothing */ + } +} + +#endif /* __ASSEMBLY__ */ + +//@} + +//! @} + +#endif /* OSC_H_INCLUDED */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/clock/pll.h b/hw-libs/drivers/SAMx70/ASF/common/services/clock/pll.h new file mode 100644 index 000000000..447bf46cf --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/clock/pll.h @@ -0,0 +1,331 @@ +/** + * \file + * + * \brief PLL management + * + * Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef CLK_PLL_H_INCLUDED +#define CLK_PLL_H_INCLUDED + +#include "parts.h" +#include "ISBoards.h" + +#if SAM3S +# include "sam3s/pll.h" +#elif SAM3XA +# include "sam3x/pll.h" +#elif SAM3U +# include "sam3u/pll.h" +#elif SAM3N +# include "sam3n/pll.h" +#elif SAM4S +# include "sam4s/pll.h" +#elif SAM4E +# include "sam4e/pll.h" +#elif SAM4C +# include "sam4c/pll.h" +#elif SAM4CM +# include "sam4cm/pll.h" +#elif SAM4CP +# include "sam4cp/pll.h" +#elif SAM4L +# include "sam4l/pll.h" +#elif SAM4N +# include "sam4n/pll.h" +#elif SAMG +# include "samg/pll.h" +#elif SAMV71 +# include "samv71/pll.h" +#elif SAMV70 +# include "samv70/pll.h" +#elif SAME70 +# include "same70/pll.h" +#elif SAMS70 +# include "sams70/pll.h" +#elif (UC3A0 || UC3A1) +# include "uc3a0_a1/pll.h" +#elif UC3A3 +# include "uc3a3_a4/pll.h" +#elif UC3B +# include "uc3b0_b1/pll.h" +#elif UC3C +# include "uc3c/pll.h" +#elif UC3D +# include "uc3d/pll.h" +#elif (UC3L0128 || UC3L0256 || UC3L3_L4) +# include "uc3l/pll.h" +#elif XMEGA +# include "xmega/pll.h" +#else +# error Unsupported chip type +#endif + +/** + * \ingroup clk_group + * \defgroup pll_group PLL Management + * + * This group contains functions and definitions related to configuring + * and enabling/disabling on-chip PLLs. A PLL will take an input signal + * (the \em source), optionally divide the frequency by a configurable + * \em divider, and then multiply the frequency by a configurable \em + * multiplier. + * + * Some devices don't support input dividers; specifying any other + * divisor than 1 on these devices will result in an assertion failure. + * Other devices may have various restrictions to the frequency range of + * the input and output signals. + * + * \par Example: Setting up PLL0 with default parameters + * + * The following example shows how to configure and enable PLL0 using + * the default parameters specified using the configuration symbols + * listed above. + * \code + pll_enable_config_defaults(0); \endcode + * + * To configure, enable PLL0 using the default parameters and to disable + * a specific feature like Wide Bandwidth Mode (a UC3A3-specific + * PLL option.), you can use this initialization process. + * \code + struct pll_config pllcfg; + if (pll_is_locked(pll_id)) { + return; // Pll already running + } + pll_enable_source(CONFIG_PLL0_SOURCE); + pll_config_defaults(&pllcfg, 0); + pll_config_set_option(&pllcfg, PLL_OPT_WBM_DISABLE); + pll_enable(&pllcfg, 0); + pll_wait_for_lock(0); \endcode + * + * When the last function call returns, PLL0 is ready to be used as the + * main system clock source. + * + * \section pll_group_config Configuration Symbols + * + * Each PLL has a set of default parameters determined by the following + * configuration symbols in the application's configuration file: + * - \b CONFIG_PLLn_SOURCE: The default clock source connected to the + * input of PLL \a n. Must be one of the values defined by the + * #pll_source enum. + * - \b CONFIG_PLLn_MUL: The default multiplier (loop divider) of PLL + * \a n. + * - \b CONFIG_PLLn_DIV: The default input divider of PLL \a n. + * + * These configuration symbols determine the result of calling + * pll_config_defaults() and pll_get_default_rate(). + * + * @{ + */ + +//! \name Chip-specific PLL characteristics +//@{ +/** + * \def PLL_MAX_STARTUP_CYCLES + * \brief Maximum PLL startup time in number of slow clock cycles + */ +/** + * \def NR_PLLS + * \brief Number of on-chip PLLs + */ + +/** + * \def PLL_MIN_HZ + * \brief Minimum frequency that the PLL can generate + */ +/** + * \def PLL_MAX_HZ + * \brief Maximum frequency that the PLL can generate + */ +/** + * \def PLL_NR_OPTIONS + * \brief Number of PLL option bits + */ +//@} + +/** + * \enum pll_source + * \brief PLL clock source + */ + +//! \name PLL configuration +//@{ + +/** + * \struct pll_config + * \brief Hardware-specific representation of PLL configuration. + * + * This structure contains one or more device-specific values + * representing the current PLL configuration. The contents of this + * structure is typically different from platform to platform, and the + * user should not access any fields except through the PLL + * configuration API. + */ + +/** + * \fn void pll_config_init(struct pll_config *cfg, + * enum pll_source src, unsigned int div, unsigned int mul) + * \brief Initialize PLL configuration from standard parameters. + * + * \note This function may be defined inline because it is assumed to be + * called very few times, and usually with constant parameters. Inlining + * it will in such cases reduce the code size significantly. + * + * \param cfg The PLL configuration to be initialized. + * \param src The oscillator to be used as input to the PLL. + * \param div PLL input divider. + * \param mul PLL loop divider (i.e. multiplier). + * + * \return A configuration which will make the PLL run at + * (\a mul / \a div) times the frequency of \a src + */ +/** + * \def pll_config_defaults(cfg, pll_id) + * \brief Initialize PLL configuration using default parameters. + * + * After this function returns, \a cfg will contain a configuration + * which will make the PLL run at (CONFIG_PLLx_MUL / CONFIG_PLLx_DIV) + * times the frequency of CONFIG_PLLx_SOURCE. + * + * \param cfg The PLL configuration to be initialized. + * \param pll_id Use defaults for this PLL. + */ +/** + * \def pll_get_default_rate(pll_id) + * \brief Get the default rate in Hz of \a pll_id + */ +/** + * \fn void pll_config_set_option(struct pll_config *cfg, + * unsigned int option) + * \brief Set the PLL option bit \a option in the configuration \a cfg. + * + * \param cfg The PLL configuration to be changed. + * \param option The PLL option bit to be set. + */ +/** + * \fn void pll_config_clear_option(struct pll_config *cfg, + * unsigned int option) + * \brief Clear the PLL option bit \a option in the configuration \a cfg. + * + * \param cfg The PLL configuration to be changed. + * \param option The PLL option bit to be cleared. + */ +/** + * \fn void pll_config_read(struct pll_config *cfg, unsigned int pll_id) + * \brief Read the currently active configuration of \a pll_id. + * + * \param cfg The configuration object into which to store the currently + * active configuration. + * \param pll_id The ID of the PLL to be accessed. + */ +/** + * \fn void pll_config_write(const struct pll_config *cfg, + * unsigned int pll_id) + * \brief Activate the configuration \a cfg on \a pll_id + * + * \param cfg The configuration object representing the PLL + * configuration to be activated. + * \param pll_id The ID of the PLL to be updated. + */ + +//@} + +//! \name Interaction with the PLL hardware +//@{ +/** + * \fn void pll_enable(const struct pll_config *cfg, + * unsigned int pll_id) + * \brief Activate the configuration \a cfg and enable PLL \a pll_id. + * + * \param cfg The PLL configuration to be activated. + * \param pll_id The ID of the PLL to be enabled. + */ +/** + * \fn void pll_disable(unsigned int pll_id) + * \brief Disable the PLL identified by \a pll_id. + * + * After this function is called, the PLL identified by \a pll_id will + * be disabled. The PLL configuration stored in hardware may be affected + * by this, so if the caller needs to restore the same configuration + * later, it should either do a pll_config_read() before disabling the + * PLL, or remember the last configuration written to the PLL. + * + * \param pll_id The ID of the PLL to be disabled. + */ +/** + * \fn bool pll_is_locked(unsigned int pll_id) + * \brief Determine whether the PLL is locked or not. + * + * \param pll_id The ID of the PLL to check. + * + * \retval true The PLL is locked and ready to use as a clock source + * \retval false The PLL is not yet locked, or has not been enabled. + */ +/** + * \fn void pll_enable_source(enum pll_source src) + * \brief Enable the source of the pll. + * The source is enabled, if the source is not already running. + * + * \param src The ID of the PLL source to enable. + */ +/** + * \fn void pll_enable_config_defaults(unsigned int pll_id) + * \brief Enable the pll with the default configuration. + * PLL is enabled, if the PLL is not already locked. + * + * \param pll_id The ID of the PLL to enable. + */ + +/** + * \brief Wait for PLL \a pll_id to become locked + * + * \todo Use a timeout to avoid waiting forever and hanging the system + * + * \param pll_id The ID of the PLL to wait for. + * + * \retval STATUS_OK The PLL is now locked. + * \retval ERR_TIMEOUT Timed out waiting for PLL to become locked. + */ +static inline int pll_wait_for_lock(unsigned int pll_id) +{ + Assert(pll_id < NR_PLLS); + + while (!pll_is_locked(pll_id)) { + /* Do nothing */ + } + + return 0; +} + +//@} +//! @} + +#endif /* CLK_PLL_H_INCLUDED */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/clock/same70/genclk.h b/hw-libs/drivers/SAMx70/ASF/common/services/clock/same70/genclk.h new file mode 100644 index 000000000..848f48290 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/clock/same70/genclk.h @@ -0,0 +1,259 @@ +/** + * \file + * + * \brief Chip-specific generic clock management. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef CHIP_GENCLK_H_INCLUDED +#define CHIP_GENCLK_H_INCLUDED + +#include +#include + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \weakgroup genclk_group + * @{ + */ + +//! \name Programmable Clock Identifiers (PCK) +//@{ +#define GENCLK_PCK_0 0 //!< PCK0 ID +#define GENCLK_PCK_1 1 //!< PCK1 ID +#define GENCLK_PCK_2 2 //!< PCK2 ID +//@} + +//! \name Programmable Clock Sources (PCK) +//@{ + +enum genclk_source { + GENCLK_PCK_SRC_SLCK_RC = 0,//!< Internal 32kHz RC oscillator as PCK source clock + GENCLK_PCK_SRC_SLCK_XTAL = 1,//!< External 32kHz crystal oscillator as PCK source clock + GENCLK_PCK_SRC_SLCK_BYPASS = 2,//!< External 32kHz bypass oscillator as PCK source clock + GENCLK_PCK_SRC_MAINCK_4M_RC = 3,//!< Internal 4MHz RC oscillator as PCK source clock + GENCLK_PCK_SRC_MAINCK_8M_RC = 4,//!< Internal 8MHz RC oscillator as PCK source clock + GENCLK_PCK_SRC_MAINCK_12M_RC = 5,//!< Internal 12MHz RC oscillator as PCK source clock + GENCLK_PCK_SRC_MAINCK_XTAL = 6,//!< External crystal oscillator as PCK source clock + GENCLK_PCK_SRC_MAINCK_BYPASS = 7,//!< External bypass oscillator as PCK source clock + GENCLK_PCK_SRC_PLLACK = 8,//!< Use PLLACK as PCK source clock + GENCLK_PCK_SRC_MCK = 9,//!< Use Master Clk as PCK source clock +}; + +//@} + +//! \name Programmable Clock Prescalers (PCK) +//@{ + +enum genclk_divider { + GENCLK_PCK_PRES_1 = PMC_PCK_PRES(0), //!< Set PCK clock prescaler to 1 + GENCLK_PCK_PRES_2 = PMC_PCK_PRES(1), //!< Set PCK clock prescaler to 2 + GENCLK_PCK_PRES_4 = PMC_PCK_PRES(2), //!< Set PCK clock prescaler to 4 + GENCLK_PCK_PRES_8 = PMC_PCK_PRES(3), //!< Set PCK clock prescaler to 8 + GENCLK_PCK_PRES_16 = PMC_PCK_PRES(4), //!< Set PCK clock prescaler to 16 + GENCLK_PCK_PRES_32 = PMC_PCK_PRES(5), //!< Set PCK clock prescaler to 32 + GENCLK_PCK_PRES_64 = PMC_PCK_PRES(6), //!< Set PCK clock prescaler to 64 +}; + +//@} + +struct genclk_config { + uint32_t ctrl; +}; + +static inline void genclk_config_defaults(struct genclk_config *p_cfg, + uint32_t ul_id) +{ + ul_id = ul_id; + p_cfg->ctrl = 0; +} + +static inline void genclk_config_read(struct genclk_config *p_cfg, + uint32_t ul_id) +{ + p_cfg->ctrl = PMC->PMC_PCK[ul_id]; +} + +static inline void genclk_config_write(const struct genclk_config *p_cfg, + uint32_t ul_id) +{ + PMC->PMC_PCK[ul_id] = p_cfg->ctrl; +} + +//! \name Programmable Clock Source and Prescaler configuration +//@{ + +static inline void genclk_config_set_source(struct genclk_config *p_cfg, + enum genclk_source e_src) +{ + p_cfg->ctrl &= (~PMC_PCK_CSS_Msk); + + switch (e_src) { + case GENCLK_PCK_SRC_SLCK_RC: + case GENCLK_PCK_SRC_SLCK_XTAL: + case GENCLK_PCK_SRC_SLCK_BYPASS: + p_cfg->ctrl |= (PMC_PCK_CSS_SLOW_CLK); + break; + + case GENCLK_PCK_SRC_MAINCK_4M_RC: + case GENCLK_PCK_SRC_MAINCK_8M_RC: + case GENCLK_PCK_SRC_MAINCK_12M_RC: + case GENCLK_PCK_SRC_MAINCK_XTAL: + case GENCLK_PCK_SRC_MAINCK_BYPASS: + p_cfg->ctrl |= (PMC_PCK_CSS_MAIN_CLK); + break; + + case GENCLK_PCK_SRC_PLLACK: + p_cfg->ctrl |= (PMC_PCK_CSS_PLLA_CLK); + break; + + case GENCLK_PCK_SRC_MCK: + p_cfg->ctrl |= (PMC_PCK_CSS_MCK); + break; + + default: + break; + } +} + +static inline void genclk_config_set_divider(struct genclk_config *p_cfg, + uint32_t e_divider) +{ + p_cfg->ctrl &= ~PMC_PCK_PRES_Msk; + p_cfg->ctrl |= e_divider; +} + +//@} + +static inline void genclk_enable(const struct genclk_config *p_cfg, uint32_t ul_id) +{ + PMC->PMC_PCK[ul_id] = p_cfg->ctrl; + pmc_enable_pck(ul_id); +} + +static inline void genclk_disable(uint32_t ul_id) +{ + pmc_disable_pck(ul_id); +} + +static inline void genclk_enable_source(enum genclk_source e_src) +{ + switch (e_src) { + case GENCLK_PCK_SRC_SLCK_RC: + if (!osc_is_ready(OSC_SLCK_32K_RC)) { + osc_enable(OSC_SLCK_32K_RC); + osc_wait_ready(OSC_SLCK_32K_RC); + } + break; + + case GENCLK_PCK_SRC_SLCK_XTAL: + if (!osc_is_ready(OSC_SLCK_32K_XTAL)) { + osc_enable(OSC_SLCK_32K_XTAL); + osc_wait_ready(OSC_SLCK_32K_XTAL); + } + break; + + case GENCLK_PCK_SRC_SLCK_BYPASS: + if (!osc_is_ready(OSC_SLCK_32K_BYPASS)) { + osc_enable(OSC_SLCK_32K_BYPASS); + osc_wait_ready(OSC_SLCK_32K_BYPASS); + } + break; + + case GENCLK_PCK_SRC_MAINCK_4M_RC: + if (!osc_is_ready(OSC_MAINCK_4M_RC)) { + osc_enable(OSC_MAINCK_4M_RC); + osc_wait_ready(OSC_MAINCK_4M_RC); + } + break; + + case GENCLK_PCK_SRC_MAINCK_8M_RC: + if (!osc_is_ready(OSC_MAINCK_8M_RC)) { + osc_enable(OSC_MAINCK_8M_RC); + osc_wait_ready(OSC_MAINCK_8M_RC); + } + break; + + case GENCLK_PCK_SRC_MAINCK_12M_RC: + if (!osc_is_ready(OSC_MAINCK_12M_RC)) { + osc_enable(OSC_MAINCK_12M_RC); + osc_wait_ready(OSC_MAINCK_12M_RC); + } + break; + + case GENCLK_PCK_SRC_MAINCK_XTAL: + if (!osc_is_ready(OSC_MAINCK_XTAL)) { + osc_enable(OSC_MAINCK_XTAL); + osc_wait_ready(OSC_MAINCK_XTAL); + } + break; + + case GENCLK_PCK_SRC_MAINCK_BYPASS: + if (!osc_is_ready(OSC_MAINCK_BYPASS)) { + osc_enable(OSC_MAINCK_BYPASS); + osc_wait_ready(OSC_MAINCK_BYPASS); + } + break; + +#ifdef CONFIG_PLL0_SOURCE + case GENCLK_PCK_SRC_PLLACK: + pll_enable_config_defaults(0); + break; +#endif + + case GENCLK_PCK_SRC_MCK: + break; + + default: + Assert(false); + break; + } +} + +//! @} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +#endif /* CHIP_GENCLK_H_INCLUDED */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/clock/same70/osc.h b/hw-libs/drivers/SAMx70/ASF/common/services/clock/same70/osc.h new file mode 100644 index 000000000..9b1f25266 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/clock/same70/osc.h @@ -0,0 +1,237 @@ +/** + * \file + * + * \brief Chip-specific oscillator management functions. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef CHIP_OSC_H_INCLUDED +#define CHIP_OSC_H_INCLUDED + +#include "ISBoards.h" +#include "pmc.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/* + * Below BOARD_XXX macros are related to the specific board, and + * should be defined by the board code, otherwise default value are used. + */ +#if !defined(BOARD_FREQ_SLCK_XTAL) +# warning The board slow clock xtal frequency has not been defined. +# define BOARD_FREQ_SLCK_XTAL (32768UL) +#endif + +#if !defined(BOARD_FREQ_SLCK_BYPASS) +# warning The board slow clock bypass frequency has not been defined. +# define BOARD_FREQ_SLCK_BYPASS (32768UL) +#endif + +#if !defined(BOARD_FREQ_MAINCK_XTAL) +# warning The board main clock xtal frequency has not been defined. +# define BOARD_FREQ_MAINCK_XTAL (12000000UL) +#endif + +#if !defined(BOARD_FREQ_MAINCK_BYPASS) +# warning The board main clock bypass frequency has not been defined. +# define BOARD_FREQ_MAINCK_BYPASS (12000000UL) +#endif + +#if !defined(BOARD_OSC_STARTUP_US) +# warning The board main clock xtal startup time has not been defined. +# define BOARD_OSC_STARTUP_US (15625UL) +#endif + +/** + * \weakgroup osc_group + * @{ + */ + +//! \name Oscillator identifiers +//@{ +#define OSC_SLCK_32K_RC 0 //!< Internal 32kHz RC oscillator. +#define OSC_SLCK_32K_XTAL 1 //!< External 32kHz crystal oscillator. +#define OSC_SLCK_32K_BYPASS 2 //!< External 32kHz bypass oscillator. +#define OSC_MAINCK_4M_RC 3 //!< Internal 4MHz RC oscillator. +#define OSC_MAINCK_8M_RC 4 //!< Internal 8MHz RC oscillator. +#define OSC_MAINCK_12M_RC 5 //!< Internal 12MHz RC oscillator. +#define OSC_MAINCK_XTAL 6 //!< External crystal oscillator. +#define OSC_MAINCK_BYPASS 7 //!< External bypass oscillator. +//@} + +//! \name Oscillator clock speed in hertz +//@{ +#define OSC_SLCK_32K_RC_HZ CHIP_FREQ_SLCK_RC //!< Internal 32kHz RC oscillator. +#define OSC_SLCK_32K_XTAL_HZ BOARD_FREQ_SLCK_XTAL //!< External 32kHz crystal oscillator. +#define OSC_SLCK_32K_BYPASS_HZ BOARD_FREQ_SLCK_BYPASS //!< External 32kHz bypass oscillator. +#define OSC_MAINCK_4M_RC_HZ CHIP_FREQ_MAINCK_RC_4MHZ //!< Internal 4MHz RC oscillator. +#define OSC_MAINCK_8M_RC_HZ CHIP_FREQ_MAINCK_RC_8MHZ //!< Internal 8MHz RC oscillator. +#define OSC_MAINCK_12M_RC_HZ CHIP_FREQ_MAINCK_RC_12MHZ //!< Internal 12MHz RC oscillator. +#define OSC_MAINCK_XTAL_HZ BOARD_FREQ_MAINCK_XTAL //!< External crystal oscillator. +#define OSC_MAINCK_BYPASS_HZ BOARD_FREQ_MAINCK_BYPASS //!< External bypass oscillator. +//@} + +static inline void osc_enable(uint32_t ul_id) +{ + switch (ul_id) { + case OSC_SLCK_32K_RC: + break; + + case OSC_SLCK_32K_XTAL: + pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL); + break; + + case OSC_SLCK_32K_BYPASS: + pmc_switch_sclk_to_32kxtal(PMC_OSC_BYPASS); + break; + + + case OSC_MAINCK_4M_RC: + pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz); + break; + + case OSC_MAINCK_8M_RC: + pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz); + break; + + case OSC_MAINCK_12M_RC: + pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz); + break; + + + case OSC_MAINCK_XTAL: + pmc_switch_mainck_to_xtal(PMC_OSC_XTAL, + pmc_us_to_moscxtst(BOARD_OSC_STARTUP_US, + OSC_SLCK_32K_RC_HZ)); + break; + + case OSC_MAINCK_BYPASS: + pmc_switch_mainck_to_xtal(PMC_OSC_BYPASS, + pmc_us_to_moscxtst(BOARD_OSC_STARTUP_US, + OSC_SLCK_32K_RC_HZ)); + break; + } +} + +static inline void osc_disable(uint32_t ul_id) +{ + switch (ul_id) { + case OSC_SLCK_32K_RC: + case OSC_SLCK_32K_XTAL: + case OSC_SLCK_32K_BYPASS: + break; + + case OSC_MAINCK_4M_RC: + case OSC_MAINCK_8M_RC: + case OSC_MAINCK_12M_RC: + pmc_osc_disable_fastrc(); + break; + + case OSC_MAINCK_XTAL: + pmc_osc_disable_xtal(PMC_OSC_XTAL); + break; + + case OSC_MAINCK_BYPASS: + pmc_osc_disable_xtal(PMC_OSC_BYPASS); + break; + } +} + +static inline bool osc_is_ready(uint32_t ul_id) +{ + switch (ul_id) { + case OSC_SLCK_32K_RC: + return 1; + + case OSC_SLCK_32K_XTAL: + case OSC_SLCK_32K_BYPASS: + return pmc_osc_is_ready_32kxtal(); + + case OSC_MAINCK_4M_RC: + case OSC_MAINCK_8M_RC: + case OSC_MAINCK_12M_RC: + case OSC_MAINCK_XTAL: + case OSC_MAINCK_BYPASS: + return pmc_osc_is_ready_mainck(); + } + + return 0; +} + +static inline uint32_t osc_get_rate(uint32_t ul_id) +{ + switch (ul_id) { + case OSC_SLCK_32K_RC: + return OSC_SLCK_32K_RC_HZ; + + case OSC_SLCK_32K_XTAL: + return BOARD_FREQ_SLCK_XTAL; + + case OSC_SLCK_32K_BYPASS: + return BOARD_FREQ_SLCK_BYPASS; + + case OSC_MAINCK_4M_RC: + return OSC_MAINCK_4M_RC_HZ; + + case OSC_MAINCK_8M_RC: + return OSC_MAINCK_8M_RC_HZ; + + case OSC_MAINCK_12M_RC: + return OSC_MAINCK_12M_RC_HZ; + + case OSC_MAINCK_XTAL: + return BOARD_FREQ_MAINCK_XTAL; + + case OSC_MAINCK_BYPASS: + return BOARD_FREQ_MAINCK_BYPASS; + } + + return 0; +} + +//! @} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +#endif /* CHIP_OSC_H_INCLUDED */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/clock/same70/pll.h b/hw-libs/drivers/SAMx70/ASF/common/services/clock/same70/pll.h new file mode 100644 index 000000000..e7c732e6f --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/clock/same70/pll.h @@ -0,0 +1,259 @@ +/** + * \file + * + * \brief Chip-specific PLL definitions. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef CHIP_PLL_H_INCLUDED +#define CHIP_PLL_H_INCLUDED + +#include + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \weakgroup pll_group + * @{ + */ + +#define PLL_OUTPUT_MIN_HZ 160000000 +#define PLL_OUTPUT_MAX_HZ 500000000 + +#define PLL_INPUT_MIN_HZ 3000000 +#define PLL_INPUT_MAX_HZ 32000000 + +#define NR_PLLS 2 +#define PLLA_ID 0 +#define UPLL_ID 1 //!< USB UTMI PLL. + +#define PLL_UPLL_HZ 480000000 + +#define PLL_COUNT 0x3fU + +enum pll_source { + PLL_SRC_MAINCK_4M_RC = OSC_MAINCK_4M_RC, //!< Internal 4MHz RC oscillator. + PLL_SRC_MAINCK_8M_RC = OSC_MAINCK_8M_RC, //!< Internal 8MHz RC oscillator. + PLL_SRC_MAINCK_12M_RC = OSC_MAINCK_12M_RC, //!< Internal 12MHz RC oscillator. + PLL_SRC_MAINCK_XTAL = OSC_MAINCK_XTAL, //!< External crystal oscillator. + PLL_SRC_MAINCK_BYPASS = OSC_MAINCK_BYPASS, //!< External bypass oscillator. + PLL_NR_SOURCES, //!< Number of PLL sources. +}; + +struct pll_config { + uint32_t ctrl; +}; + +#define pll_get_default_rate(pll_id) \ + ((osc_get_rate(CONFIG_PLL##pll_id##_SOURCE) \ + * CONFIG_PLL##pll_id##_MUL) \ + / CONFIG_PLL##pll_id##_DIV) + +/* Force UTMI PLL parameters (Hardware defined) */ +#ifdef CONFIG_PLL1_SOURCE +# undef CONFIG_PLL1_SOURCE +#endif +#ifdef CONFIG_PLL1_MUL +# undef CONFIG_PLL1_MUL +#endif +#ifdef CONFIG_PLL1_DIV +# undef CONFIG_PLL1_DIV +#endif +#define CONFIG_PLL1_SOURCE PLL_SRC_MAINCK_XTAL +#define CONFIG_PLL1_MUL 0 +#define CONFIG_PLL1_DIV 0 + +/** + * \note The SAMV71 PLL hardware interprets mul as mul+1. For readability the + * hardware mul+1 is hidden in this implementation. Use mul as mul effective + * value. + */ +static inline void pll_config_init(struct pll_config *p_cfg, + enum pll_source e_src, uint32_t ul_div, uint32_t ul_mul) +{ + uint32_t vco_hz; + + Assert(e_src < PLL_NR_SOURCES); + + if (ul_div == 0 && ul_mul == 0) { /* Must only be true for UTMI PLL */ + p_cfg->ctrl = CKGR_UCKR_UPLLCOUNT(PLL_COUNT); + } else { /* PLLA */ + /* Calculate internal VCO frequency */ + vco_hz = osc_get_rate(e_src) / ul_div; + Assert(vco_hz >= PLL_INPUT_MIN_HZ); + Assert(vco_hz <= PLL_INPUT_MAX_HZ); + + vco_hz *= ul_mul; + Assert(vco_hz >= PLL_OUTPUT_MIN_HZ); + Assert(vco_hz <= PLL_OUTPUT_MAX_HZ); + + /* PMC hardware will automatically make it mul+1 */ + p_cfg->ctrl = CKGR_PLLAR_MULA(ul_mul - 1) | CKGR_PLLAR_DIVA(ul_div) \ + | CKGR_PLLAR_PLLACOUNT(PLL_COUNT); + } +} + +#define pll_config_defaults(cfg, pll_id) \ + pll_config_init(cfg, \ + CONFIG_PLL##pll_id##_SOURCE, \ + CONFIG_PLL##pll_id##_DIV, \ + CONFIG_PLL##pll_id##_MUL) + +static inline void pll_config_read(struct pll_config *p_cfg, uint32_t ul_pll_id) +{ + Assert(ul_pll_id < NR_PLLS); + + if (ul_pll_id == PLLA_ID) { + p_cfg->ctrl = PMC->CKGR_PLLAR; + } else { + p_cfg->ctrl = PMC->CKGR_UCKR; + } +} + +static inline void pll_config_write(const struct pll_config *p_cfg, uint32_t ul_pll_id) +{ + Assert(ul_pll_id < NR_PLLS); + + if (ul_pll_id == PLLA_ID) { + pmc_disable_pllack(); // Always stop PLL first! + PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | p_cfg->ctrl; + } else { + PMC->CKGR_UCKR = p_cfg->ctrl; + } +} + +static inline void pll_enable(const struct pll_config *p_cfg, uint32_t ul_pll_id) +{ + Assert(ul_pll_id < NR_PLLS); + + if (ul_pll_id == PLLA_ID) { + pmc_disable_pllack(); // Always stop PLL first! + PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | p_cfg->ctrl; + } else { + PMC->CKGR_UCKR = p_cfg->ctrl | CKGR_UCKR_UPLLEN; + } +} + +/** + * \note This will only disable the selected PLL, not the underlying oscillator (mainck). + */ +static inline void pll_disable(uint32_t ul_pll_id) +{ + Assert(ul_pll_id < NR_PLLS); + + if (ul_pll_id == PLLA_ID) { + pmc_disable_pllack(); + } else { + PMC->CKGR_UCKR &= ~CKGR_UCKR_UPLLEN; + } +} + +static inline uint32_t pll_is_locked(uint32_t ul_pll_id) +{ + Assert(ul_pll_id < NR_PLLS); + + if (ul_pll_id == PLLA_ID) { + return pmc_is_locked_pllack(); + } else { + return pmc_is_locked_upll(); + } +} + +static inline void pll_enable_source(enum pll_source e_src) +{ + switch (e_src) { + case PLL_SRC_MAINCK_4M_RC: + case PLL_SRC_MAINCK_8M_RC: + case PLL_SRC_MAINCK_12M_RC: + case PLL_SRC_MAINCK_XTAL: + case PLL_SRC_MAINCK_BYPASS: + osc_enable(e_src); + osc_wait_ready(e_src); + break; + + default: + Assert(false); + break; + } +} + +static inline void pll_enable_config_defaults(unsigned int ul_pll_id) +{ + struct pll_config pllcfg; + + if (pll_is_locked(ul_pll_id)) { + return; // Pll already running + } + switch (ul_pll_id) { +#ifdef CONFIG_PLL0_SOURCE + case 0: + pll_enable_source(CONFIG_PLL0_SOURCE); + pll_config_init(&pllcfg, + CONFIG_PLL0_SOURCE, + CONFIG_PLL0_DIV, + CONFIG_PLL0_MUL); + break; +#endif +#ifdef CONFIG_PLL1_SOURCE + case 1: + pll_enable_source(CONFIG_PLL1_SOURCE); + pll_config_init(&pllcfg, + CONFIG_PLL1_SOURCE, + CONFIG_PLL1_DIV, + CONFIG_PLL1_MUL); + break; +#endif + default: + Assert(false); + break; + } + pll_enable(&pllcfg, ul_pll_id); + while (!pll_is_locked(ul_pll_id)); +} + +//! @} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +#endif /* CHIP_PLL_H_INCLUDED */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/clock/same70/sysclk.c b/hw-libs/drivers/SAMx70/ASF/common/services/clock/same70/sysclk.c new file mode 100644 index 000000000..b006176ea --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/clock/same70/sysclk.c @@ -0,0 +1,258 @@ +/** + * \file + * + * \brief Chip-specific system clock management functions. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \weakgroup sysclk_group + * @{ + */ + +#if defined(CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC) +/** + * \brief boolean signalling that the sysclk_init is done. + */ +uint32_t sysclk_initialized = 0; +#endif + +/** + * \brief Set system clock prescaler configuration + * + * This function will change the system clock prescaler configuration to + * match the parameters. + * + * \note The parameters to this function are device-specific. + * + * \param ul_pres The CPU clock will be divided by \f$2^{mck\_pres}\f$ + */ +void sysclk_set_prescalers(uint32_t ul_pres) +{ + pmc_mck_set_prescaler(ul_pres); + SystemCoreClockUpdate(); +} + +/** + * \brief Change the source of the main system clock. + * + * \param ul_src The new system clock source. Must be one of the constants + * from the System Clock Sources section. + */ +void sysclk_set_source(uint32_t ul_src) +{ + switch (ul_src) { + case SYSCLK_SRC_SLCK_RC: + case SYSCLK_SRC_SLCK_XTAL: + case SYSCLK_SRC_SLCK_BYPASS: + pmc_mck_set_source(PMC_MCKR_CSS_SLOW_CLK); + break; + + case SYSCLK_SRC_MAINCK_4M_RC: + case SYSCLK_SRC_MAINCK_8M_RC: + case SYSCLK_SRC_MAINCK_12M_RC: + case SYSCLK_SRC_MAINCK_XTAL: + case SYSCLK_SRC_MAINCK_BYPASS: + pmc_mck_set_source(PMC_MCKR_CSS_MAIN_CLK); + break; + + case SYSCLK_SRC_PLLACK: + pmc_mck_set_source(PMC_MCKR_CSS_PLLA_CLK); + break; + + case SYSCLK_SRC_UPLLCK: + pmc_mck_set_source(PMC_MCKR_CSS_UPLL_CLK); + break; + } + + SystemCoreClockUpdate(); +} + +#if defined(CONFIG_USBCLK_SOURCE) || defined(__DOXYGEN__) +/** + * \brief Enable USB clock. + * + * \note The SAMV71 UDP hardware interprets div as div+1. For readability the hardware div+1 + * is hidden in this implementation. Use div as div effective value. + * + * \param pll_id Source of the USB clock. + * \param div Actual clock divisor. Must be superior to 0. + */ +void sysclk_enable_usb(void) +{ + Assert(CONFIG_USBCLK_DIV > 0); + +#ifdef CONFIG_PLL0_SOURCE + if (CONFIG_USBCLK_SOURCE == USBCLK_SRC_PLL0) { + struct pll_config pllcfg; + + pll_enable_source(CONFIG_PLL0_SOURCE); + pll_config_defaults(&pllcfg, 0); + pll_enable(&pllcfg, 0); + pll_wait_for_lock(0); + pmc_switch_udpck_to_pllack(CONFIG_USBCLK_DIV - 1); + pmc_enable_udpck(); + return; + } +#endif + + if (CONFIG_USBCLK_SOURCE == USBCLK_SRC_UPLL) { + + pmc_enable_upll_clock(); + pmc_switch_udpck_to_upllck(CONFIG_USBCLK_DIV - 1); + pmc_enable_udpck(); + return; + } +} + +/** + * \brief Disable the USB clock. + * + * \note This implementation does not switch off the PLL, it just turns off the USB clock. + */ +void sysclk_disable_usb(void) +{ + pmc_disable_udpck(); +} +#endif // CONFIG_USBCLK_SOURCE + +void sysclk_init(void) +{ + struct pll_config pllcfg; + + /* Set flash wait state to max in case the below clock switching. */ + system_init_flash(CHIP_FREQ_CPU_MAX / 2); + + /* Config system clock setting */ + if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_RC) { + osc_enable(OSC_SLCK_32K_RC); + osc_wait_ready(OSC_SLCK_32K_RC); + pmc_mck_set_division(CONFIG_SYSCLK_DIV); + pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES); + } + + else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_XTAL) { + osc_enable(OSC_SLCK_32K_XTAL); + osc_wait_ready(OSC_SLCK_32K_XTAL); + pmc_mck_set_division(CONFIG_SYSCLK_DIV); + pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES); + } + + else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_BYPASS) { + osc_enable(OSC_SLCK_32K_BYPASS); + osc_wait_ready(OSC_SLCK_32K_BYPASS); + pmc_mck_set_division(CONFIG_SYSCLK_DIV); + pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES); + } + + else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_4M_RC) { + /* Already running from SYSCLK_SRC_MAINCK_4M_RC */ + } + + else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_8M_RC) { + osc_enable(OSC_MAINCK_8M_RC); + osc_wait_ready(OSC_MAINCK_8M_RC); + pmc_mck_set_division(CONFIG_SYSCLK_DIV); + pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES); + } + + else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_12M_RC) { + osc_enable(OSC_MAINCK_12M_RC); + osc_wait_ready(OSC_MAINCK_12M_RC); + pmc_mck_set_division(CONFIG_SYSCLK_DIV); + pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES); + } + + else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_XTAL) { + osc_enable(OSC_MAINCK_XTAL); + osc_wait_ready(OSC_MAINCK_XTAL); + pmc_mck_set_division(CONFIG_SYSCLK_DIV); + pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES); + } + + else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_BYPASS) { + osc_enable(OSC_MAINCK_BYPASS); + osc_wait_ready(OSC_MAINCK_BYPASS); + pmc_mck_set_division(CONFIG_SYSCLK_DIV); + pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES); + } + +#ifdef CONFIG_PLL0_SOURCE + else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_PLLACK) { + pll_enable_source(CONFIG_PLL0_SOURCE); + pll_config_defaults(&pllcfg, 0); + pll_enable(&pllcfg, 0); + pll_wait_for_lock(0); + pmc_mck_set_division(CONFIG_SYSCLK_DIV); + pmc_switch_mck_to_pllack(CONFIG_SYSCLK_PRES); + } +#endif + + else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_UPLLCK) { + pll_enable_source(CONFIG_PLL1_SOURCE); + pll_config_defaults(&pllcfg, 1); + pll_enable(&pllcfg, 1); + pll_wait_for_lock(1); + pmc_mck_set_division(CONFIG_SYSCLK_DIV); + pmc_switch_mck_to_upllck(CONFIG_SYSCLK_PRES); + } + /* Update the SystemFrequency variable */ + SystemCoreClockUpdate(); + + /* Set a flash wait state depending on the master clock frequency */ + system_init_flash(sysclk_get_cpu_hz() / CONFIG_SYSCLK_DIV); + +#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC) + /* Signal that the internal frequencies are setup */ + sysclk_initialized = 1; +#endif +} + +//! @} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/clock/same70/sysclk.h b/hw-libs/drivers/SAMx70/ASF/common/services/clock/same70/sysclk.h new file mode 100644 index 000000000..a4046c744 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/clock/same70/sysclk.h @@ -0,0 +1,465 @@ +/** + * \file + * + * \brief Chip-specific system clock management functions. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef CHIP_SYSCLK_H_INCLUDED +#define CHIP_SYSCLK_H_INCLUDED + +#include "conf_clock.h" + +#include +#include + +/** + * \page sysclk_quickstart Quick Start Guide for the System Clock Management + * service (SAMV71) + * + * This is the quick start guide for the \ref sysclk_group "System Clock + * Management" service, with step-by-step instructions on how to configure and + * use the service for specific use cases. + * + * \section sysclk_quickstart_usecases System Clock Management use cases + * - \ref sysclk_quickstart_basic + * - \ref sysclk_quickstart_use_case_2 + * + * \section sysclk_quickstart_basic Basic usage of the System Clock Management + * service + * This section will present a basic use case for the System Clock Management + * service. This use case will configure the main system clock to 120MHz, + * using an internal PLL module to multiply the frequency of a crystal attached + * to the microcontroller. + * + * \subsection sysclk_quickstart_use_case_1_prereq Prerequisites + * - None + * + * \subsection sysclk_quickstart_use_case_1_setup_steps Initialization code + * Add to the application initialization code: + * \code + sysclk_init(); +\endcode + * + * \subsection sysclk_quickstart_use_case_1_setup_steps_workflow Workflow + * -# Configure the system clocks according to the settings in conf_clock.h: + * \code sysclk_init(); \endcode + * + * \subsection sysclk_quickstart_use_case_1_example_code Example code + * Add or uncomment the following in your conf_clock.h header file, + * commenting out all other definitions of the same symbol(s): + * \code + #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK + + // Fpll0 = (Fclk * PLL_mul) / PLL_div + #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL + #define CONFIG_PLL0_MUL (120000000UL / BOARD_FREQ_MAINCK_XTAL) + #define CONFIG_PLL0_DIV 1 + + // Fbus = Fsys / BUS_div + #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1 +\endcode + * + * \subsection sysclk_quickstart_use_case_1_example_workflow Workflow + * -# Configure the main system clock to use the output of the PLL module as + * its source: + * \code #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK \endcode + * -# Configure the PLL module to use the fast external fast crystal + * oscillator as its source: + * \code #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL \endcode + * -# Configure the PLL module to multiply the external fast crystal + * oscillator frequency up to 120MHz: + * \code + #define CONFIG_PLL0_MUL (120000000UL / BOARD_FREQ_MAINCK_XTAL) + #define CONFIG_PLL0_DIV 1 +\endcode + * \note For user boards, \c BOARD_FREQ_MAINCK_XTAL should be defined in the + * board \c conf_board.h configuration + * file as the frequency of the fast crystal attached to the microcontroller. + * -# Configure the main clock to run at the full 120MHz, disable scaling of + * the main system clock speed: + * \code + #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1 +\endcode + * \note Some dividers are powers of two, while others are integer division + * factors. Refer to the formulas in the conf_clock.h template commented + * above each division define. + */ + +/** + * \page sysclk_quickstart_use_case_2 Advanced use case - Peripheral Bus Clock + * Management (SAMV71) + * + * \section sysclk_quickstart_use_case_2 Advanced use case - Peripheral Bus + * Clock Management + * This section will present a more advanced use case for the System Clock + * Management service. This use case will configure the main system clock to + * 96MHz, using an internal PLL module to multiply the frequency of a crystal + * attached to the microcontroller. The USB clock will be configured via the + * same PLL module. + * + * \subsection sysclk_quickstart_use_case_2_prereq Prerequisites + * - None + * + * \subsection sysclk_quickstart_use_case_2_setup_steps Initialization code + * Add to the application initialization code: + * \code + sysclk_init(); +\endcode + * + * \subsection sysclk_quickstart_use_case_2_setup_steps_workflow Workflow + * -# Configure the system clocks according to the settings in conf_clock.h: + * \code sysclk_init(); \endcode + * + * \subsection sysclk_quickstart_use_case_2_example_code Example code + * Add or uncomment the following in your conf_clock.h header file, + * commenting out all other definitions of the same symbol(s): + * \code + #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK + + // Fpll0 = (Fclk * PLL_mul) / PLL_div + #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL + #define CONFIG_PLL0_MUL (96000000UL / BOARD_FREQ_MAINCK_XTAL) + #define CONFIG_PLL0_DIV 1 + + // Fbus = Fsys / BUS_div + #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1 + + // Fusb = Fsys / USB_div + #define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0 + #define CONFIG_USBCLK_DIV 2 +\endcode + * + * \subsection sysclk_quickstart_use_case_2_example_workflow Workflow + * -# Configure the main system clock to use the output of the PLL0 module as + * its source: + * \code #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK \endcode + * -# Configure the PLL0 module to use the fast external fast crystal + * oscillator as its source: + * \code #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL \endcode + * -# Configure the PLL0 module to multiply the external fast crystal + * oscillator frequency up to 96MHz: + * \code + #define CONFIG_PLL0_MUL (96000000UL / BOARD_FREQ_MAINCK_XTAL) + #define CONFIG_PLL0_DIV 1 +\endcode + * \note For user boards, \c BOARD_FREQ_MAINCK_XTAL should be defined in the + * board \c conf_board.h configuration file as the frequency of the fast + * crystal attached to the microcontroller. + * -# Configure the main clock to run at the full 96MHz, disable scaling of + * the main system clock speed: + * \code + #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1 +\endcode + * \note Some dividers are powers of two, while others are integer division + * factors. Refer to the formulas in the conf_clock.h template commented + * above each division define. + * -# Configure the USB module clock to use the output of the PLL0 module as + * its source with division 2: + * \code + #define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0 + #define CONFIG_USBCLK_DIV 2 +\endcode + */ + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \weakgroup sysclk_group + * @{ + */ + +//! \name Configuration Symbols +//@{ +/** + * \def CONFIG_SYSCLK_SOURCE + * \brief Initial/static main system clock source + * + * The main system clock will be configured to use this clock during + * initialization. + */ +#ifndef CONFIG_SYSCLK_SOURCE +# define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_4M_RC +#endif +/** + * \def CONFIG_SYSCLK_PRES + * \brief Initial CPU clock divider (mck) + * + * The MCK will run at + * \f[ + * f_{MCK} = \frac{f_{sys}}{\mathrm{CONFIG\_SYSCLK\_PRES}}\,\mbox{Hz} + * \f] + * after initialization. + */ +#ifndef CONFIG_SYSCLK_PRES +# define CONFIG_SYSCLK_PRES 0 +#endif + +//@} + +//! \name Master Clock Sources (MCK) +//@{ +#define SYSCLK_SRC_SLCK_RC 0 //!< Internal 32kHz RC oscillator as master source clock +#define SYSCLK_SRC_SLCK_XTAL 1 //!< External 32kHz crystal oscillator as master source clock +#define SYSCLK_SRC_SLCK_BYPASS 2 //!< External 32kHz bypass oscillator as master source clock +#define SYSCLK_SRC_MAINCK_4M_RC 3 //!< Internal 4MHz RC oscillator as master source clock +#define SYSCLK_SRC_MAINCK_8M_RC 4 //!< Internal 8MHz RC oscillator as master source clock +#define SYSCLK_SRC_MAINCK_12M_RC 5 //!< Internal 12MHz RC oscillator as master source clock +#define SYSCLK_SRC_MAINCK_XTAL 6 //!< External crystal oscillator as master source clock +#define SYSCLK_SRC_MAINCK_BYPASS 7 //!< External bypass oscillator as master source clock +#define SYSCLK_SRC_PLLACK 8 //!< Use PLLACK as master source clock +#define SYSCLK_SRC_UPLLCK 9 //!< Use UPLLCK as master source clock +//@} + +//! \name Master Clock Prescalers (MCK) +//@{ +#define SYSCLK_PRES_1 PMC_MCKR_PRES_CLK_1 //!< Set master clock prescaler to 1 +#define SYSCLK_PRES_2 PMC_MCKR_PRES_CLK_2 //!< Set master clock prescaler to 2 +#define SYSCLK_PRES_4 PMC_MCKR_PRES_CLK_4 //!< Set master clock prescaler to 4 +#define SYSCLK_PRES_8 PMC_MCKR_PRES_CLK_8 //!< Set master clock prescaler to 8 +#define SYSCLK_PRES_16 PMC_MCKR_PRES_CLK_16 //!< Set master clock prescaler to 16 +#define SYSCLK_PRES_32 PMC_MCKR_PRES_CLK_32 //!< Set master clock prescaler to 32 +#define SYSCLK_PRES_64 PMC_MCKR_PRES_CLK_64 //!< Set master clock prescaler to 64 +#define SYSCLK_PRES_3 PMC_MCKR_PRES_CLK_3 //!< Set master clock prescaler to 3 +//@} + +//! \name Master Clock Division (MCK) +//@{ +#define SYSCLK_DIV_1 PMC_MCKR_MDIV_EQ_PCK //!< Set master clock division to 1 +#define SYSCLK_DIV_2 PMC_MCKR_MDIV_PCK_DIV2 //!< Set master clock division to 2 +#define SYSCLK_DIV_4 PMC_MCKR_MDIV_PCK_DIV4 //!< Set master clock division to 4 +#define SYSCLK_DIV_3 PMC_MCKR_MDIV_PCK_DIV3 //!< Set master clock division to 3 +//@} + +//! \name USB Clock Sources +//@{ +#define USBCLK_SRC_PLL0 0 //!< Use PLLA +#define USBCLK_SRC_UPLL 1 //!< Use UPLL +//@} + +/** + * \def CONFIG_USBCLK_SOURCE + * \brief Configuration symbol for the USB generic clock source + * + * Sets the clock source to use for the USB. The source must also be properly + * configured. + * + * Define this to one of the \c USBCLK_SRC_xxx settings. Leave it undefined if + * USB is not required. + */ +#ifdef __DOXYGEN__ +# define CONFIG_USBCLK_SOURCE +#endif + +/** + * \def CONFIG_USBCLK_DIV + * \brief Configuration symbol for the USB generic clock divider setting + * + * Sets the clock division for the USB generic clock. If a USB clock source is + * selected with CONFIG_USBCLK_SOURCE, this configuration symbol must also be + * defined. + */ +#ifdef __DOXYGEN__ +# define CONFIG_USBCLK_DIV +#endif + +/** + * \name Querying the system clock + * + * The following functions may be used to query the current frequency of + * the system clock and the CPU and bus clocks derived from it. + * sysclk_get_main_hz() and sysclk_get_cpu_hz() can be assumed to be + * available on all platforms, although some platforms may define + * additional accessors for various chip-internal bus clocks. These are + * usually not intended to be queried directly by generic code. + */ +//@{ + +/** + * \brief Return the current rate in Hz of the main system clock + * + * \todo This function assumes that the main clock source never changes + * once it's been set up, and that PLL0 always runs at the compile-time + * configured default rate. While this is probably the most common + * configuration, which we want to support as a special case for + * performance reasons, we will at some point need to support more + * dynamic setups as well. + */ +#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC) +extern uint32_t sysclk_initialized; +#endif +static inline uint32_t sysclk_get_main_hz(void) +{ +#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC) + if (!sysclk_initialized ) { + return OSC_MAINCK_4M_RC_HZ; + } +#endif + + /* Config system clock setting */ + if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_RC) { + return OSC_SLCK_32K_RC_HZ; + } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_XTAL) { + return OSC_SLCK_32K_XTAL_HZ; + } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_BYPASS) { + return OSC_SLCK_32K_BYPASS_HZ; + } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_4M_RC) { + return OSC_MAINCK_4M_RC_HZ; + } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_8M_RC) { + return OSC_MAINCK_8M_RC_HZ; + } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_12M_RC) { + return OSC_MAINCK_12M_RC_HZ; + } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_XTAL) { + return OSC_MAINCK_XTAL_HZ; + } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_BYPASS) { + return OSC_MAINCK_BYPASS_HZ; + } +#ifdef CONFIG_PLL0_SOURCE + else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_PLLACK) { + return pll_get_default_rate(0); + } +#endif + +#ifdef CONFIG_PLL1_SOURCE + else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_UPLLCK) { + return PLL_UPLL_HZ; + } +#endif + else { + /* unhandled_case(CONFIG_SYSCLK_SOURCE); */ + return 0; + } +} + +/** + * \brief Return the current rate in Hz of the CPU clock + * + * \todo This function assumes that the CPU always runs at the system + * clock frequency. We want to support at least two more scenarios: + * Fixed CPU/bus clock dividers (config symbols) and dynamic CPU/bus + * clock dividers (which may change at run time). Ditto for all the bus + * clocks. + * + * \return Frequency of the CPU clock, in Hz. + */ +static inline uint32_t sysclk_get_cpu_hz(void) +{ + /* CONFIG_SYSCLK_PRES is the register value for setting the expected */ + /* prescaler, not an immediate value. */ + return sysclk_get_main_hz() / + ((CONFIG_SYSCLK_PRES == SYSCLK_PRES_3) ? 3 : + (1 << (CONFIG_SYSCLK_PRES >> PMC_MCKR_PRES_Pos))); +} + +/** + * \brief Retrieves the current rate in Hz of the peripheral clocks. + * + * \return Frequency of the peripheral clocks, in Hz. + */ +static inline uint32_t sysclk_get_peripheral_hz(void) +{ + /* CONFIG_SYSCLK_PRES is the register value for setting the expected */ + /* prescaler, not an immediate value. */ + return sysclk_get_main_hz() / + (((CONFIG_SYSCLK_PRES == SYSCLK_PRES_3) ? 3 : (1 << (CONFIG_SYSCLK_PRES >> PMC_MCKR_PRES_Pos))) * CONFIG_SYSCLK_DIV); +} + +/** + * \brief Retrieves the current rate in Hz of the Peripheral Bus clock attached + * to the specified peripheral. + * + * \param module Pointer to the module's base address. + * + * \return Frequency of the bus attached to the specified peripheral, in Hz. + */ +static inline uint32_t sysclk_get_peripheral_bus_hz(const volatile void *module) +{ + UNUSED(module); + return sysclk_get_peripheral_hz(); +} +//@} + +//! \name Enabling and disabling synchronous clocks +//@{ + +/** + * \brief Enable a peripheral's clock. + * + * \param ul_id Id (number) of the peripheral clock. + */ +static inline void sysclk_enable_peripheral_clock(uint32_t ul_id) +{ + pmc_enable_periph_clk(ul_id); +} + +/** + * \brief Disable a peripheral's clock. + * + * \param ul_id Id (number) of the peripheral clock. + */ +static inline void sysclk_disable_peripheral_clock(uint32_t ul_id) +{ + pmc_disable_periph_clk(ul_id); +} + +//@} + +//! \name System Clock Source and Prescaler configuration +//@{ + +extern void sysclk_set_prescalers(uint32_t ul_pres); +extern void sysclk_set_source(uint32_t ul_src); + +//@} + +extern void sysclk_enable_usb(void); +extern void sysclk_disable_usb(void); + +extern void sysclk_init(void); + +//! @} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +#endif /* CHIP_SYSCLK_H_INCLUDED */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/clock/sysclk.h b/hw-libs/drivers/SAMx70/ASF/common/services/clock/sysclk.h new file mode 100644 index 000000000..7f0b9d252 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/clock/sysclk.h @@ -0,0 +1,184 @@ +/** + * \file + * + * \brief System clock management + * + * Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef SYSCLK_H_INCLUDED +#define SYSCLK_H_INCLUDED + +#include "parts.h" +#include "ISBoards.h" + +#if SAM3S +# include "sam3s/sysclk.h" +#elif SAM3U +# include "sam3u/sysclk.h" +#elif SAM3N +# include "sam3n/sysclk.h" +#elif SAM3XA +# include "sam3x/sysclk.h" +#elif SAM4S +# include "sam4s/sysclk.h" +#elif SAM4E +# include "sam4e/sysclk.h" +#elif SAM4C +# include "sam4c/sysclk.h" +#elif SAM4CM +# include "sam4cm/sysclk.h" +#elif SAM4CP +# include "sam4cp/sysclk.h" +#elif SAM4L +# include "sam4l/sysclk.h" +#elif SAM4N +# include "sam4n/sysclk.h" +#elif SAMG +# include "samg/sysclk.h" +#elif SAMV71 +# include "samv71/sysclk.h" +#elif SAMV70 +# include "samv70/sysclk.h" +#elif SAME70 +# include "same70/sysclk.h" +#elif SAMS70 +# include "sams70/sysclk.h" +#elif (UC3A0 || UC3A1) +# include "uc3a0_a1/sysclk.h" +#elif UC3A3 +# include "uc3a3_a4/sysclk.h" +#elif UC3B +# include "uc3b0_b1/sysclk.h" +#elif UC3C +# include "uc3c/sysclk.h" +#elif UC3D +# include "uc3d/sysclk.h" +#elif UC3L +# include "uc3l/sysclk.h" +#elif XMEGA +# include "xmega/sysclk.h" +#elif MEGA +# include "mega/sysclk.h" +#else +# error Unsupported chip type +#endif + +/** + * \defgroup clk_group Clock Management + */ + +/** + * \ingroup clk_group + * \defgroup sysclk_group System Clock Management + * + * See \ref sysclk_quickstart. + * + * The sysclk API covers the system clock and all + * clocks derived from it. The system clock is a chip-internal clock on + * which all synchronous clocks, i.e. CPU and bus/peripheral + * clocks, are based. The system clock is typically generated from one + * of a variety of sources, which may include crystal and RC oscillators + * as well as PLLs. The clocks derived from the system clock are + * sometimes also known as synchronous clocks, since they + * always run synchronously with respect to each other, as opposed to + * generic clocks which may run from different oscillators or + * PLLs. + * + * Most applications should simply call sysclk_init() to initialize + * everything related to the system clock and its source (oscillator, + * PLL or DFLL), and leave it at that. More advanced applications, and + * platform-specific drivers, may require additional services from the + * clock system, some of which may be platform-specific. + * + * \section sysclk_group_platform Platform Dependencies + * + * The sysclk API is partially chip- or platform-specific. While all + * platforms provide mostly the same functionality, there are some + * variations around how different bus types and clock tree structures + * are handled. + * + * The following functions are available on all platforms with the same + * parameters and functionality. These functions may be called freely by + * portable applications, drivers and services: + * - sysclk_init() + * - sysclk_set_source() + * - sysclk_get_main_hz() + * - sysclk_get_cpu_hz() + * - sysclk_get_peripheral_bus_hz() + * + * The following functions are available on all platforms, but there may + * be variations in the function signature (i.e. parameters) and + * behavior. These functions are typically called by platform-specific + * parts of drivers, and applications that aren't intended to be + * portable: + * - sysclk_enable_peripheral_clock() + * - sysclk_disable_peripheral_clock() + * - sysclk_enable_module() + * - sysclk_disable_module() + * - sysclk_module_is_enabled() + * - sysclk_set_prescalers() + * + * All other functions should be considered platform-specific. + * Enabling/disabling clocks to specific peripherals as well as + * determining the speed of these clocks should be done by calling + * functions provided by the driver for that peripheral. + * + * @{ + */ + +//! \name System Clock Initialization +//@{ +/** + * \fn void sysclk_init(void) + * \brief Initialize the synchronous clock system. + * + * This function will initialize the system clock and its source. This + * includes: + * - Mask all synchronous clocks except for any clocks which are + * essential for normal operation (for example internal memory + * clocks). + * - Set up the system clock prescalers as specified by the + * application's configuration file. + * - Enable the clock source specified by the application's + * configuration file (oscillator or PLL) and wait for it to become + * stable. + * - Set the main system clock source to the clock specified by the + * application's configuration file. + * + * Since all non-essential peripheral clocks are initially disabled, it + * is the responsibility of the peripheral driver to re-enable any + * clocks that are needed for normal operation. + */ +//@} + +//! @} + +#endif /* SYSCLK_H_INCLUDED */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/delay/delay.h b/hw-libs/drivers/SAMx70/ASF/common/services/delay/delay.h new file mode 100644 index 000000000..dd01b4780 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/delay/delay.h @@ -0,0 +1,129 @@ +/** + * \file + * + * \brief Common Delay Service + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef _DELAY_H_ +#define _DELAY_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#if UC3 +# include +#elif XMEGA +# include "xmega/cycle_counter.h" +#elif MEGA +# include "mega/cycle_counter.h" +#elif SAM +# include "sam/cycle_counter.h" +#endif + +/** + * @defgroup group_common_services_delay Busy-Wait Delay Routines + * + * This module provides simple loop-based delay routines for those + * applications requiring a brief wait during execution. Common API + * for UC3, XMEGA, and AVR MEGA. + * + * @{ + */ + +/** + * @def F_CPU + * @brief MCU Clock Frequency (Hertz) + * + * @deprecated + * The \ref F_CPU configuration constant is used for compatibility with the + * \ref group_common_services_delay routines. The common loop-based delay + * routines are designed to use the \ref clk_group modules while anticipating + * support for legacy applications assuming a statically defined clock + * frequency. Applications using a statically configured MCU clock frequency + * can define \ref F_CPU (Hertz), in which case the common delay routines will + * use this value rather than calling sysclk_get_cpu_hz() to get the current + * MCU clock frequency. + */ +#ifndef F_CPU +# define F_CPU sysclk_get_cpu_hz() +#endif + +/** + * @def delay_init + * + * @brief Initialize the delay driver. + * @param fcpu_hz CPU frequency in Hz + * + * @deprecated + * This function is provided for compatibility with ASF applications that + * may not have been updated to configure the system clock via the common + * clock service; e.g. sysclk_init() and a configuration header file are + * used to configure clocks. + * + * The functions in this module call \ref sysclk_get_cpu_hz() function to + * obtain the system clock frequency. + */ +#define delay_init(fcpu_hz) + +/** + * @def delay_s + * @brief Delay in seconds. + * @param delay Delay in seconds + */ +#define delay_s(delay) ((delay) ? cpu_delay_ms(1000 * delay, F_CPU) : cpu_delay_us(1, F_CPU)) + +/** + * @def delay_ms + * @brief Delay in milliseconds. + * @param delay Delay in milliseconds + */ +#define delay_ms(delay) ((delay) ? cpu_delay_ms(delay, F_CPU) : cpu_delay_us(1, F_CPU)) + +/** + * @def delay_us + * @brief Delay in microseconds. + * @param delay Delay in microseconds + */ +#define delay_us(delay) ((delay) ? cpu_delay_us(delay, F_CPU) : cpu_delay_us(1, F_CPU)) + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* _DELAY_H_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/delay/sam/cycle_counter.c b/hw-libs/drivers/SAMx70/ASF/common/services/delay/sam/cycle_counter.c new file mode 100644 index 000000000..ab41bcd18 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/delay/sam/cycle_counter.c @@ -0,0 +1,51 @@ +/** + * \file + * + * \brief ARM functions for busy-wait delay loops + * + * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "cycle_counter.h" + +// Delay loop is put to SRAM so that FWS will not affect delay time +OPTIMIZE_HIGH +RAMFUNC +void portable_delay_cycles(unsigned long n) +{ + UNUSED(n); + + __asm ( + "loop: DMB \n" + "SUBS R0, R0, #1 \n" + "BNE.N loop " + ); +} diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/delay/sam/cycle_counter.h b/hw-libs/drivers/SAMx70/ASF/common/services/delay/sam/cycle_counter.h new file mode 100644 index 000000000..5cd613fd0 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/delay/sam/cycle_counter.h @@ -0,0 +1,116 @@ +/** + * \file + * + * \brief ARM functions for busy-wait delay loops + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef _cycle_counter_h_ +#define _cycle_counter_h_ + +#ifdef __cplusplus +extern "C" { +#endif + + +#include + +/** + * @name Convenience functions for busy-wait delay loops + * + * @def delay_cycles + * @brief Delay program execution for a specified number of CPU cycles. + * @param n number of CPU cycles to wait + * + * @def cpu_delay_ms + * @brief Delay program execution for a specified number of milliseconds. + * @param delay number of milliseconds to wait + * @param f_cpu CPU frequency in Hertz + * + * @def cpu_delay_us + * @brief Delay program execution for a specified number of microseconds. + * @param delay number of microseconds to wait + * @param f_cpu CPU frequency in Hertz + * + * @def cpu_ms_2_cy + * @brief Convert milli-seconds into CPU cycles. + * @param ms number of milliseconds + * @param f_cpu CPU frequency in Hertz + * @return the converted number of CPU cycles + * + * @def cpu_us_2_cy + * @brief Convert micro-seconds into CPU cycles. + * @param ms number of microseconds + * @param f_cpu CPU frequency in Hertz + * @return the converted number of CPU cycles + * + * @{ + */ + +/** + * \brief Delay loop to delay n number of cycles + * + * \note The function runs in internal RAM so that flash wait states + * will not affect the delay time. + * + * \param n Number of cycles + */ +void portable_delay_cycles(unsigned long n); + +/* Cortex-M7 is faster than Cortex-M3/M4/M0+ */ +#ifdef __CM7_REV + +# define cpu_ms_2_cy(ms, f_cpu) \ + (((uint64_t)(ms) * (f_cpu) + (uint64_t)(5.932e3 - 1ul)) / (uint64_t)5.932e3) +# define cpu_us_2_cy(us, f_cpu) \ + (((uint64_t)(us) * (f_cpu) + (uint64_t)(5.932e6 - 1ul)) / (uint64_t)5.932e6) + +#else + +# define cpu_ms_2_cy(ms, f_cpu) \ + (((uint64_t)(ms) * (f_cpu) + (uint64_t)(14e3 - 1ul)) / (uint64_t)14e3) +# define cpu_us_2_cy(us, f_cpu) \ + (((uint64_t)(us) * (f_cpu) + (uint64_t)(14e6 - 1ul)) / (uint64_t)14e6) + +#endif + +#define delay_cycles portable_delay_cycles + +#define cpu_delay_ms(delay, f_cpu) delay_cycles(cpu_ms_2_cy(delay, f_cpu)) +#define cpu_delay_us(delay, f_cpu) delay_cycles(cpu_us_2_cy(delay, f_cpu)) +//! @} + + +#ifdef __cplusplus +} +#endif + +#endif /* _cycle_counter_h_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/gpio/gpio.h b/hw-libs/drivers/SAMx70/ASF/common/services/gpio/gpio.h new file mode 100644 index 000000000..cb9ef97a2 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/gpio/gpio.h @@ -0,0 +1,76 @@ +/** + * \file + * + * \brief Common GPIO API. + * + * Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef _GPIO_H_ +#define _GPIO_H_ + +#include + +#if (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) +# include "sam_gpio/sam_gpio.h" +#elif XMEGA +# include "xmega_gpio/xmega_gpio.h" +#elif MEGA || MEGA_RF +# include "mega_gpio/mega_gpio.h" +#else +# error Unsupported chip type +#endif + +/** + * \defgroup gpio_group General Purpose Input/Output + * + * This is the common API for GPIO. Additional features are available + * in the documentation of the specific modules. + * + * \section io_group_platform Platform Dependencies + * + * The following functions are available on all platforms, but there may + * be variations in the function signature (i.e. parameters) and + * behaviour. These functions are typically called by platform-specific + * parts of drivers, and applications that aren't intended to be + * portable: + * - gpio_pin_is_low() + * - gpio_pin_is_high() + * - gpio_set_pin_high() + * - gpio_set_pin_group_high() + * - gpio_set_pin_low() + * - gpio_set_pin_group_low() + * - gpio_toggle_pin() + * - gpio_toggle_pin_group() + * - gpio_configure_pin() + * - gpio_configure_group() + */ + +#endif /* _GPIO_H_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/gpio/sam_gpio/sam_gpio.h b/hw-libs/drivers/SAMx70/ASF/common/services/gpio/sam_gpio/sam_gpio.h new file mode 100644 index 000000000..27d7489c2 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/gpio/sam_gpio/sam_gpio.h @@ -0,0 +1,73 @@ +/** + * \file + * + * \brief GPIO service for SAM. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef SAM_GPIO_H_INCLUDED +#define SAM_GPIO_H_INCLUDED + +#include "compiler.h" +#include "pio.h" + +#define gpio_pin_is_low(io_id) \ + (pio_get_pin_value(io_id) ? 0 : 1) + +#define gpio_pin_is_high(io_id) \ + (pio_get_pin_value(io_id) ? 1 : 0) + +#define gpio_set_pin_high(io_id) \ + pio_set_pin_high(io_id) + +#define gpio_set_pin_low(io_id) \ + pio_set_pin_low(io_id) + +#define gpio_toggle_pin(io_id) \ + pio_toggle_pin(io_id) + +#define gpio_configure_pin(io_id,io_flags) \ + pio_configure_pin(io_id,io_flags) + +#define gpio_configure_group(port_id,port_mask,io_flags) \ + pio_configure_pin_group(port_id,port_mask,io_flags) + +#define gpio_set_pin_group_high(port_id,mask) \ + pio_set_pin_group_high(port_id,mask) + +#define gpio_set_pin_group_low(port_id,mask) \ + pio_set_pin_group_low(port_id,mask) + +#define gpio_toggle_pin_group(port_id,mask) \ + pio_toggle_pin_group(port_id,mask) + +#endif /* SAM_GPIO_H_INCLUDED */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/ioport/ioport.h b/hw-libs/drivers/SAMx70/ASF/common/services/ioport/ioport.h new file mode 100644 index 000000000..c523bda72 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/ioport/ioport.h @@ -0,0 +1,538 @@ +/** + * \file + * + * \brief Common IOPORT service main header file for AVR, UC3 and ARM + * architectures. + * + * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef IOPORT_H +#define IOPORT_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +/** + * \defgroup ioport_group Common IOPORT API + * + * See \ref ioport_quickstart. + * + * This is common IOPORT service for GPIO pin configuration and control in a + * standardized manner across the MEGA, MEGA_RF, XMEGA, UC3 and ARM devices. + * + * Port pin control code is optimized for each platform, and should produce + * both compact and fast execution times when used with constant values. + * + * \section dependencies Dependencies + * This driver depends on the following modules: + * - \ref sysclk_group for clock speed and functions. + * @{ + */ + +/** + * \def IOPORT_CREATE_PIN(port, pin) + * \brief Create IOPORT pin number + * + * Create a IOPORT pin number for use with the IOPORT functions. + * + * \param port IOPORT port (e.g. PORTA, PA or PIOA depending on chosen + * architecture) + * \param pin IOPORT zero-based index of the I/O pin + */ + +/** \brief IOPORT pin directions */ +enum ioport_direction { + IOPORT_DIR_INPUT, /*!< IOPORT input direction */ + IOPORT_DIR_OUTPUT, /*!< IOPORT output direction */ +}; + +/** \brief IOPORT levels */ +enum ioport_value { + IOPORT_PIN_LEVEL_LOW, /*!< IOPORT pin value low */ + IOPORT_PIN_LEVEL_HIGH, /*!< IOPORT pin value high */ +}; + +#if MEGA_RF +/** \brief IOPORT edge sense modes */ +enum ioport_sense { + IOPORT_SENSE_LEVEL, /*!< IOPORT sense low level */ + IOPORT_SENSE_BOTHEDGES, /*!< IOPORT sense both rising and falling edges */ + IOPORT_SENSE_FALLING, /*!< IOPORT sense falling edges */ + IOPORT_SENSE_RISING, /*!< IOPORT sense rising edges */ +}; +#elif SAM && !SAM4L +/** \brief IOPORT edge sense modes */ +enum ioport_sense { + IOPORT_SENSE_BOTHEDGES, /*!< IOPORT sense both rising and falling edges */ + IOPORT_SENSE_FALLING, /*!< IOPORT sense falling edges */ + IOPORT_SENSE_RISING, /*!< IOPORT sense rising edges */ + IOPORT_SENSE_LEVEL_LOW, /*!< IOPORT sense low level */ + IOPORT_SENSE_LEVEL_HIGH,/*!< IOPORT sense High level */ +}; +#elif XMEGA +enum ioport_sense { + IOPORT_SENSE_BOTHEDGES, /*!< IOPORT sense both rising and falling edges */ + IOPORT_SENSE_RISING, /*!< IOPORT sense rising edges */ + IOPORT_SENSE_FALLING, /*!< IOPORT sense falling edges */ + IOPORT_SENSE_LEVEL_LOW, /*!< IOPORT sense low level */ +}; +#else +enum ioport_sense { + IOPORT_SENSE_BOTHEDGES, /*!< IOPORT sense both rising and falling edges */ + IOPORT_SENSE_RISING, /*!< IOPORT sense rising edges */ + IOPORT_SENSE_FALLING, /*!< IOPORT sense falling edges */ +}; +#endif + + +#if XMEGA +# include "xmega/ioport.h" +# if defined(IOPORT_XMEGA_COMPAT) +# include "xmega/ioport_compat.h" +# endif +#elif MEGA +# include "mega/ioport.h" +#elif UC3 +# include "uc3/ioport.h" +#elif SAM +# if SAM4L +# include "sam/ioport_gpio.h" +# elif (SAMD20 | SAMD21 | SAML21| SAMR34 |SAMR35) +# include "sam0/ioport.h" +# else +# include "sam/ioport_pio.h" +# endif +#endif + +/** + * \brief Initializes the IOPORT service, ready for use. + * + * This function must be called before using any other functions in the IOPORT + * service. + */ +static inline void ioport_init(void) +{ + arch_ioport_init(); +} + +/** + * \brief Enable an IOPORT pin, based on a pin created with \ref + * IOPORT_CREATE_PIN(). + * + * \param pin IOPORT pin to enable + */ +static inline void ioport_enable_pin(ioport_pin_t pin) +{ + arch_ioport_enable_pin(pin); +} + +/** + * \brief Enable multiple pins in a single IOPORT port. + * + * \param port IOPORT port to enable + * \param mask Mask of pins within the port to enable + */ +static inline void ioport_enable_port(ioport_port_t port, + ioport_port_mask_t mask) +{ + arch_ioport_enable_port(port, mask); +} + +/** + * \brief Disable IOPORT pin, based on a pin created with \ref + * IOPORT_CREATE_PIN(). + * + * \param pin IOPORT pin to disable + */ +static inline void ioport_disable_pin(ioport_pin_t pin) +{ + arch_ioport_disable_pin(pin); +} + +/** + * \brief Disable multiple pins in a single IOPORT port. + * + * \param port IOPORT port to disable + * \param mask Pin mask of pins to disable + */ +static inline void ioport_disable_port(ioport_port_t port, + ioport_port_mask_t mask) +{ + arch_ioport_disable_port(port, mask); +} + +/** + * \brief Set multiple pin modes in a single IOPORT port, such as pull-up, + * pull-down, etc. configuration. + * + * \param port IOPORT port to configure + * \param mask Pin mask of pins to configure + * \param mode Mode masks to configure for the specified pins (\ref + * ioport_modes) + */ +static inline void ioport_set_port_mode(ioport_port_t port, + ioport_port_mask_t mask, ioport_mode_t mode) +{ + arch_ioport_set_port_mode(port, mask, mode); +} + +/** + * \brief Set pin mode for one single IOPORT pin. + * + * \param pin IOPORT pin to configure + * \param mode Mode masks to configure for the specified pin (\ref ioport_modes) + */ +static inline void ioport_set_pin_mode(ioport_pin_t pin, ioport_mode_t mode) +{ + arch_ioport_set_pin_mode(pin, mode); +} + +/** + * \brief Reset multiple pin modes in a specified IOPORT port to defaults. + * + * \param port IOPORT port to configure + * \param mask Mask of pins whose mode configuration is to be reset + */ +static inline void ioport_reset_port_mode(ioport_port_t port, + ioport_port_mask_t mask) +{ + arch_ioport_set_port_mode(port, mask, 0); +} + +/** + * \brief Reset pin mode configuration for a single IOPORT pin + * + * \param pin IOPORT pin to configure + */ +static inline void ioport_reset_pin_mode(ioport_pin_t pin) +{ + arch_ioport_set_pin_mode(pin, 0); +} + +/** + * \brief Set I/O direction for a group of pins in a single IOPORT. + * + * \param port IOPORT port to configure + * \param mask Pin mask of pins to configure + * \param dir Direction to set for the specified pins (\ref ioport_direction) + */ +static inline void ioport_set_port_dir(ioport_port_t port, + ioport_port_mask_t mask, enum ioport_direction dir) +{ + arch_ioport_set_port_dir(port, mask, dir); +} + +/** + * \brief Set direction for a single IOPORT pin. + * + * \param pin IOPORT pin to configure + * \param dir Direction to set for the specified pin (\ref ioport_direction) + */ +static inline void ioport_set_pin_dir(ioport_pin_t pin, + enum ioport_direction dir) +{ + arch_ioport_set_pin_dir(pin, dir); +} + +/** + * \brief Set an IOPORT pin to a specified logical value. + * + * \param pin IOPORT pin to configure + * \param level Logical value of the pin + */ +static inline void ioport_set_pin_level(ioport_pin_t pin, bool level) +{ + arch_ioport_set_pin_level(pin, level); +} + +/** + * \brief Set a group of IOPORT pins in a single port to a specified logical + * value. + * + * \param port IOPORT port to write to + * \param mask Pin mask of pins to modify + * \param level Level of the pins to be modified + */ +static inline void ioport_set_port_level(ioport_port_t port, + ioport_port_mask_t mask, enum ioport_value level) +{ + arch_ioport_set_port_level(port, mask, level); +} + +/** + * \brief Get current value of an IOPORT pin, which has been configured as an + * input. + * + * \param pin IOPORT pin to read + * \return Current logical value of the specified pin + */ +static inline bool ioport_get_pin_level(ioport_pin_t pin) +{ + return arch_ioport_get_pin_level(pin); +} + +/** + * \brief Get current value of several IOPORT pins in a single port, which have + * been configured as an inputs. + * + * \param port IOPORT port to read + * \param mask Pin mask of pins to read + * \return Logical levels of the specified pins from the read port, returned as + * a mask. + */ +static inline ioport_port_mask_t ioport_get_port_level(ioport_pin_t port, + ioport_port_mask_t mask) +{ + return arch_ioport_get_port_level(port, mask); +} + +/** + * \brief Toggle the value of an IOPORT pin, which has previously configured as + * an output. + * + * \param pin IOPORT pin to toggle + */ +static inline void ioport_toggle_pin_level(ioport_pin_t pin) +{ + arch_ioport_toggle_pin_level(pin); +} + +/** + * \brief Toggle the values of several IOPORT pins located in a single port. + * + * \param port IOPORT port to modify + * \param mask Pin mask of pins to toggle + */ +static inline void ioport_toggle_port_level(ioport_port_t port, + ioport_port_mask_t mask) +{ + arch_ioport_toggle_port_level(port, mask); +} + +/** + * \brief Set the pin sense mode of a single IOPORT pin. + * + * \param pin IOPORT pin to configure + * \param pin_sense Edge to sense for the pin (\ref ioport_sense) + */ +static inline void ioport_set_pin_sense_mode(ioport_pin_t pin, + enum ioport_sense pin_sense) +{ + arch_ioport_set_pin_sense_mode(pin, pin_sense); +} + +/** + * \brief Set the pin sense mode of a multiple IOPORT pins on a single port. + * + * \param port IOPORT port to configure + * \param mask Bitmask if pins whose edge sense is to be configured + * \param pin_sense Edge to sense for the pins (\ref ioport_sense) + */ +static inline void ioport_set_port_sense_mode(ioport_port_t port, + ioport_port_mask_t mask, + enum ioport_sense pin_sense) +{ + arch_ioport_set_port_sense_mode(port, mask, pin_sense); +} + +/** + * \brief Convert a pin ID into a its port ID. + * + * \param pin IOPORT pin ID to convert + * \retval Port ID for the given pin ID + */ +static inline ioport_port_t ioport_pin_to_port_id(ioport_pin_t pin) +{ + return arch_ioport_pin_to_port_id(pin); +} + +/** + * \brief Convert a pin ID into a bitmask mask for the given pin on its port. + * + * \param pin IOPORT pin ID to convert + * \retval Bitmask with a bit set that corresponds to the given pin ID in its port + */ +static inline ioport_port_mask_t ioport_pin_to_mask(ioport_pin_t pin) +{ + return arch_ioport_pin_to_mask(pin); +} + +/** @} */ + +/** + * \page ioport_quickstart Quick start guide for the common IOPORT service + * + * This is the quick start guide for the \ref ioport_group, with + * step-by-step instructions on how to configure and use the service in a + * selection of use cases. + * + * The use cases contain several code fragments. The code fragments in the + * steps for setup can be copied into a custom initialization function, while + * the steps for usage can be copied into, e.g., the main application function. + * + * \section ioport_quickstart_basic Basic use case + * In this use case we will configure one IO pin for button input and one for + * LED control. Then it will read the button state and output it on the LED. + * + * \section ioport_quickstart_basic_setup Setup steps + * + * \subsection ioport_quickstart_basic_setup_code Example code + * \code + #define MY_LED IOPORT_CREATE_PIN(PORTA, 5) + #define MY_BUTTON IOPORT_CREATE_PIN(PORTA, 6) + + ioport_init(); + + ioport_set_pin_dir(MY_LED, IOPORT_DIR_OUTPUT); + ioport_set_pin_dir(MY_BUTTON, IOPORT_DIR_INPUT); + ioport_set_pin_mode(MY_BUTTON, IOPORT_MODE_PULLUP); +\endcode + * + * \subsection ioport_quickstart_basic_setup_flow Workflow + * -# It's useful to give the GPIOs symbolic names and this can be done with + * the \ref IOPORT_CREATE_PIN macro. We define one for a LED and one for a + * button. + * - \code + #define MY_LED IOPORT_CREATE_PIN(PORTA, 5) + #define MY_BUTTON IOPORT_CREATE_PIN(PORTA, 6) +\endcode + * - \note The usefulness of the \ref IOPORT_CREATE_PIN macro and port names + * differ between architectures: + * - MEGA, MEGA_RF and XMEGA: Use \ref IOPORT_CREATE_PIN macro with port definitions + * PORTA, PORTB ... + * - UC3: Most convenient to pick up the device header file pin definition + * and us it directly. E.g.: AVR32_PIN_PB06 + * - SAM: Most convenient to pick up the device header file pin definition + * and us it directly. E.g.: PIO_PA5_IDX
+ * \ref IOPORT_CREATE_PIN can also be used with port definitions + * PIOA, PIOB ... + * -# Initialize the ioport service. This typically enables the IO module if + * needed. + * - \code ioport_init(); \endcode + * -# Set the LED GPIO as output: + * - \code ioport_set_pin_dir(MY_LED, IOPORT_DIR_OUTPUT); \endcode + * -# Set the button GPIO as input: + * - \code ioport_set_pin_dir(MY_BUTTON, IOPORT_DIR_INPUT); \endcode + * -# Enable pull-up for the button GPIO: + * - \code ioport_set_pin_mode(MY_BUTTON, IOPORT_MODE_PULLUP); \endcode + * + * \section ioport_quickstart_basic_usage Usage steps + * + * \subsection ioport_quickstart_basic_usage_code Example code + * \code + bool value; + + value = ioport_get_pin_level(MY_BUTTON); + ioport_set_pin_level(MY_LED, value); +\endcode + * + * \subsection ioport_quickstart_basic_usage_flow Workflow + * -# Define a boolean variable for state storage: + * - \code bool value; \endcode + * -# Read out the button level into variable value: + * - \code value = ioport_get_pin_level(MY_BUTTON); \endcode + * -# Set the LED to read out value from the button: + * - \code ioport_set_pin_level(MY_LED, value); \endcode + * + * \section ioport_quickstart_advanced Advanced use cases + * - \subpage ioport_quickstart_use_case_1 : Port access + */ + +/** + * \page ioport_quickstart_use_case_1 Advanced use case doing port access + * + * In this case we will read out the pins from one whole port and write the + * read value to another port. + * + * \section ioport_quickstart_use_case_1_setup Setup steps + * + * \subsection ioport_quickstart_use_case_1_setup_code Example code + * \code + #define IN_PORT IOPORT_PORTA + #define OUT_PORT IOPORT_PORTB + #define MASK 0x00000060 + + ioport_init(); + + ioport_set_port_dir(IN_PORT, MASK, IOPORT_DIR_INPUT); + ioport_set_port_dir(OUT_PORT, MASK, IOPORT_DIR_OUTPUT); +\endcode + * + * \subsection ioport_quickstart_basic_setup_flow Workflow + * -# It's useful to give the ports symbolic names: + * - \code + #define IN_PORT IOPORT_PORTA + #define OUT_PORT IOPORT_PORTB +\endcode + * - \note The port names differ between architectures: + * - MEGA_RF, MEGA and XMEGA: There are predefined names for ports: IOPORT_PORTA, + * IOPORT_PORTB ... + * - UC3: Use the index value of the different IO blocks: 0, 1 ... + * - SAM: There are predefined names for ports: IOPORT_PIOA, IOPORT_PIOB + * ... + * -# Also useful to define a mask for the bits to work with: + * - \code #define MASK 0x00000060 \endcode + * -# Initialize the ioport service. This typically enables the IO module if + * needed. + * - \code ioport_init(); \endcode + * -# Set one of the ports as input: + * - \code ioport_set_pin_dir(IN_PORT, MASK, IOPORT_DIR_INPUT); \endcode + * -# Set the other port as output: + * - \code ioport_set_pin_dir(OUT_PORT, MASK, IOPORT_DIR_OUTPUT); \endcode + * + * \section ioport_quickstart_basic_usage Usage steps + * + * \subsection ioport_quickstart_basic_usage_code Example code + * \code + ioport_port_mask_t value; + + value = ioport_get_port_level(IN_PORT, MASK); + ioport_set_port_level(OUT_PORT, MASK, value); +\endcode + * + * \subsection ioport_quickstart_basic_usage_flow Workflow + * -# Define a variable for port date storage: + * - \code ioport_port_mask_t value; \endcode + * -# Read out from one port: + * - \code value = ioport_get_port_level(IN_PORT, MASK); \endcode + * -# Put the read data out on the other port: + * - \code ioport_set_port_level(OUT_PORT, MASK, value); \endcode + */ + +#ifdef __cplusplus +} +#endif + +#endif /* IOPORT_H */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/ioport/sam/ioport_pio.h b/hw-libs/drivers/SAMx70/ASF/common/services/ioport/sam/ioport_pio.h new file mode 100644 index 000000000..76b4d0663 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/ioport/sam/ioport_pio.h @@ -0,0 +1,373 @@ +/** + * \file + * + * \brief SAM architecture specific IOPORT service implementation header file. + * + * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef IOPORT_SAM_H +#define IOPORT_SAM_H + +#include + +#define IOPORT_CREATE_PIN(port, pin) ((IOPORT_ ## port) * 32 + (pin)) +#define IOPORT_BASE_ADDRESS (uintptr_t)PIOA +#define IOPORT_PIO_OFFSET ((uintptr_t)PIOB - (uintptr_t)PIOA) + +#define IOPORT_PIOA 0 +#define IOPORT_PIOB 1 +#define IOPORT_PIOC 2 +#define IOPORT_PIOD 3 +#define IOPORT_PIOE 4 +#define IOPORT_PIOF 5 + +/** + * \weakgroup ioport_group + * \section ioport_modes IOPORT Modes + * + * For details on these please see the SAM Manual. + * + * @{ + */ + +/** \name IOPORT Mode bit definitions */ +/** @{ */ +#define IOPORT_MODE_MUX_MASK (0x7 << 0) /*!< MUX bits mask */ +#define IOPORT_MODE_MUX_BIT0 ( 1 << 0) /*!< MUX BIT0 mask */ + +#if SAM3N || SAM3S || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70 +#define IOPORT_MODE_MUX_BIT1 ( 1 << 1) /*!< MUX BIT1 mask */ +#endif + +#define IOPORT_MODE_MUX_A ( 0 << 0) /*!< MUX function A */ +#define IOPORT_MODE_MUX_B ( 1 << 0) /*!< MUX function B */ + +#if SAM3N || SAM3S || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70 +#define IOPORT_MODE_MUX_C ( 2 << 0) /*!< MUX function C */ +#define IOPORT_MODE_MUX_D ( 3 << 0) /*!< MUX function D */ +#endif + +#define IOPORT_MODE_PULLUP ( 1 << 3) /*!< Pull-up */ + +#if SAM3N || SAM3S || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70 +#define IOPORT_MODE_PULLDOWN ( 1 << 4) /*!< Pull-down */ +#endif + +#define IOPORT_MODE_OPEN_DRAIN ( 1 << 5) /*!< Open drain */ + +#define IOPORT_MODE_GLITCH_FILTER ( 1 << 6) /*!< Glitch filter */ +#define IOPORT_MODE_DEBOUNCE ( 1 << 7) /*!< Input debounce */ +/** @} */ + +/** @} */ + +typedef uint32_t ioport_mode_t; +typedef uint32_t ioport_pin_t; +typedef uint32_t ioport_port_t; +typedef uint32_t ioport_port_mask_t; + +__always_inline static ioport_port_t arch_ioport_pin_to_port_id(ioport_pin_t pin) +{ + return pin >> 5; +} + +__always_inline static Pio *arch_ioport_port_to_base(ioport_port_t port) +{ +#if (SAM4C || SAM4CM || SAM4CP) + if (port == IOPORT_PIOC) { + return (Pio *)(uintptr_t)PIOC; +# ifdef ID_PIOD + } else if (port == IOPORT_PIOD) { + return (Pio *)(uintptr_t)PIOD; +# endif + } else { + return (Pio *)((uintptr_t)IOPORT_BASE_ADDRESS + + (IOPORT_PIO_OFFSET * port)); + } +#else + return (Pio *)((uintptr_t)IOPORT_BASE_ADDRESS + + (IOPORT_PIO_OFFSET * port)); +#endif +} + +__always_inline static Pio *arch_ioport_pin_to_base(ioport_pin_t pin) +{ + return arch_ioport_port_to_base(arch_ioport_pin_to_port_id(pin)); +} + +__always_inline static ioport_port_mask_t arch_ioport_pin_to_mask(ioport_pin_t pin) +{ + return 1U << (pin & 0x1F); +} + +__always_inline static void arch_ioport_init(void) +{ +#ifdef ID_PIOA + sysclk_enable_peripheral_clock(ID_PIOA); +#endif +#ifdef ID_PIOB + sysclk_enable_peripheral_clock(ID_PIOB); +#endif +#ifdef ID_PIOC + sysclk_enable_peripheral_clock(ID_PIOC); +#endif +#ifdef ID_PIOD + sysclk_enable_peripheral_clock(ID_PIOD); +#endif +#ifdef ID_PIOE + sysclk_enable_peripheral_clock(ID_PIOE); +#endif +#ifdef ID_PIOF + sysclk_enable_peripheral_clock(ID_PIOF); +#endif +} + +__always_inline static void arch_ioport_enable_port(ioport_port_t port, + ioport_port_mask_t mask) +{ + arch_ioport_port_to_base(port)->PIO_PER = mask; +} + +__always_inline static void arch_ioport_disable_port(ioport_port_t port, + ioport_port_mask_t mask) +{ + arch_ioport_port_to_base(port)->PIO_PDR = mask; +} + +__always_inline static void arch_ioport_enable_pin(ioport_pin_t pin) +{ + arch_ioport_enable_port(arch_ioport_pin_to_port_id(pin), + arch_ioport_pin_to_mask(pin)); +} + +__always_inline static void arch_ioport_disable_pin(ioport_pin_t pin) +{ + arch_ioport_disable_port(arch_ioport_pin_to_port_id(pin), + arch_ioport_pin_to_mask(pin)); +} + +__always_inline static void arch_ioport_set_port_mode(ioport_port_t port, + ioport_port_mask_t mask, ioport_mode_t mode) +{ + Pio *base = arch_ioport_port_to_base(port); + + if (mode & IOPORT_MODE_PULLUP) { + base->PIO_PUER = mask; + } else { + base->PIO_PUDR = mask; + } + +#if defined(IOPORT_MODE_PULLDOWN) + if (mode & IOPORT_MODE_PULLDOWN) { + base->PIO_PPDER = mask; + } else { + base->PIO_PPDDR = mask; + } +#endif + + if (mode & IOPORT_MODE_OPEN_DRAIN) { + base->PIO_MDER = mask; + } else { + base->PIO_MDDR = mask; + } + + if (mode & (IOPORT_MODE_GLITCH_FILTER | IOPORT_MODE_DEBOUNCE)) { + base->PIO_IFER = mask; + } else { + base->PIO_IFDR = mask; + } + + if (mode & IOPORT_MODE_DEBOUNCE) { +#if SAM3U || SAM3XA + base->PIO_DIFSR = mask; +#else + base->PIO_IFSCER = mask; +#endif + } else { +#if SAM3U || SAM3XA + base->PIO_SCIFSR = mask; +#else + base->PIO_IFSCDR = mask; +#endif + } + +#if !defined(IOPORT_MODE_MUX_BIT1) + if (mode & IOPORT_MODE_MUX_BIT0) { + base->PIO_ABSR |= mask; + } else { + base->PIO_ABSR &= ~mask; + } +#else + if (mode & IOPORT_MODE_MUX_BIT0) { + base->PIO_ABCDSR[0] |= mask; + } else { + base->PIO_ABCDSR[0] &= ~mask; + } + + if (mode & IOPORT_MODE_MUX_BIT1) { + base->PIO_ABCDSR[1] |= mask; + } else { + base->PIO_ABCDSR[1] &= ~mask; + } +#endif +} + +__always_inline static void arch_ioport_set_pin_mode(ioport_pin_t pin, + ioport_mode_t mode) +{ + arch_ioport_set_port_mode(arch_ioport_pin_to_port_id(pin), + arch_ioport_pin_to_mask(pin), mode); +} + +__always_inline static void arch_ioport_set_port_dir(ioport_port_t port, + ioport_port_mask_t mask, enum ioport_direction group_direction) +{ + Pio *base = arch_ioport_port_to_base(port); + + if (group_direction == IOPORT_DIR_OUTPUT) { + base->PIO_OER = mask; + } else if (group_direction == IOPORT_DIR_INPUT) { + base->PIO_ODR = mask; + } + + base->PIO_OWER = mask; +} + +__always_inline static void arch_ioport_set_pin_dir(ioport_pin_t pin, + enum ioport_direction dir) +{ + Pio *base = arch_ioport_pin_to_base(pin); + + if (dir == IOPORT_DIR_OUTPUT) { + base->PIO_OER = arch_ioport_pin_to_mask(pin); + } else if (dir == IOPORT_DIR_INPUT) { + base->PIO_ODR = arch_ioport_pin_to_mask(pin); + } + + base->PIO_OWER = arch_ioport_pin_to_mask(pin); +} + +__always_inline static void arch_ioport_set_pin_level(ioport_pin_t pin, + bool level) +{ + Pio *base = arch_ioport_pin_to_base(pin); + + if (level) { + base->PIO_SODR = arch_ioport_pin_to_mask(pin); + } else { + base->PIO_CODR = arch_ioport_pin_to_mask(pin); + } +} + +__always_inline static void arch_ioport_set_port_level(ioport_port_t port, + ioport_port_mask_t mask, enum ioport_value level) +{ + Pio *base = arch_ioport_port_to_base(port); + + if (level){ + base->PIO_SODR = mask; + } else { + base->PIO_CODR = mask; + } +} + +__always_inline static bool arch_ioport_get_pin_level(ioport_pin_t pin) +{ + return arch_ioport_pin_to_base(pin)->PIO_PDSR & arch_ioport_pin_to_mask(pin); +} + +__always_inline static ioport_port_mask_t arch_ioport_get_port_level( + ioport_port_t port, ioport_port_mask_t mask) +{ + return arch_ioport_port_to_base(port)->PIO_PDSR & mask; +} + +__always_inline static void arch_ioport_toggle_pin_level(ioport_pin_t pin) +{ + Pio *port = arch_ioport_pin_to_base(pin); + ioport_port_mask_t mask = arch_ioport_pin_to_mask(pin); + + if (port->PIO_PDSR & arch_ioport_pin_to_mask(pin)) { + port->PIO_CODR = mask; + } else { + port->PIO_SODR = mask; + } +} + +__always_inline static void arch_ioport_toggle_port_level(ioport_port_t port, + ioport_port_mask_t mask) +{ + arch_ioport_port_to_base(port)->PIO_ODSR ^= mask; +} + +__always_inline static void arch_ioport_set_port_sense_mode(ioport_port_t port, + ioport_port_mask_t mask, enum ioport_sense pin_sense) +{ + Pio *base = arch_ioport_port_to_base(port); + /* AIMMR ELSR FRLHSR + * 0 X X IOPORT_SENSE_BOTHEDGES (Default) + * 1 0 0 IOPORT_SENSE_FALLING + * 1 0 1 IOPORT_SENSE_RISING + * 1 1 0 IOPORT_SENSE_LEVEL_LOW + * 1 1 1 IOPORT_SENSE_LEVEL_HIGH + */ + switch(pin_sense) { + case IOPORT_SENSE_LEVEL_LOW: + base->PIO_LSR = mask; + base->PIO_FELLSR = mask; + break; + case IOPORT_SENSE_LEVEL_HIGH: + base->PIO_LSR = mask; + base->PIO_REHLSR = mask; + break; + case IOPORT_SENSE_FALLING: + base->PIO_ESR = mask; + base->PIO_FELLSR = mask; + break; + case IOPORT_SENSE_RISING: + base->PIO_ESR = mask; + base->PIO_REHLSR = mask; + break; + default: + base->PIO_AIMDR = mask; + return; + } + base->PIO_AIMER = mask; +} + +__always_inline static void arch_ioport_set_pin_sense_mode(ioport_pin_t pin, + enum ioport_sense pin_sense) +{ + arch_ioport_set_port_sense_mode(arch_ioport_pin_to_port_id(pin), + arch_ioport_pin_to_mask(pin), pin_sense); +} + +#endif /* IOPORT_SAM_H */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/serial/sam_uart/uart_serial.h b/hw-libs/drivers/SAMx70/ASF/common/services/serial/sam_uart/uart_serial.h new file mode 100644 index 000000000..fa3fd71e7 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/serial/sam_uart/uart_serial.h @@ -0,0 +1,679 @@ +/** + * \file + * + * \brief Uart Serial for SAM. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef _UART_SERIAL_H_ +#define _UART_SERIAL_H_ + +#include "compiler.h" +#include "sysclk.h" +#if (SAMG55) +#include "flexcom.h" +#endif +#if ((!SAM4L) && (!SAMG55)) +#include "uart.h" +#endif +#include "usart.h" + +/** + * \name Serial Management Configuration + */ +//! @{ +#include "conf_uart_serial.h" + +//! @} + +/** Input parameters when initializing RS232 and similar modes. */ +typedef struct uart_rs232_options { + /** Set baud rate of the USART (unused in slave modes). */ + uint32_t baudrate; + + /** Number of bits to transmit as a character (5-bit to 9-bit). */ + uint32_t charlength; + + /** + * Parity type: USART_PMODE_DISABLED_gc, USART_PMODE_EVEN_gc, + * USART_PMODE_ODD_gc. + */ + uint32_t paritytype; + + /** 1, 1.5 or 2 stop bits. */ + uint32_t stopbits; + +} usart_rs232_options_t; + +typedef usart_rs232_options_t usart_serial_options_t; + +typedef Usart *usart_if; + +/** + * \brief Initializes the Usart in master mode. + * + * \param p_usart Base address of the USART instance. + * \param opt Options needed to set up RS232 communication (see + * \ref usart_options_t). + */ +static inline void usart_serial_init(usart_if p_usart, + usart_serial_options_t *opt) +{ +#if ((!SAM4L) && (!SAMG55)) + sam_uart_opt_t uart_settings; + uart_settings.ul_mck = sysclk_get_peripheral_hz(); + uart_settings.ul_baudrate = opt->baudrate; + uart_settings.ul_mode = opt->paritytype; +#endif + + sam_usart_opt_t usart_settings; + usart_settings.baudrate = opt->baudrate; + usart_settings.char_length = opt->charlength; + usart_settings.parity_type = opt->paritytype; + usart_settings.stop_bits= opt->stopbits; + usart_settings.channel_mode= US_MR_CHMODE_NORMAL; + +#ifdef UART + if (UART == (Uart*)p_usart) { + sysclk_enable_peripheral_clock(ID_UART); + /* Configure UART */ + uart_init((Uart*)p_usart, &uart_settings); + } +#else +# ifdef UART0 + if (UART0 == (Uart*)p_usart) { + sysclk_enable_peripheral_clock(ID_UART0); + /* Configure UART */ + uart_init((Uart*)p_usart, &uart_settings); + } +# endif +# ifdef UART1 + if (UART1 == (Uart*)p_usart) { + sysclk_enable_peripheral_clock(ID_UART1); + /* Configure UART */ + uart_init((Uart*)p_usart, &uart_settings); + } +# endif +# ifdef UART2 + if (UART2 == (Uart*)p_usart) { + sysclk_enable_peripheral_clock(ID_UART2); + /* Configure UART */ + uart_init((Uart*)p_usart, &uart_settings); + } +# endif +# ifdef UART3 + if (UART3 == (Uart*)p_usart) { + sysclk_enable_peripheral_clock(ID_UART3); + /* Configure UART */ + uart_init((Uart*)p_usart, &uart_settings); + } +# endif +# ifdef UART4 + if (UART4 == (Uart*)p_usart) { + sysclk_enable_peripheral_clock(ID_UART4); + /* Configure UART */ + uart_init((Uart*)p_usart, &uart_settings); + } +# endif +#endif /* ifdef UART */ + + +#ifdef USART + if (USART == p_usart) { +#if (!SAM4L) + sysclk_enable_peripheral_clock(ID_USART); + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_hz()); +#endif +#if (SAM4L) + sysclk_enable_peripheral_clock(p_usart); + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_bus_hz(p_usart)); +#endif + /* Enable the receiver and transmitter. */ + usart_enable_tx(p_usart); + usart_enable_rx(p_usart); + } +#else +# ifdef USART0 + if (USART0 == p_usart) { +#if (!SAM4L) +#if (SAMG55) + flexcom_enable(FLEXCOM0); + flexcom_set_opmode(FLEXCOM0, FLEXCOM_USART); +#else + sysclk_enable_peripheral_clock(ID_USART0); +#endif + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_hz()); +#endif +#if (SAM4L) + sysclk_enable_peripheral_clock(p_usart); + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_bus_hz(p_usart)); +#endif + /* Enable the receiver and transmitter. */ + usart_enable_tx(p_usart); + usart_enable_rx(p_usart); + } +# endif +# ifdef USART1 + if (USART1 == p_usart) { +#if (!SAM4L) +#if (SAMG55) + flexcom_enable(FLEXCOM1); + flexcom_set_opmode(FLEXCOM1, FLEXCOM_USART); +#else + sysclk_enable_peripheral_clock(ID_USART1); +#endif + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_hz()); +#endif +#if (SAM4L) + sysclk_enable_peripheral_clock(p_usart); + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_bus_hz(p_usart)); +#endif + /* Enable the receiver and transmitter. */ + usart_enable_tx(p_usart); + usart_enable_rx(p_usart); + } +# endif +# ifdef USART2 + if (USART2 == p_usart) { +#if (!SAM4L) +#if (SAMG55) + flexcom_enable(FLEXCOM2); + flexcom_set_opmode(FLEXCOM2, FLEXCOM_USART); +#else + sysclk_enable_peripheral_clock(ID_USART2); +#endif + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_hz()); +#endif +#if (SAM4L) + sysclk_enable_peripheral_clock(p_usart); + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_bus_hz(p_usart)); +#endif + /* Enable the receiver and transmitter. */ + usart_enable_tx(p_usart); + usart_enable_rx(p_usart); + } +# endif +# ifdef USART3 + if (USART3 == p_usart) { +#if (!SAM4L) +#if (SAMG55) + flexcom_enable(FLEXCOM3); + flexcom_set_opmode(FLEXCOM3, FLEXCOM_USART); +#else + sysclk_enable_peripheral_clock(ID_USART3); +#endif + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_hz()); +#endif +#if (SAM4L) + sysclk_enable_peripheral_clock(p_usart); + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_bus_hz(p_usart)); +#endif + /* Enable the receiver and transmitter. */ + usart_enable_tx(p_usart); + usart_enable_rx(p_usart); + } +# endif +# ifdef USART4 + if (USART4 == p_usart) { +#if (!SAM4L) +#if (SAMG55) + flexcom_enable(FLEXCOM4); + flexcom_set_opmode(FLEXCOM4, FLEXCOM_USART); +#else + sysclk_enable_peripheral_clock(ID_USART4); +#endif + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_hz()); +#endif +#if (SAM4L) + sysclk_enable_peripheral_clock(p_usart); + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_bus_hz(p_usart)); +#endif + /* Enable the receiver and transmitter. */ + usart_enable_tx(p_usart); + usart_enable_rx(p_usart); + } +# endif +# ifdef USART5 + if (USART5 == p_usart) { +#if (!SAM4L) +#if (SAMG55) + flexcom_enable(FLEXCOM5); + flexcom_set_opmode(FLEXCOM5, FLEXCOM_USART); +#else + sysclk_enable_peripheral_clock(ID_USART5); +#endif + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_hz()); +#endif +#if (SAM4L) + sysclk_enable_peripheral_clock(p_usart); + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_bus_hz(p_usart)); +#endif + /* Enable the receiver and transmitter. */ + usart_enable_tx(p_usart); + usart_enable_rx(p_usart); + } +# endif +# ifdef USART6 + if (USART6 == p_usart) { +#if (!SAM4L) +#if (SAMG55) + flexcom_enable(FLEXCOM6); + flexcom_set_opmode(FLEXCOM6, FLEXCOM_USART); +#else + sysclk_enable_peripheral_clock(ID_USART6); +#endif + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_hz()); +#endif +#if (SAM4L) + sysclk_enable_peripheral_clock(p_usart); + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_bus_hz(p_usart)); +#endif + /* Enable the receiver and transmitter. */ + usart_enable_tx(p_usart); + usart_enable_rx(p_usart); + } +# endif +# ifdef USART7 + if (USART7 == p_usart) { +#if (!SAM4L) +#if (SAMG55) + flexcom_enable(FLEXCOM7); + flexcom_set_opmode(FLEXCOM7, FLEXCOM_USART); +#else + sysclk_enable_peripheral_clock(ID_USART7); +#endif + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_hz()); +#endif +#if (SAM4L) + sysclk_enable_peripheral_clock(p_usart); + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_bus_hz(p_usart)); +#endif + /* Enable the receiver and transmitter. */ + usart_enable_tx(p_usart); + usart_enable_rx(p_usart); + } +# endif + +#endif /* ifdef USART */ + +} + +/** + * \brief Sends a character with the USART. + * + * \param p_usart Base address of the USART instance. + * \param c Character to write. + * + * \return Status. + * \retval 1 The character was written. + * \retval 0 The function timed out before the USART transmitter became + * ready to send. + */ +static inline int usart_serial_putchar(usart_if p_usart, const uint8_t c) +{ +#ifdef UART + if (UART == (Uart*)p_usart) { + while (uart_write((Uart*)p_usart, c)!=0); + return 1; + } +#else +# ifdef UART0 + if (UART0 == (Uart*)p_usart) { + while (uart_write((Uart*)p_usart, c)!=0); + return 1; + } +# endif +# ifdef UART1 + if (UART1 == (Uart*)p_usart) { + while (uart_write((Uart*)p_usart, c)!=0); + return 1; + } +# endif +# ifdef UART2 + if (UART2 == (Uart*)p_usart) { + while (uart_write((Uart*)p_usart, c)!=0); + return 1; + } +# endif +# ifdef UART3 + if (UART3 == (Uart*)p_usart) { + while (uart_write((Uart*)p_usart, c)!=0); + return 1; + } +# endif +#endif /* ifdef UART */ + + +#ifdef USART + if (USART == p_usart) { + while (usart_write(p_usart, c)!=0); + return 1; + } +#else +# ifdef USART0 + if (USART0 == p_usart) { + while (usart_write(p_usart, c)!=0); + return 1; + } +# endif +# ifdef USART1 + if (USART1 == p_usart) { + while (usart_write(p_usart, c)!=0); + return 1; + } +# endif +# ifdef USART2 + if (USART2 == p_usart) { + while (usart_write(p_usart, c)!=0); + return 1; + } +# endif +# ifdef USART3 + if (USART3 == p_usart) { + while (usart_write(p_usart, c)!=0); + return 1; + } +# endif +# ifdef USART4 + if (USART4 == p_usart) { + while (usart_write(p_usart, c)!=0); + return 1; + } +# endif +# ifdef USART5 + if (USART5 == p_usart) { + while (usart_write(p_usart, c)!=0); + return 1; + } +# endif +# ifdef USART6 + if (USART6 == p_usart) { + while (usart_write(p_usart, c)!=0); + return 1; + } +# endif +# ifdef USART7 + if (USART7 == p_usart) { + while (usart_write(p_usart, c)!=0); + return 1; + } +# endif +#endif /* ifdef USART */ + + return 0; +} +/** + * \brief Waits until a character is received, and returns it. + * + * \param p_usart Base address of the USART instance. + * \param data Data to read + * + */ +static inline void usart_serial_getchar(usart_if p_usart, uint8_t *data) +{ + uint32_t val = 0; + + /* Avoid Cppcheck Warning */ + UNUSED(val); + +#ifdef UART + if (UART == (Uart*)p_usart) { + while (uart_read((Uart*)p_usart, data)); + } +#else +# ifdef UART0 + if (UART0 == (Uart*)p_usart) { + while (uart_read((Uart*)p_usart, data)); + } +# endif +# ifdef UART1 + if (UART1 == (Uart*)p_usart) { + while (uart_read((Uart*)p_usart, data)); + } +# endif +# ifdef UART2 + if (UART2 == (Uart*)p_usart) { + while (uart_read((Uart*)p_usart, data)); + } +# endif +# ifdef UART3 + if (UART3 == (Uart*)p_usart) { + while (uart_read((Uart*)p_usart, data)); + } +# endif +#endif /* ifdef UART */ + + +#ifdef USART + if (USART == p_usart) { + while (usart_read(p_usart, &val)); + *data = (uint8_t)(val & 0xFF); + } +#else +# ifdef USART0 + if (USART0 == p_usart) { + while (usart_read(p_usart, &val)); + *data = (uint8_t)(val & 0xFF); + } +# endif +# ifdef USART1 + if (USART1 == p_usart) { + while (usart_read(p_usart, &val)); + *data = (uint8_t)(val & 0xFF); + } +# endif +# ifdef USART2 + if (USART2 == p_usart) { + while (usart_read(p_usart, &val)); + *data = (uint8_t)(val & 0xFF); + } +# endif +# ifdef USART3 + if (USART3 == p_usart) { + while (usart_read(p_usart, &val)); + *data = (uint8_t)(val & 0xFF); + } +# endif +# ifdef USART4 + if (USART4 == p_usart) { + while (usart_read(p_usart, &val)); + *data = (uint8_t)(val & 0xFF); + } +# endif +# ifdef USART5 + if (USART5 == p_usart) { + while (usart_read(p_usart, &val)); + *data = (uint8_t)(val & 0xFF); + } +# endif +# ifdef USART6 + if (USART6 == p_usart) { + while (usart_read(p_usart, &val)); + *data = (uint8_t)(val & 0xFF); + } +# endif +# ifdef USART7 + if (USART7 == p_usart) { + while (usart_read(p_usart, &val)); + *data = (uint8_t)(val & 0xFF); + } +# endif +#endif /* ifdef USART */ + +} + +/** + * \brief Check if Received data is ready. + * + * \param p_usart Base address of the USART instance. + * + * \retval 1 One data has been received. + * \retval 0 No data has been received. + */ +static inline uint32_t usart_serial_is_rx_ready(usart_if p_usart) +{ +#ifdef UART + if (UART == (Uart*)p_usart) { + return uart_is_rx_ready((Uart*)p_usart); + } +#else +# ifdef UART0 + if (UART0 == (Uart*)p_usart) { + return uart_is_rx_ready((Uart*)p_usart); + } +# endif +# ifdef UART1 + if (UART1 == (Uart*)p_usart) { + return uart_is_rx_ready((Uart*)p_usart); + } +# endif +# ifdef UART2 + if (UART2 == (Uart*)p_usart) { + return uart_is_rx_ready((Uart*)p_usart); + } +# endif +# ifdef UART3 + if (UART3 == (Uart*)p_usart) { + return uart_is_rx_ready((Uart*)p_usart); + } +# endif +#endif /* ifdef UART */ + + +#ifdef USART + if (USART == p_usart) { + return usart_is_rx_ready(p_usart); + } +#else +# ifdef USART0 + if (USART0 == p_usart) { + return usart_is_rx_ready(p_usart); + } +# endif +# ifdef USART1 + if (USART1 == p_usart) { + return usart_is_rx_ready(p_usart); + } +# endif +# ifdef USART2 + if (USART2 == p_usart) { + return usart_is_rx_ready(p_usart); + } +# endif +# ifdef USART3 + if (USART3 == p_usart) { + return usart_is_rx_ready(p_usart); + } +# endif +# ifdef USART4 + if (USART4 == p_usart) { + return usart_is_rx_ready(p_usart); + } +# endif +# ifdef USART5 + if (USART5 == p_usart) { + return usart_is_rx_ready(p_usart); + } +# endif +# ifdef USART6 + if (USART6 == p_usart) { + return usart_is_rx_ready(p_usart); + } +# endif +# ifdef USART7 + if (USART7 == p_usart) { + return usart_is_rx_ready(p_usart); + } +# endif +#endif /* ifdef USART */ + + return 0; +} + +/** + * \brief Send a sequence of bytes to a USART device + * + * \param usart Base address of the USART instance. + * \param data data buffer to write + * \param len Length of data + * + */ +status_code_t usart_serial_write_packet(usart_if usart, const uint8_t *data, + size_t len); + +/** + * \brief Receive a sequence of bytes to a USART device + * + * \param usart Base address of the USART instance. + * \param data data buffer to write + * \param len Length of data + * + */ +status_code_t usart_serial_read_packet(usart_if usart, uint8_t *data, + size_t len); + +#endif /* _UART_SERIAL_H_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/serial/serial.h b/hw-libs/drivers/SAMx70/ASF/common/services/serial/serial.h new file mode 100644 index 000000000..21bb15528 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/serial/serial.h @@ -0,0 +1,269 @@ +/** + * \file + * + * \brief Serial Mode management + * + * Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef SERIAL_H_INCLUDED +#define SERIAL_H_INCLUDED + +#include +#include "status_codes.h" + +/** + * \typedef usart_if + * + * This type can be used independently to refer to USART module for the + * architecture used. It refers to the correct type definition for the + * architecture, ie. USART_t* for XMEGA or avr32_usart_t* for UC3. + */ + +#if XMEGA +# include "xmega_usart/usart_serial.h" +#elif MEGA_RF +# include "megarf_usart/usart_serial.h" +#elif UC3 +# include "uc3_usart/usart_serial.h" +#elif (SAMB) +#include "samb_uart/uart_serial.h" +#elif (SAM0) +#include "sam0_usart/usart_serial.h" +#elif SAM +# include "sam_uart/uart_serial.h" +#else +# error Unsupported chip type +#endif + +/** + * + * \defgroup serial_group Serial Interface (Serial) + * + * See \ref serial_quickstart. + * + * This is the common API for serial interface. Additional features are available + * in the documentation of the specific modules. + * + * \section serial_group_platform Platform Dependencies + * + * The serial API is partially chip- or platform-specific. While all + * platforms provide mostly the same functionality, there are some + * variations around how different bus types and clock tree structures + * are handled. + * + * The following functions are available on all platforms, but there may + * be variations in the function signature (i.e. parameters) and + * behaviour. These functions are typically called by platform-specific + * parts of drivers, and applications that aren't intended to be + * portable: + * - usart_serial_init() + * - usart_serial_putchar() + * - usart_serial_getchar() + * - usart_serial_write_packet() + * - usart_serial_read_packet() + * + * + * @{ + */ + +//! @} + +/** + * \page serial_quickstart Quick start guide for Serial Interface service + * + * This is the quick start guide for the \ref serial_group "Serial Interface module", with + * step-by-step instructions on how to configure and use the serial in a + * selection of use cases. + * + * The use cases contain several code fragments. The code fragments in the + * steps for setup can be copied into a custom initialization function, while + * the steps for usage can be copied into, e.g., the main application function. + * + * \section serial_use_cases Serial use cases + * - \ref serial_basic_use_case + * - \subpage serial_use_case_1 + * + * \section serial_basic_use_case Basic use case - transmit a character + * In this use case, the serial module is configured for: + * - Using USARTD0 + * - Baudrate: 9600 + * - Character length: 8 bit + * - Parity mode: Disabled + * - Stop bit: None + * - RS232 mode + * + * The use case waits for a received character on the configured USART and + * echoes the character back to the same USART. + * + * \section serial_basic_use_case_setup Setup steps + * + * \subsection serial_basic_use_case_setup_prereq Prerequisites + * -# \ref sysclk_group "System Clock Management (sysclk)" + * + * \subsection serial_basic_use_case_setup_code Example code + * The following configuration must be added to the project (typically to a + * conf_uart_serial.h file, but it can also be added to your main application file.) + * + * \note The following takes SAM3X configuration for example, other devices have similar + * configuration, but their parameters may be different, refer to corresponding header files. + * + * \code + #define USART_SERIAL &USARTD0 + #define USART_SERIAL_BAUDRATE 9600 + #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT + #define USART_SERIAL_PARITY US_MR_PAR_NO + #define USART_SERIAL_STOP_BIT false +\endcode + * + * A variable for the received byte must be added: + * \code uint8_t received_byte; \endcode + * + * Add to application initialization: + * \code + sysclk_init(); + + static usart_serial_options_t usart_options = { + .baudrate = USART_SERIAL_BAUDRATE, + .charlength = USART_SERIAL_CHAR_LENGTH, + .paritytype = USART_SERIAL_PARITY, + .stopbits = USART_SERIAL_STOP_BIT + }; + + usart_serial_init(USART_SERIAL, &usart_options); +\endcode + * + * \subsection serial_basic_use_case_setup_flow Workflow + * -# Initialize system clock: + * - \code sysclk_init(); \endcode + * -# Create serial USART options struct: + * - \code + static usart_serial_options_t usart_options = { + .baudrate = USART_SERIAL_BAUDRATE, + .charlength = USART_SERIAL_CHAR_LENGTH, + .paritytype = USART_SERIAL_PARITY, + .stopbits = USART_SERIAL_STOP_BIT + }; +\endcode + * -# Initialize the serial service: + * - \code usart_serial_init(USART_SERIAL, &usart_options);\endcode + * + * \section serial_basic_use_case_usage Usage steps + * + * \subsection serial_basic_use_case_usage_code Example code + * Add to application C-file: + * \code + usart_serial_getchar(USART_SERIAL, &received_byte); + usart_serial_putchar(USART_SERIAL, received_byte); +\endcode + * + * \subsection serial_basic_use_case_usage_flow Workflow + * -# Wait for reception of a character: + * - \code usart_serial_getchar(USART_SERIAL, &received_byte); \endcode + * -# Echo the character back: + * - \code usart_serial_putchar(USART_SERIAL, received_byte); \endcode + */ + +/** + * \page serial_use_case_1 Advanced use case - Send a packet of serial data + * + * In this use case, the USART module is configured for: + * - Using USARTD0 + * - Baudrate: 9600 + * - Character length: 8 bit + * - Parity mode: Disabled + * - Stop bit: None + * - RS232 mode + * + * The use case sends a string of text through the USART. + * + * \section serial_use_case_1_setup Setup steps + * + * \subsection serial_use_case_1_setup_prereq Prerequisites + * -# \ref sysclk_group "System Clock Management (sysclk)" + * + * \subsection serial_use_case_1_setup_code Example code + * The following configuration must be added to the project (typically to a + * conf_uart_serial.h file, but it can also be added to your main application file.): + * + * \note The following takes SAM3X configuration for example, other devices have similar + * configuration, but their parameters may be different, refer to corresponding header files. + * + * \code + #define USART_SERIAL &USARTD0 + #define USART_SERIAL_BAUDRATE 9600 + #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT + #define USART_SERIAL_PARITY US_MR_PAR_NO + #define USART_SERIAL_STOP_BIT false +\endcode + * + * Add to application initialization: + * \code + sysclk_init(); + + static usart_serial_options_t usart_options = { + .baudrate = USART_SERIAL_BAUDRATE, + .charlength = USART_SERIAL_CHAR_LENGTH, + .paritytype = USART_SERIAL_PARITY, + .stopbits = USART_SERIAL_STOP_BIT + }; + + usart_serial_init(USART_SERIAL, &usart_options); +\endcode + * + * \subsection serial_use_case_1_setup_flow Workflow + * -# Initialize system clock: + * - \code sysclk_init(); \endcode + * -# Create USART options struct: + * - \code + static usart_serial_options_t usart_options = { + .baudrate = USART_SERIAL_BAUDRATE, + .charlength = USART_SERIAL_CHAR_LENGTH, + .paritytype = USART_SERIAL_PARITY, + .stopbits = USART_SERIAL_STOP_BIT + }; +\endcode + * -# Initialize in RS232 mode: + * - \code usart_serial_init(USART_SERIAL_EXAMPLE, &usart_options); \endcode + * + * \section serial_use_case_1_usage Usage steps + * + * \subsection serial_use_case_1_usage_code Example code + * Add to, e.g., main loop in application C-file: + * \code + usart_serial_write_packet(USART_SERIAL, "Test String", strlen("Test String")); +\endcode + * + * \subsection serial_use_case_1_usage_flow Workflow + * -# Write a string of text to the USART: + * - \code usart_serial_write_packet(USART_SERIAL, "Test String", strlen("Test String")); \endcode + */ + +#endif /* SERIAL_H_INCLUDED */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/serial/usart_serial.c b/hw-libs/drivers/SAMx70/ASF/common/services/serial/usart_serial.c new file mode 100644 index 000000000..df022e436 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/serial/usart_serial.c @@ -0,0 +1,77 @@ +/** + * + * \file + * + * \brief USART Serial driver functions. + * + * + * Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#include "serial.h" + +/** + * \brief Send a sequence of bytes to USART device + * + * \param usart Base address of the USART instance. + * \param data Data buffer to read + * \param len Length of data + * + */ +status_code_t usart_serial_write_packet(usart_if usart, const uint8_t *data, + size_t len) +{ + while (len) { + usart_serial_putchar(usart, *data); + len--; + data++; + } + return STATUS_OK; +} + + +/** + * \brief Receive a sequence of bytes from USART device + * + * \param usart Base address of the USART instance. + * \param data Data buffer to write + * \param len Length of data + * + */ +status_code_t usart_serial_read_packet(usart_if usart, uint8_t *data, + size_t len) +{ + while (len) { + usart_serial_getchar(usart, data); + len--; + data++; + } + return STATUS_OK; +} diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/sleepmgr/sam/sleepmgr.c b/hw-libs/drivers/SAMx70/ASF/common/services/sleepmgr/sam/sleepmgr.c new file mode 100644 index 000000000..f64fe1e56 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/sleepmgr/sam/sleepmgr.c @@ -0,0 +1,44 @@ +/** + * \file + * + * \brief SAM3/SAM4 Sleep manager implementation. + * + * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include +#include + +#if defined(CONFIG_SLEEPMGR_ENABLE) || defined(__DOXYGEN__) + +uint8_t sleepmgr_locks[SLEEPMGR_NR_OF_MODES]; + +#endif /* CONFIG_SLEEPMGR_ENABLE */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/sleepmgr/sam/sleepmgr.h b/hw-libs/drivers/SAMx70/ASF/common/services/sleepmgr/sam/sleepmgr.h new file mode 100644 index 000000000..e32f0ed8a --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/sleepmgr/sam/sleepmgr.h @@ -0,0 +1,111 @@ +/** + * \file + * + * \brief SAM3/SAM4 Sleep manager implementation. + * + * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef SAM_SLEEPMGR_INCLUDED +#define SAM_SLEEPMGR_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include + +/** + * \weakgroup sleepmgr_group + * @{ + */ +enum sleepmgr_mode { + //! Active mode. + SLEEPMGR_ACTIVE = 0, + /*! WFE sleep mode. + * Potential Wake Up sources: + * fast startup events (USB, RTC, RTT, WKUPs), + * interrupt, and events. */ + SLEEPMGR_SLEEP_WFE, + /*! WFI sleep mode. + * Potential Wake Up sources: fast startup events and interrupt. */ + SLEEPMGR_SLEEP_WFI, + /*! Wait mode, wakeup fast (in 3ms). + * XTAL is not disabled when sleep. + * Potential Wake Up sources: fast startup events */ + SLEEPMGR_WAIT_FAST, + /*! Wait mode. + * Potential Wake Up sources: fast startup events */ + SLEEPMGR_WAIT, +#if (!(SAMG51 || SAMG53 || SAMG54)) + //! Backup mode. Potential Wake Up sources: WKUPs, SM, RTT, RTC. + SLEEPMGR_BACKUP, +#endif + SLEEPMGR_NR_OF_MODES, +}; + +/** + * \internal + * \name Internal arrays + * @{ + */ +#if defined(CONFIG_SLEEPMGR_ENABLE) || defined(__DOXYGEN__) +//! Sleep mode lock counters +extern uint8_t sleepmgr_locks[]; +#endif /* CONFIG_SLEEPMGR_ENABLE */ +//! @} + + +static inline void sleepmgr_sleep(const enum sleepmgr_mode sleep_mode) +{ + Assert(sleep_mode != SLEEPMGR_ACTIVE); +#ifdef CONFIG_SLEEPMGR_ENABLE + cpu_irq_disable(); + + // Atomically enable the global interrupts and enter the sleep mode. + pmc_sleep(sleep_mode); +#else + UNUSED(sleep_mode); + cpu_irq_enable(); +#endif /* CONFIG_SLEEPMGR_ENABLE */ + +} + +//! @} + +#ifdef __cplusplus +} +#endif + +#endif /* SAM_SLEEPMGR_INCLUDED */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/sleepmgr/sleepmgr.h b/hw-libs/drivers/SAMx70/ASF/common/services/sleepmgr/sleepmgr.h new file mode 100644 index 000000000..2e919107c --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/sleepmgr/sleepmgr.h @@ -0,0 +1,263 @@ +/** + * \file + * + * \brief Sleep manager + * + * Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef SLEEPMGR_H +#define SLEEPMGR_H + +#include +#include + +#if (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAMS70 || SAME70) +# include "sam/sleepmgr.h" +#elif XMEGA +# include "xmega/sleepmgr.h" +#elif UC3 +# include "uc3/sleepmgr.h" +#elif SAM4L +# include "sam4l/sleepmgr.h" +#elif MEGA +# include "mega/sleepmgr.h" +#elif (SAMD20 || SAMD21 || SAMR21 || SAMD11 || SAMDA1) +# include "samd/sleepmgr.h" +#elif (SAML21 || SAML22 || SAMR30 || SAMR34 || SAMR35) +# include "saml/sleepmgr.h" +#elif (SAMC21) +# include "samc/sleepmgr.h" +#else +# error Unsupported device. +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \defgroup sleepmgr_group Sleep manager + * + * The sleep manager is a service for ensuring that the device is not put to + * sleep in deeper sleep modes than the system (e.g., peripheral drivers, + * services or the application) allows at any given time. + * + * It is based on the use of lock counting for the individual sleep modes, and + * will put the device to sleep in the shallowest sleep mode that has a non-zero + * lock count. The drivers/services/application can change these counts by use + * of \ref sleepmgr_lock_mode and \ref sleepmgr_unlock_mode. + * Refer to \ref sleepmgr_mode for a list of the sleep modes available for + * locking, and the device datasheet for information on their effect. + * + * The application must supply the file \ref conf_sleepmgr.h. + * + * For the sleep manager to be enabled, the symbol \ref CONFIG_SLEEPMGR_ENABLE + * must be defined, e.g., in \ref conf_sleepmgr.h. If this symbol is not + * defined, the functions are replaced with dummy functions and no RAM is used. + * + * @{ + */ + +/** + * \def CONFIG_SLEEPMGR_ENABLE + * \brief Configuration symbol for enabling the sleep manager + * + * If this symbol is not defined, the functions of this service are replaced + * with dummy functions. This is useful for reducing code size and execution + * time if the sleep manager is not needed in the application. + * + * This symbol may be defined in \ref conf_sleepmgr.h. + */ +#if defined(__DOXYGEN__) && !defined(CONFIG_SLEEPMGR_ENABLE) +# define CONFIG_SLEEPMGR_ENABLE +#endif + +/** + * \enum sleepmgr_mode + * \brief Sleep mode locks + * + * Identifiers for the different sleep mode locks. + */ + +/** + * \brief Initialize the lock counts + * + * Sets all lock counts to 0, except the very last one, which is set to 1. This + * is done to simplify the algorithm for finding the deepest allowable sleep + * mode in \ref sleepmgr_enter_sleep. + */ +static inline void sleepmgr_init(void) +{ +#ifdef CONFIG_SLEEPMGR_ENABLE + uint8_t i; + + for (i = 0; i < SLEEPMGR_NR_OF_MODES - 1; i++) { + sleepmgr_locks[i] = 0; + } + sleepmgr_locks[SLEEPMGR_NR_OF_MODES - 1] = 1; +#endif /* CONFIG_SLEEPMGR_ENABLE */ +} + +/** + * \brief Increase lock count for a sleep mode + * + * Increases the lock count for \a mode to ensure that the sleep manager does + * not put the device to sleep in the deeper sleep modes. + * + * \param mode Sleep mode to lock. + */ +static inline void sleepmgr_lock_mode(enum sleepmgr_mode mode) +{ +#ifdef CONFIG_SLEEPMGR_ENABLE + irqflags_t flags; + + if(sleepmgr_locks[mode] >= 0xff) { + while (true) { + // Warning: maximum value of sleepmgr_locks buffer is no more than 255. + // Check APP or change the data type to uint16_t. + } + } + + // Enter a critical section + flags = cpu_irq_save(); + + ++sleepmgr_locks[mode]; + + // Leave the critical section + cpu_irq_restore(flags); +#else + UNUSED(mode); +#endif /* CONFIG_SLEEPMGR_ENABLE */ +} + +/** + * \brief Decrease lock count for a sleep mode + * + * Decreases the lock count for \a mode. If the lock count reaches 0, the sleep + * manager can put the device to sleep in the deeper sleep modes. + * + * \param mode Sleep mode to unlock. + */ +static inline void sleepmgr_unlock_mode(enum sleepmgr_mode mode) +{ +#ifdef CONFIG_SLEEPMGR_ENABLE + irqflags_t flags; + + if(sleepmgr_locks[mode] == 0) { + while (true) { + // Warning: minimum value of sleepmgr_locks buffer is no less than 0. + // Check APP. + } + } + + // Enter a critical section + flags = cpu_irq_save(); + + --sleepmgr_locks[mode]; + + // Leave the critical section + cpu_irq_restore(flags); +#else + UNUSED(mode); +#endif /* CONFIG_SLEEPMGR_ENABLE */ +} + + /** + * \brief Retrieves the deepest allowable sleep mode + * + * Searches through the sleep mode lock counts, starting at the shallowest sleep + * mode, until the first non-zero lock count is found. The deepest allowable + * sleep mode is then returned. + */ +static inline enum sleepmgr_mode sleepmgr_get_sleep_mode(void) +{ + enum sleepmgr_mode sleep_mode = SLEEPMGR_ACTIVE; + +#ifdef CONFIG_SLEEPMGR_ENABLE + uint8_t *lock_ptr = sleepmgr_locks; + + // Find first non-zero lock count, starting with the shallowest modes. + while (!(*lock_ptr)) { + lock_ptr++; + sleep_mode = (enum sleepmgr_mode)(sleep_mode + 1); + } + + // Catch the case where one too many sleepmgr_unlock_mode() call has been + // performed on the deepest sleep mode. + Assert((uintptr_t)(lock_ptr - sleepmgr_locks) < SLEEPMGR_NR_OF_MODES); + +#endif /* CONFIG_SLEEPMGR_ENABLE */ + + return sleep_mode; +} + +/** + * \fn sleepmgr_enter_sleep + * \brief Go to sleep in the deepest allowed mode + * + * Searches through the sleep mode lock counts, starting at the shallowest sleep + * mode, until the first non-zero lock count is found. The device is then put to + * sleep in the sleep mode that corresponds to the lock. + * + * \note This function enables interrupts before going to sleep, and will leave + * them enabled upon return. This also applies if sleep is skipped due to ACTIVE + * mode being locked. + */ + +static inline void sleepmgr_enter_sleep(void) +{ +#ifdef CONFIG_SLEEPMGR_ENABLE + enum sleepmgr_mode sleep_mode; + + cpu_irq_disable(); + + // Find the deepest allowable sleep mode + sleep_mode = sleepmgr_get_sleep_mode(); + // Return right away if first mode (ACTIVE) is locked. + if (sleep_mode==SLEEPMGR_ACTIVE) { + cpu_irq_enable(); + return; + } + // Enter the deepest allowable sleep mode with interrupts enabled + sleepmgr_sleep(sleep_mode); +#else + cpu_irq_enable(); +#endif /* CONFIG_SLEEPMGR_ENABLE */ +} + + +//! @} + +#ifdef __cplusplus +} +#endif + +#endif /* SLEEPMGR_H */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/spi/sam_spi/spi_master.c b/hw-libs/drivers/SAMx70/ASF/common/services/spi/sam_spi/spi_master.c new file mode 100644 index 000000000..d73caf512 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/spi/sam_spi/spi_master.c @@ -0,0 +1,286 @@ +/** + * \file + * + * \brief SPI master common service for SAM. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "spi_master.h" +#if SAMG55 +#include "flexcom.h" +#include "conf_board.h" +#endif + +/** + * \brief Max number when the chip selects are connected to a 4- to 16-bit decoder. + */ +#define MAX_NUM_WITH_DECODER 0x10 + +/** + * \brief Max number when the chip selects are directly connected to peripheral device. + */ +#define MAX_NUM_WITHOUT_DECODER 0x04 + +/** + * \brief Max number when the chip selects are directly connected to peripheral device. + */ +#define NONE_CHIP_SELECT_ID 0x0f + +/** + * \brief The default chip select id. + */ +#define DEFAULT_CHIP_ID 0 + +/** \brief Initialize the SPI in master mode. + * + * \param p_spi Base address of the SPI instance. + * + */ +void spi_master_init(Spi *p_spi) +{ +#if SAMG55 + flexcom_enable(BOARD_FLEXCOM_SPI); + flexcom_set_opmode(BOARD_FLEXCOM_SPI, FLEXCOM_SPI); +#else + spi_enable_clock(p_spi); +#endif + spi_reset(p_spi); + spi_set_master_mode(p_spi); + spi_disable_mode_fault_detect(p_spi); + spi_disable_loopback(p_spi); + spi_set_peripheral_chip_select_value(p_spi, DEFAULT_CHIP_ID); + spi_set_fixed_peripheral_select(p_spi); + spi_disable_peripheral_select_decode(p_spi); + spi_set_delay_between_chip_select(p_spi, CONFIG_SPI_MASTER_DELAY_BCS); +} + +/** + * \brief Set up an SPI device. + * + * The returned device descriptor structure must be passed to the driver + * whenever that device should be used as current slave device. + * + * \param p_spi Base address of the SPI instance. + * \param device Pointer to SPI device struct that should be initialized. + * \param flags SPI configuration flags. Common flags for all + * implementations are the SPI modes SPI_MODE_0 ... + * SPI_MODE_3. + * \param baud_rate Baud rate for communication with slave device in Hz. + * \param sel_id Board specific select id. + */ +void spi_master_setup_device(Spi *p_spi, struct spi_device *device, + spi_flags_t flags, uint32_t baud_rate, board_spi_select_id_t sel_id) +{ +#if (SAM4L) + int16_t baud_div = spi_calc_baudrate_div(baud_rate, sysclk_get_pba_hz()); +#else + int16_t baud_div = spi_calc_baudrate_div(baud_rate, sysclk_get_peripheral_hz()); +#endif + /* avoid Cppcheck Warning */ + UNUSED(sel_id); + if (-1 == baud_div) { + Assert(0 == "Failed to find baudrate divider"); + } + spi_set_transfer_delay(p_spi, device->id, CONFIG_SPI_MASTER_DELAY_BS, + CONFIG_SPI_MASTER_DELAY_BCT); + spi_set_bits_per_transfer(p_spi, device->id, + CONFIG_SPI_MASTER_BITS_PER_TRANSFER); + spi_set_baudrate_div(p_spi, device->id, baud_div); + spi_configure_cs_behavior(p_spi, device->id, SPI_CS_KEEP_LOW); + spi_set_clock_polarity(p_spi, device->id, flags >> 1); + spi_set_clock_phase(p_spi, device->id, ((flags & 0x1) ^ 0x1)); +} + +/** + * \brief Select the given device on the SPI bus. + * + * Set device specific setting and call board chip select. + * + * \param p_spi Base address of the SPI instance. + * \param device SPI device. + * + */ +void spi_select_device(Spi *p_spi, struct spi_device *device) +{ + if (spi_get_peripheral_select_decode_setting(p_spi)) { + if (device->id < MAX_NUM_WITH_DECODER) { + spi_set_peripheral_chip_select_value(p_spi, device->id); + } + } else { + if (device->id < MAX_NUM_WITHOUT_DECODER) { + spi_set_peripheral_chip_select_value(p_spi, (~(1 << device->id))); + } + } +} + +/** + * \brief Deselect the given device on the SPI bus. + * + * Call board chip deselect. + * + * \param p_spi Base address of the SPI instance. + * \param device SPI device. + * + * \pre SPI device must be selected with spi_select_device() first. + */ +void spi_deselect_device(Spi *p_spi, struct spi_device *device) +{ + /* avoid Cppcheck Warning */ + UNUSED(device); + while (!spi_is_tx_empty(p_spi)) { + } + + // Assert all lines; no peripheral is selected. + spi_set_peripheral_chip_select_value(p_spi, NONE_CHIP_SELECT_ID); + + // Last transfer, so de-assert the current NPCS if CSAAT is set. + spi_set_lastxfer(p_spi); + +} + +/** + * \brief Send a sequence of bytes to an SPI device. + * + * Received bytes on the SPI bus are discarded. + * + * \param p_spi Base address of the SPI instance. + * \param data Data buffer to write. + * \param len Length of data to be written. + * + * \pre SPI device must be selected with spi_select_device() first. + */ +status_code_t spi_write_packet(Spi *p_spi, const uint8_t *data, + size_t len) +{ + uint32_t timeout = SPI_TIMEOUT; + uint32_t i = 0; + uint8_t val; + + while (len) { + timeout = SPI_TIMEOUT; + while (!spi_is_tx_ready(p_spi)) { + if (!timeout--) { + return ERR_TIMEOUT; + } + } + val = data[i]; + spi_write_single(p_spi, val); + i++; + len--; + } + + return STATUS_OK; +} + +/** + * \brief Receive a sequence of bytes from an SPI device. + * + * All bytes sent out on SPI bus are sent as value 0. + * + * \param p_spi Base address of the SPI instance. + * \param data Data buffer to read. + * \param len Length of data to be read. + * + * \pre SPI device must be selected with spi_select_device() first. + */ +status_code_t spi_read_packet(Spi *p_spi, uint8_t *data, size_t len) +{ + uint32_t timeout = SPI_TIMEOUT; + uint8_t val; + uint32_t i = 0; + + while (len) { + timeout = SPI_TIMEOUT; + while (!spi_is_tx_ready(p_spi)) { + if (!timeout--) { + return ERR_TIMEOUT; + } + } + spi_write_single(p_spi, CONFIG_SPI_MASTER_DUMMY); + + timeout = SPI_TIMEOUT; + while (!spi_is_rx_ready(p_spi)) { + if (!timeout--) { + return ERR_TIMEOUT; + } + } + spi_read_single(p_spi, &val); + + data[i] = val; + i++; + len--; + } + + return STATUS_OK; +} + +/** + * \brief Send and receive a sequence of bytes from an SPI device. + * + * \param p_spi Base address of the SPI instance. + * \param tx_data Data buffer to send. + * \param rx_data Data buffer to read. + * \param len Length of data to be read. + * + * \pre SPI device must be selected with spi_select_device() first. + */ +status_code_t spi_transceive_packet(Spi *p_spi, uint8_t *tx_data, uint8_t *rx_data, size_t len) +{ + uint32_t timeout = SPI_TIMEOUT; + uint8_t val; + uint32_t i = 0; + + while (len) { + timeout = SPI_TIMEOUT; + while (!spi_is_tx_ready(p_spi)) { + if (!timeout--) { + return ERR_TIMEOUT; + } + } + spi_write_single(p_spi, tx_data[i]); + + timeout = SPI_TIMEOUT; + while (!spi_is_rx_ready(p_spi)) { + if (!timeout--) { + return ERR_TIMEOUT; + } + } + spi_read_single(p_spi, &val); + + rx_data[i] = val; + i++; + len--; + } + + return STATUS_OK; +} +//! @} diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/spi/sam_spi/spi_master.h b/hw-libs/drivers/SAMx70/ASF/common/services/spi/sam_spi/spi_master.h new file mode 100644 index 000000000..bb66695c8 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/spi/sam_spi/spi_master.h @@ -0,0 +1,242 @@ +/** + * \file + * + * \brief SPI master common service for SAM. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SPI_MASTER_H_ +#define _SPI_MASTER_H_ + +#include "compiler.h" +#include "sysclk.h" +#include "status_codes.h" +#include "spi.h" + +/*! \name SPI Master Management Configuration */ +//! @{ +#include "conf_spi_master.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +//! Default Configuration of SPI Master Delay BCS +#ifndef CONFIG_SPI_MASTER_DELAY_BCS +#define CONFIG_SPI_MASTER_DELAY_BCS 0 +#endif + +//! Default Configuration of SPI Master Bits per Transfer Definition +#ifndef CONFIG_SPI_MASTER_BITS_PER_TRANSFER +#define CONFIG_SPI_MASTER_BITS_PER_TRANSFER SPI_CSR_BITS_8_BIT +#endif + +//! Default Configuration of SPI Master Delay BCT +#ifndef CONFIG_SPI_MASTER_DELAY_BCT +#define CONFIG_SPI_MASTER_DELAY_BCT 0 +#endif + +//! Default Configuration of SPI Master Delay BS +#ifndef CONFIG_SPI_MASTER_DELAY_BS +#define CONFIG_SPI_MASTER_DELAY_BS 0 +#endif + +//! Default Configuration of SPI Master Dummy Field +#ifndef CONFIG_SPI_MASTER_DUMMY +#define CONFIG_SPI_MASTER_DUMMY 0xFF +#endif +//! @} + +/** + * \brief Clock phase. + */ +#define SPI_CPHA (1 << 0) + +/** + * \brief Clock polarity. + */ +#define SPI_CPOL (1 << 1) + +/** + * \brief SPI mode 0. + */ +#define SPI_MODE_0 0 +/** + * \brief SPI mode 1. + */ +#define SPI_MODE_1 (SPI_CPHA) +/** + * \brief SPI mode 2. + */ +#define SPI_MODE_2 (SPI_CPOL) +/** + * \brief SPI mode 3. + */ +#define SPI_MODE_3 (SPI_CPOL | SPI_CPHA) + +#ifndef SPI_TYPE_DEFS +#define SPI_TYPE_DEFS +//! SPI Flags Definition +typedef uint8_t spi_flags_t; + +//! Board SPI Select Id Definition +typedef uint32_t board_spi_select_id_t; +#endif + +//! \brief Polled SPI device definition. +struct spi_device { + //! Board specific select id + board_spi_select_id_t id; +}; + +/** \brief Initialize the SPI in master mode. + * + * \param p_spi Base address of the SPI instance. + * + */ +extern void spi_master_init(Spi *p_spi); + +/** + * \brief Set up an SPI device. + * + * The returned device descriptor structure must be passed to the driver + * whenever that device should be used as current slave device. + * + * \param p_spi Base address of the SPI instance. + * \param device Pointer to SPI device struct that should be initialized. + * \param flags SPI configuration flags. Common flags for all + * implementations are the SPI modes SPI_MODE_0 ... + * SPI_MODE_3. + * \param baud_rate Baud rate for communication with slave device in Hz. + * \param sel_id Board specific select id. + */ +extern void spi_master_setup_device(Spi *p_spi, struct spi_device *device, + spi_flags_t flags, uint32_t baud_rate, board_spi_select_id_t sel_id); + +/** + * \brief Select the given device on the SPI bus. + * + * Set device specific setting and call board chip select. + * + * \param p_spi Base address of the SPI instance. + * \param device SPI device. + * + */ +extern void spi_select_device(Spi *p_spi, struct spi_device *device); + +/** + * \brief Deselect the given device on the SPI bus. + * + * Call board chip deselect. + * + * \param p_spi Base address of the SPI instance. + * \param device SPI device. + * + * \pre SPI device must be selected with spi_select_device() first. + */ +extern void spi_deselect_device(Spi *p_spi, struct spi_device *device); + + +/** \brief Write one byte to an SPI device. + * + * \param p_spi Base address of the SPI instance. + * \param data Data to write. + * + */ +static inline void spi_write_single(Spi *p_spi, uint8_t data) +{ + spi_put(p_spi, (uint16_t)data); +} + +/** + * \brief Send a sequence of bytes to an SPI device. + * + * Received bytes on the SPI bus are discarded. + * + * \param p_spi Base address of the SPI instance. + * \param data Data buffer to write. + * \param len Length of data to be written. + * + * \pre SPI device must be selected with spi_select_device() first. + */ +extern status_code_t spi_write_packet(Spi *p_spi, + const uint8_t *data, size_t len); + +/** \brief Receive one byte from an SPI device. + * + * \param p_spi Base address of the SPI instance. + * \param data Data to read. + * + */ +static inline void spi_read_single(Spi *p_spi, uint8_t *data) +{ + *data = (uint8_t)spi_get(p_spi); +} + +/** + * \brief Receive a sequence of bytes from an SPI device. + * + * All bytes sent out on SPI bus are sent as value 0xff. + * + * \param p_spi Base address of the SPI instance. + * \param data Data buffer to read. + * \param len Length of data to be read. + * + * \pre SPI device must be selected with spi_select_device() first. + */ +extern status_code_t spi_read_packet(Spi *p_spi, uint8_t *data, size_t len); + +/** + * \brief Send and receive a sequence of bytes from an SPI device. + * + * \param p_spi Base address of the SPI instance. + * \param tx_data Data buffer to send. + * \param rx_data Data buffer to read. + * \param len Length of data to be read. + * + * \pre SPI device must be selected with spi_select_device() first. + */ +extern status_code_t spi_transceive_packet(Spi *p_spi, uint8_t *tx_data, uint8_t *rx_data, size_t len); + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +#endif // _SPI_MASTER_H_ diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/spi/sam_usart_spi/usart_spi.c b/hw-libs/drivers/SAMx70/ASF/common/services/spi/sam_usart_spi/usart_spi.c new file mode 100644 index 000000000..1cf866fb1 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/spi/sam_usart_spi/usart_spi.c @@ -0,0 +1,336 @@ +/** + * \file + * + * \brief SAM USART in SPI mode driver functions. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "usart_spi.h" +#include "sysclk.h" +#if SAMG55 +#include "flexcom.h" +#include "conf_board.h" +#endif + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/*! \brief Enable the USART system clock in SPI master mode. + * + * \param p_usart Pointer to Base address of the USART instance. + * + */ +void usart_spi_init(Usart *p_usart) +{ +#if (!SAMG55) + + uint8_t uc_id = 0; + +#ifdef USART0 + if (p_usart == USART0) { + uc_id = ID_USART0; + } +#endif + +#ifdef USART1 + else if(p_usart == USART1) { + uc_id = ID_USART1; + } +#endif + +#ifdef USART2 + else if(p_usart == USART2) { + uc_id = ID_USART2; + } +#endif + +#ifdef USART3 + else if(p_usart == USART3) { + uc_id = ID_USART3; + } +#endif + +#endif + +#if SAM4L + sysclk_enable_peripheral_clock(p_usart); +#elif SAMG55 + flexcom_enable(BOARD_FLEXCOM_USART); + flexcom_set_opmode(BOARD_FLEXCOM_USART, FLEXCOM_USART); +#else + sysclk_enable_peripheral_clock(uc_id); +#endif +} + +/** + * \brief Set up a USART in SPI master mode device. + * + * The returned device descriptor structure must be passed to the driver + * whenever that device should be used as current slave device. + * + * \param p_usart Base address of the USART instance. + * \param device Pointer to usart device struct that should be initialized. + * \param flags USART configuration flags. Common flags for all + * implementations are the usart modes, which should be SPI_MODE_0, + * SPI_MODE_1, SPI_MODE_2, SPI_MODE_3. + * \param baud_rate Baud rate for communication with slave device in Hz. + * \param sel_id Board specific select id. + */ +void usart_spi_setup_device(Usart *p_usart, struct usart_spi_device *device, + spi_flags_t flags, unsigned long baud_rate, + board_spi_select_id_t sel_id) +{ + usart_spi_opt_t opt; + + /* avoid Cppcheck Warning */ + UNUSED(device); + UNUSED(sel_id); + + /* Basic usart SPI configuration. */ + opt.baudrate = baud_rate; + opt.char_length = US_MR_CHRL_8_BIT; + opt.spi_mode = flags; + opt.channel_mode = US_MR_CHMODE_NORMAL; + + /* Initialize the USART module as SPI master. */ +#if (SAM4L) + usart_init_spi_master(p_usart, &opt, sysclk_get_pba_hz()); +#else + usart_init_spi_master(p_usart, &opt, sysclk_get_peripheral_hz()); +#endif + + usart_enable_rx(p_usart); + usart_enable_tx(p_usart); +} + +/*! \brief Write one byte to an SPI device using USART in SPI mode. + * + * \param p_usart Base address of the USART instance. + * \param data The data to be sent out. + * + */ +void usart_spi_write_single(Usart *p_usart, uint8_t data) +{ + usart_putchar(p_usart, data); +} + +/** + * \brief Send a sequence of bytes to an SPI device using USART in SPI mode. + * + * Received bytes on the USART in SPI mode are discarded. + * + * \param p_usart Base address of the USART instance. + * \param data Data buffer to write. + * \param len Length of data. + * + * \return 0 if the USART in SPI master mode sends packet successfully. + * + * \pre USART device must be selected with usart_spi_select_device() first. + */ +uint32_t usart_spi_write_packet(Usart *p_usart, const uint8_t *data, size_t len) +{ + uint32_t dummy_data; + size_t i=0; + while(len) { + usart_putchar(p_usart, *(data+i)); + usart_getchar(p_usart, &dummy_data); + len--; + i++; + } + return 0; +} + +/*! \brief Receive one byte from an SPI device using USART in SPI mode. + * + * \param p_usart Base address of the USART instance. + * \param data Pointer to the data byte where to store the received data. + * + * \pre USART device must be selected with usart_spi_select_device() first. + */ +void usart_spi_read_single(Usart *p_usart, uint8_t *data) +{ + uint32_t temp_data = 0; + /* Dummy write one data to slave in order to read data. */ + usart_putchar(p_usart, CONFIG_USART_SPI_DUMMY); + + usart_getchar(p_usart, &temp_data); + *data = (uint8_t)temp_data; +} + +/** + * \brief Receive a sequence of bytes from a USART in SPI mode device. + * + * All bytes sent out on usart bus are sent as value 0. + * + * \param p_usart Base address of the usart instance. + * \param data Data buffer to put read data. + * \param len Length of data. + * + * \return 0 if the USART in SPI master mode reads packet successfully. + * + * \pre USART device must be selected with usart_spi_select_device() first. + */ +uint32_t usart_spi_read_packet(Usart *p_usart, uint8_t *data, size_t len) +{ + uint32_t val; + uint32_t i = 0; + + while(len) { + /* Dummy write one data to slave in order to read data. */ + usart_putchar(p_usart, CONFIG_USART_SPI_DUMMY); + usart_getchar(p_usart, &val); + + data[i] = (uint8_t)(val & 0xFF); + i++; + len--; + } + + return 0; +} + +/** + * \brief Select the given device on the SPI bus. + * + * \param p_usart Base address of the USART instance. + * \param device SPI device. + * + */ +void usart_spi_select_device(Usart *p_usart, struct usart_spi_device *device) +{ + /* avoid Cppcheck Warning */ + UNUSED(device); + + usart_spi_force_chip_select(p_usart); +} + +/** + * \brief De-select the given device on the SPI bus. + * + * \param p_usart Base address of the USART instance. + * \param device SPI device. + */ +void usart_spi_deselect_device(Usart *p_usart, struct usart_spi_device *device) +{ + /* avoid Cppcheck Warning */ + UNUSED(device); + + usart_spi_release_chip_select(p_usart); +} + +/*! \brief Check whether there are data in Transmit Holding Register or + * Transmit Shift Register in SPI master mode. + * + * \param p_usart Base address of the USART instance. + * + * \retval 1 The two registers are empty. + * \retval 0 One of the two registers contains data. + */ +uint32_t usart_spi_is_tx_empty(Usart *p_usart) +{ + return usart_is_tx_empty(p_usart); +} + +/*! \brief Check whether the USART in SPI master mode contains a received character. + * + * \param p_usart Base address of the USART instance. + * + * \retval 1 Some data have been received. + * \retval 0 No data has been received. + */ +uint32_t usart_spi_is_rx_ready(Usart *p_usart) +{ + return usart_is_rx_ready(p_usart); +} + +/*! \brief Check if the USART Transmit Holding Register is empty or not in SPI mode. + * + * \param p_usart Base address of the USART instance. + * + * \retval 1 There is no data in the Transmit Holding Register. + * \retval 0 There are data in the Transmit Holding Register. + */ +uint32_t usart_spi_is_tx_ready(Usart *p_usart) +{ + return usart_is_tx_ready(p_usart); +} + +/*! \brief Check if both receive buffers are full. + * + * \param p_usart Base address of the USART instance. + * + * \retval 1 Receive buffers are full. + * \retval 0 Receive buffers are not full. + */ +uint32_t usart_spi_is_rx_full(Usart *p_usart) +{ +#if (!SAMV71 && !SAMV70 && !SAME70 && !SAMS70) + return usart_is_rx_buf_full(p_usart); +#else + return 0; +#endif +} + +/*! \brief Enable the USART for the specified USART in SPI mode. + * + * \param p_usart Base address of the USART instance. + */ +void usart_spi_enable(Usart *p_usart) +{ + usart_enable_tx(p_usart); + usart_enable_rx(p_usart); +} + +/*! \brief Disable the USART for the specified USART in SPI mode. + * + * Ensure that nothing is transferred while setting up buffers. + * + * \param p_usart Base address of the USART instance. + * + */ +void usart_spi_disable(Usart *p_usart) +{ + usart_disable_tx(p_usart); + usart_disable_rx(p_usart); +} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/spi/sam_usart_spi/usart_spi.h b/hw-libs/drivers/SAMx70/ASF/common/services/spi/sam_usart_spi/usart_spi.h new file mode 100644 index 000000000..0bb53518c --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/spi/sam_usart_spi/usart_spi.h @@ -0,0 +1,103 @@ +/** + * \file + * + * \brief SAM USART in SPI mode driver functions. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _USART_SPI_H_ +#define _USART_SPI_H_ + +#include "compiler.h" +#include "usart.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/*! \name USART in SPI mode Management Configuration. + */ +//! @{ +#include "conf_usart_spi.h" + +//! Default Configuration of SPI Master Dummy Field +#ifndef CONFIG_USART_SPI_DUMMY + #define CONFIG_USART_SPI_DUMMY 0xFF +#endif +//! @} + +#ifndef SPI_TYPE_DEFS +#define SPI_TYPE_DEFS +//! SPI Flags Definition +typedef uint8_t spi_flags_t; + +//! Board SPI Select Id Definition +typedef uint32_t board_spi_select_id_t; +#endif + +typedef uint8_t port_pin_t; + +//! \brief Polled SPI device definition. +struct usart_spi_device { + /* Board specific select id. */ + port_pin_t id; +}; + +void usart_spi_init(Usart *p_usart); +void usart_spi_setup_device(Usart *p_usart, struct usart_spi_device *device, + spi_flags_t flags, unsigned long baud_rate, board_spi_select_id_t sel_id); +void usart_spi_write_single(Usart *p_usart, uint8_t data); +uint32_t usart_spi_write_packet(Usart *p_usart, const uint8_t *data, size_t len); +void usart_spi_read_single(Usart *p_usart, uint8_t *data); +uint32_t usart_spi_read_packet(Usart *p_usart, uint8_t *data, size_t len); +void usart_spi_select_device(Usart *p_usart, struct usart_spi_device *device); +void usart_spi_deselect_device(Usart *p_usart, struct usart_spi_device *device); +uint32_t usart_spi_is_tx_empty(Usart *p_usart); +uint32_t usart_spi_is_rx_ready(Usart *p_usart); +uint32_t usart_spi_is_tx_ready(Usart *p_usart); +uint32_t usart_spi_is_rx_full(Usart *p_usart); +void usart_spi_enable(Usart *p_usart); +void usart_spi_disable(Usart *p_usart); + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +#endif /* _USART_SPI_H_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/spi/spi_master.h b/hw-libs/drivers/SAMx70/ASF/common/services/spi/spi_master.h new file mode 100644 index 000000000..c5cd16a52 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/spi/spi_master.h @@ -0,0 +1,263 @@ +/** + * \file + * + * \brief SPI Master Mode management + * + * Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef SPI_MASTER_H_INCLUDED +#define SPI_MASTER_H_INCLUDED + +#include + +#if XMEGA +# include "xmega_spi/spi_master.h" +#elif MEGA_RF +# include "megarf_spi/spi_master.h" +#elif UC3 +# include "uc3_spi/spi_master.h" +#elif SAM +# include "sam_spi/spi_master.h" +#else +# error Unsupported chip type +#endif + +/** + * + * \defgroup spi_group Serial Peripheral Interface (SPI) + * + * This is the common API for SPI interface. Additional features are available + * in the documentation of the specific modules. + * + * \section spi_group_platform Platform Dependencies + * + * The SPI API is partially chip- or platform-specific. While all + * platforms provide mostly the same functionality, there are some + * variations around how different bus types and clock tree structures + * are handled. + * + * The following functions are available on all platforms, but there may + * be variations in the function signature (i.e. parameters) and + * behavior. These functions are typically called by platform-specific + * parts of drivers, and applications that aren't intended to be + * portable: + * - spi_master_init() + * - spi_master_setup_device() + * - spi_select_device() + * - spi_deselect_device() + * - spi_write_single() + * - spi_write_packet() + * - spi_read_single() + * - spi_read_packet() + * - spi_is_tx_empty() + * - spi_is_tx_ready() + * - spi_is_rx_full() + * - spi_is_rx_ready() + * - spi_enable() + * - spi_disable() + * - spi_is_enabled() + * + * \section spi_master_quickstart_section Quick Start Guide + * See \ref common_spi_master_quickstart + * @{ + */ + +//! @} + +/** + * \page common_spi_master_quickstart Quick Start Guide for the SPI Master Driver + * + * This is the quick start guide for the \ref spi_group "SPI Driver", with + * step-by-step instructions on how to configure and use the driver for a + * specific use case. + * + * The use case contain several code fragments. The code fragments in the + * steps for setup can be copied into a custom initialization function, while + * the steps for usage can be copied into, e.g., the main application function. + * + * The steps for setting up the SPI master for XMEGA and UC3 use exactly the + * same approach, but note that there are different names on the peripherals. So + * to use this Quick Start for UC3 please make sure that all the peripheral + * names are updated according to the UC3 datasheet. + * - \subpage spi_master_xmega + * + */ +/** + * \page spi_master_xmega Basic setup for SPI master on XMEGA devices + * + * \section spi_master_xmega_basic Basic setup for XMEGA devices + * The SPI module will be set up as master: + * - SPI on PORTD + * - 1MHz SPI clock speed + * - Slave Chip Select connected on PORTD pin 1 + * - SPI mode 0 (data on rising clock edge) + * + * \section spi_master_xmega_basic_setup Setup steps + * \subsection spi_master_xmega_basic_setup_code Example code + * Add to application C-file (e.g. main.c): + * \code + void spi_init_pins(void) + { + ioport_configure_port_pin(&PORTD, PIN1_bm, IOPORT_INIT_HIGH | IOPORT_DIR_OUTPUT); + + ioport_configure_port_pin(&PORTD, PIN4_bm, IOPORT_PULL_UP | IOPORT_DIR_INPUT); + ioport_configure_port_pin(&PORTD, PIN5_bm, IOPORT_INIT_HIGH | IOPORT_DIR_OUTPUT); + ioport_configure_port_pin(&PORTD, PIN6_bm, IOPORT_DIR_INPUT); + ioport_configure_port_pin(&PORTD, PIN7_bm, IOPORT_INIT_HIGH | IOPORT_DIR_OUTPUT); + } + + void spi_init_module(void) + { + struct spi_device spi_device_conf = { + .id = IOPORT_CREATE_PIN(PORTD, 1) + }; + + spi_master_init(&SPID); + spi_master_setup_device(&SPID, &spi_device_conf, SPI_MODE_0, 1000000, 0); + spi_enable(&SPID); + } +\endcode + * + * \subsection spi_master_xmega_basic_setup Workflow + * -# Ensure that \ref conf_spi_master.h is present for the driver. + * - \note This file is only for the driver and should not be included by the + * user. In this example the file can be left empty. + * -# Initialize the pins used by the SPI interface (this initialization is for + * the ATxmega32A4U device). + * -# Set the pin used for slave select as output high: + * \code + ioport_configure_port_pin(&PORTD, PIN1_bm, IOPORT_INIT_HIGH | IOPORT_DIR_OUTPUT); +\endcode + * -# Enable pull-up on own chip select (SS): + * \code + ioport_configure_port_pin(&PORTD, PIN4_bm, IOPORT_PULL_UP | IOPORT_DIR_INPUT); +\endcode + * \attention If this pin is pulled low the SPI module will go into slave mode. + * -# Set MOSI and SCL as output high, and set MISO as input: + * \code + ioport_configure_port_pin(&PORTD, PIN5_bm, IOPORT_INIT_HIGH | IOPORT_DIR_OUTPUT); + ioport_configure_port_pin(&PORTD, PIN6_bm, IOPORT_DIR_INPUT); + ioport_configure_port_pin(&PORTD, PIN7_bm, IOPORT_INIT_HIGH | IOPORT_DIR_OUTPUT); +\endcode + * -# Define the SPI device configuration struct to describe which pin the + * slave select (slave chip select) is connected to, in this case the slave + * select pin has been connected to PORTD pin 1 (PD1): + * - \code + struct spi_device spi_device_conf = { + .id = IOPORT_CREATE_PIN(PORTD, 1) + }; +\endcode + * -# Initialize the SPI module, in this case SPI on PORTD has been chosen: + * - \code + spi_master_init(&SPID); +\endcode + * -# Setup the SPI master module for a specific device: + * - \code + spi_master_setup_device(&SPID, &spi_device_conf, SPI_MODE_0, 1000000, 0); +\endcode + * - \note The last argument, which is zero in this case, can be ignored and is + * only included for compatibility purposes. + * -# Then enable the SPI: + * - \code + spi_enable(&SPID); +\endcode + * + * \section spi_master_xmega_basic_usage Usage steps + * \subsection spi_master_xmega_basic_usage_code Example code + * Add to, e.g., the main loop in the application C-file: + * \code + uint8_t data_buffer[1] = {0xAA}; + + struct spi_device spi_device_conf = { + .id = IOPORT_CREATE_PIN(PORTD, 1) + }; + + spi_select_device(&SPID, &spi_device_conf); + + spi_write_packet(&SPID, data_buffer, 1); + spi_read_packet(&SPID, data_buffer, 1); + + spi_deselect_device(&SPID, &spi_device_conf); +\endcode + * + * \subsection spi_master_xmega_basic_usage_flow Workflow + * -# Create a buffer for data to be sent/received on the SPI bus, in this case + * a single byte buffer is used. The buffer can be of arbitrary size as long as + * there is space left in SRAM: + * - \code + uint8_t data_buffer[1] = {0xAA}; +\endcode + * -# Define the SPI device configuration struct to describe which pin the + * slave select (slave chip select) is connected to, in this case the slave + * select pin has been connected to PORTD pin 1 (PD1): + * - \code + struct spi_device spi_device_conf = { + .id = IOPORT_CREATE_PIN(PORTD, 1) + }; +\endcode + * - \note As this struct is the same for both the initializing part and the usage + * part it could be a good idea to make the struct global, and hence accessible + * for both the initializing part and usage part. Another solution could be to + * create the struct in the main function and pass the address of the struct to + * the spi_init_module() function, e.g.: + * \code + void spi_init_module(struct spi_device *spi_device_conf) + { + ... + + spi_master_setup_device(&SPID, spi_device_conf, SPI_MODE_0, 1000000, 0); + + ... + } +\endcode + * -# Write data to the SPI slave device, in this case write one byte from the + * data_buffer: + * - \code + spi_write_packet(&SPID, data_buffer, 1); +\endcode + * -# Read data from the SPI slave device, in this case read one byte and put it + * into the data_buffer: + * - \code + spi_read_packet(&SPID, data_buffer, 1); +\endcode + * - \attention As the SPI works as a shift register so that data is shifted in at + * the same time as data is shifted out a read operation will mean that a dummy + * byte \ref CONFIG_SPI_MASTER_DUMMY is written to the SPI bus. \ref CONFIG_SPI_MASTER_DUMMY + * defaults to 0xFF, but can be changed by defining it inside the \ref conf_spi_master.h + * file. + * -# When read and write operations is done de-select the slave: + * - \code + spi_deselect_device(&SPID, &spi_device_conf); +\endcode + * + */ + +#endif /* SPI_MASTER_H_INCLUDED */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/spi/usart_spi.h b/hw-libs/drivers/SAMx70/ASF/common/services/spi/usart_spi.h new file mode 100644 index 000000000..c1657967a --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/spi/usart_spi.h @@ -0,0 +1,94 @@ +/** + * \file + * + * \brief USART in SPI mode driver functions. + * + * Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef USART_SPI_H_INCLUDED +#define USART_SPI_H_INCLUDED + +#include + +#if XMEGA +# include "xmega_usart_spi/usart_spi.h" +#elif MEGA_RF +# include "megarf_usart_spi/usart_spi.h" +#elif UC3 +# include "uc3_usart_spi/usart_spi.h" +#elif SAM +# include "sam_usart_spi/usart_spi.h" +#else +# error Unsupported chip type +#endif + +/** + * + * \defgroup usart_spi_group USART in SPI (Serial Peripheral Interface) mode + * + * This is the common API for USART in SPI mode. Additional features are available + * in the documentation of the specific modules. + * + * \section spi_group_platform Platform Dependencies + * + * The spi API is partially chip- or platform-specific. While all + * platforms provide mostly the same functionality, there are some + * variations around how different bus types and clock tree structures + * are handled. + * + * The following functions are available on all platforms, but there may + * be variations in the function signature (i.e. parameters) and + * behaviour. These functions are typically called by platform-specific + * parts of drivers, and applications that aren't intended to be + * portable: + * - usart_spi_init() + * - usart_spi_setup_device() + * - usart_spi_select_device() + * - usart_spi_deselect_device() + * - usart_spi_write_single() + * - usart_spi_write_packet() + * - usart_spi_read_single() + * - usart_spi_read_packet() + * - usart_spi_is_tx_empty() + * - usart_spi_is_tx_ready() + * - usart_spi_is_rx_full() + * - usart_spi_is_rx_ready() + * - usart_spi_enable() + * - usart_spi_disable() + * - usart_spi_is_enabled() + * + * + * @{ + */ + +//! @} + +#endif /* USART_SPI_H_INCLUDED */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/storage/ctrl_access/ctrl_access.c b/hw-libs/drivers/SAMx70/ASF/common/services/storage/ctrl_access/ctrl_access.c new file mode 100644 index 000000000..67e61a3ba --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/storage/ctrl_access/ctrl_access.c @@ -0,0 +1,634 @@ +/***************************************************************************** + * + * \file + * + * \brief Abstraction layer for memory interfaces. + * + * This module contains the interfaces: + * - MEM <-> USB; + * - MEM <-> RAM; + * - MEM <-> MEM. + * + * This module may be configured and expanded to support the following features: + * - write-protected globals; + * - password-protected data; + * - specific features; + * - etc. + * + * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + ******************************************************************************/ +/* + * Support and FAQ: visit Microchip Support + */ + + +//_____ I N C L U D E S ____________________________________________________ + +#include "compiler.h" +#include "preprocessor.h" +#ifdef FREERTOS_USED +#include "FreeRTOS.h" +#include "semphr.h" +#endif +#include "ctrl_access.h" + + +//_____ D E F I N I T I O N S ______________________________________________ + +#ifdef FREERTOS_USED + +/*! \name LUN Access Protection Macros + */ +//! @{ + +/*! \brief Locks accesses to LUNs. + * + * \return \c true if the access was successfully locked, else \c false. + */ +#define Ctrl_access_lock() ctrl_access_lock() + +/*! \brief Unlocks accesses to LUNs. + */ +#define Ctrl_access_unlock() xSemaphoreGive(ctrl_access_semphr) + +//! @} + +//! Handle to the semaphore protecting accesses to LUNs. +static xSemaphoreHandle ctrl_access_semphr = NULL; + +#else + +/*! \name LUN Access Protection Macros + */ +//! @{ + +/*! \brief Locks accesses to LUNs. + * + * \return \c true if the access was successfully locked, else \c false. + */ +#define Ctrl_access_lock() true + +/*! \brief Unlocks accesses to LUNs. + */ +#define Ctrl_access_unlock() + +//! @} + +#endif // FREERTOS_USED + + +#if MAX_LUN + +/*! \brief Initializes an entry of the LUN descriptor table. + * + * \param lun Logical Unit Number. + * + * \return LUN descriptor table entry initializer. + */ +#if ACCESS_USB == true && ACCESS_MEM_TO_RAM == true +#define Lun_desc_entry(lun) \ + {\ + TPASTE3(Lun_, lun, _test_unit_ready),\ + TPASTE3(Lun_, lun, _read_capacity),\ + TPASTE3(Lun_, lun, _unload),\ + TPASTE3(Lun_, lun, _wr_protect),\ + TPASTE3(Lun_, lun, _removal),\ + TPASTE3(Lun_, lun, _usb_read_10),\ + TPASTE3(Lun_, lun, _usb_write_10),\ + TPASTE3(Lun_, lun, _mem_2_ram),\ + TPASTE3(Lun_, lun, _ram_2_mem),\ + TPASTE3(LUN_, lun, _NAME)\ + } +#elif ACCESS_USB == true +#define Lun_desc_entry(lun) \ + {\ + TPASTE3(Lun_, lun, _test_unit_ready),\ + TPASTE3(Lun_, lun, _read_capacity),\ + TPASTE3(Lun_, lun, _unload),\ + TPASTE3(Lun_, lun, _wr_protect),\ + TPASTE3(Lun_, lun, _removal),\ + TPASTE3(Lun_, lun, _usb_read_10),\ + TPASTE3(Lun_, lun, _usb_write_10),\ + TPASTE3(LUN_, lun, _NAME)\ + } +#elif ACCESS_MEM_TO_RAM == true +#define Lun_desc_entry(lun) \ + {\ + TPASTE3(Lun_, lun, _test_unit_ready),\ + TPASTE3(Lun_, lun, _read_capacity),\ + TPASTE3(Lun_, lun, _unload),\ + TPASTE3(Lun_, lun, _wr_protect),\ + TPASTE3(Lun_, lun, _removal),\ + TPASTE3(Lun_, lun, _mem_2_ram),\ + TPASTE3(Lun_, lun, _ram_2_mem),\ + TPASTE3(LUN_, lun, _NAME)\ + } +#else +#define Lun_desc_entry(lun) \ + {\ + TPASTE3(Lun_, lun, _test_unit_ready),\ + TPASTE3(Lun_, lun, _read_capacity),\ + TPASTE3(Lun_, lun, _unload),\ + TPASTE3(Lun_, lun, _wr_protect),\ + TPASTE3(Lun_, lun, _removal),\ + TPASTE3(LUN_, lun, _NAME)\ + } +#endif + +//! LUN descriptor table. +static const struct +{ + Ctrl_status (*test_unit_ready)(void); + Ctrl_status (*read_capacity)(U32 *); + bool (*unload)(bool); + bool (*wr_protect)(void); + bool (*removal)(void); +#if ACCESS_USB == true + Ctrl_status (*usb_read_10)(U32, U16); + Ctrl_status (*usb_write_10)(U32, U16); +#endif +#if ACCESS_MEM_TO_RAM == true + Ctrl_status (*mem_2_ram)(U32, void *); + Ctrl_status (*ram_2_mem)(U32, const void *); +#endif + const char *name; +} lun_desc[MAX_LUN] = +{ +#if LUN_0 == ENABLE +# ifndef Lun_0_unload +# define Lun_0_unload NULL +# endif + Lun_desc_entry(0), +#endif +#if LUN_1 == ENABLE +# ifndef Lun_1_unload +# define Lun_1_unload NULL +# endif + Lun_desc_entry(1), +#endif +#if LUN_2 == ENABLE +# ifndef Lun_2_unload +# define Lun_2_unload NULL +# endif + Lun_desc_entry(2), +#endif +#if LUN_3 == ENABLE +# ifndef Lun_3_unload +# define Lun_3_unload NULL +# endif + Lun_desc_entry(3), +#endif +#if LUN_4 == ENABLE +# ifndef Lun_4_unload +# define Lun_4_unload NULL +# endif + Lun_desc_entry(4), +#endif +#if LUN_5 == ENABLE +# ifndef Lun_5_unload +# define Lun_5_unload NULL +# endif + Lun_desc_entry(5), +#endif +#if LUN_6 == ENABLE +# ifndef Lun_6_unload +# define Lun_6_unload NULL +# endif + Lun_desc_entry(6), +#endif +#if LUN_7 == ENABLE +# ifndef Lun_7_unload +# define Lun_7_unload NULL +# endif + Lun_desc_entry(7) +#endif +}; + +#endif + + +#if GLOBAL_WR_PROTECT == true +bool g_wr_protect; +#endif + + +/*! \name Control Interface + */ +//! @{ + + +#ifdef FREERTOS_USED + +bool ctrl_access_init(void) +{ + // If the handle to the protecting semaphore is not valid, + if (!ctrl_access_semphr) + { + // try to create the semaphore. + vSemaphoreCreateBinary(ctrl_access_semphr); + + // If the semaphore could not be created, there is no backup solution. + if (!ctrl_access_semphr) return false; + } + + return true; +} + + +/*! \brief Locks accesses to LUNs. + * + * \return \c true if the access was successfully locked, else \c false. + */ +static bool ctrl_access_lock(void) +{ + // If the semaphore could not be created, there is no backup solution. + if (!ctrl_access_semphr) return false; + + // Wait for the semaphore. + while (!xSemaphoreTake(ctrl_access_semphr, portMAX_DELAY)); + + return true; +} + +#endif // FREERTOS_USED + + +U8 get_nb_lun(void) +{ +#if MEM_USB == ENABLE +# ifndef Lun_usb_get_lun +# define Lun_usb_get_lun() host_get_lun() +# endif + U8 nb_lun; + + if (!Ctrl_access_lock()) return MAX_LUN; + + nb_lun = MAX_LUN + Lun_usb_get_lun(); + + Ctrl_access_unlock(); + + return nb_lun; +#else + return MAX_LUN; +#endif +} + + +U8 get_cur_lun(void) +{ + return LUN_ID_0; +} + + +Ctrl_status mem_test_unit_ready(U8 lun) +{ + Ctrl_status status; + + if (!Ctrl_access_lock()) return CTRL_FAIL; + + status = +#if MAX_LUN + (lun < MAX_LUN) ? lun_desc[lun].test_unit_ready() : +#endif +#if LUN_USB == ENABLE + Lun_usb_test_unit_ready(lun - LUN_ID_USB); +#else + CTRL_FAIL; +#endif + + Ctrl_access_unlock(); + + return status; +} + + +Ctrl_status mem_read_capacity(U8 lun, U32 *u32_nb_sector) +{ + Ctrl_status status; + + if (!Ctrl_access_lock()) return CTRL_FAIL; + + status = +#if MAX_LUN + (lun < MAX_LUN) ? lun_desc[lun].read_capacity(u32_nb_sector) : +#endif +#if LUN_USB == ENABLE + Lun_usb_read_capacity(lun - LUN_ID_USB, u32_nb_sector); +#else + CTRL_FAIL; +#endif + + Ctrl_access_unlock(); + + return status; +} + + +U8 mem_sector_size(U8 lun) +{ + U8 sector_size; + + if (!Ctrl_access_lock()) return 0; + + sector_size = +#if MAX_LUN + (lun < MAX_LUN) ? 1 : +#endif +#if LUN_USB == ENABLE + Lun_usb_read_sector_size(lun - LUN_ID_USB); +#else + 0; +#endif + + Ctrl_access_unlock(); + + return sector_size; +} + + +bool mem_unload(U8 lun, bool unload) +{ + bool unloaded; +#if !MAX_LUN || !defined(Lun_usb_unload) + UNUSED(lun); +#endif + + if (!Ctrl_access_lock()) return false; + + unloaded = +#if MAX_LUN + (lun < MAX_LUN) ? + (lun_desc[lun].unload ? + lun_desc[lun].unload(unload) : !unload) : +#endif +#if LUN_USB == ENABLE +# if defined(Lun_usb_unload) + Lun_usb_unload(lun - LUN_ID_USB, unload); +# else + !unload; /* Can not unload: load success, unload fail */ +# endif +#else + false; /* No mem, unload/load fail */ +#endif + + Ctrl_access_unlock(); + + return unloaded; +} + +bool mem_wr_protect(U8 lun) +{ + bool wr_protect; + + if (!Ctrl_access_lock()) return true; + + wr_protect = +#if MAX_LUN + (lun < MAX_LUN) ? lun_desc[lun].wr_protect() : +#endif +#if LUN_USB == ENABLE + Lun_usb_wr_protect(lun - LUN_ID_USB); +#else + true; +#endif + + Ctrl_access_unlock(); + + return wr_protect; +} + + +bool mem_removal(U8 lun) +{ + bool removal; +#if MAX_LUN==0 + UNUSED(lun); +#endif + + if (!Ctrl_access_lock()) return true; + + removal = +#if MAX_LUN + (lun < MAX_LUN) ? lun_desc[lun].removal() : +#endif +#if LUN_USB == ENABLE + Lun_usb_removal(); +#else + true; +#endif + + Ctrl_access_unlock(); + + return removal; +} + + +const char *mem_name(U8 lun) +{ +#if MAX_LUN==0 + UNUSED(lun); +#endif + return +#if MAX_LUN + (lun < MAX_LUN) ? lun_desc[lun].name : +#endif +#if LUN_USB == ENABLE + LUN_USB_NAME; +#else + NULL; +#endif +} + + +//! @} + + +#if ACCESS_USB == true + +/*! \name MEM <-> USB Interface + */ +//! @{ + + +Ctrl_status memory_2_usb(U8 lun, U32 addr, U16 nb_sector) +{ + Ctrl_status status; + + if (!Ctrl_access_lock()) return CTRL_FAIL; + + memory_start_read_action(nb_sector); + status = +#if MAX_LUN + (lun < MAX_LUN) ? lun_desc[lun].usb_read_10(addr, nb_sector) : +#endif + CTRL_FAIL; + memory_stop_read_action(); + + Ctrl_access_unlock(); + + return status; +} + + +Ctrl_status usb_2_memory(U8 lun, U32 addr, U16 nb_sector) +{ + Ctrl_status status; + + if (!Ctrl_access_lock()) return CTRL_FAIL; + + memory_start_write_action(nb_sector); + status = +#if MAX_LUN + (lun < MAX_LUN) ? lun_desc[lun].usb_write_10(addr, nb_sector) : +#endif + CTRL_FAIL; + memory_stop_write_action(); + + Ctrl_access_unlock(); + + return status; +} + + +//! @} + +#endif // ACCESS_USB == true + + +#if ACCESS_MEM_TO_RAM == true + +/*! \name MEM <-> RAM Interface + */ +//! @{ + + +Ctrl_status memory_2_ram(U8 lun, U32 addr, void *ram) +{ + Ctrl_status status; +#if MAX_LUN==0 + UNUSED(lun); +#endif + + if (!Ctrl_access_lock()) return CTRL_FAIL; + + memory_start_read_action(1); + status = +#if MAX_LUN + (lun < MAX_LUN) ? lun_desc[lun].mem_2_ram(addr, ram) : +#endif +#if LUN_USB == ENABLE + Lun_usb_mem_2_ram(addr, ram); +#else + CTRL_FAIL; +#endif + memory_stop_read_action(); + + Ctrl_access_unlock(); + + return status; +} + + +Ctrl_status ram_2_memory(U8 lun, U32 addr, const void *ram) +{ + Ctrl_status status; +#if MAX_LUN==0 + UNUSED(lun); +#endif + + if (!Ctrl_access_lock()) return CTRL_FAIL; + + memory_start_write_action(1); + status = +#if MAX_LUN + (lun < MAX_LUN) ? lun_desc[lun].ram_2_mem(addr, ram) : +#endif +#if LUN_USB == ENABLE + Lun_usb_ram_2_mem(addr, ram); +#else + CTRL_FAIL; +#endif + memory_stop_write_action(); + + Ctrl_access_unlock(); + + return status; +} + + +//! @} + +#endif // ACCESS_MEM_TO_RAM == true + + +#if ACCESS_STREAM == true + +/*! \name Streaming MEM <-> MEM Interface + */ +//! @{ + + + #if ACCESS_MEM_TO_MEM == true + +#include "fat.h" + +Ctrl_status stream_mem_to_mem(U8 src_lun, U32 src_addr, U8 dest_lun, U32 dest_addr, U16 nb_sector) +{ + COMPILER_ALIGNED(4) + static U8 sector_buf[FS_512B]; + Ctrl_status status = CTRL_GOOD; + + while (nb_sector--) + { + if ((status = memory_2_ram(src_lun, src_addr++, sector_buf)) != CTRL_GOOD) break; + if ((status = ram_2_memory(dest_lun, dest_addr++, sector_buf)) != CTRL_GOOD) break; + } + + return status; +} + + #endif // ACCESS_MEM_TO_MEM == true + + +Ctrl_status stream_state(U8 id) +{ + UNUSED(id); + return CTRL_GOOD; +} + + +U16 stream_stop(U8 id) +{ + UNUSED(id); + return 0; +} + + +//! @} + +#endif // ACCESS_STREAM == true diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/storage/ctrl_access/ctrl_access.h b/hw-libs/drivers/SAMx70/ASF/common/services/storage/ctrl_access/ctrl_access.h new file mode 100644 index 000000000..1fcf710f7 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/storage/ctrl_access/ctrl_access.h @@ -0,0 +1,392 @@ +/***************************************************************************** + * + * \file + * + * \brief Abstraction layer for memory interfaces. + * + * This module contains the interfaces: + * - MEM <-> USB; + * - MEM <-> RAM; + * - MEM <-> MEM. + * + * This module may be configured and expanded to support the following features: + * - write-protected globals; + * - password-protected data; + * - specific features; + * - etc. + * + * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + ******************************************************************************/ +/* + * Support and FAQ: visit Microchip Support + */ + + +#ifndef _CTRL_ACCESS_H_ +#define _CTRL_ACCESS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \defgroup group_common_services_storage_ctrl_access Memory Control Access + * + * Common abstraction layer for memory interfaces. It provides interfaces between: + * Memory and USB, Memory and RAM, Memory and Memory. Common API for XMEGA and UC3. + * + * \{ + */ + +#include "compiler.h" +#include "conf_access.h" + +#ifndef SECTOR_SIZE +#define SECTOR_SIZE 512 +#endif + +//! Status returned by CTRL_ACCESS interfaces. +typedef enum +{ + CTRL_GOOD = PASS, //!< Success, memory ready. + CTRL_FAIL = FAIL, //!< An error occurred. + CTRL_NO_PRESENT = FAIL + 1, //!< Memory unplugged. + CTRL_BUSY = FAIL + 2 //!< Memory not initialized or changed. +} Ctrl_status; + + +// FYI: Each Logical Unit Number (LUN) corresponds to a memory. + +// Check LUN defines. +#ifndef LUN_0 + #error LUN_0 must be defined as ENABLE or DISABLE in conf_access.h +#endif +#ifndef LUN_1 + #error LUN_1 must be defined as ENABLE or DISABLE in conf_access.h +#endif +#ifndef LUN_2 + #error LUN_2 must be defined as ENABLE or DISABLE in conf_access.h +#endif +#ifndef LUN_3 + #error LUN_3 must be defined as ENABLE or DISABLE in conf_access.h +#endif +#ifndef LUN_4 + #error LUN_4 must be defined as ENABLE or DISABLE in conf_access.h +#endif +#ifndef LUN_5 + #error LUN_5 must be defined as ENABLE or DISABLE in conf_access.h +#endif +#ifndef LUN_6 + #error LUN_6 must be defined as ENABLE or DISABLE in conf_access.h +#endif +#ifndef LUN_7 + #error LUN_7 must be defined as ENABLE or DISABLE in conf_access.h +#endif +#ifndef LUN_USB + #error LUN_USB must be defined as ENABLE or DISABLE in conf_access.h +#endif + +/*! \name LUN IDs + */ +//! @{ +#define LUN_ID_0 (0) //!< First static LUN. +#define LUN_ID_1 (LUN_ID_0 + LUN_0) +#define LUN_ID_2 (LUN_ID_1 + LUN_1) +#define LUN_ID_3 (LUN_ID_2 + LUN_2) +#define LUN_ID_4 (LUN_ID_3 + LUN_3) +#define LUN_ID_5 (LUN_ID_4 + LUN_4) +#define LUN_ID_6 (LUN_ID_5 + LUN_5) +#define LUN_ID_7 (LUN_ID_6 + LUN_6) +#define MAX_LUN (LUN_ID_7 + LUN_7) //!< Number of static LUNs. +#define LUN_ID_USB (MAX_LUN) //!< First dynamic LUN (USB host mass storage). +//! @} + + +// Include LUN header files. +#if LUN_0 == ENABLE + #include LUN_0_INCLUDE +#endif +#if LUN_1 == ENABLE + #include LUN_1_INCLUDE +#endif +#if LUN_2 == ENABLE + #include LUN_2_INCLUDE +#endif +#if LUN_3 == ENABLE + #include LUN_3_INCLUDE +#endif +#if LUN_4 == ENABLE + #include LUN_4_INCLUDE +#endif +#if LUN_5 == ENABLE + #include LUN_5_INCLUDE +#endif +#if LUN_6 == ENABLE + #include LUN_6_INCLUDE +#endif +#if LUN_7 == ENABLE + #include LUN_7_INCLUDE +#endif +#if LUN_USB == ENABLE + #include LUN_USB_INCLUDE +#endif + + +// Check the configuration of write protection in conf_access.h. +#ifndef GLOBAL_WR_PROTECT + #error GLOBAL_WR_PROTECT must be defined as true or false in conf_access.h +#endif + + +#if GLOBAL_WR_PROTECT == true + +//! Write protect. +extern bool g_wr_protect; + +#endif + + +/*! \name Control Interface + */ +//! @{ + +#ifdef FREERTOS_USED + +/*! \brief Initializes the LUN access locker. + * + * \return \c true if the locker was successfully initialized, else \c false. + */ +extern bool ctrl_access_init(void); + +#endif // FREERTOS_USED + +/*! \brief Returns the number of LUNs. + * + * \return Number of LUNs in the system. + */ +extern U8 get_nb_lun(void); + +/*! \brief Returns the current LUN. + * + * \return Current LUN. + * + * \todo Implement. + */ +extern U8 get_cur_lun(void); + +/*! \brief Tests the memory state and initializes the memory if required. + * + * The TEST UNIT READY SCSI primary command allows an application client to poll + * a LUN until it is ready without having to allocate memory for returned data. + * + * This command may be used to check the media status of LUNs with removable + * media. + * + * \param lun Logical Unit Number. + * + * \return Status. + */ +extern Ctrl_status mem_test_unit_ready(U8 lun); + +/*! \brief Returns the address of the last valid sector (512 bytes) in the + * memory. + * + * \param lun Logical Unit Number. + * \param u32_nb_sector Pointer to the address of the last valid sector. + * + * \return Status. + */ +extern Ctrl_status mem_read_capacity(U8 lun, U32 *u32_nb_sector); + +/*! \brief Returns the size of the physical sector. + * + * \param lun Logical Unit Number. + * + * \return Sector size (unit: 512 bytes). + */ +extern U8 mem_sector_size(U8 lun); + +/*! \brief Unload/load the medium. + * + * \param lun Logical Unit Number. + * \param unload \c true to unload the medium, \c false to load the medium. + * + * \return \c true if unload/load success, else \c false. + */ +extern bool mem_unload(U8 lun, bool unload); + +/*! \brief Returns the write-protection state of the memory. + * + * \param lun Logical Unit Number. + * + * \return \c true if the memory is write-protected, else \c false. + * + * \note Only used by removable memories with hardware-specific write + * protection. + */ +extern bool mem_wr_protect(U8 lun); + +/*! \brief Tells whether the memory is removable. + * + * \param lun Logical Unit Number. + * + * \return \c true if the memory is removable, else \c false. + */ +extern bool mem_removal(U8 lun); + +/*! \brief Returns a pointer to the LUN name. + * + * \param lun Logical Unit Number. + * + * \return Pointer to the LUN name string. + */ +extern const char *mem_name(U8 lun); + +//! @} + + +#if ACCESS_USB == true + +/*! \name MEM <-> USB Interface + */ +//! @{ + +/*! \brief Transfers data from the memory to USB. + * + * \param lun Logical Unit Number. + * \param addr Address of first memory sector to read. + * \param nb_sector Number of sectors to transfer. + * + * \return Status. + */ +extern Ctrl_status memory_2_usb(U8 lun, U32 addr, U16 nb_sector); + +/*! \brief Transfers data from USB to the memory. + * + * \param lun Logical Unit Number. + * \param addr Address of first memory sector to write. + * \param nb_sector Number of sectors to transfer. + * + * \return Status. + */ +extern Ctrl_status usb_2_memory(U8 lun, U32 addr, U16 nb_sector); + +//! @} + +#endif // ACCESS_USB == true + + +#if ACCESS_MEM_TO_RAM == true + +/*! \name MEM <-> RAM Interface + */ +//! @{ + +/*! \brief Copies 1 data sector from the memory to RAM. + * + * \param lun Logical Unit Number. + * \param addr Address of first memory sector to read. + * \param ram Pointer to RAM buffer to write. + * + * \return Status. + */ +extern Ctrl_status memory_2_ram(U8 lun, U32 addr, void *ram); + +/*! \brief Copies 1 data sector from RAM to the memory. + * + * \param lun Logical Unit Number. + * \param addr Address of first memory sector to write. + * \param ram Pointer to RAM buffer to read. + * + * \return Status. + */ +extern Ctrl_status ram_2_memory(U8 lun, U32 addr, const void *ram); + +//! @} + +#endif // ACCESS_MEM_TO_RAM == true + + +#if ACCESS_STREAM == true + +/*! \name Streaming MEM <-> MEM Interface + */ +//! @{ + +//! Erroneous streaming data transfer ID. +#define ID_STREAM_ERR 0xFF + + #if ACCESS_MEM_TO_MEM == true + +/*! \brief Copies data from one memory to another. + * + * \param src_lun Source Logical Unit Number. + * \param src_addr Source address of first memory sector to read. + * \param dest_lun Destination Logical Unit Number. + * \param dest_addr Destination address of first memory sector to write. + * \param nb_sector Number of sectors to copy. + * + * \return Status. + */ +extern Ctrl_status stream_mem_to_mem(U8 src_lun, U32 src_addr, U8 dest_lun, U32 dest_addr, U16 nb_sector); + + #endif // ACCESS_MEM_TO_MEM == true + +/*! \brief Returns the state of a streaming data transfer. + * + * \param id Transfer ID. + * + * \return Status. + * + * \todo Implement. + */ +extern Ctrl_status stream_state(U8 id); + +/*! \brief Stops a streaming data transfer. + * + * \param id Transfer ID. + * + * \return Number of remaining sectors. + * + * \todo Implement. + */ +extern U16 stream_stop(U8 id); + +//! @} + +#endif // ACCESS_STREAM == true + +/** + * \} + */ + +#ifdef __cplusplus +} +#endif + +#endif // _CTRL_ACCESS_H_ diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/usb/class/cdc/device/udi_cdc.c b/hw-libs/drivers/SAMx70/ASF/common/services/usb/class/cdc/device/udi_cdc.c new file mode 100644 index 000000000..95b02e85d --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/usb/class/cdc/device/udi_cdc.c @@ -0,0 +1,1161 @@ +/** + * \file + * + * \brief USB Device Communication Device Class (CDC) interface. + * + * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "ISBoards.h" + +#if USE_FREERTOS +#include "FreeRTOS.h" +#include +#else +#include "d_time.h" +#endif +#include "conf_usb.h" +#include "usb_protocol.h" +#include "usb_protocol_cdc.h" +#include "udd.h" +#include "udc.h" +#include "udi_cdc.h" +#include + +#ifdef UDI_CDC_LOW_RATE +# ifdef USB_DEVICE_HS_SUPPORT +# define UDI_CDC_TX_BUFFERS (UDI_CDC_DATA_EPS_HS_SIZE) +# define UDI_CDC_RX_BUFFERS (UDI_CDC_DATA_EPS_HS_SIZE) +# else +# define UDI_CDC_TX_BUFFERS (UDI_CDC_DATA_EPS_FS_SIZE) +# define UDI_CDC_RX_BUFFERS (UDI_CDC_DATA_EPS_FS_SIZE) +# endif +#else +# ifdef USB_DEVICE_HS_SUPPORT +# define UDI_CDC_TX_BUFFERS (UDI_CDC_DATA_EPS_HS_SIZE) +# define UDI_CDC_RX_BUFFERS (UDI_CDC_DATA_EPS_HS_SIZE) +# else +# define UDI_CDC_TX_BUFFERS (5*UDI_CDC_DATA_EPS_FS_SIZE) +# define UDI_CDC_RX_BUFFERS (5*UDI_CDC_DATA_EPS_FS_SIZE) +# endif +#endif + +#ifndef UDI_CDC_TX_EMPTY_NOTIFY +# define UDI_CDC_TX_EMPTY_NOTIFY(port) +#endif + +/** + * \ingroup udi_cdc_group + * \defgroup udi_cdc_group_udc Interface with USB Device Core (UDC) + * + * Structures and functions required by UDC. + * + * @{ + */ +bool udi_cdc_comm_enable(void); +void udi_cdc_comm_disable(void); +bool udi_cdc_comm_setup(void); +bool udi_cdc_data_enable(void); +void udi_cdc_data_disable(void); +bool udi_cdc_data_setup(void); +uint8_t udi_cdc_getsetting(void); +void udi_cdc_data_sof_notify(void); +UDC_DESC_STORAGE udi_api_t udi_api_cdc_comm = { + .enable = udi_cdc_comm_enable, + .disable = udi_cdc_comm_disable, + .setup = udi_cdc_comm_setup, + .getsetting = udi_cdc_getsetting, +}; +UDC_DESC_STORAGE udi_api_t udi_api_cdc_data = { + .enable = udi_cdc_data_enable, + .disable = udi_cdc_data_disable, + .setup = udi_cdc_data_setup, + .getsetting = udi_cdc_getsetting, + .sof_notify = udi_cdc_data_sof_notify, +}; +//@} + +/** + * \ingroup udi_cdc_group + * \defgroup udi_cdc_group_internal Implementation of UDI CDC + * + * Class internal implementation + * @{ + */ + +/** + * \name Internal routines + */ +//@{ + +/** + * \name Routines to control serial line + */ +//@{ + +/** + * \brief Returns the port number corresponding at current setup request + * + * \return port number + */ +static uint8_t udi_cdc_setup_to_port(void); + +/** + * \brief Sends line coding to application + * + * Called after SETUP request when line coding data is received. + */ +static void udi_cdc_line_coding_received(void); + +/** + * \brief Records new state + * + * \param port Communication port number to manage + * \param b_set State is enabled if true, else disabled + * \param bit_mask Field to process (see CDC_SERIAL_STATE_ defines) + */ +static void udi_cdc_ctrl_state_change(uint8_t port, bool b_set, le16_t bit_mask); + +/** + * \brief Check and eventually notify the USB host of new state + * + * \param port Communication port number to manage + * \param ep Port communication endpoint + */ +static void udi_cdc_ctrl_state_notify(uint8_t port, udd_ep_id_t ep); + +/** + * \brief Ack sent of serial state message + * Callback called after serial state message sent + * + * \param status UDD_EP_TRANSFER_OK, if transfer finished + * \param status UDD_EP_TRANSFER_ABORT, if transfer aborted + * \param n number of data transfered + */ +static void udi_cdc_serial_state_msg_sent(udd_ep_status_t status, iram_size_t n, udd_ep_id_t ep); + +//@} + +/** + * \name Routines to process data transfer + */ +//@{ + +/** + * \brief Enable the reception of data from the USB host + * + * The value udi_cdc_rx_trans_sel indicate the RX buffer to fill. + * + * \param port Communication port number to manage + * + * \return \c 1 if function was successfully done, otherwise \c 0. + */ +static bool udi_cdc_rx_start(uint8_t port); + +/** + * \brief Update rx buffer management with a new data + * Callback called after data reception on USB line + * + * \param status UDD_EP_TRANSFER_OK, if transfer finish + * \param status UDD_EP_TRANSFER_ABORT, if transfer aborted + * \param n number of data received + */ +static void udi_cdc_data_received(udd_ep_status_t status, iram_size_t n, udd_ep_id_t ep); + +/** + * \brief Ack sent of tx buffer + * Callback called after data transfer on USB line + * + * \param status UDD_EP_TRANSFER_OK, if transfer finished + * \param status UDD_EP_TRANSFER_ABORT, if transfer aborted + * \param n number of data transfered + */ +static void udi_cdc_data_sent(udd_ep_status_t status, iram_size_t n, udd_ep_id_t ep); + +/** + * \brief Send buffer on line or wait a SOF event + * + * \param port Communication port number to manage + */ +static void udi_cdc_tx_send(uint8_t port); + +//@} + +//@} + +/** + * \name Information about configuration of communication line + */ +//@{ +COMPILER_WORD_ALIGNED + static usb_cdc_line_coding_t udi_cdc_line_coding[UDI_CDC_PORT_NB]; +static bool udi_cdc_serial_state_msg_ongoing[UDI_CDC_PORT_NB]; +static volatile le16_t udi_cdc_state[UDI_CDC_PORT_NB]; +COMPILER_WORD_ALIGNED static usb_cdc_notify_serial_state_t uid_cdc_state_msg[UDI_CDC_PORT_NB]; + +//! Status of CDC COMM interfaces +static volatile uint8_t udi_cdc_nb_comm_enabled = 0; +//@} + +/** + * \name Variables to manage RX/TX transfer requests + * Two buffers for each sense are used to optimize the speed. + */ +//@{ + +//! Status of CDC DATA interfaces +static volatile uint8_t udi_cdc_nb_data_enabled = 0; +static volatile bool udi_cdc_data_running = false; +//! Buffer to receive data +COMPILER_ALIGNED(32) static uint8_t udi_cdc_rx_buf[UDI_CDC_PORT_NB][2][UDI_CDC_RX_BUFFERS]; +//! Data available in RX buffers +static volatile uint16_t udi_cdc_rx_buf_nb[UDI_CDC_PORT_NB][2]; +//! Give the current RX buffer used (rx0 if 0, rx1 if 1) +static volatile uint8_t udi_cdc_rx_buf_sel[UDI_CDC_PORT_NB]; +//! Read position in current RX buffer +static volatile uint16_t udi_cdc_rx_pos[UDI_CDC_PORT_NB]; +//! Signal a transfer on-going +static volatile bool udi_cdc_rx_trans_ongoing[UDI_CDC_PORT_NB]; + +//! Define a transfer halted +#define UDI_CDC_TRANS_HALTED 2 + +//! Buffer to send data +COMPILER_ALIGNED(32) static uint8_t udi_cdc_tx_buf[UDI_CDC_PORT_NB][2][UDI_CDC_TX_BUFFERS]; +//! Data available in TX buffers +static uint16_t udi_cdc_tx_buf_nb[UDI_CDC_PORT_NB][2]; +//! Give current TX buffer used (tx0 if 0, tx1 if 1) +static volatile uint8_t udi_cdc_tx_buf_sel[UDI_CDC_PORT_NB]; +//! Value of SOF during last TX transfer +static uint16_t udi_cdc_tx_sof_num[UDI_CDC_PORT_NB]; +//! Signal a transfer on-going +static volatile bool udi_cdc_tx_trans_ongoing[UDI_CDC_PORT_NB]; +//! Signal that both buffer content data to send +static volatile bool udi_cdc_tx_both_buf_to_send[UDI_CDC_PORT_NB]; + +//@} + +bool udi_cdc_comm_enable(void) +{ + uint8_t port; + uint8_t iface_comm_num; + +#if UDI_CDC_PORT_NB == 1 // To optimize code + port = 0; + udi_cdc_nb_comm_enabled = 0; +#else + if (udi_cdc_nb_comm_enabled > UDI_CDC_PORT_NB) { + udi_cdc_nb_comm_enabled = 0; + } + port = udi_cdc_nb_comm_enabled; +#endif + + // Initialize control signal management + udi_cdc_state[port] = CPU_TO_LE16(0); + + uid_cdc_state_msg[port].header.bmRequestType = + USB_REQ_DIR_IN | USB_REQ_TYPE_CLASS | + USB_REQ_RECIP_INTERFACE; + uid_cdc_state_msg[port].header.bNotification = USB_REQ_CDC_NOTIFY_SERIAL_STATE; + uid_cdc_state_msg[port].header.wValue = LE16(0); + + switch (port) { +#define UDI_CDC_PORT_TO_IFACE_COMM(index, unused) \ + case index: \ + iface_comm_num = UDI_CDC_COMM_IFACE_NUMBER_##index; \ + break; + MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_PORT_TO_IFACE_COMM, ~) +#undef UDI_CDC_PORT_TO_IFACE_COMM + default: + iface_comm_num = UDI_CDC_COMM_IFACE_NUMBER_0; + break; + } + + uid_cdc_state_msg[port].header.wIndex = LE16(iface_comm_num); + uid_cdc_state_msg[port].header.wLength = LE16(2); + uid_cdc_state_msg[port].value = CPU_TO_LE16(0); + + udi_cdc_line_coding[port].dwDTERate = CPU_TO_LE32(UDI_CDC_DEFAULT_RATE); + udi_cdc_line_coding[port].bCharFormat = UDI_CDC_DEFAULT_STOPBITS; + udi_cdc_line_coding[port].bParityType = UDI_CDC_DEFAULT_PARITY; + udi_cdc_line_coding[port].bDataBits = UDI_CDC_DEFAULT_DATABITS; + // Call application callback + // to initialize memories or indicate that interface is enabled + UDI_CDC_SET_CODING_EXT(port,(&udi_cdc_line_coding[port])); + if (!UDI_CDC_ENABLE_EXT(port)) { + return false; + } + udi_cdc_nb_comm_enabled++; + return true; +} + +bool udi_cdc_data_enable(void) +{ + uint8_t port; + +#if UDI_CDC_PORT_NB == 1 // To optimize code + port = 0; + udi_cdc_nb_data_enabled = 0; +#else + if (udi_cdc_nb_data_enabled > UDI_CDC_PORT_NB) { + udi_cdc_nb_data_enabled = 0; + } + port = udi_cdc_nb_data_enabled; +#endif + + // Initialize TX management + udi_cdc_tx_trans_ongoing[port] = false; + udi_cdc_tx_both_buf_to_send[port] = false; + udi_cdc_tx_buf_sel[port] = 0; + udi_cdc_tx_buf_nb[port][0] = 0; + udi_cdc_tx_buf_nb[port][1] = 0; + udi_cdc_tx_sof_num[port] = 0; + udi_cdc_tx_send(port); + + // Initialize RX management + udi_cdc_rx_trans_ongoing[port] = false; + udi_cdc_rx_buf_sel[port] = 0; + udi_cdc_rx_buf_nb[port][0] = 0; + udi_cdc_rx_buf_nb[port][1] = 0; + udi_cdc_rx_pos[port] = 0; + if (!udi_cdc_rx_start(port)) { + return false; + } + udi_cdc_nb_data_enabled++; + if (udi_cdc_nb_data_enabled == UDI_CDC_PORT_NB) { + udi_cdc_data_running = true; + } + return true; +} + +void udi_cdc_comm_disable(void) +{ + Assert(udi_cdc_nb_comm_enabled != 0); + udi_cdc_nb_comm_enabled--; +} + +void udi_cdc_data_disable(void) +{ + uint8_t port; + + Assert(udi_cdc_nb_data_enabled != 0); + udi_cdc_nb_data_enabled--; + port = udi_cdc_nb_data_enabled; + UDI_CDC_DISABLE_EXT(port); + udi_cdc_data_running = false; +} + +bool udi_cdc_comm_setup(void) +{ + uint8_t port = udi_cdc_setup_to_port(); + + if (Udd_setup_is_in()) { + // GET Interface Requests + if (Udd_setup_type() == USB_REQ_TYPE_CLASS) { + // Requests Class Interface Get + switch (udd_g_ctrlreq.req.bRequest) { + case USB_REQ_CDC_GET_LINE_CODING: + // Get configuration of CDC line + if (sizeof(usb_cdc_line_coding_t) != + udd_g_ctrlreq.req.wLength) + return false; // Error for USB host + udd_g_ctrlreq.payload = + (uint8_t *) & + udi_cdc_line_coding[port]; + udd_g_ctrlreq.payload_size = + sizeof(usb_cdc_line_coding_t); + return true; + } + } + } + if (Udd_setup_is_out()) { + // SET Interface Requests + if (Udd_setup_type() == USB_REQ_TYPE_CLASS) { + // Requests Class Interface Set + switch (udd_g_ctrlreq.req.bRequest) { + case USB_REQ_CDC_SET_LINE_CODING: + // Change configuration of CDC line + if (sizeof(usb_cdc_line_coding_t) != + udd_g_ctrlreq.req.wLength) + return false; // Error for USB host + udd_g_ctrlreq.callback = + udi_cdc_line_coding_received; + udd_g_ctrlreq.payload = + (uint8_t *) & + udi_cdc_line_coding[port]; + udd_g_ctrlreq.payload_size = + sizeof(usb_cdc_line_coding_t); + return true; + case USB_REQ_CDC_SET_CONTROL_LINE_STATE: + // According cdc spec 1.1 chapter 6.2.14 + UDI_CDC_SET_DTR_EXT(port, (0 != + (udd_g_ctrlreq.req.wValue + & CDC_CTRL_SIGNAL_DTE_PRESENT))); + UDI_CDC_SET_RTS_EXT(port, (0 != + (udd_g_ctrlreq.req.wValue + & CDC_CTRL_SIGNAL_ACTIVATE_CARRIER))); + return true; + } + } + } + return false; // request Not supported +} + +bool udi_cdc_data_setup(void) +{ + return false; // request Not supported +} + +uint8_t udi_cdc_getsetting(void) +{ + return 0; // CDC don't have multiple alternate setting +} + +void udi_cdc_data_sof_notify(void) +{ + static uint8_t port_notify = 0; + + // A call of udi_cdc_data_sof_notify() is done for each port + udi_cdc_tx_send(port_notify); +#if UDI_CDC_PORT_NB != 1 // To optimize code + port_notify++; + if (port_notify >= UDI_CDC_PORT_NB) { + port_notify = 0; + } +#endif +} + + +//------------------------------------------------- +//------- Internal routines to control serial line + +static uint8_t udi_cdc_setup_to_port(void) +{ + uint8_t port; + + switch (udd_g_ctrlreq.req.wIndex & 0xFF) { +#define UDI_CDC_IFACE_COMM_TO_PORT(iface, unused) \ + case UDI_CDC_COMM_IFACE_NUMBER_##iface: \ + port = iface; \ + break; + MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_IFACE_COMM_TO_PORT, ~) +#undef UDI_CDC_IFACE_COMM_TO_PORT + default: + port = 0; + break; + } + return port; +} + +static void udi_cdc_line_coding_received(void) +{ + uint8_t port = udi_cdc_setup_to_port(); + UNUSED(port); + + UDI_CDC_SET_CODING_EXT(port, (&udi_cdc_line_coding[port])); +} + +static void udi_cdc_ctrl_state_change(uint8_t port, bool b_set, le16_t bit_mask) +{ + irqflags_t flags; + udd_ep_id_t ep_comm; + +#if UDI_CDC_PORT_NB == 1 // To optimize code + port = 0; +#endif + + // Update state + flags = cpu_irq_save(); // Protect udi_cdc_state + if (b_set) { + udi_cdc_state[port] |= bit_mask; + } else { + udi_cdc_state[port] &= ~(unsigned)bit_mask; + } + cpu_irq_restore(flags); + + // Send it if possible and state changed + switch (port) { +#define UDI_CDC_PORT_TO_COMM_EP(index, unused) \ + case index: \ + ep_comm = UDI_CDC_COMM_EP_##index; \ + break; + MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_PORT_TO_COMM_EP, ~) +#undef UDI_CDC_PORT_TO_COMM_EP + default: + ep_comm = UDI_CDC_COMM_EP_0; + break; + } + udi_cdc_ctrl_state_notify(port, ep_comm); +} + + +static void udi_cdc_ctrl_state_notify(uint8_t port, udd_ep_id_t ep) +{ +#if UDI_CDC_PORT_NB == 1 // To optimize code + port = 0; +#endif + + // Send it if possible and state changed + if ((!udi_cdc_serial_state_msg_ongoing[port]) + && (udi_cdc_state[port] != uid_cdc_state_msg[port].value)) { + // Fill notification message + uid_cdc_state_msg[port].value = udi_cdc_state[port]; + // Send notification message + udi_cdc_serial_state_msg_ongoing[port] = + udd_ep_run(ep, + false, + (uint8_t *) & uid_cdc_state_msg[port], + sizeof(uid_cdc_state_msg[0]), + udi_cdc_serial_state_msg_sent); + } +} + + +static void udi_cdc_serial_state_msg_sent(udd_ep_status_t status, iram_size_t n, udd_ep_id_t ep) +{ + uint8_t port; + UNUSED(n); + UNUSED(status); + + switch (ep) { +#define UDI_CDC_GET_PORT_FROM_COMM_EP(iface, unused) \ + case UDI_CDC_COMM_EP_##iface: \ + port = iface; \ + break; + MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_GET_PORT_FROM_COMM_EP, ~) +#undef UDI_CDC_GET_PORT_FROM_COMM_EP + default: + port = 0; + break; + } + + udi_cdc_serial_state_msg_ongoing[port] = false; + + // For the irregular signals like break, the incoming ring signal, + // or the overrun error state, this will reset their values to zero + // and again will not send another notification until their state changes. + udi_cdc_state[port] &= ~(CDC_SERIAL_STATE_BREAK | + CDC_SERIAL_STATE_RING | + CDC_SERIAL_STATE_FRAMING | + CDC_SERIAL_STATE_PARITY | CDC_SERIAL_STATE_OVERRUN); + uid_cdc_state_msg[port].value &= ~(CDC_SERIAL_STATE_BREAK | + CDC_SERIAL_STATE_RING | + CDC_SERIAL_STATE_FRAMING | + CDC_SERIAL_STATE_PARITY | CDC_SERIAL_STATE_OVERRUN); + // Send it if possible and state changed + udi_cdc_ctrl_state_notify(port, ep); +} + + +//------------------------------------------------- +//------- Internal routines to process data transfer + + +static bool udi_cdc_rx_start(uint8_t port) +{ + irqflags_t flags; + uint8_t buf_sel_trans; + udd_ep_id_t ep; + +#if UDI_CDC_PORT_NB == 1 // To optimize code + port = 0; +#endif + + flags = cpu_irq_save(); + buf_sel_trans = udi_cdc_rx_buf_sel[port]; + if (udi_cdc_rx_trans_ongoing[port] || + (udi_cdc_rx_pos[port] < udi_cdc_rx_buf_nb[port][buf_sel_trans])) { + // Transfer already on-going or current buffer no empty + cpu_irq_restore(flags); + return false; + } + + // Change current buffer + udi_cdc_rx_pos[port] = 0; + udi_cdc_rx_buf_sel[port] = (buf_sel_trans==0)?1:0; + + // Start transfer on RX + udi_cdc_rx_trans_ongoing[port] = true; + cpu_irq_restore(flags); + + if (udi_cdc_multi_is_rx_ready(port)) { + UDI_CDC_RX_NOTIFY(port); + } + // Send the buffer with enable of short packet + switch (port) { +#define UDI_CDC_PORT_TO_DATA_EP_OUT(index, unused) \ + case index: \ + ep = UDI_CDC_DATA_EP_OUT_##index; \ + break; + MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_PORT_TO_DATA_EP_OUT, ~) +#undef UDI_CDC_PORT_TO_DATA_EP_OUT + default: + ep = UDI_CDC_DATA_EP_OUT_0; + break; + } + return udd_ep_run(ep, + true, + udi_cdc_rx_buf[port][buf_sel_trans], + UDI_CDC_RX_BUFFERS, + udi_cdc_data_received); +} + + +static void udi_cdc_data_received(udd_ep_status_t status, iram_size_t n, udd_ep_id_t ep) +{ + uint8_t buf_sel_trans; + uint8_t port; + + switch (ep) { +#define UDI_CDC_DATA_EP_OUT_TO_PORT(index, unused) \ + case UDI_CDC_DATA_EP_OUT_##index: \ + port = index; \ + break; + MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_DATA_EP_OUT_TO_PORT, ~) +#undef UDI_CDC_DATA_EP_OUT_TO_PORT + default: + port = 0; + break; + } + + if (UDD_EP_TRANSFER_OK != status) { + // Abort reception + return; + } + buf_sel_trans = (udi_cdc_rx_buf_sel[port]==0)?1:0; + if (!n) { + udd_ep_run( ep, + true, + udi_cdc_rx_buf[port][buf_sel_trans], + UDI_CDC_RX_BUFFERS, + udi_cdc_data_received); + return; + } + udi_cdc_rx_buf_nb[port][buf_sel_trans] = n; + udi_cdc_rx_trans_ongoing[port] = false; + udi_cdc_rx_start(port); +} + + +static void udi_cdc_data_sent(udd_ep_status_t status, iram_size_t n, udd_ep_id_t ep) +{ + uint8_t port; + UNUSED(n); + + switch (ep) { +#define UDI_CDC_DATA_EP_IN_TO_PORT(index, unused) \ + case UDI_CDC_DATA_EP_IN_##index: \ + port = index; \ + break; + MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_DATA_EP_IN_TO_PORT, ~) +#undef UDI_CDC_DATA_EP_IN_TO_PORT + default: + port = 0; + break; + } + + if (UDD_EP_TRANSFER_OK != status) { + // Abort transfer + return; + } + udi_cdc_tx_buf_nb[port][(udi_cdc_tx_buf_sel[port]==0)?1:0] = 0; + udi_cdc_tx_both_buf_to_send[port] = false; + udi_cdc_tx_trans_ongoing[port] = false; + + if (n != 0) { + UDI_CDC_TX_EMPTY_NOTIFY(port); + } + udi_cdc_tx_send(port); +} + + +static void udi_cdc_tx_send(uint8_t port) +{ + irqflags_t flags; + uint8_t buf_sel_trans; + bool b_short_packet; + udd_ep_id_t ep; + static uint16_t sof_zlp_counter = 0; + +#if UDI_CDC_PORT_NB == 1 // To optimize code + port = 0; +#endif + + if (udi_cdc_tx_trans_ongoing[port]) { + return; // Already on going or wait next SOF to send next data + } + if (udd_is_high_speed()) { + if (udi_cdc_tx_sof_num[port] == udd_get_micro_frame_number()) { + return; // Wait next SOF to send next data + } + }else{ + if (udi_cdc_tx_sof_num[port] == udd_get_frame_number()) { + return; // Wait next SOF to send next data + } + } + + flags = cpu_irq_save(); // to protect udi_cdc_tx_buf_sel + buf_sel_trans = udi_cdc_tx_buf_sel[port]; + if (udi_cdc_tx_buf_nb[port][buf_sel_trans] == 0) { + sof_zlp_counter++; + if (((!udd_is_high_speed()) && (sof_zlp_counter < 100)) + || (udd_is_high_speed() && (sof_zlp_counter < 800))) { + cpu_irq_restore(flags); + return; + } + } + sof_zlp_counter = 0; + + if (!udi_cdc_tx_both_buf_to_send[port]) { + // Send current Buffer + // and switch the current buffer + udi_cdc_tx_buf_sel[port] = (buf_sel_trans==0)?1:0; + }else{ + // Send the other Buffer + // and no switch the current buffer + buf_sel_trans = (buf_sel_trans==0)?1:0; + } + udi_cdc_tx_trans_ongoing[port] = true; + cpu_irq_restore(flags); + + b_short_packet = (udi_cdc_tx_buf_nb[port][buf_sel_trans] != UDI_CDC_TX_BUFFERS); + if (b_short_packet) { + if (udd_is_high_speed()) { + udi_cdc_tx_sof_num[port] = udd_get_micro_frame_number(); + }else{ + udi_cdc_tx_sof_num[port] = udd_get_frame_number(); + } + }else{ + udi_cdc_tx_sof_num[port] = 0; // Force next transfer without wait SOF + } + + // Send the buffer with enable of short packet + switch (port) { +#define UDI_CDC_PORT_TO_DATA_EP_IN(index, unused) \ + case index: \ + ep = UDI_CDC_DATA_EP_IN_##index; \ + break; + MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_PORT_TO_DATA_EP_IN, ~) +#undef UDI_CDC_PORT_TO_DATA_EP_IN + default: + ep = UDI_CDC_DATA_EP_IN_0; + break; + } + udd_ep_run( ep, + b_short_packet, + udi_cdc_tx_buf[port][buf_sel_trans], + udi_cdc_tx_buf_nb[port][buf_sel_trans], + udi_cdc_data_sent); +} + + +//--------------------------------------------- +//------- Application interface + + +//------- Application interface + +void udi_cdc_ctrl_signal_dcd(bool b_set) +{ + udi_cdc_ctrl_state_change(0, b_set, CDC_SERIAL_STATE_DCD); +} + +void udi_cdc_ctrl_signal_dsr(bool b_set) +{ + udi_cdc_ctrl_state_change(0, b_set, CDC_SERIAL_STATE_DSR); +} + +void udi_cdc_signal_framing_error(void) +{ + udi_cdc_ctrl_state_change(0, true, CDC_SERIAL_STATE_FRAMING); +} + +void udi_cdc_signal_parity_error(void) +{ + udi_cdc_ctrl_state_change(0, true, CDC_SERIAL_STATE_PARITY); +} + +void udi_cdc_signal_overrun(void) +{ + udi_cdc_ctrl_state_change(0, true, CDC_SERIAL_STATE_OVERRUN); +} + +void udi_cdc_multi_ctrl_signal_dcd(uint8_t port, bool b_set) +{ + udi_cdc_ctrl_state_change(port, b_set, CDC_SERIAL_STATE_DCD); +} + +void udi_cdc_multi_ctrl_signal_dsr(uint8_t port, bool b_set) +{ + udi_cdc_ctrl_state_change(port, b_set, CDC_SERIAL_STATE_DSR); +} + +void udi_cdc_multi_signal_framing_error(uint8_t port) +{ + udi_cdc_ctrl_state_change(port, true, CDC_SERIAL_STATE_FRAMING); +} + +void udi_cdc_multi_signal_parity_error(uint8_t port) +{ + udi_cdc_ctrl_state_change(port, true, CDC_SERIAL_STATE_PARITY); +} + +void udi_cdc_multi_signal_overrun(uint8_t port) +{ + udi_cdc_ctrl_state_change(port, true, CDC_SERIAL_STATE_OVERRUN); +} + +iram_size_t udi_cdc_multi_get_nb_received_data(uint8_t port) +{ + irqflags_t flags; + uint16_t pos; + iram_size_t nb_received; + +#if UDI_CDC_PORT_NB == 1 // To optimize code + port = 0; +#endif + flags = cpu_irq_save(); + pos = udi_cdc_rx_pos[port]; + nb_received = udi_cdc_rx_buf_nb[port][udi_cdc_rx_buf_sel[port]] - pos; + cpu_irq_restore(flags); + return nb_received; +} + +iram_size_t udi_cdc_get_nb_received_data(void) +{ + return udi_cdc_multi_get_nb_received_data(0); +} + +bool udi_cdc_multi_is_rx_ready(uint8_t port) +{ + return (udi_cdc_multi_get_nb_received_data(port) > 0); +} + +bool udi_cdc_is_rx_ready(void) +{ + return udi_cdc_multi_is_rx_ready(0); +} + +int udi_cdc_multi_getc(uint8_t port) +{ + irqflags_t flags; + int rx_data = 0; + bool b_databit_9; + uint16_t pos; + uint8_t buf_sel; + bool again; + +#if UDI_CDC_PORT_NB == 1 // To optimize code + port = 0; +#endif + + b_databit_9 = (9 == udi_cdc_line_coding[port].bDataBits); + +udi_cdc_getc_process_one_byte: + // Check available data + flags = cpu_irq_save(); + pos = udi_cdc_rx_pos[port]; + buf_sel = udi_cdc_rx_buf_sel[port]; + again = pos >= udi_cdc_rx_buf_nb[port][buf_sel]; + cpu_irq_restore(flags); + while (again) { + if (!udi_cdc_data_running) { + return 0; + } + goto udi_cdc_getc_process_one_byte; + } + + // Read data + rx_data |= udi_cdc_rx_buf[port][buf_sel][pos]; + udi_cdc_rx_pos[port] = pos+1; + + udi_cdc_rx_start(port); + + if (b_databit_9) { + // Receive MSB + b_databit_9 = false; + rx_data = rx_data << 8; + goto udi_cdc_getc_process_one_byte; + } + return rx_data; +} + +int udi_cdc_getc(void) +{ + return udi_cdc_multi_getc(0); +} + +iram_size_t udi_cdc_multi_read_buf(uint8_t port, void* buf, iram_size_t size) +{ + irqflags_t flags; + uint8_t *ptr_buf = (uint8_t *)buf; + iram_size_t copy_nb; + uint16_t pos; + uint8_t buf_sel; + bool again; + +#if UDI_CDC_PORT_NB == 1 // To optimize code + port = 0; +#endif + +udi_cdc_read_buf_loop_wait: + // Check available data + flags = cpu_irq_save(); + pos = udi_cdc_rx_pos[port]; + buf_sel = udi_cdc_rx_buf_sel[port]; + again = pos >= udi_cdc_rx_buf_nb[port][buf_sel]; + cpu_irq_restore(flags); + while (again) { + if (!udi_cdc_data_running) { + return size; + } + goto udi_cdc_read_buf_loop_wait; + } + + // Read data + copy_nb = udi_cdc_rx_buf_nb[port][buf_sel] - pos; + if (copy_nb>size) { + copy_nb = size; + } + memcpy(ptr_buf, &udi_cdc_rx_buf[port][buf_sel][pos], copy_nb); + udi_cdc_rx_pos[port] += copy_nb; + ptr_buf += copy_nb; + size -= copy_nb; + udi_cdc_rx_start(port); + + if (size) { + goto udi_cdc_read_buf_loop_wait; + } + return 0; +} + +static iram_size_t udi_cdc_multi_read_no_polling(uint8_t port, void* buf, iram_size_t size) +{ + uint8_t *ptr_buf = (uint8_t *)buf; + iram_size_t nb_avail_data; + uint16_t pos; + uint8_t buf_sel; + irqflags_t flags; + +#if UDI_CDC_PORT_NB == 1 // To optimize code + port = 0; +#endif + + //Data interface not started... exit + if (!udi_cdc_data_running) { + return 0; + } + + //Get number of available data + // Check available data + flags = cpu_irq_save(); // to protect udi_cdc_rx_pos & udi_cdc_rx_buf_sel + pos = udi_cdc_rx_pos[port]; + buf_sel = udi_cdc_rx_buf_sel[port]; + nb_avail_data = udi_cdc_rx_buf_nb[port][buf_sel] - pos; + cpu_irq_restore(flags); + //If the buffer contains less than the requested number of data, + //adjust read size + if(nb_avail_data0) { + memcpy(ptr_buf, &udi_cdc_rx_buf[port][buf_sel][pos], size); + flags = cpu_irq_save(); // to protect udi_cdc_rx_pos + udi_cdc_rx_pos[port] += size; + cpu_irq_restore(flags); + + ptr_buf += size; + udi_cdc_rx_start(port); + } + return(size); +} + +iram_size_t udi_cdc_read_no_polling(void* buf, iram_size_t size) +{ + return udi_cdc_multi_read_no_polling(0, buf, size); +} + +iram_size_t udi_cdc_read_buf(void* buf, iram_size_t size) +{ + return udi_cdc_multi_read_buf(0, buf, size); +} + +iram_size_t udi_cdc_multi_get_free_tx_buffer(uint8_t port) +{ + irqflags_t flags; + iram_size_t buf_sel_nb, retval; + uint8_t buf_sel; + +#if UDI_CDC_PORT_NB == 1 // To optimize code + port = 0; +#endif + + flags = cpu_irq_save(); + buf_sel = udi_cdc_tx_buf_sel[port]; + buf_sel_nb = udi_cdc_tx_buf_nb[port][buf_sel]; + if (buf_sel_nb == UDI_CDC_TX_BUFFERS) { + if ((!udi_cdc_tx_trans_ongoing[port]) + && (!udi_cdc_tx_both_buf_to_send[port])) { + /* One buffer is full, but the other buffer is not used. + * (not used = transfer on-going) + * then move to the other buffer to store data */ + udi_cdc_tx_both_buf_to_send[port] = true; + udi_cdc_tx_buf_sel[port] = (buf_sel == 0)? 1 : 0; + buf_sel_nb = 0; + } + } + retval = UDI_CDC_TX_BUFFERS - buf_sel_nb; + cpu_irq_restore(flags); + return retval; +} + +iram_size_t udi_cdc_get_free_tx_buffer(void) +{ + return udi_cdc_multi_get_free_tx_buffer(0); +} + +bool udi_cdc_multi_is_tx_ready(uint8_t port) +{ + return (udi_cdc_multi_get_free_tx_buffer(port) != 0); +} + +bool udi_cdc_is_tx_ready(void) +{ + return udi_cdc_multi_is_tx_ready(0); +} + +int udi_cdc_multi_putc(uint8_t port, int value) +{ + irqflags_t flags; + bool b_databit_9; + uint8_t buf_sel; + +#if UDI_CDC_PORT_NB == 1 // To optimize code + port = 0; +#endif + + b_databit_9 = (9 == udi_cdc_line_coding[port].bDataBits); + +udi_cdc_putc_process_one_byte: + // Check available space + if (!udi_cdc_multi_is_tx_ready(port)) { + if (!udi_cdc_data_running) { + return false; + } + goto udi_cdc_putc_process_one_byte; + } + + // Write value + flags = cpu_irq_save(); + buf_sel = udi_cdc_tx_buf_sel[port]; + udi_cdc_tx_buf[port][buf_sel][udi_cdc_tx_buf_nb[port][buf_sel]++] = value; + cpu_irq_restore(flags); + + if (b_databit_9) { + // Send MSB + b_databit_9 = false; + value = value >> 8; + goto udi_cdc_putc_process_one_byte; + } + return true; +} + +int udi_cdc_putc(int value) +{ + return udi_cdc_multi_putc(0, value); +} + +iram_size_t udi_cdc_multi_write_buf(uint8_t port, const void* buf, iram_size_t size) +{ + irqflags_t flags; + uint8_t buf_sel; + uint16_t buf_nb; + iram_size_t copy_nb; + uint8_t *ptr_buf = (uint8_t *)buf; +#define WRITE_TIMEOUT 10 + int timeout = WRITE_TIMEOUT; + +#if UDI_CDC_PORT_NB == 1 // To optimize code + port = 0; +#endif + + if (9 == udi_cdc_line_coding[port].bDataBits) { + size *=2; + } + +udi_cdc_write_buf_loop_wait: + // Check available space + if (!udi_cdc_multi_is_tx_ready(port)) { + if (!udi_cdc_data_running) { + return size; + } + if(--timeout == 0) + return size; + +#if USE_FREERTOS + vTaskDelay(1); +#else + time_delay_msec(1); +#endif + + goto udi_cdc_write_buf_loop_wait; + } + + // Write values + flags = cpu_irq_save(); + buf_sel = udi_cdc_tx_buf_sel[port]; + buf_nb = udi_cdc_tx_buf_nb[port][buf_sel]; + copy_nb = UDI_CDC_TX_BUFFERS - buf_nb; + if (copy_nb > size) { + copy_nb = size; + } + memcpy(&udi_cdc_tx_buf[port][buf_sel][buf_nb], ptr_buf, copy_nb); + udi_cdc_tx_buf_nb[port][buf_sel] = buf_nb + copy_nb; + cpu_irq_restore(flags); + + // Update buffer pointer + ptr_buf = ptr_buf + copy_nb; + size -= copy_nb; + + if (size) { + timeout = WRITE_TIMEOUT; + goto udi_cdc_write_buf_loop_wait; + } + + return 0; +} + +iram_size_t udi_cdc_write_buf(const void* buf, iram_size_t size) +{ + return udi_cdc_multi_write_buf(0, buf, size); +} + +//@} diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/usb/class/cdc/device/udi_cdc.h b/hw-libs/drivers/SAMx70/ASF/common/services/usb/class/cdc/device/udi_cdc.h new file mode 100644 index 000000000..a78486be1 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/usb/class/cdc/device/udi_cdc.h @@ -0,0 +1,800 @@ +/** + * \file + * + * \brief USB Device Communication Device Class (CDC) interface definitions. + * + * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _UDI_CDC_H_ +#define _UDI_CDC_H_ + +#include "conf_usb.h" +#include "usb_protocol.h" +#include "usb_protocol_cdc.h" +#include "udd.h" +#include "udc_desc.h" +#include "udi.h" + +// Check the number of port +#ifndef UDI_CDC_PORT_NB +# define UDI_CDC_PORT_NB 1 +#endif +#if (UDI_CDC_PORT_NB < 1) || (UDI_CDC_PORT_NB > 7) +# error UDI_CDC_PORT_NB must be between 1 and 7 +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup udi_cdc_group_udc + * @{ + */ + +//! Global structure which contains standard UDI API for UDC +extern UDC_DESC_STORAGE udi_api_t udi_api_cdc_comm; +extern UDC_DESC_STORAGE udi_api_t udi_api_cdc_data; +//@} + +/** + * \ingroup udi_cdc_group + * \defgroup udi_cdc_group_desc USB interface descriptors + * + * The following structures provide predefined USB interface descriptors. + * It must be used to define the final USB descriptors. + */ +//@{ + +/** + * \brief Communication Class interface descriptor + * + * Interface descriptor with associated functional and endpoint + * descriptors for the CDC Communication Class interface. + */ +typedef struct { + //! Standard interface descriptor + usb_iface_desc_t iface; + //! CDC Header functional descriptor + usb_cdc_hdr_desc_t header; + //! CDC Abstract Control Model functional descriptor + usb_cdc_acm_desc_t acm; + //! CDC Union functional descriptor + usb_cdc_union_desc_t union_desc; + //! CDC Call Management functional descriptor + usb_cdc_call_mgmt_desc_t call_mgmt; + //! Notification endpoint descriptor + usb_ep_desc_t ep_notify; +} udi_cdc_comm_desc_t; + + +/** + * \brief Data Class interface descriptor + * + * Interface descriptor with associated endpoint descriptors for the + * CDC Data Class interface. + */ +typedef struct { + //! Standard interface descriptor + usb_iface_desc_t iface; + //! Data IN/OUT endpoint descriptors + usb_ep_desc_t ep_in; + usb_ep_desc_t ep_out; +} udi_cdc_data_desc_t; + + +//! CDC communication endpoints size for all speeds +#define UDI_CDC_COMM_EP_SIZE 64 +//! CDC data endpoints size for FS speed (8B, 16B, 32B, 64B) +#define UDI_CDC_DATA_EPS_FS_SIZE 64 +//! CDC data endpoints size for HS speed (512B only) +#define UDI_CDC_DATA_EPS_HS_SIZE 512 + +/** + * \name Content of interface descriptors + * Up to 7 CDC interfaces can be implemented on a USB device. + */ +//@{ +//! By default no string associated to these interfaces +#ifndef UDI_CDC_IAD_STRING_ID_0 +#define UDI_CDC_IAD_STRING_ID_0 0 +#endif +#ifndef UDI_CDC_COMM_STRING_ID_0 +#define UDI_CDC_COMM_STRING_ID_0 0 +#endif +#ifndef UDI_CDC_DATA_STRING_ID_0 +#define UDI_CDC_DATA_STRING_ID_0 0 +#endif +#define UDI_CDC_IAD_DESC_0 UDI_CDC_IAD_DESC(0) +#define UDI_CDC_COMM_DESC_0 UDI_CDC_COMM_DESC(0) +#define UDI_CDC_DATA_DESC_0_FS UDI_CDC_DATA_DESC_FS(0) +#define UDI_CDC_DATA_DESC_0_HS UDI_CDC_DATA_DESC_HS(0) + +//! By default no string associated to these interfaces +#ifndef UDI_CDC_IAD_STRING_ID_1 +#define UDI_CDC_IAD_STRING_ID_1 0 +#endif +#ifndef UDI_CDC_COMM_STRING_ID_1 +#define UDI_CDC_COMM_STRING_ID_1 0 +#endif +#ifndef UDI_CDC_DATA_STRING_ID_1 +#define UDI_CDC_DATA_STRING_ID_1 0 +#endif +#define UDI_CDC_IAD_DESC_1 UDI_CDC_IAD_DESC(1) +#define UDI_CDC_COMM_DESC_1 UDI_CDC_COMM_DESC(1) +#define UDI_CDC_DATA_DESC_1_FS UDI_CDC_DATA_DESC_FS(1) +#define UDI_CDC_DATA_DESC_1_HS UDI_CDC_DATA_DESC_HS(1) + +//! By default no string associated to these interfaces +#ifndef UDI_CDC_IAD_STRING_ID_2 +#define UDI_CDC_IAD_STRING_ID_2 0 +#endif +#ifndef UDI_CDC_COMM_STRING_ID_2 +#define UDI_CDC_COMM_STRING_ID_2 0 +#endif +#ifndef UDI_CDC_DATA_STRING_ID_2 +#define UDI_CDC_DATA_STRING_ID_2 0 +#endif +#define UDI_CDC_IAD_DESC_2 UDI_CDC_IAD_DESC(2) +#define UDI_CDC_COMM_DESC_2 UDI_CDC_COMM_DESC(2) +#define UDI_CDC_DATA_DESC_2_FS UDI_CDC_DATA_DESC_FS(2) +#define UDI_CDC_DATA_DESC_2_HS UDI_CDC_DATA_DESC_HS(2) + +//! By default no string associated to these interfaces +#ifndef UDI_CDC_IAD_STRING_ID_3 +#define UDI_CDC_IAD_STRING_ID_3 0 +#endif +#ifndef UDI_CDC_COMM_STRING_ID_3 +#define UDI_CDC_COMM_STRING_ID_3 0 +#endif +#ifndef UDI_CDC_DATA_STRING_ID_3 +#define UDI_CDC_DATA_STRING_ID_3 0 +#endif +#define UDI_CDC_IAD_DESC_3 UDI_CDC_IAD_DESC(3) +#define UDI_CDC_COMM_DESC_3 UDI_CDC_COMM_DESC(3) +#define UDI_CDC_DATA_DESC_3_FS UDI_CDC_DATA_DESC_FS(3) +#define UDI_CDC_DATA_DESC_3_HS UDI_CDC_DATA_DESC_HS(3) + +//! By default no string associated to these interfaces +#ifndef UDI_CDC_IAD_STRING_ID_4 +#define UDI_CDC_IAD_STRING_ID_4 0 +#endif +#ifndef UDI_CDC_COMM_STRING_ID_4 +#define UDI_CDC_COMM_STRING_ID_4 0 +#endif +#ifndef UDI_CDC_DATA_STRING_ID_4 +#define UDI_CDC_DATA_STRING_ID_4 0 +#endif +#define UDI_CDC_IAD_DESC_4 UDI_CDC_IAD_DESC(4) +#define UDI_CDC_COMM_DESC_4 UDI_CDC_COMM_DESC(4) +#define UDI_CDC_DATA_DESC_4_FS UDI_CDC_DATA_DESC_FS(4) +#define UDI_CDC_DATA_DESC_4_HS UDI_CDC_DATA_DESC_HS(4) + +//! By default no string associated to these interfaces +#ifndef UDI_CDC_IAD_STRING_ID_5 +#define UDI_CDC_IAD_STRING_ID_5 0 +#endif +#ifndef UDI_CDC_COMM_STRING_ID_5 +#define UDI_CDC_COMM_STRING_ID_5 0 +#endif +#ifndef UDI_CDC_DATA_STRING_ID_5 +#define UDI_CDC_DATA_STRING_ID_5 0 +#endif +#define UDI_CDC_IAD_DESC_5 UDI_CDC_IAD_DESC(5) +#define UDI_CDC_COMM_DESC_5 UDI_CDC_COMM_DESC(5) +#define UDI_CDC_DATA_DESC_5_FS UDI_CDC_DATA_DESC_FS(5) +#define UDI_CDC_DATA_DESC_5_HS UDI_CDC_DATA_DESC_HS(5) + +//! By default no string associated to these interfaces +#ifndef UDI_CDC_IAD_STRING_ID_6 +#define UDI_CDC_IAD_STRING_ID_6 0 +#endif +#ifndef UDI_CDC_COMM_STRING_ID_6 +#define UDI_CDC_COMM_STRING_ID_6 0 +#endif +#ifndef UDI_CDC_DATA_STRING_ID_6 +#define UDI_CDC_DATA_STRING_ID_6 0 +#endif +#define UDI_CDC_IAD_DESC_6 UDI_CDC_IAD_DESC(6) +#define UDI_CDC_COMM_DESC_6 UDI_CDC_COMM_DESC(6) +#define UDI_CDC_DATA_DESC_6_FS UDI_CDC_DATA_DESC_FS(6) +#define UDI_CDC_DATA_DESC_6_HS UDI_CDC_DATA_DESC_HS(6) +//@} + + +//! Content of CDC IAD interface descriptor for all speeds +#define UDI_CDC_IAD_DESC(port) { \ + .bLength = sizeof(usb_iad_desc_t),\ + .bDescriptorType = USB_DT_IAD,\ + .bInterfaceCount = 2,\ + .bFunctionClass = CDC_CLASS_COMM,\ + .bFunctionSubClass = CDC_SUBCLASS_ACM,\ + .bFunctionProtocol = CDC_PROTOCOL_V25TER,\ + .bFirstInterface = UDI_CDC_COMM_IFACE_NUMBER_##port,\ + .iFunction = UDI_CDC_IAD_STRING_ID_##port,\ + } + +//! Content of CDC COMM interface descriptor for all speeds +#define UDI_CDC_COMM_DESC(port) { \ + .iface.bLength = sizeof(usb_iface_desc_t),\ + .iface.bDescriptorType = USB_DT_INTERFACE,\ + .iface.bAlternateSetting = 0,\ + .iface.bNumEndpoints = 1,\ + .iface.bInterfaceClass = CDC_CLASS_COMM,\ + .iface.bInterfaceSubClass = CDC_SUBCLASS_ACM,\ + .iface.bInterfaceProtocol = CDC_PROTOCOL_V25TER,\ + .header.bFunctionLength = sizeof(usb_cdc_hdr_desc_t),\ + .header.bDescriptorType = CDC_CS_INTERFACE,\ + .header.bDescriptorSubtype = CDC_SCS_HEADER,\ + .header.bcdCDC = LE16(0x0110),\ + .call_mgmt.bFunctionLength = sizeof(usb_cdc_call_mgmt_desc_t),\ + .call_mgmt.bDescriptorType = CDC_CS_INTERFACE,\ + .call_mgmt.bDescriptorSubtype = CDC_SCS_CALL_MGMT,\ + .call_mgmt.bmCapabilities = \ + CDC_CALL_MGMT_SUPPORTED | CDC_CALL_MGMT_OVER_DCI,\ + .acm.bFunctionLength = sizeof(usb_cdc_acm_desc_t),\ + .acm.bDescriptorType = CDC_CS_INTERFACE,\ + .acm.bDescriptorSubtype = CDC_SCS_ACM,\ + .acm.bmCapabilities = CDC_ACM_SUPPORT_LINE_REQUESTS,\ + .union_desc.bFunctionLength = sizeof(usb_cdc_union_desc_t),\ + .union_desc.bDescriptorType = CDC_CS_INTERFACE,\ + .union_desc.bDescriptorSubtype= CDC_SCS_UNION,\ + .ep_notify.bLength = sizeof(usb_ep_desc_t),\ + .ep_notify.bDescriptorType = USB_DT_ENDPOINT,\ + .ep_notify.bmAttributes = USB_EP_TYPE_INTERRUPT,\ + .ep_notify.wMaxPacketSize = LE16(UDI_CDC_COMM_EP_SIZE),\ + .ep_notify.bInterval = 0x10,\ + .ep_notify.bEndpointAddress = UDI_CDC_COMM_EP_##port,\ + .iface.bInterfaceNumber = UDI_CDC_COMM_IFACE_NUMBER_##port,\ + .call_mgmt.bDataInterface = UDI_CDC_DATA_IFACE_NUMBER_##port,\ + .union_desc.bMasterInterface = UDI_CDC_COMM_IFACE_NUMBER_##port,\ + .union_desc.bSlaveInterface0 = UDI_CDC_DATA_IFACE_NUMBER_##port,\ + .iface.iInterface = UDI_CDC_COMM_STRING_ID_##port,\ + } + +//! Content of CDC DATA interface descriptors +#define UDI_CDC_DATA_DESC_COMMON \ + .iface.bLength = sizeof(usb_iface_desc_t),\ + .iface.bDescriptorType = USB_DT_INTERFACE,\ + .iface.bAlternateSetting = 0,\ + .iface.bNumEndpoints = 2,\ + .iface.bInterfaceClass = CDC_CLASS_DATA,\ + .iface.bInterfaceSubClass = 0,\ + .iface.bInterfaceProtocol = 0,\ + .ep_in.bLength = sizeof(usb_ep_desc_t),\ + .ep_in.bDescriptorType = USB_DT_ENDPOINT,\ + .ep_in.bmAttributes = USB_EP_TYPE_BULK,\ + .ep_in.bInterval = 0,\ + .ep_out.bLength = sizeof(usb_ep_desc_t),\ + .ep_out.bDescriptorType = USB_DT_ENDPOINT,\ + .ep_out.bmAttributes = USB_EP_TYPE_BULK,\ + .ep_out.bInterval = 0, + +#define UDI_CDC_DATA_DESC_FS(port) { \ + UDI_CDC_DATA_DESC_COMMON \ + .ep_in.wMaxPacketSize = LE16(UDI_CDC_DATA_EPS_FS_SIZE),\ + .ep_out.wMaxPacketSize = LE16(UDI_CDC_DATA_EPS_FS_SIZE),\ + .ep_in.bEndpointAddress = UDI_CDC_DATA_EP_IN_##port,\ + .ep_out.bEndpointAddress = UDI_CDC_DATA_EP_OUT_##port,\ + .iface.bInterfaceNumber = UDI_CDC_DATA_IFACE_NUMBER_##port,\ + .iface.iInterface = UDI_CDC_DATA_STRING_ID_##port,\ + } + +#define UDI_CDC_DATA_DESC_HS(port) { \ + UDI_CDC_DATA_DESC_COMMON \ + .ep_in.wMaxPacketSize = LE16(UDI_CDC_DATA_EPS_HS_SIZE),\ + .ep_out.wMaxPacketSize = LE16(UDI_CDC_DATA_EPS_HS_SIZE),\ + .ep_in.bEndpointAddress = UDI_CDC_DATA_EP_IN_##port,\ + .ep_out.bEndpointAddress = UDI_CDC_DATA_EP_OUT_##port,\ + .iface.bInterfaceNumber = UDI_CDC_DATA_IFACE_NUMBER_##port,\ + .iface.iInterface = UDI_CDC_DATA_STRING_ID_##port,\ + } + +//@} + +/** + * \ingroup udi_group + * \defgroup udi_cdc_group USB Device Interface (UDI) for Communication Class Device (CDC) + * + * Common APIs used by high level application to use this USB class. + * + * These routines are used to transfer and control data + * to/from USB CDC endpoint. + * + * See \ref udi_cdc_quickstart. + * @{ + */ + +/** + * \name Interface for application with single CDC interface support + */ +//@{ + +/** + * \brief Notify a state change of DCD signal + * + * \param b_set DCD is enabled if true, else disabled + */ +void udi_cdc_ctrl_signal_dcd(bool b_set); + +/** + * \brief Notify a state change of DSR signal + * + * \param b_set DSR is enabled if true, else disabled + */ +void udi_cdc_ctrl_signal_dsr(bool b_set); + +/** + * \brief Notify a framing error + */ +void udi_cdc_signal_framing_error(void); + +/** + * \brief Notify a parity error + */ +void udi_cdc_signal_parity_error(void); + +/** + * \brief Notify a overrun + */ +void udi_cdc_signal_overrun(void); + +/** + * \brief Gets the number of byte received + * + * \return the number of data available + */ +iram_size_t udi_cdc_get_nb_received_data(void); + +/** + * \brief This function checks if a character has been received on the CDC line + * + * \return \c 1 if a byte is ready to be read. + */ +bool udi_cdc_is_rx_ready(void); + +/** + * \brief Waits and gets a value on CDC line + * + * \return value read on CDC line + */ +int udi_cdc_getc(void); + +/** + * \brief Reads a RAM buffer on CDC line + * + * \param buf Values read + * \param size Number of value read + * + * \return the number of data remaining + */ +iram_size_t udi_cdc_read_buf(void* buf, iram_size_t size); + +/** + * \brief Non polling reads of a up to 'size' data from CDC line + * + * \param port Communication port number to manage + * \param buf Buffer where to store read data + * \param size Maximum number of data to read (size of buffer) + * + * \return the number of data effectively read + */ +iram_size_t udi_cdc_read_no_polling(void* buf, iram_size_t size); + +/** + * \brief Gets the number of free byte in TX buffer + * + * \return the number of free byte in TX buffer + */ +iram_size_t udi_cdc_get_free_tx_buffer(void); + +/** + * \brief This function checks if a new character sent is possible + * The type int is used to support scanf redirection from compiler LIB. + * + * \return \c 1 if a new character can be sent + */ +bool udi_cdc_is_tx_ready(void); + +/** + * \brief Puts a byte on CDC line + * The type int is used to support printf redirection from compiler LIB. + * + * \param value Value to put + * + * \return \c 1 if function was successfully done, otherwise \c 0. + */ +int udi_cdc_putc(int value); + +/** + * \brief Writes a RAM buffer on CDC line + * + * \param buf Values to write + * \param size Number of value to write + * + * \return the number of data remaining + */ +iram_size_t udi_cdc_write_buf(const void* buf, iram_size_t size); +//@} + +/** + * \name Interface for application with multi CDC interfaces support + */ +//@{ + +/** + * \brief Notify a state change of DCD signal + * + * \param port Communication port number to manage + * \param b_set DCD is enabled if true, else disabled + */ +void udi_cdc_multi_ctrl_signal_dcd(uint8_t port, bool b_set); + +/** + * \brief Notify a state change of DSR signal + * + * \param port Communication port number to manage + * \param b_set DSR is enabled if true, else disabled + */ +void udi_cdc_multi_ctrl_signal_dsr(uint8_t port, bool b_set); + +/** + * \brief Notify a framing error + * + * \param port Communication port number to manage + */ +void udi_cdc_multi_signal_framing_error(uint8_t port); + +/** + * \brief Notify a parity error + * + * \param port Communication port number to manage + */ +void udi_cdc_multi_signal_parity_error(uint8_t port); + +/** + * \brief Notify a overrun + * + * \param port Communication port number to manage + */ +void udi_cdc_multi_signal_overrun(uint8_t port); + +/** + * \brief Gets the number of byte received + * + * \param port Communication port number to manage + * + * \return the number of data available + */ +iram_size_t udi_cdc_multi_get_nb_received_data(uint8_t port); + +/** + * \brief This function checks if a character has been received on the CDC line + * + * \param port Communication port number to manage + * + * \return \c 1 if a byte is ready to be read. + */ +bool udi_cdc_multi_is_rx_ready(uint8_t port); + +/** + * \brief Waits and gets a value on CDC line + * + * \param port Communication port number to manage + * + * \return value read on CDC line + */ +int udi_cdc_multi_getc(uint8_t port); + +/** + * \brief Reads a RAM buffer on CDC line + * + * \param port Communication port number to manage + * \param buf Values read + * \param size Number of values read + * + * \return the number of data remaining + */ +iram_size_t udi_cdc_multi_read_buf(uint8_t port, void* buf, iram_size_t size); + +/** + * \brief Gets the number of free byte in TX buffer + * + * \param port Communication port number to manage + * + * \return the number of free byte in TX buffer + */ +iram_size_t udi_cdc_multi_get_free_tx_buffer(uint8_t port); + +/** + * \brief This function checks if a new character sent is possible + * The type int is used to support scanf redirection from compiler LIB. + * + * \param port Communication port number to manage + * + * \return \c 1 if a new character can be sent + */ +bool udi_cdc_multi_is_tx_ready(uint8_t port); + +/** + * \brief Puts a byte on CDC line + * The type int is used to support printf redirection from compiler LIB. + * + * \param port Communication port number to manage + * \param value Value to put + * + * \return \c 1 if function was successfully done, otherwise \c 0. + */ +int udi_cdc_multi_putc(uint8_t port, int value); + +/** + * \brief Writes a RAM buffer on CDC line + * + * \param port Communication port number to manage + * \param buf Values to write + * \param size Number of value to write + * + * \return the number of data remaining + */ +iram_size_t udi_cdc_multi_write_buf(uint8_t port, const void* buf, iram_size_t size); +//@} + +//@} + +/** + * \page udi_cdc_quickstart Quick start guide for USB device Communication Class Device module (UDI CDC) + * + * This is the quick start guide for the \ref udi_cdc_group + * "USB device interface CDC module (UDI CDC)" with step-by-step instructions on + * how to configure and use the modules in a selection of use cases. + * + * The use cases contain several code fragments. The code fragments in the + * steps for setup can be copied into a custom initialization function, while + * the steps for usage can be copied into, e.g., the main application function. + * + * \section udi_cdc_basic_use_case Basic use case + * In this basic use case, the "USB CDC (Single Interface Device)" module is used + * with only one communication port. + * The "USB CDC (Composite Device)" module usage is described in \ref udi_cdc_use_cases + * "Advanced use cases". + * + * \section udi_cdc_basic_use_case_setup Setup steps + * \subsection udi_cdc_basic_use_case_setup_prereq Prerequisites + * \copydetails udc_basic_use_case_setup_prereq + * \subsection udi_cdc_basic_use_case_setup_code Example code + * \copydetails udc_basic_use_case_setup_code + * \subsection udi_cdc_basic_use_case_setup_flow Workflow + * \copydetails udc_basic_use_case_setup_flow + * + * \section udi_cdc_basic_use_case_usage Usage steps + * + * \subsection udi_cdc_basic_use_case_usage_code Example code + * Content of conf_usb.h: + * \code + #define UDI_CDC_ENABLE_EXT(port) my_callback_cdc_enable() + extern bool my_callback_cdc_enable(void); + #define UDI_CDC_DISABLE_EXT(port) my_callback_cdc_disable() + extern void my_callback_cdc_disable(void); + #define UDI_CDC_LOW_RATE + + #define UDI_CDC_DEFAULT_RATE 115200 + #define UDI_CDC_DEFAULT_STOPBITS CDC_STOP_BITS_1 + #define UDI_CDC_DEFAULT_PARITY CDC_PAR_NONE + #define UDI_CDC_DEFAULT_DATABITS 8 + + #include "udi_cdc_conf.h" // At the end of conf_usb.h file +\endcode + * + * Add to application C-file: + * \code + static bool my_flag_autorize_cdc_transfert = false; + bool my_callback_cdc_enable(void) + { + my_flag_autorize_cdc_transfert = true; + return true; + } + void my_callback_cdc_disable(void) + { + my_flag_autorize_cdc_transfert = false; + } + + void task(void) + { + if (my_flag_autorize_cdc_transfert) { + udi_cdc_putc('A'); + udi_cdc_getc(); + } + } +\endcode + * + * \subsection udi_cdc_basic_use_case_setup_flow Workflow + * -# Ensure that conf_usb.h is available and contains the following configuration, + * which is the USB device CDC configuration: + * - \code #define USB_DEVICE_SERIAL_NAME "12...EF" // Disk SN for CDC \endcode + * \note The USB serial number is mandatory when a CDC interface is used. + * - \code #define UDI_CDC_ENABLE_EXT(port) my_callback_cdc_enable() + extern bool my_callback_cdc_enable(void); \endcode + * \note After the device enumeration (detecting and identifying USB devices), + * the USB host starts the device configuration. When the USB CDC interface + * from the device is accepted by the host, the USB host enables this interface and the + * UDI_CDC_ENABLE_EXT() callback function is called and return true. + * Thus, when this event is received, the data transfer on CDC interface are authorized. + * - \code #define UDI_CDC_DISABLE_EXT(port) my_callback_cdc_disable() + extern void my_callback_cdc_disable(void); \endcode + * \note When the USB device is unplugged or is reset by the USB host, the USB + * interface is disabled and the UDI_CDC_DISABLE_EXT() callback function + * is called. Thus, the data transfer must be stopped on CDC interface. + * - \code #define UDI_CDC_LOW_RATE \endcode + * \note Define it when the transfer CDC Device to Host is a low rate + * (<512000 bauds) to reduce CDC buffers size. + * - \code #define UDI_CDC_DEFAULT_RATE 115200 + #define UDI_CDC_DEFAULT_STOPBITS CDC_STOP_BITS_1 + #define UDI_CDC_DEFAULT_PARITY CDC_PAR_NONE + #define UDI_CDC_DEFAULT_DATABITS 8 \endcode + * \note Default configuration of communication port at startup. + * -# Send or wait data on CDC line: + * - \code // Waits and gets a value on CDC line + int udi_cdc_getc(void); + // Reads a RAM buffer on CDC line + iram_size_t udi_cdc_read_buf(int* buf, iram_size_t size); + // Puts a byte on CDC line + int udi_cdc_putc(int value); + // Writes a RAM buffer on CDC line + iram_size_t udi_cdc_write_buf(const int* buf, iram_size_t size); \endcode + * + * \section udi_cdc_use_cases Advanced use cases + * For more advanced use of the UDI CDC module, see the following use cases: + * - \subpage udi_cdc_use_case_composite + * - \subpage udc_use_case_1 + * - \subpage udc_use_case_2 + * - \subpage udc_use_case_3 + * - \subpage udc_use_case_4 + * - \subpage udc_use_case_5 + * - \subpage udc_use_case_6 + */ + +/** + * \page udi_cdc_use_case_composite CDC in a composite device + * + * A USB Composite Device is a USB Device which uses more than one USB class. + * In this use case, the "USB CDC (Composite Device)" module is used to + * create a USB composite device. Thus, this USB module can be associated with + * another "Composite Device" module, like "USB HID Mouse (Composite Device)". + * + * Also, you can refer to application note + * + * AVR4902 ASF - USB Composite Device. + * + * \section udi_cdc_use_case_composite_setup Setup steps + * For the setup code of this use case to work, the + * \ref udi_cdc_basic_use_case "basic use case" must be followed. + * + * \section udi_cdc_use_case_composite_usage Usage steps + * + * \subsection udi_cdc_use_case_composite_usage_code Example code + * Content of conf_usb.h: + * \code + #define USB_DEVICE_EP_CTRL_SIZE 64 + #define USB_DEVICE_NB_INTERFACE (X+2) + #define USB_DEVICE_MAX_EP (X+3) + + #define UDI_CDC_DATA_EP_IN_0 (1 | USB_EP_DIR_IN) // TX + #define UDI_CDC_DATA_EP_OUT_0 (2 | USB_EP_DIR_OUT) // RX + #define UDI_CDC_COMM_EP_0 (3 | USB_EP_DIR_IN) // Notify endpoint + #define UDI_CDC_COMM_IFACE_NUMBER_0 X+0 + #define UDI_CDC_DATA_IFACE_NUMBER_0 X+1 + + #define UDI_COMPOSITE_DESC_T \ + usb_iad_desc_t udi_cdc_iad; \ + udi_cdc_comm_desc_t udi_cdc_comm; \ + udi_cdc_data_desc_t udi_cdc_data; \ + ... + #define UDI_COMPOSITE_DESC_FS \ + .udi_cdc_iad = UDI_CDC_IAD_DESC_0, \ + .udi_cdc_comm = UDI_CDC_COMM_DESC_0, \ + .udi_cdc_data = UDI_CDC_DATA_DESC_0_FS, \ + ... + #define UDI_COMPOSITE_DESC_HS \ + .udi_cdc_iad = UDI_CDC_IAD_DESC_0, \ + .udi_cdc_comm = UDI_CDC_COMM_DESC_0, \ + .udi_cdc_data = UDI_CDC_DATA_DESC_0_HS, \ + ... + #define UDI_COMPOSITE_API \ + &udi_api_cdc_comm, \ + &udi_api_cdc_data, \ + ... +\endcode + * + * \subsection udi_cdc_use_case_composite_usage_flow Workflow + * -# Ensure that conf_usb.h is available and contains the following parameters + * required for a USB composite device configuration: + * - \code // Endpoint control size, This must be: + // - 8, 16, 32 or 64 for full speed device (8 is recommended to save RAM) + // - 64 for a high speed device + #define USB_DEVICE_EP_CTRL_SIZE 64 + // Total Number of interfaces on this USB device. + // Add 2 for CDC. + #define USB_DEVICE_NB_INTERFACE (X+2) + // Total number of endpoints on this USB device. + // This must include each endpoint for each interface. + // Add 3 for CDC. + #define USB_DEVICE_MAX_EP (X+3) \endcode + * -# Ensure that conf_usb.h contains the description of + * composite device: + * - \code // The endpoint numbers chosen by you for the CDC. + // The endpoint numbers starting from 1. + #define UDI_CDC_DATA_EP_IN_0 (1 | USB_EP_DIR_IN) // TX + #define UDI_CDC_DATA_EP_OUT_0 (2 | USB_EP_DIR_OUT) // RX + #define UDI_CDC_COMM_EP_0 (3 | USB_EP_DIR_IN) // Notify endpoint + // The interface index of an interface starting from 0 + #define UDI_CDC_COMM_IFACE_NUMBER_0 X+0 + #define UDI_CDC_DATA_IFACE_NUMBER_0 X+1 \endcode + * -# Ensure that conf_usb.h contains the following parameters + * required for a USB composite device configuration: + * - \code // USB Interfaces descriptor structure + #define UDI_COMPOSITE_DESC_T \ + ... + usb_iad_desc_t udi_cdc_iad; \ + udi_cdc_comm_desc_t udi_cdc_comm; \ + udi_cdc_data_desc_t udi_cdc_data; \ + ... + // USB Interfaces descriptor value for Full Speed + #define UDI_COMPOSITE_DESC_FS \ + ... + .udi_cdc_iad = UDI_CDC_IAD_DESC_0, \ + .udi_cdc_comm = UDI_CDC_COMM_DESC_0, \ + .udi_cdc_data = UDI_CDC_DATA_DESC_0_FS, \ + ... + // USB Interfaces descriptor value for High Speed + #define UDI_COMPOSITE_DESC_HS \ + ... + .udi_cdc_iad = UDI_CDC_IAD_DESC_0, \ + .udi_cdc_comm = UDI_CDC_COMM_DESC_0, \ + .udi_cdc_data = UDI_CDC_DATA_DESC_0_HS, \ + ... + // USB Interface APIs + #define UDI_COMPOSITE_API \ + ... + &udi_api_cdc_comm, \ + &udi_api_cdc_data, \ + ... \endcode + * - \note The descriptors order given in the four lists above must be the + * same as the order defined by all interface indexes. The interface index + * orders are defined through UDI_X_IFACE_NUMBER defines.\n + * Also, the CDC requires a USB Interface Association Descriptor (IAD) for + * composite device. + */ + +#ifdef __cplusplus +} +#endif +#endif // _UDI_CDC_H_ diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/usb/class/cdc/device/udi_cdc_conf.h b/hw-libs/drivers/SAMx70/ASF/common/services/usb/class/cdc/device/udi_cdc_conf.h new file mode 100644 index 000000000..eda267e82 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/usb/class/cdc/device/udi_cdc_conf.h @@ -0,0 +1,146 @@ +/** + * \file + * + * \brief Default CDC configuration for a USB Device with a single interface + * + * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _UDI_CDC_CONF_H_ +#define _UDI_CDC_CONF_H_ + +#include "usb_protocol_cdc.h" +#include "conf_usb.h" + +#ifndef UDI_CDC_PORT_NB +# define UDI_CDC_PORT_NB 1 +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup udi_cdc_group_single_desc + * @{ + */ + +//! Control endpoint size (Endpoint 0) +#define USB_DEVICE_EP_CTRL_SIZE 64 + +#if XMEGA +/** + * \name Endpoint configuration on XMEGA + * The XMEGA supports a IN and OUT endpoint with the same number endpoint, + * thus XMEGA can support up to 7 CDC interfaces. + */ +//@{ +#define UDI_CDC_DATA_EP_IN_0 ( 1 | USB_EP_DIR_IN) // TX +#define UDI_CDC_DATA_EP_OUT_0 ( 2 | USB_EP_DIR_OUT) // RX +#define UDI_CDC_COMM_EP_0 ( 2 | USB_EP_DIR_IN) // Notify endpoint +#define UDI_CDC_DATA_EP_IN_1 ( 3 | USB_EP_DIR_IN) // TX +#define UDI_CDC_DATA_EP_OUT_1 ( 4 | USB_EP_DIR_OUT) // RX +#define UDI_CDC_COMM_EP_1 ( 4 | USB_EP_DIR_IN) // Notify endpoint +#define UDI_CDC_DATA_EP_IN_2 ( 5 | USB_EP_DIR_IN) // TX +#define UDI_CDC_DATA_EP_OUT_2 ( 6 | USB_EP_DIR_OUT) // RX +#define UDI_CDC_COMM_EP_2 ( 6 | USB_EP_DIR_IN) // Notify endpoint +#define UDI_CDC_DATA_EP_IN_3 ( 7 | USB_EP_DIR_IN) // TX +#define UDI_CDC_DATA_EP_OUT_3 ( 8 | USB_EP_DIR_OUT) // RX +#define UDI_CDC_COMM_EP_3 ( 8 | USB_EP_DIR_IN) // Notify endpoint +#define UDI_CDC_DATA_EP_IN_4 ( 9 | USB_EP_DIR_IN) // TX +#define UDI_CDC_DATA_EP_OUT_4 (10 | USB_EP_DIR_OUT) // RX +#define UDI_CDC_COMM_EP_4 (10 | USB_EP_DIR_IN) // Notify endpoint +#define UDI_CDC_DATA_EP_IN_5 (11 | USB_EP_DIR_IN) // TX +#define UDI_CDC_DATA_EP_OUT_5 (12 | USB_EP_DIR_OUT) // RX +#define UDI_CDC_COMM_EP_5 (12 | USB_EP_DIR_IN) // Notify endpoint +#define UDI_CDC_DATA_EP_IN_6 (13 | USB_EP_DIR_IN) // TX +#define UDI_CDC_DATA_EP_OUT_6 (14 | USB_EP_DIR_OUT) // RX +#define UDI_CDC_COMM_EP_6 (14 | USB_EP_DIR_IN) // Notify endpoint +//! 2 endpoints numbers used per CDC interface +#define USB_DEVICE_MAX_EP (2*UDI_CDC_PORT_NB) +//@} + +#else + +/** + * \name Default endpoint configuration + * The USBB, UDP, UDPHS and UOTGHS interfaces can support up to 2 CDC interfaces. + */ +//@{ +# if UDI_CDC_PORT_NB > 2 +# error USBB, UDP, UDPHS and UOTGHS interfaces have not enought endpoints. +# endif +#define UDI_CDC_DATA_EP_IN_0 (1 | USB_EP_DIR_IN) // TX +#define UDI_CDC_DATA_EP_OUT_0 (2 | USB_EP_DIR_OUT) // RX +#define UDI_CDC_COMM_EP_0 (3 | USB_EP_DIR_IN) // Notify endpoint +# if SAM3U + /* For 3U max endpoint size of 4 is 64, use 5 and 6 as bulk tx and rx */ +# define UDI_CDC_DATA_EP_IN_1 (6 | USB_EP_DIR_IN) // TX +# define UDI_CDC_DATA_EP_OUT_1 (5 | USB_EP_DIR_OUT) // RX +# define UDI_CDC_COMM_EP_1 (4 | USB_EP_DIR_IN) // Notify +# else +# define UDI_CDC_DATA_EP_IN_1 (4 | USB_EP_DIR_IN) // TX +# define UDI_CDC_DATA_EP_OUT_1 (5 | USB_EP_DIR_OUT) // RX +# define UDI_CDC_COMM_EP_1 (6 | USB_EP_DIR_IN) // Notify +# endif +//! 3 endpoints used per CDC interface +#undef USB_DEVICE_MAX_EP // undefine this definition in header file +#define USB_DEVICE_MAX_EP (3*UDI_CDC_PORT_NB) +//@} + +#endif + +/** + * \name Default Interface numbers + */ +//@{ +#define UDI_CDC_COMM_IFACE_NUMBER_0 0 +#define UDI_CDC_DATA_IFACE_NUMBER_0 1 +#define UDI_CDC_COMM_IFACE_NUMBER_1 2 +#define UDI_CDC_DATA_IFACE_NUMBER_1 3 +#define UDI_CDC_COMM_IFACE_NUMBER_2 4 +#define UDI_CDC_DATA_IFACE_NUMBER_2 5 +#define UDI_CDC_COMM_IFACE_NUMBER_3 6 +#define UDI_CDC_DATA_IFACE_NUMBER_3 7 +#define UDI_CDC_COMM_IFACE_NUMBER_4 8 +#define UDI_CDC_DATA_IFACE_NUMBER_4 9 +#define UDI_CDC_COMM_IFACE_NUMBER_5 10 +#define UDI_CDC_DATA_IFACE_NUMBER_5 11 +#define UDI_CDC_COMM_IFACE_NUMBER_6 12 +#define UDI_CDC_DATA_IFACE_NUMBER_6 13 +//@} + +//@} + +#ifdef __cplusplus +} +#endif +#endif // _UDI_CDC_CONF_H_ diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/usb/class/cdc/device/udi_cdc_desc.c b/hw-libs/drivers/SAMx70/ASF/common/services/usb/class/cdc/device/udi_cdc_desc.c new file mode 100644 index 000000000..09ad637e8 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/usb/class/cdc/device/udi_cdc_desc.c @@ -0,0 +1,244 @@ +/** + * \file + * + * \brief Default descriptors for a USB Device with a single interface CDC + * + * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "conf_usb.h" +#include "udd.h" +#include "udc_desc.h" +#include "udi_cdc.h" + + +/** + * \defgroup udi_cdc_group_single_desc USB device descriptors for a single interface + * + * The following structures provide the USB device descriptors required for + * USB Device with a single interface CDC. + * + * It is ready to use and do not require more definition. + * + * @{ + */ + +//! Two interfaces for a CDC device +#define USB_DEVICE_NB_INTERFACE (2*UDI_CDC_PORT_NB) + +#ifdef USB_DEVICE_LPM_SUPPORT +# define USB_VERSION USB_V2_1 +#else +# define USB_VERSION USB_V2_0 +#endif + +//! USB Device Descriptor +COMPILER_WORD_ALIGNED +UDC_DESC_STORAGE usb_dev_desc_t udc_device_desc = { + .bLength = sizeof(usb_dev_desc_t), + .bDescriptorType = USB_DT_DEVICE, + .bcdUSB = LE16(USB_VERSION), +#if UDI_CDC_PORT_NB > 1 + .bDeviceClass = 0, +#else + .bDeviceClass = CDC_CLASS_DEVICE, +#endif + .bDeviceSubClass = 0, + .bDeviceProtocol = 0, + .bMaxPacketSize0 = USB_DEVICE_EP_CTRL_SIZE, + .idVendor = LE16(USB_DEVICE_VENDOR_ID), + .idProduct = LE16(USB_DEVICE_PRODUCT_ID), + .bcdDevice = LE16((USB_DEVICE_MAJOR_VERSION << 8) + | USB_DEVICE_MINOR_VERSION), +#ifdef USB_DEVICE_MANUFACTURE_NAME + .iManufacturer = 1, +#else + .iManufacturer = 0, // No manufacture string +#endif +#ifdef USB_DEVICE_PRODUCT_NAME + .iProduct = 2, +#else + .iProduct = 0, // No product string +#endif +#if (defined USB_DEVICE_SERIAL_NAME || defined USB_DEVICE_GET_SERIAL_NAME_POINTER) + .iSerialNumber = 3, +#else + .iSerialNumber = 0, // No serial string +#endif + .bNumConfigurations = 1 +}; + + +#ifdef USB_DEVICE_HS_SUPPORT +//! USB Device Qualifier Descriptor for HS +COMPILER_WORD_ALIGNED +UDC_DESC_STORAGE usb_dev_qual_desc_t udc_device_qual = { + .bLength = sizeof(usb_dev_qual_desc_t), + .bDescriptorType = USB_DT_DEVICE_QUALIFIER, + .bcdUSB = LE16(USB_VERSION), +#if UDI_CDC_PORT_NB > 1 + .bDeviceClass = 0, +#else + .bDeviceClass = CDC_CLASS_DEVICE, +#endif + .bDeviceSubClass = 0, + .bDeviceProtocol = 0, + .bMaxPacketSize0 = USB_DEVICE_EP_CTRL_SIZE, + .bNumConfigurations = 1 +}; +#endif + +#ifdef USB_DEVICE_LPM_SUPPORT +//! USB Device Qualifier Descriptor +COMPILER_WORD_ALIGNED +UDC_DESC_STORAGE usb_dev_lpm_desc_t udc_device_lpm = { + .bos.bLength = sizeof(usb_dev_bos_desc_t), + .bos.bDescriptorType = USB_DT_BOS, + .bos.wTotalLength = LE16(sizeof(usb_dev_bos_desc_t) + sizeof(usb_dev_capa_ext_desc_t)), + .bos.bNumDeviceCaps = 1, + .capa_ext.bLength = sizeof(usb_dev_capa_ext_desc_t), + .capa_ext.bDescriptorType = USB_DT_DEVICE_CAPABILITY, + .capa_ext.bDevCapabilityType = USB_DC_USB20_EXTENSION, + .capa_ext.bmAttributes = USB_DC_EXT_LPM, +}; +#endif + +//! Structure for USB Device Configuration Descriptor +COMPILER_PACK_SET(1) +typedef struct { + usb_conf_desc_t conf; +#if UDI_CDC_PORT_NB == 1 + udi_cdc_comm_desc_t udi_cdc_comm_0; + udi_cdc_data_desc_t udi_cdc_data_0; +#else +# define UDI_CDC_DESC_STRUCTURE(index, unused) \ + usb_iad_desc_t udi_cdc_iad_##index; \ + udi_cdc_comm_desc_t udi_cdc_comm_##index; \ + udi_cdc_data_desc_t udi_cdc_data_##index; + MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_DESC_STRUCTURE, ~) +# undef UDI_CDC_DESC_STRUCTURE +#endif +} udc_desc_t; +COMPILER_PACK_RESET() + +//! USB Device Configuration Descriptor filled for full and high speed +COMPILER_WORD_ALIGNED +UDC_DESC_STORAGE udc_desc_t udc_desc_fs = { + .conf.bLength = sizeof(usb_conf_desc_t), + .conf.bDescriptorType = USB_DT_CONFIGURATION, + .conf.wTotalLength = LE16(sizeof(udc_desc_t)), + .conf.bNumInterfaces = USB_DEVICE_NB_INTERFACE, + .conf.bConfigurationValue = 1, + .conf.iConfiguration = 0, + .conf.bmAttributes = USB_CONFIG_ATTR_MUST_SET | USB_DEVICE_ATTR, + .conf.bMaxPower = USB_CONFIG_MAX_POWER(USB_DEVICE_POWER), +#if UDI_CDC_PORT_NB == 1 + .udi_cdc_comm_0 = UDI_CDC_COMM_DESC_0, + .udi_cdc_data_0 = UDI_CDC_DATA_DESC_0_FS, +#else +# define UDI_CDC_DESC_FS(index, unused) \ + .udi_cdc_iad_##index = UDI_CDC_IAD_DESC_##index,\ + .udi_cdc_comm_##index = UDI_CDC_COMM_DESC_##index,\ + .udi_cdc_data_##index = UDI_CDC_DATA_DESC_##index##_FS, + MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_DESC_FS, ~) +# undef UDI_CDC_DESC_FS +#endif +}; + +#ifdef USB_DEVICE_HS_SUPPORT +COMPILER_WORD_ALIGNED +UDC_DESC_STORAGE udc_desc_t udc_desc_hs = { + .conf.bLength = sizeof(usb_conf_desc_t), + .conf.bDescriptorType = USB_DT_CONFIGURATION, + .conf.wTotalLength = LE16(sizeof(udc_desc_t)), + .conf.bNumInterfaces = USB_DEVICE_NB_INTERFACE, + .conf.bConfigurationValue = 1, + .conf.iConfiguration = 0, + .conf.bmAttributes = USB_CONFIG_ATTR_MUST_SET | USB_DEVICE_ATTR, + .conf.bMaxPower = USB_CONFIG_MAX_POWER(USB_DEVICE_POWER), +#if UDI_CDC_PORT_NB == 1 + .udi_cdc_comm_0 = UDI_CDC_COMM_DESC_0, + .udi_cdc_data_0 = UDI_CDC_DATA_DESC_0_HS, +#else +# define UDI_CDC_DESC_HS(index, unused) \ + .udi_cdc_iad_##index = UDI_CDC_IAD_DESC_##index, \ + .udi_cdc_comm_##index = UDI_CDC_COMM_DESC_##index, \ + .udi_cdc_data_##index = UDI_CDC_DATA_DESC_##index##_HS, + MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_DESC_HS, ~) +# undef UDI_CDC_DESC_HS +#endif +}; +#endif + +/** + * \name UDC structures which content all USB Device definitions + */ +//@{ + +//! Associate an UDI for each USB interface +UDC_DESC_STORAGE udi_api_t *udi_apis[USB_DEVICE_NB_INTERFACE] = { +# define UDI_CDC_API(index, unused) \ + &udi_api_cdc_comm, \ + &udi_api_cdc_data, + MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_API, ~) +# undef UDI_CDC_API +}; + +//! Add UDI with USB Descriptors FS & HS +UDC_DESC_STORAGE udc_config_speed_t udc_config_fs[1] = { { + .desc = (usb_conf_desc_t UDC_DESC_STORAGE*)&udc_desc_fs, + .udi_apis = udi_apis, +}}; +#ifdef USB_DEVICE_HS_SUPPORT +UDC_DESC_STORAGE udc_config_speed_t udc_config_hs[1] = { { + .desc = (usb_conf_desc_t UDC_DESC_STORAGE*)&udc_desc_hs, + .udi_apis = udi_apis, +}}; +#endif + +//! Add all information about USB Device in global structure for UDC +UDC_DESC_STORAGE udc_config_t udc_config = { + .confdev_lsfs = &udc_device_desc, + .conf_lsfs = udc_config_fs, +#ifdef USB_DEVICE_HS_SUPPORT + .confdev_hs = &udc_device_desc, + .qualifier = &udc_device_qual, + .conf_hs = udc_config_hs, +#endif +#ifdef USB_DEVICE_LPM_SUPPORT + .conf_bos = &udc_device_lpm.bos, +#else + .conf_bos = NULL, +#endif +}; + +//@} +//@} diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/usb/class/cdc/usb_protocol_cdc.h b/hw-libs/drivers/SAMx70/ASF/common/services/usb/class/cdc/usb_protocol_cdc.h new file mode 100644 index 000000000..b8e3ad5a1 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/usb/class/cdc/usb_protocol_cdc.h @@ -0,0 +1,308 @@ +/** + * \file + * + * \brief USB Communication Device Class (CDC) protocol definitions + * + * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef _USB_PROTOCOL_CDC_H_ +#define _USB_PROTOCOL_CDC_H_ + +#include "compiler.h" + +/** + * \ingroup usb_protocol_group + * \defgroup cdc_protocol_group Communication Device Class Definitions + * @{ + */ + +/** + * \name Possible values of class + */ +//@{ +#define CDC_CLASS_DEVICE 0x02 //!< USB Communication Device Class +#define CDC_CLASS_COMM 0x02 //!< CDC Communication Class Interface +#define CDC_CLASS_DATA 0x0A //!< CDC Data Class Interface +//@} + +//! \name USB CDC Subclass IDs +//@{ +#define CDC_SUBCLASS_DLCM 0x01 //!< Direct Line Control Model +#define CDC_SUBCLASS_ACM 0x02 //!< Abstract Control Model +#define CDC_SUBCLASS_TCM 0x03 //!< Telephone Control Model +#define CDC_SUBCLASS_MCCM 0x04 //!< Multi-Channel Control Model +#define CDC_SUBCLASS_CCM 0x05 //!< CAPI Control Model +#define CDC_SUBCLASS_ETH 0x06 //!< Ethernet Networking Control Model +#define CDC_SUBCLASS_ATM 0x07 //!< ATM Networking Control Model +//@} + +//! \name USB CDC Communication Interface Protocol IDs +//@{ +#define CDC_PROTOCOL_V25TER 0x01 //!< Common AT commands +//@} + +//! \name USB CDC Data Interface Protocol IDs +//@{ +#define CDC_PROTOCOL_I430 0x30 //!< ISDN BRI +#define CDC_PROTOCOL_HDLC 0x31 //!< HDLC +#define CDC_PROTOCOL_TRANS 0x32 //!< Transparent +#define CDC_PROTOCOL_Q921M 0x50 //!< Q.921 management protocol +#define CDC_PROTOCOL_Q921 0x51 //!< Q.931 [sic] Data link protocol +#define CDC_PROTOCOL_Q921TM 0x52 //!< Q.921 TEI-multiplexor +#define CDC_PROTOCOL_V42BIS 0x90 //!< Data compression procedures +#define CDC_PROTOCOL_Q931 0x91 //!< Euro-ISDN protocol control +#define CDC_PROTOCOL_V120 0x92 //!< V.24 rate adaption to ISDN +#define CDC_PROTOCOL_CAPI20 0x93 //!< CAPI Commands +#define CDC_PROTOCOL_HOST 0xFD //!< Host based driver +/** + * \brief Describes the Protocol Unit Functional Descriptors [sic] + * on Communication Class Interface + */ +#define CDC_PROTOCOL_PUFD 0xFE +//@} + +//! \name USB CDC Functional Descriptor Types +//@{ +#define CDC_CS_INTERFACE 0x24 //!< Interface Functional Descriptor +#define CDC_CS_ENDPOINT 0x25 //!< Endpoint Functional Descriptor +//@} + +//! \name USB CDC Functional Descriptor Subtypes +//@{ +#define CDC_SCS_HEADER 0x00 //!< Header Functional Descriptor +#define CDC_SCS_CALL_MGMT 0x01 //!< Call Management +#define CDC_SCS_ACM 0x02 //!< Abstract Control Management +#define CDC_SCS_UNION 0x06 //!< Union Functional Descriptor +//@} + +//! \name USB CDC Request IDs +//@{ +#define USB_REQ_CDC_SEND_ENCAPSULATED_COMMAND 0x00 +#define USB_REQ_CDC_GET_ENCAPSULATED_RESPONSE 0x01 +#define USB_REQ_CDC_SET_COMM_FEATURE 0x02 +#define USB_REQ_CDC_GET_COMM_FEATURE 0x03 +#define USB_REQ_CDC_CLEAR_COMM_FEATURE 0x04 +#define USB_REQ_CDC_SET_AUX_LINE_STATE 0x10 +#define USB_REQ_CDC_SET_HOOK_STATE 0x11 +#define USB_REQ_CDC_PULSE_SETUP 0x12 +#define USB_REQ_CDC_SEND_PULSE 0x13 +#define USB_REQ_CDC_SET_PULSE_TIME 0x14 +#define USB_REQ_CDC_RING_AUX_JACK 0x15 +#define USB_REQ_CDC_SET_LINE_CODING 0x20 +#define USB_REQ_CDC_GET_LINE_CODING 0x21 +#define USB_REQ_CDC_SET_CONTROL_LINE_STATE 0x22 +#define USB_REQ_CDC_SEND_BREAK 0x23 +#define USB_REQ_CDC_SET_RINGER_PARMS 0x30 +#define USB_REQ_CDC_GET_RINGER_PARMS 0x31 +#define USB_REQ_CDC_SET_OPERATION_PARMS 0x32 +#define USB_REQ_CDC_GET_OPERATION_PARMS 0x33 +#define USB_REQ_CDC_SET_LINE_PARMS 0x34 +#define USB_REQ_CDC_GET_LINE_PARMS 0x35 +#define USB_REQ_CDC_DIAL_DIGITS 0x36 +#define USB_REQ_CDC_SET_UNIT_PARAMETER 0x37 +#define USB_REQ_CDC_GET_UNIT_PARAMETER 0x38 +#define USB_REQ_CDC_CLEAR_UNIT_PARAMETER 0x39 +#define USB_REQ_CDC_GET_PROFILE 0x3A +#define USB_REQ_CDC_SET_ETHERNET_MULTICAST_FILTERS 0x40 +#define USB_REQ_CDC_SET_ETHERNET_POWER_MANAGEMENT_PATTERNFILTER 0x41 +#define USB_REQ_CDC_GET_ETHERNET_POWER_MANAGEMENT_PATTERNFILTER 0x42 +#define USB_REQ_CDC_SET_ETHERNET_PACKET_FILTER 0x43 +#define USB_REQ_CDC_GET_ETHERNET_STATISTIC 0x44 +#define USB_REQ_CDC_SET_ATM_DATA_FORMAT 0x50 +#define USB_REQ_CDC_GET_ATM_DEVICE_STATISTICS 0x51 +#define USB_REQ_CDC_SET_ATM_DEFAULT_VC 0x52 +#define USB_REQ_CDC_GET_ATM_VC_STATISTICS 0x53 +// Added bNotification codes according cdc spec 1.1 chapter 6.3 +#define USB_REQ_CDC_NOTIFY_RING_DETECT 0x09 +#define USB_REQ_CDC_NOTIFY_SERIAL_STATE 0x20 +#define USB_REQ_CDC_NOTIFY_CALL_STATE_CHANGE 0x28 +#define USB_REQ_CDC_NOTIFY_LINE_STATE_CHANGE 0x29 +//@} + +/* + * Need to pack structures tightly, or the compiler might insert padding + * and violate the spec-mandated layout. + */ +COMPILER_PACK_SET(1) + +//! \name USB CDC Descriptors +//@{ + + +//! CDC Header Functional Descriptor +typedef struct { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + le16_t bcdCDC; +} usb_cdc_hdr_desc_t; + +//! CDC Call Management Functional Descriptor +typedef struct { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bmCapabilities; + uint8_t bDataInterface; +} usb_cdc_call_mgmt_desc_t; + +//! CDC ACM Functional Descriptor +typedef struct { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bmCapabilities; +} usb_cdc_acm_desc_t; + +//! CDC Union Functional Descriptor +typedef struct { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bMasterInterface; + uint8_t bSlaveInterface0; +} usb_cdc_union_desc_t; + + +//! \name USB CDC Call Management Capabilities +//@{ +//! Device handles call management itself +#define CDC_CALL_MGMT_SUPPORTED (1 << 0) +//! Device can send/receive call management info over a Data Class interface +#define CDC_CALL_MGMT_OVER_DCI (1 << 1) +//@} + +//! \name USB CDC ACM Capabilities +//@{ +//! Device supports the request combination of +//! Set_Comm_Feature, Clear_Comm_Feature, and Get_Comm_Feature. +#define CDC_ACM_SUPPORT_FEATURE_REQUESTS (1 << 0) +//! Device supports the request combination of +//! Set_Line_Coding, Set_Control_Line_State, Get_Line_Coding, +//! and the notification Serial_State. +#define CDC_ACM_SUPPORT_LINE_REQUESTS (1 << 1) +//! Device supports the request Send_Break +#define CDC_ACM_SUPPORT_SENDBREAK_REQUESTS (1 << 2) +//! Device supports the notification Network_Connection. +#define CDC_ACM_SUPPORT_NOTIFY_REQUESTS (1 << 3) +//@} +//@} + +//! \name USB CDC line control +//@{ + +//! \name USB CDC line coding +//@{ +//! Line Coding structure +typedef struct { + le32_t dwDTERate; + uint8_t bCharFormat; + uint8_t bParityType; + uint8_t bDataBits; +} usb_cdc_line_coding_t; +//! Possible values of bCharFormat +enum cdc_char_format { + CDC_STOP_BITS_1 = 0, //!< 1 stop bit + CDC_STOP_BITS_1_5 = 1, //!< 1.5 stop bits + CDC_STOP_BITS_2 = 2, //!< 2 stop bits +}; +//! Possible values of bParityType +enum cdc_parity { + CDC_PAR_NONE = 0, //!< No parity + CDC_PAR_ODD = 1, //!< Odd parity + CDC_PAR_EVEN = 2, //!< Even parity + CDC_PAR_MARK = 3, //!< Parity forced to 0 (space) + CDC_PAR_SPACE = 4, //!< Parity forced to 1 (mark) +}; +//@} + +//! \name USB CDC control signals +//! spec 1.1 chapter 6.2.14 +//@{ + +//! Control signal structure +typedef struct { + uint16_t value; +} usb_cdc_control_signal_t; + +//! \name Possible values in usb_cdc_control_signal_t +//@{ +//! Carrier control for half duplex modems. +//! This signal corresponds to V.24 signal 105 and RS-232 signal RTS. +//! The device ignores the value of this bit +//! when operating in full duplex mode. +#define CDC_CTRL_SIGNAL_ACTIVATE_CARRIER (1 << 1) +//! Indicates to DCE if DTE is present or not. +//! This signal corresponds to V.24 signal 108/2 and RS-232 signal DTR. +#define CDC_CTRL_SIGNAL_DTE_PRESENT (1 << 0) +//@} +//@} + + +//! \name USB CDC notification message +//@{ + +typedef struct { + uint8_t bmRequestType; + uint8_t bNotification; + le16_t wValue; + le16_t wIndex; + le16_t wLength; +} usb_cdc_notify_msg_t; + +//! \name USB CDC serial state +//@{* + +//! Hardware handshake support (cdc spec 1.1 chapter 6.3.5) +typedef struct { + usb_cdc_notify_msg_t header; + le16_t value; +} usb_cdc_notify_serial_state_t; + +//! \name Possible values in usb_cdc_notify_serial_state_t +//@{ +#define CDC_SERIAL_STATE_DCD CPU_TO_LE16((1<<0)) +#define CDC_SERIAL_STATE_DSR CPU_TO_LE16((1<<1)) +#define CDC_SERIAL_STATE_BREAK CPU_TO_LE16((1<<2)) +#define CDC_SERIAL_STATE_RING CPU_TO_LE16((1<<3)) +#define CDC_SERIAL_STATE_FRAMING CPU_TO_LE16((1<<4)) +#define CDC_SERIAL_STATE_PARITY CPU_TO_LE16((1<<5)) +#define CDC_SERIAL_STATE_OVERRUN CPU_TO_LE16((1<<6)) +//@} +//! @} + +//! @} + +COMPILER_PACK_RESET() + +//! @} + +#endif // _USB_PROTOCOL_CDC_H_ diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/usb/udc/udc.c b/hw-libs/drivers/SAMx70/ASF/common/services/usb/udc/udc.c new file mode 100644 index 000000000..e2f9527ba --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/usb/udc/udc.c @@ -0,0 +1,1135 @@ +/** + * \file + * + * \brief USB Device Controller (UDC) + * + * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "conf_usb.h" +#include "usb_protocol.h" +#include "udd.h" +#include "udc_desc.h" +#include "udi.h" +#include "udc.h" + +/** + * \ingroup udc_group + * \defgroup udc_group_interne Implementation of UDC + * + * Internal implementation + * @{ + */ + +//! \name Internal variables to manage the USB device +//! @{ + +//! Device status state (see enum usb_device_status in usb_protocol.h) +static le16_t udc_device_status; + +COMPILER_WORD_ALIGNED +//! Device interface setting value +static uint8_t udc_iface_setting = 0; + +//! Device Configuration number selected by the USB host +COMPILER_WORD_ALIGNED +static uint8_t udc_num_configuration = 0; + +//! Pointer on the selected speed device configuration +static udc_config_speed_t UDC_DESC_STORAGE *udc_ptr_conf; + +//! Pointer on interface descriptor used by SETUP request. +static usb_iface_desc_t UDC_DESC_STORAGE *udc_ptr_iface; + +//! @} + + +//! \name Internal structure to store the USB device main strings +//! @{ + +/** + * \brief Language ID of USB device (US ID by default) + */ +COMPILER_WORD_ALIGNED +static UDC_DESC_STORAGE usb_str_lgid_desc_t udc_string_desc_languageid = { + .desc.bLength = sizeof(usb_str_lgid_desc_t), + .desc.bDescriptorType = USB_DT_STRING, + .string = {LE16(USB_LANGID_EN_US)} +}; + +/** + * \brief USB device manufacture name storage + * String is allocated only if USB_DEVICE_MANUFACTURE_NAME is declared + * by usb application configuration + */ +#ifdef USB_DEVICE_MANUFACTURE_NAME +static uint8_t udc_string_manufacturer_name[] = USB_DEVICE_MANUFACTURE_NAME; +# define USB_DEVICE_MANUFACTURE_NAME_SIZE \ + (sizeof(udc_string_manufacturer_name)-1) +#else +# define USB_DEVICE_MANUFACTURE_NAME_SIZE 0 +#endif + +/** + * \brief USB device product name storage + * String is allocated only if USB_DEVICE_PRODUCT_NAME is declared + * by usb application configuration + */ +#ifdef USB_DEVICE_PRODUCT_NAME +static uint8_t udc_string_product_name[] = USB_DEVICE_PRODUCT_NAME; +# define USB_DEVICE_PRODUCT_NAME_SIZE (sizeof(udc_string_product_name)-1) +#else +# define USB_DEVICE_PRODUCT_NAME_SIZE 0 +#endif + +/** + * \brief Get USB device serial number + * + * Use the define USB_DEVICE_SERIAL_NAME to set static serial number. + * + * For dynamic serial number set the define USB_DEVICE_GET_SERIAL_NAME_POINTER + * to a suitable pointer. This will also require the serial number length + * define USB_DEVICE_GET_SERIAL_NAME_LENGTH. + */ +#if defined USB_DEVICE_GET_SERIAL_NAME_POINTER + static const uint8_t *udc_get_string_serial_name(void) + { + return (const uint8_t *)USB_DEVICE_GET_SERIAL_NAME_POINTER; + } +# define USB_DEVICE_SERIAL_NAME_SIZE \ + USB_DEVICE_GET_SERIAL_NAME_LENGTH +#elif defined USB_DEVICE_SERIAL_NAME + static const uint8_t *udc_get_string_serial_name(void) + { + return (const uint8_t *)USB_DEVICE_SERIAL_NAME; + } +# define USB_DEVICE_SERIAL_NAME_SIZE \ + (sizeof(USB_DEVICE_SERIAL_NAME)-1) +#else +# define USB_DEVICE_SERIAL_NAME_SIZE 0 +#endif + +/** + * \brief USB device string descriptor + * Structure used to transfer ASCII strings to USB String descriptor structure. + */ +struct udc_string_desc_t { + usb_str_desc_t header; + le16_t string[Max(Max(USB_DEVICE_MANUFACTURE_NAME_SIZE, \ + USB_DEVICE_PRODUCT_NAME_SIZE), USB_DEVICE_SERIAL_NAME_SIZE)]; +}; +COMPILER_WORD_ALIGNED +static UDC_DESC_STORAGE struct udc_string_desc_t udc_string_desc = { + .header.bDescriptorType = USB_DT_STRING +}; +//! @} + +usb_iface_desc_t UDC_DESC_STORAGE *udc_get_interface_desc(void) +{ + return udc_ptr_iface; +} + +/** + * \brief Returns a value to check the end of USB Configuration descriptor + * + * \return address after the last byte of USB Configuration descriptor + */ +static usb_conf_desc_t UDC_DESC_STORAGE *udc_get_eof_conf(void) +{ + return (UDC_DESC_STORAGE usb_conf_desc_t *) ((uint8_t *) + udc_ptr_conf->desc + + le16_to_cpu(udc_ptr_conf->desc->wTotalLength)); +} + +#if (0!=USB_DEVICE_MAX_EP) +/** + * \brief Search specific descriptor in global interface descriptor + * + * \param desc Address of interface descriptor + * or previous specific descriptor found + * \param desc_id Descriptor ID to search + * + * \return address of specific descriptor found + * \return NULL if it is the end of global interface descriptor + */ +static usb_conf_desc_t UDC_DESC_STORAGE *udc_next_desc_in_iface(usb_conf_desc_t + UDC_DESC_STORAGE * desc, uint8_t desc_id) +{ + usb_conf_desc_t UDC_DESC_STORAGE *ptr_eof_desc; + + ptr_eof_desc = udc_get_eof_conf(); + // Go to next descriptor + desc = (UDC_DESC_STORAGE usb_conf_desc_t *) ((uint8_t *) desc + + desc->bLength); + // Check the end of configuration descriptor + while (ptr_eof_desc > desc) { + // If new interface descriptor is found, + // then it is the end of the current global interface descriptor + if (USB_DT_INTERFACE == desc->bDescriptorType) { + break; // End of global interface descriptor + } + if (desc_id == desc->bDescriptorType) { + return desc; // Specific descriptor found + } + // Go to next descriptor + desc = (UDC_DESC_STORAGE usb_conf_desc_t *) ((uint8_t *) desc + + desc->bLength); + } + return NULL; // No specific descriptor found +} +#endif + +/** + * \brief Search an interface descriptor + * This routine updates the internal pointer udc_ptr_iface. + * + * \param iface_num Interface number to find in Configuration Descriptor + * \param setting_num Setting number of interface to find + * + * \return 1 if found or 0 if not found + */ +static bool udc_update_iface_desc(uint8_t iface_num, uint8_t setting_num) +{ + usb_conf_desc_t UDC_DESC_STORAGE *ptr_end_desc; + + if (0 == udc_num_configuration) { + return false; + } + + if (iface_num >= udc_ptr_conf->desc->bNumInterfaces) { + return false; + } + + // Start at the beginning of configuration descriptor + udc_ptr_iface = (UDC_DESC_STORAGE usb_iface_desc_t *) + udc_ptr_conf->desc; + + // Check the end of configuration descriptor + ptr_end_desc = udc_get_eof_conf(); + while (ptr_end_desc > + (UDC_DESC_STORAGE usb_conf_desc_t *) udc_ptr_iface) { + if (USB_DT_INTERFACE == udc_ptr_iface->bDescriptorType) { + // A interface descriptor is found + // Check interface and alternate setting number + if ((iface_num == udc_ptr_iface->bInterfaceNumber) && + (setting_num == + udc_ptr_iface->bAlternateSetting)) { + return true; // Interface found + } + } + // Go to next descriptor + udc_ptr_iface = (UDC_DESC_STORAGE usb_iface_desc_t *) ( + (uint8_t *) udc_ptr_iface + + udc_ptr_iface->bLength); + } + return false; // Interface not found +} + +/** + * \brief Disables an usb device interface (UDI) + * This routine call the UDI corresponding to interface number + * + * \param iface_num Interface number to disable + * + * \return 1 if it is done or 0 if interface is not found + */ +static bool udc_iface_disable(uint8_t iface_num) +{ + udi_api_t UDC_DESC_STORAGE *udi_api; + + // Select first alternate setting of the interface + // to update udc_ptr_iface before call iface->getsetting() + if (!udc_update_iface_desc(iface_num, 0)) { + return false; + } + + // Select the interface with the current alternate setting + udi_api = udc_ptr_conf->udi_apis[iface_num]; + +#if (0!=USB_DEVICE_MAX_EP) + if (!udc_update_iface_desc(iface_num, udi_api->getsetting())) { + return false; + } + + // Start at the beginning of interface descriptor + { + usb_ep_desc_t UDC_DESC_STORAGE *ep_desc; + ep_desc = (UDC_DESC_STORAGE usb_ep_desc_t *) udc_ptr_iface; + while (1) { + // Search Endpoint descriptor included in global interface descriptor + ep_desc = (UDC_DESC_STORAGE usb_ep_desc_t *) + udc_next_desc_in_iface((UDC_DESC_STORAGE + usb_conf_desc_t *) + ep_desc, USB_DT_ENDPOINT); + if (NULL == ep_desc) { + break; + } + // Free the endpoint used by the interface + udd_ep_free(ep_desc->bEndpointAddress); + } + } +#endif + + // Disable interface + udi_api->disable(); + return true; +} + +/** + * \brief Enables an usb device interface (UDI) + * This routine calls the UDI corresponding + * to the interface and setting number. + * + * \param iface_num Interface number to enable + * \param setting_num Setting number to enable + * + * \return 1 if it is done or 0 if interface is not found + */ +static bool udc_iface_enable(uint8_t iface_num, uint8_t setting_num) +{ + // Select the interface descriptor + if (!udc_update_iface_desc(iface_num, setting_num)) { + return false; + } + +#if (0!=USB_DEVICE_MAX_EP) + usb_ep_desc_t UDC_DESC_STORAGE *ep_desc; + + // Start at the beginning of the global interface descriptor + ep_desc = (UDC_DESC_STORAGE usb_ep_desc_t *) udc_ptr_iface; + while (1) { + // Search Endpoint descriptor included in the global interface descriptor + ep_desc = (UDC_DESC_STORAGE usb_ep_desc_t *) + udc_next_desc_in_iface((UDC_DESC_STORAGE + usb_conf_desc_t *) ep_desc, + USB_DT_ENDPOINT); + if (NULL == ep_desc) + break; + // Alloc the endpoint used by the interface + if (!udd_ep_alloc(ep_desc->bEndpointAddress, + ep_desc->bmAttributes, + le16_to_cpu + (ep_desc->wMaxPacketSize))) { + return false; + } + } +#endif + // Enable the interface + return udc_ptr_conf->udi_apis[iface_num]->enable(); +} + +/*! \brief Start the USB Device stack + */ +void udc_start(void) +{ + udd_enable(); +} + +/*! \brief Stop the USB Device stack + */ +void udc_stop(void) +{ + udd_disable(); + udc_reset(); +} + +/** + * \brief Reset the current configuration of the USB device, + * This routines can be called by UDD when a RESET on the USB line occurs. + */ +void udc_reset(void) +{ + uint8_t iface_num; + + if (udc_num_configuration) { + for (iface_num = 0; + iface_num < udc_ptr_conf->desc->bNumInterfaces; + iface_num++) { + udc_iface_disable(iface_num); + } + } + udc_num_configuration = 0; +#if (USB_CONFIG_ATTR_REMOTE_WAKEUP \ + == (USB_DEVICE_ATTR & USB_CONFIG_ATTR_REMOTE_WAKEUP)) + if (CPU_TO_LE16(USB_DEV_STATUS_REMOTEWAKEUP) & udc_device_status) { + // Remote wakeup is enabled then disable it + UDC_REMOTEWAKEUP_DISABLE(); + } +#endif + udc_device_status = +#if (USB_DEVICE_ATTR & USB_CONFIG_ATTR_SELF_POWERED) + CPU_TO_LE16(USB_DEV_STATUS_SELF_POWERED); +#else + CPU_TO_LE16(USB_DEV_STATUS_BUS_POWERED); +#endif +} + +void udc_sof_notify(void) +{ + uint8_t iface_num; + + if (udc_num_configuration) { + for (iface_num = 0; + iface_num < udc_ptr_conf->desc->bNumInterfaces; + iface_num++) { + if (udc_ptr_conf->udi_apis[iface_num]->sof_notify != NULL) { + udc_ptr_conf->udi_apis[iface_num]->sof_notify(); + } + } + } +} + +/** + * \brief Standard device request to get device status + * + * \return true if success + */ +static bool udc_req_std_dev_get_status(void) +{ + if (udd_g_ctrlreq.req.wLength != sizeof(udc_device_status)) { + return false; + } + + udd_set_setup_payload( (uint8_t *) & udc_device_status, + sizeof(udc_device_status)); + return true; +} + +#if (0!=USB_DEVICE_MAX_EP) +/** + * \brief Standard endpoint request to get endpoint status + * + * \return true if success + */ +static bool udc_req_std_ep_get_status(void) +{ + static le16_t udc_ep_status; + + if (udd_g_ctrlreq.req.wLength != sizeof(udc_ep_status)) { + return false; + } + + udc_ep_status = udd_ep_is_halted(udd_g_ctrlreq.req. + wIndex & 0xFF) ? CPU_TO_LE16(USB_EP_STATUS_HALTED) : 0; + + udd_set_setup_payload( (uint8_t *) & udc_ep_status, + sizeof(udc_ep_status)); + return true; +} +#endif + +/** + * \brief Standard device request to change device status + * + * \return true if success + */ +static bool udc_req_std_dev_clear_feature(void) +{ + if (udd_g_ctrlreq.req.wLength) { + return false; + } + + if (udd_g_ctrlreq.req.wValue == USB_DEV_FEATURE_REMOTE_WAKEUP) { + udc_device_status &= CPU_TO_LE16(~(uint32_t)USB_DEV_STATUS_REMOTEWAKEUP); +#if (USB_CONFIG_ATTR_REMOTE_WAKEUP \ + == (USB_DEVICE_ATTR & USB_CONFIG_ATTR_REMOTE_WAKEUP)) + UDC_REMOTEWAKEUP_DISABLE(); +#endif + return true; + } + return false; +} + +#if (0!=USB_DEVICE_MAX_EP) +/** + * \brief Standard endpoint request to clear endpoint feature + * + * \return true if success + */ +static bool udc_req_std_ep_clear_feature(void) +{ + if (udd_g_ctrlreq.req.wLength) { + return false; + } + + if (udd_g_ctrlreq.req.wValue == USB_EP_FEATURE_HALT) { + return udd_ep_clear_halt(udd_g_ctrlreq.req.wIndex & 0xFF); + } + return false; +} +#endif + +/** + * \brief Standard device request to set a feature + * + * \return true if success + */ +static bool udc_req_std_dev_set_feature(void) +{ + if (udd_g_ctrlreq.req.wLength) { + return false; + } + + switch (udd_g_ctrlreq.req.wValue) { + + case USB_DEV_FEATURE_REMOTE_WAKEUP: +#if (USB_CONFIG_ATTR_REMOTE_WAKEUP \ + == (USB_DEVICE_ATTR & USB_CONFIG_ATTR_REMOTE_WAKEUP)) + udc_device_status |= CPU_TO_LE16(USB_DEV_STATUS_REMOTEWAKEUP); + UDC_REMOTEWAKEUP_ENABLE(); + return true; +#else + return false; +#endif + +#ifdef USB_DEVICE_HS_SUPPORT + case USB_DEV_FEATURE_TEST_MODE: + if (!udd_is_high_speed()) { + break; + } + if (udd_g_ctrlreq.req.wIndex & 0xff) { + break; + } + // Unconfigure the device, terminating all ongoing requests + udc_reset(); + switch ((udd_g_ctrlreq.req.wIndex >> 8) & 0xFF) { + case USB_DEV_TEST_MODE_J: + udd_g_ctrlreq.callback = udd_test_mode_j; + return true; + + case USB_DEV_TEST_MODE_K: + udd_g_ctrlreq.callback = udd_test_mode_k; + return true; + + case USB_DEV_TEST_MODE_SE0_NAK: + udd_g_ctrlreq.callback = udd_test_mode_se0_nak; + return true; + + case USB_DEV_TEST_MODE_PACKET: + udd_g_ctrlreq.callback = udd_test_mode_packet; + return true; + + case USB_DEV_TEST_MODE_FORCE_ENABLE: // Only for downstream facing hub ports + default: + break; + } + break; +#endif + default: + break; + } + return false; +} + +/** + * \brief Standard endpoint request to halt an endpoint + * + * \return true if success + */ +#if (0!=USB_DEVICE_MAX_EP) +static bool udc_req_std_ep_set_feature(void) +{ + if (udd_g_ctrlreq.req.wLength) { + return false; + } + if (udd_g_ctrlreq.req.wValue == USB_EP_FEATURE_HALT) { + udd_ep_abort(udd_g_ctrlreq.req.wIndex & 0xFF); + return udd_ep_set_halt(udd_g_ctrlreq.req.wIndex & 0xFF); + } + return false; +} +#endif + +/** + * \brief Change the address of device + * Callback called at the end of request set address + */ +static void udc_valid_address(void) +{ + udd_set_address(udd_g_ctrlreq.req.wValue & 0x7F); +} + +/** + * \brief Standard device request to set device address + * + * \return true if success + */ +static bool udc_req_std_dev_set_address(void) +{ + if (udd_g_ctrlreq.req.wLength) { + return false; + } + + // The address must be changed at the end of setup request after the handshake + // then we use a callback to change address + udd_g_ctrlreq.callback = udc_valid_address; + return true; +} + +/** + * \brief Standard device request to get device string descriptor + * + * \return true if success + */ +static bool udc_req_std_dev_get_str_desc(void) +{ + uint8_t i; + const uint8_t *str=NULL; + uint8_t str_length = 0; + + // Link payload pointer to the string corresponding at request + switch (udd_g_ctrlreq.req.wValue & 0xff) { + case 0: + udd_set_setup_payload((uint8_t *) &udc_string_desc_languageid, + sizeof(udc_string_desc_languageid)); + break; + +#ifdef USB_DEVICE_MANUFACTURE_NAME + case 1: + str_length = USB_DEVICE_MANUFACTURE_NAME_SIZE; + str = udc_string_manufacturer_name; + break; +#endif +#ifdef USB_DEVICE_PRODUCT_NAME + case 2: + str_length = USB_DEVICE_PRODUCT_NAME_SIZE; + str = udc_string_product_name; + break; +#endif +#if defined USB_DEVICE_SERIAL_NAME || defined USB_DEVICE_GET_SERIAL_NAME_POINTER + case 3: + str_length = USB_DEVICE_SERIAL_NAME_SIZE; + str = udc_get_string_serial_name(); + break; +#endif + default: +#ifdef UDC_GET_EXTRA_STRING + if (UDC_GET_EXTRA_STRING()) { + break; + } +#endif + return false; + } + + if (str_length) { + for(i = 0; i < str_length; i++) { + udc_string_desc.string[i] = cpu_to_le16((le16_t)str[i]); + } + + udc_string_desc.header.bLength = 2 + (str_length) * 2; + udd_set_setup_payload( + (uint8_t *) &udc_string_desc, + udc_string_desc.header.bLength); + } + + return true; +} + +/** + * \brief Standard device request to get descriptors about USB device + * + * \return true if success + */ +static bool udc_req_std_dev_get_descriptor(void) +{ + uint8_t conf_num; + + conf_num = udd_g_ctrlreq.req.wValue & 0xff; + + // Check descriptor ID + switch ((uint8_t) (udd_g_ctrlreq.req.wValue >> 8)) { + case USB_DT_DEVICE: + // Device descriptor requested +#ifdef USB_DEVICE_HS_SUPPORT + if (!udd_is_high_speed()) { + udd_set_setup_payload( + (uint8_t *) udc_config.confdev_hs, + udc_config.confdev_hs->bLength); + } else +#endif + { + udd_set_setup_payload( + (uint8_t *) udc_config.confdev_lsfs, + udc_config.confdev_lsfs->bLength); + } + break; + + case USB_DT_CONFIGURATION: + // Configuration descriptor requested +#ifdef USB_DEVICE_HS_SUPPORT + if (udd_is_high_speed()) { + // HS descriptor + if (conf_num >= udc_config.confdev_hs-> + bNumConfigurations) { + return false; + } + udd_set_setup_payload( + (uint8_t *)udc_config.conf_hs[conf_num].desc, + le16_to_cpu(udc_config.conf_hs[conf_num].desc->wTotalLength)); + } else +#endif + { + // FS descriptor + if (conf_num >= udc_config.confdev_lsfs-> + bNumConfigurations) { + return false; + } + udd_set_setup_payload( + (uint8_t *)udc_config.conf_lsfs[conf_num].desc, + le16_to_cpu(udc_config.conf_lsfs[conf_num].desc->wTotalLength)); + } + ((usb_conf_desc_t *) udd_g_ctrlreq.payload)->bDescriptorType = + USB_DT_CONFIGURATION; + break; + +#ifdef USB_DEVICE_HS_SUPPORT + case USB_DT_DEVICE_QUALIFIER: + // Device qualifier descriptor requested + udd_set_setup_payload( (uint8_t *) udc_config.qualifier, + udc_config.qualifier->bLength); + break; + + case USB_DT_OTHER_SPEED_CONFIGURATION: + // Other configuration descriptor requested + if (!udd_is_high_speed()) { + // HS descriptor + if (conf_num >= udc_config.confdev_hs-> + bNumConfigurations) { + return false; + } + udd_set_setup_payload( + (uint8_t *)udc_config.conf_hs[conf_num].desc, + le16_to_cpu(udc_config.conf_hs[conf_num].desc->wTotalLength)); + } else { + // FS descriptor + if (conf_num >= udc_config.confdev_lsfs-> + bNumConfigurations) { + return false; + } + udd_set_setup_payload( + (uint8_t *)udc_config.conf_lsfs[conf_num].desc, + le16_to_cpu(udc_config.conf_lsfs[conf_num].desc->wTotalLength)); + } + ((usb_conf_desc_t *) udd_g_ctrlreq.payload)->bDescriptorType = + USB_DT_OTHER_SPEED_CONFIGURATION; + break; +#endif + + case USB_DT_BOS: + // Device BOS descriptor requested + if (udc_config.conf_bos == NULL) { + return false; + } + udd_set_setup_payload( (uint8_t *) udc_config.conf_bos, + udc_config.conf_bos->wTotalLength); + break; + + case USB_DT_STRING: + // String descriptor requested + if (!udc_req_std_dev_get_str_desc()) { + return false; + } + break; + + default: + // Unknown descriptor requested + return false; + } + // if the descriptor is larger than length requested, then reduce it + if (udd_g_ctrlreq.req.wLength < udd_g_ctrlreq.payload_size) { + udd_g_ctrlreq.payload_size = udd_g_ctrlreq.req.wLength; + } + return true; +} + +/** + * \brief Standard device request to get configuration number + * + * \return true if success + */ +static bool udc_req_std_dev_get_configuration(void) +{ + if (udd_g_ctrlreq.req.wLength != 1) { + return false; + } + + udd_set_setup_payload(&udc_num_configuration,1); + return true; +} + +/** + * \brief Standard device request to enable a configuration + * + * \return true if success + */ +static bool udc_req_std_dev_set_configuration(void) +{ + uint8_t iface_num; + + // Check request length + if (udd_g_ctrlreq.req.wLength) { + return false; + } + // Authorize configuration only if the address is valid + if (!udd_getaddress()) { + return false; + } + // Check the configuration number requested +#ifdef USB_DEVICE_HS_SUPPORT + if (udd_is_high_speed()) { + // HS descriptor + if ((udd_g_ctrlreq.req.wValue & 0xFF) > + udc_config.confdev_hs->bNumConfigurations) { + return false; + } + } else +#endif + { + // FS descriptor + if ((udd_g_ctrlreq.req.wValue & 0xFF) > + udc_config.confdev_lsfs->bNumConfigurations) { + return false; + } + } + + // Reset current configuration + udc_reset(); + + // Enable new configuration + udc_num_configuration = udd_g_ctrlreq.req.wValue & 0xFF; + if (udc_num_configuration == 0) { + return true; // Default empty configuration requested + } + // Update pointer of the configuration descriptor +#ifdef USB_DEVICE_HS_SUPPORT + if (udd_is_high_speed()) { + // HS descriptor + udc_ptr_conf = &udc_config.conf_hs[udc_num_configuration - 1]; + } else +#endif + { + // FS descriptor + udc_ptr_conf = &udc_config.conf_lsfs[udc_num_configuration - 1]; + } + // Enable all interfaces of the selected configuration + for (iface_num = 0; iface_num < udc_ptr_conf->desc->bNumInterfaces; + iface_num++) { + if (!udc_iface_enable(iface_num, 0)) { + return false; + } + } + return true; +} + +/** + * \brief Standard interface request + * to get the alternate setting number of an interface + * + * \return true if success + */ +static bool udc_req_std_iface_get_setting(void) +{ + uint8_t iface_num; + udi_api_t UDC_DESC_STORAGE *udi_api; + + if (udd_g_ctrlreq.req.wLength != 1) { + return false; // Error in request + } + if (!udc_num_configuration) { + return false; // The device is not is configured state yet + } + + // Check the interface number included in the request + iface_num = udd_g_ctrlreq.req.wIndex & 0xFF; + if (iface_num >= udc_ptr_conf->desc->bNumInterfaces) { + return false; + } + + // Select first alternate setting of the interface to update udc_ptr_iface + // before call iface->getsetting() + if (!udc_update_iface_desc(iface_num, 0)) { + return false; + } + // Get alternate setting from UDI + udi_api = udc_ptr_conf->udi_apis[iface_num]; + udc_iface_setting = udi_api->getsetting(); + + // Link value to payload pointer of request + udd_set_setup_payload(&udc_iface_setting,1); + return true; +} + +/** + * \brief Standard interface request + * to set an alternate setting of an interface + * + * \return true if success + */ +static bool udc_req_std_iface_set_setting(void) +{ + uint8_t iface_num, setting_num; + + if (udd_g_ctrlreq.req.wLength) { + return false; // Error in request + } + if (!udc_num_configuration) { + return false; // The device is not is configured state yet + } + + iface_num = udd_g_ctrlreq.req.wIndex & 0xFF; + setting_num = udd_g_ctrlreq.req.wValue & 0xFF; + + // Disable current setting + if (!udc_iface_disable(iface_num)) { + return false; + } + + // Enable new setting + return udc_iface_enable(iface_num, setting_num); +} + +/** + * \brief Main routine to manage the standard USB SETUP request + * + * \return true if the request is supported + */ +static bool udc_reqstd(void) +{ + if (Udd_setup_is_in()) { + // GET Standard Requests + if (udd_g_ctrlreq.req.wLength == 0) { + return false; // Error for USB host + } + + if (USB_REQ_RECIP_DEVICE == Udd_setup_recipient()) { + // Standard Get Device request + switch (udd_g_ctrlreq.req.bRequest) { + case USB_REQ_GET_STATUS: + return udc_req_std_dev_get_status(); + case USB_REQ_GET_DESCRIPTOR: + return udc_req_std_dev_get_descriptor(); + case USB_REQ_GET_CONFIGURATION: + return udc_req_std_dev_get_configuration(); + default: + break; + } + } + + if (USB_REQ_RECIP_INTERFACE == Udd_setup_recipient()) { + // Standard Get Interface request + switch (udd_g_ctrlreq.req.bRequest) { + case USB_REQ_GET_INTERFACE: + return udc_req_std_iface_get_setting(); + default: + break; + } + } +#if (0!=USB_DEVICE_MAX_EP) + if (USB_REQ_RECIP_ENDPOINT == Udd_setup_recipient()) { + // Standard Get Endpoint request + switch (udd_g_ctrlreq.req.bRequest) { + case USB_REQ_GET_STATUS: + return udc_req_std_ep_get_status(); + default: + break; + } + } +#endif + } else { + // SET Standard Requests + if (USB_REQ_RECIP_DEVICE == Udd_setup_recipient()) { + // Standard Set Device request + switch (udd_g_ctrlreq.req.bRequest) { + case USB_REQ_SET_ADDRESS: + return udc_req_std_dev_set_address(); + case USB_REQ_CLEAR_FEATURE: + return udc_req_std_dev_clear_feature(); + case USB_REQ_SET_FEATURE: + return udc_req_std_dev_set_feature(); + case USB_REQ_SET_CONFIGURATION: + return udc_req_std_dev_set_configuration(); + case USB_REQ_SET_DESCRIPTOR: + /* Not supported (defined as optional by the USB 2.0 spec) */ + break; + default: + break; + } + } + + if (USB_REQ_RECIP_INTERFACE == Udd_setup_recipient()) { + // Standard Set Interface request + switch (udd_g_ctrlreq.req.bRequest) { + case USB_REQ_SET_INTERFACE: + return udc_req_std_iface_set_setting(); + default: + break; + } + } +#if (0!=USB_DEVICE_MAX_EP) + if (USB_REQ_RECIP_ENDPOINT == Udd_setup_recipient()) { + // Standard Set Endpoint request + switch (udd_g_ctrlreq.req.bRequest) { + case USB_REQ_CLEAR_FEATURE: + return udc_req_std_ep_clear_feature(); + case USB_REQ_SET_FEATURE: + return udc_req_std_ep_set_feature(); + default: + break; + } + } +#endif + } + return false; +} + +/** + * \brief Send the SETUP interface request to UDI + * + * \return true if the request is supported + */ +static bool udc_req_iface(void) +{ + uint8_t iface_num; + udi_api_t UDC_DESC_STORAGE *udi_api; + + if (0 == udc_num_configuration) { + return false; // The device is not is configured state yet + } + // Check interface number + iface_num = udd_g_ctrlreq.req.wIndex & 0xFF; + if (iface_num >= udc_ptr_conf->desc->bNumInterfaces) { + return false; + } + + //* To update udc_ptr_iface with the selected interface in request + // Select first alternate setting of interface to update udc_ptr_iface + // before calling udi_api->getsetting() + if (!udc_update_iface_desc(iface_num, 0)) { + return false; + } + // Select the interface with the current alternate setting + udi_api = udc_ptr_conf->udi_apis[iface_num]; + if (!udc_update_iface_desc(iface_num, udi_api->getsetting())) { + return false; + } + + // Send the SETUP request to the UDI corresponding to the interface number + return udi_api->setup(); +} + +/** + * \brief Send the SETUP interface request to UDI + * + * \return true if the request is supported + */ +static bool udc_req_ep(void) +{ + uint8_t iface_num; + udi_api_t UDC_DESC_STORAGE *udi_api; + + if (0 == udc_num_configuration) { + return false; // The device is not is configured state yet + } + // Send this request on all enabled interfaces + iface_num = udd_g_ctrlreq.req.wIndex & 0xFF; + for (iface_num = 0; iface_num < udc_ptr_conf->desc->bNumInterfaces; + iface_num++) { + // Select the interface with the current alternate setting + udi_api = udc_ptr_conf->udi_apis[iface_num]; + if (!udc_update_iface_desc(iface_num, udi_api->getsetting())) { + return false; + } + + // Send the SETUP request to the UDI + if (udi_api->setup()) { + return true; + } + } + return false; +} + +/** + * \brief Main routine to manage the USB SETUP request. + * + * This function parses a USB SETUP request and submits an appropriate + * response back to the host or, in the case of SETUP OUT requests + * with data, sets up a buffer for receiving the data payload. + * + * The main standard requests defined by the USB 2.0 standard are handled + * internally. The interface requests are sent to UDI, and the specific request + * sent to a specific application callback. + * + * \return true if the request is supported, else the request is stalled by UDD + */ +bool udc_process_setup(void) +{ + // By default no data (receive/send) and no callbacks registered + udd_g_ctrlreq.payload_size = 0; + udd_g_ctrlreq.callback = NULL; + udd_g_ctrlreq.over_under_run = NULL; + + if (Udd_setup_is_in()) { + if (udd_g_ctrlreq.req.wLength == 0) { + return false; // Error from USB host + } + } + + // If standard request then try to decode it in UDC + if (Udd_setup_type() == USB_REQ_TYPE_STANDARD) { + if (udc_reqstd()) { + return true; + } + } + + // If interface request then try to decode it in UDI + if (Udd_setup_recipient() == USB_REQ_RECIP_INTERFACE) { + if (udc_req_iface()) { + return true; + } + } + + // If endpoint request then try to decode it in UDI + if (Udd_setup_recipient() == USB_REQ_RECIP_ENDPOINT) { + if (udc_req_ep()) { + return true; + } + } + + // Here SETUP request unknown by UDC and UDIs +#ifdef USB_DEVICE_SPECIFIC_REQUEST + // Try to decode it in specific callback + return USB_DEVICE_SPECIFIC_REQUEST(); // Ex: Vendor request,... +#else + return false; +#endif +} + +//! @} diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/usb/udc/udc.h b/hw-libs/drivers/SAMx70/ASF/common/services/usb/udc/udc.h new file mode 100644 index 000000000..d09727f33 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/usb/udc/udc.h @@ -0,0 +1,687 @@ +/** + * \file + * + * \brief Interface of the USB Device Controller (UDC) + * + * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _UDC_H_ +#define _UDC_H_ + +#include "conf_usb.h" +#include "usb_protocol.h" +#include "udc_desc.h" +#include "udd.h" + +#if USB_DEVICE_VENDOR_ID == 0 +# error USB_DEVICE_VENDOR_ID cannot be equal to 0 +#endif + +#if USB_DEVICE_PRODUCT_ID == 0 +# error USB_DEVICE_PRODUCT_ID cannot be equal to 0 +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \ingroup usb_device_group + * \defgroup udc_group USB Device Controller (UDC) + * + * The UDC provides a high-level abstraction of the usb device. + * You can use these functions to control the main device state + * (start/attach/wakeup). + * + * \section USB_DEVICE_CONF USB Device Custom configuration + * The following USB Device configuration must be included in the conf_usb.h + * file of the application. + * + * USB_DEVICE_VENDOR_ID (Word)
+ * Vendor ID provided by USB org (ATMEL 0x03EB). + * + * USB_DEVICE_PRODUCT_ID (Word)
+ * Product ID (Referenced in usb_atmel.h). + * + * USB_DEVICE_MAJOR_VERSION (Byte)
+ * Major version of the device + * + * USB_DEVICE_MINOR_VERSION (Byte)
+ * Minor version of the device + * + * USB_DEVICE_MANUFACTURE_NAME (string)
+ * ASCII name for the manufacture + * + * USB_DEVICE_PRODUCT_NAME (string)
+ * ASCII name for the product + * + * USB_DEVICE_SERIAL_NAME (string)
+ * ASCII name to enable and set a serial number + * + * USB_DEVICE_POWER (Numeric)
+ * (unit mA) Maximum device power + * + * USB_DEVICE_ATTR (Byte)
+ * USB attributes available: + * - USB_CONFIG_ATTR_SELF_POWERED + * - USB_CONFIG_ATTR_REMOTE_WAKEUP + * Note: if remote wake enabled then defines remotewakeup callbacks, + * see Table 5-2. External API from UDC - Callback + * + * USB_DEVICE_LOW_SPEED (Only defined)
+ * Force the USB Device to run in low speed + * + * USB_DEVICE_HS_SUPPORT (Only defined)
+ * Authorize the USB Device to run in high speed + * + * USB_DEVICE_MAX_EP (Byte)
+ * Define the maximum endpoint number used by the USB Device.
+ * This one is already defined in UDI default configuration. + * Ex: + * - When endpoint control 0x00, endpoint 0x01 and + * endpoint 0x82 is used then USB_DEVICE_MAX_EP=2 + * - When only endpoint control 0x00 is used then USB_DEVICE_MAX_EP=0 + * - When endpoint 0x01 and endpoint 0x81 is used then USB_DEVICE_MAX_EP=1
+ * (configuration not possible on USBB interface) + * @{ + */ + +/** + * \brief Authorizes the VBUS event + * + * \return true, if the VBUS monitoring is possible. + * + * \section udc_vbus_monitoring VBus monitoring used cases + * + * The VBus monitoring is used only for USB SELF Power application. + * + * - By default the USB device is automatically attached when Vbus is high + * or when USB is start for devices without internal Vbus monitoring. + * conf_usb.h file does not contains define USB_DEVICE_ATTACH_AUTO_DISABLE. + * \code //#define USB_DEVICE_ATTACH_AUTO_DISABLE \endcode + * + * - Add custom VBUS monitoring. conf_usb.h file contains define + * USB_DEVICE_ATTACH_AUTO_DISABLE: + * \code #define USB_DEVICE_ATTACH_AUTO_DISABLE \endcode + * User C file contains: + * \code + // Authorize VBUS monitoring + if (!udc_include_vbus_monitoring()) { + // Implement custom VBUS monitoring via GPIO or other + } + Event_VBUS_present() // VBUS interrupt or GPIO interrupt or other + { + // Attach USB Device + udc_attach(); + } +\endcode + * + * - Case of battery charging. conf_usb.h file contains define + * USB_DEVICE_ATTACH_AUTO_DISABLE: + * \code #define USB_DEVICE_ATTACH_AUTO_DISABLE \endcode + * User C file contains: + * \code + Event VBUS present() // VBUS interrupt or GPIO interrupt or .. + { + // Authorize battery charging, but wait key press to start USB. + } + Event Key press() + { + // Stop batteries charging + // Start USB + udc_attach(); + } +\endcode + */ +static inline bool udc_include_vbus_monitoring(void) +{ + return udd_include_vbus_monitoring(); +} + +/*! \brief Start the USB Device stack + */ +void udc_start(void); + +/*! \brief Stop the USB Device stack + */ +void udc_stop(void); + +/** + * \brief Attach device to the bus when possible + * + * \warning If a VBus control is included in driver, + * then it will attach device when an acceptable Vbus + * level from the host is detected. + */ +static inline void udc_attach(void) +{ + udd_attach(); +} + + +/** + * \brief Detaches the device from the bus + * + * The driver must remove pull-up on USB line D- or D+. + */ +static inline void udc_detach(void) +{ + udd_detach(); +} + + +/*! \brief The USB driver sends a resume signal called \e "Upstream Resume" + * This is authorized only when the remote wakeup feature is enabled by host. + */ +static inline void udc_remotewakeup(void) +{ + udd_send_remotewakeup(); +} + + +/** + * \brief Returns a pointer on the current interface descriptor + * + * \return pointer on the current interface descriptor. + */ +usb_iface_desc_t UDC_DESC_STORAGE *udc_get_interface_desc(void); + +//@} + +/** + * \ingroup usb_group + * \defgroup usb_device_group USB Stack Device + * + * This module includes USB Stack Device implementation. + * The stack is divided in three parts: + * - USB Device Controller (UDC) provides USB chapter 9 compliance + * - USB Device Interface (UDI) provides USB Class compliance + * - USB Device Driver (UDD) provides USB Driver for each Atmel MCU + + * Many USB Device applications can be implemented on Atmel MCU. + * Atmel provides many application notes for different applications: + * - AVR4900, provides general information about Device Stack + * - AVR4901, explains how to create a new class + * - AVR4902, explains how to create a composite device + * - AVR49xx, all device classes provided in ASF have an application note + * + * A basic USB knowledge is required to understand the USB Device + * Class application notes (HID,MS,CDC,PHDC,...). + * Then, to create an USB device with + * only one class provided by ASF, refer directly to the application note + * corresponding to this USB class. The USB Device application note for + * New Class and Composite is dedicated to advanced USB users. + * + * @{ + */ + +//! @} + +#ifdef __cplusplus +} +#endif + +/** + * \ingroup udc_group + * \defgroup udc_basic_use_case_setup_prereq USB Device Controller (UDC) - Prerequisites + * Common prerequisites for all USB devices. + * + * This module is based on USB device stack full interrupt driven, and supporting + * \ref sleepmgr_group sleepmgr. For AVR and SAM3/4 devices the \ref clk_group clock services + * is supported. For SAMD devices the \ref asfdoc_sam0_system_clock_group clock driver is supported. + * + * The following procedure must be executed to setup the project correctly: + * - Specify the clock configuration: + * - XMEGA USB devices need 48MHz clock input.\n + * XMEGA USB devices need CPU frequency higher than 12MHz.\n + * You can use either an internal RC48MHz auto calibrated by Start of Frames + * or an external OSC. + * - UC3 and SAM3/4 devices without USB high speed support need 48MHz clock input.\n + * You must use a PLL and an external OSC. + * - UC3 and SAM3/4 devices with USB high speed support need 12MHz clock input.\n + * You must use an external OSC. + * - UC3 devices with USBC hardware need CPU frequency higher than 25MHz. + * - SAMD devices without USB high speed support need 48MHz clock input.\n + * You should use DFLL with USBCRM. + * - In conf_board.h, the define CONF_BOARD_USB_PORT must be added to enable USB lines. + * (Not mandatory for all boards) + * - Enable interrupts + * - Initialize the clock service + * + * The usage of \ref sleepmgr_group sleepmgr service is optional, but recommended to reduce power + * consumption: + * - Initialize the sleep manager service + * - Activate sleep mode when the application is in IDLE state + * + * \subpage udc_conf_clock. + * + * for AVR and SAM3/4 devices, add to the initialization code: + * \code + sysclk_init(); + irq_initialize_vectors(); + cpu_irq_enable(); + board_init(); + sleepmgr_init(); // Optional +\endcode + * + * For SAMD devices, add to the initialization code: + * \code + system_init(); + irq_initialize_vectors(); + cpu_irq_enable(); + sleepmgr_init(); // Optional +\endcode + * Add to the main IDLE loop: + * \code + sleepmgr_enter_sleep(); // Optional +\endcode + * + */ + +/** + * \ingroup udc_group + * \defgroup udc_basic_use_case_setup_code USB Device Controller (UDC) - Example code + * Common example code for all USB devices. + * + * Content of conf_usb.h: + * \code + #define USB_DEVICE_VENDOR_ID 0x03EB + #define USB_DEVICE_PRODUCT_ID 0xXXXX + #define USB_DEVICE_MAJOR_VERSION 1 + #define USB_DEVICE_MINOR_VERSION 0 + #define USB_DEVICE_POWER 100 + #define USB_DEVICE_ATTR USB_CONFIG_ATTR_BUS_POWERED +\endcode + * + * Add to application C-file: + * \code + void usb_init(void) + { + udc_start(); + } +\endcode + */ + +/** + * \ingroup udc_group + * \defgroup udc_basic_use_case_setup_flow USB Device Controller (UDC) - Workflow + * Common workflow for all USB devices. + * + * -# Ensure that conf_usb.h is available and contains the following configuration + * which is the main USB device configuration: + * - \code // Vendor ID provided by USB org (ATMEL 0x03EB) + #define USB_DEVICE_VENDOR_ID 0x03EB // Type Word + // Product ID (Atmel PID referenced in usb_atmel.h) + #define USB_DEVICE_PRODUCT_ID 0xXXXX // Type Word + // Major version of the device + #define USB_DEVICE_MAJOR_VERSION 1 // Type Byte + // Minor version of the device + #define USB_DEVICE_MINOR_VERSION 0 // Type Byte + // Maximum device power (mA) + #define USB_DEVICE_POWER 100 // Type 9-bits + // USB attributes to enable features + #define USB_DEVICE_ATTR USB_CONFIG_ATTR_BUS_POWERED // Flags \endcode + * -# Call the USB device stack start function to enable stack and start USB: + * - \code udc_start(); \endcode + * \note In case of USB dual roles (Device and Host) managed through USB OTG connector + * (USB ID pin), the call of udc_start() must be removed and replaced by uhc_start(). + * SeRefer to "AVR4950 section 6.1 Dual roles" for further information about dual roles. + */ + +/** + * \page udc_conf_clock conf_clock.h examples with USB support + * + * Content of XMEGA conf_clock.h: + * \code + // Configuration based on internal RC: + // USB clock need of 48Mhz + #define CONFIG_USBCLK_SOURCE USBCLK_SRC_RCOSC + #define CONFIG_OSC_RC32_CAL 48000000UL + #define CONFIG_OSC_AUTOCAL_RC32MHZ_REF_OSC OSC_ID_USBSOF + // CPU clock need of clock > 12MHz to run with USB (Here 24MHz) + #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_RC32MHZ + #define CONFIG_SYSCLK_PSADIV SYSCLK_PSADIV_2 + #define CONFIG_SYSCLK_PSBCDIV SYSCLK_PSBCDIV_1_1 +\endcode + * + * Content of conf_clock.h for AT32UC3A0, AT32UC3A1, AT32UC3B devices (USBB): + * \code + // Configuration based on 12MHz external OSC: + #define CONFIG_PLL1_SOURCE PLL_SRC_OSC0 + #define CONFIG_PLL1_MUL 8 + #define CONFIG_PLL1_DIV 2 + #define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL1 + #define CONFIG_USBCLK_DIV 1 // Fusb = Fsys/(2 ^ USB_div) +\endcode + * + * Content of conf_clock.h for AT32UC3A3, AT32UC3A4 devices (USBB with high speed support): + * \code + // Configuration based on 12MHz external OSC: + #define CONFIG_USBCLK_SOURCE USBCLK_SRC_OSC0 + #define CONFIG_USBCLK_DIV 1 // Fusb = Fsys/(2 ^ USB_div) +\endcode + * + * Content of conf_clock.h for AT32UC3C, ATUCXXD, ATUCXXL3U, ATUCXXL4U devices (USBC): + * \code + // Configuration based on 12MHz external OSC: + #define CONFIG_PLL1_SOURCE PLL_SRC_OSC0 + #define CONFIG_PLL1_MUL 8 + #define CONFIG_PLL1_DIV 2 + #define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL1 + #define CONFIG_USBCLK_DIV 1 // Fusb = Fsys/(2 ^ USB_div) + // CPU clock need of clock > 25MHz to run with USBC + #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLL1 +\endcode + * + * Content of conf_clock.h for SAM3S, SAM3SD, SAM4S devices (UPD: USB Peripheral Device): + * \code + // PLL1 (B) Options (Fpll = (Fclk * PLL_mul) / PLL_div) + #define CONFIG_PLL1_SOURCE PLL_SRC_MAINCK_XTAL + #define CONFIG_PLL1_MUL 16 + #define CONFIG_PLL1_DIV 2 + // USB Clock Source Options (Fusb = FpllX / USB_div) + #define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL1 + #define CONFIG_USBCLK_DIV 2 +\endcode + * + * Content of conf_clock.h for SAM3U device (UPDHS: USB Peripheral Device High Speed): + * \code + // USB Clock Source fixed at UPLL. +\endcode + * + * Content of conf_clock.h for SAM3X, SAM3A devices (UOTGHS: USB OTG High Speed): + * \code + // USB Clock Source fixed at UPLL. + #define CONFIG_USBCLK_SOURCE USBCLK_SRC_UPLL + #define CONFIG_USBCLK_DIV 1 +\endcode + * + * Content of conf_clocks.h for SAMD devices (USB): + * \code + // System clock bus configuration + # define CONF_CLOCK_FLASH_WAIT_STATES 2 + + // USB Clock Source fixed at DFLL. + // SYSTEM_CLOCK_SOURCE_DFLL configuration - Digital Frequency Locked Loop + # define CONF_CLOCK_DFLL_ENABLE true + # define CONF_CLOCK_DFLL_LOOP_MODE SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY + # define CONF_CLOCK_DFLL_ON_DEMAND true + + // Set this to true to configure the GCLK when running clocks_init. + // If set to false, none of the GCLK generators will be configured in clocks_init(). + # define CONF_CLOCK_CONFIGURE_GCLK true + + // Configure GCLK generator 0 (Main Clock) + # define CONF_CLOCK_GCLK_0_ENABLE true + # define CONF_CLOCK_GCLK_0_RUN_IN_STANDBY true + # define CONF_CLOCK_GCLK_0_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_DFLL + # define CONF_CLOCK_GCLK_0_PRESCALER 1 + # define CONF_CLOCK_GCLK_0_OUTPUT_ENABLE false +\endcode + */ + +/** + * \page udc_use_case_1 Change USB speed + * + * In this use case, the USB device is used with different USB speeds. + * + * \section udc_use_case_1_setup Setup steps + * + * Prior to implement this use case, be sure to have already + * apply the UDI module "basic use case". + * + * \section udc_use_case_1_usage Usage steps + * + * \subsection udc_use_case_1_usage_code Example code + * Content of conf_usb.h: + * \code + #if // Low speed + #define USB_DEVICE_LOW_SPEED + // #define USB_DEVICE_HS_SUPPORT + + #elif // Full speed + // #define USB_DEVICE_LOW_SPEED + // #define USB_DEVICE_HS_SUPPORT + + #elif // High speed + // #define USB_DEVICE_LOW_SPEED + #define USB_DEVICE_HS_SUPPORT + + #endif +\endcode + * + * \subsection udc_use_case_1_usage_flow Workflow + * -# Ensure that conf_usb.h is available and contains the following parameters + * required for a USB device low speed (1.5Mbit/s): + * - \code #define USB_DEVICE_LOW_SPEED + //#define USB_DEVICE_HS_SUPPORT \endcode + * -# Ensure that conf_usb.h contains the following parameters + * required for a USB device full speed (12Mbit/s): + * - \code //#define USB_DEVICE_LOW_SPEED + //#define USB_DEVICE_HS_SUPPORT \endcode + * -# Ensure that conf_usb.h contains the following parameters + * required for a USB device high speed (480Mbit/s): + * - \code //#define USB_DEVICE_LOW_SPEED + #define USB_DEVICE_HS_SUPPORT \endcode + */ + +/** + * \page udc_use_case_2 Use USB strings + * + * In this use case, the usual USB strings is added in the USB device. + * + * \section udc_use_case_2_setup Setup steps + * Prior to implement this use case, be sure to have already + * apply the UDI module "basic use case". + * + * \section udc_use_case_2_usage Usage steps + * + * \subsection udc_use_case_2_usage_code Example code + * Content of conf_usb.h: + * \code + #define USB_DEVICE_MANUFACTURE_NAME "Manufacture name" + #define USB_DEVICE_PRODUCT_NAME "Product name" + #define USB_DEVICE_SERIAL_NAME "12...EF" +\endcode + * + * \subsection udc_use_case_2_usage_flow Workflow + * -# Ensure that conf_usb.h is available and contains the following parameters + * required to enable different USB strings: + * - \code // Static ASCII name for the manufacture + #define USB_DEVICE_MANUFACTURE_NAME "Manufacture name" \endcode + * - \code // Static ASCII name for the product + #define USB_DEVICE_PRODUCT_NAME "Product name" \endcode + * - \code // Static ASCII name to enable and set a serial number + #define USB_DEVICE_SERIAL_NAME "12...EF" \endcode + */ + +/** + * \page udc_use_case_3 Use USB remote wakeup feature + * + * In this use case, the USB remote wakeup feature is enabled. + * + * \section udc_use_case_3_setup Setup steps + * Prior to implement this use case, be sure to have already + * apply the UDI module "basic use case". + * + * \section udc_use_case_3_usage Usage steps + * + * \subsection udc_use_case_3_usage_code Example code + * Content of conf_usb.h: + * \code + #define USB_DEVICE_ATTR \ + (USB_CONFIG_ATTR_REMOTE_WAKEUP | USB_CONFIG_ATTR_..._POWERED) + #define UDC_REMOTEWAKEUP_ENABLE() my_callback_remotewakeup_enable() + extern void my_callback_remotewakeup_enable(void); + #define UDC_REMOTEWAKEUP_DISABLE() my_callback_remotewakeup_disable() + extern void my_callback_remotewakeup_disable(void); +\endcode + * + * Add to application C-file: + * \code + void my_callback_remotewakeup_enable(void) + { + // Enable application wakeup events (e.g. enable GPIO interrupt) + } + void my_callback_remotewakeup_disable(void) + { + // Disable application wakeup events (e.g. disable GPIO interrupt) + } + + void my_interrupt_event(void) + { + udc_remotewakeup(); + } +\endcode + * + * \subsection udc_use_case_3_usage_flow Workflow + * -# Ensure that conf_usb.h is available and contains the following parameters + * required to enable remote wakeup feature: + * - \code // Authorizes the remote wakeup feature + #define USB_DEVICE_ATTR (USB_CONFIG_ATTR_REMOTE_WAKEUP | USB_CONFIG_ATTR_..._POWERED) \endcode + * - \code // Define callback called when the host enables the remotewakeup feature + #define UDC_REMOTEWAKEUP_ENABLE() my_callback_remotewakeup_enable() + extern void my_callback_remotewakeup_enable(void); \endcode + * - \code // Define callback called when the host disables the remotewakeup feature + #define UDC_REMOTEWAKEUP_DISABLE() my_callback_remotewakeup_disable() + extern void my_callback_remotewakeup_disable(void); \endcode + * -# Send a remote wakeup (USB upstream): + * - \code udc_remotewakeup(); \endcode + */ + +/** + * \page udc_use_case_5 Bus power application recommendations + * + * In this use case, the USB device BUS power feature is enabled. + * This feature requires a correct power consumption management. + * + * \section udc_use_case_5_setup Setup steps + * Prior to implement this use case, be sure to have already + * apply the UDI module "basic use case". + * + * \section udc_use_case_5_usage Usage steps + * + * \subsection udc_use_case_5_usage_code Example code + * Content of conf_usb.h: + * \code + #define USB_DEVICE_ATTR (USB_CONFIG_ATTR_BUS_POWERED) + #define UDC_SUSPEND_EVENT() user_callback_suspend_action() + extern void user_callback_suspend_action(void) + #define UDC_RESUME_EVENT() user_callback_resume_action() + extern void user_callback_resume_action(void) +\endcode + * + * Add to application C-file: + * \code + void user_callback_suspend_action(void) + { + // Disable hardware component to reduce power consumption + } + void user_callback_resume_action(void) + { + // Re-enable hardware component + } +\endcode + * + * \subsection udc_use_case_5_usage_flow Workflow + * -# Ensure that conf_usb.h is available and contains the following parameters: + * - \code // Authorizes the BUS power feature + #define USB_DEVICE_ATTR (USB_CONFIG_ATTR_BUS_POWERED) \endcode + * - \code // Define callback called when the host suspend the USB line + #define UDC_SUSPEND_EVENT() user_callback_suspend_action() + extern void user_callback_suspend_action(void); \endcode + * - \code // Define callback called when the host or device resume the USB line + #define UDC_RESUME_EVENT() user_callback_resume_action() + extern void user_callback_resume_action(void); \endcode + * -# Reduce power consumption in suspend mode (max. 2.5mA on Vbus): + * - \code void user_callback_suspend_action(void) + { + turn_off_components(); + } \endcode + */ + +/** + * \page udc_use_case_6 USB dynamic serial number + * + * In this use case, the USB serial strings is dynamic. + * For a static serial string refer to \ref udc_use_case_2. + * + * \section udc_use_case_6_setup Setup steps + * Prior to implement this use case, be sure to have already + * apply the UDI module "basic use case". + * + * \section udc_use_case_6_usage Usage steps + * + * \subsection udc_use_case_6_usage_code Example code + * Content of conf_usb.h: + * \code + #define USB_DEVICE_SERIAL_NAME + #define USB_DEVICE_GET_SERIAL_NAME_POINTER serial_number + #define USB_DEVICE_GET_SERIAL_NAME_LENGTH 12 + extern uint8_t serial_number[]; +\endcode + * + * Add to application C-file: + * \code + uint8_t serial_number[USB_DEVICE_GET_SERIAL_NAME_LENGTH]; + + void init_build_usb_serial_number(void) + { + serial_number[0] = 'A'; + serial_number[1] = 'B'; + ... + serial_number[USB_DEVICE_GET_SERIAL_NAME_LENGTH-1] = 'C'; + } \endcode + * + * \subsection udc_use_case_6_usage_flow Workflow + * -# Ensure that conf_usb.h is available and contains the following parameters + * required to enable a USB serial number strings dynamically: + * - \code #define USB_DEVICE_SERIAL_NAME // Define this empty + #define USB_DEVICE_GET_SERIAL_NAME_POINTER serial_number // Give serial array pointer + #define USB_DEVICE_GET_SERIAL_NAME_LENGTH 12 // Give size of serial array + extern uint8_t serial_number[]; // Declare external serial array \endcode + * -# Before start USB stack, initialize the serial array + * - \code + uint8_t serial_number[USB_DEVICE_GET_SERIAL_NAME_LENGTH]; + + void init_build_usb_serial_number(void) + { + serial_number[0] = 'A'; + serial_number[1] = 'B'; + ... + serial_number[USB_DEVICE_GET_SERIAL_NAME_LENGTH-1] = 'C'; + } \endcode + */ + + + +#endif // _UDC_H_ diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/usb/udc/udc_desc.h b/hw-libs/drivers/SAMx70/ASF/common/services/usb/udc/udc_desc.h new file mode 100644 index 000000000..186dc53f0 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/usb/udc/udc_desc.h @@ -0,0 +1,125 @@ +/** + * \file + * + * \brief Common API for USB Device Interface + * + * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _UDC_DESC_H_ +#define _UDC_DESC_H_ + +#include "conf_usb.h" +#include "usb_protocol.h" +#include "udi.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \ingroup udc_group + * \defgroup udc_desc_group USB Device Descriptor + * + * @{ + */ + +/** + * \brief Defines the memory's location of USB descriptors + * + * By default the Descriptor is stored in RAM + * (UDC_DESC_STORAGE is defined empty). + * + * If you have need to free RAM space, + * it is possible to put descriptor in flash in following case: + * - USB driver authorize flash transfer (USBB on UC3 and USB on Mega) + * - USB Device is not high speed (UDC no need to change USB descriptors) + * + * For UC3 application used "const". + * + * For Mega application used "code". + */ +#define UDC_DESC_STORAGE + // Descriptor storage in internal RAM +#if (defined UDC_DATA_USE_HRAM_SUPPORT) +# if defined(__GNUC__) +# define UDC_DATA(x) COMPILER_WORD_ALIGNED __attribute__((__section__(".data_hram0"))) +# define UDC_BSS(x) COMPILER_ALIGNED(x) __attribute__((__section__(".bss_hram0"))) +# elif defined(__ICCAVR32__) +# define UDC_DATA(x) COMPILER_ALIGNED(x) __data32 +# define UDC_BSS(x) COMPILER_ALIGNED(x) __data32 +# endif +#else +# define UDC_DATA(x) COMPILER_ALIGNED(x) +# define UDC_BSS(x) COMPILER_ALIGNED(x) +#endif + + + +/** + * \brief Configuration descriptor and UDI link for one USB speed + */ +typedef struct { + //! USB configuration descriptor + usb_conf_desc_t UDC_DESC_STORAGE *desc; + //! Array of UDI API pointer + udi_api_t UDC_DESC_STORAGE *UDC_DESC_STORAGE * udi_apis; +} udc_config_speed_t; + + +/** + * \brief All information about the USB Device + */ +typedef struct { + //! USB device descriptor for low or full speed + usb_dev_desc_t UDC_DESC_STORAGE *confdev_lsfs; + //! USB configuration descriptor and UDI API pointers for low or full speed + udc_config_speed_t UDC_DESC_STORAGE *conf_lsfs; +#ifdef USB_DEVICE_HS_SUPPORT + //! USB device descriptor for high speed + usb_dev_desc_t UDC_DESC_STORAGE *confdev_hs; + //! USB device qualifier, only use in high speed mode + usb_dev_qual_desc_t UDC_DESC_STORAGE *qualifier; + //! USB configuration descriptor and UDI API pointers for high speed + udc_config_speed_t UDC_DESC_STORAGE *conf_hs; +#endif + usb_dev_bos_desc_t UDC_DESC_STORAGE *conf_bos; +} udc_config_t; + +//! Global variables of USB Device Descriptor and UDI links +extern UDC_DESC_STORAGE udc_config_t udc_config; + +//@} + +#ifdef __cplusplus +} +#endif +#endif // _UDC_DESC_H_ diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/usb/udc/udd.h b/hw-libs/drivers/SAMx70/ASF/common/services/usb/udc/udd.h new file mode 100644 index 000000000..c5fcea36d --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/usb/udc/udd.h @@ -0,0 +1,386 @@ +/** + * \file + * + * \brief Common API for USB Device Drivers (UDD) + * + * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _UDD_H_ +#define _UDD_H_ + +#include "usb_protocol.h" +#include "udc_desc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \ingroup usb_device_group + * \defgroup udd_group USB Device Driver (UDD) + * + * The UDD driver provides a low-level abstraction of the device + * controller hardware. Most events coming from the hardware such as + * interrupts, which may cause the UDD to call into the UDC and UDI. + * + * @{ + */ + +//! \brief Endpoint identifier +typedef uint8_t udd_ep_id_t; + +//! \brief Endpoint transfer status +//! Returned in parameters of callback register via udd_ep_run routine. +typedef enum { + UDD_EP_TRANSFER_OK = 0, + UDD_EP_TRANSFER_ABORT = 1, +} udd_ep_status_t; + +/** + * \brief Global variable to give and record information of the setup request management + * + * This global variable allows to decode and response a setup request. + * It can be updated by udc_process_setup() from UDC or *setup() from UDIs. + */ +typedef struct { + //! Data received in USB SETUP packet + //! Note: The swap of "req.wValues" from uin16_t to le16_t is done by UDD. + usb_setup_req_t req; + + //! Point to buffer to send or fill with data following SETUP packet + //! This buffer must be word align for DATA IN phase (use prefix COMPILER_WORD_ALIGNED for buffer) + uint8_t *payload; + + //! Size of buffer to send or fill, and content the number of byte transfered + uint16_t payload_size; + + //! Callback called after reception of ZLP from setup request + void (*callback) (void); + + //! Callback called when the buffer given (.payload) is full or empty. + //! This one return false to abort data transfer, or true with a new buffer in .payload. + bool(*over_under_run) (void); +} udd_ctrl_request_t; +extern udd_ctrl_request_t udd_g_ctrlreq; + +//! Return true if the setup request \a udd_g_ctrlreq indicates IN data transfer +#define Udd_setup_is_in() \ + (USB_REQ_DIR_IN == (udd_g_ctrlreq.req.bmRequestType & USB_REQ_DIR_MASK)) + +//! Return true if the setup request \a udd_g_ctrlreq indicates OUT data transfer +#define Udd_setup_is_out() \ + (USB_REQ_DIR_OUT == (udd_g_ctrlreq.req.bmRequestType & USB_REQ_DIR_MASK)) + +//! Return the type of the SETUP request \a udd_g_ctrlreq. \see usb_reqtype. +#define Udd_setup_type() \ + (udd_g_ctrlreq.req.bmRequestType & USB_REQ_TYPE_MASK) + +//! Return the recipient of the SETUP request \a udd_g_ctrlreq. \see usb_recipient +#define Udd_setup_recipient() \ + (udd_g_ctrlreq.req.bmRequestType & USB_REQ_RECIP_MASK) + +/** + * \brief End of halt callback function type. + * Registered by routine udd_ep_wait_stall_clear() + * Callback called when endpoint stall is cleared. + */ +typedef void (*udd_callback_halt_cleared_t) (void); + +/** + * \brief End of transfer callback function type. + * Registered by routine udd_ep_run() + * Callback called by USB interrupt after data transfer or abort (reset,...). + * + * \param status UDD_EP_TRANSFER_OK, if transfer is complete + * \param status UDD_EP_TRANSFER_ABORT, if transfer is aborted + * \param n number of data transfered + */ +typedef void (*udd_callback_trans_t) (udd_ep_status_t status, + iram_size_t nb_transfered, udd_ep_id_t ep); + +/** + * \brief Authorizes the VBUS event + * + * \return true, if the VBUS monitoring is possible. + */ +bool udd_include_vbus_monitoring(void); + +/** + * \brief Enables the USB Device mode + */ +void udd_enable(void); + +/** + * \brief Disables the USB Device mode + */ +void udd_disable(void); + +/** + * \brief Attach device to the bus when possible + * + * \warning If a VBus control is included in driver, + * then it will attach device when an acceptable Vbus + * level from the host is detected. + */ +void udd_attach(void); + +/** + * \brief Detaches the device from the bus + * + * The driver must remove pull-up on USB line D- or D+. + */ +void udd_detach(void); + +/** + * \brief Test whether the USB Device Controller is running at high + * speed or not. + * + * \return \c true if the Device is running at high speed mode, otherwise \c false. + */ +bool udd_is_high_speed(void); + +/** + * \brief Changes the USB address of device + * + * \param address New USB address + */ +void udd_set_address(uint8_t address); + +/** + * \brief Returns the USB address of device + * + * \return USB address + */ +uint8_t udd_getaddress(void); + +/** + * \brief Returns the current start of frame number + * + * \return current start of frame number. + */ +uint16_t udd_get_frame_number(void); + +/** + * \brief Returns the current micro start of frame number + * + * \return current micro start of frame number required in high speed mode. + */ +uint16_t udd_get_micro_frame_number(void); + +/*! \brief The USB driver sends a resume signal called Upstream Resume + */ +void udd_send_remotewakeup(void); + +/** + * \brief Load setup payload + * + * \param payload Pointer on payload + * \param payload_size Size of payload + */ +void udd_set_setup_payload( uint8_t *payload, uint16_t payload_size ); + + +/** + * \name Endpoint Management + * + * The following functions allow drivers to create and remove + * endpoints, as well as set, clear and query their "halted" and + * "wedged" states. + */ +//@{ + +#if (USB_DEVICE_MAX_EP != 0) + +/** + * \brief Configures and enables an endpoint + * + * \param ep Endpoint number including direction (USB_EP_DIR_IN/USB_EP_DIR_OUT). + * \param bmAttributes Attributes of endpoint declared in the descriptor. + * \param MaxEndpointSize Endpoint maximum size + * + * \return \c 1 if the endpoint is enabled, otherwise \c 0. + */ +bool udd_ep_alloc(udd_ep_id_t ep, uint8_t bmAttributes, + uint16_t MaxEndpointSize); + +/** + * \brief Disables an endpoint + * + * \param ep Endpoint number including direction (USB_EP_DIR_IN/USB_EP_DIR_OUT). + */ +void udd_ep_free(udd_ep_id_t ep); + +/** + * \brief Check if the endpoint \a ep is halted. + * + * \param ep The ID of the endpoint to check. + * + * \return \c 1 if \a ep is halted, otherwise \c 0. + */ +bool udd_ep_is_halted(udd_ep_id_t ep); + +/** + * \brief Set the halted state of the endpoint \a ep + * + * After calling this function, any transaction on \a ep will result + * in a STALL handshake being sent. Any pending transactions will be + * performed first, however. + * + * \param ep The ID of the endpoint to be halted + * + * \return \c 1 if \a ep is halted, otherwise \c 0. + */ +bool udd_ep_set_halt(udd_ep_id_t ep); + +/** + * \brief Clear the halted state of the endpoint \a ep + * + * After calling this function, any transaction on \a ep will + * be handled normally, i.e. a STALL handshake will not be sent, and + * the data toggle sequence will start at DATA0. + * + * \param ep The ID of the endpoint to be un-halted + * + * \return \c 1 if function was successfully done, otherwise \c 0. + */ +bool udd_ep_clear_halt(udd_ep_id_t ep); + +/** + * \brief Registers a callback to call when endpoint halt is cleared + * + * \param ep The ID of the endpoint to use + * \param callback NULL or function to call when endpoint halt is cleared + * + * \warning if the endpoint is not halted then the \a callback is called immediately. + * + * \return \c 1 if the register is accepted, otherwise \c 0. + */ +bool udd_ep_wait_stall_clear(udd_ep_id_t ep, + udd_callback_halt_cleared_t callback); + +/** + * \brief Allows to receive or send data on an endpoint + * + * The driver uses a specific DMA USB to transfer data + * from internal RAM to endpoint, if this one is available. + * When the transfer is finished or aborted (stall, reset, ...), the \a callback is called. + * The \a callback returns the transfer status and eventually the number of byte transfered. + * Note: The control endpoint is not authorized. + * + * \param ep The ID of the endpoint to use + * \param b_shortpacket Enabled automatic short packet + * \param buf Buffer on Internal RAM to send or fill. + * It must be align, then use COMPILER_WORD_ALIGNED. + * \param buf_size Buffer size to send or fill + * \param callback NULL or function to call at the end of transfer + * + * \warning About \a b_shortpacket, for IN endpoint it means that a short packet + * (or a Zero Length Packet) will be sent to the USB line to properly close the usb + * transfer at the end of the data transfer. + * For Bulk and Interrupt OUT endpoint, it will automatically stop the transfer + * at the end of the data transfer (received short packet). + * + * \return \c 1 if function was successfully done, otherwise \c 0. + */ +bool udd_ep_run(udd_ep_id_t ep, bool b_shortpacket, + uint8_t * buf, iram_size_t buf_size, + udd_callback_trans_t callback); +/** + * \brief Aborts transfer on going on endpoint + * + * If a transfer is on going, then it is stopped and + * the callback registered is called to signal the end of transfer. + * Note: The control endpoint is not authorized. + * + * \param ep Endpoint to abort + */ +void udd_ep_abort(udd_ep_id_t ep); + +#endif + +//@} + + +/** + * \name High speed test mode management + * + * The following functions allow the device to jump to a specific test mode required in high speed mode. + */ +//@{ +void udd_test_mode_j(void); +void udd_test_mode_k(void); +void udd_test_mode_se0_nak(void); +void udd_test_mode_packet(void); +//@} + + +/** + * \name UDC callbacks to provide for UDD + * + * The following callbacks are used by UDD. + */ +//@{ + +/** + * \brief Decodes and manages a setup request + * + * The driver call it when a SETUP packet is received. + * The \c udd_g_ctrlreq contains the data of SETUP packet. + * If this callback accepts the setup request then it must + * return \c 1 and eventually update \c udd_g_ctrlreq to send or receive data. + * + * \return \c 1 if the request is accepted, otherwise \c 0. + */ +extern bool udc_process_setup(void); + +/** + * \brief Reset the UDC + * + * The UDC must reset all configuration. + */ +extern void udc_reset(void); + +/** + * \brief To signal that a SOF is occurred + * + * The UDC must send the signal to all UDIs enabled + */ +extern void udc_sof_notify(void); + +//@} + +//@} + +#ifdef __cplusplus +} +#endif +#endif // _UDD_H_ diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/usb/udc/udi.h b/hw-libs/drivers/SAMx70/ASF/common/services/usb/udc/udi.h new file mode 100644 index 000000000..21e0fde63 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/usb/udc/udi.h @@ -0,0 +1,123 @@ +/** + * \file + * + * \brief Common API for USB Device Interface + * + * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _UDI_H_ +#define _UDI_H_ + +#include "conf_usb.h" +#include "usb_protocol.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \ingroup usb_device_group + * \defgroup udi_group USB Device Interface (UDI) + * The UDI provides a common API for all classes, + * and this is used by UDC for the main control of USB Device interface. + * @{ + */ + +/** + * \brief UDI API. + * + * The callbacks within this structure are called only by + * USB Device Controller (UDC) + * + * The udc_get_interface_desc() can be use by UDI to know the interface descriptor + * selected by UDC. + */ +typedef struct { + /** + * \brief Enable the interface. + * + * This function is called when the host selects a configuration + * to which this interface belongs through a Set Configuration + * request, and when the host selects an alternate setting of + * this interface through a Set Interface request. + * + * \return \c 1 if function was successfully done, otherwise \c 0. + */ + bool(*enable) (void); + + /** + * \brief Disable the interface. + * + * This function is called when this interface is currently + * active, and + * - the host selects any configuration through a Set + * Configuration request, or + * - the host issues a USB reset, or + * - the device is detached from the host (i.e. Vbus is no + * longer present) + */ + void (*disable) (void); + + /** + * \brief Handle a control request directed at an interface. + * + * This function is called when this interface is currently + * active and the host sends a SETUP request + * with this interface as the recipient. + * + * Use udd_g_ctrlreq to decode and response to SETUP request. + * + * \return \c 1 if this interface supports the SETUP request, otherwise \c 0. + */ + bool(*setup) (void); + + /** + * \brief Returns the current setting of the selected interface. + * + * This function is called when UDC when know alternate setting of selected interface. + * + * \return alternate setting of selected interface + */ + uint8_t(*getsetting) (void); + + /** + * \brief To signal that a SOF is occurred + */ + void(*sof_notify) (void); +} udi_api_t; + +//@} + +#ifdef __cplusplus +} +#endif +#endif // _UDI_H_ diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/usb/usb_atmel.h b/hw-libs/drivers/SAMx70/ASF/common/services/usb/usb_atmel.h new file mode 100644 index 000000000..c9dea0d6f --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/usb/usb_atmel.h @@ -0,0 +1,181 @@ +/** + * \file + * + * \brief All USB VIDs and PIDs from Atmel USB applications + * + * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _USB_ATMEL_H_ +#define _USB_ATMEL_H_ + +/** + * \defgroup usb_group USB Stack + * + * This stack includes the USB Device Stack, USB Host Stack and common + * definitions. + * @{ + */ + +//! @} + +/** + * \ingroup usb_group + * \defgroup usb_atmel_ids_group Atmel USB Identifiers + * + * This module defines Atmel PID and VIDs constants. + * + * @{ + */ + +//! \name Vendor Identifier assigned by USB org to ATMEL +#define USB_VID_ATMEL 0x03EB + + +//! \name Product Identifier assigned by ATMEL to AVR applications +//! @{ + +//! \name The range from 2000h to 20FFh is reserved to the old PID for C51, MEGA, and others. +//! @{ +#define USB_PID_ATMEL_MEGA_HIDGENERIC 0x2013 +#define USB_PID_ATMEL_MEGA_HIDKEYBOARD 0x2017 +#define USB_PID_ATMEL_MEGA_CDC 0x2018 +#define USB_PID_ATMEL_MEGA_AUDIO_IN 0x2019 +#define USB_PID_ATMEL_MEGA_MS 0x201A +#define USB_PID_ATMEL_MEGA_AUDIO_IN_OUT 0x201B +#define USB_PID_ATMEL_MEGA_HIDMOUSE 0x201C +#define USB_PID_ATMEL_MEGA_HIDMOUSE_CERTIF_U4 0x201D +#define USB_PID_ATMEL_MEGA_CDC_MULTI 0x201E +#define USB_PID_ATMEL_MEGA_MS_HIDMS_HID_USBKEY 0x2022 +#define USB_PID_ATMEL_MEGA_MS_HIDMS_HID_STK525 0x2023 +#define USB_PID_ATMEL_MEGA_MS_2 0x2029 +#define USB_PID_ATMEL_MEGA_MS_HIDMS 0x202A +#define USB_PID_ATMEL_MEGA_MS_3 0x2032 +#define USB_PID_ATMEL_MEGA_LIBUSB 0x2050 +//! @} + +//! \name The range 2100h to 21FFh is reserved to PIDs for AVR Tools. +//! @{ +#define USB_PID_ATMEL_XPLAINED 0x2122 +#define USB_PID_ATMEL_XMEGA_USB_ZIGBIT_2_4GHZ 0x214A +#define USB_PID_ATMEL_XMEGA_USB_ZIGBIT_SUBGHZ 0x214B +//! @} + +//! \name The range 2300h to 23FFh is reserved to PIDs for demo from ASF1.7=> +//! @{ +#define USB_PID_ATMEL_UC3_ENUM 0x2300 +#define USB_PID_ATMEL_UC3_MS 0x2301 +#define USB_PID_ATMEL_UC3_MS_SDRAM_LOADER 0x2302 +#define USB_PID_ATMEL_UC3_EVK1100_CTRLPANEL 0x2303 +#define USB_PID_ATMEL_UC3_HID 0x2304 +#define USB_PID_ATMEL_UC3_EVK1101_CTRLPANEL_HID 0x2305 +#define USB_PID_ATMEL_UC3_EVK1101_CTRLPANEL_HID_MS 0x2306 +#define USB_PID_ATMEL_UC3_CDC 0x2307 +#define USB_PID_ATMEL_UC3_AUDIO_MICRO 0x2308 +#define USB_PID_ATMEL_UC3_CDC_DEBUG 0x2310 // Virtual Com (debug interface) on EVK11xx +#define USB_PID_ATMEL_UC3_AUDIO_SPEAKER_MICRO 0x2311 +#define USB_PID_ATMEL_UC3_CDC_MSC 0x2312 +//! @} + +//! \name The range 2400h to 24FFh is reserved to PIDs for ASF applications +//! @{ +#define USB_PID_ATMEL_ASF_HIDMOUSE 0x2400 +#define USB_PID_ATMEL_ASF_HIDKEYBOARD 0x2401 +#define USB_PID_ATMEL_ASF_HIDGENERIC 0x2402 +#define USB_PID_ATMEL_ASF_MSC 0x2403 +#define USB_PID_ATMEL_ASF_CDC 0x2404 +#define USB_PID_ATMEL_ASF_PHDC 0x2405 +#define USB_PID_ATMEL_ASF_HIDMTOUCH 0x2406 +#define USB_PID_ATMEL_ASF_MSC_HIDMOUSE 0x2420 +#define USB_PID_ATMEL_ASF_MSC_HIDS_CDC 0x2421 +#define USB_PID_ATMEL_ASF_MSC_HIDKEYBOARD 0x2422 +#define USB_PID_ATMEL_ASF_VENDOR_CLASS 0x2423 +#define USB_PID_ATMEL_ASF_MSC_CDC 0x2424 +#define USB_PID_ATMEL_ASF_TWO_CDC 0x2425 +#define USB_PID_ATMEL_ASF_SEVEN_CDC 0x2426 +#define USB_PID_ATMEL_ASF_XPLAIN_BC_POWERONLY 0x2430 +#define USB_PID_ATMEL_ASF_XPLAIN_BC_TERMINAL 0x2431 +#define USB_PID_ATMEL_ASF_XPLAIN_BC_TOUCH 0x2432 +#define USB_PID_ATMEL_ASF_AUDIO_SPEAKER 0x2433 +#define USB_PID_ATMEL_ASF_XMEGA_B1_XPLAINED 0x2434 +//! @} + +//! \name The range 2F00h to 2FFFh is reserved to official PIDs for AVR bootloaders +//! Note, !!!! don't use this range for demos or examples !!!! +//! @{ +#define USB_PID_ATMEL_DFU_ATXMEGA64C3 0x2FD6 +#define USB_PID_ATMEL_DFU_ATXMEGA128C3 0x2FD7 +#define USB_PID_ATMEL_DFU_ATXMEGA16C4 0x2FD8 +#define USB_PID_ATMEL_DFU_ATXMEGA32C4 0x2FD9 +#define USB_PID_ATMEL_DFU_ATXMEGA256C3 0x2FDA +#define USB_PID_ATMEL_DFU_ATXMEGA384C3 0x2FDB +#define USB_PID_ATMEL_DFU_ATUCL3_L4 0x2FDC +#define USB_PID_ATMEL_DFU_ATXMEGA64A4U 0x2FDD +#define USB_PID_ATMEL_DFU_ATXMEGA128A4U 0x2FDE + +#define USB_PID_ATMEL_DFU_ATXMEGA64B3 0x2FDF +#define USB_PID_ATMEL_DFU_ATXMEGA128B3 0x2FE0 +#define USB_PID_ATMEL_DFU_ATXMEGA64B1 0x2FE1 +#define USB_PID_ATMEL_DFU_ATXMEGA256A3BU 0x2FE2 +#define USB_PID_ATMEL_DFU_ATXMEGA16A4U 0x2FE3 +#define USB_PID_ATMEL_DFU_ATXMEGA32A4U 0x2FE4 +#define USB_PID_ATMEL_DFU_ATXMEGA64A3U 0x2FE5 +#define USB_PID_ATMEL_DFU_ATXMEGA128A3U 0x2FE6 +#define USB_PID_ATMEL_DFU_ATXMEGA192A3U 0x2FE7 +#define USB_PID_ATMEL_DFU_ATXMEGA64A1U 0x2FE8 +#define USB_PID_ATMEL_DFU_ATUC3D 0x2FE9 +#define USB_PID_ATMEL_DFU_ATXMEGA128B1 0x2FEA +#define USB_PID_ATMEL_DFU_AT32UC3C 0x2FEB +#define USB_PID_ATMEL_DFU_ATXMEGA256A3U 0x2FEC +#define USB_PID_ATMEL_DFU_ATXMEGA128A1U 0x2FED +#define USB_PID_ATMEL_DFU_ATMEGA8U2 0x2FEE +#define USB_PID_ATMEL_DFU_ATMEGA16U2 0x2FEF +#define USB_PID_ATMEL_DFU_ATMEGA32U2 0x2FF0 +#define USB_PID_ATMEL_DFU_AT32UC3A3 0x2FF1 +#define USB_PID_ATMEL_DFU_ATMEGA32U6 0x2FF2 +#define USB_PID_ATMEL_DFU_ATMEGA16U4 0x2FF3 +#define USB_PID_ATMEL_DFU_ATMEGA32U4 0x2FF4 +#define USB_PID_ATMEL_DFU_AT32AP7200 0x2FF5 +#define USB_PID_ATMEL_DFU_AT32UC3B 0x2FF6 +#define USB_PID_ATMEL_DFU_AT90USB82 0x2FF7 +#define USB_PID_ATMEL_DFU_AT32UC3A 0x2FF8 +#define USB_PID_ATMEL_DFU_AT90USB64 0x2FF9 +#define USB_PID_ATMEL_DFU_AT90USB162 0x2FFA +#define USB_PID_ATMEL_DFU_AT90USB128 0x2FFB +// 2FFCh to 2FFFh used by C51 family products +//! @} + +//! @} + +//! @} + + +#endif // _USB_ATMEL_H_ diff --git a/hw-libs/drivers/SAMx70/ASF/common/services/usb/usb_protocol.h b/hw-libs/drivers/SAMx70/ASF/common/services/usb/usb_protocol.h new file mode 100644 index 000000000..bb65e5679 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/services/usb/usb_protocol.h @@ -0,0 +1,488 @@ +/** + * \file + * + * \brief USB protocol definitions. + * + * This file contains the USB definitions and data structures provided by the + * USB 2.0 specification. + * + * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _USB_PROTOCOL_H_ +#define _USB_PROTOCOL_H_ + +#include "usb_atmel.h" + +/** + * \ingroup usb_group + * \defgroup usb_protocol_group USB Protocol Definitions + * + * This module defines constants and data structures provided by the USB + * 2.0 specification. + * + * @{ + */ + +//! Value for field bcdUSB +#define USB_V2_0 0x0200 //!< USB Specification version 2.00 +#define USB_V2_1 0x0201 //!< USB Specification version 2.01 + +/*! \name Generic definitions (Class, subclass and protocol) + */ +//! @{ +#define NO_CLASS 0x00 +#define CLASS_VENDOR_SPECIFIC 0xFF +#define NO_SUBCLASS 0x00 +#define NO_PROTOCOL 0x00 +//! @} + +//! \name IAD (Interface Association Descriptor) constants +//! @{ +#define CLASS_IAD 0xEF +#define SUB_CLASS_IAD 0x02 +#define PROTOCOL_IAD 0x01 +//! @} + +/** + * \brief USB request data transfer direction (bmRequestType) + */ +#define USB_REQ_DIR_OUT (0<<7) //!< Host to device +#define USB_REQ_DIR_IN (1<<7) //!< Device to host +#define USB_REQ_DIR_MASK (1<<7) //!< Mask + +/** + * \brief USB request types (bmRequestType) + */ +#define USB_REQ_TYPE_STANDARD (0<<5) //!< Standard request +#define USB_REQ_TYPE_CLASS (1<<5) //!< Class-specific request +#define USB_REQ_TYPE_VENDOR (2<<5) //!< Vendor-specific request +#define USB_REQ_TYPE_MASK (3<<5) //!< Mask + +/** + * \brief USB recipient codes (bmRequestType) + */ +#define USB_REQ_RECIP_DEVICE (0<<0) //!< Recipient device +#define USB_REQ_RECIP_INTERFACE (1<<0) //!< Recipient interface +#define USB_REQ_RECIP_ENDPOINT (2<<0) //!< Recipient endpoint +#define USB_REQ_RECIP_OTHER (3<<0) //!< Recipient other +#define USB_REQ_RECIP_MASK (0x1F) //!< Mask + +/** + * \brief Standard USB requests (bRequest) + */ +enum usb_reqid { + USB_REQ_GET_STATUS = 0, + USB_REQ_CLEAR_FEATURE = 1, + USB_REQ_SET_FEATURE = 3, + USB_REQ_SET_ADDRESS = 5, + USB_REQ_GET_DESCRIPTOR = 6, + USB_REQ_SET_DESCRIPTOR = 7, + USB_REQ_GET_CONFIGURATION = 8, + USB_REQ_SET_CONFIGURATION = 9, + USB_REQ_GET_INTERFACE = 10, + USB_REQ_SET_INTERFACE = 11, + USB_REQ_SYNCH_FRAME = 12, +}; + +/** + * \brief Standard USB device status flags + * + */ +enum usb_device_status { + USB_DEV_STATUS_BUS_POWERED = 0, + USB_DEV_STATUS_SELF_POWERED = 1, + USB_DEV_STATUS_REMOTEWAKEUP = 2 +}; + +/** + * \brief Standard USB Interface status flags + * + */ +enum usb_interface_status { + USB_IFACE_STATUS_RESERVED = 0 +}; + +/** + * \brief Standard USB endpoint status flags + * + */ +enum usb_endpoint_status { + USB_EP_STATUS_HALTED = 1, +}; + +/** + * \brief Standard USB device feature flags + * + * \note valid for SetFeature request. + */ +enum usb_device_feature { + USB_DEV_FEATURE_REMOTE_WAKEUP = 1, //!< Remote wakeup enabled + USB_DEV_FEATURE_TEST_MODE = 2, //!< USB test mode + USB_DEV_FEATURE_OTG_B_HNP_ENABLE = 3, + USB_DEV_FEATURE_OTG_A_HNP_SUPPORT = 4, + USB_DEV_FEATURE_OTG_A_ALT_HNP_SUPPORT = 5 +}; + +/** + * \brief Test Mode possible on HS USB device + * + * \note valid for USB_DEV_FEATURE_TEST_MODE request. + */ +enum usb_device_hs_test_mode { + USB_DEV_TEST_MODE_J = 1, + USB_DEV_TEST_MODE_K = 2, + USB_DEV_TEST_MODE_SE0_NAK = 3, + USB_DEV_TEST_MODE_PACKET = 4, + USB_DEV_TEST_MODE_FORCE_ENABLE = 5, +}; + +/** + * \brief Standard USB endpoint feature/status flags + */ +enum usb_endpoint_feature { + USB_EP_FEATURE_HALT = 0, +}; + +/** + * \brief Standard USB Test Mode Selectors + */ +enum usb_test_mode_selector { + USB_TEST_J = 0x01, + USB_TEST_K = 0x02, + USB_TEST_SE0_NAK = 0x03, + USB_TEST_PACKET = 0x04, + USB_TEST_FORCE_ENABLE = 0x05, +}; + +/** + * \brief Standard USB descriptor types + */ +enum usb_descriptor_type { + USB_DT_DEVICE = 1, + USB_DT_CONFIGURATION = 2, + USB_DT_STRING = 3, + USB_DT_INTERFACE = 4, + USB_DT_ENDPOINT = 5, + USB_DT_DEVICE_QUALIFIER = 6, + USB_DT_OTHER_SPEED_CONFIGURATION = 7, + USB_DT_INTERFACE_POWER = 8, + USB_DT_OTG = 9, + USB_DT_IAD = 0x0B, + USB_DT_BOS = 0x0F, + USB_DT_DEVICE_CAPABILITY = 0x10, +}; + +/** + * \brief USB Device Capability types + */ +enum usb_capability_type { + USB_DC_USB20_EXTENSION = 0x02, +}; + +/** + * \brief USB Device Capability - USB 2.0 Extension + * To fill bmAttributes field of usb_capa_ext_desc_t structure. + */ +enum usb_capability_extension_attr { + USB_DC_EXT_LPM = 0x00000002, +}; + +#define HIRD_50_US 0 +#define HIRD_125_US 1 +#define HIRD_200_US 2 +#define HIRD_275_US 3 +#define HIRD_350_US 4 +#define HIRD_425_US 5 +#define HIRD_500_US 6 +#define HIRD_575_US 7 +#define HIRD_650_US 8 +#define HIRD_725_US 9 +#define HIRD_800_US 10 +#define HIRD_875_US 11 +#define HIRD_950_US 12 +#define HIRD_1025_US 13 +#define HIRD_1100_US 14 +#define HIRD_1175_US 15 + +/** Fields definition from a LPM TOKEN */ +#define USB_LPM_ATTRIBUT_BLINKSTATE_MASK (0xF << 0) +#define USB_LPM_ATTRIBUT_FIRD_MASK (0xF << 4) +#define USB_LPM_ATTRIBUT_REMOTEWAKE_MASK (1 << 8) +#define USB_LPM_ATTRIBUT_BLINKSTATE(value) ((value & 0xF) << 0) +#define USB_LPM_ATTRIBUT_FIRD(value) ((value & 0xF) << 4) +#define USB_LPM_ATTRIBUT_REMOTEWAKE(value) ((value & 1) << 8) +#define USB_LPM_ATTRIBUT_BLINKSTATE_L1 USB_LPM_ATTRIBUT_BLINKSTATE(1) + +/** + * \brief Standard USB endpoint transfer types + */ +enum usb_ep_type { + USB_EP_TYPE_CONTROL = 0x00, + USB_EP_TYPE_ISOCHRONOUS = 0x01, + USB_EP_TYPE_BULK = 0x02, + USB_EP_TYPE_INTERRUPT = 0x03, + USB_EP_TYPE_MASK = 0x03, +}; + +/** + * \brief Standard USB language IDs for string descriptors + */ +enum usb_langid { + USB_LANGID_EN_US = 0x0409, //!< English (United States) +}; + +/** + * \brief Mask selecting the index part of an endpoint address + */ +#define USB_EP_ADDR_MASK 0x0f + +//! \brief USB address identifier +typedef uint8_t usb_add_t; + +/** + * \brief Endpoint transfer direction is IN + */ +#define USB_EP_DIR_IN 0x80 + +/** + * \brief Endpoint transfer direction is OUT + */ +#define USB_EP_DIR_OUT 0x00 + +//! \brief Endpoint identifier +typedef uint8_t usb_ep_t; + +/** + * \brief Maximum length in bytes of a USB descriptor + * + * The maximum length of a USB descriptor is limited by the 8-bit + * bLength field. + */ +#define USB_MAX_DESC_LEN 255 + +/* + * 2-byte alignment requested for all USB structures. + */ +COMPILER_PACK_SET(1) + +/** + * \brief A USB Device SETUP request + * + * The data payload of SETUP packets always follows this structure. + */ +typedef struct { + uint8_t bmRequestType; + uint8_t bRequest; + le16_t wValue; + le16_t wIndex; + le16_t wLength; +} usb_setup_req_t; + +/** + * \brief Standard USB device descriptor structure + */ +typedef struct { + uint8_t bLength; + uint8_t bDescriptorType; + le16_t bcdUSB; + uint8_t bDeviceClass; + uint8_t bDeviceSubClass; + uint8_t bDeviceProtocol; + uint8_t bMaxPacketSize0; + le16_t idVendor; + le16_t idProduct; + le16_t bcdDevice; + uint8_t iManufacturer; + uint8_t iProduct; + uint8_t iSerialNumber; + uint8_t bNumConfigurations; +} usb_dev_desc_t; + +/** + * \brief Standard USB device qualifier descriptor structure + * + * This descriptor contains information about the device when running at + * the "other" speed (i.e. if the device is currently operating at high + * speed, this descriptor can be used to determine what would change if + * the device was operating at full speed.) + */ +typedef struct { + uint8_t bLength; + uint8_t bDescriptorType; + le16_t bcdUSB; + uint8_t bDeviceClass; + uint8_t bDeviceSubClass; + uint8_t bDeviceProtocol; + uint8_t bMaxPacketSize0; + uint8_t bNumConfigurations; + uint8_t bReserved; +} usb_dev_qual_desc_t; + +/** + * \brief USB Device BOS descriptor structure + * + * The BOS descriptor (Binary device Object Store) defines a root + * descriptor that is similar to the configuration descriptor, and is + * the base descriptor for accessing a family of related descriptors. + * A host can read a BOS descriptor and learn from the wTotalLength field + * the entire size of the device-level descriptor set, or it can read in + * the entire BOS descriptor set of device capabilities. + * The host accesses this descriptor using the GetDescriptor() request. + * The descriptor type in the GetDescriptor() request is set to BOS. + */ +typedef struct { + uint8_t bLength; + uint8_t bDescriptorType; + le16_t wTotalLength; + uint8_t bNumDeviceCaps; +} usb_dev_bos_desc_t; + + +/** + * \brief USB Device Capabilities - USB 2.0 Extension Descriptor structure + * + * Defines the set of USB 1.1-specific device level capabilities. + */ +typedef struct { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDevCapabilityType; + le32_t bmAttributes; +} usb_dev_capa_ext_desc_t; + +/** + * \brief USB Device LPM Descriptor structure + * + * The BOS descriptor and capabilities descriptors for LPM. + */ +typedef struct { + usb_dev_bos_desc_t bos; + usb_dev_capa_ext_desc_t capa_ext; +} usb_dev_lpm_desc_t; + +/** + * \brief Standard USB Interface Association Descriptor structure + */ +typedef struct { + uint8_t bLength; //!< size of this descriptor in bytes + uint8_t bDescriptorType; //!< INTERFACE descriptor type + uint8_t bFirstInterface; //!< Number of interface + uint8_t bInterfaceCount; //!< value to select alternate setting + uint8_t bFunctionClass; //!< Class code assigned by the USB + uint8_t bFunctionSubClass;//!< Sub-class code assigned by the USB + uint8_t bFunctionProtocol;//!< Protocol code assigned by the USB + uint8_t iFunction; //!< Index of string descriptor +} usb_association_desc_t; + + +/** + * \brief Standard USB configuration descriptor structure + */ +typedef struct { + uint8_t bLength; + uint8_t bDescriptorType; + le16_t wTotalLength; + uint8_t bNumInterfaces; + uint8_t bConfigurationValue; + uint8_t iConfiguration; + uint8_t bmAttributes; + uint8_t bMaxPower; +} usb_conf_desc_t; + + +#define USB_CONFIG_ATTR_MUST_SET (1 << 7) //!< Must always be set +#define USB_CONFIG_ATTR_BUS_POWERED (0 << 6) //!< Bus-powered +#define USB_CONFIG_ATTR_SELF_POWERED (1 << 6) //!< Self-powered +#define USB_CONFIG_ATTR_REMOTE_WAKEUP (1 << 5) //!< remote wakeup supported + +#define USB_CONFIG_MAX_POWER(ma) (((ma) + 1) / 2) //!< Max power in mA + +/** + * \brief Standard USB association descriptor structure + */ +typedef struct { + uint8_t bLength; //!< Size of this descriptor in bytes + uint8_t bDescriptorType; //!< Interface descriptor type + uint8_t bFirstInterface; //!< Number of interface + uint8_t bInterfaceCount; //!< value to select alternate setting + uint8_t bFunctionClass; //!< Class code assigned by the USB + uint8_t bFunctionSubClass; //!< Sub-class code assigned by the USB + uint8_t bFunctionProtocol; //!< Protocol code assigned by the USB + uint8_t iFunction; //!< Index of string descriptor +} usb_iad_desc_t; + +/** + * \brief Standard USB interface descriptor structure + */ +typedef struct { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bInterfaceNumber; + uint8_t bAlternateSetting; + uint8_t bNumEndpoints; + uint8_t bInterfaceClass; + uint8_t bInterfaceSubClass; + uint8_t bInterfaceProtocol; + uint8_t iInterface; +} usb_iface_desc_t; + +/** + * \brief Standard USB endpoint descriptor structure + */ +typedef struct { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; + uint8_t bmAttributes; + le16_t wMaxPacketSize; + uint8_t bInterval; +} usb_ep_desc_t; + + +/** + * \brief A standard USB string descriptor structure + */ +typedef struct { + uint8_t bLength; + uint8_t bDescriptorType; +} usb_str_desc_t; + +typedef struct { + usb_str_desc_t desc; + le16_t string[1]; +} usb_str_lgid_desc_t; + +COMPILER_PACK_RESET() + +//! @} + +#endif /* _USB_PROTOCOL_H_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/utils/interrupt.h b/hw-libs/drivers/SAMx70/ASF/common/utils/interrupt.h new file mode 100644 index 000000000..450d0f991 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/utils/interrupt.h @@ -0,0 +1,132 @@ +/** + * \file + * + * \brief Global interrupt management for 8- and 32-bit AVR + * + * Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef UTILS_INTERRUPT_H +#define UTILS_INTERRUPT_H + +#include + +#if XMEGA || MEGA +# include "interrupt/interrupt_avr8.h" +#elif UC3 +# include "interrupt/interrupt_avr32.h" +#elif SAM || SAMB +# include "interrupt/interrupt_sam_nvic.h" +#else +# error Unsupported device. +#endif + +/** + * \defgroup interrupt_group Global interrupt management + * + * This is a driver for global enabling and disabling of interrupts. + * + * @{ + */ + +#if defined(__DOXYGEN__) +/** + * \def CONFIG_INTERRUPT_FORCE_INTC + * \brief Force usage of the ASF INTC driver + * + * Predefine this symbol when preprocessing to force the use of the ASF INTC driver. + * This is useful to ensure compatibility across compilers and shall be used only when required + * by the application needs. + */ +# define CONFIG_INTERRUPT_FORCE_INTC +#endif + +//! \name Global interrupt flags +//@{ +/** + * \typedef irqflags_t + * \brief Type used for holding state of interrupt flag + */ + +/** + * \def cpu_irq_enable + * \brief Enable interrupts globally + */ + +/** + * \def cpu_irq_disable + * \brief Disable interrupts globally + */ + +/** + * \fn irqflags_t cpu_irq_save(void) + * \brief Get and clear the global interrupt flags + * + * Use in conjunction with \ref cpu_irq_restore. + * + * \return Current state of interrupt flags. + * + * \note This function leaves interrupts disabled. + */ + +/** + * \fn void cpu_irq_restore(irqflags_t flags) + * \brief Restore global interrupt flags + * + * Use in conjunction with \ref cpu_irq_save. + * + * \param flags State to set interrupt flag to. + */ + +/** + * \fn bool cpu_irq_is_enabled_flags(irqflags_t flags) + * \brief Check if interrupts are globally enabled in supplied flags + * + * \param flags Currents state of interrupt flags. + * + * \return True if interrupts are enabled. + */ + +/** + * \def cpu_irq_is_enabled + * \brief Check if interrupts are globally enabled + * + * \return True if interrupts are enabled. + */ +//@} + +//! @} + +/** + * \ingroup interrupt_group + * \defgroup interrupt_deprecated_group Deprecated interrupt definitions + */ + +#endif /* UTILS_INTERRUPT_H */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/utils/interrupt/interrupt_sam_nvic.c b/hw-libs/drivers/SAMx70/ASF/common/utils/interrupt/interrupt_sam_nvic.c new file mode 100644 index 000000000..269b4cea3 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/utils/interrupt/interrupt_sam_nvic.c @@ -0,0 +1,76 @@ +/** + * \file + * + * \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based) + * + * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "interrupt_sam_nvic.h" + +#if !defined(__DOXYGEN__) +/* Deprecated - global flag to determine the global interrupt state. Required by + * QTouch library, however new applications should use cpu_irq_is_enabled() + * which probes the true global interrupt state from the CPU special registers. + */ +volatile bool g_interrupt_enabled = true; +#endif + +void cpu_irq_enter_critical(void) +{ + if (cpu_irq_critical_section_counter == 0) { + if (cpu_irq_is_enabled()) { + cpu_irq_disable(); + cpu_irq_prev_interrupt_state = true; + } else { + /* Make sure the to save the prev state as false */ + cpu_irq_prev_interrupt_state = false; + } + + } + + cpu_irq_critical_section_counter++; +} + +void cpu_irq_leave_critical(void) +{ + /* Check if the user is trying to leave a critical section when not in a critical section */ + Assert(cpu_irq_critical_section_counter > 0); + + cpu_irq_critical_section_counter--; + + /* Only enable global interrupts when the counter reaches 0 and the state of the global interrupt flag + was enabled when entering critical state */ + if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) { + cpu_irq_enable(); + } +} + diff --git a/hw-libs/drivers/SAMx70/ASF/common/utils/interrupt/interrupt_sam_nvic.h b/hw-libs/drivers/SAMx70/ASF/common/utils/interrupt/interrupt_sam_nvic.h new file mode 100644 index 000000000..7d215cf6e --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/utils/interrupt/interrupt_sam_nvic.h @@ -0,0 +1,179 @@ +/** + * \file + * + * \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based) + * + * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef UTILS_INTERRUPT_INTERRUPT_H +#define UTILS_INTERRUPT_INTERRUPT_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \weakgroup interrupt_group + * + * @{ + */ + +/** + * \name Interrupt Service Routine definition + * + * @{ + */ + +/** + * \brief Define service routine + * + * \note For NVIC devices the interrupt service routines are predefined to + * add to vector table in binary generation, so there is no service + * register at run time. The routine collections are in exceptions.h. + * + * Usage: + * \code + ISR(foo_irq_handler) + { + // Function definition + ... + } +\endcode + * + * \param func Name for the function. + */ +# define ISR(func) \ + void func (void) + +/** + * \brief Initialize interrupt vectors + * + * For NVIC the interrupt vectors are put in vector table. So nothing + * to do to initialize them, except defined the vector function with + * right name. + * + * This must be called prior to \ref irq_register_handler. + */ +# define irq_initialize_vectors() \ + do { \ + } while(0) + +/** + * \brief Register handler for interrupt + * + * For NVIC the interrupt vectors are put in vector table. So nothing + * to do to register them, except defined the vector function with + * right name. + * + * Usage: + * \code + irq_initialize_vectors(); + irq_register_handler(foo_irq_handler); +\endcode + * + * \note The function \a func must be defined with the \ref ISR macro. + * \note The functions prototypes can be found in the device exception header + * files (exceptions.h). + */ +# define irq_register_handler(int_num, int_prio) \ + NVIC_ClearPendingIRQ( (IRQn_Type)int_num); \ + NVIC_SetPriority( (IRQn_Type)int_num, int_prio); \ + NVIC_EnableIRQ( (IRQn_Type)int_num); \ + +//@} + +# define cpu_irq_enable() \ + do { \ + g_interrupt_enabled = true; \ + __DMB(); \ + __enable_irq(); \ + } while (0) +# define cpu_irq_disable() \ + do { \ + __disable_irq(); \ + __DMB(); \ + g_interrupt_enabled = false; \ + } while (0) + +typedef uint32_t irqflags_t; + +#if !defined(__DOXYGEN__) +extern volatile bool g_interrupt_enabled; +#endif + +#define cpu_irq_is_enabled() (__get_PRIMASK() == 0) + +static volatile uint32_t cpu_irq_critical_section_counter; +static volatile bool cpu_irq_prev_interrupt_state; + +static inline irqflags_t cpu_irq_save(void) +{ + volatile irqflags_t flags = cpu_irq_is_enabled(); + cpu_irq_disable(); + return flags; +} + +static inline bool cpu_irq_is_enabled_flags(irqflags_t flags) +{ + return (flags); +} + +static inline void cpu_irq_restore(irqflags_t flags) +{ + if (cpu_irq_is_enabled_flags(flags)) + cpu_irq_enable(); +} + +void cpu_irq_enter_critical(void); +void cpu_irq_leave_critical(void); + +/** + * \weakgroup interrupt_deprecated_group + * @{ + */ + +#define Enable_global_interrupt() cpu_irq_enable() +#define Disable_global_interrupt() cpu_irq_disable() +#define Is_global_interrupt_enabled() cpu_irq_is_enabled() + +//@} + +//@} + +#ifdef __cplusplus +} +#endif + +#endif /* UTILS_INTERRUPT_INTERRUPT_H */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/utils/parts.h b/hw-libs/drivers/SAMx70/ASF/common/utils/parts.h new file mode 100644 index 000000000..1c147bf70 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/utils/parts.h @@ -0,0 +1,1754 @@ +/** + * \file + * + * \brief Atmel part identification macros + * + * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef ATMEL_PARTS_H +#define ATMEL_PARTS_H + +/** + * \defgroup part_macros_group Atmel part identification macros + * + * This collection of macros identify which series and families that the various + * Atmel parts belong to. These can be used to select part-dependent sections of + * code at compile time. + * + * @{ + */ + +/** + * \name Convenience macros for part checking + * @{ + */ +/* ! Check GCC and IAR part definition for 8-bit AVR */ +#define AVR8_PART_IS_DEFINED(part) \ + (defined(__ ## part ## __) || defined(__AVR_ ## part ## __)) + +/* ! Check GCC and IAR part definition for 32-bit AVR */ +#define AVR32_PART_IS_DEFINED(part) \ + (defined(__AT32 ## part ## __) || defined(__AVR32_ ## part ## __)) + +/* ! Check GCC and IAR part definition for SAM */ +#define SAM_PART_IS_DEFINED(part) (defined(__ ## part ## __)) +/** @} */ + +/** + * \defgroup uc3_part_macros_group AVR UC3 parts + * @{ + */ + +/** + * \name AVR UC3 A series + * @{ + */ +#define UC3A0 ( \ + AVR32_PART_IS_DEFINED(UC3A0128) || \ + AVR32_PART_IS_DEFINED(UC3A0256) || \ + AVR32_PART_IS_DEFINED(UC3A0512) \ + ) + +#define UC3A1 ( \ + AVR32_PART_IS_DEFINED(UC3A1128) || \ + AVR32_PART_IS_DEFINED(UC3A1256) || \ + AVR32_PART_IS_DEFINED(UC3A1512) \ + ) + +#define UC3A3 ( \ + AVR32_PART_IS_DEFINED(UC3A364) || \ + AVR32_PART_IS_DEFINED(UC3A364S) || \ + AVR32_PART_IS_DEFINED(UC3A3128) || \ + AVR32_PART_IS_DEFINED(UC3A3128S) || \ + AVR32_PART_IS_DEFINED(UC3A3256) || \ + AVR32_PART_IS_DEFINED(UC3A3256S) \ + ) + +#define UC3A4 ( \ + AVR32_PART_IS_DEFINED(UC3A464) || \ + AVR32_PART_IS_DEFINED(UC3A464S) || \ + AVR32_PART_IS_DEFINED(UC3A4128) || \ + AVR32_PART_IS_DEFINED(UC3A4128S) || \ + AVR32_PART_IS_DEFINED(UC3A4256) || \ + AVR32_PART_IS_DEFINED(UC3A4256S) \ + ) +/** @} */ + +/** + * \name AVR UC3 B series + * @{ + */ +#define UC3B0 ( \ + AVR32_PART_IS_DEFINED(UC3B064) || \ + AVR32_PART_IS_DEFINED(UC3B0128) || \ + AVR32_PART_IS_DEFINED(UC3B0256) || \ + AVR32_PART_IS_DEFINED(UC3B0512) \ + ) + +#define UC3B1 ( \ + AVR32_PART_IS_DEFINED(UC3B164) || \ + AVR32_PART_IS_DEFINED(UC3B1128) || \ + AVR32_PART_IS_DEFINED(UC3B1256) || \ + AVR32_PART_IS_DEFINED(UC3B1512) \ + ) +/** @} */ + +/** + * \name AVR UC3 C series + * @{ + */ +#define UC3C0 ( \ + AVR32_PART_IS_DEFINED(UC3C064C) || \ + AVR32_PART_IS_DEFINED(UC3C0128C) || \ + AVR32_PART_IS_DEFINED(UC3C0256C) || \ + AVR32_PART_IS_DEFINED(UC3C0512C) \ + ) + +#define UC3C1 ( \ + AVR32_PART_IS_DEFINED(UC3C164C) || \ + AVR32_PART_IS_DEFINED(UC3C1128C) || \ + AVR32_PART_IS_DEFINED(UC3C1256C) || \ + AVR32_PART_IS_DEFINED(UC3C1512C) \ + ) + +#define UC3C2 ( \ + AVR32_PART_IS_DEFINED(UC3C264C) || \ + AVR32_PART_IS_DEFINED(UC3C2128C) || \ + AVR32_PART_IS_DEFINED(UC3C2256C) || \ + AVR32_PART_IS_DEFINED(UC3C2512C) \ + ) +/** @} */ + +/** + * \name AVR UC3 D series + * @{ + */ +#define UC3D3 ( \ + AVR32_PART_IS_DEFINED(UC64D3) || \ + AVR32_PART_IS_DEFINED(UC128D3) \ + ) + +#define UC3D4 ( \ + AVR32_PART_IS_DEFINED(UC64D4) || \ + AVR32_PART_IS_DEFINED(UC128D4) \ + ) +/** @} */ + +/** + * \name AVR UC3 L series + * @{ + */ +#define UC3L0 ( \ + AVR32_PART_IS_DEFINED(UC3L016) || \ + AVR32_PART_IS_DEFINED(UC3L032) || \ + AVR32_PART_IS_DEFINED(UC3L064) \ + ) + +#define UC3L0128 ( \ + AVR32_PART_IS_DEFINED(UC3L0128) \ + ) + +#define UC3L0256 ( \ + AVR32_PART_IS_DEFINED(UC3L0256) \ + ) + +#define UC3L3 ( \ + AVR32_PART_IS_DEFINED(UC64L3U) || \ + AVR32_PART_IS_DEFINED(UC128L3U) || \ + AVR32_PART_IS_DEFINED(UC256L3U) \ + ) + +#define UC3L4 ( \ + AVR32_PART_IS_DEFINED(UC64L4U) || \ + AVR32_PART_IS_DEFINED(UC128L4U) || \ + AVR32_PART_IS_DEFINED(UC256L4U) \ + ) + +#define UC3L3_L4 (UC3L3 || UC3L4) +/** @} */ + +/** + * \name AVR UC3 families + * @{ + */ +/** AVR UC3 A family */ +#define UC3A (UC3A0 || UC3A1 || UC3A3 || UC3A4) + +/** AVR UC3 B family */ +#define UC3B (UC3B0 || UC3B1) + +/** AVR UC3 C family */ +#define UC3C (UC3C0 || UC3C1 || UC3C2) + +/** AVR UC3 D family */ +#define UC3D (UC3D3 || UC3D4) + +/** AVR UC3 L family */ +#define UC3L (UC3L0 || UC3L0128 || UC3L0256 || UC3L3_L4) +/** @} */ + +/** AVR UC3 product line */ +#define UC3 (UC3A || UC3B || UC3C || UC3D || UC3L) + +/** @} */ + +/** + * \defgroup xmega_part_macros_group AVR XMEGA parts + * @{ + */ + +/** + * \name AVR XMEGA A series + * @{ + */ +#define XMEGA_A1 ( \ + AVR8_PART_IS_DEFINED(ATxmega64A1) || \ + AVR8_PART_IS_DEFINED(ATxmega128A1) \ + ) + +#define XMEGA_A3 ( \ + AVR8_PART_IS_DEFINED(ATxmega64A3) || \ + AVR8_PART_IS_DEFINED(ATxmega128A3) || \ + AVR8_PART_IS_DEFINED(ATxmega192A3) || \ + AVR8_PART_IS_DEFINED(ATxmega256A3) \ + ) + +#define XMEGA_A3B ( \ + AVR8_PART_IS_DEFINED(ATxmega256A3B) \ + ) + +#define XMEGA_A4 ( \ + AVR8_PART_IS_DEFINED(ATxmega16A4) || \ + AVR8_PART_IS_DEFINED(ATxmega32A4) \ + ) +/** @} */ + +/** + * \name AVR XMEGA AU series + * @{ + */ +#define XMEGA_A1U ( \ + AVR8_PART_IS_DEFINED(ATxmega64A1U) || \ + AVR8_PART_IS_DEFINED(ATxmega128A1U) \ + ) + +#define XMEGA_A3U ( \ + AVR8_PART_IS_DEFINED(ATxmega64A3U) || \ + AVR8_PART_IS_DEFINED(ATxmega128A3U) || \ + AVR8_PART_IS_DEFINED(ATxmega192A3U) || \ + AVR8_PART_IS_DEFINED(ATxmega256A3U) \ + ) + +#define XMEGA_A3BU ( \ + AVR8_PART_IS_DEFINED(ATxmega256A3BU) \ + ) + +#define XMEGA_A4U ( \ + AVR8_PART_IS_DEFINED(ATxmega16A4U) || \ + AVR8_PART_IS_DEFINED(ATxmega32A4U) || \ + AVR8_PART_IS_DEFINED(ATxmega64A4U) || \ + AVR8_PART_IS_DEFINED(ATxmega128A4U) \ + ) +/** @} */ + +/** + * \name AVR XMEGA B series + * @{ + */ +#define XMEGA_B1 ( \ + AVR8_PART_IS_DEFINED(ATxmega64B1) || \ + AVR8_PART_IS_DEFINED(ATxmega128B1) \ + ) + +#define XMEGA_B3 ( \ + AVR8_PART_IS_DEFINED(ATxmega64B3) || \ + AVR8_PART_IS_DEFINED(ATxmega128B3) \ + ) +/** @} */ + +/** + * \name AVR XMEGA C series + * @{ + */ +#define XMEGA_C3 ( \ + AVR8_PART_IS_DEFINED(ATxmega384C3) || \ + AVR8_PART_IS_DEFINED(ATxmega256C3) || \ + AVR8_PART_IS_DEFINED(ATxmega192C3) || \ + AVR8_PART_IS_DEFINED(ATxmega128C3) || \ + AVR8_PART_IS_DEFINED(ATxmega64C3) || \ + AVR8_PART_IS_DEFINED(ATxmega32C3) \ + ) + +#define XMEGA_C4 ( \ + AVR8_PART_IS_DEFINED(ATxmega32C4) || \ + AVR8_PART_IS_DEFINED(ATxmega16C4) \ + ) +/** @} */ + +/** + * \name AVR XMEGA D series + * @{ + */ +#define XMEGA_D3 ( \ + AVR8_PART_IS_DEFINED(ATxmega32D3) || \ + AVR8_PART_IS_DEFINED(ATxmega64D3) || \ + AVR8_PART_IS_DEFINED(ATxmega128D3) || \ + AVR8_PART_IS_DEFINED(ATxmega192D3) || \ + AVR8_PART_IS_DEFINED(ATxmega256D3) || \ + AVR8_PART_IS_DEFINED(ATxmega384D3) \ + ) + +#define XMEGA_D4 ( \ + AVR8_PART_IS_DEFINED(ATxmega16D4) || \ + AVR8_PART_IS_DEFINED(ATxmega32D4) || \ + AVR8_PART_IS_DEFINED(ATxmega64D4) || \ + AVR8_PART_IS_DEFINED(ATxmega128D4) \ + ) +/** @} */ + +/** + * \name AVR XMEGA E series + * @{ + */ +#define XMEGA_E5 ( \ + AVR8_PART_IS_DEFINED(ATxmega8E5) || \ + AVR8_PART_IS_DEFINED(ATxmega16E5) || \ + AVR8_PART_IS_DEFINED(ATxmega32E5) \ + ) +/** @} */ + + +/** + * \name AVR XMEGA families + * @{ + */ +/** AVR XMEGA A family */ +#define XMEGA_A (XMEGA_A1 || XMEGA_A3 || XMEGA_A3B || XMEGA_A4) + +/** AVR XMEGA AU family */ +#define XMEGA_AU (XMEGA_A1U || XMEGA_A3U || XMEGA_A3BU || XMEGA_A4U) + +/** AVR XMEGA B family */ +#define XMEGA_B (XMEGA_B1 || XMEGA_B3) + +/** AVR XMEGA C family */ +#define XMEGA_C (XMEGA_C3 || XMEGA_C4) + +/** AVR XMEGA D family */ +#define XMEGA_D (XMEGA_D3 || XMEGA_D4) + +/** AVR XMEGA E family */ +#define XMEGA_E (XMEGA_E5) +/** @} */ + + +/** AVR XMEGA product line */ +#define XMEGA (XMEGA_A || XMEGA_AU || XMEGA_B || XMEGA_C || XMEGA_D || XMEGA_E) + +/** @} */ + +/** + * \defgroup mega_part_macros_group megaAVR parts + * + * \note These megaAVR groupings are based on the groups in AVR Libc for the + * part header files. They are not names of official megaAVR device series or + * families. + * + * @{ + */ + +/** + * \name ATmegaxx0/xx1 subgroups + * @{ + */ +#define MEGA_XX0 ( \ + AVR8_PART_IS_DEFINED(ATmega640) || \ + AVR8_PART_IS_DEFINED(ATmega1280) || \ + AVR8_PART_IS_DEFINED(ATmega2560) \ + ) + +#define MEGA_XX1 ( \ + AVR8_PART_IS_DEFINED(ATmega1281) || \ + AVR8_PART_IS_DEFINED(ATmega2561) \ + ) +/** @} */ + +/** + * \name megaAVR groups + * @{ + */ +/** ATmegaxx0/xx1 group */ +#define MEGA_XX0_1 (MEGA_XX0 || MEGA_XX1) + +/** ATmegaxx4 group */ +#define MEGA_XX4 ( \ + AVR8_PART_IS_DEFINED(ATmega164A) || \ + AVR8_PART_IS_DEFINED(ATmega164PA) || \ + AVR8_PART_IS_DEFINED(ATmega324A) || \ + AVR8_PART_IS_DEFINED(ATmega324PA) || \ + AVR8_PART_IS_DEFINED(ATmega324PB) || \ + AVR8_PART_IS_DEFINED(ATmega644) || \ + AVR8_PART_IS_DEFINED(ATmega644A) || \ + AVR8_PART_IS_DEFINED(ATmega644PA) || \ + AVR8_PART_IS_DEFINED(ATmega1284P) || \ + AVR8_PART_IS_DEFINED(ATmega128RFA1) \ + ) + +/** ATmegaxx4 group */ +#define MEGA_XX4_A ( \ + AVR8_PART_IS_DEFINED(ATmega164A) || \ + AVR8_PART_IS_DEFINED(ATmega164PA) || \ + AVR8_PART_IS_DEFINED(ATmega324A) || \ + AVR8_PART_IS_DEFINED(ATmega324PA) || \ + AVR8_PART_IS_DEFINED(ATmega644A) || \ + AVR8_PART_IS_DEFINED(ATmega644PA) || \ + AVR8_PART_IS_DEFINED(ATmega1284P) \ + ) + +/** ATmegaxx8 group */ +#define MEGA_XX8 ( \ + AVR8_PART_IS_DEFINED(ATmega48) || \ + AVR8_PART_IS_DEFINED(ATmega48A) || \ + AVR8_PART_IS_DEFINED(ATmega48PA) || \ + AVR8_PART_IS_DEFINED(ATmega48PB) || \ + AVR8_PART_IS_DEFINED(ATmega88) || \ + AVR8_PART_IS_DEFINED(ATmega88A) || \ + AVR8_PART_IS_DEFINED(ATmega88PA) || \ + AVR8_PART_IS_DEFINED(ATmega88PB) || \ + AVR8_PART_IS_DEFINED(ATmega168) || \ + AVR8_PART_IS_DEFINED(ATmega168A) || \ + AVR8_PART_IS_DEFINED(ATmega168PA) || \ + AVR8_PART_IS_DEFINED(ATmega168PB) || \ + AVR8_PART_IS_DEFINED(ATmega328) || \ + AVR8_PART_IS_DEFINED(ATmega328P) || \ + AVR8_PART_IS_DEFINED(ATmega328PB) \ + ) + +/** ATmegaxx8A/P/PA group */ +#define MEGA_XX8_A ( \ + AVR8_PART_IS_DEFINED(ATmega48A) || \ + AVR8_PART_IS_DEFINED(ATmega48PA) || \ + AVR8_PART_IS_DEFINED(ATmega88A) || \ + AVR8_PART_IS_DEFINED(ATmega88PA) || \ + AVR8_PART_IS_DEFINED(ATmega168A) || \ + AVR8_PART_IS_DEFINED(ATmega168PA) || \ + AVR8_PART_IS_DEFINED(ATmega328P) \ + ) + +/** ATmegaxx group */ +#define MEGA_XX ( \ + AVR8_PART_IS_DEFINED(ATmega16) || \ + AVR8_PART_IS_DEFINED(ATmega16A) || \ + AVR8_PART_IS_DEFINED(ATmega32) || \ + AVR8_PART_IS_DEFINED(ATmega32A) || \ + AVR8_PART_IS_DEFINED(ATmega64) || \ + AVR8_PART_IS_DEFINED(ATmega64A) || \ + AVR8_PART_IS_DEFINED(ATmega128) || \ + AVR8_PART_IS_DEFINED(ATmega128A) \ + ) + +/** ATmegaxxA/P/PA group */ +#define MEGA_XX_A ( \ + AVR8_PART_IS_DEFINED(ATmega16A) || \ + AVR8_PART_IS_DEFINED(ATmega32A) || \ + AVR8_PART_IS_DEFINED(ATmega64A) || \ + AVR8_PART_IS_DEFINED(ATmega128A) \ + ) +/** ATmegaxxRFA1 group */ +#define MEGA_RFA1 ( \ + AVR8_PART_IS_DEFINED(ATmega128RFA1) \ + ) + +/** ATmegaxxRFR2 group */ +#define MEGA_RFR2 ( \ + AVR8_PART_IS_DEFINED(ATmega64RFR2) || \ + AVR8_PART_IS_DEFINED(ATmega128RFR2) || \ + AVR8_PART_IS_DEFINED(ATmega256RFR2) || \ + AVR8_PART_IS_DEFINED(ATmega644RFR2) || \ + AVR8_PART_IS_DEFINED(ATmega1284RFR2) || \ + AVR8_PART_IS_DEFINED(ATmega2564RFR2) \ + ) + + +/** ATmegaxxRFxx group */ +#define MEGA_RF (MEGA_RFA1 || MEGA_RFR2) + +/** + * \name ATmegaxx_un0/un1/un2 subgroups + * @{ + */ +#define MEGA_XX_UN0 ( \ + AVR8_PART_IS_DEFINED(ATmega16) || \ + AVR8_PART_IS_DEFINED(ATmega16A) || \ + AVR8_PART_IS_DEFINED(ATmega32) || \ + AVR8_PART_IS_DEFINED(ATmega32A) \ + ) + +/** ATmegaxx group without power reduction and + * And interrupt sense register. + */ +#define MEGA_XX_UN1 ( \ + AVR8_PART_IS_DEFINED(ATmega64) || \ + AVR8_PART_IS_DEFINED(ATmega64A) || \ + AVR8_PART_IS_DEFINED(ATmega128) || \ + AVR8_PART_IS_DEFINED(ATmega128A) \ + ) + +/** ATmegaxx group without power reduction and + * And interrupt sense register. + */ +#define MEGA_XX_UN2 ( \ + AVR8_PART_IS_DEFINED(ATmega169P) || \ + AVR8_PART_IS_DEFINED(ATmega169PA) || \ + AVR8_PART_IS_DEFINED(ATmega329P) || \ + AVR8_PART_IS_DEFINED(ATmega329PA) \ + ) + +/** Devices added to complete megaAVR offering. + * Please do not use this group symbol as it is not intended + * to be permanent: the devices should be regrouped. + */ +#define MEGA_UNCATEGORIZED ( \ + AVR8_PART_IS_DEFINED(AT90CAN128) || \ + AVR8_PART_IS_DEFINED(AT90CAN32) || \ + AVR8_PART_IS_DEFINED(AT90CAN64) || \ + AVR8_PART_IS_DEFINED(AT90PWM1) || \ + AVR8_PART_IS_DEFINED(AT90PWM216) || \ + AVR8_PART_IS_DEFINED(AT90PWM2B) || \ + AVR8_PART_IS_DEFINED(AT90PWM316) || \ + AVR8_PART_IS_DEFINED(AT90PWM3B) || \ + AVR8_PART_IS_DEFINED(AT90PWM81) || \ + AVR8_PART_IS_DEFINED(AT90USB1286) || \ + AVR8_PART_IS_DEFINED(AT90USB1287) || \ + AVR8_PART_IS_DEFINED(AT90USB162) || \ + AVR8_PART_IS_DEFINED(AT90USB646) || \ + AVR8_PART_IS_DEFINED(AT90USB647) || \ + AVR8_PART_IS_DEFINED(AT90USB82) || \ + AVR8_PART_IS_DEFINED(ATmega1284) || \ + AVR8_PART_IS_DEFINED(ATmega162) || \ + AVR8_PART_IS_DEFINED(ATmega164P) || \ + AVR8_PART_IS_DEFINED(ATmega165A) || \ + AVR8_PART_IS_DEFINED(ATmega165P) || \ + AVR8_PART_IS_DEFINED(ATmega165PA) || \ + AVR8_PART_IS_DEFINED(ATmega168P) || \ + AVR8_PART_IS_DEFINED(ATmega169A) || \ + AVR8_PART_IS_DEFINED(ATmega16M1) || \ + AVR8_PART_IS_DEFINED(ATmega16U2) || \ + AVR8_PART_IS_DEFINED(ATmega16U4) || \ + AVR8_PART_IS_DEFINED(ATmega256RFA2) || \ + AVR8_PART_IS_DEFINED(ATmega324P) || \ + AVR8_PART_IS_DEFINED(ATmega325) || \ + AVR8_PART_IS_DEFINED(ATmega3250) || \ + AVR8_PART_IS_DEFINED(ATmega3250A) || \ + AVR8_PART_IS_DEFINED(ATmega3250P) || \ + AVR8_PART_IS_DEFINED(ATmega3250PA) || \ + AVR8_PART_IS_DEFINED(ATmega325A) || \ + AVR8_PART_IS_DEFINED(ATmega325P) || \ + AVR8_PART_IS_DEFINED(ATmega325PA) || \ + AVR8_PART_IS_DEFINED(ATmega329) || \ + AVR8_PART_IS_DEFINED(ATmega3290) || \ + AVR8_PART_IS_DEFINED(ATmega3290A) || \ + AVR8_PART_IS_DEFINED(ATmega3290P) || \ + AVR8_PART_IS_DEFINED(ATmega3290PA) || \ + AVR8_PART_IS_DEFINED(ATmega329A) || \ + AVR8_PART_IS_DEFINED(ATmega32M1) || \ + AVR8_PART_IS_DEFINED(ATmega32U2) || \ + AVR8_PART_IS_DEFINED(ATmega32U4) || \ + AVR8_PART_IS_DEFINED(ATmega48P) || \ + AVR8_PART_IS_DEFINED(ATmega644P) || \ + AVR8_PART_IS_DEFINED(ATmega645) || \ + AVR8_PART_IS_DEFINED(ATmega6450) || \ + AVR8_PART_IS_DEFINED(ATmega6450A) || \ + AVR8_PART_IS_DEFINED(ATmega6450P) || \ + AVR8_PART_IS_DEFINED(ATmega645A) || \ + AVR8_PART_IS_DEFINED(ATmega645P) || \ + AVR8_PART_IS_DEFINED(ATmega649) || \ + AVR8_PART_IS_DEFINED(ATmega6490) || \ + AVR8_PART_IS_DEFINED(ATmega6490A) || \ + AVR8_PART_IS_DEFINED(ATmega6490P) || \ + AVR8_PART_IS_DEFINED(ATmega649A) || \ + AVR8_PART_IS_DEFINED(ATmega649P) || \ + AVR8_PART_IS_DEFINED(ATmega64M1) || \ + AVR8_PART_IS_DEFINED(ATmega64RFA2) || \ + AVR8_PART_IS_DEFINED(ATmega8) || \ + AVR8_PART_IS_DEFINED(ATmega8515) || \ + AVR8_PART_IS_DEFINED(ATmega8535) || \ + AVR8_PART_IS_DEFINED(ATmega88P) || \ + AVR8_PART_IS_DEFINED(ATmega8A) || \ + AVR8_PART_IS_DEFINED(ATmega8U2) \ + ) + +/** Unspecified group */ +#define MEGA_UNSPECIFIED (MEGA_XX_UN0 || MEGA_XX_UN1 || MEGA_XX_UN2 || \ + MEGA_UNCATEGORIZED) + +/** @} */ + +/** megaAVR product line */ +#define MEGA (MEGA_XX0_1 || MEGA_XX4 || MEGA_XX8 || MEGA_XX || MEGA_RF || \ + MEGA_UNSPECIFIED) + +/** @} */ + +/** + * \defgroup sam_part_macros_group SAM parts + * @{ + */ + +/** + * \name SAM3S series + * @{ + */ +#define SAM3S1 ( \ + SAM_PART_IS_DEFINED(SAM3S1A) || \ + SAM_PART_IS_DEFINED(SAM3S1B) || \ + SAM_PART_IS_DEFINED(SAM3S1C) \ + ) + +#define SAM3S2 ( \ + SAM_PART_IS_DEFINED(SAM3S2A) || \ + SAM_PART_IS_DEFINED(SAM3S2B) || \ + SAM_PART_IS_DEFINED(SAM3S2C) \ + ) + +#define SAM3S4 ( \ + SAM_PART_IS_DEFINED(SAM3S4A) || \ + SAM_PART_IS_DEFINED(SAM3S4B) || \ + SAM_PART_IS_DEFINED(SAM3S4C) \ + ) + +#define SAM3S8 ( \ + SAM_PART_IS_DEFINED(SAM3S8B) || \ + SAM_PART_IS_DEFINED(SAM3S8C) \ + ) + +#define SAM3SD8 ( \ + SAM_PART_IS_DEFINED(SAM3SD8B) || \ + SAM_PART_IS_DEFINED(SAM3SD8C) \ + ) +/** @} */ + +/** + * \name SAM3U series + * @{ + */ +#define SAM3U1 ( \ + SAM_PART_IS_DEFINED(SAM3U1C) || \ + SAM_PART_IS_DEFINED(SAM3U1E) \ + ) + +#define SAM3U2 ( \ + SAM_PART_IS_DEFINED(SAM3U2C) || \ + SAM_PART_IS_DEFINED(SAM3U2E) \ + ) + +#define SAM3U4 ( \ + SAM_PART_IS_DEFINED(SAM3U4C) || \ + SAM_PART_IS_DEFINED(SAM3U4E) \ + ) +/** @} */ + +/** + * \name SAM3N series + * @{ + */ +#define SAM3N00 ( \ + SAM_PART_IS_DEFINED(SAM3N00A) || \ + SAM_PART_IS_DEFINED(SAM3N00B) \ + ) + +#define SAM3N0 ( \ + SAM_PART_IS_DEFINED(SAM3N0A) || \ + SAM_PART_IS_DEFINED(SAM3N0B) || \ + SAM_PART_IS_DEFINED(SAM3N0C) \ + ) + +#define SAM3N1 ( \ + SAM_PART_IS_DEFINED(SAM3N1A) || \ + SAM_PART_IS_DEFINED(SAM3N1B) || \ + SAM_PART_IS_DEFINED(SAM3N1C) \ + ) + +#define SAM3N2 ( \ + SAM_PART_IS_DEFINED(SAM3N2A) || \ + SAM_PART_IS_DEFINED(SAM3N2B) || \ + SAM_PART_IS_DEFINED(SAM3N2C) \ + ) + +#define SAM3N4 ( \ + SAM_PART_IS_DEFINED(SAM3N4A) || \ + SAM_PART_IS_DEFINED(SAM3N4B) || \ + SAM_PART_IS_DEFINED(SAM3N4C) \ + ) +/** @} */ + +/** + * \name SAM3X series + * @{ + */ +#define SAM3X4 ( \ + SAM_PART_IS_DEFINED(SAM3X4C) || \ + SAM_PART_IS_DEFINED(SAM3X4E) \ + ) + +#define SAM3X8 ( \ + SAM_PART_IS_DEFINED(SAM3X8C) || \ + SAM_PART_IS_DEFINED(SAM3X8E) || \ + SAM_PART_IS_DEFINED(SAM3X8H) \ + ) +/** @} */ + +/** + * \name SAM3A series + * @{ + */ +#define SAM3A4 ( \ + SAM_PART_IS_DEFINED(SAM3A4C) \ + ) + +#define SAM3A8 ( \ + SAM_PART_IS_DEFINED(SAM3A8C) \ + ) +/** @} */ + +/** + * \name SAM4S series + * @{ + */ +#define SAM4S2 ( \ + SAM_PART_IS_DEFINED(SAM4S2A) || \ + SAM_PART_IS_DEFINED(SAM4S2B) || \ + SAM_PART_IS_DEFINED(SAM4S2C) \ + ) + +#define SAM4S4 ( \ + SAM_PART_IS_DEFINED(SAM4S4A) || \ + SAM_PART_IS_DEFINED(SAM4S4B) || \ + SAM_PART_IS_DEFINED(SAM4S4C) \ + ) + +#define SAM4S8 ( \ + SAM_PART_IS_DEFINED(SAM4S8B) || \ + SAM_PART_IS_DEFINED(SAM4S8C) \ + ) + +#define SAM4S16 ( \ + SAM_PART_IS_DEFINED(SAM4S16B) || \ + SAM_PART_IS_DEFINED(SAM4S16C) \ + ) + +#define SAM4SA16 ( \ + SAM_PART_IS_DEFINED(SAM4SA16B) || \ + SAM_PART_IS_DEFINED(SAM4SA16C) \ + ) + +#define SAM4SD16 ( \ + SAM_PART_IS_DEFINED(SAM4SD16B) || \ + SAM_PART_IS_DEFINED(SAM4SD16C) \ + ) + +#define SAM4SD32 ( \ + SAM_PART_IS_DEFINED(SAM4SD32B) || \ + SAM_PART_IS_DEFINED(SAM4SD32C) \ + ) +/** @} */ + +/** + * \name SAM4L series + * @{ + */ +#define SAM4LS ( \ + SAM_PART_IS_DEFINED(SAM4LS2A) || \ + SAM_PART_IS_DEFINED(SAM4LS2B) || \ + SAM_PART_IS_DEFINED(SAM4LS2C) || \ + SAM_PART_IS_DEFINED(SAM4LS4A) || \ + SAM_PART_IS_DEFINED(SAM4LS4B) || \ + SAM_PART_IS_DEFINED(SAM4LS4C) || \ + SAM_PART_IS_DEFINED(SAM4LS8A) || \ + SAM_PART_IS_DEFINED(SAM4LS8B) || \ + SAM_PART_IS_DEFINED(SAM4LS8C) \ + ) + +#define SAM4LC ( \ + SAM_PART_IS_DEFINED(SAM4LC2A) || \ + SAM_PART_IS_DEFINED(SAM4LC2B) || \ + SAM_PART_IS_DEFINED(SAM4LC2C) || \ + SAM_PART_IS_DEFINED(SAM4LC4A) || \ + SAM_PART_IS_DEFINED(SAM4LC4B) || \ + SAM_PART_IS_DEFINED(SAM4LC4C) || \ + SAM_PART_IS_DEFINED(SAM4LC8A) || \ + SAM_PART_IS_DEFINED(SAM4LC8B) || \ + SAM_PART_IS_DEFINED(SAM4LC8C) \ + ) +/** @} */ + +/** + * \name SAMD20 series + * @{ + */ +#define SAMD20J ( \ + SAM_PART_IS_DEFINED(SAMD20J14) || \ + SAM_PART_IS_DEFINED(SAMD20J15) || \ + SAM_PART_IS_DEFINED(SAMD20J16) || \ + SAM_PART_IS_DEFINED(SAMD20J14B) || \ + SAM_PART_IS_DEFINED(SAMD20J15B) || \ + SAM_PART_IS_DEFINED(SAMD20J16B) || \ + SAM_PART_IS_DEFINED(SAMD20J17) || \ + SAM_PART_IS_DEFINED(SAMD20J18) \ + ) + +#define SAMD20G ( \ + SAM_PART_IS_DEFINED(SAMD20G14) || \ + SAM_PART_IS_DEFINED(SAMD20G15) || \ + SAM_PART_IS_DEFINED(SAMD20G16) || \ + SAM_PART_IS_DEFINED(SAMD20G14B) || \ + SAM_PART_IS_DEFINED(SAMD20G15B) || \ + SAM_PART_IS_DEFINED(SAMD20G16B) || \ + SAM_PART_IS_DEFINED(SAMD20G17) || \ + SAM_PART_IS_DEFINED(SAMD20G17U) || \ + SAM_PART_IS_DEFINED(SAMD20G18) || \ + SAM_PART_IS_DEFINED(SAMD20G18U) \ + ) + +#define SAMD20E ( \ + SAM_PART_IS_DEFINED(SAMD20E14) || \ + SAM_PART_IS_DEFINED(SAMD20E15) || \ + SAM_PART_IS_DEFINED(SAMD20E16) || \ + SAM_PART_IS_DEFINED(SAMD20E14B) || \ + SAM_PART_IS_DEFINED(SAMD20E15B) || \ + SAM_PART_IS_DEFINED(SAMD20E16B) || \ + SAM_PART_IS_DEFINED(SAMD20E17) || \ + SAM_PART_IS_DEFINED(SAMD20E18) \ + ) + +/** @} */ + +/** + * \name SAMD21 series + * @{ + */ +#define SAMD21J ( \ + SAM_PART_IS_DEFINED(SAMD21J15A) || \ + SAM_PART_IS_DEFINED(SAMD21J16A) || \ + SAM_PART_IS_DEFINED(SAMD21J17A) || \ + SAM_PART_IS_DEFINED(SAMD21J18A) || \ + SAM_PART_IS_DEFINED(SAMD21J15B) || \ + SAM_PART_IS_DEFINED(SAMD21J16B) || \ + SAM_PART_IS_DEFINED(SAMD21J17D) \ + ) + +#define SAMD21G ( \ + SAM_PART_IS_DEFINED(SAMD21G15A) || \ + SAM_PART_IS_DEFINED(SAMD21G16A) || \ + SAM_PART_IS_DEFINED(SAMD21G17A) || \ + SAM_PART_IS_DEFINED(SAMD21G17AU) || \ + SAM_PART_IS_DEFINED(SAMD21G18A) || \ + SAM_PART_IS_DEFINED(SAMD21G18AU) || \ + SAM_PART_IS_DEFINED(SAMD21G15B) || \ + SAM_PART_IS_DEFINED(SAMD21G16B) || \ + SAM_PART_IS_DEFINED(SAMD21G15L) || \ + SAM_PART_IS_DEFINED(SAMD21G16L) || \ + SAM_PART_IS_DEFINED(SAMD21G17D) || \ + SAM_PART_IS_DEFINED(SAMD21G17L) \ + ) + +#define SAMD21GXXL ( \ + SAM_PART_IS_DEFINED(SAMD21G15L) || \ + SAM_PART_IS_DEFINED(SAMD21G16L) || \ + SAM_PART_IS_DEFINED(SAMD21G17L) \ + ) + +#define SAMD21E ( \ + SAM_PART_IS_DEFINED(SAMD21E15A) || \ + SAM_PART_IS_DEFINED(SAMD21E16A) || \ + SAM_PART_IS_DEFINED(SAMD21E17A) || \ + SAM_PART_IS_DEFINED(SAMD21E18A) || \ + SAM_PART_IS_DEFINED(SAMD21E15B) || \ + SAM_PART_IS_DEFINED(SAMD21E15BU) || \ + SAM_PART_IS_DEFINED(SAMD21E16B) || \ + SAM_PART_IS_DEFINED(SAMD21E16BU) || \ + SAM_PART_IS_DEFINED(SAMD21E15L) || \ + SAM_PART_IS_DEFINED(SAMD21E16L) || \ + SAM_PART_IS_DEFINED(SAMD21E17D) || \ + SAM_PART_IS_DEFINED(SAMD21E17DU) || \ + SAM_PART_IS_DEFINED(SAMD21E17L) \ + ) + +#define SAMD21EXXL ( \ + SAM_PART_IS_DEFINED(SAMD21E15L) || \ + SAM_PART_IS_DEFINED(SAMD21E16L) || \ + SAM_PART_IS_DEFINED(SAMD21E17L) \ + ) + +/** @} */ + +/** + * \name SAMR21 series + * @{ + */ +#define SAMR21G ( \ + SAM_PART_IS_DEFINED(SAMR21G16A) || \ + SAM_PART_IS_DEFINED(SAMR21G17A) || \ + SAM_PART_IS_DEFINED(SAMR21G18A) \ + ) + +#define SAMR21E ( \ + SAM_PART_IS_DEFINED(SAMR21E16A) || \ + SAM_PART_IS_DEFINED(SAMR21E17A) || \ + SAM_PART_IS_DEFINED(SAMR21E18A) || \ + SAM_PART_IS_DEFINED(SAMR21E19A) \ + ) +/** @} */ + +/** + * \name SAMR30 series + * @{ + */ +#define SAMR30G ( \ + SAM_PART_IS_DEFINED(SAMR30G18A) \ + ) + +#define SAMR30E ( \ + SAM_PART_IS_DEFINED(SAMR30E18A) \ + ) +/** @} */ + +/** + * \name SAMR34 series + * @{ + */ +#define SAMR34J ( \ + SAM_PART_IS_DEFINED(SAMR34J18A) || \ + SAM_PART_IS_DEFINED(SAMR34J17A) || \ + SAM_PART_IS_DEFINED(SAMR34J16A) || \ + SAM_PART_IS_DEFINED(SAMR34J18B) || \ + SAM_PART_IS_DEFINED(SAMR34J17B) || \ + SAM_PART_IS_DEFINED(SAMR34J16B) \ + ) + +/* Group for SAMR34 A variant: SAMR34J [16/17/18]A */ +#define SAMR34JXXA ( \ + SAM_PART_IS_DEFINED(SAMR34J18A) || \ + SAM_PART_IS_DEFINED(SAMR34J17A) || \ + SAM_PART_IS_DEFINED(SAMR34J16A) \ +) +/* Group for SAMR34 B variant: SAMR34J [16/17/18]B */ +#define SAMR34JXXB ( \ + SAM_PART_IS_DEFINED(SAMR34J18B) || \ + SAM_PART_IS_DEFINED(SAMR34J17B) || \ + SAM_PART_IS_DEFINED(SAMR34J16B) \ +) + +/* Group for SAMR35 B variant: SAMR35J [16/17/18]B */ +#define SAMR35J ( \ + SAM_PART_IS_DEFINED(SAMR35J18B) || \ + SAM_PART_IS_DEFINED(SAMR35J17B) || \ + SAM_PART_IS_DEFINED(SAMR35J16B) \ +) +/* Group for SAMR35 B variant: SAMR35J [16/17/18]B */ +#define SAMR35JXXB ( \ + SAM_PART_IS_DEFINED(SAMR35J18B) || \ + SAM_PART_IS_DEFINED(SAMR35J17B) || \ + SAM_PART_IS_DEFINED(SAMR35J16B) \ +) + +/** + * \name SAMB11 series + * @{ + */ +#define SAMB11G ( \ + SAM_PART_IS_DEFINED(SAMB11G18A) || \ + SAM_PART_IS_DEFINED(SAMB11ZR) \ + ) +#define BTLC1000 ( \ + SAM_PART_IS_DEFINED(BTLC1000WLCSP) \ + ) + +/** @} */ + +/** + * \name SAMD09 series + * @{ + */ +#define SAMD09C ( \ + SAM_PART_IS_DEFINED(SAMD09C13A) \ + ) + +#define SAMD09D ( \ + SAM_PART_IS_DEFINED(SAMD09D14A) \ + ) +/** @} */ + +/** + * \name SAMD10 series + * @{ + */ +#define SAMD10C ( \ + SAM_PART_IS_DEFINED(SAMD10C12A) || \ + SAM_PART_IS_DEFINED(SAMD10C13A) || \ + SAM_PART_IS_DEFINED(SAMD10C14A) \ + ) + +#define SAMD10DS ( \ + SAM_PART_IS_DEFINED(SAMD10D12AS) || \ + SAM_PART_IS_DEFINED(SAMD10D13AS) || \ + SAM_PART_IS_DEFINED(SAMD10D14AS) \ + ) + +#define SAMD10DM ( \ + SAM_PART_IS_DEFINED(SAMD10D12AM) || \ + SAM_PART_IS_DEFINED(SAMD10D13AM) || \ + SAM_PART_IS_DEFINED(SAMD10D14AM) \ + ) + +#define SAMD10DU ( \ + SAM_PART_IS_DEFINED(SAMD10D14AU) \ + ) +/** @} */ + +/** + * \name SAMD11 series + * @{ + */ +#define SAMD11C ( \ + SAM_PART_IS_DEFINED(SAMD11C14A) \ + ) + +#define SAMD11DS ( \ + SAM_PART_IS_DEFINED(SAMD11D14AS) \ + ) + +#define SAMD11DM ( \ + SAM_PART_IS_DEFINED(SAMD11D14AM) \ + ) + +#define SAMD11DU ( \ + SAM_PART_IS_DEFINED(SAMD11D14AU) \ + ) +/** @} */ + +/** + * \name SAML21 series + * @{ + */ +#define SAML21E ( \ + SAM_PART_IS_DEFINED(SAML21E18A) || \ + SAM_PART_IS_DEFINED(SAML21E15B) || \ + SAM_PART_IS_DEFINED(SAML21E16B) || \ + SAM_PART_IS_DEFINED(SAML21E17B) || \ + SAM_PART_IS_DEFINED(SAML21E18B) \ + ) + +#define SAML21G ( \ + SAM_PART_IS_DEFINED(SAML21G18A) || \ + SAM_PART_IS_DEFINED(SAML21G16B) || \ + SAM_PART_IS_DEFINED(SAML21G17B) || \ + SAM_PART_IS_DEFINED(SAML21G18B) \ + ) + +#define SAML21J ( \ + SAM_PART_IS_DEFINED(SAML21J18A) || \ + SAM_PART_IS_DEFINED(SAML21J16B) || \ + SAM_PART_IS_DEFINED(SAML21J17B) || \ + SAM_PART_IS_DEFINED(SAML21J18B) \ + ) + +/* Group for SAML21 A variant: SAML21[E/G/J][18]A */ +#define SAML21XXXA ( \ + SAM_PART_IS_DEFINED(SAML21E18A) || \ + SAM_PART_IS_DEFINED(SAML21G18A) || \ + SAM_PART_IS_DEFINED(SAML21J18A) \ + ) + +/* Group for SAML21 B variant: SAML21[E/G/J][15/16/1718]B */ +#define SAML21XXXB ( \ + SAM_PART_IS_DEFINED(SAML21E15B) || \ + SAM_PART_IS_DEFINED(SAML21E16B) || \ + SAM_PART_IS_DEFINED(SAML21E17B) || \ + SAM_PART_IS_DEFINED(SAML21E18B) || \ + SAM_PART_IS_DEFINED(SAML21G16B) || \ + SAM_PART_IS_DEFINED(SAML21G17B) || \ + SAM_PART_IS_DEFINED(SAML21G18B) || \ + SAM_PART_IS_DEFINED(SAML21J16B) || \ + SAM_PART_IS_DEFINED(SAML21J17B) || \ + SAM_PART_IS_DEFINED(SAML21J18B) \ + ) + +/** @} */ + +/** + * \name SAML22 series + * @{ + */ +#define SAML22N ( \ + SAM_PART_IS_DEFINED(SAML22N16A) || \ + SAM_PART_IS_DEFINED(SAML22N17A) || \ + SAM_PART_IS_DEFINED(SAML22N18A) \ + ) + +#define SAML22G ( \ + SAM_PART_IS_DEFINED(SAML22G16A) || \ + SAM_PART_IS_DEFINED(SAML22G17A) || \ + SAM_PART_IS_DEFINED(SAML22G18A) \ + ) + +#define SAML22J ( \ + SAM_PART_IS_DEFINED(SAML22J16A) || \ + SAM_PART_IS_DEFINED(SAML22J17A) || \ + SAM_PART_IS_DEFINED(SAML22J18A) \ + ) +/** @} */ + +/** + * \name SAMDA1 series + * @{ + */ +#define SAMDA1J ( \ + SAM_PART_IS_DEFINED(SAMDA1J14A) || \ + SAM_PART_IS_DEFINED(SAMDA1J15B) || \ + SAM_PART_IS_DEFINED(SAMDA1J15A) || \ + SAM_PART_IS_DEFINED(SAMDA1J15B) || \ + SAM_PART_IS_DEFINED(SAMDA1J16A) || \ + SAM_PART_IS_DEFINED(SAMDA1J16B) \ + ) + +#define SAMDA1G ( \ + SAM_PART_IS_DEFINED(SAMDA1G14A) || \ + SAM_PART_IS_DEFINED(SAMDA1G14B) || \ + SAM_PART_IS_DEFINED(SAMDA1G15A) || \ + SAM_PART_IS_DEFINED(SAMDA1G15B) || \ + SAM_PART_IS_DEFINED(SAMDA1G16A) || \ + SAM_PART_IS_DEFINED(SAMDA1G16B) \ + ) + +#define SAMDA1E ( \ + SAM_PART_IS_DEFINED(SAMDA1E14A) || \ + SAM_PART_IS_DEFINED(SAMDA1E14B) || \ + SAM_PART_IS_DEFINED(SAMDA1E15A) || \ + SAM_PART_IS_DEFINED(SAMDA1E15B) || \ + SAM_PART_IS_DEFINED(SAMDA1E16A) || \ + SAM_PART_IS_DEFINED(SAMDA1E16B) \ + ) +/** @} */ + +/** + * \name SAMHA1 series + * @{ + */ +#define SAMHA1G ( \ + SAM_PART_IS_DEFINED(SAMHA1G14A) || \ + SAM_PART_IS_DEFINED(SAMHA1G15A) || \ + SAM_PART_IS_DEFINED(SAMHA1G16A) || \ + SAM_PART_IS_DEFINED(SAMHA1G14AB) || \ + SAM_PART_IS_DEFINED(SAMHA1G15AB) || \ + SAM_PART_IS_DEFINED(SAMHA1G16AB) \ + ) + +#define SAMHA1E ( \ + SAM_PART_IS_DEFINED(SAMHA1E14A) || \ + SAM_PART_IS_DEFINED(SAMHA1E15A) || \ + SAM_PART_IS_DEFINED(SAMHA1E16A) || \ + SAM_PART_IS_DEFINED(SAMHA1E14AB) || \ + SAM_PART_IS_DEFINED(SAMHA1E15AB) || \ + SAM_PART_IS_DEFINED(SAMHA1E16AB) \ + ) + +/** @} */ + +/** + * \name SAMHA0 series + * @{ + */ +#define SAMHA0G ( \ + SAM_PART_IS_DEFINED(SAMHA0G14AB) || \ + SAM_PART_IS_DEFINED(SAMHA0G15AB) || \ + SAM_PART_IS_DEFINED(SAMHA0G16AB) \ + ) + +#define SAMHA0E ( \ + SAM_PART_IS_DEFINED(SAMHA0E14AB) || \ + SAM_PART_IS_DEFINED(SAMHA0E15AB) || \ + SAM_PART_IS_DEFINED(SAMHA0E16AB) \ + ) + +/** @} */ + +/** + * \name SAMC20 series + * @{ + */ +#define SAMC20E ( \ + SAM_PART_IS_DEFINED(SAMC20E15A) || \ + SAM_PART_IS_DEFINED(SAMC20E16A) || \ + SAM_PART_IS_DEFINED(SAMC20E17A) || \ + SAM_PART_IS_DEFINED(SAMC20E18A) \ + ) + +#define SAMC20G ( \ + SAM_PART_IS_DEFINED(SAMC20G15A) || \ + SAM_PART_IS_DEFINED(SAMC20G16A) || \ + SAM_PART_IS_DEFINED(SAMC20G17A) || \ + SAM_PART_IS_DEFINED(SAMC20G18A) \ + ) + +#define SAMC20J ( \ + SAM_PART_IS_DEFINED(SAMC20J15A) || \ + SAM_PART_IS_DEFINED(SAMC20J16A) || \ + SAM_PART_IS_DEFINED(SAMC20J17A) || \ + SAM_PART_IS_DEFINED(SAMC20J18A) \ + ) +/** @} */ + +/** + * \name SAMC21 series + * @{ + */ +#define SAMC21E ( \ + SAM_PART_IS_DEFINED(SAMC21E15A) || \ + SAM_PART_IS_DEFINED(SAMC21E16A) || \ + SAM_PART_IS_DEFINED(SAMC21E17A) || \ + SAM_PART_IS_DEFINED(SAMC21E18A) \ + ) + +#define SAMC21G ( \ + SAM_PART_IS_DEFINED(SAMC21G15A) || \ + SAM_PART_IS_DEFINED(SAMC21G16A) || \ + SAM_PART_IS_DEFINED(SAMC21G17A) || \ + SAM_PART_IS_DEFINED(SAMC21G18A) \ + ) + +#define SAMC21J ( \ + SAM_PART_IS_DEFINED(SAMC21J15A) || \ + SAM_PART_IS_DEFINED(SAMC21J16A) || \ + SAM_PART_IS_DEFINED(SAMC21J17A) || \ + SAM_PART_IS_DEFINED(SAMC21J18A) \ + ) +/** @} */ + +/** + * \name SAM4E series + * @{ + */ +#define SAM4E8 ( \ + SAM_PART_IS_DEFINED(SAM4E8C) || \ + SAM_PART_IS_DEFINED(SAM4E8CB) || \ + SAM_PART_IS_DEFINED(SAM4E8E) \ + ) + +#define SAM4E16 ( \ + SAM_PART_IS_DEFINED(SAM4E16C) || \ + SAM_PART_IS_DEFINED(SAM4E16CB) || \ + SAM_PART_IS_DEFINED(SAM4E16E) \ + ) +/** @} */ + +/** + * \name SAM4N series + * @{ + */ +#define SAM4N8 ( \ + SAM_PART_IS_DEFINED(SAM4N8A) || \ + SAM_PART_IS_DEFINED(SAM4N8B) || \ + SAM_PART_IS_DEFINED(SAM4N8C) \ + ) + +#define SAM4N16 ( \ + SAM_PART_IS_DEFINED(SAM4N16B) || \ + SAM_PART_IS_DEFINED(SAM4N16C) \ + ) +/** @} */ + +/** + * \name SAM4C series + * @{ + */ +#define SAM4C4_0 ( \ + SAM_PART_IS_DEFINED(SAM4C4C_0) \ + ) + +#define SAM4C4_1 ( \ + SAM_PART_IS_DEFINED(SAM4C4C_1) \ + ) + +#define SAM4C4 (SAM4C4_0 || SAM4C4_1) + +#define SAM4C8_0 ( \ + SAM_PART_IS_DEFINED(SAM4C8C_0) \ + ) + +#define SAM4C8_1 ( \ + SAM_PART_IS_DEFINED(SAM4C8C_1) \ + ) + +#define SAM4C8 (SAM4C8_0 || SAM4C8_1) + +#define SAM4C16_0 ( \ + SAM_PART_IS_DEFINED(SAM4C16C_0) \ + ) + +#define SAM4C16_1 ( \ + SAM_PART_IS_DEFINED(SAM4C16C_1) \ + ) + +#define SAM4C16 (SAM4C16_0 || SAM4C16_1) + +#define SAM4C32_0 ( \ + SAM_PART_IS_DEFINED(SAM4C32C_0) ||\ + SAM_PART_IS_DEFINED(SAM4C32E_0) \ + ) + +#define SAM4C32_1 ( \ + SAM_PART_IS_DEFINED(SAM4C32C_1) ||\ + SAM_PART_IS_DEFINED(SAM4C32E_1) \ + ) + + +#define SAM4C32 (SAM4C32_0 || SAM4C32_1) + +/** @} */ + +/** + * \name SAM4CM series + * @{ + */ +#define SAM4CMP8_0 ( \ + SAM_PART_IS_DEFINED(SAM4CMP8C_0) \ + ) + +#define SAM4CMP8_1 ( \ + SAM_PART_IS_DEFINED(SAM4CMP8C_1) \ + ) + +#define SAM4CMP8 (SAM4CMP8_0 || SAM4CMP8_1) + +#define SAM4CMP16_0 ( \ + SAM_PART_IS_DEFINED(SAM4CMP16C_0) \ + ) + +#define SAM4CMP16_1 ( \ + SAM_PART_IS_DEFINED(SAM4CMP16C_1) \ + ) + +#define SAM4CMP16 (SAM4CMP16_0 || SAM4CMP16_1) + +#define SAM4CMP32_0 ( \ + SAM_PART_IS_DEFINED(SAM4CMP32C_0) \ + ) + +#define SAM4CMP32_1 ( \ + SAM_PART_IS_DEFINED(SAM4CMP32C_1) \ + ) + +#define SAM4CMP32 (SAM4CMP32_0 || SAM4CMP32_1) + +#define SAM4CMS4_0 ( \ + SAM_PART_IS_DEFINED(SAM4CMS4C_0) \ + ) + +#define SAM4CMS4_1 ( \ + SAM_PART_IS_DEFINED(SAM4CMS4C_1) \ + ) + +#define SAM4CMS4 (SAM4CMS4_0 || SAM4CMS4_1) + +#define SAM4CMS8_0 ( \ + SAM_PART_IS_DEFINED(SAM4CMS8C_0) \ + ) + +#define SAM4CMS8_1 ( \ + SAM_PART_IS_DEFINED(SAM4CMS8C_1) \ + ) + +#define SAM4CMS8 (SAM4CMS8_0 || SAM4CMS8_1) + +#define SAM4CMS16_0 ( \ + SAM_PART_IS_DEFINED(SAM4CMS16C_0) \ + ) + +#define SAM4CMS16_1 ( \ + SAM_PART_IS_DEFINED(SAM4CMS16C_1) \ + ) + +#define SAM4CMS16 (SAM4CMS16_0 || SAM4CMS16_1) + +#define SAM4CMS32_0 ( \ + SAM_PART_IS_DEFINED(SAM4CMS32C_0) \ + ) + +#define SAM4CMS32_1 ( \ + SAM_PART_IS_DEFINED(SAM4CMS32C_1) \ + ) + +#define SAM4CMS32 (SAM4CMS32_0 || SAM4CMS32_1) + +/** @} */ + +/** + * \name SAM4CP series + * @{ + */ +#define SAM4CP16_0 ( \ + SAM_PART_IS_DEFINED(SAM4CP16B_0) \ + ) + +#define SAM4CP16_1 ( \ + SAM_PART_IS_DEFINED(SAM4CP16B_1) \ + ) + +#define SAM4CP16 (SAM4CP16_0 || SAM4CP16_1) +/** @} */ + +/** + * \name SAMG series + * @{ + */ +#define SAMG51 ( \ + SAM_PART_IS_DEFINED(SAMG51G18) \ + ) + +#define SAMG53 ( \ + SAM_PART_IS_DEFINED(SAMG53G19) ||\ + SAM_PART_IS_DEFINED(SAMG53N19) \ + ) + +#define SAMG54 ( \ + SAM_PART_IS_DEFINED(SAMG54G19) ||\ + SAM_PART_IS_DEFINED(SAMG54J19) ||\ + SAM_PART_IS_DEFINED(SAMG54N19) \ + ) + +#define SAMG55 ( \ + SAM_PART_IS_DEFINED(SAMG55G18) ||\ + SAM_PART_IS_DEFINED(SAMG55G19) ||\ + SAM_PART_IS_DEFINED(SAMG55J18) ||\ + SAM_PART_IS_DEFINED(SAMG55J19) ||\ + SAM_PART_IS_DEFINED(SAMG55N19) \ + ) +/** @} */ + +/** + * \name SAMV71 series + * @{ + */ +#define SAMV71J ( \ + SAM_PART_IS_DEFINED(SAMV71J19) || \ + SAM_PART_IS_DEFINED(SAMV71J20) || \ + SAM_PART_IS_DEFINED(SAMV71J21) \ + ) + +#define SAMV71JB ( \ + SAM_PART_IS_DEFINED(SAMV71J19B) || \ + SAM_PART_IS_DEFINED(SAMV71J20B) || \ + SAM_PART_IS_DEFINED(SAMV71J21B) \ + ) + +#define SAMV71N ( \ + SAM_PART_IS_DEFINED(SAMV71N19) || \ + SAM_PART_IS_DEFINED(SAMV71N20) || \ + SAM_PART_IS_DEFINED(SAMV71N21) \ + ) + +#define SAMV71NB ( \ + SAM_PART_IS_DEFINED(SAMV71N19B) || \ + SAM_PART_IS_DEFINED(SAMV71N20B) || \ + SAM_PART_IS_DEFINED(SAMV71N21B) \ + ) + +#define SAMV71Q ( \ + SAM_PART_IS_DEFINED(SAMV71Q19) || \ + SAM_PART_IS_DEFINED(SAMV71Q20) || \ + SAM_PART_IS_DEFINED(SAMV71Q21) \ + ) + +#define SAMV71QB ( \ + SAM_PART_IS_DEFINED(SAMV71Q19B) || \ + SAM_PART_IS_DEFINED(SAMV71Q20B) || \ + SAM_PART_IS_DEFINED(SAMV71Q21B) \ + ) + +/** @} */ + +/** + * \name SAMV70 series + * @{ + */ +#define SAMV70J ( \ + SAM_PART_IS_DEFINED(SAMV70J19) || \ + SAM_PART_IS_DEFINED(SAMV70J20) \ + ) + +#define SAMV70JB ( \ + SAM_PART_IS_DEFINED(SAMV70J19B) || \ + SAM_PART_IS_DEFINED(SAMV70J20B) \ + ) + +#define SAMV70N ( \ + SAM_PART_IS_DEFINED(SAMV70N19) || \ + SAM_PART_IS_DEFINED(SAMV70N20) \ + ) + +#define SAMV70NB ( \ + SAM_PART_IS_DEFINED(SAMV70N19B) || \ + SAM_PART_IS_DEFINED(SAMV70N20B) \ + ) + +#define SAMV70Q ( \ + SAM_PART_IS_DEFINED(SAMV70Q19) || \ + SAM_PART_IS_DEFINED(SAMV70Q20) \ + ) +#define SAMV70QB ( \ + SAM_PART_IS_DEFINED(SAMV70Q19B) || \ + SAM_PART_IS_DEFINED(SAMV70Q20B) \ + ) +/** @} */ + +/** + * \name SAMS70 series + * @{ + */ +#define SAMS70J ( \ + SAM_PART_IS_DEFINED(SAMS70J19) || \ + SAM_PART_IS_DEFINED(SAMS70J20) || \ + SAM_PART_IS_DEFINED(SAMS70J21) \ + ) + +#define SAMS70JB ( \ + SAM_PART_IS_DEFINED(SAMS70J19B) || \ + SAM_PART_IS_DEFINED(SAMS70J20B) || \ + SAM_PART_IS_DEFINED(SAMS70J21B) \ + ) + +#define SAMS70N ( \ + SAM_PART_IS_DEFINED(SAMS70N19) || \ + SAM_PART_IS_DEFINED(SAMS70N20) || \ + SAM_PART_IS_DEFINED(SAMS70N21) \ + ) + +#define SAMS70NB ( \ + SAM_PART_IS_DEFINED(SAMS70N19B) || \ + SAM_PART_IS_DEFINED(SAMS70N20B) || \ + SAM_PART_IS_DEFINED(SAMS70N21B) \ + ) + +#define SAMS70Q ( \ + SAM_PART_IS_DEFINED(SAMS70Q19) || \ + SAM_PART_IS_DEFINED(SAMS70Q20) || \ + SAM_PART_IS_DEFINED(SAMS70Q21) \ + ) + +#define SAMS70QB ( \ + SAM_PART_IS_DEFINED(SAMS70Q19B) || \ + SAM_PART_IS_DEFINED(SAMS70Q20B) || \ + SAM_PART_IS_DEFINED(SAMS70Q21B) \ + ) +/** @} */ + +/** + * \name SAME70 series + * @{ + */ +#define SAME70J ( \ + SAM_PART_IS_DEFINED(SAME70J19) || \ + SAM_PART_IS_DEFINED(SAME70J20) || \ + SAM_PART_IS_DEFINED(SAME70J21) \ + ) + +#define SAME70JB ( \ + SAM_PART_IS_DEFINED(SAME70J19B) || \ + SAM_PART_IS_DEFINED(SAME70J20B) || \ + SAM_PART_IS_DEFINED(SAME70J21B) \ + ) + +#define SAME70N ( \ + SAM_PART_IS_DEFINED(SAME70N19) || \ + SAM_PART_IS_DEFINED(SAME70N20) || \ + SAM_PART_IS_DEFINED(SAME70N21) \ + ) + +#define SAME70NB ( \ + SAM_PART_IS_DEFINED(SAME70N19B) || \ + SAM_PART_IS_DEFINED(SAME70N20B) || \ + SAM_PART_IS_DEFINED(SAME70N21B) \ + ) + +#define SAME70Q ( \ + SAM_PART_IS_DEFINED(SAME70Q19) || \ + SAM_PART_IS_DEFINED(SAME70Q20) || \ + SAM_PART_IS_DEFINED(SAME70Q21) \ + ) + +#define SAME70QB ( \ + SAM_PART_IS_DEFINED(SAME70Q19B) || \ + SAM_PART_IS_DEFINED(SAME70Q20B) || \ + SAM_PART_IS_DEFINED(SAME70Q21B) \ + ) +/** @} */ + +/** + * \name SAM families + * @{ + */ +/** SAM3S Family */ +#define SAM3S (SAM3S1 || SAM3S2 || SAM3S4 || SAM3S8 || SAM3SD8) + +/** SAM3U Family */ +#define SAM3U (SAM3U1 || SAM3U2 || SAM3U4) + +/** SAM3N Family */ +#define SAM3N (SAM3N00 || SAM3N0 || SAM3N1 || SAM3N2 || SAM3N4) + +/** SAM3XA Family */ +#define SAM3XA (SAM3X4 || SAM3X8 || SAM3A4 || SAM3A8) + +/** SAM4S Family */ +#define SAM4S (SAM4S2 || SAM4S4 || SAM4S8 || SAM4S16 || SAM4SA16 || SAM4SD16 || SAM4SD32) + +/** SAM4L Family */ +#define SAM4L (SAM4LS || SAM4LC) + +/** SAMD20 Family */ +#define SAMD20 (SAMD20J || SAMD20G || SAMD20E) + +/** SAMD21 Family */ +#define SAMD21 (SAMD21J || SAMD21G || SAMD21E) + +/** SAMD09 Family */ +#define SAMD09 (SAMD09C || SAMD09D) + +/** SAMD10 Family */ +#define SAMD10 (SAMD10C || SAMD10DS || SAMD10DM || SAMD10DU) + +/** SAMD11 Family */ +#define SAMD11 (SAMD11C || SAMD11DS || SAMD11DM || SAMD11DU) + +/** SAMDA1 Family */ +#define SAMDA1 (SAMDA1J || SAMDA1G || SAMDA1E) + +/** SAMHA1 Family */ +#define SAMHA1 (SAMHA1G || SAMHA1E) + +/** SAMHA0 Family */ +#define SAMHA0 (SAMHA0G || SAMHA0E) + +/** SAMD Family */ +#define SAMD (SAMD20 || SAMD21 || SAMD09 || SAMD10 || SAMD11 || SAMDA1) + +/** SAMR21 Family */ +#define SAMR21 (SAMR21G || SAMR21E) + +/** SAMR30 Family */ +#define SAMR30 (SAMR30G || SAMR30E) + +/** SAMR34 Family */ +#define SAMR34 (SAMR34J) + +/** SAMR35 Family */ +#define SAMR35 (SAMR35J) + +/** SAMB11 Family */ +#define SAMB11 (SAMB11G || BTLC1000) + +/** SAML21 Family */ +#define SAML21 (SAML21J || SAML21G || SAML21E) + +/** SAML22 Family */ +#define SAML22 (SAML22J || SAML22G || SAML22N) +/** SAMC20 Family */ +#define SAMC20 (SAMC20J || SAMC20G || SAMC20E) + +/** SAMC21 Family */ +#define SAMC21 (SAMC21J || SAMC21G || SAMC21E) + +/** SAM4E Family */ +#define SAM4E (SAM4E8 || SAM4E16) + +/** SAM4N Family */ +#define SAM4N (SAM4N8 || SAM4N16) + +/** SAM4C Family */ +#define SAM4C_0 (SAM4C4_0 || SAM4C8_0 || SAM4C16_0 || SAM4C32_0) +#define SAM4C_1 (SAM4C4_1 || SAM4C8_1 || SAM4C16_1 || SAM4C32_1) +#define SAM4C (SAM4C4 || SAM4C8 || SAM4C16 || SAM4C32) + +/** SAM4CM Family */ +#define SAM4CM_0 (SAM4CMP8_0 || SAM4CMP16_0 || SAM4CMP32_0 || \ + SAM4CMS4_0 || SAM4CMS8_0 || SAM4CMS16_0 || SAM4CMS32_0) +#define SAM4CM_1 (SAM4CMP8_1 || SAM4CMP16_1 || SAM4CMP32_1 || \ + SAM4CMS4_1 || SAM4CMS8_1 || SAM4CMS16_1 || SAM4CMS32_1) +#define SAM4CM (SAM4CMP8 || SAM4CMP16 || SAM4CMP32 || \ + SAM4CMS4 || SAM4CMS8 || SAM4CMS16 || SAM4CMS32) + +/** SAM4CP Family */ +#define SAM4CP_0 (SAM4CP16_0) +#define SAM4CP_1 (SAM4CP16_1) +#define SAM4CP (SAM4CP16) + +/** SAMG Family */ +#define SAMG (SAMG51 || SAMG53 || SAMG54 || SAMG55) + +/** SAMB Family */ +#define SAMB (SAMB11) + +/** SAMV71 Family */ +#define SAMV71 (SAMV71J || SAMV71N || SAMV71Q || SAMV71JB || SAMV71NB || SAMV71QB) +#define SAMV71B (SAMV71JB || SAMV71NB || SAMV71QB) + +/** SAMV70 Family */ +#define SAMV70 (SAMV70J || SAMV70N || SAMV70Q || SAMV70JB || SAMV70NB || SAMV70QB) +#define SAMV70B (SAMV70JB || SAMV70NB || SAMV70QB) + +/** SAME70 Family */ +#define SAME70 (SAME70J || SAME70N || SAME70Q || SAME70JB || SAME70NB || SAME70QB) +#define SAME70B (SAME70JB || SAME70NB || SAME70QB) + +/** SAMS70 Family */ +#define SAMS70 (SAMS70J || SAMS70N || SAMS70Q || SAMS70JB || SAMS70NB || SAMS70QB) +#define SAMS70B (SAMS70JB || SAMS70NB || SAMS70QB) + +/** SAM0 product line (cortex-m0+) */ +#define SAM0 (SAMD20 || SAMD21 || SAMR21 || SAMD10 || SAMD11 || SAML21 ||\ + SAMDA1 || SAMC20 || SAMC21 || SAML22 || SAMD09 || SAMR30 || SAMHA1 ||\ + SAMHA0 || SAMR34 || SAMR35) + +/** @} */ + +/** SAM product line */ +#define SAM (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4L || SAM4E || \ + SAM0 || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG || SAMV71 || SAMV70 || SAME70 || SAMS70) + +/** @} */ + +/** @} */ + +/** @} */ + +#endif /* ATMEL_PARTS_H */ diff --git a/hw-libs/drivers/SAMx70/ASF/common/utils/stdio/read.c b/hw-libs/drivers/SAMx70/ASF/common/utils/stdio/read.c new file mode 100644 index 000000000..3812bd75a --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/utils/stdio/read.c @@ -0,0 +1,164 @@ +/** + * \file + * + * \brief System-specific implementation of the \ref _read function used by + * the standard library. + * + * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "compiler.h" + +/** + * \defgroup group_common_utils_stdio Standard I/O (stdio) + * + * Common standard I/O driver that implements the stdio + * read and write functions on AVR and SAM devices. + * + * \{ + */ + +extern volatile void *volatile stdio_base; +void (*ptr_get)(void volatile*, char*); + + +// IAR common implementation +#if ( defined(__ICCAVR32__) || defined(__ICCAVR__) || defined(__ICCARM__) ) + +#include + +#if (__VER__ < 8010000) +// Refer http://ftp.iar.se/WWWfiles/arm/webic/doc/EWARM_MigrationGuide.ENU.pdf +_STD_BEGIN +#endif + + +#pragma module_name = "?__read" + +/*! \brief Reads a number of bytes, at most \a size, into the memory area + * pointed to by \a buffer. + * + * \param handle File handle to read from. + * \param buffer Pointer to buffer to write read bytes to. + * \param size Number of bytes to read. + * + * \return The number of bytes read, \c 0 at the end of the file, or + * \c _LLIO_ERROR on failure. + */ +size_t __read(int handle, unsigned char *buffer, size_t size) +{ + int nChars = 0; + // This implementation only reads from stdin. + // For all other file handles, it returns failure. + if (handle != _LLIO_STDIN) { + return _LLIO_ERROR; + } + for (; size > 0; --size) { + ptr_get(stdio_base, (char*)buffer); + buffer++; + nChars++; + } + return nChars; +} + +/*! \brief This routine is required by IAR DLIB library since EWAVR V6.10 + * the implementation is empty to be compatible with old IAR version. + */ +int __close(int handle) +{ + UNUSED(handle); + return 0; +} + +/*! \brief This routine is required by IAR DLIB library since EWAVR V6.10 + * the implementation is empty to be compatible with old IAR version. + */ +int remove(const char* val) +{ + UNUSED(val); + return 0; +} + +/*! \brief This routine is required by IAR DLIB library since EWAVR V6.10 + * the implementation is empty to be compatible with old IAR version. + */ +long __lseek(int handle, long val, int val2) +{ + UNUSED(handle); + UNUSED(val2); + return val; +} + +#if (__VER__ < 8010000) +// Refer http://ftp.iar.se/WWWfiles/arm/webic/doc/EWARM_MigrationGuide.ENU.pdf +_STD_END +#endif + +// GCC AVR32 and SAM implementation +#elif (defined(__GNUC__) && !XMEGA && !MEGA) + +int __attribute__((weak)) +_read (int file, char * ptr, int len); // Remove GCC compiler warning + +int __attribute__((weak)) +_read (int file, char * ptr, int len) +{ + int nChars = 0; + + if (file != 0) { + return -1; + } + + for (; len > 0; --len) { + ptr_get(stdio_base, ptr); + ptr++; + nChars++; + } + return nChars; +} + +// GCC AVR implementation +#elif (defined(__GNUC__) && (XMEGA || MEGA) ) + +int _read (int *f); // Remove GCC compiler warning + +int _read (int *f) +{ + char c; + ptr_get(stdio_base,&c); + return c; +} +#endif + +/** + * \} + */ + diff --git a/hw-libs/drivers/SAMx70/ASF/common/utils/stdio/stdio_serial/stdio_serial.h b/hw-libs/drivers/SAMx70/ASF/common/utils/stdio/stdio_serial/stdio_serial.h new file mode 100644 index 000000000..86aeadd52 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/utils/stdio/stdio_serial/stdio_serial.h @@ -0,0 +1,119 @@ +/** + * + * \file + * + * \brief Common Standard I/O Serial Management. + * + * This file defines a useful set of functions for the Stdio Serial interface on AVR + * and SAM devices. + * + * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + ******************************************************************************/ +/* + * Support and FAQ: visit Microchip Support + */ + + +#ifndef _STDIO_SERIAL_H_ +#define _STDIO_SERIAL_H_ + +/** + * \defgroup group_common_utils_stdio_stdio_serial Standard serial I/O (stdio) + * \ingroup group_common_utils_stdio + * + * Common standard serial I/O management driver that + * implements a stdio serial interface on AVR and SAM devices. + * + * \{ + */ + +#include +#include "compiler.h" +#ifndef SAMD20 +# include "sysclk.h" +#endif +#include "serial.h" + +#if (XMEGA || MEGA_RF) && defined(__GNUC__) + extern int _write (char c, int *f); + extern int _read (int *f); +#endif + + +//! Pointer to the base of the USART module instance to use for stdio. +extern volatile void *volatile stdio_base; +//! Pointer to the external low level write function. +extern int (*ptr_put)(void volatile*, char); + +//! Pointer to the external low level read function. +extern void (*ptr_get)(void volatile*, char*); + +/*! \brief Initializes the stdio in Serial Mode. + * + * \param usart Base address of the USART instance. + * \param opt Options needed to set up RS232 communication (see \ref usart_options_t). + * + */ +static inline void stdio_serial_init(volatile void *usart, const usart_serial_options_t *opt) +{ + stdio_base = (void *)usart; + ptr_put = (int (*)(void volatile*,char))&usart_serial_putchar; + ptr_get = (void (*)(void volatile*,char*))&usart_serial_getchar; +# if (XMEGA || MEGA_RF) + usart_serial_init((USART_t *)usart,opt); +# elif UC3 + usart_serial_init(usart,(usart_serial_options_t *)opt); +# elif SAM + usart_serial_init((Usart *)usart,(usart_serial_options_t *)opt); +# else +# error Unsupported chip type +# endif + +# if defined(__GNUC__) +# if (XMEGA || MEGA_RF) + // For AVR GCC libc print redirection uses fdevopen. + fdevopen((int (*)(char, FILE*))(_write),(int (*)(FILE*))(_read)); +# endif +# if UC3 || SAM + // For AVR32 and SAM GCC + // Specify that stdout and stdin should not be buffered. + setbuf(stdout, NULL); + setbuf(stdin, NULL); + // Note: Already the case in IAR's Normal DLIB default configuration + // and AVR GCC library: + // - printf() emits one character at a time. + // - getchar() requests only 1 byte to exit. +# endif +# endif +} + +/** + * \} + */ + +#endif // _STDIO_SERIAL_H_ diff --git a/hw-libs/drivers/SAMx70/ASF/common/utils/stdio/write.c b/hw-libs/drivers/SAMx70/ASF/common/utils/stdio/write.c new file mode 100644 index 000000000..3765ed05a --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/common/utils/stdio/write.c @@ -0,0 +1,143 @@ +/** + * \file + * + * \brief System-specific implementation of the \ref _write function used by + * the standard library. + * + * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "compiler.h" + +/** + * \addtogroup group_common_utils_stdio + * + * \{ + */ + +volatile void *volatile stdio_base; +int (*ptr_put)(void volatile*, char); + + +#if ( defined(__ICCAVR32__) || defined(__ICCAVR__) || defined(__ICCARM__)) + +#include + +#if (__VER__ < 8010000) +// Refer http://ftp.iar.se/WWWfiles/arm/webic/doc/EWARM_MigrationGuide.ENU.pdf +_STD_BEGIN +#endif + +#pragma module_name = "?__write" + +/*! \brief Writes a number of bytes, at most \a size, from the memory area + * pointed to by \a buffer. + * + * If \a buffer is zero then \ref __write performs flushing of internal buffers, + * if any. In this case, \a handle can be \c -1 to indicate that all handles + * should be flushed. + * + * \param handle File handle to write to. + * \param buffer Pointer to buffer to read bytes to write from. + * \param size Number of bytes to write. + * + * \return The number of bytes written, or \c _LLIO_ERROR on failure. + */ +size_t __write(int handle, const unsigned char *buffer, size_t size) +{ + size_t nChars = 0; + + if (buffer == 0) { + // This means that we should flush internal buffers. + return 0; + } + + // This implementation only writes to stdout and stderr. + // For all other file handles, it returns failure. + if (handle != _LLIO_STDOUT && handle != _LLIO_STDERR) { + return _LLIO_ERROR; + } + + for (; size != 0; --size) { + if (ptr_put(stdio_base, *buffer++) < 0) { + return _LLIO_ERROR; + } + ++nChars; + } + return nChars; +} + +#if (__VER__ < 8010000) +// Refer http://ftp.iar.se/WWWfiles/arm/webic/doc/EWARM_MigrationGuide.ENU.pdf +_STD_END +#endif + + +#elif (defined(__GNUC__) && !XMEGA && !MEGA) + +int __attribute__((weak)) +_write (int file, const char *ptr, int len); + +int __attribute__((weak)) +_write (int file, const char *ptr, int len) +{ + int nChars = 0; + + if ((file != 1) && (file != 2) && (file!=3)) { + return -1; + } + + for (; len != 0; --len) { + if (ptr_put(stdio_base, *ptr++) < 0) { + return -1; + } + ++nChars; + } + return nChars; +} + +#elif (defined(__GNUC__) && (XMEGA || MEGA)) + +int _write (char c, int *f); + +int _write (char c, int *f) +{ + if (ptr_put(stdio_base, c) < 0) { + return -1; + } + return 1; +} +#endif + +/** + * \} + */ + diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/afec/afec.c b/hw-libs/drivers/SAMx70/ASF/sam/drivers/afec/afec.c new file mode 100644 index 000000000..1ca12df84 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/afec/afec.c @@ -0,0 +1,721 @@ +/** + * \file + * + * \brief Analog-Front-End Controller driver for SAM. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "afec.h" +#include "sleepmgr.h" +#include "status_codes.h" +#include "sysclk.h" +#include "pmc.h" + +/** + * \defgroup sam_drivers_afec_group Analog-Front-End Controller + * + * See \ref sam_afec_quickstart. + * + * Driver for the Analog-Front-End Controller. This driver provides access to + * the main features of the AFEC controller. + * + * @{ + */ +#if defined(AFEC1) +#define NUM_OF_AFEC (2UL) +#else +#define NUM_OF_AFEC (1UL) +#endif + +/* The gap between bit EOC15 and DRDY in interrupt register */ +#if defined __SAM4E8C__ || defined __SAM4E16C__ || defined __SAM4E8CB__ || defined __SAM4E16CB__ +#define AFEC_INTERRUPT_GAP1 (17UL) +#elif defined __SAM4E8E__ || defined __SAM4E16E__ +#define AFEC_INTERRUPT_GAP1 (8UL) +#elif (SAMV71 || SAMV70 || SAME70 || SAMS70) +/* The gap between bit EOC11 and DRDY in interrupt register */ +#define AFEC_INTERRUPT_GAP1 (12UL) +#endif + +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) +/* The gap between bit COMPE and TEMPCHG in interrupt register */ +#define AFEC_INTERRUPT_GAP2 (3UL) +#else +/* The gap between bit RXBUFF and TEMPCHG in interrupt register */ +#define AFEC_INTERRUPT_GAP2 (1UL) +#endif + +/* The number of channel in channel sequence1 register */ +#define AFEC_SEQ1_CHANNEL_NUM (8UL) + +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) +/* The interrupt source number of temperature sensor */ +#define AFEC_TEMP_INT_SOURCE_NUM (11UL) +#else +/* The interrupt source number of temperature sensor */ +#define AFEC_TEMP_INT_SOURCE_NUM (15UL) +#endif + +afec_callback_t afec_callback_pointer[NUM_OF_AFEC][_AFEC_NUM_OF_INTERRUPT_SOURCE]; + + +/** + * \internal + * \brief Get AFEC instance number. + * + * \param afec Base address of the AFEC + * + * \return AFEC instance number + */ +static uint32_t afec_find_inst_num(Afec *const afec) +{ +#if defined(AFEC1) + if (afec == AFEC1) { + return 1; + } +#endif +#if defined(AFEC0) + if (afec == AFEC0) { + return 0; + } +#endif + return 0; +} + +/** + * \internal + * \brief Get AFEC Peripheral ID. + * + * \param afec Base address of the AFEC + * + * \return AFEC Peripheral ID + */ +static uint32_t afec_find_pid(Afec *const afec) +{ +#if defined(ID_AFEC1) + if (afec == AFEC1) { + return ID_AFEC1; + } +#endif +#if defined(ID_AFEC0) + if (afec == AFEC0) { + return ID_AFEC0; + } +#endif + return ID_AFEC0; +} + +/** + * \internal + * \brief Configure the AFEC Module. + * + * \param afec Base address of the AFEC + * \param config Configuration for the AFEC + */ +static void afec_set_config(Afec *const afec, struct afec_config *config) +{ + uint32_t reg = 0; + + reg = (config->useq ? AFEC_MR_USEQ_REG_ORDER : 0) | + #if (SAMV71 || SAMV70 || SAME70 || SAMS70) + AFEC_MR_PRESCAL((config->mck / config->afec_clock )- 1) | + AFEC_MR_ONE | + #else + (config->anach ? AFEC_MR_ANACH_ALLOWED : 0) | + AFEC_MR_PRESCAL(config->mck / (2 * config->afec_clock) - 1) | + (config->settling_time) | + #endif + AFEC_MR_TRACKTIM(config->tracktim) | + AFEC_MR_TRANSFER(config->transfer) | + (config->startup_time); + + afec->AFEC_MR = reg; + + afec->AFEC_EMR = (config->tag ? AFEC_EMR_TAG : 0) | + (config->resolution) | + (config->stm ? AFEC_EMR_STM : 0); + #if (SAMV71 || SAMV70 || SAME70 || SAMS70) + afec->AFEC_ACR = AFEC_ACR_IBCTL(config->ibctl) | AFEC_ACR_PGA0EN | AFEC_ACR_PGA1EN; + #else + afec->AFEC_ACR = AFEC_ACR_IBCTL(config->ibctl); + #endif +} + +/** + * \brief Configure the AFEC channel. + * + * \param afec Base address of the AFEC + * \param channel The channel number + * \param config Configuration for the AFEC channel + */ +void afec_ch_set_config(Afec *const afec, const enum afec_channel_num channel, + struct afec_ch_config *config) +{ + afec_ch_sanity_check(afec, channel); + uint32_t reg = 0; + + reg = afec->AFEC_DIFFR; + reg &= ~(0x1u << channel); + reg |= (config->diff) ? (0x1u << channel) : 0; + afec->AFEC_DIFFR = reg; + + reg = afec->AFEC_CGR; + reg &= ~(0x03u << (2 * channel)); + reg |= (config->gain) << (2 * channel); + afec->AFEC_CGR = reg; +} + +/** + * \brief Configure the AFEC temperature sensor. + * + * \param afec Base address of the AFEC + * \param config Configuration for the AFEC temperature sensor + */ +void afec_temp_sensor_set_config(Afec *const afec, + struct afec_temp_sensor_config *config) +{ + Assert(afec == AFEC0); + + uint32_t reg = 0; + + reg = ((config->rctc) ? AFEC_TEMPMR_RTCT : 0) | (config->mode); + afec->AFEC_TEMPMR = reg; + + afec->AFEC_TEMPCWR = AFEC_TEMPCWR_TLOWTHRES(config->low_threshold) | + AFEC_TEMPCWR_THIGHTHRES(config->high_threshold); + +} + +/** + * \brief Get the AFEC default configurations. + * + * Use to initialize the configuration structure to known default values. This + * function should be called at the start of any AFEC initiation. + * + * The default configuration is as follows: + * - 12 -bit resolution + * - AFEC clock frequency is 6MHz + * - Start Up Time is 64 periods AFEC clock, for SAMV71 is 24 periods AFEC clock + * - Analog Settling Time is 3 periods of AFEC clock + * - Tracking Time is 3 periods of AFEC clock + * - Transfer Period is 5 periods AFEC clock,for SAMV71 is 7 periods AFEC clock + * - Allows different analog settings for each channel + * - The controller converts channels in a simple numeric order + * - Appends the channel number to the conversion result in AFE_LDCR register + * - Only a Single Trigger is required to get an averaged value + * - AFE Bias Current Control value is 1 + * + * \param cfg Pointer to configuration structure to be initiated. + */ +void afec_get_config_defaults(struct afec_config *const cfg) +{ + /* Sanity check argument. */ + Assert(cfg); + + cfg->resolution = AFEC_12_BITS; + cfg->mck = sysclk_get_cpu_hz(); + cfg->afec_clock = 6000000UL; + cfg->startup_time = AFEC_STARTUP_TIME_4; + #if !(SAMV71 || SAMV70 || SAME70 || SAMS70) + cfg->settling_time = AFEC_SETTLING_TIME_0; + #endif + cfg->tracktim = 2; + cfg->transfer = 1; + cfg->anach = true; + cfg->useq = false; + cfg->tag = true; + cfg->stm = true; + cfg->ibctl = 1; +} + +/** + * \brief Get the AFEC channel default configurations. + * + * Use to initialize the configuration structure to known default values. + * + * The default configuration is as follows: + * - Single Ended Mode + * - Gain value is 1 + * + * \param cfg Pointer to channel configuration structure to be initiated. + */ +void afec_ch_get_config_defaults(struct afec_ch_config *const cfg) +{ + /*Sanity check argument. */ + Assert(cfg); + + cfg->diff = false; + cfg->gain = AFEC_GAINVALUE_1; + +} + +/** + * \brief Get the AFEC Temperature Sensor default configurations. + * + * Use to initialize the configuration structure to known default values. + * + * The default configuration is as follows: + * - The temperature sensor measure is not triggered by RTC event + * - Generates an event when the converted data is in the comparison window + * - The window range is 0xFF ~ 0xFFF + * + * \param cfg Pointer to temperature sensor configuration structure + * to be initiated. + */ +void afec_temp_sensor_get_config_defaults( + struct afec_temp_sensor_config *const cfg) +{ + /*Sanity check argument. */ + Assert(cfg); + + cfg->rctc = false; + cfg->mode= AFEC_TEMP_CMP_MODE_2; + cfg->low_threshold= 0xFF; + cfg->high_threshold= 0xFFF; +} + +/** + * \brief Initialize the AFEC Module. + * + * \param afec Base address of the AFEC + * \param config Configuration for the AFEC + * + * \retval STATUS_OK Initialization is finished. + * \retval STATUS_ERR_BUSY Initialization failed. + */ +enum status_code afec_init(Afec *const afec, struct afec_config *config) +{ + Assert(afec); + Assert(config); + + if ((afec_get_interrupt_status(afec) & AFEC_ISR_DRDY) == AFEC_ISR_DRDY) { + return STATUS_ERR_BUSY; + } + + /* Reset and configure the AFEC module */ + afec->AFEC_CR = AFEC_CR_SWRST; + afec_set_config(afec, config); + + uint32_t i; + if(afec == AFEC0) { + for (i = 0; i < _AFEC_NUM_OF_INTERRUPT_SOURCE; i++){ + afec_callback_pointer[0][i] = 0; + } + } + if(afec == AFEC1) { + for (i = 0; i < _AFEC_NUM_OF_INTERRUPT_SOURCE; i++){ + afec_callback_pointer[1][i] = 0; + } + } + + return STATUS_OK; +} + +/** + * \brief Configure comparison mode. + * + * \param afec Base address of the AFEC. + * \param mode Comparison mode. + * \param channel Comparison Selected Channel. + * \param cmp_filter Compare Event Filtering. + */ +void afec_set_comparison_mode(Afec *const afec, + const enum afec_cmp_mode mode, + const enum afec_channel_num channel, uint8_t cmp_filter) +{ + if (channel != AFEC_CHANNEL_ALL) { + afec_ch_sanity_check(afec, channel); + } + + uint32_t reg; + + reg = afec->AFEC_EMR; + + reg &= ~(AFEC_EMR_CMPSEL_Msk | + AFEC_EMR_CMPMODE_Msk | + AFEC_EMR_CMPFILTER_Msk); + reg |= mode | + ((channel == AFEC_CHANNEL_ALL) ? AFEC_EMR_CMPALL + : AFEC_EMR_CMPSEL(channel)) | + AFEC_EMR_CMPFILTER(cmp_filter); + + afec->AFEC_EMR = reg; +} + +/** + * \brief Configure AFEC power mode. + * + * \param afec Base address of the AFEC. + * \param mode AFEC power mode value. + */ +void afec_set_power_mode(Afec *const afec, + const enum afec_power_mode mode) +{ + uint32_t reg; + + reg = afec->AFEC_MR; + + switch(mode) { + case AFEC_POWER_MODE_0: + reg &= ~(AFEC_MR_FWUP_ON | AFEC_MR_SLEEP_SLEEP); + break; + case AFEC_POWER_MODE_1: + reg |= AFEC_MR_FWUP_ON; + break; + case AFEC_POWER_MODE_2: + reg |= AFEC_MR_SLEEP_SLEEP; + reg &= ~AFEC_MR_FWUP_ON; + break; + } + + afec->AFEC_MR = reg; +} + +/** + * \brief Set callback for AFEC + * + * \param afec Base address of the AFEC + * \param source Interrupt source + * \param callback Callback function pointer + * \param irq_level Interrupt level + */ +void afec_set_callback(Afec *const afec, enum afec_interrupt_source source, + afec_callback_t callback, uint8_t irq_level) +{ + Assert(afec); + Assert(callback); + + uint32_t i = afec_find_inst_num(afec); + afec_callback_pointer[i][source] = callback; + if (!i) { + irq_register_handler(AFEC0_IRQn, irq_level); + } else if (i == 1) { + irq_register_handler(AFEC1_IRQn, irq_level); + } + /* Enable the specified interrupt source */ + afec_enable_interrupt(afec, source); +} + +/** + * \brief Enable AFEC interrupts. + * + * \param afec Base address of the AFEC. + * \param interrupt_source Interrupts to be enabled. + */ +void afec_enable_interrupt(Afec *const afec, + enum afec_interrupt_source interrupt_source) +{ + if (interrupt_source == AFEC_INTERRUPT_ALL) { + afec->AFEC_IER = AFEC_INTERRUPT_ALL; + return; + } + + if (interrupt_source < AFEC_INTERRUPT_DATA_READY) { + #if (SAMV71 || SAMV70 || SAME70 || SAMS70) + if (interrupt_source == AFEC_INTERRUPT_EOC_11) { + afec->AFEC_IER = 1 << AFEC_TEMP_INT_SOURCE_NUM; + #else + if (interrupt_source == AFEC_INTERRUPT_EOC_15) { + afec->AFEC_IER = 1 << AFEC_TEMP_INT_SOURCE_NUM; + #endif + } else { + afec->AFEC_IER = 1 << interrupt_source; + } + } else if (interrupt_source < AFEC_INTERRUPT_TEMP_CHANGE) { + afec->AFEC_IER = 1 << (interrupt_source + AFEC_INTERRUPT_GAP1); + } else { + afec->AFEC_IER = 1 << (interrupt_source + AFEC_INTERRUPT_GAP1 + + AFEC_INTERRUPT_GAP2); + } +} + +/** + * \brief Disable AFEC interrupts. + * + * \param afec Base address of the AFEC. + * \param interrupt_source Interrupts to be disabled. + */ +void afec_disable_interrupt(Afec *const afec, + enum afec_interrupt_source interrupt_source) +{ + if (interrupt_source == AFEC_INTERRUPT_ALL) { + afec->AFEC_IDR = AFEC_INTERRUPT_ALL; + return; + } + + if (interrupt_source < AFEC_INTERRUPT_DATA_READY) { + #if (SAMV71 || SAMV70 || SAME70 || SAMS70) + if (interrupt_source == AFEC_INTERRUPT_EOC_11) { + afec->AFEC_IDR = 1 << AFEC_TEMP_INT_SOURCE_NUM; + #else + if (interrupt_source == AFEC_INTERRUPT_EOC_15) { + afec->AFEC_IDR = 1 << AFEC_TEMP_INT_SOURCE_NUM; + #endif + } else { + afec->AFEC_IDR = 1 << interrupt_source; + } + } else if (interrupt_source < AFEC_INTERRUPT_TEMP_CHANGE) { + afec->AFEC_IDR = 1 << (interrupt_source + AFEC_INTERRUPT_GAP1); + } else { + afec->AFEC_IDR = 1 << (interrupt_source + AFEC_INTERRUPT_GAP1 + + AFEC_INTERRUPT_GAP2); + } +} + +/** + * \internal + * \brief Common AFEC interrupt handler + * + * The optional callback used by the interrupt handler is set by the + * afec_set_callback() function. + * + * \param inst_num AFEC instance number to handle interrupt for + * \param source Interrupt source number + */ +static void afec_interrupt(uint8_t inst_num, + enum afec_interrupt_source source) +{ + if (afec_callback_pointer[inst_num][source]) { + afec_callback_pointer[inst_num][source](); + } +} + +/** + * \internal + * \brief Call the callback function if the corresponding interrupt is asserted + * + * \param afec Base address of the AFEC. + */ +static void afec_process_callback(Afec *const afec) +{ + volatile uint32_t status; + uint32_t cnt, inst_num; + + status = afec_get_interrupt_status(afec) & afec_get_interrupt_mask(afec); + inst_num = afec_find_inst_num(afec); + + for (cnt = 0; cnt < _AFEC_NUM_OF_INTERRUPT_SOURCE; cnt++) { + if (cnt < AFEC_INTERRUPT_DATA_READY) { + #if defined __SAM4E8C__ || defined __SAM4E16C__ || defined __SAM4E8CB__ || defined __SAM4E16CB__ + if(cnt == AFEC_INTERRUPT_EOC_15) { + if (status & (1 << AFEC_TEMP_INT_SOURCE_NUM)) { + afec_interrupt(inst_num, (enum afec_interrupt_source)cnt); + } + } else { + if (status & (1 << cnt)) { + afec_interrupt(inst_num, (enum afec_interrupt_source)cnt); + } + } + #elif defined __SAM4E8E__ || defined __SAM4E16E__ || SAMV71 || SAMV70 || SAMS70 || SAME70 + if (status & (1 << cnt)) { + afec_interrupt(inst_num, (enum afec_interrupt_source)cnt); + } + #endif + } else if (cnt < AFEC_INTERRUPT_TEMP_CHANGE) { + if (status & (1 << (cnt + AFEC_INTERRUPT_GAP1))) { + afec_interrupt(inst_num, (enum afec_interrupt_source)cnt); + } + } else { + if (status & (1 << (cnt + AFEC_INTERRUPT_GAP1 + AFEC_INTERRUPT_GAP2))) { + afec_interrupt(inst_num, (enum afec_interrupt_source)cnt); + } + } + } +} + +/** + * \brief Interrupt handler for AFEC0. + */ +void AFEC0_Handler(void) +{ + afec_process_callback(AFEC0); +} + +/** + * \brief Interrupt handler for AFEC1. + */ +void AFEC1_Handler(void) +{ + afec_process_callback(AFEC1); +} + +/** + * \brief Enable AFEC Module. + * + * \param afec Base address of the AFEC + */ +void afec_enable(Afec *const afec) +{ + Assert(afec); + uint32_t pid; + + pid = afec_find_pid(afec); + /* Enable peripheral clock. */ + pmc_enable_periph_clk(pid); + sleepmgr_lock_mode(SLEEPMGR_SLEEP_WFI); +} + +/** + * \brief Disable AFEC Module. + * + * \param afec Base address of the AFEC + */ +void afec_disable(Afec *const afec) +{ + Assert(afec); + uint32_t pid; + + pid = afec_find_pid(afec); + /* Disable peripheral clock. */ + pmc_disable_periph_clk(pid); + sleepmgr_unlock_mode(SLEEPMGR_SLEEP_WFI); +} + +/** + * \brief Configure conversion sequence. + * + * \param afec Base address of the AFEC. + * \param ch_list Channel sequence list. + * \param uc_num Number of channels in the list. + */ +void afec_configure_sequence(Afec *const afec, + const enum afec_channel_num ch_list[], uint8_t uc_num) +{ + uint8_t uc_counter; + + /* Set user sequence mode */ + afec->AFEC_MR |= AFEC_MR_USEQ_REG_ORDER; + afec->AFEC_SEQ1R = 0; + afec->AFEC_SEQ2R = 0; + + if (uc_num < AFEC_SEQ1_CHANNEL_NUM) { + for (uc_counter = 0; uc_counter < uc_num; uc_counter++) { + afec->AFEC_SEQ1R |= + ch_list[uc_counter] << (4 * uc_counter); + } + } else { + for (uc_counter = 0; uc_counter < AFEC_SEQ1_CHANNEL_NUM; uc_counter++) { + afec->AFEC_SEQ1R |= + ch_list[uc_counter] << (4 * uc_counter); + } + for (uc_counter = 0; uc_counter < uc_num - AFEC_SEQ1_CHANNEL_NUM; + uc_counter++) { + afec->AFEC_SEQ2R |= + ch_list[uc_counter + AFEC_SEQ1_CHANNEL_NUM] << (4 * uc_counter); + } + } +} + +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Configure Automatic Error Correction. + * + * \param afec Base address of the AFEC + * \param channel Number of channels in the list. + * \param offsetcorr the Offset Correction value,signed value + * \param gaincorr the Gain Correction value. + */ +void afec_configure_auto_error_correction(Afec *const afec, + const enum afec_channel_num channel, int16_t offsetcorr, uint16_t gaincorr) +{ + + + if (channel != AFEC_CHANNEL_ALL) { + afec_ch_sanity_check(afec, channel); + } + + uint32_t reg = 0; + reg = afec->AFEC_CECR; + reg = (channel == AFEC_CHANNEL_ALL)? 0 : ~(0x1u << channel); + reg |= (channel == AFEC_CHANNEL_ALL)? AFEC_CHANNEL_ALL : (0x1u << channel); + afec->AFEC_CECR = reg; + + afec->AFEC_COSR = AFEC_COSR_CSEL; + afec->AFEC_CVR = AFEC_CVR_OFFSETCORR(offsetcorr) | AFEC_CVR_GAINCORR(gaincorr); + +} + +/** + * \brief correct the Converted Data of the selected channel if automatic error correction is enabled. + * + * \param afec Base address of the AFEC. + * \param afec_ch AFEC channel number. + * + * \return AFEC corrected value of the selected channel. + */ + uint32_t afec_get_correction_value(Afec *const afec, + const enum afec_channel_num afec_ch) +{ + uint32_t corrected_data = 0; + uint32_t converted_data = 0; + + afec_ch_sanity_check(afec, afec_ch); + + afec->AFEC_CSELR = afec_ch; + converted_data = afec->AFEC_CDR; + + corrected_data = (converted_data + (afec->AFEC_CVR & AFEC_CVR_OFFSETCORR_Msk)) * + (afec->AFEC_CVR >> AFEC_CVR_GAINCORR_Pos) / 1024u; + return corrected_data; + +} + +/** + * \brief Configure sample&hold mode. + * + * \param afec Base address of the AFEC. + * \param channel AFEC Channel number. + * \param mode sample&hold mode. + */ +void afec_set_sample_hold_mode(Afec *const afec, + const enum afec_channel_num channel, const enum afec_sample_hold_mode mode) +{ + if (channel != AFEC_CHANNEL_ALL) { + afec_ch_sanity_check(afec, channel); + } + + uint32_t reg = 0; + reg = afec->AFEC_SHMR; + if (mode == AFEC_SAMPLE_HOLD_MODE_1) { + + reg |= (channel == AFEC_CHANNEL_ALL)? AFEC_CHANNEL_ALL : 0x1u << channel; + } + else { + + reg = (channel == AFEC_CHANNEL_ALL)? 0 : ~(0x1u << channel); + } + afec->AFEC_SHMR = reg; + +} +#endif + +//@} diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/afec/afec.h b/hw-libs/drivers/SAMx70/ASF/sam/drivers/afec/afec.h new file mode 100644 index 000000000..c8e8593c5 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/afec/afec.h @@ -0,0 +1,797 @@ +/** + * \file + * + * \brief Analog-Front-End Controller driver for SAM. + * + * Copyright (c) 2013-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef AFEC_H_INCLUDED +#define AFEC_H_INCLUDED + +#include "compiler.h" +#include "status_codes.h" + +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) +/** Definitions for AFEC resolution */ +enum afec_resolution { + AFEC_12_BITS = AFEC_EMR_RES_NO_AVERAGE, /* AFEC 12-bit resolution */ + AFEC_13_BITS = AFEC_EMR_RES_OSR4, /* AFEC 13-bit resolution */ + AFEC_14_BITS = AFEC_EMR_RES_OSR16, /* AFEC 14-bit resolution */ + AFEC_15_BITS = AFEC_EMR_RES_OSR64, /* AFEC 15-bit resolution */ + AFEC_16_BITS = AFEC_EMR_RES_OSR256 /* AFEC 16-bit resolution */ +}; +#else +/** Definitions for AFEC resolution */ +enum afec_resolution { + AFEC_10_BITS = AFEC_EMR_RES_LOW_RES, /* AFEC 10-bit resolution */ + AFEC_12_BITS = AFEC_EMR_RES_NO_AVERAGE, /* AFEC 12-bit resolution */ + AFEC_13_BITS = AFEC_EMR_RES_OSR4, /* AFEC 13-bit resolution */ + AFEC_14_BITS = AFEC_EMR_RES_OSR16, /* AFEC 14-bit resolution */ + AFEC_15_BITS = AFEC_EMR_RES_OSR64, /* AFEC 15-bit resolution */ + AFEC_16_BITS = AFEC_EMR_RES_OSR256 /* AFEC 16-bit resolution */ +}; +#endif +/** Definitions for AFEC power mode */ +enum afec_power_mode { + /* AFEC core on and reference voltage circuitry on */ + AFEC_POWER_MODE_0 = 0, + /* AFEC core off and reference voltage circuitry on */ + AFEC_POWER_MODE_1, + /* AFEC core off and reference voltage circuitry off */ + AFEC_POWER_MODE_2 +}; + +/** Definitions for AFEC trigger */ +enum afec_trigger { + /* Starting a conversion is only possible by software. */ + AFEC_TRIG_SW = AFEC_MR_TRGEN_DIS, + /* External trigger */ + AFEC_TRIG_EXT = AFEC_MR_TRGSEL_AFEC_TRIG0 | AFEC_MR_TRGEN, + /* TIO Output of the Timer Counter Channel 0 */ + AFEC_TRIG_TIO_CH_0 = AFEC_MR_TRGSEL_AFEC_TRIG1 | AFEC_MR_TRGEN, + /* TIO Output of the Timer Counter Channel 1 */ + AFEC_TRIG_TIO_CH_1 = AFEC_MR_TRGSEL_AFEC_TRIG2 | AFEC_MR_TRGEN, + /* TIO Output of the Timer Counter Channel 2 */ + AFEC_TRIG_TIO_CH_2 = AFEC_MR_TRGSEL_AFEC_TRIG3 | AFEC_MR_TRGEN, + /* PWM Event Line 0 */ + AFEC_TRIG_PWM_EVENT_LINE_0 = AFEC_MR_TRGSEL_AFEC_TRIG4 | AFEC_MR_TRGEN, + /* PWM Event Line 1 */ + AFEC_TRIG_PWM_EVENT_LINE_1 = AFEC_MR_TRGSEL_AFEC_TRIG5 | AFEC_MR_TRGEN, +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) + /*Analog Comparator*/ + AFEC_TRIG_ANALOG_COMPARATOR = AFEC_MR_TRGSEL_AFEC_TRIG6 | AFEC_MR_TRGEN, +#endif + /* Freerun mode conversion. */ + AFEC_TRIG_FREERUN = 0xFF, +}; + +#if defined __SAM4E8C__ || defined __SAM4E16C__ || defined __SAM4E8CB__ || defined __SAM4E16CB__ +/** Definitions for AFEC channel number */ +enum afec_channel_num { + AFEC_CHANNEL_0 = 0, + AFEC_CHANNEL_1, + AFEC_CHANNEL_2, + AFEC_CHANNEL_3, + AFEC_CHANNEL_4, + AFEC_CHANNEL_5, + AFEC_TEMPERATURE_SENSOR = 15, + AFEC_CHANNEL_ALL = 0x803F, +} ; +#elif defined __SAM4E8E__ || defined __SAM4E16E__ +/** Definitions for AFEC channel number */ +enum afec_channel_num { + AFEC_CHANNEL_0 = 0, + AFEC_CHANNEL_1, + AFEC_CHANNEL_2, + AFEC_CHANNEL_3, + AFEC_CHANNEL_4, + AFEC_CHANNEL_5, + AFEC_CHANNEL_6, + AFEC_CHANNEL_7, + AFEC_CHANNEL_8, + AFEC_CHANNEL_9, + AFEC_CHANNEL_10, + AFEC_CHANNEL_11, + AFEC_CHANNEL_12, + AFEC_CHANNEL_13, + AFEC_CHANNEL_14, + AFEC_TEMPERATURE_SENSOR, + AFEC_CHANNEL_ALL = 0xFFFF, +} ; +#elif (SAMV71 || SAMV70 || SAME70 || SAMS70) +/** Definitions for AFEC channel number */ +enum afec_channel_num { + AFEC_CHANNEL_0 = 0, + AFEC_CHANNEL_1, + AFEC_CHANNEL_2, + AFEC_CHANNEL_3, + AFEC_CHANNEL_4, + AFEC_CHANNEL_5, + AFEC_CHANNEL_6, + AFEC_CHANNEL_7, + AFEC_CHANNEL_8, + AFEC_CHANNEL_9, + AFEC_CHANNEL_10, + AFEC_TEMPERATURE_SENSOR, + AFEC_CHANNEL_ALL = 0x0FFF, +} ; + +#define NB_CH_AFE0 (12UL) +#define NB_CH_AFE1 (12UL) +#endif + +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) +enum afec_sample_hold_mode { + /*Single Sample-and-Hold mode*/ + AFEC_SAMPLE_HOLD_MODE_0, + /*Dual Sample-and-Hold mode*/ + AFEC_SAMPLE_HOLD_MODE_1, +}; +#endif + +/** Definitions for AFEC gain value */ +enum afec_gainvalue { + AFEC_GAINVALUE_0 = 0, + AFEC_GAINVALUE_1 = 1, + AFEC_GAINVALUE_2 = 2, + AFEC_GAINVALUE_3 = 3 +}; + +/** Definitions for AFEC Start Up Time */ +enum afec_startup_time { + AFEC_STARTUP_TIME_0 = AFEC_MR_STARTUP_SUT0, + AFEC_STARTUP_TIME_1 = AFEC_MR_STARTUP_SUT8, + AFEC_STARTUP_TIME_2 = AFEC_MR_STARTUP_SUT16, + AFEC_STARTUP_TIME_3 = AFEC_MR_STARTUP_SUT24, + AFEC_STARTUP_TIME_4 = AFEC_MR_STARTUP_SUT64, + AFEC_STARTUP_TIME_5 = AFEC_MR_STARTUP_SUT80, + AFEC_STARTUP_TIME_6 = AFEC_MR_STARTUP_SUT96, + AFEC_STARTUP_TIME_7 = AFEC_MR_STARTUP_SUT112, + AFEC_STARTUP_TIME_8 = AFEC_MR_STARTUP_SUT512, + AFEC_STARTUP_TIME_9 = AFEC_MR_STARTUP_SUT576, + AFEC_STARTUP_TIME_10 = AFEC_MR_STARTUP_SUT640, + AFEC_STARTUP_TIME_11 = AFEC_MR_STARTUP_SUT704, + AFEC_STARTUP_TIME_12 = AFEC_MR_STARTUP_SUT768, + AFEC_STARTUP_TIME_13 = AFEC_MR_STARTUP_SUT832, + AFEC_STARTUP_TIME_14 = AFEC_MR_STARTUP_SUT896, + AFEC_STARTUP_TIME_15 = AFEC_MR_STARTUP_SUT960 +}; + +#if SAM4E +/** Definitions for AFEC analog settling time */ +enum afec_settling_time { + AFEC_SETTLING_TIME_0 = AFEC_MR_SETTLING_AST3, + AFEC_SETTLING_TIME_1 = AFEC_MR_SETTLING_AST5, + AFEC_SETTLING_TIME_2 = AFEC_MR_SETTLING_AST9, + AFEC_SETTLING_TIME_3 = AFEC_MR_SETTLING_AST17 +}; +#endif + +/** Definitions for Comparison Mode */ +enum afec_cmp_mode { + AFEC_CMP_MODE_0 = AFEC_EMR_CMPMODE_LOW, + AFEC_CMP_MODE_1 = AFEC_EMR_CMPMODE_HIGH, + AFEC_CMP_MODE_2 = AFEC_EMR_CMPMODE_IN, + AFEC_CMP_MODE_3 = AFEC_EMR_CMPMODE_OUT +}; + +/** Definitions for Temperature Comparison Mode */ +enum afec_temp_cmp_mode { + AFEC_TEMP_CMP_MODE_0 = AFEC_TEMPMR_TEMPCMPMOD_LOW, + AFEC_TEMP_CMP_MODE_1 = AFEC_TEMPMR_TEMPCMPMOD_HIGH, + AFEC_TEMP_CMP_MODE_2 = AFEC_TEMPMR_TEMPCMPMOD_IN, + AFEC_TEMP_CMP_MODE_3 = AFEC_TEMPMR_TEMPCMPMOD_OUT +}; + +/** + * \brief Analog-Front-End Controller configuration structure. + * + * Configuration structure for a Analog-Front-End Controller instance. + * This structure could be initialized by the \ref afec_get_config_defaults() + * function before being modified by the user application. + */ +struct afec_config { + /** Resolution */ + enum afec_resolution resolution; + /** Master Clock */ + uint32_t mck; + /** AFEC Clock */ + uint32_t afec_clock; + /** Start Up Time */ + enum afec_startup_time startup_time; + #if SAM4E + /** Analog Settling Time = (settling_time + 1) / AFEC clock */ + enum afec_settling_time settling_time; + #endif + /** Tracking Time = tracktim / AFEC clock */ + uint8_t tracktim; + /** Transfer Period = (transfer * 2 + 3) / AFEC clock */ + uint8_t transfer; + /** Analog Change */ + bool anach; + /** Use Sequence Enable */ + bool useq; + /** TAG of AFE_LDCR register */ + bool tag; + /** Single Trigger Mode */ + bool stm; + /** AFE Bias Current Control */ + uint8_t ibctl; +}; + +/** AFEC channel configuration structure.*/ +struct afec_ch_config { + /** Differential Mode */ + bool diff; + /** Gain Value */ + enum afec_gainvalue gain; +}; + +/** AFEC Temperature Sensor configuration structure.*/ +struct afec_temp_sensor_config { + /** RTC Trigger mode */ + bool rctc; + /** Temperature Comparison Mode */ + enum afec_temp_cmp_mode mode; + /** Temperature Low Threshold */ + uint16_t low_threshold; + /** Temperature High Threshold */ + uint16_t high_threshold; +}; + +#if defined __SAM4E8C__ || defined __SAM4E16C__ || defined __SAM4E8CB__ || defined __SAM4E16CB__ +/** AFEC interrupt source type */ +enum afec_interrupt_source { + AFEC_INTERRUPT_EOC_0 = 0, + AFEC_INTERRUPT_EOC_1, + AFEC_INTERRUPT_EOC_2, + AFEC_INTERRUPT_EOC_3, + AFEC_INTERRUPT_EOC_4, + AFEC_INTERRUPT_EOC_5, + AFEC_INTERRUPT_EOC_15, + AFEC_INTERRUPT_DATA_READY, + AFEC_INTERRUPT_OVERRUN_ERROR, + AFEC_INTERRUPT_COMP_ERROR, + AFEC_INTERRUPT_END_RXBUF, + AFEC_INTERRUPT_RXBUF_FULL, + AFEC_INTERRUPT_TEMP_CHANGE, + AFEC_INTERRUPT_END_CAL, + _AFEC_NUM_OF_INTERRUPT_SOURCE, + AFEC_INTERRUPT_ALL = 0xDF00803F, +}; +#elif defined __SAM4E8E__ || defined __SAM4E16E__ +/** AFEC interrupt source type */ +enum afec_interrupt_source { + AFEC_INTERRUPT_EOC_0 = 0, + AFEC_INTERRUPT_EOC_1, + AFEC_INTERRUPT_EOC_2, + AFEC_INTERRUPT_EOC_3, + AFEC_INTERRUPT_EOC_4, + AFEC_INTERRUPT_EOC_5, + AFEC_INTERRUPT_EOC_6, + AFEC_INTERRUPT_EOC_7, + AFEC_INTERRUPT_EOC_8, + AFEC_INTERRUPT_EOC_9, + AFEC_INTERRUPT_EOC_10, + AFEC_INTERRUPT_EOC_11, + AFEC_INTERRUPT_EOC_12, + AFEC_INTERRUPT_EOC_13, + AFEC_INTERRUPT_EOC_14, + AFEC_INTERRUPT_EOC_15, + AFEC_INTERRUPT_DATA_READY, + AFEC_INTERRUPT_OVERRUN_ERROR, + AFEC_INTERRUPT_COMP_ERROR, + AFEC_INTERRUPT_END_RXBUF, + AFEC_INTERRUPT_RXBUF_FULL, + AFEC_INTERRUPT_TEMP_CHANGE, + AFEC_INTERRUPT_END_CAL, + _AFEC_NUM_OF_INTERRUPT_SOURCE, + AFEC_INTERRUPT_ALL = 0xDF00FFFF, +}; +#elif (SAMV71 || SAMV70 || SAME70 || SAMS70) +/** AFEC interrupt source type */ +enum afec_interrupt_source { + AFEC_INTERRUPT_EOC_0 = 0, + AFEC_INTERRUPT_EOC_1, + AFEC_INTERRUPT_EOC_2, + AFEC_INTERRUPT_EOC_3, + AFEC_INTERRUPT_EOC_4, + AFEC_INTERRUPT_EOC_5, + AFEC_INTERRUPT_EOC_6, + AFEC_INTERRUPT_EOC_7, + AFEC_INTERRUPT_EOC_8, + AFEC_INTERRUPT_EOC_9, + AFEC_INTERRUPT_EOC_10, + AFEC_INTERRUPT_EOC_11, + AFEC_INTERRUPT_DATA_READY, + AFEC_INTERRUPT_OVERRUN_ERROR, + AFEC_INTERRUPT_COMP_ERROR, + AFEC_INTERRUPT_TEMP_CHANGE, + _AFEC_NUM_OF_INTERRUPT_SOURCE, + AFEC_INTERRUPT_ALL = 0x47000FFF, +}; +#endif + +typedef void (*afec_callback_t)(void); + +void afec_get_config_defaults(struct afec_config *const cfg); +void afec_ch_get_config_defaults(struct afec_ch_config *const cfg); +void afec_temp_sensor_get_config_defaults( + struct afec_temp_sensor_config *const cfg); +enum status_code afec_init(Afec *const afec, struct afec_config *const config); +void afec_temp_sensor_set_config(Afec *const afec, + struct afec_temp_sensor_config *config); +void afec_ch_set_config(Afec *const afec, const enum afec_channel_num channel, + struct afec_ch_config *config); +void afec_configure_sequence(Afec *const afec, + const enum afec_channel_num ch_list[], const uint8_t uc_num); +void afec_enable(Afec *const afec); +void afec_disable(Afec *const afec); +void afec_set_callback(Afec *const afec, enum afec_interrupt_source source, + afec_callback_t callback, uint8_t irq_level); + +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) +void afec_configure_auto_error_correction(Afec *const afec, + const enum afec_channel_num channel,int16_t offsetcorr, uint16_t gaincorr); + +uint32_t afec_get_correction_value(Afec *const afec, + const enum afec_channel_num afec_ch); +void afec_set_sample_hold_mode(Afec *const afec, + const enum afec_channel_num channel,const enum afec_sample_hold_mode mode); + +#endif +/** + * \internal + * \brief AFEC channel sanity check + * + * \param afec Base address of the AFEC. + * \param channel AFEC channel number. + * + */ +static inline void afec_ch_sanity_check(Afec *const afec, + const enum afec_channel_num channel) +{ + if (afec == AFEC0) { + #if defined __SAM4E8C__ || defined __SAM4E16C__ || defined __SAM4E8CB__ || defined __SAM4E16CB__ + Assert((channel < NB_CH_AFE0) || (channel == AFEC_TEMPERATURE_SENSOR)); + #elif defined __SAM4E8E__ || defined __SAM4E16E__ + Assert(channel < NB_CH_AFE0); + #elif (SAMV71 || SAMV70 || SAME70 || SAMS70) + Assert(channel < NB_CH_AFE0); + #endif + } else if (afec == AFEC1) { + Assert(channel < NB_CH_AFE1); + } + UNUSED(channel); +} + +/** + * \brief Configure conversion trigger and free run mode. + * + * \param afec Base address of the AFEC. + * \param trigger Conversion trigger. + * + */ +static inline void afec_set_trigger(Afec *const afec, + const enum afec_trigger trigger) +{ + uint32_t reg; + + reg = afec->AFEC_MR; + + if (trigger == AFEC_TRIG_FREERUN) { + reg |= AFEC_MR_FREERUN_ON; + } else { + reg &= ~(AFEC_MR_TRGSEL_Msk | AFEC_MR_TRGEN | AFEC_MR_FREERUN_ON); + reg |= trigger; + } + + afec->AFEC_MR = reg; +} + +/** + * \brief Configure conversion resolution. + * + * \param afec Base address of the AFEC. + * \param res Conversion resolution. + * + */ +static inline void afec_set_resolution(Afec *const afec, + const enum afec_resolution res) +{ + uint32_t reg; + + reg = afec->AFEC_EMR; + + reg &= ~AFEC_EMR_RES_Msk; + reg |= res; + + afec->AFEC_EMR = reg; +} + +void afec_set_comparison_mode(Afec *const afec, + const enum afec_cmp_mode mode, const enum afec_channel_num channel, + uint8_t cmp_filter); + +/** + * \brief Get comparison mode. + * + * \param afec Base address of the AFEC. + * + * \retval Compare mode value. + */ +static inline enum afec_cmp_mode afec_get_comparison_mode(Afec *const afec) +{ + return (enum afec_cmp_mode)(afec->AFEC_EMR & AFEC_EMR_CMPMODE_Msk); +} + +/** + * \brief Configure AFEC compare window. + * + * \param afec Base address of the AFEC. + * \param us_low_threshold Low threshold of compare window. + * \param us_high_threshold High threshold of compare window. + */ +static inline void afec_set_comparison_window(Afec *const afec, + const uint16_t us_low_threshold, const uint16_t us_high_threshold) +{ + afec->AFEC_CWR = AFEC_CWR_LOWTHRES(us_low_threshold) | + AFEC_CWR_HIGHTHRES(us_high_threshold); +} + +/** + * \brief Enable or disable write protection of AFEC registers. + * + * \param afec Base address of the AFEC. + * \param is_enable 1 to enable, 0 to disable. + */ +static inline void afec_set_writeprotect(Afec *const afec, + const bool is_enable) +{ + if (is_enable) { + afec->AFEC_WPMR = AFEC_WPMR_WPEN | AFEC_WPMR_WPKEY_PASSWD; + } else { + afec->AFEC_WPMR = AFEC_WPMR_WPKEY_PASSWD; + } +} + +/** + * \brief Indicate write protect status. + * + * \param afec Base address of the AFEC. + * + * \return 0 if no write protect violation occurred, or 16-bit write protect + * violation source. + */ +static inline uint32_t afec_get_writeprotect_status(Afec *const afec) +{ + uint32_t reg_value; + + reg_value = afec->AFEC_WPSR; + if (reg_value & AFEC_WPSR_WPVS) { + return (reg_value & AFEC_WPSR_WPVSRC_Msk) >> AFEC_WPSR_WPVSRC_Pos; + } else { + return 0; + } +} + +/** + * \brief Get AFEC overrun error status. + * + * \param afec Base address of the AFEC. + * + * \return AFEC overrun error status. + */ +static inline uint32_t afec_get_overrun_status(Afec *const afec) +{ + return afec->AFEC_OVER; +} + +/** + * \brief Start analog-to-digital conversion. + * + * \note If one of the hardware event is selected as AFEC trigger, + * this function can NOT start analog to digital conversion. + * + * \param afec Base address of the AFEC. + */ +static inline void afec_start_software_conversion(Afec *const afec) +{ + afec->AFEC_CR = AFEC_CR_START; +} + +void afec_set_power_mode(Afec *const afec, + const enum afec_power_mode mode); + +/** + * \brief Enable the specified AFEC channel. + * + * \param afec Base address of the AFEC. + * \param afec_ch AFEC channel number. + */ +static inline void afec_channel_enable(Afec *const afec, + const enum afec_channel_num afec_ch) +{ + if (afec_ch != AFEC_CHANNEL_ALL) { + afec_ch_sanity_check(afec, afec_ch); + } + + afec->AFEC_CHER = (afec_ch == AFEC_CHANNEL_ALL) ? + AFEC_CHANNEL_ALL : 1 << afec_ch; +} + +/** + * \brief Disable the specified AFEC channel. + * + * \param afec Base address of the AFEC. + * \param afec_ch AFEC channel number. + */ +static inline void afec_channel_disable(Afec *const afec, + const enum afec_channel_num afec_ch) +{ + if (afec_ch != AFEC_CHANNEL_ALL) { + afec_ch_sanity_check(afec, afec_ch); + } + + afec->AFEC_CHDR = (afec_ch == AFEC_CHANNEL_ALL) ? + AFEC_CHANNEL_ALL : 1 << afec_ch; +} + +/** + * \brief Get the AFEC channel status. + * + * \param afec Base address of the AFEC. + * \param afec_ch AFEC channel number. + * + * \retval 1 if channel is enabled. + * \retval 0 if channel is disabled. + */ +static inline uint32_t afec_channel_get_status(Afec *const afec, + const enum afec_channel_num afec_ch) +{ + afec_ch_sanity_check(afec, afec_ch); + + return afec->AFEC_CHSR & (1 << afec_ch); +} + +/** + * \brief Read the Converted Data of the selected channel. + * + * \param afec Base address of the AFEC. + * \param afec_ch AFEC channel number. + * + * \return AFEC converted value of the selected channel. + */ +static inline uint32_t afec_channel_get_value(Afec *const afec, + enum afec_channel_num afec_ch) +{ + afec_ch_sanity_check(afec, afec_ch); + + afec->AFEC_CSELR = afec_ch; + return afec->AFEC_CDR; +} + +/** + * \brief Set analog offset to be used for channel CSEL. + * + * \param afec Base address of the AFEC. + * \param afec_ch AFEC channel number. + * \param aoffset Analog offset value. + */ +static inline void afec_channel_set_analog_offset(Afec *const afec, + enum afec_channel_num afec_ch, uint16_t aoffset) +{ + afec_ch_sanity_check(afec, afec_ch); + + afec->AFEC_CSELR = afec_ch; + afec->AFEC_COCR = (aoffset & AFEC_COCR_AOFF_Msk); +} + +/** + * \brief Get the Last Data Converted. + * + * \param afec Base address of the AFEC. + * + * \return AFEC latest converted value. + */ +static inline uint32_t afec_get_latest_value(Afec *const afec) +{ + return afec->AFEC_LCDR & AFEC_LCDR_LDATA_Msk; +} + +/** + * \brief Get the Last Converted Channel Number. + * + * \param afec Base address of the AFEC. + * + * \return AFEC Last Converted Channel Number. + */ +static inline uint32_t afec_get_latest_chan_num(Afec *const afec) +{ + return (afec->AFEC_LCDR & AFEC_LCDR_CHNB_Msk) >> AFEC_LCDR_CHNB_Pos; +} + +void afec_enable_interrupt(Afec *const afec, + enum afec_interrupt_source interrupt_source); + +void afec_disable_interrupt(Afec *const afec, + enum afec_interrupt_source interrupt_source); + +/** + * \brief Get AFEC interrupt status. + * + * \param afec Base address of the AFEC. + * + * \return The interrupt status value. + */ +static inline uint32_t afec_get_interrupt_status(Afec *const afec) +{ + return afec->AFEC_ISR; +} + +/** + * \brief Get AFEC interrupt mask. + * + * \param afec Base address of the AFEC. + * + * \return The interrupt mask value. + */ +static inline uint32_t afec_get_interrupt_mask(Afec *const afec) +{ + return afec->AFEC_IMR; +} + +#if SAM4E +/** + * \brief Get PDC registers base address. + * + * \param afec Base address of the AFEC. + * + * \return AFEC PDC register base address. + */ +static inline Pdc *afec_get_pdc_base(Afec *const afec) +{ + Pdc *p_pdc_base = NULL; + +#ifdef PDC_AFEC0 + if (afec == AFEC0) { + p_pdc_base = PDC_AFEC0; + } +#endif + +#ifdef PDC_AFEC1 + else if (afec == AFEC1) { + p_pdc_base = PDC_AFEC1; + } +#endif + + return p_pdc_base; +} + +/** + * \brief Launch an automatic calibration of the AFEC on next sequence. + * + * \param afec Base address of the AFEC. + * + * \retval STATUS_OK An automatic calibration is launched. + * \retval STATUS_ERR_BUSY Automatic calibration can not be launched because + * the AFEC is in freerun mode. + */ +static inline enum status_code afec_start_calibration(Afec *const afec) +{ + uint32_t reg; + + reg = afec->AFEC_CHSR; + afec->AFEC_CDOR = reg; + + if ((afec->AFEC_MR & AFEC_MR_FREERUN) == AFEC_MR_FREERUN_ON) { + return STATUS_ERR_BUSY; + } + afec->AFEC_CR = AFEC_CR_AUTOCAL; + return STATUS_OK; +} +#endif + +/** + * \page sam_afec_quickstart Quickstart guide for SAM AFEC driver + * + * This is the quickstart guide for the \ref sam_drivers_afec_group + * "SAM AFEC driver" with step-by-step instructions on how to configure and use + * the driver in a selection of use cases. + * + * The use cases contain several code fragments. The code fragments in the + * steps for setup can be copied into a custom initialization function, while + * the steps for usage can be copied into, e.g., the main application function. + * + * \section afec_basic_use_case Basic use case + * In this basic use case, the AFEC module and single channel are configured for: + * - 12 -bit resolution + * - AFEC clock frequency is 6MHz + * - Start Up Time is 64 periods AFEC clock + * - Analog Settling Time is 3 periods of AFEC clock + * - Tracking Time is 3 periods of AFEC clock + * - Transfer Period is 5 periods AFEC clock + * - Allows different analog settings for each channel + * - The controller converts channels in a simple numeric order + * - Appends the channel number to the conversion result in AFE_LDCR register + * - Only a Single Trigger is required to get an averaged value + * - AFE Bias Current Control value is 1 + * - Software triggering of conversions + * - Single channel measurement + * - AFEC_CHANNEL_5 of AFEC0 as input + * + * \subsection sam_afec_quickstart_prereq Prerequisites + * -# \ref sysclk_group "System Clock Management (Sysclock)" + * + * \section afec_basic_use_case_setup Setup steps + * \subsection afec_basic_use_case_setup_code Example code + * Add to application C-file: + * \code + afec_enable(AFEC0); + afec_get_config_defaults(&afec_cfg); + afec_init(AFEC0, &afec_cfg); + afec_set_trigger(AFEC0, AFEC_TRIG_SW); + afec_channel_enable(AFEC0, AFEC_CHANNEL_5); +\endcode + * + * \subsection afec_basic_use_case_setup_flow Workflow + * -# Enable AFEC Module: + * - \code afec_enable(AFEC0); \endcode + * -# Get the AFEC default configurations: + * - \code afec_get_config_defaults(&afec_cfg); \endcode + * -# Initialize the AFEC Module: + * - \code afec_init(AFEC0, &afec_cfg); \endcode + * -# Configure conversion trigger and free run mode: + * - \code afec_set_trigger(AFEC0, AFEC_TRIG_SW); \endcode + * -# Enable Channel: + * - \code afec_channel_enable(AFEC0, AFEC_CHANNEL_5); \endcode + * + * \section afec_basic_use_case_usage Usage steps + * \subsection afec_basic_use_case_usage_code Example code + * Add to, e.g., main loop in application C-file: + * \code + afec_start_software_conversion(AFEC0); + while (afec_get_interrupt_status(AFEC0) & (1 << AFEC_CHANNEL_5)); + uint32_t result = afec_channel_get_value(AFEC0, AFEC_CHANNEL_5); +\endcode + * + * \subsection afec_basic_use_case_usage_flow Workflow + * -# Start AFEC conversion on channel: + * - \code afec_start_software_conversion(AFEC0); \endcode + * -# Wait for the conversion over: + * - \code while (afec_get_interrupt_status(AFEC0) & (1 << AFEC_CHANNEL_5)); +\endcode + * -# Get the conversion result: + * - \code uint32_t result = afec_channel_get_value(AFEC0, AFEC_CHANNEL_5); +\endcode + */ +#endif /* AFEC_H_INCLUDED */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/efc/efc.c b/hw-libs/drivers/SAMx70/ASF/sam/drivers/efc/efc.c new file mode 100644 index 000000000..0fa7d5353 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/efc/efc.c @@ -0,0 +1,438 @@ +/** + * \file + * + * \brief Enhanced Embedded Flash Controller (EEFC) driver for SAM. + * + * Copyright (c) 2011-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#include "efc.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \defgroup sam_drivers_efc_group Enhanced Embedded Flash Controller (EEFC) + * + * The Enhanced Embedded Flash Controller ensures the interface of the Flash + * block with the 32-bit internal bus. + * + * @{ + */ + +/* Address definition for read operation */ +#if (SAM3XA || SAM3U4 || SAM4SD16 || SAM4SD32) +# define READ_BUFF_ADDR0 IFLASH0_ADDR +# define READ_BUFF_ADDR1 IFLASH1_ADDR +#elif (SAM3S || SAM3N || SAM4E || SAM4N || SAMG || SAMV71 || SAMV70 || SAMS70 || SAME70) +# define READ_BUFF_ADDR IFLASH_ADDR +#elif (SAM4C || SAM4CP || SAM4CM) +#if (SAM4C32 || SAM4CMS32 || SAM4CMP32) +# define READ_BUFF_ADDR0 IFLASH0_CNC_ADDR +# define READ_BUFF_ADDR1 IFLASH1_CNC_ADDR +#else +# define READ_BUFF_ADDR IFLASH_CNC_ADDR +#endif +#elif (SAM3U || SAM4S) +# define READ_BUFF_ADDR IFLASH0_ADDR +#else +# warning Only reading unique ID for sam3/4 is implemented. +#endif + +/* Flash Writing Protection Key */ +#define FWP_KEY 0x5Au + +#if (SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM) +#define EEFC_FCR_FCMD(value) \ + ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos))) +#define EEFC_ERROR_FLAGS (EEFC_FSR_FLOCKE | EEFC_FSR_FCMDE | EEFC_FSR_FLERR) +#elif (SAMV71 || SAMV70 || SAMS70 || SAME70) +#define EEFC_ERROR_FLAGS (EEFC_FSR_FLOCKE | EEFC_FSR_FCMDE | EEFC_FSR_FLERR \ + | EEFC_FSR_UECCELSB | EEFC_FSR_MECCELSB | EEFC_FSR_UECCEMSB | EEFC_FSR_MECCEMSB) +#else +#define EEFC_ERROR_FLAGS (EEFC_FSR_FLOCKE | EEFC_FSR_FCMDE) +#endif + +#ifndef EEFC_FCR_FKEY_PASSWD +#define EEFC_FCR_FKEY_PASSWD EEFC_FCR_FKEY(FWP_KEY) +#endif + + +/* + * Local function declaration. + * Because they are RAM functions, they need 'extern' declaration. + */ +extern void efc_write_fmr(Efc *p_efc, uint32_t ul_fmr); +extern uint32_t efc_perform_fcr(Efc *p_efc, uint32_t ul_fcr); + +/** + * \brief Initialize the EFC controller. + * + * \param ul_access_mode 0 for 128-bit, EEFC_FMR_FAM for 64-bit. + * \param ul_fws The number of wait states in cycle (no shift). + * + * \return 0 if successful. + */ +uint32_t efc_init(Efc *p_efc, uint32_t ul_access_mode, uint32_t ul_fws) +{ +#if (SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || \ + SAMV71 || SAMV70 || SAMS70 || SAME70) + efc_write_fmr(p_efc, ul_access_mode | EEFC_FMR_FWS(ul_fws) | EEFC_FMR_CLOE); +#else + efc_write_fmr(p_efc, ul_access_mode | EEFC_FMR_FWS(ul_fws)); +#endif + return EFC_RC_OK; +} + +#if (SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || \ + SAMV71 || SAMV70 || SAMS70 || SAME70) +/** + * \brief Enable code loop optimization. + * + * \param p_efc Pointer to an EFC instance. + */ +void efc_enable_cloe(Efc *p_efc) +{ + uint32_t ul_fmr = p_efc->EEFC_FMR; + efc_write_fmr(p_efc, ul_fmr | EEFC_FMR_CLOE); +} + +/** + * \brief Disable code loop optimization. + * + * \param p_efc Pointer to an EFC instance. + */ +void efc_disable_cloe(Efc *p_efc) +{ + uint32_t ul_fmr = p_efc->EEFC_FMR; + efc_write_fmr(p_efc, ul_fmr & (~EEFC_FMR_CLOE)); +} +#endif + + + +/** + * \brief Enable the flash ready interrupt. + * + * \param p_efc Pointer to an EFC instance. + */ +void efc_enable_frdy_interrupt(Efc *p_efc) +{ + uint32_t ul_fmr = p_efc->EEFC_FMR; + + efc_write_fmr(p_efc, ul_fmr | EEFC_FMR_FRDY); +} + +/** + * \brief Disable the flash ready interrupt. + * + * \param p_efc Pointer to an EFC instance. + */ +void efc_disable_frdy_interrupt(Efc *p_efc) +{ + uint32_t ul_fmr = p_efc->EEFC_FMR; + + efc_write_fmr(p_efc, ul_fmr & (~EEFC_FMR_FRDY)); +} + +#if (SAMV71 || SAMV70 || SAMS70 || SAME70) +/** + * \brief Enable the write protection. + * + * \param p_efc Pointer to an EFC instance. + */ +void efc_enable_write_protection(Efc *p_efc) +{ + p_efc->EEFC_WPMR = EEFC_WPMR_WPKEY_PASSWD | EEFC_WPMR_WPEN; +} + +/** + * \brief Disable the write protection. + * + * \param p_efc Pointer to an EFC instance. + */ +void efc_disable_write_protection(Efc *p_efc) +{ + p_efc->EEFC_WPMR = EEFC_WPMR_WPKEY_PASSWD; +} +#else +/** + * \brief Set flash access mode. + * + * \param p_efc Pointer to an EFC instance. + * \param ul_mode 0 for 128-bit, EEFC_FMR_FAM for 64-bit. + */ +void efc_set_flash_access_mode(Efc *p_efc, uint32_t ul_mode) +{ + uint32_t ul_fmr = p_efc->EEFC_FMR & (~EEFC_FMR_FAM); + + efc_write_fmr(p_efc, ul_fmr | ul_mode); +} + +/** + * \brief Get flash access mode. + * + * \param p_efc Pointer to an EFC instance. + * + * \return 0 for 128-bit or EEFC_FMR_FAM for 64-bit. + */ +uint32_t efc_get_flash_access_mode(Efc *p_efc) +{ + return (p_efc->EEFC_FMR & EEFC_FMR_FAM); +} +#endif + +/** + * \brief Set flash wait state. + * + * \param p_efc Pointer to an EFC instance. + * \param ul_fws The number of wait states in cycle (no shift). + */ +void efc_set_wait_state(Efc *p_efc, uint32_t ul_fws) +{ + uint32_t ul_fmr = p_efc->EEFC_FMR & (~EEFC_FMR_FWS_Msk); + + efc_write_fmr(p_efc, ul_fmr | EEFC_FMR_FWS(ul_fws)); +} + +/** + * \brief Get flash wait state. + * + * \param p_efc Pointer to an EFC instance. + * + * \return The number of wait states in cycle (no shift). + */ +uint32_t efc_get_wait_state(Efc *p_efc) +{ + return ((p_efc->EEFC_FMR & EEFC_FMR_FWS_Msk) >> EEFC_FMR_FWS_Pos); +} + +/** + * \brief Perform the given command and wait until its completion (or an error). + * + * \note Unique ID commands are not supported, use efc_perform_read_sequence. + * + * \param p_efc Pointer to an EFC instance. + * \param ul_command Command to perform. + * \param ul_argument Optional command argument. + * + * \note This function will automatically choose to use IAP function. + * + * \return 0 if successful, otherwise returns an error code. + */ +uint32_t efc_perform_command(Efc *p_efc, uint32_t ul_command, + uint32_t ul_argument) +{ + uint32_t result; + irqflags_t flags; + + /* Unique ID commands are not supported. */ + if (ul_command == EFC_FCMD_STUI || ul_command == EFC_FCMD_SPUI) { + return EFC_RC_NOT_SUPPORT; + } + + flags = cpu_irq_save(); + /* Use RAM Function. */ + result = efc_perform_fcr(p_efc, + EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FARG(ul_argument) | + EEFC_FCR_FCMD(ul_command)); + cpu_irq_restore(flags); + return result; +} + +/** + * \brief Get the current status of the EEFC. + * + * \note This function clears the value of some status bits (FLOCKE, FCMDE). + * + * \param p_efc Pointer to an EFC instance. + * + * \return The current status. + */ +uint32_t efc_get_status(Efc *p_efc) +{ + return p_efc->EEFC_FSR; +} + +/** + * \brief Get the result of the last executed command. + * + * \param p_efc Pointer to an EFC instance. + * + * \return The result of the last executed command. + */ +uint32_t efc_get_result(Efc *p_efc) +{ + return p_efc->EEFC_FRR; +} + +/** + * \brief Perform read sequence. Supported sequences are read Unique ID and + * read User Signature + * + * \param p_efc Pointer to an EFC instance. + * \param ul_cmd_st Start command to perform. + * \param ul_cmd_sp Stop command to perform. + * \param p_ul_buf Pointer to an data buffer. + * \param ul_size Buffer size. + * + * \return 0 if successful, otherwise returns an error code. + */ +__no_inline +RAMFUNC +uint32_t efc_perform_read_sequence(Efc *p_efc, + uint32_t ul_cmd_st, uint32_t ul_cmd_sp, + uint32_t *p_ul_buf, uint32_t ul_size) +{ + volatile uint32_t ul_status; + uint32_t ul_cnt; + +#if (SAM3U4 || SAM3XA || SAM4SD16 || SAM4SD32 || SAM4C32 || SAM4CMS32|| SAM4CMP32) + uint32_t *p_ul_data = + (uint32_t *) ((p_efc == EFC0) ? + READ_BUFF_ADDR0 : READ_BUFF_ADDR1); +#elif (SAM3S || SAM4S || SAM3N || SAM3U || SAM4E || SAM4N || SAM4C || SAMG || \ + SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAMS70 || SAME70) + uint32_t *p_ul_data = (uint32_t *) READ_BUFF_ADDR; +#else + return EFC_RC_NOT_SUPPORT; +#endif + + if (p_ul_buf == NULL) { + return EFC_RC_INVALID; + } + + p_efc->EEFC_FMR |= (0x1u << 16); + + /* Send the Start Read command */ +#if (SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || \ + SAMV71 || SAMV70 || SAMS70 || SAME70) + p_efc->EEFC_FCR = EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FARG(0) + | EEFC_FCR_FCMD(ul_cmd_st); +#else + p_efc->EEFC_FCR = EEFC_FCR_FKEY(FWP_KEY) | EEFC_FCR_FARG(0) + | EEFC_FCR_FCMD(ul_cmd_st); +#endif + /* Wait for the FRDY bit in the Flash Programming Status Register + * (EEFC_FSR) falls. + */ + do { + ul_status = p_efc->EEFC_FSR; + } while ((ul_status & EEFC_FSR_FRDY) == EEFC_FSR_FRDY); + + /* The data is located in the first address of the Flash + * memory mapping. + */ + for (ul_cnt = 0; ul_cnt < ul_size; ul_cnt++) { + p_ul_buf[ul_cnt] = p_ul_data[ul_cnt]; + } + + /* To stop the read mode */ + p_efc->EEFC_FCR = +#if (SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || \ + SAMV71 || SAMV70 || SAMS70 || SAME70) + EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FARG(0) | + EEFC_FCR_FCMD(ul_cmd_sp); +#else + EEFC_FCR_FKEY(FWP_KEY) | EEFC_FCR_FARG(0) | + EEFC_FCR_FCMD(ul_cmd_sp); +#endif + /* Wait for the FRDY bit in the Flash Programming Status Register (EEFC_FSR) + * rises. + */ + do { + ul_status = p_efc->EEFC_FSR; + } while ((ul_status & EEFC_FSR_FRDY) != EEFC_FSR_FRDY); + + p_efc->EEFC_FMR &= ~(0x1u << 16); + + return EFC_RC_OK; +} + +/** + * \brief Set mode register. + * + * \param p_efc Pointer to an EFC instance. + * \param ul_fmr Value of mode register + */ +__no_inline +RAMFUNC +void efc_write_fmr(Efc *p_efc, uint32_t ul_fmr) +{ + p_efc->EEFC_FMR = ul_fmr; +} + +/** + * \brief Perform command. + * + * \param p_efc Pointer to an EFC instance. + * \param ul_fcr Flash command. + * + * \return The current status. + */ +__no_inline +RAMFUNC +uint32_t efc_perform_fcr(Efc *p_efc, uint32_t ul_fcr) +{ + volatile uint32_t ul_status; + + p_efc->EEFC_FCR = ul_fcr; + do { + ul_status = p_efc->EEFC_FSR; + } while ((ul_status & EEFC_FSR_FRDY) != EEFC_FSR_FRDY); + + return (ul_status & EEFC_ERROR_FLAGS); +} + +//@} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/efc/efc.h b/hw-libs/drivers/SAMx70/ASF/sam/drivers/efc/efc.h new file mode 100644 index 000000000..fb4c2ee67 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/efc/efc.h @@ -0,0 +1,150 @@ +/** + * \file + * + * \brief Embedded Flash Controller (EFC) driver for SAM. + * + * Copyright (c) 2011-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef EFC_H_INCLUDED +#define EFC_H_INCLUDED + +#include "compiler.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/*! \name EFC return codes */ +//! @{ +typedef enum efc_rc { + EFC_RC_OK = 0, //!< Operation OK + EFC_RC_YES = 0, //!< Yes + EFC_RC_NO = 1, //!< No + EFC_RC_ERROR = 1, //!< General error + EFC_RC_INVALID, //!< Invalid argument input + EFC_RC_NOT_SUPPORT = 0xFFFFFFFF //!< Operation is not supported +} efc_rc_t; +//! @} + +/*! \name EFC command */ +//! @{ +#define EFC_FCMD_GETD 0x00 //!< Get Flash Descriptor +#define EFC_FCMD_WP 0x01 //!< Write page +#define EFC_FCMD_WPL 0x02 //!< Write page and lock +#define EFC_FCMD_EWP 0x03 //!< Erase page and write page +#define EFC_FCMD_EWPL 0x04 //!< Erase page and write page then lock +#define EFC_FCMD_EA 0x05 //!< Erase all +#if (SAM3S8 || SAM3SD8) +#define EFC_FCMD_EPL 0x06 //!< Erase plane +#endif +#if (SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || \ + SAMV71 || SAMV70 || SAMS70 || SAME70) +#define EFC_FCMD_EPA 0x07 //!< Erase pages +#endif +#define EFC_FCMD_SLB 0x08 //!< Set Lock Bit +#define EFC_FCMD_CLB 0x09 //!< Clear Lock Bit +#define EFC_FCMD_GLB 0x0A //!< Get Lock Bit +#define EFC_FCMD_SGPB 0x0B //!< Set GPNVM Bit +#define EFC_FCMD_CGPB 0x0C //!< Clear GPNVM Bit +#define EFC_FCMD_GGPB 0x0D //!< Get GPNVM Bit +#define EFC_FCMD_STUI 0x0E //!< Start unique ID +#define EFC_FCMD_SPUI 0x0F //!< Stop unique ID +#if (!SAM3U && !SAM3SD8 && !SAM3S8) +#define EFC_FCMD_GCALB 0x10 //!< Get CALIB Bit +#endif +#if (SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || \ + SAMV71 || SAMV70 || SAMS70 || SAME70) +#define EFC_FCMD_ES 0x11 //!< Erase sector +#define EFC_FCMD_WUS 0x12 //!< Write user signature +#define EFC_FCMD_EUS 0x13 //!< Erase user signature +#define EFC_FCMD_STUS 0x14 //!< Start read user signature +#define EFC_FCMD_SPUS 0x15 //!< Stop read user signature +#endif +//! @} + +/*! The IAP function entry address */ +#define CHIP_FLASH_IAP_ADDRESS (IROM_ADDR + 8) + +/*! \name EFC access mode */ +//! @{ +#define EFC_ACCESS_MODE_128 0 +#define EFC_ACCESS_MODE_64 EEFC_FMR_FAM +//! @} + +uint32_t efc_init(Efc *p_efc, uint32_t ul_access_mode, uint32_t ul_fws); +#if (SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || \ + SAMV71 || SAMV70 || SAMS70 || SAME70) +void efc_enable_cloe(Efc *p_efc); +void efc_disable_cloe(Efc *p_efc); +#endif +void efc_enable_frdy_interrupt(Efc *p_efc); +void efc_disable_frdy_interrupt(Efc *p_efc); +#if (SAMV71 || SAMV70 || SAMS70 || SAME70) +void efc_enable_write_protection(Efc *p_efc); +void efc_disable_write_protection(Efc *p_efc); +#else +void efc_set_flash_access_mode(Efc *p_efc, uint32_t ul_mode); +uint32_t efc_get_flash_access_mode(Efc *p_efc); +#endif +void efc_set_wait_state(Efc *p_efc, uint32_t ul_fws); +uint32_t efc_get_wait_state(Efc *p_efc); +uint32_t efc_perform_command(Efc *p_efc, uint32_t ul_command, + uint32_t ul_argument); +uint32_t efc_get_status(Efc *p_efc); +uint32_t efc_get_result(Efc *p_efc); +uint32_t efc_perform_read_sequence(Efc *p_efc, + uint32_t ul_cmd_st, uint32_t ul_cmd_sp, + uint32_t *p_ul_buf, uint32_t ul_size); + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +#endif /* EFC_H_INCLUDED */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/hsmci/hsmci.c b/hw-libs/drivers/SAMx70/ASF/sam/drivers/hsmci/hsmci.c new file mode 100644 index 000000000..13341057e --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/hsmci/hsmci.c @@ -0,0 +1,1077 @@ +/** + * \file + * + * \brief SAM HSMCI driver + * + * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include +#include "conf_board.h" +#include "sd_mmc_protocol.h" +#include "sysclk.h" +#include "pmc.h" +#include "hsmci.h" + +/** + * \ingroup sam_drivers_hsmci + * \defgroup sam_drivers_hsmci_internal High Speed MultiMedia Card Interface + * (HSMCI) implementation + * + * @{ + */ + +// Check configurations +#if (!defined SD_MMC_HSMCI_MEM_CNT) || (SD_MMC_HSMCI_MEM_CNT == 0) +# warning SD_MMC_HSMCI_MEM_CNT must be defined in board.h file. +# define SD_MMC_HSMCI_MEM_CNT 1 +#endif +#ifndef CONF_BOARD_SD_MMC_HSMCI +# warning CONF_BOARD_SD_MMC_HSMCI must be defined in conf_board.h file. +#endif +#if (SAM3XA) +# if (SD_MMC_HSMCI_MEM_CNT > 2) +# warning Wrong define SD_MMC_HSMCI_MEM_CNT in board.h,\ + this part have 2 slots maximum on HSMCI. +# endif +#else +# if (SD_MMC_HSMCI_MEM_CNT > 1) +# warning Wrong define SD_MMC_HSMCI_MEM_CNT in board.h,\ + this part have 1 slots maximum on HSMCI. +# endif +#endif +#ifndef SD_MMC_HSMCI_SLOT_0_SIZE +# warning SD_MMC_HSMCI_SLOT_0_SIZE must be defined in board.h. +# define SD_MMC_HSMCI_SLOT_0_SIZE 1 +#endif +#if (SD_MMC_HSMCI_MEM_CNT > 2) +# ifndef SD_MMC_HSMCI_SLOT_1_SIZE +# warning SD_MMC_HSMCI_SLOT_1_SIZE must be defined in board.h. +# define SD_MMC_HSMCI_SLOT_1_SIZE 1 +# endif +#endif + +// Enable debug information for SD/MMC SPI module +#ifdef HSMCI_DEBUG +# include +# define hsmci_debug(...) printf(__VA_ARGS__) +#else +# define hsmci_debug(...) +#endif + +#if (SAM3S || SAM4S || SAM4E) + // PDC is used for transfer +#elif (SAM3U || SAM3XA) + // DMA is used for transfer +# include "dmac.h" +# define DMA_HW_ID_HSMCI 0 +# ifndef CONF_HSMCI_DMA_CHANNEL +# define CONF_HSMCI_DMA_CHANNEL 0 +# endif +#elif (SAMV70 || SAMV71 || SAME70 || SAMS70) + // XDMAC is used for transfer +# include "xdmac.h" +# define XDMAC_HW_ID_HSMCI 0 +# ifndef CONF_HSMCI_XDMAC_CHANNEL +# define CONF_HSMCI_XDMAC_CHANNEL DMA_CH_SD_CARD +# endif +#else +# error Not supported device +#endif + +//! Current position (byte) of the transfer started by hsmci_adtc_start() +static uint32_t hsmci_transfert_pos; +//! Size block requested by last hsmci_adtc_start() +static uint16_t hsmci_block_size; +//! Total number of block requested by last hsmci_adtc_start() +static uint16_t hsmci_nb_block; + +static void hsmci_reset(void); +static void hsmci_set_speed(uint32_t speed, uint32_t mck); +static bool hsmci_wait_busy(void); +static bool hsmci_send_cmd_execute(uint32_t cmdr, sdmmc_cmd_def_t cmd, + uint32_t arg); + +/** + * \brief Reset the HSMCI interface + */ +static void hsmci_reset(void) +{ + uint32_t mr = HSMCI->HSMCI_MR; + uint32_t dtor = HSMCI->HSMCI_DTOR; + uint32_t sdcr = HSMCI->HSMCI_SDCR; + uint32_t cstor = HSMCI->HSMCI_CSTOR; + uint32_t cfg = HSMCI->HSMCI_CFG; + HSMCI->HSMCI_CR = HSMCI_CR_SWRST; + HSMCI->HSMCI_MR = mr; + HSMCI->HSMCI_DTOR = dtor; + HSMCI->HSMCI_SDCR = sdcr; + HSMCI->HSMCI_CSTOR = cstor; + HSMCI->HSMCI_CFG = cfg; +#ifdef HSMCI_SR_DMADONE + HSMCI->HSMCI_DMA = 0; +#endif +#if (SAMV70 || SAMV71 || SAME70 || SAMS70) +#ifdef HSMCI_DMA_DMAEN + HSMCI->HSMCI_DMA = 0; +#endif +#endif + // Enable the HSMCI + HSMCI->HSMCI_CR = HSMCI_CR_PWSEN | HSMCI_CR_MCIEN; +} + +/** + * \brief Set speed of the HSMCI clock. + * + * \param speed HSMCI clock speed in Hz. + * \param mck MCK clock speed in Hz. + */ +static void hsmci_set_speed(uint32_t speed, uint32_t mck) +{ +#if (SAM4E || SAMV70 || SAMV71 || SAME70 || SAMS70) + uint32_t clkdiv = 0; + uint32_t clkodd = 0; + // clock divider, represent (((clkdiv << 1) + clkodd) + 2) + uint32_t div = 0; + + // Speed = MCK clock / (((clkdiv << 1) + clkodd) + 2) + if ((speed * 2) < mck) { + div = (mck / speed) - 2; + if (mck % speed) { + // Ensure that the card speed not be higher than expected. + div++; + } + clkdiv = div >> 1; + // clkodd is the last significant bit of the clock divider (div). + clkodd = div % 2; + } else { + clkdiv = 0; + clkodd = 0; + } + + HSMCI->HSMCI_MR &= ~HSMCI_MR_CLKDIV_Msk; + HSMCI->HSMCI_MR |= HSMCI_MR_CLKDIV(clkdiv); + if (clkodd) { + HSMCI->HSMCI_MR |= HSMCI_MR_CLKODD; + } + else { + HSMCI->HSMCI_MR &= ~HSMCI_MR_CLKODD; + } +#else + uint32_t clkdiv = 0; + uint32_t rest = 0; + + // Speed = MCK clock / (2 * (CLKDIV + 1)) + if ((speed * 2) < mck) { + clkdiv = mck / (2 * speed); + rest = mck % (2 * speed); + if (rest > 0) { + // Ensure that the card speed not be higher than expected. + clkdiv++; + } + if (clkdiv > 0) { + clkdiv -= 1; + } + } else { + clkdiv = 0; + } + HSMCI->HSMCI_MR &= ~HSMCI_MR_CLKDIV_Msk; + HSMCI->HSMCI_MR |= HSMCI_MR_CLKDIV(clkdiv); +#endif + +} + +/** \brief Wait the end of busy signal on data line + * + * \return true if success, otherwise false + */ +static bool hsmci_wait_busy(void) +{ + uint32_t busy_wait = 0xFFFFFFFF; + uint32_t sr; + + do { + sr = HSMCI->HSMCI_SR; + if (busy_wait-- == 0) { + hsmci_debug("%s: timeout\n\r", __func__); + hsmci_reset(); + return false; + } + } while (!((sr & HSMCI_SR_NOTBUSY) && ((sr & HSMCI_SR_DTIP) == 0))); + return true; +} + + +/** \brief Send a command + * + * \param cmdr CMDR register bit to use for this command + * \param cmd Command definition + * \param arg Argument of the command + * + * \return true if success, otherwise false + */ +static bool hsmci_send_cmd_execute(uint32_t cmdr, sdmmc_cmd_def_t cmd, + uint32_t arg) +{ + uint32_t sr; + + cmdr |= HSMCI_CMDR_CMDNB(cmd) | HSMCI_CMDR_SPCMD_STD; + if (cmd & SDMMC_RESP_PRESENT) { + cmdr |= HSMCI_CMDR_MAXLAT; + if (cmd & SDMMC_RESP_136) { + cmdr |= HSMCI_CMDR_RSPTYP_136_BIT; + } else if (cmd & SDMMC_RESP_BUSY) { + cmdr |= HSMCI_CMDR_RSPTYP_R1B; + } else { + cmdr |= HSMCI_CMDR_RSPTYP_48_BIT; + } + } + if (cmd & SDMMC_CMD_OPENDRAIN) { + cmdr |= HSMCI_CMDR_OPDCMD_OPENDRAIN; + } + + // Write argument + HSMCI->HSMCI_ARGR = arg; + // Write and start command + HSMCI->HSMCI_CMDR = cmdr; + + // Wait end of command + do { + sr = HSMCI->HSMCI_SR; + if (cmd & SDMMC_RESP_CRC) { + if (sr & (HSMCI_SR_CSTOE | HSMCI_SR_RTOE + | HSMCI_SR_RENDE | HSMCI_SR_RCRCE + | HSMCI_SR_RDIRE | HSMCI_SR_RINDE)) { + hsmci_debug("%s: CMD 0x%08x sr 0x%08x error\n\r", + __func__, cmd, sr); + hsmci_reset(); + return false; + } + } else { + if (sr & (HSMCI_SR_CSTOE | HSMCI_SR_RTOE + | HSMCI_SR_RENDE + | HSMCI_SR_RDIRE | HSMCI_SR_RINDE)) { + hsmci_debug("%s: CMD 0x%08x sr 0x%08x error\n\r", + __func__, cmd, sr); + hsmci_reset(); + return false; + } + } + } while (!(sr & HSMCI_SR_CMDRDY)); + + if (cmd & SDMMC_RESP_BUSY) { + if (!hsmci_wait_busy()) { + return false; + } + } + return true; +} + + +//------------------------------------------------------------------- +//--------------------- PUBLIC FUNCTIONS ---------------------------- + +void hsmci_init(void) +{ + pmc_enable_periph_clk(ID_HSMCI); +#ifdef HSMCI_SR_DMADONE + // Enable clock for DMA controller + pmc_enable_periph_clk(ID_DMAC); +#endif + +#if (SAMV70 || SAMV71 || SAME70 || SAMS70) +#ifdef HSMCI_DMA_DMAEN + // Enable clock for DMA controller + pmc_enable_periph_clk(ID_XDMAC); +#endif +#endif + + // Set the Data Timeout Register to 2 Mega Cycles + HSMCI->HSMCI_DTOR = HSMCI_DTOR_DTOMUL_1048576 | HSMCI_DTOR_DTOCYC(2); + // Set Completion Signal Timeout to 2 Mega Cycles + HSMCI->HSMCI_CSTOR = HSMCI_CSTOR_CSTOMUL_1048576 | HSMCI_CSTOR_CSTOCYC(2); + // Set Configuration Register + HSMCI->HSMCI_CFG = HSMCI_CFG_FIFOMODE | HSMCI_CFG_FERRCTRL; + // Set power saving to maximum value + HSMCI->HSMCI_MR = HSMCI_MR_PWSDIV_Msk; + + // Enable the HSMCI and the Power Saving + HSMCI->HSMCI_CR = HSMCI_CR_MCIEN | HSMCI_CR_PWSEN; +} + +uint8_t hsmci_get_bus_width(uint8_t slot) +{ + switch (slot) { + case 0: + return SD_MMC_HSMCI_SLOT_0_SIZE; +#if (SD_MMC_HSMCI_MEM_CNT == 2) + case 1: + return SD_MMC_HSMCI_SLOT_1_SIZE; +#endif + default: + return 0; // Slot number wrong + } +} + +bool hsmci_is_high_speed_capable(void) +{ + return true; +} + +void hsmci_select_device(uint8_t slot, uint32_t clock, uint8_t bus_width, bool high_speed) +{ + uint32_t hsmci_slot = HSMCI_SDCR_SDCSEL_SLOTA; + uint32_t hsmci_bus_width = HSMCI_SDCR_SDCBUS_1; + + if (high_speed) { + HSMCI->HSMCI_CFG |= HSMCI_CFG_HSMODE; + } else { + HSMCI->HSMCI_CFG &= ~HSMCI_CFG_HSMODE; + } + + hsmci_set_speed(clock, sysclk_get_peripheral_hz()); + + switch (slot) { + case 0: + hsmci_slot = HSMCI_SDCR_SDCSEL_SLOTA; + break; +#if (SD_MMC_HSMCI_MEM_CNT == 2) + case 1: + hsmci_slot = HSMCI_SDCR_SDCSEL_SLOTB; + break; +#endif + default: + Assert(false); // Slot number wrong + } + + switch (bus_width) { + case 1: + hsmci_bus_width = HSMCI_SDCR_SDCBUS_1; + break; + + case 4: + hsmci_bus_width = HSMCI_SDCR_SDCBUS_4; + break; + + case 8: + hsmci_bus_width = HSMCI_SDCR_SDCBUS_8; + break; + + default: + Assert(false); // Bus width wrong + } + HSMCI->HSMCI_SDCR = hsmci_slot | hsmci_bus_width; +} + +void hsmci_deselect_device(uint8_t slot) +{ + UNUSED(slot); + // Nothing to do +} + +void hsmci_send_clock(void) +{ + // Configure command + HSMCI->HSMCI_MR &= ~(HSMCI_MR_WRPROOF | HSMCI_MR_RDPROOF | HSMCI_MR_FBYTE); + // Write argument + HSMCI->HSMCI_ARGR = 0; + // Write and start initialization command + HSMCI->HSMCI_CMDR = HSMCI_CMDR_RSPTYP_NORESP + | HSMCI_CMDR_SPCMD_INIT + | HSMCI_CMDR_OPDCMD_OPENDRAIN; + // Wait end of initialization command + while (!(HSMCI->HSMCI_SR & HSMCI_SR_CMDRDY)); +} + +bool hsmci_send_cmd(sdmmc_cmd_def_t cmd, uint32_t arg) +{ + // Configure command + HSMCI->HSMCI_MR &= ~(HSMCI_MR_WRPROOF | HSMCI_MR_RDPROOF | HSMCI_MR_FBYTE); +#ifdef HSMCI_SR_DMADONE + // Disable DMA for HSMCI + HSMCI->HSMCI_DMA = 0; +#endif +#ifdef HSMCI_MR_PDCMODE + // Disable PDC for HSMCI + HSMCI->HSMCI_MR &= ~HSMCI_MR_PDCMODE; +#endif +#if (SAMV70 || SAMV71 || SAME70 || SAMS70) +#ifdef HSMCI_DMA_DMAEN + // Disable DMA for HSMCI + HSMCI->HSMCI_DMA = 0; +#endif +#endif + HSMCI->HSMCI_BLKR = 0; + return hsmci_send_cmd_execute(0, cmd, arg); +} + +uint32_t hsmci_get_response(void) +{ + return HSMCI->HSMCI_RSPR[0]; +} + +void hsmci_get_response_128(uint8_t* response) +{ + uint32_t response_32; + + for (uint8_t i = 0; i < 4; i++) { + response_32 = HSMCI->HSMCI_RSPR[0]; + *response = (response_32 >> 24) & 0xFF; + response++; + *response = (response_32 >> 16) & 0xFF; + response++; + *response = (response_32 >> 8) & 0xFF; + response++; + *response = (response_32 >> 0) & 0xFF; + response++; + } +} + +bool hsmci_adtc_start(sdmmc_cmd_def_t cmd, uint32_t arg, uint16_t block_size, uint16_t nb_block, bool access_block) +{ + uint32_t cmdr; + +#ifdef HSMCI_SR_DMADONE + if (access_block) { + // Enable DMA for HSMCI + HSMCI->HSMCI_DMA = HSMCI_DMA_DMAEN; + } else { + // Disable DMA for HSMCI + HSMCI->HSMCI_DMA = 0; + } +#endif + +#ifdef HSMCI_MR_PDCMODE + if (access_block) { + // Enable PDC for HSMCI + HSMCI->HSMCI_MR |= HSMCI_MR_PDCMODE; + } else { + // Disable PDC for HSMCI + HSMCI->HSMCI_MR &= ~HSMCI_MR_PDCMODE; + } +#endif + +#if (SAMV70 || SAMV71 || SAME70 || SAMS70) +#ifdef HSMCI_DMA_DMAEN + if (access_block) { + // Enable DMA for HSMCI + HSMCI->HSMCI_DMA = HSMCI_DMA_DMAEN; + } else { + // Disable DMA for HSMCI + HSMCI->HSMCI_DMA = 0; + } +#endif +#endif + // Enabling Read/Write Proof allows to stop the HSMCI Clock during + // read/write access if the internal FIFO is full. + // This will guarantee data integrity, not bandwidth. + HSMCI->HSMCI_MR |= HSMCI_MR_WRPROOF | HSMCI_MR_RDPROOF; + // Force byte transfer if needed + if (block_size & 0x3) { + HSMCI->HSMCI_MR |= HSMCI_MR_FBYTE; + } else { + HSMCI->HSMCI_MR &= ~HSMCI_MR_FBYTE; + } + + if (cmd & SDMMC_CMD_WRITE) { + cmdr = HSMCI_CMDR_TRCMD_START_DATA | HSMCI_CMDR_TRDIR_WRITE; + } else { + cmdr = HSMCI_CMDR_TRCMD_START_DATA | HSMCI_CMDR_TRDIR_READ; + } + + if (cmd & SDMMC_CMD_SDIO_BYTE) { + cmdr |= HSMCI_CMDR_TRTYP_BYTE; + // Value 0 corresponds to a 512-byte transfer + HSMCI->HSMCI_BLKR = ((block_size % 512) << HSMCI_BLKR_BCNT_Pos); + } else { + HSMCI->HSMCI_BLKR = (block_size << HSMCI_BLKR_BLKLEN_Pos) | + (nb_block << HSMCI_BLKR_BCNT_Pos); + if (cmd & SDMMC_CMD_SDIO_BLOCK) { + cmdr |= HSMCI_CMDR_TRTYP_BLOCK; + } else if (cmd & SDMMC_CMD_STREAM) { + cmdr |= HSMCI_CMDR_TRTYP_STREAM; + } else if (cmd & SDMMC_CMD_SINGLE_BLOCK) { + cmdr |= HSMCI_CMDR_TRTYP_SINGLE; + } else if (cmd & SDMMC_CMD_MULTI_BLOCK) { + cmdr |= HSMCI_CMDR_TRTYP_MULTIPLE; + } else { + Assert(false); // Incorrect flags + } + } + hsmci_transfert_pos = 0; + hsmci_block_size = block_size; + hsmci_nb_block = nb_block; + + return hsmci_send_cmd_execute(cmdr, cmd, arg); +} + +bool hsmci_adtc_stop(sdmmc_cmd_def_t cmd, uint32_t arg) +{ + return hsmci_send_cmd_execute(HSMCI_CMDR_TRCMD_STOP_DATA, cmd, arg); +} + +bool hsmci_read_word(uint32_t* value) +{ + uint32_t sr; + + Assert(((uint32_t)hsmci_block_size * hsmci_nb_block) > hsmci_transfert_pos); + + // Wait data available + do { + sr = HSMCI->HSMCI_SR; + if (sr & (HSMCI_SR_UNRE | HSMCI_SR_OVRE | \ + HSMCI_SR_DTOE | HSMCI_SR_DCRCE)) { + hsmci_debug("%s: DMA sr 0x%08x error\n\r", + __func__, sr); + hsmci_reset(); + return false; + } + } while (!(sr & HSMCI_SR_RXRDY)); + + // Read data + *value = HSMCI->HSMCI_RDR; + hsmci_transfert_pos += 4; + if (((uint32_t)hsmci_block_size * hsmci_nb_block) > hsmci_transfert_pos) { + return true; + } + + // Wait end of transfer + // Note: no need of timeout, because it is include in HSMCI + do { + sr = HSMCI->HSMCI_SR; + if (sr & (HSMCI_SR_UNRE | HSMCI_SR_OVRE | \ + HSMCI_SR_DTOE | HSMCI_SR_DCRCE)) { + hsmci_debug("%s: DMA sr 0x%08x error\n\r", + __func__, sr); + hsmci_reset(); + return false; + } + } while (!(sr & HSMCI_SR_XFRDONE)); + return true; +} + +bool hsmci_write_word(uint32_t value) +{ + uint32_t sr; + + Assert(((uint32_t)hsmci_block_size * hsmci_nb_block) > hsmci_transfert_pos); + + // Wait data available + do { + sr = HSMCI->HSMCI_SR; + if (sr & (HSMCI_SR_UNRE | HSMCI_SR_OVRE | \ + HSMCI_SR_DTOE | HSMCI_SR_DCRCE)) { + hsmci_debug("%s: DMA sr 0x%08x error\n\r", + __func__, sr); + hsmci_reset(); + return false; + } + } while (!(sr & HSMCI_SR_TXRDY)); + + // Write data + HSMCI->HSMCI_TDR = value; + hsmci_transfert_pos += 4; + if (((uint32_t)hsmci_block_size * hsmci_nb_block) > hsmci_transfert_pos) { + return true; + } + + // Wait end of transfer + // Note: no need of timeout, because it is include in HSMCI, see DTOE bit. + do { + sr = HSMCI->HSMCI_SR; + if (sr & (HSMCI_SR_UNRE | HSMCI_SR_OVRE | \ + HSMCI_SR_DTOE | HSMCI_SR_DCRCE)) { + hsmci_debug("%s: DMA sr 0x%08x error\n\r", + __func__, sr); + hsmci_reset(); + return false; + } + } while (!(sr & HSMCI_SR_NOTBUSY)); + Assert(HSMCI->HSMCI_SR & HSMCI_SR_FIFOEMPTY); + return true; +} + +#ifdef HSMCI_SR_DMADONE +bool hsmci_start_read_blocks(void *dest, uint16_t nb_block) +{ + uint32_t cfg, nb_data; + dma_transfer_descriptor_t desc; + bool transfert_byte; + + nb_data = nb_block * hsmci_block_size; + transfert_byte = ((HSMCI->HSMCI_MR & HSMCI_MR_FBYTE) || (((uint32_t)dest & 0x3) > 0)) ? 1 : 0; + + Assert(nb_data <= (((uint32_t)hsmci_block_size * hsmci_nb_block) - hsmci_transfert_pos)); + Assert(nb_data <= (transfert_byte ? + DMAC_CTRLA_BTSIZE_Msk >> DMAC_CTRLA_BTSIZE_Pos : + ((DMAC_CTRLA_BTSIZE_Msk >> DMAC_CTRLA_BTSIZE_Pos) * 4))); + + /* Set channel configuration register + * - Enable stop on done + * - Hardware Selection for the Source + * - Source with Peripheral identifier + * - Set AHB Protection + * - FIFO Configuration + */ + dmac_enable(DMAC); + dmac_channel_disable(DMAC, CONF_HSMCI_DMA_CHANNEL); + cfg = DMAC_CFG_SOD_ENABLE | DMAC_CFG_SRC_H2SEL | + DMAC_CFG_SRC_PER(DMA_HW_ID_HSMCI) | + DMAC_CFG_AHB_PROT(1) | DMAC_CFG_FIFOCFG_ALAP_CFG; + dmac_channel_set_configuration(DMAC, CONF_HSMCI_DMA_CHANNEL, cfg); + + // Prepare DMA transfer + desc.ul_source_addr = (uint32_t)&(HSMCI->HSMCI_RDR); + desc.ul_destination_addr = (uint32_t)dest; + if (transfert_byte) { + desc.ul_ctrlA = DMAC_CTRLA_BTSIZE(nb_data) + | DMAC_CTRLA_SRC_WIDTH_BYTE + | DMAC_CTRLA_DST_WIDTH_BYTE; + } else { + desc.ul_ctrlA = DMAC_CTRLA_BTSIZE(nb_data / 4) + | DMAC_CTRLA_SRC_WIDTH_WORD + | DMAC_CTRLA_DST_WIDTH_WORD; + } + desc.ul_ctrlB = DMAC_CTRLB_SRC_DSCR_FETCH_DISABLE + | DMAC_CTRLB_DST_DSCR_FETCH_DISABLE + | DMAC_CTRLB_FC_PER2MEM_DMA_FC + | DMAC_CTRLB_SRC_INCR_FIXED + | DMAC_CTRLB_DST_INCR_INCREMENTING + | DMAC_CTRLB_IEN; + desc.ul_descriptor_addr = (uint32_t)NULL; + dmac_channel_single_buf_transfer_init(DMAC, CONF_HSMCI_DMA_CHANNEL, + &desc); + + // Start DMA transfer + dmac_channel_enable(DMAC, CONF_HSMCI_DMA_CHANNEL); + hsmci_transfert_pos += nb_data; + return true; +} + +bool hsmci_wait_end_of_read_blocks(void) +{ + uint32_t sr; + // Wait end of transfer + // Note: no need of timeout, because it is include in HSMCI + do { + sr = HSMCI->HSMCI_SR; + if (sr & (HSMCI_SR_UNRE | HSMCI_SR_OVRE | \ + HSMCI_SR_DTOE | HSMCI_SR_DCRCE)) { + hsmci_debug("%s: DMA sr 0x%08x error\n\r", + __func__, sr); + hsmci_reset(); + // Disable DMA + dmac_channel_disable(DMAC, CONF_HSMCI_DMA_CHANNEL); + return false; + } + if (((uint32_t)hsmci_block_size * hsmci_nb_block) > hsmci_transfert_pos) { + // It is not the end of all transfers + // then just wait end of DMA + if (sr & HSMCI_SR_DMADONE) { + return true; + } + } + } while (!(sr & HSMCI_SR_XFRDONE)); + return true; +} + +bool hsmci_start_write_blocks(const void *src, uint16_t nb_block) +{ + bool transfert_byte; + uint32_t cfg, nb_data; + dma_transfer_descriptor_t desc; + + nb_data = nb_block * hsmci_block_size; + transfert_byte = ((HSMCI->HSMCI_MR & HSMCI_MR_FBYTE) || (((uint32_t)src & 0x3) > 0)) ? 1 : 0; + + Assert(nb_data <= (((uint32_t)hsmci_block_size * hsmci_nb_block) - hsmci_transfert_pos)); + Assert(nb_data <= (transfert_byte ? + DMAC_CTRLA_BTSIZE_Msk >> DMAC_CTRLA_BTSIZE_Pos : + ((DMAC_CTRLA_BTSIZE_Msk >> DMAC_CTRLA_BTSIZE_Pos) * 4))); + + /* Set channel configuration register: + * - Enable stop on done + * - Hardware Selection for the Destination + * - Destination with Peripheral identifier + * - Set AHB Protection + * - FIFO Configuration + */ + dmac_enable(DMAC); + Assert(!dmac_channel_is_enable(DMAC, CONF_HSMCI_DMA_CHANNEL)); + cfg = DMAC_CFG_SOD_ENABLE | DMAC_CFG_DST_H2SEL | + DMAC_CFG_DST_PER(DMA_HW_ID_HSMCI) | + DMAC_CFG_AHB_PROT(1) | DMAC_CFG_FIFOCFG_ALAP_CFG; + dmac_channel_set_configuration(DMAC, CONF_HSMCI_DMA_CHANNEL, cfg); + + // Prepare DMA transfer + desc.ul_source_addr = (uint32_t)src; + desc.ul_destination_addr = (uint32_t)&(HSMCI->HSMCI_TDR); + if (transfert_byte) { + desc.ul_ctrlA = DMAC_CTRLA_BTSIZE(nb_data) + | DMAC_CTRLA_SRC_WIDTH_BYTE + | DMAC_CTRLA_DST_WIDTH_BYTE; + } else { + desc.ul_ctrlA = DMAC_CTRLA_BTSIZE(nb_data / 4) + | DMAC_CTRLA_SRC_WIDTH_WORD + | DMAC_CTRLA_DST_WIDTH_WORD; + } + desc.ul_ctrlB = DMAC_CTRLB_SRC_DSCR_FETCH_DISABLE + | DMAC_CTRLB_DST_DSCR_FETCH_DISABLE + | DMAC_CTRLB_FC_MEM2PER_DMA_FC + | DMAC_CTRLB_SRC_INCR_INCREMENTING + | DMAC_CTRLB_DST_INCR_FIXED + | DMAC_CTRLB_IEN; + desc.ul_descriptor_addr = (uint32_t)NULL; + dmac_channel_single_buf_transfer_init(DMAC, CONF_HSMCI_DMA_CHANNEL, + &desc); + + // Start DMA transfer + dmac_channel_enable(DMAC, CONF_HSMCI_DMA_CHANNEL); + hsmci_transfert_pos += nb_data; + return true; +} + +bool hsmci_wait_end_of_write_blocks(void) +{ + uint32_t sr; + // Wait end of transfer + // Note: no need of timeout, because it is include in HSMCI, see DTOE bit. + do { + sr = HSMCI->HSMCI_SR; + if (sr & (HSMCI_SR_UNRE | HSMCI_SR_OVRE | \ + HSMCI_SR_DTOE | HSMCI_SR_DCRCE)) { + hsmci_debug("%s: DMA sr 0x%08x error\n\r", + __func__, sr); + hsmci_reset(); + // Disable DMA + dmac_channel_disable(DMAC, CONF_HSMCI_DMA_CHANNEL); + return false; + } + if (((uint32_t)hsmci_block_size * hsmci_nb_block) > hsmci_transfert_pos) { + // It is not the end of all transfers + // then just wait end of DMA + if (sr & HSMCI_SR_DMADONE) { + return true; + } + } + } while (!(sr & HSMCI_SR_NOTBUSY)); + Assert(HSMCI->HSMCI_SR & HSMCI_SR_FIFOEMPTY); + Assert(!dmac_channel_is_enable(DMAC, CONF_HSMCI_DMA_CHANNEL)); + return true; + +} +#endif // HSMCI_SR_DMADONE + +#ifdef HSMCI_MR_PDCMODE +bool hsmci_start_read_blocks(void *dest, uint16_t nb_block) +{ + uint32_t nb_data; + + nb_data = nb_block * hsmci_block_size; + Assert(nb_data <= (((uint32_t)hsmci_block_size * hsmci_nb_block) - hsmci_transfert_pos)); + Assert(nb_data <= (PERIPH_RCR_RXCTR_Msk >> PERIPH_RCR_RXCTR_Pos)); + + // Handle unaligned memory address + if (((uint32_t)dest & 0x3) || (hsmci_block_size & 0x3)) { + HSMCI->HSMCI_MR |= HSMCI_MR_FBYTE; + } else { + HSMCI->HSMCI_MR &= ~HSMCI_MR_FBYTE; + } + + // Configure PDC transfer + HSMCI->HSMCI_RPR = (uint32_t)dest; + HSMCI->HSMCI_RCR = (HSMCI->HSMCI_MR & HSMCI_MR_FBYTE) ? + nb_data : nb_data / 4; + HSMCI->HSMCI_RNCR = 0; + // Start transfer + HSMCI->HSMCI_PTCR = HSMCI_PTCR_RXTEN; + hsmci_transfert_pos += nb_data; + return true; +} + +bool hsmci_wait_end_of_read_blocks(void) +{ + uint32_t sr; + // Wait end of transfer + // Note: no need of timeout, because it is include in HSMCI, see DTOE bit. + do { + sr = HSMCI->HSMCI_SR; + if (sr & (HSMCI_SR_UNRE | HSMCI_SR_OVRE | \ + HSMCI_SR_DTOE | HSMCI_SR_DCRCE)) { + hsmci_debug("%s: PDC sr 0x%08x error\n\r", + __func__, sr); + HSMCI->HSMCI_PTCR = HSMCI_PTCR_RXTDIS | HSMCI_PTCR_TXTDIS; + hsmci_reset(); + return false; + } + + } while (!(sr & HSMCI_SR_RXBUFF)); + + if (hsmci_transfert_pos < ((uint32_t)hsmci_block_size * hsmci_nb_block)) { + return true; + } + // It is the last transfer, then wait command completed + // Note: no need of timeout, because it is include in HSMCI, see DTOE bit. + do { + sr = HSMCI->HSMCI_SR; + if (sr & (HSMCI_SR_UNRE | HSMCI_SR_OVRE | \ + HSMCI_SR_DTOE | HSMCI_SR_DCRCE)) { + hsmci_debug("%s: PDC sr 0x%08x last transfer error\n\r", + __func__, sr); + hsmci_reset(); + return false; + } + } while (!(sr & HSMCI_SR_XFRDONE)); + return true; +} + +bool hsmci_start_write_blocks(const void *src, uint16_t nb_block) +{ + uint32_t nb_data; + + nb_data = nb_block * hsmci_block_size; + Assert(nb_data <= (((uint32_t)hsmci_block_size * hsmci_nb_block) - hsmci_transfert_pos)); + Assert(nb_data <= (PERIPH_TCR_TXCTR_Msk >> PERIPH_TCR_TXCTR_Pos)); + + // Handle unaligned memory address + if (((uint32_t)src & 0x3) || (hsmci_block_size & 0x3)) { + HSMCI->HSMCI_MR |= HSMCI_MR_FBYTE; + } else { + HSMCI->HSMCI_MR &= ~HSMCI_MR_FBYTE; + } + + // Configure PDC transfer + HSMCI->HSMCI_TPR = (uint32_t)src; + HSMCI->HSMCI_TCR = (HSMCI->HSMCI_MR & HSMCI_MR_FBYTE) ? + nb_data : nb_data / 4; + HSMCI->HSMCI_TNCR = 0; + // Start transfer + HSMCI->HSMCI_PTCR = HSMCI_PTCR_TXTEN; + hsmci_transfert_pos += nb_data; + return true; +} + +bool hsmci_wait_end_of_write_blocks(void) +{ + uint32_t sr; + + // Wait end of transfer + // Note: no need of timeout, because it is include in HSMCI, see DTOE bit. + do { + sr = HSMCI->HSMCI_SR; + if (sr & + (HSMCI_SR_UNRE | HSMCI_SR_OVRE | \ + HSMCI_SR_DTOE | HSMCI_SR_DCRCE)) { + hsmci_debug("%s: PDC sr 0x%08x error\n\r", + __func__, sr); + hsmci_reset(); + HSMCI->HSMCI_PTCR = HSMCI_PTCR_RXTDIS | HSMCI_PTCR_TXTDIS; + return false; + } + } while (!(sr & HSMCI_SR_TXBUFE)); + + + if (hsmci_transfert_pos < ((uint32_t)hsmci_block_size * hsmci_nb_block)) { + return true; + } + // It is the last transfer, then wait command completed + // Note: no need of timeout, because it is include in HSMCI, see DTOE bit. + do { + sr = HSMCI->HSMCI_SR; + if (sr & (HSMCI_SR_UNRE | HSMCI_SR_OVRE | \ + HSMCI_SR_DTOE | HSMCI_SR_DCRCE)) { + hsmci_debug("%s: PDC sr 0x%08x last transfer error\n\r", + __func__, sr); + hsmci_reset(); + return false; + } + } while (!(sr & HSMCI_SR_NOTBUSY)); + Assert(HSMCI->HSMCI_SR & HSMCI_SR_FIFOEMPTY); + return true; +} +#endif // HSMCI_MR_PDCMODE + +#if (SAMV70 || SAMV71 || SAME70 || SAMS70) +#ifdef HSMCI_DMA_DMAEN +bool hsmci_start_read_blocks(void *dest, uint16_t nb_block) +{ + xdmac_channel_config_t p_cfg = {0, 0, 0, 0, 0, 0, 0, 0}; + uint32_t nb_data; + + Assert(nb_block); + Assert(dest); + + xdmac_channel_disable(XDMAC, CONF_HSMCI_XDMAC_CHANNEL); + + nb_data = nb_block * hsmci_block_size; + + if((uint32_t)dest & 3) { + p_cfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN + | XDMAC_CC_MBSIZE_SINGLE + | XDMAC_CC_DSYNC_PER2MEM + | XDMAC_CC_CSIZE_CHK_1 + | XDMAC_CC_DWIDTH_BYTE + | XDMAC_CC_SIF_AHB_IF1 + | XDMAC_CC_DIF_AHB_IF0 + | XDMAC_CC_SAM_FIXED_AM + | XDMAC_CC_DAM_INCREMENTED_AM + | XDMAC_CC_PERID(CONF_HSMCI_XDMAC_CHANNEL); + p_cfg.mbr_ubc = nb_data; + HSMCI->HSMCI_MR |= HSMCI_MR_FBYTE; + } else { + p_cfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN + | XDMAC_CC_MBSIZE_SINGLE + | XDMAC_CC_DSYNC_PER2MEM + | XDMAC_CC_CSIZE_CHK_1 + | XDMAC_CC_DWIDTH_WORD + | XDMAC_CC_SIF_AHB_IF1 + | XDMAC_CC_DIF_AHB_IF0 + | XDMAC_CC_SAM_FIXED_AM + | XDMAC_CC_DAM_INCREMENTED_AM + | XDMAC_CC_PERID(CONF_HSMCI_XDMAC_CHANNEL); + p_cfg.mbr_ubc = nb_data / 4; + HSMCI->HSMCI_MR &= ~HSMCI_MR_FBYTE; + } + p_cfg.mbr_sa = (uint32_t)&(HSMCI->HSMCI_FIFO[0]); + p_cfg.mbr_da = (uint32_t)dest; + xdmac_configure_transfer(XDMAC, CONF_HSMCI_XDMAC_CHANNEL, &p_cfg); + xdmac_channel_enable(XDMAC, CONF_HSMCI_XDMAC_CHANNEL); + hsmci_transfert_pos += nb_data; + return true; +} + +bool hsmci_wait_end_of_read_blocks(void) +{ + uint32_t sr; + uint32_t dma_sr; + // Wait end of transfer + // Note: no need of timeout, because it is include in HSMCI + do { + sr = HSMCI->HSMCI_SR; + if (sr & (HSMCI_SR_UNRE | HSMCI_SR_OVRE | \ + HSMCI_SR_DTOE | HSMCI_SR_DCRCE)) { + hsmci_debug("%s: DMA sr 0x%08x error\n\r", + __func__, sr); + hsmci_reset(); + // Disable XDMAC + xdmac_channel_disable(XDMAC, CONF_HSMCI_XDMAC_CHANNEL); + return false; + } + if (((uint32_t)hsmci_block_size * hsmci_nb_block) > hsmci_transfert_pos) { + // It is not the end of all transfers + // then just wait end of DMA + dma_sr = xdmac_channel_get_interrupt_status(XDMAC, CONF_HSMCI_XDMAC_CHANNEL); + if (dma_sr & XDMAC_CIS_BIS) { + return true; + } + } + } while (!(sr & HSMCI_SR_XFRDONE)); + return true; +} + +bool hsmci_start_write_blocks(const void *src, uint16_t nb_block) +{ + xdmac_channel_config_t p_cfg = {0, 0, 0, 0, 0, 0, 0, 0}; + uint32_t nb_data; + + Assert(nb_block); + Assert(dest); + + xdmac_channel_disable(XDMAC, CONF_HSMCI_XDMAC_CHANNEL); + + nb_data = nb_block * hsmci_block_size; + + if((uint32_t)src & 3) { + p_cfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN + | XDMAC_CC_MBSIZE_SINGLE + | XDMAC_CC_DSYNC_MEM2PER + | XDMAC_CC_CSIZE_CHK_1 + | XDMAC_CC_DWIDTH_BYTE + | XDMAC_CC_SIF_AHB_IF0 + | XDMAC_CC_DIF_AHB_IF1 + | XDMAC_CC_SAM_INCREMENTED_AM + | XDMAC_CC_DAM_FIXED_AM + | XDMAC_CC_PERID(CONF_HSMCI_XDMAC_CHANNEL); + p_cfg.mbr_ubc = nb_data; + HSMCI->HSMCI_MR |= HSMCI_MR_FBYTE; + } else { + p_cfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN + | XDMAC_CC_MBSIZE_SINGLE + | XDMAC_CC_DSYNC_MEM2PER + | XDMAC_CC_CSIZE_CHK_1 + | XDMAC_CC_DWIDTH_WORD + | XDMAC_CC_SIF_AHB_IF0 + | XDMAC_CC_DIF_AHB_IF1 + | XDMAC_CC_SAM_INCREMENTED_AM + | XDMAC_CC_DAM_FIXED_AM + | XDMAC_CC_PERID(CONF_HSMCI_XDMAC_CHANNEL); + p_cfg.mbr_ubc = nb_data / 4; + HSMCI->HSMCI_MR &= ~HSMCI_MR_FBYTE; + } + p_cfg.mbr_sa = (uint32_t)src; + p_cfg.mbr_da = (uint32_t)&(HSMCI->HSMCI_FIFO[0]); + xdmac_configure_transfer(XDMAC, CONF_HSMCI_XDMAC_CHANNEL, &p_cfg); + xdmac_channel_enable(XDMAC, CONF_HSMCI_XDMAC_CHANNEL); + hsmci_transfert_pos += nb_data; + return true; +} + +bool hsmci_wait_end_of_write_blocks(void) +{ + uint32_t sr; + uint32_t dma_sr; + // Wait end of transfer + // Note: no need of timeout, because it is include in HSMCI + do { + sr = HSMCI->HSMCI_SR; + if (sr & (HSMCI_SR_UNRE | HSMCI_SR_OVRE | \ + HSMCI_SR_DTOE | HSMCI_SR_DCRCE)) { + hsmci_debug("%s: DMA sr 0x%08x error\n\r", + __func__, sr); + hsmci_reset(); + // Disable XDMAC + xdmac_channel_disable(XDMAC, CONF_HSMCI_XDMAC_CHANNEL); + return false; + } + if (((uint32_t)hsmci_block_size * hsmci_nb_block) > hsmci_transfert_pos) { + // It is not the end of all transfers + // then just wait end of DMA + dma_sr = xdmac_channel_get_interrupt_status(XDMAC, CONF_HSMCI_XDMAC_CHANNEL); + if (dma_sr & XDMAC_CIS_BIS) { + return true; + } + } + } while (!(sr & HSMCI_SR_XFRDONE)); + + return true; +} +#endif // HSMCI_DMA_DMAEN +#endif \ No newline at end of file diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/hsmci/hsmci.h b/hw-libs/drivers/SAMx70/ASF/sam/drivers/hsmci/hsmci.h new file mode 100644 index 000000000..8b6435883 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/hsmci/hsmci.h @@ -0,0 +1,201 @@ +/** + * \file + * + * \brief SAM HSMCI driver + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef HSMCI_H_INCLUDED +#define HSMCI_H_INCLUDED + +#include "compiler.h" +#include "sd_mmc_protocol.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \defgroup sam_drivers_hsmci High Speed MultiMedia Card Interface (HSMCI) + * + * This driver interfaces the HSMCI module. + * It will add functions for SD/MMC card reading, writing and management. + * + * @{ + */ + +/** \brief Initializes the low level driver + * + * This enable the clock required and the hardware interface. + */ +void hsmci_init(void); + +/** \brief Return the maximum bus width of a slot + * + * \param slot Selected slot + * + * \return 1, 4 or 8 lines. + */ +uint8_t hsmci_get_bus_width(uint8_t slot); + +/** \brief Return the high speed capability of the driver + * + * \return true, if the high speed is supported + */ +bool hsmci_is_high_speed_capable(void); + +/** + * \brief Select a slot and initialize it + * + * \param slot Selected slot + * \param clock Maximum clock to use (Hz) + * \param bus_width Bus width to use (1, 4 or 8) + * \param high_speed true, to enable high speed mode + */ +void hsmci_select_device(uint8_t slot, uint32_t clock, uint8_t bus_width, + bool high_speed); + +/** + * \brief Deselect a slot + * + * \param slot Selected slot + */ +void hsmci_deselect_device(uint8_t slot); + +/** \brief Send 74 clock cycles on the line of selected slot + * Note: It is required after card plug and before card install. + */ +void hsmci_send_clock(void); + +/** \brief Send a command on the selected slot + * + * \param cmd Command definition + * \param arg Argument of the command + * + * \return true if success, otherwise false + */ +bool hsmci_send_cmd(sdmmc_cmd_def_t cmd, uint32_t arg); + +/** \brief Return the 32 bits response of the last command + * + * \return 32 bits response + */ +uint32_t hsmci_get_response(void); + +/** \brief Return the 128 bits response of the last command + * + * \param response Pointer on the array to fill with the 128 bits response + */ +void hsmci_get_response_128(uint8_t* response); + +/** \brief Send an ADTC command on the selected slot + * An ADTC (Addressed Data Transfer Commands) command is used + * for read/write access. + * + * \param cmd Command definition + * \param arg Argument of the command + * \param block_size Block size used for the transfer + * \param nb_block Total number of block for this transfer + * \param access_block if true, the x_read_blocks() and x_write_blocks() + * functions must be used after this function. + * If false, the mci_read_word() and mci_write_word() + * functions must be used after this function. + * + * \return true if success, otherwise false + */ +bool hsmci_adtc_start(sdmmc_cmd_def_t cmd, uint32_t arg, uint16_t block_size, + uint16_t nb_block, bool access_block); + +/** \brief Send a command to stop an ADTC command on the selected slot + * + * \param cmd Command definition + * \param arg Argument of the command + * + * \return true if success, otherwise false + */ +bool hsmci_adtc_stop(sdmmc_cmd_def_t cmd, uint32_t arg); + +/** \brief Read a word on the line + * + * \param value Pointer on a word to fill + * + * \return true if success, otherwise false + */ +bool hsmci_read_word(uint32_t* value); + +/** \brief Write a word on the line + * + * \param value Word to send + * + * \return true if success, otherwise false + */ +bool hsmci_write_word(uint32_t value); + +/** \brief Start a read blocks transfer on the line + * Note: The driver will use the DMA available to speed up the transfer. + * + * \param dest Pointer on the buffer to fill + * \param nb_block Number of block to transfer + * + * \return true if started, otherwise false + */ +bool hsmci_start_read_blocks(void *dest, uint16_t nb_block); + +/** \brief Wait the end of transfer initiated by mci_start_read_blocks() + * + * \return true if success, otherwise false + */ +bool hsmci_wait_end_of_read_blocks(void); + +/** \brief Start a write blocks transfer on the line + * Note: The driver will use the DMA available to speed up the transfer. + * + * \param src Pointer on the buffer to send + * \param nb_block Number of block to transfer + * + * \return true if started, otherwise false + */ +bool hsmci_start_write_blocks(const void *src, uint16_t nb_block); + +/** \brief Wait the end of transfer initiated by mci_start_write_blocks() + * + * \return true if success, otherwise false + */ +bool hsmci_wait_end_of_write_blocks(void); + +//! @} + +#ifdef __cplusplus +} +#endif + +#endif /* HSMCI_H_INCLUDED */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/mcan/mcan.c b/hw-libs/drivers/SAMx70/ASF/sam/drivers/mcan/mcan.c new file mode 100644 index 000000000..d76438aea --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/mcan/mcan.c @@ -0,0 +1,742 @@ +/** + * \file + * + * \brief SAM Control Area Network (MCAN) Low Level Driver + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "mcan.h" +#include "pmc.h" +#include +#include + +/** @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/** @endcond */ + +/* PCK5 ID,assigned to MCAN module */ +#define PMC_PCK_5 5 +/* Get a value of 2 to 15 bit. */ +#define BIT_2_TO_15_MASK 0x0000fffc + +/** + Message ram definition. + + NOTE: Align to beginning of .bss section (custom linker script should look like this): + + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(MCAN MCAN.*) + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + This makes sure the MCAN variables get put first so they don't extend too far in RAM (0x2040ffff is the boundary, see later in this file) + */ + +COMPILER_ALIGNED(4) +__attribute__((__section__("MCAN"))) static struct mcan_rx_element_buffer mcan0_rx_buffer[CONF_MCAN0_RX_BUFFER_NUM]; +COMPILER_ALIGNED(4) +__attribute__((__section__("MCAN"))) static struct mcan_rx_element_fifo_0 mcan0_rx_fifo_0[CONF_MCAN0_RX_FIFO_0_NUM]; +COMPILER_ALIGNED(4) +__attribute__((__section__("MCAN"))) static struct mcan_rx_element_fifo_1 mcan0_rx_fifo_1[CONF_MCAN0_RX_FIFO_1_NUM]; +COMPILER_ALIGNED(4) +__attribute__((__section__("MCAN"))) static struct mcan_tx_element mcan0_tx_buffer[CONF_MCAN0_TX_BUFFER_NUM + CONF_MCAN0_TX_FIFO_QUEUE_NUM]; +COMPILER_ALIGNED(4) +__attribute__((__section__("MCAN"))) static struct mcan_tx_event_element mcan0_tx_event_fifo[CONF_MCAN0_TX_EVENT_FIFO]; +COMPILER_ALIGNED(4) +__attribute__((__section__("MCAN"))) static struct mcan_standard_message_filter_element mcan0_rx_standard_filter[CONF_MCAN0_RX_STANDARD_ID_FILTER_NUM]; +COMPILER_ALIGNED(4) +__attribute__((__section__("MCAN"))) static struct mcan_extended_message_filter_element mcan0_rx_extended_filter[CONF_MCAN0_RX_EXTENDED_ID_FILTER_NUM]; + +COMPILER_ALIGNED(4) +__attribute__((__section__("MCAN"))) static struct mcan_rx_element_buffer mcan1_rx_buffer[CONF_MCAN1_RX_BUFFER_NUM] ; +COMPILER_ALIGNED(4) +__attribute__((__section__("MCAN"))) static struct mcan_rx_element_fifo_0 mcan1_rx_fifo_0[CONF_MCAN1_RX_FIFO_0_NUM]; +COMPILER_ALIGNED(4) +__attribute__((__section__("MCAN"))) static struct mcan_rx_element_fifo_1 mcan1_rx_fifo_1[CONF_MCAN1_RX_FIFO_1_NUM]; +COMPILER_ALIGNED(4) +__attribute__((__section__("MCAN"))) static struct mcan_tx_element mcan1_tx_buffer[CONF_MCAN1_TX_BUFFER_NUM + CONF_MCAN1_TX_FIFO_QUEUE_NUM]; +COMPILER_ALIGNED(4) +__attribute__((__section__("MCAN"))) static struct mcan_tx_event_element mcan1_tx_event_fifo[CONF_MCAN1_TX_EVENT_FIFO]; +COMPILER_ALIGNED(4) +__attribute__((__section__("MCAN"))) static struct mcan_standard_message_filter_element mcan1_rx_standard_filter[CONF_MCAN1_RX_STANDARD_ID_FILTER_NUM]; +COMPILER_ALIGNED(4) +__attribute__((__section__("MCAN"))) static struct mcan_extended_message_filter_element mcan1_rx_extended_filter[CONF_MCAN1_RX_EXTENDED_ID_FILTER_NUM]; + +/** + * \brief initialize MCAN memory . + * + * \param hw Base address of the MCAN + * + */ +static void _mcan_message_memory_init(Mcan *hw) +{ + if (hw == MCAN0) { + hw->MCAN_SIDFC = ((uint32_t)mcan0_rx_standard_filter & BIT_2_TO_15_MASK) | + MCAN_SIDFC_LSS(CONF_MCAN0_RX_STANDARD_ID_FILTER_NUM); + hw->MCAN_XIDFC = ((uint32_t)mcan0_rx_extended_filter & BIT_2_TO_15_MASK) | + MCAN_XIDFC_LSE(CONF_MCAN0_RX_EXTENDED_ID_FILTER_NUM); + hw->MCAN_RXF0C = ((uint32_t)mcan0_rx_fifo_0 & BIT_2_TO_15_MASK) | + MCAN_RXF0C_F0S(CONF_MCAN0_RX_FIFO_0_NUM); + hw->MCAN_RXF1C = ((uint32_t)mcan0_rx_fifo_1 & BIT_2_TO_15_MASK) | + MCAN_RXF1C_F1S(CONF_MCAN0_RX_FIFO_1_NUM); + hw->MCAN_RXBC = ((uint32_t)mcan0_rx_buffer & BIT_2_TO_15_MASK); + hw->MCAN_TXBC = ((uint32_t)mcan0_tx_buffer & BIT_2_TO_15_MASK) | + MCAN_TXBC_NDTB(CONF_MCAN0_TX_BUFFER_NUM) | + MCAN_TXBC_TFQS(CONF_MCAN0_TX_FIFO_QUEUE_NUM); + hw->MCAN_TXEFC = ((uint32_t)mcan0_tx_event_fifo & BIT_2_TO_15_MASK) | + MCAN_TXEFC_EFS(CONF_MCAN0_TX_EVENT_FIFO); + } else if (hw == MCAN1) { + if((uint32_t)&mcan1_rx_standard_filter > 0x2040ffff || + (uint32_t)&mcan1_rx_extended_filter > 0x2040ffff || + (uint32_t)&mcan1_rx_fifo_0 > 0x2040ffff || + (uint32_t)&mcan1_rx_fifo_1 > 0x2040ffff || + (uint32_t)&mcan1_rx_buffer > 0x2040ffff || + (uint32_t)&mcan1_tx_buffer > 0x2040ffff || + (uint32_t)mcan1_tx_event_fifo > 0x2040ffff) + { + //Error, memory needs to be at beginning of RAM to function with CAN module + while(1); + } + + hw->MCAN_SIDFC = ((uint32_t)mcan1_rx_standard_filter & BIT_2_TO_15_MASK) | + MCAN_SIDFC_LSS(CONF_MCAN1_RX_STANDARD_ID_FILTER_NUM); + hw->MCAN_XIDFC = ((uint32_t)mcan1_rx_extended_filter & BIT_2_TO_15_MASK) | + MCAN_XIDFC_LSE(CONF_MCAN1_RX_EXTENDED_ID_FILTER_NUM); + hw->MCAN_RXF0C = ((uint32_t)mcan1_rx_fifo_0 & BIT_2_TO_15_MASK) | + MCAN_RXF0C_F0S(CONF_MCAN1_RX_FIFO_0_NUM); + hw->MCAN_RXF1C = ((uint32_t)mcan1_rx_fifo_1 & BIT_2_TO_15_MASK) | + MCAN_RXF1C_F1S(CONF_MCAN1_RX_FIFO_1_NUM); + hw->MCAN_RXBC = ((uint32_t)mcan1_rx_buffer & BIT_2_TO_15_MASK); + hw->MCAN_TXBC = ((uint32_t)mcan1_tx_buffer & BIT_2_TO_15_MASK) | + MCAN_TXBC_NDTB(CONF_MCAN1_TX_BUFFER_NUM) | + MCAN_TXBC_TFQS(CONF_MCAN1_TX_FIFO_QUEUE_NUM); + hw->MCAN_TXEFC = ((uint32_t)mcan1_tx_event_fifo & BIT_2_TO_15_MASK) | + MCAN_TXEFC_EFS(CONF_MCAN1_TX_EVENT_FIFO); + } + + /** + * The data size in conf_mcan.h should be 8/12/16/20/24/32/48/64, + * The corresponding setting value in register is 0/1//2/3/4/5/6/7. + * To simplify the calculation, seperate to two group 8/12/16/20/24 which + * increased with 4 and 32/48/64 which increased with 16. + */ + if (CONF_MCAN_ELEMENT_DATA_SIZE <= 24) { + hw->MCAN_RXESC = MCAN_RXESC_RBDS((CONF_MCAN_ELEMENT_DATA_SIZE - 8) / 4) | + MCAN_RXESC_F0DS((CONF_MCAN_ELEMENT_DATA_SIZE - 8) / 4) | + MCAN_RXESC_F1DS((CONF_MCAN_ELEMENT_DATA_SIZE - 8) / 4); + hw->MCAN_TXESC = MCAN_TXESC_TBDS((CONF_MCAN_ELEMENT_DATA_SIZE - 8) / 4); + } else { + hw->MCAN_RXESC = MCAN_RXESC_RBDS((CONF_MCAN_ELEMENT_DATA_SIZE - 32) / 16 + 5) | + MCAN_RXESC_F0DS((CONF_MCAN_ELEMENT_DATA_SIZE - 32) / 16 + 5) | + MCAN_RXESC_F1DS((CONF_MCAN_ELEMENT_DATA_SIZE - 32) / 16 + 5); + hw->MCAN_TXESC = MCAN_TXESC_TBDS((CONF_MCAN_ELEMENT_DATA_SIZE - 32) / 16 + 5); + } +} + +/** + * \brief set default configuration when initialization. + * + * \param hw Base address of the MCAN + * \param config default configuration parameters. + */ +static void _mcan_set_configuration(Mcan *hw, struct mcan_config *config) +{ +#if (SAMV71B || SAME70B || SAMV70B) + /* Timing setting for Rev B */ + hw->MCAN_NBTP = MCAN_NBTP_NBRP(CONF_MCAN_NBTP_NBRP_VALUE) | + MCAN_NBTP_NSJW(CONF_MCAN_NBTP_NSJW_VALUE) | + MCAN_NBTP_NTSEG1(CONF_MCAN_NBTP_NTSEG1_VALUE) | + MCAN_NBTP_NTSEG2(CONF_MCAN_NBTP_NTSEG2_VALUE); + hw->MCAN_DBTP = MCAN_DBTP_DBRP(CONF_MCAN_FBTP_FBRP_VALUE) | + MCAN_DBTP_DSJW(CONF_MCAN_FBTP_FSJW_VALUE) | + MCAN_DBTP_DTSEG1(CONF_MCAN_FBTP_FTSEG1_VALUE) | + MCAN_DBTP_DTSEG2(CONF_MCAN_FBTP_FTSEG2_VALUE); + + hw->MCAN_TDCR = MCAN_TDCR_TDCO(config->delay_compensation_offset) | + MCAN_TDCR_TDCF(config->delay_compensation_filter_window_length); + + if (config->tdc_enable) { + hw->MCAN_DBTP |= MCAN_DBTP_TDC_ENABLED; + } +#else + /* Timing setting. */ + hw->MCAN_BTP = MCAN_BTP_BRP(CONF_MCAN_NBTP_NBRP_VALUE) | + MCAN_BTP_SJW(CONF_MCAN_NBTP_NSJW_VALUE) | + MCAN_BTP_TSEG1(CONF_MCAN_NBTP_NTSEG1_VALUE) | + MCAN_BTP_TSEG2(CONF_MCAN_NBTP_NTSEG2_VALUE); + hw->MCAN_FBTP = MCAN_FBTP_FBRP(CONF_MCAN_FBTP_FBRP_VALUE) | + MCAN_FBTP_FSJW(CONF_MCAN_FBTP_FSJW_VALUE) | + MCAN_FBTP_FTSEG1(CONF_MCAN_FBTP_FTSEG1_VALUE) | + MCAN_FBTP_FTSEG2(CONF_MCAN_FBTP_FTSEG2_VALUE) | + MCAN_FBTP_TDCO(config->delay_compensation_offset); + + if (config->tdc_enable) { + hw->MCAN_FBTP |= MCAN_FBTP_TDC_ENABLED; + } +#endif + hw->MCAN_RWD |= MCAN_RWD_WDC(config->watchdog_configuration); + + if (config->transmit_pause) { + hw->MCAN_CCCR |= MCAN_CCCR_TXP; + } + + if (!config->automatic_retransmission) { + hw->MCAN_CCCR |= MCAN_CCCR_DAR; + } + + if (config->clock_stop_request) { + hw->MCAN_CCCR |= MCAN_CCCR_CSR; + } + + hw->MCAN_TSCC = MCAN_TSCC_TCP(config->timestamp_prescaler) | + MCAN_TSCC_TSS_TCP_INC; + + hw->MCAN_TOCC = MCAN_TOCC_TOP(config->timeout_period) | + config->timeout_mode | config->timeout_enable; + + hw->MCAN_GFC = MCAN_GFC_ANFS(config->nonmatching_frames_action_standard) | + MCAN_GFC_ANFE(config->nonmatching_frames_action_extended); + if (config->remote_frames_standard_reject) { + hw->MCAN_GFC |= MCAN_GFC_RRFS; + } + if (config->remote_frames_extended_reject) { + hw->MCAN_GFC|= MCAN_GFC_RRFE; + } + + hw->MCAN_XIDAM = config->extended_id_mask; + + if (config->rx_fifo_0_overwrite) { + hw->MCAN_RXF0C |= MCAN_RXF0C_F0OM; + } + hw->MCAN_RXF0C |= MCAN_RXF0C_F0WM(config->rx_fifo_0_watermark); + + if (config->rx_fifo_1_overwrite) { + hw->MCAN_RXF1C |= MCAN_RXF1C_F1OM; + } + hw->MCAN_RXF1C |= MCAN_RXF1C_F1WM(config->rx_fifo_1_watermark); + + if (config->tx_queue_mode) { + hw->MCAN_TXBC |= MCAN_TXBC_TFQM; + } + + hw->MCAN_TXEFC |= MCAN_TXEFC_EFWM(config->tx_event_fifo_watermark); +} + +/** + * \brief enable can module clock. + * + * \param module_inst MCAN instance + * + */ +static void _mcan_enable_peripheral_clock(struct mcan_module *const module_inst) +{ + if (module_inst->hw == MCAN0) { + /* Turn on the digital interface clock. */ + pmc_enable_periph_clk(ID_MCAN0); + } else if (module_inst->hw == MCAN1) { + /* Turn on the digital interface clock. */ + pmc_enable_periph_clk(ID_MCAN1); + } +} + +/** + * \brief initialize can module. + * + * \param module_inst MCAN instance + * \param hw Base address of MCAN. + * \param config default configuration . + */ +void mcan_init(struct mcan_module *const module_inst, Mcan *hw, + struct mcan_config *config) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(hw); + Assert(config); + + /* Associate the software module instance with the hardware module */ + module_inst->hw = hw; + + pmc_disable_pck(PMC_PCK_5); + pmc_enable_upll_clock(); + pmc_switch_pck_to_upllck(PMC_PCK_5, PMC_PCK_PRES(23)); //PCK5 (CAN Core Clock) at 20 MHz ("Selected clock is divided by PRES+1" - datasheet) + pmc_enable_pck(PMC_PCK_5); + + /* Enable peripheral clock */ + _mcan_enable_peripheral_clock(module_inst); + + + /* Configuration Change Enable. */ + hw->MCAN_CCCR |= MCAN_CCCR_CCE; + + /* Initialize the message memory address. */ + _mcan_message_memory_init(hw); + + /* Set the configuration. */ + _mcan_set_configuration(hw, config); + + /* Enable the interrupt setting which no need change. */ + hw->MCAN_ILE = MCAN_ILE_EINT0 | MCAN_ILE_EINT1; + hw->MCAN_TXBTIE = 0xFFFFFFFFul; + hw->MCAN_TXBCIE = 0xFFFFFFFFul; +} + +/** + * \brief Set MCAN baudrate. + * + * \param[in] hw Pointer to the MCAN module instance + * \param[in] baudrate MCAN baudrate + */ +void mcan_set_baudrate(Mcan *hw, uint32_t baudrate) +{ + uint32_t gclk_mcan_value; + uint32_t mcan_nbtp_nbrp_value; + uint32_t mcan_nbtp_nsgw_value = 3, mcan_nbtp_ntseg1_value = 10, mcan_nbtp_ntseg2_value = 7; + + gclk_mcan_value = 20000000; //See PCK5 setup above on line 271 - CAN Core clock speed + + //bit time is [NTSEG1 + NTSEG2 + 3] and does not factor in mcan_nbtp_nsgw_value + mcan_nbtp_nbrp_value = gclk_mcan_value / baudrate / (3 + mcan_nbtp_ntseg1_value + mcan_nbtp_ntseg2_value)-1; +#if (SAMV71B || SAME70B || SAMV70B) + hw->MCAN_NBTP = MCAN_NBTP_NBRP(mcan_nbtp_nbrp_value) | + MCAN_NBTP_NSJW(mcan_nbtp_nsgw_value) | + MCAN_NBTP_NTSEG1(mcan_nbtp_ntseg1_value) | + MCAN_NBTP_NTSEG2(mcan_nbtp_ntseg2_value); +#else + hw->MCAN_BTP = MCAN_BTP_BRP(mcan_nbtp_nbrp_value) | + MCAN_BTP_SJW(mcan_nbtp_nsgw_value) | + MCAN_BTP_TSEG1(mcan_nbtp_ntseg1_value) | + MCAN_BTP_TSEG2(mcan_nbtp_ntseg2_value); +#endif +} + +/** + * \brief Set MCAN_FD baudrate. + * + * \param[in] hw Pointer to the MCAN_FD module instance + * \param[in] baudrate MCAN_FD baudrate + */ +void mcan_fd_set_baudrate(Mcan *hw, uint32_t baudrate) +{ + uint32_t gclk_mcan_fd_value; + uint32_t mcan_fd_dbtp_dbrp_value; + uint32_t mcan_fd_dbtp_dsgw_value = 3, mcan_fd_dbtp_dtseg1_value = 9, mcan_fd_dbtp_dtseg2_value = 3; + + gclk_mcan_fd_value = sysclk_get_peripheral_hz(); + + mcan_fd_dbtp_dbrp_value = gclk_mcan_fd_value / baudrate / (3 + mcan_fd_dbtp_dtseg1_value + mcan_fd_dbtp_dtseg2_value); +#if (SAMV71B || SAME70B || SAMV70B) + hw->MCAN_DBTP = MCAN_DBTP_DBRP(mcan_fd_dbtp_dbrp_value) | + MCAN_DBTP_DSJW(mcan_fd_dbtp_dsgw_value) | + MCAN_DBTP_DTSEG1(mcan_fd_dbtp_dtseg1_value) | + MCAN_DBTP_DTSEG2(mcan_fd_dbtp_dtseg2_value); +#else + hw->MCAN_FBTP = MCAN_FBTP_FBRP(mcan_fd_dbtp_dbrp_value) | + MCAN_FBTP_FSJW(mcan_fd_dbtp_dsgw_value) | + MCAN_FBTP_FTSEG1(mcan_fd_dbtp_dtseg1_value) | + MCAN_FBTP_FTSEG2(mcan_fd_dbtp_dtseg2_value); +#endif +} + +/** + * \brief start can module after initialization. + * + * \param module_inst MCAN instance + * + */ +void mcan_start(struct mcan_module *const module_inst) +{ + module_inst->hw->MCAN_CCCR &= ~MCAN_CCCR_INIT; + /* Wait for the sync. */ + while (module_inst->hw->MCAN_CCCR & MCAN_CCCR_INIT); +} + +/** + * \brief stop mcan module when bus off occurs + * + * \param module_inst MCAN instance + * + */ +void mcan_stop(struct mcan_module *const module_inst) +{ + module_inst->hw->MCAN_CCCR |= MCAN_CCCR_INIT; + /* Wait for the sync. */ + while (!(module_inst->hw->MCAN_CCCR & MCAN_CCCR_INIT)); +} + +/** + * \brief switch mcan module into fd mode. + * + * \param module_inst MCAN instance + * + */ +void mcan_enable_fd_mode(struct mcan_module *const module_inst) +{ + module_inst->hw->MCAN_CCCR |= MCAN_CCCR_INIT; + /* Wait for the sync. */ + while (!(module_inst->hw->MCAN_CCCR & MCAN_CCCR_INIT)); + module_inst->hw->MCAN_CCCR |= MCAN_CCCR_CCE; +#if (SAMV71B || SAME70B || SAMV70B) + module_inst->hw->MCAN_CCCR |= (MCAN_CCCR_FDOE | MCAN_CCCR_BRSE); +#else + module_inst->hw->MCAN_CCCR |= MCAN_CCCR_CME(2); + module_inst->hw->MCAN_CCCR |= MCAN_CCCR_CMR(2); +#endif + +} + +/** + * \brief disable fd mode of mcan module. + * + * \param module_inst MCAN instance + * + */ +void mcan_disable_fd_mode(struct mcan_module *const module_inst) +{ + module_inst->hw->MCAN_CCCR |= MCAN_CCCR_INIT; + /* Wait for the sync. */ + while (!(module_inst->hw->MCAN_CCCR & MCAN_CCCR_INIT)); + module_inst->hw->MCAN_CCCR |= MCAN_CCCR_CCE; +#if (SAMV71B || SAME70B || SAMV70B) + module_inst->hw->MCAN_CCCR &= MCAN_CCCR_FDOE; +#else + module_inst->hw->MCAN_CCCR &= MCAN_CCCR_CME(MCAN_CCCR_CME_ISO11898_1); +#endif +} + +/** + * \brief enable restricted mode of mcan module. + * + * \param module_inst MCAN instance + * + */ +void mcan_enable_restricted_operation_mode( + struct mcan_module *const module_inst) +{ + module_inst->hw->MCAN_CCCR |= MCAN_CCCR_INIT; + /* Wait for the sync. */ + while (!(module_inst->hw->MCAN_CCCR & MCAN_CCCR_INIT)); + module_inst->hw->MCAN_CCCR |= MCAN_CCCR_CCE; + + module_inst->hw->MCAN_CCCR |= MCAN_CCCR_ASM; +} + +/** + * \brief disable restricted mode of mcan module. + * + * \param module_inst MCAN instance + * + */ +void mcan_disable_restricted_operation_mode( + struct mcan_module *const module_inst) +{ + module_inst->hw->MCAN_CCCR &= ~MCAN_CCCR_ASM; +} + +/** + * \brief enable bus monitor mode of mcan module. + * + * \param module_inst MCAN instance + * + */ +void mcan_enable_bus_monitor_mode(struct mcan_module *const module_inst) +{ + module_inst->hw->MCAN_CCCR |= MCAN_CCCR_INIT; + /* Wait for the sync. */ + while (!(module_inst->hw->MCAN_CCCR & MCAN_CCCR_INIT)); + module_inst->hw->MCAN_CCCR |= MCAN_CCCR_CCE; + + module_inst->hw->MCAN_CCCR |= MCAN_CCCR_MON; +} + +/** + * \brief disable bus monitor mode of mcan module. + * + * \param module_inst MCAN instance + * + */ +void mcan_disable_bus_monitor_mode(struct mcan_module *const module_inst) +{ + module_inst->hw->MCAN_CCCR &= ~MCAN_CCCR_MON; +} + +/** + * \brief enable sleep mode of mcan module. + * + * \param module_inst MCAN instance + * + */ +void mcan_enable_sleep_mode(struct mcan_module *const module_inst) +{ + module_inst->hw->MCAN_CCCR |= MCAN_CCCR_CSR; + /* Wait for the sync. */ + while (!(module_inst->hw->MCAN_CCCR & MCAN_CCCR_INIT)); + + while (!(module_inst->hw->MCAN_CCCR & MCAN_CCCR_CSA)); +} + +/** + * \brief disable sleep mode of mcan module. + * + * \param module_inst MCAN instance + * + */ +void mcan_disable_sleep_mode(struct mcan_module *const module_inst) +{ + /* Enable peripheral clock */ + _mcan_enable_peripheral_clock(module_inst); + + module_inst->hw->MCAN_CCCR &= ~MCAN_CCCR_CSR; + while ((module_inst->hw->MCAN_CCCR & MCAN_CCCR_CSA)); +} + +/** + * \brief enable test mode of mcan module. + * + * \param module_inst MCAN instance + * + */ +void mcan_enable_test_mode(struct mcan_module *const module_inst) +{ + module_inst->hw->MCAN_CCCR |= MCAN_CCCR_INIT; + /* Wait for the sync. */ + while (!(module_inst->hw->MCAN_CCCR & MCAN_CCCR_INIT)); + module_inst->hw->MCAN_CCCR |= MCAN_CCCR_CCE; + + module_inst->hw->MCAN_CCCR |= MCAN_CCCR_TEST; + module_inst->hw->MCAN_TEST |= MCAN_TEST_LBCK; +} + +/** + * \brief disable test mode of mcan module. + * + * \param module_inst MCAN instance + * + */ +void mcan_disable_test_mode(struct mcan_module *const module_inst) +{ + module_inst->hw->MCAN_CCCR &= ~MCAN_CCCR_TEST; +} + +/** + * \brief set standard receive CAN ID. + * + * \param module_inst MCAN instance + * \param sd_filter structure of CAN ID + * \param index CAN messages memory index for different CAN ID + * + * \return status code. + */ +enum status_code mcan_set_rx_standard_filter( + struct mcan_module *const module_inst, + struct mcan_standard_message_filter_element *sd_filter, uint32_t index) +{ + if (module_inst->hw == MCAN0) { + mcan0_rx_standard_filter[index].S0.reg = sd_filter->S0.reg; + return STATUS_OK; + } else if (module_inst->hw == MCAN1) { + mcan1_rx_standard_filter[index].S0.reg = sd_filter->S0.reg; + return STATUS_OK; + } + return ERR_INVALID_ARG; +} + +/** + * \brief set extended receive CAN ID. + * + * \param module_inst MCAN instance + * \param sd_filter structure of extended CAN ID + * \param index CAN messages memory index for different CAN ID + * + * \return status code. + */ +enum status_code mcan_set_rx_extended_filter( + struct mcan_module *const module_inst, + struct mcan_extended_message_filter_element *et_filter, uint32_t index) +{ + if (module_inst->hw == MCAN0) { + mcan0_rx_extended_filter[index].F0.reg = et_filter->F0.reg; + mcan0_rx_extended_filter[index].F1.reg = et_filter->F1.reg; + return STATUS_OK; + } else if (module_inst->hw == MCAN1) { + mcan1_rx_extended_filter[index].F0.reg = et_filter->F0.reg; + mcan1_rx_extended_filter[index].F1.reg = et_filter->F1.reg; + return STATUS_OK; + } + return ERR_INVALID_ARG; +} + +/** + * \brief get dedicated rx buffer element . + * + * \param module_inst MCAN instance + * \param rx_element structure of element + * \param index CAN messages memory index for receiving CAN ID + * + * \return status code. + */ +enum status_code mcan_get_rx_buffer_element( + struct mcan_module *const module_inst, + struct mcan_rx_element_buffer *rx_element, uint32_t index) +{ + if (module_inst->hw == MCAN0) { + memcpy(rx_element, &mcan0_rx_buffer[index], sizeof(struct mcan_rx_element_buffer)); + return STATUS_OK; + } else if (module_inst->hw == MCAN1) { + memcpy(rx_element, &mcan1_rx_buffer[index], sizeof(struct mcan_rx_element_buffer)); + return STATUS_OK; + } + return ERR_INVALID_ARG; +} + +/** + * \brief get FIFO rx buffer element . + * + * \param module_inst MCAN instance + * \param rx_element structure of element + * \param index CAN messages memory index for receiving CAN ID + * + * \return status code. + */ +enum status_code mcan_get_rx_fifo_0_element( + struct mcan_module *const module_inst, + struct mcan_rx_element_fifo_0 *rx_element, uint32_t index) +{ + if (module_inst->hw == MCAN0) { + memcpy(rx_element, &mcan0_rx_fifo_0[index], sizeof(struct mcan_rx_element_buffer)); + return STATUS_OK; + } else if (module_inst->hw == MCAN1) { + memcpy(rx_element, &mcan1_rx_fifo_0[index], sizeof(struct mcan_rx_element_buffer)); + return STATUS_OK; + } + return ERR_INVALID_ARG; +} + +/** + * \brief get FIFO rx buffer element . + * + * \param module_inst MCAN instance + * \param rx_element structure of element + * \param index CAN messages memory index for receiving CAN ID + * + * \return status code. + */ +enum status_code mcan_get_rx_fifo_1_element( + struct mcan_module *const module_inst, + struct mcan_rx_element_fifo_1 *rx_element, uint32_t index) +{ + if (module_inst->hw == MCAN0) { + memcpy(rx_element, &mcan0_rx_fifo_1[index], sizeof(struct mcan_rx_element_buffer)); + return STATUS_OK; + } else if (module_inst->hw == MCAN1) { + memcpy(rx_element, &mcan1_rx_fifo_1[index], sizeof(struct mcan_rx_element_buffer)); + return STATUS_OK; + } + return ERR_INVALID_ARG; +} + +/** + * \brief set dedicated transmit buffer element . + * + * \param module_inst MCAN instance + * \param tx_element structure of element + * \param index CAN messages memory index for transmitting CAN ID + * + * \return status code. + */ +enum status_code mcan_set_tx_buffer_element( + struct mcan_module *const module_inst, + struct mcan_tx_element *tx_element, uint32_t index) +{ + uint32_t i; + if (module_inst->hw == MCAN0) { + mcan0_tx_buffer[index].T0.reg = tx_element->T0.reg; + mcan0_tx_buffer[index].T1.reg = tx_element->T1.reg; + for (i = 0; i < CONF_MCAN_ELEMENT_DATA_SIZE; i++) { + mcan0_tx_buffer[index].data[i] = tx_element->data[i]; + } + return STATUS_OK; + } else if (module_inst->hw == MCAN1) { + mcan1_tx_buffer[index].T0.reg = tx_element->T0.reg; + mcan1_tx_buffer[index].T1.reg = tx_element->T1.reg; + for (i = 0; i < CONF_MCAN_ELEMENT_DATA_SIZE; i++) { + mcan1_tx_buffer[index].data[i] = tx_element->data[i]; + } + return STATUS_OK; + } + return ERR_INVALID_ARG; +} + +/** + * \brief set FIFO transmit buffer element . + * + * \param module_inst MCAN instance + * \param tx_element structure of element + * \param index CAN messages memory index for transmitting CAN ID + * + * \return status code. + */ +enum status_code mcan_get_tx_event_fifo_element( + struct mcan_module *const module_inst, + struct mcan_tx_event_element *tx_event_element, uint32_t index) +{ + if (module_inst->hw == MCAN0) { + tx_event_element->E0.reg = mcan0_tx_event_fifo[index].E0.reg; + tx_event_element->E1.reg = mcan0_tx_event_fifo[index].E1.reg; + return STATUS_OK; + } else if (module_inst->hw == MCAN1) { + tx_event_element->E0.reg = mcan1_tx_event_fifo[index].E0.reg; + tx_event_element->E1.reg = mcan1_tx_event_fifo[index].E1.reg; + return STATUS_OK; + } + return ERR_INVALID_ARG; +} + +/** @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/** @endcond */ \ No newline at end of file diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/mcan/mcan.h b/hw-libs/drivers/SAMx70/ASF/sam/drivers/mcan/mcan.h new file mode 100644 index 000000000..c5e5b7e7e --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/mcan/mcan.h @@ -0,0 +1,1215 @@ +/** + * \file + * + * \brief SAM Control Area Network (MCAN) Low Level Driver + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef MCAN_H_INCLUDED +#define MCAN_H_INCLUDED + +#include +#include +#include "status_codes.h" +/** + * \name Message RAM + * @{ + */ + +/* -------- MCAN_RX_ELEMENT_R0 : (MCAN RX element: 0x00) (R/W 32) Rx Element R0 Configuration -------- */ +typedef union { + struct { + /* bit: 0..28 Identifier */ + uint32_t ID:29; + /* bit: 29 Remote Transmission Request */ + uint32_t RTR:1; + /* bit: 30 Extended Identifier */ + uint32_t XTD:1; + /* bit: 31 Error State Indicator */ + uint32_t ESI:1; + } bit; + /* Type used for register access */ + uint32_t reg; +} MCAN_RX_ELEMENT_R0_Type; + +#define MCAN_RX_ELEMENT_R0_ID_Pos 0 +#define MCAN_RX_ELEMENT_R0_ID_Msk (0x1FFFFFFFul << MCAN_RX_ELEMENT_R0_ID_Pos) +#define MCAN_RX_ELEMENT_R0_ID(value) ((MCAN_RX_ELEMENT_R0_ID_Msk & ((value) << MCAN_RX_ELEMENT_R0_ID_Pos))) +#define MCAN_RX_ELEMENT_R0_RTR_Pos 29 +#define MCAN_RX_ELEMENT_R0_RTR (0x1ul << MCAN_RX_ELEMENT_R0_RTR_Pos) +#define MCAN_RX_ELEMENT_R0_XTD_Pos 30 +#define MCAN_RX_ELEMENT_R0_XTD (0x1ul << MCAN_RX_ELEMENT_R0_XTD_Pos) +#define MCAN_RX_ELEMENT_R0_ESI_Pos 31 +#define MCAN_RX_ELEMENT_R0_ESI (0x1ul << MCAN_RX_ELEMENT_R0_ESI_Pos) + +/* -------- MCAN_RX_ELEMENT_R1 : (MCAN RX element: 0x01) (R/W 32) Rx Element R1 Configuration -------- */ +typedef union { + struct { + /* bit: 0..15 Rx Timestamp */ + uint32_t RXTS:16; + /* bit: 16..19 Data Length Code */ + uint32_t DLC:4; + /* bit: 20 Bit Rate Switch */ + uint32_t BRS:1; + /* bit: 21 FD Format */ + uint32_t EDL:1; + /* bit: 22..23 Reserved */ + uint32_t :2; + /* bit: 24..30 Filter Index */ + uint32_t FIDX:7; + /* bit: 31 Accepted Non-matching Frame */ + uint32_t ANMF:1; + } bit; + /* Type used for register access */ + uint32_t reg; +} MCAN_RX_ELEMENT_R1_Type; + +#define MCAN_RX_ELEMENT_R1_RXTS_Pos 0 +#define MCAN_RX_ELEMENT_R1_RXTS_Msk (0xFFFFul << MCAN_RX_ELEMENT_R1_RXTS_Pos) +#define MCAN_RX_ELEMENT_R1_RXTS(value) ((MCAN_RX_ELEMENT_R1_RXTS_Msk & ((value) << MCAN_RX_ELEMENT_R1_RXTS_Pos))) +#define MCAN_RX_ELEMENT_R1_DLC_Pos 16 +#define MCAN_RX_ELEMENT_R1_DLC_Msk (0xFul << MCAN_RX_ELEMENT_R1_DLC_Pos) +#define MCAN_RX_ELEMENT_R1_DLC(value) ((MCAN_RX_ELEMENT_R1_DLC_Msk & ((value) << MCAN_RX_ELEMENT_R1_DLC_Pos))) +#define MCAN_RX_ELEMENT_R1_BRS_Pos 20 +#define MCAN_RX_ELEMENT_R1_BRS (0x1ul << MCAN_RX_ELEMENT_R1_BRS_Pos) +#define MCAN_RX_ELEMENT_R1_FDF_Pos 21 +#define MCAN_RX_ELEMENT_R1_FDF (0x1ul << MCAN_RX_ELEMENT_R1_FDF_Pos) +#define MCAN_RX_ELEMENT_R1_FIDX_Pos 24 +#define MCAN_RX_ELEMENT_R1_FIDX_Msk (0x7Ful << MCAN_RX_ELEMENT_R1_FIDX_Pos) +#define MCAN_RX_ELEMENT_R1_FIDX(value) ((MCAN_RX_ELEMENT_R1_FIDX_Msk & ((value) << MCAN_RX_ELEMENT_R1_FIDX_Pos))) +#define MCAN_RX_ELEMENT_R1_ANMF_Pos 31 +#define MCAN_RX_ELEMENT_R1_ANMF (0x1ul << MCAN_RX_ELEMENT_R1_ANMF_Pos) + +/** + * \brief MCAN receive element structure for buffer. + */ +struct mcan_rx_element_buffer { + __IO MCAN_RX_ELEMENT_R0_Type R0; + __IO MCAN_RX_ELEMENT_R1_Type R1; + uint8_t data[CONF_MCAN_ELEMENT_DATA_SIZE]; +}; + +/** + * \brief MCAN receive element structure for FIFO 0. + */ +struct mcan_rx_element_fifo_0 { + __IO MCAN_RX_ELEMENT_R0_Type R0; + __IO MCAN_RX_ELEMENT_R1_Type R1; + uint8_t data[CONF_MCAN_ELEMENT_DATA_SIZE]; +}; + +/** + * \brief MCAN receive element structure for FIFO 1. + */ +struct mcan_rx_element_fifo_1 { + __IO MCAN_RX_ELEMENT_R0_Type R0; + __IO MCAN_RX_ELEMENT_R1_Type R1; + uint8_t data[CONF_MCAN_ELEMENT_DATA_SIZE]; +}; + +/* -------- MCAN_TX_ELEMENT_T0 : (MCAN TX element: 0x00) (R/W 32) Tx Element T0 Configuration -------- */ +typedef union { + struct { + /* bit: 0..28 Identifier */ + uint32_t ID:29; + /* bit: 29 Remote Transmission Request */ + uint32_t RTR:1; + /* bit: 30 Extended Identifier */ + uint32_t XTD:1; +#if (SAMV71B || SAME70B || SAMV70B) + /* bit: 31 Error State Indicator */ + uint32_t ESI:1; +#else + /* bit: 31 Reserved */ + uint32_t :1; +#endif + } bit; + /* Type used for register access */ + uint32_t reg; +} MCAN_TX_ELEMENT_T0_Type; + +#define MCAN_TX_ELEMENT_T0_EXTENDED_ID_Pos 0 +#define MCAN_TX_ELEMENT_T0_EXTENDED_ID_Msk (0x1FFFFFFFul << MCAN_TX_ELEMENT_T0_EXTENDED_ID_Pos) +#define MCAN_TX_ELEMENT_T0_EXTENDED_ID(value) ((MCAN_TX_ELEMENT_T0_EXTENDED_ID_Msk & ((value) << MCAN_TX_ELEMENT_T0_EXTENDED_ID_Pos))) +#define MCAN_TX_ELEMENT_T0_STANDARD_ID_Pos 18 +#define MCAN_TX_ELEMENT_T0_STANDARD_ID_Msk (0x7FFul << MCAN_TX_ELEMENT_T0_STANDARD_ID_Pos) +#define MCAN_TX_ELEMENT_T0_STANDARD_ID(value) ((MCAN_TX_ELEMENT_T0_STANDARD_ID_Msk & ((value) << MCAN_TX_ELEMENT_T0_STANDARD_ID_Pos))) +#define MCAN_TX_ELEMENT_T0_RTR_Pos 29 +#define MCAN_TX_ELEMENT_T0_RTR (0x1ul << MCAN_TX_ELEMENT_T0_RTR_Pos) +#define MCAN_TX_ELEMENT_T0_XTD_Pos 30 +#define MCAN_TX_ELEMENT_T0_XTD (0x1ul << MCAN_TX_ELEMENT_T0_XTD_Pos) +#if (SAMV71B || SAME70B || SAMV70B) +#define MCAN_TX_ELEMENT_T0_ESI_Pos 31 +#define MCAN_TX_ELEMENT_T0_ESI (0x1ul << MCAN_TX_ELEMENT_T0_ESI_Pos) +#endif + +/* -------- MCAN_TX_ELEMENT_T1 : (MCAN TX element: 0x01) (R/W 32) Tx Element T1 Configuration -------- */ +typedef union { + struct { + /* bit: 0..15 Reserved */ + uint32_t :16; + /* bit: 16..19 Data Length Code */ + uint32_t DLC:4; +#if (SAMV71B || SAME70B || SAMV70B) + /* bit: 20 Bit Rate Switch */ + uint32_t BRS:1; + /* bit: 21 FD Format */ + uint32_t FDF:1; + /* bit: 22 Reserved */ + uint32_t :1; +#else + /* bit: 20..22 Reserved */ + uint32_t :3; +#endif + /* bit: 23 Event FIFO Control */ + uint32_t EFCC:1; + /* bit: 24..31 Message Marker */ + uint32_t MM:8; + } bit; + /* Type used for register access */ + uint32_t reg; +} MCAN_TX_ELEMENT_T1_Type; + +#define MCAN_TX_ELEMENT_T1_DLC_Pos 16 +#define MCAN_TX_ELEMENT_T1_DLC_Msk (0xFul << MCAN_TX_ELEMENT_T1_DLC_Pos) +#define MCAN_TX_ELEMENT_T1_DLC(value) ((MCAN_TX_ELEMENT_T1_DLC_Msk & ((value) << MCAN_TX_ELEMENT_T1_DLC_Pos))) +/**< \brief (MCAN_RXESC) 8 byte data field */ +#define MCAN_TX_ELEMENT_T1_DLC_DATA8_Val 0x8ul +/**< \brief (MCAN_RXESC) 12 byte data field */ +#define MCAN_TX_ELEMENT_T1_DLC_DATA12_Val 0x9ul +/**< \brief (MCAN_RXESC) 16 byte data field */ +#define MCAN_TX_ELEMENT_T1_DLC_DATA16_Val 0xAul +/**< \brief (MCAN_RXESC) 20 byte data field */ +#define MCAN_TX_ELEMENT_T1_DLC_DATA20_Val 0xBul +/**< \brief (MCAN_RXESC) 24 byte data field */ +#define MCAN_TX_ELEMENT_T1_DLC_DATA24_Val 0xCul +/**< \brief (MCAN_RXESC) 32 byte data field */ +#define MCAN_TX_ELEMENT_T1_DLC_DATA32_Val 0xDul +/**< \brief (MCAN_RXESC) 48 byte data field */ +#define MCAN_TX_ELEMENT_T1_DLC_DATA48_Val 0xEul +/**< \brief (MCAN_RXESC) 64 byte data field */ +#define MCAN_TX_ELEMENT_T1_DLC_DATA64_Val 0xFul +#if (SAMV71B || SAME70B || SAMV70B) +#define MCAN_TX_ELEMENT_T1_BRS_Pos 20 +#define MCAN_TX_ELEMENT_T1_BRS (0x1ul << MCAN_TX_ELEMENT_T1_BRS_Pos) +#define MCAN_TX_ELEMENT_T1_FDF_Pos 21 +#define MCAN_TX_ELEMENT_T1_FDF (0x1ul << MCAN_TX_ELEMENT_T1_FDF_Pos) +#endif +#define MCAN_TX_ELEMENT_T1_EFC_Pos 23 +#define MCAN_TX_ELEMENT_T1_EFC (0x1ul << MCAN_TX_ELEMENT_T1_EFC_Pos) +#define MCAN_TX_ELEMENT_T1_MM_Pos 24 +#define MCAN_TX_ELEMENT_T1_MM_Msk (0xFFul << MCAN_TX_ELEMENT_T1_MM_Pos) +#define MCAN_TX_ELEMENT_T1_MM(value) ((MCAN_TX_ELEMENT_T1_MM_Msk & ((value) << MCAN_TX_ELEMENT_T1_MM_Pos))) + +/** + * \brief MCAN transfer element structure. + * + * Common element structure for transfer buffer and FIFO/QUEUE. + */ +struct mcan_tx_element { + __IO MCAN_TX_ELEMENT_T0_Type T0; + __IO MCAN_TX_ELEMENT_T1_Type T1; + uint8_t data[CONF_MCAN_ELEMENT_DATA_SIZE]; +}; + +/* -------- MCAN_TX_EVENT_ELEMENT_E0 : (MCAN TX event element: 0x00) (R/W 32) Tx Event Element E0 Configuration -------- */ +typedef union { + struct { + /* bit: 0..28 Identifier */ + uint32_t ID:29; + /* bit: 29 Remote Transmission Request */ + uint32_t RTR:1; + /* bit: 30 Extended Identifier */ + uint32_t XTD:1; + /* bit: 31 Error State Indicator */ + uint32_t ESI:1; + } bit; + /* Type used for register access */ + uint32_t reg; +} MCAN_TX_EVENT_ELEMENT_E0_Type; + +#define MCAN_TX_EVENT_ELEMENT_E0_ID_Pos 0 +#define MCAN_TX_EVENT_ELEMENT_E0_ID_Msk (0x1FFFFFFFul << MCAN_TX_EVENT_ELEMENT_E0_ID_Pos) +#define MCAN_TX_EVENT_ELEMENT_E0_ID(value) ((MCAN_TX_EVENT_ELEMENT_E0_ID_Msk & ((value) << MCAN_TX_EVENT_ELEMENT_E0_ID_Pos))) +#define MCAN_TX_EVENT_ELEMENT_E0_RTR_Pos 29 +#define MCAN_TX_EVENT_ELEMENT_E0_RTR (0x1ul << MCAN_TX_EVENT_ELEMENT_E0_RTR_Pos) +#define MCAN_TX_EVENT_ELEMENT_E0_XTD_Pos 30 +#define MCAN_TX_EVENT_ELEMENT_E0_XTD (0x1ul << MCAN_TX_EVENT_ELEMENT_E0_XTD_Pos) +#define MCAN_TX_EVENT_ELEMENT_E0_ESI_Pos 31 +#define MCAN_TX_EVENT_ELEMENT_E0_ESI (0x1ul << MCAN_TX_EVENT_ELEMENT_E0_ESI_Pos) + +/* -------- MCAN_TX_EVENT_ELEMENT_E1 : (MCAN TX event element: 0x01) (R/W 32) Tx Event Element E1 Configuration -------- */ +typedef union { + struct { + /* bit: 0..15 Tx Timestamp */ + uint32_t TXTS:16; + /* bit: 16..19 Data Length Code */ + uint32_t DLC:4; + /* bit: 20 Bit Rate Switch */ + uint32_t BRS:1; + /* bit: 21 FD Format */ + uint32_t EDL:1; + /* bit: 22..23 Event Type */ + uint32_t ET:2; + /* bit: 24..31 Message Marker */ + uint32_t MM:8; + } bit; + /* Type used for register access */ + uint32_t reg; +} MCAN_TX_EVENT_ELEMENT_E1_Type; + +#define MCAN_TX_EVENT_ELEMENT_E1_TXTS_Pos 0 +#define MCAN_TX_EVENT_ELEMENT_E1_TXTS_Msk (0xFFFFul << MCAN_TX_EVENT_ELEMENT_E1_TXTS_Pos) +#define MCAN_TX_EVENT_ELEMENT_E1_TXTS(value) ((MCAN_TX_EVENT_ELEMENT_E1_TXTS_Msk & ((value) << MCAN_TX_EVENT_ELEMENT_E1_TXTS_Pos))) +#define MCAN_TX_EVENT_ELEMENT_E1_DLC_Pos 16 +#define MCAN_TX_EVENT_ELEMENT_E1_DLC_Msk (0xFul << MCAN_TX_EVENT_ELEMENT_E1_DLC_Pos) +#define MCAN_TX_EVENT_ELEMENT_E1_DLC(value) ((MCAN_TX_EVENT_ELEMENT_E1_DLC_Msk & ((value) << MCAN_TX_EVENT_ELEMENT_E1_DLC_Pos))) +#define MCAN_TX_EVENT_ELEMENT_E1_BRS_Pos 20 +#define MCAN_TX_EVENT_ELEMENT_E1_BRS (0x1ul << MCAN_TX_EVENT_ELEMENT_E1_BRS_Pos) +#define MCAN_TX_EVENT_ELEMENT_E1_FDF_Pos 21 +#define MCAN_TX_EVENT_ELEMENT_E1_FDF (0x1ul << MCAN_TX_EVENT_ELEMENT_E1_FDF_Pos) +#define MCAN_TX_EVENT_ELEMENT_E1_ET_Pos 22 +#define MCAN_TX_EVENT_ELEMENT_E1_ET_Msk (0x3ul << MCAN_TX_EVENT_ELEMENT_E1_ET_Pos) +#define MCAN_TX_EVENT_ELEMENT_E1_ET(value) ((MCAN_TX_EVENT_ELEMENT_E1_ET_Msk & ((value) << MCAN_TX_EVENT_ELEMENT_E1_ET_Pos))) +#define MCAN_TX_EVENT_ELEMENT_E1_MM_Pos 24 +#define MCAN_TX_EVENT_ELEMENT_E1_MM_Msk (0xFFul << MCAN_TX_EVENT_ELEMENT_E1_MM_Pos) +#define MCAN_TX_EVENT_ELEMENT_E1_MM(value) ((MCAN_TX_EVENT_ELEMENT_E1_MM_Msk & ((value) << MCAN_TX_EVENT_ELEMENT_E1_MM_Pos))) + +/** + * \brief MCAN transfer event FIFO element structure. + * + * Common element structure for transfer event FIFO. + */ +struct mcan_tx_event_element { + __IO MCAN_TX_EVENT_ELEMENT_E0_Type E0; + __IO MCAN_TX_EVENT_ELEMENT_E1_Type E1; +}; + +/* -------- MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0 : (MCAN standard message ID filter element: 0x00) (R/W 32) Standard Message ID Filter Element S0 Configuration -------- */ +typedef union { + struct { + /* bit: 0..10 Standard Filter ID 2 */ + uint32_t SFID2:11; + /* bit: 11..15 Reserved */ + uint32_t :5; + /* bit: 16..26 Standard Filter ID 1 */ + uint32_t SFID1:11; + /* bit: 27..29 Standard Filter Element Configuration */ + uint32_t SFEC:3; + /* bit: 30..31 Standard Filter Type */ + uint32_t SFT:2; + } bit; + /* Type used for register access */ + uint32_t reg; +} MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_Type; + +#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID2_Pos 0 +#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID2_Msk (0x7FFul << MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID2_Pos) +#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID2(value) ((MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID2_Msk & ((value) << MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID2_Pos))) +#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID1_Pos 16 +#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID1_Msk (0x7FFul << MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID1_Pos) +#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID1(value) ((MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID1_Msk & ((value) << MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID1_Pos))) +#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_Pos 27 +#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_Msk (0x7ul << MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_Pos) +#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC(value) ((MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_Msk & ((value) << MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_Pos))) +#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_DISABLE_Val 0 +#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_STF0M_Val 1 +#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_STF1M_Val 2 +#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_REJECT_Val 3 +#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_PRIORITY_Val 4 +#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_PRIF0M_Val 5 +#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_PRIF1M_Val 6 +#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_STRXBUF_Val 7 +#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT_Pos 30 +#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT_Msk (0x3ul << MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT_Pos) +#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT(value) ((MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT_Msk & ((value) << MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT_Pos))) +#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT_RANGE MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT(0) +#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT_DUAL MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT(1) +#define MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT_CLASSIC MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT(2) + +/** + * \brief MCAN standard message ID filter element structure. + * + * Common element structure for standard message ID filter element. + */ +struct mcan_standard_message_filter_element { + __IO MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_Type S0; +}; + +/* -------- MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0 : (MCAN extended message ID filter element: 0x00) (R/W 32) Extended Message ID Filter Element F0 Configuration -------- */ +typedef union { + struct { + /* bit: 0..28 Extended Filter ID 1 */ + uint32_t EFID1:29; + /* bit: 29..31 Extended Filter Element Configuration */ + uint32_t EFEC:3; + } bit; + /* Type used for register access */ + uint32_t reg; +} MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_Type; + +#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFID1_Pos 0 +#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFID1_Msk (0x1FFFFFFFul << MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFID1_Pos) +#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFID1(value) ((MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFID1_Msk & ((value) << MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFID1_Pos))) +#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_Pos 29 +#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_Msk (0x7ul << MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_Pos) +#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC(value) ((MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_Msk & ((value) << MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_Pos))) +#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_DISABLE_Val 0 +#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_STF0M_Val 1 +#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_STF1M_Val 2 +#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_REJECT_Val 3 +#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_PRIORITY_Val 4 +#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_PRIF0M_Val 5 +#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_PRIF1M_Val 6 +#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_STRXBUF_Val 7 + +/* -------- MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1 : (MCAN extended message ID filter element: 0x01) (R/W 32) Extended Message ID Filter Element F1 Configuration -------- */ +typedef union { + struct { + /* bit: 0..28 Extended Filter ID 2 */ + uint32_t EFID2:29; + /* bit: 29 Reserved */ + uint32_t :1; + /* bit: 30..31 Extended Filter Type */ + uint32_t EFT:2; + } bit; + /* Type used for register access */ + uint32_t reg; +} MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_Type; + +#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFID2_Pos 0 +#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFID2_Msk (0x1FFFFFFFul << MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFID2_Pos) +#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFID2(value) ((MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFID2_Msk & ((value) << MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFID2_Pos))) +#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_Pos 30 +#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_Msk (0x3ul << MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_Pos) +#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT(value) ((MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_Msk & ((value) << MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_Pos))) +#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_RANGEM MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT(0) +#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_DUAL MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT(1) +#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_CLASSIC MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT(2) +#define MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_RANGE MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT(3) + +/** + * \brief MCAN extended message ID filter element structure. + * + * Common element structure for extended message ID filter element. + */ +struct mcan_extended_message_filter_element { + __IO MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_Type F0; + __IO MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_Type F1; +}; +/** @} */ + +/** + * \defgroup asfdoc_sam_mcan_group SAM Control Area Network (MCAN) Low Level Driver + * + * This driver for Atmel® | SMART SAM devices provides an low level + * interface for the configuration and management of the device's + * Control Area Network functionality. + * + * \note Since "The Control Area Network (CAN) performs communication according + * to ISO 11898-1 (Bosch CAN specification 2.0 part A,B) and to Bosch CAN FD + * specification V1.0", the driver is focus on the MAC layer and try to offer + * the APIs which can be used by upper application layer. + * + * For storage of Rx/Tx messages and for storage of the filter configuration, + * a message RAM is needed to the CAN module. In this driver, the message RAM + * is static allocated, the related setting is defined and can be changed in + * the module configuration file "conf_mcan.h". + * + * The following peripherals are used by this module: + * - CAN (Control Area Network) + * + * The following devices can use this module: + * - SAMV71 + * + * The outline of this documentation is as follows: + * - \ref asfdoc_sam_mcan_prerequisites + * - \ref asfdoc_sam_mcan_module_overview + * - \ref asfdoc_sam_mcan_special_considerations + * - \ref asfdoc_sam_mcan_extra_info + * - \ref asfdoc_sam_mcan_examples + * - \ref asfdoc_sam_mcan_api_overview + * + * + * \section asfdoc_sam_mcan_prerequisites Prerequisites + * + * There are no prerequisites for this module. + * + * + * \section asfdoc_sam_mcan_module_overview Module Overview + * + * This driver provides an interface for the Control Area Network Controller + * functions on the device. + * + * + * \section asfdoc_sam_mcan_special_considerations Special Considerations + * + * There are no special considerations for this module. + * + * + * \section asfdoc_sam_mcan_extra_info Extra Information + * + * For extra information see \ref asfdoc_sam_mcan_extra. This includes: + * - \ref asfdoc_sam_mcan_extra_acronyms + * - \ref asfdoc_sam_mcan_extra_dependencies + * - \ref asfdoc_sam_mcan_extra_errata + * - \ref asfdoc_sam_mcan_extra_history + * + * + * \section asfdoc_sam_mcan_examples Examples + * + * For a list of examples related to this driver, see + * \ref asfdoc_sam_mcan_exqsg. + * + * + * \section asfdoc_sam_mcan_api_overview API Overview + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name Module Setting + * @{ + */ + +/** + * \brief Can time out modes. + */ +enum mcan_timeout_mode { + /** Continuous operation. */ + MCAN_TIMEOUT_CONTINUES = MCAN_TOCC_TOS_CONTINUOUS, + /** Timeout controlled by TX Event FIFO. */ + MCAN_TIMEOUT_TX_EVEN_FIFO = MCAN_TOCC_TOS_TX_EV_TIMEOUT, + /** Timeout controlled by Rx FIFO 0. */ + MCAN_TIMEOUT_RX_FIFO_0 = MCAN_TOCC_TOS_RX0_EV_TIMEOUT, + /** Timeout controlled by Rx FIFO 1. */ + MCAN_TIMEOUT_RX_FIFO_1 = MCAN_TOCC_TOS_RX1_EV_TIMEOUT, +}; + + +/** + * \brief Can nonmatching frames action. + */ +enum mcan_nonmatching_frames_action { + /** Accept in Rx FIFO 0. */ + MCAN_NONMATCHING_FRAMES_FIFO_0, + /** Accept in Rx FIFO 1. */ + MCAN_NONMATCHING_FRAMES_FIFO_1, + /** Reject. */ + MCAN_NONMATCHING_FRAMES_REJECT, +}; + +/** + * \brief MCAN software device instance structure. + * + * MCAN software instance structure, used to retain software state information + * of an associated hardware module instance. + * + * \note The fields of this structure should not be altered by the user + * application; they are reserved for module-internal use only. + */ +struct mcan_module { +#if !defined(__DOXYGEN__) + /** Pointer to MCAN hardware module. */ + Mcan *hw; +#endif +}; + +/** + * \brief MCAN configuration structure. + * + * Configuration structure for an MCAN instance. This structure should be + * initialized by the \ref mcan_get_config_defaults() + * function before being modified by the user application. + */ +struct mcan_config { + /** MCAN run in standby control. */ + bool run_in_standby; + /** Start value of the Message RAM Watchdog Counter */ + uint8_t watchdog_configuration; + /** Transmit Pause. */ + bool transmit_pause; + /** Edge Filtering during Bus Integration. */ + bool edge_filtering; + /** Protocol Exception Handling. */ + bool protocol_exception_handling; + /** Automatic Retransmission. */ + bool automatic_retransmission; + /** Clock Stop Request. */ + bool clock_stop_request; + /** Clock Stop Acknowledge. */ + bool clock_stop_acknowledge; + /** Timestamp Counter Prescaler: 0x0-0xF */ + uint8_t timestamp_prescaler; + /** Timeout Period. */ + uint16_t timeout_period; + /** Timeout Mode. */ + enum mcan_timeout_mode timeout_mode; + /** Timeout enable. */ + bool timeout_enable; + /** Transceiver Delay Compensation enable. */ + bool tdc_enable; + /** Transmitter Delay Compensation Offset : 0x0-0x7F */ + uint8_t delay_compensation_offset; +#if (SAMV71B || SAME70B || SAMV70B) + /** Transmitter Delay Compensation Filter Window Length : 0x0-0x7F */ + uint8_t delay_compensation_filter_window_length; +#endif + /** Nonmatching frames action for standard frames. */ + enum mcan_nonmatching_frames_action nonmatching_frames_action_standard; + /** Nonmatching frames action for extended frames. */ + enum mcan_nonmatching_frames_action nonmatching_frames_action_extended; + /** Reject Remote Standard Frames. */ + bool remote_frames_standard_reject; + /** Reject Remote Extended Frames. */ + bool remote_frames_extended_reject; + /** Extended ID Mask: 0x0-0x1FFFFFFF. */ + uint32_t extended_id_mask; + /** Rx FIFO 0 Operation Mode. */ + bool rx_fifo_0_overwrite; + /** Rx FIFO 0 Watermark: 1-64, other value disable it. */ + uint8_t rx_fifo_0_watermark; + /** Rx FIFO 1 Operation Mode. */ + bool rx_fifo_1_overwrite; + /** Rx FIFO 1 Watermark: 1-64, other value disable it. */ + uint8_t rx_fifo_1_watermark; + /** Tx FIFO/Queue Mode, 0 for FIFO and 1 for Queue. */ + bool tx_queue_mode; + /** Tx Event FIFO Watermark: 1-32, other value disable it. */ + uint8_t tx_event_fifo_watermark; +}; + +/** + * \brief Initializes an MCAN configuration structure to defaults + * + * Initializes a given MCAN configuration struct to a set of known default + * values. This function should be called on any new instance of the + * configuration struct before being modified by the user application. + * + * The default configuration is as follows: + * \li Not run in standby mode + * \li Disable Watchdog + * \li Transmit pause enabled + * \li Edge filtering during bus integration enabled + * \li Protocol exception handling enabled + * \li Automatic retransmission enabled + * \li Clock stop request disabled + * \li Clock stop acknowledge disabled + * \li Timestamp Counter Prescaler 1 + * \li Timeout Period with 0xFFFF + * \li Timeout Mode: Continuous operation + * \li Disable Timeout + * \li Transmitter Delay Compensation Offset is 0 + * \li Transmitter Delay Compensation Filter Window Length is 0 + * \li Reject nonmatching standard frames + * \li Reject nonmatching extended frames + * \li Reject remote standard frames + * \li Reject remote extended frames + * \li Extended ID Mask is 0x1FFFFFFF + * \li Rx FIFO 0 Operation Mode: overwrite + * \li Disable Rx FIFO 0 Watermark + * \li Rx FIFO 1 Operation Mode: overwrite + * \li Disable Rx FIFO 1 Watermark + * \li Tx FIFO/Queue Mode: FIFO + * \li Disable Tx Event FIFO Watermark + * + * \param[out] config Pointer to configuration struct to initialize to + * default values + */ +static inline void mcan_get_config_defaults( + struct mcan_config *const config) +{ + /* Sanity check arguments */ + Assert(config); + + /* Default configuration values */ + config->run_in_standby = false; + config->watchdog_configuration = 0x00; + config->transmit_pause = true; + config->edge_filtering = true; + config->protocol_exception_handling = true; + config->automatic_retransmission = true; + config->clock_stop_request = false; + config->clock_stop_acknowledge = false; + config->timestamp_prescaler = 0; + config->timeout_period = 0xFFFF; + config->timeout_mode = MCAN_TIMEOUT_CONTINUES; + config->timeout_enable = false; + config->tdc_enable = false; + config->delay_compensation_offset = 0; +#if (SAMV71B || SAME70B || SAMV70B) + config->delay_compensation_filter_window_length = 0; +#endif + config->nonmatching_frames_action_standard = MCAN_NONMATCHING_FRAMES_REJECT; + config->nonmatching_frames_action_extended = MCAN_NONMATCHING_FRAMES_REJECT; + config->remote_frames_standard_reject = true; + config->remote_frames_extended_reject = true; + config->extended_id_mask = 0x1FFFFFFF; + config->rx_fifo_0_overwrite = true; + config->rx_fifo_0_watermark = 0; + config->rx_fifo_1_overwrite = true; + config->rx_fifo_1_watermark = 0; + config->tx_queue_mode = false; + config->tx_event_fifo_watermark = 0; +} + +void mcan_init(struct mcan_module *const module_inst, Mcan *hw, + struct mcan_config *config); +void mcan_set_baudrate(Mcan *hw, uint32_t baudrate); +void mcan_fd_set_baudrate(Mcan *hw, uint32_t baudrate); +void mcan_start(struct mcan_module *const module_inst); +void mcan_stop(struct mcan_module *const module_inst); +void mcan_enable_fd_mode(struct mcan_module *const module_inst); +void mcan_disable_fd_mode(struct mcan_module *const module_inst); +void mcan_enable_restricted_operation_mode( + struct mcan_module *const module_inst); +void mcan_disable_restricted_operation_mode( + struct mcan_module *const module_inst); + +void mcan_enable_bus_monitor_mode(struct mcan_module *const module_inst); +void mcan_disable_bus_monitor_mode(struct mcan_module *const module_inst); +void mcan_enable_sleep_mode(struct mcan_module *const module_inst); +void mcan_disable_sleep_mode(struct mcan_module *const module_inst); +void mcan_enable_test_mode(struct mcan_module *const module_inst); +void mcan_disable_test_mode(struct mcan_module *const module_inst); + +/** + * \brief Can read timestamp count value. + * + * \param[in] module_inst Pointer to the MCAN software instance struct + * + * \return Timestamp count value. + */ +static inline uint16_t mcan_read_timestamp_count_value( + struct mcan_module *const module_inst) +{ + return module_inst->hw->MCAN_TSCV; +} + +/** + * \brief Can read timeout count value. + * + * \param[in] module_inst Pointer to the MCAN software instance struct + * + * \return Timeout count value. + */ +static inline uint16_t mcan_read_timeout_count_value( + struct mcan_module *const module_inst) +{ + return module_inst->hw->MCAN_TOCV; +} + +/** + * \brief Can read error count. + * + * \param[in] module_inst Pointer to the MCAN software instance struct + * + * \return Error count value. + */ +static inline uint32_t mcan_read_error_count( + struct mcan_module *const module_inst) +{ + return module_inst->hw->MCAN_ECR; +} + +/** + * \brief Can read protocol status. + * + * \param[in] module_inst Pointer to the MCAN software instance struct + * + * \return protocol status value. + */ +static inline uint32_t mcan_read_protocal_status( + struct mcan_module *const module_inst) +{ + return module_inst->hw->MCAN_PSR; +} + +/** @} */ + +/** + * \name Rx Handling + * @{ + */ + +/** + * \brief Read high priority message status. + * + * \param[in] module_inst Pointer to the MCAN software instance struct + * + * \return High priority message status value. + */ +static inline uint32_t mcan_read_high_priority_message_status( + struct mcan_module *const module_inst) +{ + return module_inst->hw->MCAN_HPMS; +} + +/** + * \brief Get Rx buffer status. + * + * \param[in] module_inst Pointer to the MCAN software instance struct + * \param[in] index Index offset in Rx buffer + * + * \return Rx buffer status value. + * + * \retval true Rx Buffer updated from new message. + * \retval false Rx Buffer not updated. + */ +static inline bool mcan_rx_get_buffer_status( + struct mcan_module *const module_inst, uint32_t index) +{ + if (index < 32) { + if (module_inst->hw->MCAN_NDAT1 & (1 << index)) { + return true; + } else { + return false; + } + } else { + index -= 32; + if (module_inst->hw->MCAN_NDAT2 & (1 << index)) { + return true; + } else { + return false; + } + } +} + +/** + * \brief Clear Rx buffer status. + * + * \param[in] module_inst Pointer to the MCAN software instance struct + * \param[in] index Index offset in Rx buffer + * + */ +static inline void mcan_rx_clear_buffer_status( + struct mcan_module *const module_inst, uint32_t index) +{ + if (index < 32) { + module_inst->hw->MCAN_NDAT1 = (1 << index); + } else { + index -= 32; + module_inst->hw->MCAN_NDAT2 = (1 << index); + } +} + +/** + * \brief Get Rx FIFO status. + * + * \param[in] module_inst Pointer to the MCAN software instance struct + * \param[in] fifo_number Rx FIFO 0 or 1 + * + * \return Rx FIFO status value. + */ +static inline uint32_t mcan_rx_get_fifo_status( + struct mcan_module *const module_inst, bool fifo_number) +{ + if (!fifo_number) { + return module_inst->hw->MCAN_RXF0S; + } else { + return module_inst->hw->MCAN_RXF1S; + } +} + +/** + * \brief Set Rx acknowledge. + * + * \param[in] module_inst Pointer to the MCAN software instance struct + * \param[in] fifo_number Rx FIFO 0 or 1 + * \param[in] index Index offset in FIFO + */ +static inline void mcan_rx_fifo_acknowledge( + struct mcan_module *const module_inst, bool fifo_number, uint32_t index) +{ + if (!fifo_number) { + module_inst->hw->MCAN_RXF0A = MCAN_RXF0A_F0AI(index); + } else { + module_inst->hw->MCAN_RXF1A = MCAN_RXF1A_F1AI(index); + } +} + +/** + * \brief Get the standard message filter default value. + * + * The default configuration is as follows: + * \li Classic filter: SFID1 = filter, SFID2 = mask + * \li Store in Rx FIFO 0 if filter matches + * \li SFID2 = 0x7FFul + * \li SFID1 = 0x0ul + * + * \param[out] sd_filter Pointer to standard filter element struct to initialize to default values + */ +static inline void mcan_get_standard_message_filter_element_default( + struct mcan_standard_message_filter_element *sd_filter) +{ + sd_filter->S0.reg = MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID2_Msk | + MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID1(0) | + MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC( + MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_STF0M_Val) | + MCAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT_CLASSIC; +} + +enum status_code mcan_set_rx_standard_filter( + struct mcan_module *const module_inst, + struct mcan_standard_message_filter_element *sd_filter, uint32_t index); + +/** + * \brief Get the extended message filter default value. + * + * The default configuration is as follows: + * \li Classic filter: SFID1 = filter, SFID2 = mask + * \li Store in Rx FIFO 1 if filter matches + * \li SFID2 = 0x1FFFFFFFul + * \li SFID1 = 0x0ul + * + * \param[out] et_filter Pointer to extended filter element struct to initialize to default values + */ +static inline void mcan_get_extended_message_filter_element_default( + struct mcan_extended_message_filter_element *et_filter) +{ + et_filter->F0.reg = MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFID1(0) | + MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC( + MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_STF1M_Val); + et_filter->F1.reg = MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFID2_Msk | + MCAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_CLASSIC; +} + +enum status_code mcan_set_rx_extended_filter( + struct mcan_module *const module_inst, + struct mcan_extended_message_filter_element *et_filter, uint32_t index); + +enum status_code mcan_get_rx_buffer_element( + struct mcan_module *const module_inst, + struct mcan_rx_element_buffer *rx_element, uint32_t index); + +enum status_code mcan_get_rx_fifo_0_element( + struct mcan_module *const module_inst, + struct mcan_rx_element_fifo_0 *rx_element, uint32_t index); + +enum status_code mcan_get_rx_fifo_1_element( + struct mcan_module *const module_inst, + struct mcan_rx_element_fifo_1 *rx_element, uint32_t index); + +/** + * \brief Get Tx FIFO/Queue status. + * + * \param[in] module_inst Pointer to the MCAN software instance struct + * + * \return Tx FIFO/Queue status value. + */ +static inline uint32_t mcan_tx_get_fifo_queue_status( + struct mcan_module *const module_inst) +{ + return module_inst->hw->MCAN_TXFQS; +} + +/** + * \brief Get Tx buffer request pending status. + * + * \param[in] module_inst Pointer to the MCAN software instance struct + * + * \return Bit mask of Tx buffer request pending status value. + */ +static inline uint32_t mcan_tx_get_pending_status( + struct mcan_module *const module_inst) +{ + return module_inst->hw->MCAN_TXBRP; +} + +/** + * \brief Tx buffer add transfer request. + * + * \param[in] module_inst Pointer to the MCAN software instance struct + * \param[in] trig_mask The mask value to trigger transfer buffer + * + * \return Status of the result. + * + * \retval STATUS_OK Set the transfer request. + * \retval STATUS_ERR_BUSY The module is in configuration. + */ +static inline enum status_code mcan_tx_transfer_request( + struct mcan_module *const module_inst, uint32_t trig_mask) +{ + if (module_inst->hw->MCAN_CCCR & MCAN_CCCR_CCE) { + return ERR_BUSY; + } + module_inst->hw->MCAN_TXBAR = trig_mask; + return STATUS_OK; +} + +/** + * \brief Set Tx Queue operation. + * + * \param[in] module_inst Pointer to the MCAN software instance struct + * \param[in] trig_mask The mask value to cancel transfer buffer + * + * \return Status of the result. + * + * \retval STATUS_OK Set the transfer request. + * \retval STATUS_BUSY The module is in configuration. + */ +static inline enum status_code mcan_tx_cancel_request( + struct mcan_module *const module_inst, uint32_t trig_mask) +{ + if (module_inst->hw->MCAN_CCCR & MCAN_CCCR_CCE) { + return STATUS_ERR_BUSY; + } + module_inst->hw->MCAN_TXBCR = trig_mask; + return STATUS_OK; +} + +/** + * \brief Get Tx transmission status. + * + * \param[in] module_inst Pointer to the MCAN software instance struct + * + * \return Bit mask of Tx transmission status value. + */ +static inline uint32_t mcan_tx_get_transmission_status( + struct mcan_module *const module_inst) +{ + return module_inst->hw->MCAN_TXBTO; +} + +/** + * \brief Get Tx cancellation status. + * + * \param[in] module_inst Pointer to the MCAN software instance struct + * + * \return Bit mask of Tx cancellation status value. + */ +static inline uint32_t mcan_tx_get_cancellation_status( + struct mcan_module *const module_inst) +{ + return module_inst->hw->MCAN_TXBCF; +} + +/** + * \brief Get Tx event FIFO status. + * + * \param[in] module_inst Pointer to the MCAN software instance struct + * + * \return Tx event FIFO status value. + */ +static inline uint32_t mcan_tx_get_event_fifo_status( + struct mcan_module *const module_inst) +{ + return module_inst->hw->MCAN_TXEFS; +} + +/** + * \brief Set Tx Queue operation. + * + * \param[in] module_inst Pointer to the MCAN software instance struct + * \param[in] index Index for the transfer FIFO + */ +static inline void mcan_tx_event_fifo_acknowledge( + struct mcan_module *const module_inst, uint32_t index) +{ + module_inst->hw->MCAN_TXEFA = MCAN_TXEFA_EFAI(index); +} + +/** + * \brief Get the default transfer buffer element. + * + * The default configuration is as follows: + * \li 11-bit standard identifier + * \li Transmit data frame + * \li ID = 0x0ul + * \li Store Tx events + * \li Frame transmitted in Classic MCAN format + * \li Data Length Code is 8 + * + * \param[out] tx_element Pointer to transfer element struct to initialize to default values + */ +static inline void mcan_get_tx_buffer_element_defaults( + struct mcan_tx_element *tx_element) +{ + tx_element->T0.reg = 0; + tx_element->T1.reg = MCAN_TX_ELEMENT_T1_EFC | + MCAN_TX_ELEMENT_T1_DLC(MCAN_TX_ELEMENT_T1_DLC_DATA8_Val); +} + +enum status_code mcan_set_tx_buffer_element( + struct mcan_module *const module_inst, + struct mcan_tx_element *tx_element, uint32_t index); + +enum status_code mcan_get_tx_event_fifo_element( + struct mcan_module *const module_inst, + struct mcan_tx_event_element *tx_event_element, uint32_t index); + +/** + * \brief Can module interrupt source. + * + * Enum for the interrupt source. + */ +enum mcan_interrupt_source { + /** Rx FIFO 0 New Message Interrupt Enable. */ + MCAN_RX_FIFO_0_NEW_MESSAGE = MCAN_IE_RF0NE, + /** Rx FIFO 0 Watermark Reached Interrupt Enable. */ + MCAN_RX_FIFO_0_WATERMARK = MCAN_IE_RF0WE, + /** Rx FIFO 0 Full Interrupt Enable. */ + MCAN_RX_FIFO_0_FULL = MCAN_IE_RF0FE, + /** Rx FIFO 0 Message Lost Interrupt Enable. */ + MCAN_RX_FIFO_0_LOST_MESSAGE = MCAN_IE_RF0LE, + /** Rx FIFO 1 New Message Interrupt Enable. */ + MCAN_RX_FIFO_1_NEW_MESSAGE = MCAN_IE_RF1NE, + /** Rx FIFO 1 Watermark Reached Interrupt Enable. */ + MCAN_RX_FIFO_1_WATERMARK = MCAN_IE_RF1WE, + /** Rx FIFO 1 Full Interrupt Enable. */ + MCAN_RX_FIFO_1_FULL = MCAN_IE_RF1FE, + /** Rx FIFO 1 Message Lost Interrupt Enable. */ + MCAN_RX_FIFO_1_MESSAGE_LOST = MCAN_IE_RF1LE, + /** High Priority Message Interrupt Enable. */ + MCAN_RX_HIGH_PRIORITY_MESSAGE = MCAN_IE_HPME, + /** Transmission Completed Interrupt Enable. */ + MCAN_TIMESTAMP_COMPLETE = MCAN_IE_TCE, + /** Transmission Cancellation Finished Interrupt Enable. */ + MCAN_TX_CANCELLATION_FINISH = MCAN_IE_TCFE, + /** Tx FIFO Empty Interrupt Enable. */ + MCAN_TX_FIFO_EMPTY = MCAN_IE_TFEE, + /** Tx Event FIFO New Entry Interrupt Enable. */ + MCAN_TX_EVENT_FIFO_NEW_ENTRY = MCAN_IE_TEFNE, + /** Tx Event FIFO Watermark Reached Interrupt Enable. */ + MCAN_TX_EVENT_FIFO_WATERMARK = MCAN_IE_TEFWE, + /** Tx Event FIFO Full Interrupt Enable. */ + MCAN_TX_EVENT_FIFO_FULL = MCAN_IE_TEFFE, + /** Tx Event FIFO Element Lost Interrupt Enable. */ + MCAN_TX_EVENT_FIFO_ELEMENT_LOST = MCAN_IE_TEFLE, + /** Timestamp Wraparound Interrupt Enable. */ + MCAN_TIMESTAMP_WRAPAROUND = MCAN_IE_TSWE, + /** Message RAM Access Failure Interrupt Enable. */ + MCAN_MESSAGE_RAM_ACCESS_FAILURE = MCAN_IE_MRAFE, + /** Timeout Occurred Interrupt Enable. */ + MCAN_TIMEOUT_OCCURRED = MCAN_IE_TOOE, + /** Message stored to Dedicated Rx Buffer Interrupt Enable. */ + MCAN_RX_BUFFER_NEW_MESSAGE = MCAN_IE_DRXE, + /** Error Logging Overflow Interrupt Enable. */ + MCAN_ERROR_LOGGING_OVERFLOW = MCAN_IE_ELOE, + /** Error Passive Interrupt Enable. */ + MCAN_ERROR_PASSIVE = MCAN_IE_EPE, + /** Warning Status Interrupt Enable. */ + MCAN_WARNING_STATUS = MCAN_IE_EWE, + /** Bus_Off Status Interrupt Enable. */ + MCAN_BUS_OFF = MCAN_IE_BOE, + /** Watchdog Interrupt Enable. */ + MCAN_WATCHDOG = MCAN_IE_WDIE, + /**CRC Error Interrupt Enable */ + MCAN_CRC_ERROR = MCAN_IE_CRCEE, + /** Bit Error Interrupt Enable. */ + MCAN_BIT_ERROR = MCAN_IE_BEE, + /** Acknowledge Error Interrupt Enable . */ + MCAN_ACKNOWLEDGE_ERROR = MCAN_IE_ACKEE, + /** Format Error Interrupt Enable */ + MCAN_FORMAT_ERROR = MCAN_IE_FOEE, + /** Stuff Error Interrupt Enable */ + MCAN_STUFF_ERROR = MCAN_IE_STEE +}; + +/** + * \brief Enable MCAN interrupt. + * + * \param[in] module_inst Pointer to the MCAN software instance struct + * \param[in] source Interrupt source type + */ +static inline void mcan_enable_interrupt(struct mcan_module *const module_inst, + const enum mcan_interrupt_source source) +{ + module_inst->hw->MCAN_IE |= source; +} + +/** + * \brief Disable MCAN interrupt. + * + * \param[in] module_inst Pointer to the MCAN software instance struct + * \param[in] source Interrupt source type + */ +static inline void mcan_disable_interrupt(struct mcan_module *const module_inst, + const enum mcan_interrupt_source source) +{ + module_inst->hw->MCAN_IE &= ~source; +} + +/** + * \brief Get MCAN interrupt status. + * + * \param[in] module_inst Pointer to the MCAN software instance struct + */ +static inline uint32_t mcan_read_interrupt_status( + struct mcan_module *const module_inst) +{ + return module_inst->hw->MCAN_IR; +} + +/** + * \brief Clear MCAN interrupt status. + * + * \param[in] module_inst Pointer to the MCAN software instance struct + * \param[in] source Interrupt source type + * + * \return Bit mask of interrupt status value. + */ +static inline void mcan_clear_interrupt_status( + struct mcan_module *const module_inst, + const enum mcan_interrupt_source source) +{ + module_inst->hw->MCAN_IR = source; +} + +/** @} */ + + + +#ifdef __cplusplus +} +#endif + +/** @} */ + +/** + * \page asfdoc_sam_mcan_exqsg Examples for MCAN Driver + * + * This is a list of the available Quick Start guides (QSGs) and example + * applications for \ref asfdoc_sam_mcan_group. QSGs are simple examples with + * step-by-step instructions to configure and use this driver in a selection of + * use cases. Note that a QSG can be compiled as a standalone application or be + * added to the user application. + * + * - \subpage asfdoc_sam_mcan_module_overview + * + */ + +#endif /* CAN_H_INCLUDED */ + diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/mpu/mpu.c b/hw-libs/drivers/SAMx70/ASF/sam/drivers/mpu/mpu.c new file mode 100644 index 000000000..75cefa3bc --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/mpu/mpu.c @@ -0,0 +1,178 @@ +/** + * \file + * + * \brief SAMV70/SAMV71/SAME70/SAMS70-XULTRA board mpu config. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "mpu.h" + +/** + * \defgroup sam_drivers_mpu_group MPU - Memory Protect Unit + * @{ + */ + +/** \file */ + +/** + * \addtogroup mmu MMU Initialization + * + * \section Usage + * + * Translation Look-aside Buffers (TLBs) are an implementation technique that + * caches translations or translation table entries. TLBs avoid the requirement + * for every memory access to perform a translation table lookup. + * The ARM architecture does not specify the exact form of the TLB structures + * for any design. In a similar way to the requirements for caches, the + * architecture only defines certain principles for TLBs: + * + * The MMU supports memory accesses based on memory sections or pages: + * Super-sections Consist of 16MB blocks of memory. Support for Super sections + * is optional. + * -# Sections Consist of 1MB blocks of memory. + * -# Large pages Consist of 64KB blocks of memory. + * -# Small pages Consist of 4KB blocks of memory. + * + * Access to a memory region is controlled by the access permission bits and + * the domain field in the TLB entry. + * Memory region attributes + * Each TLB entry has an associated set of memory region attributes. These + * control accesses to the caches, + * how the write buffer is used, and if the memory region is Shareable and + * therefore must be kept coherent. + * + * Related files:\n + * \ref mmu.c\n + * \ref mmu.h \n + */ + +/*---------------------------------------------------------------------------- + * Exported functions + + *----------------------------------------------------------------------------*/ +/** + * \brief Enables the MPU module. + * + * \param dwMPUEnable Enable/Disable the memory region. + */ +void mpu_enable(uint32_t dw_mpu_enable) +{ + MPU->CTRL = dw_mpu_enable ; +} + +/** + * \brief Set active memory region. + * + * \param dwRegionNum The memory region to be active. + */ +void mpu_set_region_num(uint32_t dw_region_num) +{ + MPU->RNR = dw_region_num; +} + +/** + * \brief Disable the current active region. + */ +void mpu_disable_region(void) +{ + MPU->RASR &= 0xfffffffe; +} + +/** + * \brief Setup a memory region. + * + * \param dwRegionBaseAddr Memory region base address. + * \param dwRegionAttr Memory region attributes. + */ +void mpu_set_region(uint32_t dw_region_base_addr, uint32_t dw_region_attr) +{ + MPU->RBAR = dw_region_base_addr; + MPU->RASR = dw_region_attr; +} + + +/** + * \brief Calculate region size for the RASR. + */ +uint32_t mpu_cal_mpu_region_size(uint32_t dw_actual_size_in_bytes) +{ + uint32_t dwRegionSize = 32; + uint32_t dwReturnValue = 4; + + while( dwReturnValue < 31 ) { + if( dw_actual_size_in_bytes <= dwRegionSize ) { + break; + } else { + dwReturnValue++; + } + dwRegionSize <<= 1; + } + + return ( dwReturnValue << 1 ); +} + + +/** + * \brief Update MPU regions. + * + * \return Unused (ANSI-C compatibility). + */ +void mpu_update_regions(uint32_t dw_region_num, uint32_t dw_region_base_addr, uint32_t dw_region_attr) +{ + volatile irqflags_t flags; + + /* Get and clear the global interrupt flags */ + flags = cpu_irq_save(); + + /* Clean up data and instruction buffer */ + __DSB(); + __ISB(); + + /* Set active region */ + mpu_set_region_num(dw_region_num); + + /* Disable region */ + mpu_disable_region(); + + /* Update region attribute */ + mpu_set_region( dw_region_base_addr, dw_region_attr); + + /* Clean up data and instruction buffer to make the new region taking + effect at once */ + __DSB(); + __ISB(); + + /* Restore global interrupt flags */ + cpu_irq_restore(flags); +} + +//@} diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/mpu/mpu.h b/hw-libs/drivers/SAMx70/ASF/sam/drivers/mpu/mpu.h new file mode 100644 index 000000000..7cc5758f7 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/mpu/mpu.h @@ -0,0 +1,189 @@ +/** + * \file + * + * \brief SAMV70/SAMV71/SAME70/SAMS70-XULTRA board mpu config. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + + +#ifndef _MPU_H_ +#define _MPU_H_ + +#include "compiler.h" + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ +#define ARM_MODE_USR 0x10 + +#define PRIVILEGE_MODE 0 +#define USER_MODE 1 + +#define MPU_DEFAULT_ITCM_REGION ( 1 ) +#define MPU_DEFAULT_IFLASH_REGION ( 2 ) +#define MPU_DEFAULT_DTCM_REGION ( 3 ) +#define MPU_DEFAULT_SRAM_REGION_1 ( 4 ) +#define MPU_DEFAULT_SRAM_REGION_2 ( 5 ) +#define MPU_PERIPHERALS_REGION ( 6 ) +#define MPU_EXT_EBI_REGION ( 7 ) +#define MPU_DEFAULT_SDRAM_REGION ( 8 ) +#define MPU_QSPIMEM_REGION ( 9 ) +#define MPU_USBHSRAM_REGION ( 10 ) +#if defined MPU_HAS_NOCACHE_REGION +#define MPU_NOCACHE_SRAM_REGION ( 11 ) +#endif + +#define MPU_REGION_VALID ( 0x10 ) +#define MPU_REGION_ENABLE ( 0x01 ) +#define MPU_REGION_DISABLE ( 0x0 ) + +#define MPU_ENABLE ( 0x1 << MPU_CTRL_ENABLE_Pos) +#define MPU_HFNMIENA ( 0x1 << MPU_CTRL_HFNMIENA_Pos ) +#define MPU_PRIVDEFENA ( 0x1 << MPU_CTRL_PRIVDEFENA_Pos ) + + +#define MPU_REGION_BUFFERABLE ( 0x01 << MPU_RASR_B_Pos ) +#define MPU_REGION_CACHEABLE ( 0x01 << MPU_RASR_C_Pos ) +#define MPU_REGION_SHAREABLE ( 0x01 << MPU_RASR_S_Pos ) + +#define MPU_REGION_EXECUTE_NEVER ( 0x01 << MPU_RASR_XN_Pos ) + +#define MPU_AP_NO_ACCESS ( 0x00 << MPU_RASR_AP_Pos ) +#define MPU_AP_PRIVILEGED_READ_WRITE ( 0x01 << MPU_RASR_AP_Pos ) +#define MPU_AP_UNPRIVILEGED_READONLY ( 0x02 << MPU_RASR_AP_Pos ) +#define MPU_AP_FULL_ACCESS ( 0x03 << MPU_RASR_AP_Pos ) +#define MPU_AP_RES ( 0x04 << MPU_RASR_AP_Pos ) +#define MPU_AP_PRIVILEGED_READONLY ( 0x05 << MPU_RASR_AP_Pos ) +#define MPU_AP_READONLY ( 0x06 << MPU_RASR_AP_Pos ) +#define MPU_AP_READONLY2 ( 0x07 << MPU_RASR_AP_Pos ) + +#define MPU_TEX_B000 ( 0x01 << MPU_RASR_TEX_Pos ) +#define MPU_TEX_B001 ( 0x01 << MPU_RASR_TEX_Pos ) +#define MPU_TEX_B010 ( 0x01 << MPU_RASR_TEX_Pos ) +#define MPU_TEX_B011 ( 0x01 << MPU_RASR_TEX_Pos ) +#define MPU_TEX_B100 ( 0x01 << MPU_RASR_TEX_Pos ) +#define MPU_TEX_B101 ( 0x01 << MPU_RASR_TEX_Pos ) +#define MPU_TEX_B110 ( 0x01 << MPU_RASR_TEX_Pos ) +#define MPU_TEX_B111 ( 0x01 << MPU_RASR_TEX_Pos ) + +#define SHAREABLE 1 +#define NON_SHAREABLE 0 + +#define INNER_NORMAL_WB_RWA_TYPE(x) (( 0x04 << MPU_RASR_TEX_Pos ) | ( DISABLE << MPU_RASR_C_Pos ) | ( ENABLE << MPU_RASR_B_Pos ) | ( x << MPU_RASR_S_Pos )) +#define INNER_NORMAL_WB_NWA_TYPE(x) (( 0x04 << MPU_RASR_TEX_Pos ) | ( ENABLE << MPU_RASR_C_Pos ) | ( ENABLE << MPU_RASR_B_Pos ) | ( x << MPU_RASR_S_Pos )) +#define STRONGLY_ORDERED_SHAREABLE_TYPE (( 0x00 << MPU_RASR_TEX_Pos ) | ( DISABLE << MPU_RASR_C_Pos ) | ( DISABLE << MPU_RASR_B_Pos )) // DO not care // +#define SHAREABLE_DEVICE_TYPE (( 0x00 << MPU_RASR_TEX_Pos ) | ( DISABLE << MPU_RASR_C_Pos ) | ( ENABLE << MPU_RASR_B_Pos )) // DO not care // + + +/* Default memory map + Address range Memory region Memory type Shareability Cache policy + 0x00000000- 0x1FFFFFFF Code Normal Non-shareable WT + 0x20000000- 0x3FFFFFFF SRAM Normal Non-shareable WBWA + 0x40000000- 0x5FFFFFFF Peripheral Device Non-shareable - + 0x60000000- 0x7FFFFFFF RAM Normal Non-shareable WBWA + 0x80000000- 0x9FFFFFFF RAM Normal Non-shareable WT + 0xA0000000- 0xBFFFFFFF Device Device Shareable + 0xC0000000- 0xDFFFFFFF Device Device Non Shareable + 0xE0000000- 0xFFFFFFFF System - - + */ + +/********* IFLASH memory macros *********************/ +#define ITCM_START_ADDRESS 0x00000000UL +#define ITCM_END_ADDRESS 0x003FFFFFUL +#define IFLASH_START_ADDRESS 0x00400000UL +#define IFLASH_END_ADDRESS 0x005FFFFFUL + + +#define IFLASH_PRIVILEGE_START_ADDRESS (IFLASH_START_ADDRESS) +#define IFLASH_PRIVILEGE_END_ADDRESS (IFLASH_START_ADDRESS + 0xFFF) + +#define IFLASH_UNPRIVILEGE_START_ADDRESS (IFLASH_PRIVILEGE_END_ADDRESS + 1) +#define IFLASH_UNPRIVILEGE_END_ADDRESS (IFLASH_END_ADDRESS) + +/**************** DTCM *******************************/ +#define DTCM_START_ADDRESS 0x20000000UL +#define DTCM_END_ADDRESS 0x203FFFFFUL + + +/******* SRAM memory macros ***************************/ + +#define SRAM_START_ADDRESS 0x20400000UL +#define SRAM_END_ADDRESS 0x2045FFFFUL + +#if defined MPU_HAS_NOCACHE_REGION +#define NOCACHE_SRAM_REGION_SIZE 0x1000 +#endif + +/* Regions should be a 2^(N+1) where 4 < N < 31 */ +#define SRAM_FIRST_START_ADDRESS (SRAM_START_ADDRESS) +#define SRAM_FIRST_END_ADDRESS (SRAM_FIRST_START_ADDRESS + 0x3FFFF) // (2^18) 256 KB + +#if defined MPU_HAS_NOCACHE_REGION +#define SRAM_SECOND_START_ADDRESS (SRAM_FIRST_END_ADDRESS+1) +#define SRAM_SECOND_END_ADDRESS (SRAM_END_ADDRESS - NOCACHE_SRAM_REGION_SIZE ) // (2^17) 128 - 0x1000 KB +#define SRAM_NOCACHE_START_ADDRESS (SRAM_SECOND_END_ADDRESS + 1) +#define SRAM_NOCACHE_END_ADDRESS (SRAM_END_ADDRESS ) +#else +#define SRAM_SECOND_START_ADDRESS (SRAM_FIRST_END_ADDRESS + 1) +#define SRAM_SECOND_END_ADDRESS (SRAM_END_ADDRESS) // (2^17) 128 KB +#endif +/************** Peripherals memory region macros ********/ +#define PERIPHERALS_START_ADDRESS 0x40000000UL +#define PERIPHERALS_END_ADDRESS 0x5FFFFFFFUL + +/******* Ext EBI memory macros ***************************/ +#define EXT_EBI_START_ADDRESS 0x60000000UL +#define EXT_EBI_END_ADDRESS 0x6FFFFFFFUL + +/******* Ext-SRAM memory macros ***************************/ +#define SDRAM_START_ADDRESS 0x70000000UL +#define SDRAM_END_ADDRESS 0x7FFFFFFFUL + +/******* QSPI macros ***************************/ +#define QSPI_START_ADDRESS 0x80000000UL +#define QSPI_END_ADDRESS 0x9FFFFFFFUL + +/************** USBHS_RAM region macros ******************/ +#define USBHSRAM_START_ADDRESS 0xA0100000UL +#define USBHSRAM_END_ADDRESS 0xA01FFFFFUL + +/*---------------------------------------------------------------------------- + * Export functions + *----------------------------------------------------------------------------*/ +void mpu_enable(uint32_t dw_mpu_enable); +void mpu_set_region(uint32_t dw_region_base_addr, uint32_t dw_region_attr); +void mpu_set_region_num(uint32_t dw_region_num); +void mpu_disable_region(void); +uint32_t mpu_cal_mpu_region_size(uint32_t dw_actual_size_in_bytes); +void mpu_update_regions(uint32_t dw_region_num, uint32_t dw_region_base_addr, uint32_t dw_region_attr); + +#endif /* #ifndef _MPU_H_ */ \ No newline at end of file diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/pio/pio.c b/hw-libs/drivers/SAMx70/ASF/sam/drivers/pio/pio.c new file mode 100644 index 000000000..a9983cedb --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/pio/pio.c @@ -0,0 +1,1173 @@ +/** + * \file + * + * \brief Parallel Input/Output (PIO) Controller driver for SAM. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "pio.h" + +#ifndef PIO_WPMR_WPKEY_PASSWD +# define PIO_WPMR_WPKEY_PASSWD PIO_WPMR_WPKEY(0x50494Fu) +#endif + +/** + * \defgroup sam_drivers_pio_group Peripheral Parallel Input/Output (PIO) Controller + * + * \par Purpose + * + * The Parallel Input/Output Controller (PIO) manages up to 32 fully + * programmable input/output lines. Each I/O line may be dedicated as a + * general-purpose I/O or be assigned to a function of an embedded peripheral. + * This assures effective optimization of the pins of a product. + * + * @{ + */ + +#ifndef FREQ_SLOW_CLOCK_EXT +/* External slow clock frequency (hz) */ +#define FREQ_SLOW_CLOCK_EXT 32768 +#endif + +/** + * \brief Configure PIO internal pull-up. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + * \param ul_pull_up_enable Indicates if the pin(s) internal pull-up shall be + * configured. + */ +void pio_pull_up(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_pull_up_enable) +{ + /* Enable the pull-up(s) if necessary */ + if (ul_pull_up_enable) { + p_pio->PIO_PUER = ul_mask; + } else { + p_pio->PIO_PUDR = ul_mask; + } +} + +/** + * \brief Configure Glitch or Debouncing filter for the specified input(s). + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + * \param ul_cut_off Cuts off frequency for debouncing filter. + */ +void pio_set_debounce_filter(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_cut_off) +{ +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) + /* Set Debouncing, 0 bit field no effect */ + p_pio->PIO_IFSCER = ul_mask; +#elif (SAM3XA || SAM3U) + /* Set Debouncing, 0 bit field no effect */ + p_pio->PIO_DIFSR = ul_mask; +#else +#error "Unsupported device" +#endif + + /* + * The debouncing filter can filter a pulse of less than 1/2 Period of a + * programmable Divided Slow Clock: + * Tdiv_slclk = ((DIV+1)*2).Tslow_clock + */ + p_pio->PIO_SCDR = PIO_SCDR_DIV((FREQ_SLOW_CLOCK_EXT / + (2 * (ul_cut_off))) - 1); +} + +/** + * \brief Set a high output level on all the PIOs defined in ul_mask. + * This has no immediate effects on PIOs that are not output, but the PIO + * controller will save the value if they are changed to outputs. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + */ +void pio_set(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_SODR = ul_mask; +} + +/** + * \brief Set a low output level on all the PIOs defined in ul_mask. + * This has no immediate effects on PIOs that are not output, but the PIO + * controller will save the value if they are changed to outputs. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + */ +void pio_clear(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_CODR = ul_mask; +} + +/** + * \brief Return 1 if one or more PIOs of the given Pin instance currently have + * a high level; otherwise returns 0. This method returns the actual value that + * is being read on the pin. To return the supposed output value of a pin, use + * pio_get_output_data_status() instead. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_type PIO type. + * \param ul_mask Bitmask of one or more pin(s) to configure. + * + * \retval 1 at least one PIO currently has a high level. + * \retval 0 all PIOs have a low level. + */ +uint32_t pio_get(Pio *p_pio, const pio_type_t ul_type, + const uint32_t ul_mask) +{ + uint32_t ul_reg; + + if ((ul_type == PIO_OUTPUT_0) || (ul_type == PIO_OUTPUT_1)) { + ul_reg = p_pio->PIO_ODSR; + } else { + ul_reg = p_pio->PIO_PDSR; + } + + if ((ul_reg & ul_mask) == 0) { + return 0; + } else { + return 1; + } +} + +/** + * \brief Configure IO of a PIO controller as being controlled by a specific + * peripheral. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_type PIO type. + * \param ul_mask Bitmask of one or more pin(s) to configure. + */ +void pio_set_peripheral(Pio *p_pio, const pio_type_t ul_type, + const uint32_t ul_mask) +{ + uint32_t ul_sr; + + /* Disable interrupts on the pin(s) */ + p_pio->PIO_IDR = ul_mask; + +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) + switch (ul_type) { + case PIO_PERIPH_A: + ul_sr = p_pio->PIO_ABCDSR[0]; + p_pio->PIO_ABCDSR[0] &= (~ul_mask & ul_sr); + + ul_sr = p_pio->PIO_ABCDSR[1]; + p_pio->PIO_ABCDSR[1] &= (~ul_mask & ul_sr); + break; + case PIO_PERIPH_B: + ul_sr = p_pio->PIO_ABCDSR[0]; + p_pio->PIO_ABCDSR[0] = (ul_mask | ul_sr); + + ul_sr = p_pio->PIO_ABCDSR[1]; + p_pio->PIO_ABCDSR[1] &= (~ul_mask & ul_sr); + break; +#if (!SAMG) + case PIO_PERIPH_C: + ul_sr = p_pio->PIO_ABCDSR[0]; + p_pio->PIO_ABCDSR[0] &= (~ul_mask & ul_sr); + + ul_sr = p_pio->PIO_ABCDSR[1]; + p_pio->PIO_ABCDSR[1] = (ul_mask | ul_sr); + break; + case PIO_PERIPH_D: + ul_sr = p_pio->PIO_ABCDSR[0]; + p_pio->PIO_ABCDSR[0] = (ul_mask | ul_sr); + + ul_sr = p_pio->PIO_ABCDSR[1]; + p_pio->PIO_ABCDSR[1] = (ul_mask | ul_sr); + break; +#endif + /* Other types are invalid in this function */ + case PIO_INPUT: + case PIO_OUTPUT_0: + case PIO_OUTPUT_1: + case PIO_NOT_A_PIN: + return; + } +#elif (SAM3XA|| SAM3U) + switch (ul_type) { + case PIO_PERIPH_A: + ul_sr = p_pio->PIO_ABSR; + p_pio->PIO_ABSR &= (~ul_mask & ul_sr); + break; + + case PIO_PERIPH_B: + ul_sr = p_pio->PIO_ABSR; + p_pio->PIO_ABSR = (ul_mask | ul_sr); + break; + + // other types are invalid in this function + case PIO_INPUT: + case PIO_OUTPUT_0: + case PIO_OUTPUT_1: + case PIO_NOT_A_PIN: + return; + } +#else +#error "Unsupported device" +#endif + + /* Remove the pins from under the control of PIO */ + p_pio->PIO_PDR = ul_mask; +} + +/** + * \brief Configure one or more pin(s) or a PIO controller as inputs. + * Optionally, the corresponding internal pull-up(s) and glitch filter(s) can + * be enabled. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask indicating which pin(s) to configure as input(s). + * \param ul_attribute PIO attribute(s). + */ +void pio_set_input(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_attribute) +{ + pio_disable_interrupt(p_pio, ul_mask); + pio_pull_up(p_pio, ul_mask, ul_attribute & PIO_PULLUP); + + /* Enable Input Filter if necessary */ + if (ul_attribute & (PIO_DEGLITCH | PIO_DEBOUNCE)) { + p_pio->PIO_IFER = ul_mask; + } else { + p_pio->PIO_IFDR = ul_mask; + } + +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) + /* Enable de-glitch or de-bounce if necessary */ + if (ul_attribute & PIO_DEGLITCH) { + p_pio->PIO_IFSCDR = ul_mask; + } else { + if (ul_attribute & PIO_DEBOUNCE) { + p_pio->PIO_IFSCER = ul_mask; + } + } +#elif (SAM3XA|| SAM3U) + /* Enable de-glitch or de-bounce if necessary */ + if (ul_attribute & PIO_DEGLITCH) { + p_pio->PIO_SCIFSR = ul_mask; + } else { + if (ul_attribute & PIO_DEBOUNCE) { + p_pio->PIO_DIFSR = ul_mask; + } + } +#else +#error "Unsupported device" +#endif + + /* Configure pin as input */ + p_pio->PIO_ODR = ul_mask; + p_pio->PIO_PER = ul_mask; +} + +/** + * \brief Configure one or more pin(s) of a PIO controller as outputs, with + * the given default value. Optionally, the multi-drive feature can be enabled + * on the pin(s). + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask indicating which pin(s) to configure. + * \param ul_default_level Default level on the pin(s). + * \param ul_multidrive_enable Indicates if the pin(s) shall be configured as + * open-drain. + * \param ul_pull_up_enable Indicates if the pin shall have its pull-up + * activated. + */ +void pio_set_output(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_default_level, + const uint32_t ul_multidrive_enable, + const uint32_t ul_pull_up_enable) +{ + pio_disable_interrupt(p_pio, ul_mask); + pio_pull_up(p_pio, ul_mask, ul_pull_up_enable); + + /* Enable multi-drive if necessary */ + if (ul_multidrive_enable) { + p_pio->PIO_MDER = ul_mask; + } else { + p_pio->PIO_MDDR = ul_mask; + } + + /* Set default value */ + if (ul_default_level) { + p_pio->PIO_SODR = ul_mask; + } else { + p_pio->PIO_CODR = ul_mask; + } + + /* Configure pin(s) as output(s) */ + p_pio->PIO_OER = ul_mask; + p_pio->PIO_PER = ul_mask; +} + +/** + * \brief Perform complete pin(s) configuration; general attributes and PIO init + * if necessary. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_type PIO type. + * \param ul_mask Bitmask of one or more pin(s) to configure. + * \param ul_attribute Pins attributes. + * + * \return Whether the pin(s) have been configured properly. + */ +uint32_t pio_configure(Pio *p_pio, const pio_type_t ul_type, + const uint32_t ul_mask, const uint32_t ul_attribute) +{ + /* Configure pins */ + switch (ul_type) { + case PIO_PERIPH_A: + case PIO_PERIPH_B: +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) + case PIO_PERIPH_C: + case PIO_PERIPH_D: +#endif + pio_set_peripheral(p_pio, ul_type, ul_mask); + pio_pull_up(p_pio, ul_mask, (ul_attribute & PIO_PULLUP)); + break; + + case PIO_INPUT: + pio_set_input(p_pio, ul_mask, ul_attribute); + break; + + case PIO_OUTPUT_0: + case PIO_OUTPUT_1: + pio_set_output(p_pio, ul_mask, (ul_type == PIO_OUTPUT_1), + (ul_attribute & PIO_OPENDRAIN) ? 1 : 0, + (ul_attribute & PIO_PULLUP) ? 1 : 0); + break; + + default: + return 0; + } + + return 1; +} + +/** + * \brief Return 1 if one or more PIOs of the given Pin are configured to + * output a high level (even if they are not output). + * To get the actual value of the pin, use PIO_Get() instead. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s). + * + * \retval 1 At least one PIO is configured to output a high level. + * \retval 0 All PIOs are configured to output a low level. + */ +uint32_t pio_get_output_data_status(const Pio *p_pio, + const uint32_t ul_mask) +{ + if ((p_pio->PIO_ODSR & ul_mask) == 0) { + return 0; + } else { + return 1; + } +} + +/** + * \brief Configure PIO pin multi-driver. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + * \param ul_multi_driver_enable Indicates if the pin(s) multi-driver shall be + * configured. + */ +void pio_set_multi_driver(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_multi_driver_enable) +{ + /* Enable the multi-driver if necessary */ + if (ul_multi_driver_enable) { + p_pio->PIO_MDER = ul_mask; + } else { + p_pio->PIO_MDDR = ul_mask; + } +} + +/** + * \brief Get multi-driver status. + * + * \param p_pio Pointer to a PIO instance. + * + * \return The multi-driver mask value. + */ +uint32_t pio_get_multi_driver_status(const Pio *p_pio) +{ + return p_pio->PIO_MDSR; +} + + +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Configure PIO pin internal pull-down. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + * \param ul_pull_down_enable Indicates if the pin(s) internal pull-down shall + * be configured. + */ +void pio_pull_down(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_pull_down_enable) +{ + /* Enable the pull-down if necessary */ + if (ul_pull_down_enable) { + p_pio->PIO_PPDER = ul_mask; + } else { + p_pio->PIO_PPDDR = ul_mask; + } +} +#endif + +/** + * \brief Enable PIO output write for synchronous data output. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + */ +void pio_enable_output_write(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_OWER = ul_mask; +} + +/** + * \brief Disable PIO output write. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + */ +void pio_disable_output_write(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_OWDR = ul_mask; +} + +/** + * \brief Read PIO output write status. + * + * \param p_pio Pointer to a PIO instance. + * + * \return The output write mask value. + */ +uint32_t pio_get_output_write_status(const Pio *p_pio) +{ + return p_pio->PIO_OWSR; +} + +/** + * \brief Synchronously write on output pins. + * \note Only bits unmasked by PIO_OWSR (Output Write Status Register) are + * written. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + */ +void pio_sync_output_write(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_ODSR = ul_mask; +} + +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Configure PIO pin schmitt trigger. By default the Schmitt trigger is + * active. + * Disabling the Schmitt Trigger is requested when using the QTouch Library. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + */ +void pio_set_schmitt_trigger(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_SCHMITT = ul_mask; +} + +/** + * \brief Get PIO pin schmitt trigger status. + * + * \param p_pio Pointer to a PIO instance. + * + * \return The schmitt trigger mask value. + */ +uint32_t pio_get_schmitt_trigger(const Pio *p_pio) +{ + return p_pio->PIO_SCHMITT; +} +#endif + +/** + * \brief Configure the given interrupt source. + * Interrupt can be configured to trigger on rising edge, falling edge, + * high level, low level or simply on level change. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Interrupt source bit map. + * \param ul_attr Interrupt source attributes. + */ +void pio_configure_interrupt(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_attr) +{ + /* Configure additional interrupt mode registers. */ + if (ul_attr & PIO_IT_AIME) { + /* Enable additional interrupt mode. */ + p_pio->PIO_AIMER = ul_mask; + + /* If bit field of the selected pin is 1, set as + Rising Edge/High level detection event. */ + if (ul_attr & PIO_IT_RE_OR_HL) { + /* Rising Edge or High Level */ + p_pio->PIO_REHLSR = ul_mask; + } else { + /* Falling Edge or Low Level */ + p_pio->PIO_FELLSR = ul_mask; + } + + /* If bit field of the selected pin is 1, set as + edge detection source. */ + if (ul_attr & PIO_IT_EDGE) { + /* Edge select */ + p_pio->PIO_ESR = ul_mask; + } else { + /* Level select */ + p_pio->PIO_LSR = ul_mask; + } + } else { + /* Disable additional interrupt mode. */ + p_pio->PIO_AIMDR = ul_mask; + } +} + +/** + * \brief Enable the given interrupt source. + * The PIO must be configured as an NVIC interrupt source as well. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Interrupt sources bit map. + */ +void pio_enable_interrupt(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_IER = ul_mask; +} + +/** + * \brief Disable a given interrupt source, with no added side effects. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Interrupt sources bit map. + */ +void pio_disable_interrupt(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_IDR = ul_mask; +} + +/** + * \brief Read and clear PIO interrupt status. + * + * \param p_pio Pointer to a PIO instance. + * + * \return The interrupt status value. + */ +uint32_t pio_get_interrupt_status(const Pio *p_pio) +{ + return p_pio->PIO_ISR; +} + +/** + * \brief Read PIO interrupt mask. + * + * \param p_pio Pointer to a PIO instance. + * + * \return The interrupt mask value. + */ +uint32_t pio_get_interrupt_mask(const Pio *p_pio) +{ + return p_pio->PIO_IMR; +} + +/** + * \brief Set additional interrupt mode. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Interrupt sources bit map. + * \param ul_attribute Pin(s) attributes. + */ +void pio_set_additional_interrupt_mode(Pio *p_pio, + const uint32_t ul_mask, const uint32_t ul_attribute) +{ + /* Enables additional interrupt mode if needed */ + if (ul_attribute & PIO_IT_AIME) { + /* Enables additional interrupt mode */ + p_pio->PIO_AIMER = ul_mask; + + /* Configures the Polarity of the event detection */ + /* (Rising/Falling Edge or High/Low Level) */ + if (ul_attribute & PIO_IT_RE_OR_HL) { + /* Rising Edge or High Level */ + p_pio->PIO_REHLSR = ul_mask; + } else { + /* Falling Edge or Low Level */ + p_pio->PIO_FELLSR = ul_mask; + } + + /* Configures the type of event detection (Edge or Level) */ + if (ul_attribute & PIO_IT_EDGE) { + /* Edge select */ + p_pio->PIO_ESR = ul_mask; + } else { + /* Level select */ + p_pio->PIO_LSR = ul_mask; + } + } else { + /* Disable additional interrupt mode */ + p_pio->PIO_AIMDR = ul_mask; + } +} + +#ifndef PIO_WPMR_WPKEY_PASSWD +#define PIO_WPMR_WPKEY_PASSWD PIO_WPMR_WPKEY(0x50494FU) +#endif + +/** + * \brief Enable or disable write protect of PIO registers. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_enable 1 to enable, 0 to disable. + */ +void pio_set_writeprotect(Pio *p_pio, const uint32_t ul_enable) +{ + p_pio->PIO_WPMR = PIO_WPMR_WPKEY_PASSWD | (ul_enable & PIO_WPMR_WPEN); +} + +/** + * \brief Read write protect status. + * + * \param p_pio Pointer to a PIO instance. + * + * \return Return write protect status. + */ +uint32_t pio_get_writeprotect_status(const Pio *p_pio) +{ + return p_pio->PIO_WPSR; +} + +/** + * \brief Return the value of a pin. + * + * \param ul_pin The pin number. + * + * \return The pin value. + * + * \note If pin is output: a pull-up or pull-down could hide the actual value. + * The function \ref pio_get can be called to get the actual pin output + * level. + * \note If pin is input: PIOx must be clocked to sample the signal. + * See PMC driver. + */ +uint32_t pio_get_pin_value(uint32_t ul_pin) +{ + Pio *p_pio = pio_get_pin_group(ul_pin); + + return (p_pio->PIO_PDSR >> (ul_pin & 0x1F)) & 1; +} + +/** + * \brief Drive a GPIO pin to 1. + * + * \param ul_pin The pin index. + * + * \note The function \ref pio_configure_pin must be called beforehand. + */ +void pio_set_pin_high(uint32_t ul_pin) +{ + Pio *p_pio = pio_get_pin_group(ul_pin); + + /* Value to be driven on the I/O line: 1. */ + p_pio->PIO_SODR = 1 << (ul_pin & 0x1F); +} + +/** + * \brief Drive a GPIO pin to 0. + * + * \param ul_pin The pin index. + * + * \note The function \ref pio_configure_pin must be called before. + */ +void pio_set_pin_low(uint32_t ul_pin) +{ + Pio *p_pio = pio_get_pin_group(ul_pin); + + /* Value to be driven on the I/O line: 0. */ + p_pio->PIO_CODR = 1 << (ul_pin & 0x1F); +} + +/** + * \brief Toggle a GPIO pin. + * + * \param ul_pin The pin index. + * + * \note The function \ref pio_configure_pin must be called before. + */ +void pio_toggle_pin(uint32_t ul_pin) +{ + Pio *p_pio = pio_get_pin_group(ul_pin); + + if (p_pio->PIO_ODSR & (1 << (ul_pin & 0x1F))) { + /* Value to be driven on the I/O line: 0. */ + p_pio->PIO_CODR = 1 << (ul_pin & 0x1F); + } else { + /* Value to be driven on the I/O line: 1. */ + p_pio->PIO_SODR = 1 << (ul_pin & 0x1F); + } +} + +/** + * \brief Perform complete pin(s) configuration; general attributes and PIO init + * if necessary. + * + * \param ul_pin The pin index. + * \param ul_flags Pins attributes. + * + * \return Whether the pin(s) have been configured properly. + */ +uint32_t pio_configure_pin(uint32_t ul_pin, const uint32_t ul_flags) +{ + Pio *p_pio = pio_get_pin_group(ul_pin); + + /* Configure pins */ + switch (ul_flags & PIO_TYPE_Msk) { + case PIO_TYPE_PIO_PERIPH_A: + pio_set_peripheral(p_pio, PIO_PERIPH_A, (1 << (ul_pin & 0x1F))); + pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)), + (ul_flags & PIO_PULLUP)); + break; + case PIO_TYPE_PIO_PERIPH_B: + pio_set_peripheral(p_pio, PIO_PERIPH_B, (1 << (ul_pin & 0x1F))); + pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)), + (ul_flags & PIO_PULLUP)); + break; +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) + case PIO_TYPE_PIO_PERIPH_C: + pio_set_peripheral(p_pio, PIO_PERIPH_C, (1 << (ul_pin & 0x1F))); + pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)), + (ul_flags & PIO_PULLUP)); + break; + case PIO_TYPE_PIO_PERIPH_D: + pio_set_peripheral(p_pio, PIO_PERIPH_D, (1 << (ul_pin & 0x1F))); + pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)), + (ul_flags & PIO_PULLUP)); + break; +#endif + + case PIO_TYPE_PIO_INPUT: + pio_set_input(p_pio, (1 << (ul_pin & 0x1F)), ul_flags); + break; + + case PIO_TYPE_PIO_OUTPUT_0: + case PIO_TYPE_PIO_OUTPUT_1: + pio_set_output(p_pio, (1 << (ul_pin & 0x1F)), + ((ul_flags & PIO_TYPE_PIO_OUTPUT_1) + == PIO_TYPE_PIO_OUTPUT_1) ? 1 : 0, + (ul_flags & PIO_OPENDRAIN) ? 1 : 0, + (ul_flags & PIO_PULLUP) ? 1 : 0); + break; + + default: + return 0; + } + + return 1; +} + +/** + * \brief Drive a GPIO port to 1. + * + * \param p_pio Base address of the PIO port. + * \param ul_mask Bitmask of one or more pin(s) to toggle. + */ +void pio_set_pin_group_high(Pio *p_pio, uint32_t ul_mask) +{ + /* Value to be driven on the I/O line: 1. */ + p_pio->PIO_SODR = ul_mask; +} + +/** + * \brief Drive a GPIO port to 0. + * + * \param p_pio Base address of the PIO port. + * \param ul_mask Bitmask of one or more pin(s) to toggle. + */ +void pio_set_pin_group_low(Pio *p_pio, uint32_t ul_mask) +{ + /* Value to be driven on the I/O line: 0. */ + p_pio->PIO_CODR = ul_mask; +} + +/** + * \brief Toggle a GPIO group. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + */ +void pio_toggle_pin_group(Pio *p_pio, uint32_t ul_mask) +{ + if (p_pio->PIO_ODSR & ul_mask) { + /* Value to be driven on the I/O line: 0. */ + p_pio->PIO_CODR = ul_mask; + } else { + /* Value to be driven on the I/O line: 1. */ + p_pio->PIO_SODR = ul_mask; + } +} + +/** + * \brief Perform complete pin(s) configuration; general attributes and PIO init + * if necessary. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + * \param ul_flags Pin(s) attributes. + * + * \return Whether the pin(s) have been configured properly. + */ +uint32_t pio_configure_pin_group(Pio *p_pio, + uint32_t ul_mask, const uint32_t ul_flags) +{ + /* Configure pins */ + switch (ul_flags & PIO_TYPE_Msk) { + case PIO_TYPE_PIO_PERIPH_A: + pio_set_peripheral(p_pio, PIO_PERIPH_A, ul_mask); + pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP)); + break; + case PIO_TYPE_PIO_PERIPH_B: + pio_set_peripheral(p_pio, PIO_PERIPH_B, ul_mask); + pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP)); + break; +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) + case PIO_TYPE_PIO_PERIPH_C: + pio_set_peripheral(p_pio, PIO_PERIPH_C, ul_mask); + pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP)); + break; + case PIO_TYPE_PIO_PERIPH_D: + pio_set_peripheral(p_pio, PIO_PERIPH_D, ul_mask); + pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP)); + break; +#endif + + case PIO_TYPE_PIO_INPUT: + pio_set_input(p_pio, ul_mask, ul_flags); + break; + + case PIO_TYPE_PIO_OUTPUT_0: + case PIO_TYPE_PIO_OUTPUT_1: + pio_set_output(p_pio, ul_mask, + ((ul_flags & PIO_TYPE_PIO_OUTPUT_1) + == PIO_TYPE_PIO_OUTPUT_1) ? 1 : 0, + (ul_flags & PIO_OPENDRAIN) ? 1 : 0, + (ul_flags & PIO_PULLUP) ? 1 : 0); + break; + + default: + return 0; + } + + return 1; +} + +/** + * \brief Enable interrupt for a GPIO pin. + * + * \param ul_pin The pin index. + * + * \note The function \ref gpio_configure_pin must be called before. + */ +void pio_enable_pin_interrupt(uint32_t ul_pin) +{ + Pio *p_pio = pio_get_pin_group(ul_pin); + + p_pio->PIO_IER = 1 << (ul_pin & 0x1F); +} + + +/** + * \brief Disable interrupt for a GPIO pin. + * + * \param ul_pin The pin index. + * + * \note The function \ref gpio_configure_pin must be called before. + */ +void pio_disable_pin_interrupt(uint32_t ul_pin) +{ + Pio *p_pio = pio_get_pin_group(ul_pin); + + p_pio->PIO_IDR = 1 << (ul_pin & 0x1F); +} + + +/** + * \brief Return GPIO port for a GPIO pin. + * + * \param ul_pin The pin index. + * + * \return Pointer to \ref Pio struct for GPIO port. + */ +Pio *pio_get_pin_group(uint32_t ul_pin) +{ + Pio *p_pio; + +#if (SAM4C || SAM4CP) +# ifdef ID_PIOD + if (ul_pin > PIO_PC9_IDX) { + p_pio = PIOD; + } else if (ul_pin > PIO_PB31_IDX) { +# else + if (ul_pin > PIO_PB31_IDX) { +# endif + p_pio = PIOC; + } else { + p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5))); + } +#elif (SAM4CM) + if (ul_pin > PIO_PB21_IDX) { + p_pio = PIOC; + } else { + p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5))); + } +#else + p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5))); +#endif + return p_pio; +} + +/** + * \brief Return GPIO port peripheral ID for a GPIO pin. + * + * \param ul_pin The pin index. + * + * \return GPIO port peripheral ID. + */ +uint32_t pio_get_pin_group_id(uint32_t ul_pin) +{ + uint32_t ul_id; + +#if (SAM4C || SAM4CP) +# ifdef ID_PIOD + if (ul_pin > PIO_PC9_IDX) { + ul_id = ID_PIOD; + } else if (ul_pin > PIO_PB31_IDX) { +# else + if (ul_pin > PIO_PB31_IDX) { +# endif + ul_id = ID_PIOC; + } else { + ul_id = ID_PIOA + (ul_pin >> 5); + } +#elif (SAM4CM) + if (ul_pin > PIO_PB21_IDX) { + ul_id = ID_PIOC; + } else { + ul_id = ID_PIOA + (ul_pin >> 5); + } +#elif (SAMV70 || SAMV71 || SAME70 || SAMS70) + ul_id = ID_PIOA + (ul_pin >> 5); + + #ifdef ID_PIOD + if (ul_pin >= PIO_PD0_IDX) ul_id = ID_PIOD; + #endif + + #ifdef ID_PIOE + if (ul_pin >= PIO_PE0_IDX) ul_id = ID_PIOE; + #endif +#else + ul_id = ID_PIOA + (ul_pin >> 5); +#endif + return ul_id; +} + + +/** + * \brief Return GPIO port pin mask for a GPIO pin. + * + * \param ul_pin The pin index. + * + * \return GPIO port pin mask. + */ +uint32_t pio_get_pin_group_mask(uint32_t ul_pin) +{ + uint32_t ul_mask = 1 << (ul_pin & 0x1F); + return ul_mask; +} + +#if (SAM3S || SAM4S || SAM4E || SAMV71 || SAMV70 || SAME70 || SAMS70) +/* Capture mode enable flag */ +uint32_t pio_capture_enable_flag; + +/** + * \brief Configure PIO capture mode. + * \note PIO capture mode will be disabled automatically. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mode Bitmask of one or more modes. + */ +void pio_capture_set_mode(Pio *p_pio, uint32_t ul_mode) +{ + ul_mode &= (~PIO_PCMR_PCEN); /* Disable PIO capture mode */ + p_pio->PIO_PCMR = ul_mode; +} + +/** + * \brief Enable PIO capture mode. + * + * \param p_pio Pointer to a PIO instance. + */ +void pio_capture_enable(Pio *p_pio) +{ + p_pio->PIO_PCMR |= PIO_PCMR_PCEN; + pio_capture_enable_flag = true; +} + +/** + * \brief Disable PIO capture mode. + * + * \param p_pio Pointer to a PIO instance. + */ +void pio_capture_disable(Pio *p_pio) +{ + p_pio->PIO_PCMR &= (~PIO_PCMR_PCEN); + pio_capture_enable_flag = false; +} + +/** + * \brief Read from Capture Reception Holding Register. + * \note Data presence should be tested before any read attempt. + * + * \param p_pio Pointer to a PIO instance. + * \param pul_data Pointer to store the data. + * + * \retval 0 Success. + * \retval 1 I/O Failure, Capture data is not ready. + */ +uint32_t pio_capture_read(const Pio *p_pio, uint32_t *pul_data) +{ + /* Check if the data is ready */ + if ((p_pio->PIO_PCISR & PIO_PCISR_DRDY) == 0) { + return 1; + } + + /* Read data */ + *pul_data = p_pio->PIO_PCRHR; + return 0; +} + +/** + * \brief Enable the given interrupt source of PIO capture. The status + * register of the corresponding PIO capture controller is cleared prior + * to enabling the interrupt. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Interrupt sources bit map. + */ +void pio_capture_enable_interrupt(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_PCISR; + p_pio->PIO_PCIER = ul_mask; +} + +/** + * \brief Disable a given interrupt source of PIO capture. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Interrupt sources bit map. + */ +void pio_capture_disable_interrupt(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_PCIDR = ul_mask; +} + +/** + * \brief Read PIO interrupt status of PIO capture. + * + * \param p_pio Pointer to a PIO instance. + * + * \return The interrupt status mask value. + */ +uint32_t pio_capture_get_interrupt_status(const Pio *p_pio) +{ + return p_pio->PIO_PCISR; +} + +/** + * \brief Read PIO interrupt mask of PIO capture. + * + * \param p_pio Pointer to a PIO instance. + * + * \return The interrupt mask value. + */ +uint32_t pio_capture_get_interrupt_mask(const Pio *p_pio) +{ + return p_pio->PIO_PCIMR; +} +#if !(SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Get PDC registers base address. + * + * \param p_pio Pointer to an PIO peripheral. + * + * \return PIOA PDC register base address. + */ +Pdc *pio_capture_get_pdc_base(const Pio *p_pio) +{ + UNUSED(p_pio); /* Stop warning */ + return PDC_PIOA; +} +#endif +#endif + +#if (SAM4C || SAM4CP || SAM4CM || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Set PIO IO drive. + * + * \param p_pio Pointer to an PIO peripheral. + * \param ul_line Line index (0..31). + * \param mode IO drive mode. + */ +void pio_set_io_drive(Pio *p_pio, uint32_t ul_line, + enum pio_io_drive_mode mode) +{ + p_pio->PIO_DRIVER &= ~(1 << ul_line); + p_pio->PIO_DRIVER |= mode << ul_line; +} +#endif + +//@} + diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/pio/pio.h b/hw-libs/drivers/SAMx70/ASF/sam/drivers/pio/pio.h new file mode 100644 index 000000000..fedf3f587 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/pio/pio.h @@ -0,0 +1,367 @@ +/** + * \file + * + * \brief Parallel Input/Output (PIO) Controller driver for SAM. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef PIO_H_INCLUDED +#define PIO_H_INCLUDED + +#include "compiler.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Compute PIO register length */ +#define PIO_DELTA ((uint32_t) PIOB - (uint32_t) PIOA) + +/* GPIO Support */ +#define PIO_TYPE_Pos 27 +/* PIO Type Mask */ +#define PIO_TYPE_Msk (0xFu << PIO_TYPE_Pos) +/* The pin is not a function pin. */ +#define PIO_TYPE_NOT_A_PIN (0x0u << PIO_TYPE_Pos) +/* The pin is controlled by the peripheral A. */ +#define PIO_TYPE_PIO_PERIPH_A (0x1u << PIO_TYPE_Pos) +/* The pin is controlled by the peripheral B. */ +#define PIO_TYPE_PIO_PERIPH_B (0x2u << PIO_TYPE_Pos) +/* The pin is controlled by the peripheral C. */ +#define PIO_TYPE_PIO_PERIPH_C (0x3u << PIO_TYPE_Pos) +/* The pin is controlled by the peripheral D. */ +#define PIO_TYPE_PIO_PERIPH_D (0x4u << PIO_TYPE_Pos) +/* The pin is an input. */ +#define PIO_TYPE_PIO_INPUT (0x5u << PIO_TYPE_Pos) +/* The pin is an output and has a default level of 0. */ +#define PIO_TYPE_PIO_OUTPUT_0 (0x6u << PIO_TYPE_Pos) +/* The pin is an output and has a default level of 1. */ +#define PIO_TYPE_PIO_OUTPUT_1 (0x7u << PIO_TYPE_Pos) + +typedef enum _pio_type { + PIO_NOT_A_PIN = PIO_TYPE_NOT_A_PIN, + PIO_PERIPH_A = PIO_TYPE_PIO_PERIPH_A, + PIO_PERIPH_B = PIO_TYPE_PIO_PERIPH_B, +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) + PIO_PERIPH_C = PIO_TYPE_PIO_PERIPH_C, + PIO_PERIPH_D = PIO_TYPE_PIO_PERIPH_D, +#endif + PIO_INPUT = PIO_TYPE_PIO_INPUT, + PIO_OUTPUT_0 = PIO_TYPE_PIO_OUTPUT_0, + PIO_OUTPUT_1 = PIO_TYPE_PIO_OUTPUT_1 +} pio_type_t; + +/* Default pin configuration (no attribute). */ +#define PIO_DEFAULT (0u << 0) +/* The internal pin pull-up is active. */ +#define PIO_PULLUP (1u << 0) +/* The internal glitch filter is active. */ +#define PIO_DEGLITCH (1u << 1) +/* The pin is open-drain. */ +#define PIO_OPENDRAIN (1u << 2) + +/* The internal debouncing filter is active. */ +#define PIO_DEBOUNCE (1u << 3) + +/* Enable additional interrupt modes. */ +#define PIO_IT_AIME (1u << 4) + +/* Interrupt High Level/Rising Edge detection is active. */ +#define PIO_IT_RE_OR_HL (1u << 5) +/* Interrupt Edge detection is active. */ +#define PIO_IT_EDGE (1u << 6) + +/* Low level interrupt is active */ +#define PIO_IT_LOW_LEVEL (0 | 0 | PIO_IT_AIME) +/* High level interrupt is active */ +#define PIO_IT_HIGH_LEVEL (PIO_IT_RE_OR_HL | 0 | PIO_IT_AIME) +/* Falling edge interrupt is active */ +#define PIO_IT_FALL_EDGE (0 | PIO_IT_EDGE | PIO_IT_AIME) +/* Rising edge interrupt is active */ +#define PIO_IT_RISE_EDGE (PIO_IT_RE_OR_HL | PIO_IT_EDGE | PIO_IT_AIME) + +/* + * The #attribute# field is a bitmask that can either be set to PIO_DEFAULT, + * or combine (using bitwise OR '|') any number of the following constants: + * - PIO_PULLUP + * - PIO_DEGLITCH + * - PIO_DEBOUNCE + * - PIO_OPENDRAIN + * - PIO_IT_LOW_LEVEL + * - PIO_IT_HIGH_LEVEL + * - PIO_IT_FALL_EDGE + * - PIO_IT_RISE_EDGE + */ +void pio_pull_up(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_pull_up_enable); +void pio_set_debounce_filter(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_cut_off); +void pio_set(Pio *p_pio, const uint32_t ul_mask); +void pio_clear(Pio *p_pio, const uint32_t ul_mask); +uint32_t pio_get(Pio *p_pio, const pio_type_t ul_type, + const uint32_t ul_mask); +void pio_set_peripheral(Pio *p_pio, const pio_type_t ul_type, + const uint32_t ul_mask); +void pio_set_input(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_attribute); +void pio_set_output(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_default_level, + const uint32_t ul_multidrive_enable, + const uint32_t ul_pull_up_enable); +uint32_t pio_configure(Pio *p_pio, const pio_type_t ul_type, + const uint32_t ul_mask, const uint32_t ul_attribute); +uint32_t pio_get_output_data_status(const Pio *p_pio, + const uint32_t ul_mask); +void pio_set_multi_driver(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_multi_driver_enable); +uint32_t pio_get_multi_driver_status(const Pio *p_pio); + +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) +void pio_pull_down(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_pull_down_enable); +#endif + +void pio_enable_output_write(Pio *p_pio, const uint32_t ul_mask); +void pio_disable_output_write(Pio *p_pio, const uint32_t ul_mask); +uint32_t pio_get_output_write_status(const Pio *p_pio); +void pio_sync_output_write(Pio *p_pio, const uint32_t ul_mask); + +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) +void pio_set_schmitt_trigger(Pio *p_pio, const uint32_t ul_mask); +uint32_t pio_get_schmitt_trigger(const Pio *p_pio); +#endif + +void pio_configure_interrupt(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_attr); +void pio_enable_interrupt(Pio *p_pio, const uint32_t ul_mask); +void pio_disable_interrupt(Pio *p_pio, const uint32_t ul_mask); +uint32_t pio_get_interrupt_status(const Pio *p_pio); +uint32_t pio_get_interrupt_mask(const Pio *p_pio); +void pio_set_additional_interrupt_mode(Pio *p_pio, + const uint32_t ul_mask, const uint32_t ul_attribute); +void pio_set_writeprotect(Pio *p_pio, const uint32_t ul_enable); +uint32_t pio_get_writeprotect_status(const Pio *p_pio); + +#if (SAM3S || SAM4S || SAM4E || SAMV71 || SAMV70 || SAME70 || SAMS70) +void pio_capture_set_mode(Pio *p_pio, uint32_t ul_mode); +void pio_capture_enable(Pio *p_pio); +void pio_capture_disable(Pio *p_pio); +uint32_t pio_capture_read(const Pio *p_pio, uint32_t * pul_data); +void pio_capture_enable_interrupt(Pio *p_pio, const uint32_t ul_mask); +void pio_capture_disable_interrupt(Pio * p_pio, const uint32_t ul_mask); +uint32_t pio_capture_get_interrupt_status(const Pio *p_pio); +uint32_t pio_capture_get_interrupt_mask(const Pio *p_pio); +#if !(SAMV71 || SAMV70 || SAME70 || SAMS70) +Pdc *pio_capture_get_pdc_base(const Pio *p_pio); +#endif +#endif + +/* GPIO Support */ +uint32_t pio_get_pin_value(uint32_t pin); +void pio_set_pin_high(uint32_t pin); +void pio_set_pin_low(uint32_t pin); +void pio_toggle_pin(uint32_t pin); +void pio_enable_pin_interrupt(uint32_t pin); +void pio_disable_pin_interrupt(uint32_t pin); +Pio *pio_get_pin_group(uint32_t pin); +uint32_t pio_get_pin_group_id(uint32_t pin); +uint32_t pio_get_pin_group_mask(uint32_t pin); +uint32_t pio_configure_pin(uint32_t ul_pin, const uint32_t ul_flags); +void pio_set_pin_group_high(Pio *p_pio, uint32_t ul_mask); +void pio_set_pin_group_low(Pio *p_pio, uint32_t ul_mask); +void pio_toggle_pin_group(Pio *p_pio, uint32_t ul_mask); +uint32_t pio_configure_pin_group(Pio *p_pio, uint32_t ul_mask, + const uint32_t ul_flags); + +#if (SAM4C || SAM4CP || SAM4CM || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) +enum pio_io_drive_mode { + PIO_IO_DRIVE_LOW = 0, + PIO_IO_DRIVE_HIGH, +}; +void pio_set_io_drive(Pio *p_pio, uint32_t ul_line, + enum pio_io_drive_mode mode); +#endif + +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) +void pio_keypad_enable(Pio *p_pio); +void pio_keypad_disable(Pio *p_pio); +void pio_keypad_set_row_num(Pio *p_pio, uint8_t num); +uint8_t pio_keypad_get_row_num(const Pio *p_pio); +void pio_keypad_set_column_num(Pio *p_pio, uint8_t num); +uint8_t pio_keypad_get_column_num(const Pio *p_pio); +void pio_keypad_set_debouncing_value(Pio *p_pio, uint16_t value); +uint16_t pio_keypad_get_debouncing_value(const Pio *p_pio); +void pio_keypad_enable_interrupt(Pio *p_pio, uint32_t ul_mask); +void pio_keypad_disable_interrupt(Pio *p_pio, uint32_t ul_mask); +uint32_t pio_keypad_get_interrupt_mask(const Pio *p_pio); +uint32_t pio_keypad_get_press_status(const Pio *p_pio); +uint32_t pio_keypad_get_release_status(const Pio *p_pio); +uint8_t pio_keypad_get_simult_press_num(const Pio *p_pio); +uint8_t pio_keypad_get_simult_release_num(const Pio *p_pio); +uint8_t pio_keypad_get_press_row_index(const Pio *p_pio, uint8_t queue); +uint8_t pio_keypad_get_press_column_index(const Pio *p_pio, uint8_t queue); +uint8_t pio_keypad_get_release_row_index(const Pio *p_pio, uint8_t queue); +uint8_t pio_keypad_get_release_column_index(const Pio *p_pio, uint8_t queue); +#endif +/** + * \page sam_pio_quickstart Quick Start Guide for the SAM PIO driver + * + * This is the quick start guide for the \ref sam_drivers_pio_group "PIO Driver", + * with step-by-step instructions on how to configure and use the driver for + * specific use cases. + * + * The section described below can be compiled into e.g. the main application + * loop or any other function that will need to interface with the IO port. + * + * \section sam_pio_usecases PIO use cases + * - \ref sam_pio_quickstart_basic + * - \ref sam_pio_quickstart_use_case_2 + * + * \section sam_pio_quickstart_basic Basic usage of the PIO driver + * This section will present a basic use case for the PIO driver. This use case + * will configure pin 23 on port A as output and pin 16 as an input with pullup, + * and then toggle the output pin's value to match that of the input pin. + * + * \subsection sam_pio_quickstart_use_case_1_prereq Prerequisites + * - \ref group_pmc "Power Management Controller driver" + * + * \subsection sam_pio_quickstart_use_case_1_setup_steps Initialization code + * Add to the application initialization code: + * \code + pmc_enable_periph_clk(ID_PIOA); + + pio_set_output(PIOA, PIO_PA23, LOW, DISABLE, ENABLE); + pio_set_input(PIOA, PIO_PA16, PIO_PULLUP); +\endcode + * + * \subsection sam_pio_quickstart_use_case_1_setup_steps_workflow Workflow + * -# Enable the module clock to the PIOA peripheral: + * \code pmc_enable_periph_clk(ID_PIOA); \endcode + * -# Set pin 23 direction on PIOA as output, default low level: + * \code pio_set_output(PIOA, PIO_PA23, LOW, DISABLE, ENABLE); \endcode + * -# Set pin 16 direction on PIOA as input, with pullup: + * \code pio_set_input(PIOA, PIO_PA16, PIO_PULLUP); \endcode + * + * \subsection sam_pio_quickstart_use_case_1_example_code Example code + * Set the state of output pin 23 to match input pin 16: + * \code + if (pio_get(PIOA, PIO_TYPE_PIO_INPUT, PIO_PA16)) + pio_clear(PIOA, PIO_PA23); + else + pio_set(PIOA, PIO_PA23); +\endcode + * + * \subsection sam_pio_quickstart_use_case_1_example_workflow Workflow + * -# We check the value of the pin: + * \code + if (pio_get(PIOA, PIO_TYPE_PIO_INPUT, PIO_PA16)) +\endcode + * -# Then we set the new output value based on the read pin value: + * \code + pio_clear(PIOA, PIO_PA23); + else + pio_set(PIOA, PIO_PA23); +\endcode + */ + +/** + * \page sam_pio_quickstart_use_case_2 Advanced use case - Interrupt driven edge detection + * + * \section sam_pio_quickstart_use_case_2 Advanced Use Case 1 + * This section will present a more advanced use case for the PIO driver. This use case + * will configure pin 23 on port A as output and pin 16 as an input with pullup, + * and then toggle the output pin's value to match that of the input pin using the interrupt + * controller within the device. + * + * \subsection sam_pio_quickstart_use_case_2_prereq Prerequisites + * - \ref group_pmc "Power Management Controller driver" + * + * \subsection sam_pio_quickstart_use_case_2_setup_steps Initialization code + * Add to the application initialization code: + * \code + pmc_enable_periph_clk(ID_PIOA); + + pio_set_output(PIOA, PIO_PA23, LOW, DISABLE, ENABLE); + pio_set_input(PIOA, PIO_PA16, PIO_PULLUP); + + pio_handler_set(PIOA, ID_PIOA, PIO_PA16, PIO_IT_EDGE, pin_edge_handler); + pio_enable_interrupt(PIOA, PIO_PA16); + + NVIC_EnableIRQ(PIOA_IRQn); +\endcode + * + * \subsection sam_pio_quickstart_use_case_2_setup_steps_workflow Workflow + * -# Enable the module clock to the PIOA peripheral: + * \code pmc_enable_periph_clk(ID_PIOA); \endcode + * -# Set pin 23 direction on PIOA as output, default low level: + * \code pio_set_output(PIOA, PIO_PA23, LOW, DISABLE, ENABLE); \endcode + * -# Set pin 16 direction on PIOA as input, with pullup: + * \code pio_set_input(PIOA, PIO_PA16, PIO_PULLUP); \endcode + * -# Configure the input pin 16 interrupt mode and handler: + * \code pio_handler_set(PIOA, ID_PIOA, PIO_PA16, PIO_IT_EDGE, pin_edge_handler); \endcode + * -# Enable the interrupt for the configured input pin: + * \code pio_enable_interrupt(PIOA, PIO_PA16); \endcode + * -# Enable interrupt handling from the PIOA module: + * \code NVIC_EnableIRQ(PIOA_IRQn); \endcode + * + * \subsection sam_pio_quickstart_use_case_2_example_code Example code + * Add the following function to your application: + * \code + void pin_edge_handler(const uint32_t id, const uint32_t index) + { + if ((id == ID_PIOA) && (index == PIO_PA16)){ + if (pio_get(PIOA, PIO_TYPE_PIO_INPUT, PIO_PA16)) + pio_clear(PIOA, PIO_PA23); + else + pio_set(PIOA, PIO_PA23); + } + } +\endcode + * + * \subsection sam_pio_quickstart_use_case_2_example_workflow Workflow + * -# We check the value of the pin: + * \code + if (pio_get(PIOA, PIO_TYPE_PIO_INPUT, PIO_PA16)) +\endcode + * -# Then we set the new output value based on the read pin value: + * \code + pio_clear(PIOA, PIO_PA23); + else + pio_set(PIOA, PIO_PA23); +\endcode + */ + +#ifdef __cplusplus +} +#endif + +#endif /* PIO_H_INCLUDED */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/pio/pio_handler.c b/hw-libs/drivers/SAMx70/ASF/sam/drivers/pio/pio_handler.c new file mode 100644 index 000000000..768011877 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/pio/pio_handler.c @@ -0,0 +1,289 @@ +/** + * \file + * + * \brief Parallel Input/Output (PIO) interrupt handler for SAM. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "pio.h" +#include "pio_handler.h" + +/** + * Maximum number of interrupt sources that can be defined. This + * constant can be increased, but the current value is the smallest possible one + * that will be compatible with all existing projects. + */ +#define MAX_INTERRUPT_SOURCES 7 + +/** + * Describes a PIO interrupt source, including the PIO instance triggering the + * interrupt and the associated interrupt handler. + */ +struct s_interrupt_source { + uint32_t id; + uint32_t mask; + uint32_t attr; + + /* Interrupt handler. */ + void (*handler) (const uint32_t, const uint32_t); +}; + + +/* List of interrupt sources. */ +static struct s_interrupt_source gs_interrupt_sources[MAX_INTERRUPT_SOURCES]; + +/* Number of currently defined interrupt sources. */ +static uint32_t gs_ul_nb_sources = 0; + +#if (SAM3S || SAM4S || SAM4E) +/* PIO Capture handler */ +static void (*pio_capture_handler)(Pio *) = NULL; +extern uint32_t pio_capture_enable_flag; +#endif + +/** + * \brief Process an interrupt request on the given PIO controller. + * + * \param p_pio PIO controller base address. + * \param ul_id PIO controller ID. + */ +void pio_handler_process(Pio *p_pio, uint32_t ul_id) +{ + uint32_t status; + uint32_t i; + + /* Read PIO controller status */ + status = pio_get_interrupt_status(p_pio); + status &= pio_get_interrupt_mask(p_pio); + + /* Check pending events */ + if (status != 0) { + /* Find triggering source */ + i = 0; + while (status != 0) { + /* Source is configured on the same controller */ + if (gs_interrupt_sources[i].id == ul_id) { + /* Source has PIOs whose statuses have changed */ + if ((status & gs_interrupt_sources[i].mask) != 0) { + gs_interrupt_sources[i].handler(gs_interrupt_sources[i].id, + gs_interrupt_sources[i].mask); + status &= ~(gs_interrupt_sources[i].mask); + } + } + i++; + if (i >= MAX_INTERRUPT_SOURCES) { + break; + } + } + } + + /* Check capture events */ +#if (SAM3S || SAM4S || SAM4E) + if (pio_capture_enable_flag) { + if (pio_capture_handler) { + pio_capture_handler(p_pio); + } + } +#endif +} + +/** + * \brief Set an interrupt handler for the provided pins. + * The provided handler will be called with the triggering pin as its parameter + * as soon as an interrupt is detected. + * + * \param p_pio PIO controller base address. + * \param ul_id PIO ID. + * \param ul_mask Pins (bit mask) to configure. + * \param ul_attr Pins attribute to configure. + * \param p_handler Interrupt handler function pointer. + * + * \return 0 if successful, 1 if the maximum number of sources has been defined. + */ +uint32_t pio_handler_set(Pio *p_pio, uint32_t ul_id, uint32_t ul_mask, + uint32_t ul_attr, void (*p_handler) (uint32_t, uint32_t)) +{ + uint8_t i; + struct s_interrupt_source *pSource = NULL; + + if (gs_ul_nb_sources >= MAX_INTERRUPT_SOURCES) + return 1; + + /* Check interrupt for this pin, if already defined, redefine it. */ + for (i = 0; i <= gs_ul_nb_sources; i++) { + pSource = &(gs_interrupt_sources[i]); + if (pSource->id == ul_id && pSource->mask == ul_mask) { + break; + } + } + + if(pSource == NULL) + return 1; + + /* Define new source */ + pSource->id = ul_id; + pSource->mask = ul_mask; + pSource->attr = ul_attr; + pSource->handler = p_handler; + if (i == gs_ul_nb_sources + 1) { + gs_ul_nb_sources++; + } + + /* Configure interrupt mode */ + pio_configure_interrupt(p_pio, ul_mask, ul_attr); + + return 0; +} + +#if (SAM3S || SAM4S || SAM4E) +/** + * \brief Set a capture interrupt handler for all PIO. + * + * The handler will be called with the triggering PIO as its parameter + * as soon as an interrupt is detected. + * + * \param p_handler Interrupt handler function pointer. + * + */ +void pio_capture_handler_set(void (*p_handler)(Pio *)) +{ + pio_capture_handler = p_handler; +} +#endif + +#ifdef ID_PIOA +/** + * \brief Set an interrupt handler for the specified pin. + * The provided handler will be called with the triggering pin as its parameter + * as soon as an interrupt is detected. + * + * \param ul_pin Pin index to configure. + * \param ul_flag Pin flag. + * \param p_handler Interrupt handler function pointer. + * + * \return 0 if successful, 1 if the maximum number of sources has been defined. + */ +uint32_t pio_handler_set_pin(uint32_t ul_pin, uint32_t ul_flag, + void (*p_handler) (uint32_t, uint32_t)) +{ + Pio *p_pio = pio_get_pin_group(ul_pin); + uint32_t group_id = pio_get_pin_group_id(ul_pin); + uint32_t group_mask = pio_get_pin_group_mask(ul_pin); + + return pio_handler_set(p_pio, group_id, group_mask, ul_flag, p_handler); +} + +/** + * \brief Parallel IO Controller A interrupt handler. + * Redefined PIOA interrupt handler for NVIC interrupt table. + */ +void PIOA_Handler(void) +{ + pio_handler_process(PIOA, ID_PIOA); +} +#endif + +#ifdef ID_PIOB +/** + * \brief Parallel IO Controller B interrupt handler + * Redefined PIOB interrupt handler for NVIC interrupt table. + */ +void PIOB_Handler(void) +{ + pio_handler_process(PIOB, ID_PIOB); +} +#endif + +#ifdef ID_PIOC +/** + * \brief Parallel IO Controller C interrupt handler. + * Redefined PIOC interrupt handler for NVIC interrupt table. + */ +void PIOC_Handler(void) +{ + pio_handler_process(PIOC, ID_PIOC); +} +#endif + +#ifdef ID_PIOD +/** + * \brief Parallel IO Controller D interrupt handler. + * Redefined PIOD interrupt handler for NVIC interrupt table. + */ +void PIOD_Handler(void) +{ + pio_handler_process(PIOD, ID_PIOD); +} +#endif + +#ifdef ID_PIOE +/** + * \brief Parallel IO Controller E interrupt handler. + * Redefined PIOE interrupt handler for NVIC interrupt table. + */ +void PIOE_Handler(void) +{ + pio_handler_process(PIOE, ID_PIOE); +} +#endif + +#ifdef ID_PIOF +/** + * \brief Parallel IO Controller F interrupt handler. + * Redefined PIOF interrupt handler for NVIC interrupt table. + */ +void PIOF_Handler(void) +{ + pio_handler_process(PIOF, ID_PIOF); +} +#endif + +/** + * \brief Initialize PIO interrupt management logic. + * + * \param p_pio PIO controller base address. + * \param ul_irqn NVIC line number. + * \param ul_priority PIO controller interrupts priority. + */ +void pio_handler_set_priority(Pio *p_pio, IRQn_Type ul_irqn, uint32_t ul_priority) +{ + uint32_t bitmask = 0; + + bitmask = pio_get_interrupt_mask(p_pio); + pio_disable_interrupt(p_pio, 0xFFFFFFFF); + pio_get_interrupt_status(p_pio); + NVIC_DisableIRQ(ul_irqn); + NVIC_ClearPendingIRQ(ul_irqn); + NVIC_SetPriority(ul_irqn, ul_priority); + NVIC_EnableIRQ(ul_irqn); + pio_enable_interrupt(p_pio, bitmask); +} diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/pio/pio_handler.h b/hw-libs/drivers/SAMx70/ASF/sam/drivers/pio/pio_handler.h new file mode 100644 index 000000000..36518900f --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/pio/pio_handler.h @@ -0,0 +1,59 @@ +/** + * \file + * + * \brief Parallel Input/Output (PIO) interrupt handler for SAM. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef PIO_HANDLER_H_INCLUDED +#define PIO_HANDLER_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +void pio_handler_process(Pio *p_pio, uint32_t ul_id); +void pio_handler_set_priority(Pio *p_pio, IRQn_Type ul_irqn, uint32_t ul_priority); +uint32_t pio_handler_set(Pio *p_pio, uint32_t ul_id, uint32_t ul_mask, + uint32_t ul_attr, void (*p_handler) (uint32_t, uint32_t)); +uint32_t pio_handler_set_pin(uint32_t ul_pin, uint32_t ul_flag, + void (*p_handler) (uint32_t, uint32_t)); + +#if (SAM3S || SAM4S || SAM4E) +void pio_capture_handler_set(void (*p_handler)(Pio *)); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* PIO_HANDLER_H_INCLUDED */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/pmc/pmc.c b/hw-libs/drivers/SAMx70/ASF/sam/drivers/pmc/pmc.c new file mode 100644 index 000000000..7bb1a7017 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/pmc/pmc.c @@ -0,0 +1,1681 @@ +/** + * \file + * + * \brief Power Management Controller (PMC) driver for SAM. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "pmc.h" + +#if (SAM3N) +# define MAX_PERIPH_ID 31 +#elif (SAM3XA) +# define MAX_PERIPH_ID 44 +#elif (SAM3U) +# define MAX_PERIPH_ID 29 +#elif (SAM3S || SAM4S) +# define MAX_PERIPH_ID 34 +#elif (SAM4E) +# define MAX_PERIPH_ID 47 +#elif (SAMV71) +# define MAX_PERIPH_ID 63 +#elif (SAMV70) +# define MAX_PERIPH_ID 63 +#elif (SAME70) +# define MAX_PERIPH_ID 63 +#elif (SAMS70) +# define MAX_PERIPH_ID 63 +#elif (SAM4N) +# define MAX_PERIPH_ID 31 +#elif (SAM4C || SAM4CM || SAM4CP) +# define MAX_PERIPH_ID 43 +#elif (SAMG51) +# define MAX_PERIPH_ID 47 +#elif (SAMG53) +# define MAX_PERIPH_ID 47 +#elif (SAMG54) +# define MAX_PERIPH_ID 47 +#elif (SAMG55) +# define MAX_PERIPH_ID 50 +#endif + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \defgroup sam_drivers_pmc_group Power Management Controller (PMC) + * + * \par Purpose + * + * The Power Management Controller (PMC) optimizes power consumption by + * controlling all system and user peripheral clocks. The PMC enables/disables + * the clock inputs to many of the peripherals and the Cortex-M Processor. + * + * @{ + */ + +/** + * \brief Set the prescaler of the MCK. + * + * \param ul_pres Prescaler value. + */ +void pmc_mck_set_prescaler(uint32_t ul_pres) +{ + PMC->PMC_MCKR = + (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); +} + +#if SAMV71 || SAMV70 || SAME70 || SAMS70 +/** + * \brief Set the division of the MCK. + * + * \param ul_div Division value. + */ +void pmc_mck_set_division(uint32_t ul_div) +{ + switch (ul_div) { + case 1: + ul_div = PMC_MCKR_MDIV_EQ_PCK; + break; + case 2: + ul_div = PMC_MCKR_MDIV_PCK_DIV2; + break; + case 3: + ul_div = PMC_MCKR_MDIV_PCK_DIV3; + break; + case 4: + ul_div = PMC_MCKR_MDIV_PCK_DIV4; + break; + default: + ul_div = PMC_MCKR_MDIV_EQ_PCK; + break; + } + PMC->PMC_MCKR = + (PMC->PMC_MCKR & (~PMC_MCKR_MDIV_Msk)) | ul_div; + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); +} +#endif + +/** + * \brief Set the source of the MCK. + * + * \param ul_source Source selection value. + */ +void pmc_mck_set_source(uint32_t ul_source) +{ + PMC->PMC_MCKR = + (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | ul_source; + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); +} + +/** + * \brief Switch master clock source selection to slow clock. + * + * \param ul_pres Processor clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_mck_to_sclk(uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | + PMC_MCKR_CSS_SLOW_CLK; + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} + +/** + * \brief Switch master clock source selection to main clock. + * + * \param ul_pres Processor clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_mck_to_mainck(uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | + PMC_MCKR_CSS_MAIN_CLK; + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} + +/** + * \brief Switch master clock source selection to PLLA clock. + * + * \param ul_pres Processor clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_mck_to_pllack(uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | + PMC_MCKR_CSS_PLLA_CLK; + + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} + +#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55) +/** + * \brief Switch master clock source selection to PLLB clock. + * + * \param ul_pres Processor clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_mck_to_pllbck(uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | + PMC_MCKR_CSS_PLLB_CLK; + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} +#endif + +#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Switch master clock source selection to UPLL clock. + * + * \param ul_pres Processor clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_mck_to_upllck(uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | + PMC_MCKR_CSS_UPLL_CLK; + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} +#endif + +/** + * \brief Switch slow clock source selection to external 32k (Xtal or Bypass). + * + * \note Switching SCLK back to 32krc is only possible by shutting down the + * VDDIO power supply. + * + * \param ul_bypass 0 for Xtal, 1 for bypass. + */ +void pmc_switch_sclk_to_32kxtal(uint32_t ul_bypass) +{ + /* Set Bypass mode if required */ + if (ul_bypass == 1) { + SUPC->SUPC_MR |= SUPC_MR_KEY_PASSWD | + SUPC_MR_OSCBYPASS; + } + + SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL; +} + +/** + * \brief Check if the external 32k Xtal is ready. + * + * \retval 1 External 32k Xtal is ready. + * \retval 0 External 32k Xtal is not ready. + */ +uint32_t pmc_osc_is_ready_32kxtal(void) +{ + return ((SUPC->SUPC_SR & SUPC_SR_OSCSEL) + && (PMC->PMC_SR & PMC_SR_OSCSELS)); +} + +/** + * \brief Switch main clock source selection to internal fast RC. + * + * \param ul_moscrcf Fast RC oscillator(4/8/12Mhz). + * + * \retval 0 Success. + * \retval 1 Timeout error. + * \retval 2 Invalid frequency. + */ +void pmc_switch_mainck_to_fastrc(uint32_t ul_moscrcf) +{ + /* Enable Fast RC oscillator but DO NOT switch to RC now */ + PMC->CKGR_MOR |= (CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCEN); + + /* Wait the Fast RC to stabilize */ + while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)); + + /* Change Fast RC oscillator frequency */ + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) | + CKGR_MOR_KEY_PASSWD | ul_moscrcf; + + /* Wait the Fast RC to stabilize */ + while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)); + + /* Switch to Fast RC */ + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) | + CKGR_MOR_KEY_PASSWD; +} + +/** + * \brief Enable fast RC oscillator. + * + * \param ul_rc Fast RC oscillator(4/8/12Mhz). + */ +void pmc_osc_enable_fastrc(uint32_t ul_rc) +{ + /* Enable Fast RC oscillator but DO NOT switch to RC */ + PMC->CKGR_MOR |= (CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCEN); + /* Wait the Fast RC to stabilize */ + while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)); + + /* Change Fast RC oscillator frequency */ + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) | + CKGR_MOR_KEY_PASSWD | ul_rc; + /* Wait the Fast RC to stabilize */ + while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)); +} + +/** + * \brief Disable the internal fast RC. + */ +void pmc_osc_disable_fastrc(void) +{ + /* Disable Fast RC oscillator */ + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN & + ~CKGR_MOR_MOSCRCF_Msk) + | CKGR_MOR_KEY_PASSWD; +} + +/** + * \brief Check if the main fastrc is ready. + * + * \retval 0 Xtal is not ready, otherwise ready. + */ +uint32_t pmc_osc_is_ready_fastrc(void) +{ + return (PMC->PMC_SR & PMC_SR_MOSCRCS); +} + +/** + * \brief Enable main XTAL oscillator. + * + * \param ul_xtal_startup_time Xtal start-up time, in number of slow clocks. + */ +void pmc_osc_enable_main_xtal(uint32_t ul_xtal_startup_time) +{ + uint32_t mor = PMC->CKGR_MOR; + mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN); + mor |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTEN | + CKGR_MOR_MOSCXTST(ul_xtal_startup_time); + PMC->CKGR_MOR = mor; + /* Wait the main Xtal to stabilize */ + while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)); +} + +/** + * \brief Bypass main XTAL. + */ +void pmc_osc_bypass_main_xtal(void) +{ + uint32_t mor = PMC->CKGR_MOR; + mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN); + mor |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTBY; + /* Enable Crystal oscillator but DO NOT switch now. Keep MOSCSEL to 0 */ + PMC->CKGR_MOR = mor; + /* The MOSCXTS in PMC_SR is automatically set */ +} + +/** + * \brief Disable the main Xtal. + */ +void pmc_osc_disable_main_xtal(void) +{ + uint32_t mor = PMC->CKGR_MOR; + mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN); + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | mor; +} + +/** + * \brief Check if the main crystal is bypassed. + * + * \retval 0 Xtal is bypassed, otherwise not. + */ +uint32_t pmc_osc_is_bypassed_main_xtal(void) +{ + return (PMC->CKGR_MOR & CKGR_MOR_MOSCXTBY); +} + +/** + * \brief Check if the main crystal is ready. + * + * \note If main crystal is bypassed, it's always ready. + * + * \retval 0 main crystal is not ready, otherwise ready. + */ +uint32_t pmc_osc_is_ready_main_xtal(void) +{ + return (PMC->PMC_SR & PMC_SR_MOSCXTS); +} + +/** + * \brief Switch main clock source selection to external Xtal/Bypass. + * + * \note The function may switch MCK to SCLK if MCK source is MAINCK to avoid + * any system crash. + * + * \note If used in Xtal mode, the Xtal is automatically enabled. + * + * \param ul_bypass 0 for Xtal, 1 for bypass. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +void pmc_switch_mainck_to_xtal(uint32_t ul_bypass, + uint32_t ul_xtal_startup_time) +{ + /* Enable Main Xtal oscillator */ + if (ul_bypass) { + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) | + CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTBY | + CKGR_MOR_MOSCSEL; + } else { + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) | + CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTEN | + CKGR_MOR_MOSCXTST(ul_xtal_startup_time); + /* Wait the Xtal to stabilize */ + while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)); + + PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCSEL; + } +} + +/** + * \brief Disable the external Xtal. + * + * \param ul_bypass 0 for Xtal, 1 for bypass. + */ +void pmc_osc_disable_xtal(uint32_t ul_bypass) +{ + /* Disable xtal oscillator */ + if (ul_bypass) { + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) | + CKGR_MOR_KEY_PASSWD; + } else { + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) | + CKGR_MOR_KEY_PASSWD; + } +} + +/** + * \brief Check if the MAINCK is ready. Depending on MOSCEL, MAINCK can be one + * of Xtal, bypass or internal RC. + * + * \retval 1 Xtal is ready. + * \retval 0 Xtal is not ready. + */ +uint32_t pmc_osc_is_ready_mainck(void) +{ + return PMC->PMC_SR & PMC_SR_MOSCSELS; +} + +/** + * \brief Select Main Crystal or internal RC as main clock source. + * + * \note This function will not enable/disable RC or Main Crystal. + * + * \param ul_xtal_rc 0 internal RC is selected, otherwise Main Crystal. + */ +void pmc_mainck_osc_select(uint32_t ul_xtal_rc) +{ + uint32_t mor = PMC->CKGR_MOR; + if (ul_xtal_rc) { + mor |= CKGR_MOR_MOSCSEL; + } else { + mor &= ~CKGR_MOR_MOSCSEL; + } + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | mor; +} + +/** + * \brief Enable PLLA clock. + * + * \param mula PLLA multiplier. + * \param pllacount PLLA counter. + * \param diva Divider. + */ +void pmc_enable_pllack(uint32_t mula, uint32_t pllacount, uint32_t diva) +{ + /* first disable the PLL to unlock the lock */ + pmc_disable_pllack(); + +#if (SAM4C || SAM4CM || SAM4CP || SAMG) + PMC->CKGR_PLLAR = CKGR_PLLAR_PLLAEN(diva) | + CKGR_PLLAR_PLLACOUNT(pllacount) | CKGR_PLLAR_MULA(mula); +#else + PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_DIVA(diva) | + CKGR_PLLAR_PLLACOUNT(pllacount) | CKGR_PLLAR_MULA(mula); +#endif + while ((PMC->PMC_SR & PMC_SR_LOCKA) == 0); +} + +/** + * \brief Disable PLLA clock. + */ +void pmc_disable_pllack(void) +{ +#if (SAM4C || SAM4CM || SAM4CP || SAMG) + PMC->CKGR_PLLAR = CKGR_PLLAR_MULA(0); +#else + PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0); +#endif +} + +/** + * \brief Is PLLA locked? + * + * \retval 0 Not locked. + * \retval 1 Locked. + */ +uint32_t pmc_is_locked_pllack(void) +{ + return (PMC->PMC_SR & PMC_SR_LOCKA); +} + +#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55) +/** + * \brief Enable PLLB clock. + * + * \param mulb PLLB multiplier. + * \param pllbcount PLLB counter. + * \param divb Divider. + */ +void pmc_enable_pllbck(uint32_t mulb, uint32_t pllbcount, uint32_t divb) +{ + /* first disable the PLL to unlock the lock */ + pmc_disable_pllbck(); + +#if SAMG55 + PMC->CKGR_PLLAR = CKGR_PLLAR_PLLAEN(divb) | + CKGR_PLLAR_PLLACOUNT(pllbcount) | CKGR_PLLAR_MULA(mulb); +#else + PMC->CKGR_PLLBR = + CKGR_PLLBR_DIVB(divb) | CKGR_PLLBR_PLLBCOUNT(pllbcount) + | CKGR_PLLBR_MULB(mulb); +#endif + while ((PMC->PMC_SR & PMC_SR_LOCKB) == 0); +} + +/** + * \brief Disable PLLB clock. + */ +void pmc_disable_pllbck(void) +{ + PMC->CKGR_PLLBR = CKGR_PLLBR_MULB(0); +} + +/** + * \brief Is PLLB locked? + * + * \retval 0 Not locked. + * \retval 1 Locked. + */ +uint32_t pmc_is_locked_pllbck(void) +{ + return (PMC->PMC_SR & PMC_SR_LOCKB); +} +#endif + +#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Enable UPLL clock. + */ +void pmc_enable_upll_clock(void) +{ + PMC->CKGR_UCKR = CKGR_UCKR_UPLLCOUNT(3) | CKGR_UCKR_UPLLEN; + + /* Wait UTMI PLL Lock Status */ + while (!(PMC->PMC_SR & PMC_SR_LOCKU)); +} + +/** + * \brief Disable UPLL clock. + */ +void pmc_disable_upll_clock(void) +{ + PMC->CKGR_UCKR &= ~CKGR_UCKR_UPLLEN; +} + +/** + * \brief Is UPLL locked? + * + * \retval 0 Not locked. + * \retval 1 Locked. + */ +uint32_t pmc_is_locked_upll(void) +{ + return (PMC->PMC_SR & PMC_SR_LOCKU); +} +#endif + +/** + * \brief Enable the specified peripheral clock. + * + * \note The ID must NOT be shifted (i.e., 1 << ID_xxx). + * + * \param ul_id Peripheral ID (ID_xxx). + * + * \retval 0 Success. + * \retval 1 Invalid parameter. + */ +uint32_t pmc_enable_periph_clk(uint32_t ul_id) +{ +#if defined(REG_PMC_PCR) && !SAMG55 + uint32_t pcr; + PMC->PMC_PCR = ul_id & 0x7F; + pcr = PMC->PMC_PCR | PMC_PCR_EN | PMC_PCR_CMD; + PMC->PMC_PCR = pcr; + return 0; +#else + if (ul_id > MAX_PERIPH_ID) { + return 1; + } + + if (ul_id < 32) { + if ((PMC->PMC_PCSR0 & (1u << ul_id)) != (1u << ul_id)) { + PMC->PMC_PCER0 = 1 << ul_id; + } +#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) + } else { + ul_id -= 32; + if ((PMC->PMC_PCSR1 & (1u << ul_id)) != (1u << ul_id)) { + PMC->PMC_PCER1 = 1 << ul_id; + } +#endif + } + + return 0; +#endif /* defined(REG_PMC_PCR) && !SAMG55 */ +} + +/** + * \brief Disable the specified peripheral clock. + * + * \note The ID must NOT be shifted (i.e., 1 << ID_xxx). + * + * \param ul_id Peripheral ID (ID_xxx). + * + * \retval 0 Success. + * \retval 1 Invalid parameter. + */ +uint32_t pmc_disable_periph_clk(uint32_t ul_id) +{ +#if defined(REG_PMC_PCR) && !SAMG55 + uint32_t pcr; + PMC->PMC_PCR = ul_id & 0x7F; + pcr = PMC->PMC_PCR | PMC_PCR_CMD; + PMC->PMC_PCR = pcr; + return 0; +#else + if (ul_id > MAX_PERIPH_ID) { + return 1; + } + + if (ul_id < 32) { + if ((PMC->PMC_PCSR0 & (1u << ul_id)) == (1u << ul_id)) { + PMC->PMC_PCDR0 = 1 << ul_id; + } +#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 \ + || SAMV70 || SAME70 || SAMS70) + } else { + ul_id -= 32; + if ((PMC->PMC_PCSR1 & (1u << ul_id)) == (1u << ul_id)) { + PMC->PMC_PCDR1 = 1 << ul_id; + } +#endif + } + return 0; +#endif /* defined(REG_PMC_PCR) && !SAMG55 */ +} + +/** + * \brief Enable all peripheral clocks. + */ +void pmc_enable_all_periph_clk(void) +{ + PMC->PMC_PCER0 = PMC_MASK_STATUS0; + while ((PMC->PMC_PCSR0 & PMC_MASK_STATUS0) != PMC_MASK_STATUS0); + +#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \ + || SAMV70 || SAME70 || SAMS70) + PMC->PMC_PCER1 = PMC_MASK_STATUS1; + while ((PMC->PMC_PCSR1 & PMC_MASK_STATUS1) != PMC_MASK_STATUS1); +#endif + +#if defined(REG_PMC_PCR) && !SAMG55 + for (uint32_t id = 64; id <= 0x7F; id ++) { + pmc_enable_periph_clk(id); + } +#endif +} + +/** + * \brief Disable all peripheral clocks. + */ +void pmc_disable_all_periph_clk(void) +{ + PMC->PMC_PCDR0 = PMC_MASK_STATUS0; + while ((PMC->PMC_PCSR0 & PMC_MASK_STATUS0) != 0); + +#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \ + || SAMV70 || SAME70 || SAMS70) + PMC->PMC_PCDR1 = PMC_MASK_STATUS1; + while ((PMC->PMC_PCSR1 & PMC_MASK_STATUS1) != 0); +#endif + +#if defined(REG_PMC_PCR) && !SAMG55 + for (uint32_t id = 64; id <= 0x7F; id ++) { + pmc_disable_periph_clk(id); + } +#endif +} + +/** + * \brief Check if the specified peripheral clock is enabled. + * + * \note The ID must NOT be shifted (i.e., 1 << ID_xxx). + * + * \param ul_id Peripheral ID (ID_xxx). + * + * \retval 0 Peripheral clock is disabled or unknown. + * \retval 1 Peripheral clock is enabled. + */ +uint32_t pmc_is_periph_clk_enabled(uint32_t ul_id) +{ +#if defined(REG_PMC_PCR) && !SAMG55 + PMC->PMC_PCR = ul_id & 0x7F; + return (PMC->PMC_PCR & PMC_PCR_EN) ? 1 : 0; +#else + if (ul_id > MAX_PERIPH_ID) { + return 0; + } + +#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \ + || SAMV70 || SAME70 || SAMS70) + if (ul_id < 32) { +#endif + if ((PMC->PMC_PCSR0 & (1u << ul_id))) { + return 1; + } else { + return 0; + } +#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \ + || SAMV70 || SAME70 || SAMS70) + } else { + ul_id -= 32; + if ((PMC->PMC_PCSR1 & (1u << ul_id))) { + return 1; + } else { + return 0; + } + } +#endif +#endif /* defined(REG_PMC_PCR) && !SAMG55 */ +} + +/** + * \brief Set the prescaler for the specified programmable clock. + * + * \param ul_id Peripheral ID. + * \param ul_pres Prescaler value. + */ +void pmc_pck_set_prescaler(uint32_t ul_id, uint32_t ul_pres) +{ + PMC->PMC_PCK[ul_id] = + (PMC->PMC_PCK[ul_id] & ~PMC_PCK_PRES_Msk) | ul_pres; + while ((PMC->PMC_SCER & (PMC_SCER_PCK0 << ul_id)) + && !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id))); +} + +/** + * \brief Set the source oscillator for the specified programmable clock. + * + * \param ul_id Peripheral ID. + * \param ul_source Source selection value. + */ +void pmc_pck_set_source(uint32_t ul_id, uint32_t ul_source) +{ + PMC->PMC_PCK[ul_id] = + (PMC->PMC_PCK[ul_id] & ~PMC_PCK_CSS_Msk) | ul_source; + while ((PMC->PMC_SCER & (PMC_SCER_PCK0 << ul_id)) + && !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id))); +} + +/** + * \brief Switch programmable clock source selection to slow clock. + * + * \param ul_id Id of the programmable clock. + * \param ul_pres Programmable clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_pck_to_sclk(uint32_t ul_id, uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_SLOW_CLK | ul_pres; + for (ul_timeout = PMC_TIMEOUT; + !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} + +/** + * \brief Switch programmable clock source selection to main clock. + * + * \param ul_id Id of the programmable clock. + * \param ul_pres Programmable clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_pck_to_mainck(uint32_t ul_id, uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_MAIN_CLK | ul_pres; + for (ul_timeout = PMC_TIMEOUT; + !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} + +/** + * \brief Switch programmable clock source selection to PLLA clock. + * + * \param ul_id Id of the programmable clock. + * \param ul_pres Programmable clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_pck_to_pllack(uint32_t ul_id, uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_PLLA_CLK | ul_pres; + for (ul_timeout = PMC_TIMEOUT; + !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} + +#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55) +/** + * \brief Switch programmable clock source selection to PLLB clock. + * + * \param ul_id Id of the programmable clock. + * \param ul_pres Programmable clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_pck_to_pllbck(uint32_t ul_id, uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_PLLB_CLK | ul_pres; + for (ul_timeout = PMC_TIMEOUT; + !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} +#endif + +#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Switch programmable clock source selection to UPLL clock. + * + * \param ul_id Id of the programmable clock. + * \param ul_pres Programmable clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_pck_to_upllck(uint32_t ul_id, uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_UPLL_CLK | ul_pres; + for (ul_timeout = PMC_TIMEOUT; + !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} +#endif + +/** + * \brief Switch programmable clock source selection to mck. + * + * \param ul_id Id of the programmable clock. + * \param ul_pres Programmable clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_pck_to_mck(uint32_t ul_id, uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_MCK | ul_pres; + for (ul_timeout = PMC_TIMEOUT; + !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} + +/** + * \brief Enable the specified programmable clock. + * + * \param ul_id Id of the programmable clock. + */ +void pmc_enable_pck(uint32_t ul_id) +{ + PMC->PMC_SCER = PMC_SCER_PCK0 << ul_id; +} + +/** + * \brief Disable the specified programmable clock. + * + * \param ul_id Id of the programmable clock. + */ +void pmc_disable_pck(uint32_t ul_id) +{ + PMC->PMC_SCDR = PMC_SCER_PCK0 << ul_id; +} + +/** + * \brief Enable all programmable clocks. + */ +void pmc_enable_all_pck(void) +{ + PMC->PMC_SCER = PMC_SCER_PCK0 | PMC_SCER_PCK1 | PMC_SCER_PCK2; +} + +/** + * \brief Disable all programmable clocks. + */ +void pmc_disable_all_pck(void) +{ + PMC->PMC_SCDR = PMC_SCDR_PCK0 | PMC_SCDR_PCK1 | PMC_SCDR_PCK2; +} + +/** + * \brief Check if the specified programmable clock is enabled. + * + * \param ul_id Id of the programmable clock. + * + * \retval 0 Programmable clock is disabled or unknown. + * \retval 1 Programmable clock is enabled. + */ +uint32_t pmc_is_pck_enabled(uint32_t ul_id) +{ + if (ul_id > 2) { + return 0; + } + + return (PMC->PMC_SCSR & (PMC_SCSR_PCK0 << ul_id)); +} + +#if (SAM4C || SAM4CM || SAM4CP) +/** + * \brief Enable Coprocessor Clocks. + */ +void pmc_enable_cpck(void) +{ + PMC->PMC_SCER = PMC_SCER_CPCK | PMC_SCER_CPKEY_PASSWD; +} + +/** + * \brief Disable Coprocessor Clocks. + */ +void pmc_disable_cpck(void) +{ + PMC->PMC_SCDR = PMC_SCDR_CPCK | PMC_SCDR_CPKEY_PASSWD; +} + +/** + * \brief Check if the Coprocessor Clocks is enabled. + * + * \retval 0 Coprocessor Clocks is disabled. + * \retval 1 Coprocessor Clocks is enabled. + */ +bool pmc_is_cpck_enabled(void) +{ + if(PMC->PMC_SCSR & PMC_SCSR_CPCK) { + return 1; + } else { + return 0; + } +} + +/** + * \brief Enable Coprocessor Bus Master Clocks. + */ +void pmc_enable_cpbmck(void) +{ + PMC->PMC_SCER = PMC_SCER_CPBMCK | PMC_SCER_CPKEY_PASSWD; +} + +/** + * \brief Disable Coprocessor Bus Master Clocks. + */ +void pmc_disable_cpbmck(void) +{ + PMC->PMC_SCDR = PMC_SCDR_CPBMCK | PMC_SCDR_CPKEY_PASSWD; +} + +/** + * \brief Check if the Coprocessor Bus Master Clocks is enabled. + * + * \retval 0 Coprocessor Bus Master Clocks is disabled. + * \retval 1 Coprocessor Bus Master Clocks is enabled. + */ +bool pmc_is_cpbmck_enabled(void) +{ + if(PMC->PMC_SCSR & PMC_SCSR_CPBMCK) { + return 1; + } else { + return 0; + } +} + +/** + * \brief Set the prescaler for the Coprocessor Master Clock. + * + * \param ul_pres Prescaler value. + */ +void pmc_cpck_set_prescaler(uint32_t ul_pres) +{ + PMC->PMC_MCKR = + (PMC->PMC_MCKR & (~PMC_MCKR_CPPRES_Msk)) | PMC_MCKR_CPPRES(ul_pres); +} + +/** + * \brief Set the source for the Coprocessor Master Clock. + * + * \param ul_source Source selection value. + */ +void pmc_cpck_set_source(uint32_t ul_source) +{ + PMC->PMC_MCKR = + (PMC->PMC_MCKR & (~PMC_MCKR_CPCSS_Msk)) | ul_source; +} +#endif + +#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Switch UDP (USB) clock source selection to PLLA clock. + * + * \param ul_usbdiv Clock divisor. + */ +void pmc_switch_udpck_to_pllack(uint32_t ul_usbdiv) +{ + PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv); +} +#endif + +#if (SAM3S || SAM4S || SAMG55) +/** + * \brief Switch UDP (USB) clock source selection to PLLB clock. + * + * \param ul_usbdiv Clock divisor. + */ +void pmc_switch_udpck_to_pllbck(uint32_t ul_usbdiv) +{ + PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv) | PMC_USB_USBS; +} +#endif + +#if (SAM3XA || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Switch UDP (USB) clock source selection to UPLL clock. + * + * \param ul_usbdiv Clock divisor. + */ +void pmc_switch_udpck_to_upllck(uint32_t ul_usbdiv) +{ + PMC->PMC_USB = PMC_USB_USBS | PMC_USB_USBDIV(ul_usbdiv); +} +#endif + +#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Enable UDP (USB) clock. + */ +void pmc_enable_udpck(void) +{ +#if (SAM3S || SAM4S || SAM4E || SAMG55) + PMC->PMC_SCER = PMC_SCER_UDP; +#elif (SAMV71 || SAMV70 || SAME70 || SAMS70) + PMC->PMC_SCER = PMC_SCER_USBCLK; +#else + PMC->PMC_SCER = PMC_SCER_UOTGCLK; +# endif +} + +/** + * \brief Disable UDP (USB) clock. + */ +void pmc_disable_udpck(void) +{ +#if (SAM3S || SAM4S || SAM4E || SAMG55) + PMC->PMC_SCDR = PMC_SCDR_UDP; +#elif (SAMV71 || SAMV70 || SAME70 || SAMS70) + PMC->PMC_SCDR = PMC_SCDR_USBCLK; +#else + PMC->PMC_SCDR = PMC_SCDR_UOTGCLK; +# endif +} +#endif + +#if SAMG55 +/** + * \brief Switch UHP (USB) clock source selection to PLLA clock. + * + * \param ul_usbdiv Clock divisor. + */ +void pmc_switch_uhpck_to_pllack(uint32_t ul_usbdiv) +{ + PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv); +} + +/** + * \brief Switch UHP (USB) clock source selection to PLLB clock. + * + * \param ul_usbdiv Clock divisor. + */ +void pmc_switch_uhpck_to_pllbck(uint32_t ul_usbdiv) +{ + PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv) | PMC_USB_USBS; +} + +/** + * \brief Enable UHP (USB) clock. + */ +void pmc_enable_uhpck(void) +{ + PMC->PMC_SCER = PMC_SCER_UHP; +} +#endif + +/** + * \brief Enable PMC interrupts. + * + * \param ul_sources Interrupt sources bit map. + */ +void pmc_enable_interrupt(uint32_t ul_sources) +{ + PMC->PMC_IER = ul_sources; +} + +/** + * \brief Disable PMC interrupts. + * + * \param ul_sources Interrupt sources bit map. + */ +void pmc_disable_interrupt(uint32_t ul_sources) +{ + PMC->PMC_IDR = ul_sources; +} + +/** + * \brief Get PMC interrupt mask. + * + * \return The interrupt mask value. + */ +uint32_t pmc_get_interrupt_mask(void) +{ + return PMC->PMC_IMR; +} + +/** + * \brief Get current status. + * + * \return The current PMC status. + */ +uint32_t pmc_get_status(void) +{ + return PMC->PMC_SR; +} + +/** + * \brief Set the wake-up inputs for fast startup mode registers + * (event generation). + * + * \param ul_inputs Wake up inputs to enable. + */ +void pmc_set_fast_startup_input(uint32_t ul_inputs) +{ + ul_inputs &= PMC_FAST_STARTUP_Msk; + PMC->PMC_FSMR |= ul_inputs; +} + +/** + * \brief Clear the wake-up inputs for fast startup mode registers + * (remove event generation). + * + * \param ul_inputs Wake up inputs to disable. + */ +void pmc_clr_fast_startup_input(uint32_t ul_inputs) +{ + ul_inputs &= PMC_FAST_STARTUP_Msk; + PMC->PMC_FSMR &= ~ul_inputs; +} + +#if (SAM4C || SAM4CM || SAM4CP) +/** + * \brief Set the wake-up inputs of coprocessor for fast startup mode registers + * (event generation). + * + * \param ul_inputs Wake up inputs to enable. + */ +void pmc_cp_set_fast_startup_input(uint32_t ul_inputs) +{ + ul_inputs &= PMC_FAST_STARTUP_Msk; + PMC->PMC_CPFSMR |= ul_inputs; +} + +/** + * \brief Clear the wake-up inputs of coprocessor for fast startup mode registers + * (remove event generation). + * + * \param ul_inputs Wake up inputs to disable. + */ +void pmc_cp_clr_fast_startup_input(uint32_t ul_inputs) +{ + ul_inputs &= PMC_FAST_STARTUP_Msk; + PMC->PMC_CPFSMR &= ~ul_inputs; +} +#endif + +/** + * \brief Enable Sleep Mode. + * Enter condition: (WFE or WFI) + (SLEEPDEEP bit = 0) + (LPM bit = 0) + * + * \param uc_type 0 for wait for interrupt, 1 for wait for event. + * \note For SAM4S, SAM4C, SAM4CM, SAM4CP, SAMV71 and SAM4E series, + * since only WFI is effective, uc_type = 1 will be treated as uc_type = 0. + */ +void pmc_enable_sleepmode(uint8_t uc_type) +{ +#if !(SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70) + PMC->PMC_FSMR &= (uint32_t) ~ PMC_FSMR_LPM; // Enter Sleep mode +#endif + SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; // Deep sleep + +#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70) + UNUSED(uc_type); + __DSB(); + __WFI(); +#else + if (uc_type == 0) { + __DSB(); + __WFI(); + } else { + __DSB(); + __WFE(); + } +#endif +} + +#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70) +static uint32_t ul_flash_in_wait_mode = PMC_WAIT_MODE_FLASH_DEEP_POWERDOWN; +/** + * \brief Set the embedded flash state in wait mode + * + * \param ul_flash_state PMC_WAIT_MODE_FLASH_STANDBY flash in standby mode, + * PMC_WAIT_MODE_FLASH_DEEP_POWERDOWN flash in deep power down mode. + */ +void pmc_set_flash_in_wait_mode(uint32_t ul_flash_state) +{ + ul_flash_in_wait_mode = ul_flash_state; +} + +/** + * \brief Enable Wait Mode. Enter condition: (WAITMODE bit = 1) + FLPM + * + * \note In this function, FLPM will retain, WAITMODE bit will be set, + * Generally, this function will be called by pmc_sleep() in order to + * complete all sequence entering wait mode. + * See \ref pmc_sleep() for entering different sleep modes. + */ +void pmc_enable_waitmode(void) +{ + uint32_t i; + + /* Flash in wait mode */ + i = PMC->PMC_FSMR; + i &= ~PMC_FSMR_FLPM_Msk; +#if !(SAMV71 || SAMV70 || SAME70 || SAMS70) + i |= ul_flash_in_wait_mode; +#else + (void)ul_flash_in_wait_mode; + i |= PMC_WAIT_MODE_FLASH_IDLE; +#endif + PMC->PMC_FSMR = i; + + /* Set the WAITMODE bit = 1 */ + PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_WAITMODE; + + /* Waiting for Master Clock Ready MCKRDY = 1 */ + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); + + /* Waiting for MOSCRCEN bit cleared is strongly recommended + * to ensure that the core will not execute undesired instructions + */ + for (i = 0; i < 500; i++) { + __NOP(); + } + while (!(PMC->CKGR_MOR & CKGR_MOR_MOSCRCEN)); + +#if (!SAMG) + /* Restore Flash in idle mode */ + i = PMC->PMC_FSMR; + i &= ~PMC_FSMR_FLPM_Msk; + i |= PMC_WAIT_MODE_FLASH_IDLE; + PMC->PMC_FSMR = i; +#endif +} +#else +/** + * \brief Enable Wait Mode. Enter condition: WFE + (SLEEPDEEP bit = 0) + + * (LPM bit = 1) + */ +void pmc_enable_waitmode(void) +{ + uint32_t i; + + PMC->PMC_FSMR |= PMC_FSMR_LPM; /* Enter Wait mode */ + SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; /* Deep sleep */ + + __DSB(); + __WFE(); + + /* Waiting for MOSCRCEN bit cleared is strongly recommended + * to ensure that the core will not execute undesired instructions + */ + for (i = 0; i < 500; i++) { + __NOP(); + } + while (!(PMC->CKGR_MOR & CKGR_MOR_MOSCRCEN)); + +} +#endif + +#if (!(SAMG51 || SAMG53 || SAMG54)) +/** + * \brief Enable Backup Mode. Enter condition: WFE/(VROFF bit = 1) + + * (SLEEPDEEP bit = 1) + */ +void pmc_enable_backupmode(void) +{ +#if (SAM4C || SAM4CM || SAM4CP) + uint32_t tmp = SUPC->SUPC_MR & ~(SUPC_MR_BUPPOREN | SUPC_MR_KEY_Msk); + SUPC->SUPC_MR = tmp | SUPC_MR_KEY_PASSWD; + while (SUPC->SUPC_SR & SUPC_SR_BUPPORS); +#endif + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; +#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) + SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_VROFF_STOP_VREG; + uint32_t ul_dummy = SUPC->SUPC_MR; + UNUSED(ul_dummy); + __DSB(); + __WFE(); + __WFI(); +#else + __DSB(); + __WFE(); +#endif +} +#endif + +/** + * \brief Enable Clock Failure Detector. + */ +void pmc_enable_clock_failure_detector(void) +{ + uint32_t ul_reg = PMC->CKGR_MOR; + + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | CKGR_MOR_CFDEN | ul_reg; +} + +/** + * \brief Disable Clock Failure Detector. + */ +void pmc_disable_clock_failure_detector(void) +{ + uint32_t ul_reg = PMC->CKGR_MOR & (~CKGR_MOR_CFDEN); + + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | ul_reg; +} + +#if (SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Enable Slow Crystal Oscillator Frequency Monitoring. + */ +void pmc_enable_sclk_osc_freq_monitor(void) +{ + uint32_t ul_reg = PMC->CKGR_MOR; + + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | CKGR_MOR_XT32KFME | ul_reg; +} + +/** + * \brief Disable Slow Crystal Oscillator Frequency Monitoring. + */ +void pmc_disable_sclk_osc_freq_monitor(void) +{ + uint32_t ul_reg = PMC->CKGR_MOR & (~CKGR_MOR_XT32KFME); + + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | ul_reg; +} +#endif + +/** + * \brief Enable or disable write protect of PMC registers. + * + * \param ul_enable 1 to enable, 0 to disable. + */ +void pmc_set_writeprotect(uint32_t ul_enable) +{ + if (ul_enable) { + PMC->PMC_WPMR = PMC_WPMR_WPKEY_PASSWD | PMC_WPMR_WPEN; + } else { + PMC->PMC_WPMR = PMC_WPMR_WPKEY_PASSWD; + } +} + +/** + * \brief Return write protect status. + * + * \return Return write protect status. + */ +uint32_t pmc_get_writeprotect_status(void) +{ + return PMC->PMC_WPSR; +} + +#if (SAMG53 || SAMG54 || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Enable the specified peripheral clock. + * + * \note The ID must NOT be shifted (i.e., 1 << ID_xxx). + * + * \param ul_id Peripheral ID (ID_xxx). + * + * \retval 0 Success. + * \retval 1 Fail. + */ +uint32_t pmc_enable_sleepwalking(uint32_t ul_id) +{ + uint32_t temp; +#if (SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) + if ((7 <= ul_id) && (ul_id<= 29)) { +#else + if ((8 <= ul_id) && (ul_id<= 29)) { +#endif + temp = pmc_get_active_status0(); + if (temp & (1 << ul_id)) { + return 1; + } + PMC->PMC_SLPWK_ER0 = 1 << ul_id; + temp = pmc_get_active_status0(); + if (temp & (1 << ul_id)) { + pmc_disable_sleepwalking(ul_id); + return 1; + } + return 0; + } +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) + else if ((32 <= ul_id) && (ul_id<= 60)) { + ul_id -= 32; + temp = pmc_get_active_status1(); + if (temp & (1 << ul_id)) { + return 1; + } + PMC->PMC_SLPWK_ER1 = 1 << ul_id; + temp = pmc_get_active_status1(); + if (temp & (1 << ul_id)) { + pmc_disable_sleepwalking(ul_id); + return 1; + } + return 0; + } +#endif + else { + return 1; + } +} + +/** + * \brief Disable the sleepwalking of specified peripheral. + * + * \note The ID must NOT be shifted (i.e., 1 << ID_xxx). + * + * \param ul_id Peripheral ID (ID_xxx). + * + * \retval 0 Success. + * \retval 1 Invalid parameter. + */ +uint32_t pmc_disable_sleepwalking(uint32_t ul_id) +{ +#if (SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) + if ((7 <= ul_id) && (ul_id<= 29)) { +#else + if ((8 <= ul_id) && (ul_id<= 29)) { +#endif + PMC->PMC_SLPWK_DR0 = 1 << ul_id; + return 0; + } +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) + else if ((32 <= ul_id) && (ul_id<= 60)) { + ul_id -= 32; + PMC->PMC_SLPWK_DR1 = 1 << ul_id; + return 0; + } +#endif + else { + return 1; + } +} + +/** + * \brief Return peripheral sleepwalking enable status. + * + * \return the status register value. + */ +uint32_t pmc_get_sleepwalking_status0(void) +{ + return PMC->PMC_SLPWK_SR0; +} + +/** + * \brief Return peripheral active status. + * + * \return the status register value. + */ +uint32_t pmc_get_active_status0(void) +{ + return PMC->PMC_SLPWK_ASR0; +} + +#endif + +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Return peripheral sleepwalking enable status. + * + * \return the status register value. + */ +uint32_t pmc_get_sleepwalking_status1(void) +{ + return PMC->PMC_SLPWK_SR1; +} + +/** + * \brief Return peripheral active status. + * + * \return the status register value. + */ +uint32_t pmc_get_active_status1(void) +{ + return PMC->PMC_SLPWK_ASR1; +} +#endif + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/pmc/pmc.h b/hw-libs/drivers/SAMx70/ASF/sam/drivers/pmc/pmc.h new file mode 100644 index 000000000..22249f71d --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/pmc/pmc.h @@ -0,0 +1,540 @@ +/** + * \file + * + * \brief Power Management Controller (PMC) driver for SAM. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef PMC_H_INCLUDED +#define PMC_H_INCLUDED + +#include "compiler.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** Bit mask for peripheral clocks (PCER0) */ +#define PMC_MASK_STATUS0 (0xFFFFFFFC) + +/** Bit mask for peripheral clocks (PCER1) */ +#define PMC_MASK_STATUS1 (0xFFFFFFFF) + +/** Loop counter timeout value */ +#if !(SAME70) +#define PMC_TIMEOUT (2048) +#else +#define PMC_TIMEOUT (4096) +#endif + +/** Key to unlock CKGR_MOR register */ +#ifndef CKGR_MOR_KEY_PASSWD +#define CKGR_MOR_KEY_PASSWD CKGR_MOR_KEY(0x37U) +#endif + +/** Key used to write SUPC registers */ +#ifndef SUPC_CR_KEY_PASSWD +#define SUPC_CR_KEY_PASSWD SUPC_CR_KEY(0xA5U) +#endif + +#ifndef SUPC_MR_KEY_PASSWD +#define SUPC_MR_KEY_PASSWD SUPC_MR_KEY(0xA5U) +#endif + +/** Mask to access fast startup input */ +#define PMC_FAST_STARTUP_Msk (0x7FFFFu) + +/** PMC_WPMR Write Protect KEY, unlock it */ +#ifndef PMC_WPMR_WPKEY_PASSWD +#define PMC_WPMR_WPKEY_PASSWD PMC_WPMR_WPKEY((uint32_t) 0x504D43) +#endif + +/** Using external oscillator */ +#define PMC_OSC_XTAL 0 + +/** Oscillator in bypass mode */ +#define PMC_OSC_BYPASS 1 + +#define PMC_PCK_0 0 /* PCK0 ID */ +#define PMC_PCK_1 1 /* PCK1 ID */ +#define PMC_PCK_2 2 /* PCK2 ID */ +#if (SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) +#define PMC_PCK_3 3 /* PCK3 ID */ +#define PMC_PCK_4 4 /* PCK4 ID */ +#define PMC_PCK_5 5 /* PCK5 ID */ +#define PMC_PCK_6 6 /* PCK6 ID */ +#if SAMG55 +#define PMC_PCK_7 7 /* PCK7 ID */ +#endif +#endif + +#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** Flash state in Wait Mode */ +#define PMC_WAIT_MODE_FLASH_STANDBY PMC_FSMR_FLPM_FLASH_STANDBY +#define PMC_WAIT_MODE_FLASH_DEEP_POWERDOWN PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN +#define PMC_WAIT_MODE_FLASH_IDLE PMC_FSMR_FLPM_FLASH_IDLE +#endif + +/** Convert startup time from us to MOSCXTST */ +#define pmc_us_to_moscxtst(startup_us, slowck_freq) \ + ((startup_us * slowck_freq / 8 / 1000000) < 0x100 ? \ + (startup_us * slowck_freq / 8 / 1000000) : 0xFF) + +/** + * \name Master clock (MCK) Source and Prescaler configuration + * + * \note The following functions may be used to select the clock source and + * prescaler for the master clock. + */ +//@{ + +void pmc_mck_set_prescaler(uint32_t ul_pres); +#if SAMV71 || SAMV70 || SAME70 || SAMS70 +void pmc_mck_set_division(uint32_t ul_div); +#endif +void pmc_mck_set_source(uint32_t ul_source); +uint32_t pmc_switch_mck_to_sclk(uint32_t ul_pres); +uint32_t pmc_switch_mck_to_mainck(uint32_t ul_pres); +uint32_t pmc_switch_mck_to_pllack(uint32_t ul_pres); +#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55) +uint32_t pmc_switch_mck_to_pllbck(uint32_t ul_pres); +#endif +#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70) +uint32_t pmc_switch_mck_to_upllck(uint32_t ul_pres); +#endif +#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70) +void pmc_set_flash_in_wait_mode(uint32_t ul_flash_state); +#endif + + +//@} + +/** + * \name Slow clock (SLCK) oscillator and configuration + * + */ +//@{ + +void pmc_switch_sclk_to_32kxtal(uint32_t ul_bypass); +uint32_t pmc_osc_is_ready_32kxtal(void); + +//@} + +/** + * \name Main Clock (MAINCK) oscillator and configuration + * + */ +//@{ + +void pmc_switch_mainck_to_fastrc(uint32_t ul_moscrcf); +void pmc_osc_enable_fastrc(uint32_t ul_rc); +void pmc_osc_disable_fastrc(void); +uint32_t pmc_osc_is_ready_fastrc(void); +void pmc_osc_enable_main_xtal(uint32_t ul_xtal_startup_time); +void pmc_osc_bypass_main_xtal(void); +void pmc_osc_disable_main_xtal(void); +uint32_t pmc_osc_is_bypassed_main_xtal(void); +uint32_t pmc_osc_is_ready_main_xtal(void); +void pmc_switch_mainck_to_xtal(uint32_t ul_bypass, + uint32_t ul_xtal_startup_time); +void pmc_osc_disable_xtal(uint32_t ul_bypass); +uint32_t pmc_osc_is_ready_mainck(void); +void pmc_mainck_osc_select(uint32_t ul_xtal_rc); + +//@} + +/** + * \name PLL oscillator and configuration + * + */ +//@{ + +void pmc_enable_pllack(uint32_t mula, uint32_t pllacount, uint32_t diva); +void pmc_disable_pllack(void); +uint32_t pmc_is_locked_pllack(void); + +#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55) +void pmc_enable_pllbck(uint32_t mulb, uint32_t pllbcount, uint32_t divb); +void pmc_disable_pllbck(void); +uint32_t pmc_is_locked_pllbck(void); +#endif + +#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70) +void pmc_enable_upll_clock(void); +void pmc_disable_upll_clock(void); +uint32_t pmc_is_locked_upll(void); +#endif + +//@} + +/** + * \name Peripherals clock configuration + * + */ +//@{ + +uint32_t pmc_enable_periph_clk(uint32_t ul_id); +uint32_t pmc_disable_periph_clk(uint32_t ul_id); +void pmc_enable_all_periph_clk(void); +void pmc_disable_all_periph_clk(void); +uint32_t pmc_is_periph_clk_enabled(uint32_t ul_id); + +//@} + +/** + * \name Programmable clock Source and Prescaler configuration + * + * The following functions may be used to select the clock source and + * prescaler for the specified programmable clock. + */ +//@{ + +void pmc_pck_set_prescaler(uint32_t ul_id, uint32_t ul_pres); +void pmc_pck_set_source(uint32_t ul_id, uint32_t ul_source); +uint32_t pmc_switch_pck_to_sclk(uint32_t ul_id, uint32_t ul_pres); +uint32_t pmc_switch_pck_to_mainck(uint32_t ul_id, uint32_t ul_pres); +uint32_t pmc_switch_pck_to_pllack(uint32_t ul_id, uint32_t ul_pres); +#if (SAM4C || SAM4CM || SAM4CP) +void pmc_enable_cpck(void); +void pmc_disable_cpck(void); +bool pmc_is_cpck_enabled(void); +void pmc_enable_cpbmck(void); +void pmc_disable_cpbmck(void); +bool pmc_is_cpbmck_enabled(void); +void pmc_cpck_set_prescaler(uint32_t ul_pres); +void pmc_cpck_set_source(uint32_t ul_source); +#endif +#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55) +uint32_t pmc_switch_pck_to_pllbck(uint32_t ul_id, uint32_t ul_pres); +#endif +#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70) +uint32_t pmc_switch_pck_to_upllck(uint32_t ul_id, uint32_t ul_pres); +#endif +uint32_t pmc_switch_pck_to_mck(uint32_t ul_id, uint32_t ul_pres); +void pmc_enable_pck(uint32_t ul_id); +void pmc_disable_pck(uint32_t ul_id); +void pmc_enable_all_pck(void); +void pmc_disable_all_pck(void); +uint32_t pmc_is_pck_enabled(uint32_t ul_id); + +//@} + +/** + * \name USB clock configuration + * + */ +//@{ + +#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) +void pmc_switch_udpck_to_pllack(uint32_t ul_usbdiv); +#endif +#if (SAM3S || SAM4S || SAMG55) +void pmc_switch_udpck_to_pllbck(uint32_t ul_usbdiv); +#endif +#if (SAM3XA || SAMV71 || SAMV70 || SAME70 || SAMS70) +void pmc_switch_udpck_to_upllck(uint32_t ul_usbdiv); +#endif +#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) +void pmc_enable_udpck(void); +void pmc_disable_udpck(void); +#endif +#if SAMG55 +void pmc_switch_uhpck_to_pllack(uint32_t ul_usbdiv); +void pmc_switch_uhpck_to_pllbck(uint32_t ul_usbdiv); +void pmc_enable_uhpck(void); +#endif + +//@} + +/** + * \name Interrupt and status management + * + */ +//@{ + +void pmc_enable_interrupt(uint32_t ul_sources); +void pmc_disable_interrupt(uint32_t ul_sources); +uint32_t pmc_get_interrupt_mask(void); +uint32_t pmc_get_status(void); + +//@} + +/** + * \name Power management + * + * The following functions are used to configure sleep mode and additional + * wake up inputs. + */ +//@{ + +void pmc_set_fast_startup_input(uint32_t ul_inputs); +void pmc_clr_fast_startup_input(uint32_t ul_inputs); +#if (SAM4C || SAM4CM || SAM4CP) +void pmc_cp_set_fast_startup_input(uint32_t ul_inputs); +void pmc_cp_clr_fast_startup_input(uint32_t ul_inputs); +#endif +void pmc_enable_sleepmode(uint8_t uc_type); +void pmc_enable_waitmode(void); +#if (!(SAMG51 || SAMG53 || SAMG54)) +void pmc_enable_backupmode(void); +#endif +//@} + +/** + * \name Failure detector + * + */ +//@{ + +void pmc_enable_clock_failure_detector(void); +void pmc_disable_clock_failure_detector(void); + +//@} + +#if (SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \name Slow Crystal Oscillator Frequency Monitoring + * + */ +//@{ + +void pmc_enable_sclk_osc_freq_monitor(void); +void pmc_disable_sclk_osc_freq_monitor(void); + +//@} +#endif + +/** + * \name Write protection + * + */ +//@{ + +void pmc_set_writeprotect(uint32_t ul_enable); +uint32_t pmc_get_writeprotect_status(void); + +//@} + +#if (SAMG53 || SAMG54 || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \name Sleepwalking configuration + * + */ +//@{ + +uint32_t pmc_enable_sleepwalking(uint32_t ul_id); +uint32_t pmc_disable_sleepwalking(uint32_t ul_id); +uint32_t pmc_get_sleepwalking_status0(void); +uint32_t pmc_get_active_status0(void); +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) +uint32_t pmc_get_sleepwalking_status1(void); +uint32_t pmc_get_active_status1(void); +#endif +//@} +#endif + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +//! @} + +/** + * \page sam_pmc_quickstart Quick start guide for the SAM PMC module + * + * This is the quick start guide for the \ref sam_drivers_pmc_group "PMC module", + * with step-by-step instructions on how to configure and use the driver in a + * selection of use cases. + * + * The use cases contain several code fragments. The code fragments in the + * steps for setup can be copied into a custom initialization function, while + * the steps for usage can be copied into, e.g., the main application function. + * + * \section pmc_use_cases PMC use cases + * - \ref pmc_basic_use_case Basic use case - Switch Main Clock sources + * - \ref pmc_use_case_2 Advanced use case - Configure Programmable Clocks + * + * \section pmc_basic_use_case Basic use case - Switch Main Clock sources + * In this use case, the PMC module is configured for a variety of system clock + * sources and speeds. A LED is used to visually indicate the current clock + * speed as the source is switched. + * + * \section pmc_basic_use_case_setup Setup + * + * \subsection pmc_basic_use_case_setup_prereq Prerequisites + * -# \ref gpio_group "General Purpose I/O Management (gpio)" + * + * \subsection pmc_basic_use_case_setup_code Code + * The following function needs to be added to the user application, to flash a + * board LED a variable number of times at a rate given in CPU ticks. + * + * \code + #define FLASH_TICK_COUNT 0x00012345 + + void flash_led(uint32_t tick_count, uint8_t flash_count) + { + SysTick->CTRL = SysTick_CTRL_ENABLE_Msk; + SysTick->LOAD = tick_count; + + while (flash_count--) + { + gpio_toggle_pin(LED0_GPIO); + while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)); + gpio_toggle_pin(LED0_GPIO); + while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)); + } + } +\endcode + * + * \section pmc_basic_use_case_usage Use case + * + * \subsection pmc_basic_use_case_usage_code Example code + * Add to application C-file: + * \code + for (;;) + { + pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz); + flash_led(FLASH_TICK_COUNT, 5); + pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz); + flash_led(FLASH_TICK_COUNT, 5); + pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz); + flash_led(FLASH_TICK_COUNT, 5); + pmc_switch_mainck_to_xtal(0); + flash_led(FLASH_TICK_COUNT, 5); + } +\endcode + * + * \subsection pmc_basic_use_case_usage_flow Workflow + * -# Wrap the code in an infinite loop: + * \code + for (;;) +\endcode + * -# Switch the Master CPU frequency to the internal 12MHz RC oscillator, flash + * a LED on the board several times: + * \code + pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz); + flash_led(FLASH_TICK_COUNT, 5); +\endcode + * -# Switch the Master CPU frequency to the internal 8MHz RC oscillator, flash + * a LED on the board several times: + * \code + pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz); + flash_led(FLASH_TICK_COUNT, 5); +\endcode + * -# Switch the Master CPU frequency to the internal 4MHz RC oscillator, flash + * a LED on the board several times: + * \code + pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz); + flash_led(FLASH_TICK_COUNT, 5); +\endcode + * -# Switch the Master CPU frequency to the external crystal oscillator, flash + * a LED on the board several times: + * \code + pmc_switch_mainck_to_xtal(0, BOARD_OSC_STARTUP_US); + flash_led(FLASH_TICK_COUNT, 5); +\endcode + * + * \section pmc_use_case_2 Use case #2 - Configure Programmable Clocks + * In this use case, the PMC module is configured to start the Slow Clock from + * an attached 32KHz crystal, and start one of the Programmable Clock modules + * sourced from the Slow Clock divided down with a prescale factor of 64. + * + * \section pmc_use_case_2_setup Setup + * + * \subsection pmc_use_case_2_setup_prereq Prerequisites + * -# \ref pio_group "Parallel Input/Output Controller (pio)" + * + * \subsection pmc_use_case_2_setup_code Code + * The following code must be added to the user application: + * \code + pio_set_peripheral(PIOA, PIO_PERIPH_B, PIO_PA17); +\endcode + * + * \subsection pmc_use_case_2_setup_code_workflow Workflow + * -# Configure the PCK1 pin to output on a specific port pin (in this case, + * PIOA pin 17) of the microcontroller. + * \code + pio_set_peripheral(PIOA, PIO_PERIPH_B, PIO_PA17); +\endcode + * \note The peripheral selection and pin will vary according to your selected + * SAM device model. Refer to the "Peripheral Signal Multiplexing on I/O + * Lines" of your device's datasheet. + * + * \section pmc_use_case_2_usage Use case + * The generated PCK1 clock output can be viewed on an oscilloscope attached to + * the correct pin of the microcontroller. + * + * \subsection pmc_use_case_2_usage_code Example code + * Add to application C-file: + * \code + pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL); + pmc_switch_pck_to_sclk(PMC_PCK_1, PMC_PCK_PRES_CLK_64); + pmc_enable_pck(PMC_PCK_1); + + for (;;) + { + // Do Nothing + } +\endcode + * + * \subsection pmc_use_case_2_usage_flow Workflow + * -# Switch the Slow Clock source input to an external 32KHz crystal: + * \code + pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL); +\endcode + * -# Switch the Programmable Clock module PCK1 source clock to the Slow Clock, + * with a prescaler of 64: + * \code + pmc_switch_pck_to_sclk(PMC_PCK_1, PMC_PCK_PRES_CLK_64); +\endcode + * -# Enable Programmable Clock module PCK1: + * \code + pmc_enable_pck(PMC_PCK_1); +\endcode + * -# Enter an infinite loop: + * \code + for (;;) + { + // Do Nothing + } +\endcode + */ + +#endif /* PMC_H_INCLUDED */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/pmc/sleep.c b/hw-libs/drivers/SAMx70/ASF/sam/drivers/pmc/sleep.c new file mode 100644 index 000000000..62b76f828 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/pmc/sleep.c @@ -0,0 +1,383 @@ +/** + * \file + * + * \brief Sleep mode access + * + * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include +#include "sleep.h" + +/* SAM3,SAM4,SAMG,SAMV,SAMS and SAME series */ +#if (SAM3S || SAM3N || SAM3XA || SAM3U || SAM4S || SAM4E || SAM4N || SAM4C || \ + SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAMS70 || SAME70) +#include "pmc.h" +#include "ISBoards.h" + +#include "conf_clock.h" + +/* Checking board configuration of main clock xtal statup time */ +#if !defined(BOARD_OSC_STARTUP_US) +# warning The board main clock xtal statup time has not been defined. Using default settings. +# define BOARD_OSC_STARTUP_US (15625UL) +#endif + +#if !defined(EFC0) +# define EFC0 EFC +#endif + +/** + * Save clock settings and shutdown PLLs + */ +__always_inline static void pmc_save_clock_settings( + uint32_t *p_osc_setting, + uint32_t *p_pll0_setting, + uint32_t *p_pll1_setting, + uint32_t *p_mck_setting, + uint32_t *p_fmr_setting, +#if defined(EFC1) + uint32_t *p_fmr_setting1, +#endif + const bool disable_xtal) +{ + uint32_t mor = PMC->CKGR_MOR; + uint32_t mckr = PMC->PMC_MCKR; + uint32_t fmr = EFC0->EEFC_FMR; +# if defined(EFC1) + uint32_t fmr1 = EFC1->EEFC_FMR; +# endif + + if (p_osc_setting) { + *p_osc_setting = mor; + } + if (p_pll0_setting) { + *p_pll0_setting = PMC->CKGR_PLLAR; + } + if (p_pll1_setting) { +#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP) + *p_pll1_setting = PMC->CKGR_PLLBR; +#elif (SAM3U || SAM3XA) + *p_pll1_setting = PMC->CKGR_UCKR; +#else + *p_pll1_setting = 0; +#endif + } + if (p_mck_setting) { + *p_mck_setting = mckr; + } + if (p_fmr_setting) { + *p_fmr_setting = fmr; + } +#if defined(EFC1) + if (p_fmr_setting1) { + *p_fmr_setting1 = fmr1; + } +#endif + + /* Enable FAST RC */ + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | mor | CKGR_MOR_MOSCRCEN; + /* if MCK source is PLL, switch to mainck */ + if ((mckr & PMC_MCKR_CSS_Msk) > PMC_MCKR_CSS_MAIN_CLK) { + /* MCK -> MAINCK */ + mckr = (mckr & (~PMC_MCKR_CSS_Msk)) | PMC_MCKR_CSS_MAIN_CLK; + PMC->PMC_MCKR = mckr; + while(!(PMC->PMC_SR & PMC_SR_MCKRDY)); + } + /* MCK prescale -> 1 */ + if (mckr & PMC_MCKR_PRES_Msk) { + mckr = (mckr & (~PMC_MCKR_PRES_Msk)); + PMC->PMC_MCKR = mckr; + while(!(PMC->PMC_SR & PMC_SR_MCKRDY)); + } + /* Disable PLLs */ + pmc_disable_pllack(); +#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP) + pmc_disable_pllbck(); +#elif (SAM3U || SAM3XA) + pmc_disable_upll_clock(); +#endif + + /* Prepare for entering WAIT mode */ + /* Wait fast RC ready */ + while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)); + + /* Switch mainck to FAST RC */ +#if SAMG + /** + * For the sleepwalking feature, we need an accurate RC clock. Only 24M and + * 16M are trimmed in production. Here we select the 24M. + * And so wait state need to be 1. + */ + EFC0->EEFC_FMR = (fmr & (~EEFC_FMR_FWS_Msk)) | EEFC_FMR_FWS(1); + + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) | CKGR_MOR_MOSCRCF_24_MHz | + CKGR_MOR_KEY_PASSWD; +#else + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) | + CKGR_MOR_KEY_PASSWD; +#endif + while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)); + +#if (!SAMG) + /* FWS update */ + EFC0->EEFC_FMR = fmr & (~EEFC_FMR_FWS_Msk); +#if defined(EFC1) + EFC1->EEFC_FMR = fmr1 & (~EEFC_FMR_FWS_Msk); +#endif +#endif + + /* Disable XTALs */ + if (disable_xtal) { + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) | + CKGR_MOR_KEY_PASSWD; + } +} + +/** + * Restore clock settings + */ +__always_inline static void pmc_restore_clock_setting( + const uint32_t osc_setting, + const uint32_t pll0_setting, + const uint32_t pll1_setting, + const uint32_t mck_setting, + const uint32_t fmr_setting +#if defined(EFC1) + , const uint32_t fmr_setting1 +#endif + ) +{ + uint32_t mckr; + uint32_t pll_sr = 0; + + /* Switch mainck to external xtal */ + if (CKGR_MOR_MOSCXTBY == (osc_setting & CKGR_MOR_MOSCXTBY)) { + /* Bypass mode */ + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) | + CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTBY | + CKGR_MOR_MOSCSEL; + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN & + ~CKGR_MOR_MOSCRCF_Msk) + | CKGR_MOR_KEY_PASSWD; + } else if (CKGR_MOR_MOSCXTEN == (osc_setting & CKGR_MOR_MOSCXTEN)) { + /* Enable External XTAL */ + if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCXTEN)) { + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) | + CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTEN; + /* Wait the Xtal to stabilize */ + while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)); + } + /* Select External XTAL */ + if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) { + PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCSEL; + while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)); + } + /* Disable Fast RC */ + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN & + ~CKGR_MOR_MOSCRCF_Msk) + | CKGR_MOR_KEY_PASSWD; + } + + if (pll0_setting & CKGR_PLLAR_MULA_Msk) { +#if (SAM4C || SAM4CM || SAMG || SAM4CP) + PMC->CKGR_PLLAR = pll0_setting; +#else + PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | pll0_setting; +#endif + pll_sr |= PMC_SR_LOCKA; + } +#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP) + if (pll1_setting & CKGR_PLLBR_MULB_Msk) { + PMC->CKGR_PLLBR = pll1_setting; + pll_sr |= PMC_SR_LOCKB; + } +#elif (SAM3U || SAM3XA) + if (pll1_setting & CKGR_UCKR_UPLLEN) { + PMC->CKGR_UCKR = pll1_setting; + pll_sr |= PMC_SR_LOCKU; + } +#else + UNUSED(pll1_setting); +#endif + /* Wait MCK source ready */ + switch(mck_setting & PMC_MCKR_CSS_Msk) { + case PMC_MCKR_CSS_PLLA_CLK: + while (!(PMC->PMC_SR & PMC_SR_LOCKA)); + break; +#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP) + case PMC_MCKR_CSS_PLLB_CLK: + while (!(PMC->PMC_SR & PMC_SR_LOCKB)); + break; +#elif (SAM3U || SAM3XA) + case PMC_MCKR_CSS_UPLL_CLK: + while (!(PMC->PMC_SR & PMC_SR_LOCKU)); + break; +#endif + } + + /* Switch to faster clock */ + mckr = PMC->PMC_MCKR; + + /* Set PRES */ + PMC->PMC_MCKR = (mckr & ~PMC_MCKR_PRES_Msk) + | (mck_setting & PMC_MCKR_PRES_Msk); + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); + + /* Restore flash wait states */ + EFC0->EEFC_FMR = fmr_setting; +#if defined(EFC1) + EFC1->EEFC_FMR = fmr_setting1; +#endif + + /* Set CSS and others */ + PMC->PMC_MCKR = mck_setting; + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); + + /* Waiting all restored PLLs ready */ + while (!(PMC->PMC_SR & pll_sr)); +} + +/** If clocks are switched for some sleep mode */ +static volatile bool b_is_sleep_clock_used = false; +/** Callback invoked once when clocks are restored */ +static pmc_callback_wakeup_clocks_restored_t callback_clocks_restored = NULL; + +void pmc_sleep(int sleep_mode) +{ + switch (sleep_mode) { + case SAM_PM_SMODE_SLEEP_WFI: + case SAM_PM_SMODE_SLEEP_WFE: +#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG || SAMV71 || SAMV70 || SAMS70 || SAME70) + SCB->SCR &= (uint32_t)~SCR_SLEEPDEEP; + cpu_irq_enable(); + __DSB(); + __WFI(); + break; +#else + PMC->PMC_FSMR &= (uint32_t)~PMC_FSMR_LPM; + SCB->SCR &= (uint32_t)~SCR_SLEEPDEEP; + cpu_irq_enable(); + if (sleep_mode == SAM_PM_SMODE_SLEEP_WFI) { + __DSB(); + __WFI(); + } else { + __DSB(); + __WFE(); + } + break; +#endif + + case SAM_PM_SMODE_WAIT_FAST: + case SAM_PM_SMODE_WAIT: { + uint32_t mor, pllr0, pllr1, mckr; + uint32_t fmr; +#if defined(EFC1) + uint32_t fmr1; +#endif +#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG || SAMV71 || SAMV70 || SAMS70 || SAME70) + (sleep_mode == SAM_PM_SMODE_WAIT_FAST) ? + pmc_set_flash_in_wait_mode(PMC_FSMR_FLPM_FLASH_STANDBY) : + pmc_set_flash_in_wait_mode(PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN); +#endif + cpu_irq_disable(); + b_is_sleep_clock_used = true; + +#if (SAM4C || SAM4CM || SAM4CP) + /* Backup the sub-system 1 status and stop sub-system 1 */ + uint32_t cpclk_backup = PMC->PMC_SCSR & + (PMC_SCSR_CPCK | PMC_SCSR_CPBMCK); + PMC->PMC_SCDR = cpclk_backup | PMC_SCDR_CPKEY_PASSWD; +#endif + pmc_save_clock_settings(&mor, &pllr0, &pllr1, &mckr, &fmr, +#if defined(EFC1) + &fmr1, +#endif + (sleep_mode == SAM_PM_SMODE_WAIT)); + + /* Enter wait mode */ + cpu_irq_enable(); + + pmc_enable_waitmode(); + + cpu_irq_disable(); + pmc_restore_clock_setting(mor, pllr0, pllr1, mckr, fmr +#if defined(EFC1) + , fmr1 +#endif + ); + +#if (SAM4C || SAM4CM || SAM4CP) + /* Restore the sub-system 1 */ + PMC->PMC_SCER = cpclk_backup | PMC_SCER_CPKEY_PASSWD; +#endif + b_is_sleep_clock_used = false; + if (callback_clocks_restored) { + callback_clocks_restored(); + callback_clocks_restored = NULL; + } + cpu_irq_enable(); + + break; + } +#if (!(SAMG51 || SAMG53 || SAMG54)) + case SAM_PM_SMODE_BACKUP: + SCB->SCR |= SCR_SLEEPDEEP; +#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAMS70 || SAME70) + SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_VROFF_STOP_VREG; + cpu_irq_enable(); + __WFI() ; +#else + cpu_irq_enable(); + __WFE() ; +#endif + break; +#endif + } +} + +bool pmc_is_wakeup_clocks_restored(void) +{ + return !b_is_sleep_clock_used; +} + +void pmc_wait_wakeup_clocks_restore( + pmc_callback_wakeup_clocks_restored_t callback) +{ + if (b_is_sleep_clock_used) { + cpu_irq_disable(); + callback_clocks_restored = callback; + } else if (callback) { + callback(); + } +} + +#endif diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/pmc/sleep.h b/hw-libs/drivers/SAMx70/ASF/sam/drivers/pmc/sleep.h new file mode 100644 index 000000000..1a61237a6 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/pmc/sleep.h @@ -0,0 +1,117 @@ +/** + * \file + * + * \brief Sleep mode access + * + * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef SLEEP_H +#define SLEEP_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * \defgroup sleep_group Power Manager (PM) + * + * This is a stub on the SAM Power Manager Control (PMC) for the sleepmgr + * service. + * + * \note To minimize the code overhead, these functions do not feature + * interrupt-protected access since they are likely to be called inside + * interrupt handlers or in applications where such protection is not + * necessary. If such protection is needed, it must be ensured by the calling + * code. + * + * @{ + */ + +#if defined(__DOXYGEN__) +/** + * \brief Sets the MCU in the specified sleep mode + * \param sleep_mode Sleep mode to set. + */ +#endif +/* SAM3,SAM4,SAMG,SAMV,SAME and SAMS series */ +#if (SAM3S || SAM3N || SAM3XA || SAM3U || SAM4S || SAM4E || SAM4N || SAM4C || \ + SAM4CM || SAM4CP || SAMG || SAMV71 || SAME70 || SAMS70) +# define SAM_PM_SMODE_ACTIVE 0 /**< Active */ +# define SAM_PM_SMODE_SLEEP_WFE 1 /**< Wait for Events */ +# define SAM_PM_SMODE_SLEEP_WFI 2 /**< Wait for Interrupts */ +# define SAM_PM_SMODE_WAIT_FAST 3 /**< Wait Mode, startup fast (in 3ms) */ +# define SAM_PM_SMODE_WAIT 4 /**< Wait Mode */ +#if (!(SAMG51 || SAMG53 || SAMG54)) +# define SAM_PM_SMODE_BACKUP 5 /**< Backup Mode */ +#endif + +/** (SCR) Sleep deep bit */ +#define SCR_SLEEPDEEP (0x1 << 2) + +/** + * Clocks restored callback function type. + * Registered by routine pmc_wait_wakeup_clocks_restore() + * Callback called when all clocks are restored. + */ +typedef void (*pmc_callback_wakeup_clocks_restored_t) (void); + +/** + * Enter sleep mode + * \param sleep_mode Sleep mode to enter + */ +void pmc_sleep(int sleep_mode); + +/** + * Check if clocks are restored after wakeup + * (For WAIT mode. In WAIT mode, clocks are switched to FASTRC. + * After wakeup clocks should be restored, before that some of the + * ISR should not be served, otherwise there may be timing or clock issue.) + */ +bool pmc_is_wakeup_clocks_restored(void); + +/** + * \return true if start waiting + */ +void pmc_wait_wakeup_clocks_restore( + pmc_callback_wakeup_clocks_restored_t callback); + +#endif + +//! @} + +#ifdef __cplusplus +} +#endif + +#endif /* SLEEP_H */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/pwm/pwm.c b/hw-libs/drivers/SAMx70/ASF/sam/drivers/pwm/pwm.c new file mode 100644 index 000000000..afb034adf --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/pwm/pwm.c @@ -0,0 +1,1189 @@ +/** + * \file + * + * \brief Pulse Width Modulation (PWM) driver for SAM. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "pwm.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \defgroup sam_drivers_pwm_group Pulse Width Modulation (PWM) + * + * See \ref sam_pwm_quickstart. + * + * Driver for the PWM (Pulse Width Modulation). This driver provides access to the + * main features of the PWM controller. + * + * @{ + */ + +#ifndef PWM_WPCR_WPKEY_PASSWD +# define PWM_WPCR_WPKEY_PASSWD 0x50574D00 +#endif + +#ifndef PWM_WPCR_WPCMD_DISABLE_SW_PROT +# define PWM_WPCR_WPCMD_DISABLE_SW_PROT (PWM_WPCR_WPCMD(0)) +#endif + +#ifndef PWM_WPCR_WPCMD_ENABLE_SW_PROT +# define PWM_WPCR_WPCMD_ENABLE_SW_PROT (PWM_WPCR_WPCMD(1)) +#endif + +#ifndef PWM_WPCR_WPCMD_ENABLE_HW_PROT +# define PWM_WPCR_WPCMD_ENABLE_HW_PROT (PWM_WPCR_WPCMD(2)) +#endif + +#define PWM_CLOCK_DIV_MAX 256 +#define PWM_CLOCK_PRE_MAX 11 + +/** + * \brief Find a prescaler/divisor couple to generate the desired ul_frequency + * from ul_mck. + * + * \param ul_frequency Desired frequency in Hz. + * \param ul_mck Master clock frequency in Hz. + * + * \retval Return the value to be set in the PWM Clock Register (PWM Mode Register for + * SAM3N/SAM4N/SAM4C/SAM4CP/SAM4CM) or PWM_INVALID_ARGUMENT if the configuration cannot be met. + */ +static uint32_t pwm_clocks_generate(uint32_t ul_frequency, uint32_t ul_mck) +{ + uint32_t ul_divisors[PWM_CLOCK_PRE_MAX] = + {1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 }; + uint32_t ul_pre = 0; + uint32_t ul_div; + + /* Find prescaler and divisor values */ + do { + ul_div = (ul_mck / ul_divisors[ul_pre]) / ul_frequency; + if (ul_div <= PWM_CLOCK_DIV_MAX) { + break; + } + ul_pre++; + } while (ul_pre < PWM_CLOCK_PRE_MAX); + + /* Return result */ + if (ul_pre < PWM_CLOCK_PRE_MAX) { + return ul_div | (ul_pre << 8); + } else { + return PWM_INVALID_ARGUMENT; + } +} + +/** + * \brief Initialize the PWM source clock (clock A and clock B). + * + * \param p_pwm Pointer to a PWM instance. + * \param clock_config PWM clock configuration. + * + * \retval 0 if initialization succeeds, otherwise fails. + */ +uint32_t pwm_init(Pwm *p_pwm, pwm_clock_t *clock_config) +{ + uint32_t clock = 0; + uint32_t result; + + /* Clock A */ + if (clock_config->ul_clka != 0) { + result = pwm_clocks_generate(clock_config->ul_clka, clock_config->ul_mck); + if (result == PWM_INVALID_ARGUMENT) { + return result; + } + + clock = result; + } + + /* Clock B */ + if (clock_config->ul_clkb != 0) { + result = pwm_clocks_generate(clock_config->ul_clkb, clock_config->ul_mck); + + if (result == PWM_INVALID_ARGUMENT) { + return result; + } + + clock |= (result << 16); + } +#if (SAM3N || SAM4N || SAM4C || SAM4CP || SAM4CM) + p_pwm->PWM_MR = clock; +#else + p_pwm->PWM_CLK = clock; +#endif + return 0; +} + +/** + * \brief Initialize one PWM channel. + * + * \param p_pwm Pointer to a PWM instance. + * \param p_channel Configurations of the specified PWM channel. + * + * \retval 0 if initialization succeeds, otherwise fails. + */ +uint32_t pwm_channel_init(Pwm *p_pwm, pwm_channel_t *p_channel) +{ + uint32_t tmp_reg = 0; + uint32_t ch_num = p_channel->channel; + + /* Channel Mode/Clock Register */ + tmp_reg = (p_channel->ul_prescaler & 0xF) | + (p_channel->polarity << 9) | +#if (SAM3U || SAM3S || SAM3XA || SAM4S || SAM4E || SAMV70 || SAMV71 || SAME70 || SAMS70) + (p_channel->counter_event) | + (p_channel->b_deadtime_generator << 16) | + (p_channel->b_pwmh_output_inverted << 17) | + (p_channel->b_pwml_output_inverted << 18) | +#endif + (p_channel->alignment); + p_pwm->PWM_CH_NUM[ch_num].PWM_CMR = tmp_reg; + + /* Channel Duty Cycle Register */ + p_pwm->PWM_CH_NUM[ch_num].PWM_CDTY = p_channel->ul_duty; + + /* Channel Period Register */ + p_pwm->PWM_CH_NUM[ch_num].PWM_CPRD = p_channel->ul_period; + +#if (SAM3U || SAM3S || SAM3XA || SAM4S || SAM4E || SAMV70 || SAMV71 || SAME70 || SAMS70) + /* Channel Dead Time Register */ + if (p_channel->b_deadtime_generator) { + p_pwm->PWM_CH_NUM[ch_num].PWM_DT = + PWM_DT_DTL(p_channel-> + us_deadtime_pwml) | PWM_DT_DTH(p_channel-> + us_deadtime_pwmh); + } + + /* Output Selection Register */ + tmp_reg = p_pwm->PWM_OS & (~((PWM_OS_OSH0 | PWM_OS_OSL0) << ch_num)); + tmp_reg |= ((p_channel->output_selection.b_override_pwmh) << ch_num) | + (((p_channel->output_selection.b_override_pwml) << ch_num) + << 16); + p_pwm->PWM_OS = tmp_reg; + + /* Output Override Value Register */ + tmp_reg = p_pwm->PWM_OOV & (~((PWM_OOV_OOVH0 | PWM_OOV_OOVL0) << ch_num)); + tmp_reg |= ((p_channel->output_selection.override_level_pwmh) << ch_num) | + (((p_channel->output_selection.override_level_pwml) << ch_num) + << 16); + p_pwm->PWM_OOV = tmp_reg; + + /* Sync Channels Mode Register */ + uint32_t channel = (1 << ch_num); + if (p_channel->b_sync_ch) { + p_pwm->PWM_SCM |= channel; + } else { + p_pwm->PWM_SCM &= ~((uint32_t) channel); + } + + /* Fault Protection Value Register */ +#if (SAM4E || SAMV70 || SAMV71 || SAME70 || SAMS70) + if (p_channel->ul_fault_output_pwmh == PWM_HIGHZ) { + p_pwm->PWM_FPV2 |= (0x01 << ch_num); + } else { + p_pwm->PWM_FPV2 &= ~(0x01 << ch_num); + if (p_channel->ul_fault_output_pwmh == PWM_HIGH) { + p_pwm->PWM_FPV1 |= (0x01 << ch_num); + } else { + p_pwm->PWM_FPV1 &= (~(0x01 << ch_num)); + } + } + if (p_channel->ul_fault_output_pwml == PWM_HIGHZ) { + p_pwm->PWM_FPV2 |= ((0x01 << ch_num) << 16); + } else { + p_pwm->PWM_FPV2 &= ~((0x01 << ch_num) << 16); + if (p_channel->ul_fault_output_pwml == PWM_HIGH) { + p_pwm->PWM_FPV1 |= ((0x01 << ch_num) << 16); + } else { + p_pwm->PWM_FPV1 &= (~((0x01 << ch_num) << 16)); + } + } +#else + if (p_channel->ul_fault_output_pwmh == PWM_HIGH) { + p_pwm->PWM_FPV |= (0x01 << ch_num); + } else { + p_pwm->PWM_FPV &= (~(0x01 << ch_num)); + } + if (p_channel->ul_fault_output_pwml == PWM_HIGH) { + p_pwm->PWM_FPV |= ((0x01 << ch_num) << 16); + } else { + p_pwm->PWM_FPV &= (~((0x01 << ch_num) << 16)); + } +#endif + /* Fault Protection Enable Register */ + uint32_t fault_enable_reg = 0; +#if (SAM3XA) + if (ch_num < 4) { + ch_num *= 8; + fault_enable_reg = p_pwm->PWM_FPE1; + fault_enable_reg &= ~(0xFF << ch_num); + fault_enable_reg |= ((p_channel->fault_id) << ch_num); + p_pwm->PWM_FPE1 = fault_enable_reg; + } else { + ch_num -= 4; + ch_num *= 8; + fault_enable_reg = p_pwm->PWM_FPE2; + fault_enable_reg &= ~(0xFF << ch_num); + fault_enable_reg |= ((p_channel->fault_id) << ch_num); + p_pwm->PWM_FPE2 = fault_enable_reg; + } +#endif + +#if (SAM3U || SAM3S || SAM4S || SAM4E || SAMV70 || SAMV71 || SAME70 || SAMS70) + ch_num *= 8; + fault_enable_reg = p_pwm->PWM_FPE; + fault_enable_reg &= ~(0xFF << ch_num); + fault_enable_reg |= ((p_channel->fault_id) << ch_num); + p_pwm->PWM_FPE = fault_enable_reg; +#endif +#endif + + ch_num = p_channel->channel; + +#if SAM4E + if (!ch_num) { + if (p_channel->spread_spectrum_mode == + PWM_SPREAD_SPECTRUM_MODE_RANDOM) { + p_pwm->PWM_SSPR = PWM_SSPR_SPRD(p_channel->ul_spread) | + PWM_SSPR_SPRDM; + } else { + p_pwm->PWM_SSPR = PWM_SSPR_SPRD(p_channel->ul_spread); + } + } + p_pwm->PWM_CH_NUM_0X400[ch_num].PWM_CAE = + PWM_CAE_ADEDGV(p_channel->ul_additional_edge) | + p_channel->additional_edge_mode; +#elif (SAMV70 || SAMV71 || SAME70 || SAMS70) + if (!ch_num) { + if (p_channel->spread_spectrum_mode == + PWM_SPREAD_SPECTRUM_MODE_RANDOM) { + p_pwm->PWM_SSPR = PWM_SSPR_SPRD(p_channel->ul_spread) | + PWM_SSPR_SPRDM; + } else { + p_pwm->PWM_SSPR = PWM_SSPR_SPRD(p_channel->ul_spread); + } + } + p_pwm->PWM_CH_NUM[ch_num].PWM_CMR &= (~PWM_CMR_PPM); + p_pwm->PWM_CH_NUM[ch_num].PWM_CMR |= (p_channel->ul_ppm_mode & PWM_CMR_PPM); +#endif + + return 0; +} + +/** + * \brief Change the period of the PWM channel. + * + * \param p_pwm Pointer to a PWM instance. + * \param p_channel Configurations of the specified PWM channel. + * \param ul_period New period value. + * + * \retval 0 if changing succeeds, otherwise fails. + */ +uint32_t pwm_channel_update_period(Pwm *p_pwm, pwm_channel_t *p_channel, + uint32_t ul_period) +{ + uint32_t ch_num = p_channel->channel; + + /** Check parameter */ + if (p_channel->ul_duty > ul_period) { + return PWM_INVALID_ARGUMENT; + } else { + /* Save new period value */ + p_channel->ul_period = ul_period; + +#if (SAM3N || SAM4N || SAM4C || SAM4CP || SAM4CM) + /* Set CPD bit to change period value */ + p_pwm->PWM_CH_NUM[ch_num].PWM_CMR |= PWM_CMR_CPD; + + p_pwm->PWM_CH_NUM[ch_num].PWM_CUPD = ul_period; +#else + p_pwm->PWM_CH_NUM[ch_num].PWM_CPRDUPD = ul_period; +#endif + } + + return 0; +} + +/** + * \brief Change the duty cycle of the PWM channel. + * + * \param p_pwm Pointer to a PWM instance. + * \param p_channel Configurations of the specified PWM channel. + * \param ul_duty New duty cycle value. + * + * \retval 0 if changing succeeds, otherwise fails. + */ +uint32_t pwm_channel_update_duty(Pwm *p_pwm, pwm_channel_t *p_channel, + uint32_t ul_duty) +{ + uint32_t ch_num = p_channel->channel; + + /** Check parameter */ + if (p_channel->ul_period < ul_duty) { + return PWM_INVALID_ARGUMENT; + } else { + /* Save new duty cycle value */ + p_channel->ul_duty = ul_duty; + +#if (SAM3N || SAM4N || SAM4C || SAM4CP || SAM4CM) + /* Clear CPD bit to change duty cycle value */ + uint32_t mode = p_pwm->PWM_CH_NUM[ch_num].PWM_CMR; + mode &= ~PWM_CMR_CPD; + p_pwm->PWM_CH_NUM[ch_num].PWM_CMR = mode; + + p_pwm->PWM_CH_NUM[ch_num].PWM_CUPD = ul_duty; +#else + p_pwm->PWM_CH_NUM[ch_num].PWM_CDTYUPD = ul_duty; +#endif + } + + return 0; +} + +/** + * \brief Return channel counter value. + * + * \param p_pwm Pointer to a PWM instance. + * \param p_channel Configurations of the specified PWM channel. + * + * \return channel Counter value. + */ +uint32_t pwm_channel_get_counter(Pwm *p_pwm, pwm_channel_t *p_channel) +{ + return p_pwm->PWM_CH_NUM[p_channel->channel].PWM_CCNT; +} + + +/** + * \brief Enable the PWM channel. + * + * \note The PWM channel should be initialized by pwm_channel_init() before it is enabled. + * + * \param p_pwm Pointer to a PWM instance. + * \param ul_channel PWM channel number to enable. + */ +void pwm_channel_enable(Pwm *p_pwm, uint32_t ul_channel) +{ + p_pwm->PWM_ENA = (1 << ul_channel); +} + +/** + * \brief Disable the PWM channel. + * + * \note A disabled PWM channel can be re-initialized using pwm_channel_init(). + * + * \param p_pwm Pointer to a PWM instance. + * \param ul_channel PWM channel number to disable. + */ +void pwm_channel_disable(Pwm *p_pwm, uint32_t ul_channel) +{ + p_pwm->PWM_DIS = (1 << ul_channel); +} + + +/** + * \brief Check which PWM channel is enabled. + * + * \param p_pwm Pointer to a PWM instance. + * \param p_channel Configurations of the specified PWM channel. + * + * \return Bitmask of enabled PWM channel(s). + */ +uint32_t pwm_channel_get_status(Pwm *p_pwm) +{ + return p_pwm->PWM_SR; +} + +/** + * \brief Get channel counter event and fault protection trigger interrupt status. + * + * \param p_pwm Pointer to a PWM instance. + * + * \return Channel counter event and fault protection trigger interrupt status. + */ +uint32_t pwm_channel_get_interrupt_status(Pwm *p_pwm) +{ +#if (SAM3N || SAM4N || SAM4C || SAM4CP || SAM4CM) + return p_pwm->PWM_ISR; +#else + return p_pwm->PWM_ISR1; +#endif +} + +/** + * \brief Get channel counter event and fault protection trigger interrupt mask. + * + * \param p_pwm Pointer to a PWM instance. + * + * \return Channel counter event and fault protection trigger interrupt mask. + */ +uint32_t pwm_channel_get_interrupt_mask(Pwm *p_pwm) +{ +#if (SAM3N || SAM4N || SAM4C || SAM4CP || SAM4CM) + return p_pwm->PWM_IMR; +#else + return p_pwm->PWM_IMR1; +#endif +} + +/** + * \brief Enable the interrupt of a channel counter event and fault protection. + * + * \param p_pwm Pointer to a PWM instance. + * \param ul_event Channel number to enable counter event interrupt. + * \param ul_fault Channel number to enable fault protection interrupt(ignored + * by SAM3N/SAM4N/SAM4C/SAM4CP/SAM4CM). + */ +void pwm_channel_enable_interrupt(Pwm *p_pwm, uint32_t ul_event, + uint32_t ul_fault) +{ +#if (SAM3N || SAM4N || SAM4C || SAM4CP || SAM4CM) + p_pwm->PWM_IER = (1 << ul_event); + /* avoid Cppcheck Warning */ + UNUSED(ul_fault); +#else + p_pwm->PWM_IER1 = (1 << ul_event) | (1 << (ul_fault + 16)); +#endif +} + + +/** + * \brief Disable the interrupt of a channel counter event and fault protection. + * + * \param p_pwm Pointer to a PWM instance. + * \param ul_event Bitmask of channel number to disable counter event interrupt. + * \param ul_fault Bitmask of channel number to disable fault protection + * interrupt(ignored by SAM3N/SAM4N/SAM4C/SAM4CP/SAM4CM). + */ +void pwm_channel_disable_interrupt(Pwm *p_pwm, uint32_t ul_event, + uint32_t ul_fault) +{ +#if (SAM3N || SAM4N || SAM4C || SAM4CP || SAM4CM) + p_pwm->PWM_IDR = (1 << ul_event); + /* avoid Cppcheck Warning */ + UNUSED(ul_fault); +#else + p_pwm->PWM_IDR1 = (1 << ul_event) | (1 << (ul_fault + 16)); +#endif +} + + +#if (SAM3U || SAM3S || SAM3XA || SAM4S || SAM4E || SAMV70 || SAMV71 || SAME70 || SAMS70) +/** + * \brief Change output selection of the PWM channel. + * + * \param p_pwm Pointer to a PWM instance. + * \param p_channel Configurations of the specified PWM channel. + * \param p_output New PWM channel output selection. + * \param b_sync Boolean of changing of output selection. Set true to change the output synchronously (at the beginning of the next PWM period). Set false to change the output asynchronously (at the end of the execution of the function). + */ +void pwm_channel_update_output(Pwm *p_pwm, pwm_channel_t *p_channel, + pwm_output_t *p_output, bool b_sync) +{ + uint32_t ch_num = p_channel->channel; + uint32_t channel = (1 << ch_num); + + bool override_pwmh = p_output->b_override_pwmh; + bool override_pwml = p_output->b_override_pwml; + uint32_t pwmh = p_output->override_level_pwmh; + uint32_t pwml = p_output->override_level_pwml; + + /* Save new output configuration */ + p_channel->output_selection.b_override_pwmh = override_pwmh; + p_channel->output_selection.b_override_pwml = override_pwml; + p_channel->output_selection.override_level_pwmh = (pwm_level_t) pwmh; + p_channel->output_selection.override_level_pwml = (pwm_level_t) pwml; + + /* Change override output level */ + uint32_t override_value = p_pwm->PWM_OOV; + override_value &= ~((PWM_OOV_OOVH0 | PWM_OOV_OOVL0) << ch_num); + override_value |= (((pwml << 16) | pwmh) << ch_num); + p_pwm->PWM_OOV = override_value; + + /* Apply new output selection */ + if (b_sync) { + p_pwm->PWM_OSSUPD = ((override_pwml << ch_num) << 16) | + (override_pwmh << ch_num); + p_pwm->PWM_OSCUPD = ((!override_pwml << ch_num) << 16) | + (!override_pwmh << ch_num); + } else { + p_pwm->PWM_OSS = ((override_pwml << ch_num) << 16) | + (override_pwmh << ch_num); + p_pwm->PWM_OSC = ((!override_pwml << ch_num) << 16) | + (!override_pwmh << ch_num); + } +} + +/** + * \brief Change dead-time value for PWM outputs. + * + * \param p_pwm Pointer to a PWM instance. + * \param p_channel Configurations of the specified PWM channel. + * \param us_deadtime_pwmh New dead-time value for PWMH output. + * \param us_deadtime_pwml New dead-time value for PWML output. + */ +void pwm_channel_update_dead_time(Pwm *p_pwm, pwm_channel_t *p_channel, + uint16_t us_deadtime_pwmh, uint16_t us_deadtime_pwml) +{ + /* Save new dead time value */ + p_channel->us_deadtime_pwmh = us_deadtime_pwmh; + p_channel->us_deadtime_pwml = us_deadtime_pwml; + + /* Write channel dead time update register */ + p_pwm->PWM_CH_NUM[p_channel->channel].PWM_DTUPD = + PWM_DTUPD_DTLUPD(us_deadtime_pwml) | + PWM_DTUPD_DTHUPD(us_deadtime_pwmh); +} + + + +/** + * \brief Initialize the behavior of a fault input. + * + * \param p_pwm Pointer to a PWM instance. + * \param p_fault Configurations of a fault input. + * + * \retval 0 if configuration succeeds, otherwise fails. + */ +uint32_t pwm_fault_init(Pwm *p_pwm, pwm_fault_t *p_fault) +{ + uint32_t fault_id = p_fault->fault_id; + uint32_t fault_reg = p_pwm->PWM_FMR; + + /** Polarity of fault input */ + if (p_fault->polarity == PWM_HIGH) { + fault_reg |= fault_id; + } else { + fault_reg &= ~fault_id; + } + /** Boolean of clearing fault flag */ + if (p_fault->b_clear) { + fault_reg |= (fault_id << 8); + } else { + fault_reg &= ~(fault_id << 8); + } + /** Boolean of fault filtering */ + if (p_fault->b_filtered) { + fault_reg |= (fault_id << 16); + } else { + fault_reg &= ~(fault_id << 16); + } + + p_pwm->PWM_FMR = fault_reg; + + return 0; +} + +/** + * \brief Get fault status. + * + * \param p_pwm Pointer to a PWM instance. + * + * \return Bitmask of IDs of all active faulty. + */ +uint32_t pwm_fault_get_status(Pwm *p_pwm) +{ + return ((p_pwm->PWM_FSR >> 8) & 0xFF); +} + +/** + * \brief Get the level of a fault input. + * + * \param p_pwm Pointer to a PWM instance. + * \param id Faulty ID. + * + * \return Level of the fault input. + */ +pwm_level_t pwm_fault_get_input_level(Pwm *p_pwm, pwm_fault_id_t id) +{ + uint32_t fault_status_reg = p_pwm->PWM_FSR; + fault_status_reg >>= id; + + return ((fault_status_reg & 1) ? PWM_HIGH : PWM_LOW); +} + +/** + * \brief Clear a fault input. + * + * \param p_pwm Pointer to a PWM instance. + * \param id Faulty ID. + */ +void pwm_fault_clear_status(Pwm *p_pwm, pwm_fault_id_t id) +{ + p_pwm->PWM_FCR = id; +} + +/** + * \brief Initialize PWM comparison unit. + * + * \param p_pwm Pointer to a PWM instance. + * \param p_cmp Configurations of PWM comparison tagged by unit. + * + * \retval 0 if initialization succeeds, otherwise fails. + */ +uint32_t pwm_cmp_init(Pwm *p_pwm, pwm_cmp_t *p_cmp) +{ + uint32_t unit = p_cmp->unit; + + p_pwm->PWM_CMP[unit].PWM_CMPV = PWM_CMPV_CV(p_cmp->ul_value) | + (p_cmp->b_is_decrementing << 24); + + p_pwm->PWM_CMP[unit].PWM_CMPM = PWM_CMPM_CTR(p_cmp->ul_trigger) | + PWM_CMPM_CPR(p_cmp->ul_period) | + PWM_CMPM_CUPR(p_cmp->ul_update_period); + + /** Boolean of generating a match pulse */ + if (p_cmp->b_pulse_on_line_0) { + p_pwm->PWM_ELMR[0] |= (1 << unit); + } else { + p_pwm->PWM_ELMR[0] &= ~((uint32_t) (1 << unit)); + } + /** Boolean of generating a match pulse */ + if (p_cmp->b_pulse_on_line_1) { + p_pwm->PWM_ELMR[1] |= (1 << unit); + } else { + p_pwm->PWM_ELMR[1] &= ~((uint32_t) (1 << unit)); + } + + /** Boolean of comparison enable */ + if (p_cmp->b_enable) { + p_pwm->PWM_CMP[unit].PWM_CMPM |= PWM_CMPM_CEN; + } else { + p_pwm->PWM_CMP[unit].PWM_CMPM &= ~PWM_CMPM_CEN; + } + + return 0; +} + + +/** + * \brief Change the setting of PWM comparison. + * + * \param p_pwm Pointer to a PWM instance. + * \param p_cmp Configurations of PWM comparison tagged by unit. + * + * \retval 0 if changing succeeds, otherwise fails. + */ +uint32_t pwm_cmp_change_setting(Pwm *p_pwm, pwm_cmp_t *p_cmp) +{ + uint32_t unit = p_cmp->unit; + + p_pwm->PWM_CMP[unit].PWM_CMPVUPD = PWM_CMPV_CV(p_cmp->ul_value) | + (p_cmp->b_is_decrementing << 24); + + p_pwm->PWM_CMP[unit].PWM_CMPMUPD = PWM_CMPM_CTR(p_cmp->ul_trigger) | + PWM_CMPM_CPR(p_cmp->ul_period) | + PWM_CMPM_CUPR(p_cmp->ul_update_period); + + /** Boolean of generating a match pulse */ + if (p_cmp->b_pulse_on_line_0) { + p_pwm->PWM_ELMR[0] |= (1 << unit); + } else { + p_pwm->PWM_ELMR[0] &= ~((uint32_t) (1 << unit)); + } + /** Boolean of generating a match pulse */ + if (p_cmp->b_pulse_on_line_1) { + p_pwm->PWM_ELMR[1] |= (1 << unit); + } else { + p_pwm->PWM_ELMR[1] &= ~((uint32_t) (1 << unit)); + } + + /** Boolean of comparison enable */ + if (p_cmp->b_enable) { + p_pwm->PWM_CMP[unit].PWM_CMPMUPD |= PWM_CMPM_CEN; + } else { + p_pwm->PWM_CMP[unit].PWM_CMPMUPD &= ~PWM_CMPM_CEN; + } + + return 0; +} + + +/** + * \brief Report the value of the comparison period counter. + * + * \param p_pwm Pointer to a PWM instance. + * \param ul_cmp_unit PWM comparison unit number. + * + * \return Value of the comparison period counter. + */ +uint32_t pwm_cmp_get_period_counter(Pwm *p_pwm, uint32_t ul_cmp_unit) +{ + return (PWM_CMPM_CPRCNT(p_pwm->PWM_CMP[ul_cmp_unit].PWM_CMPM) + >> PWM_CMPM_CPRCNT_Pos); +} + +/** + * \brief Report the value of the comparison update period counter. + * + * \param p_pwm Pointer to a PWM instance. + * \param ul_cmp_unit PWM comparison unit number. + * + * \return Value of the comparison update period counter. + */ +uint32_t pwm_cmp_get_update_counter(Pwm *p_pwm, uint32_t ul_cmp_unit) +{ + return (PWM_CMPM_CUPRCNT(p_pwm->PWM_CMP[ul_cmp_unit].PWM_CMPM) + >> PWM_CMPM_CUPRCNT_Pos); +} + + +/** + * \brief Enable the interrupt of comparison. + * + * \param p_pwm Pointer to a PWM instance. + * \param ul_sources Bitmask of comparison unit. + * \param type PWM_CMP_MATCH enables the match interrupt of the unit. PWM_CMP_UPDATE enables the update interrupt of the comparison unit. + */ +void pwm_cmp_enable_interrupt(Pwm *p_pwm, uint32_t ul_sources, + pwm_cmp_interrupt_t type) +{ + if (type == PWM_CMP_MATCH) { + p_pwm->PWM_IER2 = ((1 << ul_sources) << 8); + } else if (type == PWM_CMP_UPDATE) { + p_pwm->PWM_IER2 = ((1 << ul_sources) << 16); + } else { + /* Do Nothing */ + } +} + + +/** + * \brief Disable the interrupt of comparison. + * + * \param p_pwm Pointer to a PWM instance. + * \param ul_sources Bitmask of comparison unit. + * \param type PWM_CMP_MATCH disables the match interrupt of the unit. PWM_CMP_UPDATE disables the update interrupt of the comparison unit. + */ +void pwm_cmp_disable_interrupt(Pwm *p_pwm, uint32_t ul_sources, + pwm_cmp_interrupt_t type) +{ + if (type == PWM_CMP_MATCH) { + p_pwm->PWM_IDR2 = ((1 << ul_sources) << 8); + } else if (type == PWM_CMP_UPDATE) { + p_pwm->PWM_IDR2 = ((1 << ul_sources) << 16); + } else { + /* Do Nothing */ + } +} + +#if !(SAMV70 || SAMV71 || SAME70 || SAMS70) +/** + * \brief Set PDC transfer request mode. + * + * \note If configure Synchronous channels update mode as 'PWM_SYNC_UPDATE_MODE_0' or 'PWM_SYNC_UPDATE_MODE_1' via pwm_sync_init(), ul_pdc_request will be ignored and PDC transfer request will never occur. + * + * \param p_pwm Pointer to a PWM instance. + * \param request_mode PDC transfer request mode. + * \param ul_cmp_unit PWM comparison unit number for PDC transfer request. + */ +void pwm_pdc_set_request_mode(Pwm *p_pwm, pwm_pdc_request_mode_t request_mode, + uint32_t ul_cmp_unit) +{ + uint32_t sync_mode = p_pwm->PWM_SCM; + + sync_mode &= ~(PWM_SCM_PTRCS_Msk | PWM_SCM_PTRM); + sync_mode |= (PWM_SCM_PTRCS(ul_cmp_unit) | request_mode); + + p_pwm->PWM_SCM = sync_mode; +} + + + +/** + * \brief Enable the interrupt of PDC transfer. + * + * \param p_pwm Pointer to a PWM instance. + * \param ul_sources Bitmask of PWM PDC transfer interrupt sources. + */ +void pwm_pdc_enable_interrupt(Pwm *p_pwm, uint32_t ul_sources) +{ + p_pwm->PWM_IER2 = ul_sources; +} + +/** + * \brief Disable the interrupt of PDC transfer. + * + * \param p_pwm Pointer to a PWM instance. + * \param ul_sources Bitmask of PWM PDC transfer interrupt sources. + */ +void pwm_pdc_disable_interrupt(Pwm *p_pwm, uint32_t ul_sources) +{ + p_pwm->PWM_IDR2 = ul_sources; +} +#endif + +/** + * \brief Initialize synchronous channels update mode and period. + * + * \param p_pwm Pointer to a PWM instance. + * \param mode Synchronous channels update mode. + * \param ul_update_period Time between each update of the synchronous channels. + * + * \retval 0 if initialization succeeds, otherwise fails. + */ +uint32_t pwm_sync_init(Pwm *p_pwm, pwm_sync_update_mode_t mode, + uint32_t ul_update_period) +{ + uint32_t sync_mode = p_pwm->PWM_SCM; + + sync_mode &= ~PWM_SCM_UPDM_Msk; + sync_mode |= mode; + + p_pwm->PWM_SCM = sync_mode; + + p_pwm->PWM_SCUP = PWM_SCUP_UPR(ul_update_period); + + return 0; +} + +/** + * \brief Unlock the update of synchronous channels. + * + * \note After unlock, synchronous channels will be updated at the next PWM period. + * + * \param p_pwm Pointer to a PWM instance. + */ +void pwm_sync_unlock_update(Pwm *p_pwm) +{ + p_pwm->PWM_SCUC = PWM_SCUC_UPDULOCK; +} + +/** + * \brief Change the wanted time between each update of the synchronous channels. + * + * \param p_pwm Pointer to a PWM instance. + * \param ul_update_period Time between each update of the synchronous channels. + */ +void pwm_sync_change_period(Pwm *p_pwm, uint32_t ul_update_period) +{ + p_pwm->PWM_SCUPUPD = PWM_SCUPUPD_UPRUPD(ul_update_period); +} + +/** + * \brief Get the value of the synchronization update period counter. + * + * \param p_pwm Pointer to a PWM instance. + * + * \return Value of the synchronization update Period Counter. + */ +uint32_t pwm_sync_get_period_counter(Pwm *p_pwm) +{ + return PWM_SCUP_UPRCNT(p_pwm->PWM_SCUP); +} + +/** + * \brief Enable the interrupt of synchronous channel. + * + * \param p_pwm Pointer to a PWM instance. + * \param ul_sources Bitmask of PWM synchronous channels interrupt sources. + */ +void pwm_sync_enable_interrupt(Pwm *p_pwm, uint32_t ul_sources) +{ + p_pwm->PWM_IER2 = ul_sources; +} + +/** + * \brief Disable the interrupt of synchronous channels. + * + * \param p_pwm Pointer to a PWM instance. + * \param ul_sources Bitmask of PWM synchronous channels interrupt sources. + */ +void pwm_sync_disable_interrupt(Pwm *p_pwm, uint32_t ul_sources) +{ + p_pwm->PWM_IDR2 = ul_sources; +} + +/** + * \brief Enable PWM write protect. + * + * \param p_pwm Pointer to a PWM instance. + * \param ul_group Bitmask of PWM register group. + * \param b_sw Boolean of software protect. True for software protect and false for hardware protect. + */ +void pwm_enable_protect(Pwm *p_pwm, uint32_t ul_group, bool b_sw) +{ + uint32_t wp = 0; + + if (b_sw) { + wp = PWM_WPCR_WPKEY_PASSWD | (ul_group << 2) | + PWM_WPCR_WPCMD_ENABLE_SW_PROT; + } else { + wp = PWM_WPCR_WPKEY_PASSWD | (ul_group << 2) | + PWM_WPCR_WPCMD_ENABLE_HW_PROT; + } + + p_pwm->PWM_WPCR = wp; +} + +/** + * \brief Disable PWM write protect. + * + * \note Only a hardware reset of PWM controller (handled by PMC) can disable hardware write protect. + * + * \param p_pwm Pointer to a PWM instance. + * \param ul_group Bitmask of PWM register group. + */ +void pwm_disable_protect(Pwm *p_pwm, uint32_t ul_group) +{ + p_pwm->PWM_WPCR = PWM_WPCR_WPKEY_PASSWD + | (ul_group << 2) | PWM_WPCR_WPCMD_DISABLE_SW_PROT; +} + +/** + * \brief Get PWM write protect status. + * + * \param p_pwm Pointer to a PWM instance. + * \param p_protect Pointer to a structure stored PWM protect status. + * + * \retval 0 Protection disabled. + * \retval 1 Protection enabled. + */ +bool pwm_get_protect_status(Pwm *p_pwm, pwm_protect_t *p_protect) +{ + uint32_t wpsr = p_pwm->PWM_WPSR; + + p_protect->ul_hw_status = (wpsr >> 8) & 0x3F; + /** Bitmask of PWM register group for write protect software status */ + p_protect->ul_sw_status = (wpsr & 0x3F); + + if ((PWM_WPSR_WPVS & wpsr) == PWM_WPSR_WPVS) { + p_protect->ul_offset = + (wpsr & PWM_WPSR_WPVSRC_Msk) >> + PWM_WPSR_WPVSRC_Pos; + return true; + } else { + return false; + } +} + +/** + * \brief Get interrupt status of PDC transfer, synchronous channels and comparison. + * + * \param p_pwm Pointer to a PWM instance. + * + * \return Interrupt status of PDC transfer, synchronous channels and comparison. + */ +uint32_t pwm_get_interrupt_status(Pwm *p_pwm) +{ + return p_pwm->PWM_ISR2; +} + +/** + * \brief Get interrupt mask of PDC transfer, synchronous channels and comparison. + * + * \param p_pwm Pointer to a PWM instance. + * + * \return Interrupt mask of PDC transfer, synchronous channels and comparison. + */ +uint32_t pwm_get_interrupt_mask(Pwm *p_pwm) +{ + return p_pwm->PWM_IMR2; +} +#endif + +#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMV70 || SAMV71 || SAME70 || SAMS70) +/** + * \brief Initialize PWM stepper motor mode. + * + * \param p_pwm Pointer to a PWM instance. + * \param pair PWM channels used by stepper motor. + * \param b_enable_gray Set true to enable gray count generation. Set false to disable it. + * \param b_down Set true to use down counter. Set false to use up counter. + */ +void pwm_stepper_motor_init(Pwm *p_pwm, pwm_stepper_motor_pair_t pair, + bool b_enable_gray, bool b_down) +{ + uint32_t motor = p_pwm->PWM_SMMR; + + motor &= ~((PWM_SMMR_GCEN0 | PWM_SMMR_DOWN0) << pair); + motor |= ((b_enable_gray | (b_down << 16)) << pair); + + p_pwm->PWM_SMMR = motor; +} +#endif + +#if SAM4E +/** + * \brief Change spread spectrum value. + * + * \param p_pwm Pointer to a PWM instance. + * \param p_channel Configurations of the specified PWM channel. + * \param ul_spread New spread spectrum value. + */ +void pwm_channel_update_spread(Pwm *p_pwm, pwm_channel_t *p_channel, + uint32_t ul_spread) +{ + /* Save new spread spectrum value */ + p_channel->ul_spread = ul_spread; + + /* Write spread spectrum update register */ + p_pwm->PWM_SSPUP = PWM_SSPUP_SPRDUP(ul_spread); +} + +/** + * \brief Change additional edge value and mode. + * + * \param p_pwm Pointer to a PWM instance. + * \param p_channel Configurations of the specified PWM channel. + * \param ul_additional_edge New additional edge value. + * \param additional_edge_mode New additional edge mode. + */ +void pwm_channel_update_additional_edge(Pwm *p_pwm, pwm_channel_t *p_channel, + uint32_t ul_additional_edge, + pwm_additional_edge_mode_t additional_edge_mode) +{ + /* Save new additional edge value */ + p_channel->ul_additional_edge = ul_additional_edge; + p_channel->additional_edge_mode = additional_edge_mode; + + /* Write channel additional edge update register */ + p_pwm->PWM_CH_NUM_0X400[p_channel->channel].PWM_CAEUPD = + PWM_CAEUPD_ADEDGVUP(ul_additional_edge) | additional_edge_mode; +} + +/** + * \brief Change polarity mode. + * + * \param p_pwm Pointer to a PWM instance. + * \param p_channel Configurations of the specified PWM channel. + * \param polarity_inversion_flag Polarity invertion. + * \param polarity_flag Polarity value. + */ +void pwm_channel_update_polarity_mode(Pwm *p_pwm, pwm_channel_t *p_channel, + bool polarity_inversion_flag, pwm_level_t polarity_value) +{ + if (polarity_inversion_flag) { + /* Set polarity inversion to the update register */ + p_pwm->PWM_CH_NUM_0X400[p_channel->channel].PWM_CMUPD = + PWM_CMUPD_CPOLINVUP; + } else { + /* Save new polarity value */ + p_channel->polarity = polarity_value; + + /* Write new polarity value to update register */ + if (polarity_value == PWM_HIGH) { + p_pwm->PWM_CH_NUM_0X400[p_channel->channel].PWM_CMUPD = + PWM_CMUPD_CPOLUP; + } else { + p_pwm->PWM_CH_NUM_0X400[p_channel->channel].PWM_CMUPD = 0; + } + } +} +#elif (SAMV70 || SAMV71 || SAME70 || SAMS70) +/** + * \brief Change spread spectrum value. + * + * \param p_pwm Pointer to a PWM instance. + * \param p_channel Configurations of the specified PWM channel. + * \param ul_spread New spread spectrum value. + */ +void pwm_channel_update_spread(Pwm *p_pwm, pwm_channel_t *p_channel, + uint32_t ul_spread) +{ + /* Save new spread spectrum value */ + p_channel->ul_spread = ul_spread; + + /* Write spread spectrum update register */ + p_pwm->PWM_SSPUP = PWM_SSPUP_SPRDUP(ul_spread); +} + +/** + * \brief Change leading edge value and mode. + * + * \param p_pwm Pointer to a PWM instance. + * \param p_channel Configurations of the specified PWM channel. + * \param ul_leading_edge_delay Leading-Edge Blanking Delay for TRGINx. + * \param leading_edge_blanking_mode New additional edge mode. + */ +void pwm_channel_update_leading_edge(Pwm *p_pwm, pwm_channel_t *p_channel, + uint32_t ul_leading_edge_delay, + pwm_leading_edge_blanking_mode_t leading_edge_blanking_mode) +{ + /* Save new leading edge value */ + p_channel->ul_leading_edge_delay = ul_leading_edge_delay; + p_channel->leading_edge_blanking_mode = leading_edge_blanking_mode; + + /* Write channel leading edge update register */ + if (p_channel->channel == 1) { + p_pwm->PWM_LEBR1 = PWM_LEBR1_LEBDELAY(ul_leading_edge_delay) | leading_edge_blanking_mode; + } else if (p_channel->channel == 2) { + p_pwm->PWM_LEBR2 = PWM_LEBR2_LEBDELAY(ul_leading_edge_delay) | leading_edge_blanking_mode; + } +} +#endif + +#if (SAMV70 || SAMV71 || SAME70 || SAMS70) +/** + * \brief Set dma duty. + * + * \param p_pwm Pointer to a PWM instance. + * \param ul_dma_duty_value The dma duty to be set. + */ +void pwm_set_dma_duty(Pwm *p_pwm, uint32_t ul_dma_duty_value) +{ + uint32_t ul_mask = p_pwm->PWM_DMAR & (~PWM_DMAR_DMADUTY_Msk); + p_pwm->PWM_DMAR = ul_mask | PWM_DMAR_DMADUTY(ul_dma_duty_value); +} + +/** + * \brief set external trigger mode. + * + * \param p_pwm Pointer to a PWM instance. + * \param p_channel Configurations of the specified PWM channel. + * \param ul_mode The external trigger mode to be set. + */ +void pwm_set_ext_trigger_mode(Pwm *p_pwm, pwm_channel_t *p_channel, uint32_t ul_mode) +{ + if (p_channel->channel == 1) { + p_pwm->PWM_ETRG1 = ul_mode; + } else if (p_channel->channel == 2) { + p_pwm->PWM_ETRG2 = ul_mode; + } +} +#endif + +//@} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/pwm/pwm.h b/hw-libs/drivers/SAMx70/ASF/sam/drivers/pwm/pwm.h new file mode 100644 index 000000000..9f3d340db --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/pwm/pwm.h @@ -0,0 +1,695 @@ +/** + * \file + * + * \brief Pulse Width Modulation (PWM) driver for SAM. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef PWM_H_INCLUDED +#define PWM_H_INCLUDED + +#include "compiler.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +#define PWM_INVALID_ARGUMENT 0xFFFF + +/** Definitions for PWM channel number */ +typedef enum _pwm_ch_t { + PWM_CHANNEL_0 = 0, + PWM_CHANNEL_1 = 1, + PWM_CHANNEL_2 = 2, + PWM_CHANNEL_3 = 3, +#if (SAM3XA) + PWM_CHANNEL_4 = 4, + PWM_CHANNEL_5 = 5, + PWM_CHANNEL_6 = 6, + PWM_CHANNEL_7 = 7 +#endif /* (SAM3XA) */ +} pwm_ch_t; + +/** Definitions for PWM channel alignment */ +typedef enum { + PWM_ALIGN_LEFT = (0 << 8), /* The period is left aligned. */ + PWM_ALIGN_CENTER = (1 << 8) /* The period is center aligned. */ +} pwm_align_t; + +/** Definitions for PWM level */ +typedef enum { + PWM_LOW = LOW, /* Low level */ + PWM_HIGH = HIGH, /* High level */ +#if (SAM4E || SAMV70 || SAMV71 || SAME70 || SAMS70) + PWM_HIGHZ, /* High Impedance */ +#endif +} pwm_level_t; + +/** Input parameters when initializing PWM */ +typedef struct { + /** Frequency of clock A in Hz (set 0 to turn it off) */ + uint32_t ul_clka; + /** Frequency of clock B in Hz (set 0 to turn it off) */ + uint32_t ul_clkb; + /** Frequency of master clock in Hz */ + uint32_t ul_mck; +} pwm_clock_t; + +#if (SAM3U || SAM3S || SAM3XA || SAM4S || SAM4E || SAMV70 || SAMV71 || SAME70 || SAMS70) +/** Definitions for PWM channels used by motor stepper */ +typedef enum { + PWM_STEPPER_MOTOR_CH_0_1 = 0, /* Channel 0 and 1 */ + PWM_STEPPER_MOTOR_CH_2_3 = 1, /* Channel 2 and 3 */ +#if (SAM3XA) + PWM_STEPPER_MOTOR_CH_4_5 = 2, /* Channel 4 and 5 */ + PWM_STEPPER_MOTOR_CH_6_7 = 3 /* Channel 6 and 7 */ +#endif /* (SAM3XA) */ +} pwm_stepper_motor_pair_t; + +/** Definitions for PWM synchronous channels update mode */ +typedef enum { + PWM_SYNC_UPDATE_MODE_0 = PWM_SCM_UPDM_MODE0, + PWM_SYNC_UPDATE_MODE_1 = PWM_SCM_UPDM_MODE1, + PWM_SYNC_UPDATE_MODE_2 = PWM_SCM_UPDM_MODE2 +} pwm_sync_update_mode_t; + +/** Definitions for PWM event */ +typedef enum { + PWM_EVENT_PERIOD_END = (0 << 10), /* The channel counter event occurs at the end of the PWM period. */ + PWM_EVENT_PERIOD_HALF_END = (1 << 10) /* The channel counter event occurs at the half of the PWM period. */ +} pwm_counter_event_t; + +/** Definitions for PWM fault input ID */ +typedef enum { +#if (SAM3U) + PWM_FAULT_MAINOSC = (1 << 0), + PWM_FAULT_PWMFI2 = (1 << 1), + PWM_FAULT_PWMFI0 = (1 << 2), + PWM_FAULT_PWMFI1 = (1 << 3), +#elif (SAM3S || SAM4S ) + PWM_FAULT_PWMFI0 = (1 << 0), + PWM_FAULT_MAINOSC = (1 << 1), + PWM_FAULT_ADC = (1 << 2), + PWM_FAULT_ACC = (1 << 3), + PWM_FAULT_TIMER_0 = (1 << 4), + PWM_FAULT_TIMER_1 = (1 << 5), +#elif (SAM4E ) + PWM_FAULT_MAINOSC = (1 << 0), + PWM_FAULT_ADC = (1 << 1), + PWM_FAULT_PWMFI0 = (1 << 2), + PWM_FAULT_PWMFI1 = (1 << 3), + PWM_FAULT_PWMFI2 = (1 << 4), + PWM_FAULT_PWMFI3 = (1 << 5), + PWM_FAULT_PWMFI4 = (1 << 6), + PWM_FAULT_PWMFI5 = (1 << 7), +#elif (SAMV70 || SAMV71 || SAME70 || SAMS70) + PWM_FAULT_PWMC0_PWMFI0 = (1 << 0), + PWM_FAULT_PWMC0_PWMFI1 = (1 << 1), + PWM_FAULT_PWMC0_PWMFI2 = (1 << 2), + PWM_FAULT_PWMC1_PWMFI0 = (1 << 0), + PWM_FAULT_PWMC1_PWMFI1 = (1 << 1), + PWM_FAULT_PWMC1_PWMFI2 = (1 << 2), + PWM_FAULT_MAINOSC = (1 << 3), + PWM_FAULT_AFEC0 = (1 << 4), + PWM_FAULT_AFEC1 = (1 << 5), + PWM_FAULT_ACC = (1 << 6), + PWM_FAULT_TIMER_0 = (1 << 7), + PWM_FAULT_TIMER_1 = (1 << 7), +#elif (SAM3XA) + PWM_FAULT_PWMFI0 = (1 << 0), + PWM_FAULT_PWMFI1 = (1 << 1), + PWM_FAULT_PWMFI2 = (1 << 2), + PWM_FAULT_MAINOSC = (1 << 3), + PWM_FAULT_ADC = (1 << 4), + PWM_FAULT_TIMER_0 = (1 << 5), +#endif +} pwm_fault_id_t; + +/** Definitions of PWM register group */ +typedef enum { + PWM_GROUP_CLOCK = (1 << 0), + PWM_GROUP_DISABLE = (1 << 1), + PWM_GROUP_MODE = (1 << 2), + PWM_GROUP_PERIOD = (1 << 3), + PWM_GROUP_DEAD_TIME = (1 << 4), + PWM_GROUP_FAULT = (1 << 5) +} pwm_protect_reg_group_t; + +/** Definitions for PWM comparison interrupt */ +typedef enum { + PWM_CMP_MATCH = 8, /* Comparison unit match */ + PWM_CMP_UPDATE = 16 /* Comparison unit update */ +} pwm_cmp_interrupt_t; + +/** Definitions for PWM comparison unit */ +typedef enum { + PWM_CMP_UNIT_0 = 0, + PWM_CMP_UNIT_1 = 1, + PWM_CMP_UNIT_2 = 2, + PWM_CMP_UNIT_3 = 3, + PWM_CMP_UNIT_4 = 4, + PWM_CMP_UNIT_5 = 5, + PWM_CMP_UNIT_6 = 6, + PWM_CMP_UNIT_7 = 7 +} pmc_cmp_unit_t; + +/** Definitions for PWM PDC transfer request mode */ +typedef enum { + PWM_PDC_UPDATE_PERIOD_ELAPSED = (0 << 20), /* PDC transfer request is set as soon as the update period elapses. */ + PWM_PDC_COMPARISON_MATCH = (1 << 20) /* PDC transfer request is set as soon as the selected comparison matches. */ +} pwm_pdc_request_mode_t; + +/** Definitions for PWM PDC transfer interrupt */ +typedef enum { + PWM_PDC_TX_END = (1 << 1), /* PDC Tx end */ + PWM_PDC_TX_EMPTY = (1 << 2) /* PDC Tx buffer empty */ +} pwm_pdc_interrupt_t; + +/** Definitions for PWM synchronous channels interrupt */ +typedef enum { + PWM_SYNC_WRITE_READY = (1 << 0), /* Write Ready for Synchronous Channels Update */ + PWM_SYNC_UNDERRUN = (1 << 3) /* Synchronous Channels Update Underrun Error */ +} pwm_sync_interrupt_t; + +#if (SAM4E || SAMV70 || SAMV71 || SAME70 || SAMS70) +typedef enum { + PWM_SPREAD_SPECTRUM_MODE_TRIANGULAR = 0, + PWM_SPREAD_SPECTRUM_MODE_RANDOM +} pwm_spread_spectrum_mode_t; +#if (SAMV70 || SAMV71 || SAME70 || SAMS70) +typedef enum { + PWM_LEADING_EDGE1_MODE_LINC = PWM_LEBR1_PWMLFEN, + PWM_LEADING_EDGE1_MODE_LDEC = PWM_LEBR1_PWMLREN, + PWM_LEADING_EDGE1_MODE_HINC = PWM_LEBR1_PWMHFEN, + PWM_LEADING_EDGE1_MODE_HDEC = PWM_LEBR1_PWMHREN, + PWM_LEADING_EDGE2_MODE_LINC = PWM_LEBR2_PWMLFEN, + PWM_LEADING_EDGE2_MODE_LDEC = PWM_LEBR2_PWMLREN, + PWM_LEADING_EDGE2_MODE_HINC = PWM_LEBR2_PWMHFEN, + PWM_LEADING_EDGE2_MODE_HDEC = PWM_LEBR2_PWMHREN, +} pwm_leading_edge_blanking_mode_t; +#else +typedef enum { + PWM_ADDITIONAL_EDGE_MODE_INC = PWM_CAE_ADEDGM_INC, + PWM_ADDITIONAL_EDGE_MODE_DEC = PWM_CAE_ADEDGM_DEC, + PWM_ADDITIONAL_EDGE_MODE_BOTH = PWM_CAE_ADEDGM_BOTH, +} pwm_additional_edge_mode_t; +#endif +#endif + +/** Configurations of a PWM channel output */ +typedef struct { + /** Boolean of using override output as PWMH */ + bool b_override_pwmh; + /** Boolean of using override output as PWML */ + bool b_override_pwml; + /** Level of override output for PWMH */ + pwm_level_t override_level_pwmh; + /** Level of override output for PWML */ + pwm_level_t override_level_pwml; +} pwm_output_t; + +/** Configurations of PWM comparison */ +typedef struct { + /** Comparison unit number */ + uint32_t unit; + /** Boolean of comparison enable */ + bool b_enable; + /** Comparison value */ + uint32_t ul_value; + /** Comparison mode */ + bool b_is_decrementing; + /** Comparison trigger value */ + uint32_t ul_trigger; + /** Comparison period value */ + uint32_t ul_period; + /** Comparison update period value */ + uint32_t ul_update_period; + /** Boolean of generating a match pulse on PWM event line 0 */ + bool b_pulse_on_line_0; + /** Boolean of generating a match pulse on PWM event line 1 */ + bool b_pulse_on_line_1; +} pwm_cmp_t; + +/** Configuration of PWM fault input behaviors */ +typedef struct { + /** Fault ID */ + pwm_fault_id_t fault_id; + /** Polarity of fault input */ + pwm_level_t polarity; + /** Boolean of clearing fault flag */ + bool b_clear; + /** Boolean of fault filtering */ + bool b_filtered; +} pwm_fault_t; + +/** Structure of PWM write-protect information */ +typedef struct { + /** Bitmask of PWM register group for write protect hardware status */ + uint32_t ul_hw_status; + /** Bitmask of PWM register group for write protect software status */ + uint32_t ul_sw_status; + /** Offset address of PWM register in which a write access has been attempted */ + uint32_t ul_offset; +} pwm_protect_t; +#endif /* (SAM3U || SAM3S || SAM3XA || SAM4S || SAM4E || SAMV70 || SAMV71 || SAME70 || SAMS70) */ + +/** Input parameters when configuring a PWM channel mode */ +typedef struct { + /** Channel number */ + uint32_t channel; + /** Channel prescaler */ + uint32_t ul_prescaler; + /** Channel alignment */ + pwm_align_t alignment; + /** Channel initial polarity */ + pwm_level_t polarity; + /** Duty Cycle Value */ + uint32_t ul_duty; + /** Period Cycle Value */ + uint32_t ul_period; + +#if (SAM3U || SAM3S || SAM3XA || SAM4S || SAM4E || SAMV70 || SAMV71 || SAME70 || SAMS70) + /** Channel counter event */ + pwm_counter_event_t counter_event; + /** Boolean of channel dead-time generator */ + bool b_deadtime_generator; + /** Boolean of channel dead-time PWMH output inverted */ + bool b_pwmh_output_inverted; + /** Boolean of channel dead-time PWML output inverted */ + bool b_pwml_output_inverted; + /** Dead-time Value for PWMH Output */ + uint16_t us_deadtime_pwmh; + /** Dead-time Value for PWML Output */ + uint16_t us_deadtime_pwml; + /** Channel output */ + pwm_output_t output_selection; + /** Boolean of Synchronous Channel */ + bool b_sync_ch; + /** Fault ID of the channel */ + pwm_fault_id_t fault_id; + /** Channel PWMH output level in fault protection */ + pwm_level_t ul_fault_output_pwmh; + /** Channel PWML output level in fault protection */ + pwm_level_t ul_fault_output_pwml; +#endif /* (SAM3U || SAM3S || SAM3XA || SAM4S || SAM4E || SAMV70 || SAMV71 || SAME70 || SAMS70) */ +#if SAM4E + /** Spread Spectrum Value */ + uint32_t ul_spread; + /** Spread Spectrum Mode */ + pwm_spread_spectrum_mode_t spread_spectrum_mode; + /** Additional Edge Value */ + uint32_t ul_additional_edge; + /** Additional Edge Mode */ + pwm_additional_edge_mode_t additional_edge_mode; +#elif (SAMV70 || SAMV71 || SAME70 || SAMS70) + /** Spread Spectrum Value */ + uint32_t ul_spread; + /** Spread Spectrum Mode */ + pwm_spread_spectrum_mode_t spread_spectrum_mode; + /** Leading Edge Value */ + uint32_t ul_leading_edge_delay; + /** Leading Edge Mode */ + pwm_leading_edge_blanking_mode_t leading_edge_blanking_mode; + /** PPM Mode in Channel mode */ + uint32_t ul_ppm_mode; +#endif +} pwm_channel_t; + + +uint32_t pwm_init(Pwm *p_pwm, pwm_clock_t *clock_config); +uint32_t pwm_channel_init(Pwm *p_pwm, pwm_channel_t *p_channel); +uint32_t pwm_channel_update_period(Pwm *p_pwm, pwm_channel_t *p_channel, + uint32_t ul_period); +uint32_t pwm_channel_update_duty(Pwm *p_pwm, pwm_channel_t *p_channel, + uint32_t ul_duty); +uint32_t pwm_channel_get_counter(Pwm *p_pwm, pwm_channel_t *p_channel); +void pwm_channel_enable(Pwm *p_pwm, uint32_t ul_channel); +void pwm_channel_disable(Pwm *p_pwm, uint32_t ul_channel); +uint32_t pwm_channel_get_status(Pwm *p_pwm); +uint32_t pwm_channel_get_interrupt_status(Pwm *p_pwm); +uint32_t pwm_channel_get_interrupt_mask(Pwm *p_pwm); +void pwm_channel_enable_interrupt(Pwm *p_pwm, uint32_t ul_event, + uint32_t ul_fault); +void pwm_channel_disable_interrupt(Pwm *p_pwm, uint32_t ul_event, + uint32_t ul_fault); + +#if (SAM3U || SAM3S || SAM3XA || SAM4S || SAM4E || SAMV70 || SAMV71 || SAME70 || SAMS70) +void pwm_channel_update_output(Pwm *p_pwm, pwm_channel_t *p_channel, + pwm_output_t *p_output, bool b_sync); +void pwm_channel_update_dead_time(Pwm *p_pwm, pwm_channel_t *p_channel, + uint16_t us_deadtime_pwmh, uint16_t us_deadtime_pwml); + +uint32_t pwm_fault_init(Pwm *p_pwm, pwm_fault_t *p_fault); +uint32_t pwm_fault_get_status(Pwm *p_pwm); +pwm_level_t pwm_fault_get_input_level(Pwm *p_pwm, pwm_fault_id_t id); +void pwm_fault_clear_status(Pwm *p_pwm, pwm_fault_id_t id); + +uint32_t pwm_cmp_init(Pwm *p_pwm, pwm_cmp_t *p_cmp); +uint32_t pwm_cmp_change_setting(Pwm *p_pwm, pwm_cmp_t *p_cmp); +uint32_t pwm_cmp_get_period_counter(Pwm *p_pwm, uint32_t ul_cmp_unit); +uint32_t pwm_cmp_get_update_counter(Pwm *p_pwm, uint32_t ul_cmp_unit); +void pwm_cmp_enable_interrupt(Pwm *p_pwm, uint32_t ul_sources, + pwm_cmp_interrupt_t type); +void pwm_cmp_disable_interrupt(Pwm *p_pwm, uint32_t ul_sources, + pwm_cmp_interrupt_t type); +#if !(SAMV70 || SAMV71 || SAME70 || SAMS70) +void pwm_pdc_set_request_mode(Pwm *p_pwm, pwm_pdc_request_mode_t request_mode, + uint32_t ul_cmp_unit); + +void pwm_pdc_enable_interrupt(Pwm *p_pwm, uint32_t ul_sources); +void pwm_pdc_disable_interrupt(Pwm *p_pwm, uint32_t ul_sources); +#endif +uint32_t pwm_sync_init(Pwm *p_pwm, pwm_sync_update_mode_t mode, + uint32_t ul_update_period); +void pwm_sync_unlock_update(Pwm *p_pwm); +void pwm_sync_change_period(Pwm *p_pwm, uint32_t ul_update_period); +uint32_t pwm_sync_get_period_counter(Pwm * p_pwm); +void pwm_sync_enable_interrupt(Pwm *p_pwm, uint32_t ul_sources); +void pwm_sync_disable_interrupt(Pwm *p_pwm, uint32_t ul_sources); + +void pwm_enable_protect(Pwm *p_pwm, uint32_t ul_group, bool b_sw); +void pwm_disable_protect(Pwm *p_pwm, uint32_t ul_group); +bool pwm_get_protect_status(Pwm *p_pwm, pwm_protect_t * p_protect); + +uint32_t pwm_get_interrupt_status(Pwm *p_pwm); +uint32_t pwm_get_interrupt_mask(Pwm *p_pwm); +#endif /* (SAM3U || SAM3S || SAM3XA || SAM4S || SAM4E || SAMV70 || SAMV71 || SAME70 || SAMS70) */ + +#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMV70 || SAMV71 || SAME70 || SAMS70) +void pwm_stepper_motor_init(Pwm *p_pwm, pwm_stepper_motor_pair_t pair, + bool b_enable_gray, bool b_down); +#endif /* (SAM3S || SAM3XA || SAM4S || SAM4E || SAMV70 || SAMV71 || SAME70 || SAMS70) */ + +#if SAM4E +void pwm_channel_update_spread(Pwm *p_pwm, pwm_channel_t *p_channel, + uint32_t ul_spread); +void pwm_channel_update_additional_edge(Pwm *p_pwm, pwm_channel_t *p_channel, + uint32_t ul_additional_edge, + pwm_additional_edge_mode_t additional_edge_mode); +void pwm_channel_update_polarity_mode(Pwm *p_pwm, pwm_channel_t *p_channel, + bool polarity_inversion_flag, pwm_level_t polarity_value); +#elif (SAMV70 || SAMV71 || SAME70 || SAMS70) +void pwm_channel_update_spread(Pwm *p_pwm, pwm_channel_t *p_channel, + uint32_t ul_spread); +void pwm_channel_update_leading_edge(Pwm *p_pwm, pwm_channel_t *p_channel, + uint32_t ul_leading_edge_delay, + pwm_leading_edge_blanking_mode_t leading_edge_blanking_mode); +#endif + +#if (SAMV70 || SAMV71 || SAME70 || SAMS70) +void pwm_set_dma_duty(Pwm *p_pwm, uint32_t ul_dma_duty_value); +void pwm_set_ext_trigger_mode(Pwm *p_pwm, pwm_channel_t *p_channel, uint32_t ul_mode); +#endif + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \page sam_pwm_quickstart Quickstart guide for SAM PWM module + * + * This is the quickstart guide for the \ref sam_drivers_pwm_group "PWM module", + * with step-by-step instructions on how to configure and use the drivers in a + * selection of use cases. + * + * The use cases contain several code fragments. The code fragments in the + * steps for setup can be copied into a custom initialization function, while + * the steps for usage can be copied into, e.g., the main application function. + * + * \section pwm_basic_use_case Basic use case + * In this basic use case, the PWM module is configured to: + * - Output a square wave on PWM channel 0 + * - The frequency of the square wave is 1KHz, 50% duty cycle + * - Clock A as the source clock + * - The output wave can be checked on the selected output pin + * + * \section pwm_basic_use_case_setup Setup steps + * + * \subsection pwm_basic_use_case_setup_prereq Prerequisites + * - \ref group_pmc "Power Management Controller driver" + * - \ref gpio_group "General Purpose I/O Management (gpio)" + * + * \subsection pwm_basic_use_case_setup_code Example code + * Add this PWM initialization code at the beginning of the main function: + * \code + pwm_channel_t pwm_channel_instance; + + pmc_enable_periph_clk(ID_PWM); + + pwm_channel_disable(PWM, PWM_CHANNEL_0); + + pwm_clock_t clock_setting = { + .ul_clka = 1000 * 100, + .ul_clkb = 0, + .ul_mck = 48000000 + }; + pwm_init(PWM, &clock_setting); + + pwm_channel_instance.ul_prescaler = PWM_CMR_CPRE_CLKA; + pwm_channel_instance.ul_period = 100; + pwm_channel_instance.ul_duty = 50; + pwm_channel_instance.channel = PWM_CHANNEL_0; + pwm_channel_init(PWM, &pwm_channel_instance); +\endcode + * + * \subsection pwm_basic_use_case_setup_flow Workflow + * -# Define the PWM channel instance in order to configure channel 0: + * - \code pwm_channel_t pwm_channel_instance; \endcode + * -# Enable the module clock for the PWM peripheral: + * - \code pmc_enable_periph_clk(ID_PWM); \endcode + * -# Disable PWM channel 0: + * - \code pwm_channel_disable(PWM, PWM_CHANNEL_0); \endcode + * -# Setup clock for PWM module: + * - \code + pwm_clock_t clock_setting = { + .ul_clka = 1000 * 100, + .ul_clkb = 0, + .ul_mck = 48000000 + }; + pwm_init(PWM, &clock_setting); +\endcode + * - \note 1. Only Clock A is configured (clock B is not used). + * 2. The expected frequency is 1KHz, system main clock is assumed to be 48MHz. + * -# Initialize channel instance and configure PWM channel 0, selecting clock A + * as its source clock and setting the duty cycle at 50%: + * - \code + pwm_channel_instance.ul_prescaler = PWM_CMR_CPRE_CLKA; + pwm_channel_instance.ul_period = 100; + pwm_channel_instance.ul_duty = 50; + pwm_channel_instance.channel = PWM_CHANNEL_0; + pwm_channel_init(PWM, &pwm_channel_instance); +\endcode + * - \note 1. Period is left-aligned and output waveform starts at a low level. + * 2. The pwm_channel_instance can be re-used to configure other PWM channels + * after setting the required parameters. + * + * \section pwm_basic_use_case_usage Usage steps + * + * \subsection pwm_basic_use_case_usage_code Example code + * Add to, e.g., main loop in application C-file: + * \code + pwm_channel_enable(PWM, PWM_CHANNEL_0); +\endcode + * + * \subsection pwm_basic_use_case_usage_flow Workflow + * -# Enable PWM channel 0 and output square wave on this channel: + * - \code pwm_channel_enable(PWM, PWM_CHANNEL_0); \endcode + * + * \section pwm_use_cases Advanced use cases + * For more advanced use of the pwm driver, see the following use cases: + * - \subpage pwm_use_case_1 : PWM channel 0 outputs square wave and duty cycle + * is updated in the PWM ISR. + */ + +/** + * \page pwm_use_case_1 Use case #1 + * + * In this use case, the PWM module is configured to: + * - Output a square wave on PWM channel 0 + * - The frequency of the square wave is 1KHz + * - The duty cycle is changed in the PWM ISR + * - Clock A as the source clock + * - The output wave can be checked on the selected output pin + * + * \section pwm_use_case_1_setup Setup steps + * + * \subsection pwm_use_case_1_setup_prereq Prerequisites + * - \ref group_pmc "Power Management Controller driver" + * - \ref gpio_group "General Purpose I/O Management (gpio)" + * + * \subsection pwm_use_case_1_setup_code Example code + * Add to application C-file: + * \code + pwm_channel_t pwm_channel_instance; +\endcode + * + * \code + void PWM_Handler(void) + { + static uint32_t ul_duty = 0; + uint32_t ul_status; + static uint8_t uc_countn = 0; + static uint8_t uc_flag = 1; + + ul_status = pwm_channel_get_interrupt_status(PWM); + if ((ul_status & PWM_CHANNEL_0) == PWM_CHANNEL_0) { + uc_count++; + if (uc_count == 10) { + if (uc_flag) { + ul_duty++; + if (ul_duty == 100) { + uc_flag = 0; + } + } else { + ul_duty--; + if (ul_duty == 0) { + uc_flag = 1; + } + } + uc_count = 0; + pwm_channel_instance.channel = PWM_CHANNEL_0; + pwm_channel_update_duty(PWM, &pwm_channel_instance, ul_duty); + } + } + } +\endcode + * + * \code + pmc_enable_periph_clk(ID_PWM); + + pwm_channel_disable(PWM, PWM_CHANNEL_0); + + pwm_clock_t clock_setting = { + .ul_clka = 1000 * 100, + .ul_clkb = 0, + .ul_mck = 48000000 + }; + pwm_init(PWM, &clock_setting); + + pwm_channel_instance.ul_prescaler = PWM_CMR_CPRE_CLKA; + pwm_channel_instance.ul_period = 100; + pwm_channel_instance.ul_duty = 0; + pwm_channel_instance.channel = PWM_CHANNEL_0; + pwm_channel_init(PWM, &pwm_channel_instance); + + pwm_channel_enable_interrupt(PWM, PWM_CHANNEL_0, 0); +\endcode + * + * \subsection pwm_use_case_1_setup_flow Workflow + * -# Define the PWM channel instance in order to configure channel 0: + * - \code pwm_channel_t pwm_channel_instance; \endcode + * -# Define the PWM interrupt handler in the application: + * - \code void PWM_Handler(void); \endcode + * -# In PWM_Handler(), get PWM interrupt status: + * - \code ul_status = pwm_channel_get_interrupt_status(PWM); \endcode + * -# In PWM_Handler(), check whether the PWM channel 0 interrupt has occurred: + * - \code + if ((ul_status & PWM_CHANNEL_0) == PWM_CHANNEL_0) { + } +\endcode + * -# In PWM_Handler(), if the PWM channel 0 interrupt has occurred, update the ul_duty value: + * - \code + uc_count++; + if (uc_count == 10) { + if (uc_flag) { + ul_duty++; + if (ul_duty >= 100) { + uc_flag = 0; + } + } else { + ul_duty--; + if (ul_duty == 0) { + uc_flag = 1; + } + } + } +\endcode + * -# In PWM_Handler(), if the ul_duty value has been updated, change the square wave duty: + * - \code + pwm_channel_instance.channel = PWM_CHANNEL_0; + pwm_channel_update_duty(PWM, &pwm_channel_instance, ul_duty); +\endcode + * -# Enable the PWM clock: + * - \code pmc_enable_periph_clk(ID_PWM); \endcode + * -# Disable PWM channel 0: + * - \code pwm_channel_disable(PWM, PWM_CHANNEL_0); \endcode + * -# Setup clock for PWM module: + * - \code + pwm_clock_t clock_setting = { + .ul_clka = 1000 * 100, + .ul_clkb = 0, + .ul_mck = 48000000 + }; + pwm_init(PWM, &clock_setting); +\endcode + * - \note 1. Only Clock A is configured (clock B is not used). + * 2. The expected frequency is 1KHz, system main clock is assumed to be 48Mhz. + * -# Initialize channel instance and configure PWM channel 0, selecting clock A + * as its source clock and setting the initial ducy as 0%: + * - \code + pwm_channel_instance.ul_prescaler = PWM_CMR_CPRE_CLKA; + pwm_channel_instance.ul_period = 100; + pwm_channel_instance.ul_duty = 0; + pwm_channel_instance.channel = PWM_CHANNEL_0; + pwm_channel_init(PWM, &pwm_channel_instance); +\endcode + * - \note 1. Period is left-aligned and output waveform starts at a low level. + * 2. The pwm_channel_instance can be re-used to configure other PWM channels + * after setting the required parameters. + * -# Enable channel 0 interrupt: + * - \code pwm_channel_enable_interrupt(PWM, PWM_CHANNEL_0, 0); \endcode + * - \note 1.In order to enable the PWM interrupt, the NVIC must be configured + * to enable the PWM interrupt. 2. When the channel 0 counter reaches the channel + * period, the interrupt (counter event) will occur. + * + * \section pwm_use_case_1_usage Usage steps + * + * \subsection pwm_use_case_1_usage_code Example code + * \code + pwm_channel_enable(PWM, PWM_CHANNEL_0); +\endcode + * + * \subsection pwn_use_case_1_usage_flow Workflow + * -# Enable PWM channel 0 and output square wave on this channel: + * - \code pwm_channel_enable(PWM, PWM_CHANNEL_0); \endcode + * + */ + +#endif /* PWM_H_INCLUDED */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/rtc/rtc.c b/hw-libs/drivers/SAMx70/ASF/sam/drivers/rtc/rtc.c new file mode 100644 index 000000000..fa1b6558f --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/rtc/rtc.c @@ -0,0 +1,931 @@ +/** + * \file + * + * \brief Real-Time Clock (RTC) driver for SAM. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "rtc.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \defgroup sam_drivers_rtc_group Real-Time Clock (RTC) + * + * See \ref sam_rtc_quickstart. + * + * The RTC provides a full binary-coded decimal (BCD) clock that includes + * century (19/20), year (with leap years), month, date, day, hour, minute + * and second. + * + * @{ + */ + +/* RTC Write Protect Key "RTC" in ASCII */ +#define RTC_WP_KEY (0x525443) + +/* The BCD code shift value */ +#define BCD_SHIFT 4 + +/* The BCD code mask value */ +#define BCD_MASK 0xfu + +/* The BCD mul/div factor value */ +#define BCD_FACTOR 10 + +/** + * \brief Set the RTC hour mode. + * + * \param p_rtc Pointer to an RTC instance. + * \param ul_mode 1 for 12-hour mode, 0 for 24-hour mode. + */ +void rtc_set_hour_mode(Rtc *p_rtc, uint32_t ul_mode) +{ + if (ul_mode) { + p_rtc->RTC_MR |= RTC_MR_HRMOD; + } else { + p_rtc->RTC_MR &= (~RTC_MR_HRMOD); + } +} + +/** + * \brief Get the RTC hour mode. + * + * \param p_rtc Pointer to an RTC instance. + * + * \return 1 for 12-hour mode, 0 for 24-hour mode. + */ +uint32_t rtc_get_hour_mode(Rtc *p_rtc) +{ + uint32_t ul_temp = p_rtc->RTC_MR; + + if (ul_temp & RTC_MR_HRMOD) { + return 1; + } else { + return 0; + } +} + +/** + * \brief Enable RTC interrupts. + * + * \param p_rtc Pointer to an RTC instance. + * \param ul_sources Interrupts to be enabled. + */ +void rtc_enable_interrupt(Rtc *p_rtc, uint32_t ul_sources) +{ + p_rtc->RTC_IER = ul_sources; +} + +/** + * \brief Disable RTC interrupts. + * + * \param p_rtc Pointer to an RTC instance. + * \param ul_sources Interrupts to be disabled. + */ +void rtc_disable_interrupt(Rtc *p_rtc, uint32_t ul_sources) +{ + p_rtc->RTC_IDR = ul_sources; +} + +/** + * \brief Read RTC interrupt mask. + * + * \param p_rtc Pointer to an RTC instance. + * + * \return The interrupt mask value. + */ +uint32_t rtc_get_interrupt_mask(Rtc *p_rtc) +{ + return p_rtc->RTC_IMR; +} + +/** + * \brief Get the RTC time value. + * + * \param p_rtc Pointer to an RTC instance. + * \param pul_hour Current hour, 24-hour mode. + * \param pul_minute Current minute. + * \param pul_second Current second. + */ +void rtc_get_time(Rtc *p_rtc, uint32_t *pul_hour, uint32_t *pul_minute, + uint32_t *pul_second) +{ + uint32_t ul_time; + uint32_t ul_temp; + + /* Get the current RTC time (multiple reads are necessary to insure a stable value). */ + ul_time = p_rtc->RTC_TIMR; + while (ul_time != p_rtc->RTC_TIMR) { + ul_time = p_rtc->RTC_TIMR; + } + + /* Hour */ + if (pul_hour) { + ul_temp = (ul_time & RTC_TIMR_HOUR_Msk) >> RTC_TIMR_HOUR_Pos; + *pul_hour = (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK); + + if ((ul_time & RTC_TIMR_AMPM) == RTC_TIMR_AMPM) { + *pul_hour += 12; + } + } + + /* Minute */ + if (pul_minute) { + ul_temp = (ul_time & RTC_TIMR_MIN_Msk) >> RTC_TIMR_MIN_Pos; + *pul_minute = (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK); + } + + /* Second */ + if (pul_second) { + ul_temp = (ul_time & RTC_TIMR_SEC_Msk) >> RTC_TIMR_SEC_Pos; + *pul_second = (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK); + } +} + +/** + * \brief Set the RTC time value. + * + * \param p_rtc Pointer to an RTC instance. + * \param ul_hour Current hour, 24-hour mode. + * \param ul_minute Current minute. + * \param ul_second Current second. + * + * \return 0 for OK, else invalid setting. + */ +uint32_t rtc_set_time(Rtc *p_rtc, uint32_t ul_hour, uint32_t ul_minute, + uint32_t ul_second) +{ + uint32_t ul_time = 0; + + /* If 12-hour mode, set AMPM bit */ + if ((p_rtc->RTC_MR & RTC_MR_HRMOD) == RTC_MR_HRMOD) { + if (ul_hour > 12) { + ul_hour -= 12; + ul_time |= RTC_TIMR_AMPM; + } + } + + /* Hour */ + ul_time |= ((ul_hour / BCD_FACTOR) << (RTC_TIMR_HOUR_Pos + BCD_SHIFT)) | + ((ul_hour % BCD_FACTOR) << RTC_TIMR_HOUR_Pos); + + /* Minute */ + ul_time |= ((ul_minute / BCD_FACTOR) << (RTC_TIMR_MIN_Pos + BCD_SHIFT)) | + ((ul_minute % BCD_FACTOR) << RTC_TIMR_MIN_Pos); + + /* Second */ + ul_time |= ((ul_second / BCD_FACTOR) << (RTC_TIMR_SEC_Pos + BCD_SHIFT)) | + ((ul_second % BCD_FACTOR) << RTC_TIMR_SEC_Pos); + + //Clear RTC_SR.SEC so we can tell when the second periodic event happens + p_rtc->RTC_SCCR = RTC_SCCR_SECCLR; + + //At this point we should not be in update mode (counting stopped) + if((p_rtc->RTC_CR & (RTC_CR_UPDTIM | RTC_CR_UPDCAL)) != 0) + p_rtc->RTC_CR &= ~(RTC_CR_UPDTIM | RTC_CR_UPDCAL); //If we are, clear it so it will start counting so the following will always succeed + + /* Update time register. Check the spec for the flow. */ + while ((p_rtc->RTC_SR & RTC_SR_SEC) != RTC_SR_SEC); + p_rtc->RTC_CR |= RTC_CR_UPDTIM; + while ((p_rtc->RTC_SR & RTC_SR_ACKUPD) != RTC_SR_ACKUPD); + p_rtc->RTC_SCCR = RTC_SCCR_ACKCLR; + p_rtc->RTC_TIMR = ul_time; + p_rtc->RTC_CR &= (~RTC_CR_UPDTIM); + + return (p_rtc->RTC_VER & RTC_VER_NVTIM); +} + +/** + * \brief Set the RTC alarm time value. + * + * \param p_rtc Pointer to an RTC instance. + * \param ul_hour_flag 1 for setting, 0 for not setting. + * \param ul_hour Alarm hour value, 24-hour mode. + * \param ul_minute_flag 1 for setting, 0 for not setting. + * \param ul_minute Alarm minute value. + * \param ul_second_flag 1 for setting, 0 for not setting. + * \param ul_second Alarm second value. + * + * \return 0 for OK, else invalid setting. + */ +uint32_t rtc_set_time_alarm(Rtc *p_rtc, + uint32_t ul_hour_flag, uint32_t ul_hour, + uint32_t ul_minute_flag, uint32_t ul_minute, + uint32_t ul_second_flag, uint32_t ul_second) +{ + uint32_t ul_alarm = 0; + + /* Hour alarm setting */ + if (ul_hour_flag) { + /* If 12-hour mode, set AMPM bit */ + if ((p_rtc->RTC_MR & RTC_MR_HRMOD) == RTC_MR_HRMOD) { + if (ul_hour > 12) { + ul_hour -= 12; + ul_alarm |= RTC_TIMR_AMPM; + } + } + + ul_alarm |= ((ul_hour / BCD_FACTOR) << (RTC_TIMR_HOUR_Pos + BCD_SHIFT)) | + ((ul_hour % BCD_FACTOR) << RTC_TIMR_HOUR_Pos); + } + + /* Minute alarm setting */ + if (ul_minute_flag) { + ul_alarm |= ((ul_minute / BCD_FACTOR) << (RTC_TIMR_MIN_Pos + BCD_SHIFT)) | + ((ul_minute % BCD_FACTOR) << RTC_TIMR_MIN_Pos); + } + + /* Second alarm setting */ + if (ul_second_flag) { + ul_alarm |= ((ul_second / BCD_FACTOR) << (RTC_TIMR_SEC_Pos + BCD_SHIFT)) | + ((ul_second % BCD_FACTOR) << RTC_TIMR_SEC_Pos); + } + + p_rtc->RTC_TIMALR &= ~(RTC_TIMALR_SECEN | RTC_TIMALR_MINEN | RTC_TIMALR_HOUREN); + p_rtc->RTC_TIMALR = ul_alarm; + p_rtc->RTC_TIMALR |= (RTC_TIMALR_SECEN | RTC_TIMALR_MINEN | RTC_TIMALR_HOUREN); + + return (p_rtc->RTC_VER & RTC_VER_NVTIMALR); +} + +/** + * \brief Get the RTC date value. + * + * \param p_rtc Pointer to an RTC instance. + * \param pul_year Current year. + * \param pul_month Current month. + * \param pul_day Current day. + * \param pul_week Current day in current week. + */ +void rtc_get_date(Rtc *p_rtc, uint32_t *pul_year, uint32_t *pul_month, + uint32_t *pul_day, uint32_t *pul_week) +{ + uint32_t ul_date; + uint32_t ul_cent; + uint32_t ul_temp; + + /* Get the current date (multiple reads are necessary to insure a stable value). */ + ul_date = p_rtc->RTC_CALR; + while (ul_date != p_rtc->RTC_CALR) { + ul_date = p_rtc->RTC_CALR; + } + + /* Retrieve year */ + if (pul_year) { + ul_temp = (ul_date & RTC_CALR_CENT_Msk) >> RTC_CALR_CENT_Pos; + ul_cent = (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK); + ul_temp = (ul_date & RTC_CALR_YEAR_Msk) >> RTC_CALR_YEAR_Pos; + *pul_year = (ul_cent * BCD_FACTOR * BCD_FACTOR) + + (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK); + } + + /* Retrieve month */ + if (pul_month) { + ul_temp = (ul_date & RTC_CALR_MONTH_Msk) >> RTC_CALR_MONTH_Pos; + *pul_month = (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK); + } + + /* Retrieve day */ + if (pul_day) { + ul_temp = (ul_date & RTC_CALR_DATE_Msk) >> RTC_CALR_DATE_Pos; + *pul_day = (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK); + } + + /* Retrieve week */ + if (pul_week) { + *pul_week = ((ul_date & RTC_CALR_DAY_Msk) >> RTC_CALR_DAY_Pos); + } +} + +/** + * \brief Set the RTC date. + * + * \param p_rtc Pointer to an RTC instance. + * \param ul_year Current year. + * \param ul_month Current month. + * \param ul_day Current day. + * \param ul_week Current day in current week. + * + * \return 0 for OK, else invalid setting. + */ +uint32_t rtc_set_date(Rtc *p_rtc, uint32_t ul_year, uint32_t ul_month, + uint32_t ul_day, uint32_t ul_week) +{ + uint32_t ul_date = 0; + + /* Cent */ + ul_date |= ((ul_year / BCD_FACTOR / BCD_FACTOR / BCD_FACTOR) << + (RTC_CALR_CENT_Pos + BCD_SHIFT) | + ((ul_year / BCD_FACTOR / BCD_FACTOR) % BCD_FACTOR) << RTC_CALR_CENT_Pos); + + /* Year */ + ul_date |= (((ul_year / BCD_FACTOR) % BCD_FACTOR) << + (RTC_CALR_YEAR_Pos + BCD_SHIFT)) | + ((ul_year % BCD_FACTOR) << RTC_CALR_YEAR_Pos); + + /* Month */ + ul_date |= ((ul_month / BCD_FACTOR) << (RTC_CALR_MONTH_Pos + BCD_SHIFT)) | + ((ul_month % BCD_FACTOR) << RTC_CALR_MONTH_Pos); + + /* Week */ + ul_date |= (ul_week << RTC_CALR_DAY_Pos); + + /* Day */ + ul_date |= ((ul_day / BCD_FACTOR) << (RTC_CALR_DATE_Pos + BCD_SHIFT)) | + ((ul_day % BCD_FACTOR) << RTC_CALR_DATE_Pos); + + //Clear RTC_SR.SEC so we can tell when the second periodic event happens + p_rtc->RTC_SCCR = RTC_SCCR_SECCLR; + + //At this point we should not be in update mode (counting stopped) + if((p_rtc->RTC_CR & (RTC_CR_UPDTIM | RTC_CR_UPDCAL)) != 0) + p_rtc->RTC_CR &= ~(RTC_CR_UPDTIM | RTC_CR_UPDCAL); //If we are, clear it so it will start counting so the following will always succeed + + /* Update calendar register. Check the spec for the flow. */ + while ((p_rtc->RTC_SR & RTC_SR_SEC) != RTC_SR_SEC); + p_rtc->RTC_CR |= RTC_CR_UPDCAL; + while ((p_rtc->RTC_SR & RTC_SR_ACKUPD) != RTC_SR_ACKUPD); + p_rtc->RTC_SCCR = RTC_SCCR_ACKCLR; + p_rtc->RTC_CALR = ul_date; + p_rtc->RTC_CR &= (~RTC_CR_UPDCAL); + + return (p_rtc->RTC_VER & RTC_VER_NVCAL); +} + +/** + * \brief Set the RTC alarm date value. + * + * \param p_rtc Pointer to an RTC instance. + * \param ul_month_flag 1 for setting, 0 for not setting. + * \param ul_month Alarm month value. + * \param ul_day_flag 1 for setting, 0 for not setting. + * \param ul_day Alarm day value. + * + * \return 0 for OK, else invalid setting. + */ +uint32_t rtc_set_date_alarm(Rtc *p_rtc, + uint32_t ul_month_flag, uint32_t ul_month, + uint32_t ul_day_flag, uint32_t ul_day) +{ + uint32_t ul_alarm = 0; + + /* Month alarm setting */ + if (ul_month_flag) { + ul_alarm |= ((ul_month / BCD_FACTOR) << (RTC_CALR_MONTH_Pos + BCD_SHIFT)) | + ((ul_month % BCD_FACTOR) << RTC_CALR_MONTH_Pos); + } + + /* Day alarm setting */ + if (ul_day_flag) { + ul_alarm |= ((ul_day / BCD_FACTOR) << (RTC_CALR_DATE_Pos + BCD_SHIFT)) | + ((ul_day % BCD_FACTOR) << RTC_CALR_DATE_Pos); + } + + /* Set alarm */ + p_rtc->RTC_CALALR &= ~(RTC_CALALR_MTHEN | RTC_CALALR_DATEEN); + p_rtc->RTC_CALALR = ul_alarm; + p_rtc->RTC_CALALR |= (RTC_CALALR_MTHEN | RTC_CALALR_DATEEN); + + return (p_rtc->RTC_VER & RTC_VER_NVCALALR); +} + +/** + * \brief Clear the RTC time alarm setting. + * + * \param p_rtc Pointer to an RTC instance. + */ +void rtc_clear_time_alarm(Rtc *p_rtc) +{ + p_rtc->RTC_TIMALR = 0; +} + +/** + * \brief Clear the RTC date alarm setting. + * + * \param p_rtc Pointer to an RTC instance. + */ +void rtc_clear_date_alarm(Rtc *p_rtc) +{ + /* Need a valid value without enabling */ + p_rtc->RTC_CALALR = RTC_CALALR_MONTH(0x01) | RTC_CALALR_DATE(0x01); +} + +/** + * \brief Get the RTC status. + * + * \param p_rtc Pointer to an RTC instance. + * + * \return Status of the RTC. + */ +uint32_t rtc_get_status(Rtc *p_rtc) +{ + return (p_rtc->RTC_SR); +} + +/** + * \brief Set the RTC SCCR to clear status bits. + * + * \param p_rtc Pointer to an RTC instance. + * \param ul_clear Some flag bits which will be cleared. + */ +void rtc_clear_status(Rtc *p_rtc, uint32_t ul_clear) +{ + p_rtc->RTC_SCCR = ul_clear; +} + +/** + * \brief Get the RTC valid entry. + * + * \param p_rtc Pointer to an RTC instance. + * + * \return 0 for no invalid data, else has contained invalid data. + */ +uint32_t rtc_get_valid_entry(Rtc *p_rtc) +{ + return (p_rtc->RTC_VER); +} + +/** + * \brief Set the RTC time event selection. + * + * \param p_rtc Pointer to an RTC instance. + * \param ul_selection Time event selection to be enabled. + */ +void rtc_set_time_event(Rtc *p_rtc, uint32_t ul_selection) +{ + p_rtc->RTC_CR &= ~RTC_CR_TIMEVSEL_Msk; + p_rtc->RTC_CR |= (ul_selection << RTC_CR_TIMEVSEL_Pos) & RTC_CR_TIMEVSEL_Msk; +} + +/** + * \brief Set the RTC calendar event selection. + * + * \param p_rtc Pointer to an RTC instance. + * \param ul_selection Calendar event selection to be enabled.. + */ +void rtc_set_calendar_event(Rtc *p_rtc, uint32_t ul_selection) +{ + p_rtc->RTC_CR &= ~RTC_CR_CALEVSEL_Msk; + p_rtc->RTC_CR |= (ul_selection << RTC_CR_CALEVSEL_Pos) & RTC_CR_CALEVSEL_Msk; +} + +#if ((SAM3S8) || (SAM3SD8) || (SAM4S) || (SAM4N) || (SAM4C) || (SAMG) || (SAM4CP) || (SAM4CM) || defined(__DOXYGEN__)) +/** + * \brief Set the RTC calendar mode. + * + * \note This function is only available on SAM3S8/3SD8/4S/4N/4C/G devices. + * + * \param p_rtc Pointer to an RTC instance. + * \param ul_mode 1 for Persian mode,0 for Gregorian mode. + */ +void rtc_set_calendar_mode(Rtc *p_rtc, uint32_t ul_mode) +{ + if (ul_mode) { + p_rtc->RTC_MR |= RTC_MR_PERSIAN; + } else { + p_rtc->RTC_MR &= (~RTC_MR_PERSIAN); + } +} + +/** + * \brief Get the RTC calendar mode. + * + * \note This function is only available on SAM3S8/3SD8/4S/4N/4C/G devices. + * + * \param p_rtc Pointer to an RTC instance. + * + * \return 1 for Persian calendar, 0 for Gregorian calendar. + */ +uint32_t rtc_get_calendar_mode(Rtc *p_rtc) +{ + uint32_t ul_temp = p_rtc->RTC_MR; + + if (ul_temp & RTC_MR_PERSIAN) { + return 1; + } else { + return 0; + } +} + +/** + * \brief Set the RTC calibration. + * + * \note This function is only available on SAM3S8/3SD8/4S/4N/4C/G devices. + * + * \param p_rtc Pointer to an RTC instance. + * \param ul_direction_ppm Positive/negative correction. + * \param ul_correction Correction value. + * \param ul_range_ppm Low/high range correction. + */ +void rtc_set_calibration(Rtc *p_rtc, uint32_t ul_direction_ppm, + uint32_t ul_correction, uint32_t ul_range_ppm) +{ + uint32_t ul_temp; + + ul_temp = p_rtc->RTC_MR; + + if (ul_direction_ppm) { + ul_temp |= RTC_MR_NEGPPM; + } else { + ul_temp &= (~RTC_MR_NEGPPM); + } + + ul_temp &= (~RTC_MR_CORRECTION_Msk); + ul_temp |= RTC_MR_CORRECTION(ul_correction); + + if (ul_range_ppm) { + ul_temp |= RTC_MR_HIGHPPM; + } else { + ul_temp &= (~RTC_MR_HIGHPPM); + } + + p_rtc->RTC_MR = ul_temp; +} +#endif + +#if ((SAM3S8) || (SAM3SD8) || (SAM4S) || (SAM4C) || (SAMG) || (SAM4CP) || (SAM4CM) || SAMV71 || SAMV70 || SAME70 || SAMS70 || defined(__DOXYGEN__)) +/** + * \brief Set the RTC output waveform. + * + * \note This function is only available on SAM3S8/3SD8/4S/4C/G/V/S/E devices. + * + * \param p_rtc Pointer to an RTC instance. + * \param ul_channel Output channel selection. + * \param ul_value Output source selection value. + */ +void rtc_set_waveform(Rtc *p_rtc, uint32_t ul_channel, uint32_t ul_value) +{ + if (ul_channel == 0) { + switch (ul_value) { + case 0: + p_rtc->RTC_MR &= ~RTC_MR_OUT0_Msk; + p_rtc->RTC_MR |= RTC_MR_OUT0_NO_WAVE; + break; + + case 1: + p_rtc->RTC_MR &= ~RTC_MR_OUT0_Msk; + p_rtc->RTC_MR |= RTC_MR_OUT0_FREQ1HZ; + break; + + case 2: + p_rtc->RTC_MR &= ~RTC_MR_OUT0_Msk; + p_rtc->RTC_MR |= RTC_MR_OUT0_FREQ32HZ; + break; + + case 3: + p_rtc->RTC_MR &= ~RTC_MR_OUT0_Msk; + p_rtc->RTC_MR |= RTC_MR_OUT0_FREQ64HZ; + break; + + case 4: + p_rtc->RTC_MR &= ~RTC_MR_OUT0_Msk; + p_rtc->RTC_MR |= RTC_MR_OUT0_FREQ512HZ; + break; + +#if (!SAMG) + case 5: + p_rtc->RTC_MR &= ~RTC_MR_OUT0_Msk; + p_rtc->RTC_MR |= RTC_MR_OUT0_ALARM_TOGGLE; + break; +#endif + + case 6: + p_rtc->RTC_MR &= ~RTC_MR_OUT0_Msk; + p_rtc->RTC_MR |= RTC_MR_OUT0_ALARM_FLAG; + break; + +#if (!SAMG) + case 7: + p_rtc->RTC_MR &= ~RTC_MR_OUT0_Msk; + p_rtc->RTC_MR |= RTC_MR_OUT0_PROG_PULSE; + break; +#endif + + default: + break; + } + } else { + #if (!SAM4C && !SAM4CP && !SAM4CM) + switch (ul_value) { + case 0: + p_rtc->RTC_MR &= ~RTC_MR_OUT1_Msk; + p_rtc->RTC_MR |= RTC_MR_OUT1_NO_WAVE; + break; + + case 1: + p_rtc->RTC_MR &= ~RTC_MR_OUT1_Msk; + p_rtc->RTC_MR |= RTC_MR_OUT1_FREQ1HZ; + break; + + case 2: + p_rtc->RTC_MR &= ~RTC_MR_OUT1_Msk; + p_rtc->RTC_MR |= RTC_MR_OUT1_FREQ32HZ; + break; + + case 3: + p_rtc->RTC_MR &= ~RTC_MR_OUT1_Msk; + p_rtc->RTC_MR |= RTC_MR_OUT1_FREQ64HZ; + break; + + case 4: + p_rtc->RTC_MR &= ~RTC_MR_OUT1_Msk; + p_rtc->RTC_MR |= RTC_MR_OUT1_FREQ512HZ; + break; + +#if (!SAMG) + case 5: + p_rtc->RTC_MR &= ~RTC_MR_OUT1_Msk; + p_rtc->RTC_MR |= RTC_MR_OUT1_ALARM_TOGGLE; + break; +#endif + + case 6: + p_rtc->RTC_MR &= ~RTC_MR_OUT1_Msk; + p_rtc->RTC_MR |= RTC_MR_OUT1_ALARM_FLAG; + break; + +#if (!SAMG) + case 7: + p_rtc->RTC_MR &= ~RTC_MR_OUT1_Msk; + p_rtc->RTC_MR |= RTC_MR_OUT1_PROG_PULSE; + break; +#endif + + default: + break; + } + #endif + } +} + +#if ((SAM3S8) || (SAM3SD8) || (SAM4S) || (SAM4C) || SAMV71 || SAMV70 || SAME70 || SAMS70 || defined(__DOXYGEN__)) +/** + * \brief Set the pulse output waveform parameters. + * + * \note This function is only available on SAM3S8/3SD8/4S/4C/V/S/E devices. + * + * \param p_rtc Pointer to an RTC instance. + * \param ul_time_high High duration of the output pulse. + * \param ul_period Period of the output pulse. + */ +void rtc_set_pulse_parameter(Rtc *p_rtc, uint32_t ul_time_high, + uint32_t ul_period) +{ + uint32_t ul_temp; + + ul_temp = p_rtc->RTC_MR; + + ul_temp |= (RTC_MR_THIGH_Msk & ((ul_time_high) << RTC_MR_THIGH_Pos)); + ul_temp |= (RTC_MR_TPERIOD_Msk & ((ul_period) << RTC_MR_TPERIOD_Pos)); + + p_rtc->RTC_MR = ul_temp; +} +#endif +#endif + + +#if ((SAM3N) || (SAM3U) || (SAM3XA) || defined(__DOXYGEN__)) +/** + * \brief Enable or disable write protection of RTC registers. + * + * \note This function is only available on SAM3N/3U/3XA devices. + * + * \param p_rtc Pointer to an RTC instance. + * \param ul_enable 1 to enable, 0 to disable. + */ +void rtc_set_writeprotect(Rtc *p_rtc, uint32_t ul_enable) +{ + if (ul_enable) { + p_rtc->RTC_WPMR = RTC_WPMR_WPKEY(RTC_WP_KEY) | RTC_WPMR_WPEN; + } else { + p_rtc->RTC_WPMR = RTC_WPMR_WPKEY(RTC_WP_KEY); + } +} +#endif /* ((SAM3N) || (SAM3U) || (SAM3XA)) */ + +#if SAM4C || SAM4CP || SAM4CM || defined(__DOXYGEN__) +/** + * \brief Get the RTC tamper time value. + * + * \note This function is only available on SAM4C devices. + * + * \note This function should be called before rtc_get_tamper_source() + * function call, Otherwise the tamper time will be cleared. + * + * \param p_rtc Pointer to an RTC instance. + * \param pul_hour Current hour, 24-hour mode. + * \param pul_minute Current minute. + * \param pul_second Current second. + * \param reg_num Current tamper register set number. + */ +void rtc_get_tamper_time(Rtc *p_rtc, uint32_t *pul_hour, uint32_t *pul_minute, + uint32_t *pul_second, uint8_t reg_num) +{ + uint32_t ul_time; + uint32_t ul_temp; + + /* Get the current RTC time (multiple reads are to insure a stable value). */ + ul_time = p_rtc->RTC_TS[reg_num].RTC_TSTR; + while (ul_time != p_rtc->RTC_TS[reg_num].RTC_TSTR) { + ul_time = p_rtc->RTC_TS[reg_num].RTC_TSTR; + } + + /* Hour */ + if (pul_hour) { + ul_temp = (ul_time & RTC_TSTR_HOUR_Msk) >> RTC_TSTR_HOUR_Pos; + *pul_hour = (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK); + + if ((ul_time & RTC_TSTR_AMPM) == RTC_TSTR_AMPM) { + *pul_hour += 12; + } + } + + /* Minute */ + if (pul_minute) { + ul_temp = (ul_time & RTC_TSTR_MIN_Msk) >> RTC_TSTR_MIN_Pos; + *pul_minute = (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK); + } + + /* Second */ + if (pul_second) { + ul_temp = (ul_time & RTC_TSTR_SEC_Msk) >> RTC_TSTR_SEC_Pos; + *pul_second = (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK); + } +} + +/** + * \brief Get the RTC tamper date. + * + * \note This function is only available on SAM4C devices. + * + * \note This function should be called before rtc_get_tamper_source() + * function call, Otherwise the tamper date will be cleared. + * + * \param p_rtc Pointer to an RTC instance. + * \param pul_year Current year. + * \param pul_month Current month. + * \param pul_day Current day. + * \param pul_week Current day in current week. + * \param reg_num Current tamper register set number. + */ +void rtc_get_tamper_date(Rtc *p_rtc, uint32_t *pul_year, uint32_t *pul_month, + uint32_t *pul_day, uint32_t *pul_week, uint8_t reg_num) +{ + uint32_t ul_date; + uint32_t ul_cent; + uint32_t ul_temp; + + /* Get the current date (multiple reads are to insure a stable value). */ + ul_date = p_rtc->RTC_TS[reg_num].RTC_TSDR; + while (ul_date != p_rtc->RTC_TS[reg_num].RTC_TSDR) { + ul_date = p_rtc->RTC_TS[reg_num].RTC_TSDR; + } + + /* Retrieve year */ + if (pul_year) { + ul_temp = (ul_date & RTC_TSDR_CENT_Msk) >> RTC_TSDR_CENT_Pos; + ul_cent = (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK); + ul_temp = (ul_date & RTC_TSDR_YEAR_Msk) >> RTC_TSDR_YEAR_Pos; + *pul_year = (ul_cent * BCD_FACTOR * BCD_FACTOR) + + (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK); + } + + /* Retrieve month */ + if (pul_month) { + ul_temp = (ul_date & RTC_TSDR_MONTH_Msk) >> RTC_TSDR_MONTH_Pos; + *pul_month = (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK); + } + + /* Retrieve day */ + if (pul_day) { + ul_temp = (ul_date & RTC_TSDR_DATE_Msk) >> RTC_TSDR_DATE_Pos; + *pul_day = (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK); + } + + /* Retrieve week */ + if (pul_week) { + *pul_week = ((ul_date & RTC_TSDR_DAY_Msk) >> RTC_TSDR_DAY_Pos); + } +} + +/** + * \brief Get the RTC tamper source. + * + * \note This function is only available on SAM4C devices. + * + * \param p_rtc Pointer to an RTC instance. + * \param reg_num Current tamper register set number. + * + * \return Tamper source. + */ +uint32_t rtc_get_tamper_source(Rtc *p_rtc, uint8_t reg_num) +{ + return (p_rtc->RTC_TS[reg_num].RTC_TSSR & RTC_TSSR_TSRC_Msk) >> + RTC_TSSR_TSRC_Pos; +} + +/** + * \brief Get the RTC tamper event counter. + * + * \note This function is only available on SAM4C devices. + * + * \note This function should be called before rtc_get_tamper_source() + * function call, Otherwise the tamper event counter will be cleared. + * + * \param p_rtc Pointer to an RTC instance. + * + * \return Tamper event counter + */ +uint32_t rtc_get_tamper_event_counter(Rtc *p_rtc) +{ + return (p_rtc->RTC_TS[0].RTC_TSTR & RTC_TSTR_TEVCNT_Msk) >> + RTC_TSTR_TEVCNT_Pos; +} + +/** + * \brief Check the system is in backup mode when RTC tamper event happen. + * + * \note This function is only available on SAM4C devices. + * + * \note This function should be called before rtc_get_tamper_source() + * function call, Otherwise the flag indicates tamper occur in backup + * mode will be cleared. + * + * \param p_rtc Pointer to an RTC instance. + * \param reg_num Current tamper register set number. + * + * \return True - The system is in backup mode when the tamper event occurs. + * Flase - The system is different from backup mode. + */ +bool rtc_is_tamper_occur_in_backup_mode(Rtc *p_rtc, uint8_t reg_num) +{ + if(p_rtc->RTC_TS[reg_num].RTC_TSTR & RTC_TSTR_BACKUP) { + return true; + } else { + return false; + } +} +#endif + +#if (SAMG55) || defined(__DOXYGEN__) +/** + * \brief Get the RTC milliseconds value. + * + * \note This function is only available on SAMG55 devices. + * + * \param p_rtc Pointer to an RTC instance. + * + * \return Number of 1/1024 seconds elapsed within one second. + */ +uint32_t rtc_get_milliseconds(Rtc *p_rtc) +{ + return (p_rtc->RTC_MSR) & RTC_MSR_MS_Msk; +} +#endif + + +//@} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/rtc/rtc.h b/hw-libs/drivers/SAMx70/ASF/sam/drivers/rtc/rtc.h new file mode 100644 index 000000000..a95908e1b --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/rtc/rtc.h @@ -0,0 +1,182 @@ +/** + * \file + * + * \brief Real-Time Clock (RTC) driver for SAM. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef RTC_H_INCLUDED +#define RTC_H_INCLUDED + +#include "compiler.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +void rtc_set_hour_mode(Rtc *p_rtc, uint32_t ul_mode); +uint32_t rtc_get_hour_mode(Rtc *p_rtc); +void rtc_enable_interrupt(Rtc *p_rtc, uint32_t ul_sources); +void rtc_disable_interrupt(Rtc *p_rtc, uint32_t ul_sources); +uint32_t rtc_get_interrupt_mask(Rtc *p_rtc); +void rtc_get_time(Rtc *p_rtc, uint32_t *pul_hour, uint32_t *pul_minute, + uint32_t *pul_second); +uint32_t rtc_set_time(Rtc *p_rtc, uint32_t ul_hour, uint32_t ul_minute, + uint32_t ul_second); +uint32_t rtc_set_time_alarm(Rtc *p_rtc, + uint32_t ul_hour_flag, uint32_t ul_hour, + uint32_t ul_minute_flag, uint32_t ul_minute, + uint32_t ul_second_flag, uint32_t ul_second); +void rtc_get_date(Rtc *p_rtc, uint32_t *pul_year, uint32_t *pul_month, + uint32_t *pul_day, uint32_t *pul_week); +uint32_t rtc_set_date(Rtc *p_rtc, uint32_t ul_year, uint32_t ul_month, + uint32_t ul_day, uint32_t ul_week); +uint32_t rtc_set_date_alarm(Rtc *p_rtc, + uint32_t ul_month_flag, uint32_t ul_month, + uint32_t ul_day_flag, uint32_t ul_day); +void rtc_clear_time_alarm(Rtc *p_rtc); +void rtc_clear_date_alarm(Rtc *p_rtc); +uint32_t rtc_get_status(Rtc *p_rtc); +void rtc_clear_status(Rtc *p_rtc, uint32_t ul_clear); +uint32_t rtc_get_valid_entry(Rtc *p_rtc); +void rtc_set_time_event(Rtc *p_rtc, uint32_t ul_selection); +void rtc_set_calendar_event(Rtc *p_rtc, uint32_t ul_selection); + +#if ((SAM3S8) || (SAM3SD8) || (SAM4S) || (SAM4N) || (SAM4C) || (SAMG) || (SAM4CP) || (SAM4CM) || defined(__DOXYGEN__)) +void rtc_set_calendar_mode(Rtc *p_rtc, uint32_t ul_mode); +uint32_t rtc_get_calendar_mode(Rtc *p_rtc); +void rtc_set_calibration(Rtc *p_rtc, uint32_t ul_direction_ppm, + uint32_t ul_correction, uint32_t ul_range_ppm); +#endif + +#if ((SAM3S8) || (SAM3SD8) || (SAM4S) || (SAM4C) || (SAMG) || (SAM4CP) || (SAM4CM) || SAMV71 || SAMV70 || SAME70 || SAMS70 || defined(__DOXYGEN__)) +void rtc_set_waveform(Rtc *p_rtc, uint32_t ul_channel, uint32_t ul_value); +#if ((SAM3S8) || (SAM3SD8) || (SAM4S) || (SAM4C)|| (SAM4CP) || (SAM4CM) || SAMV71 || SAMV70 || SAME70 || SAMS70 || defined(__DOXYGEN__)) +void rtc_set_pulse_parameter(Rtc *p_rtc, uint32_t ul_time_high, + uint32_t ul_period); +#endif +#endif + +#if ((SAM3N) || (SAM3U) || (SAM3XA) || defined(__DOXYGEN__)) +void rtc_set_writeprotect(Rtc *p_rtc, uint32_t ul_enable); +#endif /* ((SAM3N) || (SAM3U) || (SAM3XA)) */ + +#if ((SAM4C) || (SAM4CP) || (SAM4CM) || defined(__DOXYGEN__)) +void rtc_get_tamper_time(Rtc *p_rtc, uint32_t *pul_hour, uint32_t *pul_minute, + uint32_t *pul_second, uint8_t reg_num); +void rtc_get_tamper_date(Rtc *p_rtc, uint32_t *pul_year, uint32_t *pul_month, + uint32_t *pul_day, uint32_t *pul_week, uint8_t reg_num); +uint32_t rtc_get_tamper_source(Rtc *p_rtc, uint8_t reg_num); +uint32_t rtc_get_tamper_event_counter(Rtc *p_rtc); +bool rtc_is_tamper_occur_in_backup_mode(Rtc *p_rtc, uint8_t reg_num); +#endif + +#if (SAMG55 || defined(__DOXYGEN__)) +uint32_t rtc_get_milliseconds(Rtc *p_rtc); +#endif + +/** + * \page sam_rtc_quickstart Quickstart guide for SAM RTC driver + * + * This is the quickstart guide for the \ref rtc_group "SAM RTC driver", + * with step-by-step instructions on how to configure and use the driver in a + * selection of use cases. + * + * The use cases contain several code fragments. The code fragments in the + * steps for setup can be copied into a custom initialization function, while + * the steps for usage can be copied into, e.g., the main application function. + * + * \section rtc_basic_use_case Basic use case + * In this basic use case, the RTC module is using 32kHz external crystal and + * configured for 24-hour mode. It will read the current date and time. + * + * \subsection sam_rtc_quickstart_prereq Prerequisites + * -# \ref sysclk_group "System Clock Management (Sysclock)" + * + * \section rtc_basic_use_case_setup Setup steps + * \subsection rtc_basic_use_case_setup_code Example code + * Add to application C-file: + * \code + void rtc_setup(void) + { + pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL); + + while (!pmc_osc_is_ready_32kxtal()); + + rtc_set_hour_mode(RTC, 0); + } +\endcode + * + * \subsection rtc_basic_use_case_setup_flow Workflow + * - \note Please make sure the external 32kHz crystal is available. + * -# Enable the External 32K crystal : + * - \code pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL); \endcode + * -# Wait for 32K crystal ready: + * - \code while (!pmc_osc_is_ready_32kxtal()); \endcode + * -# Set default RTC configuration, 24-hour mode . + * - \code rtc_set_hour_mode(RTC, 0); \endcode + * + * \section rtc_basic_use_case_usage Usage steps + * \subsection rtc_basic_use_case_usage_code Example code + * Add to, e.g., main loop in application C-file: + * \code + uint32_t hour, minute, second; + uint32_t year, month, day, week; + + rtc_get_time(RTC, &hour, &minute, &second); + rtc_get_date(RTC, &year, &month, &day, &week); +\endcode + * + * \subsection rtc_basic_use_case_usage_flow Workflow + * -# Start Define the variables for the date and time: + * - \code uint32_t hour, minute, second; \endcode + * - \code uint32_t year, month, day, week; \endcode + * -# Read current time: + * - \code rtc_get_time(RTC, &hour, &minute, &second); \endcode + * -# Read current date: + * - \code rtc_get_date(RTC, &year, &month, &day, &week); \endcode + * + */ + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +#endif /* RTC_H_INCLUDED */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/rtt/rtt.c b/hw-libs/drivers/SAMx70/ASF/sam/drivers/rtt/rtt.c new file mode 100644 index 000000000..431d009bb --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/rtt/rtt.c @@ -0,0 +1,261 @@ +/** + * \file + * + * \brief Real-time Timer (RTT) driver for SAM. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "rtt.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \defgroup sam_drivers_rtt_group Real-time Timer (RTT) + * + * The Real-time Timer is built around a 32-bit counter used to count + * roll-over events of the programmable 16-bit prescaler, which enables + * counting elapsed seconds from a 32 kHz slow clock source. + * This is a driver for configuration and use of the RTT peripheral. + * + * @{ + */ + +/* + * In follow series chip, the bit RTC1HZ and RTTDIS in RTT_MR are write only. + * So we use a variable to record status of these bits. + */ +#if (SAM4N || SAM4S || SAM4E || SAM4C || SAMG51 || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) +static uint32_t g_wobits_in_rtt_mr = 0; +#endif + +/** + * \brief Initialize the given RTT. + * + * \note This function restarts the real-time timer. If w_prescaler is equal to zero, + * the prescaler period is equal to 2^16 * SCLK period. If not, the prescaler period + * is equal to us_prescaler * SCLK period. + * + * \param p_rtt Pointer to an RTT instance. + * \param us_prescaler Prescaler value for the RTT. + * + * \return 0 if successful. + */ +uint32_t rtt_init(Rtt *p_rtt, uint16_t us_prescaler) +{ +#if (SAM4N || SAM4S || SAM4E || SAM4C || SAMG51 || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) + p_rtt->RTT_MR = (us_prescaler | RTT_MR_RTTRST | g_wobits_in_rtt_mr); +#else + p_rtt->RTT_MR = (us_prescaler | RTT_MR_RTTRST); +#endif + return 0; +} + +#if (SAM4N || SAM4S || SAM4E || SAM4C || SAMG51 || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Select RTT counter source. + * + * \param p_rtt Pointer to an RTT instance. + * \param is_rtc_sel RTC 1Hz Clock Selection. + */ +void rtt_sel_source(Rtt *p_rtt, bool is_rtc_sel) +{ + if(is_rtc_sel) { + g_wobits_in_rtt_mr |= RTT_MR_RTC1HZ; + p_rtt->RTT_MR |= g_wobits_in_rtt_mr; + } else { + g_wobits_in_rtt_mr &= ~RTT_MR_RTC1HZ; + p_rtt->RTT_MR |= g_wobits_in_rtt_mr; + } +} + +/** + * \brief Enable RTT. + * + * \param p_rtt Pointer to an RTT instance. + */ +void rtt_enable(Rtt *p_rtt) +{ + g_wobits_in_rtt_mr &= ~RTT_MR_RTTDIS; + p_rtt->RTT_MR |= g_wobits_in_rtt_mr; +} +/** + * \brief Disable RTT. + * + * \param p_rtt Pointer to an RTT instance. + */ +void rtt_disable(Rtt *p_rtt) +{ + g_wobits_in_rtt_mr |= RTT_MR_RTTDIS; + p_rtt->RTT_MR |= g_wobits_in_rtt_mr; +} +#elif (SAMG53 || SAMG54 || SAMG55) +void rtt_sel_source(Rtt *p_rtt, bool is_rtc_sel) +{ + if(is_rtc_sel) { + p_rtt->RTT_MR |= RTT_MR_RTC1HZ; + } else { + p_rtt->RTT_MR &= ~RTT_MR_RTC1HZ; + } +} + +void rtt_enable(Rtt *p_rtt) +{ + p_rtt->RTT_MR &= ~RTT_MR_RTTDIS; +} +/** + * \brief Disable RTT. + * + * \param p_rtt Pointer to an RTT instance. + */ +void rtt_disable(Rtt *p_rtt) +{ + p_rtt->RTT_MR |= RTT_MR_RTTDIS; +} +#endif + +/** + * \brief Enable RTT interrupts. + * + * \param p_rtt Pointer to an RTT instance. + * \param ul_sources Interrupts to be enabled. + */ +void rtt_enable_interrupt(Rtt *p_rtt, uint32_t ul_sources) +{ + uint32_t temp; + + temp = p_rtt->RTT_MR; + temp |= ul_sources; +#if (SAM4N || SAM4S || SAM4E || SAM4C || SAMG51 || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) + temp |= g_wobits_in_rtt_mr; +#endif + p_rtt->RTT_MR = temp; +} + +/** + * \brief Disable RTT interrupts. + * + * \param p_rtt Pointer to an RTT instance. + * \param ul_sources Interrupts to be disabled. + */ +void rtt_disable_interrupt(Rtt *p_rtt, uint32_t ul_sources) +{ + uint32_t temp = 0; + + temp = p_rtt->RTT_MR; + temp &= (~ul_sources); +#if (SAM4N || SAM4S || SAM4E || SAM4C || SAMG51 || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) + temp |= g_wobits_in_rtt_mr; +#endif + p_rtt->RTT_MR = temp; +} + +/** + * \brief Read the current value of the RTT timer value. + * + * \param p_rtt Pointer to an RTT instance. + * + * \return The current Real-time Timer value. + */ +uint32_t rtt_read_timer_value(Rtt *p_rtt) +{ + uint32_t rtt_val = p_rtt->RTT_VR; + + while (rtt_val != p_rtt->RTT_VR) { + rtt_val = p_rtt->RTT_VR; + } + + return rtt_val; +} + +/** + * \brief Get the status register value of the given RTT. + * + * \param p_rtt Pointer to an RTT instance. + * + * \return The Real-time Timer status. + */ +uint32_t rtt_get_status(Rtt *p_rtt) +{ + return p_rtt->RTT_SR; +} + +/** + * \brief Configure the RTT to generate an alarm at the given time. + * alarm happens when CRTV value equals ALMV+1, so RTT_AR should be alarmtime - 1. + * if you want to get alarm when rtt hit 0 , ALMV should be set to 0xFFFFFFFF. + * + * \param p_rtt Pointer to an RTT instance. + * \param ul_alarm_time Alarm time,Alarm time = ALMV + 1. + * + * \retval 0 Configuration is done. + */ +uint32_t rtt_write_alarm_time(Rtt *p_rtt, uint32_t ul_alarm_time) +{ + uint32_t flag; + + flag = p_rtt->RTT_MR & RTT_MR_ALMIEN; + + rtt_disable_interrupt(RTT, RTT_MR_ALMIEN); + + /** + * Alarm time = ALMV + 1,If the incoming parameter + * is 0, the ALMV is set to 0xFFFFFFFF. + */ + if(ul_alarm_time == 0) { + p_rtt->RTT_AR = 0xFFFFFFFF; + } + else { + p_rtt->RTT_AR = ul_alarm_time - 1; + } + + if (flag) { + rtt_enable_interrupt(RTT, RTT_MR_ALMIEN); + } + + return 0; +} + +//@} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/rtt/rtt.h b/hw-libs/drivers/SAMx70/ASF/sam/drivers/rtt/rtt.h new file mode 100644 index 000000000..695c27217 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/rtt/rtt.h @@ -0,0 +1,70 @@ +/** + * \file + * + * \brief Real-time Timer (RTT) driver for SAM. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef RTT_H_INCLUDED +#define RTT_H_INCLUDED + +#include "compiler.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +uint32_t rtt_init(Rtt *p_rtt, uint16_t us_prescaler); +#if (SAM4N || SAM4S || SAM4E || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) +void rtt_sel_source(Rtt *p_rtt, bool is_rtc_sel); +void rtt_enable(Rtt *p_rtt); +void rtt_disable(Rtt *p_rtt); +#endif +void rtt_enable_interrupt(Rtt *p_rtt, uint32_t ul_sources); +void rtt_disable_interrupt(Rtt *p_rtt, uint32_t ul_sources); +uint32_t rtt_read_timer_value(Rtt *p_rtt); +uint32_t rtt_get_status(Rtt *p_rtt); +uint32_t rtt_write_alarm_time(Rtt *p_rtt, uint32_t ul_alarm_time); + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +#endif /* RTT_H_INCLUDED */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/spi/spi.c b/hw-libs/drivers/SAMx70/ASF/sam/drivers/spi/spi.c new file mode 100644 index 000000000..61f3a6052 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/spi/spi.c @@ -0,0 +1,472 @@ +/** + * \file + * + * \brief Serial Peripheral Interface (SPI) driver for SAM. + * + * Copyright (c) 2011-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#include "spi.h" +#include "sysclk.h" + +/** + * \brief Calculate \f$ \left\lceil \frac{a}{b} \right\rceil \f$ using + * integer arithmetic. + * + * \param a An integer + * \param b Another integer + * + * \return (\a a / \a b) rounded up to the nearest integer. + */ +#define div_ceil(a, b) (((a) + (b) - 1) / (b)) + +/** + * \defgroup sam_drivers_spi_group Serial Peripheral Interface (SPI) + * + * See \ref sam_spi_quickstart. + * + * The SPI circuit is a synchronous serial data link that provides communication + * with external devices in Master or Slave mode. Connection to Peripheral DMA + * Controller channel capabilities optimizes data transfers. + * + * @{ + */ +#ifndef SPI_WPMR_WPKEY_PASSWD +#define SPI_WPMR_WPKEY_PASSWD SPI_WPMR_WPKEY((uint32_t) 0x535049) +#endif + +/** + * \brief Enable SPI clock. + * + * \param p_spi Pointer to an SPI instance. + */ +void spi_enable_clock(Spi *p_spi) +{ +#if (SAM4S || SAM3S || SAM3N || SAM3U || SAM4E || SAM4N || SAMG51|| SAMG53|| SAMG54) + UNUSED(p_spi); + sysclk_enable_peripheral_clock(ID_SPI); +#elif (SAM3XA || SAM4C || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) + if (p_spi == SPI0) { + sysclk_enable_peripheral_clock(ID_SPI0); + } + #ifdef SPI1 + else if (p_spi == SPI1) { + sysclk_enable_peripheral_clock(ID_SPI1); + } + #endif +#elif (SAMG55) + if (p_spi == SPI0) { + sysclk_enable_peripheral_clock(ID_FLEXCOM0); + } + #ifdef SPI1 + else if (p_spi == SPI1) { + sysclk_enable_peripheral_clock(ID_FLEXCOM1); + } + #endif + #ifdef SPI2 + else if (p_spi == SPI2) { + sysclk_enable_peripheral_clock(ID_FLEXCOM2); + } + #endif + #ifdef SPI3 + else if (p_spi == SPI3) { + sysclk_enable_peripheral_clock(ID_FLEXCOM3); + } + #endif + #ifdef SPI4 + else if (p_spi == SPI4) { + sysclk_enable_peripheral_clock(ID_FLEXCOM4); + } + #endif + #ifdef SPI5 + else if (p_spi == SPI5) { + sysclk_enable_peripheral_clock(ID_FLEXCOM5); + } + #endif + #ifdef SPI6 + else if (p_spi == SPI6) { + sysclk_enable_peripheral_clock(ID_FLEXCOM6); + } + #endif + #ifdef SPI7 + else if (p_spi == SPI7) { + sysclk_enable_peripheral_clock(ID_FLEXCOM7); + } + #endif +#elif SAM4L + sysclk_enable_peripheral_clock(p_spi); +#endif +} + +/** + * \brief Disable SPI clock. + * + * \param p_spi Pointer to an SPI instance. + */ +void spi_disable_clock(Spi *p_spi) +{ +#if (SAM4S || SAM3S || SAM3N || SAM3U || SAM4E || SAM4N || SAMG51|| SAMG53|| SAMG54) + UNUSED(p_spi); + sysclk_disable_peripheral_clock(ID_SPI); +#elif (SAM3XA || SAM4C || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) + if (p_spi == SPI0) { + sysclk_disable_peripheral_clock(ID_SPI0); + } + #ifdef SPI1 + else if (p_spi == SPI1) { + sysclk_disable_peripheral_clock(ID_SPI1); + } + #endif +#elif (SAMG55) + if (p_spi == SPI0) { + sysclk_disable_peripheral_clock(ID_FLEXCOM0); + } + #ifdef SPI1 + else if (p_spi == SPI1) { + sysclk_disable_peripheral_clock(ID_FLEXCOM1); + } + #endif + #ifdef SPI2 + else if (p_spi == SPI2) { + sysclk_disable_peripheral_clock(ID_FLEXCOM2); + } + #endif + #ifdef SPI3 + else if (p_spi == SPI3) { + sysclk_disable_peripheral_clock(ID_FLEXCOM3); + } + #endif + #ifdef SPI4 + else if (p_spi == SPI4) { + sysclk_disable_peripheral_clock(ID_FLEXCOM4); + } + #endif + #ifdef SPI5 + else if (p_spi == SPI5) { + sysclk_disable_peripheral_clock(ID_FLEXCOM5); + } + #endif + #ifdef SPI6 + else if (p_spi == SPI6) { + sysclk_disable_peripheral_clock(ID_FLEXCOM6); + } + #endif + #ifdef SPI7 + else if (p_spi == SPI7) { + sysclk_disable_peripheral_clock(ID_FLEXCOM7); + } + #endif +#elif SAM4L + sysclk_disable_peripheral_clock(p_spi); +#endif +} + +/** + * \brief Set Peripheral Chip Select (PCS) value. + * + * \param p_spi Pointer to an SPI instance. + * \param ul_value Peripheral Chip Select value. + * If PCS decode mode is not used, use \ref spi_get_pcs to build + * the value to use. + * On reset the decode mode is not enabled. + * The decode mode can be enabled/disabled by follow functions: + * \ref spi_enable_peripheral_select_decode, + * \ref spi_disable_peripheral_select_decode. + */ +void spi_set_peripheral_chip_select_value(Spi *p_spi, uint32_t ul_value) +{ + p_spi->SPI_MR &= (~SPI_MR_PCS_Msk); + p_spi->SPI_MR |= SPI_MR_PCS(ul_value); +} + +/** + * \brief Set delay between chip selects (in number of MCK clocks). + * If DLYBCS <= 6, 6 MCK clocks will be inserted by default. + * + * \param p_spi Pointer to an SPI instance. + * \param ul_delay Delay between chip selects (in number of MCK clocks). + */ +void spi_set_delay_between_chip_select(Spi *p_spi, uint32_t ul_delay) +{ + p_spi->SPI_MR &= (~SPI_MR_DLYBCS_Msk); + p_spi->SPI_MR |= SPI_MR_DLYBCS(ul_delay); +} + +/** + * \brief Read the received data and it's peripheral chip select value. + * While SPI works in fixed peripheral select mode, the peripheral chip select + * value is meaningless. + * + * \param p_spi Pointer to an SPI instance. + * \param data Pointer to the location where to store the received data word. + * \param p_pcs Pointer to fill Peripheral Chip Select Value. + * + * \retval SPI_OK on Success. + * \retval SPI_ERROR_TIMEOUT on Time-out. + */ +spi_status_t spi_read(Spi *p_spi, uint16_t *us_data, uint8_t *p_pcs) +{ + uint32_t timeout = SPI_TIMEOUT; + static uint32_t reg_value; + + while (!(p_spi->SPI_SR & SPI_SR_RDRF)) { + if (!timeout--) { + return SPI_ERROR_TIMEOUT; + } + } + + reg_value = p_spi->SPI_RDR; + if (spi_get_peripheral_select_mode(p_spi)) { + *p_pcs = (uint8_t) ((reg_value & SPI_RDR_PCS_Msk) >> SPI_RDR_PCS_Pos); + } + *us_data = (uint16_t) (reg_value & SPI_RDR_RD_Msk); + + return SPI_OK; +} + +/** + * \brief Write the transmitted data with specified peripheral chip select value. + * + * \param p_spi Pointer to an SPI instance. + * \param us_data The data to transmit. + * \param uc_pcs Peripheral Chip Select Value while SPI works in peripheral select + * mode, otherwise it's meaningless. + * \param uc_last Indicate whether this data is the last one while SPI is working + * in variable peripheral select mode. + * + * \retval SPI_OK on Success. + * \retval SPI_ERROR_TIMEOUT on Time-out. + */ +spi_status_t spi_write(Spi *p_spi, uint16_t us_data, + uint8_t uc_pcs, uint8_t uc_last) +{ + uint32_t timeout = SPI_TIMEOUT; + uint32_t value; + + while (!(p_spi->SPI_SR & SPI_SR_TDRE)) { + if (!timeout--) { + return SPI_ERROR_TIMEOUT; + } + } + + if (spi_get_peripheral_select_mode(p_spi)) { + value = SPI_TDR_TD(us_data) | SPI_TDR_PCS(uc_pcs); + if (uc_last) { + value |= SPI_TDR_LASTXFER; + } + } else { + value = SPI_TDR_TD(us_data); + } + + p_spi->SPI_TDR = value; + + return SPI_OK; +} + +/** + * \brief Set clock default state. + * + * \param p_spi Pointer to an SPI instance. + * \param ul_pcs_ch Peripheral Chip Select channel (0~3). + * \param ul_polarity Default clock state is logical one(high)/zero(low). + */ +void spi_set_clock_polarity(Spi *p_spi, uint32_t ul_pcs_ch, + uint32_t ul_polarity) +{ + if (ul_polarity) { + p_spi->SPI_CSR[ul_pcs_ch] |= SPI_CSR_CPOL; + } else { + p_spi->SPI_CSR[ul_pcs_ch] &= (~SPI_CSR_CPOL); + } +} + +/** + * \brief Set Data Capture Phase. + * + * \param p_spi Pointer to an SPI instance. + * \param ul_pcs_ch Peripheral Chip Select channel (0~3). + * \param ul_phase Data capture on the rising/falling edge of clock. + */ +void spi_set_clock_phase(Spi *p_spi, uint32_t ul_pcs_ch, uint32_t ul_phase) +{ + if (ul_phase) { + p_spi->SPI_CSR[ul_pcs_ch] |= SPI_CSR_NCPHA; + } else { + p_spi->SPI_CSR[ul_pcs_ch] &= (~SPI_CSR_NCPHA); + } +} + +/** + * \brief Configure CS behavior for SPI transfer (\ref spi_cs_behavior_t). + * + * \param p_spi Pointer to an SPI instance. + * \param ul_pcs_ch Peripheral Chip Select channel (0~3). + * \param ul_cs_behavior Behavior of the Chip Select after transfer. + */ +void spi_configure_cs_behavior(Spi *p_spi, uint32_t ul_pcs_ch, + uint32_t ul_cs_behavior) +{ + if (ul_cs_behavior == SPI_CS_RISE_FORCED) { + p_spi->SPI_CSR[ul_pcs_ch] &= (~SPI_CSR_CSAAT); + p_spi->SPI_CSR[ul_pcs_ch] |= SPI_CSR_CSNAAT; + } else if (ul_cs_behavior == SPI_CS_RISE_NO_TX) { + p_spi->SPI_CSR[ul_pcs_ch] &= (~SPI_CSR_CSAAT); + p_spi->SPI_CSR[ul_pcs_ch] &= (~SPI_CSR_CSNAAT); + } else if (ul_cs_behavior == SPI_CS_KEEP_LOW) { + p_spi->SPI_CSR[ul_pcs_ch] |= SPI_CSR_CSAAT; + } +} + +/** + * \brief Set number of bits per transfer. + * + * \param p_spi Pointer to an SPI instance. + * \param ul_pcs_ch Peripheral Chip Select channel (0~3). + * \param ul_bits Number of bits (8~16), use the pattern defined + * in the device header file. + */ +void spi_set_bits_per_transfer(Spi *p_spi, uint32_t ul_pcs_ch, + uint32_t ul_bits) +{ + p_spi->SPI_CSR[ul_pcs_ch] &= (~SPI_CSR_BITS_Msk); + p_spi->SPI_CSR[ul_pcs_ch] |= ul_bits; +} + +/** + * \brief Calculate the baudrate divider. + * + * \param baudrate Baudrate value. + * \param mck SPI module input clock frequency (MCK clock, Hz). + * + * \return Divider or error code. + * \retval > 0 Success. + * \retval < 0 Error. + */ +int16_t spi_calc_baudrate_div(const uint32_t baudrate, uint32_t mck) +{ + int baud_div = div_ceil(mck, baudrate); + + /* The value of baud_div is from 1 to 255 in the SCBR field. */ + if (baud_div <= 0 || baud_div > 255) { + return -1; + } + + return baud_div; +} + +/** + * \brief Set Serial Clock Baud Rate divider value (SCBR). + * + * \param p_spi Pointer to an SPI instance. + * \param ul_pcs_ch Peripheral Chip Select channel (0~3). + * \param uc_baudrate_divider Baudrate divider from MCK. + * + * \return + * \retval is 0 Success. + * \retval is -1 Error. + */ +int16_t spi_set_baudrate_div(Spi *p_spi, uint32_t ul_pcs_ch, + uint8_t uc_baudrate_divider) +{ + /* Programming the SCBR field to 0 is forbidden */ + if (!uc_baudrate_divider) + return -1; + + p_spi->SPI_CSR[ul_pcs_ch] &= (~SPI_CSR_SCBR_Msk); + p_spi->SPI_CSR[ul_pcs_ch] |= SPI_CSR_SCBR(uc_baudrate_divider); + return 0; +} + +/** + * \brief Configure timing for SPI transfer. + * + * \param p_spi Pointer to an SPI instance. + * \param ul_pcs_ch Peripheral Chip Select channel (0~3). + * \param uc_dlybs Delay before SPCK (in number of MCK clocks). + * \param uc_dlybct Delay between consecutive transfers (in number of MCK clocks). + */ +void spi_set_transfer_delay(Spi *p_spi, uint32_t ul_pcs_ch, + uint8_t uc_dlybs, uint8_t uc_dlybct) +{ + p_spi->SPI_CSR[ul_pcs_ch] &= ~(SPI_CSR_DLYBS_Msk | SPI_CSR_DLYBCT_Msk); + p_spi->SPI_CSR[ul_pcs_ch] |= SPI_CSR_DLYBS(uc_dlybs) + | SPI_CSR_DLYBCT(uc_dlybct); +} + + +/** + * \brief Enable or disable write protection of SPI registers. + * + * \param p_spi Pointer to an SPI instance. + * \param ul_enable 1 to enable, 0 to disable. + */ +void spi_set_writeprotect(Spi *p_spi, uint32_t ul_enable) +{ +#if SAM4L + if (ul_enable) { + p_spi->SPI_WPCR = SPI_WPCR_SPIWPKEY_VALUE | SPI_WPCR_SPIWPEN; + } else { + p_spi->SPI_WPCR = SPI_WPCR_SPIWPKEY_VALUE; + } +#else + if (ul_enable) { + p_spi->SPI_WPMR = SPI_WPMR_WPKEY_PASSWD | SPI_WPMR_WPEN; + } else { + p_spi->SPI_WPMR = SPI_WPMR_WPKEY_PASSWD; + } +#endif +} + +/** + * \brief Indicate write protect status. + * + * \param p_spi Pointer to an SPI instance. + * + * \return SPI_WPSR value. + */ +uint32_t spi_get_writeprotect_status(Spi *p_spi) +{ + return p_spi->SPI_WPSR; +} + +/** + * @} + */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/spi/spi.h b/hw-libs/drivers/SAMx70/ASF/sam/drivers/spi/spi.h new file mode 100644 index 000000000..56ae93a25 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/spi/spi.h @@ -0,0 +1,628 @@ +/** + * \file + * + * \brief Serial Peripheral Interface (SPI) driver for SAM. + * + * Copyright (c) 2011-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef SPI_H_INCLUDED +#define SPI_H_INCLUDED + +#include "compiler.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** Time-out value (number of attempts). */ +#define SPI_TIMEOUT 15000 + +/** Status codes used by the SPI driver. */ +typedef enum +{ + SPI_ERROR = -1, + SPI_OK = 0, + SPI_ERROR_TIMEOUT = 1, + SPI_ERROR_ARGUMENT, + SPI_ERROR_OVERRUN, + SPI_ERROR_MODE_FAULT, + SPI_ERROR_OVERRUN_AND_MODE_FAULT +} spi_status_t; + +/** SPI Chip Select behavior modes while transferring. */ +typedef enum spi_cs_behavior { + /** CS does not rise until a new transfer is requested on different chip select. */ + SPI_CS_KEEP_LOW = SPI_CSR_CSAAT, + /** CS rises if there is no more data to transfer. */ + SPI_CS_RISE_NO_TX = 0, + /** CS is de-asserted systematically during a time DLYBCS. */ + SPI_CS_RISE_FORCED = SPI_CSR_CSNAAT +} spi_cs_behavior_t; + +/** + * \brief Generate Peripheral Chip Select Value from Chip Select ID + * \note When chip select n is working, PCS bit n is set to low level. + * + * \param chip_sel_id The chip select number used + */ +#define spi_get_pcs(chip_sel_id) ((~(1u<<(chip_sel_id)))&0xF) + +/** + * \brief Reset SPI and set it to Slave mode. + * + * \param p_spi Pointer to an SPI instance. + */ +static void spi_reset(Spi *p_spi) +{ + p_spi->SPI_CR = SPI_CR_SWRST; +} + +/** + * \brief Enable SPI. + * + * \param p_spi Pointer to an SPI instance. + */ +static void spi_enable(Spi *p_spi) +{ + p_spi->SPI_CR = SPI_CR_SPIEN; +} + +/** + * \brief Disable SPI. + * + * \note CS is de-asserted, which indicates that the last data is done, and user + * should check TX_EMPTY before disabling SPI. + * + * \param p_spi Pointer to an SPI instance. + */ +static void spi_disable(Spi *p_spi) +{ + p_spi->SPI_CR = SPI_CR_SPIDIS; +} + +/** + * \brief Issue a LASTXFER command. + * The next transfer is the last transfer and after that CS is de-asserted. + * + * \param p_spi Pointer to an SPI instance. + */ +static inline void spi_set_lastxfer(Spi *p_spi) +{ + p_spi->SPI_CR = SPI_CR_LASTXFER; +} + +/** + * \brief Set SPI to Master mode. + * + * \param p_spi Pointer to an SPI instance. + */ +static void spi_set_master_mode(Spi *p_spi) +{ + p_spi->SPI_MR |= SPI_MR_MSTR; +} + +/** + * \brief Set SPI to Slave mode. + * + * \param p_spi Pointer to an SPI instance. + */ +static inline void spi_set_slave_mode(Spi *p_spi) +{ + p_spi->SPI_MR &= (~SPI_MR_MSTR); +} + +/** + * \brief Get SPI work mode. + * + * \param p_spi Pointer to an SPI instance. + * + * \return 1 for master mode, 0 for slave mode. + */ +static inline uint32_t spi_get_mode(Spi *p_spi) +{ + if (p_spi->SPI_MR & SPI_MR_MSTR) { + return 1; + } else { + return 0; + } +} + +/** + * \brief Set Variable Peripheral Select. + * Peripheral Chip Select can be controlled by SPI_TDR. + * + * \param p_spi Pointer to an SPI instance. + */ +static void spi_set_variable_peripheral_select(Spi *p_spi) +{ + p_spi->SPI_MR |= SPI_MR_PS; +} + +/** + * \brief Set Fixed Peripheral Select. + * Peripheral Chip Select is controlled by SPI_MR. + * + * \param p_spi Pointer to an SPI instance. + */ +static inline void spi_set_fixed_peripheral_select(Spi *p_spi) +{ + p_spi->SPI_MR &= (~SPI_MR_PS); +} + +/** + * \brief Get Peripheral Select mode. + * + * \param p_spi Pointer to an SPI instance. + * + * \return 1 for Variable mode, 0 for fixed mode. + */ +static inline uint32_t spi_get_peripheral_select_mode(Spi *p_spi) +{ + if (p_spi->SPI_MR & SPI_MR_PS) { + return 1; + } else { + return 0; + } +} + +/** + * \brief Enable Peripheral Select Decode. + * + * \param p_spi Pointer to an SPI instance. + */ +static void spi_enable_peripheral_select_decode(Spi *p_spi) +{ + p_spi->SPI_MR |= SPI_MR_PCSDEC; +} + +/** + * \brief Disable Peripheral Select Decode. + * + * \param p_spi Pointer to an SPI instance. + */ +static inline void spi_disable_peripheral_select_decode(Spi *p_spi) +{ + p_spi->SPI_MR &= (~SPI_MR_PCSDEC); +} + +/** + * \brief Get Peripheral Select Decode mode. + * + * \param p_spi Pointer to an SPI instance. + * + * \return 1 for decode mode, 0 for direct mode. + */ +static inline uint32_t spi_get_peripheral_select_decode_setting(Spi *p_spi) +{ + if (p_spi->SPI_MR & SPI_MR_PCSDEC) { + return 1; + } else { + return 0; + } +} + +/** + * \brief Enable Mode Fault Detection. + * + * \param p_spi Pointer to an SPI instance. + */ +static inline void spi_enable_mode_fault_detect(Spi *p_spi) +{ + p_spi->SPI_MR &= (~SPI_MR_MODFDIS); +} + +/** + * \brief Disable Mode Fault Detection. + * + * \param p_spi Pointer to an SPI instance. + */ +static void spi_disable_mode_fault_detect(Spi *p_spi) +{ + p_spi->SPI_MR |= SPI_MR_MODFDIS; +} + +/** + * \brief Check if mode fault detection is enabled. + * + * \param p_spi Pointer to an SPI instance. + * + * \return 1 for disabled, 0 for enabled. + */ +static inline uint32_t spi_get_mode_fault_detect_setting(Spi *p_spi) +{ + if (p_spi->SPI_MR & SPI_MR_MODFDIS) { + return 1; + } else { + return 0; + } +} + +/** + * \brief Enable waiting RX_EMPTY before transfer starts. + * + * \param p_spi Pointer to an SPI instance. + */ +static void spi_enable_tx_on_rx_empty(Spi *p_spi) +{ + p_spi->SPI_MR |= SPI_MR_WDRBT; +} + +/** + * \brief Disable waiting RX_EMPTY before transfer starts. + * + * \param p_spi Pointer to an SPI instance. + */ +static void spi_disable_tx_on_rx_empty(Spi *p_spi) +{ + p_spi->SPI_MR &= (~SPI_MR_WDRBT); +} + +/** + * \brief Check if SPI waits RX_EMPTY before transfer starts. + * + * \param p_spi Pointer to an SPI instance. + * + * \return 1 for SPI waits, 0 for no wait. + */ +static uint32_t spi_get_tx_on_rx_empty_setting(Spi *p_spi) +{ + if (p_spi->SPI_MR & SPI_MR_WDRBT) { + return 1; + } else { + return 0; + } +} + +/** + * \brief Enable loopback mode. + * + * \param p_spi Pointer to an SPI instance. + */ +static inline void spi_enable_loopback(Spi *p_spi) +{ + p_spi->SPI_MR |= SPI_MR_LLB; +} + +/** + * \brief Disable loopback mode. + * + * \param p_spi Pointer to an SPI instance. + */ +static inline void spi_disable_loopback(Spi *p_spi) +{ + p_spi->SPI_MR &= (~SPI_MR_LLB); +} + +void spi_enable_clock(Spi *p_spi); +void spi_disable_clock(Spi *p_spi); +void spi_set_peripheral_chip_select_value(Spi *p_spi, uint32_t ul_value); +void spi_set_delay_between_chip_select(Spi *p_spi, uint32_t ul_delay); +spi_status_t spi_read(Spi *p_spi, uint16_t *us_data, uint8_t *p_pcs); +spi_status_t spi_write(Spi *p_spi, uint16_t us_data, uint8_t uc_pcs, + uint8_t uc_last); + +/** + * \brief Read status register. + * + * \param p_spi Pointer to an SPI instance. + * + * \return SPI status register value. + */ +static inline uint32_t spi_read_status(Spi *p_spi) +{ + return p_spi->SPI_SR; +} + +/** + * \brief Test if the SPI is enabled. + * + * \param p_spi Pointer to an SPI instance. + * + * \return 1 if the SPI is enabled, otherwise 0. + */ +static uint32_t spi_is_enabled(Spi *p_spi) +{ + if (p_spi->SPI_SR & SPI_SR_SPIENS) { + return 1; + } else { + return 0; + } +} + +/** + * \brief Put one data to a SPI peripheral. + * + * \param p_spi Base address of the SPI instance. + * \param data The data byte to be loaded + * + */ +static inline void spi_put(Spi *p_spi, uint16_t data) +{ + p_spi->SPI_TDR = SPI_TDR_TD(data); +} + +/** \brief Get one data to a SPI peripheral. + * + * \param p_spi Base address of the SPI instance. + * \return The data byte + * + */ +static inline uint16_t spi_get(Spi *p_spi) +{ + return (p_spi->SPI_RDR & SPI_RDR_RD_Msk); +} + +/** + * \brief Check if all transmissions are complete. + * + * \param p_spi Pointer to an SPI instance. + * + * \retval 1 if transmissions are complete. + * \retval 0 if transmissions are not complete. + */ +static uint32_t spi_is_tx_empty(Spi *p_spi) +{ + if (p_spi->SPI_SR & SPI_SR_TXEMPTY) { + return 1; + } else { + return 0; + } +} + +/** + * \brief Check if all transmissions are ready. + * + * \param p_spi Pointer to an SPI instance. + * + * \retval 1 if transmissions are complete. + * \retval 0 if transmissions are not complete. + */ +static uint32_t spi_is_tx_ready(Spi *p_spi) +{ + if (p_spi->SPI_SR & SPI_SR_TDRE) { + return 1; + } else { + return 0; + } +} + +/** + * \brief Check if the SPI contains a received character. + * + * \param p_spi Pointer to an SPI instance. + * + * \return 1 if the SPI Receive Holding Register is full, otherwise 0. + */ +static inline uint32_t spi_is_rx_full(Spi *p_spi) +{ + if (p_spi->SPI_SR & SPI_SR_RDRF) { + return 1; + } else { + return 0; + } +} + +/** + * \brief Check if all receptions are ready. + * + * \param p_spi Pointer to an SPI instance. + * + * \return 1 if the SPI Receiver is ready, otherwise 0. + */ +static inline uint32_t spi_is_rx_ready(Spi *p_spi) +{ + if ((p_spi->SPI_SR & (SPI_SR_RDRF | SPI_SR_TXEMPTY)) + == (SPI_SR_RDRF | SPI_SR_TXEMPTY)) { + return 1; + } else { + return 0; + } +} + +/** + * \brief Enable SPI interrupts. + * + * \param p_spi Pointer to an SPI instance. + * \param ul_sources Interrupts to be enabled. + */ +static inline void spi_enable_interrupt(Spi *p_spi, uint32_t ul_sources) +{ + p_spi->SPI_IER = ul_sources; +} + +/** + * \brief Disable SPI interrupts. + * + * \param p_spi Pointer to an SPI instance. + * \param ul_sources Interrupts to be disabled. + */ +static inline void spi_disable_interrupt(Spi *p_spi, uint32_t ul_sources) +{ + p_spi->SPI_IDR = ul_sources; +} + +/** + * \brief Read SPI interrupt mask. + * + * \param p_spi Pointer to an SPI instance. + * + * \return The interrupt mask value. + */ +static inline uint32_t spi_read_interrupt_mask(Spi *p_spi) +{ + return p_spi->SPI_IMR; +} + +void spi_set_clock_polarity(Spi *p_spi, uint32_t ul_pcs_ch, + uint32_t ul_polarity); +void spi_set_clock_phase(Spi *p_spi, uint32_t ul_pcs_ch, uint32_t ul_phase); +void spi_configure_cs_behavior(Spi *p_spi, uint32_t ul_pcs_ch, + uint32_t ul_cs_behavior); +void spi_set_bits_per_transfer(Spi *p_spi, uint32_t ul_pcs_ch, uint32_t ul_bits); +int16_t spi_calc_baudrate_div(const uint32_t baudrate, uint32_t mck); +int16_t spi_set_baudrate_div(Spi *p_spi, uint32_t ul_pcs_ch, + uint8_t uc_baudrate_divider); +void spi_set_transfer_delay(Spi *p_spi, uint32_t ul_pcs_ch, uint8_t uc_dlybs, + uint8_t uc_dlybct); + +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM) +/** + * \brief Get PDC registers base address. + * + * \param p_spi Pointer to an SPI instance. + * + * \return PDC registers base for PDC driver to access. + */ +static inline Pdc *spi_get_pdc_base(Spi *p_spi) +{ + return (Pdc *)&(p_spi->SPI_RPR); +} +#endif + +#if (SAM3U || SAM3XA || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Get transmit data register address for DMA operation. + * + * \param p_spi Pointer to an SPI instance. + * + * \return Transmit address for DMA access. + */ +static inline void *spi_get_tx_access(Spi *p_spi) +{ + return (void *)&(p_spi->SPI_TDR); +} + +/** + * \brief Get receive data register address for DMA operation. + * + * \param p_spi Pointer to an SPI instance. + * + * \return Receive address for DMA access. + */ +static inline void *spi_get_rx_access(Spi *p_spi) +{ + return (void *)&(p_spi->SPI_RDR); +} +#endif + +void spi_set_writeprotect(Spi *p_spi, uint32_t ul_enable); +uint32_t spi_get_writeprotect_status(Spi *p_spi); + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \page sam_spi_quickstart Quickstart guide for SAM SPI driver + * + * This is the quickstart guide for the \ref spi_group "SAM SPI driver", + * with step-by-step instructions on how to configure and use the driver in a + * selection of use cases. + * + * The use cases contain several code fragments. The code fragments in the + * steps for setup can be copied into a custom initialization function, while + * the steps for usage can be copied into, e.g.the main application function. + * + * \section spi_basic_use_case Basic use case + * In this basic use case, the SPI module are configured for: + * - Master mode + * - Interrupt-based handling + * + * \subsection sam_spi_quickstart_prereq Prerequisites + * -# \ref sysclk_group "System Clock Management (Sysclock)" + * + * \section spi_basic_use_case_setup Setup steps + * \subsection spi_basic_use_case_setup_code Example code + * Add to application C-file: + * \code + void spi_master_init(Spi *p_spi) + { + spi_enable_clock(p_spi); + spi_reset(p_spi); + spi_set_master_mode(p_spi); + spi_disable_mode_fault_detect(p_spi); + spi_disable_loopback(p_spi); + spi_set_peripheral_chip_select_value(p_spi, + spi_get_pcs(DEFAULT_CHIP_ID)); + spi_set_fixed_peripheral_select(p_spi); + spi_disable_peripheral_select_decode(p_spi); + spi_set_delay_between_chip_select(p_spi, CONFIG_SPI_MASTER_DELAY_BCS); + } + void spi_master_setup_device(Spi *p_spi, struct spi_device *device, + spi_flags_t flags, uint32_t baud_rate, board_spi_select_id_t sel_id) + { + spi_set_transfer_delay(p_spi, device->id, CONFIG_SPI_MASTER_DELAY_BS, + CONFIG_SPI_MASTER_DELAY_BCT); + + spi_set_bits_per_transfer(p_spi, device->id, CONFIG_SPI_MASTER_BITS_PER_TRANSFER); + spi_set_baudrate_div(p_spi, device->id, + spi_calc_baudrate_div(baud_rate, sysclk_get_peripheral_hz())); + + spi_configure_cs_behavior(p_spi, device->id, SPI_CS_KEEP_LOW); + + spi_set_clock_polarity(p_spi, device->id, flags >> 1); + spi_set_clock_phase(p_spi, device->id, ((flags & 0x1) ^ 0x1)); + } +\endcode + * + * \subsection spi_basic_use_case_setup_flow Workflow + * -# Initialize the SPI in master mode: + * - \code + void spi_master_init(SPI_EXAMPLE); +\endcode + * -# Set up an SPI device: + * - \code void spi_master_setup_device(SPI_EXAMPLE, &SPI_DEVICE_EXAMPLE, + SPI_MODE_0, SPI_EXAMPLE_BAUDRATE, 0); \endcode + * - \note The returned device descriptor structure must be passed to the driver + * whenever that device should be used as current slave device. + * -# Enable SPI module: + * - \code spi_enable(SPI_EXAMPLE); \endcode + */ +#endif /* SPI_H_INCLUDED */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/tc/tc.c b/hw-libs/drivers/SAMx70/ASF/sam/drivers/tc/tc.c new file mode 100644 index 000000000..61c7c5d7e --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/tc/tc.c @@ -0,0 +1,766 @@ +/** + * \file + * + * \brief SAM Timer Counter (TC) driver. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include +#include "tc.h" + +/// @cond +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +#ifndef TC_WPMR_WPKEY_PASSWD +#define TC_WPMR_WPKEY_PASSWD TC_WPMR_WPKEY((uint32_t)0x54494D) +#endif + +/** + * \brief Configure TC for timer, waveform generation, or capture. + * + * \param[in,out] p_tc Module hardware register base address pointer + * \param[in] ul_channel Channel to configure + * \param[in] ul_mode Control mode register bitmask value to set + * + * \note For more information regarding ul_mode configuration refer to + * the section entitled "Channel Mode Register: Capture Mode" and/or section + * "Waveform Operating Mode" in the device-specific datasheet. + * + * \note If the TC is configured for waveform generation then the external event + * selection (EEVT) should only be set to TC_CMR_EEVT_TIOB, or the + * equivalent value of 0, if it really is the intention to use TIOB as an + * external event trigger. This is because this setting forces TIOB to be + * an input, even if the external event trigger has not been enabled with + * TC_CMR_ENETRG, and thus prevents normal operation of TIOB. + */ +void tc_init( + Tc *p_tc, + uint32_t ul_channel, + uint32_t ul_mode) +{ + TcChannel *tc_channel; + + /* Validate inputs. */ + Assert(p_tc); + Assert(ul_channel < + (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); + tc_channel = p_tc->TC_CHANNEL + ul_channel; + + /* Disable TC clock. */ + tc_channel->TC_CCR = TC_CCR_CLKDIS; + + /* Disable interrupts. */ + tc_channel->TC_IDR = 0xFFFFFFFF; + + /* Clear status register. */ + tc_channel->TC_SR; + + /* Set mode. */ + tc_channel->TC_CMR = ul_mode; +} + +/** + * \brief Asserts a SYNC signal to generate a software trigger on + * all channels. + * + * \param[out] p_tc Module hardware register base address pointer + * + */ +void tc_sync_trigger( + Tc *p_tc) +{ + /* Validate inputs. */ + Assert(p_tc); + + p_tc->TC_BCR = TC_BCR_SYNC; +} + +/** + * \brief Configure the TC Block mode. + * + * \note The function tc_init() must be called prior to this one. + * + * \param[out] p_tc Module hardware register base address pointer + * \param[in] ul_blockmode Block mode register value to set + * + * \note For more information regarding ul_blockmode configuration refer to + * the section entitled "TC Block Mode Register" in the device-specific datasheet. + */ +void tc_set_block_mode( + Tc *p_tc, + uint32_t ul_blockmode) +{ + /* Validate inputs. */ + Assert(p_tc); + + p_tc->TC_BMR = ul_blockmode; +} + +#if (!SAM3U) || defined(__DOXYGEN__) + +/** + * \brief Configure TC for 2-bit Gray Counter for Stepper Motor. + * \note The function tc_init() must be called prior to this one. + * + * \note This function is not available on SAM3U devices. + * + * \param[out] p_tc Module hardware register base address pointer + * \param[in] ul_channel Channel to configure + * \param[in] ul_steppermode Stepper motor mode register value to set + * + * \return 0 for OK. + */ +uint32_t tc_init_2bit_gray( + Tc *p_tc, + uint32_t ul_channel, + uint32_t ul_steppermode) +{ + /* Validate inputs. */ + Assert(p_tc); + Assert(ul_channel < + (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); + + p_tc->TC_CHANNEL[ul_channel].TC_SMMR = ul_steppermode; + return 0; +} + +#endif /* (!SAM3U) || defined(__DOXYGEN__) */ + +/** + * \brief Start the TC clock on the specified channel. + * + * \param[out] p_tc Module hardware register base address pointer + * \param[in] ul_channel Channel to configure + */ +void tc_start( + Tc *p_tc, + uint32_t ul_channel) +{ + /* Validate inputs. */ + Assert(p_tc); + Assert(ul_channel < + (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); + + p_tc->TC_CHANNEL[ul_channel].TC_CCR = TC_CCR_CLKEN | TC_CCR_SWTRG; +} + +/** + * \brief Stop the TC clock on the specified channel. + * + * \param[out] p_tc Module hardware register base address pointer + * \param[in] ul_channel Channel to configure + */ +void tc_stop( + Tc *p_tc, + uint32_t ul_channel) +{ + /* Validate inputs. */ + Assert(p_tc); + Assert(ul_channel < + (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); + + p_tc->TC_CHANNEL[ul_channel].TC_CCR = TC_CCR_CLKDIS; +} + +/** + * \brief Read the counter value on the specified channel. + * + * \param[in] p_tc Module hardware register base address pointer + * \param[in] ul_channel Channel to read + * + * \return The counter value. + */ +uint32_t tc_read_cv( + Tc *p_tc, + uint32_t ul_channel) +{ + /* Validate inputs. */ + Assert(p_tc); + Assert(ul_channel < + (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); + + return p_tc->TC_CHANNEL[ul_channel].TC_CV; +} + +/** + * \brief Read TC Register A (RA) on the specified channel. + * + * \param[in] p_tc Module hardware register base address pointer + * \param[in] ul_channel Channel to read + * + * \return The TC Register A (RA) value. + */ +uint32_t tc_read_ra( + Tc *p_tc, + uint32_t ul_channel) +{ + /* Validate inputs. */ + Assert(p_tc); + Assert(ul_channel < + (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); + + return p_tc->TC_CHANNEL[ul_channel].TC_RA; +} + +/** + * \brief Read TC Register B (RB) on the specified channel. + * + * \param[in] p_tc Module hardware register base address pointer + * \param[in] ul_channel Channel to read + * + * \return The TC Register B (RB) value. + */ +uint32_t tc_read_rb( + Tc *p_tc, + uint32_t ul_channel) +{ + /* Validate inputs. */ + Assert(p_tc); + Assert(ul_channel < + (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); + + return p_tc->TC_CHANNEL[ul_channel].TC_RB; +} + +/** + * \brief Read TC Register C (RC) on the specified channel. + * + * \param[in] p_tc Module hardware register base address pointer + * \param[in] ul_channel Channel to read + * + * \return The Register C (RC) value. + */ +uint32_t tc_read_rc( + Tc *p_tc, + uint32_t ul_channel) +{ + /* Validate inputs. */ + Assert(p_tc); + Assert(ul_channel < + (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); + + return p_tc->TC_CHANNEL[ul_channel].TC_RC; +} + +/** + * \brief Write to TC Register A (RA) on the specified channel. + * + * \param[out] p_tc Module hardware register base address pointer + * \param[in] ul_channel Channel to write + * \param[in] ul_value Value to write + */ +void tc_write_ra( + Tc *p_tc, + uint32_t ul_channel, + uint32_t ul_value) +{ + /* Validate inputs. */ + Assert(p_tc); + Assert(ul_channel < + (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); + + p_tc->TC_CHANNEL[ul_channel].TC_RA = ul_value; +} + +/** + * \brief Write to TC Register B (RB) on the specified channel. + * + * \param[out] p_tc Module hardware register base address pointer + * \param[in] ul_channel Channel to write + * \param[in] ul_value Value to write + */ +void tc_write_rb( + Tc *p_tc, + uint32_t ul_channel, + uint32_t ul_value) +{ + /* Validate inputs. */ + Assert(p_tc); + Assert(ul_channel < + (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); + + p_tc->TC_CHANNEL[ul_channel].TC_RB = ul_value; +} + +/** + * \brief Write to TC Register C (RC) on the selected channel. + * + * \param[out] p_tc Module hardware register base address pointer + * \param[in] ul_channel Channel to write + * \param[in] ul_value Value to write + */ +void tc_write_rc( + Tc *p_tc, + uint32_t ul_channel, + uint32_t ul_value) +{ + /* Validate inputs. */ + Assert(p_tc); + Assert(ul_channel < + (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); + + p_tc->TC_CHANNEL[ul_channel].TC_RC = ul_value; +} + +/** + * \brief Enable the TC interrupts on the specified channel. + * + * \param[in,out] p_tc Module hardware register base address pointer + * \param[in] ul_channel Channel to configure + * \param[in] ul_sources Bitmask of interrupt sources + * + * Where the input parameter ul_sources can be one or more of the following: + * + * + * + * + * + * + * + * + * + * + * + * + * + *
Parameter ValueDescription
TC_IER_COVFSEnables the Counter Overflow Interrupt
TC_IER_LOVRSEnables the Load Overrun Interrupt
TC_IER_CPASEnables the RA Compare Interrupt
TC_IER_CPBSEnables the RB Compare Interrupt
TC_IER_CPCSEnables the RC Compare Interrupt
TC_IER_LDRASEnables the RA Load Interrupt
TC_IER_LDRBSEnables the RB Load Interrupt
TC_IER_ETRGSEnables the External Trigger Interrupt
+ */ +void tc_enable_interrupt( + Tc *p_tc, + uint32_t ul_channel, + uint32_t ul_sources) +{ + TcChannel *tc_channel; + + /* Validate inputs. */ + Assert(p_tc); + Assert(ul_channel < + (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); + tc_channel = p_tc->TC_CHANNEL + ul_channel; + tc_channel->TC_IER = ul_sources; +} + +/** + * \brief Disable TC interrupts on the specified channel. + * + * \param[in,out] p_tc Module hardware register base address pointer + * \param[in] ul_channel Channel to configure + * \param[in] ul_sources A bitmask of Interrupt sources + * + * Where the input parameter ul_sources can be one or more of the following: + * + * + * + * + * + * + * + * + * + * + * + * + * + *
Parameter ValueDescription
TC_IDR_COVFSDisables the Counter Overflow Interrupt
TC_IDR_LOVRSDisables the Load Overrun Interrupt
TC_IDR_CPASDisables the RA Compare Interrupt
TC_IDR_CPBSDisables the RB Compare Interrupt
TC_IDR_CPCSDisables the RC Compare Interrupt
TC_IDR_LDRASDisables the RA Load Interrupt
TC_IDR_LDRBSDisables the RB Load Interrupt
TC_IDR_ETRGSDisables the External Trigger Interrupt
+ */ +void tc_disable_interrupt( + Tc *p_tc, + uint32_t ul_channel, + uint32_t ul_sources) +{ + TcChannel *tc_channel; + + /* Validate inputs. */ + Assert(p_tc); + Assert(ul_channel < + (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); + tc_channel = p_tc->TC_CHANNEL + ul_channel; + tc_channel->TC_IDR = ul_sources; +} + +/** + * \brief Read the TC interrupt mask for the specified channel. + * + * \param[in] p_tc Module hardware register base address pointer + * \param[in] ul_channel Channel to read + * + * \return The TC interrupt mask value. + */ +uint32_t tc_get_interrupt_mask( + Tc *p_tc, + uint32_t ul_channel) +{ + TcChannel *tc_channel; + + /* Validate inputs. */ + Assert(p_tc); + Assert(ul_channel < + (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); + tc_channel = p_tc->TC_CHANNEL + ul_channel; + return tc_channel->TC_IMR; +} + +/** + * \brief Get the current status for the specified TC channel. + * + * \param[in] p_tc Module hardware register base address pointer + * \param[in] ul_channel Channel number + * + * \return The current TC status. + */ +uint32_t tc_get_status( + Tc *p_tc, + uint32_t ul_channel) +{ + TcChannel *tc_channel; + + /* Validate inputs. */ + Assert(p_tc); + Assert(ul_channel < + (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); + + tc_channel = p_tc->TC_CHANNEL + ul_channel; + return tc_channel->TC_SR; +} + +/* TC divisor used to find the lowest acceptable timer frequency */ +#define TC_DIV_FACTOR 65536 + +#if (!SAM4L) && !defined(__DOXYGEN__) + +#ifndef FREQ_SLOW_CLOCK_EXT +#define FREQ_SLOW_CLOCK_EXT 32768 /* External slow clock frequency (hz) */ +#endif + +/** + * \brief Find the best MCK divisor. + * + * Finds the best MCK divisor given the timer frequency and MCK. The result + * is guaranteed to satisfy the following equation: + * \code (MCK / (DIV * 65536)) <= freq <= (MCK / DIV) \endcode + * With DIV being the lowest possible value, to maximize timing adjust resolution. + * + * \param[in] ul_freq Desired timer frequency + * \param[in] ul_mck Master clock frequency + * \param[out] p_uldiv Divisor value + * \param[out] p_ultcclks TCCLKS field value for divisor + * \param[in] ul_boardmck Board clock frequency + * + * \return The divisor found status. + * \retval 0 No suitable divisor was found + * \retval 1 A divisor was found + */ +uint32_t tc_find_mck_divisor( + uint32_t ul_freq, + uint32_t ul_mck, + uint32_t *p_uldiv, + uint32_t *p_ultcclks, + uint32_t ul_boardmck) +{ + const uint32_t divisors[5] = { 2, 8, 32, 128, + ul_boardmck / FREQ_SLOW_CLOCK_EXT }; + uint32_t ul_index; + uint32_t ul_high, ul_low; + + /* Satisfy frequency bound. */ + for (ul_index = 0; + ul_index < (sizeof(divisors) / sizeof(divisors[0])); + ul_index++) { + ul_high = ul_mck / divisors[ul_index]; + ul_low = ul_high / TC_DIV_FACTOR; + if (ul_freq > ul_high) { + return 0; + } else if (ul_freq >= ul_low) { + break; + } + } + if (ul_index >= (sizeof(divisors) / sizeof(divisors[0]))) { + return 0; + } + + /* Store results. */ + if (p_uldiv) { + *p_uldiv = divisors[ul_index]; + } + + if (p_ultcclks) { + *p_ultcclks = ul_index; + } + + return 1; +} + +#endif /* (!SAM4L) */ + +#if (SAM4L) || defined(__DOXYGEN__) +/** + * \brief Find the best PBA/MCK divisor. + * + * For SAM4L devices: Finds the best PBA divisor given the timer + * frequency and PBA clock. The result is guaranteed to satisfy the following equation: + * \code (ul_pbaclk / (2* DIV * 65536)) <= freq <= (ul_pbaclk / (2* DIV)) \endcode + * with DIV being the lowest possible value, to maximize timing adjust resolution. + * + * For non SAM4L devices: Finds the best MCK divisor given the timer frequency + * and MCK. The result is guaranteed to satisfy the following equation: + * \code (MCK / (DIV * 65536)) <= freq <= (MCK / DIV) \endcode + * with DIV being the lowest possible value, to maximize timing adjust resolution. + * + * \param[in] ul_freq Desired timer frequency + * \param[in] ul_mck PBA clock frequency + * \param[out] p_uldiv Divisor value + * \param[out] p_ultcclks TCCLKS field value for divisor + * \param[in] ul_boardmck Board clock frequency (set to 0 for SAM4L devices) + * + * \return The divisor found status. + * \retval 0 No suitable divisor was found + * \retval 1 A divisor was found + */ +uint32_t tc_find_mck_divisor( + uint32_t ul_freq, + uint32_t ul_mck, + uint32_t *p_uldiv, + uint32_t *p_ultcclks, + uint32_t ul_boardmck) +{ + const uint32_t divisors[5] = { 0, 2, 8, 32, 128}; + uint32_t ul_index; + uint32_t ul_high, ul_low; + + UNUSED(ul_boardmck); + + /* Satisfy frequency bound. */ + for (ul_index = 1; + ul_index < (sizeof(divisors) / sizeof(divisors[0])); + ul_index++) { + ul_high = ul_mck / divisors[ul_index]; + ul_low = ul_high / TC_DIV_FACTOR; + if (ul_freq > ul_high) { + return 0; + } else if (ul_freq >= ul_low) { + break; + } + } + if (ul_index >= (sizeof(divisors) / sizeof(divisors[0]))) { + return 0; + } + + /* Store results. */ + if (p_uldiv) { + *p_uldiv = divisors[ul_index]; + } + + if (p_ultcclks) { + *p_ultcclks = ul_index; + } + + return 1; +} + +#endif /* (SAM4L) || defined(__DOXYGEN__) */ + +#if (!SAM4L && !SAMG) || defined(__DOXYGEN__) + +/** + * \brief Enable TC QDEC interrupts. + * + * \note This function is not available on SAM4L or SAMG devices. + * + * \param[out] p_tc Module hardware register base address pointer + * \param[in] ul_sources A bitmask of QDEC interrupts to be enabled + * + * Where the input parameter ul_sources can be one or more of the following: + * + * + * + * + * + * + * + * + *
Parameter ValueDescription
TC_QIER_IDXEnable the rising edge detected on IDX input interrupt
TC_QIER_DIRCHGEnable the change in rotation direction detected interrupt
TC_QIER_QERREnable the quadrature error detected on PHA/PHB interrupt
+ */ +void tc_enable_qdec_interrupt( + Tc *p_tc, + uint32_t ul_sources) +{ + /* Validate inputs. */ + Assert(p_tc); + + p_tc->TC_QIER = ul_sources; +} + +/** + * \brief Disable TC QDEC interrupts. + * + * \note This function is not available on SAM4L or SAMG devices. + * + * \param[out] p_tc Module hardware register base address pointer + * \param[in] ul_sources A bitmask of QDEC interrupts to be disabled + * + * Where the input parameter ul_sources can be one or more of the following: + * + * + * + * + * + * + * + * + *
Parameter ValueDescription
TC_QIDR_IDXDisable the rising edge detected on IDX input interrupt
TC_QIDR_DIRCHGDisable the change in rotation direction detected interrupt
TC_QIDR_QERRDisable the quadrature error detected on PHA/PHB interrupt
+ */ +void tc_disable_qdec_interrupt( + Tc *p_tc, + uint32_t ul_sources) +{ + /* Validate inputs. */ + Assert(p_tc); + + p_tc->TC_QIDR = ul_sources; +} + +/** + * \brief Read TC QDEC interrupt mask. + * + * \note This function is not available on SAM4L or SAMG devices. + * + * \param[in] p_tc Module hardware register base address pointer + * + * \return The QDEC interrupt mask value. + */ +uint32_t tc_get_qdec_interrupt_mask( + Tc *p_tc) +{ + /* Validate inputs. */ + Assert(p_tc); + + return p_tc->TC_QIMR; +} + +/** + * \brief Get current TC QDEC interrupt status. + * + * \note This function is not available on SAM4L or SAMG devices. + * + * \param[in] p_tc Module hardware register base address pointer + * + * \return The TC QDEC interrupt status. + */ +uint32_t tc_get_qdec_interrupt_status( + Tc *p_tc) +{ + /* Validate inputs. */ + Assert(p_tc); + + return p_tc->TC_QISR; +} + +#endif /* (!SAM4L && !SAMG) || defined(__DOXYGEN__) */ + +#if (!SAM3U) || defined(__DOXYGEN__) + +/** + * \brief Enable or disable write protection of TC registers. + * + * \note This function is not available on SAM3U devices. + * + * \param[out] p_tc Module hardware register base address pointer + * \param[in] ul_enable 1 to enable, 0 to disable + */ +void tc_set_writeprotect( + Tc *p_tc, + uint32_t ul_enable) +{ + /* Validate inputs. */ + Assert(p_tc); + + if (ul_enable) { + p_tc->TC_WPMR = TC_WPMR_WPKEY_PASSWD | TC_WPMR_WPEN; + } else { + p_tc->TC_WPMR = TC_WPMR_WPKEY_PASSWD; + } +} + +#endif /* (!SAM3U) || defined(__DOXYGEN__) */ + +#if SAM4L || defined(__DOXYGEN__) + +/** + * \brief Indicate TC features. + * + * \note This function is only available on SAM4L devices. + * + * \param[in] p_tc Module hardware register base address pointer + * + * \return The TC FEATURES register contents. + */ +uint32_t tc_get_feature( + Tc *p_tc) +{ + /* Validate inputs. */ + Assert(p_tc); + + return p_tc->TC_FEATURES; +} + +/** + * \brief Indicate TC version. + * + * \note This function is only available on SAM4L devices. + * + * \param[in] p_tc Module hardware register base address pointer + * + * \return The TC VERSION register contents. + */ +uint32_t tc_get_version( + Tc *p_tc) +{ + /* Validate inputs. */ + Assert(p_tc); + + return p_tc->TC_VERSION; +} + +#endif /* SAM4L || defined(__DOXYGEN__) */ + +/// @cond +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/tc/tc.h b/hw-libs/drivers/SAMx70/ASF/sam/drivers/tc/tc.h new file mode 100644 index 000000000..8377f24cf --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/tc/tc.h @@ -0,0 +1,445 @@ +/** + * \file + * + * \brief SAM Timer Counter (TC) driver. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef TC_H_INCLUDED +#define TC_H_INCLUDED + +/** + * \defgroup asfdoc_sam_drivers_tc_group SAM3/4S/4L/4E/4N/4CM/4C/G Timer Counter (TC) Driver + * + * This driver for Atmel® | SMART ARM®-based microcontrollers + * provides an interface for the configuration and management of the + * device's Timer Counter functionality. + * + * The Timer Counter (TC) includes several identical 16-bit or 32-bit + * Timer Counter channels. Each channel can be independently programmed + * to perform a wide range of functions that includes frequency + * measurement, event counting, interval measurement, pulse generation, + * delay timing, and pulse width modulation. + * + * Devices from the following series can use this module: + * - Atmel | SMART SAM3 + * - Atmel | SMART SAM4S + * - Atmel | SMART SAM4L + * - Atmel | SMART SAM4E + * - Atmel | SMART SAM4N + * - Atmel | SMART SAM4CM + * - Atmel | SMART SAM4C + * - Atmel | SMART SAMG + * + * The outline of this documentation is as follows: + * - \ref asfdoc_sam_drivers_tc_prerequisites + * - \ref asfdoc_sam_drivers_tc_module_overview + * - \ref asfdoc_sam_drivers_tc_special_considerations + * - \ref asfdoc_sam_drivers_tc_extra_info + * - \ref asfdoc_sam_drivers_tc_examples + * - \ref asfdoc_sam_drivers_tc_api_overview + * + * + * \section asfdoc_sam_drivers_tc_prerequisites Prerequisites + * + * There are no prerequisites for this module. + * + * + * \section asfdoc_sam_drivers_tc_module_overview Module Overview + * The Timer Counter (TC) includes several identical 16-bit or 32-bit Timer + * Counter channels. The number of TC channels is device specific, refer + * to the device-specific datasheet for more information. + * + * Each channel can be independently programmed to perform a wide range of + * functions that includes frequency measurement, event counting, interval measurement, + * pulse generation, delay timing, and pulse width modulation. + * + * Each channel has three external clock inputs, five internal clock inputs, + * and two multi-purpose input/output signals which can be configured by the user. + * Each channel drives an internal interrupt signal which can be programmed to + * generate processor interrupts. + * + * The Timer Counter (TC) embeds a quadrature decoder logic connected in front of + * the timers. When enabled, the quadrature decoder performs the input line + * filtering, decoding of quadrature signals and connects to the timers/counters + * in order to read the position and speed of the motor. + * + * + * \section asfdoc_sam_drivers_tc_special_considerations Special Considerations + * \subsection asfdoc_sam_drivers_tc_special_considerations_clock External Clock + * In all cases, if an external clock is used, the duration of each of its levels + * must be longer than the master clock (MCLK) period. The external clock frequency + * must be at least 2.5 times lower than the master clock. + * + * \subsection asfdoc_sam_drivers_tc_special_considerations_trigger External Trigger + * If an external trigger is used, the duration of its pulses must be longer than + * the master clock (MCLK) period in order to be detected. + * + * + * \section asfdoc_sam_drivers_tc_extra_info Extra Information + * + * For extra information, see \ref asfdoc_sam_drivers_tc_extra. This includes: + * - \ref asfdoc_sam_drivers_tc_extra_acronyms + * - \ref asfdoc_sam_drivers_tc_extra_dependencies + * - \ref asfdoc_sam_drivers_tc_extra_errata + * - \ref asfdoc_sam_drivers_tc_extra_history + * + * \section asfdoc_sam_drivers_tc_examples Examples + * + * For a list of examples related to this driver, see + * \ref asfdoc_sam_drivers_tc_exqsg. + * + * + * \section asfdoc_sam_drivers_tc_api_overview API Overview + * @{ + */ + +#include + +/// @cond +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +void tc_init(Tc *p_tc, uint32_t ul_Channel, uint32_t ul_Mode); +void tc_sync_trigger(Tc *p_tc); +void tc_set_block_mode(Tc *p_tc, uint32_t ul_blockmode); + +#if (!SAM3U) || defined(__DOXYGEN__) +uint32_t tc_init_2bit_gray(Tc *p_tc, uint32_t ul_channel, + uint32_t ul_steppermode); +#endif /* (!SAM3U) || defined(__DOXYGEN__) */ + +void tc_start(Tc *p_tc, uint32_t ul_channel); +void tc_stop(Tc *p_tc, uint32_t ul_channel); + +uint32_t tc_read_cv(Tc *p_tc, uint32_t ul_channel); +uint32_t tc_read_ra(Tc *p_tc, uint32_t ul_channel); +uint32_t tc_read_rb(Tc *p_tc, uint32_t ul_channel); +uint32_t tc_read_rc(Tc *p_tc, uint32_t ul_channel); + +void tc_write_ra(Tc *p_tc, uint32_t ul_channel, + uint32_t ul_value); +void tc_write_rb(Tc *p_tc, uint32_t ul_channel, + uint32_t ul_value); +void tc_write_rc(Tc *p_tc, uint32_t ul_channel, + uint32_t ul_value); + +uint32_t tc_find_mck_divisor(uint32_t ul_freq, uint32_t ul_mck, + uint32_t *p_uldiv, uint32_t *ul_tcclks, uint32_t ul_boardmck); +void tc_enable_interrupt(Tc *p_tc, uint32_t ul_channel, + uint32_t ul_sources); +void tc_disable_interrupt(Tc *p_tc, uint32_t ul_channel, + uint32_t ul_sources); +uint32_t tc_get_interrupt_mask(Tc *p_tc, uint32_t ul_channel); +uint32_t tc_get_status(Tc *p_tc, uint32_t ul_channel); +#if (!SAM4L && !SAMG) || defined(__DOXYGEN__) +void tc_enable_qdec_interrupt(Tc *p_tc, uint32_t ul_sources); +void tc_disable_qdec_interrupt(Tc *p_tc, uint32_t ul_sources); +uint32_t tc_get_qdec_interrupt_mask(Tc *p_tc); +uint32_t tc_get_qdec_interrupt_status(Tc *p_tc); +#endif /* (!SAM4L && !SAMG) || defined(__DOXYGEN__) */ + +#if (!SAM3U) +void tc_set_writeprotect(Tc *p_tc, uint32_t ul_enable); +#endif /* (!SAM3U) */ + +#if SAM4L || defined(__DOXYGEN__) +uint32_t tc_get_feature(Tc *p_tc); +uint32_t tc_get_version(Tc *p_tc); +#endif /* SAM4L || defined(__DOXYGEN__) */ + +/// @cond +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +/** @} */ + +/** + * \page asfdoc_sam_drivers_tc_extra Extra Information for Timer Counter Driver + * + * \section asfdoc_sam_drivers_tc_extra_acronyms Acronyms + * Below is a table listing the acronyms used in this module, along with their + * intended meanings. + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
AcronymDefinition
MCKMaster Clock
PBAPeripheral Bus A clock
PHAQuadrature Decoder input signal Phase A
PHBQuadrature Decoder input signal Phase B
QDECQuadrature Decoder
QSGQuick Start Guide
RARegister A
RBRegister B
RCRegister C
TIOBTimer Input Output B
+ * + * + * \section asfdoc_sam_drivers_tc_extra_dependencies Dependencies + * This driver has the following dependencies: + * + * - \ref clk_group "System Clock Management (sysclock)" + * - \ref asfdoc_sam_drivers_gpio_group "General Purpose I/O (GPIO) driver" + * - \ref asfdoc_sam_drivers_pmc_group "Power Manager Controller (PMC) driver" + * + * + * \section asfdoc_sam_drivers_tc_extra_errata Errata + * There are no errata related to this driver. + * + * + * \section asfdoc_sam_drivers_tc_extra_history Module History + * An overview of the module history is presented in the table below, with + * details on the enhancements and fixes made to the module since its first + * release. The current version of this corresponds to the newest version in + * the table. + * + * + * + * + * + * + * + * + *
Changelog
Initial document release
+ */ + +/** + * \page asfdoc_sam_drivers_tc_exqsg Examples for Timer Counter + * + * This is a list of the available Quick Start Guides (QSGs) and example + * applications for \ref asfdoc_sam_drivers_tc_group. QSGs are simple examples with + * step-by-step instructions to configure and use this driver in a selection of + * use cases. Note that a QSG can be compiled as a standalone application or be + * added to the user application. + * + * - \subpage asfdoc_sam_drivers_tc_qsg + * - \subpage asfdoc_sam_drivers_tc_example + * + * \page asfdoc_sam_drivers_tc_document_revision_history Document Revision History + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
Doc. Rev. + * Date + * Comments + *
42301B07/2015Updated title of application note and added list of supported devices
42301A05/2014Initial document release
+ * + */ + +/** + * \page asfdoc_sam_drivers_tc_qsg Quick Start Guide for the TC driver + * + * This is the quick start guide for the \ref asfdoc_sam_drivers_tc_group, with + * step-by-step instructions on how to configure and use the driver for + * a specific use case. The code examples can be copied into the main + * application loop or any other function that will need to control the + * AST module. + * + * \section asfdoc_sam_drivers_tc_qsg_use_cases Use Cases + * - \ref asfdoc_sam_drivers_tc_qsg_basic_capture + * - \ref asfdoc_sam_drivers_tc_qsg_basic_waveform + * + * \section asfdoc_sam_drivers_tc_qsg_basic_capture TC Capture Mode Basic Usage + * + * This use case will demonstrate how to initialize the TC module to + * operate in capture mode using interrupts. Note, that the macros + * used to select the TC channel are device specific. Refer to the + * appropriate device-specific datasheet for more information. + * + * + * \section asfdoc_sam_drivers_tc_qsg_basic_capture_setup Setup Steps + * + * \subsection asfdoc_sam_tc_qsg_basic_capture_prereq Prerequisites + * + * This module requires the following services: + * - \ref clk_group "System Clock Management (sysclock)" + * - \ref asfdoc_sam_drivers_gpio_group "General Purpose I/O (GPIO) driver" + * + * \subsection asfdoc_sam_drivers_tc_qsg_basic_capture_setup_code Setup Code + * + * Add these macros to the top of your main application C-file: + * \snippet conf_board.h tc_define_peripheral + * \snippet conf_board.h tc_define_ch2 + * \snippet conf_board.h tc_define_irq_handler + * + * Add this macro and functions to your main application C-file: + * \snippet tc_capture_waveform_example.c tc_capture_selection + * \snippet tc_capture_waveform_example.c tc_capture_init + * \snippet tc_capture_waveform_example.c tc_capture_irq_handler_start + * \snippet tc_capture_waveform_example.c tc_capture_irq_handler_end + * + * \subsection asfdoc_sam_drivers_tc_qsg_basic_capture_setup_workflow Workflow + * + * -# Enable the TC module's capture pin: + * \snippet tc_capture_waveform_example.c tc_capture_gpio + * -# Initialize the capture channel to the following: + * - Load RA on the rising edge of TIOA + * - Load RB on the falling edge of TIOA + * - Set the external trigger to TIOA + * - Set the external trigger to falling edge + * \snippet tc_capture_waveform_example.c tc_capture_init_call + * -# Enable the TC interrupt using NVIC: + * \snippet tc_capture_waveform_example.c tc_capture_init_irq + * -# Enable the capture channel interrupt: + * \snippet tc_capture_waveform_example.c tc_capture_init_module_irq + * -# In the \ref TC_Handler_null "TC_Handler()" function, the load. + * RB interrupt can be checked by: + * \snippet tc_capture_waveform_example.c tc_capture_irq_handler_status + * \code } \endcode + * -# In the \ref TC_Handler_null "TC_Handler()" function, the RA value. + * can be read by: + * \code uint32_t gs_ul_captured_ra; \endcode + * \snippet tc_capture_waveform_example.c tc_capture_irq_handler_read_ra + * -# In the \ref TC_Handler_null "TC_Handler()" function, the RB value. + * can be read by: + * \code uint32_t gs_ul_captured_rb; \endcode + * \snippet tc_capture_waveform_example.c tc_capture_irq_handler_read_rb + * + * \section asfdoc_sam_drivers_tc_qsg_basic_waveform TC Waveform Mode Basic Usage + * + * This use case will demonstrate how to initialize the TC module to + * operate in waveform mode. Note, that the macros used to select + * the TC channel are device specific. Refer to the appropriate + * device-specific datasheet for more information. + * + * + * \section asfdoc_sam_drivers_tc_qsg_basic_waveform_setup Setup Steps + * + * \subsection asfdoc_sam_tc_qsg_basic_waveform_prereq Prerequisites + * + * This module requires the following services: + * - \ref clk_group "System Clock Management (sysclock)" + * - \ref asfdoc_sam_drivers_gpio_group "General Purpose I/O (GPIO) driver" + * + * \subsection asfdoc_sam_drivers_tc_qsg_basic_waveform_setup_code Setup Code + * + * Add these macros to the top of your main application C-file: + * \snippet conf_board.h tc_define_peripheral + * \snippet conf_board.h tc_define_ch1 + * + * Add these macros and function to your main application C-file: + * \code #define TC_WAVEFORM_TIMER_SELECTION TC_CMR_TCCLKS_TIMER_CLOCK4 \endcode + * \code #define TC_WAVEFORM_DIVISOR 128 \endcode + * \code #define TC_WAVEFORM_FREQUENCY 178 \endcode + * \code #define TC_WAVEFORM_DUTY_CYCLE 30 \endcode + * \code + * static void tc_waveform_initialize(void) + * { + * uint32_t ra, rc; + * + * // Configure the PMC to enable the TC module. + * sysclk_enable_peripheral_clock(ID_TC_WAVEFORM); + * + * // Init TC to waveform mode. + * tc_init(TC, TC_CHANNEL_WAVEFORM, + * TC_WAVEFORM_TIMER_SELECTION // Waveform Clock Selection + * | TC_CMR_WAVE // Waveform mode is enabled + * | TC_CMR_ACPA_SET // RA Compare Effect: set + * | TC_CMR_ACPC_CLEAR // RC Compare Effect: clear + * | TC_CMR_CPCTRG // UP mode with automatic trigger on RC Compare + * ); + * + * // Configure waveform frequency and duty cycle. + * rc = (sysclk_get_peripheral_bus_hz(TC) / + * TC_WAVEFORM_DIVISOR / + * TC_WAVEFORM_FREQUENCY; + * tc_write_rc(TC, TC_CHANNEL_WAVEFORM, rc); + * ra = (100 - TC_WAVEFORM_FREQUENCY_DUTY_CYCLE * rc / 100; + * tc_write_ra(TC, TC_CHANNEL_WAVEFORM, ra); + * + * // Enable TC TC_CHANNEL_WAVEFORM. + * tc_start(TC, TC_CHANNEL_WAVEFORM); + * } \endcode + * + * \subsection asfdoc_sam_drivers_tc_qsg_basic_waveform_setup_workflow Workflow + * + * -# Enable the TC module's waveform pin: + * \snippet tc_capture_waveform_example.c tc_waveform_gpio + * -# Initialize the waveform channel to the following: + * - Output frequency of 178Hz, with a duty-cycle of 30% + * - Use TC_CMR_TCCLKS_TIMER_CLOCK4, with a divisor of 128 + * \snippet tc_capture_waveform_example.c tc_waveform_init_call + */ +#endif /* TC_H_INCLUDED */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/tc/tc_capture_waveform_example/tc_capture_waveform_example.h b/hw-libs/drivers/SAMx70/ASF/sam/drivers/tc/tc_capture_waveform_example/tc_capture_waveform_example.h new file mode 100644 index 000000000..63b32e5bb --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/tc/tc_capture_waveform_example/tc_capture_waveform_example.h @@ -0,0 +1,135 @@ +/** + * \file + * + * \brief TC Capture Waveform Example for SAM. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef TC_CAPTURE_WAVEFORM_EXAMPLE_H_INCLUDED +#define TC_CAPTURE_WAVEFORM_EXAMPLE_H_INCLUDED + +/** + * \page asfdoc_sam_drivers_tc_example Timer Counter Capture Waveform Example + * + * \section asfdoc_sam_drivers_tc_example_purpose Purpose + * + * This example indicates how to use the Timer Counter in capture mode and + * waveform mode in order to measure the pulse frequency and count the total + * pulse number of an external signal injected into the device's TIOA pin. + * + * + * \section asfdoc_sam_drivers_tc_example_requirements Requirements + * + * This package can be used with SAM4 evaluation kits such as the SAM4L EK, + * the SAM4L Xplained Pro, and other evaluation kits. Refer to the list of + * kits available for the actual device on http://www.microchip.com. + * + * It generates a waveform on the Timer Counter pin PIN_TC_WAVEFORM, + * and it captures a waveform from pin PIN_TC_CAPTURE. Refer to the + * respective device evaluation kit's board file (conf_board.h) in order + * to examine these #defines. + * + * Connect PIN_TC_WAVEFORM to PIN_TC_CAPTURE on the evaluation kit. + * + * + * \section asfdoc_sam_drivers_tc_example_description Description + * + * This example shows how to configure the Timer Counter in both waveform and + * capture operating modes. In capture mode, a pulse signal (output from PIN_TC_WAVEFORM) + * is connected to PIN_TC_CAPTURE, and Register A (RA) and Register B (RB) will be loaded + * when their programmed event occurs. + * + * When the Timer Counter interrupt occurs, its interrupt handler reads the RA + * and RB register values (for computing pulse frequency) and also increases the total + * pulse count number. The current pulse frequency and total pulse count number are + * both output via the debug UART. + * + * The code can be roughly broken down as follows: + *
    + *
  • Select pre-defined waveform frequency and duty cycle to be generated + *
  • Configure TC_CHANNEL_WAVEFORM as waveform output + *
  • Configure TC_CHANNEL_CAPTURE as a capture input + *
  • Configure capture Register A (RA) to be loaded when a rising edge on TIOA occurs + *
  • Configure capture Register B (RB) to be loaded when a falling edge on TIOA occurs + *
  • Configure a Timer Counter interrupt and enable the RB load interrupt + *
  • Pressing 'c' in the terminal window, starts capture + *
  • Pressing 's' in the terminal window, stops capture and dumps the information captured so far + *
+ * + * + * \section asfdoc_sam_drivers_tc_example_files Main Files + * + * - tc.c: Timer Counter driver + * - tc.h: Timer Counter driver header file + * - tc_capture_waveform_example.c: Timer Counter example application + * + * + * \section asfdoc_sam_drivers_tc_example_compilinfo Compilation Information + * + * This software is written for GNU GCC and IAR Embedded Workbench® + * for Atmel®. Other compilers may or may not work. + * + * + * \section asfdoc_sam_drivers_tc_example_usage Usage + * + * -# Build the program and download it into the evaluation board. + * -# On the computer, open, and configure a terminal application. + * (e.g., HyperTerminal on Microsoft® Windows®) with these settings: + * - 115200 baud + * - 8 bits of data + * - No parity + * - 1 stop bit + * - No flow control + * -# Start the application. + * -# In the terminal window, the following text should appear: + * \code + * -- TC capture waveform example xxx -- + * -- xxxxxx-xx + * -- Compiled: xxx xx xxxx xx:xx:xx -- \endcode + * -# Choose the item from the following menu to test: + * \code + * Menu : + * ------ + * Output waveform property: + * 0: Set Frequency = 178 Hz, Duty Cycle = 30% + * 1: Set Frequency = 375 Hz, Duty Cycle = 50% + * 2: Set Frequency = 800 Hz, Duty Cycle = 75% + * 3: Set Frequency = 1000 Hz, Duty Cycle = 80% + * 4: Set Frequency = 4000 Hz, Duty Cycle = 55% + * ------------------------------------------- + * c: Capture waveform from TC(TC_PERIPHERAL) channel(TC_CHANNEL_CAPTURE) + * s: Stop capture and display captured information + * h: Display menu + * ------ \endcode + */ + +#endif /* TC_CAPTURE_WAVEFORM_EXAMPLE_H_INCLUDED */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/twihs/twihs.c b/hw-libs/drivers/SAMx70/ASF/sam/drivers/twihs/twihs.c new file mode 100644 index 000000000..52a858a6e --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/twihs/twihs.c @@ -0,0 +1,740 @@ +/** + * \file + * + * \brief Two-Wire Interface (TWIHS) driver for SAM. + * + * Copyright (c) 2013-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "twihs.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \defgroup sam_drivers_twihs_group High-Speed Two-Wire Interface (TWIHS) + * + * Driver for the TWIHS (High-Speed Two-Wire Interface). This driver provides access to the main + * features of the TWIHS controller. + * The TWIHS interconnects components on a unique two-wire bus. + * The TWIHS is programmable as a master or a slave with sequential or single-byte access. + * Multiple master capability is supported. + * The High Speed of 3.4Mbits per second can be achieved in slave mode only. + * + * \par Usage + * + * -# Enable the TWIHS peripheral clock in the PMC. + * -# Enable the required TWIHS PIOs (see pio.h). + * -# Enable TWIHS master mode by calling twihs_enable_master_mode if it is a master on the I2C bus. + * -# Configure the TWIHS in master mode by calling twihs_master_init. + * -# Send data to a slave device on the I2C bus by calling twihs_master_write. + * -# Receive data from a slave device on the I2C bus by calling the twihs_master_read. + * -# Enable TWIHS slave mode by calling twihs_enable_slave_mode if it is a slave on the I2C bus. + * -# Configure the TWIHS in slave mode by calling twihs_slave_init. + * + * @{ + */ + +/* Low level time limit of I2C Fast Mode. */ +#define LOW_LEVEL_TIME_LIMIT 384000 +#define I2C_FAST_MODE_SPEED 400000 +#define TWIHS_CLK_DIVIDER 2 +#define TWIHS_CLK_CALC_ARGU 3 +#define TWIHS_CLK_DIV_MAX 0xFF +#define TWIHS_CLK_DIV_MIN 7 + +/** + * \brief Enable TWIHS master mode. + * + * \param p_twihs Pointer to a TWIHS instance. + */ +void twihs_enable_master_mode(Twihs *p_twihs) +{ + /* Set Master Disable bit and Slave Disable bit */ + p_twihs->TWIHS_CR = TWIHS_CR_MSDIS; + p_twihs->TWIHS_CR = TWIHS_CR_SVDIS; + + /* Set Master Enable bit */ + p_twihs->TWIHS_CR = TWIHS_CR_MSEN; +} + +/** + * \brief Disable TWIHS master mode. + * + * \param p_twihs Pointer to a TWIHS instance. + */ +void twihs_disable_master_mode(Twihs *p_twihs) +{ + /* Set Master Disable bit */ + p_twihs->TWIHS_CR = TWIHS_CR_MSDIS; +} + +/** + * \brief Initialize TWIHS master mode. + * + * \param p_twihs Pointer to a TWIHS instance. + * \param p_opt Options for initializing the TWIHS module (see \ref twihs_options_t). + * + * \return TWIHS_SUCCESS if initialization is complete, error code otherwise. + */ +uint32_t twihs_master_init(Twihs *p_twihs, const twihs_options_t *p_opt) +{ + uint32_t status = TWIHS_SUCCESS; + + /* Disable TWIHS interrupts */ + p_twihs->TWIHS_IDR = ~0UL; + + /* Dummy read in status register */ + p_twihs->TWIHS_SR; + + /* Reset TWIHS peripheral */ + twihs_reset(p_twihs); + + twihs_enable_master_mode(p_twihs); + + /* Select the speed */ + if (twihs_set_speed(p_twihs, p_opt->speed, p_opt->master_clk) == FAIL) { + /* The desired speed setting is rejected */ + status = TWIHS_INVALID_ARGUMENT; + } + + return status; +} + +/** + * \brief Set the I2C bus speed in conjunction with the clock frequency. + * + * \param p_twihs Pointer to a TWIHS instance. + * \param ul_speed The desired I2C bus speed (in Hz). + * \param ul_mck Main clock of the device (in Hz). + * + * \retval PASS New speed setting is accepted. + * \retval FAIL New speed setting is rejected. + */ +uint32_t twihs_set_speed(Twihs *p_twihs, uint32_t ul_speed, uint32_t ul_mck) +{ + uint32_t ckdiv = 0; + uint32_t c_lh_div; + uint32_t cldiv, chdiv; + + /* High-Speed can be only used in slave mode, 400k is the max speed allowed for master */ + if (ul_speed > I2C_FAST_MODE_SPEED) { + return FAIL; + } + + /* Low level time not less than 1.3us of I2C Fast Mode. */ + if (ul_speed > LOW_LEVEL_TIME_LIMIT) { + /* Low level of time fixed for 1.3us. */ + cldiv = ul_mck / (LOW_LEVEL_TIME_LIMIT * TWIHS_CLK_DIVIDER) - TWIHS_CLK_CALC_ARGU; + chdiv = ul_mck / ((ul_speed + (ul_speed - LOW_LEVEL_TIME_LIMIT)) * TWIHS_CLK_DIVIDER) - TWIHS_CLK_CALC_ARGU; + + /* cldiv must fit in 8 bits, ckdiv must fit in 3 bits */ + while ((cldiv > TWIHS_CLK_DIV_MAX) && (ckdiv < TWIHS_CLK_DIV_MIN)) { + /* Increase clock divider */ + ckdiv++; + /* Divide cldiv value */ + cldiv /= TWIHS_CLK_DIVIDER; + } + /* chdiv must fit in 8 bits, ckdiv must fit in 3 bits */ + while ((chdiv > TWIHS_CLK_DIV_MAX) && (ckdiv < TWIHS_CLK_DIV_MIN)) { + /* Increase clock divider */ + ckdiv++; + /* Divide cldiv value */ + chdiv /= TWIHS_CLK_DIVIDER; + } + + /* set clock waveform generator register */ + p_twihs->TWIHS_CWGR = + TWIHS_CWGR_CLDIV(cldiv) | TWIHS_CWGR_CHDIV(chdiv) | + TWIHS_CWGR_CKDIV(ckdiv); + } else { + c_lh_div = ul_mck / (ul_speed * TWIHS_CLK_DIVIDER) - TWIHS_CLK_CALC_ARGU; + + /* cldiv must fit in 8 bits, ckdiv must fit in 3 bits */ + while ((c_lh_div > TWIHS_CLK_DIV_MAX) && (ckdiv < TWIHS_CLK_DIV_MIN)) { + /* Increase clock divider */ + ckdiv++; + /* Divide cldiv value */ + c_lh_div /= TWIHS_CLK_DIVIDER; + } + + /* set clock waveform generator register */ + p_twihs->TWIHS_CWGR = + TWIHS_CWGR_CLDIV(c_lh_div) | TWIHS_CWGR_CHDIV(c_lh_div) | + TWIHS_CWGR_CKDIV(ckdiv); + } + + return PASS; +} + +/** + * \brief Test if a chip answers a given I2C address. + * + * \param p_twihs Pointer to a TWIHS instance. + * \param uc_slave_addr Address of the remote chip to search for. + * + * \return TWIHS_SUCCESS if a chip was found, error code otherwise. + */ +uint32_t twihs_probe(Twihs *p_twihs, uint8_t uc_slave_addr) +{ + twihs_packet_t packet; + uint8_t data = 0; + + /* Data to send */ + packet.buffer = &data; + /* Data length */ + packet.length = 1; + /* Slave chip address */ + packet.chip = (uint32_t) uc_slave_addr; + /* Internal chip address */ + packet.addr[0] = 0; + /* Address length */ + packet.addr_length = 0; + + /* Perform a master write access */ + return (twihs_master_write(p_twihs, &packet)); +} + + +/** + * \internal + * \brief Construct the TWIHS module address register field + * + * The TWIHS module address register is sent out MSB first. And the size controls + * which byte is the MSB to start with. + * + * Please see the device datasheet for details on this. + */ +static uint32_t twihs_mk_addr(const uint8_t *addr, int len) +{ + uint32_t val; + + if (len == 0) + return 0; + + val = addr[0]; + if (len > 1) { + val <<= 8; + val |= addr[1]; + } + if (len > 2) { + val <<= 8; + val |= addr[2]; + } + return val; +} + +/** + * \brief Read multiple bytes from a TWIHS compatible slave device. + * + * \note This function will NOT return until all data has been read or error occurs. + * + * \param p_twihs Pointer to a TWIHS instance. + * \param p_packet Packet information and data (see \ref twihs_packet_t). + * + * \return TWIHS_SUCCESS if all bytes were read, error code otherwise. + */ +uint32_t twihs_master_read(Twihs *p_twihs, twihs_packet_t *p_packet) +{ + uint32_t status, cnt = p_packet->length; + uint8_t *buffer = p_packet->buffer; + uint32_t timeout = TWIHS_TIMEOUT; + + /* Check argument */ + if (cnt == 0) { + return TWIHS_INVALID_ARGUMENT; + } + + /* Set read mode, slave address and 3 internal address byte lengths */ + p_twihs->TWIHS_MMR = 0; + p_twihs->TWIHS_MMR = TWIHS_MMR_MREAD | TWIHS_MMR_DADR(p_packet->chip) | + ((p_packet->addr_length << TWIHS_MMR_IADRSZ_Pos) & + TWIHS_MMR_IADRSZ_Msk); + + /* Set internal address for remote chip */ + p_twihs->TWIHS_IADR = 0; + p_twihs->TWIHS_IADR = twihs_mk_addr(p_packet->addr, p_packet->addr_length); + + /* Send a START Condition */ + p_twihs->TWIHS_CR = TWIHS_CR_START; + + while (cnt > 0) { + status = p_twihs->TWIHS_SR; + if (status & TWIHS_SR_NACK) { + return TWIHS_RECEIVE_NACK; + } + if (!timeout--) { + return TWIHS_ERROR_TIMEOUT; + } + /* Last byte ? */ + if (cnt == 1) { + p_twihs->TWIHS_CR = TWIHS_CR_STOP; + } + + if (!(status & TWIHS_SR_RXRDY)) { + continue; + } + *buffer++ = p_twihs->TWIHS_RHR; + + cnt--; + timeout = TWIHS_TIMEOUT; + } + + while (!(p_twihs->TWIHS_SR & TWIHS_SR_TXCOMP)) { + } + + p_twihs->TWIHS_SR; + + return TWIHS_SUCCESS; +} + +/** + * \brief Write multiple bytes to a TWIHS compatible slave device. + * + * \note This function will NOT return until all data has been written or error occurred. + * + * \param p_twihs Pointer to a TWIHS instance. + * \param p_packet Packet information and data (see \ref twihs_packet_t). + * + * \return TWIHS_SUCCESS if all bytes were written, error code otherwise. + */ +uint32_t twihs_master_write(Twihs *p_twihs, twihs_packet_t *p_packet) +{ + uint32_t status, cnt = p_packet->length; + uint8_t *buffer = p_packet->buffer; + + /* Check argument */ + if (cnt == 0) { + return TWIHS_INVALID_ARGUMENT; + } + + /* Set write mode, slave address and 3 internal address byte lengths */ + p_twihs->TWIHS_MMR = 0; + p_twihs->TWIHS_MMR = TWIHS_MMR_DADR(p_packet->chip) | + ((p_packet->addr_length << TWIHS_MMR_IADRSZ_Pos) & + TWIHS_MMR_IADRSZ_Msk); + + /* Set internal address for remote chip */ + p_twihs->TWIHS_IADR = 0; + p_twihs->TWIHS_IADR = twihs_mk_addr(p_packet->addr, p_packet->addr_length); + + /* Send all bytes */ + while (cnt > 0) { + status = p_twihs->TWIHS_SR; + if (status & TWIHS_SR_NACK) { + return TWIHS_RECEIVE_NACK; + } + + if (!(status & TWIHS_SR_TXRDY)) { + continue; + } + p_twihs->TWIHS_THR = *buffer++; + + cnt--; + } + + while (1) { + status = p_twihs->TWIHS_SR; + if (status & TWIHS_SR_NACK) { + return TWIHS_RECEIVE_NACK; + } + + if (status & TWIHS_SR_TXRDY) { + break; + } + } + + p_twihs->TWIHS_CR = TWIHS_CR_STOP; + + while (!(p_twihs->TWIHS_SR & TWIHS_SR_TXCOMP)) { + } + + return TWIHS_SUCCESS; +} + +/** + * \brief Enable TWIHS interrupts. + * + * \param p_twihs Pointer to a TWIHS instance. + * \param ul_sources Interrupts to be enabled. + */ +void twihs_enable_interrupt(Twihs *p_twihs, uint32_t ul_sources) +{ + /* Enable the specified interrupts */ + p_twihs->TWIHS_IER = ul_sources; +} + +/** + * \brief Disable TWIHS interrupts. + * + * \param p_twihs Pointer to a TWIHS instance. + * \param ul_sources Interrupts to be disabled. + */ +void twihs_disable_interrupt(Twihs *p_twihs, uint32_t ul_sources) +{ + /* Disable the specified interrupts */ + p_twihs->TWIHS_IDR = ul_sources; + /* Dummy read */ + p_twihs->TWIHS_SR; +} + +/** + * \brief Get TWIHS interrupt status. + * + * \param p_twihs Pointer to a TWIHS instance. + * + * \retval TWIHS interrupt status. + */ +uint32_t twihs_get_interrupt_status(Twihs *p_twihs) +{ + return p_twihs->TWIHS_SR; +} + +/** + * \brief Read TWIHS interrupt mask. + * + * \param p_twihs Pointer to a TWIHS instance. + * + * \return The interrupt mask value. + */ +uint32_t twihs_get_interrupt_mask(Twihs *p_twihs) +{ + return p_twihs->TWIHS_IMR; +} + +/** + * \brief Reads a byte from the TWIHS bus. + * + * \param p_twihs Pointer to a TWIHS instance. + * + * \return The byte read. + */ +uint8_t twihs_read_byte(Twihs *p_twihs) +{ + return p_twihs->TWIHS_RHR; +} + +/** + * \brief Sends a byte of data to one of the TWIHS slaves on the bus. + * + * \param p_twihs Pointer to a TWIHS instance. + * \param byte The byte to send. + */ +void twihs_write_byte(Twihs *p_twihs, uint8_t uc_byte) +{ + p_twihs->TWIHS_THR = uc_byte; +} + +/** + * \brief Enable TWIHS slave mode. + * + * \param p_twihs Pointer to a TWIHS instance. + */ +void twihs_enable_slave_mode(Twihs *p_twihs) +{ + /* Set Master Disable bit and Slave Disable bit */ + p_twihs->TWIHS_CR = TWIHS_CR_MSDIS; + p_twihs->TWIHS_CR = TWIHS_CR_SVDIS; + + /* Set Slave Enable bit */ + p_twihs->TWIHS_CR = TWIHS_CR_SVEN; +} + +/** + * \brief Disable TWIHS slave mode. + * + * \param p_twihs Pointer to a TWIHS instance. + */ +void twihs_disable_slave_mode(Twihs *p_twihs) +{ + /* Set Slave Disable bit */ + p_twihs->TWIHS_CR = TWIHS_CR_SVDIS; +} + +/** + * \brief Initialize TWIHS slave mode. + * + * \param p_twihs Pointer to a TWIHS instance. + * \param ul_device_addr Device address of the SAM slave device on the I2C bus. + */ +void twihs_slave_init(Twihs *p_twihs, uint32_t ul_device_addr) +{ + /* Disable TWIHS interrupts */ + p_twihs->TWIHS_IDR = ~0UL; + p_twihs->TWIHS_SR; + + /* Reset TWIHS */ + twihs_reset(p_twihs); + + /* Set slave address in slave mode */ + p_twihs->TWIHS_SMR = TWIHS_SMR_SADR(ul_device_addr); + + /* Enable slave mode */ + twihs_enable_slave_mode(p_twihs); +} + +/** + * \brief Set TWIHS slave address. + * + * \param p_twihs Pointer to a TWIHS instance. + * \param ul_device_addr Device address of the SAM slave device on the I2C bus. + */ +void twihs_set_slave_addr(Twihs *p_twihs, uint32_t ul_device_addr) +{ + /* Set slave address */ + p_twihs->TWIHS_SMR = TWIHS_SMR_SADR(ul_device_addr); +} + +/** + * \brief Read data from master. + * + * \note This function will NOT return until master sends a STOP condition. + * + * \param p_twihs Pointer to a TWIHS instance. + * \param p_data Pointer to the data buffer where data received will be stored. + * + * \return Number of bytes read. + */ +uint32_t twihs_slave_read(Twihs *p_twihs, uint8_t *p_data) +{ + uint32_t status, cnt = 0; + + do { + status = p_twihs->TWIHS_SR; + if (status & TWIHS_SR_SVACC) { + if (!(status & (TWIHS_SR_GACC | TWIHS_SR_SVREAD)) && + (status & TWIHS_SR_RXRDY)) { + *p_data++ = (uint8_t) p_twihs->TWIHS_RHR; + cnt++; + } + } else if ((status & (TWIHS_SR_EOSACC | TWIHS_SR_TXCOMP)) + == (TWIHS_SR_EOSACC | TWIHS_SR_TXCOMP)) { + break; + } + } while (1); + + return cnt; +} + +/** + * \brief Write data to TWIHS bus. + * + * \note This function will NOT return until master sends a STOP condition. + * + * \param p_twihs Pointer to a TWIHS instance. + * \param p_data Pointer to the data buffer to be sent. + * + * \return Number of bytes written. + */ +uint32_t twihs_slave_write(Twihs *p_twihs, uint8_t *p_data) +{ + uint32_t status, cnt = 0; + + do { + status = p_twihs->TWIHS_SR; + if (status & TWIHS_SR_SVACC) { + if (!(status & (TWIHS_SR_GACC | TWIHS_SR_NACK)) && + ((status & (TWIHS_SR_SVREAD | TWIHS_SR_TXRDY)) + == (TWIHS_SR_SVREAD | TWIHS_SR_TXRDY))) { + p_twihs->TWIHS_THR = *p_data++; + cnt++; + } + } else if ((status & (TWIHS_SR_EOSACC | TWIHS_SR_TXCOMP)) + == (TWIHS_SR_EOSACC | TWIHS_SR_TXCOMP)) { + break; + } + } while (1); + + return cnt; +} + +/** + * \brief Reset TWIHS. + * + * \param p_twihs Pointer to a TWIHS instance. + */ +void twihs_reset(Twihs *p_twihs) +{ + /* Set SWRST bit to reset TWIHS peripheral */ + p_twihs->TWIHS_CR = TWIHS_CR_SWRST; + p_twihs->TWIHS_RHR; +} + +#if !(SAMV70 || SAMV71 || SAME70 || SAMS70) +/** + * \brief Get TWIHS PDC base address. + * + * \param p_twihs Pointer to a TWIHS instance. + * + * \return TWIHS PDC registers base for PDC driver to access. + */ +Pdc *twihs_get_pdc_base(Twihs *p_twihs) +{ + Pdc *p_pdc_base = NULL; + + if (p_twihs == TWI0) { + p_pdc_base = PDC_TWI0; + } else { + Assert(false); + } + + return p_pdc_base; +} +#endif + +/** + * \brief Enables/Disables write protection mode. + * + * \param p_twihs Pointer to a TWIHS instance. + * \param flag ture for enable, false for disable. + */ +void twihs_set_write_protection(Twihs *p_twihs, bool flag) +{ + if (flag) { + p_twihs->TWIHS_WPMR = TWIHS_WPMR_WPKEY_PASSWD | TWIHS_WPMR_WPEN; + } else { + p_twihs->TWIHS_WPMR = TWIHS_WPMR_WPKEY_PASSWD; + } +} + +/** + * \brief Read the write protection status. + * + * \param p_twihs Pointer to a TWIHS instance. + * \param p_status Pointer to save the status. + */ +void twihs_read_write_protection_status(Twihs *p_twihs, uint32_t *p_status) +{ + *p_status = p_twihs->TWIHS_WPSR; +} + +/** + * \brief Set the prescaler, TLOW:SEXT, TLOW:MEXT and clock high max cycles for SMBUS mode. + * + * \param p_twihs Base address of the TWIHS instance. + * \param ul_timing Parameter for prescaler, TLOW:SEXT, TLOW:MEXT and clock high max cycles. + */ +void twihs_smbus_set_timing(Twihs *p_twihs, uint32_t ul_timing) +{ + p_twihs->TWIHS_SMBTR = ul_timing;; +} + +#if !(SAMV70 || SAMV71 || SAME70 || SAMS70) +/** + * \brief Set length/direction/PEC for alternative command mode. + * + * \param p_twihs Base address of the TWIHS instance. + * \param ul_alt_cmd Alternative command parameters. + */ +void twihs_set_alternative_command(Twihs *p_twihs, uint32_t ul_alt_cmd) +{ + p_twihs->TWIHS_ACR = ul_alt_cmd;; +} +#endif + +/** + * \brief Set the filter for TWIHS. + * + * \param p_twihs Base address of the TWIHS instance. + * \param ul_filter Filter value. + */ +void twihs_set_filter(Twihs *p_twihs, uint32_t ul_filter) +{ + p_twihs->TWIHS_FILTR = ul_filter;; +} + +/** + * \brief A mask can be applied on the slave device address in slave mode in order to allow multiple + * address answer. For each bit of the MASK field set to one the corresponding SADR bit will be masked. + * + * \param p_twihs Base address of the TWIHS instance. + * \param ul_mask Mask value. + */ +void twihs_mask_slave_addr(Twihs *p_twihs, uint32_t ul_mask) +{ + p_twihs->TWIHS_SMR |= TWIHS_SMR_MASK(ul_mask); +} + +#if (SAMG53 || SAMG54 || SAMV70 || SAMV71 || SAME70 || SAMS70) +/** + * \brief Set sleepwalking match mode. + * + * \param p_twihs Pointer to a TWIHS instance. + * \param ul_matching_addr1 Address 1 value. + * \param ul_matching_addr2 Address 2 value. + * \param ul_matching_addr3 Address 3 value. + * \param ul_matching_data Data value. + * \param flag1 ture for set, false for no. + * \param flag2 ture for set, false for no. + * \param flag3 ture for set, false for no. + * \param flag ture for set, false for no. + */ +void twihs_set_sleepwalking(Twihs *p_twihs, + uint32_t ul_matching_addr1, bool flag1, + uint32_t ul_matching_addr2, bool flag2, + uint32_t ul_matching_addr3, bool flag3, + uint32_t ul_matching_data, bool flag) +{ + uint32_t temp = 0; + + if (flag1) { + temp |= TWIHS_SWMR_SADR1(ul_matching_addr1); + } + + if (flag2) { + temp |= TWIHS_SWMR_SADR2(ul_matching_addr2); + } + + if (flag3) { + temp |= TWIHS_SWMR_SADR3(ul_matching_addr3); + } + + if (flag) { + temp |= TWIHS_SWMR_DATAM(ul_matching_data); + } + + p_twihs->TWIHS_SWMR = temp; +} +#endif +//@} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/twihs/twihs.h b/hw-libs/drivers/SAMx70/ASF/sam/drivers/twihs/twihs.h new file mode 100644 index 000000000..6e6d282b5 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/twihs/twihs.h @@ -0,0 +1,422 @@ +/** + * \file + * + * \brief Two-Wire Interface High Speed (TWIHS) driver for SAM. + * + * Copyright (c) 2013-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef TWIHS_H_INCLUDED +#define TWIHS_H_INCLUDED + +#include "compiler.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** Time-out value (number of attempts). */ +#define TWIHS_TIMEOUT 30000 + +/** + * \brief Return codes for TWIHS APIs. + * @{ + */ +#define TWIHS_SUCCESS 0 +#define TWIHS_INVALID_ARGUMENT 1 +#define TWIHS_ARBITRATION_LOST 2 +#define TWIHS_NO_CHIP_FOUND 3 +#define TWIHS_RECEIVE_OVERRUN 4 +#define TWIHS_RECEIVE_NACK 5 +#define TWIHS_SEND_OVERRUN 6 +#define TWIHS_SEND_NACK 7 +#define TWIHS_BUSY 8 +#define TWIHS_ERROR_TIMEOUT 9 +/** + * @} + */ + +/** + * \brief Input parameters when initializing the TWIHS module mode. + */ +typedef struct twihs_options { + //! MCK for TWIHS. + uint32_t master_clk; + //! The baud rate of the TWIHS bus. + uint32_t speed; + //! The desired address. + uint8_t chip; + //! SMBUS mode (set 1 to use SMBUS quick command, otherwise don't). + uint8_t smbus; +} twihs_options_t; + +/** + * \brief Information concerning the data transmission. + */ +typedef struct twihs_packet { + //! TWIHS address/commands to issue to the other chip (node). + uint8_t addr[3]; + //! Length of the TWIHS data address segment (1-3 bytes). + uint32_t addr_length; + //! Where to find the data to be transferred. + void *buffer; + //! How many bytes do we want to transfer. + uint32_t length; + //! TWIHS chip address to communicate with. + uint8_t chip; +} twihs_packet_t; + +/** + * \brief If Master mode is enabled, a SMBUS Quick Command is sent. + * + * \param p_twihs Base address of the TWIHS instance. + */ +static inline void twihs_enable_smbus_quick_command(Twihs *p_twihs) +{ + p_twihs->TWIHS_CR = TWIHS_CR_QUICK; +} + +/** + * \brief Enable high speed mode. + * + * \param p_twihs Base address of the TWIHS instance. + */ +static inline void twihs_enable_highspeed(Twihs *p_twihs) +{ + p_twihs->TWIHS_CR = TWIHS_CR_HSEN; +} + +/** + * \brief Disable high speed mode. + * + * \param p_twihs Base address of the TWIHS instance. + */ +static inline void twihs_disable_highspeed(Twihs *p_twihs) +{ + p_twihs->TWIHS_CR = TWIHS_CR_HSDIS; +} + +/** + * \brief Enable SMBus mode. + * + * \param p_twihs Base address of the TWIHS instance. + */ +static inline void twihs_enable_smbus(Twihs *p_twihs) +{ + p_twihs->TWIHS_CR = TWIHS_CR_SMBEN; +} + +/** + * \brief Disable SMBus mode. + * + * \param p_twihs Base address of the TWIHS instance. + */ +static inline void twihs_disable_smbus(Twihs *p_twihs) +{ + p_twihs->TWIHS_CR = TWIHS_CR_SMBDIS; +} + +/** + * \brief Enable packet error checking. + * + * \param p_twihs Base address of the TWIHS instance. + */ +static inline void twihs_enable_pec(Twihs *p_twihs) +{ + p_twihs->TWIHS_CR = TWIHS_CR_PECEN; +} + +/** + * \brief Disable packet error checking. + * + * \param p_twihs Base address of the TWIHS instance. + */ +static inline void twihs_disable_pec(Twihs *p_twihs) +{ + p_twihs->TWIHS_CR = TWIHS_CR_PECDIS; +} + +/** + * \brief Request a packet error checking. + * + * \param p_twihs Base address of the TWIHS instance. + */ +static inline void twihs_request_pec(Twihs *p_twihs) +{ + p_twihs->TWIHS_CR = TWIHS_CR_PECRQ; +} + +/** + * \brief If master mode is enabled, send a bus clear command. + * + * \param p_twihs Base address of the TWIHS instance. + */ +static inline void twihs_send_clear(Twihs *p_twihs) +{ + p_twihs->TWIHS_CR = TWIHS_CR_CLEAR; +} + +#if !(SAMV70 || SAMV71 || SAME70 || SAMS70) +/** + * \brief Enable alternative command mode. + * + * \param p_twihs Base address of the TWIHS instance. + */ +static inline void twihs_enable_alternative_command(Twihs *p_twihs) +{ + p_twihs->TWIHS_CR = TWIHS_CR_ACMEN; +} + +/** + * \brief Enable alternative command mode. + * + * \param p_twihs Base address of the TWIHS instance. + */ +static inline void twihs_disable_alternative_command(Twihs *p_twihs) +{ + p_twihs->TWIHS_CR = TWIHS_CR_ACMDIS; +} +#endif + +/** + * \brief Normal value to be returned in the ACK cycle of the data phase in slave receiver mode. + * + * \param p_twihs Base address of the TWIHS instance. + */ +static inline void twihs_disable_slave_nack(Twihs *p_twihs) +{ + p_twihs->TWIHS_SMR &= ~TWIHS_SMR_NACKEN; +} + +/** + * \brief NACK value to be returned in the ACK cycle of the data phase in slave receiver mode. + * + * \param p_twihs Base address of the TWIHS instance. + */ +static inline void twihs_enable_slave_nack(Twihs *p_twihs) +{ + p_twihs->TWIHS_SMR |= TWIHS_SMR_NACKEN; +} + +/** + * \brief Acknowledge of the SMBus Default Address disabled. + * + * \param p_twihs Base address of the TWIHS instance. + */ +static inline void twihs_disable_slave_default_addr(Twihs *p_twihs) +{ + p_twihs->TWIHS_SMR &= ~TWIHS_SMR_SMDA; +} + +/** + * \brief Acknowledge of the SMBus Default Address enabled. + * + * \param p_twihs Base address of the TWIHS instance. + */ +static inline void twihs_enable_slave_default_addr(Twihs *p_twihs) +{ + p_twihs->TWIHS_SMR |= TWIHS_SMR_SMDA; +} + +/** + * \brief Acknowledge of the SMBus Host Header disabled. + * + * \param p_twihs Base address of the TWIHS instance. + */ +static inline void twihs_disable_smbus_host_header(Twihs *p_twihs) +{ + p_twihs->TWIHS_SMR &= ~TWIHS_SMR_SMHH; +} + +/** + * \brief Acknowledge of the SMBus Host Header enabled. + * + * \param p_twihs Base address of the TWIHS instance. + */ +static inline void twihs_enable_smbus_host_header(Twihs *p_twihs) +{ + p_twihs->TWIHS_SMR |= TWIHS_SMR_SMHH; +} + +/** + * \brief Clock stretching disabled in slave mode, OVRE and UNRE will indicate overrun and underrun. + * + * \param p_twihs Base address of the TWIHS instance. + */ +static inline void twihs_disable_clock_wait_state(Twihs *p_twihs) +{ + p_twihs->TWIHS_SMR |= TWIHS_SMR_SCLWSDIS; +} + +/** + * \brief Clear clock wait state disable mode. + * + * \param p_twihs Base address of the TWIHS instance. + */ +static inline void twihs_clear_disable_clock_wait_state(Twihs *p_twihs) +{ + p_twihs->TWIHS_SMR &= ~TWIHS_SMR_SCLWSDIS; +} + +#if (SAMG53 || SAMG54 || SAMV70 || SAMV71 || SAME70 || SAMS70) +/** + * \brief Slave Address 1 matching disabled. + * + * \param p_twihs Base address of the TWIHS instance. + */ +static inline void twihs_disable_slave_addr1_matching(Twihs *p_twihs) +{ + p_twihs->TWIHS_SMR &= ~TWIHS_SMR_SADR1EN; +} + +/** + * \brief Slave Address 1 matching enabled. + * + * \param p_twihs Base address of the TWIHS instance. + */ +static inline void twihs_enable_slave_addr1_matching(Twihs *p_twihs) +{ + p_twihs->TWIHS_SMR |= TWIHS_SMR_SADR1EN; +} + +/** + * \brief Slave Address 2 matching disabled. + * + * \param p_twihs Base address of the TWIHS instance. + */ +static inline void twihs_disable_slave_addr2_matching(Twihs *p_twihs) +{ + p_twihs->TWIHS_SMR &= ~TWIHS_SMR_SADR2EN; +} + +/** + * \brief Slave Address 2 matching enabled. + * + * \param p_twihs Base address of the TWIHS instance. + */ +static inline void twihs_enable_slave_addr2_matching(Twihs *p_twihs) +{ + p_twihs->TWIHS_SMR |= TWIHS_SMR_SADR2EN; +} + +/** + * \brief Slave Address 3 matching disabled. + * + * \param p_twihs Base address of the TWIHS instance. + */ +static inline void twihs_disable_slave_addr3_matching(Twihs *p_twihs) +{ + p_twihs->TWIHS_SMR &= ~TWIHS_SMR_SADR3EN; +} + +/** + * \brief Slave Address 3 matching enabled. + * + * \param p_twihs Base address of the TWIHS instance. + */ +static inline void twihs_enable_slave_addr3_matching(Twihs *p_twihs) +{ + p_twihs->TWIHS_SMR |= TWIHS_SMR_SADR3EN; +} + +/** + * \brief First received data matching disabled. + * + * \param p_twihs Base address of the TWIHS instance. + */ +static inline void twihs_disable_slave_data_matching(Twihs *p_twihs) +{ + p_twihs->TWIHS_SMR &= ~TWIHS_SMR_DATAMEN; +} + +/** + * \brief First received data matching enabled. + * + * \param p_twihs Base address of the TWIHS instance. + */ +static inline void twihs_enable_slave_data_matching(Twihs *p_twihs) +{ + p_twihs->TWIHS_SMR |= TWIHS_SMR_DATAMEN; +} + +void twihs_set_sleepwalking(Twihs *p_twihs, + uint32_t ul_matching_addr1, bool flag1, + uint32_t ul_matching_addr2, bool flag2, + uint32_t ul_matching_addr3, bool flag3, + uint32_t ul_matching_data, bool flag); +#endif + +void twihs_enable_master_mode(Twihs *p_twihs); +void twihs_disable_master_mode(Twihs *p_twihs); +uint32_t twihs_master_init(Twihs *p_twihs, const twihs_options_t *p_opt); +uint32_t twihs_set_speed(Twihs *p_twihs, uint32_t ul_speed, uint32_t ul_mck); +uint32_t twihs_probe(Twihs *p_twihs, uint8_t uc_slave_addr); +uint32_t twihs_master_read(Twihs *p_twihs, twihs_packet_t *p_packet); +uint32_t twihs_master_write(Twihs *p_twihs, twihs_packet_t *p_packet); +void twihs_enable_interrupt(Twihs *p_twihs, uint32_t ul_sources); +void twihs_disable_interrupt(Twihs *p_twihs, uint32_t ul_sources); +uint32_t twihs_get_interrupt_status(Twihs *p_twihs); +uint32_t twihs_get_interrupt_mask(Twihs *p_twihs); +uint8_t twihs_read_byte(Twihs *p_twihs); +void twihs_write_byte(Twihs *p_twihs, uint8_t uc_byte); +void twihs_enable_slave_mode(Twihs *p_twihs); +void twihs_disable_slave_mode(Twihs *p_twihs); +void twihs_slave_init(Twihs *p_twihs, uint32_t ul_device_addr); +void twihs_set_slave_addr(Twihs *p_twihs, uint32_t ul_device_addr); +uint32_t twihs_slave_read(Twihs *p_twihs, uint8_t *p_data); +uint32_t twihs_slave_write(Twihs *p_twihs, uint8_t *p_data); +void twihs_reset(Twihs *p_twihs); +#if !(SAMV70 || SAMV71 || SAME70 || SAMS70) +Pdc *twihs_get_pdc_base(Twihs *p_twihs); +#endif +void twihs_set_write_protection(Twihs *p_twihs, bool flag); +void twihs_read_write_protection_status(Twihs *p_twihs, uint32_t *p_status); +void twihs_smbus_set_timing(Twihs *p_twihs, uint32_t ul_timing); +#if !(SAMV70 || SAMV71 || SAME70 || SAMS70) +void twihs_set_alternative_command(Twihs *p_twihs, uint32_t ul_alt_cmd); +#endif +void twihs_set_filter(Twihs *p_twihs, uint32_t ul_filter); +void twihs_mask_slave_addr(Twihs *p_twihs, uint32_t ul_mask); + + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +#endif /* TWIHS_H_INCLUDED */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/uart/uart.c b/hw-libs/drivers/SAMx70/ASF/sam/drivers/uart/uart.c new file mode 100644 index 000000000..02151004d --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/uart/uart.c @@ -0,0 +1,559 @@ +/** + * \file + * + * \brief Universal Asynchronous Receiver Transceiver (UART) driver for SAM. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "uart.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \defgroup sam_drivers_uart_group Universal Asynchronous Receiver Transceiver (UART) + * + * The Universal Asynchronous Receiver Transmitter features a two-pin UART that + * can be used for communication and trace purposes and offers an ideal medium + * for in-situ programming solutions. Moreover, the association with two + * peripheral DMA controller (PDC) channels permits packet handling for these + * tasks with processor time reduced to a minimum. + * + * \par Usage + * + * -# Enable the UART peripheral clock in the PMC. + * -# Enable the required UART PIOs (see pio.h). + * -# Configure the UART by calling uart_init. + * -# Send data through the UART using the uart_write. + * -# Receive data from the UART using the uart_read; the availability of data + * can be polled with uart_is_rx_ready. + * -# Disable the transmitter and/or the receiver of the UART with + * uart_disable_tx and uart_disable_rx. + * + * @{ + */ + +/** + * \brief Configure UART with the specified parameters. + * + * \note The PMC and PIOs must be configured first. + * + * \param p_uart Pointer to a UART instance. + * \param p_uart_opt Pointer to sam_uart_opt_t instance. + * + * \retval 0 Success. + * \retval 1 Bad baud rate generator value. + */ +uint32_t uart_init(Uart *p_uart, const sam_uart_opt_t *p_uart_opt) +{ + uint32_t clock_divisor = 0; + + /* Reset and disable receiver & transmitter */ + p_uart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX + | UART_CR_RXDIS | UART_CR_TXDIS; + + /* Check and configure baudrate */ + /* Asynchronous, no oversampling */ + clock_divisor = ((p_uart_opt->ul_mck / UART_MCK_DIV) + p_uart_opt->ul_baudrate/2) / p_uart_opt->ul_baudrate; // Round to closest baud rate + if (clock_divisor < UART_MCK_DIV_MIN_FACTOR || clock_divisor > UART_MCK_DIV_MAX_FACTOR) + return 1; + + /* Set baud rate */ + p_uart->UART_BRGR = clock_divisor; + /* Configure mode */ + p_uart->UART_MR = p_uart_opt->ul_mode; + +#if (!SAMV71 && !SAMV70 && !SAME70 && !SAMS70) + /* Disable PDC channel */ + p_uart->UART_PTCR = UART_PTCR_RXTDIS | UART_PTCR_TXTDIS; +#endif + + /* Enable receiver and transmitter */ + p_uart->UART_CR = UART_CR_RXEN | UART_CR_TXEN; + + return 0; +} + +uint32_t uart_baud_rate(Uart *p_uart, uint32_t ul_mck) +{ + uint32_t baud_rate = (ul_mck / UART_MCK_DIV) / p_uart->UART_BRGR; + return baud_rate; +} + +/** + * \brief Enable UART transmitter. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_enable_tx(Uart *p_uart) +{ + /* Enable transmitter */ + p_uart->UART_CR = UART_CR_TXEN; +} + +/** + * \brief Disable UART transmitter. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_disable_tx(Uart *p_uart) +{ + /* Disable transmitter */ + p_uart->UART_CR = UART_CR_TXDIS; +} + +/** + * \brief Reset UART transmitter. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_reset_tx(Uart *p_uart) +{ + /* Reset transmitter */ + p_uart->UART_CR = UART_CR_RSTTX | UART_CR_TXDIS; +} + +/** + * \brief Enable UART receiver. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_enable_rx(Uart *p_uart) +{ + /* Enable receiver */ + p_uart->UART_CR = UART_CR_RXEN; +} + +/** + * \brief Disable UART receiver. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_disable_rx(Uart *p_uart) +{ + /* Disable receiver */ + p_uart->UART_CR = UART_CR_RXDIS; +} + +/** + * \brief Reset UART receiver. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_reset_rx(Uart *p_uart) +{ + /* Reset receiver */ + p_uart->UART_CR = UART_CR_RSTRX | UART_CR_RXDIS; +} + +/** + * \brief Enable UART receiver and transmitter. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_enable(Uart *p_uart) +{ + /* Enable receiver and transmitter */ + p_uart->UART_CR = UART_CR_RXEN | UART_CR_TXEN; +} + +/** + * \brief Disable UART receiver and transmitter. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_disable(Uart *p_uart) +{ + /* Disable receiver and transmitter */ + p_uart->UART_CR = UART_CR_RXDIS | UART_CR_TXDIS; +} + +/** + * \brief Reset UART receiver and transmitter. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_reset(Uart *p_uart) +{ + /* Reset and disable receiver & transmitter */ + p_uart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX + | UART_CR_RXDIS | UART_CR_TXDIS; +} + +/** \brief Enable UART interrupts. + * + * \param p_uart Pointer to a UART instance. + * \param ul_sources Interrupts to be enabled. + */ +void uart_enable_interrupt(Uart *p_uart, uint32_t ul_sources) +{ + p_uart->UART_IER = ul_sources; +} + +/** \brief Disable UART interrupts. + * + * \param p_uart Pointer to a UART instance. + * \param ul_sources Interrupts to be disabled. + */ +void uart_disable_interrupt(Uart *p_uart, uint32_t ul_sources) +{ + p_uart->UART_IDR = ul_sources; +} + +/** \brief Read UART interrupt mask. + * + * \param p_uart Pointer to a UART instance. + * + * \return The interrupt mask value. + */ +uint32_t uart_get_interrupt_mask(Uart *p_uart) +{ + return p_uart->UART_IMR; +} + +/** + * \brief Get current status. + * + * \param p_uart Pointer to a UART instance. + * + * \return The current UART status. + */ +uint32_t uart_get_status(Uart *p_uart) +{ + return p_uart->UART_SR; +} + +/** + * \brief Reset status bits. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_reset_status(Uart *p_uart) +{ + p_uart->UART_CR = UART_CR_RSTSTA; +} + +/** + * \brief Check if Transmit is Ready. + * Check if data has been loaded in UART_THR and is waiting to be loaded in the + * Transmit Shift Register (TSR). + * + * \param p_uart Pointer to a UART instance. + * + * \retval 1 Data has been transmitted. + * \retval 0 Transmit is not ready, data pending. + */ +uint32_t uart_is_tx_ready(Uart *p_uart) +{ + return (p_uart->UART_SR & UART_SR_TXRDY) > 0; +} + +/** + * \brief Check if Transmit Hold Register is empty. + * Check if the last data written in UART_THR has been loaded in TSR and the + * last data loaded in TSR has been transmitted. + * + * \param p_uart Pointer to a UART instance. + * + * \retval 1 Transmitter is empty. + * \retval 0 Transmitter is not empty. + */ +uint32_t uart_is_tx_empty(Uart *p_uart) +{ + return (p_uart->UART_SR & UART_SR_TXEMPTY) > 0; +} + +/** + * \brief Check if Received data is ready. + * Check if data has been received and loaded in UART_RHR. + * + * \param p_uart Pointer to a UART instance. + * + * \retval 1 One data has been received. + * \retval 0 No data has been received. + */ +uint32_t uart_is_rx_ready(Uart *p_uart) +{ + return (p_uart->UART_SR & UART_SR_RXRDY) > 0; +} + +/** + * \brief Check if both transmit buffers are sent out. + * + * \param p_uart Pointer to a UART instance. + * + * \retval 1 Transmit buffer is empty. + * \retval 0 Transmit buffer is not empty. + */ +uint32_t uart_is_tx_buf_empty(Uart *p_uart) +{ + return (p_uart->UART_SR & UART_SR_TXEMPTY) > 0; +} + +/** + * \brief Set UART clock divisor value + * + * \param p_uart Pointer to a UART instance. + * \param us_divisor Value to be set. + * + */ +void uart_set_clock_divisor(Uart *p_uart, uint16_t us_divisor) +{ + p_uart->UART_BRGR = us_divisor; +} + +/** + * \brief Write to UART Transmit Holding Register + * Before writing user should check if tx is ready (or empty). + * + * \param p_uart Pointer to a UART instance. + * \param data Data to be sent. + * + * \retval 0 Success. + * \retval 1 I/O Failure, UART is not ready. + */ +uint32_t uart_write(Uart *p_uart, const uint8_t uc_data) +{ + /* Check if the transmitter is ready */ + if (!(p_uart->UART_SR & UART_SR_TXRDY)) + return 1; + + /* Send character */ + p_uart->UART_THR = uc_data; + return 0; +} + +/** + * \brief Read from UART Receive Holding Register. + * Before reading user should check if rx is ready. + * + * \param p_uart Pointer to a UART instance. + * + * \retval 0 Success. + * \retval 1 I/O Failure, UART is not ready. + */ +uint32_t uart_read(Uart *p_uart, uint8_t *puc_data) +{ + /* Check if the receiver is ready */ + if ((p_uart->UART_SR & UART_SR_RXRDY) == 0) + return 1; + + /* Read character */ + *puc_data = (uint8_t) p_uart->UART_RHR; + return 0; +} + +#if (!SAMV71 && !SAMV70 && !SAME70 && !SAMS70) +/** + * \brief Check if one receive buffer is filled. + * + * \param p_uart Pointer to a UART instance. + * + * \retval 1 Receive is completed. + * \retval 0 Receive is still pending. + */ +uint32_t uart_is_rx_buf_end(Uart *p_uart) +{ + return (p_uart->UART_SR & UART_SR_ENDRX) > 0; +} + +/** + * \brief Check if one transmit buffer is sent out. + * + * \param p_uart Pointer to a UART instance. + * + * \retval 1 Transmit is completed. + * \retval 0 Transmit is still pending. + */ +uint32_t uart_is_tx_buf_end(Uart *p_uart) +{ + return (p_uart->UART_SR & UART_SR_ENDTX) > 0; +} + +/** + * \brief Check if both receive buffers are full. + * + * \param p_uart Pointer to a UART instance. + * + * \retval 1 Receive buffers are full. + * \retval 0 Receive buffers are not full. + */ +uint32_t uart_is_rx_buf_full(Uart *p_uart) +{ + return (p_uart->UART_SR & UART_SR_RXBUFF) > 0; +} + +/** + * \brief Get UART PDC base address. + * + * \param p_uart Pointer to a UART instance. + * + * \return UART PDC registers base for PDC driver to access. + */ +Pdc *uart_get_pdc_base(Uart *p_uart) +{ + Pdc *p_pdc_base; + +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM) + if (p_uart == UART0) + p_pdc_base = PDC_UART0; +#elif (SAM3XA || SAM3U) + if (p_uart == UART) + p_pdc_base = PDC_UART; +#else +#error "Unsupported device" +#endif + +#if (SAM3S || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM) + if (p_uart == UART1) + p_pdc_base = PDC_UART1; +#endif + +#if (SAM4N) + if (p_uart == UART2) + p_pdc_base = PDC_UART2; +#endif + + return p_pdc_base; +} +#endif + +#if (SAM4C || SAM4CP || SAM4CM) +/** + * \brief Enable UART optical interface. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_enable_optical_interface(Uart *p_uart) +{ + Assert(p_uart == UART1); + p_uart->UART_MR |= UART_MR_OPT_EN; +} + +/** + * \brief Disable UART optical interface. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_disable_optical_interface(Uart *p_uart) +{ + Assert(p_uart == UART1); + p_uart->UART_MR &= ~UART_MR_OPT_EN; +} + +/** + * \brief Enable UART optical interface. + * + * \param p_uart Pointer to a UART instance. + * \param cfg Pointer to a UART optical interface configuration. + */ +void uart_config_optical_interface(Uart *p_uart, + struct uart_config_optical *cfg) +{ + Assert(p_uart == UART1); + uint32_t reg = p_uart->UART_MR; + + reg &= ~(UART_MR_OPT_RXINV | UART_MR_OPT_MDINV | UART_MR_FILTER + | UART_MR_OPT_CLKDIV_Msk | UART_MR_OPT_DUTY_Msk + | UART_MR_OPT_CMPTH_Msk); + reg |= (cfg->rx_inverted ? UART_MR_OPT_RXINV : 0) + | (cfg->tx_inverted ? UART_MR_OPT_MDINV : 0) + | (cfg->rx_filter ? UART_MR_FILTER : 0) + | UART_MR_OPT_CLKDIV(cfg->clk_div) + | cfg->duty | cfg->threshold; + + p_uart->UART_MR = reg; +} +#endif + +#if (SAMG53 || SAMG54 || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Set sleepwalking match mode. + * + * \param p_uart Pointer to a UART instance. + * \param ul_low_value First comparison value for received character. + * \param ul_high_value Second comparison value for received character. + * \param cmpmode ture for start condition, false for flag only. + * \param cmppar ture for parity check, false for no. + */ +void uart_set_sleepwalking(Uart *p_uart, uint8_t ul_low_value, + bool cmpmode, bool cmppar, uint8_t ul_high_value) +{ + Assert(ul_low_value <= ul_high_value); + + uint32_t temp = 0; + + if (cmpmode) { + temp |= UART_CMPR_CMPMODE_START_CONDITION; + } + + if (cmppar) { + temp |= UART_CMPR_CMPPAR; + } + + temp |= UART_CMPR_VAL1(ul_low_value); + + temp |= UART_CMPR_VAL2(ul_high_value); + + p_uart->UART_CMPR= temp; +} + +/** + * \brief Enables/Disables write protection mode. + * + * \param p_uart Pointer to a UART instance. + * \param flag ture for enable, false for disable. + */ +void uart_set_write_protection(Uart *p_uart, bool flag) +{ + if (flag) { + p_uart->UART_WPMR = UART_WPMR_WPKEY_PASSWD | UART_WPMR_WPEN; + } else { + p_uart->UART_WPMR = UART_WPMR_WPKEY_PASSWD; + } +} +#endif + +//@} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/uart/uart.h b/hw-libs/drivers/SAMx70/ASF/sam/drivers/uart/uart.h new file mode 100644 index 000000000..7ef1e3b7b --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/uart/uart.h @@ -0,0 +1,151 @@ +/** + * \file + * + * \brief Universal Asynchronous Receiver Transceiver (UART) driver for SAM. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef UART_H_INCLUDED +#define UART_H_INCLUDED + +#include "compiler.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/* UART internal div factor for sampling */ +#define UART_MCK_DIV 16 +/* Div factor to get the maximum baud rate */ +#define UART_MCK_DIV_MIN_FACTOR 1 +/* Div factor to get the minimum baud rate */ +#define UART_MCK_DIV_MAX_FACTOR 65535 + +/*! \brief Option list for UART peripheral initialization */ +typedef struct sam_uart_opt { + /** MCK for UART */ + uint32_t ul_mck; + /** Expected baud rate */ + uint32_t ul_baudrate; + /** Initialize value for UART mode register */ + uint32_t ul_mode; +} sam_uart_opt_t; + +uint32_t uart_init(Uart *p_uart, const sam_uart_opt_t *p_uart_opt); +uint32_t uart_baud_rate(Uart *p_uart, uint32_t ul_mck); +void uart_enable_tx(Uart *p_uart); +void uart_disable_tx(Uart *p_uart); +void uart_reset_tx(Uart *p_uart); +void uart_enable_rx(Uart *p_uart); +void uart_disable_rx(Uart *p_uart); +void uart_reset_rx(Uart *p_uart); +void uart_enable(Uart *p_uart); +void uart_disable(Uart *p_uart); +void uart_reset(Uart *p_uart); +void uart_enable_interrupt(Uart *p_uart, uint32_t ul_sources); +void uart_disable_interrupt(Uart *p_uart, uint32_t ul_sources); +uint32_t uart_get_interrupt_mask(Uart *p_uart); +uint32_t uart_get_status(Uart *p_uart); +void uart_reset_status(Uart *p_uart); +uint32_t uart_is_tx_ready(Uart *p_uart); +uint32_t uart_is_tx_empty(Uart *p_uart); +uint32_t uart_is_rx_ready(Uart *p_uart); +uint32_t uart_is_tx_buf_empty(Uart *p_uart); +void uart_set_clock_divisor(Uart *p_uart, uint16_t us_divisor); +uint32_t uart_write(Uart *p_uart, const uint8_t uc_data); +uint32_t uart_read(Uart *p_uart, uint8_t *puc_data); +#if (!SAMV71 && !SAMV70 && !SAME70 && !SAMS70) +uint32_t uart_is_rx_buf_end(Uart *p_uart); +uint32_t uart_is_tx_buf_end(Uart *p_uart); +uint32_t uart_is_rx_buf_full(Uart *p_uart); +Pdc *uart_get_pdc_base(Uart *p_uart); +#endif +#if (SAMG53 || SAMG54 || SAMV71 || SAMV70 || SAME70 || SAMS70) +void uart_set_sleepwalking(Uart *p_uart, uint8_t ul_low_value, + bool cmpmode, bool cmppar, uint8_t ul_high_value); +void uart_set_write_protection(Uart *p_uart, bool flag); +#endif + +#if (SAM4C || SAM4CP || SAM4CM) +enum uart_optical_duty_cycle { + UART_MOD_CLK_DUTY_50_00 = UART_MR_OPT_DUTY_DUTY_50, + UART_MOD_CLK_DUTY_43_75 = UART_MR_OPT_DUTY_DUTY_43P75, + UART_MOD_CLK_DUTY_37_50 = UART_MR_OPT_DUTY_DUTY_37P5, + UART_MOD_CLK_DUTY_31_25 = UART_MR_OPT_DUTY_DUTY_31P25, + UART_MOD_CLK_DUTY_25_00 = UART_MR_OPT_DUTY_DUTY_25, + UART_MOD_CLK_DUTY_18_75 = UART_MR_OPT_DUTY_DUTY_18P75, + UART_MOD_CLK_DUTY_12_50 = UART_MR_OPT_DUTY_DUTY_12P5, + UART_MOD_CLK_DUTY_06_25 = UART_MR_OPT_DUTY_DUTY_6P25, +}; + +enum uart_optical_cmp_threshold { + UART_RX_CMP_THRESHOLD_VDDIO_DIV_10_0 = UART_MR_OPT_CMPTH_VDDIO_DIV10, + UART_RX_CMP_THRESHOLD_VDDIO_DIV_5_0 = UART_MR_OPT_CMPTH_VDDIO_DIV5, + UART_RX_CMP_THRESHOLD_VDDIO_DIV_3_3 = UART_MR_OPT_CMPTH_VDDIO_DIV3P3, + UART_RX_CMP_THRESHOLD_VDDIO_DIV_2_5 = UART_MR_OPT_CMPTH_VDDIO_DIV2P5, + UART_RX_CMP_THRESHOLD_VDDIO_DIV_2_0 = UART_MR_OPT_CMPTH_VDDIO_DIV2, +}; + +struct uart_config_optical { + /* UART Receive Data Inverted */ + bool rx_inverted; + /* UART Modulated Data Inverted */ + bool tx_inverted; + /* UART Receiver Digital Filter */ + bool rx_filter; + /* Optical Link Clock Divider */ + uint8_t clk_div; + /* Optical Link Modulation Clock Duty Cycle */ + enum uart_optical_duty_cycle duty; + /* Receive Path Comparator Threshold */ + enum uart_optical_cmp_threshold threshold; +}; + +void uart_enable_optical_interface(Uart *p_uart); +void uart_disable_optical_interface(Uart *p_uart); +void uart_config_optical_interface(Uart *p_uart, + struct uart_config_optical *cfg); +#endif + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +#endif /* UART_H_INCLUDED */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/usart/usart.c b/hw-libs/drivers/SAMx70/ASF/sam/drivers/usart/usart.c new file mode 100644 index 000000000..34680b248 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/usart/usart.c @@ -0,0 +1,2094 @@ +/** + * \file + * + * \brief Universal Synchronous Asynchronous Receiver Transmitter (USART) driver + * for SAM. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "usart.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \defgroup sam_drivers_usart_group Universal Synchronous Asynchronous + * Receiver Transmitter (USART) + * + * The Universal Synchronous Asynchronous Receiver Transceiver (USART) + * provides one full duplex universal synchronous asynchronous serial link. + * Data frame format is widely programmable (data length, parity, number of + * stop bits) to support a maximum of standards. The receiver implements + * parity error, framing error and overrun error detection. The receiver + * time-out enables handling variable-length frames and the transmitter + * timeguard facilitates communications with slow remote devices. Multidrop + * communications are also supported through address bit handling in reception + * and transmission. The driver supports the following modes: + * RS232, RS485, SPI, IrDA, ISO7816, MODEM, Hardware handshaking and LIN. + * + * @{ + */ + +/* The write protect key value. */ +#ifndef US_WPMR_WPKEY_PASSWD +#define US_WPMR_WPKEY_PASSWD US_WPMR_WPKEY(0x555341U) +#endif + +#ifndef US_WPMR_WPKEY_PASSWD +# define US_WPMR_WPKEY_PASSWD US_WPMR_WPKEY(US_WPKEY_VALUE) +#endif + +/* The CD value scope programmed in MR register. */ +#define MIN_CD_VALUE 0x01 +#define MIN_CD_VALUE_SPI 0x04 +#define MAX_CD_VALUE US_BRGR_CD_Msk + +/* The receiver sampling divide of baudrate clock. */ +#define HIGH_FRQ_SAMPLE_DIV 16 +#define LOW_FRQ_SAMPLE_DIV 8 + +/* Max transmitter timeguard. */ +#define MAX_TRAN_GUARD_TIME US_TTGR_TG_Msk + +/* The non-existent parity error number. */ +#define USART_PARITY_ERROR 5 + +/* ISO7816 protocol type. */ +#define ISO7816_T_0 0 +#define ISO7816_T_1 1 + +/** + * \brief Calculate a clock divider(CD) and a fractional part (FP) for the + * USART asynchronous modes to generate a baudrate as close as possible to + * the baudrate set point. + * + * \note Baud rate calculation: Baudrate = ul_mck/(Over * (CD + FP/8)) + * (Over being 16 or 8). The maximal oversampling is selected if it allows to + * generate a baudrate close to the set point. + * + * \param p_usart Pointer to a USART instance. + * \param baudrate Baud rate set point. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 Baud rate is successfully initialized. + * \retval 1 Baud rate set point is out of range for the given input clock + * frequency. + */ +uint32_t usart_set_async_baudrate(Usart *p_usart, + uint32_t baudrate, uint32_t ul_mck) +{ + uint32_t over; + uint32_t cd_fp; + uint32_t cd; + uint32_t fp; + + /* Calculate the receiver sampling divide of baudrate clock. */ + if (ul_mck >= HIGH_FRQ_SAMPLE_DIV * baudrate) { + over = HIGH_FRQ_SAMPLE_DIV; + } else { + over = LOW_FRQ_SAMPLE_DIV; + } + + /* Calculate clock divider according to the fraction calculated formula. */ + cd_fp = (8 * ul_mck + (over * baudrate) / 2) / (over * baudrate); + cd = cd_fp >> 3; + fp = cd_fp & 0x07; + if (cd < MIN_CD_VALUE || cd > MAX_CD_VALUE) { + return 1; + } + + /* Configure the OVER bit in MR register. */ + if (over == 8) { + p_usart->US_MR |= US_MR_OVER; + } + + /* Configure the baudrate generate register. */ + p_usart->US_BRGR = (cd << US_BRGR_CD_Pos) | (fp << US_BRGR_FP_Pos); + + return 0; +} + +/** + * \brief Calculate a clock divider for the USART synchronous master modes + * to generate a baudrate as close as possible to the baudrate set point. + * + * \note Synchronous baudrate calculation: baudrate = ul_mck / cd + * + * \param p_usart Pointer to a USART instance. + * \param baudrate Baud rate set point. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 Baud rate is successfully initialized. + * \retval 1 Baud rate set point is out of range for the given input clock + * frequency. + */ +static uint32_t usart_set_sync_master_baudrate(Usart *p_usart, + uint32_t baudrate, uint32_t ul_mck) +{ + uint32_t cd; + + /* Calculate clock divider according to the formula in synchronous mode. */ + cd = (ul_mck + baudrate / 2) / baudrate; + + if (cd < MIN_CD_VALUE || cd > MAX_CD_VALUE) { + return 1; + } + + /* Configure the baudrate generate register. */ + p_usart->US_BRGR = cd << US_BRGR_CD_Pos; + + p_usart->US_MR = (p_usart->US_MR & ~US_MR_USCLKS_Msk) | + US_MR_USCLKS_MCK | US_MR_SYNC; + return 0; +} + +/** + * \brief Select the SCK pin as the source of baud rate for the USART + * synchronous slave modes. + * + * \param p_usart Pointer to a USART instance. + */ +static void usart_set_sync_slave_baudrate(Usart *p_usart) +{ + p_usart->US_MR = (p_usart->US_MR & ~US_MR_USCLKS_Msk) | + US_MR_USCLKS_SCK | US_MR_SYNC; +} + +/** + * \brief Calculate a clock divider (\e CD) for the USART SPI master mode to + * generate a baud rate as close as possible to the baud rate set point. + * + * \note Baud rate calculation: + * \f$ Baudrate = \frac{SelectedClock}{CD} \f$. + * + * \param p_usart Pointer to a USART instance. + * \param baudrate Baud rate set point. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 Baud rate is successfully initialized. + * \retval 1 Baud rate set point is out of range for the given input clock + * frequency. + */ +static uint32_t usart_set_spi_master_baudrate(Usart *p_usart, + uint32_t baudrate, uint32_t ul_mck) +{ + uint32_t cd; + + /* Calculate the clock divider according to the formula in SPI mode. */ + cd = (ul_mck + baudrate / 2) / baudrate; + + if (cd < MIN_CD_VALUE_SPI || cd > MAX_CD_VALUE) { + return 1; + } + + p_usart->US_BRGR = cd << US_BRGR_CD_Pos; + + return 0; +} + +/** + * \brief Select the SCK pin as the source of baudrate for the USART SPI slave + * mode. + * + * \param p_usart Pointer to a USART instance. + */ +static void usart_set_spi_slave_baudrate(Usart *p_usart) +{ + p_usart->US_MR &= ~US_MR_USCLKS_Msk; + p_usart->US_MR |= US_MR_USCLKS_SCK; +} + +/** + * \brief Reset the USART and disable TX and RX. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_reset(Usart *p_usart) +{ + /* Disable the Write Protect. */ + usart_disable_writeprotect(p_usart); + + /* Reset registers that could cause unpredictable behavior after reset. */ + p_usart->US_MR = 0; + p_usart->US_RTOR = 0; + p_usart->US_TTGR = 0; + + /* Disable TX and RX. */ + usart_reset_tx(p_usart); + usart_reset_rx(p_usart); + /* Reset status bits. */ + usart_reset_status(p_usart); + /* Turn off RTS and DTR if exist. */ + usart_drive_RTS_pin_high(p_usart); +#if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E) + usart_drive_DTR_pin_high(p_usart); +#endif +} + +/** + * \brief Configure USART to work in RS232 mode. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_rs232(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck) +{ + static uint32_t ul_reg_val; + + /* Reset the USART and shut down TX and RX. */ + usart_reset(p_usart); + + ul_reg_val = 0; + /* Check whether the input values are legal. */ + if (!p_usart_opt || usart_set_async_baudrate(p_usart, + p_usart_opt->baudrate, ul_mck)) { + return 1; + } + + /* Configure the USART option. */ + ul_reg_val |= p_usart_opt->char_length | p_usart_opt->parity_type | + p_usart_opt->channel_mode | p_usart_opt->stop_bits; + + /* Configure the USART mode as normal mode. */ + ul_reg_val |= US_MR_USART_MODE_NORMAL; + + p_usart->US_MR |= ul_reg_val; + + return 0; +} + +/** + * \brief Configure USART to work in hardware handshaking mode. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_hw_handshaking(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck) +{ + /* Initialize the USART as standard RS232. */ + if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) { + return 1; + } + + /* Set hardware handshaking mode. */ + p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | + US_MR_USART_MODE_HW_HANDSHAKING; + + return 0; +} + +#if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E) + +/** + * \brief Configure USART to work in modem mode. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_modem(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck) +{ + /* + * SAM3S, SAM4S and SAM4E series support MODEM mode only on USART1, + * SAM3U and SAM4L series support MODEM mode only on USART0. + */ +#if (SAM3S || SAM4S || SAM4E) +#ifdef USART1 + if (p_usart != USART1) { + return 1; + } +#endif +#elif (SAM3U || SAM4L) + if (p_usart != USART0) { + return 1; + } +#endif + + /* Initialize the USART as standard RS232. */ + if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) { + return 1; + } + + /* Set MODEM mode. */ + p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | + US_MR_USART_MODE_MODEM; + + return 0; +} +#endif + +/** + * \brief Configure USART to work in SYNC mode and act as a master. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_sync_master(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck) +{ + static uint32_t ul_reg_val; + + /* Reset the USART and shut down TX and RX. */ + usart_reset(p_usart); + + ul_reg_val = 0; + /* Check whether the input values are legal. */ + if (!p_usart_opt || usart_set_sync_master_baudrate(p_usart, + p_usart_opt->baudrate, ul_mck)) { + return 1; + } + + /* Configure the USART option. */ + ul_reg_val |= p_usart_opt->char_length | p_usart_opt->parity_type | + p_usart_opt->channel_mode | p_usart_opt->stop_bits; + + /* Set normal mode and output clock as synchronous master. */ + ul_reg_val |= US_MR_USART_MODE_NORMAL | US_MR_CLKO; + p_usart->US_MR |= ul_reg_val; + + return 0; +} + +/** + * \brief Configure USART to work in SYNC mode and act as a slave. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_sync_slave(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt) +{ + static uint32_t ul_reg_val; + + /* Reset the USART and shut down TX and RX. */ + usart_reset(p_usart); + + ul_reg_val = 0; + usart_set_sync_slave_baudrate(p_usart); + + /* Check whether the input values are legal. */ + if (!p_usart_opt) { + return 1; + } + + /* Configure the USART option. */ + ul_reg_val |= p_usart_opt->char_length | p_usart_opt->parity_type | + p_usart_opt->channel_mode | p_usart_opt->stop_bits; + + /* Set normal mode. */ + ul_reg_val |= US_MR_USART_MODE_NORMAL; + p_usart->US_MR |= ul_reg_val; + + return 0; +} + +/** + * \brief Configure USART to work in RS485 mode. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_rs485(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck) +{ + /* Initialize the USART as standard RS232. */ + if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) { + return 1; + } + + /* Set RS485 mode. */ + p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | + US_MR_USART_MODE_RS485; + + return 0; +} + +#if (!SAMG55 && !SAMV71 && !SAMV70 && !SAME70 && !SAMS70) +/** + * \brief Configure USART to work in IrDA mode. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_irda(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck) +{ + /* Initialize the USART as standard RS232. */ + if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) { + return 1; + } + + /* Set IrDA filter. */ + p_usart->US_IF = p_usart_opt->irda_filter; + + /* Set IrDA mode. */ + p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | + US_MR_USART_MODE_IRDA; + + return 0; +} +#endif + +#if (!SAMV71 && !SAMV70 && !SAME70 && !SAMS70) +/** + * \brief Calculate a clock divider (\e CD) for the USART ISO7816 mode to + * generate an ISO7816 clock as close as possible to the clock set point. + * + * \note ISO7816 clock calculation: Clock = ul_mck / cd + * + * \param p_usart Pointer to a USART instance. + * \param clock ISO7816 clock set point. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 ISO7816 clock is successfully initialized. + * \retval 1 ISO7816 clock set point is out of range for the given input clock + * frequency. + */ +static uint32_t usart_set_iso7816_clock(Usart *p_usart, + uint32_t clock, uint32_t ul_mck) +{ + uint32_t cd; + + /* Calculate clock divider according to the formula in ISO7816 mode. */ + cd = (ul_mck + clock / 2) / clock; + + if (cd < MIN_CD_VALUE || cd > MAX_CD_VALUE) { + return 1; + } + + p_usart->US_MR = (p_usart->US_MR & ~(US_MR_USCLKS_Msk | US_MR_SYNC | + US_MR_OVER)) | US_MR_USCLKS_MCK | US_MR_CLKO; + + /* Configure the baudrate generate register. */ + p_usart->US_BRGR = cd << US_BRGR_CD_Pos; + + return 0; +} + +/** + * \brief Configure USART to work in ISO7816 mode. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_iso7816(Usart *p_usart, + const usart_iso7816_opt_t *p_usart_opt, uint32_t ul_mck) +{ + static uint32_t ul_reg_val; + + /* Reset the USART and shut down TX and RX. */ + usart_reset(p_usart); + + ul_reg_val = 0; + + /* Check whether the input values are legal. */ + if (!p_usart_opt || ((p_usart_opt->parity_type != US_MR_PAR_EVEN) && + (p_usart_opt->parity_type != US_MR_PAR_ODD))) { + return 1; + } + + if (p_usart_opt->protocol_type == ISO7816_T_0) { + ul_reg_val |= US_MR_USART_MODE_IS07816_T_0 | US_MR_NBSTOP_2_BIT | + (p_usart_opt->max_iterations << US_MR_MAX_ITERATION_Pos); + + if (p_usart_opt->bit_order) { + ul_reg_val |= US_MR_MSBF; + } + } else if (p_usart_opt->protocol_type == ISO7816_T_1) { + /* + * Only LSBF is used in the T=1 protocol, and max_iterations field + * is only used in T=0 mode. + */ + if (p_usart_opt->bit_order || p_usart_opt->max_iterations) { + return 1; + } + + /* Set USART mode to ISO7816, T=1, and always uses 1 stop bit. */ + ul_reg_val |= US_MR_USART_MODE_IS07816_T_1 | US_MR_NBSTOP_1_BIT; + } else { + return 1; + } + + /* Set up the baudrate. */ + if (usart_set_iso7816_clock(p_usart, p_usart_opt->iso7816_hz, ul_mck)) { + return 1; + } + + /* Set FIDI register: bit rate = iso7816_hz / fidi_ratio. */ + p_usart->US_FIDI = p_usart_opt->fidi_ratio; + + /* Set ISO7816 parity type in the MODE register. */ + ul_reg_val |= p_usart_opt->parity_type; + + if (p_usart_opt->inhibit_nack) { + ul_reg_val |= US_MR_INACK; + } + if (p_usart_opt->dis_suc_nack) { + ul_reg_val |= US_MR_DSNACK; + } + + p_usart->US_MR |= ul_reg_val; + + return 0; +} + +/** + * \brief Reset the ITERATION in US_CSR when the ISO7816 mode is enabled. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_reset_iterations(Usart *p_usart) +{ + p_usart->US_CR = US_CR_RSTIT; +} + +/** + * \brief Reset NACK in US_CSR. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_reset_nack(Usart *p_usart) +{ + p_usart->US_CR = US_CR_RSTNACK; +} + +/** + * \brief Check if both receive buffers are full. + * + * \param p_usart Pointer to a USART instance. + * + * \retval 1 Receive buffers are full. + * \retval 0 Receive buffers are not full. + */ +uint32_t usart_is_rx_buf_full(Usart *p_usart) +{ + return (p_usart->US_CSR & US_CSR_RXBUFF) > 0; +} + +#if (!SAM4L) +/** + * \brief Check if one receive buffer is filled. + * + * \param p_usart Pointer to a USART instance. + * + * \retval 1 Receive is complete. + * \retval 0 Receive is still pending. + */ +uint32_t usart_is_rx_buf_end(Usart *p_usart) +{ + return (p_usart->US_CSR & US_CSR_ENDRX) > 0; +} + +/** + * \brief Check if one transmit buffer is empty. + * + * \param p_usart Pointer to a USART instance. + * + * \retval 1 Transmit is complete. + * \retval 0 Transmit is still pending. + */ +uint32_t usart_is_tx_buf_end(Usart *p_usart) +{ + return (p_usart->US_CSR & US_CSR_ENDTX) > 0; +} + +/** + * \brief Check if both transmit buffers are empty. + * + * \param p_usart Pointer to a USART instance. + * + * \retval 1 Transmit buffers are empty. + * \retval 0 Transmit buffers are not empty. + */ +uint32_t usart_is_tx_buf_empty(Usart *p_usart) +{ + return (p_usart->US_CSR & US_CSR_TXBUFE) > 0; +} +#endif + +/** + * \brief Get the total number of errors that occur during an ISO7816 transfer. + * + * \param p_usart Pointer to a USART instance. + * + * \return The number of errors that occurred. + */ +uint8_t usart_get_error_number(Usart *p_usart) +{ + return (p_usart->US_NER & US_NER_NB_ERRORS_Msk); +} + +#endif + +/** + * \brief Configure USART to work in SPI mode and act as a master. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_spi_master(Usart *p_usart, + const usart_spi_opt_t *p_usart_opt, uint32_t ul_mck) +{ + static uint32_t ul_reg_val; + + /* Reset the USART and shut down TX and RX. */ + usart_reset(p_usart); + + ul_reg_val = 0; + /* Check whether the input values are legal. */ + if (!p_usart_opt || (p_usart_opt->spi_mode > SPI_MODE_3) || + usart_set_spi_master_baudrate(p_usart, p_usart_opt->baudrate, + ul_mck)) { + return 1; + } + + /* Configure the character length bit in MR register. */ + ul_reg_val |= p_usart_opt->char_length; + + /* Set SPI master mode and channel mode. */ + ul_reg_val |= US_MR_USART_MODE_SPI_MASTER | US_MR_CLKO | + p_usart_opt->channel_mode; + + switch (p_usart_opt->spi_mode) { + case SPI_MODE_0: + ul_reg_val |= US_MR_CPHA; + ul_reg_val &= ~US_MR_CPOL; + break; + + case SPI_MODE_1: + ul_reg_val &= ~US_MR_CPHA; + ul_reg_val &= ~US_MR_CPOL; + break; + + case SPI_MODE_2: + ul_reg_val |= US_MR_CPHA; + ul_reg_val |= US_MR_CPOL; + break; + + case SPI_MODE_3: + ul_reg_val &= ~US_MR_CPHA; + ul_reg_val |= US_MR_CPOL; + break; + + default: + break; + } + + p_usart->US_MR |= ul_reg_val; + + return 0; +} + +/** + * \brief Configure USART to work in SPI mode and act as a slave. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_spi_slave(Usart *p_usart, + const usart_spi_opt_t *p_usart_opt) +{ + static uint32_t ul_reg_val; + + /* Reset the USART and shut down TX and RX. */ + usart_reset(p_usart); + + ul_reg_val = 0; + usart_set_spi_slave_baudrate(p_usart); + + /* Check whether the input values are legal. */ + if (!p_usart_opt || p_usart_opt->spi_mode > SPI_MODE_3) { + return 1; + } + + /* Configure the character length bit in MR register. */ + ul_reg_val |= p_usart_opt->char_length; + + /* Set SPI slave mode and channel mode. */ + ul_reg_val |= US_MR_USART_MODE_SPI_SLAVE | p_usart_opt->channel_mode; + + switch (p_usart_opt->spi_mode) { + case SPI_MODE_0: + ul_reg_val |= US_MR_CPHA; + ul_reg_val &= ~US_MR_CPOL; + break; + + case SPI_MODE_1: + ul_reg_val &= ~US_MR_CPHA; + ul_reg_val &= ~US_MR_CPOL; + break; + + case SPI_MODE_2: + ul_reg_val |= US_MR_CPHA; + ul_reg_val |= US_MR_CPOL; + break; + + case SPI_MODE_3: + ul_reg_val |= US_MR_CPOL; + ul_reg_val &= ~US_MR_CPHA; + break; + + default: + break; + } + + p_usart->US_MR |= ul_reg_val; + + return 0; +} + +#if (SAM3XA || SAM4L || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) + +/** + * \brief Configure USART to work in LIN mode and act as a LIN master. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param ul_baudrate Baudrate to be used. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_lin_master(Usart *p_usart,uint32_t ul_baudrate, + uint32_t ul_mck) +{ + /* Reset the USART and shut down TX and RX. */ + usart_reset(p_usart); + + /* Set up the baudrate. */ + if (usart_set_async_baudrate(p_usart, ul_baudrate, ul_mck)) { + return 1; + } + + /* Set LIN master mode. */ + p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | + US_MR_USART_MODE_LIN_MASTER; + + usart_enable_rx(p_usart); + usart_enable_tx(p_usart); + + return 0; +} + +/** + * \brief Configure USART to work in LIN mode and act as a LIN slave. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param ul_baudrate Baudrate to be used. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_lin_slave(Usart *p_usart, uint32_t ul_baudrate, + uint32_t ul_mck) +{ + /* Reset the USART and shut down TX and RX. */ + usart_reset(p_usart); + + usart_enable_rx(p_usart); + usart_enable_tx(p_usart); + + /* Set LIN slave mode. */ + p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | + US_MR_USART_MODE_LIN_SLAVE; + + /* Set up the baudrate. */ + if (usart_set_async_baudrate(p_usart, ul_baudrate, ul_mck)) { + return 1; + } + + return 0; +} + +/** + * \brief Abort the current LIN transmission. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_abort_tx(Usart *p_usart) +{ + p_usart->US_CR = US_CR_LINABT; +} + +/** + * \brief Send a wakeup signal on the LIN bus. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_send_wakeup_signal(Usart *p_usart) +{ + p_usart->US_CR = US_CR_LINWKUP; +} + +/** + * \brief Configure the LIN node action, which should be one of PUBLISH, + * SUBSCRIBE or IGNORE. + * + * \param p_usart Pointer to a USART instance. + * \param uc_action 0 for PUBLISH, 1 for SUBSCRIBE, 2 for IGNORE. + */ +void usart_lin_set_node_action(Usart *p_usart, uint8_t uc_action) +{ + p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_NACT_Msk) | + (uc_action << US_LINMR_NACT_Pos); +} + +/** + * \brief Disable the parity check during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_disable_parity(Usart *p_usart) +{ + p_usart->US_LINMR |= US_LINMR_PARDIS; +} + +/** + * \brief Enable the parity check during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_enable_parity(Usart *p_usart) +{ + p_usart->US_LINMR &= ~US_LINMR_PARDIS; +} + +/** + * \brief Disable the checksum during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_disable_checksum(Usart *p_usart) +{ + p_usart->US_LINMR |= US_LINMR_CHKDIS; +} + +/** + * \brief Enable the checksum during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_enable_checksum(Usart *p_usart) +{ + p_usart->US_LINMR &= ~US_LINMR_CHKDIS; +} + +/** + * \brief Configure the checksum type during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + * \param uc_type 0 for LIN 2.0 Enhanced checksum or 1 for LIN 1.3 Classic + * checksum. + */ +void usart_lin_set_checksum_type(Usart *p_usart, uint8_t uc_type) +{ + p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_CHKTYP) | + (uc_type << 4); +} + +/** + * \brief Configure the data length mode during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + * \param uc_mode Indicate the data length type: 0 if the data length is + * defined by the DLC of LIN mode register or 1 if the data length is defined + * by the bit 5 and 6 of the identifier. + */ +void usart_lin_set_data_len_mode(Usart *p_usart, uint8_t uc_mode) +{ + p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_DLM) | + (uc_mode << 5); +} + +/** + * \brief Disable the frame slot mode during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_disable_frame_slot(Usart *p_usart) +{ + p_usart->US_LINMR |= US_LINMR_FSDIS; +} + +/** + * \brief Enable the frame slot mode during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_enable_frame_slot(Usart *p_usart) +{ + p_usart->US_LINMR &= ~US_LINMR_FSDIS; +} + +/** + * \brief Configure the wakeup signal type during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + * \param uc_type Indicate the checksum type: 0 if the wakeup signal is a + * LIN 2.0 wakeup signal; 1 if the wakeup signal is a LIN 1.3 wakeup signal. + */ +void usart_lin_set_wakeup_signal_type(Usart *p_usart, uint8_t uc_type) +{ + p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_WKUPTYP) | + (uc_type << 7); +} + +/** + * \brief Configure the response data length if the data length is defined by + * the DLC field during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + * \param uc_len Indicate the response data length. + */ +void usart_lin_set_response_data_len(Usart *p_usart, uint8_t uc_len) +{ + p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_DLC_Msk) | + ((uc_len - 1) << US_LINMR_DLC_Pos); +} + +/** + * \brief The LIN mode register is not written by the PDC. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_disable_pdc_mode(Usart *p_usart) +{ + p_usart->US_LINMR &= ~US_LINMR_PDCM; +} + +/** + * \brief The LIN mode register (except this flag) is written by the PDC. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_enable_pdc_mode(Usart *p_usart) +{ + p_usart->US_LINMR |= US_LINMR_PDCM; +} + +/** + * \brief Configure the LIN identifier when USART works in LIN master mode. + * + * \param p_usart Pointer to a USART instance. + * \param uc_id The identifier to be transmitted. + */ +void usart_lin_set_tx_identifier(Usart *p_usart, uint8_t uc_id) +{ + p_usart->US_LINIR = (p_usart->US_LINIR & ~US_LINIR_IDCHR_Msk) | + US_LINIR_IDCHR(uc_id); +} + +/** + * \brief Read the identifier when USART works in LIN mode. + * + * \param p_usart Pointer to a USART instance. + * + * \return The last identifier received in LIN slave mode or the last + * identifier transmitted in LIN master mode. + */ +uint8_t usart_lin_read_identifier(Usart *p_usart) +{ + return (p_usart->US_LINIR & US_LINIR_IDCHR_Msk); +} + +/** + * \brief Get data length. + * + * \param p_usart Pointer to a USART instance. + * + * \return Data length. + */ +uint8_t usart_lin_get_data_length(Usart *usart) +{ + if (usart->US_LINMR & US_LINMR_DLM) { + uint8_t data_length = 1 << ((usart->US_LINIR >> + (US_LINIR_IDCHR_Pos + 4)) & 0x03); + return data_length; + } else { + return ((usart->US_LINMR & US_LINMR_DLC_Msk) >> US_LINMR_DLC_Pos) + 1; + } +} + +#endif + +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Get identifier send status. + * + * \param p_usart Pointer to a USART instance. + * + * \return + * 0: No LIN identifier has been sent since the last RSTSTA. + * 1: :At least one LIN identifier has been sent since the last RSTSTA. + */ +uint8_t usart_lin_identifier_send_complete(Usart *usart) +{ + return (usart->US_CSR & US_CSR_LINID) > 0; +} + +/** + * \brief Get identifier received status. + * + * \param p_usart Pointer to a USART instance. + * + * \return + * 0: No LIN identifier has been reveived since the last RSTSTA. + * 1: At least one LIN identifier has been received since the last RSTSTA. + */ +uint8_t usart_lin_identifier_reception_complete(Usart *usart) +{ + return (usart->US_CSR & US_CSR_LINID) > 0; +} + +/** + * \brief Get transmission status. + * + * \param p_usart Pointer to a USART instance. + * + * \return + * 0: The USART is idle or a LIN transfer is ongoing. + * 1: A LIN transfer has been completed since the last RSTSTA. + */ +uint8_t usart_lin_tx_complete(Usart *usart) +{ + return (usart->US_CSR & US_CSR_LINTC) > 0; +} + +/** + * \brief Configure USART to work in LON mode. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param ul_baudrate Baudrate to be used. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_lon(Usart *p_usart,uint32_t ul_baudrate, + uint32_t ul_mck) +{ + /* Reset the USART and shut down TX and RX. */ + usart_reset(p_usart); + + /* Set up the baudrate. */ + if (usart_set_async_baudrate(p_usart, ul_baudrate, ul_mck)) { + return 1; + } + + /* Set LIN master mode. */ + p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | + US_MR_USART_MODE_LON; + + usart_enable_rx(p_usart); + usart_enable_tx(p_usart); + + return 0; +} + +/** + * \brief set LON parameter value. + * + * \param p_usart Pointer to a USART instance. + * \param uc_type 0: LON comm_type = 1 mode, + * 1: LON comm_type = 2 mode + */ +void usart_lon_set_comm_type(Usart *p_usart, uint8_t uc_type) +{ + p_usart->US_LONMR = (p_usart->US_LONMR & ~US_LONMR_COMMT) | + (uc_type << 0); +} + +/** + * \brief Disable LON Collision Detection Feature. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lon_disable_coll_detection(Usart *p_usart) +{ + p_usart->US_LONMR |= US_LONMR_COLDET; +} + +/** + * \brief Enable LON Collision Detection Feature. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lon_enable_coll_detection(Usart *p_usart) +{ + p_usart->US_LONMR &= ~US_LONMR_COLDET; +} + +/** + * \brief set Terminate Frame upon Collision Notification. + * + * \param p_usart Pointer to a USART instance. + * \param uc_type 0: Do not terminate the frame in LON comm_type = 1 mode upon collision detection. + * 1:Terminate the frame in LON comm_type = 1 mode upon collision detection if possible. + */ +void usart_lon_set_tcol(Usart *p_usart, uint8_t uc_type) +{ + p_usart->US_LONMR = (p_usart->US_LONMR & ~US_LONMR_TCOL) | + (uc_type << 2); +} + +/** + * \brief set LON Collision Detection on Frame Tail. + * + * \param p_usart Pointer to a USART instance. + * \param uc_type 0: Detect collisions after CRC has been sent but prior end of transmission in LON comm_type = 1 mode. + * 1: Ignore collisions after CRC has been sent but prior end of transmission in LON comm_type = 1 mode. + */ +void usart_lon_set_cdtail(Usart *p_usart, uint8_t uc_type) +{ + p_usart->US_LONMR = (p_usart->US_LONMR & ~US_LONMR_CDTAIL) | + (uc_type << 3); +} + +/** + * \brief set LON DMA Mode. + * + * \param p_usart Pointer to a USART instance. + * \param uc_type 0: The LON data length register US_LONDL is not written by the DMA. + * 1: The LON data length register US_LONDL is written by the DMA. + */ +void usart_lon_set_dmam(Usart *p_usart, uint8_t uc_type) +{ + p_usart->US_LONMR = (p_usart->US_LONMR & ~US_LONMR_DMAM) | + (uc_type << 4); +} + +/** + * \brief set LON Beta1 Length after Transmission. + * + * \param p_usart Pointer to a USART instance. + * \param ul_len 1-16777215: LON beta1 length after transmission in tbit + */ +void usart_lon_set_beta1_tx_len(Usart *p_usart, uint32_t ul_len) +{ + p_usart->US_LONB1TX = US_LONB1TX_BETA1TX(ul_len); +} + +/** + * \brief set LON Beta1 Length after Reception. + * + * \param p_usart Pointer to a USART instance. + * \param ul_len 1-16777215: LON beta1 length after reception in tbit. + */ +void usart_lon_set_beta1_rx_len(Usart *p_usart, uint32_t ul_len) +{ + p_usart->US_LONB1RX = US_LONB1RX_BETA1RX(ul_len); +} + +/** + * \brief set LON Priority. + * + * \param p_usart Pointer to a USART instance. + * \param uc_psnb 0 -127: LON Priority Slot Number. + * \param uc_nps 0 -127: LON Node Priority Slot. + */ +void usart_lon_set_priority(Usart *p_usart, uint8_t uc_psnb, uint8_t uc_nps) +{ + p_usart->US_LONPRIO = US_LONPRIO_PSNB(uc_psnb) | US_LONPRIO_NPS(uc_nps); +} + +/** + * \brief set LON Indeterminate Time after Transmission. + * + * \param p_usart Pointer to a USART instance. + * \param ul_time 1-16777215: LON Indeterminate Time after Transmission (comm_type = 1 mode only). + */ +void usart_lon_set_tx_idt(Usart *p_usart, uint32_t ul_time) +{ + p_usart->US_IDTTX = US_IDTTX_IDTTX(ul_time); +} + +/** + * \brief set LON Indeterminate Time after Reception. + * + * \param p_usart Pointer to a USART instance. + * \param ul_time 1-16777215: LON Indeterminate Time after Reception (comm_type = 1 mode only). + */ +void usart_lon_set_rx_idt(Usart *p_usart, uint32_t ul_time) +{ + p_usart->US_IDTRX = US_IDTRX_IDTRX(ul_time); +} + +/** + * \brief set LON Preamble Length. + * + * \param p_usart Pointer to a USART instance. + * \param ul_len 1-16383: LON preamble length in tbit(without byte-sync). + */ +void usart_lon_set_pre_len(Usart *p_usart, uint32_t ul_len) +{ + p_usart->US_LONPR = US_LONPR_LONPL(ul_len); +} + +/** + * \brief set LON Data Length. + * + * \param p_usart Pointer to a USART instance. + * \param uc_len 0-255: LON data length is LONDL+1 bytes. + */ +void usart_lon_set_data_len(Usart *p_usart, uint8_t uc_len) +{ + p_usart->US_LONDL = US_LONDL_LONDL(uc_len); +} + +/** + * \brief set LON Priority. + * + * \param p_usart Pointer to a USART instance. + * \param uc_bli LON Backlog Increment. + * \param uc_altp LON Alternate Path Bit. + * \param uc_pb LON Priority Bit. + */ +void usart_lon_set_l2hdr(Usart *p_usart, uint8_t uc_bli, uint8_t uc_altp, uint8_t uc_pb) +{ + p_usart->US_LONL2HDR = US_LONL2HDR_BLI(uc_bli) | (uc_altp << 6) | (uc_pb << 7); +} + +/** + * \brief Check if LON Transmission End. + * + * \param p_usart Pointer to a USART instance. + * + * \retval 1 At least one transmission has been performed since the last RSTSTA. + * \retval 0 Transmission on going or no transmission occurred since the last RSTSTA. + */ +uint32_t usart_lon_is_tx_end(Usart *p_usart) +{ + return (p_usart->US_CSR & US_CSR_LTXD) > 0; +} + +/** + * \brief Check if LON Reception End. + * + * \param p_usart Pointer to a USART instance. + * + * \retval 1 At least one Reception has been performed since the last RSTSTA. + * \retval 0 Reception on going or no Reception occurred since the last RSTSTA. + */ +uint32_t usart_lon_is_rx_end(Usart *p_usart) +{ + return (p_usart->US_CSR & US_CSR_LRXD) > 0; +} +#endif + +/** + * \brief Enable USART transmitter. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_enable_tx(Usart *p_usart) +{ + p_usart->US_CR = US_CR_TXEN; +} + +/** + * \brief Disable USART transmitter. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_disable_tx(Usart *p_usart) +{ + p_usart->US_CR = US_CR_TXDIS; +} + +/** + * \brief Immediately stop and disable USART transmitter. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_reset_tx(Usart *p_usart) +{ + /* Reset transmitter */ + p_usart->US_CR = US_CR_RSTTX | US_CR_TXDIS; +} + +/** + * \brief Configure the transmit timeguard register. + * + * \param p_usart Pointer to a USART instance. + * \param timeguard The value of transmit timeguard. + */ +void usart_set_tx_timeguard(Usart *p_usart, uint32_t timeguard) +{ + p_usart->US_TTGR = timeguard; +} + +/** + * \brief Enable USART receiver. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_enable_rx(Usart *p_usart) +{ + p_usart->US_CR = US_CR_RXEN; +} + +/** + * \brief Disable USART receiver. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_disable_rx(Usart *p_usart) +{ + p_usart->US_CR = US_CR_RXDIS; +} + +/** + * \brief Immediately stop and disable USART receiver. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_reset_rx(Usart *p_usart) +{ + /* Reset Receiver */ + p_usart->US_CR = US_CR_RSTRX | US_CR_RXDIS; +} + +/** + * \brief Configure the receive timeout register. + * + * \param p_usart Pointer to a USART instance. + * \param timeout The value of receive timeout. + */ +void usart_set_rx_timeout(Usart *p_usart, uint32_t timeout) +{ + p_usart->US_RTOR = timeout; +} + +/** + * \brief Enable USART interrupts. + * + * \param p_usart Pointer to a USART peripheral. + * \param ul_sources Interrupt sources bit map. + */ +void usart_enable_interrupt(Usart *p_usart, uint32_t ul_sources) +{ + p_usart->US_IER = ul_sources; +} + +/** + * \brief Disable USART interrupts. + * + * \param p_usart Pointer to a USART peripheral. + * \param ul_sources Interrupt sources bit map. + */ +void usart_disable_interrupt(Usart *p_usart, uint32_t ul_sources) +{ + p_usart->US_IDR = ul_sources; +} + +/** + * \brief Read USART interrupt mask. + * + * \param p_usart Pointer to a USART peripheral. + * + * \return The interrupt mask value. + */ +uint32_t usart_get_interrupt_mask(Usart *p_usart) +{ + return p_usart->US_IMR; +} + +/** + * \brief Get current status. + * + * \param p_usart Pointer to a USART instance. + * + * \return The current USART status. + */ +uint32_t usart_get_status(Usart *p_usart) +{ + return p_usart->US_CSR; +} + +/** + * \brief Reset status bits (PARE, OVER, MANERR, UNRE and PXBRK in US_CSR). + * + * \param p_usart Pointer to a USART instance. + */ +void usart_reset_status(Usart *p_usart) +{ + p_usart->US_CR = US_CR_RSTSTA; +} + +/** + * \brief Start transmission of a break. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_start_tx_break(Usart *p_usart) +{ + p_usart->US_CR = US_CR_STTBRK; +} + +/** + * \brief Stop transmission of a break. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_stop_tx_break(Usart *p_usart) +{ + p_usart->US_CR = US_CR_STPBRK; +} + +/** + * \brief Start waiting for a character before clocking the timeout count. + * Reset the status bit TIMEOUT in US_CSR. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_start_rx_timeout(Usart *p_usart) +{ + p_usart->US_CR = US_CR_STTTO; +} + +/** + * \brief In Multidrop mode only, the next character written to the US_THR + * is sent with the address bit set. + * + * \param p_usart Pointer to a USART instance. + * \param ul_addr The address to be sent out. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_send_address(Usart *p_usart, uint32_t ul_addr) +{ + if ((p_usart->US_MR & US_MR_PAR_MULTIDROP) != US_MR_PAR_MULTIDROP) { + return 1; + } + + p_usart->US_CR = US_CR_SENDA; + + if (usart_write(p_usart, ul_addr)) { + return 1; + } else { + return 0; + } +} + +/** + * \brief Restart the receive timeout. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_restart_rx_timeout(Usart *p_usart) +{ + p_usart->US_CR = US_CR_RETTO; +} + +#if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E) + +/** + * \brief Drive the pin DTR to 0. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_drive_DTR_pin_low(Usart *p_usart) +{ + p_usart->US_CR = US_CR_DTREN; +} + +/** + * \brief Drive the pin DTR to 1. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_drive_DTR_pin_high(Usart *p_usart) +{ + p_usart->US_CR = US_CR_DTRDIS; +} + +#endif + +/** + * \brief Drive the pin RTS to 0. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_drive_RTS_pin_low(Usart *p_usart) +{ + p_usart->US_CR = US_CR_RTSEN; +} + +/** + * \brief Drive the pin RTS to 1. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_drive_RTS_pin_high(Usart *p_usart) +{ + p_usart->US_CR = US_CR_RTSDIS; +} + +/** + * \brief Drive the slave select line NSS (RTS pin) to 0 in SPI master mode. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_spi_force_chip_select(Usart *p_usart) +{ + p_usart->US_CR = US_CR_FCS; +} + +/** + * \brief Drive the slave select line NSS (RTS pin) to 1 in SPI master mode. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_spi_release_chip_select(Usart *p_usart) +{ + p_usart->US_CR = US_CR_RCS; +} + +/** + * \brief Check if Transmit is Ready. + * Check if data have been loaded in USART_THR and are waiting to be loaded + * into the Transmit Shift Register (TSR). + * + * \param p_usart Pointer to a USART instance. + * + * \retval 1 No data is in the Transmit Holding Register. + * \retval 0 There is data in the Transmit Holding Register. + */ +uint32_t usart_is_tx_ready(Usart *p_usart) +{ + return (p_usart->US_CSR & US_CSR_TXRDY) > 0; +} + +/** + * \brief Check if Transmit Holding Register is empty. + * Check if the last data written in USART_THR have been loaded in TSR and the + * last data loaded in TSR have been transmitted. + * + * \param p_usart Pointer to a USART instance. + * + * \retval 1 Transmitter is empty. + * \retval 0 Transmitter is not empty. + */ +uint32_t usart_is_tx_empty(Usart *p_usart) +{ + return (p_usart->US_CSR & US_CSR_TXEMPTY) > 0; +} + +/** + * \brief Check if the received data are ready. + * Check if Data have been received and loaded into USART_RHR. + * + * \param p_usart Pointer to a USART instance. + * + * \retval 1 Some data has been received. + * \retval 0 No data has been received. + */ +uint32_t usart_is_rx_ready(Usart *p_usart) +{ + return (p_usart->US_CSR & US_CSR_RXRDY) > 0; +} + +/** + * \brief Write to USART Transmit Holding Register. + * + * \note Before writing user should check if tx is ready (or empty). + * + * \param p_usart Pointer to a USART instance. + * \param c Data to be sent. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_write(Usart *p_usart, uint32_t c) +{ + if (!(p_usart->US_CSR & US_CSR_TXRDY)) { + return 1; + } + + p_usart->US_THR = US_THR_TXCHR(c); + return 0; +} + +/** + * \brief Write to USART Transmit Holding Register. + * + * \note Before writing user should check if tx is ready (or empty). + * + * \param p_usart Pointer to a USART instance. + * \param c Data to be sent. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_putchar(Usart *p_usart, uint32_t c) +{ + while (!(p_usart->US_CSR & US_CSR_TXRDY)) { + } + + p_usart->US_THR = US_THR_TXCHR(c); + + return 0; +} + +/** + * \brief Write one-line string through USART. + * + * \param p_usart Pointer to a USART instance. + * \param string Pointer to one-line string to be sent. + */ +void usart_write_line(Usart *p_usart, const char *string) +{ + while (*string != '\0') { + usart_putchar(p_usart, *string++); + } +} + +/** + * \brief Read from USART Receive Holding Register. + * + * \note Before reading user should check if rx is ready. + * + * \param p_usart Pointer to a USART instance. + * \param c Pointer where the one-byte received data will be stored. + * + * \retval 0 on success. + * \retval 1 if no data is available or errors. + */ +uint32_t usart_read(Usart *p_usart, uint32_t *c) +{ + if (!(p_usart->US_CSR & US_CSR_RXRDY)) { + return 1; + } + + /* Read character */ + *c = p_usart->US_RHR & US_RHR_RXCHR_Msk; + + return 0; +} + +/** + * \brief Read from USART Receive Holding Register. + * Before reading user should check if rx is ready. + * + * \param p_usart Pointer to a USART instance. + * \param c Pointer where the one-byte received data will be stored. + * + * \retval 0 Data has been received. + * \retval 1 on failure. + */ +uint32_t usart_getchar(Usart *p_usart, uint32_t *c) +{ + /* Wait until it's not empty or timeout has reached. */ + while (!(p_usart->US_CSR & US_CSR_RXRDY)) { + } + + /* Read character */ + *c = p_usart->US_RHR & US_RHR_RXCHR_Msk; + + return 0; +} + +#if (SAM3XA || SAM3U) +/** + * \brief Get Transmit address for DMA operation. + * + * \param p_usart Pointer to a USART instance. + * + * \return Transmit address for DMA access. + */ +uint32_t *usart_get_tx_access(Usart *p_usart) +{ + return (uint32_t *)&(p_usart->US_THR); +} + +/** + * \brief Get Receive address for DMA operation. + * + * \param p_usart Pointer to a USART instance. + * + * \return Receive address for DMA access. + */ +uint32_t *usart_get_rx_access(Usart *p_usart) +{ + return (uint32_t *)&(p_usart->US_RHR); +} +#endif + +#if (!SAM4L && !SAMV71 && !SAMV70 && !SAME70 && !SAMS70) +/** + * \brief Get USART PDC base address. + * + * \param p_usart Pointer to a UART instance. + * + * \return USART PDC registers base for PDC driver to access. + */ +Pdc *usart_get_pdc_base(Usart *p_usart) +{ + Pdc *p_pdc_base; + + p_pdc_base = (Pdc *)NULL; + +#ifdef PDC_USART + if (p_usart == USART) { + p_pdc_base = PDC_USART; + return p_pdc_base; + } +#endif +#ifdef PDC_USART0 + if (p_usart == USART0) { + p_pdc_base = PDC_USART0; + return p_pdc_base; + } +#endif +#ifdef PDC_USART1 + else if (p_usart == USART1) { + p_pdc_base = PDC_USART1; + return p_pdc_base; + } +#endif +#ifdef PDC_USART2 + else if (p_usart == USART2) { + p_pdc_base = PDC_USART2; + return p_pdc_base; + } +#endif +#ifdef PDC_USART3 + else if (p_usart == USART3) { + p_pdc_base = PDC_USART3; + return p_pdc_base; + } +#endif +#ifdef PDC_USART4 + else if (p_usart == USART4) { + p_pdc_base = PDC_USART4; + return p_pdc_base; + } +#endif +#ifdef PDC_USART5 + else if (p_usart == USART5) { + p_pdc_base = PDC_USART5; + return p_pdc_base; + } +#endif +#ifdef PDC_USART6 + else if (p_usart == USART6) { + p_pdc_base = PDC_USART6; + return p_pdc_base; + } +#endif +#ifdef PDC_USART7 + else if (p_usart == USART7) { + p_pdc_base = PDC_USART7; + return p_pdc_base; + } +#endif + + return p_pdc_base; +} +#endif + +/** + * \brief Enable write protect of USART registers. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_enable_writeprotect(Usart *p_usart) +{ + p_usart->US_WPMR = US_WPMR_WPEN | US_WPMR_WPKEY_PASSWD; +} + +/** + * \brief Disable write protect of USART registers. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_disable_writeprotect(Usart *p_usart) +{ + p_usart->US_WPMR = US_WPMR_WPKEY_PASSWD; +} + +/** + * \brief Get write protect status. + * + * \param p_usart Pointer to a USART instance. + * + * \return 0 if no write protect violation occurred, or 16-bit write protect + * violation source. + */ +uint32_t usart_get_writeprotect_status(Usart *p_usart) +{ + uint32_t reg_value; + + reg_value = p_usart->US_WPSR; + if (reg_value & US_WPSR_WPVS) { + return (reg_value & US_WPSR_WPVSRC_Msk) >> US_WPSR_WPVSRC_Pos; + } else { + return 0; + } +} + +#if (SAM3S || SAM4S || SAM3U || SAM3XA || SAM4L || SAM4E || SAM4C || SAM4CP || SAM4CM) + +/** + * \brief Configure the transmitter preamble length when the Manchester + * encode/decode is enabled. + * + * \param p_usart Pointer to a USART instance. + * \param uc_len The transmitter preamble length, which should be 0 ~ 15. + */ +void usart_man_set_tx_pre_len(Usart *p_usart, uint8_t uc_len) +{ + p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_PL_Msk) | + US_MAN_TX_PL(uc_len); +} + +/** + * \brief Configure the transmitter preamble pattern when the Manchester + * encode/decode is enabled, which should be 0 ~ 3. + * + * \param p_usart Pointer to a USART instance. + * \param uc_pattern 0 if the preamble is composed of '1's; + * 1 if the preamble is composed of '0's; + * 2 if the preamble is composed of '01's; + * 3 if the preamble is composed of '10's. + */ +void usart_man_set_tx_pre_pattern(Usart *p_usart, uint8_t uc_pattern) +{ + p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_PP_Msk) | + (uc_pattern << US_MAN_TX_PP_Pos); +} + +/** + * \brief Configure the transmitter Manchester polarity when the Manchester + * encode/decode is enabled. + * + * \param p_usart Pointer to a USART instance. + * \param uc_polarity Indicate the transmitter Manchester polarity, which + * should be 0 or 1. + */ +void usart_man_set_tx_polarity(Usart *p_usart, uint8_t uc_polarity) +{ + p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_MPOL) | + (uc_polarity << 12); +} + +/** + * \brief Configure the detected receiver preamble length when the Manchester + * encode/decode is enabled. + * + * \param p_usart Pointer to a USART instance. + * \param uc_len The detected receiver preamble length, which should be 0 ~ 15. + */ +void usart_man_set_rx_pre_len(Usart *p_usart, uint8_t uc_len) +{ + p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_PL_Msk) | + US_MAN_RX_PL(uc_len); +} + +/** + * \brief Configure the detected receiver preamble pattern when the Manchester + * encode/decode is enabled, which should be 0 ~ 3. + * + * \param p_usart Pointer to a USART instance. + * \param uc_pattern 0 if the preamble is composed of '1's; + * 1 if the preamble is composed of '0's; + * 2 if the preamble is composed of '01's; + * 3 if the preamble is composed of '10's. + */ +void usart_man_set_rx_pre_pattern(Usart *p_usart, uint8_t uc_pattern) +{ + p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_PP_Msk) | + (uc_pattern << US_MAN_RX_PP_Pos); +} + +/** + * \brief Configure the receiver Manchester polarity when the Manchester + * encode/decode is enabled. + * + * \param p_usart Pointer to a USART instance. + * \param uc_polarity Indicate the receiver Manchester polarity, which should + * be 0 or 1. + */ +void usart_man_set_rx_polarity(Usart *p_usart, uint8_t uc_polarity) +{ + p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_MPOL) | + (uc_polarity << 28); +} + +/** + * \brief Enable drift compensation. + * + * \note The 16X clock mode must be enabled. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_man_enable_drift_compensation(Usart *p_usart) +{ + p_usart->US_MAN |= US_MAN_DRIFT; +} + +/** + * \brief Disable drift compensation. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_man_disable_drift_compensation(Usart *p_usart) +{ + p_usart->US_MAN &= ~US_MAN_DRIFT; +} + +#endif + +#if SAM4L + +uint32_t usart_get_version(Usart *p_usart) +{ + return p_usart->US_VERSION; +} + +#endif + +#if SAMG55 +/** + * \brief Set sleepwalking match mode. + * + * \param p_uart Pointer to a USART instance. + * \param ul_low_value First comparison value for received character. + * \param ul_high_value Second comparison value for received character. + * \param cmpmode ture for start condition, false for flag only. + * \param cmppar ture for parity check, false for no. + */ +void usart_set_sleepwalking(Usart *p_uart, uint8_t ul_low_value, + bool cmpmode, bool cmppar, uint8_t ul_high_value) +{ + Assert(ul_low_value <= ul_high_value); + + uint32_t temp = 0; + + if (cmpmode) { + temp |= US_CMPR_CMPMODE_START_CONDITION; + } + + if (cmppar) { + temp |= US_CMPR_CMPPAR; + } + + temp |= US_CMPR_VAL1(ul_low_value); + + temp |= US_CMPR_VAL2(ul_high_value); + + p_uart->US_CMPR= temp; +} +#endif + +//@} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/usart/usart.h b/hw-libs/drivers/SAMx70/ASF/sam/drivers/usart/usart.h new file mode 100644 index 000000000..8b205fde7 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/usart/usart.h @@ -0,0 +1,773 @@ +/** + * \file + * + * \brief Universal Synchronous Asynchronous Receiver Transmitter (USART) driver + * for SAM. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef USART_H_INCLUDED +#define USART_H_INCLUDED + +#include "compiler.h" + +/** + * \defgroup group_sam_drivers_usart Universal Synchronous Asynchronous Receiver + * Transmitter (USART). + * + * See \ref sam_usart_quickstart. + * + * This is a low-level driver implementation for the SAM Universal + * Synchronous/Asynchronous Receiver/Transmitter. + * + * @{ + */ + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** Clock phase. */ +#define SPI_CPHA (1 << 0) + +/** Clock polarity. */ +#define SPI_CPOL (1 << 1) + +/** SPI mode definition. */ +#define SPI_MODE_0 0 +#define SPI_MODE_1 (SPI_CPHA) +#define SPI_MODE_2 (SPI_CPOL) +#define SPI_MODE_3 (SPI_CPOL | SPI_CPHA) + +/**micro definition for LIN mode of SAMV71*/ +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) +#ifndef US_MR_USART_MODE_LIN_MASTER +#define US_MR_USART_MODE_LIN_MASTER 0x0A +#endif +#ifndef US_MR_USART_MODE_LIN_SLAVE +#define US_MR_USART_MODE_LIN_SLAVE 0x0B +#endif +#endif +/* Input parameters when initializing RS232 and similar modes. */ +typedef struct { + /* Set baud rate of the USART (unused in slave modes). */ + uint32_t baudrate; + + /* + * Number of bits, which should be one of the following: US_MR_CHRL_5_BIT, + * US_MR_CHRL_6_BIT, US_MR_CHRL_7_BIT, US_MR_CHRL_8_BIT or + * US_MR_MODE9. + */ + uint32_t char_length; + + /* + * Parity type, which should be one of the following: US_MR_PAR_EVEN, + * US_MR_PAR_ODD, US_MR_PAR_SPACE, US_MR_PAR_MARK, US_MR_PAR_NO + * or US_MR_PAR_MULTIDROP. + */ + uint32_t parity_type; + + /* + * Number of stop bits between two characters: US_MR_NBSTOP_1_BIT, + * US_MR_NBSTOP_1_5_BIT, US_MR_NBSTOP_2_BIT. + * \note US_MR_NBSTOP_1_5_BIT is supported in asynchronous modes only. + */ + uint32_t stop_bits; + + /* + * Run the channel in test mode, which should be one of following: + * US_MR_CHMODE_NORMAL, US_MR_CHMODE_AUTOMATIC, + * US_MR_CHMODE_LOCAL_LOOPBACK, US_MR_CHMODE_REMOTE_LOOPBACK. + */ + uint32_t channel_mode; + + /* Filter of IrDA mode, useless in other modes. */ + uint32_t irda_filter; +} sam_usart_opt_t; + +/* Input parameters when initializing ISO7816 mode. */ +typedef struct { + /* Set the frequency of the ISO7816 clock. */ + uint32_t iso7816_hz; + + /* + * The number of ISO7816 clock ticks in every bit period (1 to 2047, + * 0 = disable clock). Baudrate rate = iso7816_hz / fidi_ratio. + */ + uint32_t fidi_ratio; + + /* + * How to calculate the parity bit: US_MR_PAR_EVEN for normal mode or + * US_MR_PAR_ODD for inverse mode. + */ + uint32_t parity_type; + + /* + * Inhibit Non Acknowledge: + * - 0: the NACK is generated; + * - 1: the NACK is not generated. + * + * \note This bit will be used only in ISO7816 mode, protocol T = 0 + * receiver. + */ + uint32_t inhibit_nack; + + /* + * Disable successive NACKs. + * - 0: NACK is sent on the ISO line as soon as a parity error occurs + * in the received character. Successive parity errors are counted up to + * the value in the max_iterations field. These parity errors generate + * a NACK on the ISO line. As soon as this value is reached, no additional + * NACK is sent on the ISO line. The ITERATION flag is asserted. + */ + uint32_t dis_suc_nack; + + /* Max number of repetitions (0 to 7). */ + uint32_t max_iterations; + + /* + * Bit order in transmitted characters: + * - 0: LSB first; + * - 1: MSB first. + */ + uint32_t bit_order; + + /* + * Which protocol is used: + * - 0: T = 0; + * - 1: T = 1. + */ + uint32_t protocol_type; +} usart_iso7816_opt_t; + +/* Input parameters when initializing SPI mode. */ +typedef struct { + /* Set the frequency of the SPI clock (unused in slave mode). */ + uint32_t baudrate; + + /* + * Number of bits, which should be one of the following: US_MR_CHRL_5_BIT, + * US_MR_CHRL_6_BIT, US_MR_CHRL_7_BIT, US_MR_CHRL_8_BIT or + * US_MR_MODE9. + */ + uint32_t char_length; + + /* + * Which SPI mode to use, which should be one of the following: + * SPI_MODE_0, SPI_MODE_1, SPI_MODE_2, SPI_MODE_3. + */ + uint32_t spi_mode; + + /* + * Run the channel in test mode, which should be one of following: + * US_MR_CHMODE_NORMAL, US_MR_CHMODE_AUTOMATIC, + * US_MR_CHMODE_LOCAL_LOOPBACK, US_MR_CHMODE_REMOTE_LOOPBACK. + */ + uint32_t channel_mode; +} usart_spi_opt_t; + +void usart_reset(Usart *p_usart); +uint32_t usart_set_async_baudrate(Usart *p_usart, + uint32_t baudrate, uint32_t ul_mck); +uint32_t usart_init_rs232(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck); +uint32_t usart_init_hw_handshaking(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck); +#if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E) +uint32_t usart_init_modem(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck); +#endif +uint32_t usart_init_sync_master(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck); +uint32_t usart_init_sync_slave(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt); +uint32_t usart_init_rs485(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck); +#if (!SAMG55 && !SAMV71 && !SAMV70 && !SAME70 && !SAMS70) +uint32_t usart_init_irda(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck); +#endif +#if (!SAMV71 && !SAMV70 && !SAME70 && !SAMS70) +uint32_t usart_init_iso7816(Usart *p_usart, + const usart_iso7816_opt_t *p_usart_opt, uint32_t ul_mck); +void usart_reset_iterations(Usart *p_usart); +void usart_reset_nack(Usart *p_usart); +uint32_t usart_is_rx_buf_end(Usart *p_usart); +uint32_t usart_is_tx_buf_end(Usart *p_usart); +uint32_t usart_is_rx_buf_full(Usart *p_usart); +uint32_t usart_is_tx_buf_empty(Usart *p_usart); +uint8_t usart_get_error_number(Usart *p_usart); +#endif +uint32_t usart_init_spi_master(Usart *p_usart, + const usart_spi_opt_t *p_usart_opt, uint32_t ul_mck); +uint32_t usart_init_spi_slave(Usart *p_usart, + const usart_spi_opt_t *p_usart_opt); +#if (SAM3XA || SAM4L || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) +uint32_t usart_init_lin_master(Usart *p_usart, uint32_t ul_baudrate, + uint32_t ul_mck); +uint32_t usart_init_lin_slave(Usart *p_usart, uint32_t ul_baudrate, + uint32_t ul_mck); +void usart_lin_abort_tx(Usart *p_usart); +void usart_lin_send_wakeup_signal(Usart *p_usart); +void usart_lin_set_node_action(Usart *p_usart, uint8_t uc_action); +void usart_lin_disable_parity(Usart *p_usart); +void usart_lin_enable_parity(Usart *p_usart); +void usart_lin_disable_checksum(Usart *p_usart); +void usart_lin_enable_checksum(Usart *p_usart); +void usart_lin_set_checksum_type(Usart *p_usart, uint8_t uc_type); +void usart_lin_set_data_len_mode(Usart *p_usart, uint8_t uc_mode); +void usart_lin_disable_frame_slot(Usart *p_usart); +void usart_lin_enable_frame_slot(Usart *p_usart); +void usart_lin_set_wakeup_signal_type(Usart *p_usart, uint8_t uc_type); +void usart_lin_set_response_data_len(Usart *p_usart, uint8_t uc_len); +void usart_lin_disable_pdc_mode(Usart *p_usart); +void usart_lin_enable_pdc_mode(Usart *p_usart); +void usart_lin_set_tx_identifier(Usart *p_usart, uint8_t uc_id); +uint8_t usart_lin_read_identifier(Usart *p_usart); +uint8_t usart_lin_get_data_length(Usart *usart); +#endif +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) +uint8_t usart_lin_identifier_send_complete(Usart *usart); +uint8_t usart_lin_identifier_reception_complete(Usart *usart); +uint8_t usart_lin_tx_complete(Usart *usart); +uint32_t usart_init_lon(Usart *p_usart, uint32_t ul_baudrate, uint32_t ul_mck); +void usart_lon_set_comm_type(Usart *p_usart, uint8_t uc_type); +void usart_lon_disable_coll_detection(Usart *p_usart); +void usart_lon_enable_coll_detection(Usart *p_usart); +void usart_lon_set_tcol(Usart *p_usart, uint8_t uc_type); +void usart_lon_set_cdtail(Usart *p_usart, uint8_t uc_type); +void usart_lon_set_dmam(Usart *p_usart, uint8_t uc_type); +void usart_lon_set_beta1_tx_len(Usart *p_usart, uint32_t ul_len); +void usart_lon_set_beta1_rx_len(Usart *p_usart, uint32_t ul_len); +void usart_lon_set_priority(Usart *p_usart, uint8_t uc_psnb, uint8_t uc_nps); +void usart_lon_set_tx_idt(Usart *p_usart, uint32_t ul_time); +void usart_lon_set_rx_idt(Usart *p_usart, uint32_t ul_time); +void usart_lon_set_pre_len(Usart *p_usart, uint32_t ul_len); +void usart_lon_set_data_len(Usart *p_usart, uint8_t uc_len); +void usart_lon_set_l2hdr(Usart *p_usart, uint8_t uc_bli, uint8_t uc_altp, uint8_t uc_pb); +uint32_t usart_lon_is_tx_end(Usart *p_usart); +uint32_t usart_lon_is_rx_end(Usart *p_usart); +#endif +void usart_enable_tx(Usart *p_usart); +void usart_disable_tx(Usart *p_usart); +void usart_reset_tx(Usart *p_usart); +void usart_set_tx_timeguard(Usart *p_usart, uint32_t timeguard); +void usart_enable_rx(Usart *p_usart); +void usart_disable_rx(Usart *p_usart); +void usart_reset_rx(Usart *p_usart); +void usart_set_rx_timeout(Usart *p_usart, uint32_t timeout); +void usart_enable_interrupt(Usart *p_usart, uint32_t ul_sources); +void usart_disable_interrupt(Usart *p_usart, uint32_t ul_sources); +uint32_t usart_get_interrupt_mask(Usart *p_usart); +uint32_t usart_get_status(Usart *p_usart); +void usart_reset_status(Usart *p_usart); +void usart_start_tx_break(Usart *p_usart); +void usart_stop_tx_break(Usart *p_usart); +void usart_start_rx_timeout(Usart *p_usart); +uint32_t usart_send_address(Usart *p_usart, uint32_t ul_addr); +void usart_restart_rx_timeout(Usart *p_usart); +#if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E) +void usart_drive_DTR_pin_low(Usart *p_usart); +void usart_drive_DTR_pin_high(Usart *p_usart); +#endif +void usart_drive_RTS_pin_low(Usart *p_usart); +void usart_drive_RTS_pin_high(Usart *p_usart); +void usart_spi_force_chip_select(Usart *p_usart); +void usart_spi_release_chip_select(Usart *p_usart); +uint32_t usart_is_tx_ready(Usart *p_usart); +uint32_t usart_is_tx_empty(Usart *p_usart); +uint32_t usart_is_rx_ready(Usart *p_usart); +uint32_t usart_write(Usart *p_usart, uint32_t c); +uint32_t usart_putchar(Usart *p_usart, uint32_t c); +void usart_write_line(Usart *p_usart, const char *string); +uint32_t usart_read(Usart *p_usart, uint32_t *c); +uint32_t usart_getchar(Usart *p_usart, uint32_t *c); +#if (SAM3XA || SAM3U) +uint32_t *usart_get_tx_access(Usart *p_usart); +uint32_t *usart_get_rx_access(Usart *p_usart); +#endif +#if (!SAM4L && !SAMV71 && !SAMV70 && !SAME70 && !SAMS70) +Pdc *usart_get_pdc_base(Usart *p_usart); +#endif +void usart_enable_writeprotect(Usart *p_usart); +void usart_disable_writeprotect(Usart *p_usart); +uint32_t usart_get_writeprotect_status(Usart *p_usart); +#if (SAM3S || SAM4S || SAM3U || SAM3XA || SAM4L || SAM4E || SAM4C || SAM4CP || SAM4CM || SAMV70 || SAMV71 || SAMS70 || SAME70) +void usart_man_set_tx_pre_len(Usart *p_usart, uint8_t uc_len); +void usart_man_set_tx_pre_pattern(Usart *p_usart, uint8_t uc_pattern); +void usart_man_set_tx_polarity(Usart *p_usart, uint8_t uc_polarity); +void usart_man_set_rx_pre_len(Usart *p_usart, uint8_t uc_len); +void usart_man_set_rx_pre_pattern(Usart *p_usart, uint8_t uc_pattern); +void usart_man_set_rx_polarity(Usart *p_usart, uint8_t uc_polarity); +void usart_man_enable_drift_compensation(Usart *p_usart); +void usart_man_disable_drift_compensation(Usart *p_usart); +#endif + +#if SAM4L +uint32_t usart_get_version(Usart *p_usart); +#endif + +#if SAMG55 +void usart_set_sleepwalking(Usart *p_uart, uint8_t ul_low_value, + bool cmpmode, bool cmppar, uint8_t ul_high_value); +#endif + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +//! @} + +/** + * \page sam_usart_quickstart Quick start guide for the SAM USART module + * + * This is the quick start guide for the \ref group_sam_drivers_usart + * "USART module", with step-by-step instructions on how to configure and + * use the driver in a selection of use cases. + * + * The use cases contain several code fragments. The code fragments in the + * steps for setup can be copied into a custom initialization function, while + * the steps for usage can be copied into, e.g., the main application function. + * + * \note Some SAM devices contain both USART and UART modules, with the latter + * being a subset in functionality of the former but physically separate + * peripherals. UART modules are compatible with the USART driver, but + * only for the functions and modes supported by the base UART driver. + * + * \section usart_use_cases USART use cases + * - \ref usart_basic_use_case + * - \subpage usart_use_case_1 + * - \subpage usart_use_case_2 + * + * \note The USART pins configuration are not included here. Please refer + * the related code in board_init() function. + * + * \section usart_basic_use_case Basic use case - transmit a character + * In this use case, the USART module is configured for: + * - Using USART0 + * - Baudrate: 9600 + * - Character length: 8 bit + * - Parity mode: Disabled + * - Stop bit: None + * - RS232 mode + * + * \section usart_basic_use_case_setup Setup steps + * + * \subsection usart_basic_use_case_setup_prereq Prerequisites + * -# \ref sysclk_group "System Clock Management (sysclock)" + * -# \ref ioport_group "Common IOPORT API (ioport)" + * + * \subsection usart_basic_use_case_setup_code Example code + * The following configuration must be added to the project (typically to a + * conf_usart.h file, but it can also be added to your main application file.) + * \code + #define USART_SERIAL USART0 + #define USART_SERIAL_ID ID_USART0 //USART0 for sam4l + #define USART_SERIAL_BAUDRATE 9600 + #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT + #define USART_SERIAL_PARITY US_MR_PAR_NO + #define USART_SERIAL_STOP_BIT US_MR_NBSTOP_1_BIT +\endcode + * + * Add to application initialization: + * \code + sysclk_init(); + + board_init(); + + const sam_usart_opt_t usart_console_settings = { + USART_SERIAL_BAUDRATE, + USART_SERIAL_CHAR_LENGTH, + USART_SERIAL_PARITY, + USART_SERIAL_STOP_BIT, + US_MR_CHMODE_NORMAL + }; + #if SAM4L + sysclk_enable_peripheral_clock(USART_SERIAL); + #else + sysclk_enable_peripheral_clock(USART_SERIAL_ID); + #endif + usart_init_rs232(USART_SERIAL, &usart_console_settings, + sysclk_get_main_hz()); + usart_enable_tx(USART_SERIAL); + usart_enable_rx(USART_SERIAL); +\endcode + * + * \subsection usart_basic_use_case_setup_flow Workflow + * -# Initialize system clock: + * \code + sysclk_init(); +\endcode + * -# Configure the USART Tx and Rx pins by call the board init function: + * \code + board_init(); +\endcode + * \note Set the following define in conf_board.h file to enable COM port,it will be used in + * board_init() function to set up IOPorts for the USART pins. + * For SAM4L: + * \code + #define CONF_BOARD_COM_PORT +\endcode + * For other SAM devices: + * \code + #define CONF_BOARD_UART_CONSOLE +\endcode + * -# Create USART options struct: + * \code + const sam_usart_opt_t usart_console_settings = { + USART_SERIAL_BAUDRATE, + USART_SERIAL_CHAR_LENGTH, + USART_SERIAL_PARITY, + USART_SERIAL_STOP_BIT, + US_MR_CHMODE_NORMAL + }; +\endcode + * -# Enable the clock to the USART module: + * \code + #if SAM4L + sysclk_enable_peripheral_clock(USART_SERIAL); + #else + sysclk_enable_peripheral_clock(USART_SERIAL_ID); + #endif +\endcode + * -# Initialize the USART module in RS232 mode: + * \code + usart_init_rs232(USART_SERIAL, &usart_console_settings, + sysclk_get_main_hz()); +\endcode + * -# Enable the Rx and Tx modes of the USART module: + * \code + usart_enable_tx(USART_SERIAL); + usart_enable_rx(USART_SERIAL); +\endcode + * + * \section usart_basic_use_case_usage Usage steps + * + * \subsection usart_basic_use_case_usage_code Example code + * Add to application C-file: + * \code + usart_putchar(USART_SERIAL, 'a'); +\endcode + * + * \subsection usart_basic_use_case_usage_flow Workflow + * -# Send an 'a' character via USART + * \code usart_putchar(USART_SERIAL, 'a'); \endcode + */ + +/** + * \page usart_use_case_1 USART receive character and echo back + * + * In this use case, the USART module is configured for: + * - Using USART0 + * - Baudrate: 9600 + * - Character length: 8 bit + * - Parity mode: Disabled + * - Stop bit: None + * - RS232 mode + * + * The use case waits for a received character on the configured USART and + * echoes the character back to the same USART. + * + * \section usart_use_case_1_setup Setup steps + * + * \subsection usart_use_case_1_setup_prereq Prerequisites + * -# \ref sysclk_group "System Clock Management (sysclock)" + * -# \ref ioport_group "Common IOPORT API (ioport)" + * + * \subsection usart_use_case_1_setup_code Example code + * The following configuration must be added to the project (typically to a + * conf_usart.h file, but it can also be added to your main application file.): + * \code + #define USART_SERIAL USART0 + #define USART_SERIAL_ID ID_USART0 //USART0 for sam4l + #define USART_SERIAL_BAUDRATE 9600 + #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT + #define USART_SERIAL_PARITY US_MR_PAR_NO + #define USART_SERIAL_STOP_BIT US_MR_NBSTOP_1_BIT +\endcode + * + * A variable for the received byte must be added: + * \code + uint32_t received_byte; +\endcode + * + * Add to application initialization: + * \code + sysclk_init(); + + board_init(); + + const sam_usart_opt_t usart_console_settings = { + USART_SERIAL_BAUDRATE, + USART_SERIAL_CHAR_LENGTH, + USART_SERIAL_PARITY, + USART_SERIAL_STOP_BIT, + US_MR_CHMODE_NORMAL + }; + + #if SAM4L + sysclk_enable_peripheral_clock(USART_SERIAL); + #else + sysclk_enable_peripheral_clock(USART_SERIAL_ID); + #endif + + usart_init_rs232(USART_SERIAL, &usart_console_settings, + sysclk_get_main_hz()); + usart_enable_tx(USART_SERIAL); + usart_enable_rx(USART_SERIAL); +\endcode + * + * \subsection usart_use_case_1_setup_flow Workflow + * -# Initialize system clock: + * \code + sysclk_init(); +\endcode + * -# Configure the USART Tx and Rx pins by call the board init function: + * \code + board_init(); +\endcode + * \note Set the following define in conf_board.h file to enable COM port,it will be used in + * board_init() function to set up IOPorts for the USART pins. + * For SAM4L: + * \code + #define CONF_BOARD_COM_PORT +\endcode + * For other SAM devices: + * \code + #define CONF_BOARD_UART_CONSOLE +\endcode + * -# Create USART options struct: + * \code + const sam_usart_opt_t usart_console_settings = { + USART_SERIAL_BAUDRATE, + USART_SERIAL_CHAR_LENGTH, + USART_SERIAL_PARITY, + USART_SERIAL_STOP_BIT, + US_MR_CHMODE_NORMAL + }; +\endcode + * -# Enable the clock to the USART module: + * \code + #if SAM4L + sysclk_enable_peripheral_clock(USART_SERIAL); + #else + sysclk_enable_peripheral_clock(USART_SERIAL_ID); + #endif +\endcode + * -# Initialize the USART module in RS232 mode: + * \code + usart_init_rs232(USART_SERIAL, &usart_console_settings, + sysclk_get_main_hz()); +\endcode + * -# Enable the Rx and Tx modes of the USART module: + * \code + usart_enable_tx(USART_SERIAL); + usart_enable_rx(USART_SERIAL); +\endcode + * + * \section usart_use_case_1_usage Usage steps + * + * \subsection usart_use_case_1_usage_code Example code + * Add to, e.g., main loop in application C-file: + * \code + received_byte = usart_getchar(USART_SERIAL); + usart_putchar(USART_SERIAL, received_byte); +\endcode + * + * \subsection usart_use_case_1_usage_flow Workflow + * -# Wait for reception of a character: + * \code usart_getchar(USART_SERIAL, &received_byte); \endcode + * -# Echo the character back: + * \code usart_putchar(USART_SERIAL, received_byte); \endcode + */ + +/** + * \page usart_use_case_2 USART receive character and echo back via interrupts + * + * In this use case, the USART module is configured for: + * - Using USART0 + * - Baudrate: 9600 + * - Character length: 8 bit + * - Parity mode: Disabled + * - Stop bit: None + * - RS232 mode + * + * The use case waits for a received character on the configured USART and + * echoes the character back to the same USART. The character reception is + * performed via an interrupt handler, rather than the polling method used + * in \ref usart_use_case_1. + * + * \section usart_use_case_2_setup Setup steps + * + * \subsection usart_use_case_2_setup_prereq Prerequisites + * -# \ref sysclk_group "System Clock Management (sysclock)" + * -# \ref pio_group "Parallel Input/Output Controller (pio)" + * -# \ref pmc_group "Power Management Controller (pmc)" + * + * \subsection usart_use_case_2_setup_code Example code + * The following configuration must be added to the project (typically to a + * conf_usart.h file, but it can also be added to your main application file.): + * \code + #define USART_SERIAL USART0 + #define USART_SERIAL_ID ID_USART0 //USART0 for sam4l + #define USART_SERIAL_ISR_HANDLER USART0_Handler + #define USART_SERIAL_BAUDRATE 9600 + #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT + #define USART_SERIAL_PARITY US_MR_PAR_NO + #define USART_SERIAL_STOP_BIT US_MR_NBSTOP_1_BIT +\endcode + * + * A variable for the received byte must be added: + * \code + uint32_t received_byte; +\endcode + * + * Add to application initialization: + * \code + sysclk_init(); + + board_init(); + + const sam_usart_opt_t usart_console_settings = { + USART_SERIAL_BAUDRATE, + USART_SERIAL_CHAR_LENGTH, + USART_SERIAL_PARITY, + USART_SERIAL_STOP_BIT, + US_MR_CHMODE_NORMAL + }; + + #if SAM4L + sysclk_enable_peripheral_clock(USART_SERIAL); + #else + sysclk_enable_peripheral_clock(USART_SERIAL_ID); + #endif + + usart_init_rs232(USART_SERIAL, &usart_console_settings, + sysclk_get_main_hz()); + usart_enable_tx(USART_SERIAL); + usart_enable_rx(USART_SERIAL); + + usart_enable_interrupt(USART_SERIAL, US_IER_RXRDY); + NVIC_EnableIRQ(USART_SERIAL_IRQ); +\endcode + * + * \subsection usart_use_case_2_setup_flow Workflow + * -# Initialize system clock: + * \code + sysclk_init(); +\endcode + * -# Configure the USART Tx and Rx pins by call the board init function: + * \code + board_init(); +\endcode + * \note Set the following define in conf_board.h file to enable COM port,it will be used in + * board_init() function to set up IOPorts for the USART pins. + * For SAM4L: + * \code + #define CONF_BOARD_COM_PORT +\endcode + * For other SAM devices: + * \code + #define CONF_BOARD_UART_CONSOLE +\endcode + * -# Create USART options struct: + * \code + const sam_usart_opt_t usart_console_settings = { + USART_SERIAL_BAUDRATE, + USART_SERIAL_CHAR_LENGTH, + USART_SERIAL_PARITY, + USART_SERIAL_STOP_BIT, + US_MR_CHMODE_NORMAL + }; +\endcode + * -# Enable the clock to the USART module: + * \code + #if SAM4L + sysclk_enable_peripheral_clock(USART_SERIAL); + #else + sysclk_enable_peripheral_clock(USART_SERIAL_ID); + #endif +\endcode + * -# Initialize the USART module in RS232 mode: + * \code + usart_init_rs232(USART_SERIAL, &usart_console_settings, + sysclk_get_main_hz()); +\endcode + * -# Enable the Rx and Tx modes of the USART module: + * \code + usart_enable_tx(USART_SERIAL); + usart_enable_rx(USART_SERIAL); +\endcode + * -# Enable the USART character reception interrupt, and general interrupts + * for the USART module. + * \code + usart_enable_interrupt(USART_SERIAL, US_IER_RXRDY); + NVIC_EnableIRQ(USART_SERIAL_IRQ); +\endcode + * \section usart_use_case_2_usage Usage steps + * + * \subsection usart_use_case_2_usage_code Example code + * Add to your main application C-file the USART interrupt handler: + * \code + void USART_SERIAL_ISR_HANDLER(void) + { + uint32_t dw_status = usart_get_status(USART_SERIAL); + + if (dw_status & US_CSR_RXRDY) { + uint32_t received_byte; + + usart_read(USART_SERIAL, &received_byte); + usart_write(USART_SERIAL, received_byte); + } + } +\endcode + * + * \subsection usart_use_case_2_usage_flow Workflow + * -# When the USART ISR fires, retrieve the USART module interrupt flags: + * \code uint32_t dw_status = usart_get_status(USART_SERIAL); \endcode + * -# Check if the USART Receive Character interrupt has fired: + * \code if (dw_status & US_CSR_RXRDY) \endcode + * -# If a character has been received, fetch it into a temporary variable: + * \code usart_read(USART_SERIAL, &received_byte); \endcode + * -# Echo the character back: + * \code usart_write(USART_SERIAL, received_byte); \endcode + */ + +#endif /* USART_H_INCLUDED */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/usbhs/usbhs_device.c b/hw-libs/drivers/SAMx70/ASF/sam/drivers/usbhs/usbhs_device.c new file mode 100644 index 000000000..140b4cf2e --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/usbhs/usbhs_device.c @@ -0,0 +1,2209 @@ +/** + * \file + * + * \brief USB Device Driver for USBHS. Compliant with common UDD driver. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "conf_usb.h" +#include "sysclk.h" +#include "udd.h" +#include "usbhs_otg.h" +#include "usbhs_device.h" +#include + +#ifndef UDD_NO_SLEEP_MGR +# include "sleep.h" +# include "sleepmgr.h" +#endif + +#if !(SAMV71 || SAMV70 || SAME70 || SAMS70) +# error The current USBHS Device Driver supports only SAMV71, SAMV70, SAME70 and SAMS70. +#endif +#ifndef UDD_USB_INT_FUN +# define UDD_USB_INT_FUN USBHS_Handler +#endif + +#ifndef UDD_USB_INT_LEVEL +# define UDD_USB_INT_LEVEL 5 // By default USB interrupt have low priority +#endif + +#define UDD_EP_USED(ep) (USB_DEVICE_MAX_EP >= ep) + +#if ( (UDD_EP_USED( 1) && Is_udd_endpoint_dma_supported( 1)) \ + ||(UDD_EP_USED( 2) && Is_udd_endpoint_dma_supported( 2)) \ + ||(UDD_EP_USED( 3) && Is_udd_endpoint_dma_supported( 3)) \ + ||(UDD_EP_USED( 4) && Is_udd_endpoint_dma_supported( 4)) \ + ||(UDD_EP_USED( 5) && Is_udd_endpoint_dma_supported( 5)) \ + ||(UDD_EP_USED( 6) && Is_udd_endpoint_dma_supported( 6)) \ + ||(UDD_EP_USED( 7) && Is_udd_endpoint_dma_supported( 7)) \ + ||(UDD_EP_USED( 8) && Is_udd_endpoint_dma_supported( 8)) \ + ||(UDD_EP_USED( 9) && Is_udd_endpoint_dma_supported( 9)) \ + ||(UDD_EP_USED(10) && Is_udd_endpoint_dma_supported(10)) \ + ||(UDD_EP_USED(11) && Is_udd_endpoint_dma_supported(11)) \ + ||(UDD_EP_USED(12) && Is_udd_endpoint_dma_supported(12)) \ + ||(UDD_EP_USED(13) && Is_udd_endpoint_dma_supported(13)) \ + ||(UDD_EP_USED(14) && Is_udd_endpoint_dma_supported(14)) \ + ||(UDD_EP_USED(15) && Is_udd_endpoint_dma_supported(15)) \ + ) +# define UDD_EP_DMA_SUPPORTED +#endif + +#if ( (UDD_EP_USED( 1) && !Is_udd_endpoint_dma_supported( 1)) \ + ||(UDD_EP_USED( 2) && !Is_udd_endpoint_dma_supported( 2)) \ + ||(UDD_EP_USED( 3) && !Is_udd_endpoint_dma_supported( 3)) \ + ||(UDD_EP_USED( 4) && !Is_udd_endpoint_dma_supported( 4)) \ + ||(UDD_EP_USED( 5) && !Is_udd_endpoint_dma_supported( 5)) \ + ||(UDD_EP_USED( 6) && !Is_udd_endpoint_dma_supported( 6)) \ + ||(UDD_EP_USED( 7) && !Is_udd_endpoint_dma_supported( 7)) \ + ||(UDD_EP_USED( 8) && !Is_udd_endpoint_dma_supported( 8)) \ + ||(UDD_EP_USED( 9) && !Is_udd_endpoint_dma_supported( 9)) \ + ||(UDD_EP_USED(10) && !Is_udd_endpoint_dma_supported(10)) \ + ||(UDD_EP_USED(11) && !Is_udd_endpoint_dma_supported(11)) \ + ||(UDD_EP_USED(12) && !Is_udd_endpoint_dma_supported(12)) \ + ||(UDD_EP_USED(13) && !Is_udd_endpoint_dma_supported(13)) \ + ||(UDD_EP_USED(14) && !Is_udd_endpoint_dma_supported(14)) \ + ||(UDD_EP_USED(15) && !Is_udd_endpoint_dma_supported(15)) \ + ) +# define UDD_EP_FIFO_SUPPORTED +#endif + +// for debug text +//#define dbg_print printf +#define dbg_print(...) + +#ifdef UDD_EP_DMA_SUPPORTED +// for DCache +/** + * \brief Flush content in DCache to physical memory + * \param addr The memory address to flush + * \param dsize The size of the memory + */ +static void _dcache_flush(void *addr, uint32_t dsize) +{ +#ifdef CONF_BOARD_ENABLE_CACHE_AT_INIT + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32U; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) + if (op_addr & (linesize - 1)) { + op_size += op_addr & (linesize - 1); + op_addr &= ~(linesize - 1); + } + __ISB(); + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); +#endif +} + +/** + * \brief Preparation for unaligned buffer invalidation + * \param addr The memory address to invalidate + * \param dsize The size of the memory + */ +static void _dcache_invalidate_prepare(void *addr, uint32_t dsize) +{ +#ifdef CONF_BOARD_ENABLE_CACHE_AT_INIT + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32U; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) + uint32_t addr1 = op_addr; + uint32_t addr2 = op_addr + op_size; + if (addr1 & (linesize - 1) || addr2 & (linesize - 1)) { + addr1 &= ~(linesize - 1); + addr2 &= ~(linesize - 1); + __ISB(); + __DSB(); + SCB->DCCIMVAC = addr1; + SCB->DCCIMVAC = addr2; + __DSB(); + __ISB(); + } +#endif +} + +/** + * \brief Invalidate DCache of physical memory + * \param addr The memory address to invalidate + * \param dsize The size of the memory + */ +static void _dcache_invalidate(void *addr, uint32_t dsize) +{ +#ifdef CONF_BOARD_ENABLE_CACHE_AT_INIT + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32U; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) + if (op_addr & (linesize - 1)) { + op_size += op_addr & (linesize - 1); + op_addr &= ~(linesize - 1); + } + __ISB(); + __DSB(); + + while (op_size > 0) { + /* D-Cache Invalidate by MVA to PoC */ + *(volatile uint32_t *)(0xE000EF5C) = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); +#endif +} +#endif + +/** + * \ingroup udd_group + * \defgroup udd_udphs_group USB High-Speed Port for device mode (USBHS) + * + * \section USBHS_CONF USBHS Custom configuration + * The following USBHS driver configuration must be included in the conf_usb.h + * file of the application. + * + * UDD_USB_INT_LEVEL
+ * Option to change the interrupt priority (0 to 15) by default 5 (recommended). + * + * UDD_USB_INT_FUN
+ * Option to fit interrupt function to what defined in exception table. + * + * UDD_ISOCHRONOUS_NB_BANK(ep)
+ * Feature to reduce or increase isochronous endpoints buffering (1 to 3). + * Default value 2. + * + * UDD_BULK_NB_BANK(ep)
+ * Feature to reduce or increase bulk endpoints buffering (1 to 2). + * Default value 2. + * + * UDD_INTERRUPT_NB_BANK(ep)
+ * Feature to reduce or increase interrupt endpoints buffering (1 to 2). + * Default value 1. + * + * UDD_NO_SLEEP_MGR
+ * Feature to work without sleep manager module. + * Default not defined. + * Note that with this feature defined sleep manager must not be used in + * application. + * + * \section Callbacks management + * The USB driver is fully managed by interrupt and does not request periodique + * task. Thereby, the USB events use callbacks to transfer the information. + * The callbacks are declared in static during compilation or in variable during + * code execution. + * + * Static declarations defined in conf_usb.h: + * - UDC_VBUS_EVENT(bool b_present)
+ * To signal Vbus level change + * - UDC_SUSPEND_EVENT()
+ * Called when USB bus enter in suspend mode + * - UDC_RESUME_EVENT()
+ * Called when USB bus is wakeup + * - UDC_SOF_EVENT()
+ * Called for each received SOF, Note: Each 1ms in HS/FS mode only. + * + * Dynamic callbacks, called "endpoint job" , are registered + * in udd_ep_job_t structure via the following functions: + * - udd_ep_run()
+ * To call it when a transfer is finish + * - udd_ep_wait_stall_clear()
+ * To call it when a endpoint halt is disabled + * + * \section Power mode management + * The Sleep modes authorized : + * - in USB IDLE state, the USBHS needs of USB clock and authorizes up to sleep mode WFI. + * - in USB SUSPEND state, the USBHS no needs USB clock and authorizes up to sleep mode WAIT. + * @{ + */ + +// Check USB Device configuration +#ifndef USB_DEVICE_EP_CTRL_SIZE +# error USB_DEVICE_EP_CTRL_SIZE not defined +#endif +#ifndef USB_DEVICE_MAX_EP +# error USB_DEVICE_MAX_EP not defined +#endif + +// Note: USB_DEVICE_MAX_EP does not include control endpoint +#if USB_DEVICE_MAX_EP > (UDD_MAX_PEP_NB-1) +# error USB_DEVICE_MAX_EP is too high and not supported by this part +#endif + +#define UDD_EP_ISO_NBANK_ERROR(ep) \ + ( (UDD_ISOCHRONOUS_NB_BANK(ep) < 1) \ + || (UDD_ISOCHRONOUS_NB_BANK(ep) > 3) ) +#define UDD_EP_BULK_NBANK_ERROR(ep) \ + ( (UDD_BULK_NB_BANK(ep) < 1) || (UDD_BULK_NB_BANK(ep) > 2) ) +#define UDD_EP_INT_NBANK_ERROR(ep) \ + ( (UDD_INTERRUPT_NB_BANK(ep) < 1) || (UDD_INTERRUPT_NB_BANK(ep) > 2) ) + +#define UDD_EP_ISO_NB_BANK_ERROR(ep) \ + (UDD_EP_USED(ep) && UDD_EP_ISO_NBANK_ERROR(ep)) +#define UDD_EP_BULK_NB_BANK_ERROR(ep) \ + (UDD_EP_USED(ep) && UDD_EP_ISO_NBANK_ERROR(ep)) +#define UDD_EP_INT_NB_BANK_ERROR(ep) \ + (UDD_EP_USED(ep) && UDD_EP_ISO_NBANK_ERROR(ep)) + +#define UDD_EP_NB_BANK_ERROR(ep, type) \ + (ATPASTE3(UDD_EP_, type, _NB_BANK_ERROR(ep))) + +#define UDD_ISO_NB_BANK_ERROR \ + ( UDD_EP_NB_BANK_ERROR( 1, ISO) \ + || UDD_EP_NB_BANK_ERROR( 2, ISO) \ + || UDD_EP_NB_BANK_ERROR( 3, ISO) \ + || UDD_EP_NB_BANK_ERROR( 4, ISO) \ + || UDD_EP_NB_BANK_ERROR( 5, ISO) \ + || UDD_EP_NB_BANK_ERROR( 6, ISO) \ + || UDD_EP_NB_BANK_ERROR( 7, ISO) \ + || UDD_EP_NB_BANK_ERROR( 8, ISO) \ + || UDD_EP_NB_BANK_ERROR( 9, ISO) \ + || UDD_EP_NB_BANK_ERROR(10, ISO) \ + || UDD_EP_NB_BANK_ERROR(11, ISO) \ + || UDD_EP_NB_BANK_ERROR(12, ISO) \ + || UDD_EP_NB_BANK_ERROR(13, ISO) \ + || UDD_EP_NB_BANK_ERROR(14, ISO) \ + || UDD_EP_NB_BANK_ERROR(15, ISO) ) +#define UDD_BULK_NB_BANK_ERROR \ + ( UDD_EP_NB_BANK_ERROR( 1, BULK) \ + || UDD_EP_NB_BANK_ERROR( 2, BULK) \ + || UDD_EP_NB_BANK_ERROR( 3, BULK) \ + || UDD_EP_NB_BANK_ERROR( 4, BULK) \ + || UDD_EP_NB_BANK_ERROR( 5, BULK) \ + || UDD_EP_NB_BANK_ERROR( 6, BULK) \ + || UDD_EP_NB_BANK_ERROR( 7, BULK) \ + || UDD_EP_NB_BANK_ERROR( 8, BULK) \ + || UDD_EP_NB_BANK_ERROR( 9, BULK) \ + || UDD_EP_NB_BANK_ERROR(10, BULK) \ + || UDD_EP_NB_BANK_ERROR(11, BULK) \ + || UDD_EP_NB_BANK_ERROR(12, BULK) \ + || UDD_EP_NB_BANK_ERROR(13, BULK) \ + || UDD_EP_NB_BANK_ERROR(14, BULK) \ + || UDD_EP_NB_BANK_ERROR(15, BULK) ) +#define UDD_INTERRUPT_NB_BANK_ERROR \ + ( UDD_EP_NB_BANK_ERROR( 1, INT) \ + || UDD_EP_NB_BANK_ERROR( 2, INT) \ + || UDD_EP_NB_BANK_ERROR( 3, INT) \ + || UDD_EP_NB_BANK_ERROR( 4, INT) \ + || UDD_EP_NB_BANK_ERROR( 5, INT) \ + || UDD_EP_NB_BANK_ERROR( 6, INT) \ + || UDD_EP_NB_BANK_ERROR( 7, INT) \ + || UDD_EP_NB_BANK_ERROR( 8, INT) \ + || UDD_EP_NB_BANK_ERROR( 9, INT) \ + || UDD_EP_NB_BANK_ERROR(10, INT) \ + || UDD_EP_NB_BANK_ERROR(11, INT) \ + || UDD_EP_NB_BANK_ERROR(12, INT) \ + || UDD_EP_NB_BANK_ERROR(13, INT) \ + || UDD_EP_NB_BANK_ERROR(14, INT) \ + || UDD_EP_NB_BANK_ERROR(15, INT) ) + +#ifndef UDD_ISOCHRONOUS_NB_BANK +# define UDD_ISOCHRONOUS_NB_BANK(ep) 2 +#else +# if UDD_ISO_NB_BANK_ERROR +# error UDD_ISOCHRONOUS_NB_BANK(ep) must be define within 1 to 3. +# endif +#endif + +#ifndef UDD_BULK_NB_BANK +# define UDD_BULK_NB_BANK(ep) 2 +#else +# if UDD_BULK_NB_BANK_ERROR +# error UDD_BULK_NB_BANK must be define with 1 or 2. +# endif +#endif + +#ifndef UDD_INTERRUPT_NB_BANK +# define UDD_INTERRUPT_NB_BANK(ep) 1 +#else +# if UDD_INTERRUPT_NB_BANK_ERROR +# error UDD_INTERRUPT_NB_BANK must be define with 1 or 2. +# endif +#endif + + +/** + * \name Power management routine. + */ +//@{ + +#ifndef UDD_NO_SLEEP_MGR + +//! Definition of sleep levels +#define USBHS_SLEEP_MODE_USB_SUSPEND SLEEPMGR_WAIT_FAST +#define USBHS_SLEEP_MODE_USB_IDLE SLEEPMGR_SLEEP_WFI + +//! State of USB line +static bool udd_b_idle; +//! State of sleep manager +static bool udd_b_sleep_initialized = false; + + +/*! \brief Authorize or not the CPU powerdown mode + * + * \param b_idle true to authorize idle mode + */ +static void udd_sleep_mode(bool b_idle) +{ + if (!b_idle && udd_b_idle) { + dbg_print("_S "); + sleepmgr_unlock_mode(USBHS_SLEEP_MODE_USB_IDLE); + } + if (b_idle && !udd_b_idle) { + dbg_print("_W "); + sleepmgr_lock_mode(USBHS_SLEEP_MODE_USB_IDLE); + } + udd_b_idle = b_idle; +} +#else + +static void udd_sleep_mode(bool b_idle) +{ + b_idle = b_idle; +} + +#endif // UDD_NO_SLEEP_MGR + +//@} + +/** + * \name VBus monitor routine + */ +//@{ +#if OTG_VBUS_IO + +# if !defined(UDD_NO_SLEEP_MGR) && !defined(USB_VBUS_WKUP) +/* Lock to SLEEPMGR_SLEEP_WFI if VBus not connected */ +static bool b_vbus_sleep_lock = false; +/** + * Lock sleep mode for VBus PIO pin change detection + */ +static void udd_vbus_monitor_sleep_mode(bool b_lock) +{ + if (b_lock && !b_vbus_sleep_lock) { + b_vbus_sleep_lock = true; + sleepmgr_lock_mode(SLEEPMGR_SLEEP_WFI); + } + if (!b_lock && b_vbus_sleep_lock) { + b_vbus_sleep_lock = false; + sleepmgr_unlock_mode(SLEEPMGR_SLEEP_WFI); + } +} +# else +# define udd_vbus_monitor_sleep_mode(lock) +# endif + +/** + * USB VBus pin change handler + */ +static void udd_vbus_handler(uint32_t id, uint32_t mask) +{ + /* PIO interrupt status has been cleared, just detect level */ + bool b_vbus_high = Is_otg_vbus_high(); + if (b_vbus_high) { + udd_vbus_monitor_sleep_mode(false); + udd_attach(); + } else { + udd_vbus_monitor_sleep_mode(true); + udd_detach(); + } + UDC_VBUS_EVENT(b_vbus_high); +} + +#endif +//@} + +/** + * \name Control endpoint low level management routine. + * + * This function performs control endpoint mangement. + * It handle the SETUP/DATA/HANDSHAKE phases of a control transaction. + */ +//@{ + +//! Global variable to give and record information about setup request management +COMPILER_WORD_ALIGNED udd_ctrl_request_t udd_g_ctrlreq; + +//! Bit definitions about endpoint control state machine for udd_ep_control_state +typedef enum { + UDD_EPCTRL_SETUP = 0, //!< Wait a SETUP packet + UDD_EPCTRL_DATA_OUT = 1, //!< Wait a OUT data packet + UDD_EPCTRL_DATA_IN = 2, //!< Wait a IN data packet + UDD_EPCTRL_HANDSHAKE_WAIT_IN_ZLP = 3, //!< Wait a IN ZLP packet + UDD_EPCTRL_HANDSHAKE_WAIT_OUT_ZLP = 4, //!< Wait a OUT ZLP packet + UDD_EPCTRL_STALL_REQ = 5, //!< STALL enabled on IN & OUT packet +} udd_ctrl_ep_state_t; + +//! State of the endpoint control management +static udd_ctrl_ep_state_t udd_ep_control_state; + +//! Total number of data received/sent during data packet phase with previous payload buffers +static uint16_t udd_ctrl_prev_payload_buf_cnt; + +//! Number of data received/sent to/from udd_g_ctrlreq.payload buffer +static uint16_t udd_ctrl_payload_buf_cnt; + +/** + * \brief Reset control endpoint + * + * Called after a USB line reset or when UDD is enabled + */ +static void udd_reset_ep_ctrl(void); + +/** + * \brief Reset control endpoint management + * + * Called after a USB line reset or at the end of SETUP request (after ZLP) + */ +static void udd_ctrl_init(void); + +//! \brief Managed reception of SETUP packet on control endpoint +static void udd_ctrl_setup_received(void); + +//! \brief Managed reception of IN packet on control endpoint +static void udd_ctrl_in_sent(void); + +//! \brief Managed reception of OUT packet on control endpoint +static void udd_ctrl_out_received(void); + +//! \brief Managed underflow event of IN packet on control endpoint +static void udd_ctrl_underflow(void); + +//! \brief Managed overflow event of OUT packet on control endpoint +static void udd_ctrl_overflow(void); + +//! \brief Managed stall event of IN/OUT packet on control endpoint +static void udd_ctrl_stall_data(void); + +//! \brief Send a ZLP IN on control endpoint +static void udd_ctrl_send_zlp_in(void); + +//! \brief Send a ZLP OUT on control endpoint +static void udd_ctrl_send_zlp_out(void); + +//! \brief Call callback associated to setup request +static void udd_ctrl_endofrequest(void); + + +/** + * \brief Main interrupt routine for control endpoint + * + * This switchs control endpoint events to correct sub function. + * + * \return \c 1 if an event about control endpoint is occured, otherwise \c 0. + */ +static bool udd_ctrl_interrupt(void); + +//@} + + +/** + * \name Management of bulk/interrupt/isochronous endpoints + * + * The UDD manages the data transfer on endpoints: + * - Start data tranfer on endpoint with USB Device DMA + * - Send a ZLP packet if requested + * - Call callback registered to signal end of transfer + * The transfer abort and stall feature are supported. + */ +//@{ +#if (0!=USB_DEVICE_MAX_EP) + +//! Structure definition about job registered on an endpoint +typedef struct { + union { + //! Callback to call at the end of transfer + udd_callback_trans_t call_trans; + + //! Callback to call when the endpoint halt is cleared + udd_callback_halt_cleared_t call_nohalt; + }; + //! Buffer located in internal RAM to send or fill during job + uint8_t *buf; + //! Size of buffer to send or fill + iram_size_t buf_size; + //!< Size of data transfered + iram_size_t buf_cnt; + //!< Size of data loaded (or prepared for DMA) last time + iram_size_t buf_load; + //! A job is registered on this endpoint + uint8_t busy:1; + //! A short packet is requested for this job on endpoint IN + uint8_t b_shortpacket:1; + //! A stall has been requested but not executed + uint8_t stall_requested:1; +} udd_ep_job_t; + + +//! Array to register a job on bulk/interrupt/isochronous endpoint +static udd_ep_job_t udd_ep_job[USB_DEVICE_MAX_EP]; + +//! \brief Reset all job table +static void udd_ep_job_table_reset(void); + +//! \brief Abort all endpoint jobs on going +static void udd_ep_job_table_kill(void); + +#ifdef UDD_EP_FIFO_SUPPORTED + /** + * \brief Fill banks and send them + * + * \param ep endpoint number of job to abort + */ + static void udd_ep_in_sent(udd_ep_id_t ep); + + /** + * \brief Store received banks + * + * \param ep endpoint number of job to abort + */ + static void udd_ep_out_received(udd_ep_id_t ep); +#endif + +/** + * \brief Abort endpoint job on going + * + * \param ep endpoint number of job to abort + */ +static void udd_ep_abort_job(udd_ep_id_t ep); + +/** + * \brief Call the callback associated to the job which is finished + * + * \param ptr_job job to complete + * \param b_abort if true then the job has been aborted + */ +static void udd_ep_finish_job(udd_ep_job_t * ptr_job, bool b_abort, uint8_t ep_num); + +#ifdef UDD_EP_DMA_SUPPORTED + /** + * \brief Start the next transfer if necessary or complet the job associated. + * + * \param ep endpoint number without direction flag + */ + static void udd_ep_trans_done(udd_ep_id_t ep); +#endif + +/** + * \brief Main interrupt routine for bulk/interrupt/isochronous endpoints + * + * This switchs endpoint events to correct sub function. + * + * \return \c 1 if an event about bulk/interrupt/isochronous endpoints has occured, otherwise \c 0. + */ +static bool udd_ep_interrupt(void); + +#endif // (0!=USB_DEVICE_MAX_EP) +//@} + + +//-------------------------------------------------------- +//--- INTERNAL ROUTINES TO MANAGED GLOBAL EVENTS + +/** + * \internal + * \brief Function called by USBHS interrupt to manage USB Device interrupts + * + * USB Device interrupt events are splited in three parts: + * - USB line events (SOF, reset, suspend, resume, wakeup) + * - control endpoint events (setup reception, end of data transfer, underflow, overflow, stall) + * - bulk/interrupt/isochronous endpoints events (end of data transfer) + * + * Note: + * Here, the global interrupt mask is not clear when an USB interrupt is enabled + * because this one can not be occured during the USB ISR (=during INTX is masked). + * See Technical reference $3.8.3 Masking interrupt requests in peripheral modules. + */ +#ifdef UHD_ENABLE +void udd_interrupt(void); +void udd_interrupt(void) +#else +ISR(UDD_USB_INT_FUN) +#endif +{ +#ifndef UDD_NO_SLEEP_MGR + /* For fast wakeup clocks restore + * In WAIT mode, clocks are switched to FASTRC. + * After wakeup clocks should be restored, before that ISR should not + * be served. + */ + if (!pmc_is_wakeup_clocks_restored() && !Is_udd_suspend()) { + cpu_irq_disable(); + return; + } +#endif + if (Is_udd_sof()) { + udd_ack_sof(); + if (Is_udd_full_speed_mode()) { + udc_sof_notify(); + } +#ifdef UDC_SOF_EVENT + UDC_SOF_EVENT(); +#endif + goto udd_interrupt_sof_end; + } + + if (Is_udd_msof()) { + udd_ack_msof(); + udc_sof_notify(); + goto udd_interrupt_sof_end; + } + + dbg_print("%c ", udd_is_high_speed() ? 'H' : 'F'); + + if (udd_ctrl_interrupt()) { + goto udd_interrupt_end; // Interrupt acked by control endpoint managed + } + +#if (0 != USB_DEVICE_MAX_EP) + if (udd_ep_interrupt()) { + goto udd_interrupt_end; // Interrupt acked by bulk/interrupt/isochronous endpoint managed + } +#endif + + // USB bus reset detection + if (Is_udd_reset()) { + udd_ack_reset(); + dbg_print("RST "); + // Abort all jobs on-going +#if (USB_DEVICE_MAX_EP != 0) + udd_ep_job_table_kill(); +#endif + // Reset USB Device Stack Core + udc_reset(); + // Reset endpoint control + udd_reset_ep_ctrl(); + // Reset endpoint control management + udd_ctrl_init(); + goto udd_interrupt_end; + } + + if (Is_udd_suspend_interrupt_enabled() && Is_udd_suspend()) { + otg_unfreeze_clock(); + // The suspend interrupt is automatic acked when a wakeup occur + udd_disable_suspend_interrupt(); + udd_enable_wake_up_interrupt(); + otg_freeze_clock(); // Mandatory to exit of sleep mode after a wakeup event + udd_sleep_mode(false); // Enter in SUSPEND mode +#ifdef UDC_SUSPEND_EVENT + UDC_SUSPEND_EVENT(); +#endif + goto udd_interrupt_end; + } + + if (Is_udd_wake_up_interrupt_enabled() && Is_udd_wake_up()) { + // Ack wakeup interrupt and enable suspend interrupt + otg_unfreeze_clock(); + // Check USB clock ready after suspend and eventually sleep USB clock + while (!Is_otg_clock_usable()) { + if (Is_udd_suspend()) { + break; // In case of USB state change in HS + } + }; + // The wakeup interrupt is automatic acked when a suspend occur + udd_disable_wake_up_interrupt(); + udd_enable_suspend_interrupt(); + udd_sleep_mode(true); // Enter in IDLE mode +#ifdef UDC_RESUME_EVENT + UDC_RESUME_EVENT(); +#endif + goto udd_interrupt_end; + } + +udd_interrupt_end: + dbg_print("\n\r"); +udd_interrupt_sof_end: + return; +} + + +bool udd_include_vbus_monitoring(void) +{ +#if OTG_VBUS_IO + return true; +#else + return false; +#endif +} + + +void udd_enable(void) +{ + irqflags_t flags; + + flags = cpu_irq_save(); + +#ifdef UHD_ENABLE + // DUAL ROLE INITIALIZATION + if (otg_dual_enable()) { + // The current mode has been started by otg_dual_enable() + cpu_irq_restore(flags); + return; + } +#else + // SINGLE DEVICE MODE INITIALIZATION + /* Enable peripheral clock for USBHS */ + pmc_enable_periph_clk(ID_USBHS); + + sysclk_enable_usb(); + + // Here, only the device mode is possible, then link USBHS interrupt to UDD interrupt + NVIC_SetPriority((IRQn_Type) ID_USBHS, UDD_USB_INT_LEVEL); + NVIC_EnableIRQ((IRQn_Type) ID_USBHS); + + // Always authorize asynchrone USB interrupts to exit of sleep mode + // For SAM USB wake up device except BACKUP mode + pmc_set_fast_startup_input(PMC_FSMR_USBAL); +#endif + +#if (OTG_ID_IO) && (defined UHD_ENABLE) + // Check that the device mode is selected by ID pin + if (!Is_otg_id_device()) { + cpu_irq_restore(flags); + return; // Device is not the current mode + } +#else + // ID pin not used then force device mode + USBHS->USBHS_CTRL = USBHS_CTRL_UIMOD_DEVICE; +#endif + // Enable USB hardware + otg_enable(); + + // Set the USB speed requested by configuration file +#ifdef USB_DEVICE_LOW_SPEED + udd_low_speed_enable(); +#else + udd_low_speed_disable(); +#ifdef USB_DEVICE_HS_SUPPORT + udd_high_speed_enable(); +#else + udd_high_speed_disable(); +#endif +#endif // USB_DEVICE_LOW_SPEED + + otg_unfreeze_clock(); + // Check USB clock + while (!Is_otg_clock_usable()); + + // Reset internal variables +#if (0!=USB_DEVICE_MAX_EP) + udd_ep_job_table_reset(); +#endif + + otg_freeze_clock(); + +#ifndef UDD_NO_SLEEP_MGR + if (!udd_b_sleep_initialized) { + udd_b_sleep_initialized = true; + // Initialize the sleep mode authorized for the USB suspend mode + udd_b_idle = false; + sleepmgr_lock_mode(USBHS_SLEEP_MODE_USB_SUSPEND); + } else { + udd_sleep_mode(false); // Enter idle mode + } +#endif + +#if OTG_VBUS_IO + /* Initialize VBus monitor */ + otg_vbus_init(udd_vbus_handler); + udd_vbus_monitor_sleep_mode(true); + /* Force VBus interrupt when VBus is always high + * This is possible due to a short timing between a Host mode stop/start. + */ + if (Is_otg_vbus_high()) { + udd_vbus_handler(USB_VBUS_PIO_ID, USB_VBUS_PIO_MASK); + } +#else + udd_attach(); +#endif + + cpu_irq_restore(flags); +} + + +void udd_disable(void) +{ + irqflags_t flags; + +#ifdef UHD_ENABLE +# if OTG_ID_IO + if (Is_otg_id_host()) { + // Freeze clock to switch mode + otg_freeze_clock(); + udd_detach(); + otg_disable(); + return; // Host mode running, ignore UDD disable + } +# else + if (Is_otg_host_mode_forced()) { + return; // Host mode running, ignore UDD disable + } +#endif +#endif + + flags = cpu_irq_save(); + otg_unfreeze_clock(); + udd_detach(); +#ifndef UDD_NO_SLEEP_MGR + if (udd_b_sleep_initialized) { + udd_b_sleep_initialized = false; + sleepmgr_unlock_mode(USBHS_SLEEP_MODE_USB_SUSPEND); + } +#endif + +#ifndef UHD_ENABLE + otg_disable(); + sysclk_disable_usb(); + pmc_disable_periph_clk(ID_USBHS); + // Else the USB clock disable is done by UHC which manage USB dual role +#endif + cpu_irq_restore(flags); +} + + +void udd_attach(void) +{ + irqflags_t flags; + flags = cpu_irq_save(); + + // At startup the USB bus state is unknown, + // therefore the state is considered IDLE to not miss any USB event + udd_sleep_mode(true); + otg_unfreeze_clock(); + + // This section of clock check can be improved with a chek of + // USB clock source via sysclk() + // Check USB clock because the source can be a PLL + while (!Is_otg_clock_usable()); + + // Authorize attach if Vbus is present + udd_attach_device(); + + // Enable USB line events + udd_enable_reset_interrupt(); + udd_enable_suspend_interrupt(); + udd_enable_wake_up_interrupt(); + udd_enable_sof_interrupt(); +#ifdef USB_DEVICE_HS_SUPPORT + udd_enable_msof_interrupt(); +#endif + // Reset following interupts flag + udd_ack_reset(); + udd_ack_sof(); + udd_ack_msof(); + + // The first suspend interrupt must be forced + // The first suspend interrupt is not detected else raise it + udd_raise_suspend(); + + udd_ack_wake_up(); + otg_freeze_clock(); + cpu_irq_restore(flags); +} + + +void udd_detach(void) +{ + otg_unfreeze_clock(); + + // Detach device from the bus + udd_detach_device(); + otg_freeze_clock(); + udd_sleep_mode(false); +} + + +bool udd_is_high_speed(void) +{ +#ifdef USB_DEVICE_HS_SUPPORT + return !Is_udd_full_speed_mode(); +#else + return false; +#endif +} + + +void udd_set_address(uint8_t address) +{ + udd_disable_address(); + udd_configure_address(address); + udd_enable_address(); +} + + +uint8_t udd_getaddress(void) +{ + return udd_get_configured_address(); +} + + +uint16_t udd_get_frame_number(void) +{ + return udd_frame_number(); +} + +uint16_t udd_get_micro_frame_number(void) +{ + return udd_micro_frame_number(); +} + +void udd_send_remotewakeup(void) +{ +#ifndef UDD_NO_SLEEP_MGR + if (!udd_b_idle) +#endif + { + udd_sleep_mode(true); // Enter in IDLE mode + otg_unfreeze_clock(); + udd_initiate_remote_wake_up(); + } +} + + +void udd_set_setup_payload(uint8_t *payload, uint16_t payload_size) +{ + udd_g_ctrlreq.payload = payload; + udd_g_ctrlreq.payload_size = payload_size; +} + + +#if (0 != USB_DEVICE_MAX_EP) +bool udd_ep_alloc(udd_ep_id_t ep, uint8_t bmAttributes, + uint16_t MaxEndpointSize) +{ + bool b_dir_in; + uint16_t ep_allocated; + uint8_t nb_bank, bank, i; + + b_dir_in = ep & USB_EP_DIR_IN; + ep = ep & USB_EP_ADDR_MASK; + + if (ep > USB_DEVICE_MAX_EP) { + return false; + } + if (Is_udd_endpoint_enabled(ep)) { + return false; + } + dbg_print("alloc(%x, %d) ", ep, MaxEndpointSize); + + // Bank choise + switch (bmAttributes & USB_EP_TYPE_MASK) { + case USB_EP_TYPE_ISOCHRONOUS: + nb_bank = UDD_ISOCHRONOUS_NB_BANK(ep); + break; + case USB_EP_TYPE_INTERRUPT: + nb_bank = UDD_INTERRUPT_NB_BANK(ep); + break; + case USB_EP_TYPE_BULK: + nb_bank = UDD_BULK_NB_BANK(ep); + break; + default: + Assert(false); + return false; + } + switch (nb_bank) { + case 1: + bank = USBHS_DEVEPTCFG_EPBK_1_BANK >> + USBHS_DEVEPTCFG_EPBK_Pos; + break; + case 2: + bank = USBHS_DEVEPTCFG_EPBK_2_BANK >> + USBHS_DEVEPTCFG_EPBK_Pos; + break; + case 3: + bank = USBHS_DEVEPTCFG_EPBK_3_BANK >> + USBHS_DEVEPTCFG_EPBK_Pos; + break; + default: + Assert(false); + return false; + } + + // Check if endpoint size is 8,16,32,64,128,256,512 or 1023 + Assert(MaxEndpointSize < 1024); + Assert((MaxEndpointSize == 1023) + || !(MaxEndpointSize & (MaxEndpointSize - 1))); + Assert(MaxEndpointSize >= 8); + + // Set configuration of new endpoint + udd_configure_endpoint(ep, bmAttributes, (b_dir_in ? 1 : 0), + MaxEndpointSize, bank); + ep_allocated = 1 << ep; + + // Unalloc endpoints superior + for (i = USB_DEVICE_MAX_EP; i > ep; i--) { + if (Is_udd_endpoint_enabled(i)) { + ep_allocated |= 1 << i; + udd_disable_endpoint(i); + udd_unallocate_memory(i); + } + } + + // Realloc/Enable endpoints + for (i = ep; i <= USB_DEVICE_MAX_EP; i++) { + if (ep_allocated & (1 << i)) { + udd_ep_job_t *ptr_job = &udd_ep_job[i - 1]; + bool b_restart = ptr_job->busy; + // Restart running job because + // memory window slides up and its data is lost + ptr_job->busy = false; + // Re-allocate memory + udd_allocate_memory(i); + udd_enable_endpoint(i); + if (!Is_udd_endpoint_configured(i)) { + dbg_print("ErrRealloc%d ", i); + if (NULL == ptr_job->call_trans) { + return false; + } + if (Is_udd_endpoint_in(i)) { + i |= USB_EP_DIR_IN; + } + ptr_job->call_trans(UDD_EP_TRANSFER_ABORT, + ptr_job->buf_cnt, i); + return false; + } + udd_enable_endpoint_bank_autoswitch(i); + if (b_restart) { + // Re-run the job remaining part +# ifdef UDD_EP_FIFO_SUPPORTED + if (!Is_udd_endpoint_dma_supported(i) + && !Is_udd_endpoint_in(i)) { + ptr_job->buf_cnt -= ptr_job->buf_load; + } +# else + ptr_job->buf_cnt -= ptr_job->buf_load; +# endif + b_restart = udd_ep_run(Is_udd_endpoint_in(i) ? + (i | USB_EP_DIR_IN) : i, + ptr_job->b_shortpacket, + &ptr_job->buf[ptr_job->buf_cnt], + ptr_job->buf_size + - ptr_job->buf_cnt, + ptr_job->call_trans); + if (!b_restart) { + dbg_print("ErrReRun%d ", i); + return false; + } + } + } + } + return true; +} + + +void udd_ep_free(udd_ep_id_t ep) +{ + uint8_t ep_index = ep & USB_EP_ADDR_MASK; + if (USB_DEVICE_MAX_EP < ep_index) { + return; + } + udd_disable_endpoint(ep_index); + udd_unallocate_memory(ep_index); + udd_ep_abort_job(ep); + udd_ep_job[ep_index - 1].stall_requested = false; +} + + +bool udd_ep_is_halted(udd_ep_id_t ep) +{ + uint8_t ep_index = ep & USB_EP_ADDR_MASK; + return Is_udd_endpoint_stall_requested(ep_index); +} + + +bool udd_ep_set_halt(udd_ep_id_t ep) +{ + uint8_t ep_index = ep & USB_EP_ADDR_MASK; + udd_ep_job_t *ptr_job = &udd_ep_job[ep_index - 1]; + irqflags_t flags; + + if (USB_DEVICE_MAX_EP < ep_index) { + return false; + } + + if (Is_udd_endpoint_stall_requested(ep_index) // Endpoint stalled + || ptr_job->stall_requested) { // Endpoint stall is requested + return true; // Already STALL + } + + if (ptr_job->busy == true) { + return false; // Job on going, stall impossible + } + + flags = cpu_irq_save(); + if ((ep & USB_EP_DIR_IN) && (0 != udd_nb_busy_bank(ep_index))) { + // Delay the stall after the end of IN transfer on USB line + ptr_job->stall_requested = true; +#ifdef UDD_EP_FIFO_SUPPORTED + udd_disable_in_send_interrupt(ep_index); + udd_enable_endpoint_bank_autoswitch(ep_index); +#endif + udd_enable_bank_interrupt(ep_index); + udd_enable_endpoint_interrupt(ep_index); + cpu_irq_restore(flags); + return true; + } + // Stall endpoint immediately + udd_disable_endpoint_bank_autoswitch(ep_index); + udd_ack_stall(ep_index); + udd_enable_stall_handshake(ep_index); + cpu_irq_restore(flags); + return true; +} + + +bool udd_ep_clear_halt(udd_ep_id_t ep) +{ + uint8_t ep_index = ep & USB_EP_ADDR_MASK; + udd_ep_job_t *ptr_job = &udd_ep_job[ep_index - 1]; + bool b_stall_cleared = false; + + if (USB_DEVICE_MAX_EP < ep_index) + return false; + + if (ptr_job->stall_requested) { + // Endpoint stall has been requested but not done + // Remove stall request + ptr_job->stall_requested = false; + udd_disable_bank_interrupt(ep_index); + udd_disable_endpoint_interrupt(ep_index); + b_stall_cleared = true; + } + if (Is_udd_endpoint_stall_requested(ep_index)) { + if (Is_udd_stall(ep_index)) { + udd_ack_stall(ep_index); + // A packet has been stalled + // then reset datatoggle + udd_reset_data_toggle(ep_index); + } + // Disable stall + udd_disable_stall_handshake(ep_index); + udd_enable_endpoint_bank_autoswitch(ep_index); + b_stall_cleared = true; + } + if (b_stall_cleared) { + // If a job is register on clear halt action + // then execute callback + if (ptr_job->busy == true) { + ptr_job->busy = false; + ptr_job->call_nohalt(); + } + } + return true; +} + + +bool udd_ep_run(udd_ep_id_t ep, bool b_shortpacket, + uint8_t * buf, iram_size_t buf_size, + udd_callback_trans_t callback) +{ + bool b_dir_in = Is_udd_endpoint_in(ep & USB_EP_ADDR_MASK); + udd_ep_job_t *ptr_job; + irqflags_t flags; + + ep &= USB_EP_ADDR_MASK; + if (USB_DEVICE_MAX_EP < ep) { + return false; + } + + // Get job about endpoint + ptr_job = &udd_ep_job[ep - 1]; + + if ((!Is_udd_endpoint_enabled(ep)) + || Is_udd_endpoint_stall_requested(ep) + || ptr_job->stall_requested) { + return false; // Endpoint is halted + } + + flags = cpu_irq_save(); + if (ptr_job->busy == true) { + cpu_irq_restore(flags); + return false; // Job already on going + } + ptr_job->busy = true; + cpu_irq_restore(flags); + + // No job running. Let's setup a new one. + ptr_job->buf = buf; + ptr_job->buf_size = buf_size; + ptr_job->buf_cnt = 0; + ptr_job->buf_load = 0; + ptr_job->call_trans = callback; + ptr_job->b_shortpacket = b_shortpacket || (buf_size == 0); + +#ifdef UDD_EP_FIFO_SUPPORTED + // No DMA support + if (!Is_udd_endpoint_dma_supported(ep)) { + dbg_print("ex%x.%c%d\n\r", ep, b_dir_in ? 'i':'o', buf_size); + flags = cpu_irq_save(); + udd_enable_endpoint_interrupt(ep); + if (b_dir_in) { + udd_disable_endpoint_bank_autoswitch(ep); + udd_enable_in_send_interrupt(ep); + } else { + udd_disable_endpoint_bank_autoswitch(ep); + udd_enable_out_received_interrupt(ep); + } + cpu_irq_restore(flags); + return true; + } +#endif // UDD_EP_FIFO_SUPPORTED + +#ifdef UDD_EP_DMA_SUPPORTED + // Request first DMA transfer + dbg_print("(exDMA%x) ", ep); + if (buf && buf_size) { + if (!b_dir_in) { + _dcache_invalidate_prepare(buf, buf_size); + } else { + _dcache_flush(buf, buf_size); + } + } + udd_ep_trans_done(ep); + return true; +#endif +} + + +void udd_ep_abort(udd_ep_id_t ep) +{ + uint8_t ep_index = ep & USB_EP_ADDR_MASK; + +#ifdef UDD_EP_FIFO_SUPPORTED + if (!Is_udd_endpoint_dma_supported(ep_index)) { + // Disable interrupts + udd_disable_endpoint_interrupt(ep_index); + udd_disable_out_received_interrupt(ep_index); + udd_disable_in_send_interrupt(ep_index); + } else +#endif + { + // Stop DMA transfer + udd_disable_endpoint_dma_interrupt(ep_index); + udd_endpoint_dma_set_control(ep_index, 0); + } + udd_disable_endpoint_interrupt(ep_index); + // Kill IN banks + __DSB(); + __ISB(); + if (ep & USB_EP_DIR_IN) { + while(udd_nb_busy_bank(ep_index)) { + udd_kill_last_in_bank(ep_index); + while(Is_udd_kill_last(ep_index)); + } + } + udd_ep_abort_job(ep); +} + + +bool udd_ep_wait_stall_clear(udd_ep_id_t ep, + udd_callback_halt_cleared_t callback) +{ + udd_ep_job_t *ptr_job; + + ep &= USB_EP_ADDR_MASK; + if (USB_DEVICE_MAX_EP < ep) { + return false; + } + + ptr_job = &udd_ep_job[ep - 1]; + + if (!Is_udd_endpoint_enabled(ep)) { + return false; // Endpoint not enabled + } + + // Wait clear halt endpoint + if (ptr_job->busy == true) { + return false; // Job already on going + } + + if (Is_udd_endpoint_stall_requested(ep) + || ptr_job->stall_requested) { + // Endpoint halted then registes the callback + ptr_job->busy = true; + ptr_job->call_nohalt = callback; + } else { + // endpoint not halted then call directly callback + callback(); + } + return true; +} +#endif // (0 != USB_DEVICE_MAX_EP) + + +#ifdef USB_DEVICE_HS_SUPPORT + +void udd_test_mode_j(void) +{ + udd_enable_hs_test_mode(); + udd_enable_hs_test_mode_j(); +} + + +void udd_test_mode_k(void) +{ + udd_enable_hs_test_mode(); + udd_enable_hs_test_mode_k(); +} + + +void udd_test_mode_se0_nak(void) +{ + udd_enable_hs_test_mode(); +} + + +void udd_test_mode_packet(void) +{ + uint8_t i; + uint8_t *ptr_dest; + const uint8_t *ptr_src; + + const uint8_t test_packet[] = { + // 00000000 * 9 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + // 01010101 * 8 + 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, + // 01110111 * 8 + 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, + // 0, {111111S * 15}, 111111 + 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, + // S, 111111S, {0111111S * 7} + 0x7F, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD, + // 00111111, {S0111111 * 9}, S0 + 0xFC, 0x7E, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD, 0x7E + }; + + // Reconfigure control endpoint to bulk IN endpoint + udd_disable_endpoint(0); + udd_configure_endpoint(0, USB_EP_TYPE_BULK, 1, + 64, USBHS_DEVEPTCFG_EPBK_1_BANK); + udd_allocate_memory(0); + udd_enable_endpoint(0); + + udd_enable_hs_test_mode(); + udd_enable_hs_test_mode_packet(); + + // Send packet on endpoint 0 + ptr_dest = (uint8_t *) & udd_get_endpoint_fifo_access(0, 8); + ptr_src = test_packet; + + for (i = 0; i < sizeof(test_packet); i++) { + *ptr_dest++ = *ptr_src++; + } + udd_ack_fifocon(0); +} +#endif // USB_DEVICE_HS_SUPPORT + + + +//-------------------------------------------------------- +//--- INTERNAL ROUTINES TO MANAGED THE CONTROL ENDPOINT + +static void udd_reset_ep_ctrl(void) +{ + irqflags_t flags; + + // Reset USB address to 0 + udd_configure_address(0); + udd_enable_address(); + + // Alloc and configure control endpoint + udd_configure_endpoint(0, + USB_EP_TYPE_CONTROL, + 0, + USB_DEVICE_EP_CTRL_SIZE, + USBHS_DEVEPTCFG_EPBK_1_BANK); + + udd_allocate_memory(0); + udd_enable_endpoint(0); + flags = cpu_irq_save(); + udd_enable_setup_received_interrupt(0); + udd_enable_out_received_interrupt(0); + udd_enable_endpoint_interrupt(0); + cpu_irq_restore(flags); +} + +static void udd_ctrl_init(void) +{ + irqflags_t flags; + flags = cpu_irq_save(); + + // In case of abort of IN Data Phase: + // No need to abort IN transfer (rise TXINI), + // because it is automatically done by hardware when a Setup packet is received. + // But the interrupt must be disabled to don't generate interrupt TXINI + // after SETUP reception. + udd_disable_in_send_interrupt(0); + cpu_irq_restore(flags); + + // In case of OUT ZLP event is no processed before Setup event occurs + udd_ack_out_received(0); + + udd_g_ctrlreq.callback = NULL; + udd_g_ctrlreq.over_under_run = NULL; + udd_g_ctrlreq.payload_size = 0; + udd_ep_control_state = UDD_EPCTRL_SETUP; +} + + +static void udd_ctrl_setup_received(void) +{ + irqflags_t flags; + uint8_t i; + + if (UDD_EPCTRL_SETUP != udd_ep_control_state) { + // May be a hidden DATA or ZLP phase or protocol abort + udd_ctrl_endofrequest(); + + // Reinitializes control endpoint management + udd_ctrl_init(); + } + // Fill setup request structure + if (8 != udd_byte_count(0)) { + udd_ctrl_stall_data(); + udd_ack_setup_received(0); + return; // Error data number doesn't correspond to SETUP packet + } + + uint16_t nb_data = udd_byte_count(0); + volatile uint8_t *ptr = (uint8_t *) & udd_get_endpoint_fifo_access(0,8); + for (i = 0; i < nb_data; i++) { + ((uint8_t*) &udd_g_ctrlreq.req)[i] = *ptr++; + } + // Manage LSB/MSB to fit with CPU usage + udd_g_ctrlreq.req.wValue = le16_to_cpu(udd_g_ctrlreq.req.wValue); + udd_g_ctrlreq.req.wIndex = le16_to_cpu(udd_g_ctrlreq.req.wIndex); + udd_g_ctrlreq.req.wLength = le16_to_cpu(udd_g_ctrlreq.req.wLength); + + // Decode setup request + if (udc_process_setup() == false) { + // Setup request unknow then stall it + udd_ctrl_stall_data(); + udd_ack_setup_received(0); + return; + } + udd_ack_setup_received(0); + + if (Udd_setup_is_in()) { + // IN data phase requested + udd_ctrl_prev_payload_buf_cnt = 0; + udd_ctrl_payload_buf_cnt = 0; + udd_ep_control_state = UDD_EPCTRL_DATA_IN; + udd_ctrl_in_sent(); // Send first data transfer + } else { + if (0 == udd_g_ctrlreq.req.wLength) { + // No data phase requested + // Send IN ZLP to ACK setup request + udd_ctrl_send_zlp_in(); + return; + } + // OUT data phase requested + udd_ctrl_prev_payload_buf_cnt = 0; + udd_ctrl_payload_buf_cnt = 0; + udd_ep_control_state = UDD_EPCTRL_DATA_OUT; + // To detect a protocol error, enable nak interrupt on data IN phase + udd_ack_nak_in(0); + flags = cpu_irq_save(); + udd_enable_nak_in_interrupt(0); + cpu_irq_restore(flags); + } +} + + +static void udd_ctrl_in_sent(void) +{ + static bool b_shortpacket = false; + uint16_t nb_remain; + uint8_t i; + volatile uint8_t *ptr_dest; + volatile uint8_t *ptr_src; + irqflags_t flags; + + flags = cpu_irq_save(); + udd_disable_in_send_interrupt(0); + cpu_irq_restore(flags); + + if (UDD_EPCTRL_HANDSHAKE_WAIT_IN_ZLP == udd_ep_control_state) { + // ZLP on IN is sent, then valid end of setup request + udd_ctrl_endofrequest(); + // Reinitializes control endpoint management + udd_ctrl_init(); + return; + } + Assert(udd_ep_control_state == UDD_EPCTRL_DATA_IN); + + nb_remain = udd_g_ctrlreq.payload_size - udd_ctrl_payload_buf_cnt; + if (0 == nb_remain) { + // All content of current buffer payload are sent + // Update number of total data sending by previous playlaod buffer + udd_ctrl_prev_payload_buf_cnt += udd_ctrl_payload_buf_cnt; + if ((udd_g_ctrlreq.req.wLength == udd_ctrl_prev_payload_buf_cnt) + || b_shortpacket) { + // All data requested are transfered or a short packet has been sent + // then it is the end of data phase. + // Generate an OUT ZLP for handshake phase. + udd_ctrl_send_zlp_out(); + return; + } + // Need of new buffer because the data phase is not complete + if ((!udd_g_ctrlreq.over_under_run) + || (!udd_g_ctrlreq.over_under_run())) { + // Underrun then send zlp on IN + // Here nb_remain=0 and allows to send a IN ZLP + } else { + // A new payload buffer is given + udd_ctrl_payload_buf_cnt = 0; + nb_remain = udd_g_ctrlreq.payload_size; + } + } + // Continue transfer and send next data + if (nb_remain >= USB_DEVICE_EP_CTRL_SIZE) { + nb_remain = USB_DEVICE_EP_CTRL_SIZE; + b_shortpacket = false; + } else { + b_shortpacket = true; + } + // Fill buffer of endpoint control + ptr_dest = (uint8_t *) & udd_get_endpoint_fifo_access(0, 8); + ptr_src = udd_g_ctrlreq.payload + udd_ctrl_payload_buf_cnt; + // Critical section + // Only in case of DATA IN phase abort without USB Reset signal after. + // The IN data don't must be written in endpoint 0 DPRAM during + // a next setup reception in same endpoint 0 DPRAM. + // Thereby, an OUT ZLP reception must check before IN data write + // and if no OUT ZLP is recevied the data must be written quickly (800us) + // before an eventually ZLP OUT and SETUP reception + flags = cpu_irq_save(); + if (Is_udd_out_received(0)) { + // IN DATA phase aborted by OUT ZLP + cpu_irq_restore(flags); + udd_ep_control_state = UDD_EPCTRL_HANDSHAKE_WAIT_OUT_ZLP; + return; // Exit of IN DATA phase + } + // Write quickly the IN data + for (i = 0; i < nb_remain; i++) { + *ptr_dest++ = *ptr_src++; + } + udd_ctrl_payload_buf_cnt += nb_remain; + + // Validate and send the data available in the control endpoint buffer + __DSB(); + __ISB(); + udd_ack_in_send(0); + udd_enable_in_send_interrupt(0); + // In case of abort of DATA IN phase, no need to enable nak OUT interrupt + // because OUT endpoint is already free and ZLP OUT accepted. + cpu_irq_restore(flags); +} + + +static void udd_ctrl_out_received(void) +{ + irqflags_t flags; + uint8_t i; + uint16_t nb_data; + + if (UDD_EPCTRL_DATA_OUT != udd_ep_control_state) { + if ((UDD_EPCTRL_DATA_IN == udd_ep_control_state) + || (UDD_EPCTRL_HANDSHAKE_WAIT_OUT_ZLP == + udd_ep_control_state)) { + // End of SETUP request: + // - Data IN Phase aborted, + // - or last Data IN Phase hidden by ZLP OUT sending quiclky, + // - or ZLP OUT received normaly. + udd_ctrl_endofrequest(); + } else { + // Protocol error during SETUP request + udd_ctrl_stall_data(); + } + // Reinitializes control endpoint management + udd_ctrl_init(); + return; + } + // Read data received during OUT phase + nb_data = udd_byte_count(0); + if (udd_g_ctrlreq.payload_size < (udd_ctrl_payload_buf_cnt + nb_data)) { + // Payload buffer too small + nb_data = udd_g_ctrlreq.payload_size - udd_ctrl_payload_buf_cnt; + } + volatile uint8_t *ptr_src = (uint8_t *) & udd_get_endpoint_fifo_access(0, 8); + volatile uint8_t *ptr_dest = udd_g_ctrlreq.payload + udd_ctrl_payload_buf_cnt; + for (i = 0; i < nb_data; i++) { + *ptr_dest++ = *ptr_src++; + } + udd_ctrl_payload_buf_cnt += nb_data; + + if ((USB_DEVICE_EP_CTRL_SIZE != nb_data) + || (udd_g_ctrlreq.req.wLength <= + (udd_ctrl_prev_payload_buf_cnt + + udd_ctrl_payload_buf_cnt))) { + // End of reception because it is a short packet + // Before send ZLP, call intermediat calback + // in case of data receiv generate a stall + udd_g_ctrlreq.payload_size = udd_ctrl_payload_buf_cnt; + if (NULL != udd_g_ctrlreq.over_under_run) { + if (!udd_g_ctrlreq.over_under_run()) { + // Stall ZLP + udd_ctrl_stall_data(); + // Ack reception of OUT to replace NAK by a STALL + udd_ack_out_received(0); + return; + } + } + // Send IN ZLP to ACK setup request + udd_ack_out_received(0); + udd_ctrl_send_zlp_in(); + return; + } + + if (udd_g_ctrlreq.payload_size == udd_ctrl_payload_buf_cnt) { + // Overrun then request a new payload buffer + if (!udd_g_ctrlreq.over_under_run) { + // No callback availabled to request a new payload buffer + udd_ctrl_stall_data(); + // Ack reception of OUT to replace NAK by a STALL + udd_ack_out_received(0); + return; + } + if (!udd_g_ctrlreq.over_under_run()) { + // No new payload buffer delivered + udd_ctrl_stall_data(); + // Ack reception of OUT to replace NAK by a STALL + udd_ack_out_received(0); + return; + } + // New payload buffer available + // Update number of total data received + udd_ctrl_prev_payload_buf_cnt += udd_ctrl_payload_buf_cnt; + // Reinit reception on payload buffer + udd_ctrl_payload_buf_cnt = 0; + } + // Free buffer of control endpoint to authorize next reception + udd_ack_out_received(0); + // To detect a protocol error, enable nak interrupt on data IN phase + udd_ack_nak_in(0); + flags = cpu_irq_save(); + udd_enable_nak_in_interrupt(0); + cpu_irq_restore(flags); +} + + +static void udd_ctrl_underflow(void) +{ + if (Is_udd_out_received(0)) + return; // Underflow ignored if OUT data is received + + if (UDD_EPCTRL_DATA_OUT == udd_ep_control_state) { + // Host want to stop OUT transaction + // then stop to wait OUT data phase and wait IN ZLP handshake + udd_ctrl_send_zlp_in(); + } else if (UDD_EPCTRL_HANDSHAKE_WAIT_OUT_ZLP == udd_ep_control_state) { + // A OUT handshake is waiting by device, + // but host want extra IN data then stall extra IN data + udd_enable_stall_handshake(0); + } +} + + +static void udd_ctrl_overflow(void) +{ + if (Is_udd_in_send(0)) + return; // Overflow ignored if IN data is received + + // The case of UDD_EPCTRL_DATA_IN is not managed + // because the OUT endpoint is already free and OUT ZLP accepted + + if (UDD_EPCTRL_HANDSHAKE_WAIT_IN_ZLP == udd_ep_control_state) { + // A IN handshake is waiting by device, + // but host want extra OUT data then stall extra OUT data + udd_enable_stall_handshake(0); + } +} + + +static void udd_ctrl_stall_data(void) +{ + // Stall all packets on IN & OUT control endpoint + udd_ep_control_state = UDD_EPCTRL_STALL_REQ; + udd_enable_stall_handshake(0); +} + + +static void udd_ctrl_send_zlp_in(void) +{ + irqflags_t flags; + + udd_ep_control_state = UDD_EPCTRL_HANDSHAKE_WAIT_IN_ZLP; + + // Validate and send empty IN packet on control endpoint + flags = cpu_irq_save(); + // Send ZLP on IN endpoint + udd_ack_in_send(0); + udd_enable_in_send_interrupt(0); + // To detect a protocol error, enable nak interrupt on data OUT phase + udd_ack_nak_out(0); + udd_enable_nak_out_interrupt(0); + cpu_irq_restore(flags); +} + + +static void udd_ctrl_send_zlp_out(void) +{ + irqflags_t flags; + + udd_ep_control_state = UDD_EPCTRL_HANDSHAKE_WAIT_OUT_ZLP; + // No action is necessary to accept OUT ZLP + // because the buffer of control endpoint is already free + + // To detect a protocol error, enable nak interrupt on data IN phase + flags = cpu_irq_save(); + udd_ack_nak_in(0); + udd_enable_nak_in_interrupt(0); + cpu_irq_restore(flags); +} + + +static void udd_ctrl_endofrequest(void) +{ + // If a callback is registered then call it + if (udd_g_ctrlreq.callback) { + udd_g_ctrlreq.callback(); + } +} + + +static bool udd_ctrl_interrupt(void) +{ + + if (!Is_udd_endpoint_interrupt(0)) { + return false; // No interrupt events on control endpoint + } + + dbg_print("0: "); + + // By default disable overflow and underflow interrupt + udd_disable_nak_in_interrupt(0); + udd_disable_nak_out_interrupt(0); + + // Search event on control endpoint + if (Is_udd_setup_received(0)) { + dbg_print("stup "); + // SETUP packet received + udd_ctrl_setup_received(); + return true; + } + if (Is_udd_in_send(0) && Is_udd_in_send_interrupt_enabled(0)) { + dbg_print("in "); + // IN packet sent + udd_ctrl_in_sent(); + return true; + } + if (Is_udd_out_received(0)) { + dbg_print("out "); + // OUT packet received + udd_ctrl_out_received(); + return true; + } + if (Is_udd_nak_out(0)) { + dbg_print("nako "); + // Overflow on OUT packet + udd_ack_nak_out(0); + udd_ctrl_overflow(); + return true; + } + if (Is_udd_nak_in(0)) { + dbg_print("naki "); + // Underflow on IN packet + udd_ack_nak_in(0); + udd_ctrl_underflow(); + return true; + } + dbg_print("n%x ", USBHS_ARRAY(USBHS_DEVEPTISR[0], 0)); + return false; +} + + +//-------------------------------------------------------- +//--- INTERNAL ROUTINES TO MANAGED THE BULK/INTERRUPT/ISOCHRONOUS ENDPOINTS + +#if (0 != USB_DEVICE_MAX_EP) + +static void udd_ep_job_table_reset(void) +{ + uint8_t i; + for (i = 0; i < USB_DEVICE_MAX_EP; i++) { + udd_ep_job[i].busy = false; + udd_ep_job[i].stall_requested = false; + } +} + + +static void udd_ep_job_table_kill(void) +{ + uint8_t i; + + // For each endpoint, kill job + for (i = 0; i < USB_DEVICE_MAX_EP; i++) { + udd_ep_finish_job(&udd_ep_job[i], true, i + 1); + } +} + + +static void udd_ep_abort_job(udd_ep_id_t ep) +{ + ep &= USB_EP_ADDR_MASK; + + // Abort job on endpoint + udd_ep_finish_job(&udd_ep_job[ep - 1], true, ep); +} + + +static void udd_ep_finish_job(udd_ep_job_t * ptr_job, bool b_abort, uint8_t ep_num) +{ + if (ptr_job->busy == false) { + return; // No on-going job + } + dbg_print("(JobE%x:%d) ", (ptr_job-udd_ep_job)+1, b_abort); + ptr_job->busy = false; + if (NULL == ptr_job->call_trans) { + return; // No callback linked to job + } + if (Is_udd_endpoint_in(ep_num)) { + ep_num |= USB_EP_DIR_IN; + } + ptr_job->call_trans((b_abort) ? UDD_EP_TRANSFER_ABORT : + UDD_EP_TRANSFER_OK, ptr_job->buf_size, ep_num); +} + +#ifdef UDD_EP_DMA_SUPPORTED +static void udd_ep_trans_done(udd_ep_id_t ep) +{ + uint32_t udd_dma_ctrl = 0; + udd_ep_job_t *ptr_job; + iram_size_t next_trans; + irqflags_t flags; + + // Get job corresponding at endpoint + ptr_job = &udd_ep_job[ep - 1]; + + if (!ptr_job->busy) { + return; // No job is running, then ignore it (system error) + } + + if (ptr_job->buf_cnt != ptr_job->buf_size) { + // Need to send or receiv other data + next_trans = ptr_job->buf_size - ptr_job->buf_cnt; + + if (UDD_ENDPOINT_MAX_TRANS < next_trans) { + // The USB hardware support a maximum + // transfer size of UDD_ENDPOINT_MAX_TRANS Bytes + next_trans = UDD_ENDPOINT_MAX_TRANS; + + // Set 0 to tranfer the maximum + udd_dma_ctrl = USBHS_DEVDMACONTROL_BUFF_LENGTH(0); + } else { + udd_dma_ctrl = USBHS_DEVDMACONTROL_BUFF_LENGTH(next_trans); + } + if (Is_udd_endpoint_in(ep)) { + if (0 != (next_trans % udd_get_endpoint_size(ep))) { + // Enable short packet option + // else the DMA transfer is accepted + // and interrupt DMA valid but nothing is sent. + udd_dma_ctrl |= USBHS_DEVDMACONTROL_END_B_EN; + // No need to request another ZLP + ptr_job->b_shortpacket = false; + } + } else { + if ((USB_EP_TYPE_ISOCHRONOUS != udd_get_endpoint_type(ep)) + || (next_trans <= (iram_size_t) udd_get_endpoint_size(ep))) { + + // Enable short packet reception + udd_dma_ctrl |= USBHS_DEVDMACONTROL_END_TR_IT + | USBHS_DEVDMACONTROL_END_TR_EN; + } + } + + // Start USB DMA to fill or read fifo of the selected endpoint + udd_endpoint_dma_set_addr(ep, (uint32_t) & ptr_job->buf[ptr_job->buf_cnt]); + udd_dma_ctrl |= USBHS_DEVDMACONTROL_END_BUFFIT | + USBHS_DEVDMACONTROL_CHANN_ENB; + + + // Disable IRQs to have a short sequence + // between read of EOT_STA and DMA enable + flags = cpu_irq_save(); + if (!(udd_endpoint_dma_get_status(ep) + & USBHS_DEVDMASTATUS_END_TR_ST)) { + dbg_print("dmaS%x ", ep); + udd_endpoint_dma_set_control(ep, udd_dma_ctrl); + ptr_job->buf_cnt += next_trans; + ptr_job->buf_load = next_trans; + udd_enable_endpoint_dma_interrupt(ep); + cpu_irq_restore(flags); + return; + } + cpu_irq_restore(flags); + + // Here a ZLP has been recieved + // and the DMA transfer must be not started. + // It is the end of transfer + ptr_job->buf_size = ptr_job->buf_cnt; + } + if (Is_udd_endpoint_in(ep)) { + if (ptr_job->b_shortpacket) { + dbg_print("zlpS%x ", ep); + // Need to send a ZLP (No possible with USB DMA) + // enable interrupt to wait a free bank to sent ZLP + udd_ack_in_send(ep); + if (Is_udd_write_enabled(ep)) { + // Force interrupt in case of ep already free + udd_raise_in_send(ep); + } + udd_enable_in_send_interrupt(ep); + udd_enable_endpoint_interrupt(ep); + return; + } + } else { + _dcache_invalidate_prepare(ptr_job->buf, ptr_job->buf_size); + _dcache_invalidate(ptr_job->buf, ptr_job->buf_size); + } + dbg_print("dmaE "); + // Call callback to signal end of transfer + udd_ep_finish_job(ptr_job, false, ep); +} +#endif + +#ifdef UDD_EP_FIFO_SUPPORTED +static void udd_ep_in_sent(udd_ep_id_t ep) +{ + udd_ep_job_t *ptr_job = &udd_ep_job[ep - 1]; + uint8_t *ptr_src = &ptr_job->buf[ptr_job->buf_cnt]; + uint8_t *ptr_dst = (uint8_t *) & udd_get_endpoint_fifo_access(ep, 8); + uint32_t pkt_size = udd_get_endpoint_size(ep); + uint32_t nb_data = 0, i; + uint32_t nb_remain; + irqflags_t flags; + + // All transfer done, including ZLP, Finish Job + if (ptr_job->buf_cnt >= ptr_job->buf_size && !ptr_job->b_shortpacket) { + flags = cpu_irq_save(); + udd_disable_in_send_interrupt(ep); + udd_disable_endpoint_interrupt(ep); + cpu_irq_restore(flags); + + ptr_job->buf_size = ptr_job->buf_cnt; // buf_size is passed to callback as XFR count + udd_ep_finish_job(ptr_job, false, ep); + return; + } else { + // ACK TXINI + udd_ack_in_send(ep); + // Fill FIFO + ptr_dst = (uint8_t *) & udd_get_endpoint_fifo_access(ep, 8); + ptr_src = &ptr_job->buf[ptr_job->buf_cnt]; + nb_remain = ptr_job->buf_size - ptr_job->buf_cnt; + // Fill a bank even if no data (ZLP) + nb_data = min(nb_remain, pkt_size); + // Modify job information + ptr_job->buf_cnt += nb_data; + ptr_job->buf_load = nb_data; + + // Copy buffer to FIFO + for (i = 0; i < nb_data; i++) { + *ptr_dst++ = *ptr_src++; + } + // Switch to next bank + __DSB(); + __ISB(); + udd_ack_fifocon(ep); + // ZLP? + if (nb_data < pkt_size) { + ptr_job->b_shortpacket = false; + } + } +} + +static void udd_ep_out_received(udd_ep_id_t ep) +{ + udd_ep_job_t *ptr_job = &udd_ep_job[ep - 1]; + uint32_t nb_data = 0, i; + uint32_t nb_remain = ptr_job->buf_size - ptr_job->buf_cnt; + uint32_t pkt_size = udd_get_endpoint_size(ep); + uint8_t *ptr_src = (uint8_t *) & udd_get_endpoint_fifo_access(ep, 8); + uint8_t *ptr_dst = &ptr_job->buf[ptr_job->buf_cnt]; + bool b_full = false, b_short = false; + + // Clear RX OUT + udd_ack_out_received(ep); + + // Read byte count + nb_data = udd_byte_count(ep); + if (nb_data < pkt_size) { + b_short = true; + } + //dbg_print("o%d ", ep); + //dbg_print("%d ", nb_data); + // Copy data if there is + if (nb_data > 0) { + if (nb_data >= nb_remain) { + nb_data = nb_remain; + b_full = true; + } + // Modify job information + ptr_job->buf_cnt += nb_data; + ptr_job->buf_load = nb_data; + // Copy FIFO to buffer + for (i = 0; i < nb_data; i++) { + *ptr_dst++ = *ptr_src++; + } + __DSB(); + __ISB(); + } + // Clear FIFO Status + udd_ack_fifocon(ep); + // Finish job on error or short packet + if (b_full || b_short) { + //dbg_print("EoO%d\n\r", ep); + udd_disable_out_received_interrupt(ep); + udd_disable_endpoint_interrupt(ep); + ptr_job->buf_size = ptr_job->buf_cnt; // buf_size is passed to callback as XFR count + udd_ep_finish_job(ptr_job, false, ep); + } +} +#endif // #ifdef UDD_EP_FIFO_SUPPORTED + +static bool udd_ep_interrupt(void) +{ + udd_ep_id_t ep; + udd_ep_job_t *ptr_job; + + // For each endpoint different of control endpoint (0) + for (ep = 1; ep <= USB_DEVICE_MAX_EP; ep++) { + // Get job corresponding at endpoint + ptr_job = &udd_ep_job[ep - 1]; + +#ifdef UDD_EP_DMA_SUPPORTED + // Check DMA event + if (Is_udd_endpoint_dma_interrupt_enabled(ep) + && Is_udd_endpoint_dma_interrupt(ep)) { + uint32_t nb_remaining; + if (udd_endpoint_dma_get_status(ep) + & USBHS_DEVDMASTATUS_CHANN_ENB) { + return true; // Ignore EOT_STA interrupt + } + dbg_print("dma%x: ", ep); + udd_disable_endpoint_dma_interrupt(ep); + // Save number of data no transfered + nb_remaining = (udd_endpoint_dma_get_status(ep) & + USBHS_DEVDMASTATUS_BUFF_COUNT_Msk) + >> USBHS_DEVDMASTATUS_BUFF_COUNT_Pos; + if (nb_remaining) { + // Transfer no complete (short packet or ZLP) then: + // Update number of data transfered + ptr_job->buf_cnt -= nb_remaining; + // Set transfer complete to stop the transfer + ptr_job->buf_size = ptr_job->buf_cnt; + } + udd_ep_trans_done(ep); + return true; + } +#endif +#ifdef UDD_EP_FIFO_SUPPORTED + // Check RXRDY and TXEMPTY event for none DMA endpoints + if (!Is_udd_endpoint_dma_supported(ep) + && Is_udd_endpoint_interrupt_enabled(ep)) { + dbg_print("ep%x: ", ep); + // RXOUT: Full packet received + if (Is_udd_out_received(ep) + && Is_udd_out_received_interrupt_enabled(ep)) { + dbg_print("Out "); + udd_ep_out_received(ep); + return true; + } + // TXIN: packet sent + if (Is_udd_in_send(ep) + && Is_udd_in_send_interrupt_enabled(ep)) { + dbg_print("In "); + udd_ep_in_sent(ep); + return true; + } + // Errors: Abort? + if (Is_udd_overflow(ep) + || Is_udd_underflow(ep) + || Is_udd_crc_error(ep)) { + dbg_print("Err "); + udd_ep_abort(ep); + return true; + } + } +#endif // UDD_EP_FIFO_SUPPORTED + // Check empty bank interrupt event + if (Is_udd_endpoint_interrupt_enabled(ep)) { + dbg_print("bg%x: ", ep); + if (Is_udd_in_send_interrupt_enabled(ep) + && Is_udd_in_send(ep)) { + dbg_print("I "); + udd_disable_in_send_interrupt(ep); + // One bank is free then send a ZLP + udd_ack_in_send(ep); + udd_ack_fifocon(ep); + udd_ep_finish_job(ptr_job, false, ep); + return true; + } + if (Is_udd_bank_interrupt_enabled(ep) + && (0 == udd_nb_busy_bank(ep))) { + dbg_print("EoT "); + // End of background transfer on IN endpoint + udd_disable_bank_interrupt(ep); + udd_disable_endpoint_interrupt(ep); + + Assert(ptr_job->stall_requested); + // A stall has been requested during backgound transfer + ptr_job->stall_requested = false; + udd_disable_endpoint_bank_autoswitch(ep); + udd_enable_stall_handshake(ep); + udd_reset_data_toggle(ep); + return true; + } + } + } + return false; +} +#endif // (0 != USB_DEVICE_MAX_EP) + +//@} diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/usbhs/usbhs_device.h b/hw-libs/drivers/SAMx70/ASF/sam/drivers/usbhs/usbhs_device.h new file mode 100644 index 000000000..c0e681596 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/usbhs/usbhs_device.h @@ -0,0 +1,645 @@ +/** + * \file + * + * \brief USB Device Driver for USBHS. Compliant with common UDD driver. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef USBHS_DEVICE_H_INCLUDED +#define USBHS_DEVICE_H_INCLUDED + +#include "compiler.h" +#include "preprocessor.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +#ifndef USBHS_RAM_ADDR +#define USBHS_RAM_ADDR 0xA0100000u +#endif + +//! \ingroup udd_group +//! \defgroup udd_udphs_group USB High-Speed Port for device mode (USBHS) +//! USBHS low-level driver for USB device mode +//! +//! @{ + +#ifndef USBHS_DEVEPTCFG_EPDIR_Pos +// Bit pos is not defined in SAM header file but we need it. +# define USBHS_DEVEPTCFG_EPDIR_Pos 8 +#endif + +//! @name USBHS Device IP properties +//! These macros give access to IP properties +//! @{ + //! Get maximal number of endpoints +#define udd_get_endpoint_max_nbr() (9) +#define UDD_MAX_PEP_NB (udd_get_endpoint_max_nbr() + 1) + //! Get maximal number of banks of endpoints +#define udd_get_endpoint_bank_max_nbr(ep) ((ep == 0) ? 1 : (( ep <= 2) ? 3 : 2)) + //! Get maximal size of endpoint (3X, 1024/64) +#define udd_get_endpoint_size_max(ep) (((ep) == 0) ? 64 : 1024) + //! Get DMA support of endpoints +#define Is_udd_endpoint_dma_supported(ep) ((((ep) >= 1) && ((ep) <= 7)) ? true : false) + //! Get High Band Width support of endpoints +#define Is_udd_endpoint_high_bw_supported(ep) (((ep) >= 2) ? true : false) +//! @} + +//! @name USBHS Device speeds management +//! @{ + //! Enable/disable device low-speed mode +#define udd_low_speed_enable() (Set_bits(USBHS->USBHS_DEVCTRL, USBHS_DEVCTRL_LS)) +#define udd_low_speed_disable() (Clr_bits(USBHS->USBHS_DEVCTRL, USBHS_DEVCTRL_LS)) + //! Test if device low-speed mode is forced +#define Is_udd_low_speed_enable() (Tst_bits(USBHS->USBHS_DEVCTRL, USBHS_DEVCTRL_LS)) + +#ifdef USBHS_DEVCTRL_SPDCONF_HIGH_SPEED + //! Enable high speed mode +# define udd_high_speed_enable() (Wr_bitfield(USBHS->USBHS_DEVCTRL, USBHS_DEVCTRL_SPDCONF_Msk, 0)) + //! Disable high speed mode +# define udd_high_speed_disable() (Wr_bitfield(USBHS->USBHS_DEVCTRL, USBHS_DEVCTRL_SPDCONF_Msk, 3)) + //! Test if controller is in full speed mode +# define Is_udd_full_speed_mode() (Rd_bitfield(USBHS->USBHS_SR, USBHS_SR_SPEED_Msk) == USBHS_SR_SPEED_FULL_SPEED) +#else +# define udd_high_speed_enable() do { } while (0) +# define udd_high_speed_disable() do { } while (0) +# define Is_udd_full_speed_mode() true +#endif +//! @} + +//! @name USBHS Device HS test mode management +//! @{ +#ifdef USBHS_DEVCTRL_SPDCONF_HIGH_SPEED + //! Enable high speed test mode +# define udd_enable_hs_test_mode() (Wr_bitfield(USBHS->USBHS_DEVCTRL, USBHS_DEVCTRL_SPDCONF_Msk, 2)) +# define udd_enable_hs_test_mode_j() (Set_bits(USBHS->USBHS_DEVCTRL, USBHS_DEVCTRL_TSTJ)) +# define udd_enable_hs_test_mode_k() (Set_bits(USBHS->USBHS_DEVCTRL, USBHS_DEVCTRL_TSTK)) +# define udd_enable_hs_test_mode_packet() (Set_bits(USBHS->USBHS_DEVCTRL, USBHS_DEVCTRL_TSTPCKT)) +#endif +//! @} + +//! @name USBHS device attach control +//! These macros manage the USBHS Device attach. +//! @{ + //! Detaches from USB bus +#define udd_detach_device() (Set_bits(USBHS->USBHS_DEVCTRL, USBHS_DEVCTRL_DETACH)) + //! Attaches to USB bus +#define udd_attach_device() (Clr_bits(USBHS->USBHS_DEVCTRL, USBHS_DEVCTRL_DETACH)) + //! Test if the device is detached +#define Is_udd_detached() (Tst_bits(USBHS->USBHS_DEVCTRL, USBHS_DEVCTRL_DETACH)) +//! @} + + +//! @name USBHS device bus events control +//! These macros manage the USBHS Device bus events. +//! @{ + +//! Initiates a remote wake-up event +//! @{ +#define udd_initiate_remote_wake_up() (Set_bits(USBHS->USBHS_DEVCTRL, USBHS_DEVCTRL_RMWKUP)) +#define Is_udd_pending_remote_wake_up() (Tst_bits(USBHS->USBHS_DEVCTRL, USBHS_DEVCTRL_RMWKUP)) +//! @} + +//! Manage upstream resume event (=remote wakeup) +//! The USB driver sends a resume signal called "Upstream Resume" +//! @{ +#define udd_enable_remote_wake_up_interrupt() (USBHS->USBHS_DEVIER = USBHS_DEVIER_UPRSMES) +#define udd_disable_remote_wake_up_interrupt() (USBHS->USBHS_DEVIDR = USBHS_DEVIDR_UPRSMEC) +#define Is_udd_remote_wake_up_interrupt_enabled() (Tst_bits(USBHS->USBHS_DEVIMR, USBHS_DEVIMR_UPRSME)) +#define udd_ack_remote_wake_up_start() (USBHS->USBHS_DEVICR = USBHS_DEVICR_UPRSMC) +#define udd_raise_remote_wake_up_start() (USBHS->USBHS_DEVIFR = USBHS_DEVIFR_UPRSMS) +#define Is_udd_remote_wake_up_start() (Tst_bits(USBHS->USBHS_DEVISR, USBHS_DEVISR_UPRSM)) +//! @} + +//! Manage downstream resume event (=remote wakeup from host) +//! The USB controller detects a valid "End of Resume" signal initiated by the host +//! @{ +#define udd_enable_resume_interrupt() (USBHS->USBHS_DEVIER = USBHS_DEVIER_EORSMES) +#define udd_disable_resume_interrupt() (USBHS->USBHS_DEVIDR = USBHS_DEVIDR_EORSMEC) +#define Is_udd_resume_interrupt_enabled() (Tst_bits(USBHS->USBHS_DEVIMR, USBHS_DEVIMR_EORSME)) +#define udd_ack_resume() (USBHS->USBHS_DEVICR = USBHS_DEVICR_EORSMC) +#define udd_raise_resume() (USBHS->USBHS_DEVIFR = USBHS_DEVIFR_EORSMS) +#define Is_udd_resume() (Tst_bits(USBHS->USBHS_DEVISR, USBHS_DEVISR_EORSM)) +//! @} + +//! Manage wake-up event (=usb line activity) +//! The USB controller is reactivated by a filtered non-idle signal from the lines +//! @{ +#define udd_enable_wake_up_interrupt() (USBHS->USBHS_DEVIER = USBHS_DEVIER_WAKEUPES) +#define udd_disable_wake_up_interrupt() (USBHS->USBHS_DEVIDR = USBHS_DEVIDR_WAKEUPEC) +#define Is_udd_wake_up_interrupt_enabled() (Tst_bits(USBHS->USBHS_DEVIMR, USBHS_DEVIMR_WAKEUPE)) +#define udd_ack_wake_up() (USBHS->USBHS_DEVICR = USBHS_DEVICR_WAKEUPC) +#define udd_raise_wake_up() (USBHS->USBHS_DEVIFR = USBHS_DEVIFR_WAKEUPS) +#define Is_udd_wake_up() (Tst_bits(USBHS->USBHS_DEVISR, USBHS_DEVISR_WAKEUP)) +//! @} + +//! Manage reset event +//! Set when a USB "End of Reset" has been detected +//! @{ +#define udd_enable_reset_interrupt() (USBHS->USBHS_DEVIER = USBHS_DEVIER_EORSTES) +#define udd_disable_reset_interrupt() (USBHS->USBHS_DEVIDR = USBHS_DEVIDR_EORSTEC) +#define Is_udd_reset_interrupt_enabled() (Tst_bits(USBHS->USBHS_DEVIMR, USBHS_DEVIMR_EORSTE)) +#define udd_ack_reset() (USBHS->USBHS_DEVICR = USBHS_DEVICR_EORSTC) +#define udd_raise_reset() (USBHS->USBHS_DEVIFR = USBHS_DEVIFR_EORSTS) +#define Is_udd_reset() (Tst_bits(USBHS->USBHS_DEVISR, USBHS_DEVISR_EORST)) +//! @} + +//! Manage start of frame event +//! @{ +#define udd_enable_sof_interrupt() (USBHS->USBHS_DEVIER = USBHS_DEVIER_SOFES) +#define udd_disable_sof_interrupt() (USBHS->USBHS_DEVIDR = USBHS_DEVIDR_SOFEC) +#define Is_udd_sof_interrupt_enabled() (Tst_bits(USBHS->USBHS_DEVIMR, USBHS_DEVIMR_SOFE)) +#define udd_ack_sof() (USBHS->USBHS_DEVICR = USBHS_DEVICR_SOFC) +#define udd_raise_sof() (USBHS->USBHS_DEVIFR = USBHS_DEVIFR_SOFS) +#define Is_udd_sof() (Tst_bits(USBHS->USBHS_DEVISR, USBHS_DEVISR_SOF)) +#define udd_frame_number() (Rd_bitfield(USBHS->USBHS_DEVFNUM, USBHS_DEVFNUM_FNUM_Msk)) +#define Is_udd_frame_number_crc_error() (Tst_bits(USBHS->USBHS_DEVFNUM, USBHS_DEVFNUM_FNCERR)) +//! @} + +//! Manage Micro start of frame event (High Speed Only) +//! @{ +#define udd_enable_msof_interrupt() (USBHS->USBHS_DEVIER = USBHS_DEVIER_MSOFES) +#define udd_disable_msof_interrupt() (USBHS->USBHS_DEVIDR = USBHS_DEVIDR_MSOFEC) +#define Is_udd_msof_interrupt_enabled() (Tst_bits(USBHS->USBHS_DEVIMR, USBHS_DEVIMR_MSOFE)) +#define udd_ack_msof() (USBHS->USBHS_DEVICR = USBHS_DEVIMR_MSOFE) +#define udd_raise_msof() (USBHS->USBHS_DEVIFR = USBHS_DEVIFR_MSOFS) +#define Is_udd_msof() (Tst_bits(USBHS->USBHS_DEVISR, USBHS_DEVISR_MSOF)) +#define udd_micro_frame_number() \ + (Rd_bitfield(USBHS->USBHS_DEVFNUM, (USBHS_DEVFNUM_FNUM_Msk|USBHS_DEVFNUM_MFNUM_Msk))) +//! @} + +//! Manage suspend event +//! @{ +#define udd_enable_suspend_interrupt() (USBHS->USBHS_DEVIER = USBHS_DEVIER_SUSPES) +#define udd_disable_suspend_interrupt() (USBHS->USBHS_DEVIDR = USBHS_DEVIDR_SUSPEC) +#define Is_udd_suspend_interrupt_enabled() (Tst_bits(USBHS->USBHS_DEVIMR, USBHS_DEVIMR_SUSPE)) +#define udd_ack_suspend() (USBHS->USBHS_DEVICR = USBHS_DEVICR_SUSPC) +#define udd_raise_suspend() (USBHS->USBHS_DEVIFR = USBHS_DEVIFR_SUSPS) +#define Is_udd_suspend() (Tst_bits(USBHS->USBHS_DEVISR, USBHS_DEVISR_SUSP)) +//! @} + +//! @} + +//! @name USBHS device address control +//! These macros manage the USBHS Device address. +//! @{ + //! enables USB device address +#define udd_enable_address() (Set_bits(USBHS->USBHS_DEVCTRL, USBHS_DEVCTRL_ADDEN)) + //! disables USB device address +#define udd_disable_address() (Clr_bits(USBHS->USBHS_DEVCTRL, USBHS_DEVCTRL_ADDEN)) +#define Is_udd_address_enabled() (Tst_bits(USBHS->USBHS_DEVCTRL, USBHS_DEVCTRL_ADDEN)) + //! configures the USB device address +#define udd_configure_address(addr) (Wr_bitfield(USBHS->USBHS_DEVCTRL, USBHS_DEVCTRL_UADD_Msk, addr)) + //! gets the currently configured USB device address +#define udd_get_configured_address() (Rd_bitfield(USBHS->USBHS_DEVCTRL, USBHS_DEVCTRL_UADD_Msk)) +//! @} + + +//! @name USBHS Device endpoint drivers +//! These macros manage the common features of the endpoints. +//! @{ + +//! Generic macro for USBHS registers that can be arrayed +//! @{ +#define USBHS_ARRAY(reg,index) ((&(USBHS->reg))[(index)]) +//! @} + +//! @name USBHS Device endpoint configuration +//! @{ + //! enables the selected endpoint +#define udd_enable_endpoint(ep) (Set_bits(USBHS->USBHS_DEVEPT, USBHS_DEVEPT_EPEN0 << (ep))) + //! disables the selected endpoint +#define udd_disable_endpoint(ep) (Clr_bits(USBHS->USBHS_DEVEPT, USBHS_DEVEPT_EPEN0 << (ep))) + //! tests if the selected endpoint is enabled +#define Is_udd_endpoint_enabled(ep) (Tst_bits(USBHS->USBHS_DEVEPT, USBHS_DEVEPT_EPEN0 << (ep))) + //! resets the selected endpoint +#define udd_reset_endpoint(ep) \ + do { \ + Set_bits(USBHS->USBHS_DEVEPT, USBHS_DEVEPT_EPRST0 << (ep)); \ + Clr_bits(USBHS->USBHS_DEVEPT, USBHS_DEVEPT_EPRST0 << (ep)); \ + } while (0) + //! Tests if the selected endpoint is being reset +#define Is_udd_resetting_endpoint(ep) (Tst_bits(USBHS->USBHS_DEVEPT, USBHS_DEVEPT_EPRST0 << (ep))) + + //! Configures the selected endpoint type +#define udd_configure_endpoint_type(ep, type) (Wr_bitfield(USBHS_ARRAY(USBHS_DEVEPTCFG[0], ep), USBHS_DEVEPTCFG_EPTYPE_Msk, type)) + //! Gets the configured selected endpoint type +#define udd_get_endpoint_type(ep) (Rd_bitfield(USBHS_ARRAY(USBHS_DEVEPTCFG[0], ep), USBHS_DEVEPTCFG_EPTYPE_Msk)) + //! Enables the bank autoswitch for the selected endpoint +#define udd_enable_endpoint_bank_autoswitch(ep) (Set_bits(USBHS_ARRAY(USBHS_DEVEPTCFG[0], ep), USBHS_DEVEPTCFG_AUTOSW)) + //! Disables the bank autoswitch for the selected endpoint +#define udd_disable_endpoint_bank_autoswitch(ep) (Clr_bits(USBHS_ARRAY(USBHS_DEVEPTCFG[0], ep), USBHS_DEVEPTCFG_AUTOSW)) +#define Is_udd_endpoint_bank_autoswitch_enabled(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTCFG[0], ep), USBHS_DEVEPTCFG_AUTOSW)) + //! Configures the selected endpoint direction +#define udd_configure_endpoint_direction(ep, dir) (Wr_bitfield(USBHS_ARRAY(USBHS_DEVEPTCFG[0], ep), USBHS_DEVEPTCFG_EPDIR, dir)) + //! Gets the configured selected endpoint direction +#define udd_get_endpoint_direction(ep) (Rd_bitfield(USBHS_ARRAY(USBHS_DEVEPTCFG[0], ep), USBHS_DEVEPTCFG_EPDIR)) +#define Is_udd_endpoint_in(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTCFG[0], ep), USBHS_DEVEPTCFG_EPDIR)) + //! Bounds given integer size to allowed range and rounds it up to the nearest + //! available greater size, then applies register format of USBHS controller + //! for endpoint size bit-field. +#define udd_format_endpoint_size(size) (32 - clz(((uint32_t)min(max(size, 8), 1024) << 1) - 1) - 1 - 3) + //! Configures the selected endpoint size +#define udd_configure_endpoint_size(ep, size) (Wr_bitfield(USBHS_ARRAY(USBHS_DEVEPTCFG[0], ep), USBHS_DEVEPTCFG_EPSIZE_Msk, udd_format_endpoint_size(size))) + //! Gets the configured selected endpoint size +#define udd_get_endpoint_size(ep) (8 << Rd_bitfield(USBHS_ARRAY(USBHS_DEVEPTCFG[0], ep), USBHS_DEVEPTCFG_EPSIZE_Msk)) + //! Configures the selected endpoint number of banks +#define udd_configure_endpoint_bank(ep, bank) (Wr_bitfield(USBHS_ARRAY(USBHS_DEVEPTCFG[0], ep), USBHS_DEVEPTCFG_EPBK_Msk, bank)) + //! Gets the configured selected endpoint number of banks +#define udd_get_endpoint_bank(ep) (Rd_bitfield(USBHS_ARRAY(USBHS_DEVEPTCFG[0], ep), USBHS_DEVEPTCFG_EPBK_Msk)+1) + //! Allocates the configuration selected endpoint in DPRAM memory +#define udd_allocate_memory(ep) (Set_bits(USBHS_ARRAY(USBHS_DEVEPTCFG[0], ep), USBHS_DEVEPTCFG_ALLOC)) + //! un-allocates the configuration selected endpoint in DPRAM memory +#define udd_unallocate_memory(ep) (Clr_bits(USBHS_ARRAY(USBHS_DEVEPTCFG[0], ep), USBHS_DEVEPTCFG_ALLOC)) +#define Is_udd_memory_allocated(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTCFG[0], ep), USBHS_DEVEPTCFG_ALLOC)) + + //! Configures selected endpoint in one step +#define udd_configure_endpoint(ep, type, dir, size, bank) (\ + Wr_bits(USBHS_ARRAY(USBHS_DEVEPTCFG[0], ep), USBHS_DEVEPTCFG_EPTYPE_Msk |\ + USBHS_DEVEPTCFG_EPDIR |\ + USBHS_DEVEPTCFG_EPSIZE_Msk |\ + USBHS_DEVEPTCFG_EPBK_Msk , \ + (((uint32_t)(type) << USBHS_DEVEPTCFG_EPTYPE_Pos) & USBHS_DEVEPTCFG_EPTYPE_Msk) |\ + (((uint32_t)(dir ) << USBHS_DEVEPTCFG_EPDIR_Pos ) & USBHS_DEVEPTCFG_EPDIR) |\ + ( (uint32_t)udd_format_endpoint_size(size) << USBHS_DEVEPTCFG_EPSIZE_Pos) |\ + (((uint32_t)(bank) << USBHS_DEVEPTCFG_EPBK_Pos) & USBHS_DEVEPTCFG_EPBK_Msk))\ +) + //! Tests if current endpoint is configured +#define Is_udd_endpoint_configured(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTISR[0], ep), USBHS_DEVEPTISR_CFGOK)) + //! Returns the control direction +#define udd_control_direction() (Rd_bitfield(USBHS_ARRAY(USBHS_DEVEPTISR[0], EP_CONTROL), USBHS_DEVEPTISR_CTRLDIR)) + + //! Resets the data toggle sequence +#define udd_reset_data_toggle(ep) (USBHS_ARRAY(USBHS_DEVEPTIER[0], ep) = USBHS_DEVEPTIER_RSTDTS) + //! Tests if the data toggle sequence is being reset +#define Is_udd_data_toggle_reset(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTIMR[0], ep), USBHS_DEVEPTIMR_RSTDT)) + //! Returns data toggle +#define udd_data_toggle(ep) (Rd_bitfield(USBHS_ARRAY(USBHS_DEVEPTISR[0], ep), USBHS_DEVEPTISR_DTSEQ_Msk)) +//! @} + + +//! @name USBHS Device control endpoint +//! These macros control the endpoints. +//! @{ + +//! @name USBHS Device control endpoint interrupts +//! These macros control the endpoints interrupts. +//! @{ + //! Enables the selected endpoint interrupt +#define udd_enable_endpoint_interrupt(ep) (USBHS->USBHS_DEVIER = USBHS_DEVIER_PEP_0 << (ep)) + //! Disables the selected endpoint interrupt +#define udd_disable_endpoint_interrupt(ep) (USBHS->USBHS_DEVIDR = USBHS_DEVIDR_PEP_0 << (ep)) + //! Tests if the selected endpoint interrupt is enabled +#define Is_udd_endpoint_interrupt_enabled(ep) (Tst_bits(USBHS->USBHS_DEVIMR, USBHS_DEVIMR_PEP_0 << (ep))) + //! Tests if an interrupt is triggered by the selected endpoint +#define Is_udd_endpoint_interrupt(ep) (Tst_bits(USBHS->USBHS_DEVISR, USBHS_DEVISR_PEP_0 << (ep))) + //! Returns the lowest endpoint number generating an endpoint interrupt or MAX_PEP_NB if none +#define udd_get_interrupt_endpoint_number() (ctz(((USBHS->USBHS_DEVISR >> USBHS_DEVISR_PEP_Pos) & \ + (USBHS->USBHS_DEVIMR >> USBHS_DEVIMR_PEP_Pos)) | \ + (1 << MAX_PEP_NB))) +#define USBHS_DEVISR_PEP_Pos 12 +#define USBHS_DEVIMR_PEP_Pos 12 +//! @} + +//! @name USBHS Device control endpoint errors +//! These macros control the endpoint errors. +//! @{ + //! Enables the STALL handshake +#define udd_enable_stall_handshake(ep) (USBHS_ARRAY(USBHS_DEVEPTIER[0], ep) = USBHS_DEVEPTIER_STALLRQS) + //! Disables the STALL handshake +#define udd_disable_stall_handshake(ep) (USBHS_ARRAY(USBHS_DEVEPTIDR[0], ep) = USBHS_DEVEPTIDR_STALLRQC) + //! Tests if STALL handshake request is running +#define Is_udd_endpoint_stall_requested(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTIMR[0], ep), USBHS_DEVEPTIMR_STALLRQ)) + //! Tests if STALL sent +#define Is_udd_stall(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTISR[0], ep), USBHS_DEVEPTISR_STALLEDI)) + //! ACKs STALL sent +#define udd_ack_stall(ep) (USBHS_ARRAY(USBHS_DEVEPTICR[0], ep) = USBHS_DEVEPTICR_STALLEDIC) + //! Raises STALL sent +#define udd_raise_stall(ep) (USBHS_ARRAY(USBHS_DEVEPTIFR[0], ep) = USBHS_DEVEPTIFR_STALLEDIS) + //! Enables STALL sent interrupt +#define udd_enable_stall_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIER[0], ep) = USBHS_DEVEPTIER_STALLEDES) + //! Disables STALL sent interrupt +#define udd_disable_stall_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIDR[0], ep) = USBHS_DEVEPTIDR_STALLEDEC) + //! Tests if STALL sent interrupt is enabled +#define Is_udd_stall_interrupt_enabled(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTIMR[0], ep), USBHS_DEVEPTIMR_STALLEDE)) + + //! Tests if NAK OUT received +#define Is_udd_nak_out(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTISR[0], ep), USBHS_DEVEPTISR_NAKOUTI)) + //! ACKs NAK OUT received +#define udd_ack_nak_out(ep) (USBHS_ARRAY(USBHS_DEVEPTICR[0], ep) = USBHS_DEVEPTICR_NAKOUTIC) + //! Raises NAK OUT received +#define udd_raise_nak_out(ep) (USBHS_ARRAY(USBHS_DEVEPTIFR[0], ep) = USBHS_DEVEPTIFR_NAKOUTIS) + //! Enables NAK OUT interrupt +#define udd_enable_nak_out_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIER[0], ep) = USBHS_DEVEPTIER_NAKOUTES) + //! Disables NAK OUT interrupt +#define udd_disable_nak_out_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIDR[0], ep) = USBHS_DEVEPTIDR_NAKOUTEC) + //! Tests if NAK OUT interrupt is enabled +#define Is_udd_nak_out_interrupt_enabled(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTIMR[0], ep), USBHS_DEVEPTIMR_NAKOUTE)) + + //! Tests if NAK IN received +#define Is_udd_nak_in(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTISR[0], ep), USBHS_DEVEPTISR_NAKINI)) + //! ACKs NAK IN received +#define udd_ack_nak_in(ep) (USBHS_ARRAY(USBHS_DEVEPTICR[0], ep) = USBHS_DEVEPTICR_NAKINIC) + //! Raises NAK IN received +#define udd_raise_nak_in(ep) (USBHS_ARRAY(USBHS_DEVEPTIFR[0], ep) = USBHS_DEVEPTIFR_NAKINIS) + //! Enables NAK IN interrupt +#define udd_enable_nak_in_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIER[0], ep) = USBHS_DEVEPTIER_NAKINES) + //! Disables NAK IN interrupt +#define udd_disable_nak_in_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIDR[0], ep) = USBHS_DEVEPTIDR_NAKINEC) + //! Tests if NAK IN interrupt is enabled +#define Is_udd_nak_in_interrupt_enabled(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTIMR[0], ep), USBHS_DEVEPTIMR_NAKINE)) + + //! ACKs endpoint isochronous overflow interrupt +#define udd_ack_overflow_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTICR[0], ep) = USBHS_DEVEPTICR_OVERFIC) + //! Raises endpoint isochronous overflow interrupt +#define udd_raise_overflow_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIFR[0], ep) = USBHS_DEVEPTIFR_OVERFIS) + //! Tests if an overflow occurs +#define Is_udd_overflow(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTISR[0], ep), USBHS_DEVEPTISR_OVERFI)) + //! Enables overflow interrupt +#define udd_enable_overflow_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIER[0], ep) = USBHS_DEVEPTIER_OVERFES) + //! Disables overflow interrupt +#define udd_disable_overflow_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIDR[0], ep) = USBHS_DEVEPTIDR_OVERFEC) + //! Tests if overflow interrupt is enabled +#define Is_udd_overflow_interrupt_enabled(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTIMR[0], ep), USBHS_DEVEPTIMR_OVERFE)) + + //! ACKs endpoint isochronous underflow interrupt +#define udd_ack_underflow_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTICR[0], ep) = USBHS_DEVEPTICR_UNDERFIC) + //! Raises endpoint isochronous underflow interrupt +#define udd_raise_underflow_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIFR[0], ep) = USBHS_DEVEPTIFR_UNDERFIS) + //! Tests if an underflow occurs +#define Is_udd_underflow(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTISR[0], ep), USBHS_DEVEPTISR_UNDERFI)) + //! Enables underflow interrupt +#define udd_enable_underflow_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIER[0], ep) = USBHS_DEVEPTIER_UNDERFES) + //! Disables underflow interrupt +#define udd_disable_underflow_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIDR[0], ep) = USBHS_DEVEPTIDR_UNDERFEC) + //! Tests if underflow interrupt is enabled +#define Is_udd_underflow_interrupt_enabled(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTIMR[0], ep), USBHS_DEVEPTIMR_UNDERFE)) + + //! Tests if CRC ERROR ISO OUT detected +#define Is_udd_crc_error(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTISR[0], ep), USBHS_DEVEPTISR_CRCERRI)) + //! ACKs CRC ERROR ISO OUT detected +#define udd_ack_crc_error(ep) (USBHS_ARRAY(USBHS_DEVEPTICR[0], ep) = USBHS_DEVEPTICR_CRCERRIC) + //! Raises CRC ERROR ISO OUT detected +#define udd_raise_crc_error(ep) (USBHS_ARRAY(USBHS_DEVEPTIFR[0], ep) = USBHS_DEVEPTIFR_CRCERRIS) + //! Enables CRC ERROR ISO OUT detected interrupt +#define udd_enable_crc_error_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIER[0], ep) = USBHS_DEVEPTIER_CRCERRES) + //! Disables CRC ERROR ISO OUT detected interrupt +#define udd_disable_crc_error_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIDR[0], ep) = USBHS_DEVEPTIDR_CRCERREC) + //! Tests if CRC ERROR ISO OUT detected interrupt is enabled +#define Is_udd_crc_error_interrupt_enabled(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTIMR[0], ep), USBHS_DEVEPTIMR_CRCERRE)) +//! @} + +//! @name USBHS Device control endpoint transfer +//! These macros control the endpoint transfer. +//! @{ + + //! Tests if endpoint read allowed +#define Is_udd_read_enabled(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTISR[0], ep), USBHS_DEVEPTISR_RWALL)) + //! Tests if endpoint write allowed +#define Is_udd_write_enabled(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTISR[0], ep), USBHS_DEVEPTISR_RWALL)) + + //! Returns the byte count +#define udd_byte_count(ep) (Rd_bitfield(USBHS_ARRAY(USBHS_DEVEPTISR[0], ep), USBHS_DEVEPTISR_BYCT_Msk)) + //! Clears FIFOCON bit +#define udd_ack_fifocon(ep) (USBHS_ARRAY(USBHS_DEVEPTIDR[0], ep) = USBHS_DEVEPTIDR_FIFOCONC) + //! Tests if FIFOCON bit set +#define Is_udd_fifocon(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTIMR[0], ep), USBHS_DEVEPTIMR_FIFOCON)) + + //! Returns the number of busy banks +#define udd_nb_busy_bank(ep) (Rd_bitfield(USBHS_ARRAY(USBHS_DEVEPTISR[0], ep), USBHS_DEVEPTISR_NBUSYBK_Msk)) + //! Returns the number of the current bank +#define udd_current_bank(ep) (Rd_bitfield(USBHS_ARRAY(USBHS_DEVEPTISR[0], ep), USBHS_DEVEPTISR_CURRBK_Msk)) + //! Kills last bank +#define udd_kill_last_in_bank(ep) (USBHS_ARRAY(USBHS_DEVEPTIER[0], ep) = USBHS_DEVEPTIER_KILLBKS) +#define Is_udd_kill_last(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTIMR[0], ep), USBHS_DEVEPTIMR_KILLBK)) + //! Tests if last bank killed +#define Is_udd_last_in_bank_killed(ep) (!Tst_bits(USBHS_ARRAY(USBHS_DEVEPTIMR[0], ep), USBHS_DEVEPTIMR_KILLBK)) + //! Forces all banks full (OUT) or free (IN) interrupt +#define udd_force_bank_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIFR[0], ep) = USBHS_DEVEPTIFR_NBUSYBKS) + //! Unforces all banks full (OUT) or free (IN) interrupt +#define udd_unforce_bank_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIFR[0], ep) = USBHS_DEVEPTIFR_NBUSYBKS) + //! Enables all banks full (OUT) or free (IN) interrupt +#define udd_enable_bank_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIER[0], ep) = USBHS_DEVEPTIER_NBUSYBKES) + //! Disables all banks full (OUT) or free (IN) interrupt +#define udd_disable_bank_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIDR[0], ep) = USBHS_DEVEPTIDR_NBUSYBKEC) + //! Tests if all banks full (OUT) or free (IN) interrupt enabled +#define Is_udd_bank_interrupt_enabled(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTIMR[0], ep), USBHS_DEVEPTIMR_NBUSYBKE)) + + //! Tests if SHORT PACKET received +#define Is_udd_short_packet(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTISR[0], ep), USBHS_DEVEPTISR_SHORTPACKET)) + //! ACKs SHORT PACKET received +#define udd_ack_short_packet(ep) (USBHS_ARRAY(USBHS_DEVEPTICR[0], ep) = USBHS_DEVEPTICR_SHORTPACKETC) + //! Raises SHORT PACKET received +#define udd_raise_short_packet(ep) (USBHS_ARRAY(USBHS_DEVEPTIFR[0], ep) = USBHS_DEVEPTIFR_SHORTPACKETS) + //! Enables SHORT PACKET received interrupt +#define udd_enable_short_packet_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIER[0], ep) = USBHS_DEVEPTIER_SHORTPACKETES) + //! Disables SHORT PACKET received interrupt +#define udd_disable_short_packet_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIDR[0], ep) = USBHS_DEVEPTIDR_SHORTPACKETEC) + //! Tests if SHORT PACKET received interrupt is enabled +#define Is_udd_short_packet_interrupt_enabled(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTIMR[0], ep), USBHS_DEVEPTIMR_SHORTPACKETE)) + + //! Tests if SETUP received +#define Is_udd_setup_received(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTISR[0], ep), USBHS_DEVEPTISR_RXSTPI)) + //! ACKs SETUP received +#define udd_ack_setup_received(ep) (USBHS_ARRAY(USBHS_DEVEPTICR[0], ep) = USBHS_DEVEPTICR_RXSTPIC) + //! Raises SETUP received +#define udd_raise_setup_received(ep) (USBHS_ARRAY(USBHS_DEVEPTIFR[0], ep) = USBHS_DEVEPTIFR_RXSTPIS) + //! Enables SETUP received interrupt +#define udd_enable_setup_received_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIER[0], ep) = USBHS_DEVEPTIER_RXSTPES) + //! Disables SETUP received interrupt +#define udd_disable_setup_received_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIDR[0], ep) = USBHS_DEVEPTIDR_RXSTPEC) + //! Tests if SETUP received interrupt is enabled +#define Is_udd_setup_received_interrupt_enabled(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTIMR[0], ep), USBHS_DEVEPTIMR_RXSTPE)) + + //! Tests if OUT received +#define Is_udd_out_received(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTISR[0], ep), USBHS_DEVEPTISR_RXOUTI)) + //! ACKs OUT received +#define udd_ack_out_received(ep) (USBHS_ARRAY(USBHS_DEVEPTICR[0], ep) = USBHS_DEVEPTICR_RXOUTIC) + //! Raises OUT received +#define udd_raise_out_received(ep) (USBHS_ARRAY(USBHS_DEVEPTIFR[0], ep) = USBHS_DEVEPTIFR_RXOUTIS) + //! Enables OUT received interrupt +#define udd_enable_out_received_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIER[0], ep) = USBHS_DEVEPTIER_RXOUTES) + //! Disables OUT received interrupt +#define udd_disable_out_received_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIDR[0], ep) = USBHS_DEVEPTIDR_RXOUTEC) + //! Tests if OUT received interrupt is enabled +#define Is_udd_out_received_interrupt_enabled(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTIMR[0], ep), USBHS_DEVEPTIMR_RXOUTE)) + + //! Tests if IN sending +#define Is_udd_in_send(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTISR[0], ep), USBHS_DEVEPTISR_TXINI)) + //! ACKs IN sending +#define udd_ack_in_send(ep) (USBHS_ARRAY(USBHS_DEVEPTICR[0], ep) = USBHS_DEVEPTICR_TXINIC) + //! Raises IN sending +#define udd_raise_in_send(ep) (USBHS_ARRAY(USBHS_DEVEPTIFR[0], ep) = USBHS_DEVEPTIFR_TXINIS) + //! Enables IN sending interrupt +#define udd_enable_in_send_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIER[0], ep) = USBHS_DEVEPTIER_TXINES) + //! Disables IN sending interrupt +#define udd_disable_in_send_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIDR[0], ep) = USBHS_DEVEPTIDR_TXINEC) + //! Tests if IN sending interrupt is enabled +#define Is_udd_in_send_interrupt_enabled(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTIMR[0], ep), USBHS_DEVEPTIMR_TXINE)) + + + //! Get 64-, 32-, 16- or 8-bit access to FIFO data register of selected endpoint. + //! @param ep Endpoint of which to access FIFO data register + //! @param scale Data scale in bits: 64, 32, 16 or 8 + //! @return Volatile 64-, 32-, 16- or 8-bit data pointer to FIFO data register + //! @warning It is up to the user of this macro to make sure that all accesses + //! are aligned with their natural boundaries except 64-bit accesses which + //! require only 32-bit alignment. + //! @warning It is up to the user of this macro to make sure that used HSB + //! addresses are identical to the DPRAM internal pointer modulo 32 bits. +#define udd_get_endpoint_fifo_access(ep, scale) \ + (((volatile TPASTE2(U, scale) (*)[0x8000 / ((scale) / 8)])USBHS_RAM_ADDR)[(ep)]) + +//! @name USBHS endpoint DMA drivers +//! These macros manage the common features of the endpoint DMA channels. +//! @{ + + //! Maximum transfer size on USB DMA +#define UDD_ENDPOINT_MAX_TRANS 0x10000 + //! Enables the disabling of HDMA requests by endpoint interrupts +#define udd_enable_endpoint_int_dis_hdma_req(ep) (USBHS_ARRAY(USBHS_DEVEPTIER[0](ep) = USBHS_DEVEPTIER_EPDISHDMAS) + //! Disables the disabling of HDMA requests by endpoint interrupts +#define udd_disable_endpoint_int_dis_hdma_req(ep) (USBHS_ARRAY(USBHS_DEVEPTIDR[0](ep) = USBHS_DEVEPTIDR_EPDISHDMAC) + //! Tests if the disabling of HDMA requests by endpoint interrupts is enabled +#define Is_udd_endpoint_int_dis_hdma_req_enabled(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTIMR[0](ep), USBHS_DEVEPTIMR_EPDISHDMA)) + + //! Raises the selected endpoint DMA channel interrupt +#define udd_raise_endpoint_dma_interrupt(ep) (USBHS->USBHS_DEVIFR = USBHS_DEVIFR_DMA_1 << ((ep) - 1)) + //! Raises the selected endpoint DMA channel interrupt +#define udd_clear_endpoint_dma_interrupt(ep) (USBHS->USBHS_DEVICR = USBHS_DEVISR_DMA_1 << ((ep) - 1)) + //! Tests if an interrupt is triggered by the selected endpoint DMA channel +#define Is_udd_endpoint_dma_interrupt(ep) (Tst_bits(USBHS->USBHS_DEVISR, USBHS_DEVISR_DMA_1 << ((ep) - 1))) + //! Enables the selected endpoint DMA channel interrupt +#define udd_enable_endpoint_dma_interrupt(ep) (USBHS->USBHS_DEVIER = USBHS_DEVIER_DMA_1 << ((ep) - 1)) + //! Disables the selected endpoint DMA channel interrupt +#define udd_disable_endpoint_dma_interrupt(ep) (USBHS->USBHS_DEVIDR = USBHS_DEVIDR_DMA_1 << ((ep) - 1)) + //! Tests if the selected endpoint DMA channel interrupt is enabled +#define Is_udd_endpoint_dma_interrupt_enabled(ep) (Tst_bits(USBHS->USBHS_DEVIMR, USBHS_DEVIMR_DMA_1 << ((ep) - 1))) + + //! Access points to the USBHS device DMA memory map with arrayed registers + //! @{ + //! Structure for DMA next descriptor register +typedef struct { + uint32_t *NXT_DSC_ADD; +} uotghs_dma_nextdesc_t; + //! Structure for DMA control register +typedef struct { + uint32_t CHANN_ENB:1, + LDNXT_DSC:1, + END_TR_EN:1, + END_B_EN:1, + END_TR_IT:1, + END_BUFFIT:1, + DESC_LD_IT:1, + BUST_LCK:1, + reserved:8, + BUFF_LENGTH:16; +} uotghs_dma_control_t; + //! Structure for DMA status register +typedef struct { + uint32_t CHANN_ENB:1, + CHANN_ACT:1, + reserved0:2, + END_TR_ST:1, + END_BF_ST:1, + DESC_LDST:1, + reserved1:9, + BUFF_COUNT:16; +} uotghs_dma_status_t; + //! Structure for DMA descriptor +typedef struct { + union { + uint32_t nextdesc; + uotghs_dma_nextdesc_t NEXTDESC; + }; + uint32_t addr; + union { + uint32_t control; + uotghs_dma_control_t CONTROL; + }; + uint32_t reserved; +} sam_uotghs_dmadesc_t, uotghs_dmadesc_t; + //! Structure for DMA registers in a channel +typedef struct { + union { + uint32_t nextdesc; + uotghs_dma_nextdesc_t NEXTDESC; + }; + uint32_t addr; + union { + uint32_t control; + uotghs_dma_control_t CONTROL; + }; + union { + unsigned long status; + uotghs_dma_status_t STATUS; + }; +} sam_uotghs_dmach_t, uotghs_dmach_t; + //! DMA channel control command +#define UDD_ENDPOINT_DMA_STOP_NOW (0) +#define UDD_ENDPOINT_DMA_RUN_AND_STOP (USBHS_DEVDMACONTROL_CHANN_ENB) +#define UDD_ENDPOINT_DMA_LOAD_NEXT_DESC (USBHS_DEVDMACONTROL_LDNXT_DSC) +#define UDD_ENDPOINT_DMA_RUN_AND_LINK (USBHS_DEVDMACONTROL_CHANN_ENB|USBHS_DEVDMACONTROL_LDNXT_DSC) + //! Structure for DMA registers +#define USBHS_UDDMA_ARRAY(ep) (((volatile uotghs_dmach_t *)USBHS->USBHS_DEVDMA)[(ep) - 1]) + + //! Set control desc to selected endpoint DMA channel +#define udd_endpoint_dma_set_control(ep,desc) (USBHS_UDDMA_ARRAY(ep).control = desc) + //! Get control desc to selected endpoint DMA channel +#define udd_endpoint_dma_get_control(ep) (USBHS_UDDMA_ARRAY(ep).control) + //! Set RAM address to selected endpoint DMA channel +#define udd_endpoint_dma_set_addr(ep,add) (USBHS_UDDMA_ARRAY(ep).addr = add) + //! Get status to selected endpoint DMA channel +#define udd_endpoint_dma_get_status(ep) (USBHS_UDDMA_ARRAY(ep).status) + //! @} +//! @} + +//! @} +//! @} +//! @} +//! @} + + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +#endif /* USBHS_DEVICE_H_INCLUDED */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/usbhs/usbhs_otg.h b/hw-libs/drivers/SAMx70/ASF/sam/drivers/usbhs/usbhs_otg.h new file mode 100644 index 000000000..8afed250b --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/usbhs/usbhs_otg.h @@ -0,0 +1,200 @@ +/** + * \file + * + * \brief USB OTG Driver for USBHS. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef USBHS_OTG_H_INCLUDED +#define USBHS_OTG_H_INCLUDED + +#include "compiler.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Get USB VBus/ID pin configuration in board configuration */ +#include "conf_board.h" +#include "ISBoards.h" +#include "ioport.h" +#include "pio.h" +#include "pio_handler.h" + +__always_inline static void otg_io_pin_init(uint32_t pin, uint32_t flags, + IRQn_Type port_irqn, uint8_t irq_level, + void (*handler)(uint32_t,uint32_t), uint32_t wkup) +{ + // IOPORT must be initialized before by ioport_init(), \see ioport_group. + pio_handler_set_pin(pin, flags, handler); + ioport_set_pin_sense_mode(pin, IOPORT_SENSE_BOTHEDGES); + NVIC_SetPriority(port_irqn, irq_level); + NVIC_EnableIRQ(port_irqn); + pio_enable_pin_interrupt(pin); + if (wkup) { + pmc_set_fast_startup_input(wkup); + } +} + +//! \ingroup usb_group +//! \defgroup otg_group USBHS OTG Driver +//! USBHS low-level driver for OTG features +//! +//! @{ + +/** + * \brief USB interrupt level + * By default USB interrupt have low priority. + */ +#ifndef USB_INT_LEVEL +# define USB_INT_LEVEL 5 +#endif + +/** + * \brief Initialize the dual role + * This function is implemented in usbhs_host.c file. + * + * \return \c true if the ID pin management has been started, otherwise \c false. + */ +bool otg_dual_enable(void); + +/** + * \brief Uninitialize the dual role + * This function is implemented in usbhs_host.c file. + */ +void otg_dual_disable(void); + + +//! @name USBHS OTG ID pin management +//! The ID pin come from the USB OTG connector (A and B receptacle) and +//! allows to select the USB mode host or device. +//! +//! The ID pin can be managed through PIO pin. +//! This feature is optional, and it is enabled if USB_ID_PIN +//! is defined in board.h and CONF_BOARD_USB_ID_DETECT defined in +//! conf_board.h. +//! @{ +#define OTG_ID_DETECT (defined(CONF_BOARD_USB_PORT) && \ + defined(CONF_BOARD_USB_ID_DETECT)) +#define OTG_ID_IO (defined(USB_ID_PIN) && OTG_ID_DETECT) + +#if OTG_ID_IO +#define otg_id_init(handler) otg_io_pin_init(USB_ID_PIN, USB_ID_FLAGS, \ + USB_ID_PIN_IRQn, USB_INT_LEVEL, handler, false) +# define otg_id_interrupt_enable() pio_enable_pin_interrupt(USB_ID_PIN) +# define otg_id_interrupt_disable() pio_disable_pin_interrupt(USB_ID_PIN) +# define Is_otg_id_device() ioport_get_pin_level(USB_ID_PIN) +# define Is_otg_id_host() (!Is_otg_id_device()) +#endif + +#define otg_force_device_mode() (Set_bits(USBHS->USBHS_CTRL, USBHS_CTRL_UIMOD)) + //! Test if device mode is forced +#define Is_otg_device_mode_forced() (Tst_bits(USBHS->USBHS_CTRL, USBHS_CTRL_UIMOD)) + //! Disable external OTG_ID pin and force host mode +#define otg_force_host_mode() (Clr_bits(USBHS->USBHS_CTRL, USBHS_CTRL_UIMOD)) + //! Test if host mode is forced +#define Is_otg_host_mode_forced() (!Tst_bits(USBHS->USBHS_CTRL, USBHS_CTRL_UIMOD)) + +//! @} + +//! @name USBHS OTG VBUS pin management +//! USBHS peripheral does not support VBUS management and it's monitored by a PIO +//! pin. +//! This feature is optional, and it is enabled if USB_VBUS_PIN is defined in +//! board.h and CONF_BOARD_USB_VBUS_DETECT defined in conf_board.h. +//! +//! @note ioport_init() must be invoked before using VBus pin functions since +//! they use IOPORT API, \see ioport_group. +//! +//! @{ +#define OTG_VBUS_DETECT (defined(CONF_BOARD_USB_PORT) && \ + defined(CONF_BOARD_USB_VBUS_DETECT)) +#define OTG_VBUS_IO (defined(USB_VBUS_PIN) && OTG_VBUS_DETECT) +#ifndef USB_VBUS_WKUP +# define USB_VBUS_WKUP 0 +#endif + +#define otg_vbus_init(handler) otg_io_pin_init(USB_VBUS_PIN, USB_VBUS_FLAGS, \ + USB_VBUS_PIN_IRQn, USB_INT_LEVEL, handler, USB_VBUS_WKUP) +#define Is_otg_vbus_high() ioport_get_pin_level(USB_VBUS_PIN) +#define Is_otg_vbus_low() (!Is_otg_vbus_high()) +#define otg_enable_vbus_interrupt() pio_enable_pin_interrupt(USB_VBUS_PIN) +#define otg_disable_vbus_interrupt() pio_disable_pin_interrupt(USB_VBUS_PIN) +//! @} + +//! @name USBHS OTG main management +//! These macros allows to enable/disable pad and USBHS hardware +//! @{ + //! Reset USB macro +#define otg_reset() \ + do { \ + USBHS->USBHS_CTRL = 0; \ + while( USBHS->USBHS_SR & 0x3FFF) {\ + USBHS->USBHS_SCR = 0xFFFFFFFF;\ + } \ + } while (0) + //! Enable USB macro +#define otg_enable() (Set_bits(USBHS->USBHS_CTRL, USBHS_CTRL_USBE)) + //! Disable USB macro +#define otg_disable() (Clr_bits(USBHS->USBHS_CTRL, USBHS_CTRL_USBE)) +#define Is_otg_enabled() (Tst_bits(USBHS->USBHS_CTRL, USBHS_CTRL_USBE)) + + //! Check Clock Usable + //! For parts with HS feature, this one corresponding at UTMI clock +#define Is_otg_clock_usable() (Tst_bits(USBHS->USBHS_SR, USBHS_SR_CLKUSABLE)) + + //! Stop (freeze) internal USB clock +#define otg_freeze_clock() (Set_bits(USBHS->USBHS_CTRL, USBHS_CTRL_FRZCLK)) +#define otg_unfreeze_clock() (Clr_bits(USBHS->USBHS_CTRL, USBHS_CTRL_FRZCLK)) +#define Is_otg_clock_frozen() (Tst_bits(USBHS->USBHS_CTRL, USBHS_CTRL_FRZCLK)) + + //! Enables RDERR interrupt +#define otg_enable_rderr_interrupt() (Set_bits(USBHS->USBHS_CTRL, USBHS_CTRL_RDERRE)) + //! Disables RDERR interrupt +#define otg_disable_rderr_interrupt() (Clr_bits(USBHS->USBHS_CTRL, USBHS_CTRL_RDERRE)) +#define Is_otg_rderr_interrupt_enabled() (Tst_bits(USBHS->USBHS_CTRL, USBHS_CTRL_RDERRE)) + //! ACKs RDERR interrupt +#define otg_ack_rderr_interrupt() (USBHS->USBHS_SCR = USBHS_SCR_RDERRIC) + //! Raises RDERR interrupt +#define otg_raise_rderr_interrupt() (USBHS->USBHS_SFR = USBHS_SFR_RDERRIS) + //! Tests if a RDERR occurs +#define Is_otg_rderr_interrupt() (Tst_bits(USBHS->USBHS_SR, USBHS_SR_RDERRI)) +//! @} + +//! @} + +#ifdef __cplusplus +} +#endif + + +#endif /* USBHS_OTG_H_INCLUDED */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/wdt/wdt.c b/hw-libs/drivers/SAMx70/ASF/sam/drivers/wdt/wdt.c new file mode 100644 index 000000000..0e23b899f --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/wdt/wdt.c @@ -0,0 +1,172 @@ +/** + * \file + * + * \brief Watchdog Timer (WDT) driver for SAM. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#include "wdt.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \defgroup sam_drivers_wdt_group Watchdog Timer (WDT) + * + * Driver for the WDT (Watchdog Timer). This driver provides access to the main + * features of the WDT controller. + * The Watchdog Timer can be used to prevent system lock-up if the software + * becomes trapped in a deadlock. It features a 12-bit down counter that allows + * a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It can + * generate a general reset or a processor reset only. In addition, it can be + * stopped while the processor is in debug mode or idle mode. + * + * @{ + */ + +#define WDT_KEY_PASSWORD 0xA5000000 +#define WDT_SLCK_DIV 128 +#define WDT_MAX_VALUE 4095 + +/** + * \brief Get counter value or permitted range value of watchdog timer from the + * desired timeout period (in us). + * + * \note The value returned by this function can be used by wdt_init() if it is + * not WDT_INVALID_ARGUMENT. + * + * \param ul_us The desired timeout period (in us). + * \param ul_sclk The slow clock on board (in Hz). + * + * \return If the desired period is beyond the watchdog period, this function + * returns WDT_INVALID_ARGUMENT. Otherwise it returns valid value. + */ +uint32_t wdt_get_timeout_value(uint32_t ul_us, uint32_t ul_sclk) +{ + uint32_t max, min; + + min = WDT_SLCK_DIV * 1000000 / ul_sclk; + max = min * WDT_MAX_VALUE; + + if ((ul_us < min) || (ul_us > max)) { + return WDT_INVALID_ARGUMENT; + } + + return WDT_MR_WDV(ul_us / min); +} + +/** + * \brief Initialize watchdog timer with the given mode. + * + * \param p_wdt Pointer to a WDT instance. + * \param ul_mode Bitmask of watchdog timer mode. + * \param us_counter The value loaded in the 12-bit Watchdog Counter. + * \param us_delta The permitted range for reloading the Watchdog Timer. + */ +void wdt_init(Wdt *p_wdt, uint32_t ul_mode, uint16_t us_counter, + uint16_t us_delta) +{ + p_wdt->WDT_MR = ul_mode | + WDT_MR_WDV(us_counter) | WDT_MR_WDD(us_delta); +} + +/** + * \brief Disable the watchdog timer. + */ +void wdt_disable(Wdt *p_wdt) +{ + p_wdt->WDT_MR = WDT_MR_WDDIS; + +} + +/** + * \brief Restart the watchdog timer. + */ +void wdt_restart(Wdt *p_wdt) +{ + if (p_wdt == WDT) { + p_wdt->WDT_CR = WDT_KEY_PASSWORD | WDT_CR_WDRSTT; + } +#if (SAM4C || SAM4CM || SAM4CP) + else { + p_wdt->WDT_CR = RSWDT_CR_KEY(0xC4u) | RSWDT_CR_WDRSTT; + } +#endif +} + +/** + * \brief Check the watchdog timer status. + * + * \return Bitmask of watchdog timer status. + */ +uint32_t wdt_get_status(Wdt *p_wdt) +{ + return p_wdt->WDT_SR; +} + +/** + * \brief Get the timeout period of the WatchDog Timer in microseconds. + * + * \param p_wdt Pointer to a WDT instance. + * \param ul_sclk The slow clock frequency (in Hz). + * + * \return The timeout period in microseconds. + */ +uint32_t wdt_get_us_timeout_period(Wdt *p_wdt, uint32_t ul_sclk) +{ + return WDT_MR_WDV(p_wdt->WDT_MR) * WDT_SLCK_DIV / ul_sclk * 1000000; +} + +//@} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/wdt/wdt.h b/hw-libs/drivers/SAMx70/ASF/sam/drivers/wdt/wdt.h new file mode 100644 index 000000000..13a57f5a2 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/wdt/wdt.h @@ -0,0 +1,78 @@ +/** + * \file + * + * \brief Watchdog Timer (WDT) driver for SAM. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef WDT_H_INCLUDED +#define WDT_H_INCLUDED + +#include "compiler.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +#define WDT_INVALID_ARGUMENT 0xFFFF + +uint32_t wdt_get_timeout_value(uint32_t ul_us, uint32_t ul_sclk); +void wdt_init(Wdt *p_wdt, uint32_t ul_mode, uint16_t us_counter, + uint16_t us_delta); +void wdt_disable(Wdt *p_wdt); +void wdt_restart(Wdt *p_wdt); +uint32_t wdt_get_status(Wdt *p_wdt); +uint32_t wdt_get_us_timeout_period(Wdt *p_wdt, uint32_t ul_sclk); + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +#endif /* WDT_H_INCLUDED */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/xdmac/xdmac.c b/hw-libs/drivers/SAMx70/ASF/sam/drivers/xdmac/xdmac.c new file mode 100644 index 000000000..54d308068 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/xdmac/xdmac.c @@ -0,0 +1,62 @@ +/** + * \file + * + * \brief SAM XDMA Controller (XDMAC) driver. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "xdmac.h" + +/** + * \brief Configure DMA for a transfer. + * + * \param[out] xdmac Module hardware register base address pointer. + * \param[in] channel_num The used channel number. + * \param[in] cfg The configuration for used channel + */ +void xdmac_configure_transfer(Xdmac *xdmac, + uint32_t channel_num, xdmac_channel_config_t *cfg) +{ + Assert(xdmac); + Assert(channel_num < XDMACCHID_NUMBER); + Assert(cfg); + + xdmac_channel_get_interrupt_status( xdmac, channel_num); + xdmac_channel_set_source_addr(xdmac, channel_num, cfg->mbr_sa); + xdmac_channel_set_destination_addr(xdmac, channel_num, cfg->mbr_da); + xdmac_channel_set_microblock_control(xdmac, channel_num, cfg->mbr_ubc); + xdmac_channel_set_block_control(xdmac, channel_num, cfg->mbr_bc); + xdmac_channel_set_datastride_mempattern(xdmac, channel_num, cfg->mbr_ds); + xdmac_channel_set_source_microblock_stride(xdmac, channel_num, cfg->mbr_sus); + xdmac_channel_set_destination_microblock_stride(xdmac, channel_num, cfg->mbr_dus); + xdmac_channel_set_config(xdmac, channel_num, cfg->mbr_cfg ); +} \ No newline at end of file diff --git a/hw-libs/drivers/SAMx70/ASF/sam/drivers/xdmac/xdmac.h b/hw-libs/drivers/SAMx70/ASF/sam/drivers/xdmac/xdmac.h new file mode 100644 index 000000000..148f68d35 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/drivers/xdmac/xdmac.h @@ -0,0 +1,844 @@ +/** + * \file + * + * \brief SAM XDMA Controller (DMAC) driver. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef XDMAC_H_INCLUDED +#define XDMAC_H_INCLUDED + +/** + * \defgroup asfdoc_sam_drivers_xdmac_group SAMV71/V70/E70/S70 XDMA Controller (XDMAC) Driver + * + * This driver for Atmel® | SMART SAM XDMA Controller (XDMAC) is a AHB-protocol central + * direct memory access controller. It performs peripheral data transfer and memory move operations + * over one or two bus ports through the unidirectional communication channel. + * This is a driver for the configuration, enabling, disabling, and use of the XDMAC peripheral. + * + * Devices from the following series can use this module: + * - Atmel | SMART SAMV71 + * - Atmel | SMART SAMV70 + * - Atmel | SMART SAMS70 + * - Atmel | SMART SAME70 + * + * The outline of this documentation is as follows: + * - \ref asfdoc_sam_drivers_xdmac_prerequisites + * - \ref asfdoc_sam_drivers_xdmac_module_overview + * - \ref asfdoc_sam_drivers_xdmac_special_considerations + * - \ref asfdoc_sam_drivers_xdmac_extra_info + * - \ref asfdoc_sam_drivers_xdmac_examples + * - \ref asfdoc_sam_drivers_xdmac_api_overview + * + * + * \section asfdoc_sam_drivers_xdmac_prerequisites Prerequisites + * + * There are no prerequisites for this module. + * + * + * \section asfdoc_sam_drivers_xdmac_module_overview Module Overview + * The DMA Controller (XDMAC) is a AHB-protocol central direct memory access controller. + * It performs peripheral data transfer and memory move operations over one or two bus ports + * through the unidirectional communication channel. Each channel is fully programmable and + * provides both peripheral or memory to memory transfer. The channel features are configurable + * at implementation time. + * + * + * \section asfdoc_sam_drivers_xdmac_special_considerations Special Considerations + * There are no special considerations for this module. + * + * + * \section asfdoc_sam_drivers_xdmac_extra_info Extra Information + * + * For extra information, see \ref asfdoc_sam_drivers_xdmac_extra. This includes: + * - \ref asfdoc_sam_drivers_xdmac_extra_acronyms + * - \ref asfdoc_sam_drivers_xdmac_extra_dependencies + * - \ref asfdoc_sam_drivers_xdmac_extra_errata + * - \ref asfdoc_sam_drivers_xdmac_extra_history + * + * \section asfdoc_sam_drivers_xdmac_examples Examples + * + * For a list of examples related to this driver, see + * \ref asfdoc_sam_drivers_xdmac_exqsg. + * + * + * \section asfdoc_sam_drivers_xdmac_api_overview API Overview + * @{ + */ + +#include +#include + +/** @cond */ +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/** @endcond */ + +#include "conf_board.h" + +/** DMA channel hardware interface number */ +#define XDMAC_CHANNEL_HWID_HSMCI 0 +#define XDMAC_CHANNEL_HWID_SPI0_TX 1 +#define XDMAC_CHANNEL_HWID_SPI0_RX 2 +#define XDMAC_CHANNEL_HWID_SPI1_TX 3 +#define XDMAC_CHANNEL_HWID_SPI1_RX 4 +#define XDMAC_CHANNEL_HWID_QSPI_TX 5 +#define XDMAC_CHANNEL_HWID_QSPI_RX 6 +#define XDMAC_CHANNEL_HWID_USART0_TX 7 +#define XDMAC_CHANNEL_HWID_USART0_RX 8 +#define XDMAC_CHANNEL_HWID_USART1_TX 9 +#define XDMAC_CHANNEL_HWID_USART1_RX 10 +#define XDMAC_CHANNEL_HWID_USART2_TX 11 +#define XDMAC_CHANNEL_HWID_USART2_RX 12 +#define XDMAC_CHANNEL_HWID_PWM0 13 +#define XDMAC_CHANNEL_HWID_TWIHS0_TX 14 +#define XDMAC_CHANNEL_HWID_TWIHS0_RX 15 +#define XDMAC_CHANNEL_HWID_TWIHS1_TX 16 +#define XDMAC_CHANNEL_HWID_TWIHS1_RX 17 +#define XDMAC_CHANNEL_HWID_TWIHS2_TX 18 +#define XDMAC_CHANNEL_HWID_TWIHS2_RX 19 +#define XDMAC_CHANNEL_HWID_UART0_TX 20 +#define XDMAC_CHANNEL_HWID_UART0_RX 21 +#define XDMAC_CHANNEL_HWID_UART1_TX 22 +#define XDMAC_CHANNEL_HWID_UART1_RX 23 +#define XDMAC_CHANNEL_HWID_UART2_TX 24 +#define XDMAC_CHANNEL_HWID_UART2_RX 25 +#define XDMAC_CHANNEL_HWID_UART3_TX 26 +#define XDMAC_CHANNEL_HWID_UART3_RX 27 +#define XDMAC_CHANNEL_HWID_UART4_TX 28 +#define XDMAC_CHANNEL_HWID_UART4_RX 29 +#define XDMAC_CHANNEL_HWID_DAC 30 +#define XDMAC_CHANNEL_HWID_SSC_TX 32 +#define XDMAC_CHANNEL_HWID_SSC_RX 33 +#define XDMAC_CHANNEL_HWID_PIOA 34 +#define XDMAC_CHANNEL_HWID_AFEC0 35 +#define XDMAC_CHANNEL_HWID_AFEC1 36 +#define XDMAC_CHANNEL_HWID_AES_TX 37 +#define XDMAC_CHANNEL_HWID_AES_RX 38 +#define XDMAC_CHANNEL_HWID_PWM1 39 +#define XDMAC_CHANNEL_HWID_TC0 40 +#define XDMAC_CHANNEL_HWID_TC1 41 +#define XDMAC_CHANNEL_HWID_TC2 42 +#define XDMAC_CHANNEL_HWID_TC3 43 + +/* XDMA_MBR_UBC */ +#define XDMAC_UBC_NDE (0x1u << 24) +#define XDMAC_UBC_NDE_FETCH_DIS (0x0u << 24) +#define XDMAC_UBC_NDE_FETCH_EN (0x1u << 24) +#define XDMAC_UBC_NSEN (0x1u << 25) +#define XDMAC_UBC_NSEN_UNCHANGED (0x0u << 25) +#define XDMAC_UBC_NSEN_UPDATED (0x1u << 25) +#define XDMAC_UBC_NDEN (0x1u << 26) +#define XDMAC_UBC_NDEN_UNCHANGED (0x0u << 26) +#define XDMAC_UBC_NDEN_UPDATED (0x1u << 26) +#define XDMAC_UBC_NVIEW_Pos 27 +#define XDMAC_UBC_NVIEW_Msk (0x3u << XDMAC_UBC_NVIEW_Pos) +#define XDMAC_UBC_NVIEW_NDV0 (0x0u << XDMAC_UBC_NVIEW_Pos) +#define XDMAC_UBC_NVIEW_NDV1 (0x1u << XDMAC_UBC_NVIEW_Pos) +#define XDMAC_UBC_NVIEW_NDV2 (0x2u << XDMAC_UBC_NVIEW_Pos) +#define XDMAC_UBC_NVIEW_NDV3 (0x3u << XDMAC_UBC_NVIEW_Pos) +#define XDMAC_UBC_UBLEN_Pos 0 +#define XDMAC_UBC_UBLEN_Msk (0xffffffu << XDMAC_UBC_UBLEN_Pos) +#define XDMAC_UBC_UBLEN(value) ((XDMAC_UBC_UBLEN_Msk & ((value) << XDMAC_UBC_UBLEN_Pos))) + +// added by InertialSense +#define DMA_CHAN_BUSY(_ch_) (xdmac_channel_get_status(XDMAC) & (1 << (_ch_))) + +/** XDMA config register for channel */ +typedef struct { + /** Microblock Control Member. */ + uint32_t mbr_ubc; + /** Source Address Member. */ + uint32_t mbr_sa; + /** Destination Address Member. */ + uint32_t mbr_da; + /** Configuration Register. */ + uint32_t mbr_cfg; + /** Block Control Member. */ + uint32_t mbr_bc; + /** Data Stride Member. */ + uint32_t mbr_ds; + /** Source Microblock Stride Member. */ + uint32_t mbr_sus; + /** Destination Microblock Stride Member. */ + uint32_t mbr_dus; +} xdmac_channel_config_t; + +/** + * \brief Structure for storing parameters for DMA view0 that can be + * performed by the DMA Master transfer. + */ +typedef struct { + /** Next Descriptor Address number. */ + uint32_t mbr_nda; + /** Microblock Control Member. */ + uint32_t mbr_ubc; + /** Transfer Address Member. */ + uint32_t mbr_ta; +} lld_view0; + +/** + * \brief Structure for storing parameters for DMA view1 that can be + * performed by the DMA Master transfer. + */ +typedef struct { + /** Next Descriptor Address number. */ + uint32_t mbr_nda; + /** Microblock Control Member. */ + uint32_t mbr_ubc; + /** Source Address Member. */ + uint32_t mbr_sa; + /** Destination Address Member. */ + uint32_t mbr_da; +} lld_view1; + +/** + * \brief Structure for storing parameters for DMA view2 that can be + * performed by the DMA Master transfer. + */ +typedef struct { + /** Next Descriptor Address number. */ + uint32_t mbr_nda; + /** Microblock Control Member. */ + uint32_t mbr_ubc; + /** Source Address Member. */ + uint32_t mbr_sa; + /** Destination Address Member. */ + uint32_t mbr_da; + /** Configuration Register. */ + uint32_t mbr_cfg; +} lld_view2; + +/** + * \brief Structure for storing parameters for DMA view3 that can be + * performed by the DMA Master transfer. + */ +typedef struct { + /** Next Descriptor Address number. */ + uint32_t mbr_nda; + /** Microblock Control Member. */ + uint32_t mbr_ubc; + /** Source Address Member. */ + uint32_t mbr_sa; + /** Destination Address Member. */ + uint32_t mbr_da; + /** Configuration Register. */ + uint32_t mbr_cfg; + /** Block Control Member. */ + uint32_t mbr_bc; + /** Data Stride Member. */ + uint32_t mbr_ds; + /** Source Microblock Stride Member. */ + uint32_t mbr_sus; + /** Destination Microblock Stride Member. */ + uint32_t mbr_dus; +} lld_view3; + +/** + * \brief Get XDMAC global type. + * + * \param[out] xdmac Module hardware register base address pointer. + */ +static inline uint32_t xdmac_get_type( Xdmac *xdmac) +{ + Assert(xdmac); + return xdmac->XDMAC_GTYPE; +} + +/** + * \brief Get XDMAC global configuration. + * + * \param[out] xdmac Module hardware register base address pointer. + */ +static inline uint32_t xdmac_get_config(Xdmac *xdmac) +{ + Assert(xdmac); + return xdmac->XDMAC_GCFG; +} + +/** + * \brief Get XDMAC global weighted arbiter configuration. + * + * \param[out] xdmac Module hardware register base address pointer. + */ +static inline uint32_t xdmac_get_arbiter(Xdmac *xdmac) +{ + Assert(xdmac); + return xdmac->XDMAC_GWAC; +} + +/** + * \brief Enables XDMAC global interrupt. + * + * \param[out] xdmac Module hardware register base address pointer. + * \param[in] channel_num XDMA Channel number (range 0 to 23). + */ +static inline void xdmac_enable_interrupt(Xdmac *xdmac, uint32_t channel_num) +{ + Assert(xdmac); + xdmac->XDMAC_GIE = ( XDMAC_GIE_IE0 << channel_num) ; +} + +/** + * \brief Disables XDMAC global interrupt + * + * \param[out] xdmac Module hardware register base address pointer. + * \param[in] channel_num XDMA Channel number (range 0 to 23). + */ +static inline void xdmac_disable_interrupt(Xdmac *xdmac, uint32_t channel_num) +{ + Assert(xdmac); + xdmac->XDMAC_GID = (XDMAC_GID_ID0 << channel_num); +} + +/** + * \brief Get XDMAC global interrupt mask. + * + * \param[out] xdmac Module hardware register base address pointer. + */ +static inline uint32_t xdmac_get_interrupt_mask(Xdmac *xdmac) +{ + Assert(xdmac); + return (xdmac->XDMAC_GIM); +} + +/** + * \brief Get XDMAC global interrupt status. + * + * \param[out] xdmac Module hardware register base address pointer. + */ +static inline uint32_t xdmac_get_interrupt_status(Xdmac *xdmac) +{ + Assert(xdmac); + return (xdmac->XDMAC_GIS); +} + +/** + * \brief enables the relevant channel of given XDMAC. + * + * \param[out] xdmac Module hardware register base address pointer. + * \param[in] channel_num XDMA Channel number (range 0 to 23) + */ +static inline void xdmac_channel_enable(Xdmac *xdmac, uint32_t channel_num) +{ + Assert(xdmac); + Assert(channel_num < XDMACCHID_NUMBER); + + /* Update DCache before DMA transmit */ +#if CONF_BOARD_ENABLE_DCACHE == 1 + SCB_CleanInvalidateDCache(); +#endif + + xdmac->XDMAC_GE = (XDMAC_GE_EN0 << channel_num); +} + +/** + * \brief enables the relevant channel of given XDMAC without invalidating data cache. + * + * \param[out] xdmac Module hardware register base address pointer. + * \param[in] channel_num XDMA Channel number (range 0 to 23) + */ +static inline void xdmac_channel_enable_no_cache(Xdmac *xdmac, uint32_t channel_num) +{ + Assert(xdmac); + Assert(channel_num < XDMACCHID_NUMBER); + xdmac->XDMAC_GE = (XDMAC_GE_EN0 << channel_num); +} + +/** + * \brief Disables the relevant channel of given XDMAC. + * + * \param[out] xdmac Module hardware register base address pointer. + * \param[in] channel_num XDMA Channel number (range 0 to 23) + */ +static inline void xdmac_channel_disable(Xdmac *xdmac, uint32_t channel_num) +{ + Assert(xdmac); + Assert(channel_num < XDMACCHID_NUMBER); + xdmac->XDMAC_GD =(XDMAC_GD_DI0 << channel_num); +} + +/** + * \brief Get Global channel status of given XDMAC. + * \note: When set to 1, this bit indicates that the channel x is enabled. + If a channel disable request is issued, this bit remains asserted + until pending transaction is completed. + * \param[out] xdmac Module hardware register base address pointer. + */ +static inline uint32_t xdmac_channel_get_status(Xdmac *xdmac) +{ + Assert(xdmac); + return xdmac->XDMAC_GS; +} + +/** + * \brief Suspend the relevant channel's read. + * + * \param[out] xdmac Module hardware register base address pointer. + * \param[in] channel_num XDMA Channel number (range 0 to 23). + */ +static inline void xdmac_channel_read_suspend(Xdmac *xdmac, uint32_t channel_num) +{ + Assert(xdmac); + Assert(channel_num < XDMACCHID_NUMBER); + xdmac->XDMAC_GRS |= XDMAC_GRS_RS0 << channel_num; +} + +/** + * \brief Suspend the relevant channel's write. + * + * \param[out] xdmac Module hardware register base address pointer. + * \param[in] channel_num XDMA Channel number (range 0 to 23). + */ +static inline void xdmac_channel_write_suspend(Xdmac *xdmac, uint32_t channel_num) +{ + Assert(xdmac); + Assert(channel_num < XDMACCHID_NUMBER); + xdmac->XDMAC_GWS |= XDMAC_GWS_WS0 << channel_num; +} + +/** + * \brief Suspend the relevant channel's read & write. + * + * \param[out] xdmac Module hardware register base address pointer. + * \param[in] channel_num XDMA Channel number (range 0 to 23). + */ +static inline void xdmac_channel_readwrite_suspend(Xdmac *xdmac, uint32_t channel_num) +{ + Assert(xdmac); + Assert(channel_num < XDMACCHID_NUMBER); + xdmac->XDMAC_GRWS = (XDMAC_GRWS_RWS0 << channel_num); +} + +/** + * \brief Resume the relevant channel's read & write. + * + * \param[out] xdmac Module hardware register base address pointer. + * \param[in] channel_num XDMA Channel number (range 0 to 23). + */ +static inline void xdmac_channel_readwrite_resume(Xdmac *xdmac, uint32_t channel_num) +{ + Assert(xdmac); + Assert(channel_num < XDMACCHID_NUMBER); + xdmac->XDMAC_GRWR = (XDMAC_GRWR_RWR0 << channel_num); +} + +/** + * \brief Set software transfer request on the relevant channel. + * + * \param[out] xdmac Module hardware register base address pointer. + * \param[in] channel_num XDMA Channel number (range 0 to 23). + */ +static inline void xdmac_channel_software_request(Xdmac *xdmac, uint32_t channel_num) +{ + Assert(xdmac); + Assert(channel_num < XDMACCHID_NUMBER); + xdmac->XDMAC_GSWR = (XDMAC_GSWR_SWREQ0 << channel_num); +} + +/** + * \brief Get software transfer status of the relevant channel. + * + * \param[out] xdmac Module hardware register base address pointer. + */ +static inline uint32_t xdmac_get_software_request_status(Xdmac *xdmac) +{ + Assert(xdmac); + return xdmac->XDMAC_GSWS; +} + +/** + * \brief Enable interrupt with mask on the relevant channel of given XDMA. + * + * \param[out] xdmac Module hardware register base address pointer. + * \param[in] channel_num XDMA Channel number (range 0 to 23). + * \param[in] mask Interrupt mask. + */ +static inline void xdmac_channel_enable_interrupt(Xdmac *xdmac, uint32_t channel_num, uint32_t mask) +{ + Assert(xdmac); + Assert(channel_num < XDMACCHID_NUMBER); + xdmac->XDMAC_CHID[channel_num].XDMAC_CIE = mask; +} + +/** + * \brief Disable interrupt with mask on the relevant channel of given XDMA. + * + * \param[out] xdmac Module hardware register base address pointer. + * \param[in] channel_num XDMA Channel number (range 0 to 23). + * \param[in] mask Interrupt mask. + */ +static inline void xdmac_channel_disable_interrupt(Xdmac *xdmac, uint32_t channel_num, uint32_t mask) +{ + Assert(xdmac); + Assert(channel_num < XDMACCHID_NUMBER); + xdmac->XDMAC_CHID[channel_num].XDMAC_CID = mask; +} + +/** + * \brief Get interrupt mask for the relevant channel of given XDMA. + * + * \param[out] xdmac Module hardware register base address pointer. + * \param[in] channel_num XDMA Channel number (range 0 to 23). + */ +static inline uint32_t xdmac_channel_get_interrupt_mask(Xdmac *xdmac, uint32_t channel_num) +{ + Assert(xdmac); + Assert(channel_num < XDMACCHID_NUMBER); + return xdmac->XDMAC_CHID[channel_num].XDMAC_CIM; +} + +/** + * \brief Get interrupt status for the relevant channel of given XDMA. + * + * \param[out] xdmac Module hardware register base address pointer. + * \param[in] channel_num XDMA Channel number (range 0 to 23). + */ +static inline uint32_t xdmac_channel_get_interrupt_status(Xdmac *xdmac, uint32_t channel_num) +{ + Assert(xdmac); + Assert(channel_num < XDMACCHID_NUMBER); + return xdmac->XDMAC_CHID[channel_num].XDMAC_CIS; +} + +/** + * \brief Set software flush request on the relevant channel. + * + * \param[out] xdmac Module hardware register base address pointer. + * \param[in] channel_num XDMA Channel number (range 0 to 23). + */ +static inline void xdmac_channel_software_flush_request(Xdmac *xdmac, uint32_t channel_num) +{ + Assert(xdmac); + Assert(channel_num < XDMACCHID_NUMBER); + xdmac->XDMAC_GSWF = (XDMAC_GSWF_SWF0 << channel_num); + while( !(xdmac_channel_get_interrupt_status(xdmac, channel_num) & XDMAC_CIS_FIS) ); +} + +/** + * \brief Set source address for the relevant channel of given XDMA. + * + * \param[out] xdmac Module hardware register base address pointer + * \param[in] channel_num DMA Channel number (range 0 to 23) + * \param[in] src_addr Source address + */ +static inline void xdmac_channel_set_source_addr(Xdmac *xdmac, uint32_t channel_num, uint32_t src_addr) +{ + Assert(xdmac); + Assert(channel_num < XDMACCHID_NUMBER); + xdmac->XDMAC_CHID[channel_num].XDMAC_CSA = src_addr; +} + +/** + * \brief Set destination address for the relevant channel of given XDMA. + * + * \param[out] xdmac Module hardware register base address pointer + * \param[in] channel_num DMA Channel number (range 0 to 23) + * \param[in] dst_addr Destination address + */ +static inline void xdmac_channel_set_destination_addr(Xdmac *xdmac, uint32_t channel_num, uint32_t dst_addr) +{ + Assert(xdmac); + Assert(channel_num < XDMACCHID_NUMBER); + xdmac->XDMAC_CHID[channel_num].XDMAC_CDA = dst_addr; +} + +/** + * \brief Set next descriptor's address & interface for the relevant channel of given XDMA. + * + * \param[out] xdmac Module hardware register base address pointer + * \param[in] channel_num DMA Channel number (range 0 to 23) + * \param[in] desc_addr Address of next descriptor. + * \param[in] ndaif Interface of next descriptor. + */ +static inline void xdmac_channel_set_descriptor_addr(Xdmac *xdmac, uint32_t channel_num, + uint32_t desc_addr, uint8_t ndaif) +{ + Assert(xdmac); + Assert(channel_num < XDMACCHID_NUMBER); + Assert(ndaif<2); + xdmac->XDMAC_CHID[channel_num].XDMAC_CNDA = (desc_addr & 0xFFFFFFFC) | ndaif; +} + +/** + * \brief Set next descriptor's configuration for the relevant channel of given XDMA. + * + * \param[out] xdmac Module hardware register base address pointer + * \param[in] channel_num DMA Channel number (range 0 to 23) + * \param[in] config Configuration of next descriptor. + */ +static inline void xdmac_channel_set_descriptor_control(Xdmac *xdmac, uint32_t channel_num, uint32_t config) +{ + Assert(xdmac); + Assert(channel_num < XDMACCHID_NUMBER); + xdmac->XDMAC_CHID[channel_num].XDMAC_CNDC = config; +} + +/** + * \brief Set microblock length for the relevant channel of given XDMA. + * + * \param[out] xdmac Module hardware register base address pointer + * \param[in] channel_num DMA Channel number (range 0 to 23) + * \param[in] ublen Microblock length. + */ +static inline void xdmac_channel_set_microblock_control(Xdmac *xdmac, uint32_t channel_num, uint32_t ublen) +{ + Assert(xdmac); + Assert(channel_num < XDMACCHID_NUMBER); + xdmac->XDMAC_CHID[channel_num].XDMAC_CUBC = XDMAC_CUBC_UBLEN(ublen); +} + +/** + * \brief Set block length for the relevant channel of given XDMA. + * + * \param[out] xdmac Module hardware register base address pointer + * \param[in] channel_num XDMA Channel number (range 0 to 23) + * \param[in] blen Block length. + */ +static inline void xdmac_channel_set_block_control(Xdmac *xdmac, uint32_t channel_num, uint32_t blen) +{ + Assert(xdmac); + Assert(channel_num < XDMACCHID_NUMBER); + xdmac->XDMAC_CHID[channel_num].XDMAC_CBC = XDMAC_CBC_BLEN(blen); +} + +/** + * \brief Set configuration for the relevant channel of given XDMA. + * + * \param[out] xdmac Module hardware register base address pointer + * \param[in] channel_num XDMA Channel number (range 0 to 23) + * \param[in] config Channel configuration. + */ +static inline void xdmac_channel_set_config(Xdmac *xdmac, uint32_t channel_num, uint32_t config) +{ + Assert(xdmac); + Assert(channel_num < XDMACCHID_NUMBER); + xdmac->XDMAC_CHID[channel_num].XDMAC_CC = config; +} + +/** + * \brief Set the relevant channel's data stride memory pattern of given XDMA. + * + * \param[out] xdmac Module hardware register base address pointer + * \param[in] channel_num XDMA Channel number (range 0 to 23) + * \param[in] dds_msp Data stride memory pattern. + */ +static inline void xdmac_channel_set_datastride_mempattern(Xdmac *xdmac, uint32_t channel_num, uint32_t dds_msp) +{ + Assert(xdmac); + Assert(channel_num < XDMACCHID_NUMBER); + xdmac->XDMAC_CHID[channel_num].XDMAC_CDS_MSP = dds_msp; +} + +/** + * \brief Set the relevant channel's source microblock stride of given XDMA. + * + * \param[out] xdmac Module hardware register base address pointer + * \param[in] channel_num XDMA Channel number (range 0 to 23) + * \param[in] subs Source microblock stride. + */ +static inline void xdmac_channel_set_source_microblock_stride(Xdmac *xdmac, + uint32_t channel_num, uint32_t subs) +{ + Assert(xdmac); + Assert(channel_num < XDMACCHID_NUMBER); + xdmac->XDMAC_CHID[channel_num].XDMAC_CSUS = XDMAC_CSUS_SUBS(subs); +} + +/** + * \brief Set the relevant channel's destination microblock stride of given XDMA. + * + * \param[out] xdmac Module hardware register base address pointer + * \param[in] channel_num XDMA Channel number (range 0 to 23) + * \param[in] dubs Destination microblock stride. + */ +static inline void xdmac_channel_set_destination_microblock_stride(Xdmac *xdmac, + uint32_t channel_num, uint32_t dubs) +{ + Assert(xdmac); + Assert(channel_num < XDMACCHID_NUMBER); + xdmac->XDMAC_CHID[channel_num].XDMAC_CDUS = XDMAC_CDUS_DUBS(dubs); +} + +void xdmac_configure_transfer(Xdmac *xdmac, uint32_t channel_num, + xdmac_channel_config_t *p_cfg); + +/** @cond */ +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/** @endcond */ + + /** @} */ + +/** + * \page asfdoc_sam_drivers_xdmac_extra Extra Information for Extensible Direct Memory Access Controller Driver + * + * \section asfdoc_sam_drivers_xdmac_extra_acronyms Acronyms + * Below is a table listing the acronyms used in this module, along with their + * intended meanings. + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
AcronymDefinition
AHBAMBA High-performance Bus
AMBAAdvanced Microcontroller Bus Architecture
FIFOFirst In First Out
LLDLinked List Descriptor
QSGQuick Start Guide
+ * + * + * \section asfdoc_sam_drivers_xdmac_extra_dependencies Dependencies + * This driver has the following dependencies: + * + * - None + * + * + * \section asfdoc_sam_drivers_xdmac_extra_errata Errata + * There are no errata related to this driver. + * + * + * \section asfdoc_sam_drivers_xdmac_extra_history Module History + * An overview of the module history is presented in the table below, with + * details on the enhancements and fixes made to the module since its first + * release. The current version of this corresponds to the newest version in + * the table. + * + * + * + * + * + * + * + * + *
Changelog
Initial document release
+ */ + +/** + * \page asfdoc_sam_drivers_xdmac_exqsg Examples for Direct Memory Access Controller Driver + * + * This is a list of the available Quick Start Guides (QSGs) and example + * applications for \ref asfdoc_sam_drivers_xdmac_group. QSGs are simple examples with + * step-by-step instructions to configure and use this driver in a selection of + * use cases. Note that QSGs can be compiled as a standalone application or be + * added to the user application. + * + * - \subpage asfdoc_sam_drivers_xdmac_qsg + * - \subpage asfdoc_sam_drivers_xdmac_example + * + * \page asfdoc_sam_drivers_xdmac_document_revision_history Document Revision History + * + * + * + * + * + * + * + * + * + *
Doc. Rev. + * Date + * Comments + *
XXXXXA08/2015Initial document release
+ * + */ + + /** + * \page asfdoc_sam_drivers_xdmac_qsg Quick Start Guide for the XDMAC driver + * + * This is the quick start guide for the \ref asfdoc_sam_drivers_xdmac_group, with + * step-by-step instructions on how to configure and use the driver for + * a specific use case.The code examples can be copied into e.g the main + * application loop or any other function that will need to control the + * XDMAC module. + * + * \section asfdoc_sam_drivers_xdmac_qsg_use_cases Use Cases + * - \ref asfdoc_sam_drivers_xdmac_qsg_basic + * + * \section asfdoc_sam_drivers_xdmac_qsg_basic XDMAC Basic Usage + * + * This use case will demonstrate how to config the XDMAC module to + * perform a single memory to memory transfer. + * + * + * \section asfdoc_sam_drivers_xdmac_qsg_basic_setup Setup Steps + * + * \subsection asfdoc_sam_drivers_xdmac_qsg_basic_prereq Prerequisites + * + * This module requires the following service + * - \ref clk_group "System Clock Management (sysclock)" + * + * \subsection asfdoc_sam_drivers_xdmac_qsg_basic_setup_code Setup Code + * + * Add these macros and global variable to the top of your application's C-file: + * \snippet xdmac_example.c xdmac_define_channel + * \snippet xdmac_example.c xdmac_define_buffer + * + * Add this to the main loop or a setup function: + * \snippet xdmac_example.c xdmac_configure_transfer + * + * \subsection asfdoc_sam_drivers_xdmac_qsg_basic_setup_workflow Workflow + * + * -# Configure XDMAC transfer: + * \snippet xdmac_example.c xdmac_configure_transfer + * -# Enable the XDMAC interrupt: + * \snippet xdmac_example.c xdmac_enable_interrupt + * \snippet xdmac_example.c xdmac_channel_enable_interrupt + * -# Eanble the channel: + * \snippet xdmac_example.c xdmac_channel_enable + * + */ + +#endif /* XDMAC_H_INCLUDED */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/services/flash_efc/flash_efc.c b/hw-libs/drivers/SAMx70/ASF/sam/services/flash_efc/flash_efc.c new file mode 100644 index 000000000..85754fd2a --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/services/flash_efc/flash_efc.c @@ -0,0 +1,1081 @@ +/** + * \file + * + * \brief Embedded Flash service for SAM. + * + * Copyright (c) 2011-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#include +#include +#include "flash_efc.h" +#include "sysclk.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \defgroup sam_services_flash_efc_group Embedded Flash Service + * + * The Embedded Flash service provides functions for internal flash operations. + * + * @{ + */ + +#if (SAM4E || SAM4N || SAM4S || SAM4C || SAMG || SAM4CP || SAM4CM || \ + SAMV71 || SAMV70 || SAMS70 || SAME70) +/* User signature size */ +# define FLASH_USER_SIG_SIZE (512) +#endif + +#if SAM4S +/* Internal Flash Controller 0. */ +# define EFC EFC0 +#if (SAM4SD16 || SAM4SD32) +/* The max GPNVM number. */ +# define GPNVM_NUM_MAX 3 +#else +/* The max GPNVM number. */ +# define GPNVM_NUM_MAX 2 +#endif +/* Internal Flash 0 base address. */ +# define IFLASH_ADDR IFLASH0_ADDR +/* Internal flash page size. */ +# define IFLASH_PAGE_SIZE IFLASH0_PAGE_SIZE +/* Internal flash lock region size. */ +# define IFLASH_LOCK_REGION_SIZE IFLASH0_LOCK_REGION_SIZE +#elif (SAM3XA || SAM3U4) +/* Internal Flash Controller 0. */ +# define EFC EFC0 +/* The max GPNVM number. */ +# define GPNVM_NUM_MAX 3 +/* Internal Flash 0 base address. */ +# define IFLASH_ADDR IFLASH0_ADDR +/* Internal flash page size. */ +# define IFLASH_PAGE_SIZE IFLASH0_PAGE_SIZE +/* Internal flash lock region size. */ +# define IFLASH_LOCK_REGION_SIZE IFLASH0_LOCK_REGION_SIZE +#elif (SAM3U) +/* There is no EFC1 for SAM3U except for SAM3U4 */ +# undef EFC1 +/* Internal Flash Controller 0. */ +# define EFC EFC0 +/* The max GPNVM number. */ +# define GPNVM_NUM_MAX 2 +/* Internal Flash 0 base address. */ +# define IFLASH_ADDR IFLASH0_ADDR +/* Internal flash page size. */ +# define IFLASH_PAGE_SIZE IFLASH0_PAGE_SIZE +/* Internal flash lock region size. */ +# define IFLASH_LOCK_REGION_SIZE IFLASH0_LOCK_REGION_SIZE +#elif (SAM3S8 || SAM3SD8) +/* The max GPNVM number. */ +# define GPNVM_NUM_MAX 3 +/* Internal flash page size. */ +# define IFLASH_PAGE_SIZE IFLASH0_PAGE_SIZE +/* Internal flash lock region size. */ +# define IFLASH_LOCK_REGION_SIZE IFLASH0_LOCK_REGION_SIZE +#elif (SAM4C32 || SAM4CMP32 || SAM4CMS32) +/* The max GPNVM number SAM4C(M)32. */ +# define GPNVM_NUM_MAX 3 +#elif (SAMG) +/* The max GPNVM number SAMG. */ +# define GPNVM_NUM_MAX 8 +#elif (SAMV71 || SAMV70 || SAMS70 || SAME70) +/* The max GPNVM number SAMV/S/E. */ +# define GPNVM_NUM_MAX 9 +#else +/* The max GPNVM number. */ +# define GPNVM_NUM_MAX 2 +#endif + +#if (SAM4C || SAM4CP || SAM4CM) +#if (SAM4C32 || SAM4CMP32 || SAM4CMS32) +# define EFC EFC0 +/* Internal Flash 0 base address. */ +# define IFLASH0_ADDR IFLASH0_CNC_ADDR +# define IFLASH1_ADDR IFLASH1_CNC_ADDR +# define IFLASH_ADDR IFLASH0_ADDR +/* Internal flash page size. */ +# define IFLASH_PAGE_SIZE IFLASH0_PAGE_SIZE +/* Internal flash lock region size. */ +# define IFLASH_LOCK_REGION_SIZE IFLASH0_LOCK_REGION_SIZE +#else +#define IFLASH_ADDR IFLASH_CNC_ADDR +#endif +#endif + +/* Flash page buffer for alignment */ +static uint32_t gs_ul_page_buffer[IFLASH_PAGE_SIZE / sizeof(uint32_t)]; + +/** + * \brief Translate the given flash address to page and offset values. + * \note pus_page and pus_offset must not be null in order to store the + * corresponding values. + * + * \param pp_efc Pointer to an EFC pointer. + * \param ul_addr Address to translate. + * \param pus_page The first page accessed. + * \param pus_offset Byte offset in the first page. + */ +static void translate_address(Efc **pp_efc, uint32_t ul_addr, + uint16_t *pus_page, uint16_t *pus_offset) +{ + Efc *p_efc; + uint16_t us_page; + uint16_t us_offset; + +#if (SAM3XA || SAM3U4) + if (ul_addr >= IFLASH1_ADDR) { + p_efc = EFC1; + us_page = (ul_addr - IFLASH1_ADDR) / IFLASH1_PAGE_SIZE; + us_offset = (ul_addr - IFLASH1_ADDR) % IFLASH1_PAGE_SIZE; + } else { + p_efc = EFC0; + us_page = (ul_addr - IFLASH0_ADDR) / IFLASH0_PAGE_SIZE; + us_offset = (ul_addr - IFLASH0_ADDR) % IFLASH0_PAGE_SIZE; + } +#elif (SAM4SD16 || SAM4SD32 || SAM4C32 || SAM4CMP32 || SAM4CMS32) + uint32_t uc_gpnvm2; + uc_gpnvm2 = flash_is_gpnvm_set(2); + if (ul_addr >= IFLASH1_ADDR) { + if(uc_gpnvm2 == FLASH_RC_YES) { + p_efc = EFC0; + } else { + p_efc = EFC1; + } + us_page = (ul_addr - IFLASH1_ADDR) / IFLASH1_PAGE_SIZE; + us_offset = (ul_addr - IFLASH1_ADDR) % IFLASH1_PAGE_SIZE; + } else { + if(uc_gpnvm2 == FLASH_RC_YES) { + p_efc = EFC1; + } else { + p_efc = EFC0; + } + us_page = (ul_addr - IFLASH0_ADDR) / IFLASH0_PAGE_SIZE; + us_offset = (ul_addr - IFLASH0_ADDR) % IFLASH0_PAGE_SIZE; + } +#elif (SAM3S8 || SAM3SD8) + p_efc = EFC; + us_page = (ul_addr - IFLASH0_ADDR) / IFLASH0_PAGE_SIZE; + us_offset = (ul_addr - IFLASH0_ADDR) % IFLASH0_PAGE_SIZE; +#else + Assert(ul_addr >= IFLASH_ADDR); + Assert(ul_addr <= (IFLASH_ADDR + IFLASH_SIZE)); + + p_efc = EFC; + us_page = (ul_addr - IFLASH_ADDR) / IFLASH_PAGE_SIZE; + us_offset = (ul_addr - IFLASH_ADDR) % IFLASH_PAGE_SIZE; +#endif + + /* Store values */ + if (pp_efc) { + *pp_efc = p_efc; + } + + if (pus_page) { + *pus_page = us_page; + } + + if (pus_offset) { + *pus_offset = us_offset; + } +} + +/** + * \brief Compute the address of a flash by the given page and offset. + * + * \param p_efc Pointer to an EFC instance. + * \param us_page Page number. + * \param us_offset Byte offset inside page. + * \param pul_addr Computed address (optional). + */ +static void compute_address(Efc *p_efc, uint16_t us_page, uint16_t us_offset, + uint32_t *pul_addr) +{ + uint32_t ul_addr; + +/* Dual bank flash */ +#ifdef EFC1 + /* Compute address */ +#if (SAM4SD16 || SAM4SD32 || SAM4C32 || SAM4CMP32 || SAM4CMS32) + uint32_t uc_gpnvm2; + uc_gpnvm2 = flash_is_gpnvm_set(2); + if (p_efc == EFC0) { + if(uc_gpnvm2 == FLASH_RC_YES) { + ul_addr = IFLASH1_ADDR + us_page * IFLASH_PAGE_SIZE + us_offset; + } else { + ul_addr = IFLASH0_ADDR + us_page * IFLASH_PAGE_SIZE + us_offset; + } + } else { + if(uc_gpnvm2 == FLASH_RC_YES) { + ul_addr = IFLASH0_ADDR + us_page * IFLASH_PAGE_SIZE + us_offset; + } else { + ul_addr = IFLASH1_ADDR + us_page * IFLASH_PAGE_SIZE + us_offset; + } + } +#else + ul_addr = (p_efc == EFC0) ? + IFLASH0_ADDR + us_page * IFLASH_PAGE_SIZE + us_offset : + IFLASH1_ADDR + us_page * IFLASH_PAGE_SIZE + us_offset; +#endif +/* One bank flash */ +#else + /* avoid Cppcheck Warning */ + UNUSED(p_efc); + /* Compute address */ + ul_addr = IFLASH_ADDR + us_page * IFLASH_PAGE_SIZE + us_offset; +#endif + + /* Store result */ + if (pul_addr != NULL) { + *pul_addr = ul_addr; + } +} + +/** + * \brief Compute the lock range associated with the given address range. + * + * \param ul_start Start address of lock range. + * \param ul_end End address of lock range. + * \param pul_actual_start Actual start address of lock range. + * \param pul_actual_end Actual end address of lock range. + */ +static void compute_lock_range(uint32_t ul_start, uint32_t ul_end, + uint32_t *pul_actual_start, uint32_t *pul_actual_end) +{ + uint32_t ul_actual_start, ul_actual_end; + + ul_actual_start = ul_start - (ul_start % IFLASH_LOCK_REGION_SIZE); + ul_actual_end = ul_end - (ul_end % IFLASH_LOCK_REGION_SIZE) + + IFLASH_LOCK_REGION_SIZE - 1; + + if (pul_actual_start) { + *pul_actual_start = ul_actual_start; + } + + if (pul_actual_end) { + *pul_actual_end = ul_actual_end; + } +} + +/** + * \brief Initialize the flash service. + * + * \param ul_mode FLASH_ACCESS_MODE_128 or FLASH_ACCESS_MODE_64. + * \param ul_fws The number of wait states in cycle (no shift). + * + * \return 0 if successful; otherwise returns an error code. + */ +uint32_t flash_init(uint32_t ul_mode, uint32_t ul_fws) +{ + efc_init(EFC, ul_mode, ul_fws); + +#ifdef EFC1 + efc_init(EFC1, ul_mode, ul_fws); +#endif + + return FLASH_RC_OK; +} + +/** + * \brief Set flash wait state. + * + * \param ul_address Flash bank start address. + * \param ul_fws The number of wait states in cycle (no shift). + * + * \return 0 if successful; otherwise returns an error code. + */ +uint32_t flash_set_wait_state(uint32_t ul_address, uint32_t ul_fws) +{ + Efc *p_efc; + + translate_address(&p_efc, ul_address, NULL, NULL); + efc_set_wait_state(p_efc, ul_fws); + + return FLASH_RC_OK; +} + +/** + * \brief Set flash wait state. + * + * \param ul_address Flash bank start address. + * \param ul_fws The number of wait states in cycle (no shift). + * + * \return 0 if successful; otherwise returns an error code. + */ +uint32_t flash_set_wait_state_adaptively(uint32_t ul_address) +{ + Efc *p_efc; + uint32_t clock = sysclk_get_cpu_hz(); + + translate_address(&p_efc, ul_address, NULL, NULL); + + /* Set FWS for embedded Flash access according to operating frequency */ + if (clock < CHIP_FREQ_FWS_0) { + efc_set_wait_state(p_efc, 0); + } else if (clock < CHIP_FREQ_FWS_1) { + efc_set_wait_state(p_efc, 1); + } else if (clock < CHIP_FREQ_FWS_2) { + efc_set_wait_state(p_efc, 2); +#if (SAM3XA || SAM3U) + } else if (clock < CHIP_FREQ_FWS_3) { + efc_set_wait_state(p_efc, 3); + } else { + efc_set_wait_state(p_efc, 4); + } +#elif (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CP || SAM4CM || \ + SAMV71 || SAMV70 || SAMS70 || SAME70) + } else if (clock < CHIP_FREQ_FWS_3) { + efc_set_wait_state(p_efc, 3); + } else if (clock < CHIP_FREQ_FWS_4) { + efc_set_wait_state(p_efc, 4); + } else { + efc_set_wait_state(p_efc, 5); + } +#else + } else { + efc_set_wait_state(p_efc, 3); + } +#endif + + return FLASH_RC_OK; +} + +/** + * \brief Get flash wait state. + * + * \param ul_address Flash bank start address. + * + * \return The number of wait states in cycle (no shift). + */ +uint32_t flash_get_wait_state(uint32_t ul_address) +{ + Efc *p_efc; + + translate_address(&p_efc, ul_address, NULL, NULL); + return efc_get_wait_state(p_efc); +} + +/** + * \brief Get flash descriptor. + * + * \param ul_address Flash bank start address. + * \param pul_flash_descriptor Pointer to a data buffer to store flash descriptor. + * \param ul_size Data buffer size in DWORD. + * + * \return The actual descriptor length. + */ +uint32_t flash_get_descriptor(uint32_t ul_address, + uint32_t *pul_flash_descriptor, uint32_t ul_size) +{ + Efc *p_efc; + uint32_t ul_tmp; + uint32_t ul_cnt; + + translate_address(&p_efc, ul_address, NULL, NULL); + + /* Command fails */ + if (FLASH_RC_OK != efc_perform_command(p_efc, EFC_FCMD_GETD, 0)) { + return 0; + } else { + /* Read until no result */ + for (ul_cnt = 0;; ul_cnt++) { + ul_tmp = efc_get_result(p_efc); + if ((ul_size > ul_cnt) && (ul_tmp != 0)) { + *pul_flash_descriptor++ = ul_tmp; + } else { + break; + } + } + } + + return ul_cnt; +} + +/** + * \brief Get flash total page count for the specified bank. + * + * \note The flash descriptor must be fetched from flash_get_descriptor + * function first. + * + * \param pul_flash_descriptor Pointer to a flash descriptor. + * + * \return The flash total page count. + */ +uint32_t flash_get_page_count(const uint32_t *pul_flash_descriptor) +{ + return (pul_flash_descriptor[1] / pul_flash_descriptor[2]); +} + +/** + * \brief Get flash page count per region (plane) for the specified bank. + * + * \note The flash descriptor must be fetched from flash_get_descriptor + * function first. + * + * \param pul_flash_descriptor Pointer to a flash descriptor. + * + * \return The flash page count per region (plane). + */ +uint32_t flash_get_page_count_per_region(const uint32_t *pul_flash_descriptor) +{ + return (pul_flash_descriptor[4] / pul_flash_descriptor[2]); +} + +/** + * \brief Get flash region (plane) count for the specified bank. + * + * \note The flash descriptor must be fetched from flash_get_descriptor + * function first. + * + * \param pul_flash_descriptor Pointer to a flash descriptor. + * + * \return The flash region (plane) count. + */ +uint32_t flash_get_region_count(const uint32_t *pul_flash_descriptor) +{ + return (pul_flash_descriptor[3]); +} + +/** + * \brief Erase the entire flash. + * + * \note Only the flash bank including ul_address will be erased. If there are + * two flash banks, we need to call this function twice with each bank start + * address. + * + * \param ul_address Flash bank start address. + * + * \return 0 if successful; otherwise returns an error code. + */ +uint32_t flash_erase_all(uint32_t ul_address) +{ + Efc *p_efc; + + translate_address(&p_efc, ul_address, NULL, NULL); + + if (EFC_RC_OK != efc_perform_command(p_efc, EFC_FCMD_EA, 0)) { + return FLASH_RC_ERROR; + } + + return FLASH_RC_OK; +} + +#if (SAM3S8 || SAM3SD8) +/** + * \brief Erase the flash by plane. + * + * \param ul_address Flash plane start address. + * + * \note Erase plane command needs a page number parameter which belongs to + * the plane to be erased. + * + * \return 0 if successful; otherwise returns an error code. + */ +uint32_t flash_erase_plane(uint32_t ul_address) +{ + Efc *p_efc; + uint16_t us_page; + + translate_address(&p_efc, ul_address, &us_page, NULL); + + if (EFC_RC_OK != efc_perform_command(p_efc, EFC_FCMD_EPL, us_page)) { + return FLASH_RC_ERROR; + } + + return FLASH_RC_OK; +} +#endif + +#if (SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || \ + SAMV71 || SAMV70 || SAMS70 || SAME70) +/** + * \brief Erase the specified pages of flash. + * + * \param ul_address Flash bank start address. + * + * \return 0 if successful; otherwise returns an error code. + */ +uint32_t flash_erase_page(uint32_t ul_address, uint8_t uc_page_num) +{ + Efc *p_efc; + uint16_t us_page; + + if (uc_page_num >= IFLASH_ERASE_PAGES_INVALID) { + return FLASH_RC_INVALID; + } + + if (ul_address & (IFLASH_PAGE_SIZE - 1)) { + return FLASH_RC_INVALID; + } + + translate_address(&p_efc, ul_address, &us_page, NULL); + + if (EFC_RC_OK != efc_perform_command(p_efc, EFC_FCMD_EPA, + (us_page | uc_page_num))) { + return FLASH_RC_ERROR; + } + + return FLASH_RC_OK; +} + +/** + * \brief Erase the flash sector. + * + * \note Erase sector command needs a page number parameter which belongs to + * the sector to be erased. + * + * \param ul_address Flash sector start address. + * + * \return 0 if successful; otherwise returns an error code. + */ +uint32_t flash_erase_sector(uint32_t ul_address) +{ + Efc *p_efc; + uint16_t us_page; + + translate_address(&p_efc, ul_address, &us_page, NULL); + + if (EFC_RC_OK != efc_perform_command(p_efc, EFC_FCMD_ES, us_page)) { + return FLASH_RC_ERROR; + } + + return FLASH_RC_OK; +} +#endif + +/** + * \brief Write a data buffer on flash. + * + * \note This function works in polling mode, and thus only returns when the + * data has been effectively written. + * \note For dual bank flash, this function doesn't support cross write from + * bank 0 to bank 1. In this case, flash_write must be called twice (ie for + * each bank). + * + * \param ul_address Write address. + * \param p_buffer Data buffer. + * \param ul_size Size of data buffer in bytes. + * \param ul_erase_flag Flag to set if erase first. + * + * \return 0 if successful, otherwise returns an error code. + */ +uint32_t flash_write(uint32_t ul_address, const void *p_buffer, + uint32_t ul_size, uint32_t ul_erase_flag) +{ + Efc *p_efc; + uint32_t ul_fws_temp; + uint16_t us_page; + uint16_t us_offset; + uint32_t writeSize; + uint32_t ul_page_addr; + uint16_t us_padding; + uint32_t ul_error; + uint32_t ul_idx; + uint32_t *p_aligned_dest; + uint8_t *puc_page_buffer = (uint8_t *) gs_ul_page_buffer; + + translate_address(&p_efc, ul_address, &us_page, &us_offset); + +#if SAM3S || SAM3N || SAM3XA || SAM3U + /* According to the errata, set the wait state value to 6. */ + ul_fws_temp = efc_get_wait_state(p_efc); + efc_set_wait_state(p_efc, 6); +#else + UNUSED(ul_fws_temp); +#endif + + /* Write all pages */ + while (ul_size > 0) { + /* Copy data in temporary buffer to avoid alignment problems. */ + writeSize = Min((uint32_t) IFLASH_PAGE_SIZE - us_offset, + ul_size); + compute_address(p_efc, us_page, 0, &ul_page_addr); + us_padding = IFLASH_PAGE_SIZE - us_offset - writeSize; + + /* Pre-buffer data */ + memcpy(puc_page_buffer, (void *)ul_page_addr, us_offset); + + /* Buffer data */ + memcpy(puc_page_buffer + us_offset, p_buffer, writeSize); + + /* Post-buffer data */ + memcpy(puc_page_buffer + us_offset + writeSize, + (void *)(ul_page_addr + us_offset + writeSize), + us_padding); + + /* Write page. + * Writing 8-bit and 16-bit data is not allowed and may lead to + * unpredictable data corruption. + */ + uint32_t tmp; + p_aligned_dest = (uint32_t *) ul_page_addr; + for (ul_idx = 0; ul_idx < (IFLASH_PAGE_SIZE / sizeof(uint32_t)); ++ul_idx) + { + tmp = gs_ul_page_buffer[ul_idx]; + *p_aligned_dest = tmp; + p_aligned_dest++; + } + + if (ul_erase_flag) { + ul_error = efc_perform_command(p_efc, EFC_FCMD_EWP, + us_page); + } else { + ul_error = efc_perform_command(p_efc, EFC_FCMD_WP, + us_page); + } + + if (ul_error) { + return ul_error; + } + + /* Progression */ + p_buffer = (void *)((uint32_t) p_buffer + writeSize); + ul_size -= writeSize; + us_page++; + us_offset = 0; + } + +#if SAM3S || SAM3N || SAM3XA || SAM3U + /* According to the errata, restore the wait state value. */ + efc_set_wait_state(p_efc, ul_fws_temp); +#endif + + return FLASH_RC_OK; +} + + +/** + * \brief Lock all the regions in the given address range. The actual lock + * range is reported through two output parameters. + * + * \param ul_start Start address of lock range. + * \param ul_end End address of lock range. + * \param pul_actual_start Start address of the actual lock range (optional). + * \param pul_actual_end End address of the actual lock range (optional). + * + * \return 0 if successful, otherwise returns an error code. + */ +uint32_t flash_lock(uint32_t ul_start, uint32_t ul_end, + uint32_t *pul_actual_start, uint32_t *pul_actual_end) +{ + Efc *p_efc; + uint32_t ul_actual_start, ul_actual_end; + uint16_t us_start_page, us_end_page; + uint32_t ul_error; + uint16_t us_num_pages_in_region = + IFLASH_LOCK_REGION_SIZE / IFLASH_PAGE_SIZE; + + /* Compute actual lock range and store it */ + compute_lock_range(ul_start, ul_end, &ul_actual_start, &ul_actual_end); + + if (pul_actual_start != NULL) { + *pul_actual_start = ul_actual_start; + } + + if (pul_actual_end != NULL) { + *pul_actual_end = ul_actual_end; + } + + /* Compute page numbers */ + translate_address(&p_efc, ul_actual_start, &us_start_page, 0); + translate_address(0, ul_actual_end, &us_end_page, 0); + + /* Lock all pages */ + while (us_start_page < us_end_page) { + ul_error = efc_perform_command(p_efc, EFC_FCMD_SLB, us_start_page); + + if (ul_error) { + return ul_error; + } + us_start_page += us_num_pages_in_region; + } + + return FLASH_RC_OK; +} + +/** + * \brief Unlock all the regions in the given address range. The actual unlock + * range is reported through two output parameters. + * + * \param ul_start Start address of unlock range. + * \param ul_end End address of unlock range. + * \param pul_actual_start Start address of the actual unlock range (optional). + * \param pul_actual_end End address of the actual unlock range (optional). + * + * \return 0 if successful, otherwise returns an error code. + */ +uint32_t flash_unlock(uint32_t ul_start, uint32_t ul_end, + uint32_t *pul_actual_start, uint32_t *pul_actual_end) +{ + Efc *p_efc; + uint32_t ul_actual_start, ul_actual_end; + uint16_t us_start_page, us_end_page; + uint32_t ul_error; + uint16_t us_num_pages_in_region = + IFLASH_LOCK_REGION_SIZE / IFLASH_PAGE_SIZE; + + /* Compute actual unlock range and store it */ + compute_lock_range(ul_start, ul_end, &ul_actual_start, &ul_actual_end); + if (pul_actual_start != NULL) { + *pul_actual_start = ul_actual_start; + } + if (pul_actual_end != NULL) { + *pul_actual_end = ul_actual_end; + } + + /* Compute page numbers */ + translate_address(&p_efc, ul_actual_start, &us_start_page, 0); + translate_address(0, ul_actual_end, &us_end_page, 0); + + /* Unlock all pages */ + while (us_start_page < us_end_page) { + ul_error = efc_perform_command(p_efc, EFC_FCMD_CLB, + us_start_page); + if (ul_error) { + return ul_error; + } + us_start_page += us_num_pages_in_region; + } + + return FLASH_RC_OK; +} + +/** + * \brief Get the number of locked regions inside the given address range. + * + * \param ul_start Start address of range + * \param ul_end End address of range. + * + * \return The number of locked regions inside the given address range. + */ +uint32_t flash_is_locked(uint32_t ul_start, uint32_t ul_end) +{ + Efc *p_efc; + uint16_t us_start_page, us_end_page; + uint8_t uc_start_region, uc_end_region; + uint16_t us_num_pages_in_region; + uint32_t ul_status; + uint32_t ul_error; + uint32_t ul_num_locked_regions = 0; + uint32_t ul_count = 0; + uint32_t ul_bit = 0; + + Assert(ul_end >= ul_start); + +#ifdef EFC1 + Assert(((ul_start >= IFLASH0_ADDR) + && (ul_end <= IFLASH0_ADDR + IFLASH0_SIZE)) + || ((ul_start >= IFLASH1_ADDR) + && (ul_end <= IFLASH1_ADDR + IFLASH1_SIZE))); +#else + Assert((ul_start >= IFLASH_ADDR) + && (ul_end <= IFLASH_ADDR + IFLASH_SIZE)); +#endif + + /* Compute page numbers */ + translate_address(&p_efc, ul_start, &us_start_page, 0); + translate_address(0, ul_end, &us_end_page, 0); + + /* Compute region numbers */ + us_num_pages_in_region = IFLASH_LOCK_REGION_SIZE / IFLASH_PAGE_SIZE; + uc_start_region = us_start_page / us_num_pages_in_region; + uc_end_region = us_end_page / us_num_pages_in_region; + + /* Retrieve lock status */ + ul_error = efc_perform_command(p_efc, EFC_FCMD_GLB, 0); + if (ul_error) { + return ul_error; + } + UNUSED(ul_error); + + /* Skip unrequested regions (if necessary) */ + ul_status = efc_get_result(p_efc); + while (!(ul_count <= uc_start_region && + uc_start_region < (ul_count + 32))) { + ul_status = efc_get_result(p_efc); + ul_count += 32; + } + + /* Check status of each involved region */ + ul_bit = uc_start_region - ul_count; + + /* Number of region to check (must be > 0) */ + ul_count = uc_end_region - uc_start_region + 1; + + while (ul_count > 0) { + if (ul_status & (1 << (ul_bit))) { + ul_num_locked_regions++; + } + + ul_count -= 1; + ul_bit += 1; + if (ul_bit == 32) { + ul_status = efc_get_result(p_efc); + ul_bit = 0; + } + } + + return ul_num_locked_regions; +} + +/** + * \brief Set the given GPNVM bit. + * + * \param ul_gpnvm GPNVM bit index. + * + * \return 0 if successful; otherwise returns an error code. + */ +uint32_t flash_set_gpnvm(uint32_t ul_gpnvm) +{ + if (ul_gpnvm >= GPNVM_NUM_MAX) { + return FLASH_RC_INVALID; + } + + if (FLASH_RC_YES == flash_is_gpnvm_set(ul_gpnvm)) { + return FLASH_RC_OK; + } + + if (EFC_RC_OK == efc_perform_command(EFC, EFC_FCMD_SGPB, ul_gpnvm)) { + return FLASH_RC_OK; + } + + return FLASH_RC_ERROR; +} + +/** + * \brief Clear the given GPNVM bit. + * + * \param ul_gpnvm GPNVM bit index. + * + * \return 0 if successful; otherwise returns an error code. + */ +uint32_t flash_clear_gpnvm(uint32_t ul_gpnvm) +{ + if (ul_gpnvm >= GPNVM_NUM_MAX) { + return FLASH_RC_INVALID; + } + + if (FLASH_RC_NO == flash_is_gpnvm_set(ul_gpnvm)) { + return FLASH_RC_OK; + } + + if (EFC_RC_OK == efc_perform_command(EFC, EFC_FCMD_CGPB, ul_gpnvm)) { + return FLASH_RC_OK; + } + + return FLASH_RC_ERROR; +} + +/** + * \brief Check if the given GPNVM bit is set or not. + * + * \param ul_gpnvm GPNVM bit index. + * + * \retval 1 If the given GPNVM bit is currently set. + * \retval 0 If the given GPNVM bit is currently cleared. + * otherwise returns an error code. + */ +uint32_t flash_is_gpnvm_set(uint32_t ul_gpnvm) +{ + uint32_t ul_gpnvm_bits; + + if (ul_gpnvm >= GPNVM_NUM_MAX) { + return FLASH_RC_INVALID; + } + + if (EFC_RC_OK != efc_perform_command(EFC, EFC_FCMD_GGPB, 0)) { + return FLASH_RC_ERROR; + } + + ul_gpnvm_bits = efc_get_result(EFC); + if (ul_gpnvm_bits & (1 << ul_gpnvm)) { + return FLASH_RC_YES; + } + + return FLASH_RC_NO; +} + +/** + * \brief Set security bit. + * + * \return 0 if successful; otherwise returns an error code. + */ +uint32_t flash_enable_security_bit(void) +{ + return flash_set_gpnvm(0); +} + +/** + * \brief Check if the security bit is set or not. + * + * \retval 1 If the security bit is currently set. + * \retval 0 If the security bit is currently cleared. + * otherwise returns an error code. + */ +uint32_t flash_is_security_bit_enabled(void) +{ + return flash_is_gpnvm_set(0); +} + +/** + * \brief Read the flash unique ID. + * + * \param pul_data Pointer to a data buffer to store 128-bit unique ID. + * \param ul_size Data buffer size in DWORD. + * + * \return 0 if successful; otherwise returns an error code. + */ +uint32_t flash_read_unique_id(uint32_t *pul_data, uint32_t ul_size) +{ + uint32_t uid_buf[4]; + uint32_t ul_idx; + + if (FLASH_RC_OK != efc_perform_read_sequence(EFC, EFC_FCMD_STUI, + EFC_FCMD_SPUI, uid_buf, 4)) { + return FLASH_RC_ERROR; + } + + if (ul_size > 4) { + /* Only 4 dword to store unique ID */ + ul_size = 4; + } + + for (ul_idx = 0; ul_idx < ul_size; ul_idx++) { + pul_data[ul_idx] = uid_buf[ul_idx]; + } + + return FLASH_RC_OK; +} + +#if (SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || \ + SAMV71 || SAMV70 || SAMS70 || SAME70) +/** + * \brief Read the flash user signature. + * + * \param p_data Pointer to a data buffer to store 512 bytes of user signature. + * \param ul_size Data buffer size in 32 bit words. + * + * \return 0 if successful; otherwise returns an error code. + */ +uint32_t flash_read_user_signature(uint32_t *p_data, uint32_t ul_size) +{ + if (ul_size > (FLASH_USER_SIG_SIZE / sizeof(uint32_t))) { + /* Only 512 byte to store user signature */ + ul_size = FLASH_USER_SIG_SIZE / sizeof(uint32_t); + } + + /* Send the read user signature commands */ + if (FLASH_RC_OK != efc_perform_read_sequence(EFC, EFC_FCMD_STUS, + EFC_FCMD_SPUS, p_data, ul_size)) { + return FLASH_RC_ERROR; + } + + return FLASH_RC_OK; +} + +/** + * \brief Write the flash user signature. + * + * \param p_data Pointer to a data buffer to store info for the user signature. + * \param ul_size Data buffer size in 32 bit words. + * + * \return 0 if successful; otherwise returns an error code. + */ +uint32_t flash_write_user_signature(const void *p_buffer, uint32_t ul_size) +{ + uint32_t ul_idx; + uint32_t *p_dest; + + /* The user signature should be no longer than 512 bytes */ + if (ul_size > (IFLASH_PAGE_SIZE / sizeof(uint32_t))) { + return FLASH_RC_INVALID; + } + + /* Copy Buffer data */ + memcpy((uint8_t *) gs_ul_page_buffer, p_buffer, + ul_size * sizeof(uint32_t)); + + /* Write page buffer. + * Writing 8-bit and 16-bit data is not allowed and may lead to + * unpredictable data corruption. + */ + p_dest = (uint32_t *)IFLASH_ADDR; + for (ul_idx = 0; ul_idx < (IFLASH_PAGE_SIZE / sizeof(uint32_t)); + ul_idx++) { + *p_dest++ = gs_ul_page_buffer[ul_idx]; + } + + /* Send the write signature command */ + if (FLASH_RC_OK != efc_perform_command(EFC, EFC_FCMD_WUS, 0)) { + return FLASH_RC_ERROR; + } + + return FLASH_RC_OK; +} + +/** + * \brief Erase the flash user signature. + * + * \return 0 if successful; otherwise returns an error code. + */ +uint32_t flash_erase_user_signature(void) +{ + /* Perform the erase user signature command */ + return efc_perform_command(EFC, EFC_FCMD_EUS, 0); +} +#endif + +//@} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/hw-libs/drivers/SAMx70/ASF/sam/services/flash_efc/flash_efc.h b/hw-libs/drivers/SAMx70/ASF/sam/services/flash_efc/flash_efc.h new file mode 100644 index 000000000..c27652fd8 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/services/flash_efc/flash_efc.h @@ -0,0 +1,147 @@ +/** + * \file + * + * \brief Embedded Flash service for SAM. + * + * Copyright (c) 2011-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef FLASH_H_INCLUDED +#define FLASH_H_INCLUDED + +#include "compiler.h" +#include "efc.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus + extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/*! \name Flash driver return codes */ +//! @{ +typedef enum flash_rc { + FLASH_RC_OK = 0, //!< Operation OK + FLASH_RC_YES = 1, //!< Yes + FLASH_RC_NO = 0, //!< No + FLASH_RC_ERROR = 0x10, //!< General error + FLASH_RC_INVALID, //!< Invalid argument input + FLASH_RC_NOT_SUPPORT = 0xFFFFFFFF //!< Operation is not supported +} flash_rc_t; +//! @} + +/*! \name Flash erase page num in FARG[1:0] + \note The erase page commands should be cautiouly used as EPA4/EPA32 will not + take effect according to errata and EPA8/EPA16 must module 8/16 page addresses.*/ +//! @{ +typedef enum flash_farg_page_num { + /* 4 of pages to be erased with EPA command*/ + IFLASH_ERASE_PAGES_4=0, + /* 8 of pages to be erased with EPA command*/ + IFLASH_ERASE_PAGES_8, + /* 16 of pages to be erased with EPA command*/ + IFLASH_ERASE_PAGES_16, + /* 32 of pages to be erased with EPA command*/ + IFLASH_ERASE_PAGES_32, + /* Parameter is not support */ + IFLASH_ERASE_PAGES_INVALID, +}flash_farg_page_num_t; +//! @} + +/*! \name Flash access mode */ +//! @{ +#define FLASH_ACCESS_MODE_128 EFC_ACCESS_MODE_128 +#define FLASH_ACCESS_MODE_64 EFC_ACCESS_MODE_64 +//! @} + +uint32_t flash_init(uint32_t ul_mode, uint32_t ul_fws); +uint32_t flash_set_wait_state(uint32_t ul_address, uint32_t ul_fws); +uint32_t flash_set_wait_state_adaptively(uint32_t ul_address); +uint32_t flash_get_wait_state(uint32_t ul_address); +uint32_t flash_get_descriptor(uint32_t ul_address, + uint32_t *pul_flash_descriptor, uint32_t ul_size); +uint32_t flash_get_page_count(const uint32_t *pul_flash_descriptor); +uint32_t flash_get_page_count_per_region(const uint32_t *pul_flash_descriptor); +uint32_t flash_get_region_count(const uint32_t *pul_flash_descriptor); +uint32_t flash_erase_all(uint32_t ul_address); + +#if (SAM3S8 || SAM3SD8) +uint32_t flash_erase_plane(uint32_t ul_address); +#endif + +#if (SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || \ + SAMV71 || SAMV70 || SAMS70 || SAME70) +uint32_t flash_erase_page(uint32_t ul_address, uint8_t uc_page_num); +uint32_t flash_erase_sector(uint32_t ul_address); +#endif + +uint32_t flash_write(uint32_t ul_address, const void *p_buffer, + uint32_t ul_size, uint32_t ul_erase_flag); +uint32_t flash_lock(uint32_t ul_start, uint32_t ul_end, + uint32_t *pul_actual_start, uint32_t *pul_actual_end); +uint32_t flash_unlock(uint32_t ul_start, uint32_t ul_end, + uint32_t *pul_actual_start, uint32_t *pul_actual_end); +uint32_t flash_is_locked(uint32_t ul_start, uint32_t ul_end); +uint32_t flash_set_gpnvm(uint32_t ul_gpnvm); +uint32_t flash_clear_gpnvm(uint32_t ul_gpnvm); +uint32_t flash_is_gpnvm_set(uint32_t ul_gpnvm); +uint32_t flash_enable_security_bit(void); +uint32_t flash_is_security_bit_enabled(void); +uint32_t flash_read_unique_id(uint32_t *pul_data, uint32_t ul_size); + +#if (SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || \ + SAMV71 || SAMV70 || SAMS70 || SAME70) +uint32_t flash_read_user_signature(uint32_t *p_data, uint32_t ul_size); +uint32_t flash_write_user_signature(const void *p_buffer, uint32_t ul_size); +uint32_t flash_erase_user_signature(void); +#endif + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +#endif /* FLASH_H_INCLUDED */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/acc.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/acc.h new file mode 100644 index 000000000..741aacfe3 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/acc.h @@ -0,0 +1,141 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_ACC_COMPONENT_ +#define _SAME70_ACC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Analog Comparator Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_ACC Analog Comparator Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Acc hardware registers */ +typedef struct { + __O uint32_t ACC_CR; /**< \brief (Acc Offset: 0x00) Control Register */ + __IO uint32_t ACC_MR; /**< \brief (Acc Offset: 0x04) Mode Register */ + __I uint32_t Reserved1[7]; + __O uint32_t ACC_IER; /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */ + __O uint32_t ACC_IDR; /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */ + __I uint32_t ACC_IMR; /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t ACC_ISR; /**< \brief (Acc Offset: 0x30) Interrupt Status Register */ + __I uint32_t Reserved2[24]; + __IO uint32_t ACC_ACR; /**< \brief (Acc Offset: 0x94) Analog Control Register */ + __I uint32_t Reserved3[19]; + __IO uint32_t ACC_WPMR; /**< \brief (Acc Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t ACC_WPSR; /**< \brief (Acc Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved4[4]; + __I uint32_t ACC_VER; /**< \brief (Acc Offset: 0xFC) Version Register */ +} Acc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */ +#define ACC_CR_SWRST (0x1u << 0) /**< \brief (ACC_CR) Software Reset */ +/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */ +#define ACC_MR_SELMINUS_Pos 0 +#define ACC_MR_SELMINUS_Msk (0x7u << ACC_MR_SELMINUS_Pos) /**< \brief (ACC_MR) Selection for Minus Comparator Input */ +#define ACC_MR_SELMINUS(value) ((ACC_MR_SELMINUS_Msk & ((value) << ACC_MR_SELMINUS_Pos))) +#define ACC_MR_SELMINUS_TS (0x0u << 0) /**< \brief (ACC_MR) Select TS */ +#define ACC_MR_SELMINUS_ADVREFP (0x1u << 0) /**< \brief (ACC_MR) Select ADVREFP */ +#define ACC_MR_SELMINUS_VREFP (0x1u << 0) /**< \brief (ACC_MR) Select VREFP */ +#define ACC_MR_SELMINUS_DAC0 (0x2u << 0) /**< \brief (ACC_MR) Select DAC0 */ +#define ACC_MR_SELMINUS_DAC1 (0x3u << 0) /**< \brief (ACC_MR) Select DAC1 */ +#define ACC_MR_SELMINUS_AFE0_AD0 (0x4u << 0) /**< \brief (ACC_MR) Select AFE0_AD0 */ +#define ACC_MR_SELMINUS_AFE0_AD1 (0x5u << 0) /**< \brief (ACC_MR) Select AFE0_AD1 */ +#define ACC_MR_SELMINUS_AFE0_AD2 (0x6u << 0) /**< \brief (ACC_MR) Select AFE0_AD2 */ +#define ACC_MR_SELMINUS_AFE0_AD3 (0x7u << 0) /**< \brief (ACC_MR) Select AFE0_AD3 */ +#define ACC_MR_SELPLUS_Pos 4 +#define ACC_MR_SELPLUS_Msk (0x7u << ACC_MR_SELPLUS_Pos) /**< \brief (ACC_MR) Selection For Plus Comparator Input */ +#define ACC_MR_SELPLUS(value) ((ACC_MR_SELPLUS_Msk & ((value) << ACC_MR_SELPLUS_Pos))) +#define ACC_MR_SELPLUS_AFE0_AD0 (0x0u << 4) /**< \brief (ACC_MR) Select AFE0_AD0 */ +#define ACC_MR_SELPLUS_AFE0_AD1 (0x1u << 4) /**< \brief (ACC_MR) Select AFE0_AD1 */ +#define ACC_MR_SELPLUS_AFE0_AD2 (0x2u << 4) /**< \brief (ACC_MR) Select AFE0_AD2 */ +#define ACC_MR_SELPLUS_AFE0_AD3 (0x3u << 4) /**< \brief (ACC_MR) Select AFE0_AD3 */ +#define ACC_MR_SELPLUS_AFE0_AD4 (0x4u << 4) /**< \brief (ACC_MR) Select AFE0_AD4 */ +#define ACC_MR_SELPLUS_AFE0_AD5 (0x5u << 4) /**< \brief (ACC_MR) Select AFE0_AD5 */ +#define ACC_MR_SELPLUS_AFE1_AD0 (0x6u << 4) /**< \brief (ACC_MR) Select AFE1_AD0 */ +#define ACC_MR_SELPLUS_AFE1_AD1 (0x7u << 4) /**< \brief (ACC_MR) Select AFE1_AD1 */ +#define ACC_MR_ACEN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator Enable */ +#define ACC_MR_ACEN_DIS (0x0u << 8) /**< \brief (ACC_MR) Analog comparator disabled. */ +#define ACC_MR_ACEN_EN (0x1u << 8) /**< \brief (ACC_MR) Analog comparator enabled. */ +#define ACC_MR_EDGETYP_Pos 9 +#define ACC_MR_EDGETYP_Msk (0x3u << ACC_MR_EDGETYP_Pos) /**< \brief (ACC_MR) Edge Type */ +#define ACC_MR_EDGETYP(value) ((ACC_MR_EDGETYP_Msk & ((value) << ACC_MR_EDGETYP_Pos))) +#define ACC_MR_EDGETYP_RISING (0x0u << 9) /**< \brief (ACC_MR) Only rising edge of comparator output */ +#define ACC_MR_EDGETYP_FALLING (0x1u << 9) /**< \brief (ACC_MR) Falling edge of comparator output */ +#define ACC_MR_EDGETYP_ANY (0x2u << 9) /**< \brief (ACC_MR) Any edge of comparator output */ +#define ACC_MR_INV (0x1u << 12) /**< \brief (ACC_MR) Invert Comparator Output */ +#define ACC_MR_INV_DIS (0x0u << 12) /**< \brief (ACC_MR) Analog comparator output is directly processed. */ +#define ACC_MR_INV_EN (0x1u << 12) /**< \brief (ACC_MR) Analog comparator output is inverted prior to being processed. */ +#define ACC_MR_SELFS (0x1u << 13) /**< \brief (ACC_MR) Selection Of Fault Source */ +#define ACC_MR_SELFS_CE (0x0u << 13) /**< \brief (ACC_MR) The CE flag is used to drive the FAULT output. */ +#define ACC_MR_SELFS_OUTPUT (0x1u << 13) /**< \brief (ACC_MR) The output of the analog comparator flag is used to drive the FAULT output. */ +#define ACC_MR_FE (0x1u << 14) /**< \brief (ACC_MR) Fault Enable */ +#define ACC_MR_FE_DIS (0x0u << 14) /**< \brief (ACC_MR) The FAULT output is tied to 0. */ +#define ACC_MR_FE_EN (0x1u << 14) /**< \brief (ACC_MR) The FAULT output is driven by the signal defined by SELFS. */ +/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */ +#define ACC_IER_CE (0x1u << 0) /**< \brief (ACC_IER) Comparison Edge */ +/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */ +#define ACC_IDR_CE (0x1u << 0) /**< \brief (ACC_IDR) Comparison Edge */ +/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */ +#define ACC_IMR_CE (0x1u << 0) /**< \brief (ACC_IMR) Comparison Edge */ +/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */ +#define ACC_ISR_CE (0x1u << 0) /**< \brief (ACC_ISR) Comparison Edge (cleared on read) */ +#define ACC_ISR_SCO (0x1u << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */ +#define ACC_ISR_MASK (0x1u << 31) /**< \brief (ACC_ISR) Flag Mask */ +/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */ +#define ACC_ACR_ISEL (0x1u << 0) /**< \brief (ACC_ACR) Current Selection */ +#define ACC_ACR_ISEL_LOPW (0x0u << 0) /**< \brief (ACC_ACR) Low-power option. */ +#define ACC_ACR_ISEL_HISP (0x1u << 0) /**< \brief (ACC_ACR) High-speed option. */ +#define ACC_ACR_HYST_Pos 1 +#define ACC_ACR_HYST_Msk (0x3u << ACC_ACR_HYST_Pos) /**< \brief (ACC_ACR) Hysteresis Selection */ +#define ACC_ACR_HYST(value) ((ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos))) +/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protection Mode Register -------- */ +#define ACC_WPMR_WPEN (0x1u << 0) /**< \brief (ACC_WPMR) Write Protection Enable */ +#define ACC_WPMR_WPKEY_Pos 8 +#define ACC_WPMR_WPKEY_Msk (0xffffffu << ACC_WPMR_WPKEY_Pos) /**< \brief (ACC_WPMR) Write Protection Key */ +#define ACC_WPMR_WPKEY(value) ((ACC_WPMR_WPKEY_Msk & ((value) << ACC_WPMR_WPKEY_Pos))) +#define ACC_WPMR_WPKEY_PASSWD (0x414343u << 8) /**< \brief (ACC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protection Status Register -------- */ +#define ACC_WPSR_WPVS (0x1u << 0) /**< \brief (ACC_WPSR) Write Protection Violation Status */ +/* -------- ACC_VER : (ACC Offset: 0xFC) Version Register -------- */ +#define ACC_VER_VERSION_Pos 0 +#define ACC_VER_VERSION_Msk (0xfffu << ACC_VER_VERSION_Pos) /**< \brief (ACC_VER) Version of the Hardware Module */ +#define ACC_VER_MFN_Pos 16 +#define ACC_VER_MFN_Msk (0x7u << ACC_VER_MFN_Pos) /**< \brief (ACC_VER) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_ACC_COMPONENT_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/aes.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/aes.h new file mode 100644 index 000000000..5a53659ee --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/aes.h @@ -0,0 +1,203 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_AES_COMPONENT_ +#define _SAME70_AES_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Advanced Encryption Standard */ +/* ============================================================================= */ +/** \addtogroup SAME70_AES Advanced Encryption Standard */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Aes hardware registers */ +typedef struct { + __O uint32_t AES_CR; /**< \brief (Aes Offset: 0x00) Control Register */ + __IO uint32_t AES_MR; /**< \brief (Aes Offset: 0x04) Mode Register */ + __I uint32_t Reserved1[2]; + __O uint32_t AES_IER; /**< \brief (Aes Offset: 0x10) Interrupt Enable Register */ + __O uint32_t AES_IDR; /**< \brief (Aes Offset: 0x14) Interrupt Disable Register */ + __I uint32_t AES_IMR; /**< \brief (Aes Offset: 0x18) Interrupt Mask Register */ + __I uint32_t AES_ISR; /**< \brief (Aes Offset: 0x1C) Interrupt Status Register */ + __O uint32_t AES_KEYWR[8]; /**< \brief (Aes Offset: 0x20) Key Word Register */ + __O uint32_t AES_IDATAR[4]; /**< \brief (Aes Offset: 0x40) Input Data Register */ + __I uint32_t AES_ODATAR[4]; /**< \brief (Aes Offset: 0x50) Output Data Register */ + __O uint32_t AES_IVR[4]; /**< \brief (Aes Offset: 0x60) Initialization Vector Register */ + __IO uint32_t AES_AADLENR; /**< \brief (Aes Offset: 0x70) Additional Authenticated Data Length Register */ + __IO uint32_t AES_CLENR; /**< \brief (Aes Offset: 0x74) Plaintext/Ciphertext Length Register */ + __IO uint32_t AES_GHASHR[4]; /**< \brief (Aes Offset: 0x78) GCM Intermediate Hash Word Register */ + __I uint32_t AES_TAGR[4]; /**< \brief (Aes Offset: 0x88) GCM Authentication Tag Word Register */ + __I uint32_t AES_CTRR; /**< \brief (Aes Offset: 0x98) GCM Encryption Counter Value Register */ + __IO uint32_t AES_GCMHR[4]; /**< \brief (Aes Offset: 0x9C) GCM H Word Register */ + __I uint32_t Reserved2[20]; + __I uint32_t AES_VERSION; /**< \brief (Aes Offset: 0xFC) Version Register */ +} Aes; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- AES_CR : (AES Offset: 0x00) Control Register -------- */ +#define AES_CR_START (0x1u << 0) /**< \brief (AES_CR) Start Processing */ +#define AES_CR_SWRST (0x1u << 8) /**< \brief (AES_CR) Software Reset */ +#define AES_CR_LOADSEED (0x1u << 16) /**< \brief (AES_CR) Random Number Generator Seed Loading */ +/* -------- AES_MR : (AES Offset: 0x04) Mode Register -------- */ +#define AES_MR_CIPHER (0x1u << 0) /**< \brief (AES_MR) Processing Mode */ +#define AES_MR_GTAGEN (0x1u << 1) /**< \brief (AES_MR) GCM Automatic Tag Generation Enable */ +#define AES_MR_DUALBUFF (0x1u << 3) /**< \brief (AES_MR) Dual Input Buffer */ +#define AES_MR_DUALBUFF_INACTIVE (0x0u << 3) /**< \brief (AES_MR) AES_IDATARx cannot be written during processing of previous block. */ +#define AES_MR_DUALBUFF_ACTIVE (0x1u << 3) /**< \brief (AES_MR) AES_IDATARx can be written during processing of previous block when SMOD = 0x2. It speeds up the overall runtime of large files. */ +#define AES_MR_PROCDLY_Pos 4 +#define AES_MR_PROCDLY_Msk (0xfu << AES_MR_PROCDLY_Pos) /**< \brief (AES_MR) Processing Delay */ +#define AES_MR_PROCDLY(value) ((AES_MR_PROCDLY_Msk & ((value) << AES_MR_PROCDLY_Pos))) +#define AES_MR_SMOD_Pos 8 +#define AES_MR_SMOD_Msk (0x3u << AES_MR_SMOD_Pos) /**< \brief (AES_MR) Start Mode */ +#define AES_MR_SMOD(value) ((AES_MR_SMOD_Msk & ((value) << AES_MR_SMOD_Pos))) +#define AES_MR_SMOD_MANUAL_START (0x0u << 8) /**< \brief (AES_MR) Manual Mode */ +#define AES_MR_SMOD_AUTO_START (0x1u << 8) /**< \brief (AES_MR) Auto Mode */ +#define AES_MR_SMOD_IDATAR0_START (0x2u << 8) /**< \brief (AES_MR) AES_IDATAR0 access only Auto Mode (DMA) */ +#define AES_MR_KEYSIZE_Pos 10 +#define AES_MR_KEYSIZE_Msk (0x3u << AES_MR_KEYSIZE_Pos) /**< \brief (AES_MR) Key Size */ +#define AES_MR_KEYSIZE(value) ((AES_MR_KEYSIZE_Msk & ((value) << AES_MR_KEYSIZE_Pos))) +#define AES_MR_KEYSIZE_AES128 (0x0u << 10) /**< \brief (AES_MR) AES Key Size is 128 bits */ +#define AES_MR_KEYSIZE_AES192 (0x1u << 10) /**< \brief (AES_MR) AES Key Size is 192 bits */ +#define AES_MR_KEYSIZE_AES256 (0x2u << 10) /**< \brief (AES_MR) AES Key Size is 256 bits */ +#define AES_MR_OPMOD_Pos 12 +#define AES_MR_OPMOD_Msk (0x7u << AES_MR_OPMOD_Pos) /**< \brief (AES_MR) Operation Mode */ +#define AES_MR_OPMOD(value) ((AES_MR_OPMOD_Msk & ((value) << AES_MR_OPMOD_Pos))) +#define AES_MR_OPMOD_ECB (0x0u << 12) /**< \brief (AES_MR) ECB: Electronic Code Book mode */ +#define AES_MR_OPMOD_CBC (0x1u << 12) /**< \brief (AES_MR) CBC: Cipher Block Chaining mode */ +#define AES_MR_OPMOD_OFB (0x2u << 12) /**< \brief (AES_MR) OFB: Output Feedback mode */ +#define AES_MR_OPMOD_CFB (0x3u << 12) /**< \brief (AES_MR) CFB: Cipher Feedback mode */ +#define AES_MR_OPMOD_CTR (0x4u << 12) /**< \brief (AES_MR) CTR: Counter mode (16-bit internal counter) */ +#define AES_MR_OPMOD_GCM (0x5u << 12) /**< \brief (AES_MR) GCM: Galois/Counter mode */ +#define AES_MR_LOD (0x1u << 15) /**< \brief (AES_MR) Last Output Data Mode */ +#define AES_MR_CFBS_Pos 16 +#define AES_MR_CFBS_Msk (0x7u << AES_MR_CFBS_Pos) /**< \brief (AES_MR) Cipher Feedback Data Size */ +#define AES_MR_CFBS(value) ((AES_MR_CFBS_Msk & ((value) << AES_MR_CFBS_Pos))) +#define AES_MR_CFBS_SIZE_128BIT (0x0u << 16) /**< \brief (AES_MR) 128-bit */ +#define AES_MR_CFBS_SIZE_64BIT (0x1u << 16) /**< \brief (AES_MR) 64-bit */ +#define AES_MR_CFBS_SIZE_32BIT (0x2u << 16) /**< \brief (AES_MR) 32-bit */ +#define AES_MR_CFBS_SIZE_16BIT (0x3u << 16) /**< \brief (AES_MR) 16-bit */ +#define AES_MR_CFBS_SIZE_8BIT (0x4u << 16) /**< \brief (AES_MR) 8-bit */ +#define AES_MR_CKEY_Pos 20 +#define AES_MR_CKEY_Msk (0xfu << AES_MR_CKEY_Pos) /**< \brief (AES_MR) Key */ +#define AES_MR_CKEY(value) ((AES_MR_CKEY_Msk & ((value) << AES_MR_CKEY_Pos))) +#define AES_MR_CKEY_PASSWD (0xEu << 20) /**< \brief (AES_MR) This field must be written with 0xE to allow CMTYPx bit configuration changes. Any other values will abort the write operation in CMTYPx bits.Always reads as 0. */ +#define AES_MR_CMTYP1 (0x1u << 24) /**< \brief (AES_MR) Countermeasure Type 1 */ +#define AES_MR_CMTYP1_NOPROT_EXTKEY (0x0u << 24) /**< \brief (AES_MR) Countermeasure type 1 is disabled. */ +#define AES_MR_CMTYP1_PROT_EXTKEY (0x1u << 24) /**< \brief (AES_MR) Countermeasure type 1 is enabled. */ +#define AES_MR_CMTYP2 (0x1u << 25) /**< \brief (AES_MR) Countermeasure Type 2 */ +#define AES_MR_CMTYP2_NO_PAUSE (0x0u << 25) /**< \brief (AES_MR) Countermeasure type 2 is disabled. */ +#define AES_MR_CMTYP2_PAUSE (0x1u << 25) /**< \brief (AES_MR) Countermeasure type 2 is enabled. */ +#define AES_MR_CMTYP3 (0x1u << 26) /**< \brief (AES_MR) Countermeasure Type 3 */ +#define AES_MR_CMTYP3_NO_DUMMY (0x0u << 26) /**< \brief (AES_MR) Countermeasure type 3 is disabled. */ +#define AES_MR_CMTYP3_DUMMY (0x1u << 26) /**< \brief (AES_MR) Countermeasure type 3 is enabled. */ +#define AES_MR_CMTYP4 (0x1u << 27) /**< \brief (AES_MR) Countermeasure Type 4 */ +#define AES_MR_CMTYP4_NO_RESTART (0x0u << 27) /**< \brief (AES_MR) Countermeasure type 4 is disabled. */ +#define AES_MR_CMTYP4_RESTART (0x1u << 27) /**< \brief (AES_MR) Countermeasure type 4 is enabled. */ +#define AES_MR_CMTYP5 (0x1u << 28) /**< \brief (AES_MR) Countermeasure Type 5 */ +#define AES_MR_CMTYP5_NO_ADDACCESS (0x0u << 28) /**< \brief (AES_MR) Countermeasure type 5 is disabled. */ +#define AES_MR_CMTYP5_ADDACCESS (0x1u << 28) /**< \brief (AES_MR) Countermeasure type 5 is enabled. */ +#define AES_MR_CMTYP6 (0x1u << 29) /**< \brief (AES_MR) Countermeasure Type 6 */ +#define AES_MR_CMTYP6_NO_IDLECURRENT (0x0u << 29) /**< \brief (AES_MR) Countermeasure type 6 is disabled. */ +#define AES_MR_CMTYP6_IDLECURRENT (0x1u << 29) /**< \brief (AES_MR) Countermeasure type 6 is enabled. */ +/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */ +#define AES_IER_DATRDY (0x1u << 0) /**< \brief (AES_IER) Data Ready Interrupt Enable */ +#define AES_IER_URAD (0x1u << 8) /**< \brief (AES_IER) Unspecified Register Access Detection Interrupt Enable */ +#define AES_IER_TAGRDY (0x1u << 16) /**< \brief (AES_IER) GCM Tag Ready Interrupt Enable */ +/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */ +#define AES_IDR_DATRDY (0x1u << 0) /**< \brief (AES_IDR) Data Ready Interrupt Disable */ +#define AES_IDR_URAD (0x1u << 8) /**< \brief (AES_IDR) Unspecified Register Access Detection Interrupt Disable */ +#define AES_IDR_TAGRDY (0x1u << 16) /**< \brief (AES_IDR) GCM Tag Ready Interrupt Disable */ +/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */ +#define AES_IMR_DATRDY (0x1u << 0) /**< \brief (AES_IMR) Data Ready Interrupt Mask */ +#define AES_IMR_URAD (0x1u << 8) /**< \brief (AES_IMR) Unspecified Register Access Detection Interrupt Mask */ +#define AES_IMR_TAGRDY (0x1u << 16) /**< \brief (AES_IMR) GCM Tag Ready Interrupt Mask */ +/* -------- AES_ISR : (AES Offset: 0x1C) Interrupt Status Register -------- */ +#define AES_ISR_DATRDY (0x1u << 0) /**< \brief (AES_ISR) Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) */ +#define AES_ISR_URAD (0x1u << 8) /**< \brief (AES_ISR) Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) */ +#define AES_ISR_URAT_Pos 12 +#define AES_ISR_URAT_Msk (0xfu << AES_ISR_URAT_Pos) /**< \brief (AES_ISR) Unspecified Register Access (cleared by writing SWRST in AES_CR) */ +#define AES_ISR_URAT_IDR_WR_PROCESSING (0x0u << 12) /**< \brief (AES_ISR) Input Data Register written during the data processing when SMOD = 0x2 mode. */ +#define AES_ISR_URAT_ODR_RD_PROCESSING (0x1u << 12) /**< \brief (AES_ISR) Output Data Register read during the data processing. */ +#define AES_ISR_URAT_MR_WR_PROCESSING (0x2u << 12) /**< \brief (AES_ISR) Mode Register written during the data processing. */ +#define AES_ISR_URAT_ODR_RD_SUBKGEN (0x3u << 12) /**< \brief (AES_ISR) Output Data Register read during the sub-keys generation. */ +#define AES_ISR_URAT_MR_WR_SUBKGEN (0x4u << 12) /**< \brief (AES_ISR) Mode Register written during the sub-keys generation. */ +#define AES_ISR_URAT_WOR_RD_ACCESS (0x5u << 12) /**< \brief (AES_ISR) Write-only register read access. */ +#define AES_ISR_TAGRDY (0x1u << 16) /**< \brief (AES_ISR) GCM Tag Ready */ +/* -------- AES_KEYWR[8] : (AES Offset: 0x20) Key Word Register -------- */ +#define AES_KEYWR_KEYW_Pos 0 +#define AES_KEYWR_KEYW_Msk (0xffffffffu << AES_KEYWR_KEYW_Pos) /**< \brief (AES_KEYWR[8]) Key Word */ +#define AES_KEYWR_KEYW(value) ((AES_KEYWR_KEYW_Msk & ((value) << AES_KEYWR_KEYW_Pos))) +/* -------- AES_IDATAR[4] : (AES Offset: 0x40) Input Data Register -------- */ +#define AES_IDATAR_IDATA_Pos 0 +#define AES_IDATAR_IDATA_Msk (0xffffffffu << AES_IDATAR_IDATA_Pos) /**< \brief (AES_IDATAR[4]) Input Data Word */ +#define AES_IDATAR_IDATA(value) ((AES_IDATAR_IDATA_Msk & ((value) << AES_IDATAR_IDATA_Pos))) +/* -------- AES_ODATAR[4] : (AES Offset: 0x50) Output Data Register -------- */ +#define AES_ODATAR_ODATA_Pos 0 +#define AES_ODATAR_ODATA_Msk (0xffffffffu << AES_ODATAR_ODATA_Pos) /**< \brief (AES_ODATAR[4]) Output Data */ +/* -------- AES_IVR[4] : (AES Offset: 0x60) Initialization Vector Register -------- */ +#define AES_IVR_IV_Pos 0 +#define AES_IVR_IV_Msk (0xffffffffu << AES_IVR_IV_Pos) /**< \brief (AES_IVR[4]) Initialization Vector */ +#define AES_IVR_IV(value) ((AES_IVR_IV_Msk & ((value) << AES_IVR_IV_Pos))) +/* -------- AES_AADLENR : (AES Offset: 0x70) Additional Authenticated Data Length Register -------- */ +#define AES_AADLENR_AADLEN_Pos 0 +#define AES_AADLENR_AADLEN_Msk (0xffffffffu << AES_AADLENR_AADLEN_Pos) /**< \brief (AES_AADLENR) Additional Authenticated Data Length */ +#define AES_AADLENR_AADLEN(value) ((AES_AADLENR_AADLEN_Msk & ((value) << AES_AADLENR_AADLEN_Pos))) +/* -------- AES_CLENR : (AES Offset: 0x74) Plaintext/Ciphertext Length Register -------- */ +#define AES_CLENR_CLEN_Pos 0 +#define AES_CLENR_CLEN_Msk (0xffffffffu << AES_CLENR_CLEN_Pos) /**< \brief (AES_CLENR) Plaintext/Ciphertext Length */ +#define AES_CLENR_CLEN(value) ((AES_CLENR_CLEN_Msk & ((value) << AES_CLENR_CLEN_Pos))) +/* -------- AES_GHASHR[4] : (AES Offset: 0x78) GCM Intermediate Hash Word Register -------- */ +#define AES_GHASHR_GHASH_Pos 0 +#define AES_GHASHR_GHASH_Msk (0xffffffffu << AES_GHASHR_GHASH_Pos) /**< \brief (AES_GHASHR[4]) Intermediate GCM Hash Word x */ +#define AES_GHASHR_GHASH(value) ((AES_GHASHR_GHASH_Msk & ((value) << AES_GHASHR_GHASH_Pos))) +/* -------- AES_TAGR[4] : (AES Offset: 0x88) GCM Authentication Tag Word Register -------- */ +#define AES_TAGR_TAG_Pos 0 +#define AES_TAGR_TAG_Msk (0xffffffffu << AES_TAGR_TAG_Pos) /**< \brief (AES_TAGR[4]) GCM Authentication Tag x */ +/* -------- AES_CTRR : (AES Offset: 0x98) GCM Encryption Counter Value Register -------- */ +#define AES_CTRR_CTR_Pos 0 +#define AES_CTRR_CTR_Msk (0xffffffffu << AES_CTRR_CTR_Pos) /**< \brief (AES_CTRR) GCM Encryption Counter */ +/* -------- AES_GCMHR[4] : (AES Offset: 0x9C) GCM H Word Register -------- */ +#define AES_GCMHR_H_Pos 0 +#define AES_GCMHR_H_Msk (0xffffffffu << AES_GCMHR_H_Pos) /**< \brief (AES_GCMHR[4]) GCM H Word x */ +#define AES_GCMHR_H(value) ((AES_GCMHR_H_Msk & ((value) << AES_GCMHR_H_Pos))) +/* -------- AES_VERSION : (AES Offset: 0xFC) Version Register -------- */ +#define AES_VERSION_VERSION_Pos 0 +#define AES_VERSION_VERSION_Msk (0xfffu << AES_VERSION_VERSION_Pos) /**< \brief (AES_VERSION) Version of the Hardware Module */ +#define AES_VERSION_MFN_Pos 16 +#define AES_VERSION_MFN_Msk (0x7u << AES_VERSION_MFN_Pos) /**< \brief (AES_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_AES_COMPONENT_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/afec.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/afec.h new file mode 100644 index 000000000..4159447df --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/afec.h @@ -0,0 +1,495 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_AFEC_COMPONENT_ +#define _SAME70_AFEC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Analog Front-End Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_AFEC Analog Front-End Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Afec hardware registers */ +typedef struct { + __O uint32_t AFEC_CR; /**< \brief (Afec Offset: 0x00) AFEC Control Register */ + __IO uint32_t AFEC_MR; /**< \brief (Afec Offset: 0x04) AFEC Mode Register */ + __IO uint32_t AFEC_EMR; /**< \brief (Afec Offset: 0x08) AFEC Extended Mode Register */ + __IO uint32_t AFEC_SEQ1R; /**< \brief (Afec Offset: 0x0C) AFEC Channel Sequence 1 Register */ + __IO uint32_t AFEC_SEQ2R; /**< \brief (Afec Offset: 0x10) AFEC Channel Sequence 2 Register */ + __O uint32_t AFEC_CHER; /**< \brief (Afec Offset: 0x14) AFEC Channel Enable Register */ + __O uint32_t AFEC_CHDR; /**< \brief (Afec Offset: 0x18) AFEC Channel Disable Register */ + __I uint32_t AFEC_CHSR; /**< \brief (Afec Offset: 0x1C) AFEC Channel Status Register */ + __I uint32_t AFEC_LCDR; /**< \brief (Afec Offset: 0x20) AFEC Last Converted Data Register */ + __O uint32_t AFEC_IER; /**< \brief (Afec Offset: 0x24) AFEC Interrupt Enable Register */ + __O uint32_t AFEC_IDR; /**< \brief (Afec Offset: 0x28) AFEC Interrupt Disable Register */ + __I uint32_t AFEC_IMR; /**< \brief (Afec Offset: 0x2C) AFEC Interrupt Mask Register */ + __I uint32_t AFEC_ISR; /**< \brief (Afec Offset: 0x30) AFEC Interrupt Status Register */ + __I uint32_t Reserved1[6]; + __I uint32_t AFEC_OVER; /**< \brief (Afec Offset: 0x4C) AFEC Overrun Status Register */ + __IO uint32_t AFEC_CWR; /**< \brief (Afec Offset: 0x50) AFEC Compare Window Register */ + __IO uint32_t AFEC_CGR; /**< \brief (Afec Offset: 0x54) AFEC Channel Gain Register */ + __I uint32_t Reserved2[2]; + __IO uint32_t AFEC_DIFFR; /**< \brief (Afec Offset: 0x60) AFEC Channel Differential Register */ + __IO uint32_t AFEC_CSELR; /**< \brief (Afec Offset: 0x64) AFEC Channel Selection Register */ + __I uint32_t AFEC_CDR; /**< \brief (Afec Offset: 0x68) AFEC Channel Data Register */ + __IO uint32_t AFEC_COCR; /**< \brief (Afec Offset: 0x6C) AFEC Channel Offset Compensation Register */ + __IO uint32_t AFEC_TEMPMR; /**< \brief (Afec Offset: 0x70) AFEC Temperature Sensor Mode Register */ + __IO uint32_t AFEC_TEMPCWR; /**< \brief (Afec Offset: 0x74) AFEC Temperature Compare Window Register */ + __I uint32_t Reserved3[7]; + __IO uint32_t AFEC_ACR; /**< \brief (Afec Offset: 0x94) AFEC Analog Control Register */ + __I uint32_t Reserved4[2]; + __IO uint32_t AFEC_SHMR; /**< \brief (Afec Offset: 0xA0) AFEC Sample & Hold Mode Register */ + __I uint32_t Reserved5[11]; + __IO uint32_t AFEC_COSR; /**< \brief (Afec Offset: 0xD0) AFEC Correction Select Register */ + __IO uint32_t AFEC_CVR; /**< \brief (Afec Offset: 0xD4) AFEC Correction Values Register */ + __IO uint32_t AFEC_CECR; /**< \brief (Afec Offset: 0xD8) AFEC Channel Error Correction Register */ + __I uint32_t Reserved6[2]; + __IO uint32_t AFEC_WPMR; /**< \brief (Afec Offset: 0xE4) AFEC Write Protection Mode Register */ + __I uint32_t AFEC_WPSR; /**< \brief (Afec Offset: 0xE8) AFEC Write Protection Status Register */ + __I uint32_t Reserved7[4]; + __I uint32_t AFEC_VERSION; /**< \brief (Afec Offset: 0xFC) AFEC Version Register */ +} Afec; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- AFEC_CR : (AFEC Offset: 0x00) AFEC Control Register -------- */ +#define AFEC_CR_SWRST (0x1u << 0) /**< \brief (AFEC_CR) Software Reset */ +#define AFEC_CR_START (0x1u << 1) /**< \brief (AFEC_CR) Start Conversion */ +/* -------- AFEC_MR : (AFEC Offset: 0x04) AFEC Mode Register -------- */ +#define AFEC_MR_TRGEN (0x1u << 0) /**< \brief (AFEC_MR) Trigger Enable */ +#define AFEC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (AFEC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */ +#define AFEC_MR_TRGEN_EN (0x1u << 0) /**< \brief (AFEC_MR) Hardware trigger selected by TRGSEL field is enabled. */ +#define AFEC_MR_TRGSEL_Pos 1 +#define AFEC_MR_TRGSEL_Msk (0x7u << AFEC_MR_TRGSEL_Pos) /**< \brief (AFEC_MR) Trigger Selection */ +#define AFEC_MR_TRGSEL(value) ((AFEC_MR_TRGSEL_Msk & ((value) << AFEC_MR_TRGSEL_Pos))) +#define AFEC_MR_TRGSEL_AFEC_TRIG0 (0x0u << 1) /**< \brief (AFEC_MR) AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG1 (0x1u << 1) /**< \brief (AFEC_MR) TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG2 (0x2u << 1) /**< \brief (AFEC_MR) TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG3 (0x3u << 1) /**< \brief (AFEC_MR) TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG4 (0x4u << 1) /**< \brief (AFEC_MR) PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG5 (0x5u << 1) /**< \brief (AFEC_MR) PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG6 (0x6u << 1) /**< \brief (AFEC_MR) Analog Comparator */ +#define AFEC_MR_SLEEP (0x1u << 5) /**< \brief (AFEC_MR) Sleep Mode */ +#define AFEC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (AFEC_MR) Normal mode: The AFE and reference voltage circuitry are kept ON between conversions. */ +#define AFEC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (AFEC_MR) Sleep mode: The AFE and reference voltage circuitry are OFF between conversions. */ +#define AFEC_MR_FWUP (0x1u << 6) /**< \brief (AFEC_MR) Fast Wake-up */ +#define AFEC_MR_FWUP_OFF (0x0u << 6) /**< \brief (AFEC_MR) Normal Sleep mode: The sleep mode is defined by the SLEEP bit. */ +#define AFEC_MR_FWUP_ON (0x1u << 6) /**< \brief (AFEC_MR) Fast wake-up Sleep mode: The voltage reference is ON between conversions and AFE is OFF. */ +#define AFEC_MR_FREERUN (0x1u << 7) /**< \brief (AFEC_MR) Free Run Mode */ +#define AFEC_MR_FREERUN_OFF (0x0u << 7) /**< \brief (AFEC_MR) Normal mode */ +#define AFEC_MR_FREERUN_ON (0x1u << 7) /**< \brief (AFEC_MR) Free Run mode: Never wait for any trigger. */ +#define AFEC_MR_PRESCAL_Pos 8 +#define AFEC_MR_PRESCAL_Msk (0xffu << AFEC_MR_PRESCAL_Pos) /**< \brief (AFEC_MR) Prescaler Rate Selection */ +#define AFEC_MR_PRESCAL(value) ((AFEC_MR_PRESCAL_Msk & ((value) << AFEC_MR_PRESCAL_Pos))) +#define AFEC_MR_STARTUP_Pos 16 +#define AFEC_MR_STARTUP_Msk (0xfu << AFEC_MR_STARTUP_Pos) /**< \brief (AFEC_MR) Start-up Time */ +#define AFEC_MR_STARTUP(value) ((AFEC_MR_STARTUP_Msk & ((value) << AFEC_MR_STARTUP_Pos))) +#define AFEC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (AFEC_MR) 0 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (AFEC_MR) 8 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (AFEC_MR) 16 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (AFEC_MR) 24 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (AFEC_MR) 64 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (AFEC_MR) 80 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (AFEC_MR) 96 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (AFEC_MR) 112 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (AFEC_MR) 512 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (AFEC_MR) 576 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (AFEC_MR) 640 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (AFEC_MR) 704 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (AFEC_MR) 768 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (AFEC_MR) 832 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (AFEC_MR) 896 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (AFEC_MR) 960 periods of AFE clock */ +#define AFEC_MR_ONE (0x1u << 23) /**< \brief (AFEC_MR) One */ +#define AFEC_MR_TRACKTIM_Pos 24 +#define AFEC_MR_TRACKTIM_Msk (0xfu << AFEC_MR_TRACKTIM_Pos) /**< \brief (AFEC_MR) Tracking Time */ +#define AFEC_MR_TRACKTIM(value) ((AFEC_MR_TRACKTIM_Msk & ((value) << AFEC_MR_TRACKTIM_Pos))) +#define AFEC_MR_TRANSFER_Pos 28 +#define AFEC_MR_TRANSFER_Msk (0x3u << AFEC_MR_TRANSFER_Pos) /**< \brief (AFEC_MR) Transfer Period */ +#define AFEC_MR_TRANSFER(value) ((AFEC_MR_TRANSFER_Msk & ((value) << AFEC_MR_TRANSFER_Pos))) +#define AFEC_MR_USEQ (0x1u << 31) /**< \brief (AFEC_MR) User Sequence Enable */ +#define AFEC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (AFEC_MR) Normal mode: The controller converts channels in a simple numeric order. */ +#define AFEC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (AFEC_MR) User Sequence mode: The sequence respects what is defined in AFEC_SEQ1R and AFEC_SEQ1R. */ +/* -------- AFEC_EMR : (AFEC Offset: 0x08) AFEC Extended Mode Register -------- */ +#define AFEC_EMR_CMPMODE_Pos 0 +#define AFEC_EMR_CMPMODE_Msk (0x3u << AFEC_EMR_CMPMODE_Pos) /**< \brief (AFEC_EMR) Comparison Mode */ +#define AFEC_EMR_CMPMODE(value) ((AFEC_EMR_CMPMODE_Msk & ((value) << AFEC_EMR_CMPMODE_Pos))) +#define AFEC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */ +#define AFEC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */ +#define AFEC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is in the comparison window. */ +#define AFEC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is out of the comparison window. */ +#define AFEC_EMR_CMPSEL_Pos 3 +#define AFEC_EMR_CMPSEL_Msk (0x1fu << AFEC_EMR_CMPSEL_Pos) /**< \brief (AFEC_EMR) Comparison Selected Channel */ +#define AFEC_EMR_CMPSEL(value) ((AFEC_EMR_CMPSEL_Msk & ((value) << AFEC_EMR_CMPSEL_Pos))) +#define AFEC_EMR_CMPALL (0x1u << 9) /**< \brief (AFEC_EMR) Compare All Channels */ +#define AFEC_EMR_CMPFILTER_Pos 12 +#define AFEC_EMR_CMPFILTER_Msk (0x3u << AFEC_EMR_CMPFILTER_Pos) /**< \brief (AFEC_EMR) Compare Event Filtering */ +#define AFEC_EMR_CMPFILTER(value) ((AFEC_EMR_CMPFILTER_Msk & ((value) << AFEC_EMR_CMPFILTER_Pos))) +#define AFEC_EMR_RES_Pos 16 +#define AFEC_EMR_RES_Msk (0x7u << AFEC_EMR_RES_Pos) /**< \brief (AFEC_EMR) Resolution */ +#define AFEC_EMR_RES(value) ((AFEC_EMR_RES_Msk & ((value) << AFEC_EMR_RES_Pos))) +#define AFEC_EMR_RES_NO_AVERAGE (0x0u << 16) /**< \brief (AFEC_EMR) 12-bit resolution, AFE sample rate is maximum (no averaging). */ +#define AFEC_EMR_RES_OSR4 (0x2u << 16) /**< \brief (AFEC_EMR) 13-bit resolution, AFE sample rate divided by 4 (averaging). */ +#define AFEC_EMR_RES_OSR16 (0x3u << 16) /**< \brief (AFEC_EMR) 14-bit resolution, AFE sample rate divided by 16 (averaging). */ +#define AFEC_EMR_RES_OSR64 (0x4u << 16) /**< \brief (AFEC_EMR) 15-bit resolution, AFE sample rate divided by 64 (averaging). */ +#define AFEC_EMR_RES_OSR256 (0x5u << 16) /**< \brief (AFEC_EMR) 16-bit resolution, AFE sample rate divided by 256 (averaging). */ +#define AFEC_EMR_TAG (0x1u << 24) /**< \brief (AFEC_EMR) TAG of the AFEC_LDCR */ +#define AFEC_EMR_STM (0x1u << 25) /**< \brief (AFEC_EMR) Single Trigger Mode */ +#define AFEC_EMR_SIGNMODE_Pos 28 +#define AFEC_EMR_SIGNMODE_Msk (0x3u << AFEC_EMR_SIGNMODE_Pos) /**< \brief (AFEC_EMR) Sign Mode */ +#define AFEC_EMR_SIGNMODE(value) ((AFEC_EMR_SIGNMODE_Msk & ((value) << AFEC_EMR_SIGNMODE_Pos))) +#define AFEC_EMR_SIGNMODE_SE_UNSG_DF_SIGN (0x0u << 28) /**< \brief (AFEC_EMR) Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions. */ +#define AFEC_EMR_SIGNMODE_SE_SIGN_DF_UNSG (0x1u << 28) /**< \brief (AFEC_EMR) Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions. */ +#define AFEC_EMR_SIGNMODE_ALL_UNSIGNED (0x2u << 28) /**< \brief (AFEC_EMR) All channels: Unsigned conversions. */ +#define AFEC_EMR_SIGNMODE_ALL_SIGNED (0x3u << 28) /**< \brief (AFEC_EMR) All channels: Signed conversions. */ +/* -------- AFEC_SEQ1R : (AFEC Offset: 0x0C) AFEC Channel Sequence 1 Register -------- */ +#define AFEC_SEQ1R_USCH0_Pos 0 +#define AFEC_SEQ1R_USCH0_Msk (0xfu << AFEC_SEQ1R_USCH0_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 0 */ +#define AFEC_SEQ1R_USCH0(value) ((AFEC_SEQ1R_USCH0_Msk & ((value) << AFEC_SEQ1R_USCH0_Pos))) +#define AFEC_SEQ1R_USCH1_Pos 4 +#define AFEC_SEQ1R_USCH1_Msk (0xfu << AFEC_SEQ1R_USCH1_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 1 */ +#define AFEC_SEQ1R_USCH1(value) ((AFEC_SEQ1R_USCH1_Msk & ((value) << AFEC_SEQ1R_USCH1_Pos))) +#define AFEC_SEQ1R_USCH2_Pos 8 +#define AFEC_SEQ1R_USCH2_Msk (0xfu << AFEC_SEQ1R_USCH2_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 2 */ +#define AFEC_SEQ1R_USCH2(value) ((AFEC_SEQ1R_USCH2_Msk & ((value) << AFEC_SEQ1R_USCH2_Pos))) +#define AFEC_SEQ1R_USCH3_Pos 12 +#define AFEC_SEQ1R_USCH3_Msk (0xfu << AFEC_SEQ1R_USCH3_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 3 */ +#define AFEC_SEQ1R_USCH3(value) ((AFEC_SEQ1R_USCH3_Msk & ((value) << AFEC_SEQ1R_USCH3_Pos))) +#define AFEC_SEQ1R_USCH4_Pos 16 +#define AFEC_SEQ1R_USCH4_Msk (0xfu << AFEC_SEQ1R_USCH4_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 4 */ +#define AFEC_SEQ1R_USCH4(value) ((AFEC_SEQ1R_USCH4_Msk & ((value) << AFEC_SEQ1R_USCH4_Pos))) +#define AFEC_SEQ1R_USCH5_Pos 20 +#define AFEC_SEQ1R_USCH5_Msk (0xfu << AFEC_SEQ1R_USCH5_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 5 */ +#define AFEC_SEQ1R_USCH5(value) ((AFEC_SEQ1R_USCH5_Msk & ((value) << AFEC_SEQ1R_USCH5_Pos))) +#define AFEC_SEQ1R_USCH6_Pos 24 +#define AFEC_SEQ1R_USCH6_Msk (0xfu << AFEC_SEQ1R_USCH6_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 6 */ +#define AFEC_SEQ1R_USCH6(value) ((AFEC_SEQ1R_USCH6_Msk & ((value) << AFEC_SEQ1R_USCH6_Pos))) +#define AFEC_SEQ1R_USCH7_Pos 28 +#define AFEC_SEQ1R_USCH7_Msk (0xfu << AFEC_SEQ1R_USCH7_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 7 */ +#define AFEC_SEQ1R_USCH7(value) ((AFEC_SEQ1R_USCH7_Msk & ((value) << AFEC_SEQ1R_USCH7_Pos))) +/* -------- AFEC_SEQ2R : (AFEC Offset: 0x10) AFEC Channel Sequence 2 Register -------- */ +#define AFEC_SEQ2R_USCH8_Pos 0 +#define AFEC_SEQ2R_USCH8_Msk (0xfu << AFEC_SEQ2R_USCH8_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 8 */ +#define AFEC_SEQ2R_USCH8(value) ((AFEC_SEQ2R_USCH8_Msk & ((value) << AFEC_SEQ2R_USCH8_Pos))) +#define AFEC_SEQ2R_USCH9_Pos 4 +#define AFEC_SEQ2R_USCH9_Msk (0xfu << AFEC_SEQ2R_USCH9_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 9 */ +#define AFEC_SEQ2R_USCH9(value) ((AFEC_SEQ2R_USCH9_Msk & ((value) << AFEC_SEQ2R_USCH9_Pos))) +#define AFEC_SEQ2R_USCH10_Pos 8 +#define AFEC_SEQ2R_USCH10_Msk (0xfu << AFEC_SEQ2R_USCH10_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 10 */ +#define AFEC_SEQ2R_USCH10(value) ((AFEC_SEQ2R_USCH10_Msk & ((value) << AFEC_SEQ2R_USCH10_Pos))) +#define AFEC_SEQ2R_USCH11_Pos 12 +#define AFEC_SEQ2R_USCH11_Msk (0xfu << AFEC_SEQ2R_USCH11_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 11 */ +#define AFEC_SEQ2R_USCH11(value) ((AFEC_SEQ2R_USCH11_Msk & ((value) << AFEC_SEQ2R_USCH11_Pos))) +#define AFEC_SEQ2R_USCH12_Pos 16 +#define AFEC_SEQ2R_USCH12_Msk (0xfu << AFEC_SEQ2R_USCH12_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 12 */ +#define AFEC_SEQ2R_USCH12(value) ((AFEC_SEQ2R_USCH12_Msk & ((value) << AFEC_SEQ2R_USCH12_Pos))) +#define AFEC_SEQ2R_USCH13_Pos 20 +#define AFEC_SEQ2R_USCH13_Msk (0xfu << AFEC_SEQ2R_USCH13_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 13 */ +#define AFEC_SEQ2R_USCH13(value) ((AFEC_SEQ2R_USCH13_Msk & ((value) << AFEC_SEQ2R_USCH13_Pos))) +#define AFEC_SEQ2R_USCH14_Pos 24 +#define AFEC_SEQ2R_USCH14_Msk (0xfu << AFEC_SEQ2R_USCH14_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 14 */ +#define AFEC_SEQ2R_USCH14(value) ((AFEC_SEQ2R_USCH14_Msk & ((value) << AFEC_SEQ2R_USCH14_Pos))) +#define AFEC_SEQ2R_USCH15_Pos 28 +#define AFEC_SEQ2R_USCH15_Msk (0xfu << AFEC_SEQ2R_USCH15_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 15 */ +#define AFEC_SEQ2R_USCH15(value) ((AFEC_SEQ2R_USCH15_Msk & ((value) << AFEC_SEQ2R_USCH15_Pos))) +/* -------- AFEC_CHER : (AFEC Offset: 0x14) AFEC Channel Enable Register -------- */ +#define AFEC_CHER_CH0 (0x1u << 0) /**< \brief (AFEC_CHER) Channel 0 Enable */ +#define AFEC_CHER_CH1 (0x1u << 1) /**< \brief (AFEC_CHER) Channel 1 Enable */ +#define AFEC_CHER_CH2 (0x1u << 2) /**< \brief (AFEC_CHER) Channel 2 Enable */ +#define AFEC_CHER_CH3 (0x1u << 3) /**< \brief (AFEC_CHER) Channel 3 Enable */ +#define AFEC_CHER_CH4 (0x1u << 4) /**< \brief (AFEC_CHER) Channel 4 Enable */ +#define AFEC_CHER_CH5 (0x1u << 5) /**< \brief (AFEC_CHER) Channel 5 Enable */ +#define AFEC_CHER_CH6 (0x1u << 6) /**< \brief (AFEC_CHER) Channel 6 Enable */ +#define AFEC_CHER_CH7 (0x1u << 7) /**< \brief (AFEC_CHER) Channel 7 Enable */ +#define AFEC_CHER_CH8 (0x1u << 8) /**< \brief (AFEC_CHER) Channel 8 Enable */ +#define AFEC_CHER_CH9 (0x1u << 9) /**< \brief (AFEC_CHER) Channel 9 Enable */ +#define AFEC_CHER_CH10 (0x1u << 10) /**< \brief (AFEC_CHER) Channel 10 Enable */ +#define AFEC_CHER_CH11 (0x1u << 11) /**< \brief (AFEC_CHER) Channel 11 Enable */ +/* -------- AFEC_CHDR : (AFEC Offset: 0x18) AFEC Channel Disable Register -------- */ +#define AFEC_CHDR_CH0 (0x1u << 0) /**< \brief (AFEC_CHDR) Channel 0 Disable */ +#define AFEC_CHDR_CH1 (0x1u << 1) /**< \brief (AFEC_CHDR) Channel 1 Disable */ +#define AFEC_CHDR_CH2 (0x1u << 2) /**< \brief (AFEC_CHDR) Channel 2 Disable */ +#define AFEC_CHDR_CH3 (0x1u << 3) /**< \brief (AFEC_CHDR) Channel 3 Disable */ +#define AFEC_CHDR_CH4 (0x1u << 4) /**< \brief (AFEC_CHDR) Channel 4 Disable */ +#define AFEC_CHDR_CH5 (0x1u << 5) /**< \brief (AFEC_CHDR) Channel 5 Disable */ +#define AFEC_CHDR_CH6 (0x1u << 6) /**< \brief (AFEC_CHDR) Channel 6 Disable */ +#define AFEC_CHDR_CH7 (0x1u << 7) /**< \brief (AFEC_CHDR) Channel 7 Disable */ +#define AFEC_CHDR_CH8 (0x1u << 8) /**< \brief (AFEC_CHDR) Channel 8 Disable */ +#define AFEC_CHDR_CH9 (0x1u << 9) /**< \brief (AFEC_CHDR) Channel 9 Disable */ +#define AFEC_CHDR_CH10 (0x1u << 10) /**< \brief (AFEC_CHDR) Channel 10 Disable */ +#define AFEC_CHDR_CH11 (0x1u << 11) /**< \brief (AFEC_CHDR) Channel 11 Disable */ +/* -------- AFEC_CHSR : (AFEC Offset: 0x1C) AFEC Channel Status Register -------- */ +#define AFEC_CHSR_CH0 (0x1u << 0) /**< \brief (AFEC_CHSR) Channel 0 Status */ +#define AFEC_CHSR_CH1 (0x1u << 1) /**< \brief (AFEC_CHSR) Channel 1 Status */ +#define AFEC_CHSR_CH2 (0x1u << 2) /**< \brief (AFEC_CHSR) Channel 2 Status */ +#define AFEC_CHSR_CH3 (0x1u << 3) /**< \brief (AFEC_CHSR) Channel 3 Status */ +#define AFEC_CHSR_CH4 (0x1u << 4) /**< \brief (AFEC_CHSR) Channel 4 Status */ +#define AFEC_CHSR_CH5 (0x1u << 5) /**< \brief (AFEC_CHSR) Channel 5 Status */ +#define AFEC_CHSR_CH6 (0x1u << 6) /**< \brief (AFEC_CHSR) Channel 6 Status */ +#define AFEC_CHSR_CH7 (0x1u << 7) /**< \brief (AFEC_CHSR) Channel 7 Status */ +#define AFEC_CHSR_CH8 (0x1u << 8) /**< \brief (AFEC_CHSR) Channel 8 Status */ +#define AFEC_CHSR_CH9 (0x1u << 9) /**< \brief (AFEC_CHSR) Channel 9 Status */ +#define AFEC_CHSR_CH10 (0x1u << 10) /**< \brief (AFEC_CHSR) Channel 10 Status */ +#define AFEC_CHSR_CH11 (0x1u << 11) /**< \brief (AFEC_CHSR) Channel 11 Status */ +/* -------- AFEC_LCDR : (AFEC Offset: 0x20) AFEC Last Converted Data Register -------- */ +#define AFEC_LCDR_LDATA_Pos 0 +#define AFEC_LCDR_LDATA_Msk (0xffffu << AFEC_LCDR_LDATA_Pos) /**< \brief (AFEC_LCDR) Last Data Converted */ +#define AFEC_LCDR_CHNB_Pos 24 +#define AFEC_LCDR_CHNB_Msk (0xfu << AFEC_LCDR_CHNB_Pos) /**< \brief (AFEC_LCDR) Channel Number */ +/* -------- AFEC_IER : (AFEC Offset: 0x24) AFEC Interrupt Enable Register -------- */ +#define AFEC_IER_EOC0 (0x1u << 0) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 0 */ +#define AFEC_IER_EOC1 (0x1u << 1) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 1 */ +#define AFEC_IER_EOC2 (0x1u << 2) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 2 */ +#define AFEC_IER_EOC3 (0x1u << 3) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 3 */ +#define AFEC_IER_EOC4 (0x1u << 4) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 4 */ +#define AFEC_IER_EOC5 (0x1u << 5) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 5 */ +#define AFEC_IER_EOC6 (0x1u << 6) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 6 */ +#define AFEC_IER_EOC7 (0x1u << 7) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 7 */ +#define AFEC_IER_EOC8 (0x1u << 8) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 8 */ +#define AFEC_IER_EOC9 (0x1u << 9) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 9 */ +#define AFEC_IER_EOC10 (0x1u << 10) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 10 */ +#define AFEC_IER_EOC11 (0x1u << 11) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 11 */ +#define AFEC_IER_DRDY (0x1u << 24) /**< \brief (AFEC_IER) Data Ready Interrupt Enable */ +#define AFEC_IER_GOVRE (0x1u << 25) /**< \brief (AFEC_IER) General Overrun Error Interrupt Enable */ +#define AFEC_IER_COMPE (0x1u << 26) /**< \brief (AFEC_IER) Comparison Event Interrupt Enable */ +#define AFEC_IER_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IER) Temperature Change Interrupt Enable */ +/* -------- AFEC_IDR : (AFEC Offset: 0x28) AFEC Interrupt Disable Register -------- */ +#define AFEC_IDR_EOC0 (0x1u << 0) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 0 */ +#define AFEC_IDR_EOC1 (0x1u << 1) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 1 */ +#define AFEC_IDR_EOC2 (0x1u << 2) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 2 */ +#define AFEC_IDR_EOC3 (0x1u << 3) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 3 */ +#define AFEC_IDR_EOC4 (0x1u << 4) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 4 */ +#define AFEC_IDR_EOC5 (0x1u << 5) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 5 */ +#define AFEC_IDR_EOC6 (0x1u << 6) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 6 */ +#define AFEC_IDR_EOC7 (0x1u << 7) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 7 */ +#define AFEC_IDR_EOC8 (0x1u << 8) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 8 */ +#define AFEC_IDR_EOC9 (0x1u << 9) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 9 */ +#define AFEC_IDR_EOC10 (0x1u << 10) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 10 */ +#define AFEC_IDR_EOC11 (0x1u << 11) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 11 */ +#define AFEC_IDR_DRDY (0x1u << 24) /**< \brief (AFEC_IDR) Data Ready Interrupt Disable */ +#define AFEC_IDR_GOVRE (0x1u << 25) /**< \brief (AFEC_IDR) General Overrun Error Interrupt Disable */ +#define AFEC_IDR_COMPE (0x1u << 26) /**< \brief (AFEC_IDR) Comparison Event Interrupt Disable */ +#define AFEC_IDR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IDR) Temperature Change Interrupt Disable */ +/* -------- AFEC_IMR : (AFEC Offset: 0x2C) AFEC Interrupt Mask Register -------- */ +#define AFEC_IMR_EOC0 (0x1u << 0) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 0 */ +#define AFEC_IMR_EOC1 (0x1u << 1) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 1 */ +#define AFEC_IMR_EOC2 (0x1u << 2) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 2 */ +#define AFEC_IMR_EOC3 (0x1u << 3) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 3 */ +#define AFEC_IMR_EOC4 (0x1u << 4) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 4 */ +#define AFEC_IMR_EOC5 (0x1u << 5) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 5 */ +#define AFEC_IMR_EOC6 (0x1u << 6) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 6 */ +#define AFEC_IMR_EOC7 (0x1u << 7) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 7 */ +#define AFEC_IMR_EOC8 (0x1u << 8) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 8 */ +#define AFEC_IMR_EOC9 (0x1u << 9) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 9 */ +#define AFEC_IMR_EOC10 (0x1u << 10) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 10 */ +#define AFEC_IMR_EOC11 (0x1u << 11) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 11 */ +#define AFEC_IMR_DRDY (0x1u << 24) /**< \brief (AFEC_IMR) Data Ready Interrupt Mask */ +#define AFEC_IMR_GOVRE (0x1u << 25) /**< \brief (AFEC_IMR) General Overrun Error Interrupt Mask */ +#define AFEC_IMR_COMPE (0x1u << 26) /**< \brief (AFEC_IMR) Comparison Event Interrupt Mask */ +#define AFEC_IMR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IMR) Temperature Change Interrupt Mask */ +/* -------- AFEC_ISR : (AFEC Offset: 0x30) AFEC Interrupt Status Register -------- */ +#define AFEC_ISR_EOC0 (0x1u << 0) /**< \brief (AFEC_ISR) End of Conversion 0 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC1 (0x1u << 1) /**< \brief (AFEC_ISR) End of Conversion 1 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC2 (0x1u << 2) /**< \brief (AFEC_ISR) End of Conversion 2 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC3 (0x1u << 3) /**< \brief (AFEC_ISR) End of Conversion 3 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC4 (0x1u << 4) /**< \brief (AFEC_ISR) End of Conversion 4 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC5 (0x1u << 5) /**< \brief (AFEC_ISR) End of Conversion 5 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC6 (0x1u << 6) /**< \brief (AFEC_ISR) End of Conversion 6 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC7 (0x1u << 7) /**< \brief (AFEC_ISR) End of Conversion 7 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC8 (0x1u << 8) /**< \brief (AFEC_ISR) End of Conversion 8 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC9 (0x1u << 9) /**< \brief (AFEC_ISR) End of Conversion 9 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC10 (0x1u << 10) /**< \brief (AFEC_ISR) End of Conversion 10 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC11 (0x1u << 11) /**< \brief (AFEC_ISR) End of Conversion 11 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_DRDY (0x1u << 24) /**< \brief (AFEC_ISR) Data Ready (cleared by reading AFEC_LCDR) */ +#define AFEC_ISR_GOVRE (0x1u << 25) /**< \brief (AFEC_ISR) General Overrun Error (cleared by reading AFEC_ISR) */ +#define AFEC_ISR_COMPE (0x1u << 26) /**< \brief (AFEC_ISR) Comparison Error (cleared by reading AFEC_ISR) */ +#define AFEC_ISR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_ISR) Temperature Change (cleared on read) */ +/* -------- AFEC_OVER : (AFEC Offset: 0x4C) AFEC Overrun Status Register -------- */ +#define AFEC_OVER_OVRE0 (0x1u << 0) /**< \brief (AFEC_OVER) Overrun Error 0 */ +#define AFEC_OVER_OVRE1 (0x1u << 1) /**< \brief (AFEC_OVER) Overrun Error 1 */ +#define AFEC_OVER_OVRE2 (0x1u << 2) /**< \brief (AFEC_OVER) Overrun Error 2 */ +#define AFEC_OVER_OVRE3 (0x1u << 3) /**< \brief (AFEC_OVER) Overrun Error 3 */ +#define AFEC_OVER_OVRE4 (0x1u << 4) /**< \brief (AFEC_OVER) Overrun Error 4 */ +#define AFEC_OVER_OVRE5 (0x1u << 5) /**< \brief (AFEC_OVER) Overrun Error 5 */ +#define AFEC_OVER_OVRE6 (0x1u << 6) /**< \brief (AFEC_OVER) Overrun Error 6 */ +#define AFEC_OVER_OVRE7 (0x1u << 7) /**< \brief (AFEC_OVER) Overrun Error 7 */ +#define AFEC_OVER_OVRE8 (0x1u << 8) /**< \brief (AFEC_OVER) Overrun Error 8 */ +#define AFEC_OVER_OVRE9 (0x1u << 9) /**< \brief (AFEC_OVER) Overrun Error 9 */ +#define AFEC_OVER_OVRE10 (0x1u << 10) /**< \brief (AFEC_OVER) Overrun Error 10 */ +#define AFEC_OVER_OVRE11 (0x1u << 11) /**< \brief (AFEC_OVER) Overrun Error 11 */ +/* -------- AFEC_CWR : (AFEC Offset: 0x50) AFEC Compare Window Register -------- */ +#define AFEC_CWR_LOWTHRES_Pos 0 +#define AFEC_CWR_LOWTHRES_Msk (0xffffu << AFEC_CWR_LOWTHRES_Pos) /**< \brief (AFEC_CWR) Low Threshold */ +#define AFEC_CWR_LOWTHRES(value) ((AFEC_CWR_LOWTHRES_Msk & ((value) << AFEC_CWR_LOWTHRES_Pos))) +#define AFEC_CWR_HIGHTHRES_Pos 16 +#define AFEC_CWR_HIGHTHRES_Msk (0xffffu << AFEC_CWR_HIGHTHRES_Pos) /**< \brief (AFEC_CWR) High Threshold */ +#define AFEC_CWR_HIGHTHRES(value) ((AFEC_CWR_HIGHTHRES_Msk & ((value) << AFEC_CWR_HIGHTHRES_Pos))) +/* -------- AFEC_CGR : (AFEC Offset: 0x54) AFEC Channel Gain Register -------- */ +#define AFEC_CGR_GAIN0_Pos 0 +#define AFEC_CGR_GAIN0_Msk (0x3u << AFEC_CGR_GAIN0_Pos) /**< \brief (AFEC_CGR) Gain for Channel 0 */ +#define AFEC_CGR_GAIN0(value) ((AFEC_CGR_GAIN0_Msk & ((value) << AFEC_CGR_GAIN0_Pos))) +#define AFEC_CGR_GAIN1_Pos 2 +#define AFEC_CGR_GAIN1_Msk (0x3u << AFEC_CGR_GAIN1_Pos) /**< \brief (AFEC_CGR) Gain for Channel 1 */ +#define AFEC_CGR_GAIN1(value) ((AFEC_CGR_GAIN1_Msk & ((value) << AFEC_CGR_GAIN1_Pos))) +#define AFEC_CGR_GAIN2_Pos 4 +#define AFEC_CGR_GAIN2_Msk (0x3u << AFEC_CGR_GAIN2_Pos) /**< \brief (AFEC_CGR) Gain for Channel 2 */ +#define AFEC_CGR_GAIN2(value) ((AFEC_CGR_GAIN2_Msk & ((value) << AFEC_CGR_GAIN2_Pos))) +#define AFEC_CGR_GAIN3_Pos 6 +#define AFEC_CGR_GAIN3_Msk (0x3u << AFEC_CGR_GAIN3_Pos) /**< \brief (AFEC_CGR) Gain for Channel 3 */ +#define AFEC_CGR_GAIN3(value) ((AFEC_CGR_GAIN3_Msk & ((value) << AFEC_CGR_GAIN3_Pos))) +#define AFEC_CGR_GAIN4_Pos 8 +#define AFEC_CGR_GAIN4_Msk (0x3u << AFEC_CGR_GAIN4_Pos) /**< \brief (AFEC_CGR) Gain for Channel 4 */ +#define AFEC_CGR_GAIN4(value) ((AFEC_CGR_GAIN4_Msk & ((value) << AFEC_CGR_GAIN4_Pos))) +#define AFEC_CGR_GAIN5_Pos 10 +#define AFEC_CGR_GAIN5_Msk (0x3u << AFEC_CGR_GAIN5_Pos) /**< \brief (AFEC_CGR) Gain for Channel 5 */ +#define AFEC_CGR_GAIN5(value) ((AFEC_CGR_GAIN5_Msk & ((value) << AFEC_CGR_GAIN5_Pos))) +#define AFEC_CGR_GAIN6_Pos 12 +#define AFEC_CGR_GAIN6_Msk (0x3u << AFEC_CGR_GAIN6_Pos) /**< \brief (AFEC_CGR) Gain for Channel 6 */ +#define AFEC_CGR_GAIN6(value) ((AFEC_CGR_GAIN6_Msk & ((value) << AFEC_CGR_GAIN6_Pos))) +#define AFEC_CGR_GAIN7_Pos 14 +#define AFEC_CGR_GAIN7_Msk (0x3u << AFEC_CGR_GAIN7_Pos) /**< \brief (AFEC_CGR) Gain for Channel 7 */ +#define AFEC_CGR_GAIN7(value) ((AFEC_CGR_GAIN7_Msk & ((value) << AFEC_CGR_GAIN7_Pos))) +#define AFEC_CGR_GAIN8_Pos 16 +#define AFEC_CGR_GAIN8_Msk (0x3u << AFEC_CGR_GAIN8_Pos) /**< \brief (AFEC_CGR) Gain for Channel 8 */ +#define AFEC_CGR_GAIN8(value) ((AFEC_CGR_GAIN8_Msk & ((value) << AFEC_CGR_GAIN8_Pos))) +#define AFEC_CGR_GAIN9_Pos 18 +#define AFEC_CGR_GAIN9_Msk (0x3u << AFEC_CGR_GAIN9_Pos) /**< \brief (AFEC_CGR) Gain for Channel 9 */ +#define AFEC_CGR_GAIN9(value) ((AFEC_CGR_GAIN9_Msk & ((value) << AFEC_CGR_GAIN9_Pos))) +#define AFEC_CGR_GAIN10_Pos 20 +#define AFEC_CGR_GAIN10_Msk (0x3u << AFEC_CGR_GAIN10_Pos) /**< \brief (AFEC_CGR) Gain for Channel 10 */ +#define AFEC_CGR_GAIN10(value) ((AFEC_CGR_GAIN10_Msk & ((value) << AFEC_CGR_GAIN10_Pos))) +#define AFEC_CGR_GAIN11_Pos 22 +#define AFEC_CGR_GAIN11_Msk (0x3u << AFEC_CGR_GAIN11_Pos) /**< \brief (AFEC_CGR) Gain for Channel 11 */ +#define AFEC_CGR_GAIN11(value) ((AFEC_CGR_GAIN11_Msk & ((value) << AFEC_CGR_GAIN11_Pos))) +/* -------- AFEC_DIFFR : (AFEC Offset: 0x60) AFEC Channel Differential Register -------- */ +#define AFEC_DIFFR_DIFF0 (0x1u << 0) /**< \brief (AFEC_DIFFR) Differential inputs for channel 0 */ +#define AFEC_DIFFR_DIFF1 (0x1u << 1) /**< \brief (AFEC_DIFFR) Differential inputs for channel 1 */ +#define AFEC_DIFFR_DIFF2 (0x1u << 2) /**< \brief (AFEC_DIFFR) Differential inputs for channel 2 */ +#define AFEC_DIFFR_DIFF3 (0x1u << 3) /**< \brief (AFEC_DIFFR) Differential inputs for channel 3 */ +#define AFEC_DIFFR_DIFF4 (0x1u << 4) /**< \brief (AFEC_DIFFR) Differential inputs for channel 4 */ +#define AFEC_DIFFR_DIFF5 (0x1u << 5) /**< \brief (AFEC_DIFFR) Differential inputs for channel 5 */ +#define AFEC_DIFFR_DIFF6 (0x1u << 6) /**< \brief (AFEC_DIFFR) Differential inputs for channel 6 */ +#define AFEC_DIFFR_DIFF7 (0x1u << 7) /**< \brief (AFEC_DIFFR) Differential inputs for channel 7 */ +#define AFEC_DIFFR_DIFF8 (0x1u << 8) /**< \brief (AFEC_DIFFR) Differential inputs for channel 8 */ +#define AFEC_DIFFR_DIFF9 (0x1u << 9) /**< \brief (AFEC_DIFFR) Differential inputs for channel 9 */ +#define AFEC_DIFFR_DIFF10 (0x1u << 10) /**< \brief (AFEC_DIFFR) Differential inputs for channel 10 */ +#define AFEC_DIFFR_DIFF11 (0x1u << 11) /**< \brief (AFEC_DIFFR) Differential inputs for channel 11 */ +/* -------- AFEC_CSELR : (AFEC Offset: 0x64) AFEC Channel Selection Register -------- */ +#define AFEC_CSELR_CSEL_Pos 0 +#define AFEC_CSELR_CSEL_Msk (0xfu << AFEC_CSELR_CSEL_Pos) /**< \brief (AFEC_CSELR) Channel Selection */ +#define AFEC_CSELR_CSEL(value) ((AFEC_CSELR_CSEL_Msk & ((value) << AFEC_CSELR_CSEL_Pos))) +/* -------- AFEC_CDR : (AFEC Offset: 0x68) AFEC Channel Data Register -------- */ +#define AFEC_CDR_DATA_Pos 0 +#define AFEC_CDR_DATA_Msk (0xffffu << AFEC_CDR_DATA_Pos) /**< \brief (AFEC_CDR) Converted Data */ +/* -------- AFEC_COCR : (AFEC Offset: 0x6C) AFEC Channel Offset Compensation Register -------- */ +#define AFEC_COCR_AOFF_Pos 0 +#define AFEC_COCR_AOFF_Msk (0xfffu << AFEC_COCR_AOFF_Pos) /**< \brief (AFEC_COCR) Analog Offset */ +#define AFEC_COCR_AOFF(value) ((AFEC_COCR_AOFF_Msk & ((value) << AFEC_COCR_AOFF_Pos))) +/* -------- AFEC_TEMPMR : (AFEC Offset: 0x70) AFEC Temperature Sensor Mode Register -------- */ +#define AFEC_TEMPMR_RTCT (0x1u << 0) /**< \brief (AFEC_TEMPMR) Temperature Sensor RTC Trigger Mode */ +#define AFEC_TEMPMR_TEMPCMPMOD_Pos 4 +#define AFEC_TEMPMR_TEMPCMPMOD_Msk (0x3u << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< \brief (AFEC_TEMPMR) Temperature Comparison Mode */ +#define AFEC_TEMPMR_TEMPCMPMOD(value) ((AFEC_TEMPMR_TEMPCMPMOD_Msk & ((value) << AFEC_TEMPMR_TEMPCMPMOD_Pos))) +#define AFEC_TEMPMR_TEMPCMPMOD_LOW (0x0u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is lower than the low threshold of the window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_HIGH (0x1u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is higher than the high threshold of the window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_IN (0x2u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is in the comparison window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_OUT (0x3u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is out of the comparison window. */ +/* -------- AFEC_TEMPCWR : (AFEC Offset: 0x74) AFEC Temperature Compare Window Register -------- */ +#define AFEC_TEMPCWR_TLOWTHRES_Pos 0 +#define AFEC_TEMPCWR_TLOWTHRES_Msk (0xffffu << AFEC_TEMPCWR_TLOWTHRES_Pos) /**< \brief (AFEC_TEMPCWR) Temperature Low Threshold */ +#define AFEC_TEMPCWR_TLOWTHRES(value) ((AFEC_TEMPCWR_TLOWTHRES_Msk & ((value) << AFEC_TEMPCWR_TLOWTHRES_Pos))) +#define AFEC_TEMPCWR_THIGHTHRES_Pos 16 +#define AFEC_TEMPCWR_THIGHTHRES_Msk (0xffffu << AFEC_TEMPCWR_THIGHTHRES_Pos) /**< \brief (AFEC_TEMPCWR) Temperature High Threshold */ +#define AFEC_TEMPCWR_THIGHTHRES(value) ((AFEC_TEMPCWR_THIGHTHRES_Msk & ((value) << AFEC_TEMPCWR_THIGHTHRES_Pos))) +/* -------- AFEC_ACR : (AFEC Offset: 0x94) AFEC Analog Control Register -------- */ +#define AFEC_ACR_PGA0EN (0x1u << 2) /**< \brief (AFEC_ACR) PGA0 Enable */ +#define AFEC_ACR_PGA1EN (0x1u << 3) /**< \brief (AFEC_ACR) PGA1 Enable */ +#define AFEC_ACR_IBCTL_Pos 8 +#define AFEC_ACR_IBCTL_Msk (0x3u << AFEC_ACR_IBCTL_Pos) /**< \brief (AFEC_ACR) AFE Bias Current Control */ +#define AFEC_ACR_IBCTL(value) ((AFEC_ACR_IBCTL_Msk & ((value) << AFEC_ACR_IBCTL_Pos))) +/* -------- AFEC_SHMR : (AFEC Offset: 0xA0) AFEC Sample & Hold Mode Register -------- */ +#define AFEC_SHMR_DUAL0 (0x1u << 0) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 0 */ +#define AFEC_SHMR_DUAL1 (0x1u << 1) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 1 */ +#define AFEC_SHMR_DUAL2 (0x1u << 2) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 2 */ +#define AFEC_SHMR_DUAL3 (0x1u << 3) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 3 */ +#define AFEC_SHMR_DUAL4 (0x1u << 4) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 4 */ +#define AFEC_SHMR_DUAL5 (0x1u << 5) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 5 */ +#define AFEC_SHMR_DUAL6 (0x1u << 6) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 6 */ +#define AFEC_SHMR_DUAL7 (0x1u << 7) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 7 */ +#define AFEC_SHMR_DUAL8 (0x1u << 8) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 8 */ +#define AFEC_SHMR_DUAL9 (0x1u << 9) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 9 */ +#define AFEC_SHMR_DUAL10 (0x1u << 10) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 10 */ +#define AFEC_SHMR_DUAL11 (0x1u << 11) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 11 */ +/* -------- AFEC_COSR : (AFEC Offset: 0xD0) AFEC Correction Select Register -------- */ +#define AFEC_COSR_CSEL (0x1u << 0) /**< \brief (AFEC_COSR) Sample & Hold unit Correction Select */ +/* -------- AFEC_CVR : (AFEC Offset: 0xD4) AFEC Correction Values Register -------- */ +#define AFEC_CVR_OFFSETCORR_Pos 0 +#define AFEC_CVR_OFFSETCORR_Msk (0xffffu << AFEC_CVR_OFFSETCORR_Pos) /**< \brief (AFEC_CVR) Offset Correction */ +#define AFEC_CVR_OFFSETCORR(value) ((AFEC_CVR_OFFSETCORR_Msk & ((value) << AFEC_CVR_OFFSETCORR_Pos))) +#define AFEC_CVR_GAINCORR_Pos 16 +#define AFEC_CVR_GAINCORR_Msk (0xffffu << AFEC_CVR_GAINCORR_Pos) /**< \brief (AFEC_CVR) Gain Correction */ +#define AFEC_CVR_GAINCORR(value) ((AFEC_CVR_GAINCORR_Msk & ((value) << AFEC_CVR_GAINCORR_Pos))) +/* -------- AFEC_CECR : (AFEC Offset: 0xD8) AFEC Channel Error Correction Register -------- */ +#define AFEC_CECR_ECORR0 (0x1u << 0) /**< \brief (AFEC_CECR) Error Correction Enable for channel 0 */ +#define AFEC_CECR_ECORR1 (0x1u << 1) /**< \brief (AFEC_CECR) Error Correction Enable for channel 1 */ +#define AFEC_CECR_ECORR2 (0x1u << 2) /**< \brief (AFEC_CECR) Error Correction Enable for channel 2 */ +#define AFEC_CECR_ECORR3 (0x1u << 3) /**< \brief (AFEC_CECR) Error Correction Enable for channel 3 */ +#define AFEC_CECR_ECORR4 (0x1u << 4) /**< \brief (AFEC_CECR) Error Correction Enable for channel 4 */ +#define AFEC_CECR_ECORR5 (0x1u << 5) /**< \brief (AFEC_CECR) Error Correction Enable for channel 5 */ +#define AFEC_CECR_ECORR6 (0x1u << 6) /**< \brief (AFEC_CECR) Error Correction Enable for channel 6 */ +#define AFEC_CECR_ECORR7 (0x1u << 7) /**< \brief (AFEC_CECR) Error Correction Enable for channel 7 */ +#define AFEC_CECR_ECORR8 (0x1u << 8) /**< \brief (AFEC_CECR) Error Correction Enable for channel 8 */ +#define AFEC_CECR_ECORR9 (0x1u << 9) /**< \brief (AFEC_CECR) Error Correction Enable for channel 9 */ +#define AFEC_CECR_ECORR10 (0x1u << 10) /**< \brief (AFEC_CECR) Error Correction Enable for channel 10 */ +#define AFEC_CECR_ECORR11 (0x1u << 11) /**< \brief (AFEC_CECR) Error Correction Enable for channel 11 */ +/* -------- AFEC_WPMR : (AFEC Offset: 0xE4) AFEC Write Protection Mode Register -------- */ +#define AFEC_WPMR_WPEN (0x1u << 0) /**< \brief (AFEC_WPMR) Write Protection Enable */ +#define AFEC_WPMR_WPKEY_Pos 8 +#define AFEC_WPMR_WPKEY_Msk (0xffffffu << AFEC_WPMR_WPKEY_Pos) /**< \brief (AFEC_WPMR) Write Protect KEY */ +#define AFEC_WPMR_WPKEY(value) ((AFEC_WPMR_WPKEY_Msk & ((value) << AFEC_WPMR_WPKEY_Pos))) +#define AFEC_WPMR_WPKEY_PASSWD (0x414443u << 8) /**< \brief (AFEC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- AFEC_WPSR : (AFEC Offset: 0xE8) AFEC Write Protection Status Register -------- */ +#define AFEC_WPSR_WPVS (0x1u << 0) /**< \brief (AFEC_WPSR) Write Protect Violation Status */ +#define AFEC_WPSR_WPVSRC_Pos 8 +#define AFEC_WPSR_WPVSRC_Msk (0xffffu << AFEC_WPSR_WPVSRC_Pos) /**< \brief (AFEC_WPSR) Write Protect Violation Source */ +/* -------- AFEC_VERSION : (AFEC Offset: 0xFC) AFEC Version Register -------- */ +#define AFEC_VERSION_VERSION_Pos 0 +#define AFEC_VERSION_VERSION_Msk (0xfffu << AFEC_VERSION_VERSION_Pos) /**< \brief (AFEC_VERSION) Version of the Hardware Module */ +#define AFEC_VERSION_MFN_Pos 16 +#define AFEC_VERSION_MFN_Msk (0x7u << AFEC_VERSION_MFN_Pos) /**< \brief (AFEC_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_AFEC_COMPONENT_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/chipid.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/chipid.h new file mode 100644 index 000000000..3ba65d34e --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/chipid.h @@ -0,0 +1,128 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_CHIPID_COMPONENT_ +#define _SAME70_CHIPID_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Chip Identifier */ +/* ============================================================================= */ +/** \addtogroup SAME70_CHIPID Chip Identifier */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Chipid hardware registers */ +typedef struct { + __I uint32_t CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */ + __I uint32_t CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */ +} Chipid; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */ +#define CHIPID_CIDR_VERSION_Pos 0 +#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */ +#define CHIPID_CIDR_EPROC_Pos 5 +#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */ +#define CHIPID_CIDR_EPROC_SAMx7 (0x0u << 5) /**< \brief (CHIPID_CIDR) Cortex-M7 */ +#define CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */ +#define CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */ +#define CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */ +#define CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */ +#define CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */ +#define CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */ +#define CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */ +#define CHIPID_CIDR_NVPSIZ_Pos 8 +#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */ +#define CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */ +#define CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_160K (0x8u << 8) /**< \brief (CHIPID_CIDR) 160 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_Pos 12 +#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) Second Nonvolatile Program Memory Size */ +#define CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */ +#define CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_Pos 16 +#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */ +#define CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_192K (0x1u << 16) /**< \brief (CHIPID_CIDR) 192 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_384K (0x2u << 16) /**< \brief (CHIPID_CIDR) 384 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_ARCH_Pos 20 +#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */ +#define CHIPID_CIDR_ARCH_SAME70 (0x10u << 20) /**< \brief (CHIPID_CIDR) SAM E70 */ +#define CHIPID_CIDR_ARCH_SAMS70 (0x11u << 20) /**< \brief (CHIPID_CIDR) SAM S70 */ +#define CHIPID_CIDR_ARCH_SAMV71 (0x12u << 20) /**< \brief (CHIPID_CIDR) SAM V71 */ +#define CHIPID_CIDR_ARCH_SAMV70 (0x13u << 20) /**< \brief (CHIPID_CIDR) SAM V70 */ +#define CHIPID_CIDR_NVPTYP_Pos 28 +#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */ +#define CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */ +#define CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */ +#define CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */ +#define CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size */ +#define CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */ +#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */ +/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */ +#define CHIPID_EXID_EXID_Pos 0 +#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */ + +/*@}*/ + + +#endif /* _SAME70_CHIPID_COMPONENT_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/dacc.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/dacc.h new file mode 100644 index 000000000..899126fca --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/dacc.h @@ -0,0 +1,217 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_DACC_COMPONENT_ +#define _SAME70_DACC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_DACC Digital-to-Analog Converter Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Dacc hardware registers */ +typedef struct { + __O uint32_t DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */ + __IO uint32_t DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */ + __IO uint32_t DACC_TRIGR; /**< \brief (Dacc Offset: 0x08) Trigger Register */ + __I uint32_t Reserved1[1]; + __O uint32_t DACC_CHER; /**< \brief (Dacc Offset: 0x10) Channel Enable Register */ + __O uint32_t DACC_CHDR; /**< \brief (Dacc Offset: 0x14) Channel Disable Register */ + __I uint32_t DACC_CHSR; /**< \brief (Dacc Offset: 0x18) Channel Status Register */ + __O uint32_t DACC_CDR[2]; /**< \brief (Dacc Offset: 0x1C) Conversion Data Register */ + __O uint32_t DACC_IER; /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */ + __O uint32_t DACC_IDR; /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */ + __I uint32_t DACC_IMR; /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t DACC_ISR; /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */ + __I uint32_t Reserved2[24]; + __IO uint32_t DACC_ACR; /**< \brief (Dacc Offset: 0x94) Analog Current Register */ + __I uint32_t Reserved3[19]; + __IO uint32_t DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved4[4]; + __I uint32_t DACC_VERSION; /**< \brief (Dacc Offset: 0xFC) Version Register */ +} Dacc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */ +#define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */ +/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */ +#define DACC_MR_MAXS0 (0x1u << 0) /**< \brief (DACC_MR) Max Speed Mode for Channel 0 */ +#define DACC_MR_MAXS0_TRIG_EVENT (0x0u << 0) /**< \brief (DACC_MR) Triggered by selected event */ +#define DACC_MR_MAXS0_MAXIMUM (0x1u << 0) /**< \brief (DACC_MR) Max Speed Mode enabled */ +#define DACC_MR_MAXS1 (0x1u << 1) /**< \brief (DACC_MR) Max Speed Mode for Channel 1 */ +#define DACC_MR_MAXS1_TRIG_EVENT (0x0u << 1) /**< \brief (DACC_MR) Triggered by selected event */ +#define DACC_MR_MAXS1_MAXIMUM (0x1u << 1) /**< \brief (DACC_MR) Max Speed Mode enabled */ +#define DACC_MR_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer Mode */ +#define DACC_MR_WORD_DISABLED (0x0u << 4) /**< \brief (DACC_MR) One data to convert is written to the FIFO per access to DACC */ +#define DACC_MR_WORD_ENABLED (0x1u << 4) /**< \brief (DACC_MR) Two data to convert are written to the FIFO per access to DACC (reduces number of requests to DMA and the number of system bus accesses) */ +#define DACC_MR_ZERO (0x1u << 5) /**< \brief (DACC_MR) Must always be written to 0. */ +#define DACC_MR_REFRESH_Pos 8 +#define DACC_MR_REFRESH_Msk (0xffu << DACC_MR_REFRESH_Pos) /**< \brief (DACC_MR) Refresh Period */ +#define DACC_MR_REFRESH(value) ((DACC_MR_REFRESH_Msk & ((value) << DACC_MR_REFRESH_Pos))) +#define DACC_MR_DIFF (0x1u << 23) /**< \brief (DACC_MR) Differential Mode */ +#define DACC_MR_DIFF_DISABLED (0x0u << 23) /**< \brief (DACC_MR) DAC0 and DAC1 outputs can be separately configured */ +#define DACC_MR_DIFF_ENABLED (0x1u << 23) /**< \brief (DACC_MR) DACP and DACN outputs are configured by the channel 0 value. */ +#define DACC_MR_PRESCALER_Pos 24 +#define DACC_MR_PRESCALER_Msk (0xfu << DACC_MR_PRESCALER_Pos) /**< \brief (DACC_MR) Peripheral Clock to DAC Clock Ratio */ +#define DACC_MR_PRESCALER(value) ((DACC_MR_PRESCALER_Msk & ((value) << DACC_MR_PRESCALER_Pos))) +/* -------- DACC_TRIGR : (DACC Offset: 0x08) Trigger Register -------- */ +#define DACC_TRIGR_TRGEN0 (0x1u << 0) /**< \brief (DACC_TRIGR) Trigger Enable of Channel 0 */ +#define DACC_TRIGR_TRGEN0_DIS (0x0u << 0) /**< \brief (DACC_TRIGR) External trigger mode disabled. DAC is in free running mode. */ +#define DACC_TRIGR_TRGEN0_EN (0x1u << 0) /**< \brief (DACC_TRIGR) External trigger mode enabled. */ +#define DACC_TRIGR_TRGEN1 (0x1u << 1) /**< \brief (DACC_TRIGR) Trigger Enable of Channel 1 */ +#define DACC_TRIGR_TRGEN1_DIS (0x0u << 1) /**< \brief (DACC_TRIGR) External trigger mode disabled. DAC is in free running mode. */ +#define DACC_TRIGR_TRGEN1_EN (0x1u << 1) /**< \brief (DACC_TRIGR) External trigger mode enabled. */ +#define DACC_TRIGR_TRGSEL0_Pos 4 +#define DACC_TRIGR_TRGSEL0_Msk (0x7u << DACC_TRIGR_TRGSEL0_Pos) /**< \brief (DACC_TRIGR) Trigger Selection of Channel 0 */ +#define DACC_TRIGR_TRGSEL0(value) ((DACC_TRIGR_TRGSEL0_Msk & ((value) << DACC_TRIGR_TRGSEL0_Pos))) +#define DACC_TRIGR_TRGSEL0_TRGSEL0 (0x0u << 4) /**< \brief (DACC_TRIGR) DATRG */ +#define DACC_TRIGR_TRGSEL0_TRGSEL1 (0x1u << 4) /**< \brief (DACC_TRIGR) TC0 output */ +#define DACC_TRIGR_TRGSEL0_TRGSEL2 (0x2u << 4) /**< \brief (DACC_TRIGR) TC1 output */ +#define DACC_TRIGR_TRGSEL0_TRGSEL3 (0x3u << 4) /**< \brief (DACC_TRIGR) TC2 output */ +#define DACC_TRIGR_TRGSEL0_TRGSEL4 (0x4u << 4) /**< \brief (DACC_TRIGR) PWM0 event 0 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL5 (0x5u << 4) /**< \brief (DACC_TRIGR) PWM0 event 1 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL6 (0x6u << 4) /**< \brief (DACC_TRIGR) PWM1 event 0 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL7 (0x7u << 4) /**< \brief (DACC_TRIGR) PWM1 event 1 */ +#define DACC_TRIGR_TRGSEL1_Pos 8 +#define DACC_TRIGR_TRGSEL1_Msk (0x7u << DACC_TRIGR_TRGSEL1_Pos) /**< \brief (DACC_TRIGR) Trigger Selection of Channel 1 */ +#define DACC_TRIGR_TRGSEL1(value) ((DACC_TRIGR_TRGSEL1_Msk & ((value) << DACC_TRIGR_TRGSEL1_Pos))) +#define DACC_TRIGR_TRGSEL1_TRGSEL0 (0x0u << 8) /**< \brief (DACC_TRIGR) DATRG */ +#define DACC_TRIGR_TRGSEL1_TRGSEL1 (0x1u << 8) /**< \brief (DACC_TRIGR) TC0 output */ +#define DACC_TRIGR_TRGSEL1_TRGSEL2 (0x2u << 8) /**< \brief (DACC_TRIGR) TC1 output */ +#define DACC_TRIGR_TRGSEL1_TRGSEL3 (0x3u << 8) /**< \brief (DACC_TRIGR) TC2 output */ +#define DACC_TRIGR_TRGSEL1_TRGSEL4 (0x4u << 8) /**< \brief (DACC_TRIGR) PWM0 event 0 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL5 (0x5u << 8) /**< \brief (DACC_TRIGR) PWM0 event 1 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL6 (0x6u << 8) /**< \brief (DACC_TRIGR) PWM1 event 0 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL7 (0x7u << 8) /**< \brief (DACC_TRIGR) PWM1 event 1 */ +#define DACC_TRIGR_OSR0_Pos 16 +#define DACC_TRIGR_OSR0_Msk (0x7u << DACC_TRIGR_OSR0_Pos) /**< \brief (DACC_TRIGR) Over Sampling Ratio of Channel 0 */ +#define DACC_TRIGR_OSR0(value) ((DACC_TRIGR_OSR0_Msk & ((value) << DACC_TRIGR_OSR0_Pos))) +#define DACC_TRIGR_OSR0_OSR_1 (0x0u << 16) /**< \brief (DACC_TRIGR) OSR = 1 */ +#define DACC_TRIGR_OSR0_OSR_2 (0x1u << 16) /**< \brief (DACC_TRIGR) OSR = 2 */ +#define DACC_TRIGR_OSR0_OSR_4 (0x2u << 16) /**< \brief (DACC_TRIGR) OSR = 4 */ +#define DACC_TRIGR_OSR0_OSR_8 (0x3u << 16) /**< \brief (DACC_TRIGR) OSR = 8 */ +#define DACC_TRIGR_OSR0_OSR_16 (0x4u << 16) /**< \brief (DACC_TRIGR) OSR = 16 */ +#define DACC_TRIGR_OSR0_OSR_32 (0x5u << 16) /**< \brief (DACC_TRIGR) OSR = 32 */ +#define DACC_TRIGR_OSR1_Pos 20 +#define DACC_TRIGR_OSR1_Msk (0x7u << DACC_TRIGR_OSR1_Pos) /**< \brief (DACC_TRIGR) Over Sampling Ratio of Channel 1 */ +#define DACC_TRIGR_OSR1(value) ((DACC_TRIGR_OSR1_Msk & ((value) << DACC_TRIGR_OSR1_Pos))) +#define DACC_TRIGR_OSR1_OSR_1 (0x0u << 20) /**< \brief (DACC_TRIGR) OSR = 1 */ +#define DACC_TRIGR_OSR1_OSR_2 (0x1u << 20) /**< \brief (DACC_TRIGR) OSR = 2 */ +#define DACC_TRIGR_OSR1_OSR_4 (0x2u << 20) /**< \brief (DACC_TRIGR) OSR = 4 */ +#define DACC_TRIGR_OSR1_OSR_8 (0x3u << 20) /**< \brief (DACC_TRIGR) OSR = 8 */ +#define DACC_TRIGR_OSR1_OSR_16 (0x4u << 20) /**< \brief (DACC_TRIGR) OSR = 16 */ +#define DACC_TRIGR_OSR1_OSR_32 (0x5u << 20) /**< \brief (DACC_TRIGR) OSR = 32 */ +/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */ +#define DACC_CHER_CH0 (0x1u << 0) /**< \brief (DACC_CHER) Channel 0 Enable */ +#define DACC_CHER_CH1 (0x1u << 1) /**< \brief (DACC_CHER) Channel 1 Enable */ +/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */ +#define DACC_CHDR_CH0 (0x1u << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */ +#define DACC_CHDR_CH1 (0x1u << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */ +/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */ +#define DACC_CHSR_CH0 (0x1u << 0) /**< \brief (DACC_CHSR) Channel 0 Status */ +#define DACC_CHSR_CH1 (0x1u << 1) /**< \brief (DACC_CHSR) Channel 1 Status */ +#define DACC_CHSR_DACRDY0 (0x1u << 8) /**< \brief (DACC_CHSR) DAC ready flag */ +#define DACC_CHSR_DACRDY1 (0x1u << 9) /**< \brief (DACC_CHSR) DAC ready flag */ +/* -------- DACC_CDR[2] : (DACC Offset: 0x1C) Conversion Data Register -------- */ +#define DACC_CDR_DATA0_Pos 0 +#define DACC_CDR_DATA0_Msk (0xffffu << DACC_CDR_DATA0_Pos) /**< \brief (DACC_CDR[2]) Data to Convert for channel 0 */ +#define DACC_CDR_DATA0(value) ((DACC_CDR_DATA0_Msk & ((value) << DACC_CDR_DATA0_Pos))) +#define DACC_CDR_DATA1_Pos 16 +#define DACC_CDR_DATA1_Msk (0xffffu << DACC_CDR_DATA1_Pos) /**< \brief (DACC_CDR[2]) Data to Convert for channel 1 */ +#define DACC_CDR_DATA1(value) ((DACC_CDR_DATA1_Msk & ((value) << DACC_CDR_DATA1_Pos))) +/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */ +#define DACC_IER_TXRDY0 (0x1u << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable of channel 0 */ +#define DACC_IER_TXRDY1 (0x1u << 1) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable of channel 1 */ +#define DACC_IER_EOC0 (0x1u << 4) /**< \brief (DACC_IER) End of Conversion Interrupt Enable of channel 0 */ +#define DACC_IER_EOC1 (0x1u << 5) /**< \brief (DACC_IER) End of Conversion Interrupt Enable of channel 1 */ +#define DACC_IER_ENDTX0 (0x1u << 8) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable of channel 0 */ +#define DACC_IER_ENDTX1 (0x1u << 9) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable of channel 1 */ +#define DACC_IER_TXBUFE0 (0x1u << 12) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable of channel 0 */ +#define DACC_IER_TXBUFE1 (0x1u << 13) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable of channel 1 */ +/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */ +#define DACC_IDR_TXRDY0 (0x1u << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable of channel 0 */ +#define DACC_IDR_TXRDY1 (0x1u << 1) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable of channel 1 */ +#define DACC_IDR_EOC0 (0x1u << 4) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable of channel 0 */ +#define DACC_IDR_EOC1 (0x1u << 5) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable of channel 1 */ +#define DACC_IDR_ENDTX0 (0x1u << 8) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable of channel 0 */ +#define DACC_IDR_ENDTX1 (0x1u << 9) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable of channel 1 */ +#define DACC_IDR_TXBUFE0 (0x1u << 12) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable of channel 0 */ +#define DACC_IDR_TXBUFE1 (0x1u << 13) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable of channel 1 */ +/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */ +#define DACC_IMR_TXRDY0 (0x1u << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask of channel 0 */ +#define DACC_IMR_TXRDY1 (0x1u << 1) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask of channel 1 */ +#define DACC_IMR_EOC0 (0x1u << 4) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask of channel 0 */ +#define DACC_IMR_EOC1 (0x1u << 5) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask of channel 1 */ +#define DACC_IMR_ENDTX0 (0x1u << 8) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask of channel 0 */ +#define DACC_IMR_ENDTX1 (0x1u << 9) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask of channel 1 */ +#define DACC_IMR_TXBUFE0 (0x1u << 12) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask of channel 0 */ +#define DACC_IMR_TXBUFE1 (0x1u << 13) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask of channel 1 */ +/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */ +#define DACC_ISR_TXRDY0 (0x1u << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag of channel 0 */ +#define DACC_ISR_TXRDY1 (0x1u << 1) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag of channel 1 */ +#define DACC_ISR_EOC0 (0x1u << 4) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag of channel 0 */ +#define DACC_ISR_EOC1 (0x1u << 5) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag of channel 1 */ +#define DACC_ISR_ENDTX0 (0x1u << 8) /**< \brief (DACC_ISR) End of DMA Interrupt Flag of channel 0 */ +#define DACC_ISR_ENDTX1 (0x1u << 9) /**< \brief (DACC_ISR) End of DMA Interrupt Flag of channel 1 */ +#define DACC_ISR_TXBUFE0 (0x1u << 12) /**< \brief (DACC_ISR) Transmit Buffer Empty of channel 0 */ +#define DACC_ISR_TXBUFE1 (0x1u << 13) /**< \brief (DACC_ISR) Transmit Buffer Empty of channel 1 */ +/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */ +#define DACC_ACR_IBCTLCH0_Pos 0 +#define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */ +#define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos))) +#define DACC_ACR_IBCTLCH1_Pos 2 +#define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */ +#define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos))) +/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protection Mode register -------- */ +#define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protection Enable */ +#define DACC_WPMR_WPKEY_Pos 8 +#define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect Key */ +#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos))) +#define DACC_WPMR_WPKEY_PASSWD (0x444143u << 8) /**< \brief (DACC_WPMR) Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0. */ +/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protection Status register -------- */ +#define DACC_WPSR_WPVS (0x1u << 0) /**< \brief (DACC_WPSR) Write Protection Violation Status */ +#define DACC_WPSR_WPVSRC_Pos 8 +#define DACC_WPSR_WPVSRC_Msk (0xffu << DACC_WPSR_WPVSRC_Pos) /**< \brief (DACC_WPSR) Write Protection Violation Source */ +/* -------- DACC_VERSION : (DACC Offset: 0xFC) Version Register -------- */ +#define DACC_VERSION_VERSION_Pos 0 +#define DACC_VERSION_VERSION_Msk (0xfffu << DACC_VERSION_VERSION_Pos) /**< \brief (DACC_VERSION) Version */ +#define DACC_VERSION_MFN_Pos 16 +#define DACC_VERSION_MFN_Msk (0x7u << DACC_VERSION_MFN_Pos) /**< \brief (DACC_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_DACC_COMPONENT_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/efc.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/efc.h new file mode 100644 index 000000000..34b7c70da --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/efc.h @@ -0,0 +1,123 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_EFC_COMPONENT_ +#define _SAME70_EFC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_EFC Embedded Flash Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Efc hardware registers */ +typedef struct { + __IO uint32_t EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */ + __O uint32_t EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */ + __I uint32_t EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */ + __I uint32_t EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */ + __I uint32_t Reserved1[1]; + __I uint32_t EEFC_VERSION; /**< \brief (Efc Offset: 0x14) EEFC Version Register */ + __I uint32_t Reserved2[51]; + __IO uint32_t EEFC_WPMR; /**< \brief (Efc Offset: 0xE4) Write Protection Mode Register */ +} Efc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */ +#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Flash Ready Interrupt Enable */ +#define EEFC_FMR_FWS_Pos 8 +#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */ +#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos))) +#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */ +#define EEFC_FMR_CLOE (0x1u << 26) /**< \brief (EEFC_FMR) Code Loop Optimization Enable */ +/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */ +#define EEFC_FCR_FCMD_Pos 0 +#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */ +#define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos))) +#define EEFC_FCR_FCMD_GETD (0x0u << 0) /**< \brief (EEFC_FCR) Get Flash descriptor */ +#define EEFC_FCR_FCMD_WP (0x1u << 0) /**< \brief (EEFC_FCR) Write page */ +#define EEFC_FCR_FCMD_WPL (0x2u << 0) /**< \brief (EEFC_FCR) Write page and lock */ +#define EEFC_FCR_FCMD_EWP (0x3u << 0) /**< \brief (EEFC_FCR) Erase page and write page */ +#define EEFC_FCR_FCMD_EWPL (0x4u << 0) /**< \brief (EEFC_FCR) Erase page and write page then lock */ +#define EEFC_FCR_FCMD_EA (0x5u << 0) /**< \brief (EEFC_FCR) Erase all */ +#define EEFC_FCR_FCMD_EPA (0x7u << 0) /**< \brief (EEFC_FCR) Erase pages */ +#define EEFC_FCR_FCMD_SLB (0x8u << 0) /**< \brief (EEFC_FCR) Set lock bit */ +#define EEFC_FCR_FCMD_CLB (0x9u << 0) /**< \brief (EEFC_FCR) Clear lock bit */ +#define EEFC_FCR_FCMD_GLB (0xAu << 0) /**< \brief (EEFC_FCR) Get lock bit */ +#define EEFC_FCR_FCMD_SGPB (0xBu << 0) /**< \brief (EEFC_FCR) Set GPNVM bit */ +#define EEFC_FCR_FCMD_CGPB (0xCu << 0) /**< \brief (EEFC_FCR) Clear GPNVM bit */ +#define EEFC_FCR_FCMD_GGPB (0xDu << 0) /**< \brief (EEFC_FCR) Get GPNVM bit */ +#define EEFC_FCR_FCMD_STUI (0xEu << 0) /**< \brief (EEFC_FCR) Start read unique identifier */ +#define EEFC_FCR_FCMD_SPUI (0xFu << 0) /**< \brief (EEFC_FCR) Stop read unique identifier */ +#define EEFC_FCR_FCMD_GCALB (0x10u << 0) /**< \brief (EEFC_FCR) Get CALIB bit */ +#define EEFC_FCR_FCMD_ES (0x11u << 0) /**< \brief (EEFC_FCR) Erase sector */ +#define EEFC_FCR_FCMD_WUS (0x12u << 0) /**< \brief (EEFC_FCR) Write user signature */ +#define EEFC_FCR_FCMD_EUS (0x13u << 0) /**< \brief (EEFC_FCR) Erase user signature */ +#define EEFC_FCR_FCMD_STUS (0x14u << 0) /**< \brief (EEFC_FCR) Start read user signature */ +#define EEFC_FCR_FCMD_SPUS (0x15u << 0) /**< \brief (EEFC_FCR) Stop read user signature */ +#define EEFC_FCR_FARG_Pos 8 +#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */ +#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos))) +#define EEFC_FCR_FKEY_Pos 24 +#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */ +#define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos))) +#define EEFC_FCR_FKEY_PASSWD (0x5Au << 24) /**< \brief (EEFC_FCR) The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. */ +/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */ +#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status (cleared when Flash is busy) */ +#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status (cleared on read or by writing EEFC_FCR) */ +#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status (cleared on read) */ +#define EEFC_FSR_FLERR (0x1u << 3) /**< \brief (EEFC_FSR) Flash Error Status (cleared when a programming operation starts) */ +#define EEFC_FSR_UECCELSB (0x1u << 16) /**< \brief (EEFC_FSR) Unique ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) */ +#define EEFC_FSR_MECCELSB (0x1u << 17) /**< \brief (EEFC_FSR) Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) */ +#define EEFC_FSR_UECCEMSB (0x1u << 18) /**< \brief (EEFC_FSR) Unique ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) */ +#define EEFC_FSR_MECCEMSB (0x1u << 19) /**< \brief (EEFC_FSR) Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) */ +/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */ +#define EEFC_FRR_FVALUE_Pos 0 +#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */ +/* -------- EEFC_VERSION : (EFC Offset: 0x14) EEFC Version Register -------- */ +#define EEFC_VERSION_VERSION_Pos 0 +#define EEFC_VERSION_VERSION_Msk (0xfffu << EEFC_VERSION_VERSION_Pos) /**< \brief (EEFC_VERSION) Version of the Hardware Module */ +#define EEFC_VERSION_MFN_Pos 16 +#define EEFC_VERSION_MFN_Msk (0x7u << EEFC_VERSION_MFN_Pos) /**< \brief (EEFC_VERSION) Metal Fix Number */ +/* -------- EEFC_WPMR : (EFC Offset: 0xE4) Write Protection Mode Register -------- */ +#define EEFC_WPMR_WPEN (0x1u << 0) /**< \brief (EEFC_WPMR) Write Protection Enable */ +#define EEFC_WPMR_WPKEY_Pos 8 +#define EEFC_WPMR_WPKEY_Msk (0xffffffu << EEFC_WPMR_WPKEY_Pos) /**< \brief (EEFC_WPMR) Write Protection Key */ +#define EEFC_WPMR_WPKEY(value) ((EEFC_WPMR_WPKEY_Msk & ((value) << EEFC_WPMR_WPKEY_Pos))) +#define EEFC_WPMR_WPKEY_PASSWD (0x454643u << 8) /**< \brief (EEFC_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAME70_EFC_COMPONENT_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/gmac.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/gmac.h new file mode 100644 index 000000000..7da341a00 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/gmac.h @@ -0,0 +1,1307 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_GMAC_COMPONENT_ +#define _SAME70_GMAC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Gigabit Ethernet MAC */ +/* ============================================================================= */ +/** \addtogroup SAME70_GMAC Gigabit Ethernet MAC */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief GmacSa hardware registers */ +typedef struct { + __IO uint32_t GMAC_SAB; /**< \brief (GmacSa Offset: 0x0) Specific Address 1 Bottom Register */ + __IO uint32_t GMAC_SAT; /**< \brief (GmacSa Offset: 0x4) Specific Address 1 Top Register */ +} GmacSa; +/** \brief Gmac hardware registers */ +#define GMACSA_NUMBER 4 +typedef struct { + __IO uint32_t GMAC_NCR; /**< \brief (Gmac Offset: 0x000) Network Control Register */ + __IO uint32_t GMAC_NCFGR; /**< \brief (Gmac Offset: 0x004) Network Configuration Register */ + __I uint32_t GMAC_NSR; /**< \brief (Gmac Offset: 0x008) Network Status Register */ + __IO uint32_t GMAC_UR; /**< \brief (Gmac Offset: 0x00C) User Register */ + __IO uint32_t GMAC_DCFGR; /**< \brief (Gmac Offset: 0x010) DMA Configuration Register */ + __IO uint32_t GMAC_TSR; /**< \brief (Gmac Offset: 0x014) Transmit Status Register */ + __IO uint32_t GMAC_RBQB; /**< \brief (Gmac Offset: 0x018) Receive Buffer Queue Base Address Register */ + __IO uint32_t GMAC_TBQB; /**< \brief (Gmac Offset: 0x01C) Transmit Buffer Queue Base Address Register */ + __IO uint32_t GMAC_RSR; /**< \brief (Gmac Offset: 0x020) Receive Status Register */ + __I uint32_t GMAC_ISR; /**< \brief (Gmac Offset: 0x024) Interrupt Status Register */ + __O uint32_t GMAC_IER; /**< \brief (Gmac Offset: 0x028) Interrupt Enable Register */ + __O uint32_t GMAC_IDR; /**< \brief (Gmac Offset: 0x02C) Interrupt Disable Register */ + __IO uint32_t GMAC_IMR; /**< \brief (Gmac Offset: 0x030) Interrupt Mask Register */ + __IO uint32_t GMAC_MAN; /**< \brief (Gmac Offset: 0x034) PHY Maintenance Register */ + __I uint32_t GMAC_RPQ; /**< \brief (Gmac Offset: 0x038) Received Pause Quantum Register */ + __IO uint32_t GMAC_TPQ; /**< \brief (Gmac Offset: 0x03C) Transmit Pause Quantum Register */ + __IO uint32_t GMAC_TPSF; /**< \brief (Gmac Offset: 0x040) TX Partial Store and Forward Register */ + __IO uint32_t GMAC_RPSF; /**< \brief (Gmac Offset: 0x044) RX Partial Store and Forward Register */ + __IO uint32_t GMAC_RJFML; /**< \brief (Gmac Offset: 0x048) RX Jumbo Frame Max Length Register */ + __I uint32_t Reserved1[13]; + __IO uint32_t GMAC_HRB; /**< \brief (Gmac Offset: 0x080) Hash Register Bottom */ + __IO uint32_t GMAC_HRT; /**< \brief (Gmac Offset: 0x084) Hash Register Top */ + GmacSa GMAC_SA[GMACSA_NUMBER]; /**< \brief (Gmac Offset: 0x088) 1 .. 4 */ + __IO uint32_t GMAC_TIDM1; /**< \brief (Gmac Offset: 0x0A8) Type ID Match 1 Register */ + __IO uint32_t GMAC_TIDM2; /**< \brief (Gmac Offset: 0x0AC) Type ID Match 2 Register */ + __IO uint32_t GMAC_TIDM3; /**< \brief (Gmac Offset: 0x0B0) Type ID Match 3 Register */ + __IO uint32_t GMAC_TIDM4; /**< \brief (Gmac Offset: 0x0B4) Type ID Match 4 Register */ + __IO uint32_t GMAC_WOL; /**< \brief (Gmac Offset: 0x0B8) Wake on LAN Register */ + __IO uint32_t GMAC_IPGS; /**< \brief (Gmac Offset: 0x0BC) IPG Stretch Register */ + __IO uint32_t GMAC_SVLAN; /**< \brief (Gmac Offset: 0x0C0) Stacked VLAN Register */ + __IO uint32_t GMAC_TPFCP; /**< \brief (Gmac Offset: 0x0C4) Transmit PFC Pause Register */ + __IO uint32_t GMAC_SAMB1; /**< \brief (Gmac Offset: 0x0C8) Specific Address 1 Mask Bottom Register */ + __IO uint32_t GMAC_SAMT1; /**< \brief (Gmac Offset: 0x0CC) Specific Address 1 Mask Top Register */ + __I uint32_t Reserved2[3]; + __IO uint32_t GMAC_NSC; /**< \brief (Gmac Offset: 0x0DC) 1588 Timer Nanosecond Comparison Register */ + __IO uint32_t GMAC_SCL; /**< \brief (Gmac Offset: 0x0E0) 1588 Timer Second Comparison Low Register */ + __IO uint32_t GMAC_SCH; /**< \brief (Gmac Offset: 0x0E4) 1588 Timer Second Comparison High Register */ + __I uint32_t GMAC_EFTSH; /**< \brief (Gmac Offset: 0x0E8) PTP Event Frame Transmitted Seconds High Register */ + __I uint32_t GMAC_EFRSH; /**< \brief (Gmac Offset: 0x0EC) PTP Event Frame Received Seconds High Register */ + __I uint32_t GMAC_PEFTSH; /**< \brief (Gmac Offset: 0x0F0) PTP Peer Event Frame Transmitted Seconds High Register */ + __I uint32_t GMAC_PEFRSH; /**< \brief (Gmac Offset: 0x0F4) PTP Peer Event Frame Received Seconds High Register */ + __I uint32_t Reserved3[1]; + __I uint32_t GMAC_MID; /**< \brief (Gmac Offset: 0x0FC) Module ID Register */ + __I uint32_t GMAC_OTLO; /**< \brief (Gmac Offset: 0x100) Octets Transmitted Low Register */ + __I uint32_t GMAC_OTHI; /**< \brief (Gmac Offset: 0x104) Octets Transmitted High Register */ + __I uint32_t GMAC_FT; /**< \brief (Gmac Offset: 0x108) Frames Transmitted Register */ + __I uint32_t GMAC_BCFT; /**< \brief (Gmac Offset: 0x10C) Broadcast Frames Transmitted Register */ + __I uint32_t GMAC_MFT; /**< \brief (Gmac Offset: 0x110) Multicast Frames Transmitted Register */ + __I uint32_t GMAC_PFT; /**< \brief (Gmac Offset: 0x114) Pause Frames Transmitted Register */ + __I uint32_t GMAC_BFT64; /**< \brief (Gmac Offset: 0x118) 64 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT127; /**< \brief (Gmac Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT255; /**< \brief (Gmac Offset: 0x120) 128 to 255 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT511; /**< \brief (Gmac Offset: 0x124) 256 to 511 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT1023; /**< \brief (Gmac Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT1518; /**< \brief (Gmac Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register */ + __I uint32_t GMAC_GTBFT1518; /**< \brief (Gmac Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TUR; /**< \brief (Gmac Offset: 0x134) Transmit Underruns Register */ + __I uint32_t GMAC_SCF; /**< \brief (Gmac Offset: 0x138) Single Collision Frames Register */ + __I uint32_t GMAC_MCF; /**< \brief (Gmac Offset: 0x13C) Multiple Collision Frames Register */ + __I uint32_t GMAC_EC; /**< \brief (Gmac Offset: 0x140) Excessive Collisions Register */ + __I uint32_t GMAC_LC; /**< \brief (Gmac Offset: 0x144) Late Collisions Register */ + __I uint32_t GMAC_DTF; /**< \brief (Gmac Offset: 0x148) Deferred Transmission Frames Register */ + __I uint32_t GMAC_CSE; /**< \brief (Gmac Offset: 0x14C) Carrier Sense Errors Register */ + __I uint32_t GMAC_ORLO; /**< \brief (Gmac Offset: 0x150) Octets Received Low Received Register */ + __I uint32_t GMAC_ORHI; /**< \brief (Gmac Offset: 0x154) Octets Received High Received Register */ + __I uint32_t GMAC_FR; /**< \brief (Gmac Offset: 0x158) Frames Received Register */ + __I uint32_t GMAC_BCFR; /**< \brief (Gmac Offset: 0x15C) Broadcast Frames Received Register */ + __I uint32_t GMAC_MFR; /**< \brief (Gmac Offset: 0x160) Multicast Frames Received Register */ + __I uint32_t GMAC_PFR; /**< \brief (Gmac Offset: 0x164) Pause Frames Received Register */ + __I uint32_t GMAC_BFR64; /**< \brief (Gmac Offset: 0x168) 64 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR127; /**< \brief (Gmac Offset: 0x16C) 65 to 127 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR255; /**< \brief (Gmac Offset: 0x170) 128 to 255 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR511; /**< \brief (Gmac Offset: 0x174) 256 to 511 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR1023; /**< \brief (Gmac Offset: 0x178) 512 to 1023 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR1518; /**< \brief (Gmac Offset: 0x17C) 1024 to 1518 Byte Frames Received Register */ + __I uint32_t GMAC_TMXBFR; /**< \brief (Gmac Offset: 0x180) 1519 to Maximum Byte Frames Received Register */ + __I uint32_t GMAC_UFR; /**< \brief (Gmac Offset: 0x184) Undersize Frames Received Register */ + __I uint32_t GMAC_OFR; /**< \brief (Gmac Offset: 0x188) Oversize Frames Received Register */ + __I uint32_t GMAC_JR; /**< \brief (Gmac Offset: 0x18C) Jabbers Received Register */ + __I uint32_t GMAC_FCSE; /**< \brief (Gmac Offset: 0x190) Frame Check Sequence Errors Register */ + __I uint32_t GMAC_LFFE; /**< \brief (Gmac Offset: 0x194) Length Field Frame Errors Register */ + __I uint32_t GMAC_RSE; /**< \brief (Gmac Offset: 0x198) Receive Symbol Errors Register */ + __I uint32_t GMAC_AE; /**< \brief (Gmac Offset: 0x19C) Alignment Errors Register */ + __I uint32_t GMAC_RRE; /**< \brief (Gmac Offset: 0x1A0) Receive Resource Errors Register */ + __I uint32_t GMAC_ROE; /**< \brief (Gmac Offset: 0x1A4) Receive Overrun Register */ + __I uint32_t GMAC_IHCE; /**< \brief (Gmac Offset: 0x1A8) IP Header Checksum Errors Register */ + __I uint32_t GMAC_TCE; /**< \brief (Gmac Offset: 0x1AC) TCP Checksum Errors Register */ + __I uint32_t GMAC_UCE; /**< \brief (Gmac Offset: 0x1B0) UDP Checksum Errors Register */ + __I uint32_t Reserved4[2]; + __IO uint32_t GMAC_TISUBN; /**< \brief (Gmac Offset: 0x1BC) 1588 Timer Increment Sub-nanoseconds Register */ + __IO uint32_t GMAC_TSH; /**< \brief (Gmac Offset: 0x1C0) 1588 Timer Seconds High Register */ + __I uint32_t Reserved5[3]; + __IO uint32_t GMAC_TSL; /**< \brief (Gmac Offset: 0x1D0) 1588 Timer Seconds Low Register */ + __IO uint32_t GMAC_TN; /**< \brief (Gmac Offset: 0x1D4) 1588 Timer Nanoseconds Register */ + __O uint32_t GMAC_TA; /**< \brief (Gmac Offset: 0x1D8) 1588 Timer Adjust Register */ + __IO uint32_t GMAC_TI; /**< \brief (Gmac Offset: 0x1DC) 1588 Timer Increment Register */ + __I uint32_t GMAC_EFTSL; /**< \brief (Gmac Offset: 0x1E0) PTP Event Frame Transmitted Seconds Low Register */ + __I uint32_t GMAC_EFTN; /**< \brief (Gmac Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds Register */ + __I uint32_t GMAC_EFRSL; /**< \brief (Gmac Offset: 0x1E8) PTP Event Frame Received Seconds Low Register */ + __I uint32_t GMAC_EFRN; /**< \brief (Gmac Offset: 0x1EC) PTP Event Frame Received Nanoseconds Register */ + __I uint32_t GMAC_PEFTSL; /**< \brief (Gmac Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds Low Register */ + __I uint32_t GMAC_PEFTN; /**< \brief (Gmac Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds Register */ + __I uint32_t GMAC_PEFRSL; /**< \brief (Gmac Offset: 0x1F8) PTP Peer Event Frame Received Seconds Low Register */ + __I uint32_t GMAC_PEFRN; /**< \brief (Gmac Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds Register */ + __I uint32_t Reserved6[28]; + __I uint32_t GMAC_RXLPI; /**< \brief (Gmac Offset: 0x270) Received LPI Transitions */ + __I uint32_t GMAC_RXLPITIME; /**< \brief (Gmac Offset: 0x274) Received LPI Time */ + __I uint32_t GMAC_TXLPI; /**< \brief (Gmac Offset: 0x278) Transmit LPI Transitions */ + __I uint32_t GMAC_TXLPITIME; /**< \brief (Gmac Offset: 0x27C) Transmit LPI Time */ + __I uint32_t Reserved7[96]; + __I uint32_t GMAC_ISRPQ[5]; /**< \brief (Gmac Offset: 0x400) Interrupt Status Register Priority Queue (index = 1) */ + __I uint32_t Reserved8[11]; + __IO uint32_t GMAC_TBQBAPQ[5]; /**< \brief (Gmac Offset: 0x440) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) */ + __I uint32_t Reserved9[11]; + __IO uint32_t GMAC_RBQBAPQ[5]; /**< \brief (Gmac Offset: 0x480) Receive Buffer Queue Base Address Register Priority Queue (index = 1) */ + __I uint32_t Reserved10[3]; + __IO uint32_t GMAC_RBSRPQ[5]; /**< \brief (Gmac Offset: 0x4A0) Receive Buffer Size Register Priority Queue (index = 1) */ + __I uint32_t Reserved11[2]; + __IO uint32_t GMAC_CBSCR; /**< \brief (Gmac Offset: 0x4BC) Credit-Based Shaping Control Register */ + __IO uint32_t GMAC_CBSISQA; /**< \brief (Gmac Offset: 0x4C0) Credit-Based Shaping IdleSlope Register for Queue A */ + __IO uint32_t GMAC_CBSISQB; /**< \brief (Gmac Offset: 0x4C4) Credit-Based Shaping IdleSlope Register for Queue B */ + __I uint32_t Reserved12[14]; + __IO uint32_t GMAC_ST1RPQ[4]; /**< \brief (Gmac Offset: 0x500) Screening Type 1 Register Priority Queue (index = 0) */ + __I uint32_t Reserved13[12]; + __IO uint32_t GMAC_ST2RPQ[8]; /**< \brief (Gmac Offset: 0x540) Screening Type 2 Register Priority Queue (index = 0) */ + __I uint32_t Reserved14[39]; + __O uint32_t GMAC_IERPQ[5]; /**< \brief (Gmac Offset: 0x5FC) Interrupt Enable Register Priority Queue (index = 1) */ + __I uint32_t Reserved15[3]; + __O uint32_t GMAC_IDRPQ[5]; /**< \brief (Gmac Offset: 0x61C) Interrupt Disable Register Priority Queue (index = 1) */ + __I uint32_t Reserved16[3]; + __IO uint32_t GMAC_IMRPQ[5]; /**< \brief (Gmac Offset: 0x63C) Interrupt Mask Register Priority Queue (index = 1) */ + __I uint32_t Reserved17[36]; + __IO uint32_t GMAC_ST2ER[4]; /**< \brief (Gmac Offset: 0x6E0) Screening Type 2 Ethertype Register (index = 0) */ + __I uint32_t Reserved18[4]; + __IO uint32_t GMAC_ST2CW00; /**< \brief (Gmac Offset: 0x700) Screening Type 2 Compare Word 0 Register (index = 0) */ + __IO uint32_t GMAC_ST2CW10; /**< \brief (Gmac Offset: 0x704) Screening Type 2 Compare Word 1 Register (index = 0) */ + __IO uint32_t GMAC_ST2CW01; /**< \brief (Gmac Offset: 0x708) Screening Type 2 Compare Word 0 Register (index = 1) */ + __IO uint32_t GMAC_ST2CW11; /**< \brief (Gmac Offset: 0x70C) Screening Type 2 Compare Word 1 Register (index = 1) */ + __IO uint32_t GMAC_ST2CW02; /**< \brief (Gmac Offset: 0x710) Screening Type 2 Compare Word 0 Register (index = 2) */ + __IO uint32_t GMAC_ST2CW12; /**< \brief (Gmac Offset: 0x714) Screening Type 2 Compare Word 1 Register (index = 2) */ + __IO uint32_t GMAC_ST2CW03; /**< \brief (Gmac Offset: 0x718) Screening Type 2 Compare Word 0 Register (index = 3) */ + __IO uint32_t GMAC_ST2CW13; /**< \brief (Gmac Offset: 0x71C) Screening Type 2 Compare Word 1 Register (index = 3) */ + __IO uint32_t GMAC_ST2CW04; /**< \brief (Gmac Offset: 0x720) Screening Type 2 Compare Word 0 Register (index = 4) */ + __IO uint32_t GMAC_ST2CW14; /**< \brief (Gmac Offset: 0x724) Screening Type 2 Compare Word 1 Register (index = 4) */ + __IO uint32_t GMAC_ST2CW05; /**< \brief (Gmac Offset: 0x728) Screening Type 2 Compare Word 0 Register (index = 5) */ + __IO uint32_t GMAC_ST2CW15; /**< \brief (Gmac Offset: 0x72C) Screening Type 2 Compare Word 1 Register (index = 5) */ + __IO uint32_t GMAC_ST2CW06; /**< \brief (Gmac Offset: 0x730) Screening Type 2 Compare Word 0 Register (index = 6) */ + __IO uint32_t GMAC_ST2CW16; /**< \brief (Gmac Offset: 0x734) Screening Type 2 Compare Word 1 Register (index = 6) */ + __IO uint32_t GMAC_ST2CW07; /**< \brief (Gmac Offset: 0x738) Screening Type 2 Compare Word 0 Register (index = 7) */ + __IO uint32_t GMAC_ST2CW17; /**< \brief (Gmac Offset: 0x73C) Screening Type 2 Compare Word 1 Register (index = 7) */ + __IO uint32_t GMAC_ST2CW08; /**< \brief (Gmac Offset: 0x740) Screening Type 2 Compare Word 0 Register (index = 8) */ + __IO uint32_t GMAC_ST2CW18; /**< \brief (Gmac Offset: 0x744) Screening Type 2 Compare Word 1 Register (index = 8) */ + __IO uint32_t GMAC_ST2CW09; /**< \brief (Gmac Offset: 0x748) Screening Type 2 Compare Word 0 Register (index = 9) */ + __IO uint32_t GMAC_ST2CW19; /**< \brief (Gmac Offset: 0x74C) Screening Type 2 Compare Word 1 Register (index = 9) */ + __IO uint32_t GMAC_ST2CW010; /**< \brief (Gmac Offset: 0x750) Screening Type 2 Compare Word 0 Register (index = 10) */ + __IO uint32_t GMAC_ST2CW110; /**< \brief (Gmac Offset: 0x754) Screening Type 2 Compare Word 1 Register (index = 10) */ + __IO uint32_t GMAC_ST2CW011; /**< \brief (Gmac Offset: 0x758) Screening Type 2 Compare Word 0 Register (index = 11) */ + __IO uint32_t GMAC_ST2CW111; /**< \brief (Gmac Offset: 0x75C) Screening Type 2 Compare Word 1 Register (index = 11) */ + __IO uint32_t GMAC_ST2CW012; /**< \brief (Gmac Offset: 0x760) Screening Type 2 Compare Word 0 Register (index = 12) */ + __IO uint32_t GMAC_ST2CW112; /**< \brief (Gmac Offset: 0x764) Screening Type 2 Compare Word 1 Register (index = 12) */ + __IO uint32_t GMAC_ST2CW013; /**< \brief (Gmac Offset: 0x768) Screening Type 2 Compare Word 0 Register (index = 13) */ + __IO uint32_t GMAC_ST2CW113; /**< \brief (Gmac Offset: 0x76C) Screening Type 2 Compare Word 1 Register (index = 13) */ + __IO uint32_t GMAC_ST2CW014; /**< \brief (Gmac Offset: 0x770) Screening Type 2 Compare Word 0 Register (index = 14) */ + __IO uint32_t GMAC_ST2CW114; /**< \brief (Gmac Offset: 0x774) Screening Type 2 Compare Word 1 Register (index = 14) */ + __IO uint32_t GMAC_ST2CW015; /**< \brief (Gmac Offset: 0x778) Screening Type 2 Compare Word 0 Register (index = 15) */ + __IO uint32_t GMAC_ST2CW115; /**< \brief (Gmac Offset: 0x77C) Screening Type 2 Compare Word 1 Register (index = 15) */ + __IO uint32_t GMAC_ST2CW016; /**< \brief (Gmac Offset: 0x780) Screening Type 2 Compare Word 0 Register (index = 16) */ + __IO uint32_t GMAC_ST2CW116; /**< \brief (Gmac Offset: 0x784) Screening Type 2 Compare Word 1 Register (index = 16) */ + __IO uint32_t GMAC_ST2CW017; /**< \brief (Gmac Offset: 0x788) Screening Type 2 Compare Word 0 Register (index = 17) */ + __IO uint32_t GMAC_ST2CW117; /**< \brief (Gmac Offset: 0x78C) Screening Type 2 Compare Word 1 Register (index = 17) */ + __IO uint32_t GMAC_ST2CW018; /**< \brief (Gmac Offset: 0x790) Screening Type 2 Compare Word 0 Register (index = 18) */ + __IO uint32_t GMAC_ST2CW118; /**< \brief (Gmac Offset: 0x794) Screening Type 2 Compare Word 1 Register (index = 18) */ + __IO uint32_t GMAC_ST2CW019; /**< \brief (Gmac Offset: 0x798) Screening Type 2 Compare Word 0 Register (index = 19) */ + __IO uint32_t GMAC_ST2CW119; /**< \brief (Gmac Offset: 0x79C) Screening Type 2 Compare Word 1 Register (index = 19) */ + __IO uint32_t GMAC_ST2CW020; /**< \brief (Gmac Offset: 0x7A0) Screening Type 2 Compare Word 0 Register (index = 20) */ + __IO uint32_t GMAC_ST2CW120; /**< \brief (Gmac Offset: 0x7A4) Screening Type 2 Compare Word 1 Register (index = 20) */ + __IO uint32_t GMAC_ST2CW021; /**< \brief (Gmac Offset: 0x7A8) Screening Type 2 Compare Word 0 Register (index = 21) */ + __IO uint32_t GMAC_ST2CW121; /**< \brief (Gmac Offset: 0x7AC) Screening Type 2 Compare Word 1 Register (index = 21) */ + __IO uint32_t GMAC_ST2CW022; /**< \brief (Gmac Offset: 0x7B0) Screening Type 2 Compare Word 0 Register (index = 22) */ + __IO uint32_t GMAC_ST2CW122; /**< \brief (Gmac Offset: 0x7B4) Screening Type 2 Compare Word 1 Register (index = 22) */ + __IO uint32_t GMAC_ST2CW023; /**< \brief (Gmac Offset: 0x7B8) Screening Type 2 Compare Word 0 Register (index = 23) */ + __IO uint32_t GMAC_ST2CW123; /**< \brief (Gmac Offset: 0x7BC) Screening Type 2 Compare Word 1 Register (index = 23) */ +} Gmac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- GMAC_NCR : (GMAC Offset: 0x000) Network Control Register -------- */ +#define GMAC_NCR_LBL (0x1u << 1) /**< \brief (GMAC_NCR) Loop Back Local */ +#define GMAC_NCR_RXEN (0x1u << 2) /**< \brief (GMAC_NCR) Receive Enable */ +#define GMAC_NCR_TXEN (0x1u << 3) /**< \brief (GMAC_NCR) Transmit Enable */ +#define GMAC_NCR_MPE (0x1u << 4) /**< \brief (GMAC_NCR) Management Port Enable */ +#define GMAC_NCR_CLRSTAT (0x1u << 5) /**< \brief (GMAC_NCR) Clear Statistics Registers */ +#define GMAC_NCR_INCSTAT (0x1u << 6) /**< \brief (GMAC_NCR) Increment Statistics Registers */ +#define GMAC_NCR_WESTAT (0x1u << 7) /**< \brief (GMAC_NCR) Write Enable for Statistics Registers */ +#define GMAC_NCR_BP (0x1u << 8) /**< \brief (GMAC_NCR) Back pressure */ +#define GMAC_NCR_TSTART (0x1u << 9) /**< \brief (GMAC_NCR) Start Transmission */ +#define GMAC_NCR_THALT (0x1u << 10) /**< \brief (GMAC_NCR) Transmit Halt */ +#define GMAC_NCR_TXPF (0x1u << 11) /**< \brief (GMAC_NCR) Transmit Pause Frame */ +#define GMAC_NCR_TXZQPF (0x1u << 12) /**< \brief (GMAC_NCR) Transmit Zero Quantum Pause Frame */ +#define GMAC_NCR_SRTSM (0x1u << 15) /**< \brief (GMAC_NCR) Store Receive Time Stamp to Memory */ +#define GMAC_NCR_ENPBPR (0x1u << 16) /**< \brief (GMAC_NCR) Enable PFC Priority-based Pause Reception */ +#define GMAC_NCR_TXPBPF (0x1u << 17) /**< \brief (GMAC_NCR) Transmit PFC Priority-based Pause Frame */ +#define GMAC_NCR_FNP (0x1u << 18) /**< \brief (GMAC_NCR) Flush Next Packet */ +/* -------- GMAC_NCFGR : (GMAC Offset: 0x004) Network Configuration Register -------- */ +#define GMAC_NCFGR_SPD (0x1u << 0) /**< \brief (GMAC_NCFGR) Speed */ +#define GMAC_NCFGR_FD (0x1u << 1) /**< \brief (GMAC_NCFGR) Full Duplex */ +#define GMAC_NCFGR_DNVLAN (0x1u << 2) /**< \brief (GMAC_NCFGR) Discard Non-VLAN FRAMES */ +#define GMAC_NCFGR_JFRAME (0x1u << 3) /**< \brief (GMAC_NCFGR) Jumbo Frame Size */ +#define GMAC_NCFGR_CAF (0x1u << 4) /**< \brief (GMAC_NCFGR) Copy All Frames */ +#define GMAC_NCFGR_NBC (0x1u << 5) /**< \brief (GMAC_NCFGR) No Broadcast */ +#define GMAC_NCFGR_MTIHEN (0x1u << 6) /**< \brief (GMAC_NCFGR) Multicast Hash Enable */ +#define GMAC_NCFGR_UNIHEN (0x1u << 7) /**< \brief (GMAC_NCFGR) Unicast Hash Enable */ +#define GMAC_NCFGR_MAXFS (0x1u << 8) /**< \brief (GMAC_NCFGR) 1536 Maximum Frame Size */ +#define GMAC_NCFGR_RTY (0x1u << 12) /**< \brief (GMAC_NCFGR) Retry Test */ +#define GMAC_NCFGR_PEN (0x1u << 13) /**< \brief (GMAC_NCFGR) Pause Enable */ +#define GMAC_NCFGR_RXBUFO_Pos 14 +#define GMAC_NCFGR_RXBUFO_Msk (0x3u << GMAC_NCFGR_RXBUFO_Pos) /**< \brief (GMAC_NCFGR) Receive Buffer Offset */ +#define GMAC_NCFGR_RXBUFO(value) ((GMAC_NCFGR_RXBUFO_Msk & ((value) << GMAC_NCFGR_RXBUFO_Pos))) +#define GMAC_NCFGR_LFERD (0x1u << 16) /**< \brief (GMAC_NCFGR) Length Field Error Frame Discard */ +#define GMAC_NCFGR_RFCS (0x1u << 17) /**< \brief (GMAC_NCFGR) Remove FCS */ +#define GMAC_NCFGR_CLK_Pos 18 +#define GMAC_NCFGR_CLK_Msk (0x7u << GMAC_NCFGR_CLK_Pos) /**< \brief (GMAC_NCFGR) MDC CLock Division */ +#define GMAC_NCFGR_CLK(value) ((GMAC_NCFGR_CLK_Msk & ((value) << GMAC_NCFGR_CLK_Pos))) +#define GMAC_NCFGR_CLK_MCK_8 (0x0u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 8 (MCK up to 20 MHz) */ +#define GMAC_NCFGR_CLK_MCK_16 (0x1u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 16 (MCK up to 40 MHz) */ +#define GMAC_NCFGR_CLK_MCK_32 (0x2u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 32 (MCK up to 80 MHz) */ +#define GMAC_NCFGR_CLK_MCK_48 (0x3u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 48 (MCK up to 120 MHz) */ +#define GMAC_NCFGR_CLK_MCK_64 (0x4u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 64 (MCK up to 160 MHz) */ +#define GMAC_NCFGR_CLK_MCK_96 (0x5u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 96 (MCK up to 240 MHz) */ +#define GMAC_NCFGR_DBW_Pos 21 +#define GMAC_NCFGR_DBW_Msk (0x3u << GMAC_NCFGR_DBW_Pos) /**< \brief (GMAC_NCFGR) Data Bus Width */ +#define GMAC_NCFGR_DBW(value) ((GMAC_NCFGR_DBW_Msk & ((value) << GMAC_NCFGR_DBW_Pos))) +#define GMAC_NCFGR_DCPF (0x1u << 23) /**< \brief (GMAC_NCFGR) Disable Copy of Pause Frames */ +#define GMAC_NCFGR_RXCOEN (0x1u << 24) /**< \brief (GMAC_NCFGR) Receive Checksum Offload Enable */ +#define GMAC_NCFGR_EFRHD (0x1u << 25) /**< \brief (GMAC_NCFGR) Enable Frames Received in Half Duplex */ +#define GMAC_NCFGR_IRXFCS (0x1u << 26) /**< \brief (GMAC_NCFGR) Ignore RX FCS */ +#define GMAC_NCFGR_IPGSEN (0x1u << 28) /**< \brief (GMAC_NCFGR) IP Stretch Enable */ +#define GMAC_NCFGR_RXBP (0x1u << 29) /**< \brief (GMAC_NCFGR) Receive Bad Preamble */ +#define GMAC_NCFGR_IRXER (0x1u << 30) /**< \brief (GMAC_NCFGR) Ignore IPG GRXER */ +/* -------- GMAC_NSR : (GMAC Offset: 0x008) Network Status Register -------- */ +#define GMAC_NSR_MDIO (0x1u << 1) /**< \brief (GMAC_NSR) MDIO Input Status */ +#define GMAC_NSR_IDLE (0x1u << 2) /**< \brief (GMAC_NSR) PHY Management Logic Idle */ +/* -------- GMAC_UR : (GMAC Offset: 0x00C) User Register -------- */ +#define GMAC_UR_RMII (0x1u << 0) /**< \brief (GMAC_UR) Reduced MII Mode */ +/* -------- GMAC_DCFGR : (GMAC Offset: 0x010) DMA Configuration Register -------- */ +#define GMAC_DCFGR_FBLDO_Pos 0 +#define GMAC_DCFGR_FBLDO_Msk (0x1fu << GMAC_DCFGR_FBLDO_Pos) /**< \brief (GMAC_DCFGR) Fixed Burst Length for DMA Data Operations: */ +#define GMAC_DCFGR_FBLDO(value) ((GMAC_DCFGR_FBLDO_Msk & ((value) << GMAC_DCFGR_FBLDO_Pos))) +#define GMAC_DCFGR_FBLDO_SINGLE (0x1u << 0) /**< \brief (GMAC_DCFGR) 00001: Always use SINGLE AHB bursts */ +#define GMAC_DCFGR_FBLDO_INCR4 (0x4u << 0) /**< \brief (GMAC_DCFGR) 001xx: Attempt to use INCR4 AHB bursts (Default) */ +#define GMAC_DCFGR_FBLDO_INCR8 (0x8u << 0) /**< \brief (GMAC_DCFGR) 01xxx: Attempt to use INCR8 AHB bursts */ +#define GMAC_DCFGR_FBLDO_INCR16 (0x10u << 0) /**< \brief (GMAC_DCFGR) 1xxxx: Attempt to use INCR16 AHB bursts */ +#define GMAC_DCFGR_ESMA (0x1u << 6) /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Management Descriptor Accesses */ +#define GMAC_DCFGR_ESPA (0x1u << 7) /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Packet Data Accesses */ +#define GMAC_DCFGR_RXBMS_Pos 8 +#define GMAC_DCFGR_RXBMS_Msk (0x3u << GMAC_DCFGR_RXBMS_Pos) /**< \brief (GMAC_DCFGR) Receiver Packet Buffer Memory Size Select */ +#define GMAC_DCFGR_RXBMS(value) ((GMAC_DCFGR_RXBMS_Msk & ((value) << GMAC_DCFGR_RXBMS_Pos))) +#define GMAC_DCFGR_RXBMS_EIGHTH (0x0u << 8) /**< \brief (GMAC_DCFGR) 4/8 Kbyte Memory Size */ +#define GMAC_DCFGR_RXBMS_QUARTER (0x1u << 8) /**< \brief (GMAC_DCFGR) 4/4 Kbytes Memory Size */ +#define GMAC_DCFGR_RXBMS_HALF (0x2u << 8) /**< \brief (GMAC_DCFGR) 4/2 Kbytes Memory Size */ +#define GMAC_DCFGR_RXBMS_FULL (0x3u << 8) /**< \brief (GMAC_DCFGR) 4 Kbytes Memory Size */ +#define GMAC_DCFGR_TXPBMS (0x1u << 10) /**< \brief (GMAC_DCFGR) Transmitter Packet Buffer Memory Size Select */ +#define GMAC_DCFGR_TXCOEN (0x1u << 11) /**< \brief (GMAC_DCFGR) Transmitter Checksum Generation Offload Enable */ +#define GMAC_DCFGR_DRBS_Pos 16 +#define GMAC_DCFGR_DRBS_Msk (0xffu << GMAC_DCFGR_DRBS_Pos) /**< \brief (GMAC_DCFGR) DMA Receive Buffer Size */ +#define GMAC_DCFGR_DRBS(value) ((GMAC_DCFGR_DRBS_Msk & ((value) << GMAC_DCFGR_DRBS_Pos))) +#define GMAC_DCFGR_DDRP (0x1u << 24) /**< \brief (GMAC_DCFGR) DMA Discard Receive Packets */ +/* -------- GMAC_TSR : (GMAC Offset: 0x014) Transmit Status Register -------- */ +#define GMAC_TSR_UBR (0x1u << 0) /**< \brief (GMAC_TSR) Used Bit Read */ +#define GMAC_TSR_COL (0x1u << 1) /**< \brief (GMAC_TSR) Collision Occurred */ +#define GMAC_TSR_RLE (0x1u << 2) /**< \brief (GMAC_TSR) Retry Limit Exceeded */ +#define GMAC_TSR_TXGO (0x1u << 3) /**< \brief (GMAC_TSR) Transmit Go */ +#define GMAC_TSR_TFC (0x1u << 4) /**< \brief (GMAC_TSR) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_TSR_TXCOMP (0x1u << 5) /**< \brief (GMAC_TSR) Transmit Complete */ +#define GMAC_TSR_HRESP (0x1u << 8) /**< \brief (GMAC_TSR) HRESP Not OK */ +/* -------- GMAC_RBQB : (GMAC Offset: 0x018) Receive Buffer Queue Base Address Register -------- */ +#define GMAC_RBQB_ADDR_Pos 2 +#define GMAC_RBQB_ADDR_Msk (0x3fffffffu << GMAC_RBQB_ADDR_Pos) /**< \brief (GMAC_RBQB) Receive Buffer Queue Base Address */ +#define GMAC_RBQB_ADDR(value) ((GMAC_RBQB_ADDR_Msk & ((value) << GMAC_RBQB_ADDR_Pos))) +/* -------- GMAC_TBQB : (GMAC Offset: 0x01C) Transmit Buffer Queue Base Address Register -------- */ +#define GMAC_TBQB_ADDR_Pos 2 +#define GMAC_TBQB_ADDR_Msk (0x3fffffffu << GMAC_TBQB_ADDR_Pos) /**< \brief (GMAC_TBQB) Transmit Buffer Queue Base Address */ +#define GMAC_TBQB_ADDR(value) ((GMAC_TBQB_ADDR_Msk & ((value) << GMAC_TBQB_ADDR_Pos))) +/* -------- GMAC_RSR : (GMAC Offset: 0x020) Receive Status Register -------- */ +#define GMAC_RSR_BNA (0x1u << 0) /**< \brief (GMAC_RSR) Buffer Not Available */ +#define GMAC_RSR_REC (0x1u << 1) /**< \brief (GMAC_RSR) Frame Received */ +#define GMAC_RSR_RXOVR (0x1u << 2) /**< \brief (GMAC_RSR) Receive Overrun */ +#define GMAC_RSR_HNO (0x1u << 3) /**< \brief (GMAC_RSR) HRESP Not OK */ +/* -------- GMAC_ISR : (GMAC Offset: 0x024) Interrupt Status Register -------- */ +#define GMAC_ISR_MFS (0x1u << 0) /**< \brief (GMAC_ISR) Management Frame Sent */ +#define GMAC_ISR_RCOMP (0x1u << 1) /**< \brief (GMAC_ISR) Receive Complete */ +#define GMAC_ISR_RXUBR (0x1u << 2) /**< \brief (GMAC_ISR) RX Used Bit Read */ +#define GMAC_ISR_TXUBR (0x1u << 3) /**< \brief (GMAC_ISR) TX Used Bit Read */ +#define GMAC_ISR_TUR (0x1u << 4) /**< \brief (GMAC_ISR) Transmit Underrun */ +#define GMAC_ISR_RLEX (0x1u << 5) /**< \brief (GMAC_ISR) Retry Limit Exceeded */ +#define GMAC_ISR_TFC (0x1u << 6) /**< \brief (GMAC_ISR) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_ISR_TCOMP (0x1u << 7) /**< \brief (GMAC_ISR) Transmit Complete */ +#define GMAC_ISR_ROVR (0x1u << 10) /**< \brief (GMAC_ISR) Receive Overrun */ +#define GMAC_ISR_HRESP (0x1u << 11) /**< \brief (GMAC_ISR) HRESP Not OK */ +#define GMAC_ISR_PFNZ (0x1u << 12) /**< \brief (GMAC_ISR) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_ISR_PTZ (0x1u << 13) /**< \brief (GMAC_ISR) Pause Time Zero */ +#define GMAC_ISR_PFTR (0x1u << 14) /**< \brief (GMAC_ISR) Pause Frame Transmitted */ +#define GMAC_ISR_DRQFR (0x1u << 18) /**< \brief (GMAC_ISR) PTP Delay Request Frame Received */ +#define GMAC_ISR_SFR (0x1u << 19) /**< \brief (GMAC_ISR) PTP Sync Frame Received */ +#define GMAC_ISR_DRQFT (0x1u << 20) /**< \brief (GMAC_ISR) PTP Delay Request Frame Transmitted */ +#define GMAC_ISR_SFT (0x1u << 21) /**< \brief (GMAC_ISR) PTP Sync Frame Transmitted */ +#define GMAC_ISR_PDRQFR (0x1u << 22) /**< \brief (GMAC_ISR) PDelay Request Frame Received */ +#define GMAC_ISR_PDRSFR (0x1u << 23) /**< \brief (GMAC_ISR) PDelay Response Frame Received */ +#define GMAC_ISR_PDRQFT (0x1u << 24) /**< \brief (GMAC_ISR) PDelay Request Frame Transmitted */ +#define GMAC_ISR_PDRSFT (0x1u << 25) /**< \brief (GMAC_ISR) PDelay Response Frame Transmitted */ +#define GMAC_ISR_SRI (0x1u << 26) /**< \brief (GMAC_ISR) TSU Seconds Register Increment */ +#define GMAC_ISR_WOL (0x1u << 28) /**< \brief (GMAC_ISR) Wake On LAN */ +/* -------- GMAC_IER : (GMAC Offset: 0x028) Interrupt Enable Register -------- */ +#define GMAC_IER_MFS (0x1u << 0) /**< \brief (GMAC_IER) Management Frame Sent */ +#define GMAC_IER_RCOMP (0x1u << 1) /**< \brief (GMAC_IER) Receive Complete */ +#define GMAC_IER_RXUBR (0x1u << 2) /**< \brief (GMAC_IER) RX Used Bit Read */ +#define GMAC_IER_TXUBR (0x1u << 3) /**< \brief (GMAC_IER) TX Used Bit Read */ +#define GMAC_IER_TUR (0x1u << 4) /**< \brief (GMAC_IER) Transmit Underrun */ +#define GMAC_IER_RLEX (0x1u << 5) /**< \brief (GMAC_IER) Retry Limit Exceeded or Late Collision */ +#define GMAC_IER_TFC (0x1u << 6) /**< \brief (GMAC_IER) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IER_TCOMP (0x1u << 7) /**< \brief (GMAC_IER) Transmit Complete */ +#define GMAC_IER_ROVR (0x1u << 10) /**< \brief (GMAC_IER) Receive Overrun */ +#define GMAC_IER_HRESP (0x1u << 11) /**< \brief (GMAC_IER) HRESP Not OK */ +#define GMAC_IER_PFNZ (0x1u << 12) /**< \brief (GMAC_IER) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_IER_PTZ (0x1u << 13) /**< \brief (GMAC_IER) Pause Time Zero */ +#define GMAC_IER_PFTR (0x1u << 14) /**< \brief (GMAC_IER) Pause Frame Transmitted */ +#define GMAC_IER_EXINT (0x1u << 15) /**< \brief (GMAC_IER) External Interrupt */ +#define GMAC_IER_DRQFR (0x1u << 18) /**< \brief (GMAC_IER) PTP Delay Request Frame Received */ +#define GMAC_IER_SFR (0x1u << 19) /**< \brief (GMAC_IER) PTP Sync Frame Received */ +#define GMAC_IER_DRQFT (0x1u << 20) /**< \brief (GMAC_IER) PTP Delay Request Frame Transmitted */ +#define GMAC_IER_SFT (0x1u << 21) /**< \brief (GMAC_IER) PTP Sync Frame Transmitted */ +#define GMAC_IER_PDRQFR (0x1u << 22) /**< \brief (GMAC_IER) PDelay Request Frame Received */ +#define GMAC_IER_PDRSFR (0x1u << 23) /**< \brief (GMAC_IER) PDelay Response Frame Received */ +#define GMAC_IER_PDRQFT (0x1u << 24) /**< \brief (GMAC_IER) PDelay Request Frame Transmitted */ +#define GMAC_IER_PDRSFT (0x1u << 25) /**< \brief (GMAC_IER) PDelay Response Frame Transmitted */ +#define GMAC_IER_SRI (0x1u << 26) /**< \brief (GMAC_IER) TSU Seconds Register Increment */ +#define GMAC_IER_WOL (0x1u << 28) /**< \brief (GMAC_IER) Wake On LAN */ +/* -------- GMAC_IDR : (GMAC Offset: 0x02C) Interrupt Disable Register -------- */ +#define GMAC_IDR_MFS (0x1u << 0) /**< \brief (GMAC_IDR) Management Frame Sent */ +#define GMAC_IDR_RCOMP (0x1u << 1) /**< \brief (GMAC_IDR) Receive Complete */ +#define GMAC_IDR_RXUBR (0x1u << 2) /**< \brief (GMAC_IDR) RX Used Bit Read */ +#define GMAC_IDR_TXUBR (0x1u << 3) /**< \brief (GMAC_IDR) TX Used Bit Read */ +#define GMAC_IDR_TUR (0x1u << 4) /**< \brief (GMAC_IDR) Transmit Underrun */ +#define GMAC_IDR_RLEX (0x1u << 5) /**< \brief (GMAC_IDR) Retry Limit Exceeded or Late Collision */ +#define GMAC_IDR_TFC (0x1u << 6) /**< \brief (GMAC_IDR) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IDR_TCOMP (0x1u << 7) /**< \brief (GMAC_IDR) Transmit Complete */ +#define GMAC_IDR_ROVR (0x1u << 10) /**< \brief (GMAC_IDR) Receive Overrun */ +#define GMAC_IDR_HRESP (0x1u << 11) /**< \brief (GMAC_IDR) HRESP Not OK */ +#define GMAC_IDR_PFNZ (0x1u << 12) /**< \brief (GMAC_IDR) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_IDR_PTZ (0x1u << 13) /**< \brief (GMAC_IDR) Pause Time Zero */ +#define GMAC_IDR_PFTR (0x1u << 14) /**< \brief (GMAC_IDR) Pause Frame Transmitted */ +#define GMAC_IDR_EXINT (0x1u << 15) /**< \brief (GMAC_IDR) External Interrupt */ +#define GMAC_IDR_DRQFR (0x1u << 18) /**< \brief (GMAC_IDR) PTP Delay Request Frame Received */ +#define GMAC_IDR_SFR (0x1u << 19) /**< \brief (GMAC_IDR) PTP Sync Frame Received */ +#define GMAC_IDR_DRQFT (0x1u << 20) /**< \brief (GMAC_IDR) PTP Delay Request Frame Transmitted */ +#define GMAC_IDR_SFT (0x1u << 21) /**< \brief (GMAC_IDR) PTP Sync Frame Transmitted */ +#define GMAC_IDR_PDRQFR (0x1u << 22) /**< \brief (GMAC_IDR) PDelay Request Frame Received */ +#define GMAC_IDR_PDRSFR (0x1u << 23) /**< \brief (GMAC_IDR) PDelay Response Frame Received */ +#define GMAC_IDR_PDRQFT (0x1u << 24) /**< \brief (GMAC_IDR) PDelay Request Frame Transmitted */ +#define GMAC_IDR_PDRSFT (0x1u << 25) /**< \brief (GMAC_IDR) PDelay Response Frame Transmitted */ +#define GMAC_IDR_SRI (0x1u << 26) /**< \brief (GMAC_IDR) TSU Seconds Register Increment */ +#define GMAC_IDR_WOL (0x1u << 28) /**< \brief (GMAC_IDR) Wake On LAN */ +/* -------- GMAC_IMR : (GMAC Offset: 0x030) Interrupt Mask Register -------- */ +#define GMAC_IMR_MFS (0x1u << 0) /**< \brief (GMAC_IMR) Management Frame Sent */ +#define GMAC_IMR_RCOMP (0x1u << 1) /**< \brief (GMAC_IMR) Receive Complete */ +#define GMAC_IMR_RXUBR (0x1u << 2) /**< \brief (GMAC_IMR) RX Used Bit Read */ +#define GMAC_IMR_TXUBR (0x1u << 3) /**< \brief (GMAC_IMR) TX Used Bit Read */ +#define GMAC_IMR_TUR (0x1u << 4) /**< \brief (GMAC_IMR) Transmit Underrun */ +#define GMAC_IMR_RLEX (0x1u << 5) /**< \brief (GMAC_IMR) Retry Limit Exceeded */ +#define GMAC_IMR_TFC (0x1u << 6) /**< \brief (GMAC_IMR) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IMR_TCOMP (0x1u << 7) /**< \brief (GMAC_IMR) Transmit Complete */ +#define GMAC_IMR_ROVR (0x1u << 10) /**< \brief (GMAC_IMR) Receive Overrun */ +#define GMAC_IMR_HRESP (0x1u << 11) /**< \brief (GMAC_IMR) HRESP Not OK */ +#define GMAC_IMR_PFNZ (0x1u << 12) /**< \brief (GMAC_IMR) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_IMR_PTZ (0x1u << 13) /**< \brief (GMAC_IMR) Pause Time Zero */ +#define GMAC_IMR_PFTR (0x1u << 14) /**< \brief (GMAC_IMR) Pause Frame Transmitted */ +#define GMAC_IMR_EXINT (0x1u << 15) /**< \brief (GMAC_IMR) External Interrupt */ +#define GMAC_IMR_DRQFR (0x1u << 18) /**< \brief (GMAC_IMR) PTP Delay Request Frame Received */ +#define GMAC_IMR_SFR (0x1u << 19) /**< \brief (GMAC_IMR) PTP Sync Frame Received */ +#define GMAC_IMR_DRQFT (0x1u << 20) /**< \brief (GMAC_IMR) PTP Delay Request Frame Transmitted */ +#define GMAC_IMR_SFT (0x1u << 21) /**< \brief (GMAC_IMR) PTP Sync Frame Transmitted */ +#define GMAC_IMR_PDRQFR (0x1u << 22) /**< \brief (GMAC_IMR) PDelay Request Frame Received */ +#define GMAC_IMR_PDRSFR (0x1u << 23) /**< \brief (GMAC_IMR) PDelay Response Frame Received */ +#define GMAC_IMR_PDRQFT (0x1u << 24) /**< \brief (GMAC_IMR) PDelay Request Frame Transmitted */ +#define GMAC_IMR_PDRSFT (0x1u << 25) /**< \brief (GMAC_IMR) PDelay Response Frame Transmitted */ +#define GMAC_IMR_SRI (0x1u << 26) /**< \brief (GMAC_IMR) TSU Seconds Register Increment */ +#define GMAC_IMR_WOL (0x1u << 28) /**< \brief (GMAC_IMR) Wake On LAN */ +/* -------- GMAC_MAN : (GMAC Offset: 0x034) PHY Maintenance Register -------- */ +#define GMAC_MAN_DATA_Pos 0 +#define GMAC_MAN_DATA_Msk (0xffffu << GMAC_MAN_DATA_Pos) /**< \brief (GMAC_MAN) PHY Data */ +#define GMAC_MAN_DATA(value) ((GMAC_MAN_DATA_Msk & ((value) << GMAC_MAN_DATA_Pos))) +#define GMAC_MAN_WTN_Pos 16 +#define GMAC_MAN_WTN_Msk (0x3u << GMAC_MAN_WTN_Pos) /**< \brief (GMAC_MAN) Write Ten */ +#define GMAC_MAN_WTN(value) ((GMAC_MAN_WTN_Msk & ((value) << GMAC_MAN_WTN_Pos))) +#define GMAC_MAN_REGA_Pos 18 +#define GMAC_MAN_REGA_Msk (0x1fu << GMAC_MAN_REGA_Pos) /**< \brief (GMAC_MAN) Register Address */ +#define GMAC_MAN_REGA(value) ((GMAC_MAN_REGA_Msk & ((value) << GMAC_MAN_REGA_Pos))) +#define GMAC_MAN_PHYA_Pos 23 +#define GMAC_MAN_PHYA_Msk (0x1fu << GMAC_MAN_PHYA_Pos) /**< \brief (GMAC_MAN) PHY Address */ +#define GMAC_MAN_PHYA(value) ((GMAC_MAN_PHYA_Msk & ((value) << GMAC_MAN_PHYA_Pos))) +#define GMAC_MAN_OP_Pos 28 +#define GMAC_MAN_OP_Msk (0x3u << GMAC_MAN_OP_Pos) /**< \brief (GMAC_MAN) Operation */ +#define GMAC_MAN_OP(value) ((GMAC_MAN_OP_Msk & ((value) << GMAC_MAN_OP_Pos))) +#define GMAC_MAN_CLTTO (0x1u << 30) /**< \brief (GMAC_MAN) Clause 22 Operation */ +#define GMAC_MAN_WZO (0x1u << 31) /**< \brief (GMAC_MAN) Write ZERO */ +/* -------- GMAC_RPQ : (GMAC Offset: 0x038) Received Pause Quantum Register -------- */ +#define GMAC_RPQ_RPQ_Pos 0 +#define GMAC_RPQ_RPQ_Msk (0xffffu << GMAC_RPQ_RPQ_Pos) /**< \brief (GMAC_RPQ) Received Pause Quantum */ +/* -------- GMAC_TPQ : (GMAC Offset: 0x03C) Transmit Pause Quantum Register -------- */ +#define GMAC_TPQ_TPQ_Pos 0 +#define GMAC_TPQ_TPQ_Msk (0xffffu << GMAC_TPQ_TPQ_Pos) /**< \brief (GMAC_TPQ) Transmit Pause Quantum */ +#define GMAC_TPQ_TPQ(value) ((GMAC_TPQ_TPQ_Msk & ((value) << GMAC_TPQ_TPQ_Pos))) +/* -------- GMAC_TPSF : (GMAC Offset: 0x040) TX Partial Store and Forward Register -------- */ +#define GMAC_TPSF_TPB1ADR_Pos 0 +#define GMAC_TPSF_TPB1ADR_Msk (0xfffu << GMAC_TPSF_TPB1ADR_Pos) /**< \brief (GMAC_TPSF) Transmit Partial Store and Forward Address */ +#define GMAC_TPSF_TPB1ADR(value) ((GMAC_TPSF_TPB1ADR_Msk & ((value) << GMAC_TPSF_TPB1ADR_Pos))) +#define GMAC_TPSF_ENTXP (0x1u << 31) /**< \brief (GMAC_TPSF) Enable TX Partial Store and Forward Operation */ +/* -------- GMAC_RPSF : (GMAC Offset: 0x044) RX Partial Store and Forward Register -------- */ +#define GMAC_RPSF_RPB1ADR_Pos 0 +#define GMAC_RPSF_RPB1ADR_Msk (0xfffu << GMAC_RPSF_RPB1ADR_Pos) /**< \brief (GMAC_RPSF) Receive Partial Store and Forward Address */ +#define GMAC_RPSF_RPB1ADR(value) ((GMAC_RPSF_RPB1ADR_Msk & ((value) << GMAC_RPSF_RPB1ADR_Pos))) +#define GMAC_RPSF_ENRXP (0x1u << 31) /**< \brief (GMAC_RPSF) Enable RX Partial Store and Forward Operation */ +/* -------- GMAC_RJFML : (GMAC Offset: 0x048) RX Jumbo Frame Max Length Register -------- */ +#define GMAC_RJFML_FML_Pos 0 +#define GMAC_RJFML_FML_Msk (0x3fffu << GMAC_RJFML_FML_Pos) /**< \brief (GMAC_RJFML) Frame Max Length */ +#define GMAC_RJFML_FML(value) ((GMAC_RJFML_FML_Msk & ((value) << GMAC_RJFML_FML_Pos))) +/* -------- GMAC_HRB : (GMAC Offset: 0x080) Hash Register Bottom -------- */ +#define GMAC_HRB_ADDR_Pos 0 +#define GMAC_HRB_ADDR_Msk (0xffffffffu << GMAC_HRB_ADDR_Pos) /**< \brief (GMAC_HRB) Hash Address */ +#define GMAC_HRB_ADDR(value) ((GMAC_HRB_ADDR_Msk & ((value) << GMAC_HRB_ADDR_Pos))) +/* -------- GMAC_HRT : (GMAC Offset: 0x084) Hash Register Top -------- */ +#define GMAC_HRT_ADDR_Pos 0 +#define GMAC_HRT_ADDR_Msk (0xffffffffu << GMAC_HRT_ADDR_Pos) /**< \brief (GMAC_HRT) Hash Address */ +#define GMAC_HRT_ADDR(value) ((GMAC_HRT_ADDR_Msk & ((value) << GMAC_HRT_ADDR_Pos))) +/* -------- GMAC_SAB : (GMAC Offset: N/A) Specific Address 1 Bottom Register -------- */ +#define GMAC_SAB_ADDR_Pos 0 +#define GMAC_SAB_ADDR_Msk (0xffffffffu << GMAC_SAB_ADDR_Pos) /**< \brief (GMAC_SAB) Specific Address 1 */ +#define GMAC_SAB_ADDR(value) ((GMAC_SAB_ADDR_Msk & ((value) << GMAC_SAB_ADDR_Pos))) +/* -------- GMAC_SAT : (GMAC Offset: N/A) Specific Address 1 Top Register -------- */ +#define GMAC_SAT_ADDR_Pos 0 +#define GMAC_SAT_ADDR_Msk (0xffffu << GMAC_SAT_ADDR_Pos) /**< \brief (GMAC_SAT) Specific Address 1 */ +#define GMAC_SAT_ADDR(value) ((GMAC_SAT_ADDR_Msk & ((value) << GMAC_SAT_ADDR_Pos))) +/* -------- GMAC_TIDM1 : (GMAC Offset: 0x0A8) Type ID Match 1 Register -------- */ +#define GMAC_TIDM1_TID_Pos 0 +#define GMAC_TIDM1_TID_Msk (0xffffu << GMAC_TIDM1_TID_Pos) /**< \brief (GMAC_TIDM1) Type ID Match 1 */ +#define GMAC_TIDM1_TID(value) ((GMAC_TIDM1_TID_Msk & ((value) << GMAC_TIDM1_TID_Pos))) +#define GMAC_TIDM1_ENID1 (0x1u << 31) /**< \brief (GMAC_TIDM1) Enable Copying of TID Matched Frames */ +/* -------- GMAC_TIDM2 : (GMAC Offset: 0x0AC) Type ID Match 2 Register -------- */ +#define GMAC_TIDM2_TID_Pos 0 +#define GMAC_TIDM2_TID_Msk (0xffffu << GMAC_TIDM2_TID_Pos) /**< \brief (GMAC_TIDM2) Type ID Match 2 */ +#define GMAC_TIDM2_TID(value) ((GMAC_TIDM2_TID_Msk & ((value) << GMAC_TIDM2_TID_Pos))) +#define GMAC_TIDM2_ENID2 (0x1u << 31) /**< \brief (GMAC_TIDM2) Enable Copying of TID Matched Frames */ +/* -------- GMAC_TIDM3 : (GMAC Offset: 0x0B0) Type ID Match 3 Register -------- */ +#define GMAC_TIDM3_TID_Pos 0 +#define GMAC_TIDM3_TID_Msk (0xffffu << GMAC_TIDM3_TID_Pos) /**< \brief (GMAC_TIDM3) Type ID Match 3 */ +#define GMAC_TIDM3_TID(value) ((GMAC_TIDM3_TID_Msk & ((value) << GMAC_TIDM3_TID_Pos))) +#define GMAC_TIDM3_ENID3 (0x1u << 31) /**< \brief (GMAC_TIDM3) Enable Copying of TID Matched Frames */ +/* -------- GMAC_TIDM4 : (GMAC Offset: 0x0B4) Type ID Match 4 Register -------- */ +#define GMAC_TIDM4_TID_Pos 0 +#define GMAC_TIDM4_TID_Msk (0xffffu << GMAC_TIDM4_TID_Pos) /**< \brief (GMAC_TIDM4) Type ID Match 4 */ +#define GMAC_TIDM4_TID(value) ((GMAC_TIDM4_TID_Msk & ((value) << GMAC_TIDM4_TID_Pos))) +#define GMAC_TIDM4_ENID4 (0x1u << 31) /**< \brief (GMAC_TIDM4) Enable Copying of TID Matched Frames */ +/* -------- GMAC_WOL : (GMAC Offset: 0x0B8) Wake on LAN Register -------- */ +#define GMAC_WOL_IP_Pos 0 +#define GMAC_WOL_IP_Msk (0xffffu << GMAC_WOL_IP_Pos) /**< \brief (GMAC_WOL) ARP Request IP Address */ +#define GMAC_WOL_IP(value) ((GMAC_WOL_IP_Msk & ((value) << GMAC_WOL_IP_Pos))) +#define GMAC_WOL_MAG (0x1u << 16) /**< \brief (GMAC_WOL) Magic Packet Event Enable */ +#define GMAC_WOL_ARP (0x1u << 17) /**< \brief (GMAC_WOL) ARP Request IP Address */ +#define GMAC_WOL_SA1 (0x1u << 18) /**< \brief (GMAC_WOL) Specific Address Register 1 Event Enable */ +#define GMAC_WOL_MTI (0x1u << 19) /**< \brief (GMAC_WOL) Multicast Hash Event Enable */ +/* -------- GMAC_IPGS : (GMAC Offset: 0x0BC) IPG Stretch Register -------- */ +#define GMAC_IPGS_FL_Pos 0 +#define GMAC_IPGS_FL_Msk (0xffffu << GMAC_IPGS_FL_Pos) /**< \brief (GMAC_IPGS) Frame Length */ +#define GMAC_IPGS_FL(value) ((GMAC_IPGS_FL_Msk & ((value) << GMAC_IPGS_FL_Pos))) +/* -------- GMAC_SVLAN : (GMAC Offset: 0x0C0) Stacked VLAN Register -------- */ +#define GMAC_SVLAN_VLAN_TYPE_Pos 0 +#define GMAC_SVLAN_VLAN_TYPE_Msk (0xffffu << GMAC_SVLAN_VLAN_TYPE_Pos) /**< \brief (GMAC_SVLAN) User Defined VLAN_TYPE Field */ +#define GMAC_SVLAN_VLAN_TYPE(value) ((GMAC_SVLAN_VLAN_TYPE_Msk & ((value) << GMAC_SVLAN_VLAN_TYPE_Pos))) +#define GMAC_SVLAN_ESVLAN (0x1u << 31) /**< \brief (GMAC_SVLAN) Enable Stacked VLAN Processing Mode */ +/* -------- GMAC_TPFCP : (GMAC Offset: 0x0C4) Transmit PFC Pause Register -------- */ +#define GMAC_TPFCP_PEV_Pos 0 +#define GMAC_TPFCP_PEV_Msk (0xffu << GMAC_TPFCP_PEV_Pos) /**< \brief (GMAC_TPFCP) Priority Enable Vector */ +#define GMAC_TPFCP_PEV(value) ((GMAC_TPFCP_PEV_Msk & ((value) << GMAC_TPFCP_PEV_Pos))) +#define GMAC_TPFCP_PQ_Pos 8 +#define GMAC_TPFCP_PQ_Msk (0xffu << GMAC_TPFCP_PQ_Pos) /**< \brief (GMAC_TPFCP) Pause Quantum */ +#define GMAC_TPFCP_PQ(value) ((GMAC_TPFCP_PQ_Msk & ((value) << GMAC_TPFCP_PQ_Pos))) +/* -------- GMAC_SAMB1 : (GMAC Offset: 0x0C8) Specific Address 1 Mask Bottom Register -------- */ +#define GMAC_SAMB1_ADDR_Pos 0 +#define GMAC_SAMB1_ADDR_Msk (0xffffffffu << GMAC_SAMB1_ADDR_Pos) /**< \brief (GMAC_SAMB1) Specific Address 1 Mask */ +#define GMAC_SAMB1_ADDR(value) ((GMAC_SAMB1_ADDR_Msk & ((value) << GMAC_SAMB1_ADDR_Pos))) +/* -------- GMAC_SAMT1 : (GMAC Offset: 0x0CC) Specific Address 1 Mask Top Register -------- */ +#define GMAC_SAMT1_ADDR_Pos 0 +#define GMAC_SAMT1_ADDR_Msk (0xffffu << GMAC_SAMT1_ADDR_Pos) /**< \brief (GMAC_SAMT1) Specific Address 1 Mask */ +#define GMAC_SAMT1_ADDR(value) ((GMAC_SAMT1_ADDR_Msk & ((value) << GMAC_SAMT1_ADDR_Pos))) +/* -------- GMAC_NSC : (GMAC Offset: 0x0DC) 1588 Timer Nanosecond Comparison Register -------- */ +#define GMAC_NSC_NANOSEC_Pos 0 +#define GMAC_NSC_NANOSEC_Msk (0x3fffffu << GMAC_NSC_NANOSEC_Pos) /**< \brief (GMAC_NSC) 1588 Timer Nanosecond Comparison Value */ +#define GMAC_NSC_NANOSEC(value) ((GMAC_NSC_NANOSEC_Msk & ((value) << GMAC_NSC_NANOSEC_Pos))) +/* -------- GMAC_SCL : (GMAC Offset: 0x0E0) 1588 Timer Second Comparison Low Register -------- */ +#define GMAC_SCL_SEC_Pos 0 +#define GMAC_SCL_SEC_Msk (0xffffffffu << GMAC_SCL_SEC_Pos) /**< \brief (GMAC_SCL) 1588 Timer Second Comparison Value */ +#define GMAC_SCL_SEC(value) ((GMAC_SCL_SEC_Msk & ((value) << GMAC_SCL_SEC_Pos))) +/* -------- GMAC_SCH : (GMAC Offset: 0x0E4) 1588 Timer Second Comparison High Register -------- */ +#define GMAC_SCH_SEC_Pos 0 +#define GMAC_SCH_SEC_Msk (0xffffu << GMAC_SCH_SEC_Pos) /**< \brief (GMAC_SCH) 1588 Timer Second Comparison Value */ +#define GMAC_SCH_SEC(value) ((GMAC_SCH_SEC_Msk & ((value) << GMAC_SCH_SEC_Pos))) +/* -------- GMAC_EFTSH : (GMAC Offset: 0x0E8) PTP Event Frame Transmitted Seconds High Register -------- */ +#define GMAC_EFTSH_RUD_Pos 0 +#define GMAC_EFTSH_RUD_Msk (0xffffu << GMAC_EFTSH_RUD_Pos) /**< \brief (GMAC_EFTSH) Register Update */ +/* -------- GMAC_EFRSH : (GMAC Offset: 0x0EC) PTP Event Frame Received Seconds High Register -------- */ +#define GMAC_EFRSH_RUD_Pos 0 +#define GMAC_EFRSH_RUD_Msk (0xffffu << GMAC_EFRSH_RUD_Pos) /**< \brief (GMAC_EFRSH) Register Update */ +/* -------- GMAC_PEFTSH : (GMAC Offset: 0x0F0) PTP Peer Event Frame Transmitted Seconds High Register -------- */ +#define GMAC_PEFTSH_RUD_Pos 0 +#define GMAC_PEFTSH_RUD_Msk (0xffffu << GMAC_PEFTSH_RUD_Pos) /**< \brief (GMAC_PEFTSH) Register Update */ +/* -------- GMAC_PEFRSH : (GMAC Offset: 0x0F4) PTP Peer Event Frame Received Seconds High Register -------- */ +#define GMAC_PEFRSH_RUD_Pos 0 +#define GMAC_PEFRSH_RUD_Msk (0xffffu << GMAC_PEFRSH_RUD_Pos) /**< \brief (GMAC_PEFRSH) Register Update */ +/* -------- GMAC_MID : (GMAC Offset: 0x0FC) Module ID Register -------- */ +#define GMAC_MID_MREV_Pos 0 +#define GMAC_MID_MREV_Msk (0xffffu << GMAC_MID_MREV_Pos) /**< \brief (GMAC_MID) Module Revision */ +#define GMAC_MID_MID_Pos 16 +#define GMAC_MID_MID_Msk (0xffffu << GMAC_MID_MID_Pos) /**< \brief (GMAC_MID) Module Identification Number */ +/* -------- GMAC_OTLO : (GMAC Offset: 0x100) Octets Transmitted Low Register -------- */ +#define GMAC_OTLO_TXO_Pos 0 +#define GMAC_OTLO_TXO_Msk (0xffffffffu << GMAC_OTLO_TXO_Pos) /**< \brief (GMAC_OTLO) Transmitted Octets */ +/* -------- GMAC_OTHI : (GMAC Offset: 0x104) Octets Transmitted High Register -------- */ +#define GMAC_OTHI_TXO_Pos 0 +#define GMAC_OTHI_TXO_Msk (0xffffu << GMAC_OTHI_TXO_Pos) /**< \brief (GMAC_OTHI) Transmitted Octets */ +/* -------- GMAC_FT : (GMAC Offset: 0x108) Frames Transmitted Register -------- */ +#define GMAC_FT_FTX_Pos 0 +#define GMAC_FT_FTX_Msk (0xffffffffu << GMAC_FT_FTX_Pos) /**< \brief (GMAC_FT) Frames Transmitted without Error */ +/* -------- GMAC_BCFT : (GMAC Offset: 0x10C) Broadcast Frames Transmitted Register -------- */ +#define GMAC_BCFT_BFTX_Pos 0 +#define GMAC_BCFT_BFTX_Msk (0xffffffffu << GMAC_BCFT_BFTX_Pos) /**< \brief (GMAC_BCFT) Broadcast Frames Transmitted without Error */ +/* -------- GMAC_MFT : (GMAC Offset: 0x110) Multicast Frames Transmitted Register -------- */ +#define GMAC_MFT_MFTX_Pos 0 +#define GMAC_MFT_MFTX_Msk (0xffffffffu << GMAC_MFT_MFTX_Pos) /**< \brief (GMAC_MFT) Multicast Frames Transmitted without Error */ +/* -------- GMAC_PFT : (GMAC Offset: 0x114) Pause Frames Transmitted Register -------- */ +#define GMAC_PFT_PFTX_Pos 0 +#define GMAC_PFT_PFTX_Msk (0xffffu << GMAC_PFT_PFTX_Pos) /**< \brief (GMAC_PFT) Pause Frames Transmitted Register */ +/* -------- GMAC_BFT64 : (GMAC Offset: 0x118) 64 Byte Frames Transmitted Register -------- */ +#define GMAC_BFT64_NFTX_Pos 0 +#define GMAC_BFT64_NFTX_Msk (0xffffffffu << GMAC_BFT64_NFTX_Pos) /**< \brief (GMAC_BFT64) 64 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT127 : (GMAC Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT127_NFTX_Pos 0 +#define GMAC_TBFT127_NFTX_Msk (0xffffffffu << GMAC_TBFT127_NFTX_Pos) /**< \brief (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT255 : (GMAC Offset: 0x120) 128 to 255 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT255_NFTX_Pos 0 +#define GMAC_TBFT255_NFTX_Msk (0xffffffffu << GMAC_TBFT255_NFTX_Pos) /**< \brief (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT511 : (GMAC Offset: 0x124) 256 to 511 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT511_NFTX_Pos 0 +#define GMAC_TBFT511_NFTX_Msk (0xffffffffu << GMAC_TBFT511_NFTX_Pos) /**< \brief (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT1023 : (GMAC Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT1023_NFTX_Pos 0 +#define GMAC_TBFT1023_NFTX_Msk (0xffffffffu << GMAC_TBFT1023_NFTX_Pos) /**< \brief (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT1518 : (GMAC Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT1518_NFTX_Pos 0 +#define GMAC_TBFT1518_NFTX_Msk (0xffffffffu << GMAC_TBFT1518_NFTX_Pos) /**< \brief (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted without Error */ +/* -------- GMAC_GTBFT1518 : (GMAC Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register -------- */ +#define GMAC_GTBFT1518_NFTX_Pos 0 +#define GMAC_GTBFT1518_NFTX_Msk (0xffffffffu << GMAC_GTBFT1518_NFTX_Pos) /**< \brief (GMAC_GTBFT1518) Greater than 1518 Byte Frames Transmitted without Error */ +/* -------- GMAC_TUR : (GMAC Offset: 0x134) Transmit Underruns Register -------- */ +#define GMAC_TUR_TXUNR_Pos 0 +#define GMAC_TUR_TXUNR_Msk (0x3ffu << GMAC_TUR_TXUNR_Pos) /**< \brief (GMAC_TUR) Transmit Underruns */ +/* -------- GMAC_SCF : (GMAC Offset: 0x138) Single Collision Frames Register -------- */ +#define GMAC_SCF_SCOL_Pos 0 +#define GMAC_SCF_SCOL_Msk (0x3ffffu << GMAC_SCF_SCOL_Pos) /**< \brief (GMAC_SCF) Single Collision */ +/* -------- GMAC_MCF : (GMAC Offset: 0x13C) Multiple Collision Frames Register -------- */ +#define GMAC_MCF_MCOL_Pos 0 +#define GMAC_MCF_MCOL_Msk (0x3ffffu << GMAC_MCF_MCOL_Pos) /**< \brief (GMAC_MCF) Multiple Collision */ +/* -------- GMAC_EC : (GMAC Offset: 0x140) Excessive Collisions Register -------- */ +#define GMAC_EC_XCOL_Pos 0 +#define GMAC_EC_XCOL_Msk (0x3ffu << GMAC_EC_XCOL_Pos) /**< \brief (GMAC_EC) Excessive Collisions */ +/* -------- GMAC_LC : (GMAC Offset: 0x144) Late Collisions Register -------- */ +#define GMAC_LC_LCOL_Pos 0 +#define GMAC_LC_LCOL_Msk (0x3ffu << GMAC_LC_LCOL_Pos) /**< \brief (GMAC_LC) Late Collisions */ +/* -------- GMAC_DTF : (GMAC Offset: 0x148) Deferred Transmission Frames Register -------- */ +#define GMAC_DTF_DEFT_Pos 0 +#define GMAC_DTF_DEFT_Msk (0x3ffffu << GMAC_DTF_DEFT_Pos) /**< \brief (GMAC_DTF) Deferred Transmission */ +/* -------- GMAC_CSE : (GMAC Offset: 0x14C) Carrier Sense Errors Register -------- */ +#define GMAC_CSE_CSR_Pos 0 +#define GMAC_CSE_CSR_Msk (0x3ffu << GMAC_CSE_CSR_Pos) /**< \brief (GMAC_CSE) Carrier Sense Error */ +/* -------- GMAC_ORLO : (GMAC Offset: 0x150) Octets Received Low Received Register -------- */ +#define GMAC_ORLO_RXO_Pos 0 +#define GMAC_ORLO_RXO_Msk (0xffffffffu << GMAC_ORLO_RXO_Pos) /**< \brief (GMAC_ORLO) Received Octets */ +/* -------- GMAC_ORHI : (GMAC Offset: 0x154) Octets Received High Received Register -------- */ +#define GMAC_ORHI_RXO_Pos 0 +#define GMAC_ORHI_RXO_Msk (0xffffu << GMAC_ORHI_RXO_Pos) /**< \brief (GMAC_ORHI) Received Octets */ +/* -------- GMAC_FR : (GMAC Offset: 0x158) Frames Received Register -------- */ +#define GMAC_FR_FRX_Pos 0 +#define GMAC_FR_FRX_Msk (0xffffffffu << GMAC_FR_FRX_Pos) /**< \brief (GMAC_FR) Frames Received without Error */ +/* -------- GMAC_BCFR : (GMAC Offset: 0x15C) Broadcast Frames Received Register -------- */ +#define GMAC_BCFR_BFRX_Pos 0 +#define GMAC_BCFR_BFRX_Msk (0xffffffffu << GMAC_BCFR_BFRX_Pos) /**< \brief (GMAC_BCFR) Broadcast Frames Received without Error */ +/* -------- GMAC_MFR : (GMAC Offset: 0x160) Multicast Frames Received Register -------- */ +#define GMAC_MFR_MFRX_Pos 0 +#define GMAC_MFR_MFRX_Msk (0xffffffffu << GMAC_MFR_MFRX_Pos) /**< \brief (GMAC_MFR) Multicast Frames Received without Error */ +/* -------- GMAC_PFR : (GMAC Offset: 0x164) Pause Frames Received Register -------- */ +#define GMAC_PFR_PFRX_Pos 0 +#define GMAC_PFR_PFRX_Msk (0xffffu << GMAC_PFR_PFRX_Pos) /**< \brief (GMAC_PFR) Pause Frames Received Register */ +/* -------- GMAC_BFR64 : (GMAC Offset: 0x168) 64 Byte Frames Received Register -------- */ +#define GMAC_BFR64_NFRX_Pos 0 +#define GMAC_BFR64_NFRX_Msk (0xffffffffu << GMAC_BFR64_NFRX_Pos) /**< \brief (GMAC_BFR64) 64 Byte Frames Received without Error */ +/* -------- GMAC_TBFR127 : (GMAC Offset: 0x16C) 65 to 127 Byte Frames Received Register -------- */ +#define GMAC_TBFR127_NFRX_Pos 0 +#define GMAC_TBFR127_NFRX_Msk (0xffffffffu << GMAC_TBFR127_NFRX_Pos) /**< \brief (GMAC_TBFR127) 65 to 127 Byte Frames Received without Error */ +/* -------- GMAC_TBFR255 : (GMAC Offset: 0x170) 128 to 255 Byte Frames Received Register -------- */ +#define GMAC_TBFR255_NFRX_Pos 0 +#define GMAC_TBFR255_NFRX_Msk (0xffffffffu << GMAC_TBFR255_NFRX_Pos) /**< \brief (GMAC_TBFR255) 128 to 255 Byte Frames Received without Error */ +/* -------- GMAC_TBFR511 : (GMAC Offset: 0x174) 256 to 511 Byte Frames Received Register -------- */ +#define GMAC_TBFR511_NFRX_Pos 0 +#define GMAC_TBFR511_NFRX_Msk (0xffffffffu << GMAC_TBFR511_NFRX_Pos) /**< \brief (GMAC_TBFR511) 256 to 511 Byte Frames Received without Error */ +/* -------- GMAC_TBFR1023 : (GMAC Offset: 0x178) 512 to 1023 Byte Frames Received Register -------- */ +#define GMAC_TBFR1023_NFRX_Pos 0 +#define GMAC_TBFR1023_NFRX_Msk (0xffffffffu << GMAC_TBFR1023_NFRX_Pos) /**< \brief (GMAC_TBFR1023) 512 to 1023 Byte Frames Received without Error */ +/* -------- GMAC_TBFR1518 : (GMAC Offset: 0x17C) 1024 to 1518 Byte Frames Received Register -------- */ +#define GMAC_TBFR1518_NFRX_Pos 0 +#define GMAC_TBFR1518_NFRX_Msk (0xffffffffu << GMAC_TBFR1518_NFRX_Pos) /**< \brief (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received without Error */ +/* -------- GMAC_TMXBFR : (GMAC Offset: 0x180) 1519 to Maximum Byte Frames Received Register -------- */ +#define GMAC_TMXBFR_NFRX_Pos 0 +#define GMAC_TMXBFR_NFRX_Msk (0xffffffffu << GMAC_TMXBFR_NFRX_Pos) /**< \brief (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received without Error */ +/* -------- GMAC_UFR : (GMAC Offset: 0x184) Undersize Frames Received Register -------- */ +#define GMAC_UFR_UFRX_Pos 0 +#define GMAC_UFR_UFRX_Msk (0x3ffu << GMAC_UFR_UFRX_Pos) /**< \brief (GMAC_UFR) Undersize Frames Received */ +/* -------- GMAC_OFR : (GMAC Offset: 0x188) Oversize Frames Received Register -------- */ +#define GMAC_OFR_OFRX_Pos 0 +#define GMAC_OFR_OFRX_Msk (0x3ffu << GMAC_OFR_OFRX_Pos) /**< \brief (GMAC_OFR) Oversized Frames Received */ +/* -------- GMAC_JR : (GMAC Offset: 0x18C) Jabbers Received Register -------- */ +#define GMAC_JR_JRX_Pos 0 +#define GMAC_JR_JRX_Msk (0x3ffu << GMAC_JR_JRX_Pos) /**< \brief (GMAC_JR) Jabbers Received */ +/* -------- GMAC_FCSE : (GMAC Offset: 0x190) Frame Check Sequence Errors Register -------- */ +#define GMAC_FCSE_FCKR_Pos 0 +#define GMAC_FCSE_FCKR_Msk (0x3ffu << GMAC_FCSE_FCKR_Pos) /**< \brief (GMAC_FCSE) Frame Check Sequence Errors */ +/* -------- GMAC_LFFE : (GMAC Offset: 0x194) Length Field Frame Errors Register -------- */ +#define GMAC_LFFE_LFER_Pos 0 +#define GMAC_LFFE_LFER_Msk (0x3ffu << GMAC_LFFE_LFER_Pos) /**< \brief (GMAC_LFFE) Length Field Frame Errors */ +/* -------- GMAC_RSE : (GMAC Offset: 0x198) Receive Symbol Errors Register -------- */ +#define GMAC_RSE_RXSE_Pos 0 +#define GMAC_RSE_RXSE_Msk (0x3ffu << GMAC_RSE_RXSE_Pos) /**< \brief (GMAC_RSE) Receive Symbol Errors */ +/* -------- GMAC_AE : (GMAC Offset: 0x19C) Alignment Errors Register -------- */ +#define GMAC_AE_AER_Pos 0 +#define GMAC_AE_AER_Msk (0x3ffu << GMAC_AE_AER_Pos) /**< \brief (GMAC_AE) Alignment Errors */ +/* -------- GMAC_RRE : (GMAC Offset: 0x1A0) Receive Resource Errors Register -------- */ +#define GMAC_RRE_RXRER_Pos 0 +#define GMAC_RRE_RXRER_Msk (0x3ffffu << GMAC_RRE_RXRER_Pos) /**< \brief (GMAC_RRE) Receive Resource Errors */ +/* -------- GMAC_ROE : (GMAC Offset: 0x1A4) Receive Overrun Register -------- */ +#define GMAC_ROE_RXOVR_Pos 0 +#define GMAC_ROE_RXOVR_Msk (0x3ffu << GMAC_ROE_RXOVR_Pos) /**< \brief (GMAC_ROE) Receive Overruns */ +/* -------- GMAC_IHCE : (GMAC Offset: 0x1A8) IP Header Checksum Errors Register -------- */ +#define GMAC_IHCE_HCKER_Pos 0 +#define GMAC_IHCE_HCKER_Msk (0xffu << GMAC_IHCE_HCKER_Pos) /**< \brief (GMAC_IHCE) IP Header Checksum Errors */ +/* -------- GMAC_TCE : (GMAC Offset: 0x1AC) TCP Checksum Errors Register -------- */ +#define GMAC_TCE_TCKER_Pos 0 +#define GMAC_TCE_TCKER_Msk (0xffu << GMAC_TCE_TCKER_Pos) /**< \brief (GMAC_TCE) TCP Checksum Errors */ +/* -------- GMAC_UCE : (GMAC Offset: 0x1B0) UDP Checksum Errors Register -------- */ +#define GMAC_UCE_UCKER_Pos 0 +#define GMAC_UCE_UCKER_Msk (0xffu << GMAC_UCE_UCKER_Pos) /**< \brief (GMAC_UCE) UDP Checksum Errors */ +/* -------- GMAC_TISUBN : (GMAC Offset: 0x1BC) 1588 Timer Increment Sub-nanoseconds Register -------- */ +#define GMAC_TISUBN_LSBTIR_Pos 0 +#define GMAC_TISUBN_LSBTIR_Msk (0xffffu << GMAC_TISUBN_LSBTIR_Pos) /**< \brief (GMAC_TISUBN) Lower Significant Bits of Timer Increment Register */ +#define GMAC_TISUBN_LSBTIR(value) ((GMAC_TISUBN_LSBTIR_Msk & ((value) << GMAC_TISUBN_LSBTIR_Pos))) +/* -------- GMAC_TSH : (GMAC Offset: 0x1C0) 1588 Timer Seconds High Register -------- */ +#define GMAC_TSH_TCS_Pos 0 +#define GMAC_TSH_TCS_Msk (0xffffu << GMAC_TSH_TCS_Pos) /**< \brief (GMAC_TSH) Timer Count in Seconds */ +#define GMAC_TSH_TCS(value) ((GMAC_TSH_TCS_Msk & ((value) << GMAC_TSH_TCS_Pos))) +/* -------- GMAC_TSL : (GMAC Offset: 0x1D0) 1588 Timer Seconds Low Register -------- */ +#define GMAC_TSL_TCS_Pos 0 +#define GMAC_TSL_TCS_Msk (0xffffffffu << GMAC_TSL_TCS_Pos) /**< \brief (GMAC_TSL) Timer Count in Seconds */ +#define GMAC_TSL_TCS(value) ((GMAC_TSL_TCS_Msk & ((value) << GMAC_TSL_TCS_Pos))) +/* -------- GMAC_TN : (GMAC Offset: 0x1D4) 1588 Timer Nanoseconds Register -------- */ +#define GMAC_TN_TNS_Pos 0 +#define GMAC_TN_TNS_Msk (0x3fffffffu << GMAC_TN_TNS_Pos) /**< \brief (GMAC_TN) Timer Count in Nanoseconds */ +#define GMAC_TN_TNS(value) ((GMAC_TN_TNS_Msk & ((value) << GMAC_TN_TNS_Pos))) +/* -------- GMAC_TA : (GMAC Offset: 0x1D8) 1588 Timer Adjust Register -------- */ +#define GMAC_TA_ITDT_Pos 0 +#define GMAC_TA_ITDT_Msk (0x3fffffffu << GMAC_TA_ITDT_Pos) /**< \brief (GMAC_TA) Increment/Decrement */ +#define GMAC_TA_ITDT(value) ((GMAC_TA_ITDT_Msk & ((value) << GMAC_TA_ITDT_Pos))) +#define GMAC_TA_ADJ (0x1u << 31) /**< \brief (GMAC_TA) Adjust 1588 Timer */ +/* -------- GMAC_TI : (GMAC Offset: 0x1DC) 1588 Timer Increment Register -------- */ +#define GMAC_TI_CNS_Pos 0 +#define GMAC_TI_CNS_Msk (0xffu << GMAC_TI_CNS_Pos) /**< \brief (GMAC_TI) Count Nanoseconds */ +#define GMAC_TI_CNS(value) ((GMAC_TI_CNS_Msk & ((value) << GMAC_TI_CNS_Pos))) +#define GMAC_TI_ACNS_Pos 8 +#define GMAC_TI_ACNS_Msk (0xffu << GMAC_TI_ACNS_Pos) /**< \brief (GMAC_TI) Alternative Count Nanoseconds */ +#define GMAC_TI_ACNS(value) ((GMAC_TI_ACNS_Msk & ((value) << GMAC_TI_ACNS_Pos))) +#define GMAC_TI_NIT_Pos 16 +#define GMAC_TI_NIT_Msk (0xffu << GMAC_TI_NIT_Pos) /**< \brief (GMAC_TI) Number of Increments */ +#define GMAC_TI_NIT(value) ((GMAC_TI_NIT_Msk & ((value) << GMAC_TI_NIT_Pos))) +/* -------- GMAC_EFTSL : (GMAC Offset: 0x1E0) PTP Event Frame Transmitted Seconds Low Register -------- */ +#define GMAC_EFTSL_RUD_Pos 0 +#define GMAC_EFTSL_RUD_Msk (0xffffffffu << GMAC_EFTSL_RUD_Pos) /**< \brief (GMAC_EFTSL) Register Update */ +/* -------- GMAC_EFTN : (GMAC Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds Register -------- */ +#define GMAC_EFTN_RUD_Pos 0 +#define GMAC_EFTN_RUD_Msk (0x3fffffffu << GMAC_EFTN_RUD_Pos) /**< \brief (GMAC_EFTN) Register Update */ +/* -------- GMAC_EFRSL : (GMAC Offset: 0x1E8) PTP Event Frame Received Seconds Low Register -------- */ +#define GMAC_EFRSL_RUD_Pos 0 +#define GMAC_EFRSL_RUD_Msk (0xffffffffu << GMAC_EFRSL_RUD_Pos) /**< \brief (GMAC_EFRSL) Register Update */ +/* -------- GMAC_EFRN : (GMAC Offset: 0x1EC) PTP Event Frame Received Nanoseconds Register -------- */ +#define GMAC_EFRN_RUD_Pos 0 +#define GMAC_EFRN_RUD_Msk (0x3fffffffu << GMAC_EFRN_RUD_Pos) /**< \brief (GMAC_EFRN) Register Update */ +/* -------- GMAC_PEFTSL : (GMAC Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds Low Register -------- */ +#define GMAC_PEFTSL_RUD_Pos 0 +#define GMAC_PEFTSL_RUD_Msk (0xffffffffu << GMAC_PEFTSL_RUD_Pos) /**< \brief (GMAC_PEFTSL) Register Update */ +/* -------- GMAC_PEFTN : (GMAC Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds Register -------- */ +#define GMAC_PEFTN_RUD_Pos 0 +#define GMAC_PEFTN_RUD_Msk (0x3fffffffu << GMAC_PEFTN_RUD_Pos) /**< \brief (GMAC_PEFTN) Register Update */ +/* -------- GMAC_PEFRSL : (GMAC Offset: 0x1F8) PTP Peer Event Frame Received Seconds Low Register -------- */ +#define GMAC_PEFRSL_RUD_Pos 0 +#define GMAC_PEFRSL_RUD_Msk (0xffffffffu << GMAC_PEFRSL_RUD_Pos) /**< \brief (GMAC_PEFRSL) Register Update */ +/* -------- GMAC_PEFRN : (GMAC Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds Register -------- */ +#define GMAC_PEFRN_RUD_Pos 0 +#define GMAC_PEFRN_RUD_Msk (0x3fffffffu << GMAC_PEFRN_RUD_Pos) /**< \brief (GMAC_PEFRN) Register Update */ +/* -------- GMAC_RXLPI : (GMAC Offset: 0x270) Received LPI Transitions -------- */ +#define GMAC_RXLPI_COUNT_Pos 0 +#define GMAC_RXLPI_COUNT_Msk (0xffffu << GMAC_RXLPI_COUNT_Pos) /**< \brief (GMAC_RXLPI) Count of RX LPI transitions (cleared on read) */ +/* -------- GMAC_RXLPITIME : (GMAC Offset: 0x274) Received LPI Time -------- */ +#define GMAC_RXLPITIME_LPITIME_Pos 0 +#define GMAC_RXLPITIME_LPITIME_Msk (0xffffffu << GMAC_RXLPITIME_LPITIME_Pos) /**< \brief (GMAC_RXLPITIME) Time in LPI (cleared on read) */ +/* -------- GMAC_TXLPI : (GMAC Offset: 0x278) Transmit LPI Transitions -------- */ +#define GMAC_TXLPI_COUNT_Pos 0 +#define GMAC_TXLPI_COUNT_Msk (0xffffu << GMAC_TXLPI_COUNT_Pos) /**< \brief (GMAC_TXLPI) Count of LPI transitions (cleared on read) */ +/* -------- GMAC_TXLPITIME : (GMAC Offset: 0x27C) Transmit LPI Time -------- */ +#define GMAC_TXLPITIME_LPITIME_Pos 0 +#define GMAC_TXLPITIME_LPITIME_Msk (0xffffffu << GMAC_TXLPITIME_LPITIME_Pos) /**< \brief (GMAC_TXLPITIME) Time in LPI (cleared on read) */ +/* -------- GMAC_ISRPQ[5] : (GMAC Offset: 0x400) Interrupt Status Register Priority Queue (index = 1) -------- */ +#define GMAC_ISRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_ISRPQ[5]) Receive Complete */ +#define GMAC_ISRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_ISRPQ[5]) RX Used Bit Read */ +#define GMAC_ISRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_ISRPQ[5]) Retry Limit Exceeded or Late Collision */ +#define GMAC_ISRPQ_TFC (0x1u << 6) /**< \brief (GMAC_ISRPQ[5]) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_ISRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_ISRPQ[5]) Transmit Complete */ +#define GMAC_ISRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_ISRPQ[5]) Receive Overrun */ +#define GMAC_ISRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_ISRPQ[5]) HRESP Not OK */ +/* -------- GMAC_TBQBAPQ[5] : (GMAC Offset: 0x440) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) -------- */ +#define GMAC_TBQBAPQ_TXBQBA_Pos 2 +#define GMAC_TBQBAPQ_TXBQBA_Msk (0x3fffffffu << GMAC_TBQBAPQ_TXBQBA_Pos) /**< \brief (GMAC_TBQBAPQ[5]) Transmit Buffer Queue Base Address */ +#define GMAC_TBQBAPQ_TXBQBA(value) ((GMAC_TBQBAPQ_TXBQBA_Msk & ((value) << GMAC_TBQBAPQ_TXBQBA_Pos))) +/* -------- GMAC_RBQBAPQ[5] : (GMAC Offset: 0x480) Receive Buffer Queue Base Address Register Priority Queue (index = 1) -------- */ +#define GMAC_RBQBAPQ_RXBQBA_Pos 2 +#define GMAC_RBQBAPQ_RXBQBA_Msk (0x3fffffffu << GMAC_RBQBAPQ_RXBQBA_Pos) /**< \brief (GMAC_RBQBAPQ[5]) Receive Buffer Queue Base Address */ +#define GMAC_RBQBAPQ_RXBQBA(value) ((GMAC_RBQBAPQ_RXBQBA_Msk & ((value) << GMAC_RBQBAPQ_RXBQBA_Pos))) +/* -------- GMAC_RBSRPQ[5] : (GMAC Offset: 0x4A0) Receive Buffer Size Register Priority Queue (index = 1) -------- */ +#define GMAC_RBSRPQ_RBS_Pos 0 +#define GMAC_RBSRPQ_RBS_Msk (0xffffu << GMAC_RBSRPQ_RBS_Pos) /**< \brief (GMAC_RBSRPQ[5]) Receive Buffer Size */ +#define GMAC_RBSRPQ_RBS(value) ((GMAC_RBSRPQ_RBS_Msk & ((value) << GMAC_RBSRPQ_RBS_Pos))) +/* -------- GMAC_CBSCR : (GMAC Offset: 0x4BC) Credit-Based Shaping Control Register -------- */ +#define GMAC_CBSCR_QBE (0x1u << 0) /**< \brief (GMAC_CBSCR) Queue B CBS Enable */ +#define GMAC_CBSCR_QAE (0x1u << 1) /**< \brief (GMAC_CBSCR) Queue A CBS Enable */ +/* -------- GMAC_CBSISQA : (GMAC Offset: 0x4C0) Credit-Based Shaping IdleSlope Register for Queue A -------- */ +#define GMAC_CBSISQA_IS_Pos 0 +#define GMAC_CBSISQA_IS_Msk (0xffffffffu << GMAC_CBSISQA_IS_Pos) /**< \brief (GMAC_CBSISQA) IdleSlope */ +#define GMAC_CBSISQA_IS(value) ((GMAC_CBSISQA_IS_Msk & ((value) << GMAC_CBSISQA_IS_Pos))) +/* -------- GMAC_CBSISQB : (GMAC Offset: 0x4C4) Credit-Based Shaping IdleSlope Register for Queue B -------- */ +#define GMAC_CBSISQB_IS_Pos 0 +#define GMAC_CBSISQB_IS_Msk (0xffffffffu << GMAC_CBSISQB_IS_Pos) /**< \brief (GMAC_CBSISQB) IdleSlope */ +#define GMAC_CBSISQB_IS(value) ((GMAC_CBSISQB_IS_Msk & ((value) << GMAC_CBSISQB_IS_Pos))) +/* -------- GMAC_ST1RPQ[4] : (GMAC Offset: 0x500) Screening Type 1 Register Priority Queue (index = 0) -------- */ +#define GMAC_ST1RPQ_QNB_Pos 0 +#define GMAC_ST1RPQ_QNB_Msk (0x7u << GMAC_ST1RPQ_QNB_Pos) /**< \brief (GMAC_ST1RPQ[4]) Queue Number (0-5) */ +#define GMAC_ST1RPQ_QNB(value) ((GMAC_ST1RPQ_QNB_Msk & ((value) << GMAC_ST1RPQ_QNB_Pos))) +#define GMAC_ST1RPQ_DSTCM_Pos 4 +#define GMAC_ST1RPQ_DSTCM_Msk (0xffu << GMAC_ST1RPQ_DSTCM_Pos) /**< \brief (GMAC_ST1RPQ[4]) Differentiated Services or Traffic Class Match */ +#define GMAC_ST1RPQ_DSTCM(value) ((GMAC_ST1RPQ_DSTCM_Msk & ((value) << GMAC_ST1RPQ_DSTCM_Pos))) +#define GMAC_ST1RPQ_UDPM_Pos 12 +#define GMAC_ST1RPQ_UDPM_Msk (0xffffu << GMAC_ST1RPQ_UDPM_Pos) /**< \brief (GMAC_ST1RPQ[4]) UDP Port Match */ +#define GMAC_ST1RPQ_UDPM(value) ((GMAC_ST1RPQ_UDPM_Msk & ((value) << GMAC_ST1RPQ_UDPM_Pos))) +#define GMAC_ST1RPQ_DSTCE (0x1u << 28) /**< \brief (GMAC_ST1RPQ[4]) Differentiated Services or Traffic Class Match Enable */ +#define GMAC_ST1RPQ_UDPE (0x1u << 29) /**< \brief (GMAC_ST1RPQ[4]) UDP Port Match Enable */ +/* -------- GMAC_ST2RPQ[8] : (GMAC Offset: 0x540) Screening Type 2 Register Priority Queue (index = 0) -------- */ +#define GMAC_ST2RPQ_QNB_Pos 0 +#define GMAC_ST2RPQ_QNB_Msk (0x7u << GMAC_ST2RPQ_QNB_Pos) /**< \brief (GMAC_ST2RPQ[8]) Queue Number (0-5) */ +#define GMAC_ST2RPQ_QNB(value) ((GMAC_ST2RPQ_QNB_Msk & ((value) << GMAC_ST2RPQ_QNB_Pos))) +#define GMAC_ST2RPQ_VLANP_Pos 4 +#define GMAC_ST2RPQ_VLANP_Msk (0x7u << GMAC_ST2RPQ_VLANP_Pos) /**< \brief (GMAC_ST2RPQ[8]) VLAN Priority */ +#define GMAC_ST2RPQ_VLANP(value) ((GMAC_ST2RPQ_VLANP_Msk & ((value) << GMAC_ST2RPQ_VLANP_Pos))) +#define GMAC_ST2RPQ_VLANE (0x1u << 8) /**< \brief (GMAC_ST2RPQ[8]) VLAN Enable */ +#define GMAC_ST2RPQ_I2ETH_Pos 9 +#define GMAC_ST2RPQ_I2ETH_Msk (0x7u << GMAC_ST2RPQ_I2ETH_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 EtherType register x */ +#define GMAC_ST2RPQ_I2ETH(value) ((GMAC_ST2RPQ_I2ETH_Msk & ((value) << GMAC_ST2RPQ_I2ETH_Pos))) +#define GMAC_ST2RPQ_ETHE (0x1u << 12) /**< \brief (GMAC_ST2RPQ[8]) EtherType Enable */ +#define GMAC_ST2RPQ_COMPA_Pos 13 +#define GMAC_ST2RPQ_COMPA_Msk (0x1fu << GMAC_ST2RPQ_COMPA_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 Compare Word 0/Word 1 register x */ +#define GMAC_ST2RPQ_COMPA(value) ((GMAC_ST2RPQ_COMPA_Msk & ((value) << GMAC_ST2RPQ_COMPA_Pos))) +#define GMAC_ST2RPQ_COMPAE (0x1u << 18) /**< \brief (GMAC_ST2RPQ[8]) Compare A Enable */ +#define GMAC_ST2RPQ_COMPB_Pos 19 +#define GMAC_ST2RPQ_COMPB_Msk (0x1fu << GMAC_ST2RPQ_COMPB_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 Compare Word 0/Word 1 register x */ +#define GMAC_ST2RPQ_COMPB(value) ((GMAC_ST2RPQ_COMPB_Msk & ((value) << GMAC_ST2RPQ_COMPB_Pos))) +#define GMAC_ST2RPQ_COMPBE (0x1u << 24) /**< \brief (GMAC_ST2RPQ[8]) Compare B Enable */ +#define GMAC_ST2RPQ_COMPC_Pos 25 +#define GMAC_ST2RPQ_COMPC_Msk (0x1fu << GMAC_ST2RPQ_COMPC_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 Compare Word 0/Word 1 register x */ +#define GMAC_ST2RPQ_COMPC(value) ((GMAC_ST2RPQ_COMPC_Msk & ((value) << GMAC_ST2RPQ_COMPC_Pos))) +#define GMAC_ST2RPQ_COMPCE (0x1u << 30) /**< \brief (GMAC_ST2RPQ[8]) Compare C Enable */ +/* -------- GMAC_IERPQ[5] : (GMAC Offset: 0x5FC) Interrupt Enable Register Priority Queue (index = 1) -------- */ +#define GMAC_IERPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IERPQ[5]) Receive Complete */ +#define GMAC_IERPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IERPQ[5]) RX Used Bit Read */ +#define GMAC_IERPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IERPQ[5]) Retry Limit Exceeded or Late Collision */ +#define GMAC_IERPQ_TFC (0x1u << 6) /**< \brief (GMAC_IERPQ[5]) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IERPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IERPQ[5]) Transmit Complete */ +#define GMAC_IERPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IERPQ[5]) Receive Overrun */ +#define GMAC_IERPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IERPQ[5]) HRESP Not OK */ +/* -------- GMAC_IDRPQ[5] : (GMAC Offset: 0x61C) Interrupt Disable Register Priority Queue (index = 1) -------- */ +#define GMAC_IDRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IDRPQ[5]) Receive Complete */ +#define GMAC_IDRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IDRPQ[5]) RX Used Bit Read */ +#define GMAC_IDRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IDRPQ[5]) Retry Limit Exceeded or Late Collision */ +#define GMAC_IDRPQ_TFC (0x1u << 6) /**< \brief (GMAC_IDRPQ[5]) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IDRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IDRPQ[5]) Transmit Complete */ +#define GMAC_IDRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IDRPQ[5]) Receive Overrun */ +#define GMAC_IDRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IDRPQ[5]) HRESP Not OK */ +/* -------- GMAC_IMRPQ[5] : (GMAC Offset: 0x63C) Interrupt Mask Register Priority Queue (index = 1) -------- */ +#define GMAC_IMRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IMRPQ[5]) Receive Complete */ +#define GMAC_IMRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IMRPQ[5]) RX Used Bit Read */ +#define GMAC_IMRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IMRPQ[5]) Retry Limit Exceeded or Late Collision */ +#define GMAC_IMRPQ_AHB (0x1u << 6) /**< \brief (GMAC_IMRPQ[5]) AHB Error */ +#define GMAC_IMRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IMRPQ[5]) Transmit Complete */ +#define GMAC_IMRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IMRPQ[5]) Receive Overrun */ +#define GMAC_IMRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IMRPQ[5]) HRESP Not OK */ +/* -------- GMAC_ST2ER[4] : (GMAC Offset: 0x6E0) Screening Type 2 Ethertype Register (index = 0) -------- */ +#define GMAC_ST2ER_COMPVAL_Pos 0 +#define GMAC_ST2ER_COMPVAL_Msk (0xffffu << GMAC_ST2ER_COMPVAL_Pos) /**< \brief (GMAC_ST2ER[4]) Ethertype Compare Value */ +#define GMAC_ST2ER_COMPVAL(value) ((GMAC_ST2ER_COMPVAL_Msk & ((value) << GMAC_ST2ER_COMPVAL_Pos))) +/* -------- GMAC_ST2CW00 : (GMAC Offset: 0x700) Screening Type 2 Compare Word 0 Register (index = 0) -------- */ +#define GMAC_ST2CW00_MASKVAL_Pos 0 +#define GMAC_ST2CW00_MASKVAL_Msk (0xffffu << GMAC_ST2CW00_MASKVAL_Pos) /**< \brief (GMAC_ST2CW00) Mask Value */ +#define GMAC_ST2CW00_MASKVAL(value) ((GMAC_ST2CW00_MASKVAL_Msk & ((value) << GMAC_ST2CW00_MASKVAL_Pos))) +#define GMAC_ST2CW00_COMPVAL_Pos 16 +#define GMAC_ST2CW00_COMPVAL_Msk (0xffffu << GMAC_ST2CW00_COMPVAL_Pos) /**< \brief (GMAC_ST2CW00) Compare Value */ +#define GMAC_ST2CW00_COMPVAL(value) ((GMAC_ST2CW00_COMPVAL_Msk & ((value) << GMAC_ST2CW00_COMPVAL_Pos))) +/* -------- GMAC_ST2CW10 : (GMAC Offset: 0x704) Screening Type 2 Compare Word 1 Register (index = 0) -------- */ +#define GMAC_ST2CW10_OFFSVAL_Pos 0 +#define GMAC_ST2CW10_OFFSVAL_Msk (0x7fu << GMAC_ST2CW10_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW10) Offset Value in Bytes */ +#define GMAC_ST2CW10_OFFSVAL(value) ((GMAC_ST2CW10_OFFSVAL_Msk & ((value) << GMAC_ST2CW10_OFFSVAL_Pos))) +#define GMAC_ST2CW10_OFFSSTRT_Pos 7 +#define GMAC_ST2CW10_OFFSSTRT_Msk (0x3u << GMAC_ST2CW10_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW10) Ethernet Frame Offset Start */ +#define GMAC_ST2CW10_OFFSSTRT(value) ((GMAC_ST2CW10_OFFSSTRT_Msk & ((value) << GMAC_ST2CW10_OFFSSTRT_Pos))) +#define GMAC_ST2CW10_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW10) Offset from the start of the frame */ +#define GMAC_ST2CW10_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW10) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW10_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW10) Offset from the byte after the IP header field */ +#define GMAC_ST2CW10_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW10) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW01 : (GMAC Offset: 0x708) Screening Type 2 Compare Word 0 Register (index = 1) -------- */ +#define GMAC_ST2CW01_MASKVAL_Pos 0 +#define GMAC_ST2CW01_MASKVAL_Msk (0xffffu << GMAC_ST2CW01_MASKVAL_Pos) /**< \brief (GMAC_ST2CW01) Mask Value */ +#define GMAC_ST2CW01_MASKVAL(value) ((GMAC_ST2CW01_MASKVAL_Msk & ((value) << GMAC_ST2CW01_MASKVAL_Pos))) +#define GMAC_ST2CW01_COMPVAL_Pos 16 +#define GMAC_ST2CW01_COMPVAL_Msk (0xffffu << GMAC_ST2CW01_COMPVAL_Pos) /**< \brief (GMAC_ST2CW01) Compare Value */ +#define GMAC_ST2CW01_COMPVAL(value) ((GMAC_ST2CW01_COMPVAL_Msk & ((value) << GMAC_ST2CW01_COMPVAL_Pos))) +/* -------- GMAC_ST2CW11 : (GMAC Offset: 0x70C) Screening Type 2 Compare Word 1 Register (index = 1) -------- */ +#define GMAC_ST2CW11_OFFSVAL_Pos 0 +#define GMAC_ST2CW11_OFFSVAL_Msk (0x7fu << GMAC_ST2CW11_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW11) Offset Value in Bytes */ +#define GMAC_ST2CW11_OFFSVAL(value) ((GMAC_ST2CW11_OFFSVAL_Msk & ((value) << GMAC_ST2CW11_OFFSVAL_Pos))) +#define GMAC_ST2CW11_OFFSSTRT_Pos 7 +#define GMAC_ST2CW11_OFFSSTRT_Msk (0x3u << GMAC_ST2CW11_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW11) Ethernet Frame Offset Start */ +#define GMAC_ST2CW11_OFFSSTRT(value) ((GMAC_ST2CW11_OFFSSTRT_Msk & ((value) << GMAC_ST2CW11_OFFSSTRT_Pos))) +#define GMAC_ST2CW11_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW11) Offset from the start of the frame */ +#define GMAC_ST2CW11_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW11) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW11_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW11) Offset from the byte after the IP header field */ +#define GMAC_ST2CW11_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW11) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW02 : (GMAC Offset: 0x710) Screening Type 2 Compare Word 0 Register (index = 2) -------- */ +#define GMAC_ST2CW02_MASKVAL_Pos 0 +#define GMAC_ST2CW02_MASKVAL_Msk (0xffffu << GMAC_ST2CW02_MASKVAL_Pos) /**< \brief (GMAC_ST2CW02) Mask Value */ +#define GMAC_ST2CW02_MASKVAL(value) ((GMAC_ST2CW02_MASKVAL_Msk & ((value) << GMAC_ST2CW02_MASKVAL_Pos))) +#define GMAC_ST2CW02_COMPVAL_Pos 16 +#define GMAC_ST2CW02_COMPVAL_Msk (0xffffu << GMAC_ST2CW02_COMPVAL_Pos) /**< \brief (GMAC_ST2CW02) Compare Value */ +#define GMAC_ST2CW02_COMPVAL(value) ((GMAC_ST2CW02_COMPVAL_Msk & ((value) << GMAC_ST2CW02_COMPVAL_Pos))) +/* -------- GMAC_ST2CW12 : (GMAC Offset: 0x714) Screening Type 2 Compare Word 1 Register (index = 2) -------- */ +#define GMAC_ST2CW12_OFFSVAL_Pos 0 +#define GMAC_ST2CW12_OFFSVAL_Msk (0x7fu << GMAC_ST2CW12_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW12) Offset Value in Bytes */ +#define GMAC_ST2CW12_OFFSVAL(value) ((GMAC_ST2CW12_OFFSVAL_Msk & ((value) << GMAC_ST2CW12_OFFSVAL_Pos))) +#define GMAC_ST2CW12_OFFSSTRT_Pos 7 +#define GMAC_ST2CW12_OFFSSTRT_Msk (0x3u << GMAC_ST2CW12_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW12) Ethernet Frame Offset Start */ +#define GMAC_ST2CW12_OFFSSTRT(value) ((GMAC_ST2CW12_OFFSSTRT_Msk & ((value) << GMAC_ST2CW12_OFFSSTRT_Pos))) +#define GMAC_ST2CW12_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW12) Offset from the start of the frame */ +#define GMAC_ST2CW12_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW12) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW12_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW12) Offset from the byte after the IP header field */ +#define GMAC_ST2CW12_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW12) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW03 : (GMAC Offset: 0x718) Screening Type 2 Compare Word 0 Register (index = 3) -------- */ +#define GMAC_ST2CW03_MASKVAL_Pos 0 +#define GMAC_ST2CW03_MASKVAL_Msk (0xffffu << GMAC_ST2CW03_MASKVAL_Pos) /**< \brief (GMAC_ST2CW03) Mask Value */ +#define GMAC_ST2CW03_MASKVAL(value) ((GMAC_ST2CW03_MASKVAL_Msk & ((value) << GMAC_ST2CW03_MASKVAL_Pos))) +#define GMAC_ST2CW03_COMPVAL_Pos 16 +#define GMAC_ST2CW03_COMPVAL_Msk (0xffffu << GMAC_ST2CW03_COMPVAL_Pos) /**< \brief (GMAC_ST2CW03) Compare Value */ +#define GMAC_ST2CW03_COMPVAL(value) ((GMAC_ST2CW03_COMPVAL_Msk & ((value) << GMAC_ST2CW03_COMPVAL_Pos))) +/* -------- GMAC_ST2CW13 : (GMAC Offset: 0x71C) Screening Type 2 Compare Word 1 Register (index = 3) -------- */ +#define GMAC_ST2CW13_OFFSVAL_Pos 0 +#define GMAC_ST2CW13_OFFSVAL_Msk (0x7fu << GMAC_ST2CW13_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW13) Offset Value in Bytes */ +#define GMAC_ST2CW13_OFFSVAL(value) ((GMAC_ST2CW13_OFFSVAL_Msk & ((value) << GMAC_ST2CW13_OFFSVAL_Pos))) +#define GMAC_ST2CW13_OFFSSTRT_Pos 7 +#define GMAC_ST2CW13_OFFSSTRT_Msk (0x3u << GMAC_ST2CW13_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW13) Ethernet Frame Offset Start */ +#define GMAC_ST2CW13_OFFSSTRT(value) ((GMAC_ST2CW13_OFFSSTRT_Msk & ((value) << GMAC_ST2CW13_OFFSSTRT_Pos))) +#define GMAC_ST2CW13_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW13) Offset from the start of the frame */ +#define GMAC_ST2CW13_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW13) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW13_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW13) Offset from the byte after the IP header field */ +#define GMAC_ST2CW13_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW13) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW04 : (GMAC Offset: 0x720) Screening Type 2 Compare Word 0 Register (index = 4) -------- */ +#define GMAC_ST2CW04_MASKVAL_Pos 0 +#define GMAC_ST2CW04_MASKVAL_Msk (0xffffu << GMAC_ST2CW04_MASKVAL_Pos) /**< \brief (GMAC_ST2CW04) Mask Value */ +#define GMAC_ST2CW04_MASKVAL(value) ((GMAC_ST2CW04_MASKVAL_Msk & ((value) << GMAC_ST2CW04_MASKVAL_Pos))) +#define GMAC_ST2CW04_COMPVAL_Pos 16 +#define GMAC_ST2CW04_COMPVAL_Msk (0xffffu << GMAC_ST2CW04_COMPVAL_Pos) /**< \brief (GMAC_ST2CW04) Compare Value */ +#define GMAC_ST2CW04_COMPVAL(value) ((GMAC_ST2CW04_COMPVAL_Msk & ((value) << GMAC_ST2CW04_COMPVAL_Pos))) +/* -------- GMAC_ST2CW14 : (GMAC Offset: 0x724) Screening Type 2 Compare Word 1 Register (index = 4) -------- */ +#define GMAC_ST2CW14_OFFSVAL_Pos 0 +#define GMAC_ST2CW14_OFFSVAL_Msk (0x7fu << GMAC_ST2CW14_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW14) Offset Value in Bytes */ +#define GMAC_ST2CW14_OFFSVAL(value) ((GMAC_ST2CW14_OFFSVAL_Msk & ((value) << GMAC_ST2CW14_OFFSVAL_Pos))) +#define GMAC_ST2CW14_OFFSSTRT_Pos 7 +#define GMAC_ST2CW14_OFFSSTRT_Msk (0x3u << GMAC_ST2CW14_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW14) Ethernet Frame Offset Start */ +#define GMAC_ST2CW14_OFFSSTRT(value) ((GMAC_ST2CW14_OFFSSTRT_Msk & ((value) << GMAC_ST2CW14_OFFSSTRT_Pos))) +#define GMAC_ST2CW14_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW14) Offset from the start of the frame */ +#define GMAC_ST2CW14_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW14) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW14_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW14) Offset from the byte after the IP header field */ +#define GMAC_ST2CW14_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW14) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW05 : (GMAC Offset: 0x728) Screening Type 2 Compare Word 0 Register (index = 5) -------- */ +#define GMAC_ST2CW05_MASKVAL_Pos 0 +#define GMAC_ST2CW05_MASKVAL_Msk (0xffffu << GMAC_ST2CW05_MASKVAL_Pos) /**< \brief (GMAC_ST2CW05) Mask Value */ +#define GMAC_ST2CW05_MASKVAL(value) ((GMAC_ST2CW05_MASKVAL_Msk & ((value) << GMAC_ST2CW05_MASKVAL_Pos))) +#define GMAC_ST2CW05_COMPVAL_Pos 16 +#define GMAC_ST2CW05_COMPVAL_Msk (0xffffu << GMAC_ST2CW05_COMPVAL_Pos) /**< \brief (GMAC_ST2CW05) Compare Value */ +#define GMAC_ST2CW05_COMPVAL(value) ((GMAC_ST2CW05_COMPVAL_Msk & ((value) << GMAC_ST2CW05_COMPVAL_Pos))) +/* -------- GMAC_ST2CW15 : (GMAC Offset: 0x72C) Screening Type 2 Compare Word 1 Register (index = 5) -------- */ +#define GMAC_ST2CW15_OFFSVAL_Pos 0 +#define GMAC_ST2CW15_OFFSVAL_Msk (0x7fu << GMAC_ST2CW15_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW15) Offset Value in Bytes */ +#define GMAC_ST2CW15_OFFSVAL(value) ((GMAC_ST2CW15_OFFSVAL_Msk & ((value) << GMAC_ST2CW15_OFFSVAL_Pos))) +#define GMAC_ST2CW15_OFFSSTRT_Pos 7 +#define GMAC_ST2CW15_OFFSSTRT_Msk (0x3u << GMAC_ST2CW15_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW15) Ethernet Frame Offset Start */ +#define GMAC_ST2CW15_OFFSSTRT(value) ((GMAC_ST2CW15_OFFSSTRT_Msk & ((value) << GMAC_ST2CW15_OFFSSTRT_Pos))) +#define GMAC_ST2CW15_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW15) Offset from the start of the frame */ +#define GMAC_ST2CW15_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW15) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW15_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW15) Offset from the byte after the IP header field */ +#define GMAC_ST2CW15_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW15) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW06 : (GMAC Offset: 0x730) Screening Type 2 Compare Word 0 Register (index = 6) -------- */ +#define GMAC_ST2CW06_MASKVAL_Pos 0 +#define GMAC_ST2CW06_MASKVAL_Msk (0xffffu << GMAC_ST2CW06_MASKVAL_Pos) /**< \brief (GMAC_ST2CW06) Mask Value */ +#define GMAC_ST2CW06_MASKVAL(value) ((GMAC_ST2CW06_MASKVAL_Msk & ((value) << GMAC_ST2CW06_MASKVAL_Pos))) +#define GMAC_ST2CW06_COMPVAL_Pos 16 +#define GMAC_ST2CW06_COMPVAL_Msk (0xffffu << GMAC_ST2CW06_COMPVAL_Pos) /**< \brief (GMAC_ST2CW06) Compare Value */ +#define GMAC_ST2CW06_COMPVAL(value) ((GMAC_ST2CW06_COMPVAL_Msk & ((value) << GMAC_ST2CW06_COMPVAL_Pos))) +/* -------- GMAC_ST2CW16 : (GMAC Offset: 0x734) Screening Type 2 Compare Word 1 Register (index = 6) -------- */ +#define GMAC_ST2CW16_OFFSVAL_Pos 0 +#define GMAC_ST2CW16_OFFSVAL_Msk (0x7fu << GMAC_ST2CW16_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW16) Offset Value in Bytes */ +#define GMAC_ST2CW16_OFFSVAL(value) ((GMAC_ST2CW16_OFFSVAL_Msk & ((value) << GMAC_ST2CW16_OFFSVAL_Pos))) +#define GMAC_ST2CW16_OFFSSTRT_Pos 7 +#define GMAC_ST2CW16_OFFSSTRT_Msk (0x3u << GMAC_ST2CW16_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW16) Ethernet Frame Offset Start */ +#define GMAC_ST2CW16_OFFSSTRT(value) ((GMAC_ST2CW16_OFFSSTRT_Msk & ((value) << GMAC_ST2CW16_OFFSSTRT_Pos))) +#define GMAC_ST2CW16_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW16) Offset from the start of the frame */ +#define GMAC_ST2CW16_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW16) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW16_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW16) Offset from the byte after the IP header field */ +#define GMAC_ST2CW16_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW16) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW07 : (GMAC Offset: 0x738) Screening Type 2 Compare Word 0 Register (index = 7) -------- */ +#define GMAC_ST2CW07_MASKVAL_Pos 0 +#define GMAC_ST2CW07_MASKVAL_Msk (0xffffu << GMAC_ST2CW07_MASKVAL_Pos) /**< \brief (GMAC_ST2CW07) Mask Value */ +#define GMAC_ST2CW07_MASKVAL(value) ((GMAC_ST2CW07_MASKVAL_Msk & ((value) << GMAC_ST2CW07_MASKVAL_Pos))) +#define GMAC_ST2CW07_COMPVAL_Pos 16 +#define GMAC_ST2CW07_COMPVAL_Msk (0xffffu << GMAC_ST2CW07_COMPVAL_Pos) /**< \brief (GMAC_ST2CW07) Compare Value */ +#define GMAC_ST2CW07_COMPVAL(value) ((GMAC_ST2CW07_COMPVAL_Msk & ((value) << GMAC_ST2CW07_COMPVAL_Pos))) +/* -------- GMAC_ST2CW17 : (GMAC Offset: 0x73C) Screening Type 2 Compare Word 1 Register (index = 7) -------- */ +#define GMAC_ST2CW17_OFFSVAL_Pos 0 +#define GMAC_ST2CW17_OFFSVAL_Msk (0x7fu << GMAC_ST2CW17_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW17) Offset Value in Bytes */ +#define GMAC_ST2CW17_OFFSVAL(value) ((GMAC_ST2CW17_OFFSVAL_Msk & ((value) << GMAC_ST2CW17_OFFSVAL_Pos))) +#define GMAC_ST2CW17_OFFSSTRT_Pos 7 +#define GMAC_ST2CW17_OFFSSTRT_Msk (0x3u << GMAC_ST2CW17_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW17) Ethernet Frame Offset Start */ +#define GMAC_ST2CW17_OFFSSTRT(value) ((GMAC_ST2CW17_OFFSSTRT_Msk & ((value) << GMAC_ST2CW17_OFFSSTRT_Pos))) +#define GMAC_ST2CW17_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW17) Offset from the start of the frame */ +#define GMAC_ST2CW17_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW17) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW17_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW17) Offset from the byte after the IP header field */ +#define GMAC_ST2CW17_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW17) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW08 : (GMAC Offset: 0x740) Screening Type 2 Compare Word 0 Register (index = 8) -------- */ +#define GMAC_ST2CW08_MASKVAL_Pos 0 +#define GMAC_ST2CW08_MASKVAL_Msk (0xffffu << GMAC_ST2CW08_MASKVAL_Pos) /**< \brief (GMAC_ST2CW08) Mask Value */ +#define GMAC_ST2CW08_MASKVAL(value) ((GMAC_ST2CW08_MASKVAL_Msk & ((value) << GMAC_ST2CW08_MASKVAL_Pos))) +#define GMAC_ST2CW08_COMPVAL_Pos 16 +#define GMAC_ST2CW08_COMPVAL_Msk (0xffffu << GMAC_ST2CW08_COMPVAL_Pos) /**< \brief (GMAC_ST2CW08) Compare Value */ +#define GMAC_ST2CW08_COMPVAL(value) ((GMAC_ST2CW08_COMPVAL_Msk & ((value) << GMAC_ST2CW08_COMPVAL_Pos))) +/* -------- GMAC_ST2CW18 : (GMAC Offset: 0x744) Screening Type 2 Compare Word 1 Register (index = 8) -------- */ +#define GMAC_ST2CW18_OFFSVAL_Pos 0 +#define GMAC_ST2CW18_OFFSVAL_Msk (0x7fu << GMAC_ST2CW18_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW18) Offset Value in Bytes */ +#define GMAC_ST2CW18_OFFSVAL(value) ((GMAC_ST2CW18_OFFSVAL_Msk & ((value) << GMAC_ST2CW18_OFFSVAL_Pos))) +#define GMAC_ST2CW18_OFFSSTRT_Pos 7 +#define GMAC_ST2CW18_OFFSSTRT_Msk (0x3u << GMAC_ST2CW18_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW18) Ethernet Frame Offset Start */ +#define GMAC_ST2CW18_OFFSSTRT(value) ((GMAC_ST2CW18_OFFSSTRT_Msk & ((value) << GMAC_ST2CW18_OFFSSTRT_Pos))) +#define GMAC_ST2CW18_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW18) Offset from the start of the frame */ +#define GMAC_ST2CW18_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW18) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW18_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW18) Offset from the byte after the IP header field */ +#define GMAC_ST2CW18_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW18) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW09 : (GMAC Offset: 0x748) Screening Type 2 Compare Word 0 Register (index = 9) -------- */ +#define GMAC_ST2CW09_MASKVAL_Pos 0 +#define GMAC_ST2CW09_MASKVAL_Msk (0xffffu << GMAC_ST2CW09_MASKVAL_Pos) /**< \brief (GMAC_ST2CW09) Mask Value */ +#define GMAC_ST2CW09_MASKVAL(value) ((GMAC_ST2CW09_MASKVAL_Msk & ((value) << GMAC_ST2CW09_MASKVAL_Pos))) +#define GMAC_ST2CW09_COMPVAL_Pos 16 +#define GMAC_ST2CW09_COMPVAL_Msk (0xffffu << GMAC_ST2CW09_COMPVAL_Pos) /**< \brief (GMAC_ST2CW09) Compare Value */ +#define GMAC_ST2CW09_COMPVAL(value) ((GMAC_ST2CW09_COMPVAL_Msk & ((value) << GMAC_ST2CW09_COMPVAL_Pos))) +/* -------- GMAC_ST2CW19 : (GMAC Offset: 0x74C) Screening Type 2 Compare Word 1 Register (index = 9) -------- */ +#define GMAC_ST2CW19_OFFSVAL_Pos 0 +#define GMAC_ST2CW19_OFFSVAL_Msk (0x7fu << GMAC_ST2CW19_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW19) Offset Value in Bytes */ +#define GMAC_ST2CW19_OFFSVAL(value) ((GMAC_ST2CW19_OFFSVAL_Msk & ((value) << GMAC_ST2CW19_OFFSVAL_Pos))) +#define GMAC_ST2CW19_OFFSSTRT_Pos 7 +#define GMAC_ST2CW19_OFFSSTRT_Msk (0x3u << GMAC_ST2CW19_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW19) Ethernet Frame Offset Start */ +#define GMAC_ST2CW19_OFFSSTRT(value) ((GMAC_ST2CW19_OFFSSTRT_Msk & ((value) << GMAC_ST2CW19_OFFSSTRT_Pos))) +#define GMAC_ST2CW19_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW19) Offset from the start of the frame */ +#define GMAC_ST2CW19_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW19) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW19_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW19) Offset from the byte after the IP header field */ +#define GMAC_ST2CW19_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW19) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW010 : (GMAC Offset: 0x750) Screening Type 2 Compare Word 0 Register (index = 10) -------- */ +#define GMAC_ST2CW010_MASKVAL_Pos 0 +#define GMAC_ST2CW010_MASKVAL_Msk (0xffffu << GMAC_ST2CW010_MASKVAL_Pos) /**< \brief (GMAC_ST2CW010) Mask Value */ +#define GMAC_ST2CW010_MASKVAL(value) ((GMAC_ST2CW010_MASKVAL_Msk & ((value) << GMAC_ST2CW010_MASKVAL_Pos))) +#define GMAC_ST2CW010_COMPVAL_Pos 16 +#define GMAC_ST2CW010_COMPVAL_Msk (0xffffu << GMAC_ST2CW010_COMPVAL_Pos) /**< \brief (GMAC_ST2CW010) Compare Value */ +#define GMAC_ST2CW010_COMPVAL(value) ((GMAC_ST2CW010_COMPVAL_Msk & ((value) << GMAC_ST2CW010_COMPVAL_Pos))) +/* -------- GMAC_ST2CW110 : (GMAC Offset: 0x754) Screening Type 2 Compare Word 1 Register (index = 10) -------- */ +#define GMAC_ST2CW110_OFFSVAL_Pos 0 +#define GMAC_ST2CW110_OFFSVAL_Msk (0x7fu << GMAC_ST2CW110_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW110) Offset Value in Bytes */ +#define GMAC_ST2CW110_OFFSVAL(value) ((GMAC_ST2CW110_OFFSVAL_Msk & ((value) << GMAC_ST2CW110_OFFSVAL_Pos))) +#define GMAC_ST2CW110_OFFSSTRT_Pos 7 +#define GMAC_ST2CW110_OFFSSTRT_Msk (0x3u << GMAC_ST2CW110_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW110) Ethernet Frame Offset Start */ +#define GMAC_ST2CW110_OFFSSTRT(value) ((GMAC_ST2CW110_OFFSSTRT_Msk & ((value) << GMAC_ST2CW110_OFFSSTRT_Pos))) +#define GMAC_ST2CW110_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW110) Offset from the start of the frame */ +#define GMAC_ST2CW110_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW110) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW110_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW110) Offset from the byte after the IP header field */ +#define GMAC_ST2CW110_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW110) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW011 : (GMAC Offset: 0x758) Screening Type 2 Compare Word 0 Register (index = 11) -------- */ +#define GMAC_ST2CW011_MASKVAL_Pos 0 +#define GMAC_ST2CW011_MASKVAL_Msk (0xffffu << GMAC_ST2CW011_MASKVAL_Pos) /**< \brief (GMAC_ST2CW011) Mask Value */ +#define GMAC_ST2CW011_MASKVAL(value) ((GMAC_ST2CW011_MASKVAL_Msk & ((value) << GMAC_ST2CW011_MASKVAL_Pos))) +#define GMAC_ST2CW011_COMPVAL_Pos 16 +#define GMAC_ST2CW011_COMPVAL_Msk (0xffffu << GMAC_ST2CW011_COMPVAL_Pos) /**< \brief (GMAC_ST2CW011) Compare Value */ +#define GMAC_ST2CW011_COMPVAL(value) ((GMAC_ST2CW011_COMPVAL_Msk & ((value) << GMAC_ST2CW011_COMPVAL_Pos))) +/* -------- GMAC_ST2CW111 : (GMAC Offset: 0x75C) Screening Type 2 Compare Word 1 Register (index = 11) -------- */ +#define GMAC_ST2CW111_OFFSVAL_Pos 0 +#define GMAC_ST2CW111_OFFSVAL_Msk (0x7fu << GMAC_ST2CW111_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW111) Offset Value in Bytes */ +#define GMAC_ST2CW111_OFFSVAL(value) ((GMAC_ST2CW111_OFFSVAL_Msk & ((value) << GMAC_ST2CW111_OFFSVAL_Pos))) +#define GMAC_ST2CW111_OFFSSTRT_Pos 7 +#define GMAC_ST2CW111_OFFSSTRT_Msk (0x3u << GMAC_ST2CW111_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW111) Ethernet Frame Offset Start */ +#define GMAC_ST2CW111_OFFSSTRT(value) ((GMAC_ST2CW111_OFFSSTRT_Msk & ((value) << GMAC_ST2CW111_OFFSSTRT_Pos))) +#define GMAC_ST2CW111_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW111) Offset from the start of the frame */ +#define GMAC_ST2CW111_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW111) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW111_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW111) Offset from the byte after the IP header field */ +#define GMAC_ST2CW111_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW111) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW012 : (GMAC Offset: 0x760) Screening Type 2 Compare Word 0 Register (index = 12) -------- */ +#define GMAC_ST2CW012_MASKVAL_Pos 0 +#define GMAC_ST2CW012_MASKVAL_Msk (0xffffu << GMAC_ST2CW012_MASKVAL_Pos) /**< \brief (GMAC_ST2CW012) Mask Value */ +#define GMAC_ST2CW012_MASKVAL(value) ((GMAC_ST2CW012_MASKVAL_Msk & ((value) << GMAC_ST2CW012_MASKVAL_Pos))) +#define GMAC_ST2CW012_COMPVAL_Pos 16 +#define GMAC_ST2CW012_COMPVAL_Msk (0xffffu << GMAC_ST2CW012_COMPVAL_Pos) /**< \brief (GMAC_ST2CW012) Compare Value */ +#define GMAC_ST2CW012_COMPVAL(value) ((GMAC_ST2CW012_COMPVAL_Msk & ((value) << GMAC_ST2CW012_COMPVAL_Pos))) +/* -------- GMAC_ST2CW112 : (GMAC Offset: 0x764) Screening Type 2 Compare Word 1 Register (index = 12) -------- */ +#define GMAC_ST2CW112_OFFSVAL_Pos 0 +#define GMAC_ST2CW112_OFFSVAL_Msk (0x7fu << GMAC_ST2CW112_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW112) Offset Value in Bytes */ +#define GMAC_ST2CW112_OFFSVAL(value) ((GMAC_ST2CW112_OFFSVAL_Msk & ((value) << GMAC_ST2CW112_OFFSVAL_Pos))) +#define GMAC_ST2CW112_OFFSSTRT_Pos 7 +#define GMAC_ST2CW112_OFFSSTRT_Msk (0x3u << GMAC_ST2CW112_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW112) Ethernet Frame Offset Start */ +#define GMAC_ST2CW112_OFFSSTRT(value) ((GMAC_ST2CW112_OFFSSTRT_Msk & ((value) << GMAC_ST2CW112_OFFSSTRT_Pos))) +#define GMAC_ST2CW112_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW112) Offset from the start of the frame */ +#define GMAC_ST2CW112_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW112) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW112_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW112) Offset from the byte after the IP header field */ +#define GMAC_ST2CW112_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW112) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW013 : (GMAC Offset: 0x768) Screening Type 2 Compare Word 0 Register (index = 13) -------- */ +#define GMAC_ST2CW013_MASKVAL_Pos 0 +#define GMAC_ST2CW013_MASKVAL_Msk (0xffffu << GMAC_ST2CW013_MASKVAL_Pos) /**< \brief (GMAC_ST2CW013) Mask Value */ +#define GMAC_ST2CW013_MASKVAL(value) ((GMAC_ST2CW013_MASKVAL_Msk & ((value) << GMAC_ST2CW013_MASKVAL_Pos))) +#define GMAC_ST2CW013_COMPVAL_Pos 16 +#define GMAC_ST2CW013_COMPVAL_Msk (0xffffu << GMAC_ST2CW013_COMPVAL_Pos) /**< \brief (GMAC_ST2CW013) Compare Value */ +#define GMAC_ST2CW013_COMPVAL(value) ((GMAC_ST2CW013_COMPVAL_Msk & ((value) << GMAC_ST2CW013_COMPVAL_Pos))) +/* -------- GMAC_ST2CW113 : (GMAC Offset: 0x76C) Screening Type 2 Compare Word 1 Register (index = 13) -------- */ +#define GMAC_ST2CW113_OFFSVAL_Pos 0 +#define GMAC_ST2CW113_OFFSVAL_Msk (0x7fu << GMAC_ST2CW113_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW113) Offset Value in Bytes */ +#define GMAC_ST2CW113_OFFSVAL(value) ((GMAC_ST2CW113_OFFSVAL_Msk & ((value) << GMAC_ST2CW113_OFFSVAL_Pos))) +#define GMAC_ST2CW113_OFFSSTRT_Pos 7 +#define GMAC_ST2CW113_OFFSSTRT_Msk (0x3u << GMAC_ST2CW113_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW113) Ethernet Frame Offset Start */ +#define GMAC_ST2CW113_OFFSSTRT(value) ((GMAC_ST2CW113_OFFSSTRT_Msk & ((value) << GMAC_ST2CW113_OFFSSTRT_Pos))) +#define GMAC_ST2CW113_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW113) Offset from the start of the frame */ +#define GMAC_ST2CW113_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW113) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW113_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW113) Offset from the byte after the IP header field */ +#define GMAC_ST2CW113_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW113) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW014 : (GMAC Offset: 0x770) Screening Type 2 Compare Word 0 Register (index = 14) -------- */ +#define GMAC_ST2CW014_MASKVAL_Pos 0 +#define GMAC_ST2CW014_MASKVAL_Msk (0xffffu << GMAC_ST2CW014_MASKVAL_Pos) /**< \brief (GMAC_ST2CW014) Mask Value */ +#define GMAC_ST2CW014_MASKVAL(value) ((GMAC_ST2CW014_MASKVAL_Msk & ((value) << GMAC_ST2CW014_MASKVAL_Pos))) +#define GMAC_ST2CW014_COMPVAL_Pos 16 +#define GMAC_ST2CW014_COMPVAL_Msk (0xffffu << GMAC_ST2CW014_COMPVAL_Pos) /**< \brief (GMAC_ST2CW014) Compare Value */ +#define GMAC_ST2CW014_COMPVAL(value) ((GMAC_ST2CW014_COMPVAL_Msk & ((value) << GMAC_ST2CW014_COMPVAL_Pos))) +/* -------- GMAC_ST2CW114 : (GMAC Offset: 0x774) Screening Type 2 Compare Word 1 Register (index = 14) -------- */ +#define GMAC_ST2CW114_OFFSVAL_Pos 0 +#define GMAC_ST2CW114_OFFSVAL_Msk (0x7fu << GMAC_ST2CW114_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW114) Offset Value in Bytes */ +#define GMAC_ST2CW114_OFFSVAL(value) ((GMAC_ST2CW114_OFFSVAL_Msk & ((value) << GMAC_ST2CW114_OFFSVAL_Pos))) +#define GMAC_ST2CW114_OFFSSTRT_Pos 7 +#define GMAC_ST2CW114_OFFSSTRT_Msk (0x3u << GMAC_ST2CW114_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW114) Ethernet Frame Offset Start */ +#define GMAC_ST2CW114_OFFSSTRT(value) ((GMAC_ST2CW114_OFFSSTRT_Msk & ((value) << GMAC_ST2CW114_OFFSSTRT_Pos))) +#define GMAC_ST2CW114_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW114) Offset from the start of the frame */ +#define GMAC_ST2CW114_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW114) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW114_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW114) Offset from the byte after the IP header field */ +#define GMAC_ST2CW114_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW114) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW015 : (GMAC Offset: 0x778) Screening Type 2 Compare Word 0 Register (index = 15) -------- */ +#define GMAC_ST2CW015_MASKVAL_Pos 0 +#define GMAC_ST2CW015_MASKVAL_Msk (0xffffu << GMAC_ST2CW015_MASKVAL_Pos) /**< \brief (GMAC_ST2CW015) Mask Value */ +#define GMAC_ST2CW015_MASKVAL(value) ((GMAC_ST2CW015_MASKVAL_Msk & ((value) << GMAC_ST2CW015_MASKVAL_Pos))) +#define GMAC_ST2CW015_COMPVAL_Pos 16 +#define GMAC_ST2CW015_COMPVAL_Msk (0xffffu << GMAC_ST2CW015_COMPVAL_Pos) /**< \brief (GMAC_ST2CW015) Compare Value */ +#define GMAC_ST2CW015_COMPVAL(value) ((GMAC_ST2CW015_COMPVAL_Msk & ((value) << GMAC_ST2CW015_COMPVAL_Pos))) +/* -------- GMAC_ST2CW115 : (GMAC Offset: 0x77C) Screening Type 2 Compare Word 1 Register (index = 15) -------- */ +#define GMAC_ST2CW115_OFFSVAL_Pos 0 +#define GMAC_ST2CW115_OFFSVAL_Msk (0x7fu << GMAC_ST2CW115_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW115) Offset Value in Bytes */ +#define GMAC_ST2CW115_OFFSVAL(value) ((GMAC_ST2CW115_OFFSVAL_Msk & ((value) << GMAC_ST2CW115_OFFSVAL_Pos))) +#define GMAC_ST2CW115_OFFSSTRT_Pos 7 +#define GMAC_ST2CW115_OFFSSTRT_Msk (0x3u << GMAC_ST2CW115_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW115) Ethernet Frame Offset Start */ +#define GMAC_ST2CW115_OFFSSTRT(value) ((GMAC_ST2CW115_OFFSSTRT_Msk & ((value) << GMAC_ST2CW115_OFFSSTRT_Pos))) +#define GMAC_ST2CW115_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW115) Offset from the start of the frame */ +#define GMAC_ST2CW115_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW115) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW115_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW115) Offset from the byte after the IP header field */ +#define GMAC_ST2CW115_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW115) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW016 : (GMAC Offset: 0x780) Screening Type 2 Compare Word 0 Register (index = 16) -------- */ +#define GMAC_ST2CW016_MASKVAL_Pos 0 +#define GMAC_ST2CW016_MASKVAL_Msk (0xffffu << GMAC_ST2CW016_MASKVAL_Pos) /**< \brief (GMAC_ST2CW016) Mask Value */ +#define GMAC_ST2CW016_MASKVAL(value) ((GMAC_ST2CW016_MASKVAL_Msk & ((value) << GMAC_ST2CW016_MASKVAL_Pos))) +#define GMAC_ST2CW016_COMPVAL_Pos 16 +#define GMAC_ST2CW016_COMPVAL_Msk (0xffffu << GMAC_ST2CW016_COMPVAL_Pos) /**< \brief (GMAC_ST2CW016) Compare Value */ +#define GMAC_ST2CW016_COMPVAL(value) ((GMAC_ST2CW016_COMPVAL_Msk & ((value) << GMAC_ST2CW016_COMPVAL_Pos))) +/* -------- GMAC_ST2CW116 : (GMAC Offset: 0x784) Screening Type 2 Compare Word 1 Register (index = 16) -------- */ +#define GMAC_ST2CW116_OFFSVAL_Pos 0 +#define GMAC_ST2CW116_OFFSVAL_Msk (0x7fu << GMAC_ST2CW116_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW116) Offset Value in Bytes */ +#define GMAC_ST2CW116_OFFSVAL(value) ((GMAC_ST2CW116_OFFSVAL_Msk & ((value) << GMAC_ST2CW116_OFFSVAL_Pos))) +#define GMAC_ST2CW116_OFFSSTRT_Pos 7 +#define GMAC_ST2CW116_OFFSSTRT_Msk (0x3u << GMAC_ST2CW116_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW116) Ethernet Frame Offset Start */ +#define GMAC_ST2CW116_OFFSSTRT(value) ((GMAC_ST2CW116_OFFSSTRT_Msk & ((value) << GMAC_ST2CW116_OFFSSTRT_Pos))) +#define GMAC_ST2CW116_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW116) Offset from the start of the frame */ +#define GMAC_ST2CW116_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW116) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW116_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW116) Offset from the byte after the IP header field */ +#define GMAC_ST2CW116_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW116) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW017 : (GMAC Offset: 0x788) Screening Type 2 Compare Word 0 Register (index = 17) -------- */ +#define GMAC_ST2CW017_MASKVAL_Pos 0 +#define GMAC_ST2CW017_MASKVAL_Msk (0xffffu << GMAC_ST2CW017_MASKVAL_Pos) /**< \brief (GMAC_ST2CW017) Mask Value */ +#define GMAC_ST2CW017_MASKVAL(value) ((GMAC_ST2CW017_MASKVAL_Msk & ((value) << GMAC_ST2CW017_MASKVAL_Pos))) +#define GMAC_ST2CW017_COMPVAL_Pos 16 +#define GMAC_ST2CW017_COMPVAL_Msk (0xffffu << GMAC_ST2CW017_COMPVAL_Pos) /**< \brief (GMAC_ST2CW017) Compare Value */ +#define GMAC_ST2CW017_COMPVAL(value) ((GMAC_ST2CW017_COMPVAL_Msk & ((value) << GMAC_ST2CW017_COMPVAL_Pos))) +/* -------- GMAC_ST2CW117 : (GMAC Offset: 0x78C) Screening Type 2 Compare Word 1 Register (index = 17) -------- */ +#define GMAC_ST2CW117_OFFSVAL_Pos 0 +#define GMAC_ST2CW117_OFFSVAL_Msk (0x7fu << GMAC_ST2CW117_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW117) Offset Value in Bytes */ +#define GMAC_ST2CW117_OFFSVAL(value) ((GMAC_ST2CW117_OFFSVAL_Msk & ((value) << GMAC_ST2CW117_OFFSVAL_Pos))) +#define GMAC_ST2CW117_OFFSSTRT_Pos 7 +#define GMAC_ST2CW117_OFFSSTRT_Msk (0x3u << GMAC_ST2CW117_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW117) Ethernet Frame Offset Start */ +#define GMAC_ST2CW117_OFFSSTRT(value) ((GMAC_ST2CW117_OFFSSTRT_Msk & ((value) << GMAC_ST2CW117_OFFSSTRT_Pos))) +#define GMAC_ST2CW117_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW117) Offset from the start of the frame */ +#define GMAC_ST2CW117_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW117) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW117_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW117) Offset from the byte after the IP header field */ +#define GMAC_ST2CW117_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW117) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW018 : (GMAC Offset: 0x790) Screening Type 2 Compare Word 0 Register (index = 18) -------- */ +#define GMAC_ST2CW018_MASKVAL_Pos 0 +#define GMAC_ST2CW018_MASKVAL_Msk (0xffffu << GMAC_ST2CW018_MASKVAL_Pos) /**< \brief (GMAC_ST2CW018) Mask Value */ +#define GMAC_ST2CW018_MASKVAL(value) ((GMAC_ST2CW018_MASKVAL_Msk & ((value) << GMAC_ST2CW018_MASKVAL_Pos))) +#define GMAC_ST2CW018_COMPVAL_Pos 16 +#define GMAC_ST2CW018_COMPVAL_Msk (0xffffu << GMAC_ST2CW018_COMPVAL_Pos) /**< \brief (GMAC_ST2CW018) Compare Value */ +#define GMAC_ST2CW018_COMPVAL(value) ((GMAC_ST2CW018_COMPVAL_Msk & ((value) << GMAC_ST2CW018_COMPVAL_Pos))) +/* -------- GMAC_ST2CW118 : (GMAC Offset: 0x794) Screening Type 2 Compare Word 1 Register (index = 18) -------- */ +#define GMAC_ST2CW118_OFFSVAL_Pos 0 +#define GMAC_ST2CW118_OFFSVAL_Msk (0x7fu << GMAC_ST2CW118_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW118) Offset Value in Bytes */ +#define GMAC_ST2CW118_OFFSVAL(value) ((GMAC_ST2CW118_OFFSVAL_Msk & ((value) << GMAC_ST2CW118_OFFSVAL_Pos))) +#define GMAC_ST2CW118_OFFSSTRT_Pos 7 +#define GMAC_ST2CW118_OFFSSTRT_Msk (0x3u << GMAC_ST2CW118_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW118) Ethernet Frame Offset Start */ +#define GMAC_ST2CW118_OFFSSTRT(value) ((GMAC_ST2CW118_OFFSSTRT_Msk & ((value) << GMAC_ST2CW118_OFFSSTRT_Pos))) +#define GMAC_ST2CW118_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW118) Offset from the start of the frame */ +#define GMAC_ST2CW118_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW118) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW118_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW118) Offset from the byte after the IP header field */ +#define GMAC_ST2CW118_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW118) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW019 : (GMAC Offset: 0x798) Screening Type 2 Compare Word 0 Register (index = 19) -------- */ +#define GMAC_ST2CW019_MASKVAL_Pos 0 +#define GMAC_ST2CW019_MASKVAL_Msk (0xffffu << GMAC_ST2CW019_MASKVAL_Pos) /**< \brief (GMAC_ST2CW019) Mask Value */ +#define GMAC_ST2CW019_MASKVAL(value) ((GMAC_ST2CW019_MASKVAL_Msk & ((value) << GMAC_ST2CW019_MASKVAL_Pos))) +#define GMAC_ST2CW019_COMPVAL_Pos 16 +#define GMAC_ST2CW019_COMPVAL_Msk (0xffffu << GMAC_ST2CW019_COMPVAL_Pos) /**< \brief (GMAC_ST2CW019) Compare Value */ +#define GMAC_ST2CW019_COMPVAL(value) ((GMAC_ST2CW019_COMPVAL_Msk & ((value) << GMAC_ST2CW019_COMPVAL_Pos))) +/* -------- GMAC_ST2CW119 : (GMAC Offset: 0x79C) Screening Type 2 Compare Word 1 Register (index = 19) -------- */ +#define GMAC_ST2CW119_OFFSVAL_Pos 0 +#define GMAC_ST2CW119_OFFSVAL_Msk (0x7fu << GMAC_ST2CW119_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW119) Offset Value in Bytes */ +#define GMAC_ST2CW119_OFFSVAL(value) ((GMAC_ST2CW119_OFFSVAL_Msk & ((value) << GMAC_ST2CW119_OFFSVAL_Pos))) +#define GMAC_ST2CW119_OFFSSTRT_Pos 7 +#define GMAC_ST2CW119_OFFSSTRT_Msk (0x3u << GMAC_ST2CW119_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW119) Ethernet Frame Offset Start */ +#define GMAC_ST2CW119_OFFSSTRT(value) ((GMAC_ST2CW119_OFFSSTRT_Msk & ((value) << GMAC_ST2CW119_OFFSSTRT_Pos))) +#define GMAC_ST2CW119_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW119) Offset from the start of the frame */ +#define GMAC_ST2CW119_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW119) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW119_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW119) Offset from the byte after the IP header field */ +#define GMAC_ST2CW119_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW119) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW020 : (GMAC Offset: 0x7A0) Screening Type 2 Compare Word 0 Register (index = 20) -------- */ +#define GMAC_ST2CW020_MASKVAL_Pos 0 +#define GMAC_ST2CW020_MASKVAL_Msk (0xffffu << GMAC_ST2CW020_MASKVAL_Pos) /**< \brief (GMAC_ST2CW020) Mask Value */ +#define GMAC_ST2CW020_MASKVAL(value) ((GMAC_ST2CW020_MASKVAL_Msk & ((value) << GMAC_ST2CW020_MASKVAL_Pos))) +#define GMAC_ST2CW020_COMPVAL_Pos 16 +#define GMAC_ST2CW020_COMPVAL_Msk (0xffffu << GMAC_ST2CW020_COMPVAL_Pos) /**< \brief (GMAC_ST2CW020) Compare Value */ +#define GMAC_ST2CW020_COMPVAL(value) ((GMAC_ST2CW020_COMPVAL_Msk & ((value) << GMAC_ST2CW020_COMPVAL_Pos))) +/* -------- GMAC_ST2CW120 : (GMAC Offset: 0x7A4) Screening Type 2 Compare Word 1 Register (index = 20) -------- */ +#define GMAC_ST2CW120_OFFSVAL_Pos 0 +#define GMAC_ST2CW120_OFFSVAL_Msk (0x7fu << GMAC_ST2CW120_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW120) Offset Value in Bytes */ +#define GMAC_ST2CW120_OFFSVAL(value) ((GMAC_ST2CW120_OFFSVAL_Msk & ((value) << GMAC_ST2CW120_OFFSVAL_Pos))) +#define GMAC_ST2CW120_OFFSSTRT_Pos 7 +#define GMAC_ST2CW120_OFFSSTRT_Msk (0x3u << GMAC_ST2CW120_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW120) Ethernet Frame Offset Start */ +#define GMAC_ST2CW120_OFFSSTRT(value) ((GMAC_ST2CW120_OFFSSTRT_Msk & ((value) << GMAC_ST2CW120_OFFSSTRT_Pos))) +#define GMAC_ST2CW120_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW120) Offset from the start of the frame */ +#define GMAC_ST2CW120_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW120) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW120_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW120) Offset from the byte after the IP header field */ +#define GMAC_ST2CW120_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW120) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW021 : (GMAC Offset: 0x7A8) Screening Type 2 Compare Word 0 Register (index = 21) -------- */ +#define GMAC_ST2CW021_MASKVAL_Pos 0 +#define GMAC_ST2CW021_MASKVAL_Msk (0xffffu << GMAC_ST2CW021_MASKVAL_Pos) /**< \brief (GMAC_ST2CW021) Mask Value */ +#define GMAC_ST2CW021_MASKVAL(value) ((GMAC_ST2CW021_MASKVAL_Msk & ((value) << GMAC_ST2CW021_MASKVAL_Pos))) +#define GMAC_ST2CW021_COMPVAL_Pos 16 +#define GMAC_ST2CW021_COMPVAL_Msk (0xffffu << GMAC_ST2CW021_COMPVAL_Pos) /**< \brief (GMAC_ST2CW021) Compare Value */ +#define GMAC_ST2CW021_COMPVAL(value) ((GMAC_ST2CW021_COMPVAL_Msk & ((value) << GMAC_ST2CW021_COMPVAL_Pos))) +/* -------- GMAC_ST2CW121 : (GMAC Offset: 0x7AC) Screening Type 2 Compare Word 1 Register (index = 21) -------- */ +#define GMAC_ST2CW121_OFFSVAL_Pos 0 +#define GMAC_ST2CW121_OFFSVAL_Msk (0x7fu << GMAC_ST2CW121_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW121) Offset Value in Bytes */ +#define GMAC_ST2CW121_OFFSVAL(value) ((GMAC_ST2CW121_OFFSVAL_Msk & ((value) << GMAC_ST2CW121_OFFSVAL_Pos))) +#define GMAC_ST2CW121_OFFSSTRT_Pos 7 +#define GMAC_ST2CW121_OFFSSTRT_Msk (0x3u << GMAC_ST2CW121_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW121) Ethernet Frame Offset Start */ +#define GMAC_ST2CW121_OFFSSTRT(value) ((GMAC_ST2CW121_OFFSSTRT_Msk & ((value) << GMAC_ST2CW121_OFFSSTRT_Pos))) +#define GMAC_ST2CW121_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW121) Offset from the start of the frame */ +#define GMAC_ST2CW121_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW121) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW121_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW121) Offset from the byte after the IP header field */ +#define GMAC_ST2CW121_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW121) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW022 : (GMAC Offset: 0x7B0) Screening Type 2 Compare Word 0 Register (index = 22) -------- */ +#define GMAC_ST2CW022_MASKVAL_Pos 0 +#define GMAC_ST2CW022_MASKVAL_Msk (0xffffu << GMAC_ST2CW022_MASKVAL_Pos) /**< \brief (GMAC_ST2CW022) Mask Value */ +#define GMAC_ST2CW022_MASKVAL(value) ((GMAC_ST2CW022_MASKVAL_Msk & ((value) << GMAC_ST2CW022_MASKVAL_Pos))) +#define GMAC_ST2CW022_COMPVAL_Pos 16 +#define GMAC_ST2CW022_COMPVAL_Msk (0xffffu << GMAC_ST2CW022_COMPVAL_Pos) /**< \brief (GMAC_ST2CW022) Compare Value */ +#define GMAC_ST2CW022_COMPVAL(value) ((GMAC_ST2CW022_COMPVAL_Msk & ((value) << GMAC_ST2CW022_COMPVAL_Pos))) +/* -------- GMAC_ST2CW122 : (GMAC Offset: 0x7B4) Screening Type 2 Compare Word 1 Register (index = 22) -------- */ +#define GMAC_ST2CW122_OFFSVAL_Pos 0 +#define GMAC_ST2CW122_OFFSVAL_Msk (0x7fu << GMAC_ST2CW122_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW122) Offset Value in Bytes */ +#define GMAC_ST2CW122_OFFSVAL(value) ((GMAC_ST2CW122_OFFSVAL_Msk & ((value) << GMAC_ST2CW122_OFFSVAL_Pos))) +#define GMAC_ST2CW122_OFFSSTRT_Pos 7 +#define GMAC_ST2CW122_OFFSSTRT_Msk (0x3u << GMAC_ST2CW122_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW122) Ethernet Frame Offset Start */ +#define GMAC_ST2CW122_OFFSSTRT(value) ((GMAC_ST2CW122_OFFSSTRT_Msk & ((value) << GMAC_ST2CW122_OFFSSTRT_Pos))) +#define GMAC_ST2CW122_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW122) Offset from the start of the frame */ +#define GMAC_ST2CW122_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW122) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW122_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW122) Offset from the byte after the IP header field */ +#define GMAC_ST2CW122_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW122) Offset from the byte after the TCP/UDP header field */ +/* -------- GMAC_ST2CW023 : (GMAC Offset: 0x7B8) Screening Type 2 Compare Word 0 Register (index = 23) -------- */ +#define GMAC_ST2CW023_MASKVAL_Pos 0 +#define GMAC_ST2CW023_MASKVAL_Msk (0xffffu << GMAC_ST2CW023_MASKVAL_Pos) /**< \brief (GMAC_ST2CW023) Mask Value */ +#define GMAC_ST2CW023_MASKVAL(value) ((GMAC_ST2CW023_MASKVAL_Msk & ((value) << GMAC_ST2CW023_MASKVAL_Pos))) +#define GMAC_ST2CW023_COMPVAL_Pos 16 +#define GMAC_ST2CW023_COMPVAL_Msk (0xffffu << GMAC_ST2CW023_COMPVAL_Pos) /**< \brief (GMAC_ST2CW023) Compare Value */ +#define GMAC_ST2CW023_COMPVAL(value) ((GMAC_ST2CW023_COMPVAL_Msk & ((value) << GMAC_ST2CW023_COMPVAL_Pos))) +/* -------- GMAC_ST2CW123 : (GMAC Offset: 0x7BC) Screening Type 2 Compare Word 1 Register (index = 23) -------- */ +#define GMAC_ST2CW123_OFFSVAL_Pos 0 +#define GMAC_ST2CW123_OFFSVAL_Msk (0x7fu << GMAC_ST2CW123_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW123) Offset Value in Bytes */ +#define GMAC_ST2CW123_OFFSVAL(value) ((GMAC_ST2CW123_OFFSVAL_Msk & ((value) << GMAC_ST2CW123_OFFSVAL_Pos))) +#define GMAC_ST2CW123_OFFSSTRT_Pos 7 +#define GMAC_ST2CW123_OFFSSTRT_Msk (0x3u << GMAC_ST2CW123_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW123) Ethernet Frame Offset Start */ +#define GMAC_ST2CW123_OFFSSTRT(value) ((GMAC_ST2CW123_OFFSSTRT_Msk & ((value) << GMAC_ST2CW123_OFFSSTRT_Pos))) +#define GMAC_ST2CW123_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW123) Offset from the start of the frame */ +#define GMAC_ST2CW123_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW123) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW123_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW123) Offset from the byte after the IP header field */ +#define GMAC_ST2CW123_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW123) Offset from the byte after the TCP/UDP header field */ + +/*@}*/ + + +#endif /* _SAME70_GMAC_COMPONENT_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/gpbr.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/gpbr.h new file mode 100644 index 000000000..d6d19b0d3 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/gpbr.h @@ -0,0 +1,58 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_GPBR_COMPONENT_ +#define _SAME70_GPBR_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR General Purpose Backup Registers */ +/* ============================================================================= */ +/** \addtogroup SAME70_GPBR General Purpose Backup Registers */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Gpbr hardware registers */ +typedef struct { + __IO uint32_t SYS_GPBR[8]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */ +} Gpbr; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SYS_GPBR[8] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */ +#define SYS_GPBR_GPBR_VALUE_Pos 0 +#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[8]) Value of GPBR x */ +#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos))) + +/*@}*/ + + +#endif /* _SAME70_GPBR_COMPONENT_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/hsmci.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/hsmci.h new file mode 100644 index 000000000..d2f35e30f --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/hsmci.h @@ -0,0 +1,347 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_HSMCI_COMPONENT_ +#define _SAME70_HSMCI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */ +/* ============================================================================= */ +/** \addtogroup SAME70_HSMCI High Speed MultiMedia Card Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Hsmci hardware registers */ +typedef struct { + __O uint32_t HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */ + __IO uint32_t HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */ + __IO uint32_t HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */ + __IO uint32_t HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */ + __IO uint32_t HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */ + __O uint32_t HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */ + __IO uint32_t HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */ + __IO uint32_t HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */ + __I uint32_t HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */ + __I uint32_t HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */ + __O uint32_t HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */ + __I uint32_t Reserved1[2]; + __I uint32_t HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */ + __O uint32_t HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */ + __O uint32_t HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */ + __I uint32_t HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */ + __IO uint32_t HSMCI_DMA; /**< \brief (Hsmci Offset: 0x50) DMA Configuration Register */ + __IO uint32_t HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */ + __I uint32_t Reserved2[35]; + __IO uint32_t HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved3[4]; + __I uint32_t HSMCI_VERSION; /**< \brief (Hsmci Offset: 0xFC) Version Register */ + __I uint32_t Reserved4[64]; + __IO uint32_t HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */ +} Hsmci; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */ +#define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */ +#define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */ +#define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */ +#define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */ +#define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */ +/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */ +#define HSMCI_MR_CLKDIV_Pos 0 +#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */ +#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos))) +#define HSMCI_MR_PWSDIV_Pos 8 +#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */ +#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos))) +#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR) Read Proof Enable */ +#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR) Write Proof Enable */ +#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */ +#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */ +#define HSMCI_MR_CLKODD (0x1u << 16) /**< \brief (HSMCI_MR) Clock divider is odd */ +/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */ +#define HSMCI_DTOR_DTOCYC_Pos 0 +#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */ +#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos))) +#define HSMCI_DTOR_DTOMUL_Pos 4 +#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */ +#define HSMCI_DTOR_DTOMUL(value) ((HSMCI_DTOR_DTOMUL_Msk & ((value) << HSMCI_DTOR_DTOMUL_Pos))) +#define HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */ +#define HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */ +#define HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */ +#define HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */ +#define HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */ +#define HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */ +#define HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */ +#define HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */ +/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */ +#define HSMCI_SDCR_SDCSEL_Pos 0 +#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */ +#define HSMCI_SDCR_SDCSEL(value) ((HSMCI_SDCR_SDCSEL_Msk & ((value) << HSMCI_SDCR_SDCSEL_Pos))) +#define HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */ +#define HSMCI_SDCR_SDCBUS_Pos 6 +#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */ +#define HSMCI_SDCR_SDCBUS(value) ((HSMCI_SDCR_SDCBUS_Msk & ((value) << HSMCI_SDCR_SDCBUS_Pos))) +#define HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */ +#define HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bits */ +#define HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bits */ +/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */ +#define HSMCI_ARGR_ARG_Pos 0 +#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */ +#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos))) +/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */ +#define HSMCI_CMDR_CMDNB_Pos 0 +#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */ +#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos))) +#define HSMCI_CMDR_RSPTYP_Pos 6 +#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */ +#define HSMCI_CMDR_RSPTYP(value) ((HSMCI_CMDR_RSPTYP_Msk & ((value) << HSMCI_CMDR_RSPTYP_Pos))) +#define HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response */ +#define HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response */ +#define HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response */ +#define HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */ +#define HSMCI_CMDR_SPCMD_Pos 8 +#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */ +#define HSMCI_CMDR_SPCMD(value) ((HSMCI_CMDR_SPCMD_Msk & ((value) << HSMCI_CMDR_SPCMD_Pos))) +#define HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */ +#define HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */ +#define HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */ +#define HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */ +#define HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */ +#define HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */ +#define HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */ +#define HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */ +#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */ +#define HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */ +#define HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */ +#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */ +#define HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */ +#define HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */ +#define HSMCI_CMDR_TRCMD_Pos 16 +#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */ +#define HSMCI_CMDR_TRCMD(value) ((HSMCI_CMDR_TRCMD_Msk & ((value) << HSMCI_CMDR_TRCMD_Pos))) +#define HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */ +#define HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */ +#define HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */ +#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */ +#define HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */ +#define HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */ +#define HSMCI_CMDR_TRTYP_Pos 19 +#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */ +#define HSMCI_CMDR_TRTYP(value) ((HSMCI_CMDR_TRTYP_Msk & ((value) << HSMCI_CMDR_TRTYP_Pos))) +#define HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SD Card Single Block */ +#define HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SD Card Multiple Block */ +#define HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */ +#define HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */ +#define HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */ +#define HSMCI_CMDR_IOSPCMD_Pos 24 +#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */ +#define HSMCI_CMDR_IOSPCMD(value) ((HSMCI_CMDR_IOSPCMD_Msk & ((value) << HSMCI_CMDR_IOSPCMD_Pos))) +#define HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */ +#define HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */ +#define HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */ +#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */ +#define HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */ +#define HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */ +#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge */ +/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */ +#define HSMCI_BLKR_BCNT_Pos 0 +#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */ +#define HSMCI_BLKR_BCNT(value) ((HSMCI_BLKR_BCNT_Msk & ((value) << HSMCI_BLKR_BCNT_Pos))) +#define HSMCI_BLKR_BLKLEN_Pos 16 +#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */ +#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos))) +/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */ +#define HSMCI_CSTOR_CSTOCYC_Pos 0 +#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */ +#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos))) +#define HSMCI_CSTOR_CSTOMUL_Pos 4 +#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */ +#define HSMCI_CSTOR_CSTOMUL(value) ((HSMCI_CSTOR_CSTOMUL_Msk & ((value) << HSMCI_CSTOR_CSTOMUL_Pos))) +#define HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */ +#define HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */ +#define HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */ +#define HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */ +#define HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */ +#define HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */ +#define HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */ +#define HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */ +/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */ +#define HSMCI_RSPR_RSP_Pos 0 +#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */ +/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */ +#define HSMCI_RDR_DATA_Pos 0 +#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */ +/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */ +#define HSMCI_TDR_DATA_Pos 0 +#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */ +#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos))) +/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */ +#define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready (cleared by reading HSMCI_RDR) */ +#define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready (cleared by writing in HSMCI_TDR) */ +#define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended (cleared on read) */ +#define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress (cleared at the end of CRC16 calculation) */ +#define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */ +#define HSMCI_SR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A (cleared on read) */ +#define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */ +#define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received (cleared on read) */ +#define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error (cleared on read) */ +#define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error (cleared on read) */ +#define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error (cleared on read) */ +#define HSMCI_SR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_SR) DMA Block Overrun Error (cleared on read) */ +#define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */ +#define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */ +#define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received (cleared on read) */ +#define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error (cleared on read) */ +#define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) */ +#define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) */ +/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */ +#define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */ +#define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */ +#define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */ +#define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */ +#define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */ +#define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */ +#define HSMCI_IER_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */ +#define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */ +#define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */ +#define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */ +#define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */ +#define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */ +#define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */ +#define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */ +#define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */ +#define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */ +#define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */ +#define HSMCI_IER_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IER) DMA Block Overrun Error Interrupt Enable */ +#define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */ +#define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */ +#define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */ +#define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */ +#define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */ +#define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */ +/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */ +#define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */ +#define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */ +#define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */ +#define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */ +#define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */ +#define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */ +#define HSMCI_IDR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */ +#define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */ +#define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */ +#define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */ +#define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */ +#define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */ +#define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */ +#define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */ +#define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */ +#define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */ +#define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */ +#define HSMCI_IDR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable */ +#define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */ +#define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */ +#define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */ +#define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */ +#define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */ +#define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */ +/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */ +#define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */ +#define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */ +#define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */ +#define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */ +#define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */ +#define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */ +#define HSMCI_IMR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */ +#define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */ +#define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */ +#define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */ +#define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */ +#define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */ +#define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */ +#define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */ +#define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */ +#define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */ +#define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */ +#define HSMCI_IMR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask */ +#define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */ +#define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */ +#define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */ +#define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */ +#define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */ +#define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */ +/* -------- HSMCI_DMA : (HSMCI Offset: 0x50) DMA Configuration Register -------- */ +#define HSMCI_DMA_CHKSIZE_Pos 4 +#define HSMCI_DMA_CHKSIZE_Msk (0x7u << HSMCI_DMA_CHKSIZE_Pos) /**< \brief (HSMCI_DMA) DMA Channel Read and Write Chunk Size */ +#define HSMCI_DMA_CHKSIZE(value) ((HSMCI_DMA_CHKSIZE_Msk & ((value) << HSMCI_DMA_CHKSIZE_Pos))) +#define HSMCI_DMA_CHKSIZE_1 (0x0u << 4) /**< \brief (HSMCI_DMA) 1 data available */ +#define HSMCI_DMA_CHKSIZE_2 (0x1u << 4) /**< \brief (HSMCI_DMA) 2 data available */ +#define HSMCI_DMA_CHKSIZE_4 (0x2u << 4) /**< \brief (HSMCI_DMA) 4 data available */ +#define HSMCI_DMA_CHKSIZE_8 (0x3u << 4) /**< \brief (HSMCI_DMA) 8 data available */ +#define HSMCI_DMA_CHKSIZE_16 (0x4u << 4) /**< \brief (HSMCI_DMA) 16 data available */ +#define HSMCI_DMA_DMAEN (0x1u << 8) /**< \brief (HSMCI_DMA) DMA Hardware Handshaking Enable */ +/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */ +#define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */ +#define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */ +#define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */ +#define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */ +/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */ +#define HSMCI_WPMR_WPEN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protect Enable */ +#define HSMCI_WPMR_WPKEY_Pos 8 +#define HSMCI_WPMR_WPKEY_Msk (0xffffffu << HSMCI_WPMR_WPKEY_Pos) /**< \brief (HSMCI_WPMR) Write Protect Key */ +#define HSMCI_WPMR_WPKEY(value) ((HSMCI_WPMR_WPKEY_Msk & ((value) << HSMCI_WPMR_WPKEY_Pos))) +#define HSMCI_WPMR_WPKEY_PASSWD (0x4D4349u << 8) /**< \brief (HSMCI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */ +#define HSMCI_WPSR_WPVS (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */ +#define HSMCI_WPSR_WPVSRC_Pos 8 +#define HSMCI_WPSR_WPVSRC_Msk (0xffffu << HSMCI_WPSR_WPVSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Source */ +/* -------- HSMCI_VERSION : (HSMCI Offset: 0xFC) Version Register -------- */ +#define HSMCI_VERSION_VERSION_Pos 0 +#define HSMCI_VERSION_VERSION_Msk (0xfffu << HSMCI_VERSION_VERSION_Pos) /**< \brief (HSMCI_VERSION) Hardware Module Version */ +#define HSMCI_VERSION_MFN_Pos 16 +#define HSMCI_VERSION_MFN_Msk (0x7u << HSMCI_VERSION_MFN_Pos) /**< \brief (HSMCI_VERSION) Metal Fix Number */ +/* -------- HSMCI_FIFO[256] : (HSMCI Offset: 0x200) FIFO Memory Aperture0 -------- */ +#define HSMCI_FIFO_DATA_Pos 0 +#define HSMCI_FIFO_DATA_Msk (0xffffffffu << HSMCI_FIFO_DATA_Pos) /**< \brief (HSMCI_FIFO[256]) Data to Read or Data to Write */ +#define HSMCI_FIFO_DATA(value) ((HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos))) + +/*@}*/ + + +#endif /* _SAME70_HSMCI_COMPONENT_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/i2sc.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/i2sc.h new file mode 100644 index 000000000..ea0afdbec --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/i2sc.h @@ -0,0 +1,174 @@ +/** + * \file + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_I2SC_COMPONENT_ +#define _SAME70_I2SC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Inter-IC Sound Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_I2SC Inter-IC Sound Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief I2sc hardware registers */ +typedef struct { + __O uint32_t I2SC_CR; /**< \brief (I2sc Offset: 0x00) Control Register */ + __IO uint32_t I2SC_MR; /**< \brief (I2sc Offset: 0x04) Mode Register */ + __I uint32_t I2SC_SR; /**< \brief (I2sc Offset: 0x08) Status Register */ + __O uint32_t I2SC_SCR; /**< \brief (I2sc Offset: 0x0C) Status Clear Register */ + __O uint32_t I2SC_SSR; /**< \brief (I2sc Offset: 0x10) Status Set Register */ + __O uint32_t I2SC_IER; /**< \brief (I2sc Offset: 0x14) Interrupt Enable Register */ + __O uint32_t I2SC_IDR; /**< \brief (I2sc Offset: 0x18) Interrupt Disable Register */ + __I uint32_t I2SC_IMR; /**< \brief (I2sc Offset: 0x1C) Interrupt Mask Register */ + __I uint32_t I2SC_RHR; /**< \brief (I2sc Offset: 0x20) Receiver Holding Register */ + __O uint32_t I2SC_THR; /**< \brief (I2sc Offset: 0x24) Transmitter Holding Register */ + __I uint32_t I2SC_VERSION; /**< \brief (I2sc Offset: 0x28) Version Register */ +} I2sc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- I2SC_CR : (I2SC Offset: 0x00) Control Register -------- */ +#define I2SC_CR_RXEN (0x1u << 0) /**< \brief (I2SC_CR) Receiver Enable */ +#define I2SC_CR_RXDIS (0x1u << 1) /**< \brief (I2SC_CR) Receiver Disable */ +#define I2SC_CR_CKEN (0x1u << 2) /**< \brief (I2SC_CR) Clocks Enable */ +#define I2SC_CR_CKDIS (0x1u << 3) /**< \brief (I2SC_CR) Clocks Disable */ +#define I2SC_CR_TXEN (0x1u << 4) /**< \brief (I2SC_CR) Transmitter Enable */ +#define I2SC_CR_TXDIS (0x1u << 5) /**< \brief (I2SC_CR) Transmitter Disable */ +#define I2SC_CR_SWRST (0x1u << 7) /**< \brief (I2SC_CR) Software Reset */ +/* -------- I2SC_MR : (I2SC Offset: 0x04) Mode Register -------- */ +#define I2SC_MR_MODE (0x1u << 0) /**< \brief (I2SC_MR) Inter-IC Sound Controller Mode */ +#define I2SC_MR_MODE_SLAVE (0x0u << 0) /**< \brief (I2SC_MR) I2SCK and i2SWS pin inputs used as bit clock and word select/frame synchronization. */ +#define I2SC_MR_MODE_MASTER (0x1u << 0) /**< \brief (I2SC_MR) Bit clock and word select/frame synchronization generated by I2SC from MCK and output to I2SCK and I2SWS pins. MCK is output as master clock on I2SMCK if I2SC_MR.IMCKMODE is set. */ +#define I2SC_MR_DATALENGTH_Pos 2 +#define I2SC_MR_DATALENGTH_Msk (0x7u << I2SC_MR_DATALENGTH_Pos) /**< \brief (I2SC_MR) Data Word Length */ +#define I2SC_MR_DATALENGTH(value) ((I2SC_MR_DATALENGTH_Msk & ((value) << I2SC_MR_DATALENGTH_Pos))) +#define I2SC_MR_DATALENGTH_32_BITS (0x0u << 2) /**< \brief (I2SC_MR) Data length is set to 32 bits */ +#define I2SC_MR_DATALENGTH_24_BITS (0x1u << 2) /**< \brief (I2SC_MR) Data length is set to 24 bits */ +#define I2SC_MR_DATALENGTH_20_BITS (0x2u << 2) /**< \brief (I2SC_MR) Data length is set to 20 bits */ +#define I2SC_MR_DATALENGTH_18_BITS (0x3u << 2) /**< \brief (I2SC_MR) Data length is set to 18 bits */ +#define I2SC_MR_DATALENGTH_16_BITS (0x4u << 2) /**< \brief (I2SC_MR) Data length is set to 16 bits */ +#define I2SC_MR_DATALENGTH_16_BITS_COMPACT (0x5u << 2) /**< \brief (I2SC_MR) Data length is set to 16-bit compact stereo. Left sample in bits 15:0 and right sample in bits 31:16 of same word. */ +#define I2SC_MR_DATALENGTH_8_BITS (0x6u << 2) /**< \brief (I2SC_MR) Data length is set to 8 bits */ +#define I2SC_MR_DATALENGTH_8_BITS_COMPACT (0x7u << 2) /**< \brief (I2SC_MR) Data length is set to 8-bit compact stereo. Left sample in bits 7:0 and right sample in bits 15:8 of the same word. */ +#define I2SC_MR_FORMAT_Pos 6 +#define I2SC_MR_FORMAT_Msk (0x3u << I2SC_MR_FORMAT_Pos) /**< \brief (I2SC_MR) Data Format */ +#define I2SC_MR_FORMAT(value) ((I2SC_MR_FORMAT_Msk & ((value) << I2SC_MR_FORMAT_Pos))) +#define I2SC_MR_FORMAT_I2S (0x0u << 6) /**< \brief (I2SC_MR) I2S format, stereo with I2SWS low for left channel, and MSB of sample starting one I2SCK period after I2SWS edge */ +#define I2SC_MR_FORMAT_LJ (0x1u << 6) /**< \brief (I2SC_MR) Left-justified format, stereo with I2SWS high for left channel, and MSB of sample starting on I2SWS edge */ +#define I2SC_MR_RXMONO (0x1u << 8) /**< \brief (I2SC_MR) Receive Mono */ +#define I2SC_MR_RXDMA (0x1u << 9) /**< \brief (I2SC_MR) Single or Multiple DMA Controller Channels for Receiver */ +#define I2SC_MR_RXLOOP (0x1u << 10) /**< \brief (I2SC_MR) Loop-back Test Mode */ +#define I2SC_MR_TXMONO (0x1u << 12) /**< \brief (I2SC_MR) Transmit Mono */ +#define I2SC_MR_TXDMA (0x1u << 13) /**< \brief (I2SC_MR) Single or Multiple DMA Controller Channels for Transmitter */ +#define I2SC_MR_TXSAME (0x1u << 14) /**< \brief (I2SC_MR) Transmit Data when Underrun */ +#define I2SC_MR_IMCKDIV_Pos 16 +#define I2SC_MR_IMCKDIV_Msk (0x3fu << I2SC_MR_IMCKDIV_Pos) /**< \brief (I2SC_MR) Selected Clock to I2SC Master Clock Ratio */ +#define I2SC_MR_IMCKDIV(value) ((I2SC_MR_IMCKDIV_Msk & ((value) << I2SC_MR_IMCKDIV_Pos))) +#define I2SC_MR_IMCKFS_Pos 24 +#define I2SC_MR_IMCKFS_Msk (0x3fu << I2SC_MR_IMCKFS_Pos) /**< \brief (I2SC_MR) Master Clock to fs Ratio */ +#define I2SC_MR_IMCKFS(value) ((I2SC_MR_IMCKFS_Msk & ((value) << I2SC_MR_IMCKFS_Pos))) +#define I2SC_MR_IMCKFS_M2SF32 (0x0u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 32 */ +#define I2SC_MR_IMCKFS_M2SF64 (0x1u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 64 */ +#define I2SC_MR_IMCKFS_M2SF96 (0x2u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 96 */ +#define I2SC_MR_IMCKFS_M2SF128 (0x3u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 128 */ +#define I2SC_MR_IMCKFS_M2SF192 (0x5u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 192 */ +#define I2SC_MR_IMCKFS_M2SF256 (0x7u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 256 */ +#define I2SC_MR_IMCKFS_M2SF384 (0xBu << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 384 */ +#define I2SC_MR_IMCKFS_M2SF512 (0xFu << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 512 */ +#define I2SC_MR_IMCKFS_M2SF768 (0x17u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 768 */ +#define I2SC_MR_IMCKFS_M2SF1024 (0x1Fu << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 1024 */ +#define I2SC_MR_IMCKFS_M2SF1536 (0x2Fu << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 1536 */ +#define I2SC_MR_IMCKFS_M2SF2048 (0x3Fu << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 2048 */ +#define I2SC_MR_IMCKMODE (0x1u << 30) /**< \brief (I2SC_MR) Master Clock Mode */ +#define I2SC_MR_IWS (0x1u << 31) /**< \brief (I2SC_MR) I2SWS Slot Width */ +/* -------- I2SC_SR : (I2SC Offset: 0x08) Status Register -------- */ +#define I2SC_SR_RXEN (0x1u << 0) /**< \brief (I2SC_SR) Receiver Enabled */ +#define I2SC_SR_RXRDY (0x1u << 1) /**< \brief (I2SC_SR) Receive Ready */ +#define I2SC_SR_RXOR (0x1u << 2) /**< \brief (I2SC_SR) Receive Overrun */ +#define I2SC_SR_TXEN (0x1u << 4) /**< \brief (I2SC_SR) Transmitter Enabled */ +#define I2SC_SR_TXRDY (0x1u << 5) /**< \brief (I2SC_SR) Transmit Ready */ +#define I2SC_SR_TXUR (0x1u << 6) /**< \brief (I2SC_SR) Transmit Underrun */ +#define I2SC_SR_RXORCH_Pos 8 +#define I2SC_SR_RXORCH_Msk (0x3u << I2SC_SR_RXORCH_Pos) /**< \brief (I2SC_SR) Receive Overrun Channel */ +#define I2SC_SR_TXURCH_Pos 20 +#define I2SC_SR_TXURCH_Msk (0x3u << I2SC_SR_TXURCH_Pos) /**< \brief (I2SC_SR) Transmit Underrun Channel */ +/* -------- I2SC_SCR : (I2SC Offset: 0x0C) Status Clear Register -------- */ +#define I2SC_SCR_RXOR (0x1u << 2) /**< \brief (I2SC_SCR) Receive Overrun Status Clear */ +#define I2SC_SCR_TXUR (0x1u << 6) /**< \brief (I2SC_SCR) Transmit Underrun Status Clear */ +#define I2SC_SCR_RXORCH_Pos 8 +#define I2SC_SCR_RXORCH_Msk (0x3u << I2SC_SCR_RXORCH_Pos) /**< \brief (I2SC_SCR) Receive Overrun Per Channel Status Clear */ +#define I2SC_SCR_RXORCH(value) ((I2SC_SCR_RXORCH_Msk & ((value) << I2SC_SCR_RXORCH_Pos))) +#define I2SC_SCR_TXURCH_Pos 20 +#define I2SC_SCR_TXURCH_Msk (0x3u << I2SC_SCR_TXURCH_Pos) /**< \brief (I2SC_SCR) Transmit Underrun Per Channel Status Clear */ +#define I2SC_SCR_TXURCH(value) ((I2SC_SCR_TXURCH_Msk & ((value) << I2SC_SCR_TXURCH_Pos))) +/* -------- I2SC_SSR : (I2SC Offset: 0x10) Status Set Register -------- */ +#define I2SC_SSR_RXOR (0x1u << 2) /**< \brief (I2SC_SSR) Receive Overrun Status Set */ +#define I2SC_SSR_TXUR (0x1u << 6) /**< \brief (I2SC_SSR) Transmit Underrun Status Set */ +#define I2SC_SSR_RXORCH_Pos 8 +#define I2SC_SSR_RXORCH_Msk (0x3u << I2SC_SSR_RXORCH_Pos) /**< \brief (I2SC_SSR) Receive Overrun Per Channel Status Set */ +#define I2SC_SSR_RXORCH(value) ((I2SC_SSR_RXORCH_Msk & ((value) << I2SC_SSR_RXORCH_Pos))) +#define I2SC_SSR_TXURCH_Pos 20 +#define I2SC_SSR_TXURCH_Msk (0x3u << I2SC_SSR_TXURCH_Pos) /**< \brief (I2SC_SSR) Transmit Underrun Per Channel Status Set */ +#define I2SC_SSR_TXURCH(value) ((I2SC_SSR_TXURCH_Msk & ((value) << I2SC_SSR_TXURCH_Pos))) +/* -------- I2SC_IER : (I2SC Offset: 0x14) Interrupt Enable Register -------- */ +#define I2SC_IER_RXRDY (0x1u << 1) /**< \brief (I2SC_IER) Receiver Ready Interrupt Enable */ +#define I2SC_IER_RXOR (0x1u << 2) /**< \brief (I2SC_IER) Receiver Overrun Interrupt Enable */ +#define I2SC_IER_TXRDY (0x1u << 5) /**< \brief (I2SC_IER) Transmit Ready Interrupt Enable */ +#define I2SC_IER_TXUR (0x1u << 6) /**< \brief (I2SC_IER) Transmit Underflow Interrupt Enable */ +/* -------- I2SC_IDR : (I2SC Offset: 0x18) Interrupt Disable Register -------- */ +#define I2SC_IDR_RXRDY (0x1u << 1) /**< \brief (I2SC_IDR) Receiver Ready Interrupt Disable */ +#define I2SC_IDR_RXOR (0x1u << 2) /**< \brief (I2SC_IDR) Receiver Overrun Interrupt Disable */ +#define I2SC_IDR_TXRDY (0x1u << 5) /**< \brief (I2SC_IDR) Transmit Ready Interrupt Disable */ +#define I2SC_IDR_TXUR (0x1u << 6) /**< \brief (I2SC_IDR) Transmit Underflow Interrupt Disable */ +/* -------- I2SC_IMR : (I2SC Offset: 0x1C) Interrupt Mask Register -------- */ +#define I2SC_IMR_RXRDY (0x1u << 1) /**< \brief (I2SC_IMR) Receiver Ready Interrupt Disable */ +#define I2SC_IMR_RXOR (0x1u << 2) /**< \brief (I2SC_IMR) Receiver Overrun Interrupt Disable */ +#define I2SC_IMR_TXRDY (0x1u << 5) /**< \brief (I2SC_IMR) Transmit Ready Interrupt Disable */ +#define I2SC_IMR_TXUR (0x1u << 6) /**< \brief (I2SC_IMR) Transmit Underflow Interrupt Disable */ +/* -------- I2SC_RHR : (I2SC Offset: 0x20) Receiver Holding Register -------- */ +#define I2SC_RHR_RHR_Pos 0 +#define I2SC_RHR_RHR_Msk (0xffffffffu << I2SC_RHR_RHR_Pos) /**< \brief (I2SC_RHR) Receiver Holding Register */ +/* -------- I2SC_THR : (I2SC Offset: 0x24) Transmitter Holding Register -------- */ +#define I2SC_THR_THR_Pos 0 +#define I2SC_THR_THR_Msk (0xffffffffu << I2SC_THR_THR_Pos) /**< \brief (I2SC_THR) Transmitter Holding Register */ +#define I2SC_THR_THR(value) ((I2SC_THR_THR_Msk & ((value) << I2SC_THR_THR_Pos))) +/* -------- I2SC_VERSION : (I2SC Offset: 0x28) Version Register -------- */ +#define I2SC_VERSION_VERSION_Pos 0 +#define I2SC_VERSION_VERSION_Msk (0xfffu << I2SC_VERSION_VERSION_Pos) /**< \brief (I2SC_VERSION) Version of the Hardware Module */ +#define I2SC_VERSION_MFN_Pos 16 +#define I2SC_VERSION_MFN_Msk (0x7u << I2SC_VERSION_MFN_Pos) /**< \brief (I2SC_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_I2SC_COMPONENT_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/icm.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/icm.h new file mode 100644 index 000000000..98a4e3faa --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/icm.h @@ -0,0 +1,229 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_ICM_COMPONENT_ +#define _SAME70_ICM_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Integrity Check Monitor */ +/* ============================================================================= */ +/** \addtogroup SAME70_ICM Integrity Check Monitor */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Icm hardware registers */ +typedef struct { + __IO uint32_t ICM_CFG; /**< \brief (Icm Offset: 0x00) Configuration Register */ + __O uint32_t ICM_CTRL; /**< \brief (Icm Offset: 0x04) Control Register */ + __I uint32_t ICM_SR; /**< \brief (Icm Offset: 0x08) Status Register */ + __I uint32_t Reserved1[1]; + __O uint32_t ICM_IER; /**< \brief (Icm Offset: 0x10) Interrupt Enable Register */ + __O uint32_t ICM_IDR; /**< \brief (Icm Offset: 0x14) Interrupt Disable Register */ + __I uint32_t ICM_IMR; /**< \brief (Icm Offset: 0x18) Interrupt Mask Register */ + __I uint32_t ICM_ISR; /**< \brief (Icm Offset: 0x1C) Interrupt Status Register */ + __I uint32_t ICM_UASR; /**< \brief (Icm Offset: 0x20) Undefined Access Status Register */ + __I uint32_t Reserved2[3]; + __IO uint32_t ICM_DSCR; /**< \brief (Icm Offset: 0x30) Region Descriptor Area Start Address Register */ + __IO uint32_t ICM_HASH; /**< \brief (Icm Offset: 0x34) Region Hash Area Start Address Register */ + __O uint32_t ICM_UIHVAL[8]; /**< \brief (Icm Offset: 0x38) User Initial Hash Value 0 Register */ + __I uint32_t Reserved3[37]; + __I uint32_t ICM_ADDRSIZE; /**< \brief (Icm Offset: 0xEC) Address Size Register */ + __I uint32_t ICM_IPNAME[2]; /**< \brief (Icm Offset: 0xF0) IP Name 1 Register */ + __I uint32_t ICM_FEATURES; /**< \brief (Icm Offset: 0xF8) Feature Register */ + __I uint32_t ICM_VERSION; /**< \brief (Icm Offset: 0xFC) Version Register */ +} Icm; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- ICM_CFG : (ICM Offset: 0x00) Configuration Register -------- */ +#define ICM_CFG_WBDIS (0x1u << 0) /**< \brief (ICM_CFG) Write Back Disable */ +#define ICM_CFG_EOMDIS (0x1u << 1) /**< \brief (ICM_CFG) End of Monitoring Disable */ +#define ICM_CFG_SLBDIS (0x1u << 2) /**< \brief (ICM_CFG) Secondary List Branching Disable */ +#define ICM_CFG_BBC_Pos 4 +#define ICM_CFG_BBC_Msk (0xfu << ICM_CFG_BBC_Pos) /**< \brief (ICM_CFG) Bus Burden Control */ +#define ICM_CFG_BBC(value) ((ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos))) +#define ICM_CFG_ASCD (0x1u << 8) /**< \brief (ICM_CFG) Automatic Switch To Compare Digest */ +#define ICM_CFG_DUALBUFF (0x1u << 9) /**< \brief (ICM_CFG) Dual Input Buffer */ +#define ICM_CFG_UIHASH (0x1u << 12) /**< \brief (ICM_CFG) User Initial Hash Value */ +#define ICM_CFG_UALGO_Pos 13 +#define ICM_CFG_UALGO_Msk (0x7u << ICM_CFG_UALGO_Pos) /**< \brief (ICM_CFG) User SHA Algorithm */ +#define ICM_CFG_UALGO(value) ((ICM_CFG_UALGO_Msk & ((value) << ICM_CFG_UALGO_Pos))) +#define ICM_CFG_UALGO_SHA1 (0x0u << 13) /**< \brief (ICM_CFG) SHA1 algorithm processed */ +#define ICM_CFG_UALGO_SHA256 (0x1u << 13) /**< \brief (ICM_CFG) SHA256 algorithm processed */ +#define ICM_CFG_UALGO_SHA224 (0x4u << 13) /**< \brief (ICM_CFG) SHA224 algorithm processed */ +#define ICM_CFG_HAPROT_Pos 16 +#define ICM_CFG_HAPROT_Msk (0x3fu << ICM_CFG_HAPROT_Pos) /**< \brief (ICM_CFG) Region Hash Area Protection */ +#define ICM_CFG_HAPROT(value) ((ICM_CFG_HAPROT_Msk & ((value) << ICM_CFG_HAPROT_Pos))) +#define ICM_CFG_DAPROT_Pos 24 +#define ICM_CFG_DAPROT_Msk (0x3fu << ICM_CFG_DAPROT_Pos) /**< \brief (ICM_CFG) Region Descriptor Area Protection */ +#define ICM_CFG_DAPROT(value) ((ICM_CFG_DAPROT_Msk & ((value) << ICM_CFG_DAPROT_Pos))) +/* -------- ICM_CTRL : (ICM Offset: 0x04) Control Register -------- */ +#define ICM_CTRL_ENABLE (0x1u << 0) /**< \brief (ICM_CTRL) ICM Enable */ +#define ICM_CTRL_DISABLE (0x1u << 1) /**< \brief (ICM_CTRL) ICM Disable Register */ +#define ICM_CTRL_SWRST (0x1u << 2) /**< \brief (ICM_CTRL) Software Reset */ +#define ICM_CTRL_REHASH_Pos 4 +#define ICM_CTRL_REHASH_Msk (0xfu << ICM_CTRL_REHASH_Pos) /**< \brief (ICM_CTRL) Recompute Internal Hash */ +#define ICM_CTRL_REHASH(value) ((ICM_CTRL_REHASH_Msk & ((value) << ICM_CTRL_REHASH_Pos))) +#define ICM_CTRL_RMDIS_Pos 8 +#define ICM_CTRL_RMDIS_Msk (0xfu << ICM_CTRL_RMDIS_Pos) /**< \brief (ICM_CTRL) Region Monitoring Disable */ +#define ICM_CTRL_RMDIS(value) ((ICM_CTRL_RMDIS_Msk & ((value) << ICM_CTRL_RMDIS_Pos))) +#define ICM_CTRL_RMEN_Pos 12 +#define ICM_CTRL_RMEN_Msk (0xfu << ICM_CTRL_RMEN_Pos) /**< \brief (ICM_CTRL) Region Monitoring Enable */ +#define ICM_CTRL_RMEN(value) ((ICM_CTRL_RMEN_Msk & ((value) << ICM_CTRL_RMEN_Pos))) +/* -------- ICM_SR : (ICM Offset: 0x08) Status Register -------- */ +#define ICM_SR_ENABLE (0x1u << 0) /**< \brief (ICM_SR) ICM Controller Enable Register */ +#define ICM_SR_RAWRMDIS_Pos 8 +#define ICM_SR_RAWRMDIS_Msk (0xfu << ICM_SR_RAWRMDIS_Pos) /**< \brief (ICM_SR) RAW Region Monitoring Disabled Status */ +#define ICM_SR_RAWRMDIS(value) ((ICM_SR_RAWRMDIS_Msk & ((value) << ICM_SR_RAWRMDIS_Pos))) +#define ICM_SR_RMDIS_Pos 12 +#define ICM_SR_RMDIS_Msk (0xfu << ICM_SR_RMDIS_Pos) /**< \brief (ICM_SR) Region Monitoring Disabled Status */ +#define ICM_SR_RMDIS(value) ((ICM_SR_RMDIS_Msk & ((value) << ICM_SR_RMDIS_Pos))) +/* -------- ICM_IER : (ICM Offset: 0x10) Interrupt Enable Register -------- */ +#define ICM_IER_RHC_Pos 0 +#define ICM_IER_RHC_Msk (0xfu << ICM_IER_RHC_Pos) /**< \brief (ICM_IER) Region Hash Completed Interrupt Enable */ +#define ICM_IER_RHC(value) ((ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos))) +#define ICM_IER_RDM_Pos 4 +#define ICM_IER_RDM_Msk (0xfu << ICM_IER_RDM_Pos) /**< \brief (ICM_IER) Region Digest Mismatch Interrupt Enable */ +#define ICM_IER_RDM(value) ((ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos))) +#define ICM_IER_RBE_Pos 8 +#define ICM_IER_RBE_Msk (0xfu << ICM_IER_RBE_Pos) /**< \brief (ICM_IER) Region Bus Error Interrupt Enable */ +#define ICM_IER_RBE(value) ((ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos))) +#define ICM_IER_RWC_Pos 12 +#define ICM_IER_RWC_Msk (0xfu << ICM_IER_RWC_Pos) /**< \brief (ICM_IER) Region Wrap Condition detected Interrupt Enable */ +#define ICM_IER_RWC(value) ((ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos))) +#define ICM_IER_REC_Pos 16 +#define ICM_IER_REC_Msk (0xfu << ICM_IER_REC_Pos) /**< \brief (ICM_IER) Region End bit Condition Detected Interrupt Enable */ +#define ICM_IER_REC(value) ((ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos))) +#define ICM_IER_RSU_Pos 20 +#define ICM_IER_RSU_Msk (0xfu << ICM_IER_RSU_Pos) /**< \brief (ICM_IER) Region Status Updated Interrupt Disable */ +#define ICM_IER_RSU(value) ((ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos))) +#define ICM_IER_URAD (0x1u << 24) /**< \brief (ICM_IER) Undefined Register Access Detection Interrupt Enable */ +/* -------- ICM_IDR : (ICM Offset: 0x14) Interrupt Disable Register -------- */ +#define ICM_IDR_RHC_Pos 0 +#define ICM_IDR_RHC_Msk (0xfu << ICM_IDR_RHC_Pos) /**< \brief (ICM_IDR) Region Hash Completed Interrupt Disable */ +#define ICM_IDR_RHC(value) ((ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos))) +#define ICM_IDR_RDM_Pos 4 +#define ICM_IDR_RDM_Msk (0xfu << ICM_IDR_RDM_Pos) /**< \brief (ICM_IDR) Region Digest Mismatch Interrupt Disable */ +#define ICM_IDR_RDM(value) ((ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos))) +#define ICM_IDR_RBE_Pos 8 +#define ICM_IDR_RBE_Msk (0xfu << ICM_IDR_RBE_Pos) /**< \brief (ICM_IDR) Region Bus Error Interrupt Disable */ +#define ICM_IDR_RBE(value) ((ICM_IDR_RBE_Msk & ((value) << ICM_IDR_RBE_Pos))) +#define ICM_IDR_RWC_Pos 12 +#define ICM_IDR_RWC_Msk (0xfu << ICM_IDR_RWC_Pos) /**< \brief (ICM_IDR) Region Wrap Condition Detected Interrupt Disable */ +#define ICM_IDR_RWC(value) ((ICM_IDR_RWC_Msk & ((value) << ICM_IDR_RWC_Pos))) +#define ICM_IDR_REC_Pos 16 +#define ICM_IDR_REC_Msk (0xfu << ICM_IDR_REC_Pos) /**< \brief (ICM_IDR) Region End bit Condition detected Interrupt Disable */ +#define ICM_IDR_REC(value) ((ICM_IDR_REC_Msk & ((value) << ICM_IDR_REC_Pos))) +#define ICM_IDR_RSU_Pos 20 +#define ICM_IDR_RSU_Msk (0xfu << ICM_IDR_RSU_Pos) /**< \brief (ICM_IDR) Region Status Updated Interrupt Disable */ +#define ICM_IDR_RSU(value) ((ICM_IDR_RSU_Msk & ((value) << ICM_IDR_RSU_Pos))) +#define ICM_IDR_URAD (0x1u << 24) /**< \brief (ICM_IDR) Undefined Register Access Detection Interrupt Disable */ +/* -------- ICM_IMR : (ICM Offset: 0x18) Interrupt Mask Register -------- */ +#define ICM_IMR_RHC_Pos 0 +#define ICM_IMR_RHC_Msk (0xfu << ICM_IMR_RHC_Pos) /**< \brief (ICM_IMR) Region Hash Completed Interrupt Mask */ +#define ICM_IMR_RDM_Pos 4 +#define ICM_IMR_RDM_Msk (0xfu << ICM_IMR_RDM_Pos) /**< \brief (ICM_IMR) Region Digest Mismatch Interrupt Mask */ +#define ICM_IMR_RBE_Pos 8 +#define ICM_IMR_RBE_Msk (0xfu << ICM_IMR_RBE_Pos) /**< \brief (ICM_IMR) Region Bus Error Interrupt Mask */ +#define ICM_IMR_RWC_Pos 12 +#define ICM_IMR_RWC_Msk (0xfu << ICM_IMR_RWC_Pos) /**< \brief (ICM_IMR) Region Wrap Condition Detected Interrupt Mask */ +#define ICM_IMR_REC_Pos 16 +#define ICM_IMR_REC_Msk (0xfu << ICM_IMR_REC_Pos) /**< \brief (ICM_IMR) Region End bit Condition Detected Interrupt Mask */ +#define ICM_IMR_RSU_Pos 20 +#define ICM_IMR_RSU_Msk (0xfu << ICM_IMR_RSU_Pos) /**< \brief (ICM_IMR) Region Status Updated Interrupt Mask */ +#define ICM_IMR_URAD (0x1u << 24) /**< \brief (ICM_IMR) Undefined Register Access Detection Interrupt Mask */ +/* -------- ICM_ISR : (ICM Offset: 0x1C) Interrupt Status Register -------- */ +#define ICM_ISR_RHC_Pos 0 +#define ICM_ISR_RHC_Msk (0xfu << ICM_ISR_RHC_Pos) /**< \brief (ICM_ISR) Region Hash Completed */ +#define ICM_ISR_RDM_Pos 4 +#define ICM_ISR_RDM_Msk (0xfu << ICM_ISR_RDM_Pos) /**< \brief (ICM_ISR) Region Digest Mismatch */ +#define ICM_ISR_RBE_Pos 8 +#define ICM_ISR_RBE_Msk (0xfu << ICM_ISR_RBE_Pos) /**< \brief (ICM_ISR) Region Bus Error */ +#define ICM_ISR_RWC_Pos 12 +#define ICM_ISR_RWC_Msk (0xfu << ICM_ISR_RWC_Pos) /**< \brief (ICM_ISR) Region Wrap Condition Detected */ +#define ICM_ISR_REC_Pos 16 +#define ICM_ISR_REC_Msk (0xfu << ICM_ISR_REC_Pos) /**< \brief (ICM_ISR) Region End bit Condition Detected */ +#define ICM_ISR_RSU_Pos 20 +#define ICM_ISR_RSU_Msk (0xfu << ICM_ISR_RSU_Pos) /**< \brief (ICM_ISR) Region Status Updated Detected */ +#define ICM_ISR_URAD (0x1u << 24) /**< \brief (ICM_ISR) Undefined Register Access Detection Status */ +/* -------- ICM_UASR : (ICM Offset: 0x20) Undefined Access Status Register -------- */ +#define ICM_UASR_URAT_Pos 0 +#define ICM_UASR_URAT_Msk (0x7u << ICM_UASR_URAT_Pos) /**< \brief (ICM_UASR) Undefined Register Access Trace */ +#define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER (0x0u << 0) /**< \brief (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded. */ +#define ICM_UASR_URAT_ICM_CFG_MODIFIED (0x1u << 0) /**< \brief (ICM_UASR) ICM_CFG modified during active monitoring. */ +#define ICM_UASR_URAT_ICM_DSCR_MODIFIED (0x2u << 0) /**< \brief (ICM_UASR) ICM_DSCR modified during active monitoring. */ +#define ICM_UASR_URAT_ICM_HASH_MODIFIED (0x3u << 0) /**< \brief (ICM_UASR) ICM_HASH modified during active monitoring */ +#define ICM_UASR_URAT_READ_ACCESS (0x4u << 0) /**< \brief (ICM_UASR) Write-only register read access */ +/* -------- ICM_DSCR : (ICM Offset: 0x30) Region Descriptor Area Start Address Register -------- */ +#define ICM_DSCR_DASA_Pos 6 +#define ICM_DSCR_DASA_Msk (0x3ffffffu << ICM_DSCR_DASA_Pos) /**< \brief (ICM_DSCR) Descriptor Area Start Address */ +#define ICM_DSCR_DASA(value) ((ICM_DSCR_DASA_Msk & ((value) << ICM_DSCR_DASA_Pos))) +/* -------- ICM_HASH : (ICM Offset: 0x34) Region Hash Area Start Address Register -------- */ +#define ICM_HASH_HASA_Pos 7 +#define ICM_HASH_HASA_Msk (0x1ffffffu << ICM_HASH_HASA_Pos) /**< \brief (ICM_HASH) Hash Area Start Address */ +#define ICM_HASH_HASA(value) ((ICM_HASH_HASA_Msk & ((value) << ICM_HASH_HASA_Pos))) +/* -------- ICM_UIHVAL[8] : (ICM Offset: 0x38) User Initial Hash Value 0 Register -------- */ +#define ICM_UIHVAL_VAL_Pos 0 +#define ICM_UIHVAL_VAL_Msk (0xffffffffu << ICM_UIHVAL_VAL_Pos) /**< \brief (ICM_UIHVAL[8]) Initial Hash Value */ +#define ICM_UIHVAL_VAL(value) ((ICM_UIHVAL_VAL_Msk & ((value) << ICM_UIHVAL_VAL_Pos))) +/* -------- ICM_ADDRSIZE : (ICM Offset: 0xEC) Address Size Register -------- */ +#define ICM_ADDRSIZE_ADDRSIZE_Pos 0 +#define ICM_ADDRSIZE_ADDRSIZE_Msk (0xffffu << ICM_ADDRSIZE_ADDRSIZE_Pos) /**< \brief (ICM_ADDRSIZE) Peripheral Bus Address Area Size */ +/* -------- ICM_IPNAME[2] : (ICM Offset: 0xF0) IP Name 1 Register -------- */ +#define ICM_IPNAME_IPNAME_Pos 0 +#define ICM_IPNAME_IPNAME_Msk (0xffffffffu << ICM_IPNAME_IPNAME_Pos) /**< \brief (ICM_IPNAME[2]) IP Name in ASCII Format */ +/* -------- ICM_FEATURES : (ICM Offset: 0xF8) Feature Register -------- */ +#define ICM_FEATURES_CFGALGO (0x1u << 0) /**< \brief (ICM_FEATURES) Configurable Algorithms */ +#define ICM_FEATURES_RFU (0x1u << 1) /**< \brief (ICM_FEATURES) Reserved for Future Use */ +#define ICM_FEATURES_CFGPP (0x1u << 2) /**< \brief (ICM_FEATURES) Configurable Processing Period */ +#define ICM_FEATURES_HDPP (0x1u << 3) /**< \brief (ICM_FEATURES) Hardcoded Processing Period */ +#define ICM_FEATURES_PDC (0x1u << 4) /**< \brief (ICM_FEATURES) Peripheral DMA Logic */ +#define ICM_FEATURES_NAIS (0x1u << 5) /**< \brief (ICM_FEATURES) No Access to Intermediate State */ +#define ICM_FEATURES_EF (0x1u << 6) /**< \brief (ICM_FEATURES) Embedded LFSR */ +#define ICM_FEATURES_SI (0x1u << 7) /**< \brief (ICM_FEATURES) Scan Intrusion */ +#define ICM_FEATURES_BTYP (0x1u << 8) /**< \brief (ICM_FEATURES) Bridge Type */ +#define ICM_FEATURES_PDCOFF0C (0x1u << 9) /**< \brief (ICM_FEATURES) PDC Offset is 0x0C */ +#define ICM_FEATURES_HSHA1 (0x1u << 16) /**< \brief (ICM_FEATURES) SHA1 Hardcoded Mode */ +#define ICM_FEATURES_HSHA224 (0x1u << 17) /**< \brief (ICM_FEATURES) SHA224 Hardcoded Mode */ +#define ICM_FEATURES_HSHA256 (0x1u << 18) /**< \brief (ICM_FEATURES) SHA256 Hardcoded Mode */ +#define ICM_FEATURES_HSHA384 (0x1u << 19) /**< \brief (ICM_FEATURES) SHA384 Hardcoded Mode */ +#define ICM_FEATURES_HSHA512 (0x1u << 20) /**< \brief (ICM_FEATURES) SHA512 Hardcoded Mode */ +/* -------- ICM_VERSION : (ICM Offset: 0xFC) Version Register -------- */ +#define ICM_VERSION_VERSION_Pos 0 +#define ICM_VERSION_VERSION_Msk (0xfffu << ICM_VERSION_VERSION_Pos) /**< \brief (ICM_VERSION) Version of the Hardware Module */ +#define ICM_VERSION_MFN_Pos 16 +#define ICM_VERSION_MFN_Msk (0x7u << ICM_VERSION_MFN_Pos) /**< \brief (ICM_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_ICM_COMPONENT_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/isi.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/isi.h new file mode 100644 index 000000000..c44674130 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/isi.h @@ -0,0 +1,293 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_ISI_COMPONENT_ +#define _SAME70_ISI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Image Sensor Interface */ +/* ============================================================================= */ +/** \addtogroup SAME70_ISI Image Sensor Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Isi hardware registers */ +typedef struct { + __IO uint32_t ISI_CFG1; /**< \brief (Isi Offset: 0x00) ISI Configuration 1 Register */ + __IO uint32_t ISI_CFG2; /**< \brief (Isi Offset: 0x04) ISI Configuration 2 Register */ + __IO uint32_t ISI_PSIZE; /**< \brief (Isi Offset: 0x08) ISI Preview Size Register */ + __IO uint32_t ISI_PDECF; /**< \brief (Isi Offset: 0x0C) ISI Preview Decimation Factor Register */ + __IO uint32_t ISI_Y2R_SET0; /**< \brief (Isi Offset: 0x10) ISI Color Space Conversion YCrCb To RGB Set 0 Register */ + __IO uint32_t ISI_Y2R_SET1; /**< \brief (Isi Offset: 0x14) ISI Color Space Conversion YCrCb To RGB Set 1 Register */ + __IO uint32_t ISI_R2Y_SET0; /**< \brief (Isi Offset: 0x18) ISI Color Space Conversion RGB To YCrCb Set 0 Register */ + __IO uint32_t ISI_R2Y_SET1; /**< \brief (Isi Offset: 0x1C) ISI Color Space Conversion RGB To YCrCb Set 1 Register */ + __IO uint32_t ISI_R2Y_SET2; /**< \brief (Isi Offset: 0x20) ISI Color Space Conversion RGB To YCrCb Set 2 Register */ + __O uint32_t ISI_CR; /**< \brief (Isi Offset: 0x24) ISI Control Register */ + __I uint32_t ISI_SR; /**< \brief (Isi Offset: 0x28) ISI Status Register */ + __O uint32_t ISI_IER; /**< \brief (Isi Offset: 0x2C) ISI Interrupt Enable Register */ + __O uint32_t ISI_IDR; /**< \brief (Isi Offset: 0x30) ISI Interrupt Disable Register */ + __I uint32_t ISI_IMR; /**< \brief (Isi Offset: 0x34) ISI Interrupt Mask Register */ + __O uint32_t ISI_DMA_CHER; /**< \brief (Isi Offset: 0x38) DMA Channel Enable Register */ + __O uint32_t ISI_DMA_CHDR; /**< \brief (Isi Offset: 0x3C) DMA Channel Disable Register */ + __I uint32_t ISI_DMA_CHSR; /**< \brief (Isi Offset: 0x40) DMA Channel Status Register */ + __IO uint32_t ISI_DMA_P_ADDR; /**< \brief (Isi Offset: 0x44) DMA Preview Base Address Register */ + __IO uint32_t ISI_DMA_P_CTRL; /**< \brief (Isi Offset: 0x48) DMA Preview Control Register */ + __IO uint32_t ISI_DMA_P_DSCR; /**< \brief (Isi Offset: 0x4C) DMA Preview Descriptor Address Register */ + __IO uint32_t ISI_DMA_C_ADDR; /**< \brief (Isi Offset: 0x50) DMA Codec Base Address Register */ + __IO uint32_t ISI_DMA_C_CTRL; /**< \brief (Isi Offset: 0x54) DMA Codec Control Register */ + __IO uint32_t ISI_DMA_C_DSCR; /**< \brief (Isi Offset: 0x58) DMA Codec Descriptor Address Register */ + __I uint32_t Reserved1[34]; + __IO uint32_t ISI_WPMR; /**< \brief (Isi Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t ISI_WPSR; /**< \brief (Isi Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved2[4]; + __I uint32_t ISI_VERSION; /**< \brief (Isi Offset: 0xFC) Version Register */ +} Isi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- ISI_CFG1 : (ISI Offset: 0x00) ISI Configuration 1 Register -------- */ +#define ISI_CFG1_HSYNC_POL (0x1u << 2) /**< \brief (ISI_CFG1) Horizontal Synchronization Polarity */ +#define ISI_CFG1_VSYNC_POL (0x1u << 3) /**< \brief (ISI_CFG1) Vertical Synchronization Polarity */ +#define ISI_CFG1_PIXCLK_POL (0x1u << 4) /**< \brief (ISI_CFG1) Pixel Clock Polarity */ +#define ISI_CFG1_GRAYLE (0x1u << 5) /**< \brief (ISI_CFG1) Grayscale Little Endian */ +#define ISI_CFG1_EMB_SYNC (0x1u << 6) /**< \brief (ISI_CFG1) Embedded Synchronization */ +#define ISI_CFG1_CRC_SYNC (0x1u << 7) /**< \brief (ISI_CFG1) Embedded Synchronization Correction */ +#define ISI_CFG1_FRATE_Pos 8 +#define ISI_CFG1_FRATE_Msk (0x7u << ISI_CFG1_FRATE_Pos) /**< \brief (ISI_CFG1) Frame Rate [0..7] */ +#define ISI_CFG1_FRATE(value) ((ISI_CFG1_FRATE_Msk & ((value) << ISI_CFG1_FRATE_Pos))) +#define ISI_CFG1_DISCR (0x1u << 11) /**< \brief (ISI_CFG1) Disable Codec Request */ +#define ISI_CFG1_FULL (0x1u << 12) /**< \brief (ISI_CFG1) Full Mode is Allowed */ +#define ISI_CFG1_THMASK_Pos 13 +#define ISI_CFG1_THMASK_Msk (0x3u << ISI_CFG1_THMASK_Pos) /**< \brief (ISI_CFG1) Threshold Mask */ +#define ISI_CFG1_THMASK(value) ((ISI_CFG1_THMASK_Msk & ((value) << ISI_CFG1_THMASK_Pos))) +#define ISI_CFG1_THMASK_BEATS_4 (0x0u << 13) /**< \brief (ISI_CFG1) Only 4 beats AHB burst allowed */ +#define ISI_CFG1_THMASK_BEATS_8 (0x1u << 13) /**< \brief (ISI_CFG1) Only 4 and 8 beats AHB burst allowed */ +#define ISI_CFG1_THMASK_BEATS_16 (0x2u << 13) /**< \brief (ISI_CFG1) 4, 8 and 16 beats AHB burst allowed */ +#define ISI_CFG1_SLD_Pos 16 +#define ISI_CFG1_SLD_Msk (0xffu << ISI_CFG1_SLD_Pos) /**< \brief (ISI_CFG1) Start of Line Delay */ +#define ISI_CFG1_SLD(value) ((ISI_CFG1_SLD_Msk & ((value) << ISI_CFG1_SLD_Pos))) +#define ISI_CFG1_SFD_Pos 24 +#define ISI_CFG1_SFD_Msk (0xffu << ISI_CFG1_SFD_Pos) /**< \brief (ISI_CFG1) Start of Frame Delay */ +#define ISI_CFG1_SFD(value) ((ISI_CFG1_SFD_Msk & ((value) << ISI_CFG1_SFD_Pos))) +/* -------- ISI_CFG2 : (ISI Offset: 0x04) ISI Configuration 2 Register -------- */ +#define ISI_CFG2_IM_VSIZE_Pos 0 +#define ISI_CFG2_IM_VSIZE_Msk (0x7ffu << ISI_CFG2_IM_VSIZE_Pos) /**< \brief (ISI_CFG2) Vertical Size of the Image Sensor [0..2047] */ +#define ISI_CFG2_IM_VSIZE(value) ((ISI_CFG2_IM_VSIZE_Msk & ((value) << ISI_CFG2_IM_VSIZE_Pos))) +#define ISI_CFG2_GS_MODE (0x1u << 11) /**< \brief (ISI_CFG2) Grayscale Pixel Format Mode */ +#define ISI_CFG2_RGB_MODE (0x1u << 12) /**< \brief (ISI_CFG2) RGB Input Mode */ +#define ISI_CFG2_GRAYSCALE (0x1u << 13) /**< \brief (ISI_CFG2) Grayscale Mode Format Enable */ +#define ISI_CFG2_RGB_SWAP (0x1u << 14) /**< \brief (ISI_CFG2) RGB Format Swap Mode */ +#define ISI_CFG2_COL_SPACE (0x1u << 15) /**< \brief (ISI_CFG2) Color Space for the Image Data */ +#define ISI_CFG2_IM_HSIZE_Pos 16 +#define ISI_CFG2_IM_HSIZE_Msk (0x7ffu << ISI_CFG2_IM_HSIZE_Pos) /**< \brief (ISI_CFG2) Horizontal Size of the Image Sensor [0..2047] */ +#define ISI_CFG2_IM_HSIZE(value) ((ISI_CFG2_IM_HSIZE_Msk & ((value) << ISI_CFG2_IM_HSIZE_Pos))) +#define ISI_CFG2_YCC_SWAP_Pos 28 +#define ISI_CFG2_YCC_SWAP_Msk (0x3u << ISI_CFG2_YCC_SWAP_Pos) /**< \brief (ISI_CFG2) YCrCb Format Swap Mode */ +#define ISI_CFG2_YCC_SWAP(value) ((ISI_CFG2_YCC_SWAP_Msk & ((value) << ISI_CFG2_YCC_SWAP_Pos))) +#define ISI_CFG2_YCC_SWAP_DEFAULT (0x0u << 28) /**< \brief (ISI_CFG2) Byte 0 Cb(i)Byte 1 Y(i)Byte 2 Cr(i)Byte 3 Y(i+1) */ +#define ISI_CFG2_YCC_SWAP_MODE1 (0x1u << 28) /**< \brief (ISI_CFG2) Byte 0 Cr(i)Byte 1 Y(i)Byte 2 Cb(i)Byte 3 Y(i+1) */ +#define ISI_CFG2_YCC_SWAP_MODE2 (0x2u << 28) /**< \brief (ISI_CFG2) Byte 0 Y(i)Byte 1 Cb(i)Byte 2 Y(i+1)Byte 3 Cr(i) */ +#define ISI_CFG2_YCC_SWAP_MODE3 (0x3u << 28) /**< \brief (ISI_CFG2) Byte 0 Y(i)Byte 1 Cr(i)Byte 2 Y(i+1)Byte 3 Cb(i) */ +#define ISI_CFG2_RGB_CFG_Pos 30 +#define ISI_CFG2_RGB_CFG_Msk (0x3u << ISI_CFG2_RGB_CFG_Pos) /**< \brief (ISI_CFG2) RGB Pixel Mapping Configuration */ +#define ISI_CFG2_RGB_CFG(value) ((ISI_CFG2_RGB_CFG_Msk & ((value) << ISI_CFG2_RGB_CFG_Pos))) +#define ISI_CFG2_RGB_CFG_DEFAULT (0x0u << 30) /**< \brief (ISI_CFG2) Byte 0 R/G(MSB)Byte 1 G(LSB)/BByte 2 R/G(MSB)Byte 3 G(LSB)/B */ +#define ISI_CFG2_RGB_CFG_MODE1 (0x1u << 30) /**< \brief (ISI_CFG2) Byte 0 B/G(MSB)Byte 1 G(LSB)/RByte 2 B/G(MSB)Byte 3 G(LSB)/R */ +#define ISI_CFG2_RGB_CFG_MODE2 (0x2u << 30) /**< \brief (ISI_CFG2) Byte 0 G(LSB)/RByte 1 B/G(MSB)Byte 2 G(LSB)/RByte 3 B/G(MSB) */ +#define ISI_CFG2_RGB_CFG_MODE3 (0x3u << 30) /**< \brief (ISI_CFG2) Byte 0 G(LSB)/BByte 1 R/G(MSB)Byte 2 G(LSB)/BByte 3 R/G(MSB) */ +/* -------- ISI_PSIZE : (ISI Offset: 0x08) ISI Preview Size Register -------- */ +#define ISI_PSIZE_PREV_VSIZE_Pos 0 +#define ISI_PSIZE_PREV_VSIZE_Msk (0x3ffu << ISI_PSIZE_PREV_VSIZE_Pos) /**< \brief (ISI_PSIZE) Vertical Size for the Preview Path */ +#define ISI_PSIZE_PREV_VSIZE(value) ((ISI_PSIZE_PREV_VSIZE_Msk & ((value) << ISI_PSIZE_PREV_VSIZE_Pos))) +#define ISI_PSIZE_PREV_HSIZE_Pos 16 +#define ISI_PSIZE_PREV_HSIZE_Msk (0x3ffu << ISI_PSIZE_PREV_HSIZE_Pos) /**< \brief (ISI_PSIZE) Horizontal Size for the Preview Path */ +#define ISI_PSIZE_PREV_HSIZE(value) ((ISI_PSIZE_PREV_HSIZE_Msk & ((value) << ISI_PSIZE_PREV_HSIZE_Pos))) +/* -------- ISI_PDECF : (ISI Offset: 0x0C) ISI Preview Decimation Factor Register -------- */ +#define ISI_PDECF_DEC_FACTOR_Pos 0 +#define ISI_PDECF_DEC_FACTOR_Msk (0xffu << ISI_PDECF_DEC_FACTOR_Pos) /**< \brief (ISI_PDECF) Decimation Factor */ +#define ISI_PDECF_DEC_FACTOR(value) ((ISI_PDECF_DEC_FACTOR_Msk & ((value) << ISI_PDECF_DEC_FACTOR_Pos))) +/* -------- ISI_Y2R_SET0 : (ISI Offset: 0x10) ISI Color Space Conversion YCrCb To RGB Set 0 Register -------- */ +#define ISI_Y2R_SET0_C0_Pos 0 +#define ISI_Y2R_SET0_C0_Msk (0xffu << ISI_Y2R_SET0_C0_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C0 */ +#define ISI_Y2R_SET0_C0(value) ((ISI_Y2R_SET0_C0_Msk & ((value) << ISI_Y2R_SET0_C0_Pos))) +#define ISI_Y2R_SET0_C1_Pos 8 +#define ISI_Y2R_SET0_C1_Msk (0xffu << ISI_Y2R_SET0_C1_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C1 */ +#define ISI_Y2R_SET0_C1(value) ((ISI_Y2R_SET0_C1_Msk & ((value) << ISI_Y2R_SET0_C1_Pos))) +#define ISI_Y2R_SET0_C2_Pos 16 +#define ISI_Y2R_SET0_C2_Msk (0xffu << ISI_Y2R_SET0_C2_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C2 */ +#define ISI_Y2R_SET0_C2(value) ((ISI_Y2R_SET0_C2_Msk & ((value) << ISI_Y2R_SET0_C2_Pos))) +#define ISI_Y2R_SET0_C3_Pos 24 +#define ISI_Y2R_SET0_C3_Msk (0xffu << ISI_Y2R_SET0_C3_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C3 */ +#define ISI_Y2R_SET0_C3(value) ((ISI_Y2R_SET0_C3_Msk & ((value) << ISI_Y2R_SET0_C3_Pos))) +/* -------- ISI_Y2R_SET1 : (ISI Offset: 0x14) ISI Color Space Conversion YCrCb To RGB Set 1 Register -------- */ +#define ISI_Y2R_SET1_C4_Pos 0 +#define ISI_Y2R_SET1_C4_Msk (0x1ffu << ISI_Y2R_SET1_C4_Pos) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Matrix Coefficient C4 */ +#define ISI_Y2R_SET1_C4(value) ((ISI_Y2R_SET1_C4_Msk & ((value) << ISI_Y2R_SET1_C4_Pos))) +#define ISI_Y2R_SET1_Yoff (0x1u << 12) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Luminance Default Offset */ +#define ISI_Y2R_SET1_Croff (0x1u << 13) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Red Chrominance Default Offset */ +#define ISI_Y2R_SET1_Cboff (0x1u << 14) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Blue Chrominance Default Offset */ +/* -------- ISI_R2Y_SET0 : (ISI Offset: 0x18) ISI Color Space Conversion RGB To YCrCb Set 0 Register -------- */ +#define ISI_R2Y_SET0_C0_Pos 0 +#define ISI_R2Y_SET0_C0_Msk (0x7fu << ISI_R2Y_SET0_C0_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C0 */ +#define ISI_R2Y_SET0_C0(value) ((ISI_R2Y_SET0_C0_Msk & ((value) << ISI_R2Y_SET0_C0_Pos))) +#define ISI_R2Y_SET0_C1_Pos 8 +#define ISI_R2Y_SET0_C1_Msk (0x7fu << ISI_R2Y_SET0_C1_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C1 */ +#define ISI_R2Y_SET0_C1(value) ((ISI_R2Y_SET0_C1_Msk & ((value) << ISI_R2Y_SET0_C1_Pos))) +#define ISI_R2Y_SET0_C2_Pos 16 +#define ISI_R2Y_SET0_C2_Msk (0x7fu << ISI_R2Y_SET0_C2_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C2 */ +#define ISI_R2Y_SET0_C2(value) ((ISI_R2Y_SET0_C2_Msk & ((value) << ISI_R2Y_SET0_C2_Pos))) +#define ISI_R2Y_SET0_Roff (0x1u << 24) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Red Component Offset */ +/* -------- ISI_R2Y_SET1 : (ISI Offset: 0x1C) ISI Color Space Conversion RGB To YCrCb Set 1 Register -------- */ +#define ISI_R2Y_SET1_C3_Pos 0 +#define ISI_R2Y_SET1_C3_Msk (0x7fu << ISI_R2Y_SET1_C3_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C3 */ +#define ISI_R2Y_SET1_C3(value) ((ISI_R2Y_SET1_C3_Msk & ((value) << ISI_R2Y_SET1_C3_Pos))) +#define ISI_R2Y_SET1_C4_Pos 8 +#define ISI_R2Y_SET1_C4_Msk (0x7fu << ISI_R2Y_SET1_C4_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C4 */ +#define ISI_R2Y_SET1_C4(value) ((ISI_R2Y_SET1_C4_Msk & ((value) << ISI_R2Y_SET1_C4_Pos))) +#define ISI_R2Y_SET1_C5_Pos 16 +#define ISI_R2Y_SET1_C5_Msk (0x7fu << ISI_R2Y_SET1_C5_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C5 */ +#define ISI_R2Y_SET1_C5(value) ((ISI_R2Y_SET1_C5_Msk & ((value) << ISI_R2Y_SET1_C5_Pos))) +#define ISI_R2Y_SET1_Goff (0x1u << 24) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Green Component Offset */ +/* -------- ISI_R2Y_SET2 : (ISI Offset: 0x20) ISI Color Space Conversion RGB To YCrCb Set 2 Register -------- */ +#define ISI_R2Y_SET2_C6_Pos 0 +#define ISI_R2Y_SET2_C6_Msk (0x7fu << ISI_R2Y_SET2_C6_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C6 */ +#define ISI_R2Y_SET2_C6(value) ((ISI_R2Y_SET2_C6_Msk & ((value) << ISI_R2Y_SET2_C6_Pos))) +#define ISI_R2Y_SET2_C7_Pos 8 +#define ISI_R2Y_SET2_C7_Msk (0x7fu << ISI_R2Y_SET2_C7_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C7 */ +#define ISI_R2Y_SET2_C7(value) ((ISI_R2Y_SET2_C7_Msk & ((value) << ISI_R2Y_SET2_C7_Pos))) +#define ISI_R2Y_SET2_C8_Pos 16 +#define ISI_R2Y_SET2_C8_Msk (0x7fu << ISI_R2Y_SET2_C8_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C8 */ +#define ISI_R2Y_SET2_C8(value) ((ISI_R2Y_SET2_C8_Msk & ((value) << ISI_R2Y_SET2_C8_Pos))) +#define ISI_R2Y_SET2_Boff (0x1u << 24) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Blue Component Offset */ +/* -------- ISI_CR : (ISI Offset: 0x24) ISI Control Register -------- */ +#define ISI_CR_ISI_EN (0x1u << 0) /**< \brief (ISI_CR) ISI Module Enable Request */ +#define ISI_CR_ISI_DIS (0x1u << 1) /**< \brief (ISI_CR) ISI Module Disable Request */ +#define ISI_CR_ISI_SRST (0x1u << 2) /**< \brief (ISI_CR) ISI Software Reset Request */ +#define ISI_CR_ISI_CDC (0x1u << 8) /**< \brief (ISI_CR) ISI Codec Request */ +/* -------- ISI_SR : (ISI Offset: 0x28) ISI Status Register -------- */ +#define ISI_SR_ENABLE (0x1u << 0) /**< \brief (ISI_SR) Module Enable */ +#define ISI_SR_DIS_DONE (0x1u << 1) /**< \brief (ISI_SR) Module Disable Request has Terminated (cleared on read) */ +#define ISI_SR_SRST (0x1u << 2) /**< \brief (ISI_SR) Module Software Reset Request has Terminated (cleared on read) */ +#define ISI_SR_CDC_PND (0x1u << 8) /**< \brief (ISI_SR) Pending Codec Request */ +#define ISI_SR_VSYNC (0x1u << 10) /**< \brief (ISI_SR) Vertical Synchronization (cleared on read) */ +#define ISI_SR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_SR) Preview DMA Transfer has Terminated (cleared on read) */ +#define ISI_SR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_SR) Codec DMA Transfer has Terminated (cleared on read) */ +#define ISI_SR_SIP (0x1u << 19) /**< \brief (ISI_SR) Synchronization in Progress */ +#define ISI_SR_P_OVR (0x1u << 24) /**< \brief (ISI_SR) Preview Datapath Overflow (cleared on read) */ +#define ISI_SR_C_OVR (0x1u << 25) /**< \brief (ISI_SR) Codec Datapath Overflow (cleared on read) */ +#define ISI_SR_CRC_ERR (0x1u << 26) /**< \brief (ISI_SR) CRC Synchronization Error (cleared on read) */ +#define ISI_SR_FR_OVR (0x1u << 27) /**< \brief (ISI_SR) Frame Rate Overrun (cleared on read) */ +/* -------- ISI_IER : (ISI Offset: 0x2C) ISI Interrupt Enable Register -------- */ +#define ISI_IER_DIS_DONE (0x1u << 1) /**< \brief (ISI_IER) Disable Done Interrupt Enable */ +#define ISI_IER_SRST (0x1u << 2) /**< \brief (ISI_IER) Software Reset Interrupt Enable */ +#define ISI_IER_VSYNC (0x1u << 10) /**< \brief (ISI_IER) Vertical Synchronization Interrupt Enable */ +#define ISI_IER_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IER) Preview DMA Transfer Done Interrupt Enable */ +#define ISI_IER_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IER) Codec DMA Transfer Done Interrupt Enable */ +#define ISI_IER_P_OVR (0x1u << 24) /**< \brief (ISI_IER) Preview Datapath Overflow Interrupt Enable */ +#define ISI_IER_C_OVR (0x1u << 25) /**< \brief (ISI_IER) Codec Datapath Overflow Interrupt Enable */ +#define ISI_IER_CRC_ERR (0x1u << 26) /**< \brief (ISI_IER) Embedded Synchronization CRC Error Interrupt Enable */ +#define ISI_IER_FR_OVR (0x1u << 27) /**< \brief (ISI_IER) Frame Rate Overflow Interrupt Enable */ +/* -------- ISI_IDR : (ISI Offset: 0x30) ISI Interrupt Disable Register -------- */ +#define ISI_IDR_DIS_DONE (0x1u << 1) /**< \brief (ISI_IDR) Disable Done Interrupt Disable */ +#define ISI_IDR_SRST (0x1u << 2) /**< \brief (ISI_IDR) Software Reset Interrupt Disable */ +#define ISI_IDR_VSYNC (0x1u << 10) /**< \brief (ISI_IDR) Vertical Synchronization Interrupt Disable */ +#define ISI_IDR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IDR) Preview DMA Transfer Done Interrupt Disable */ +#define ISI_IDR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IDR) Codec DMA Transfer Done Interrupt Disable */ +#define ISI_IDR_P_OVR (0x1u << 24) /**< \brief (ISI_IDR) Preview Datapath Overflow Interrupt Disable */ +#define ISI_IDR_C_OVR (0x1u << 25) /**< \brief (ISI_IDR) Codec Datapath Overflow Interrupt Disable */ +#define ISI_IDR_CRC_ERR (0x1u << 26) /**< \brief (ISI_IDR) Embedded Synchronization CRC Error Interrupt Disable */ +#define ISI_IDR_FR_OVR (0x1u << 27) /**< \brief (ISI_IDR) Frame Rate Overflow Interrupt Disable */ +/* -------- ISI_IMR : (ISI Offset: 0x34) ISI Interrupt Mask Register -------- */ +#define ISI_IMR_DIS_DONE (0x1u << 1) /**< \brief (ISI_IMR) Module Disable Operation Completed */ +#define ISI_IMR_SRST (0x1u << 2) /**< \brief (ISI_IMR) Software Reset Completed */ +#define ISI_IMR_VSYNC (0x1u << 10) /**< \brief (ISI_IMR) Vertical Synchronization */ +#define ISI_IMR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IMR) Preview DMA Transfer Completed */ +#define ISI_IMR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IMR) Codec DMA Transfer Completed */ +#define ISI_IMR_P_OVR (0x1u << 24) /**< \brief (ISI_IMR) Preview FIFO Overflow */ +#define ISI_IMR_C_OVR (0x1u << 25) /**< \brief (ISI_IMR) Codec FIFO Overflow */ +#define ISI_IMR_CRC_ERR (0x1u << 26) /**< \brief (ISI_IMR) CRC Synchronization Error */ +#define ISI_IMR_FR_OVR (0x1u << 27) /**< \brief (ISI_IMR) Frame Rate Overrun */ +/* -------- ISI_DMA_CHER : (ISI Offset: 0x38) DMA Channel Enable Register -------- */ +#define ISI_DMA_CHER_P_CH_EN (0x1u << 0) /**< \brief (ISI_DMA_CHER) Preview Channel Enable */ +#define ISI_DMA_CHER_C_CH_EN (0x1u << 1) /**< \brief (ISI_DMA_CHER) Codec Channel Enable */ +/* -------- ISI_DMA_CHDR : (ISI Offset: 0x3C) DMA Channel Disable Register -------- */ +#define ISI_DMA_CHDR_P_CH_DIS (0x1u << 0) /**< \brief (ISI_DMA_CHDR) Preview Channel Disable Request */ +#define ISI_DMA_CHDR_C_CH_DIS (0x1u << 1) /**< \brief (ISI_DMA_CHDR) Codec Channel Disable Request */ +/* -------- ISI_DMA_CHSR : (ISI Offset: 0x40) DMA Channel Status Register -------- */ +#define ISI_DMA_CHSR_P_CH_S (0x1u << 0) /**< \brief (ISI_DMA_CHSR) Preview DMA Channel Status */ +#define ISI_DMA_CHSR_C_CH_S (0x1u << 1) /**< \brief (ISI_DMA_CHSR) Code DMA Channel Status */ +/* -------- ISI_DMA_P_ADDR : (ISI Offset: 0x44) DMA Preview Base Address Register -------- */ +#define ISI_DMA_P_ADDR_P_ADDR_Pos 2 +#define ISI_DMA_P_ADDR_P_ADDR_Msk (0x3fffffffu << ISI_DMA_P_ADDR_P_ADDR_Pos) /**< \brief (ISI_DMA_P_ADDR) Preview Image Base Address */ +#define ISI_DMA_P_ADDR_P_ADDR(value) ((ISI_DMA_P_ADDR_P_ADDR_Msk & ((value) << ISI_DMA_P_ADDR_P_ADDR_Pos))) +/* -------- ISI_DMA_P_CTRL : (ISI Offset: 0x48) DMA Preview Control Register -------- */ +#define ISI_DMA_P_CTRL_P_FETCH (0x1u << 0) /**< \brief (ISI_DMA_P_CTRL) Descriptor Fetch Control Bit */ +#define ISI_DMA_P_CTRL_P_WB (0x1u << 1) /**< \brief (ISI_DMA_P_CTRL) Descriptor Writeback Control Bit */ +#define ISI_DMA_P_CTRL_P_IEN (0x1u << 2) /**< \brief (ISI_DMA_P_CTRL) Transfer Done Flag Control */ +#define ISI_DMA_P_CTRL_P_DONE (0x1u << 3) /**< \brief (ISI_DMA_P_CTRL) Preview Transfer Done */ +/* -------- ISI_DMA_P_DSCR : (ISI Offset: 0x4C) DMA Preview Descriptor Address Register -------- */ +#define ISI_DMA_P_DSCR_P_DSCR_Pos 2 +#define ISI_DMA_P_DSCR_P_DSCR_Msk (0x3fffffffu << ISI_DMA_P_DSCR_P_DSCR_Pos) /**< \brief (ISI_DMA_P_DSCR) Preview Descriptor Base Address */ +#define ISI_DMA_P_DSCR_P_DSCR(value) ((ISI_DMA_P_DSCR_P_DSCR_Msk & ((value) << ISI_DMA_P_DSCR_P_DSCR_Pos))) +/* -------- ISI_DMA_C_ADDR : (ISI Offset: 0x50) DMA Codec Base Address Register -------- */ +#define ISI_DMA_C_ADDR_C_ADDR_Pos 2 +#define ISI_DMA_C_ADDR_C_ADDR_Msk (0x3fffffffu << ISI_DMA_C_ADDR_C_ADDR_Pos) /**< \brief (ISI_DMA_C_ADDR) Codec Image Base Address */ +#define ISI_DMA_C_ADDR_C_ADDR(value) ((ISI_DMA_C_ADDR_C_ADDR_Msk & ((value) << ISI_DMA_C_ADDR_C_ADDR_Pos))) +/* -------- ISI_DMA_C_CTRL : (ISI Offset: 0x54) DMA Codec Control Register -------- */ +#define ISI_DMA_C_CTRL_C_FETCH (0x1u << 0) /**< \brief (ISI_DMA_C_CTRL) Descriptor Fetch Control Bit */ +#define ISI_DMA_C_CTRL_C_WB (0x1u << 1) /**< \brief (ISI_DMA_C_CTRL) Descriptor Writeback Control Bit */ +#define ISI_DMA_C_CTRL_C_IEN (0x1u << 2) /**< \brief (ISI_DMA_C_CTRL) Transfer Done Flag Control */ +#define ISI_DMA_C_CTRL_C_DONE (0x1u << 3) /**< \brief (ISI_DMA_C_CTRL) Codec Transfer Done */ +/* -------- ISI_DMA_C_DSCR : (ISI Offset: 0x58) DMA Codec Descriptor Address Register -------- */ +#define ISI_DMA_C_DSCR_C_DSCR_Pos 2 +#define ISI_DMA_C_DSCR_C_DSCR_Msk (0x3fffffffu << ISI_DMA_C_DSCR_C_DSCR_Pos) /**< \brief (ISI_DMA_C_DSCR) Codec Descriptor Base Address */ +#define ISI_DMA_C_DSCR_C_DSCR(value) ((ISI_DMA_C_DSCR_C_DSCR_Msk & ((value) << ISI_DMA_C_DSCR_C_DSCR_Pos))) +/* -------- ISI_WPMR : (ISI Offset: 0xE4) Write Protection Mode Register -------- */ +#define ISI_WPMR_WPEN (0x1u << 0) /**< \brief (ISI_WPMR) Write Protection Enable */ +#define ISI_WPMR_WPKEY_Pos 8 +#define ISI_WPMR_WPKEY_Msk (0xffffffu << ISI_WPMR_WPKEY_Pos) /**< \brief (ISI_WPMR) Write Protection Key Password */ +#define ISI_WPMR_WPKEY(value) ((ISI_WPMR_WPKEY_Msk & ((value) << ISI_WPMR_WPKEY_Pos))) +#define ISI_WPMR_WPKEY_PASSWD (0x495349u << 8) /**< \brief (ISI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- ISI_WPSR : (ISI Offset: 0xE8) Write Protection Status Register -------- */ +#define ISI_WPSR_WPVS (0x1u << 0) /**< \brief (ISI_WPSR) Write Protection Violation Status */ +#define ISI_WPSR_WPVSRC_Pos 8 +#define ISI_WPSR_WPVSRC_Msk (0xffffu << ISI_WPSR_WPVSRC_Pos) /**< \brief (ISI_WPSR) Write Protection Violation Source */ +/* -------- ISI_VERSION : (ISI Offset: 0xFC) Version Register -------- */ +#define ISI_VERSION_VERSION_Pos 0 +#define ISI_VERSION_VERSION_Msk (0xfffu << ISI_VERSION_VERSION_Pos) /**< \brief (ISI_VERSION) Version of the Hardware Module */ +#define ISI_VERSION_MFN_Pos 16 +#define ISI_VERSION_MFN_Msk (0x7u << ISI_VERSION_MFN_Pos) /**< \brief (ISI_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_ISI_COMPONENT_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/matrix.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/matrix.h new file mode 100644 index 000000000..40d858f66 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/matrix.h @@ -0,0 +1,328 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_MATRIX_COMPONENT_ +#define _SAME70_MATRIX_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */ +/* ============================================================================= */ +/** \addtogroup SAME70_MATRIX AHB Bus Matrix */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief MatrixPr hardware registers */ +typedef struct { + __IO uint32_t MATRIX_PRAS; /**< \brief (MatrixPr Offset: 0x0) Priority Register A for Slave 0 */ + __IO uint32_t MATRIX_PRBS; /**< \brief (MatrixPr Offset: 0x4) Priority Register B for Slave 0 */ +} MatrixPr; +/** \brief Matrix hardware registers */ +#define MATRIXPR_NUMBER 9 +typedef struct { + __IO uint32_t MATRIX_MCFG0; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register 0 */ + __IO uint32_t MATRIX_MCFG1; /**< \brief (Matrix Offset: 0x0004) Master Configuration Register 1 */ + __IO uint32_t MATRIX_MCFG2; /**< \brief (Matrix Offset: 0x0008) Master Configuration Register 2 */ + __IO uint32_t MATRIX_MCFG3; /**< \brief (Matrix Offset: 0x000C) Master Configuration Register 3 */ + __IO uint32_t MATRIX_MCFG4; /**< \brief (Matrix Offset: 0x0010) Master Configuration Register 4 */ + __IO uint32_t MATRIX_MCFG5; /**< \brief (Matrix Offset: 0x0014) Master Configuration Register 5 */ + __IO uint32_t MATRIX_MCFG6; /**< \brief (Matrix Offset: 0x0018) Master Configuration Register 6 */ + __I uint32_t Reserved1[1]; + __IO uint32_t MATRIX_MCFG8; /**< \brief (Matrix Offset: 0x0020) Master Configuration Register 8 */ + __IO uint32_t MATRIX_MCFG9; /**< \brief (Matrix Offset: 0x0024) Master Configuration Register 9 */ + __IO uint32_t MATRIX_MCFG10; /**< \brief (Matrix Offset: 0x0028) Master Configuration Register 10 */ + __IO uint32_t MATRIX_MCFG11; /**< \brief (Matrix Offset: 0x002C) Master Configuration Register 11 */ + __IO uint32_t MATRIX_MCFG12; /**< \brief (Matrix Offset: 0x0030) Master Configuration Register 12 */ + __I uint32_t Reserved2[3]; + __IO uint32_t MATRIX_SCFG[9]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */ + __I uint32_t Reserved3[7]; + MatrixPr MATRIX_PR[MATRIXPR_NUMBER]; /**< \brief (Matrix Offset: 0x0080) 0 .. 8 */ + __I uint32_t Reserved4[14]; + __IO uint32_t MATRIX_MRCR; /**< \brief (Matrix Offset: 0x0100) Master Remap Control Register */ + __I uint32_t Reserved5[3]; + __IO uint32_t CCFG_CAN0; /**< \brief (Matrix Offset: 0x0110) CAN0 Configuration Register */ + __IO uint32_t CCFG_SYSIO; /**< \brief (Matrix Offset: 0x0114) System I/O and CAN1 Configuration Register */ + __IO uint32_t CCFG_PCCR; /**< \brief (Matrix Offset: 0x0118) Peripheral Clock Configuration Register */ + __IO uint32_t CCFG_DYNCFG; /**< \brief (Matrix Offset: 0x011C) Dynamic Clock Gating Register */ + __I uint32_t Reserved6[1]; + __IO uint32_t CCFG_SMCNFCS; /**< \brief (Matrix Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register */ + __I uint32_t Reserved7[47]; + __IO uint32_t MATRIX_WPMR; /**< \brief (Matrix Offset: 0x01E4) Write Protection Mode Register */ + __I uint32_t MATRIX_WPSR; /**< \brief (Matrix Offset: 0x01E8) Write Protection Status Register */ + __I uint32_t Reserved8[4]; + __I uint32_t MATRIX_VERSION; /**< \brief (Matrix Offset: 0x01FC) Version Register */ +} Matrix; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- MATRIX_MCFG0 : (MATRIX Offset: 0x0000) Master Configuration Register 0 -------- */ +#define MATRIX_MCFG0_ULBT_Pos 0 +#define MATRIX_MCFG0_ULBT_Msk (0x7u << MATRIX_MCFG0_ULBT_Pos) /**< \brief (MATRIX_MCFG0) Undefined Length Burst Type */ +#define MATRIX_MCFG0_ULBT(value) ((MATRIX_MCFG0_ULBT_Msk & ((value) << MATRIX_MCFG0_ULBT_Pos))) +#define MATRIX_MCFG0_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG0) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG0_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG0) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG0_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG0) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG0_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG0) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG0_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG0) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG0_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG0) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG0_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG0) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG0_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG0) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG1 : (MATRIX Offset: 0x0004) Master Configuration Register 1 -------- */ +#define MATRIX_MCFG1_ULBT_Pos 0 +#define MATRIX_MCFG1_ULBT_Msk (0x7u << MATRIX_MCFG1_ULBT_Pos) /**< \brief (MATRIX_MCFG1) Undefined Length Burst Type */ +#define MATRIX_MCFG1_ULBT(value) ((MATRIX_MCFG1_ULBT_Msk & ((value) << MATRIX_MCFG1_ULBT_Pos))) +#define MATRIX_MCFG1_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG1) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG1_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG1) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG1_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG1) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG1_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG1) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG1_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG1) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG1_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG1) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG1_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG1) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG1_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG1) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG2 : (MATRIX Offset: 0x0008) Master Configuration Register 2 -------- */ +#define MATRIX_MCFG2_ULBT_Pos 0 +#define MATRIX_MCFG2_ULBT_Msk (0x7u << MATRIX_MCFG2_ULBT_Pos) /**< \brief (MATRIX_MCFG2) Undefined Length Burst Type */ +#define MATRIX_MCFG2_ULBT(value) ((MATRIX_MCFG2_ULBT_Msk & ((value) << MATRIX_MCFG2_ULBT_Pos))) +#define MATRIX_MCFG2_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG2) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG2_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG2) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG2_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG2) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG2_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG2) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG2_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG2) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG2_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG2) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG2_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG2) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG2_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG2) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG3 : (MATRIX Offset: 0x000C) Master Configuration Register 3 -------- */ +#define MATRIX_MCFG3_ULBT_Pos 0 +#define MATRIX_MCFG3_ULBT_Msk (0x7u << MATRIX_MCFG3_ULBT_Pos) /**< \brief (MATRIX_MCFG3) Undefined Length Burst Type */ +#define MATRIX_MCFG3_ULBT(value) ((MATRIX_MCFG3_ULBT_Msk & ((value) << MATRIX_MCFG3_ULBT_Pos))) +#define MATRIX_MCFG3_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG3) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG3_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG3) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG3_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG3) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG3_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG3) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG3_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG3) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG3_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG3) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG3_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG3) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG3_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG3) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG4 : (MATRIX Offset: 0x0010) Master Configuration Register 4 -------- */ +#define MATRIX_MCFG4_ULBT_Pos 0 +#define MATRIX_MCFG4_ULBT_Msk (0x7u << MATRIX_MCFG4_ULBT_Pos) /**< \brief (MATRIX_MCFG4) Undefined Length Burst Type */ +#define MATRIX_MCFG4_ULBT(value) ((MATRIX_MCFG4_ULBT_Msk & ((value) << MATRIX_MCFG4_ULBT_Pos))) +#define MATRIX_MCFG4_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG4) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG4_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG4) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG4_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG4) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG4_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG4) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG4_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG4) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG4_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG4) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG4_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG4) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG4_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG4) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG5 : (MATRIX Offset: 0x0014) Master Configuration Register 5 -------- */ +#define MATRIX_MCFG5_ULBT_Pos 0 +#define MATRIX_MCFG5_ULBT_Msk (0x7u << MATRIX_MCFG5_ULBT_Pos) /**< \brief (MATRIX_MCFG5) Undefined Length Burst Type */ +#define MATRIX_MCFG5_ULBT(value) ((MATRIX_MCFG5_ULBT_Msk & ((value) << MATRIX_MCFG5_ULBT_Pos))) +#define MATRIX_MCFG5_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG5) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG5_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG5) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG5_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG5) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG5_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG5) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG5_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG5) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG5_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG5) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG5_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG5) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG5_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG5) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG6 : (MATRIX Offset: 0x0018) Master Configuration Register 6 -------- */ +#define MATRIX_MCFG6_ULBT_Pos 0 +#define MATRIX_MCFG6_ULBT_Msk (0x7u << MATRIX_MCFG6_ULBT_Pos) /**< \brief (MATRIX_MCFG6) Undefined Length Burst Type */ +#define MATRIX_MCFG6_ULBT(value) ((MATRIX_MCFG6_ULBT_Msk & ((value) << MATRIX_MCFG6_ULBT_Pos))) +#define MATRIX_MCFG6_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG6) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG6_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG6) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG6_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG6) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG6_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG6) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG6_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG6) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG6_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG6) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG6_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG6) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG6_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG6) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG8 : (MATRIX Offset: 0x0020) Master Configuration Register 8 -------- */ +#define MATRIX_MCFG8_ULBT_Pos 0 +#define MATRIX_MCFG8_ULBT_Msk (0x7u << MATRIX_MCFG8_ULBT_Pos) /**< \brief (MATRIX_MCFG8) Undefined Length Burst Type */ +#define MATRIX_MCFG8_ULBT(value) ((MATRIX_MCFG8_ULBT_Msk & ((value) << MATRIX_MCFG8_ULBT_Pos))) +#define MATRIX_MCFG8_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG8) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG8_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG8) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG8_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG8) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG8_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG8) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG8_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG8) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG8_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG8) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG8_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG8) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG8_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG8) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG9 : (MATRIX Offset: 0x0024) Master Configuration Register 9 -------- */ +#define MATRIX_MCFG9_ULBT_Pos 0 +#define MATRIX_MCFG9_ULBT_Msk (0x7u << MATRIX_MCFG9_ULBT_Pos) /**< \brief (MATRIX_MCFG9) Undefined Length Burst Type */ +#define MATRIX_MCFG9_ULBT(value) ((MATRIX_MCFG9_ULBT_Msk & ((value) << MATRIX_MCFG9_ULBT_Pos))) +#define MATRIX_MCFG9_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG9) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG9_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG9) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG9_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG9) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG9_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG9) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG9_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG9) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG9_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG9) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG9_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG9) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG9_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG9) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG10 : (MATRIX Offset: 0x0028) Master Configuration Register 10 -------- */ +#define MATRIX_MCFG10_ULBT_Pos 0 +#define MATRIX_MCFG10_ULBT_Msk (0x7u << MATRIX_MCFG10_ULBT_Pos) /**< \brief (MATRIX_MCFG10) Undefined Length Burst Type */ +#define MATRIX_MCFG10_ULBT(value) ((MATRIX_MCFG10_ULBT_Msk & ((value) << MATRIX_MCFG10_ULBT_Pos))) +#define MATRIX_MCFG10_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG10) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG10_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG10) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG10_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG10) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG10_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG10) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG10_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG10) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG10_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG10) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG10_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG10) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG10_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG10) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_MCFG11 : (MATRIX Offset: 0x002C) Master Configuration Register 11 -------- */ +#define MATRIX_MCFG11_ULBT_Pos 0 +#define MATRIX_MCFG11_ULBT_Msk (0x7u << MATRIX_MCFG11_ULBT_Pos) /**< \brief (MATRIX_MCFG11) Undefined Length Burst Type */ +#define MATRIX_MCFG11_ULBT(value) ((MATRIX_MCFG11_ULBT_Msk & ((value) << MATRIX_MCFG11_ULBT_Pos))) +#define MATRIX_MCFG11_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG11) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG11_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG11) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG11_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG11) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG11_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG11) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG11_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG11) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG11_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG11) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG11_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG11) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG11_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG11) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_SCFG[9] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */ +#define MATRIX_SCFG_SLOT_CYCLE_Pos 0 +#define MATRIX_SCFG_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[9]) Maximum Bus Grant Duration for Masters */ +#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos))) +#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16 +#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[9]) Default Master Type */ +#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos))) +#define MATRIX_SCFG_DEFMSTR_TYPE_NONE (0x0u << 16) /**< \brief (MATRIX_SCFG[9]) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */ +#define MATRIX_SCFG_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG[9]) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */ +#define MATRIX_SCFG_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG[9]) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */ +#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18 +#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[9]) Fixed Default Master */ +#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos))) +/* -------- MATRIX_PRAS : (MATRIX Offset: N/A) Priority Register A for Slave 0 -------- */ +#define MATRIX_PRAS_M0PR_Pos 0 +#define MATRIX_PRAS_M0PR_Msk (0x3u << MATRIX_PRAS_M0PR_Pos) /**< \brief (MATRIX_PRAS) Master 0 Priority */ +#define MATRIX_PRAS_M0PR(value) ((MATRIX_PRAS_M0PR_Msk & ((value) << MATRIX_PRAS_M0PR_Pos))) +#define MATRIX_PRAS_M1PR_Pos 4 +#define MATRIX_PRAS_M1PR_Msk (0x3u << MATRIX_PRAS_M1PR_Pos) /**< \brief (MATRIX_PRAS) Master 1 Priority */ +#define MATRIX_PRAS_M1PR(value) ((MATRIX_PRAS_M1PR_Msk & ((value) << MATRIX_PRAS_M1PR_Pos))) +#define MATRIX_PRAS_M2PR_Pos 8 +#define MATRIX_PRAS_M2PR_Msk (0x3u << MATRIX_PRAS_M2PR_Pos) /**< \brief (MATRIX_PRAS) Master 2 Priority */ +#define MATRIX_PRAS_M2PR(value) ((MATRIX_PRAS_M2PR_Msk & ((value) << MATRIX_PRAS_M2PR_Pos))) +#define MATRIX_PRAS_M3PR_Pos 12 +#define MATRIX_PRAS_M3PR_Msk (0x3u << MATRIX_PRAS_M3PR_Pos) /**< \brief (MATRIX_PRAS) Master 3 Priority */ +#define MATRIX_PRAS_M3PR(value) ((MATRIX_PRAS_M3PR_Msk & ((value) << MATRIX_PRAS_M3PR_Pos))) +#define MATRIX_PRAS_M4PR_Pos 16 +#define MATRIX_PRAS_M4PR_Msk (0x3u << MATRIX_PRAS_M4PR_Pos) /**< \brief (MATRIX_PRAS) Master 4 Priority */ +#define MATRIX_PRAS_M4PR(value) ((MATRIX_PRAS_M4PR_Msk & ((value) << MATRIX_PRAS_M4PR_Pos))) +#define MATRIX_PRAS_M5PR_Pos 20 +#define MATRIX_PRAS_M5PR_Msk (0x3u << MATRIX_PRAS_M5PR_Pos) /**< \brief (MATRIX_PRAS) Master 5 Priority */ +#define MATRIX_PRAS_M5PR(value) ((MATRIX_PRAS_M5PR_Msk & ((value) << MATRIX_PRAS_M5PR_Pos))) +#define MATRIX_PRAS_M6PR_Pos 24 +#define MATRIX_PRAS_M6PR_Msk (0x3u << MATRIX_PRAS_M6PR_Pos) /**< \brief (MATRIX_PRAS) Master 6 Priority */ +#define MATRIX_PRAS_M6PR(value) ((MATRIX_PRAS_M6PR_Msk & ((value) << MATRIX_PRAS_M6PR_Pos))) +/* -------- MATRIX_PRBS : (MATRIX Offset: N/A) Priority Register B for Slave 0 -------- */ +#define MATRIX_PRBS_M8PR_Pos 0 +#define MATRIX_PRBS_M8PR_Msk (0x3u << MATRIX_PRBS_M8PR_Pos) /**< \brief (MATRIX_PRBS) Master 8 Priority */ +#define MATRIX_PRBS_M8PR(value) ((MATRIX_PRBS_M8PR_Msk & ((value) << MATRIX_PRBS_M8PR_Pos))) +#define MATRIX_PRBS_M9PR_Pos 4 +#define MATRIX_PRBS_M9PR_Msk (0x3u << MATRIX_PRBS_M9PR_Pos) /**< \brief (MATRIX_PRBS) Master 9 Priority */ +#define MATRIX_PRBS_M9PR(value) ((MATRIX_PRBS_M9PR_Msk & ((value) << MATRIX_PRBS_M9PR_Pos))) +#define MATRIX_PRBS_M10PR_Pos 8 +#define MATRIX_PRBS_M10PR_Msk (0x3u << MATRIX_PRBS_M10PR_Pos) /**< \brief (MATRIX_PRBS) Master 10 Priority */ +#define MATRIX_PRBS_M10PR(value) ((MATRIX_PRBS_M10PR_Msk & ((value) << MATRIX_PRBS_M10PR_Pos))) +#define MATRIX_PRBS_M11PR_Pos 12 +#define MATRIX_PRBS_M11PR_Msk (0x3u << MATRIX_PRBS_M11PR_Pos) /**< \brief (MATRIX_PRBS) Master 11 Priority */ +#define MATRIX_PRBS_M11PR(value) ((MATRIX_PRBS_M11PR_Msk & ((value) << MATRIX_PRBS_M11PR_Pos))) +#define MATRIX_PRBS_M12PR_Pos 16 +#define MATRIX_PRBS_M12PR_Msk (0x3u << MATRIX_PRBS_M12PR_Pos) /**< \brief (MATRIX_PRBS) Master 12 Priority */ +#define MATRIX_PRBS_M12PR(value) ((MATRIX_PRBS_M12PR_Msk & ((value) << MATRIX_PRBS_M12PR_Pos))) +/* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */ +#define MATRIX_MRCR_RCB0 (0x1u << 0) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 0 */ +#define MATRIX_MRCR_RCB1 (0x1u << 1) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 1 */ +#define MATRIX_MRCR_RCB2 (0x1u << 2) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 2 */ +#define MATRIX_MRCR_RCB3 (0x1u << 3) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 3 */ +#define MATRIX_MRCR_RCB4 (0x1u << 4) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 4 */ +#define MATRIX_MRCR_RCB5 (0x1u << 5) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 5 */ +#define MATRIX_MRCR_RCB6 (0x1u << 6) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 6 */ +#define MATRIX_MRCR_RCB8 (0x1u << 8) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 8 */ +#define MATRIX_MRCR_RCB9 (0x1u << 9) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 9 */ +#define MATRIX_MRCR_RCB10 (0x1u << 10) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 10 */ +#define MATRIX_MRCR_RCB11 (0x1u << 11) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 11 */ +#define MATRIX_MRCR_RCB12 (0x1u << 12) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 12 */ +/* -------- CCFG_CAN0 : (MATRIX Offset: 0x0110) CAN0 Configuration Register -------- */ +#define CCFG_CAN0_CAN0DMABA_Pos 16 +#define CCFG_CAN0_CAN0DMABA_Msk (0xffffu << CCFG_CAN0_CAN0DMABA_Pos) /**< \brief (CCFG_CAN0) CAN0 DMA Base Address */ +#define CCFG_CAN0_CAN0DMABA(value) ((CCFG_CAN0_CAN0DMABA_Msk & ((value) << CCFG_CAN0_CAN0DMABA_Pos))) +/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O and CAN1 Configuration Register -------- */ +#define CCFG_SYSIO_SYSIO4 (0x1u << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */ +#define CCFG_SYSIO_SYSIO5 (0x1u << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */ +#define CCFG_SYSIO_SYSIO6 (0x1u << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */ +#define CCFG_SYSIO_SYSIO7 (0x1u << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */ +#define CCFG_SYSIO_SYSIO12 (0x1u << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */ +#define CCFG_SYSIO_CAN1DMABA_Pos 16 +#define CCFG_SYSIO_CAN1DMABA_Msk (0xffffu << CCFG_SYSIO_CAN1DMABA_Pos) /**< \brief (CCFG_SYSIO) CAN1 DMA Base Address */ +#define CCFG_SYSIO_CAN1DMABA(value) ((CCFG_SYSIO_CAN1DMABA_Msk & ((value) << CCFG_SYSIO_CAN1DMABA_Pos))) +/* -------- CCFG_PCCR : (MATRIX Offset: 0x0118) Peripheral Clock Configuration Register -------- */ +#define CCFG_PCCR_TC0CC (0x1u << 20) /**< \brief (CCFG_PCCR) TC0 Clock Configuration */ +#define CCFG_PCCR_I2SC0CC (0x1u << 21) /**< \brief (CCFG_PCCR) I2SC0 Clock Configuration */ +#define CCFG_PCCR_I2SC1CC (0x1u << 22) /**< \brief (CCFG_PCCR) I2SC1 Clock Configuration */ +/* -------- CCFG_DYNCKG : (MATRIX Offset: 0x11c) (R/W 32) Dynamic Clock Gating Register -------- */ +#define CCFG_DYNCKG_MATCKG (0x1u << 0) /**< \brief (CCFG_DYNCKG) MATRIX Dynamic Clock Gating */ +#define CCFG_DYNCKG_BRIDCKG (0x1u << 1) /**< \brief (CCFG_DYNCKG) Bridge Dynamic Clock Gating Enable */ +#define CCFG_DYNCKG_EFCCKG (0x1u << 2) /**< \brief (CCFG_DYNCKG) EFC Dynamic Clock Gating Enable */ +/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register -------- */ +#define CCFG_SMCNFCS_SMC_NFCS0 (0x1u << 0) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS1 (0x1u << 1) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS2 (0x1u << 2) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS3 (0x1u << 3) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment */ +#define CCFG_SMCNFCS_SDRAMEN (0x1u << 4) /**< \brief (CCFG_SMCNFCS) SDRAM Enable */ +/* -------- MATRIX_WPMR : (MATRIX Offset: 0x01E4) Write Protection Mode Register -------- */ +#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protection Enable */ +#define MATRIX_WPMR_WPKEY_Pos 8 +#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protection Key */ +#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos))) +#define MATRIX_WPMR_WPKEY_PASSWD (0x4D4154u << 8) /**< \brief (MATRIX_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- MATRIX_WPSR : (MATRIX Offset: 0x01E8) Write Protection Status Register -------- */ +#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protection Violation Status */ +#define MATRIX_WPSR_WPVSRC_Pos 8 +#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protection Violation Source */ +/* -------- MATRIX_VERSION : (MATRIX Offset: 0x01FC) Version Register -------- */ +#define MATRIX_VERSION_VERSION_Pos 0 +#define MATRIX_VERSION_VERSION_Msk (0xfffu << MATRIX_VERSION_VERSION_Pos) /**< \brief (MATRIX_VERSION) Version of the Hardware Module */ +#define MATRIX_VERSION_MFN_Pos 16 +#define MATRIX_VERSION_MFN_Msk (0x7u << MATRIX_VERSION_MFN_Pos) /**< \brief (MATRIX_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_MATRIX_COMPONENT_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/mcan.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/mcan.h new file mode 100644 index 000000000..490dc5c39 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/mcan.h @@ -0,0 +1,940 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_MCAN_COMPONENT_ +#define _SAME70_MCAN_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Controller Area Network */ +/* ============================================================================= */ +/** \addtogroup SAME70_MCAN Controller Area Network */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Mcan hardware registers */ +typedef struct { + __I uint32_t MCAN_CREL; /**< \brief (Mcan Offset: 0x00) Core Release Register */ + __I uint32_t MCAN_ENDN; /**< \brief (Mcan Offset: 0x04) Endian Register */ + __IO uint32_t MCAN_CUST; /**< \brief (Mcan Offset: 0x08) Customer Register */ +#if (__SAM_M7_REVB == 1) + __IO uint32_t MCAN_DBTP; /**< \brief (Mcan Offset: 0x0C) Data Bit Timing and Prescaler Register */ +#else + __IO uint32_t MCAN_FBTP; /**< \brief (Mcan Offset: 0x0C) Fast Bit Timing and Prescaler Register */ +#endif + __IO uint32_t MCAN_TEST; /**< \brief (Mcan Offset: 0x10) Test Register */ + __IO uint32_t MCAN_RWD; /**< \brief (Mcan Offset: 0x14) RAM Watchdog Register */ + __IO uint32_t MCAN_CCCR; /**< \brief (Mcan Offset: 0x18) CC Control Register */ +#if (__SAM_M7_REVB == 1) + __IO uint32_t MCAN_NBTP; /**< \brief (Mcan Offset: 0x1C) Nominal Bit Timing and Prescaler Register */ +#else + __IO uint32_t MCAN_BTP; /**< \brief (Mcan Offset: 0x1C) Bit Timing and Prescaler Register */ +#endif + __IO uint32_t MCAN_TSCC; /**< \brief (Mcan Offset: 0x20) Timestamp Counter Configuration Register */ + __IO uint32_t MCAN_TSCV; /**< \brief (Mcan Offset: 0x24) Timestamp Counter Value Register */ + __IO uint32_t MCAN_TOCC; /**< \brief (Mcan Offset: 0x28) Timeout Counter Configuration Register */ + __IO uint32_t MCAN_TOCV; /**< \brief (Mcan Offset: 0x2C) Timeout Counter Value Register */ + __I uint32_t Reserved1[4]; + __I uint32_t MCAN_ECR; /**< \brief (Mcan Offset: 0x40) Error Counter Register */ + __I uint32_t MCAN_PSR; /**< \brief (Mcan Offset: 0x44) Protocol Status Register */ +#if (__SAM_M7_REVB == 1) + __IO uint32_t MCAN_TDCR; /**< \brief (Mcan Offset: 0x48) Transmit Delay Compensation Register */ + __I uint32_t Reserved2[1]; +#else + __I uint32_t Reserved2[2]; +#endif + __IO uint32_t MCAN_IR; /**< \brief (Mcan Offset: 0x50) Interrupt Register */ + __IO uint32_t MCAN_IE; /**< \brief (Mcan Offset: 0x54) Interrupt Enable Register */ + __IO uint32_t MCAN_ILS; /**< \brief (Mcan Offset: 0x58) Interrupt Line Select Register */ + __IO uint32_t MCAN_ILE; /**< \brief (Mcan Offset: 0x5C) Interrupt Line Enable Register */ + __I uint32_t Reserved3[8]; + __IO uint32_t MCAN_GFC; /**< \brief (Mcan Offset: 0x80) Global Filter Configuration Register */ + __IO uint32_t MCAN_SIDFC; /**< \brief (Mcan Offset: 0x84) Standard ID Filter Configuration Register */ + __IO uint32_t MCAN_XIDFC; /**< \brief (Mcan Offset: 0x88) Extended ID Filter Configuration Register */ + __I uint32_t Reserved4[1]; + __IO uint32_t MCAN_XIDAM; /**< \brief (Mcan Offset: 0x90) Extended ID AND Mask Register */ + __I uint32_t MCAN_HPMS; /**< \brief (Mcan Offset: 0x94) High Priority Message Status Register */ + __IO uint32_t MCAN_NDAT1; /**< \brief (Mcan Offset: 0x98) New Data 1 Register */ + __IO uint32_t MCAN_NDAT2; /**< \brief (Mcan Offset: 0x9C) New Data 2 Register */ + __IO uint32_t MCAN_RXF0C; /**< \brief (Mcan Offset: 0xA0) Receive FIFO 0 Configuration Register */ + __I uint32_t MCAN_RXF0S; /**< \brief (Mcan Offset: 0xA4) Receive FIFO 0 Status Register */ + __IO uint32_t MCAN_RXF0A; /**< \brief (Mcan Offset: 0xA8) Receive FIFO 0 Acknowledge Register */ + __IO uint32_t MCAN_RXBC; /**< \brief (Mcan Offset: 0xAC) Receive Rx Buffer Configuration Register */ + __IO uint32_t MCAN_RXF1C; /**< \brief (Mcan Offset: 0xB0) Receive FIFO 1 Configuration Register */ + __I uint32_t MCAN_RXF1S; /**< \brief (Mcan Offset: 0xB4) Receive FIFO 1 Status Register */ + __IO uint32_t MCAN_RXF1A; /**< \brief (Mcan Offset: 0xB8) Receive FIFO 1 Acknowledge Register */ + __IO uint32_t MCAN_RXESC; /**< \brief (Mcan Offset: 0xBC) Receive Buffer / FIFO Element Size Configuration Register */ + __IO uint32_t MCAN_TXBC; /**< \brief (Mcan Offset: 0xC0) Transmit Buffer Configuration Register */ + __I uint32_t MCAN_TXFQS; /**< \brief (Mcan Offset: 0xC4) Transmit FIFO/Queue Status Register */ + __IO uint32_t MCAN_TXESC; /**< \brief (Mcan Offset: 0xC8) Transmit Buffer Element Size Configuration Register */ + __I uint32_t MCAN_TXBRP; /**< \brief (Mcan Offset: 0xCC) Transmit Buffer Request Pending Register */ + __IO uint32_t MCAN_TXBAR; /**< \brief (Mcan Offset: 0xD0) Transmit Buffer Add Request Register */ + __IO uint32_t MCAN_TXBCR; /**< \brief (Mcan Offset: 0xD4) Transmit Buffer Cancellation Request Register */ + __I uint32_t MCAN_TXBTO; /**< \brief (Mcan Offset: 0xD8) Transmit Buffer Transmission Occurred Register */ + __I uint32_t MCAN_TXBCF; /**< \brief (Mcan Offset: 0xDC) Transmit Buffer Cancellation Finished Register */ + __IO uint32_t MCAN_TXBTIE; /**< \brief (Mcan Offset: 0xE0) Transmit Buffer Transmission Interrupt Enable Register */ + __IO uint32_t MCAN_TXBCIE; /**< \brief (Mcan Offset: 0xE4) Transmit Buffer Cancellation Finished Interrupt Enable Register */ + __I uint32_t Reserved5[2]; + __IO uint32_t MCAN_TXEFC; /**< \brief (Mcan Offset: 0xF0) Transmit Event FIFO Configuration Register */ + __I uint32_t MCAN_TXEFS; /**< \brief (Mcan Offset: 0xF4) Transmit Event FIFO Status Register */ + __IO uint32_t MCAN_TXEFA; /**< \brief (Mcan Offset: 0xF8) Transmit Event FIFO Acknowledge Register */ +} Mcan; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- MCAN_CREL : (MCAN Offset: 0x00) Core Release Register -------- */ +#define MCAN_CREL_DAY_Pos 0 +#define MCAN_CREL_DAY_Msk (0xffu << MCAN_CREL_DAY_Pos) /**< \brief (MCAN_CREL) Timestamp Day */ +#define MCAN_CREL_MON_Pos 8 +#define MCAN_CREL_MON_Msk (0xffu << MCAN_CREL_MON_Pos) /**< \brief (MCAN_CREL) Timestamp Month */ +#define MCAN_CREL_YEAR_Pos 16 +#define MCAN_CREL_YEAR_Msk (0xfu << MCAN_CREL_YEAR_Pos) /**< \brief (MCAN_CREL) Timestamp Year */ +#define MCAN_CREL_SUBSTEP_Pos 20 +#define MCAN_CREL_SUBSTEP_Msk (0xfu << MCAN_CREL_SUBSTEP_Pos) /**< \brief (MCAN_CREL) Sub-step of Core Release */ +#define MCAN_CREL_STEP_Pos 24 +#define MCAN_CREL_STEP_Msk (0xfu << MCAN_CREL_STEP_Pos) /**< \brief (MCAN_CREL) Step of Core Release */ +#define MCAN_CREL_REL_Pos 28 +#define MCAN_CREL_REL_Msk (0xfu << MCAN_CREL_REL_Pos) /**< \brief (MCAN_CREL) Core Release */ +/* -------- MCAN_ENDN : (MCAN Offset: 0x04) Endian Register -------- */ +#define MCAN_ENDN_ETV_Pos 0 +#define MCAN_ENDN_ETV_Msk (0xffffffffu << MCAN_ENDN_ETV_Pos) /**< \brief (MCAN_ENDN) Endianness Test Value */ +/* -------- MCAN_CUST : (MCAN Offset: 0x08) Customer Register -------- */ +#define MCAN_CUST_CSV_Pos 0 +#define MCAN_CUST_CSV_Msk (0xffffffffu << MCAN_CUST_CSV_Pos) /**< \brief (MCAN_CUST) Customer-specific Value */ +#define MCAN_CUST_CSV(value) ((MCAN_CUST_CSV_Msk & ((value) << MCAN_CUST_CSV_Pos))) +/* -------- MCAN_FBTP : (MCAN Offset: 0x0C) Fast Bit Timing and Prescaler Register -------- */ +#define MCAN_FBTP_FSJW_Pos 0 +#define MCAN_FBTP_FSJW_Msk (0x3u << MCAN_FBTP_FSJW_Pos) /**< \brief (MCAN_FBTP) Fast (Re) Synchronization Jump Width */ +#define MCAN_FBTP_FSJW(value) ((MCAN_FBTP_FSJW_Msk & ((value) << MCAN_FBTP_FSJW_Pos))) +#define MCAN_FBTP_FTSEG2_Pos 4 +#define MCAN_FBTP_FTSEG2_Msk (0x7u << MCAN_FBTP_FTSEG2_Pos) /**< \brief (MCAN_FBTP) Fast Time Segment After Sample Point */ +#define MCAN_FBTP_FTSEG2(value) ((MCAN_FBTP_FTSEG2_Msk & ((value) << MCAN_FBTP_FTSEG2_Pos))) +#define MCAN_FBTP_FTSEG1_Pos 8 +#define MCAN_FBTP_FTSEG1_Msk (0xfu << MCAN_FBTP_FTSEG1_Pos) /**< \brief (MCAN_FBTP) Fast Time Segment Before Sample Point */ +#define MCAN_FBTP_FTSEG1(value) ((MCAN_FBTP_FTSEG1_Msk & ((value) << MCAN_FBTP_FTSEG1_Pos))) +#define MCAN_FBTP_FBRP_Pos 16 +#define MCAN_FBTP_FBRP_Msk (0x1fu << MCAN_FBTP_FBRP_Pos) /**< \brief (MCAN_FBTP) Fast Baud Rate Prescaler */ +#define MCAN_FBTP_FBRP(value) ((MCAN_FBTP_FBRP_Msk & ((value) << MCAN_FBTP_FBRP_Pos))) +#define MCAN_FBTP_TDC (0x1u << 23) /**< \brief (MCAN_FBTP) Transceiver Delay Compensation */ +#define MCAN_FBTP_TDC_DISABLED (0x0u << 23) /**< \brief (MCAN_FBTP) Transceiver Delay Compensation disabled. */ +#define MCAN_FBTP_TDC_ENABLED (0x1u << 23) /**< \brief (MCAN_FBTP) Transceiver Delay Compensation enabled. */ +#define MCAN_FBTP_TDCO_Pos 24 +#define MCAN_FBTP_TDCO_Msk (0x1fu << MCAN_FBTP_TDCO_Pos) /**< \brief (MCAN_FBTP) Transce iver Delay Compensation Offset */ +#define MCAN_FBTP_TDCO(value) ((MCAN_FBTP_TDCO_Msk & ((value) << MCAN_FBTP_TDCO_Pos))) +/* -------- MCAN_DBTP : (MCAN Offset: 0x0C) Data Bit Timing and Prescaler Register -------- */ +#define MCAN_DBTP_DSJW_Pos 0 +#define MCAN_DBTP_DSJW_Msk (0x7u << MCAN_DBTP_DSJW_Pos) /**< \brief (MCAN_DBTP) Data (Re) Synchronization Jump Width */ +#define MCAN_DBTP_DSJW(value) ((MCAN_DBTP_DSJW_Msk & ((value) << MCAN_DBTP_DSJW_Pos))) +#define MCAN_DBTP_DTSEG2_Pos 4 +#define MCAN_DBTP_DTSEG2_Msk (0xfu << MCAN_DBTP_DTSEG2_Pos) /**< \brief (MCAN_DBTP) Data Time Segment After Sample Point */ +#define MCAN_DBTP_DTSEG2(value) ((MCAN_DBTP_DTSEG2_Msk & ((value) << MCAN_DBTP_DTSEG2_Pos))) +#define MCAN_DBTP_DTSEG1_Pos 8 +#define MCAN_DBTP_DTSEG1_Msk (0x1fu << MCAN_DBTP_DTSEG1_Pos) /**< \brief (MCAN_DBTP) Data Time Segment Before Sample Point */ +#define MCAN_DBTP_DTSEG1(value) ((MCAN_DBTP_DTSEG1_Msk & ((value) << MCAN_DBTP_DTSEG1_Pos))) +#define MCAN_DBTP_DBRP_Pos 16 +#define MCAN_DBTP_DBRP_Msk (0x1fu << MCAN_DBTP_DBRP_Pos) /**< \brief (MCAN_DBTP) Data Bit Rate Prescaler */ +#define MCAN_DBTP_DBRP(value) ((MCAN_DBTP_DBRP_Msk & ((value) << MCAN_DBTP_DBRP_Pos))) +#define MCAN_DBTP_TDC (0x1u << 23) /**< \brief (MCAN_DBTP) Transmitter Delay Compensation */ +#define MCAN_DBTP_TDC_DISABLED (0x0u << 23) /**< \brief (MCAN_DBTP) Transmitter Delay Compensation disabled. */ +#define MCAN_DBTP_TDC_ENABLED (0x1u << 23) /**< \brief (MCAN_DBTP) Transmitter Delay Compensation enabled. */ +/* -------- MCAN_TEST : (MCAN Offset: 0x10) Test Register -------- */ +#define MCAN_TEST_LBCK (0x1u << 4) /**< \brief (MCAN_TEST) Loop Back Mode (read/write) */ +#define MCAN_TEST_LBCK_DISABLED (0x0u << 4) /**< \brief (MCAN_TEST) Reset value. Loop Back mode is disabled. */ +#define MCAN_TEST_LBCK_ENABLED (0x1u << 4) /**< \brief (MCAN_TEST) Loop Back mode is enabled (see Section 6.1.9). */ +#define MCAN_TEST_TX_Pos 5 +#define MCAN_TEST_TX_Msk (0x3u << MCAN_TEST_TX_Pos) /**< \brief (MCAN_TEST) Control of Transmit Pin (read/write) */ +#define MCAN_TEST_TX(value) ((MCAN_TEST_TX_Msk & ((value) << MCAN_TEST_TX_Pos))) +#define MCAN_TEST_TX_RESET (0x0u << 5) /**< \brief (MCAN_TEST) Reset value, CANTX controlled by the CAN Core, updated at the end of the CAN bit time. */ +#define MCAN_TEST_TX_SAMPLE_POINT_MONITORING (0x1u << 5) /**< \brief (MCAN_TEST) Sample Point can be monitored at pin CANTX. */ +#define MCAN_TEST_TX_DOMINANT (0x2u << 5) /**< \brief (MCAN_TEST) Dominant ('0') level at pin CANTX. */ +#define MCAN_TEST_TX_RECESSIVE (0x3u << 5) /**< \brief (MCAN_TEST) Recessive ('1') at pin CANTX. */ +#define MCAN_TEST_RX (0x1u << 7) /**< \brief (MCAN_TEST) Receive Pin (read-only) */ +#define MCAN_TEST_TDCV_Pos 8 +#define MCAN_TEST_TDCV_Msk (0x3fu << MCAN_TEST_TDCV_Pos) /**< \brief (MCAN_TEST) Transceiver Delay Compensation Value (read-only) */ +#define MCAN_TEST_TDCV(value) ((MCAN_TEST_TDCV_Msk & ((value) << MCAN_TEST_TDCV_Pos))) +/* -------- MCAN_RWD : (MCAN Offset: 0x14) RAM Watchdog Register -------- */ +#define MCAN_RWD_WDC_Pos 0 +#define MCAN_RWD_WDC_Msk (0xffu << MCAN_RWD_WDC_Pos) /**< \brief (MCAN_RWD) Watchdog Configuration (read/write) */ +#define MCAN_RWD_WDC(value) ((MCAN_RWD_WDC_Msk & ((value) << MCAN_RWD_WDC_Pos))) +#define MCAN_RWD_WDV_Pos 8 +#define MCAN_RWD_WDV_Msk (0xffu << MCAN_RWD_WDV_Pos) /**< \brief (MCAN_RWD) Watchdog Value (read-only) */ +#define MCAN_RWD_WDV(value) ((MCAN_RWD_WDV_Msk & ((value) << MCAN_RWD_WDV_Pos))) +/* -------- MCAN_CCCR : (MCAN Offset: 0x18) CC Control Register -------- */ +#define MCAN_CCCR_INIT (0x1u << 0) /**< \brief (MCAN_CCCR) Initialization (read/write) */ +#define MCAN_CCCR_INIT_DISABLED (0x0u << 0) /**< \brief (MCAN_CCCR) Normal operation. */ +#define MCAN_CCCR_INIT_ENABLED (0x1u << 0) /**< \brief (MCAN_CCCR) Initialization is started. */ +#define MCAN_CCCR_CCE (0x1u << 1) /**< \brief (MCAN_CCCR) Configuration Change Enable (read/write, write protection) */ +#define MCAN_CCCR_CCE_PROTECTED (0x0u << 1) /**< \brief (MCAN_CCCR) The processor has no write access to the protected configuration registers. */ +#define MCAN_CCCR_CCE_CONFIGURABLE (0x1u << 1) /**< \brief (MCAN_CCCR) The processor has write access to the protected configuration registers (while MCAN_CCCR.INIT = '1'). */ +#define MCAN_CCCR_ASM (0x1u << 2) /**< \brief (MCAN_CCCR) Restricted Operation Mode (read/write, write protection against '1') */ +#define MCAN_CCCR_ASM_NORMAL (0x0u << 2) /**< \brief (MCAN_CCCR) Normal CAN operation. */ +#define MCAN_CCCR_ASM_RESTRICTED (0x1u << 2) /**< \brief (MCAN_CCCR) Restricted operation mode active. */ +#define MCAN_CCCR_CSA (0x1u << 3) /**< \brief (MCAN_CCCR) Clock Stop Acknowledge (read-only) */ +#define MCAN_CCCR_CSR (0x1u << 4) /**< \brief (MCAN_CCCR) Clock Stop Request (read/write) */ +#define MCAN_CCCR_CSR_NO_CLOCK_STOP (0x0u << 4) /**< \brief (MCAN_CCCR) No clock stop is requested. */ +#define MCAN_CCCR_CSR_CLOCK_STOP (0x1u << 4) /**< \brief (MCAN_CCCR) Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pend-ing transfer requests have been completed and the CAN bus reached idle. */ +#define MCAN_CCCR_MON (0x1u << 5) /**< \brief (MCAN_CCCR) Bus Monitoring Mode (read/write, write protection against '1') */ +#define MCAN_CCCR_MON_DISABLED (0x0u << 5) /**< \brief (MCAN_CCCR) Bus Monitoring mode is disabled. */ +#define MCAN_CCCR_MON_ENABLED (0x1u << 5) /**< \brief (MCAN_CCCR) Bus Monitoring mode is enabled. */ +#define MCAN_CCCR_DAR (0x1u << 6) /**< \brief (MCAN_CCCR) Disable Automatic Retransmission (read/write, write protection) */ +#define MCAN_CCCR_DAR_AUTO_RETX (0x0u << 6) /**< \brief (MCAN_CCCR) Automatic retransmission of messages not transmitted successfully enabled. */ +#define MCAN_CCCR_DAR_NO_AUTO_RETX (0x1u << 6) /**< \brief (MCAN_CCCR) Automatic retransmission disabled. */ +#define MCAN_CCCR_TEST (0x1u << 7) /**< \brief (MCAN_CCCR) Test Mode Enable (read/write, write protection against '1') */ +#define MCAN_CCCR_TEST_DISABLED (0x0u << 7) /**< \brief (MCAN_CCCR) Normal operation, MCAN_TEST register holds reset values. */ +#define MCAN_CCCR_TEST_ENABLED (0x1u << 7) /**< \brief (MCAN_CCCR) Test mode, write access to MCAN_TEST register enabled. */ +#define MCAN_CCCR_CME_Pos 8 +#define MCAN_CCCR_CME_Msk (0x3u << MCAN_CCCR_CME_Pos) /**< \brief (MCAN_CCCR) CAN Mode Enable (read/write, write protection) */ +#define MCAN_CCCR_CME(value) ((MCAN_CCCR_CME_Msk & ((value) << MCAN_CCCR_CME_Pos))) +#define MCAN_CCCR_CME_ISO11898_1 (0x0u << 8) /**< \brief (MCAN_CCCR) CAN operation according to ISO11898-1 enabled */ +#define MCAN_CCCR_CME_FD (0x1u << 8) /**< \brief (MCAN_CCCR) CAN FD operation enabled */ +#define MCAN_CCCR_CMR_Pos 10 +#define MCAN_CCCR_CMR_Msk (0x3u << MCAN_CCCR_CMR_Pos) /**< \brief (MCAN_CCCR) CAN Mode Request (read/write) */ +#define MCAN_CCCR_CMR(value) ((MCAN_CCCR_CMR_Msk & ((value) << MCAN_CCCR_CMR_Pos))) +#define MCAN_CCCR_CMR_NO_CHANGE (0x0u << 10) /**< \brief (MCAN_CCCR) No mode change */ +#define MCAN_CCCR_CMR_FD (0x1u << 10) /**< \brief (MCAN_CCCR) Request CAN FD operation */ +#define MCAN_CCCR_CMR_FD_BITRATE_SWITCH (0x2u << 10) /**< \brief (MCAN_CCCR) Request CAN FD operation with bit rate switching */ +#define MCAN_CCCR_CMR_ISO11898_1 (0x3u << 10) /**< \brief (MCAN_CCCR) Request CAN operation according ISO11898-1 */ +#define MCAN_CCCR_FDO (0x1u << 12) /**< \brief (MCAN_CCCR) CAN FD Operation (read-only) */ +#define MCAN_CCCR_FDBS (0x1u << 13) /**< \brief (MCAN_CCCR) CAN FD Bit Rate Switching (read-only) */ +#define MCAN_CCCR_FDOE (0x1u << 8) /**< \brief (MCAN_CCCR) CAN FD Operation Enable (read/write, write protection) */ +#define MCAN_CCCR_FDOE_DISABLED (0x0u << 8) /**< \brief (MCAN_CCCR) FD operation disabled. */ +#define MCAN_CCCR_FDOE_ENABLED (0x1u << 8) /**< \brief (MCAN_CCCR) FD operation enabled. */ +#define MCAN_CCCR_BRSE (0x1u << 9) /**< \brief (MCAN_CCCR) Bit Rate Switching Enable (read/write, write protection) */ +#define MCAN_CCCR_BRSE_DISABLED (0x0u << 9) /**< \brief (MCAN_CCCR) Bit rate switching for transmissions disabled. */ +#define MCAN_CCCR_BRSE_ENABLED (0x1u << 9) /**< \brief (MCAN_CCCR) Bit rate switching for transmissions enabled. */ +#define MCAN_CCCR_PXHD (0x1u << 12) /**< \brief (MCAN_CCCR) Protocol Exception Event Handling (read/write, write protection) */ +#define MCAN_CCCR_EFBI (0x1u << 13) /**< \brief (MCAN_CCCR) Edge Filtering during Bus Integration (read/write, write protection) */ +#define MCAN_CCCR_TXP (0x1u << 14) /**< \brief (MCAN_CCCR) Transmit Pause (read/write, write protection) */ +#define MCAN_CCCR_NISO (0x1u << 15) /**< \brief (MCAN_CCCR) Non-ISO Operation */ +/* -------- MCAN_BTP : (MCAN Offset: 0x1C) Bit Timing and Prescaler Register -------- */ +#define MCAN_BTP_SJW_Pos 0 +#define MCAN_BTP_SJW_Msk (0xfu << MCAN_BTP_SJW_Pos) /**< \brief (MCAN_BTP) (Re) Synchronization Jump Width */ +#define MCAN_BTP_SJW(value) ((MCAN_BTP_SJW_Msk & ((value) << MCAN_BTP_SJW_Pos))) +#define MCAN_BTP_TSEG2_Pos 4 +#define MCAN_BTP_TSEG2_Msk (0xfu << MCAN_BTP_TSEG2_Pos) /**< \brief (MCAN_BTP) Time Segment After Sample Point */ +#define MCAN_BTP_TSEG2(value) ((MCAN_BTP_TSEG2_Msk & ((value) << MCAN_BTP_TSEG2_Pos))) +#define MCAN_BTP_TSEG1_Pos 8 +#define MCAN_BTP_TSEG1_Msk (0x3fu << MCAN_BTP_TSEG1_Pos) /**< \brief (MCAN_BTP) Time Segment Before Sample Point */ +#define MCAN_BTP_TSEG1(value) ((MCAN_BTP_TSEG1_Msk & ((value) << MCAN_BTP_TSEG1_Pos))) +#define MCAN_BTP_BRP_Pos 16 +#define MCAN_BTP_BRP_Msk (0x3ffu << MCAN_BTP_BRP_Pos) /**< \brief (MCAN_BTP) Baud Rate Prescaler */ +#define MCAN_BTP_BRP(value) ((MCAN_BTP_BRP_Msk & ((value) << MCAN_BTP_BRP_Pos))) +/* -------- MCAN_NBTP : (MCAN Offset: 0x1C) Nominal Bit Timing and Prescaler Register -------- */ +#define MCAN_NBTP_NTSEG2_Pos 0 +#define MCAN_NBTP_NTSEG2_Msk (0x7fu << MCAN_NBTP_NTSEG2_Pos) /**< \brief (MCAN_NBTP) Nominal Time Segment After Sample Point */ +#define MCAN_NBTP_NTSEG2(value) ((MCAN_NBTP_NTSEG2_Msk & ((value) << MCAN_NBTP_NTSEG2_Pos))) +#define MCAN_NBTP_NTSEG1_Pos 8 +#define MCAN_NBTP_NTSEG1_Msk (0xffu << MCAN_NBTP_NTSEG1_Pos) /**< \brief (MCAN_NBTP) Nominal Time Segment Before Sample Point */ +#define MCAN_NBTP_NTSEG1(value) ((MCAN_NBTP_NTSEG1_Msk & ((value) << MCAN_NBTP_NTSEG1_Pos))) +#define MCAN_NBTP_NBRP_Pos 16 +#define MCAN_NBTP_NBRP_Msk (0x1ffu << MCAN_NBTP_NBRP_Pos) /**< \brief (MCAN_NBTP) Nominal Bit Rate Prescaler */ +#define MCAN_NBTP_NBRP(value) ((MCAN_NBTP_NBRP_Msk & ((value) << MCAN_NBTP_NBRP_Pos))) +#define MCAN_NBTP_NSJW_Pos 25 +#define MCAN_NBTP_NSJW_Msk (0x7fu << MCAN_NBTP_NSJW_Pos) /**< \brief (MCAN_NBTP) Nominal (Re) Synchronization Jump Width */ +#define MCAN_NBTP_NSJW(value) ((MCAN_NBTP_NSJW_Msk & ((value) << MCAN_NBTP_NSJW_Pos))) +/* -------- MCAN_TSCC : (MCAN Offset: 0x20) Timestamp Counter Configuration Register -------- */ +#define MCAN_TSCC_TSS_Pos 0 +#define MCAN_TSCC_TSS_Msk (0x3u << MCAN_TSCC_TSS_Pos) /**< \brief (MCAN_TSCC) Timestamp Select */ +#define MCAN_TSCC_TSS(value) ((MCAN_TSCC_TSS_Msk & ((value) << MCAN_TSCC_TSS_Pos))) +#define MCAN_TSCC_TSS_ALWAYS_0 (0x0u << 0) /**< \brief (MCAN_TSCC) Timestamp counter value always 0x0000 */ +#define MCAN_TSCC_TSS_TCP_INC (0x1u << 0) /**< \brief (MCAN_TSCC) Timestamp counter value incremented according to TCP */ +#define MCAN_TSCC_TSS_EXT_TIMESTAMP (0x2u << 0) /**< \brief (MCAN_TSCC) External timestamp counter value used */ +#define MCAN_TSCC_TCP_Pos 16 +#define MCAN_TSCC_TCP_Msk (0xfu << MCAN_TSCC_TCP_Pos) /**< \brief (MCAN_TSCC) Timestamp Counter Prescaler */ +#define MCAN_TSCC_TCP(value) ((MCAN_TSCC_TCP_Msk & ((value) << MCAN_TSCC_TCP_Pos))) +/* -------- MCAN_TSCV : (MCAN Offset: 0x24) Timestamp Counter Value Register -------- */ +#define MCAN_TSCV_TSC_Pos 0 +#define MCAN_TSCV_TSC_Msk (0xffffu << MCAN_TSCV_TSC_Pos) /**< \brief (MCAN_TSCV) Timestamp Counter (cleared on write) */ +#define MCAN_TSCV_TSC(value) ((MCAN_TSCV_TSC_Msk & ((value) << MCAN_TSCV_TSC_Pos))) +/* -------- MCAN_TOCC : (MCAN Offset: 0x28) Timeout Counter Configuration Register -------- */ +#define MCAN_TOCC_ETOC (0x1u << 0) /**< \brief (MCAN_TOCC) Enable Timeout Counter */ +#define MCAN_TOCC_ETOC_NO_TIMEOUT (0x0u << 0) /**< \brief (MCAN_TOCC) Timeout Counter disabled. */ +#define MCAN_TOCC_ETOC_TOS_CONTROLLED (0x1u << 0) /**< \brief (MCAN_TOCC) Timeout Counter enabled. */ +#define MCAN_TOCC_TOS_Pos 1 +#define MCAN_TOCC_TOS_Msk (0x3u << MCAN_TOCC_TOS_Pos) /**< \brief (MCAN_TOCC) Timeout Select */ +#define MCAN_TOCC_TOS(value) ((MCAN_TOCC_TOS_Msk & ((value) << MCAN_TOCC_TOS_Pos))) +#define MCAN_TOCC_TOS_CONTINUOUS (0x0u << 1) /**< \brief (MCAN_TOCC) Continuous operation */ +#define MCAN_TOCC_TOS_TX_EV_TIMEOUT (0x1u << 1) /**< \brief (MCAN_TOCC) Timeout controlled by Tx Event FIFO */ +#define MCAN_TOCC_TOS_RX0_EV_TIMEOUT (0x2u << 1) /**< \brief (MCAN_TOCC) Timeout controlled by Receive FIFO 0 */ +#define MCAN_TOCC_TOS_RX1_EV_TIMEOUT (0x3u << 1) /**< \brief (MCAN_TOCC) Timeout controlled by Receive FIFO 1 */ +#define MCAN_TOCC_TOP_Pos 16 +#define MCAN_TOCC_TOP_Msk (0xffffu << MCAN_TOCC_TOP_Pos) /**< \brief (MCAN_TOCC) Timeout Period */ +#define MCAN_TOCC_TOP(value) ((MCAN_TOCC_TOP_Msk & ((value) << MCAN_TOCC_TOP_Pos))) +/* -------- MCAN_TOCV : (MCAN Offset: 0x2C) Timeout Counter Value Register -------- */ +#define MCAN_TOCV_TOC_Pos 0 +#define MCAN_TOCV_TOC_Msk (0xffffu << MCAN_TOCV_TOC_Pos) /**< \brief (MCAN_TOCV) Timeout Counter (cleared on write) */ +#define MCAN_TOCV_TOC(value) ((MCAN_TOCV_TOC_Msk & ((value) << MCAN_TOCV_TOC_Pos))) +/* -------- MCAN_ECR : (MCAN Offset: 0x40) Error Counter Register -------- */ +#define MCAN_ECR_TEC_Pos 0 +#define MCAN_ECR_TEC_Msk (0xffu << MCAN_ECR_TEC_Pos) /**< \brief (MCAN_ECR) Transmit Error Counter */ +#define MCAN_ECR_REC_Pos 8 +#define MCAN_ECR_REC_Msk (0x7fu << MCAN_ECR_REC_Pos) /**< \brief (MCAN_ECR) Receive Error Counter */ +#define MCAN_ECR_RP (0x1u << 15) /**< \brief (MCAN_ECR) Receive Error Passive */ +#define MCAN_ECR_CEL_Pos 16 +#define MCAN_ECR_CEL_Msk (0xffu << MCAN_ECR_CEL_Pos) /**< \brief (MCAN_ECR) CAN Error Logging (cleared on read) */ +/* -------- MCAN_PSR : (MCAN Offset: 0x44) Protocol Status Register -------- */ +#define MCAN_PSR_LEC_Pos 0 +#define MCAN_PSR_LEC_Msk (0x7u << MCAN_PSR_LEC_Pos) /**< \brief (MCAN_PSR) Last Error Code (set to 111 on read) */ +#define MCAN_PSR_LEC_NO_ERROR (0x0u << 0) /**< \brief (MCAN_PSR) No error occurred since LEC has been reset by successful reception or transmission. */ +#define MCAN_PSR_LEC_STUFF_ERROR (0x1u << 0) /**< \brief (MCAN_PSR) More than 5 equal bits in a sequence have occurred in a part of a received meSsage where this is not allowed. */ +#define MCAN_PSR_LEC_FORM_ERROR (0x2u << 0) /**< \brief (MCAN_PSR) A fixed format part of a received frame has the wrong format. */ +#define MCAN_PSR_LEC_ACK_ERROR (0x3u << 0) /**< \brief (MCAN_PSR) The message transmitted by the MCAN was not acknowledged by another node. */ +#define MCAN_PSR_LEC_BIT1_ERROR (0x4u << 0) /**< \brief (MCAN_PSR) During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant. */ +#define MCAN_PSR_LEC_BIT0_ERROR (0x5u << 0) /**< \brief (MCAN_PSR) During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the processor to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). */ +#define MCAN_PSR_LEC_CRC_ERROR (0x6u << 0) /**< \brief (MCAN_PSR) The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. */ +#define MCAN_PSR_LEC_NO_CHANGE (0x7u << 0) /**< \brief (MCAN_PSR) Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows the value '7', no CAN bus event was detected since the last processor read access to the Protocol Status Register. */ +#define MCAN_PSR_ACT_Pos 3 +#define MCAN_PSR_ACT_Msk (0x3u << MCAN_PSR_ACT_Pos) /**< \brief (MCAN_PSR) Activity */ +#define MCAN_PSR_ACT_SYNCHRONIZING (0x0u << 3) /**< \brief (MCAN_PSR) Node is synchronizing on CAN communication */ +#define MCAN_PSR_ACT_IDLE (0x1u << 3) /**< \brief (MCAN_PSR) Node is neither receiver nor transmitter */ +#define MCAN_PSR_ACT_RECEIVER (0x2u << 3) /**< \brief (MCAN_PSR) Node is operating as receiver */ +#define MCAN_PSR_ACT_TRANSMITTER (0x3u << 3) /**< \brief (MCAN_PSR) Node is operating as transmitter */ +#define MCAN_PSR_EP (0x1u << 5) /**< \brief (MCAN_PSR) Error Passive */ +#define MCAN_PSR_EW (0x1u << 6) /**< \brief (MCAN_PSR) Warning Status */ +#define MCAN_PSR_BO (0x1u << 7) /**< \brief (MCAN_PSR) Bus_Off Status */ +#define MCAN_PSR_FLEC_Pos 8 +#define MCAN_PSR_FLEC_Msk (0x7u << MCAN_PSR_FLEC_Pos) /**< \brief (MCAN_PSR) Fast Last Error Code (set to 111 on read) */ +#define MCAN_PSR_DLEC_Pos 8 +#define MCAN_PSR_DLEC_Msk (0x7u << MCAN_PSR_DLEC_Pos) /**< \brief (MCAN_PSR) Data Phase Last Error Code (set to 111 on read) */ +#define MCAN_PSR_RESI (0x1u << 11) /**< \brief (MCAN_PSR) ESI Flag of Last Received CAN FD Message (cleared on read) */ +#define MCAN_PSR_RBRS (0x1u << 12) /**< \brief (MCAN_PSR) BRS Flag of Last Received CAN FD Message (cleared on read) */ +#define MCAN_PSR_REDL (0x1u << 13) /**< \brief (MCAN_PSR) Received a CAN FD Message (cleared on read) */ +#define MCAN_PSR_RFDF (0x1u << 13) /**< \brief (MCAN_PSR) Received a CAN FD Message (cleared on read) */ +#define MCAN_PSR_PXE (0x1u << 14) /**< \brief (MCAN_PSR) Protocol Exception Event (cleared on read) */ +#define MCAN_PSR_TDCV_Pos 16 +#define MCAN_PSR_TDCV_Msk (0x7fu << MCAN_PSR_TDCV_Pos) /**< \brief (MCAN_PSR) Transmitter Delay Compensation Value */ +/* -------- MCAN_TDCR : (MCAN Offset: 0x48) Transmit Delay Compensation Register -------- */ +#define MCAN_TDCR_TDCF_Pos 0 +#define MCAN_TDCR_TDCF_Msk (0x7fu << MCAN_TDCR_TDCF_Pos) /**< \brief (MCAN_TDCR) Transmitter Delay Compensation Filter */ +#define MCAN_TDCR_TDCF(value) ((MCAN_TDCR_TDCF_Msk & ((value) << MCAN_TDCR_TDCF_Pos))) +#define MCAN_TDCR_TDCO_Pos 8 +#define MCAN_TDCR_TDCO_Msk (0x7fu << MCAN_TDCR_TDCO_Pos) /**< \brief (MCAN_TDCR) Transmitter Delay Compensation Offset */ +#define MCAN_TDCR_TDCO(value) ((MCAN_TDCR_TDCO_Msk & ((value) << MCAN_TDCR_TDCO_Pos))) +/* -------- MCAN_IR : (MCAN Offset: 0x50) Interrupt Register -------- */ +#define MCAN_IR_RF0N (0x1u << 0) /**< \brief (MCAN_IR) Receive FIFO 0 New Message */ +#define MCAN_IR_RF0W (0x1u << 1) /**< \brief (MCAN_IR) Receive FIFO 0 Watermark Reached */ +#define MCAN_IR_RF0F (0x1u << 2) /**< \brief (MCAN_IR) Receive FIFO 0 Full */ +#define MCAN_IR_RF0L (0x1u << 3) /**< \brief (MCAN_IR) Receive FIFO 0 Message Lost */ +#define MCAN_IR_RF1N (0x1u << 4) /**< \brief (MCAN_IR) Receive FIFO 1 New Message */ +#define MCAN_IR_RF1W (0x1u << 5) /**< \brief (MCAN_IR) Receive FIFO 1 Watermark Reached */ +#define MCAN_IR_RF1F (0x1u << 6) /**< \brief (MCAN_IR) Receive FIFO 1 Full */ +#define MCAN_IR_RF1L (0x1u << 7) /**< \brief (MCAN_IR) Receive FIFO 1 Message Lost */ +#define MCAN_IR_HPM (0x1u << 8) /**< \brief (MCAN_IR) High Priority Message */ +#define MCAN_IR_TC (0x1u << 9) /**< \brief (MCAN_IR) Transmission Completed */ +#define MCAN_IR_TCF (0x1u << 10) /**< \brief (MCAN_IR) Transmission Cancellation Finished */ +#define MCAN_IR_TFE (0x1u << 11) /**< \brief (MCAN_IR) Tx FIFO Empty */ +#define MCAN_IR_TEFN (0x1u << 12) /**< \brief (MCAN_IR) Tx Event FIFO New Entry */ +#define MCAN_IR_TEFW (0x1u << 13) /**< \brief (MCAN_IR) Tx Event FIFO Watermark Reached */ +#define MCAN_IR_TEFF (0x1u << 14) /**< \brief (MCAN_IR) Tx Event FIFO Full */ +#define MCAN_IR_TEFL (0x1u << 15) /**< \brief (MCAN_IR) Tx Event FIFO Element Lost */ +#define MCAN_IR_TSW (0x1u << 16) /**< \brief (MCAN_IR) Timestamp Wraparound */ +#define MCAN_IR_MRAF (0x1u << 17) /**< \brief (MCAN_IR) Message RAM Access Failure */ +#define MCAN_IR_TOO (0x1u << 18) /**< \brief (MCAN_IR) Timeout Occurred */ +#define MCAN_IR_DRX (0x1u << 19) /**< \brief (MCAN_IR) Message stored to Dedicated Receive Buffer */ +#define MCAN_IR_ELO (0x1u << 22) /**< \brief (MCAN_IR) Error Logging Overflow */ +#define MCAN_IR_EP (0x1u << 23) /**< \brief (MCAN_IR) Error Passive */ +#define MCAN_IR_EW (0x1u << 24) /**< \brief (MCAN_IR) Warning Status */ +#define MCAN_IR_BO (0x1u << 25) /**< \brief (MCAN_IR) Bus_Off Status */ +#define MCAN_IR_WDI (0x1u << 26) /**< \brief (MCAN_IR) Watchdog Interrupt */ +#define MCAN_IR_CRCE (0x1u << 27) /**< \brief (MCAN_IR) CRC Error */ +#define MCAN_IR_BE (0x1u << 28) /**< \brief (MCAN_IR) Bit Error */ +#define MCAN_IR_ACKE (0x1u << 29) /**< \brief (MCAN_IR) Acknowledge Error */ +#define MCAN_IR_FOE (0x1u << 30) /**< \brief (MCAN_IR) Format Error */ +#define MCAN_IR_STE (0x1u << 31) /**< \brief (MCAN_IR) Stuff Error */ +#define MCAN_IR_PEA (0x1u << 27) /**< \brief (MCAN_IR) Protocol Error in Arbitration Phase */ +#define MCAN_IR_PED (0x1u << 28) /**< \brief (MCAN_IR) Protocol Error in Data Phase */ +#define MCAN_IR_ARA (0x1u << 29) /**< \brief (MCAN_IR) Access to Reserved Address */ +/* -------- MCAN_IE : (MCAN Offset: 0x54) Interrupt Enable Register -------- */ +#define MCAN_IE_RF0NE (0x1u << 0) /**< \brief (MCAN_IE) Receive FIFO 0 New Message Interrupt Enable */ +#define MCAN_IE_RF0WE (0x1u << 1) /**< \brief (MCAN_IE) Receive FIFO 0 Watermark Reached Interrupt Enable */ +#define MCAN_IE_RF0FE (0x1u << 2) /**< \brief (MCAN_IE) Receive FIFO 0 Full Interrupt Enable */ +#define MCAN_IE_RF0LE (0x1u << 3) /**< \brief (MCAN_IE) Receive FIFO 0 Message Lost Interrupt Enable */ +#define MCAN_IE_RF1NE (0x1u << 4) /**< \brief (MCAN_IE) Receive FIFO 1 New Message Interrupt Enable */ +#define MCAN_IE_RF1WE (0x1u << 5) /**< \brief (MCAN_IE) Receive FIFO 1 Watermark Reached Interrupt Enable */ +#define MCAN_IE_RF1FE (0x1u << 6) /**< \brief (MCAN_IE) Receive FIFO 1 Full Interrupt Enable */ +#define MCAN_IE_RF1LE (0x1u << 7) /**< \brief (MCAN_IE) Receive FIFO 1 Message Lost Interrupt Enable */ +#define MCAN_IE_HPME (0x1u << 8) /**< \brief (MCAN_IE) High Priority Message Interrupt Enable */ +#define MCAN_IE_TCE (0x1u << 9) /**< \brief (MCAN_IE) Transmission Completed Interrupt Enable */ +#define MCAN_IE_TCFE (0x1u << 10) /**< \brief (MCAN_IE) Transmission Cancellation Finished Interrupt Enable */ +#define MCAN_IE_TFEE (0x1u << 11) /**< \brief (MCAN_IE) Tx FIFO Empty Interrupt Enable */ +#define MCAN_IE_TEFNE (0x1u << 12) /**< \brief (MCAN_IE) Tx Event FIFO New Entry Interrupt Enable */ +#define MCAN_IE_TEFWE (0x1u << 13) /**< \brief (MCAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable */ +#define MCAN_IE_TEFFE (0x1u << 14) /**< \brief (MCAN_IE) Tx Event FIFO Full Interrupt Enable */ +#define MCAN_IE_TEFLE (0x1u << 15) /**< \brief (MCAN_IE) Tx Event FIFO Event Lost Interrupt Enable */ +#define MCAN_IE_TSWE (0x1u << 16) /**< \brief (MCAN_IE) Timestamp Wraparound Interrupt Enable */ +#define MCAN_IE_MRAFE (0x1u << 17) /**< \brief (MCAN_IE) Message RAM Access Failure Interrupt Enable */ +#define MCAN_IE_TOOE (0x1u << 18) /**< \brief (MCAN_IE) Timeout Occurred Interrupt Enable */ +#define MCAN_IE_DRXE (0x1u << 19) /**< \brief (MCAN_IE) Message stored to Dedicated Receive Buffer Interrupt Enable */ +#define MCAN_IE_ELOE (0x1u << 22) /**< \brief (MCAN_IE) Error Logging Overflow Interrupt Enable */ +#define MCAN_IE_EPE (0x1u << 23) /**< \brief (MCAN_IE) Error Passive Interrupt Enable */ +#define MCAN_IE_EWE (0x1u << 24) /**< \brief (MCAN_IE) Warning Status Interrupt Enable */ +#define MCAN_IE_BOE (0x1u << 25) /**< \brief (MCAN_IE) Bus_Off Status Interrupt Enable */ +#define MCAN_IE_WDIE (0x1u << 26) /**< \brief (MCAN_IE) Watchdog Interrupt Enable */ +#define MCAN_IE_CRCEE (0x1u << 27) /**< \brief (MCAN_IE) CRC Error Interrupt Enable */ +#define MCAN_IE_BEE (0x1u << 28) /**< \brief (MCAN_IE) Bit Error Interrupt Enable */ +#define MCAN_IE_ACKEE (0x1u << 29) /**< \brief (MCAN_IE) Acknowledge Error Interrupt Enable */ +#define MCAN_IE_FOEE (0x1u << 30) /**< \brief (MCAN_IE) Format Error Interrupt Enable */ +#define MCAN_IE_STEE (0x1u << 31) /**< \brief (MCAN_IE) Stuff Error Interrupt Enable */ +#define MCAN_IE_PEAE (0x1u << 27) /**< \brief (MCAN_IE) Protocol Error in Arbitration Phase Enable */ +#define MCAN_IE_PEDE (0x1u << 28) /**< \brief (MCAN_IE) Protocol Error in Data Phase Enable */ +#define MCAN_IE_ARAE (0x1u << 29) /**< \brief (MCAN_IE) Access to Reserved Address Enable */ +/* -------- MCAN_ILS : (MCAN Offset: 0x58) Interrupt Line Select Register -------- */ +#define MCAN_ILS_RF0NL (0x1u << 0) /**< \brief (MCAN_ILS) Receive FIFO 0 New Message Interrupt Line */ +#define MCAN_ILS_RF0WL (0x1u << 1) /**< \brief (MCAN_ILS) Receive FIFO 0 Watermark Reached Interrupt Line */ +#define MCAN_ILS_RF0FL (0x1u << 2) /**< \brief (MCAN_ILS) Receive FIFO 0 Full Interrupt Line */ +#define MCAN_ILS_RF0LL (0x1u << 3) /**< \brief (MCAN_ILS) Receive FIFO 0 Message Lost Interrupt Line */ +#define MCAN_ILS_RF1NL (0x1u << 4) /**< \brief (MCAN_ILS) Receive FIFO 1 New Message Interrupt Line */ +#define MCAN_ILS_RF1WL (0x1u << 5) /**< \brief (MCAN_ILS) Receive FIFO 1 Watermark Reached Interrupt Line */ +#define MCAN_ILS_RF1FL (0x1u << 6) /**< \brief (MCAN_ILS) Receive FIFO 1 Full Interrupt Line */ +#define MCAN_ILS_RF1LL (0x1u << 7) /**< \brief (MCAN_ILS) Receive FIFO 1 Message Lost Interrupt Line */ +#define MCAN_ILS_HPML (0x1u << 8) /**< \brief (MCAN_ILS) High Priority Message Interrupt Line */ +#define MCAN_ILS_TCL (0x1u << 9) /**< \brief (MCAN_ILS) Transmission Completed Interrupt Line */ +#define MCAN_ILS_TCFL (0x1u << 10) /**< \brief (MCAN_ILS) Transmission Cancellation Finished Interrupt Line */ +#define MCAN_ILS_TFEL (0x1u << 11) /**< \brief (MCAN_ILS) Tx FIFO Empty Interrupt Line */ +#define MCAN_ILS_TEFNL (0x1u << 12) /**< \brief (MCAN_ILS) Tx Event FIFO New Entry Interrupt Line */ +#define MCAN_ILS_TEFWL (0x1u << 13) /**< \brief (MCAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line */ +#define MCAN_ILS_TEFFL (0x1u << 14) /**< \brief (MCAN_ILS) Tx Event FIFO Full Interrupt Line */ +#define MCAN_ILS_TEFLL (0x1u << 15) /**< \brief (MCAN_ILS) Tx Event FIFO Event Lost Interrupt Line */ +#define MCAN_ILS_TSWL (0x1u << 16) /**< \brief (MCAN_ILS) Timestamp Wraparound Interrupt Line */ +#define MCAN_ILS_MRAFL (0x1u << 17) /**< \brief (MCAN_ILS) Message RAM Access Failure Interrupt Line */ +#define MCAN_ILS_TOOL (0x1u << 18) /**< \brief (MCAN_ILS) Timeout Occurred Interrupt Line */ +#define MCAN_ILS_DRXL (0x1u << 19) /**< \brief (MCAN_ILS) Message stored to Dedicated Receive Buffer Interrupt Line */ +#define MCAN_ILS_ELOL (0x1u << 22) /**< \brief (MCAN_ILS) Error Logging Overflow Interrupt Line */ +#define MCAN_ILS_EPL (0x1u << 23) /**< \brief (MCAN_ILS) Error Passive Interrupt Line */ +#define MCAN_ILS_EWL (0x1u << 24) /**< \brief (MCAN_ILS) Warning Status Interrupt Line */ +#define MCAN_ILS_BOL (0x1u << 25) /**< \brief (MCAN_ILS) Bus_Off Status Interrupt Line */ +#define MCAN_ILS_WDIL (0x1u << 26) /**< \brief (MCAN_ILS) Watchdog Interrupt Line */ +#define MCAN_ILS_CRCEL (0x1u << 27) /**< \brief (MCAN_ILS) CRC Error Interrupt Line */ +#define MCAN_ILS_BEL (0x1u << 28) /**< \brief (MCAN_ILS) Bit Error Interrupt Line */ +#define MCAN_ILS_ACKEL (0x1u << 29) /**< \brief (MCAN_ILS) Acknowledge Error Interrupt Line */ +#define MCAN_ILS_FOEL (0x1u << 30) /**< \brief (MCAN_ILS) Format Error Interrupt Line */ +#define MCAN_ILS_STEL (0x1u << 31) /**< \brief (MCAN_ILS) Stuff Error Interrupt Line */ +#define MCAN_ILS_PEAL (0x1u << 27) /**< \brief (MCAN_ILS) Protocol Error in Arbitration Phase Line */ +#define MCAN_ILS_PEDL (0x1u << 28) /**< \brief (MCAN_ILS) Protocol Error in Data Phase Line */ +#define MCAN_ILS_ARAL (0x1u << 29) /**< \brief (MCAN_ILS) Access to Reserved Address Line */ +/* -------- MCAN_ILE : (MCAN Offset: 0x5C) Interrupt Line Enable Register -------- */ +#define MCAN_ILE_EINT0 (0x1u << 0) /**< \brief (MCAN_ILE) Enable Interrupt Line 0 */ +#define MCAN_ILE_EINT1 (0x1u << 1) /**< \brief (MCAN_ILE) Enable Interrupt Line 1 */ +/* -------- MCAN_GFC : (MCAN Offset: 0x80) Global Filter Configuration Register -------- */ +#define MCAN_GFC_RRFE (0x1u << 0) /**< \brief (MCAN_GFC) Reject Remote Frames Extended */ +#define MCAN_GFC_RRFE_FILTER (0x0u << 0) /**< \brief (MCAN_GFC) Filter remote frames with 29-bit extended IDs. */ +#define MCAN_GFC_RRFE_REJECT (0x1u << 0) /**< \brief (MCAN_GFC) Reject all remote frames with 29-bit extended IDs. */ +#define MCAN_GFC_RRFS (0x1u << 1) /**< \brief (MCAN_GFC) Reject Remote Frames Standard */ +#define MCAN_GFC_RRFS_FILTER (0x0u << 1) /**< \brief (MCAN_GFC) Filter remote frames with 11-bit standard IDs. */ +#define MCAN_GFC_RRFS_REJECT (0x1u << 1) /**< \brief (MCAN_GFC) Reject all remote frames with 11-bit standard IDs. */ +#define MCAN_GFC_ANFE_Pos 2 +#define MCAN_GFC_ANFE_Msk (0x3u << MCAN_GFC_ANFE_Pos) /**< \brief (MCAN_GFC) Accept Non-matching Frames Extended */ +#define MCAN_GFC_ANFE(value) ((MCAN_GFC_ANFE_Msk & ((value) << MCAN_GFC_ANFE_Pos))) +#define MCAN_GFC_ANFE_RX_FIFO_0 (0x0u << 2) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 0 */ +#define MCAN_GFC_ANFE_RX_FIFO_1 (0x1u << 2) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 1 */ +#define MCAN_GFC_ANFS_Pos 4 +#define MCAN_GFC_ANFS_Msk (0x3u << MCAN_GFC_ANFS_Pos) /**< \brief (MCAN_GFC) Accept Non-matching Frames Standard */ +#define MCAN_GFC_ANFS(value) ((MCAN_GFC_ANFS_Msk & ((value) << MCAN_GFC_ANFS_Pos))) +#define MCAN_GFC_ANFS_RX_FIFO_0 (0x0u << 4) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 0 */ +#define MCAN_GFC_ANFS_RX_FIFO_1 (0x1u << 4) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 1 */ +/* -------- MCAN_SIDFC : (MCAN Offset: 0x84) Standard ID Filter Configuration Register -------- */ +#define MCAN_SIDFC_FLSSA_Pos 2 +#define MCAN_SIDFC_FLSSA_Msk (0x3fffu << MCAN_SIDFC_FLSSA_Pos) /**< \brief (MCAN_SIDFC) Filter List Standard Start Address */ +#define MCAN_SIDFC_FLSSA(value) ((MCAN_SIDFC_FLSSA_Msk & ((value) << MCAN_SIDFC_FLSSA_Pos))) +#define MCAN_SIDFC_LSS_Pos 16 +#define MCAN_SIDFC_LSS_Msk (0xffu << MCAN_SIDFC_LSS_Pos) /**< \brief (MCAN_SIDFC) List Size Standard */ +#define MCAN_SIDFC_LSS(value) ((MCAN_SIDFC_LSS_Msk & ((value) << MCAN_SIDFC_LSS_Pos))) +/* -------- MCAN_XIDFC : (MCAN Offset: 0x88) Extended ID Filter Configuration Register -------- */ +#define MCAN_XIDFC_FLESA_Pos 2 +#define MCAN_XIDFC_FLESA_Msk (0x3fffu << MCAN_XIDFC_FLESA_Pos) /**< \brief (MCAN_XIDFC) Filter List Extended Start Address */ +#define MCAN_XIDFC_FLESA(value) ((MCAN_XIDFC_FLESA_Msk & ((value) << MCAN_XIDFC_FLESA_Pos))) +#define MCAN_XIDFC_LSE_Pos 16 +#define MCAN_XIDFC_LSE_Msk (0x7fu << MCAN_XIDFC_LSE_Pos) /**< \brief (MCAN_XIDFC) List Size Extended */ +#define MCAN_XIDFC_LSE(value) ((MCAN_XIDFC_LSE_Msk & ((value) << MCAN_XIDFC_LSE_Pos))) +/* -------- MCAN_XIDAM : (MCAN Offset: 0x90) Extended ID AND Mask Register -------- */ +#define MCAN_XIDAM_EIDM_Pos 0 +#define MCAN_XIDAM_EIDM_Msk (0x1fffffffu << MCAN_XIDAM_EIDM_Pos) /**< \brief (MCAN_XIDAM) Extended ID Mask */ +#define MCAN_XIDAM_EIDM(value) ((MCAN_XIDAM_EIDM_Msk & ((value) << MCAN_XIDAM_EIDM_Pos))) +/* -------- MCAN_HPMS : (MCAN Offset: 0x94) High Priority Message Status Register -------- */ +#define MCAN_HPMS_BIDX_Pos 0 +#define MCAN_HPMS_BIDX_Msk (0x3fu << MCAN_HPMS_BIDX_Pos) /**< \brief (MCAN_HPMS) Buffer Index */ +#define MCAN_HPMS_MSI_Pos 6 +#define MCAN_HPMS_MSI_Msk (0x3u << MCAN_HPMS_MSI_Pos) /**< \brief (MCAN_HPMS) Message Storage Indicator */ +#define MCAN_HPMS_MSI_NO_FIFO_SEL (0x0u << 6) /**< \brief (MCAN_HPMS) No FIFO selected. */ +#define MCAN_HPMS_MSI_LOST (0x1u << 6) /**< \brief (MCAN_HPMS) FIFO message lost. */ +#define MCAN_HPMS_MSI_FIFO_0 (0x2u << 6) /**< \brief (MCAN_HPMS) Message stored in FIFO 0. */ +#define MCAN_HPMS_MSI_FIFO_1 (0x3u << 6) /**< \brief (MCAN_HPMS) Message stored in FIFO 1. */ +#define MCAN_HPMS_FIDX_Pos 8 +#define MCAN_HPMS_FIDX_Msk (0x7fu << MCAN_HPMS_FIDX_Pos) /**< \brief (MCAN_HPMS) Filter Index */ +#define MCAN_HPMS_FLST (0x1u << 15) /**< \brief (MCAN_HPMS) Filter List */ +/* -------- MCAN_NDAT1 : (MCAN Offset: 0x98) New Data 1 Register -------- */ +#define MCAN_NDAT1_ND0 (0x1u << 0) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND1 (0x1u << 1) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND2 (0x1u << 2) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND3 (0x1u << 3) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND4 (0x1u << 4) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND5 (0x1u << 5) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND6 (0x1u << 6) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND7 (0x1u << 7) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND8 (0x1u << 8) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND9 (0x1u << 9) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND10 (0x1u << 10) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND11 (0x1u << 11) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND12 (0x1u << 12) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND13 (0x1u << 13) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND14 (0x1u << 14) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND15 (0x1u << 15) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND16 (0x1u << 16) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND17 (0x1u << 17) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND18 (0x1u << 18) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND19 (0x1u << 19) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND20 (0x1u << 20) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND21 (0x1u << 21) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND22 (0x1u << 22) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND23 (0x1u << 23) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND24 (0x1u << 24) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND25 (0x1u << 25) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND26 (0x1u << 26) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND27 (0x1u << 27) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND28 (0x1u << 28) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND29 (0x1u << 29) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND30 (0x1u << 30) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND31 (0x1u << 31) /**< \brief (MCAN_NDAT1) New Data */ +/* -------- MCAN_NDAT2 : (MCAN Offset: 0x9C) New Data 2 Register -------- */ +#define MCAN_NDAT2_ND32 (0x1u << 0) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND33 (0x1u << 1) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND34 (0x1u << 2) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND35 (0x1u << 3) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND36 (0x1u << 4) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND37 (0x1u << 5) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND38 (0x1u << 6) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND39 (0x1u << 7) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND40 (0x1u << 8) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND41 (0x1u << 9) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND42 (0x1u << 10) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND43 (0x1u << 11) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND44 (0x1u << 12) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND45 (0x1u << 13) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND46 (0x1u << 14) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND47 (0x1u << 15) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND48 (0x1u << 16) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND49 (0x1u << 17) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND50 (0x1u << 18) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND51 (0x1u << 19) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND52 (0x1u << 20) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND53 (0x1u << 21) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND54 (0x1u << 22) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND55 (0x1u << 23) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND56 (0x1u << 24) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND57 (0x1u << 25) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND58 (0x1u << 26) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND59 (0x1u << 27) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND60 (0x1u << 28) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND61 (0x1u << 29) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND62 (0x1u << 30) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND63 (0x1u << 31) /**< \brief (MCAN_NDAT2) New Data */ +/* -------- MCAN_RXF0C : (MCAN Offset: 0xA0) Receive FIFO 0 Configuration Register -------- */ +#define MCAN_RXF0C_F0SA_Pos 2 +#define MCAN_RXF0C_F0SA_Msk (0x3fffu << MCAN_RXF0C_F0SA_Pos) /**< \brief (MCAN_RXF0C) Receive FIFO 0 Start Address */ +#define MCAN_RXF0C_F0SA(value) ((MCAN_RXF0C_F0SA_Msk & ((value) << MCAN_RXF0C_F0SA_Pos))) +#define MCAN_RXF0C_F0S_Pos 16 +#define MCAN_RXF0C_F0S_Msk (0x7fu << MCAN_RXF0C_F0S_Pos) /**< \brief (MCAN_RXF0C) Receive FIFO 0 Start Address */ +#define MCAN_RXF0C_F0S(value) ((MCAN_RXF0C_F0S_Msk & ((value) << MCAN_RXF0C_F0S_Pos))) +#define MCAN_RXF0C_F0WM_Pos 24 +#define MCAN_RXF0C_F0WM_Msk (0x7fu << MCAN_RXF0C_F0WM_Pos) /**< \brief (MCAN_RXF0C) Receive FIFO 0 Watermark */ +#define MCAN_RXF0C_F0WM(value) ((MCAN_RXF0C_F0WM_Msk & ((value) << MCAN_RXF0C_F0WM_Pos))) +#define MCAN_RXF0C_F0OM (0x1u << 31) /**< \brief (MCAN_RXF0C) FIFO 0 Operation Mode */ +/* -------- MCAN_RXF0S : (MCAN Offset: 0xA4) Receive FIFO 0 Status Register -------- */ +#define MCAN_RXF0S_F0FL_Pos 0 +#define MCAN_RXF0S_F0FL_Msk (0x7fu << MCAN_RXF0S_F0FL_Pos) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Fill Level */ +#define MCAN_RXF0S_F0GI_Pos 8 +#define MCAN_RXF0S_F0GI_Msk (0x3fu << MCAN_RXF0S_F0GI_Pos) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Get Index */ +#define MCAN_RXF0S_F0PI_Pos 16 +#define MCAN_RXF0S_F0PI_Msk (0x3fu << MCAN_RXF0S_F0PI_Pos) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Put Index */ +#define MCAN_RXF0S_F0F (0x1u << 24) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Fill Level */ +#define MCAN_RXF0S_RF0L (0x1u << 25) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Message Lost */ +/* -------- MCAN_RXF0A : (MCAN Offset: 0xA8) Receive FIFO 0 Acknowledge Register -------- */ +#define MCAN_RXF0A_F0AI_Pos 0 +#define MCAN_RXF0A_F0AI_Msk (0x3fu << MCAN_RXF0A_F0AI_Pos) /**< \brief (MCAN_RXF0A) Receive FIFO 0 Acknowledge Index */ +#define MCAN_RXF0A_F0AI(value) ((MCAN_RXF0A_F0AI_Msk & ((value) << MCAN_RXF0A_F0AI_Pos))) +/* -------- MCAN_RXBC : (MCAN Offset: 0xAC) Receive Rx Buffer Configuration Register -------- */ +#define MCAN_RXBC_RBSA_Pos 2 +#define MCAN_RXBC_RBSA_Msk (0x3fffu << MCAN_RXBC_RBSA_Pos) /**< \brief (MCAN_RXBC) Receive Buffer Start Address */ +#define MCAN_RXBC_RBSA(value) ((MCAN_RXBC_RBSA_Msk & ((value) << MCAN_RXBC_RBSA_Pos))) +/* -------- MCAN_RXF1C : (MCAN Offset: 0xB0) Receive FIFO 1 Configuration Register -------- */ +#define MCAN_RXF1C_F1SA_Pos 2 +#define MCAN_RXF1C_F1SA_Msk (0x3fffu << MCAN_RXF1C_F1SA_Pos) /**< \brief (MCAN_RXF1C) Receive FIFO 1 Start Address */ +#define MCAN_RXF1C_F1SA(value) ((MCAN_RXF1C_F1SA_Msk & ((value) << MCAN_RXF1C_F1SA_Pos))) +#define MCAN_RXF1C_F1S_Pos 16 +#define MCAN_RXF1C_F1S_Msk (0x7fu << MCAN_RXF1C_F1S_Pos) /**< \brief (MCAN_RXF1C) Receive FIFO 1 Start Address */ +#define MCAN_RXF1C_F1S(value) ((MCAN_RXF1C_F1S_Msk & ((value) << MCAN_RXF1C_F1S_Pos))) +#define MCAN_RXF1C_F1WM_Pos 24 +#define MCAN_RXF1C_F1WM_Msk (0x7fu << MCAN_RXF1C_F1WM_Pos) /**< \brief (MCAN_RXF1C) Receive FIFO 1 Watermark */ +#define MCAN_RXF1C_F1WM(value) ((MCAN_RXF1C_F1WM_Msk & ((value) << MCAN_RXF1C_F1WM_Pos))) +#define MCAN_RXF1C_F1OM (0x1u << 31) /**< \brief (MCAN_RXF1C) FIFO 1 Operation Mode */ +/* -------- MCAN_RXF1S : (MCAN Offset: 0xB4) Receive FIFO 1 Status Register -------- */ +#define MCAN_RXF1S_F1FL_Pos 0 +#define MCAN_RXF1S_F1FL_Msk (0x7fu << MCAN_RXF1S_F1FL_Pos) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Fill Level */ +#define MCAN_RXF1S_F1GI_Pos 8 +#define MCAN_RXF1S_F1GI_Msk (0x3fu << MCAN_RXF1S_F1GI_Pos) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Get Index */ +#define MCAN_RXF1S_F1PI_Pos 16 +#define MCAN_RXF1S_F1PI_Msk (0x3fu << MCAN_RXF1S_F1PI_Pos) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Put Index */ +#define MCAN_RXF1S_F1F (0x1u << 24) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Fill Level */ +#define MCAN_RXF1S_RF1L (0x1u << 25) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Message Lost */ +#define MCAN_RXF1S_DMS_Pos 30 +#define MCAN_RXF1S_DMS_Msk (0x3u << MCAN_RXF1S_DMS_Pos) /**< \brief (MCAN_RXF1S) Debug Message Status */ +#define MCAN_RXF1S_DMS_IDLE (0x0u << 30) /**< \brief (MCAN_RXF1S) Idle state, wait for reception of debug messages, DMA request is cleared. */ +#define MCAN_RXF1S_DMS_MSG_A (0x1u << 30) /**< \brief (MCAN_RXF1S) Debug message A received. */ +#define MCAN_RXF1S_DMS_MSG_AB (0x2u << 30) /**< \brief (MCAN_RXF1S) Debug messages A, B received. */ +#define MCAN_RXF1S_DMS_MSG_ABC (0x3u << 30) /**< \brief (MCAN_RXF1S) Debug messages A, B, C received, DMA request is set. */ +/* -------- MCAN_RXF1A : (MCAN Offset: 0xB8) Receive FIFO 1 Acknowledge Register -------- */ +#define MCAN_RXF1A_F1AI_Pos 0 +#define MCAN_RXF1A_F1AI_Msk (0x3fu << MCAN_RXF1A_F1AI_Pos) /**< \brief (MCAN_RXF1A) Receive FIFO 1 Acknowledge Index */ +#define MCAN_RXF1A_F1AI(value) ((MCAN_RXF1A_F1AI_Msk & ((value) << MCAN_RXF1A_F1AI_Pos))) +/* -------- MCAN_RXESC : (MCAN Offset: 0xBC) Receive Buffer / FIFO Element Size Configuration Register -------- */ +#define MCAN_RXESC_F0DS_Pos 0 +#define MCAN_RXESC_F0DS_Msk (0x7u << MCAN_RXESC_F0DS_Pos) /**< \brief (MCAN_RXESC) Receive FIFO 0 Data Field Size */ +#define MCAN_RXESC_F0DS(value) ((MCAN_RXESC_F0DS_Msk & ((value) << MCAN_RXESC_F0DS_Pos))) +#define MCAN_RXESC_F0DS_8_BYTE (0x0u << 0) /**< \brief (MCAN_RXESC) 8-byte data field */ +#define MCAN_RXESC_F0DS_12_BYTE (0x1u << 0) /**< \brief (MCAN_RXESC) 12-byte data field */ +#define MCAN_RXESC_F0DS_16_BYTE (0x2u << 0) /**< \brief (MCAN_RXESC) 16-byte data field */ +#define MCAN_RXESC_F0DS_20_BYTE (0x3u << 0) /**< \brief (MCAN_RXESC) 20-byte data field */ +#define MCAN_RXESC_F0DS_24_BYTE (0x4u << 0) /**< \brief (MCAN_RXESC) 24-byte data field */ +#define MCAN_RXESC_F0DS_32_BYTE (0x5u << 0) /**< \brief (MCAN_RXESC) 32-byte data field */ +#define MCAN_RXESC_F0DS_48_BYTE (0x6u << 0) /**< \brief (MCAN_RXESC) 48-byte data field */ +#define MCAN_RXESC_F0DS_64_BYTE (0x7u << 0) /**< \brief (MCAN_RXESC) 64-byte data field */ +#define MCAN_RXESC_F1DS_Pos 4 +#define MCAN_RXESC_F1DS_Msk (0x7u << MCAN_RXESC_F1DS_Pos) /**< \brief (MCAN_RXESC) Receive FIFO 1 Data Field Size */ +#define MCAN_RXESC_F1DS(value) ((MCAN_RXESC_F1DS_Msk & ((value) << MCAN_RXESC_F1DS_Pos))) +#define MCAN_RXESC_F1DS_8_BYTE (0x0u << 4) /**< \brief (MCAN_RXESC) 8-byte data field */ +#define MCAN_RXESC_F1DS_12_BYTE (0x1u << 4) /**< \brief (MCAN_RXESC) 12-byte data field */ +#define MCAN_RXESC_F1DS_16_BYTE (0x2u << 4) /**< \brief (MCAN_RXESC) 16-byte data field */ +#define MCAN_RXESC_F1DS_20_BYTE (0x3u << 4) /**< \brief (MCAN_RXESC) 20-byte data field */ +#define MCAN_RXESC_F1DS_24_BYTE (0x4u << 4) /**< \brief (MCAN_RXESC) 24-byte data field */ +#define MCAN_RXESC_F1DS_32_BYTE (0x5u << 4) /**< \brief (MCAN_RXESC) 32-byte data field */ +#define MCAN_RXESC_F1DS_48_BYTE (0x6u << 4) /**< \brief (MCAN_RXESC) 48-byte data field */ +#define MCAN_RXESC_F1DS_64_BYTE (0x7u << 4) /**< \brief (MCAN_RXESC) 64-byte data field */ +#define MCAN_RXESC_RBDS_Pos 8 +#define MCAN_RXESC_RBDS_Msk (0x7u << MCAN_RXESC_RBDS_Pos) /**< \brief (MCAN_RXESC) Receive Buffer Data Field Size */ +#define MCAN_RXESC_RBDS(value) ((MCAN_RXESC_RBDS_Msk & ((value) << MCAN_RXESC_RBDS_Pos))) +#define MCAN_RXESC_RBDS_8_BYTE (0x0u << 8) /**< \brief (MCAN_RXESC) 8-byte data field */ +#define MCAN_RXESC_RBDS_12_BYTE (0x1u << 8) /**< \brief (MCAN_RXESC) 12-byte data field */ +#define MCAN_RXESC_RBDS_16_BYTE (0x2u << 8) /**< \brief (MCAN_RXESC) 16-byte data field */ +#define MCAN_RXESC_RBDS_20_BYTE (0x3u << 8) /**< \brief (MCAN_RXESC) 20-byte data field */ +#define MCAN_RXESC_RBDS_24_BYTE (0x4u << 8) /**< \brief (MCAN_RXESC) 24-byte data field */ +#define MCAN_RXESC_RBDS_32_BYTE (0x5u << 8) /**< \brief (MCAN_RXESC) 32-byte data field */ +#define MCAN_RXESC_RBDS_48_BYTE (0x6u << 8) /**< \brief (MCAN_RXESC) 48-byte data field */ +#define MCAN_RXESC_RBDS_64_BYTE (0x7u << 8) /**< \brief (MCAN_RXESC) 64-byte data field */ +/* -------- MCAN_TXBC : (MCAN Offset: 0xC0) Transmit Buffer Configuration Register -------- */ +#define MCAN_TXBC_TBSA_Pos 2 +#define MCAN_TXBC_TBSA_Msk (0x3fffu << MCAN_TXBC_TBSA_Pos) /**< \brief (MCAN_TXBC) Tx Buffers Start Address */ +#define MCAN_TXBC_TBSA(value) ((MCAN_TXBC_TBSA_Msk & ((value) << MCAN_TXBC_TBSA_Pos))) +#define MCAN_TXBC_NDTB_Pos 16 +#define MCAN_TXBC_NDTB_Msk (0x3fu << MCAN_TXBC_NDTB_Pos) /**< \brief (MCAN_TXBC) Number of Dedicated Transmit Buffers */ +#define MCAN_TXBC_NDTB(value) ((MCAN_TXBC_NDTB_Msk & ((value) << MCAN_TXBC_NDTB_Pos))) +#define MCAN_TXBC_TFQS_Pos 24 +#define MCAN_TXBC_TFQS_Msk (0x3fu << MCAN_TXBC_TFQS_Pos) /**< \brief (MCAN_TXBC) Transmit FIFO/Queue Size */ +#define MCAN_TXBC_TFQS(value) ((MCAN_TXBC_TFQS_Msk & ((value) << MCAN_TXBC_TFQS_Pos))) +#define MCAN_TXBC_TFQM (0x1u << 30) /**< \brief (MCAN_TXBC) Tx FIFO/Queue Mode */ +/* -------- MCAN_TXFQS : (MCAN Offset: 0xC4) Transmit FIFO/Queue Status Register -------- */ +#define MCAN_TXFQS_TFFL_Pos 0 +#define MCAN_TXFQS_TFFL_Msk (0x3fu << MCAN_TXFQS_TFFL_Pos) /**< \brief (MCAN_TXFQS) Tx FIFO Free Level */ +#define MCAN_TXFQS_TFGI_Pos 8 +#define MCAN_TXFQS_TFGI_Msk (0x1fu << MCAN_TXFQS_TFGI_Pos) /**< \brief (MCAN_TXFQS) Tx FIFO Get Index */ +#define MCAN_TXFQS_TFQPI_Pos 16 +#define MCAN_TXFQS_TFQPI_Msk (0x1fu << MCAN_TXFQS_TFQPI_Pos) /**< \brief (MCAN_TXFQS) Tx FIFO/Queue Put Index */ +#define MCAN_TXFQS_TFQF (0x1u << 21) /**< \brief (MCAN_TXFQS) Tx FIFO/Queue Full */ +/* -------- MCAN_TXESC : (MCAN Offset: 0xC8) Transmit Buffer Element Size Configuration Register -------- */ +#define MCAN_TXESC_TBDS_Pos 0 +#define MCAN_TXESC_TBDS_Msk (0x7u << MCAN_TXESC_TBDS_Pos) /**< \brief (MCAN_TXESC) Tx Buffer Data Field Size */ +#define MCAN_TXESC_TBDS(value) ((MCAN_TXESC_TBDS_Msk & ((value) << MCAN_TXESC_TBDS_Pos))) +#define MCAN_TXESC_TBDS_8_BYTE (0x0u << 0) /**< \brief (MCAN_TXESC) 8-byte data field */ +#define MCAN_TXESC_TBDS_12_BYTE (0x1u << 0) /**< \brief (MCAN_TXESC) 12-byte data field */ +#define MCAN_TXESC_TBDS_16_BYTE (0x2u << 0) /**< \brief (MCAN_TXESC) 16-byte data field */ +#define MCAN_TXESC_TBDS_20_BYTE (0x3u << 0) /**< \brief (MCAN_TXESC) 20-byte data field */ +#define MCAN_TXESC_TBDS_24_BYTE (0x4u << 0) /**< \brief (MCAN_TXESC) 24-byte data field */ +#define MCAN_TXESC_TBDS_32_BYTE (0x5u << 0) /**< \brief (MCAN_TXESC) 32-byte data field */ +#define MCAN_TXESC_TBDS_48_BYTE (0x6u << 0) /**< \brief (MCAN_TXESC) 48- byte data field */ +#define MCAN_TXESC_TBDS_64_BYTE (0x7u << 0) /**< \brief (MCAN_TXESC) 64-byte data field */ +/* -------- MCAN_TXBRP : (MCAN Offset: 0xCC) Transmit Buffer Request Pending Register -------- */ +#define MCAN_TXBRP_TRP0 (0x1u << 0) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 0 */ +#define MCAN_TXBRP_TRP1 (0x1u << 1) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 1 */ +#define MCAN_TXBRP_TRP2 (0x1u << 2) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 2 */ +#define MCAN_TXBRP_TRP3 (0x1u << 3) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 3 */ +#define MCAN_TXBRP_TRP4 (0x1u << 4) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 4 */ +#define MCAN_TXBRP_TRP5 (0x1u << 5) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 5 */ +#define MCAN_TXBRP_TRP6 (0x1u << 6) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 6 */ +#define MCAN_TXBRP_TRP7 (0x1u << 7) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 7 */ +#define MCAN_TXBRP_TRP8 (0x1u << 8) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 8 */ +#define MCAN_TXBRP_TRP9 (0x1u << 9) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 9 */ +#define MCAN_TXBRP_TRP10 (0x1u << 10) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 10 */ +#define MCAN_TXBRP_TRP11 (0x1u << 11) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 11 */ +#define MCAN_TXBRP_TRP12 (0x1u << 12) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 12 */ +#define MCAN_TXBRP_TRP13 (0x1u << 13) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 13 */ +#define MCAN_TXBRP_TRP14 (0x1u << 14) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 14 */ +#define MCAN_TXBRP_TRP15 (0x1u << 15) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 15 */ +#define MCAN_TXBRP_TRP16 (0x1u << 16) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 16 */ +#define MCAN_TXBRP_TRP17 (0x1u << 17) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 17 */ +#define MCAN_TXBRP_TRP18 (0x1u << 18) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 18 */ +#define MCAN_TXBRP_TRP19 (0x1u << 19) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 19 */ +#define MCAN_TXBRP_TRP20 (0x1u << 20) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 20 */ +#define MCAN_TXBRP_TRP21 (0x1u << 21) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 21 */ +#define MCAN_TXBRP_TRP22 (0x1u << 22) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 22 */ +#define MCAN_TXBRP_TRP23 (0x1u << 23) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 23 */ +#define MCAN_TXBRP_TRP24 (0x1u << 24) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 24 */ +#define MCAN_TXBRP_TRP25 (0x1u << 25) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 25 */ +#define MCAN_TXBRP_TRP26 (0x1u << 26) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 26 */ +#define MCAN_TXBRP_TRP27 (0x1u << 27) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 27 */ +#define MCAN_TXBRP_TRP28 (0x1u << 28) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 28 */ +#define MCAN_TXBRP_TRP29 (0x1u << 29) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 29 */ +#define MCAN_TXBRP_TRP30 (0x1u << 30) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 30 */ +#define MCAN_TXBRP_TRP31 (0x1u << 31) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 31 */ +/* -------- MCAN_TXBAR : (MCAN Offset: 0xD0) Transmit Buffer Add Request Register -------- */ +#define MCAN_TXBAR_AR0 (0x1u << 0) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 0 */ +#define MCAN_TXBAR_AR1 (0x1u << 1) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 1 */ +#define MCAN_TXBAR_AR2 (0x1u << 2) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 2 */ +#define MCAN_TXBAR_AR3 (0x1u << 3) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 3 */ +#define MCAN_TXBAR_AR4 (0x1u << 4) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 4 */ +#define MCAN_TXBAR_AR5 (0x1u << 5) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 5 */ +#define MCAN_TXBAR_AR6 (0x1u << 6) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 6 */ +#define MCAN_TXBAR_AR7 (0x1u << 7) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 7 */ +#define MCAN_TXBAR_AR8 (0x1u << 8) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 8 */ +#define MCAN_TXBAR_AR9 (0x1u << 9) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 9 */ +#define MCAN_TXBAR_AR10 (0x1u << 10) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 10 */ +#define MCAN_TXBAR_AR11 (0x1u << 11) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 11 */ +#define MCAN_TXBAR_AR12 (0x1u << 12) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 12 */ +#define MCAN_TXBAR_AR13 (0x1u << 13) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 13 */ +#define MCAN_TXBAR_AR14 (0x1u << 14) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 14 */ +#define MCAN_TXBAR_AR15 (0x1u << 15) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 15 */ +#define MCAN_TXBAR_AR16 (0x1u << 16) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 16 */ +#define MCAN_TXBAR_AR17 (0x1u << 17) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 17 */ +#define MCAN_TXBAR_AR18 (0x1u << 18) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 18 */ +#define MCAN_TXBAR_AR19 (0x1u << 19) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 19 */ +#define MCAN_TXBAR_AR20 (0x1u << 20) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 20 */ +#define MCAN_TXBAR_AR21 (0x1u << 21) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 21 */ +#define MCAN_TXBAR_AR22 (0x1u << 22) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 22 */ +#define MCAN_TXBAR_AR23 (0x1u << 23) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 23 */ +#define MCAN_TXBAR_AR24 (0x1u << 24) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 24 */ +#define MCAN_TXBAR_AR25 (0x1u << 25) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 25 */ +#define MCAN_TXBAR_AR26 (0x1u << 26) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 26 */ +#define MCAN_TXBAR_AR27 (0x1u << 27) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 27 */ +#define MCAN_TXBAR_AR28 (0x1u << 28) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 28 */ +#define MCAN_TXBAR_AR29 (0x1u << 29) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 29 */ +#define MCAN_TXBAR_AR30 (0x1u << 30) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 30 */ +#define MCAN_TXBAR_AR31 (0x1u << 31) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 31 */ +/* -------- MCAN_TXBCR : (MCAN Offset: 0xD4) Transmit Buffer Cancellation Request Register -------- */ +#define MCAN_TXBCR_CR0 (0x1u << 0) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 0 */ +#define MCAN_TXBCR_CR1 (0x1u << 1) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 1 */ +#define MCAN_TXBCR_CR2 (0x1u << 2) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 2 */ +#define MCAN_TXBCR_CR3 (0x1u << 3) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 3 */ +#define MCAN_TXBCR_CR4 (0x1u << 4) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 4 */ +#define MCAN_TXBCR_CR5 (0x1u << 5) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 5 */ +#define MCAN_TXBCR_CR6 (0x1u << 6) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 6 */ +#define MCAN_TXBCR_CR7 (0x1u << 7) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 7 */ +#define MCAN_TXBCR_CR8 (0x1u << 8) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 8 */ +#define MCAN_TXBCR_CR9 (0x1u << 9) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 9 */ +#define MCAN_TXBCR_CR10 (0x1u << 10) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 10 */ +#define MCAN_TXBCR_CR11 (0x1u << 11) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 11 */ +#define MCAN_TXBCR_CR12 (0x1u << 12) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 12 */ +#define MCAN_TXBCR_CR13 (0x1u << 13) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 13 */ +#define MCAN_TXBCR_CR14 (0x1u << 14) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 14 */ +#define MCAN_TXBCR_CR15 (0x1u << 15) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 15 */ +#define MCAN_TXBCR_CR16 (0x1u << 16) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 16 */ +#define MCAN_TXBCR_CR17 (0x1u << 17) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 17 */ +#define MCAN_TXBCR_CR18 (0x1u << 18) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 18 */ +#define MCAN_TXBCR_CR19 (0x1u << 19) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 19 */ +#define MCAN_TXBCR_CR20 (0x1u << 20) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 20 */ +#define MCAN_TXBCR_CR21 (0x1u << 21) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 21 */ +#define MCAN_TXBCR_CR22 (0x1u << 22) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 22 */ +#define MCAN_TXBCR_CR23 (0x1u << 23) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 23 */ +#define MCAN_TXBCR_CR24 (0x1u << 24) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 24 */ +#define MCAN_TXBCR_CR25 (0x1u << 25) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 25 */ +#define MCAN_TXBCR_CR26 (0x1u << 26) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 26 */ +#define MCAN_TXBCR_CR27 (0x1u << 27) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 27 */ +#define MCAN_TXBCR_CR28 (0x1u << 28) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 28 */ +#define MCAN_TXBCR_CR29 (0x1u << 29) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 29 */ +#define MCAN_TXBCR_CR30 (0x1u << 30) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 30 */ +#define MCAN_TXBCR_CR31 (0x1u << 31) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 31 */ +/* -------- MCAN_TXBTO : (MCAN Offset: 0xD8) Transmit Buffer Transmission Occurred Register -------- */ +#define MCAN_TXBTO_TO0 (0x1u << 0) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 0 */ +#define MCAN_TXBTO_TO1 (0x1u << 1) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 1 */ +#define MCAN_TXBTO_TO2 (0x1u << 2) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 2 */ +#define MCAN_TXBTO_TO3 (0x1u << 3) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 3 */ +#define MCAN_TXBTO_TO4 (0x1u << 4) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 4 */ +#define MCAN_TXBTO_TO5 (0x1u << 5) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 5 */ +#define MCAN_TXBTO_TO6 (0x1u << 6) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 6 */ +#define MCAN_TXBTO_TO7 (0x1u << 7) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 7 */ +#define MCAN_TXBTO_TO8 (0x1u << 8) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 8 */ +#define MCAN_TXBTO_TO9 (0x1u << 9) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 9 */ +#define MCAN_TXBTO_TO10 (0x1u << 10) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 10 */ +#define MCAN_TXBTO_TO11 (0x1u << 11) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 11 */ +#define MCAN_TXBTO_TO12 (0x1u << 12) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 12 */ +#define MCAN_TXBTO_TO13 (0x1u << 13) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 13 */ +#define MCAN_TXBTO_TO14 (0x1u << 14) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 14 */ +#define MCAN_TXBTO_TO15 (0x1u << 15) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 15 */ +#define MCAN_TXBTO_TO16 (0x1u << 16) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 16 */ +#define MCAN_TXBTO_TO17 (0x1u << 17) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 17 */ +#define MCAN_TXBTO_TO18 (0x1u << 18) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 18 */ +#define MCAN_TXBTO_TO19 (0x1u << 19) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 19 */ +#define MCAN_TXBTO_TO20 (0x1u << 20) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 20 */ +#define MCAN_TXBTO_TO21 (0x1u << 21) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 21 */ +#define MCAN_TXBTO_TO22 (0x1u << 22) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 22 */ +#define MCAN_TXBTO_TO23 (0x1u << 23) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 23 */ +#define MCAN_TXBTO_TO24 (0x1u << 24) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 24 */ +#define MCAN_TXBTO_TO25 (0x1u << 25) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 25 */ +#define MCAN_TXBTO_TO26 (0x1u << 26) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 26 */ +#define MCAN_TXBTO_TO27 (0x1u << 27) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 27 */ +#define MCAN_TXBTO_TO28 (0x1u << 28) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 28 */ +#define MCAN_TXBTO_TO29 (0x1u << 29) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 29 */ +#define MCAN_TXBTO_TO30 (0x1u << 30) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 30 */ +#define MCAN_TXBTO_TO31 (0x1u << 31) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 31 */ +/* -------- MCAN_TXBCF : (MCAN Offset: 0xDC) Transmit Buffer Cancellation Finished Register -------- */ +#define MCAN_TXBCF_CF0 (0x1u << 0) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 0 */ +#define MCAN_TXBCF_CF1 (0x1u << 1) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 1 */ +#define MCAN_TXBCF_CF2 (0x1u << 2) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 2 */ +#define MCAN_TXBCF_CF3 (0x1u << 3) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 3 */ +#define MCAN_TXBCF_CF4 (0x1u << 4) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 4 */ +#define MCAN_TXBCF_CF5 (0x1u << 5) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 5 */ +#define MCAN_TXBCF_CF6 (0x1u << 6) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 6 */ +#define MCAN_TXBCF_CF7 (0x1u << 7) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 7 */ +#define MCAN_TXBCF_CF8 (0x1u << 8) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 8 */ +#define MCAN_TXBCF_CF9 (0x1u << 9) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 9 */ +#define MCAN_TXBCF_CF10 (0x1u << 10) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 10 */ +#define MCAN_TXBCF_CF11 (0x1u << 11) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 11 */ +#define MCAN_TXBCF_CF12 (0x1u << 12) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 12 */ +#define MCAN_TXBCF_CF13 (0x1u << 13) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 13 */ +#define MCAN_TXBCF_CF14 (0x1u << 14) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 14 */ +#define MCAN_TXBCF_CF15 (0x1u << 15) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 15 */ +#define MCAN_TXBCF_CF16 (0x1u << 16) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 16 */ +#define MCAN_TXBCF_CF17 (0x1u << 17) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 17 */ +#define MCAN_TXBCF_CF18 (0x1u << 18) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 18 */ +#define MCAN_TXBCF_CF19 (0x1u << 19) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 19 */ +#define MCAN_TXBCF_CF20 (0x1u << 20) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 20 */ +#define MCAN_TXBCF_CF21 (0x1u << 21) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 21 */ +#define MCAN_TXBCF_CF22 (0x1u << 22) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 22 */ +#define MCAN_TXBCF_CF23 (0x1u << 23) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 23 */ +#define MCAN_TXBCF_CF24 (0x1u << 24) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 24 */ +#define MCAN_TXBCF_CF25 (0x1u << 25) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 25 */ +#define MCAN_TXBCF_CF26 (0x1u << 26) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 26 */ +#define MCAN_TXBCF_CF27 (0x1u << 27) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 27 */ +#define MCAN_TXBCF_CF28 (0x1u << 28) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 28 */ +#define MCAN_TXBCF_CF29 (0x1u << 29) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 29 */ +#define MCAN_TXBCF_CF30 (0x1u << 30) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 30 */ +#define MCAN_TXBCF_CF31 (0x1u << 31) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 31 */ +/* -------- MCAN_TXBTIE : (MCAN Offset: 0xE0) Transmit Buffer Transmission Interrupt Enable Register -------- */ +#define MCAN_TXBTIE_TIE0 (0x1u << 0) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 0 */ +#define MCAN_TXBTIE_TIE1 (0x1u << 1) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 1 */ +#define MCAN_TXBTIE_TIE2 (0x1u << 2) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 2 */ +#define MCAN_TXBTIE_TIE3 (0x1u << 3) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 3 */ +#define MCAN_TXBTIE_TIE4 (0x1u << 4) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 4 */ +#define MCAN_TXBTIE_TIE5 (0x1u << 5) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 5 */ +#define MCAN_TXBTIE_TIE6 (0x1u << 6) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 6 */ +#define MCAN_TXBTIE_TIE7 (0x1u << 7) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 7 */ +#define MCAN_TXBTIE_TIE8 (0x1u << 8) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 8 */ +#define MCAN_TXBTIE_TIE9 (0x1u << 9) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 9 */ +#define MCAN_TXBTIE_TIE10 (0x1u << 10) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 10 */ +#define MCAN_TXBTIE_TIE11 (0x1u << 11) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 11 */ +#define MCAN_TXBTIE_TIE12 (0x1u << 12) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 12 */ +#define MCAN_TXBTIE_TIE13 (0x1u << 13) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 13 */ +#define MCAN_TXBTIE_TIE14 (0x1u << 14) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 14 */ +#define MCAN_TXBTIE_TIE15 (0x1u << 15) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 15 */ +#define MCAN_TXBTIE_TIE16 (0x1u << 16) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 16 */ +#define MCAN_TXBTIE_TIE17 (0x1u << 17) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 17 */ +#define MCAN_TXBTIE_TIE18 (0x1u << 18) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 18 */ +#define MCAN_TXBTIE_TIE19 (0x1u << 19) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 19 */ +#define MCAN_TXBTIE_TIE20 (0x1u << 20) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 20 */ +#define MCAN_TXBTIE_TIE21 (0x1u << 21) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 21 */ +#define MCAN_TXBTIE_TIE22 (0x1u << 22) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 22 */ +#define MCAN_TXBTIE_TIE23 (0x1u << 23) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 23 */ +#define MCAN_TXBTIE_TIE24 (0x1u << 24) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 24 */ +#define MCAN_TXBTIE_TIE25 (0x1u << 25) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 25 */ +#define MCAN_TXBTIE_TIE26 (0x1u << 26) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 26 */ +#define MCAN_TXBTIE_TIE27 (0x1u << 27) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 27 */ +#define MCAN_TXBTIE_TIE28 (0x1u << 28) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 28 */ +#define MCAN_TXBTIE_TIE29 (0x1u << 29) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 29 */ +#define MCAN_TXBTIE_TIE30 (0x1u << 30) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 30 */ +#define MCAN_TXBTIE_TIE31 (0x1u << 31) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 31 */ +/* -------- MCAN_TXBCIE : (MCAN Offset: 0xE4) Transmit Buffer Cancellation Finished Interrupt Enable Register -------- */ +#define MCAN_TXBCIE_CFIE0 (0x1u << 0) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 0 */ +#define MCAN_TXBCIE_CFIE1 (0x1u << 1) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 1 */ +#define MCAN_TXBCIE_CFIE2 (0x1u << 2) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 2 */ +#define MCAN_TXBCIE_CFIE3 (0x1u << 3) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 3 */ +#define MCAN_TXBCIE_CFIE4 (0x1u << 4) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 4 */ +#define MCAN_TXBCIE_CFIE5 (0x1u << 5) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 5 */ +#define MCAN_TXBCIE_CFIE6 (0x1u << 6) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 6 */ +#define MCAN_TXBCIE_CFIE7 (0x1u << 7) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 7 */ +#define MCAN_TXBCIE_CFIE8 (0x1u << 8) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 8 */ +#define MCAN_TXBCIE_CFIE9 (0x1u << 9) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 9 */ +#define MCAN_TXBCIE_CFIE10 (0x1u << 10) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 10 */ +#define MCAN_TXBCIE_CFIE11 (0x1u << 11) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 11 */ +#define MCAN_TXBCIE_CFIE12 (0x1u << 12) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 12 */ +#define MCAN_TXBCIE_CFIE13 (0x1u << 13) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 13 */ +#define MCAN_TXBCIE_CFIE14 (0x1u << 14) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 14 */ +#define MCAN_TXBCIE_CFIE15 (0x1u << 15) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 15 */ +#define MCAN_TXBCIE_CFIE16 (0x1u << 16) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 16 */ +#define MCAN_TXBCIE_CFIE17 (0x1u << 17) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 17 */ +#define MCAN_TXBCIE_CFIE18 (0x1u << 18) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 18 */ +#define MCAN_TXBCIE_CFIE19 (0x1u << 19) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 19 */ +#define MCAN_TXBCIE_CFIE20 (0x1u << 20) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 20 */ +#define MCAN_TXBCIE_CFIE21 (0x1u << 21) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 21 */ +#define MCAN_TXBCIE_CFIE22 (0x1u << 22) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 22 */ +#define MCAN_TXBCIE_CFIE23 (0x1u << 23) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 23 */ +#define MCAN_TXBCIE_CFIE24 (0x1u << 24) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 24 */ +#define MCAN_TXBCIE_CFIE25 (0x1u << 25) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 25 */ +#define MCAN_TXBCIE_CFIE26 (0x1u << 26) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 26 */ +#define MCAN_TXBCIE_CFIE27 (0x1u << 27) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 27 */ +#define MCAN_TXBCIE_CFIE28 (0x1u << 28) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 28 */ +#define MCAN_TXBCIE_CFIE29 (0x1u << 29) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 29 */ +#define MCAN_TXBCIE_CFIE30 (0x1u << 30) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 30 */ +#define MCAN_TXBCIE_CFIE31 (0x1u << 31) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 31 */ +/* -------- MCAN_TXEFC : (MCAN Offset: 0xF0) Transmit Event FIFO Configuration Register -------- */ +#define MCAN_TXEFC_EFSA_Pos 2 +#define MCAN_TXEFC_EFSA_Msk (0x3fffu << MCAN_TXEFC_EFSA_Pos) /**< \brief (MCAN_TXEFC) Event FIFO Start Address */ +#define MCAN_TXEFC_EFSA(value) ((MCAN_TXEFC_EFSA_Msk & ((value) << MCAN_TXEFC_EFSA_Pos))) +#define MCAN_TXEFC_EFS_Pos 16 +#define MCAN_TXEFC_EFS_Msk (0x3fu << MCAN_TXEFC_EFS_Pos) /**< \brief (MCAN_TXEFC) Event FIFO Size */ +#define MCAN_TXEFC_EFS(value) ((MCAN_TXEFC_EFS_Msk & ((value) << MCAN_TXEFC_EFS_Pos))) +#define MCAN_TXEFC_EFWM_Pos 24 +#define MCAN_TXEFC_EFWM_Msk (0x3fu << MCAN_TXEFC_EFWM_Pos) /**< \brief (MCAN_TXEFC) Event FIFO Watermark */ +#define MCAN_TXEFC_EFWM(value) ((MCAN_TXEFC_EFWM_Msk & ((value) << MCAN_TXEFC_EFWM_Pos))) +/* -------- MCAN_TXEFS : (MCAN Offset: 0xF4) Transmit Event FIFO Status Register -------- */ +#define MCAN_TXEFS_EFFL_Pos 0 +#define MCAN_TXEFS_EFFL_Msk (0x3fu << MCAN_TXEFS_EFFL_Pos) /**< \brief (MCAN_TXEFS) Event FIFO Fill Level */ +#define MCAN_TXEFS_EFGI_Pos 8 +#define MCAN_TXEFS_EFGI_Msk (0x1fu << MCAN_TXEFS_EFGI_Pos) /**< \brief (MCAN_TXEFS) Event FIFO Get Index */ +#define MCAN_TXEFS_EFPI_Pos 16 +#define MCAN_TXEFS_EFPI_Msk (0x1fu << MCAN_TXEFS_EFPI_Pos) /**< \brief (MCAN_TXEFS) Event FIFO Put Index */ +#define MCAN_TXEFS_EFF (0x1u << 24) /**< \brief (MCAN_TXEFS) Event FIFO Full */ +#define MCAN_TXEFS_TEFL (0x1u << 25) /**< \brief (MCAN_TXEFS) Tx Event FIFO Element Lost */ +/* -------- MCAN_TXEFA : (MCAN Offset: 0xF8) Transmit Event FIFO Acknowledge Register -------- */ +#define MCAN_TXEFA_EFAI_Pos 0 +#define MCAN_TXEFA_EFAI_Msk (0x1fu << MCAN_TXEFA_EFAI_Pos) /**< \brief (MCAN_TXEFA) Event FIFO Acknowledge Index */ +#define MCAN_TXEFA_EFAI(value) ((MCAN_TXEFA_EFAI_Msk & ((value) << MCAN_TXEFA_EFAI_Pos))) + +/*@}*/ + + +#endif /* _SAME70_MCAN_COMPONENT_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/pio.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/pio.h new file mode 100644 index 000000000..ac8663a66 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/pio.h @@ -0,0 +1,1722 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_PIO_COMPONENT_ +#define _SAME70_PIO_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_PIO Parallel Input/Output Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Pio hardware registers */ +typedef struct { + __O uint32_t PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */ + __O uint32_t PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */ + __I uint32_t PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */ + __I uint32_t Reserved1[1]; + __O uint32_t PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */ + __O uint32_t PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */ + __I uint32_t PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */ + __I uint32_t Reserved2[1]; + __O uint32_t PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */ + __O uint32_t PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */ + __I uint32_t PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */ + __I uint32_t Reserved3[1]; + __O uint32_t PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */ + __O uint32_t PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */ + __IO uint32_t PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */ + __I uint32_t PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */ + __O uint32_t PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */ + __O uint32_t PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */ + __I uint32_t PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */ + __I uint32_t PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */ + __O uint32_t PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */ + __O uint32_t PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */ + __I uint32_t PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */ + __I uint32_t Reserved4[1]; + __O uint32_t PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */ + __O uint32_t PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */ + __I uint32_t PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */ + __I uint32_t Reserved5[1]; + __IO uint32_t PIO_ABCDSR[2]; /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */ + __I uint32_t Reserved6[2]; + __O uint32_t PIO_IFSCDR; /**< \brief (Pio Offset: 0x0080) Input Filter Slow Clock Disable Register */ + __O uint32_t PIO_IFSCER; /**< \brief (Pio Offset: 0x0084) Input Filter Slow Clock Enable Register */ + __I uint32_t PIO_IFSCSR; /**< \brief (Pio Offset: 0x0088) Input Filter Slow Clock Status Register */ + __IO uint32_t PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */ + __O uint32_t PIO_PPDDR; /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */ + __O uint32_t PIO_PPDER; /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */ + __I uint32_t PIO_PPDSR; /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */ + __I uint32_t Reserved7[1]; + __O uint32_t PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */ + __O uint32_t PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */ + __I uint32_t PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */ + __I uint32_t Reserved8[1]; + __O uint32_t PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */ + __O uint32_t PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disable Register */ + __I uint32_t PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */ + __I uint32_t Reserved9[1]; + __O uint32_t PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */ + __O uint32_t PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */ + __I uint32_t PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */ + __I uint32_t Reserved10[1]; + __O uint32_t PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low-Level Select Register */ + __O uint32_t PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/High-Level Select Register */ + __I uint32_t PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */ + __I uint32_t Reserved11[1]; + __I uint32_t PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */ + __IO uint32_t PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protection Mode Register */ + __I uint32_t PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protection Status Register */ + __I uint32_t Reserved12[4]; + __I uint32_t PIO_VERSION; /**< \brief (Pio Offset: 0x00FC) Version Register */ + __IO uint32_t PIO_SCHMITT; /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */ + __I uint32_t Reserved13[5]; + __IO uint32_t PIO_DRIVER; /**< \brief (Pio Offset: 0x0118) I/O Drive Register */ + __I uint32_t Reserved14[13]; + __IO uint32_t PIO_PCMR; /**< \brief (Pio Offset: 0x0150) Parallel Capture Mode Register */ + __O uint32_t PIO_PCIER; /**< \brief (Pio Offset: 0x0154) Parallel Capture Interrupt Enable Register */ + __O uint32_t PIO_PCIDR; /**< \brief (Pio Offset: 0x0158) Parallel Capture Interrupt Disable Register */ + __I uint32_t PIO_PCIMR; /**< \brief (Pio Offset: 0x015C) Parallel Capture Interrupt Mask Register */ + __I uint32_t PIO_PCISR; /**< \brief (Pio Offset: 0x0160) Parallel Capture Interrupt Status Register */ + __I uint32_t PIO_PCRHR; /**< \brief (Pio Offset: 0x0164) Parallel Capture Reception Holding Register */ +} Pio; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */ +#define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */ +/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */ +#define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */ +/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */ +#define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */ +/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */ +#define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */ +/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */ +#define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */ +/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */ +#define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */ +/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */ +#define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */ +/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */ +#define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */ +/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */ +#define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filter Status */ +/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */ +#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */ +/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */ +#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */ +/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */ +#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */ +/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */ +#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */ +/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */ +#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */ +#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */ +#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */ +#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */ +#define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi-drive Enable */ +/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */ +#define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi-drive Disable */ +/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */ +#define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi-drive Status */ +/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */ +#define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull-Up Disable */ +/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */ +#define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull-Up Enable */ +/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */ +#define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull-Up Status */ +/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */ +#define PIO_ABCDSR_P0 (0x1u << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P1 (0x1u << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P2 (0x1u << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P3 (0x1u << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P4 (0x1u << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P5 (0x1u << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P6 (0x1u << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P7 (0x1u << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P8 (0x1u << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P9 (0x1u << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P10 (0x1u << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P11 (0x1u << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P12 (0x1u << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P13 (0x1u << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P14 (0x1u << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P15 (0x1u << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P16 (0x1u << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P17 (0x1u << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P18 (0x1u << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P19 (0x1u << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P20 (0x1u << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P21 (0x1u << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P22 (0x1u << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P23 (0x1u << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P24 (0x1u << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P25 (0x1u << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P26 (0x1u << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P27 (0x1u << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P28 (0x1u << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P29 (0x1u << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P30 (0x1u << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P31 (0x1u << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +/* -------- PIO_IFSCDR : (PIO Offset: 0x0080) Input Filter Slow Clock Disable Register -------- */ +#define PIO_IFSCDR_P0 (0x1u << 0) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P1 (0x1u << 1) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P2 (0x1u << 2) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P3 (0x1u << 3) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P4 (0x1u << 4) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P5 (0x1u << 5) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P6 (0x1u << 6) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P7 (0x1u << 7) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P8 (0x1u << 8) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P9 (0x1u << 9) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P10 (0x1u << 10) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P11 (0x1u << 11) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P12 (0x1u << 12) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P13 (0x1u << 13) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P14 (0x1u << 14) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P15 (0x1u << 15) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P16 (0x1u << 16) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P17 (0x1u << 17) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P18 (0x1u << 18) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P19 (0x1u << 19) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P20 (0x1u << 20) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P21 (0x1u << 21) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P22 (0x1u << 22) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P23 (0x1u << 23) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P24 (0x1u << 24) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P25 (0x1u << 25) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P26 (0x1u << 26) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P27 (0x1u << 27) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P28 (0x1u << 28) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P29 (0x1u << 29) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P30 (0x1u << 30) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P31 (0x1u << 31) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +/* -------- PIO_IFSCER : (PIO Offset: 0x0084) Input Filter Slow Clock Enable Register -------- */ +#define PIO_IFSCER_P0 (0x1u << 0) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P1 (0x1u << 1) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P2 (0x1u << 2) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P3 (0x1u << 3) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P4 (0x1u << 4) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P5 (0x1u << 5) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P6 (0x1u << 6) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P7 (0x1u << 7) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P8 (0x1u << 8) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P9 (0x1u << 9) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P10 (0x1u << 10) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P11 (0x1u << 11) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P12 (0x1u << 12) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P13 (0x1u << 13) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P14 (0x1u << 14) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P15 (0x1u << 15) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P16 (0x1u << 16) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P17 (0x1u << 17) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P18 (0x1u << 18) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P19 (0x1u << 19) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P20 (0x1u << 20) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P21 (0x1u << 21) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P22 (0x1u << 22) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P23 (0x1u << 23) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P24 (0x1u << 24) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P25 (0x1u << 25) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P26 (0x1u << 26) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P27 (0x1u << 27) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P28 (0x1u << 28) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P29 (0x1u << 29) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P30 (0x1u << 30) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P31 (0x1u << 31) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +/* -------- PIO_IFSCSR : (PIO Offset: 0x0088) Input Filter Slow Clock Status Register -------- */ +#define PIO_IFSCSR_P0 (0x1u << 0) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P1 (0x1u << 1) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P2 (0x1u << 2) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P3 (0x1u << 3) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P4 (0x1u << 4) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P5 (0x1u << 5) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P6 (0x1u << 6) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P7 (0x1u << 7) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P8 (0x1u << 8) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P9 (0x1u << 9) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P10 (0x1u << 10) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P11 (0x1u << 11) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P12 (0x1u << 12) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P13 (0x1u << 13) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P14 (0x1u << 14) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P15 (0x1u << 15) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P16 (0x1u << 16) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P17 (0x1u << 17) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P18 (0x1u << 18) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P19 (0x1u << 19) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P20 (0x1u << 20) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P21 (0x1u << 21) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P22 (0x1u << 22) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P23 (0x1u << 23) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P24 (0x1u << 24) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P25 (0x1u << 25) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P26 (0x1u << 26) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P27 (0x1u << 27) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P28 (0x1u << 28) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P29 (0x1u << 29) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P30 (0x1u << 30) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P31 (0x1u << 31) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */ +#define PIO_SCDR_DIV_Pos 0 +#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos))) +/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */ +#define PIO_PPDDR_P0 (0x1u << 0) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P1 (0x1u << 1) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P2 (0x1u << 2) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P3 (0x1u << 3) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P4 (0x1u << 4) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P5 (0x1u << 5) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P6 (0x1u << 6) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P7 (0x1u << 7) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P8 (0x1u << 8) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P9 (0x1u << 9) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P10 (0x1u << 10) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P11 (0x1u << 11) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P12 (0x1u << 12) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P13 (0x1u << 13) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P14 (0x1u << 14) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P15 (0x1u << 15) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P16 (0x1u << 16) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P17 (0x1u << 17) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P18 (0x1u << 18) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P19 (0x1u << 19) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P20 (0x1u << 20) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P21 (0x1u << 21) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P22 (0x1u << 22) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P23 (0x1u << 23) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P24 (0x1u << 24) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P25 (0x1u << 25) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P26 (0x1u << 26) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P27 (0x1u << 27) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P28 (0x1u << 28) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P29 (0x1u << 29) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P30 (0x1u << 30) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P31 (0x1u << 31) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */ +#define PIO_PPDER_P0 (0x1u << 0) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P1 (0x1u << 1) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P2 (0x1u << 2) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P3 (0x1u << 3) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P4 (0x1u << 4) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P5 (0x1u << 5) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P6 (0x1u << 6) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P7 (0x1u << 7) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P8 (0x1u << 8) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P9 (0x1u << 9) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P10 (0x1u << 10) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P11 (0x1u << 11) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P12 (0x1u << 12) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P13 (0x1u << 13) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P14 (0x1u << 14) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P15 (0x1u << 15) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P16 (0x1u << 16) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P17 (0x1u << 17) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P18 (0x1u << 18) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P19 (0x1u << 19) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P20 (0x1u << 20) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P21 (0x1u << 21) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P22 (0x1u << 22) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P23 (0x1u << 23) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P24 (0x1u << 24) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P25 (0x1u << 25) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P26 (0x1u << 26) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P27 (0x1u << 27) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P28 (0x1u << 28) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P29 (0x1u << 29) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P30 (0x1u << 30) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P31 (0x1u << 31) /**< \brief (PIO_PPDER) Pull-Down Enable */ +/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */ +#define PIO_PPDSR_P0 (0x1u << 0) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P1 (0x1u << 1) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P2 (0x1u << 2) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P3 (0x1u << 3) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P4 (0x1u << 4) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P5 (0x1u << 5) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P6 (0x1u << 6) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P7 (0x1u << 7) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P8 (0x1u << 8) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P9 (0x1u << 9) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P10 (0x1u << 10) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P11 (0x1u << 11) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P12 (0x1u << 12) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P13 (0x1u << 13) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P14 (0x1u << 14) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P15 (0x1u << 15) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P16 (0x1u << 16) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P17 (0x1u << 17) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P18 (0x1u << 18) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P19 (0x1u << 19) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P20 (0x1u << 20) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P21 (0x1u << 21) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P22 (0x1u << 22) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P23 (0x1u << 23) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P24 (0x1u << 24) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P25 (0x1u << 25) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P26 (0x1u << 26) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P27 (0x1u << 27) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P28 (0x1u << 28) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P29 (0x1u << 29) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P30 (0x1u << 30) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P31 (0x1u << 31) /**< \brief (PIO_PPDSR) Pull-Down Status */ +/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */ +#define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable */ +/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */ +#define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable */ +/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */ +#define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status */ +/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */ +#define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disable Register -------- */ +#define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */ +#define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) IO Line Index */ +/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */ +#define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */ +#define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection */ +/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */ +#define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low-Level Select Register -------- */ +#define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/High-Level Select Register -------- */ +#define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */ +#define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */ +#define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status */ +/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protection Mode Register -------- */ +#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protection Enable */ +#define PIO_WPMR_WPKEY_Pos 8 +#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protection Key */ +#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos))) +#define PIO_WPMR_WPKEY_PASSWD (0x50494Fu << 8) /**< \brief (PIO_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protection Status Register -------- */ +#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protection Violation Status */ +#define PIO_WPSR_WPVSRC_Pos 8 +#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protection Violation Source */ +/* -------- PIO_VERSION : (PIO Offset: 0x00FC) Version Register -------- */ +#define PIO_VERSION_VERSION_Pos 0 +#define PIO_VERSION_VERSION_Msk (0xfffu << PIO_VERSION_VERSION_Pos) /**< \brief (PIO_VERSION) Hardware Module Version */ +#define PIO_VERSION_MFN_Pos 16 +#define PIO_VERSION_MFN_Msk (0x7u << PIO_VERSION_MFN_Pos) /**< \brief (PIO_VERSION) Metal Fix Number */ +/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */ +#define PIO_SCHMITT_SCHMITT0 (0x1u << 0) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT1 (0x1u << 1) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT2 (0x1u << 2) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT3 (0x1u << 3) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT4 (0x1u << 4) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT5 (0x1u << 5) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT6 (0x1u << 6) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT7 (0x1u << 7) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT8 (0x1u << 8) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT9 (0x1u << 9) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT10 (0x1u << 10) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT11 (0x1u << 11) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT12 (0x1u << 12) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT13 (0x1u << 13) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT14 (0x1u << 14) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT15 (0x1u << 15) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT16 (0x1u << 16) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT17 (0x1u << 17) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT18 (0x1u << 18) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT19 (0x1u << 19) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT20 (0x1u << 20) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT21 (0x1u << 21) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT22 (0x1u << 22) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT23 (0x1u << 23) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT24 (0x1u << 24) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT25 (0x1u << 25) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT26 (0x1u << 26) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT27 (0x1u << 27) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT28 (0x1u << 28) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT29 (0x1u << 29) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT30 (0x1u << 30) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT31 (0x1u << 31) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +/* -------- PIO_DRIVER : (PIO Offset: 0x0118) I/O Drive Register -------- */ +#define PIO_DRIVER_LINE0 (0x1u << 0) /**< \brief (PIO_DRIVER) Drive of PIO Line 0 */ +#define PIO_DRIVER_LINE0_LOW_DRIVE (0x0u << 0) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE0_HIGH_DRIVE (0x1u << 0) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE1 (0x1u << 1) /**< \brief (PIO_DRIVER) Drive of PIO Line 1 */ +#define PIO_DRIVER_LINE1_LOW_DRIVE (0x0u << 1) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE1_HIGH_DRIVE (0x1u << 1) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE2 (0x1u << 2) /**< \brief (PIO_DRIVER) Drive of PIO Line 2 */ +#define PIO_DRIVER_LINE2_LOW_DRIVE (0x0u << 2) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE2_HIGH_DRIVE (0x1u << 2) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE3 (0x1u << 3) /**< \brief (PIO_DRIVER) Drive of PIO Line 3 */ +#define PIO_DRIVER_LINE3_LOW_DRIVE (0x0u << 3) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE3_HIGH_DRIVE (0x1u << 3) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE4 (0x1u << 4) /**< \brief (PIO_DRIVER) Drive of PIO Line 4 */ +#define PIO_DRIVER_LINE4_LOW_DRIVE (0x0u << 4) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE4_HIGH_DRIVE (0x1u << 4) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE5 (0x1u << 5) /**< \brief (PIO_DRIVER) Drive of PIO Line 5 */ +#define PIO_DRIVER_LINE5_LOW_DRIVE (0x0u << 5) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE5_HIGH_DRIVE (0x1u << 5) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE6 (0x1u << 6) /**< \brief (PIO_DRIVER) Drive of PIO Line 6 */ +#define PIO_DRIVER_LINE6_LOW_DRIVE (0x0u << 6) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE6_HIGH_DRIVE (0x1u << 6) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE7 (0x1u << 7) /**< \brief (PIO_DRIVER) Drive of PIO Line 7 */ +#define PIO_DRIVER_LINE7_LOW_DRIVE (0x0u << 7) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE7_HIGH_DRIVE (0x1u << 7) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE8 (0x1u << 8) /**< \brief (PIO_DRIVER) Drive of PIO Line 8 */ +#define PIO_DRIVER_LINE8_LOW_DRIVE (0x0u << 8) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE8_HIGH_DRIVE (0x1u << 8) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE9 (0x1u << 9) /**< \brief (PIO_DRIVER) Drive of PIO Line 9 */ +#define PIO_DRIVER_LINE9_LOW_DRIVE (0x0u << 9) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE9_HIGH_DRIVE (0x1u << 9) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE10 (0x1u << 10) /**< \brief (PIO_DRIVER) Drive of PIO Line 10 */ +#define PIO_DRIVER_LINE10_LOW_DRIVE (0x0u << 10) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE10_HIGH_DRIVE (0x1u << 10) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE11 (0x1u << 11) /**< \brief (PIO_DRIVER) Drive of PIO Line 11 */ +#define PIO_DRIVER_LINE11_LOW_DRIVE (0x0u << 11) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE11_HIGH_DRIVE (0x1u << 11) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE12 (0x1u << 12) /**< \brief (PIO_DRIVER) Drive of PIO Line 12 */ +#define PIO_DRIVER_LINE12_LOW_DRIVE (0x0u << 12) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE12_HIGH_DRIVE (0x1u << 12) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE13 (0x1u << 13) /**< \brief (PIO_DRIVER) Drive of PIO Line 13 */ +#define PIO_DRIVER_LINE13_LOW_DRIVE (0x0u << 13) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE13_HIGH_DRIVE (0x1u << 13) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE14 (0x1u << 14) /**< \brief (PIO_DRIVER) Drive of PIO Line 14 */ +#define PIO_DRIVER_LINE14_LOW_DRIVE (0x0u << 14) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE14_HIGH_DRIVE (0x1u << 14) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE15 (0x1u << 15) /**< \brief (PIO_DRIVER) Drive of PIO Line 15 */ +#define PIO_DRIVER_LINE15_LOW_DRIVE (0x0u << 15) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE15_HIGH_DRIVE (0x1u << 15) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE16 (0x1u << 16) /**< \brief (PIO_DRIVER) Drive of PIO Line 16 */ +#define PIO_DRIVER_LINE16_LOW_DRIVE (0x0u << 16) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE16_HIGH_DRIVE (0x1u << 16) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE17 (0x1u << 17) /**< \brief (PIO_DRIVER) Drive of PIO Line 17 */ +#define PIO_DRIVER_LINE17_LOW_DRIVE (0x0u << 17) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE17_HIGH_DRIVE (0x1u << 17) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE18 (0x1u << 18) /**< \brief (PIO_DRIVER) Drive of PIO Line 18 */ +#define PIO_DRIVER_LINE18_LOW_DRIVE (0x0u << 18) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE18_HIGH_DRIVE (0x1u << 18) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE19 (0x1u << 19) /**< \brief (PIO_DRIVER) Drive of PIO Line 19 */ +#define PIO_DRIVER_LINE19_LOW_DRIVE (0x0u << 19) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE19_HIGH_DRIVE (0x1u << 19) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE20 (0x1u << 20) /**< \brief (PIO_DRIVER) Drive of PIO Line 20 */ +#define PIO_DRIVER_LINE20_LOW_DRIVE (0x0u << 20) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE20_HIGH_DRIVE (0x1u << 20) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE21 (0x1u << 21) /**< \brief (PIO_DRIVER) Drive of PIO Line 21 */ +#define PIO_DRIVER_LINE21_LOW_DRIVE (0x0u << 21) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE21_HIGH_DRIVE (0x1u << 21) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE22 (0x1u << 22) /**< \brief (PIO_DRIVER) Drive of PIO Line 22 */ +#define PIO_DRIVER_LINE22_LOW_DRIVE (0x0u << 22) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE22_HIGH_DRIVE (0x1u << 22) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE23 (0x1u << 23) /**< \brief (PIO_DRIVER) Drive of PIO Line 23 */ +#define PIO_DRIVER_LINE23_LOW_DRIVE (0x0u << 23) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE23_HIGH_DRIVE (0x1u << 23) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE24 (0x1u << 24) /**< \brief (PIO_DRIVER) Drive of PIO Line 24 */ +#define PIO_DRIVER_LINE24_LOW_DRIVE (0x0u << 24) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE24_HIGH_DRIVE (0x1u << 24) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE25 (0x1u << 25) /**< \brief (PIO_DRIVER) Drive of PIO Line 25 */ +#define PIO_DRIVER_LINE25_LOW_DRIVE (0x0u << 25) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE25_HIGH_DRIVE (0x1u << 25) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE26 (0x1u << 26) /**< \brief (PIO_DRIVER) Drive of PIO Line 26 */ +#define PIO_DRIVER_LINE26_LOW_DRIVE (0x0u << 26) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE26_HIGH_DRIVE (0x1u << 26) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE27 (0x1u << 27) /**< \brief (PIO_DRIVER) Drive of PIO Line 27 */ +#define PIO_DRIVER_LINE27_LOW_DRIVE (0x0u << 27) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE27_HIGH_DRIVE (0x1u << 27) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE28 (0x1u << 28) /**< \brief (PIO_DRIVER) Drive of PIO Line 28 */ +#define PIO_DRIVER_LINE28_LOW_DRIVE (0x0u << 28) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE28_HIGH_DRIVE (0x1u << 28) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE29 (0x1u << 29) /**< \brief (PIO_DRIVER) Drive of PIO Line 29 */ +#define PIO_DRIVER_LINE29_LOW_DRIVE (0x0u << 29) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE29_HIGH_DRIVE (0x1u << 29) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE30 (0x1u << 30) /**< \brief (PIO_DRIVER) Drive of PIO Line 30 */ +#define PIO_DRIVER_LINE30_LOW_DRIVE (0x0u << 30) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE30_HIGH_DRIVE (0x1u << 30) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE31 (0x1u << 31) /**< \brief (PIO_DRIVER) Drive of PIO Line 31 */ +#define PIO_DRIVER_LINE31_LOW_DRIVE (0x0u << 31) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE31_HIGH_DRIVE (0x1u << 31) /**< \brief (PIO_DRIVER) Highest drive */ +/* -------- PIO_PCMR : (PIO Offset: 0x0150) Parallel Capture Mode Register -------- */ +#define PIO_PCMR_PCEN (0x1u << 0) /**< \brief (PIO_PCMR) Parallel Capture Mode Enable */ +#define PIO_PCMR_DSIZE_Pos 4 +#define PIO_PCMR_DSIZE_Msk (0x3u << PIO_PCMR_DSIZE_Pos) /**< \brief (PIO_PCMR) Parallel Capture Mode Data Size */ +#define PIO_PCMR_DSIZE(value) ((PIO_PCMR_DSIZE_Msk & ((value) << PIO_PCMR_DSIZE_Pos))) +#define PIO_PCMR_DSIZE_BYTE (0x0u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a byte (8-bit) */ +#define PIO_PCMR_DSIZE_HALFWORD (0x1u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a half-word (16-bit) */ +#define PIO_PCMR_DSIZE_WORD (0x2u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a word (32-bit) */ +#define PIO_PCMR_ALWYS (0x1u << 9) /**< \brief (PIO_PCMR) Parallel Capture Mode Always Sampling */ +#define PIO_PCMR_HALFS (0x1u << 10) /**< \brief (PIO_PCMR) Parallel Capture Mode Half Sampling */ +#define PIO_PCMR_FRSTS (0x1u << 11) /**< \brief (PIO_PCMR) Parallel Capture Mode First Sample */ +/* -------- PIO_PCIER : (PIO Offset: 0x0154) Parallel Capture Interrupt Enable Register -------- */ +#define PIO_PCIER_DRDY (0x1u << 0) /**< \brief (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable */ +#define PIO_PCIER_OVRE (0x1u << 1) /**< \brief (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable */ +#define PIO_PCIER_ENDRX (0x1u << 2) /**< \brief (PIO_PCIER) End of Reception Transfer Interrupt Enable */ +#define PIO_PCIER_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIER) Reception Buffer Full Interrupt Enable */ +/* -------- PIO_PCIDR : (PIO Offset: 0x0158) Parallel Capture Interrupt Disable Register -------- */ +#define PIO_PCIDR_DRDY (0x1u << 0) /**< \brief (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable */ +#define PIO_PCIDR_OVRE (0x1u << 1) /**< \brief (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable */ +#define PIO_PCIDR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIDR) End of Reception Transfer Interrupt Disable */ +#define PIO_PCIDR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIDR) Reception Buffer Full Interrupt Disable */ +/* -------- PIO_PCIMR : (PIO Offset: 0x015C) Parallel Capture Interrupt Mask Register -------- */ +#define PIO_PCIMR_DRDY (0x1u << 0) /**< \brief (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask */ +#define PIO_PCIMR_OVRE (0x1u << 1) /**< \brief (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask */ +#define PIO_PCIMR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIMR) End of Reception Transfer Interrupt Mask */ +#define PIO_PCIMR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIMR) Reception Buffer Full Interrupt Mask */ +/* -------- PIO_PCISR : (PIO Offset: 0x0160) Parallel Capture Interrupt Status Register -------- */ +#define PIO_PCISR_DRDY (0x1u << 0) /**< \brief (PIO_PCISR) Parallel Capture Mode Data Ready */ +#define PIO_PCISR_OVRE (0x1u << 1) /**< \brief (PIO_PCISR) Parallel Capture Mode Overrun Error */ +/* -------- PIO_PCRHR : (PIO Offset: 0x0164) Parallel Capture Reception Holding Register -------- */ +#define PIO_PCRHR_RDATA_Pos 0 +#define PIO_PCRHR_RDATA_Msk (0xffffffffu << PIO_PCRHR_RDATA_Pos) /**< \brief (PIO_PCRHR) Parallel Capture Mode Reception Data */ + +/*@}*/ + + +#endif /* _SAME70_PIO_COMPONENT_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/pmc.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/pmc.h new file mode 100644 index 000000000..ea4579b8a --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/pmc.h @@ -0,0 +1,774 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_PMC_COMPONENT_ +#define _SAME70_PMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Power Management Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_PMC Power Management Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Pmc hardware registers */ +typedef struct { + __O uint32_t PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */ + __O uint32_t PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */ + __I uint32_t PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */ + __I uint32_t Reserved1[1]; + __O uint32_t PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */ + __O uint32_t PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */ + __I uint32_t PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */ + __IO uint32_t CKGR_UCKR; /**< \brief (Pmc Offset: 0x001C) UTMI Clock Register */ + __IO uint32_t CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */ + __IO uint32_t CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */ + __IO uint32_t CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */ + __I uint32_t Reserved3[1]; + __IO uint32_t PMC_USB; /**< \brief (Pmc Offset: 0x0038) USB Clock Register */ + __I uint32_t Reserved4[1]; + __IO uint32_t PMC_PCK[8]; /**< \brief (Pmc Offset: 0x40) Programmable Clock Register (chid = 0) */ + __O uint32_t PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */ + __O uint32_t PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */ + __I uint32_t PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */ + __I uint32_t PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */ + __IO uint32_t PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */ + __IO uint32_t PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */ + __O uint32_t PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */ + __I uint32_t Reserved5[26]; + __IO uint32_t PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protection Mode Register */ + __I uint32_t PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protection Status Register */ + __I uint32_t Reserved6[4]; + __I uint32_t PMC_VERSION; /**< \brief (Pmc Offset: 0x00FC) Version Register */ + __O uint32_t PMC_PCER1; /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */ + __O uint32_t PMC_PCDR1; /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */ + __I uint32_t PMC_PCSR1; /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */ + __IO uint32_t PMC_PCR; /**< \brief (Pmc Offset: 0x010C) Peripheral Control Register */ + __IO uint32_t PMC_OCR; /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */ + __O uint32_t PMC_SLPWK_ER0; /**< \brief (Pmc Offset: 0x0114) SleepWalking Enable Register 0 */ + __O uint32_t PMC_SLPWK_DR0; /**< \brief (Pmc Offset: 0x0118) SleepWalking Disable Register 0 */ + __I uint32_t PMC_SLPWK_SR0; /**< \brief (Pmc Offset: 0x011C) SleepWalking Status Register 0 */ + __I uint32_t PMC_SLPWK_ASR0; /**< \brief (Pmc Offset: 0x0120) SleepWalking Activity Status Register 0 */ + __I uint32_t Reserved7[3]; + __IO uint32_t PMC_PMMR; /**< \brief (Pmc Offset: 0x0130) PLL Maximum Multiplier Value Register */ + __O uint32_t PMC_SLPWK_ER1; /**< \brief (Pmc Offset: 0x0134) SleepWalking Enable Register 1 */ + __O uint32_t PMC_SLPWK_DR1; /**< \brief (Pmc Offset: 0x0138) SleepWalking Disable Register 1 */ + __I uint32_t PMC_SLPWK_SR1; /**< \brief (Pmc Offset: 0x013C) SleepWalking Status Register 1 */ + __I uint32_t PMC_SLPWK_ASR1; /**< \brief (Pmc Offset: 0x0140) SleepWalking Activity Status Register 1 */ + __I uint32_t PMC_SLPWK_AIPR; /**< \brief (Pmc Offset: 0x0144) SleepWalking Activity In Progress Register */ + __I uint32_t Reserved8[4]; + __IO uint32_t PMC_APLLACR; /**< \brief (Pmc Offset: 0x0158) Audio PLL Analog Configuration Register */ + __IO uint32_t PMC_WMST; /**< \brief (Pmc Offset: 0x015C) Wait Mode Startup Time Register */ +} Pmc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */ +#define PMC_SCER_USBCLK (0x1u << 5) /**< \brief (PMC_SCER) Enable USB FS Clock */ +#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */ +#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */ +#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */ +#define PMC_SCER_PCK3 (0x1u << 11) /**< \brief (PMC_SCER) Programmable Clock 3 Output Enable */ +#define PMC_SCER_PCK4 (0x1u << 12) /**< \brief (PMC_SCER) Programmable Clock 4 Output Enable */ +#define PMC_SCER_PCK5 (0x1u << 13) /**< \brief (PMC_SCER) Programmable Clock 5 Output Enable */ +#define PMC_SCER_PCK6 (0x1u << 14) /**< \brief (PMC_SCER) Programmable Clock 6 Output Enable */ +/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */ +#define PMC_SCDR_USBCLK (0x1u << 5) /**< \brief (PMC_SCDR) Disable USB FS Clock */ +#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */ +#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */ +#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */ +#define PMC_SCDR_PCK3 (0x1u << 11) /**< \brief (PMC_SCDR) Programmable Clock 3 Output Disable */ +#define PMC_SCDR_PCK4 (0x1u << 12) /**< \brief (PMC_SCDR) Programmable Clock 4 Output Disable */ +#define PMC_SCDR_PCK5 (0x1u << 13) /**< \brief (PMC_SCDR) Programmable Clock 5 Output Disable */ +#define PMC_SCDR_PCK6 (0x1u << 14) /**< \brief (PMC_SCDR) Programmable Clock 6 Output Disable */ +/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */ +#define PMC_SCSR_HCLKS (0x1u << 0) /**< \brief (PMC_SCSR) Processor Clock Status */ +#define PMC_SCSR_USBCLK (0x1u << 5) /**< \brief (PMC_SCSR) USB FS Clock Status */ +#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */ +#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */ +#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */ +#define PMC_SCSR_PCK3 (0x1u << 11) /**< \brief (PMC_SCSR) Programmable Clock 3 Output Status */ +#define PMC_SCSR_PCK4 (0x1u << 12) /**< \brief (PMC_SCSR) Programmable Clock 4 Output Status */ +#define PMC_SCSR_PCK5 (0x1u << 13) /**< \brief (PMC_SCSR) Programmable Clock 5 Output Status */ +#define PMC_SCSR_PCK6 (0x1u << 14) /**< \brief (PMC_SCSR) Programmable Clock 6 Output Status */ +/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */ +#define PMC_PCER0_PID7 (0x1u << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */ +#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */ +#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */ +#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */ +#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */ +#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */ +#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */ +#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */ +#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */ +#define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */ +#define PMC_PCER0_PID17 (0x1u << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */ +#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */ +#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */ +#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */ +#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */ +#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */ +#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */ +#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */ +#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */ +#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */ +#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */ +#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */ +#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */ +#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */ +#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */ +/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */ +#define PMC_PCDR0_PID7 (0x1u << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */ +#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */ +#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */ +#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */ +#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */ +#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */ +#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */ +#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */ +#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */ +#define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */ +#define PMC_PCDR0_PID17 (0x1u << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */ +#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */ +#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */ +#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */ +#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */ +#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */ +#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */ +#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */ +#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */ +#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */ +#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */ +#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */ +#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */ +#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */ +#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */ +/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */ +#define PMC_PCSR0_PID7 (0x1u << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */ +#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */ +#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */ +#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */ +#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */ +#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */ +#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */ +#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */ +#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */ +#define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */ +#define PMC_PCSR0_PID17 (0x1u << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */ +#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */ +#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */ +#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */ +#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */ +#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */ +#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */ +#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */ +#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */ +#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */ +#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */ +#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */ +#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */ +#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */ +#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */ +/* -------- CKGR_UCKR : (PMC Offset: 0x001C) UTMI Clock Register -------- */ +#define CKGR_UCKR_UPLLEN (0x1u << 16) /**< \brief (CKGR_UCKR) UTMI PLL Enable */ +#define CKGR_UCKR_UPLLCOUNT_Pos 20 +#define CKGR_UCKR_UPLLCOUNT_Msk (0xfu << CKGR_UCKR_UPLLCOUNT_Pos) /**< \brief (CKGR_UCKR) UTMI PLL Start-up Time */ +#define CKGR_UCKR_UPLLCOUNT(value) ((CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos))) +/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */ +#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */ +#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */ +#define CKGR_MOR_WAITMODE (0x1u << 2) /**< \brief (CKGR_MOR) Wait Mode Command (Write-only) */ +#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */ +#define CKGR_MOR_MOSCRCF_Pos 4 +#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */ +#define CKGR_MOR_MOSCRCF(value) ((CKGR_MOR_MOSCRCF_Msk & ((value) << CKGR_MOR_MOSCRCF_Pos))) +#define CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) /**< \brief (CKGR_MOR) Fast RC oscillator frequency is at 4 MHz (default) */ +#define CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) /**< \brief (CKGR_MOR) Fast RC oscillator frequency is at 8 MHz */ +#define CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) /**< \brief (CKGR_MOR) Fast RC oscillator frequency is at 12 MHz */ +#define CKGR_MOR_MOSCXTST_Pos 8 +#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */ +#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos))) +#define CKGR_MOR_KEY_Pos 16 +#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Write Access Password */ +#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos))) +#define CKGR_MOR_KEY_PASSWD (0x37u << 16) /**< \brief (CKGR_MOR) Writing any other value in this field aborts the write operation.Always reads as 0. */ +#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */ +#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */ +#define CKGR_MOR_XT32KFME (0x1u << 26) /**< \brief (CKGR_MOR) Slow Crystal Oscillator Frequency Monitoring Enable */ +/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */ +#define CKGR_MCFR_MAINF_Pos 0 +#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */ +#define CKGR_MCFR_MAINF(value) ((CKGR_MCFR_MAINF_Msk & ((value) << CKGR_MCFR_MAINF_Pos))) +#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Frequency Measure Ready */ +#define CKGR_MCFR_RCMEAS (0x1u << 20) /**< \brief (CKGR_MCFR) RC Oscillator Frequency Measure (write-only) */ +#define CKGR_MCFR_CCSS (0x1u << 24) /**< \brief (CKGR_MCFR) Counter Clock Source Selection */ +/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */ +#define CKGR_PLLAR_DIVA_Pos 0 +#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) PLLA Front End Divider */ +#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos))) +#define CKGR_PLLAR_DIVA_0 (0x0u << 0) /**< \brief (CKGR_PLLAR) Divider output is 0 and PLLA is disabled. */ +#define CKGR_PLLAR_DIVA_BYPASS (0x1u << 0) /**< \brief (CKGR_PLLAR) Divider is bypassed (divide by 1) and PLLA is enabled. */ +#define CKGR_PLLAR_PLLACOUNT_Pos 8 +#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */ +#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos))) +#define CKGR_PLLAR_MULA_Pos 16 +#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */ +#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos))) +#define CKGR_PLLAR_ONE (0x1u << 29) /**< \brief (CKGR_PLLAR) Must Be Set to 1 */ +/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */ +#define PMC_MCKR_CSS_Pos 0 +#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */ +#define PMC_MCKR_CSS(value) ((PMC_MCKR_CSS_Msk & ((value) << PMC_MCKR_CSS_Pos))) +#define PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */ +#define PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */ +#define PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */ +#define PMC_MCKR_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_MCKR) Divided UPLL Clock is selected */ +#define PMC_MCKR_PRES_Pos 4 +#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */ +#define PMC_MCKR_PRES(value) ((PMC_MCKR_PRES_Msk & ((value) << PMC_MCKR_PRES_Pos))) +#define PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */ +#define PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */ +#define PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */ +#define PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */ +#define PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */ +#define PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */ +#define PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */ +#define PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */ +#define PMC_MCKR_MDIV_Pos 8 +#define PMC_MCKR_MDIV_Msk (0x3u << PMC_MCKR_MDIV_Pos) /**< \brief (PMC_MCKR) Master Clock Division */ +#define PMC_MCKR_MDIV(value) ((PMC_MCKR_MDIV_Msk & ((value) << PMC_MCKR_MDIV_Pos))) +#define PMC_MCKR_MDIV_EQ_PCK (0x0u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 1. */ +#define PMC_MCKR_MDIV_PCK_DIV2 (0x1u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 2. */ +#define PMC_MCKR_MDIV_PCK_DIV4 (0x2u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 4. */ +#define PMC_MCKR_MDIV_PCK_DIV3 (0x3u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 3. */ +#define PMC_MCKR_UPLLDIV2 (0x1u << 13) /**< \brief (PMC_MCKR) UPLL Divisor by 2 */ +/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */ +#define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB Input Clock Selection */ +#define PMC_USB_USBDIV_Pos 8 +#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock */ +#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos))) +/* -------- PMC_PCK[8] : (PMC Offset: 0x40) Programmable Clock Register (chid = 0) -------- */ +#define PMC_PCK_CSS_Pos 0 +#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[8]) Programmable Clock Source Selection */ +#define PMC_PCK_CSS(value) ((PMC_PCK_CSS_Msk & ((value) << PMC_PCK_CSS_Pos))) +#define PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[8]) Slow Clock is selected */ +#define PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[8]) Main Clock is selected */ +#define PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[8]) PLLA Clock is selected */ +#define PMC_PCK_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_PCK[8]) Divided UPLL Clock is selected */ +#define PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[8]) Master Clock is selected */ +#define PMC_PCK_PRES_Pos 4 +#define PMC_PCK_PRES_Msk (0xffu << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[8]) Programmable Clock Prescaler */ +#define PMC_PCK_PRES(value) ((PMC_PCK_PRES_Msk & ((value) << PMC_PCK_PRES_Pos))) +/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */ +#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */ +#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */ +#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */ +#define PMC_IER_LOCKU (0x1u << 6) /**< \brief (PMC_IER) UTMI PLL Lock Interrupt Enable */ +#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */ +#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */ +#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */ +#define PMC_IER_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IER) Programmable Clock Ready 3 Interrupt Enable */ +#define PMC_IER_PCKRDY4 (0x1u << 12) /**< \brief (PMC_IER) Programmable Clock Ready 4 Interrupt Enable */ +#define PMC_IER_PCKRDY5 (0x1u << 13) /**< \brief (PMC_IER) Programmable Clock Ready 5 Interrupt Enable */ +#define PMC_IER_PCKRDY6 (0x1u << 14) /**< \brief (PMC_IER) Programmable Clock Ready 6 Interrupt Enable */ +#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */ +#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */ +#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */ +#define PMC_IER_XT32KERR (0x1u << 21) /**< \brief (PMC_IER) Slow Crystal Oscillator Error Interrupt Enable */ +/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */ +#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */ +#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */ +#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */ +#define PMC_IDR_LOCKU (0x1u << 6) /**< \brief (PMC_IDR) UTMI PLL Lock Interrupt Disable */ +#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */ +#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */ +#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */ +#define PMC_IDR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IDR) Programmable Clock Ready 3 Interrupt Disable */ +#define PMC_IDR_PCKRDY4 (0x1u << 12) /**< \brief (PMC_IDR) Programmable Clock Ready 4 Interrupt Disable */ +#define PMC_IDR_PCKRDY5 (0x1u << 13) /**< \brief (PMC_IDR) Programmable Clock Ready 5 Interrupt Disable */ +#define PMC_IDR_PCKRDY6 (0x1u << 14) /**< \brief (PMC_IDR) Programmable Clock Ready 6 Interrupt Disable */ +#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */ +#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */ +#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */ +#define PMC_IDR_XT32KERR (0x1u << 21) /**< \brief (PMC_IDR) Slow Crystal Oscillator Error Interrupt Disable */ +/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */ +#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main Crystal Oscillator Status */ +#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */ +#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */ +#define PMC_SR_LOCKU (0x1u << 6) /**< \brief (PMC_SR) UTMI PLL Lock Status */ +#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */ +#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY4 (0x1u << 12) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY5 (0x1u << 13) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY6 (0x1u << 14) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */ +#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */ +#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */ +#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */ +#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */ +#define PMC_SR_XT32KERR (0x1u << 21) /**< \brief (PMC_SR) Slow Crystal Oscillator Error */ +/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */ +#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */ +#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */ +#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */ +#define PMC_IMR_LOCKU (0x1u << 6) /**< \brief (PMC_IMR) UTMI PLL Lock Interrupt Mask */ +#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */ +#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */ +#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */ +#define PMC_IMR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IMR) Programmable Clock Ready 3 Interrupt Mask */ +#define PMC_IMR_PCKRDY4 (0x1u << 12) /**< \brief (PMC_IMR) Programmable Clock Ready 4 Interrupt Mask */ +#define PMC_IMR_PCKRDY5 (0x1u << 13) /**< \brief (PMC_IMR) Programmable Clock Ready 5 Interrupt Mask */ +#define PMC_IMR_PCKRDY6 (0x1u << 14) /**< \brief (PMC_IMR) Programmable Clock Ready 6 Interrupt Mask */ +#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */ +#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */ +#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */ +#define PMC_IMR_XT32KERR (0x1u << 21) /**< \brief (PMC_IMR) Slow Crystal Oscillator Error Interrupt Mask */ +/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */ +#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */ +#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */ +#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */ +#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */ +#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */ +#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */ +#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */ +#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */ +#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */ +#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */ +#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */ +#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */ +#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */ +#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */ +#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */ +#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */ +#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */ +#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */ +#define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */ +#define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low-power Mode */ +#define PMC_FSMR_FLPM_Pos 21 +#define PMC_FSMR_FLPM_Msk (0x3u << PMC_FSMR_FLPM_Pos) /**< \brief (PMC_FSMR) Flash Low-power Mode */ +#define PMC_FSMR_FLPM(value) ((PMC_FSMR_FLPM_Msk & ((value) << PMC_FSMR_FLPM_Pos))) +#define PMC_FSMR_FLPM_FLASH_STANDBY (0x0u << 21) /**< \brief (PMC_FSMR) Flash is in Standby Mode when system enters Wait Mode */ +#define PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN (0x1u << 21) /**< \brief (PMC_FSMR) Flash is in Deep-power-down mode when system enters Wait Mode */ +#define PMC_FSMR_FLPM_FLASH_IDLE (0x2u << 21) /**< \brief (PMC_FSMR) Idle mode */ +#define PMC_FSMR_FFLPM (0x1u << 23) /**< \brief (PMC_FSMR) Force Flash Low-power Mode */ +/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */ +#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 0 */ +#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 1 */ +#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 2 */ +#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 3 */ +#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 4 */ +#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 5 */ +#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 6 */ +#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 7 */ +#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 8 */ +#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 9 */ +#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 10 */ +#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 11 */ +#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 12 */ +#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 13 */ +#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 14 */ +#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 15 */ +/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */ +#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */ +/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protection Mode Register -------- */ +#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protection Enable */ +#define PMC_WPMR_WPKEY_Pos 8 +#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protection Key */ +#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos))) +#define PMC_WPMR_WPKEY_PASSWD (0x504D43u << 8) /**< \brief (PMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protection Status Register -------- */ +#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protection Violation Status */ +#define PMC_WPSR_WPVSRC_Pos 8 +#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protection Violation Source */ +/* -------- PMC_VERSION : (PMC Offset: 0x00FC) Version Register -------- */ +#define PMC_VERSION_VERSION_Pos 0 +#define PMC_VERSION_VERSION_Msk (0xfffu << PMC_VERSION_VERSION_Pos) /**< \brief (PMC_VERSION) Version of the Hardware Module */ +#define PMC_VERSION_MFN_Pos 16 +#define PMC_VERSION_MFN_Msk (0x7u << PMC_VERSION_MFN_Pos) /**< \brief (PMC_VERSION) Metal Fix Number */ +/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */ +#define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */ +#define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */ +#define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */ +#define PMC_PCER1_PID35 (0x1u << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */ +#define PMC_PCER1_PID37 (0x1u << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */ +#define PMC_PCER1_PID39 (0x1u << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */ +#define PMC_PCER1_PID40 (0x1u << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */ +#define PMC_PCER1_PID41 (0x1u << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */ +#define PMC_PCER1_PID42 (0x1u << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */ +#define PMC_PCER1_PID43 (0x1u << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */ +#define PMC_PCER1_PID44 (0x1u << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */ +#define PMC_PCER1_PID45 (0x1u << 13) /**< \brief (PMC_PCER1) Peripheral Clock 45 Enable */ +#define PMC_PCER1_PID46 (0x1u << 14) /**< \brief (PMC_PCER1) Peripheral Clock 46 Enable */ +#define PMC_PCER1_PID47 (0x1u << 15) /**< \brief (PMC_PCER1) Peripheral Clock 47 Enable */ +#define PMC_PCER1_PID48 (0x1u << 16) /**< \brief (PMC_PCER1) Peripheral Clock 48 Enable */ +#define PMC_PCER1_PID49 (0x1u << 17) /**< \brief (PMC_PCER1) Peripheral Clock 49 Enable */ +#define PMC_PCER1_PID50 (0x1u << 18) /**< \brief (PMC_PCER1) Peripheral Clock 50 Enable */ +#define PMC_PCER1_PID51 (0x1u << 19) /**< \brief (PMC_PCER1) Peripheral Clock 51 Enable */ +#define PMC_PCER1_PID52 (0x1u << 20) /**< \brief (PMC_PCER1) Peripheral Clock 52 Enable */ +#define PMC_PCER1_PID53 (0x1u << 21) /**< \brief (PMC_PCER1) Peripheral Clock 53 Enable */ +#define PMC_PCER1_PID56 (0x1u << 24) /**< \brief (PMC_PCER1) Peripheral Clock 56 Enable */ +#define PMC_PCER1_PID57 (0x1u << 25) /**< \brief (PMC_PCER1) Peripheral Clock 57 Enable */ +#define PMC_PCER1_PID58 (0x1u << 26) /**< \brief (PMC_PCER1) Peripheral Clock 58 Enable */ +#define PMC_PCER1_PID59 (0x1u << 27) /**< \brief (PMC_PCER1) Peripheral Clock 59 Enable */ +#define PMC_PCER1_PID60 (0x1u << 28) /**< \brief (PMC_PCER1) Peripheral Clock 60 Enable */ +/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */ +#define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */ +#define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */ +#define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */ +#define PMC_PCDR1_PID35 (0x1u << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */ +#define PMC_PCDR1_PID37 (0x1u << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */ +#define PMC_PCDR1_PID39 (0x1u << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */ +#define PMC_PCDR1_PID40 (0x1u << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */ +#define PMC_PCDR1_PID41 (0x1u << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */ +#define PMC_PCDR1_PID42 (0x1u << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */ +#define PMC_PCDR1_PID43 (0x1u << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */ +#define PMC_PCDR1_PID44 (0x1u << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */ +#define PMC_PCDR1_PID45 (0x1u << 13) /**< \brief (PMC_PCDR1) Peripheral Clock 45 Disable */ +#define PMC_PCDR1_PID46 (0x1u << 14) /**< \brief (PMC_PCDR1) Peripheral Clock 46 Disable */ +#define PMC_PCDR1_PID47 (0x1u << 15) /**< \brief (PMC_PCDR1) Peripheral Clock 47 Disable */ +#define PMC_PCDR1_PID48 (0x1u << 16) /**< \brief (PMC_PCDR1) Peripheral Clock 48 Disable */ +#define PMC_PCDR1_PID49 (0x1u << 17) /**< \brief (PMC_PCDR1) Peripheral Clock 49 Disable */ +#define PMC_PCDR1_PID50 (0x1u << 18) /**< \brief (PMC_PCDR1) Peripheral Clock 50 Disable */ +#define PMC_PCDR1_PID51 (0x1u << 19) /**< \brief (PMC_PCDR1) Peripheral Clock 51 Disable */ +#define PMC_PCDR1_PID52 (0x1u << 20) /**< \brief (PMC_PCDR1) Peripheral Clock 52 Disable */ +#define PMC_PCDR1_PID53 (0x1u << 21) /**< \brief (PMC_PCDR1) Peripheral Clock 53 Disable */ +#define PMC_PCDR1_PID56 (0x1u << 24) /**< \brief (PMC_PCDR1) Peripheral Clock 56 Disable */ +#define PMC_PCDR1_PID57 (0x1u << 25) /**< \brief (PMC_PCDR1) Peripheral Clock 57 Disable */ +#define PMC_PCDR1_PID58 (0x1u << 26) /**< \brief (PMC_PCDR1) Peripheral Clock 58 Disable */ +#define PMC_PCDR1_PID59 (0x1u << 27) /**< \brief (PMC_PCDR1) Peripheral Clock 59 Disable */ +#define PMC_PCDR1_PID60 (0x1u << 28) /**< \brief (PMC_PCDR1) Peripheral Clock 60 Disable */ +/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */ +#define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */ +#define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */ +#define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */ +#define PMC_PCSR1_PID35 (0x1u << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */ +#define PMC_PCSR1_PID37 (0x1u << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */ +#define PMC_PCSR1_PID39 (0x1u << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */ +#define PMC_PCSR1_PID40 (0x1u << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */ +#define PMC_PCSR1_PID41 (0x1u << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */ +#define PMC_PCSR1_PID42 (0x1u << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */ +#define PMC_PCSR1_PID43 (0x1u << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */ +#define PMC_PCSR1_PID44 (0x1u << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */ +#define PMC_PCSR1_PID45 (0x1u << 13) /**< \brief (PMC_PCSR1) Peripheral Clock 45 Status */ +#define PMC_PCSR1_PID46 (0x1u << 14) /**< \brief (PMC_PCSR1) Peripheral Clock 46 Status */ +#define PMC_PCSR1_PID47 (0x1u << 15) /**< \brief (PMC_PCSR1) Peripheral Clock 47 Status */ +#define PMC_PCSR1_PID48 (0x1u << 16) /**< \brief (PMC_PCSR1) Peripheral Clock 48 Status */ +#define PMC_PCSR1_PID49 (0x1u << 17) /**< \brief (PMC_PCSR1) Peripheral Clock 49 Status */ +#define PMC_PCSR1_PID50 (0x1u << 18) /**< \brief (PMC_PCSR1) Peripheral Clock 50 Status */ +#define PMC_PCSR1_PID51 (0x1u << 19) /**< \brief (PMC_PCSR1) Peripheral Clock 51 Status */ +#define PMC_PCSR1_PID52 (0x1u << 20) /**< \brief (PMC_PCSR1) Peripheral Clock 52 Status */ +#define PMC_PCSR1_PID53 (0x1u << 21) /**< \brief (PMC_PCSR1) Peripheral Clock 53 Status */ +#define PMC_PCSR1_PID56 (0x1u << 24) /**< \brief (PMC_PCSR1) Peripheral Clock 56 Status */ +#define PMC_PCSR1_PID57 (0x1u << 25) /**< \brief (PMC_PCSR1) Peripheral Clock 57 Status */ +#define PMC_PCSR1_PID58 (0x1u << 26) /**< \brief (PMC_PCSR1) Peripheral Clock 58 Status */ +#define PMC_PCSR1_PID59 (0x1u << 27) /**< \brief (PMC_PCSR1) Peripheral Clock 59 Status */ +#define PMC_PCSR1_PID60 (0x1u << 28) /**< \brief (PMC_PCSR1) Peripheral Clock 60 Status */ +/* -------- PMC_PCR : (PMC Offset: 0x010C) Peripheral Control Register -------- */ +#define PMC_PCR_PID_Pos 0 +#define PMC_PCR_PID_Msk (0x7fu << PMC_PCR_PID_Pos) /**< \brief (PMC_PCR) Peripheral ID */ +#define PMC_PCR_PID(value) ((PMC_PCR_PID_Msk & ((value) << PMC_PCR_PID_Pos))) +#define PMC_PCR_GCLKCSS_Pos 8 +#define PMC_PCR_GCLKCSS_Msk (0x7u << PMC_PCR_GCLKCSS_Pos) /**< \brief (PMC_PCR) Generic Clock Source Selection */ +#define PMC_PCR_GCLKCSS(value) ((PMC_PCR_GCLKCSS_Msk & ((value) << PMC_PCR_GCLKCSS_Pos))) +#define PMC_PCR_GCLKCSS_SLOW_CLK (0x0u << 8) /**< \brief (PMC_PCR) Slow clock is selected */ +#define PMC_PCR_GCLKCSS_MAIN_CLK (0x1u << 8) /**< \brief (PMC_PCR) Main clock is selected */ +#define PMC_PCR_GCLKCSS_PLLA_CLK (0x2u << 8) /**< \brief (PMC_PCR) PLLACK is selected */ +#define PMC_PCR_GCLKCSS_UPLL_CLK (0x3u << 8) /**< \brief (PMC_PCR) UPLL Clock is selected */ +#define PMC_PCR_GCLKCSS_MCK_CLK (0x4u << 8) /**< \brief (PMC_PCR) Master Clock is selected */ +#define PMC_PCR_CMD (0x1u << 12) /**< \brief (PMC_PCR) Command */ +#define PMC_PCR_DIV_Pos 16 +#define PMC_PCR_DIV_Msk (0x3u << PMC_PCR_DIV_Pos) /**< \brief (PMC_PCR) Divisor Value */ +#define PMC_PCR_DIV(value) ((PMC_PCR_DIV_Msk & ((value) << PMC_PCR_DIV_Pos))) +#define PMC_PCR_DIV_PERIPH_DIV_MCK (0x0u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK */ +#define PMC_PCR_DIV_PERIPH_DIV2_MCK (0x1u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/2 */ +#define PMC_PCR_DIV_PERIPH_DIV4_MCK (0x2u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/4 */ +#define PMC_PCR_DIV_PERIPH_DIV8_MCK (0x3u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/8 */ +#define PMC_PCR_GCLKDIV_Pos 20 +#define PMC_PCR_GCLKDIV_Msk (0xffu << PMC_PCR_GCLKDIV_Pos) /**< \brief (PMC_PCR) Generic Clock Division Ratio */ +#define PMC_PCR_GCLKDIV(value) ((PMC_PCR_GCLKDIV_Msk & ((value) << PMC_PCR_GCLKDIV_Pos))) +#define PMC_PCR_EN (0x1u << 28) /**< \brief (PMC_PCR) Enable */ +#define PMC_PCR_GCLKEN (0x1u << 29) /**< \brief (PMC_PCR) Generic Clock Enable */ +/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */ +#define PMC_OCR_CAL4_Pos 0 +#define PMC_OCR_CAL4_Msk (0x7fu << PMC_OCR_CAL4_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 MHz */ +#define PMC_OCR_CAL4(value) ((PMC_OCR_CAL4_Msk & ((value) << PMC_OCR_CAL4_Pos))) +#define PMC_OCR_SEL4 (0x1u << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 MHz */ +#define PMC_OCR_CAL8_Pos 8 +#define PMC_OCR_CAL8_Msk (0x7fu << PMC_OCR_CAL8_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 MHz */ +#define PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos))) +#define PMC_OCR_SEL8 (0x1u << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 MHz */ +#define PMC_OCR_CAL12_Pos 16 +#define PMC_OCR_CAL12_Msk (0x7fu << PMC_OCR_CAL12_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 MHz */ +#define PMC_OCR_CAL12(value) ((PMC_OCR_CAL12_Msk & ((value) << PMC_OCR_CAL12_Pos))) +#define PMC_OCR_SEL12 (0x1u << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 MHz */ +/* -------- PMC_SLPWK_ER0 : (PMC Offset: 0x0114) SleepWalking Enable Register 0 -------- */ +#define PMC_SLPWK_ER0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_ER0) Peripheral 7 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_ER0) Peripheral 8 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_ER0) Peripheral 9 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_ER0) Peripheral 10 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_ER0) Peripheral 11 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_ER0) Peripheral 12 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_ER0) Peripheral 13 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_ER0) Peripheral 14 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_ER0) Peripheral 15 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_ER0) Peripheral 16 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_ER0) Peripheral 17 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_ER0) Peripheral 18 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_ER0) Peripheral 19 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_ER0) Peripheral 20 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_ER0) Peripheral 21 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_ER0) Peripheral 22 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_ER0) Peripheral 23 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_ER0) Peripheral 24 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_ER0) Peripheral 25 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_ER0) Peripheral 26 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_ER0) Peripheral 27 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_ER0) Peripheral 28 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_ER0) Peripheral 29 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_ER0) Peripheral 30 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_ER0) Peripheral 31 SleepWalking Enable */ +/* -------- PMC_SLPWK_DR0 : (PMC Offset: 0x0118) SleepWalking Disable Register 0 -------- */ +#define PMC_SLPWK_DR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_DR0) Peripheral 7 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_DR0) Peripheral 8 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_DR0) Peripheral 9 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_DR0) Peripheral 10 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_DR0) Peripheral 11 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_DR0) Peripheral 12 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_DR0) Peripheral 13 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_DR0) Peripheral 14 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_DR0) Peripheral 15 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_DR0) Peripheral 16 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_DR0) Peripheral 17 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_DR0) Peripheral 18 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_DR0) Peripheral 19 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_DR0) Peripheral 20 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_DR0) Peripheral 21 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_DR0) Peripheral 22 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_DR0) Peripheral 23 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_DR0) Peripheral 24 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_DR0) Peripheral 25 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_DR0) Peripheral 26 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_DR0) Peripheral 27 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_DR0) Peripheral 28 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_DR0) Peripheral 29 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_DR0) Peripheral 30 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_DR0) Peripheral 31 SleepWalking Disable */ +/* -------- PMC_SLPWK_SR0 : (PMC Offset: 0x011C) SleepWalking Status Register 0 -------- */ +#define PMC_SLPWK_SR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_SR0) Peripheral 7 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_SR0) Peripheral 8 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_SR0) Peripheral 9 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_SR0) Peripheral 10 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_SR0) Peripheral 11 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_SR0) Peripheral 12 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_SR0) Peripheral 13 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_SR0) Peripheral 14 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_SR0) Peripheral 15 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_SR0) Peripheral 16 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_SR0) Peripheral 17 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_SR0) Peripheral 18 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_SR0) Peripheral 19 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_SR0) Peripheral 20 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_SR0) Peripheral 21 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_SR0) Peripheral 22 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_SR0) Peripheral 23 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_SR0) Peripheral 24 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_SR0) Peripheral 25 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_SR0) Peripheral 26 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_SR0) Peripheral 27 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_SR0) Peripheral 28 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_SR0) Peripheral 29 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_SR0) Peripheral 30 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_SR0) Peripheral 31 SleepWalking Status */ +/* -------- PMC_SLPWK_ASR0 : (PMC Offset: 0x0120) SleepWalking Activity Status Register 0 -------- */ +#define PMC_SLPWK_ASR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_ASR0) Peripheral 7 Activity Status */ +#define PMC_SLPWK_ASR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_ASR0) Peripheral 8 Activity Status */ +#define PMC_SLPWK_ASR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_ASR0) Peripheral 9 Activity Status */ +#define PMC_SLPWK_ASR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_ASR0) Peripheral 10 Activity Status */ +#define PMC_SLPWK_ASR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_ASR0) Peripheral 11 Activity Status */ +#define PMC_SLPWK_ASR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_ASR0) Peripheral 12 Activity Status */ +#define PMC_SLPWK_ASR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_ASR0) Peripheral 13 Activity Status */ +#define PMC_SLPWK_ASR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_ASR0) Peripheral 14 Activity Status */ +#define PMC_SLPWK_ASR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_ASR0) Peripheral 15 Activity Status */ +#define PMC_SLPWK_ASR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_ASR0) Peripheral 16 Activity Status */ +#define PMC_SLPWK_ASR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_ASR0) Peripheral 17 Activity Status */ +#define PMC_SLPWK_ASR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_ASR0) Peripheral 18 Activity Status */ +#define PMC_SLPWK_ASR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_ASR0) Peripheral 19 Activity Status */ +#define PMC_SLPWK_ASR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_ASR0) Peripheral 20 Activity Status */ +#define PMC_SLPWK_ASR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_ASR0) Peripheral 21 Activity Status */ +#define PMC_SLPWK_ASR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_ASR0) Peripheral 22 Activity Status */ +#define PMC_SLPWK_ASR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_ASR0) Peripheral 23 Activity Status */ +#define PMC_SLPWK_ASR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_ASR0) Peripheral 24 Activity Status */ +#define PMC_SLPWK_ASR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_ASR0) Peripheral 25 Activity Status */ +#define PMC_SLPWK_ASR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_ASR0) Peripheral 26 Activity Status */ +#define PMC_SLPWK_ASR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_ASR0) Peripheral 27 Activity Status */ +#define PMC_SLPWK_ASR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_ASR0) Peripheral 28 Activity Status */ +#define PMC_SLPWK_ASR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_ASR0) Peripheral 29 Activity Status */ +#define PMC_SLPWK_ASR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_ASR0) Peripheral 30 Activity Status */ +#define PMC_SLPWK_ASR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_ASR0) Peripheral 31 Activity Status */ +/* -------- PMC_PMMR : (PMC Offset: 0x0130) PLL Maximum Multiplier Value Register -------- */ +#define PMC_PMMR_PLLA_MMAX_Pos 0 +#define PMC_PMMR_PLLA_MMAX_Msk (0x7ffu << PMC_PMMR_PLLA_MMAX_Pos) /**< \brief (PMC_PMMR) PLLA Maximum Allowed Multiplier Value */ +#define PMC_PMMR_PLLA_MMAX(value) ((PMC_PMMR_PLLA_MMAX_Msk & ((value) << PMC_PMMR_PLLA_MMAX_Pos))) +/* -------- PMC_SLPWK_ER1 : (PMC Offset: 0x0134) SleepWalking Enable Register 1 -------- */ +#define PMC_SLPWK_ER1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_ER1) Peripheral 32 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_ER1) Peripheral 33 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_ER1) Peripheral 34 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_ER1) Peripheral 35 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_ER1) Peripheral 37 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_ER1) Peripheral 39 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_ER1) Peripheral 40 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_ER1) Peripheral 41 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_ER1) Peripheral 42 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_ER1) Peripheral 43 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_ER1) Peripheral 44 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_ER1) Peripheral 45 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_ER1) Peripheral 46 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_ER1) Peripheral 47 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_ER1) Peripheral 48 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_ER1) Peripheral 49 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_ER1) Peripheral 50 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_ER1) Peripheral 51 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_ER1) Peripheral 52 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_ER1) Peripheral 53 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_ER1) Peripheral 56 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_ER1) Peripheral 57 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_ER1) Peripheral 58 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_ER1) Peripheral 59 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_ER1) Peripheral 60 SleepWalking Enable */ +/* -------- PMC_SLPWK_DR1 : (PMC Offset: 0x0138) SleepWalking Disable Register 1 -------- */ +#define PMC_SLPWK_DR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_DR1) Peripheral 32 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_DR1) Peripheral 33 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_DR1) Peripheral 34 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_DR1) Peripheral 35 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_DR1) Peripheral 37 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_DR1) Peripheral 39 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_DR1) Peripheral 40 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_DR1) Peripheral 41 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_DR1) Peripheral 42 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_DR1) Peripheral 43 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_DR1) Peripheral 44 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_DR1) Peripheral 45 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_DR1) Peripheral 46 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_DR1) Peripheral 47 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_DR1) Peripheral 48 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_DR1) Peripheral 49 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_DR1) Peripheral 50 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_DR1) Peripheral 51 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_DR1) Peripheral 52 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_DR1) Peripheral 53 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_DR1) Peripheral 56 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_DR1) Peripheral 57 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_DR1) Peripheral 58 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_DR1) Peripheral 59 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_DR1) Peripheral 60 SleepWalking Disable */ +/* -------- PMC_SLPWK_SR1 : (PMC Offset: 0x013C) SleepWalking Status Register 1 -------- */ +#define PMC_SLPWK_SR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_SR1) Peripheral 32 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_SR1) Peripheral 33 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_SR1) Peripheral 34 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_SR1) Peripheral 35 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_SR1) Peripheral 37 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_SR1) Peripheral 39 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_SR1) Peripheral 40 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_SR1) Peripheral 41 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_SR1) Peripheral 42 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_SR1) Peripheral 43 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_SR1) Peripheral 44 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_SR1) Peripheral 45 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_SR1) Peripheral 46 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_SR1) Peripheral 47 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_SR1) Peripheral 48 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_SR1) Peripheral 49 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_SR1) Peripheral 50 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_SR1) Peripheral 51 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_SR1) Peripheral 52 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_SR1) Peripheral 53 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_SR1) Peripheral 56 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_SR1) Peripheral 57 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_SR1) Peripheral 58 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_SR1) Peripheral 59 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_SR1) Peripheral 60 SleepWalking Status */ +/* -------- PMC_SLPWK_ASR1 : (PMC Offset: 0x0140) SleepWalking Activity Status Register 1 -------- */ +#define PMC_SLPWK_ASR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_ASR1) Peripheral 32 Activity Status */ +#define PMC_SLPWK_ASR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_ASR1) Peripheral 33 Activity Status */ +#define PMC_SLPWK_ASR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_ASR1) Peripheral 34 Activity Status */ +#define PMC_SLPWK_ASR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_ASR1) Peripheral 35 Activity Status */ +#define PMC_SLPWK_ASR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_ASR1) Peripheral 37 Activity Status */ +#define PMC_SLPWK_ASR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_ASR1) Peripheral 39 Activity Status */ +#define PMC_SLPWK_ASR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_ASR1) Peripheral 40 Activity Status */ +#define PMC_SLPWK_ASR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_ASR1) Peripheral 41 Activity Status */ +#define PMC_SLPWK_ASR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_ASR1) Peripheral 42 Activity Status */ +#define PMC_SLPWK_ASR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_ASR1) Peripheral 43 Activity Status */ +#define PMC_SLPWK_ASR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_ASR1) Peripheral 44 Activity Status */ +#define PMC_SLPWK_ASR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_ASR1) Peripheral 45 Activity Status */ +#define PMC_SLPWK_ASR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_ASR1) Peripheral 46 Activity Status */ +#define PMC_SLPWK_ASR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_ASR1) Peripheral 47 Activity Status */ +#define PMC_SLPWK_ASR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_ASR1) Peripheral 48 Activity Status */ +#define PMC_SLPWK_ASR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_ASR1) Peripheral 49 Activity Status */ +#define PMC_SLPWK_ASR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_ASR1) Peripheral 50 Activity Status */ +#define PMC_SLPWK_ASR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_ASR1) Peripheral 51 Activity Status */ +#define PMC_SLPWK_ASR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_ASR1) Peripheral 52 Activity Status */ +#define PMC_SLPWK_ASR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_ASR1) Peripheral 53 Activity Status */ +#define PMC_SLPWK_ASR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_ASR1) Peripheral 56 Activity Status */ +#define PMC_SLPWK_ASR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_ASR1) Peripheral 57 Activity Status */ +#define PMC_SLPWK_ASR1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_ASR1) Peripheral 58 Activity Status */ +#define PMC_SLPWK_ASR1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_ASR1) Peripheral 59 Activity Status */ +#define PMC_SLPWK_ASR1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_ASR1) Peripheral 60 Activity Status */ +/* -------- PMC_SLPWK_AIPR : (PMC Offset: 0x0144) SleepWalking Activity In Progress Register -------- */ +#define PMC_SLPWK_AIPR_AIP (0x1u << 0) /**< \brief (PMC_SLPWK_AIPR) Activity In Progress */ +/* -------- PMC_APLLACR : (PMC Offset: 0x0158) Audio PLL Analog Configuration Register -------- */ +#define PMC_APLLACR_DCOFLTSEL_Pos 0 +#define PMC_APLLACR_DCOFLTSEL_Msk (0xfu << PMC_APLLACR_DCOFLTSEL_Pos) /**< \brief (PMC_APLLACR) DCO Filter Selection */ +#define PMC_APLLACR_DCOFLTSEL(value) ((PMC_APLLACR_DCOFLTSEL_Msk & ((value) << PMC_APLLACR_DCOFLTSEL_Pos))) +#define PMC_APLLACR_FLTSEL_Pos 4 +#define PMC_APLLACR_FLTSEL_Msk (0xfu << PMC_APLLACR_FLTSEL_Pos) /**< \brief (PMC_APLLACR) PLL Filter Selection */ +#define PMC_APLLACR_FLTSEL(value) ((PMC_APLLACR_FLTSEL_Msk & ((value) << PMC_APLLACR_FLTSEL_Pos))) +#define PMC_APLLACR_BIAS_Pos 8 +#define PMC_APLLACR_BIAS_Msk (0x3u << PMC_APLLACR_BIAS_Pos) /**< \brief (PMC_APLLACR) Bias Voltage Selection */ +#define PMC_APLLACR_BIAS(value) ((PMC_APLLACR_BIAS_Msk & ((value) << PMC_APLLACR_BIAS_Pos))) +/* -------- PMC_WMST : (PMC Offset: 0x015C) Wait Mode Startup Time Register -------- */ +#define PMC_WMST_WMST_Pos 0 +#define PMC_WMST_WMST_Msk (0xffu << PMC_WMST_WMST_Pos) /**< \brief (PMC_WMST) Wait Mode Startup Time */ +#define PMC_WMST_WMST(value) ((PMC_WMST_WMST_Msk & ((value) << PMC_WMST_WMST_Pos))) +#define PMC_WMST_KEY_Pos 24 +#define PMC_WMST_KEY_Msk (0xffu << PMC_WMST_KEY_Pos) /**< \brief (PMC_WMST) Write Access Password */ +#define PMC_WMST_KEY(value) ((PMC_WMST_KEY_Msk & ((value) << PMC_WMST_KEY_Pos))) +#define PMC_WMST_KEY_PASSWD (0x5Au << 24) /**< \brief (PMC_WMST) Writing any other value in this field aborts the write operation.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAME70_PMC_COMPONENT_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/pwm.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/pwm.h new file mode 100644 index 000000000..f9dbdcd2b --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/pwm.h @@ -0,0 +1,656 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_PWM_COMPONENT_ +#define _SAME70_PWM_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_PWM Pulse Width Modulation Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief PwmCh_num hardware registers */ +typedef struct { + __IO uint32_t PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */ + __IO uint32_t PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */ + __O uint32_t PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */ + __IO uint32_t PWM_CPRD; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */ + __O uint32_t PWM_CPRDUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */ + __I uint32_t PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */ + __IO uint32_t PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */ + __O uint32_t PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */ +} PwmCh_num; +/** \brief PwmCmp hardware registers */ +typedef struct { + __IO uint32_t PWM_CMPV; /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */ + __O uint32_t PWM_CMPVUPD; /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */ + __IO uint32_t PWM_CMPM; /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */ + __O uint32_t PWM_CMPMUPD; /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */ +} PwmCmp; +/** \brief Pwm hardware registers */ +#define PWMCMP_NUMBER 8 +#define PWMCH_NUM_NUMBER 4 +typedef struct { + __IO uint32_t PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */ + __O uint32_t PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */ + __O uint32_t PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */ + __I uint32_t PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */ + __O uint32_t PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */ + __O uint32_t PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */ + __I uint32_t PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */ + __I uint32_t PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */ + __IO uint32_t PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */ + __O uint32_t PWM_DMAR; /**< \brief (Pwm Offset: 0x24) PWM DMA Register */ + __IO uint32_t PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */ + __IO uint32_t PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */ + __O uint32_t PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */ + __O uint32_t PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */ + __O uint32_t PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */ + __I uint32_t PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */ + __I uint32_t PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */ + __IO uint32_t PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */ + __IO uint32_t PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */ + __O uint32_t PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */ + __O uint32_t PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */ + __O uint32_t PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */ + __O uint32_t PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */ + __IO uint32_t PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */ + __I uint32_t PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */ + __O uint32_t PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */ + __IO uint32_t PWM_FPV1; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register 1 */ + __IO uint32_t PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */ + __I uint32_t Reserved1[3]; + __IO uint32_t PWM_ELMR[8]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t PWM_SSPR; /**< \brief (Pwm Offset: 0xA0) PWM Spread Spectrum Register */ + __O uint32_t PWM_SSPUP; /**< \brief (Pwm Offset: 0xA4) PWM Spread Spectrum Update Register */ + __I uint32_t Reserved3[2]; + __IO uint32_t PWM_SMMR; /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */ + __I uint32_t Reserved4[3]; + __IO uint32_t PWM_FPV2; /**< \brief (Pwm Offset: 0xC0) PWM Fault Protection Value 2 Register */ + __I uint32_t Reserved5[8]; + __O uint32_t PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protection Control Register */ + __I uint32_t PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protection Status Register */ + __I uint32_t Reserved6[4]; + __I uint32_t PWM_VERSION; /**< \brief (Pwm Offset: 0xFC) Version Register */ + __I uint32_t Reserved7[12]; + PwmCmp PWM_CMP[PWMCMP_NUMBER]; /**< \brief (Pwm Offset: 0x130) 0 .. 7 */ + __I uint32_t Reserved8[20]; + PwmCh_num PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */ + __I uint32_t Reserved9[96]; + __O uint32_t PWM_CMUPD0; /**< \brief (Pwm Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) */ + __I uint32_t Reserved10[7]; + __O uint32_t PWM_CMUPD1; /**< \brief (Pwm Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) */ + __I uint32_t Reserved11[2]; + __IO uint32_t PWM_ETRG1; /**< \brief (Pwm Offset: 0x42C) PWM External Trigger Register (trg_num = 1) */ + __IO uint32_t PWM_LEBR1; /**< \brief (Pwm Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1) */ + __I uint32_t Reserved12[3]; + __O uint32_t PWM_CMUPD2; /**< \brief (Pwm Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) */ + __I uint32_t Reserved13[2]; + __IO uint32_t PWM_ETRG2; /**< \brief (Pwm Offset: 0x44C) PWM External Trigger Register (trg_num = 2) */ + __IO uint32_t PWM_LEBR2; /**< \brief (Pwm Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2) */ + __I uint32_t Reserved14[3]; + __O uint32_t PWM_CMUPD3; /**< \brief (Pwm Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) */ +} Pwm; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */ +#define PWM_CLK_DIVA_Pos 0 +#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA Divide Factor */ +#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos))) +#define PWM_CLK_DIVA_CLKA_POFF (0x0u << 0) /**< \brief (PWM_CLK) CLKA clock is turned off */ +#define PWM_CLK_DIVA_PREA (0x1u << 0) /**< \brief (PWM_CLK) CLKA clock is clock selected by PREA */ +#define PWM_CLK_PREA_Pos 8 +#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA Source Clock Selection */ +#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos))) +#define PWM_CLK_PREA_CLK (0x0u << 8) /**< \brief (PWM_CLK) Peripheral clock */ +#define PWM_CLK_PREA_CLK_DIV2 (0x1u << 8) /**< \brief (PWM_CLK) Peripheral clock/2 */ +#define PWM_CLK_PREA_CLK_DIV4 (0x2u << 8) /**< \brief (PWM_CLK) Peripheral clock/4 */ +#define PWM_CLK_PREA_CLK_DIV8 (0x3u << 8) /**< \brief (PWM_CLK) Peripheral clock/8 */ +#define PWM_CLK_PREA_CLK_DIV16 (0x4u << 8) /**< \brief (PWM_CLK) Peripheral clock/16 */ +#define PWM_CLK_PREA_CLK_DIV32 (0x5u << 8) /**< \brief (PWM_CLK) Peripheral clock/32 */ +#define PWM_CLK_PREA_CLK_DIV64 (0x6u << 8) /**< \brief (PWM_CLK) Peripheral clock/64 */ +#define PWM_CLK_PREA_CLK_DIV128 (0x7u << 8) /**< \brief (PWM_CLK) Peripheral clock/128 */ +#define PWM_CLK_PREA_CLK_DIV256 (0x8u << 8) /**< \brief (PWM_CLK) Peripheral clock/256 */ +#define PWM_CLK_PREA_CLK_DIV512 (0x9u << 8) /**< \brief (PWM_CLK) Peripheral clock/512 */ +#define PWM_CLK_PREA_CLK_DIV1024 (0xAu << 8) /**< \brief (PWM_CLK) Peripheral clock/1024 */ +#define PWM_CLK_DIVB_Pos 16 +#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKB Divide Factor */ +#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos))) +#define PWM_CLK_DIVB_CLKB_POFF (0x0u << 16) /**< \brief (PWM_CLK) CLKB clock is turned off */ +#define PWM_CLK_DIVB_PREB (0x1u << 16) /**< \brief (PWM_CLK) CLKB clock is clock selected by PREB */ +#define PWM_CLK_PREB_Pos 24 +#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKB Source Clock Selection */ +#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos))) +#define PWM_CLK_PREB_CLK (0x0u << 24) /**< \brief (PWM_CLK) Peripheral clock */ +#define PWM_CLK_PREB_CLK_DIV2 (0x1u << 24) /**< \brief (PWM_CLK) Peripheral clock/2 */ +#define PWM_CLK_PREB_CLK_DIV4 (0x2u << 24) /**< \brief (PWM_CLK) Peripheral clock/4 */ +#define PWM_CLK_PREB_CLK_DIV8 (0x3u << 24) /**< \brief (PWM_CLK) Peripheral clock/8 */ +#define PWM_CLK_PREB_CLK_DIV16 (0x4u << 24) /**< \brief (PWM_CLK) Peripheral clock/16 */ +#define PWM_CLK_PREB_CLK_DIV32 (0x5u << 24) /**< \brief (PWM_CLK) Peripheral clock/32 */ +#define PWM_CLK_PREB_CLK_DIV64 (0x6u << 24) /**< \brief (PWM_CLK) Peripheral clock/64 */ +#define PWM_CLK_PREB_CLK_DIV128 (0x7u << 24) /**< \brief (PWM_CLK) Peripheral clock/128 */ +#define PWM_CLK_PREB_CLK_DIV256 (0x8u << 24) /**< \brief (PWM_CLK) Peripheral clock/256 */ +#define PWM_CLK_PREB_CLK_DIV512 (0x9u << 24) /**< \brief (PWM_CLK) Peripheral clock/512 */ +#define PWM_CLK_PREB_CLK_DIV1024 (0xAu << 24) /**< \brief (PWM_CLK) Peripheral clock/1024 */ +/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */ +#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */ +/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */ +#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */ +/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */ +#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */ +/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */ +#define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */ +#define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */ +#define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */ +#define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */ +#define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */ +#define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */ +#define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */ +#define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */ +/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */ +#define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */ +#define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */ +#define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */ +#define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */ +#define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */ +#define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */ +#define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */ +#define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */ +/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */ +#define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */ +#define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */ +#define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */ +#define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */ +#define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */ +#define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */ +#define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */ +#define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */ +/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */ +#define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */ +#define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */ +#define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */ +#define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */ +#define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */ +#define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */ +#define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */ +#define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */ +/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */ +#define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */ +#define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */ +#define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */ +#define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */ +#define PWM_SCM_UPDM_Pos 16 +#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */ +#define PWM_SCM_UPDM(value) ((PWM_SCM_UPDM_Msk & ((value) << PWM_SCM_UPDM_Pos))) +#define PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */ +#define PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */ +#define PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the DMA and automatic update of synchronous channels */ +#define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) DMA Transfer Request Mode */ +#define PWM_SCM_PTRCS_Pos 21 +#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) DMA Transfer Request Comparison Selection */ +#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos))) +/* -------- PWM_DMAR : (PWM Offset: 0x24) PWM DMA Register -------- */ +#define PWM_DMAR_DMADUTY_Pos 0 +#define PWM_DMAR_DMADUTY_Msk (0xffffffu << PWM_DMAR_DMADUTY_Pos) /**< \brief (PWM_DMAR) Duty-Cycle Holding Register for DMA Access */ +#define PWM_DMAR_DMADUTY(value) ((PWM_DMAR_DMADUTY_Msk & ((value) << PWM_DMAR_DMADUTY_Pos))) +/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */ +#define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */ +/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */ +#define PWM_SCUP_UPR_Pos 0 +#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */ +#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos))) +#define PWM_SCUP_UPRCNT_Pos 4 +#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */ +#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos))) +/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */ +#define PWM_SCUPUPD_UPRUPD_Pos 0 +#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */ +#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos))) +/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */ +#define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */ +#define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */ +#define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */ +#define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */ +#define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */ +#define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */ +#define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */ +#define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */ +#define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */ +#define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */ +#define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */ +#define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */ +#define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */ +#define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */ +#define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */ +#define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */ +#define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */ +#define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */ +/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */ +#define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */ +#define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */ +#define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */ +#define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */ +#define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */ +#define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */ +#define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */ +#define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */ +#define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */ +#define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */ +#define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */ +#define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */ +#define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */ +#define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */ +#define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */ +#define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */ +#define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */ +#define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */ +/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */ +#define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */ +#define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */ +#define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */ +#define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */ +#define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */ +#define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */ +#define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */ +#define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */ +#define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */ +#define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */ +#define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */ +#define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */ +#define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */ +#define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */ +#define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */ +#define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */ +#define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */ +#define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */ +/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */ +#define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */ +#define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */ +#define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */ +#define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */ +#define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */ +#define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */ +#define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */ +#define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */ +#define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */ +#define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */ +#define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */ +#define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */ +#define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */ +#define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */ +#define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */ +#define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */ +#define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */ +#define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */ +/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */ +#define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */ +#define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */ +#define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */ +#define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */ +#define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */ +#define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */ +#define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */ +#define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */ +/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */ +#define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */ +#define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */ +#define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */ +#define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */ +#define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */ +#define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */ +#define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */ +#define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */ +/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */ +#define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */ +#define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */ +#define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */ +#define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */ +#define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */ +#define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */ +#define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */ +#define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */ +/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */ +#define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */ +#define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */ +#define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */ +#define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */ +#define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */ +#define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */ +#define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */ +#define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */ +/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */ +#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */ +#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */ +#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */ +#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */ +#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */ +#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */ +#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */ +#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */ +/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */ +#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */ +#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */ +#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */ +#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */ +#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */ +#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */ +#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */ +#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */ +/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */ +#define PWM_FMR_FPOL_Pos 0 +#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity */ +#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos))) +#define PWM_FMR_FMOD_Pos 8 +#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode */ +#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos))) +#define PWM_FMR_FFIL_Pos 16 +#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering */ +#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos))) +/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */ +#define PWM_FSR_FIV_Pos 0 +#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value */ +#define PWM_FSR_FS_Pos 8 +#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status */ +/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */ +#define PWM_FCR_FCLR_Pos 0 +#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear */ +#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos))) +/* -------- PWM_FPV1 : (PWM Offset: 0x68) PWM Fault Protection Value Register 1 -------- */ +#define PWM_FPV1_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 0 */ +#define PWM_FPV1_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 1 */ +#define PWM_FPV1_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 2 */ +#define PWM_FPV1_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 3 */ +#define PWM_FPV1_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 0 */ +#define PWM_FPV1_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 1 */ +#define PWM_FPV1_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 2 */ +#define PWM_FPV1_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 3 */ +/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */ +#define PWM_FPE_FPE0_Pos 0 +#define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 0 */ +#define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos))) +#define PWM_FPE_FPE1_Pos 8 +#define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 1 */ +#define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos))) +#define PWM_FPE_FPE2_Pos 16 +#define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 2 */ +#define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos))) +#define PWM_FPE_FPE3_Pos 24 +#define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 3 */ +#define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos))) +/* -------- PWM_ELMR[8] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */ +#define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[8]) Comparison 0 Selection */ +#define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[8]) Comparison 1 Selection */ +#define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[8]) Comparison 2 Selection */ +#define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[8]) Comparison 3 Selection */ +#define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[8]) Comparison 4 Selection */ +#define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[8]) Comparison 5 Selection */ +#define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[8]) Comparison 6 Selection */ +#define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[8]) Comparison 7 Selection */ +/* -------- PWM_SSPR : (PWM Offset: 0xA0) PWM Spread Spectrum Register -------- */ +#define PWM_SSPR_SPRD_Pos 0 +#define PWM_SSPR_SPRD_Msk (0xffffffu << PWM_SSPR_SPRD_Pos) /**< \brief (PWM_SSPR) Spread Spectrum Limit Value */ +#define PWM_SSPR_SPRD(value) ((PWM_SSPR_SPRD_Msk & ((value) << PWM_SSPR_SPRD_Pos))) +#define PWM_SSPR_SPRDM (0x1u << 24) /**< \brief (PWM_SSPR) Spread Spectrum Counter Mode */ +/* -------- PWM_SSPUP : (PWM Offset: 0xA4) PWM Spread Spectrum Update Register -------- */ +#define PWM_SSPUP_SPRDUP_Pos 0 +#define PWM_SSPUP_SPRDUP_Msk (0xffffffu << PWM_SSPUP_SPRDUP_Pos) /**< \brief (PWM_SSPUP) Spread Spectrum Limit Value Update */ +#define PWM_SSPUP_SPRDUP(value) ((PWM_SSPUP_SPRDUP_Msk & ((value) << PWM_SSPUP_SPRDUP_Pos))) +/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */ +#define PWM_SMMR_GCEN0 (0x1u << 0) /**< \brief (PWM_SMMR) Gray Count ENable */ +#define PWM_SMMR_GCEN1 (0x1u << 1) /**< \brief (PWM_SMMR) Gray Count ENable */ +#define PWM_SMMR_DOWN0 (0x1u << 16) /**< \brief (PWM_SMMR) DOWN Count */ +#define PWM_SMMR_DOWN1 (0x1u << 17) /**< \brief (PWM_SMMR) DOWN Count */ +/* -------- PWM_FPV2 : (PWM Offset: 0xC0) PWM Fault Protection Value 2 Register -------- */ +#define PWM_FPV2_FPZH0 (0x1u << 0) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 0 */ +#define PWM_FPV2_FPZH1 (0x1u << 1) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 1 */ +#define PWM_FPV2_FPZH2 (0x1u << 2) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 2 */ +#define PWM_FPV2_FPZH3 (0x1u << 3) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 3 */ +#define PWM_FPV2_FPZL0 (0x1u << 16) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 0 */ +#define PWM_FPV2_FPZL1 (0x1u << 17) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 1 */ +#define PWM_FPV2_FPZL2 (0x1u << 18) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 2 */ +#define PWM_FPV2_FPZL3 (0x1u << 19) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 3 */ +/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protection Control Register -------- */ +#define PWM_WPCR_WPCMD_Pos 0 +#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protection Command */ +#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos))) +#define PWM_WPCR_WPCMD_DISABLE_SW_PROT (0x0u << 0) /**< \brief (PWM_WPCR) Disables the software write protection of the register groups of which the bit WPRGx is at '1'. */ +#define PWM_WPCR_WPCMD_ENABLE_SW_PROT (0x1u << 0) /**< \brief (PWM_WPCR) Enables the software write protection of the register groups of which the bit WPRGx is at '1'. */ +#define PWM_WPCR_WPCMD_ENABLE_HW_PROT (0x2u << 0) /**< \brief (PWM_WPCR) Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface. */ +#define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protection Register Group 0 */ +#define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protection Register Group 1 */ +#define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protection Register Group 2 */ +#define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protection Register Group 3 */ +#define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protection Register Group 4 */ +#define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protection Register Group 5 */ +#define PWM_WPCR_WPKEY_Pos 8 +#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protection Key */ +#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos))) +#define PWM_WPCR_WPKEY_PASSWD (0x50574Du << 8) /**< \brief (PWM_WPCR) Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0 */ +/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protection Status Register -------- */ +#define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */ +#define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPVSRC_Pos 16 +#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */ +/* -------- PWM_VERSION : (PWM Offset: 0xFC) Version Register -------- */ +#define PWM_VERSION_VERSION_Pos 0 +#define PWM_VERSION_VERSION_Msk (0xfffu << PWM_VERSION_VERSION_Pos) /**< \brief (PWM_VERSION) Version of the Hardware Module */ +#define PWM_VERSION_MFN_Pos 16 +#define PWM_VERSION_MFN_Msk (0x7u << PWM_VERSION_MFN_Pos) /**< \brief (PWM_VERSION) Metal Fix Number */ +/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */ +#define PWM_CMPV_CV_Pos 0 +#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */ +#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos))) +#define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */ +/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */ +#define PWM_CMPVUPD_CVUPD_Pos 0 +#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */ +#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos))) +#define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */ +/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */ +#define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */ +#define PWM_CMPM_CTR_Pos 4 +#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */ +#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos))) +#define PWM_CMPM_CPR_Pos 8 +#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */ +#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos))) +#define PWM_CMPM_CPRCNT_Pos 12 +#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */ +#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos))) +#define PWM_CMPM_CUPR_Pos 16 +#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */ +#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos))) +#define PWM_CMPM_CUPRCNT_Pos 20 +#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */ +#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos))) +/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */ +#define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */ +#define PWM_CMPMUPD_CTRUPD_Pos 4 +#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */ +#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos))) +#define PWM_CMPMUPD_CPRUPD_Pos 8 +#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */ +#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos))) +#define PWM_CMPMUPD_CUPRUPD_Pos 16 +#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */ +#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos))) +/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */ +#define PWM_CMR_CPRE_Pos 0 +#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */ +#define PWM_CMR_CPRE(value) ((PWM_CMR_CPRE_Msk & ((value) << PWM_CMR_CPRE_Pos))) +#define PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Peripheral clock */ +#define PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Peripheral clock/2 */ +#define PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Peripheral clock/4 */ +#define PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Peripheral clock/8 */ +#define PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Peripheral clock/16 */ +#define PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Peripheral clock/32 */ +#define PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Peripheral clock/64 */ +#define PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Peripheral clock/128 */ +#define PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Peripheral clock/256 */ +#define PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Peripheral clock/512 */ +#define PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Peripheral clock/1024 */ +#define PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */ +#define PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */ +#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */ +#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */ +#define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */ +#define PWM_CMR_UPDS (0x1u << 11) /**< \brief (PWM_CMR) Update Selection */ +#define PWM_CMR_DPOLI (0x1u << 12) /**< \brief (PWM_CMR) Disabled Polarity Inverted */ +#define PWM_CMR_TCTS (0x1u << 13) /**< \brief (PWM_CMR) Timer Counter Trigger Selection */ +#define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */ +#define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */ +#define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */ +#define PWM_CMR_PPM (0x1u << 19) /**< \brief (PWM_CMR) Push-Pull Mode */ +/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */ +#define PWM_CDTY_CDTY_Pos 0 +#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */ +#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos))) +/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */ +#define PWM_CDTYUPD_CDTYUPD_Pos 0 +#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */ +#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos))) +/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */ +#define PWM_CPRD_CPRD_Pos 0 +#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */ +#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos))) +/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */ +#define PWM_CPRDUPD_CPRDUPD_Pos 0 +#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */ +#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos))) +/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */ +#define PWM_CCNT_CNT_Pos 0 +#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */ +/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */ +#define PWM_DT_DTH_Pos 0 +#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */ +#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos))) +#define PWM_DT_DTL_Pos 16 +#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */ +#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos))) +/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */ +#define PWM_DTUPD_DTHUPD_Pos 0 +#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */ +#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos))) +#define PWM_DTUPD_DTLUPD_Pos 16 +#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */ +#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos))) +/* -------- PWM_CMUPD0 : (PWM Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) -------- */ +#define PWM_CMUPD0_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD0) Channel Polarity Update */ +#define PWM_CMUPD0_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD0) Channel Polarity Inversion Update */ +/* -------- PWM_CMUPD1 : (PWM Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) -------- */ +#define PWM_CMUPD1_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD1) Channel Polarity Update */ +#define PWM_CMUPD1_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD1) Channel Polarity Inversion Update */ +/* -------- PWM_ETRG1 : (PWM Offset: 0x42C) PWM External Trigger Register (trg_num = 1) -------- */ +#define PWM_ETRG1_MAXCNT_Pos 0 +#define PWM_ETRG1_MAXCNT_Msk (0xffffffu << PWM_ETRG1_MAXCNT_Pos) /**< \brief (PWM_ETRG1) Maximum Counter value */ +#define PWM_ETRG1_MAXCNT(value) ((PWM_ETRG1_MAXCNT_Msk & ((value) << PWM_ETRG1_MAXCNT_Pos))) +#define PWM_ETRG1_TRGMODE_Pos 24 +#define PWM_ETRG1_TRGMODE_Msk (0x3u << PWM_ETRG1_TRGMODE_Pos) /**< \brief (PWM_ETRG1) External Trigger Mode */ +#define PWM_ETRG1_TRGMODE(value) ((PWM_ETRG1_TRGMODE_Msk & ((value) << PWM_ETRG1_TRGMODE_Pos))) +#define PWM_ETRG1_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG1) External trigger is not enabled. */ +#define PWM_ETRG1_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG1) External PWM Reset Mode */ +#define PWM_ETRG1_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG1) External PWM Start Mode */ +#define PWM_ETRG1_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG1) Cycle-by-cycle Duty Mode */ +#define PWM_ETRG1_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG1) Edge Selection */ +#define PWM_ETRG1_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */ +#define PWM_ETRG1_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */ +#define PWM_ETRG1_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG1) Filtered input */ +#define PWM_ETRG1_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG1) Trigger Source */ +#define PWM_ETRG1_RFEN (0x1u << 31) /**< \brief (PWM_ETRG1) Recoverable Fault Enable */ +/* -------- PWM_LEBR1 : (PWM Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1) -------- */ +#define PWM_LEBR1_LEBDELAY_Pos 0 +#define PWM_LEBR1_LEBDELAY_Msk (0x7fu << PWM_LEBR1_LEBDELAY_Pos) /**< \brief (PWM_LEBR1) Leading-Edge Blanking Delay for TRGINx */ +#define PWM_LEBR1_LEBDELAY(value) ((PWM_LEBR1_LEBDELAY_Msk & ((value) << PWM_LEBR1_LEBDELAY_Pos))) +#define PWM_LEBR1_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR1) PWML Falling Edge Enable */ +#define PWM_LEBR1_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR1) PWML Rising Edge Enable */ +#define PWM_LEBR1_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR1) PWMH Falling Edge Enable */ +#define PWM_LEBR1_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR1) PWMH Rising Edge Enable */ +/* -------- PWM_CMUPD2 : (PWM Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) -------- */ +#define PWM_CMUPD2_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD2) Channel Polarity Update */ +#define PWM_CMUPD2_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD2) Channel Polarity Inversion Update */ +/* -------- PWM_ETRG2 : (PWM Offset: 0x44C) PWM External Trigger Register (trg_num = 2) -------- */ +#define PWM_ETRG2_MAXCNT_Pos 0 +#define PWM_ETRG2_MAXCNT_Msk (0xffffffu << PWM_ETRG2_MAXCNT_Pos) /**< \brief (PWM_ETRG2) Maximum Counter value */ +#define PWM_ETRG2_MAXCNT(value) ((PWM_ETRG2_MAXCNT_Msk & ((value) << PWM_ETRG2_MAXCNT_Pos))) +#define PWM_ETRG2_TRGMODE_Pos 24 +#define PWM_ETRG2_TRGMODE_Msk (0x3u << PWM_ETRG2_TRGMODE_Pos) /**< \brief (PWM_ETRG2) External Trigger Mode */ +#define PWM_ETRG2_TRGMODE(value) ((PWM_ETRG2_TRGMODE_Msk & ((value) << PWM_ETRG2_TRGMODE_Pos))) +#define PWM_ETRG2_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG2) External trigger is not enabled. */ +#define PWM_ETRG2_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG2) External PWM Reset Mode */ +#define PWM_ETRG2_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG2) External PWM Start Mode */ +#define PWM_ETRG2_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG2) Cycle-by-cycle Duty Mode */ +#define PWM_ETRG2_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG2) Edge Selection */ +#define PWM_ETRG2_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */ +#define PWM_ETRG2_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */ +#define PWM_ETRG2_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG2) Filtered input */ +#define PWM_ETRG2_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG2) Trigger Source */ +#define PWM_ETRG2_RFEN (0x1u << 31) /**< \brief (PWM_ETRG2) Recoverable Fault Enable */ +/* -------- PWM_LEBR2 : (PWM Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2) -------- */ +#define PWM_LEBR2_LEBDELAY_Pos 0 +#define PWM_LEBR2_LEBDELAY_Msk (0x7fu << PWM_LEBR2_LEBDELAY_Pos) /**< \brief (PWM_LEBR2) Leading-Edge Blanking Delay for TRGINx */ +#define PWM_LEBR2_LEBDELAY(value) ((PWM_LEBR2_LEBDELAY_Msk & ((value) << PWM_LEBR2_LEBDELAY_Pos))) +#define PWM_LEBR2_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR2) PWML Falling Edge Enable */ +#define PWM_LEBR2_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR2) PWML Rising Edge Enable */ +#define PWM_LEBR2_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR2) PWMH Falling Edge Enable */ +#define PWM_LEBR2_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR2) PWMH Rising Edge Enable */ +/* -------- PWM_CMUPD3 : (PWM Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) -------- */ +#define PWM_CMUPD3_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD3) Channel Polarity Update */ +#define PWM_CMUPD3_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD3) Channel Polarity Inversion Update */ + +/*@}*/ + + +#endif /* _SAME70_PWM_COMPONENT_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/qspi.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/qspi.h new file mode 100644 index 000000000..f10534c52 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/qspi.h @@ -0,0 +1,235 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_QSPI_COMPONENT_ +#define _SAME70_QSPI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Quad Serial Peripheral Interface */ +/* ============================================================================= */ +/** \addtogroup SAME70_QSPI Quad Serial Peripheral Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Qspi hardware registers */ +typedef struct { + __O uint32_t QSPI_CR; /**< \brief (Qspi Offset: 0x00) Control Register */ + __IO uint32_t QSPI_MR; /**< \brief (Qspi Offset: 0x04) Mode Register */ + __I uint32_t QSPI_RDR; /**< \brief (Qspi Offset: 0x08) Receive Data Register */ + __O uint32_t QSPI_TDR; /**< \brief (Qspi Offset: 0x0C) Transmit Data Register */ + __I uint32_t QSPI_SR; /**< \brief (Qspi Offset: 0x10) Status Register */ + __O uint32_t QSPI_IER; /**< \brief (Qspi Offset: 0x14) Interrupt Enable Register */ + __O uint32_t QSPI_IDR; /**< \brief (Qspi Offset: 0x18) Interrupt Disable Register */ + __I uint32_t QSPI_IMR; /**< \brief (Qspi Offset: 0x1C) Interrupt Mask Register */ + __IO uint32_t QSPI_SCR; /**< \brief (Qspi Offset: 0x20) Serial Clock Register */ + __I uint32_t Reserved1[3]; + __IO uint32_t QSPI_IAR; /**< \brief (Qspi Offset: 0x30) Instruction Address Register */ + __IO uint32_t QSPI_ICR; /**< \brief (Qspi Offset: 0x34) Instruction Code Register */ + __IO uint32_t QSPI_IFR; /**< \brief (Qspi Offset: 0x38) Instruction Frame Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t QSPI_SMR; /**< \brief (Qspi Offset: 0x40) Scrambling Mode Register */ + __O uint32_t QSPI_SKR; /**< \brief (Qspi Offset: 0x44) Scrambling Key Register */ + __I uint32_t Reserved3[39]; + __IO uint32_t QSPI_WPMR; /**< \brief (Qspi Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t QSPI_WPSR; /**< \brief (Qspi Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved4[4]; + __I uint32_t QSPI_VERSION; /**< \brief (Qspi Offset: 0x00FC) Version Register */ +} Qspi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- QSPI_CR : (QSPI Offset: 0x00) Control Register -------- */ +#define QSPI_CR_QSPIEN (0x1u << 0) /**< \brief (QSPI_CR) QSPI Enable */ +#define QSPI_CR_QSPIDIS (0x1u << 1) /**< \brief (QSPI_CR) QSPI Disable */ +#define QSPI_CR_SWRST (0x1u << 7) /**< \brief (QSPI_CR) QSPI Software Reset */ +#define QSPI_CR_LASTXFER (0x1u << 24) /**< \brief (QSPI_CR) Last Transfer */ +/* -------- QSPI_MR : (QSPI Offset: 0x04) Mode Register -------- */ +#define QSPI_MR_SMM (0x1u << 0) /**< \brief (QSPI_MR) Serial Memory Mode */ +#define QSPI_MR_SMM_SPI (0x0u << 0) /**< \brief (QSPI_MR) The QSPI is in SPI mode. */ +#define QSPI_MR_SMM_MEMORY (0x1u << 0) /**< \brief (QSPI_MR) The QSPI is in Serial Memory mode. */ +#define QSPI_MR_LLB (0x1u << 1) /**< \brief (QSPI_MR) Local Loopback Enable */ +#define QSPI_MR_LLB_DISABLED (0x0u << 1) /**< \brief (QSPI_MR) Local loopback path disabled. */ +#define QSPI_MR_LLB_ENABLED (0x1u << 1) /**< \brief (QSPI_MR) Local loopback path enabled. */ +#define QSPI_MR_WDRBT (0x1u << 2) /**< \brief (QSPI_MR) Wait Data Read Before Transfer */ +#define QSPI_MR_WDRBT_DISABLED (0x0u << 2) /**< \brief (QSPI_MR) No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is. */ +#define QSPI_MR_WDRBT_ENABLED (0x1u << 2) /**< \brief (QSPI_MR) In SPI mode, a transfer can start only if the QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception. */ +#define QSPI_MR_CSMODE_Pos 4 +#define QSPI_MR_CSMODE_Msk (0x3u << QSPI_MR_CSMODE_Pos) /**< \brief (QSPI_MR) Chip Select Mode */ +#define QSPI_MR_CSMODE(value) ((QSPI_MR_CSMODE_Msk & ((value) << QSPI_MR_CSMODE_Pos))) +#define QSPI_MR_CSMODE_NOT_RELOADED (0x0u << 4) /**< \brief (QSPI_MR) The chip select is deasserted if TD has not been reloaded before the end of the current transfer. */ +#define QSPI_MR_CSMODE_LASTXFER (0x1u << 4) /**< \brief (QSPI_MR) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred. */ +#define QSPI_MR_CSMODE_SYSTEMATICALLY (0x2u << 4) /**< \brief (QSPI_MR) The chip select is deasserted systematically after each transfer. */ +#define QSPI_MR_NBBITS_Pos 8 +#define QSPI_MR_NBBITS_Msk (0xfu << QSPI_MR_NBBITS_Pos) /**< \brief (QSPI_MR) Number Of Bits Per Transfer */ +#define QSPI_MR_NBBITS(value) ((QSPI_MR_NBBITS_Msk & ((value) << QSPI_MR_NBBITS_Pos))) +#define QSPI_MR_NBBITS_8_BIT (0x0u << 8) /**< \brief (QSPI_MR) 8 bits for transfer */ +#define QSPI_MR_NBBITS_9_BIT (0x1u << 8) /**< \brief (QSPI_MR) 9 bits for transfer */ +#define QSPI_MR_NBBITS_10_BIT (0x2u << 8) /**< \brief (QSPI_MR) 10 bits for transfer */ +#define QSPI_MR_NBBITS_11_BIT (0x3u << 8) /**< \brief (QSPI_MR) 11 bits for transfer */ +#define QSPI_MR_NBBITS_12_BIT (0x4u << 8) /**< \brief (QSPI_MR) 12 bits for transfer */ +#define QSPI_MR_NBBITS_13_BIT (0x5u << 8) /**< \brief (QSPI_MR) 13 bits for transfer */ +#define QSPI_MR_NBBITS_14_BIT (0x6u << 8) /**< \brief (QSPI_MR) 14 bits for transfer */ +#define QSPI_MR_NBBITS_15_BIT (0x7u << 8) /**< \brief (QSPI_MR) 15 bits for transfer */ +#define QSPI_MR_NBBITS_16_BIT (0x8u << 8) /**< \brief (QSPI_MR) 16 bits for transfer */ +#define QSPI_MR_DLYBCT_Pos 16 +#define QSPI_MR_DLYBCT_Msk (0xffu << QSPI_MR_DLYBCT_Pos) /**< \brief (QSPI_MR) Delay Between Consecutive Transfers */ +#define QSPI_MR_DLYBCT(value) ((QSPI_MR_DLYBCT_Msk & ((value) << QSPI_MR_DLYBCT_Pos))) +#define QSPI_MR_DLYCS_Pos 24 +#define QSPI_MR_DLYCS_Msk (0xffu << QSPI_MR_DLYCS_Pos) /**< \brief (QSPI_MR) Minimum Inactive QCS Delay */ +#define QSPI_MR_DLYCS(value) ((QSPI_MR_DLYCS_Msk & ((value) << QSPI_MR_DLYCS_Pos))) +/* -------- QSPI_RDR : (QSPI Offset: 0x08) Receive Data Register -------- */ +#define QSPI_RDR_RD_Pos 0 +#define QSPI_RDR_RD_Msk (0xffffu << QSPI_RDR_RD_Pos) /**< \brief (QSPI_RDR) Receive Data */ +/* -------- QSPI_TDR : (QSPI Offset: 0x0C) Transmit Data Register -------- */ +#define QSPI_TDR_TD_Pos 0 +#define QSPI_TDR_TD_Msk (0xffffu << QSPI_TDR_TD_Pos) /**< \brief (QSPI_TDR) Transmit Data */ +#define QSPI_TDR_TD(value) ((QSPI_TDR_TD_Msk & ((value) << QSPI_TDR_TD_Pos))) +/* -------- QSPI_SR : (QSPI Offset: 0x10) Status Register -------- */ +#define QSPI_SR_RDRF (0x1u << 0) /**< \brief (QSPI_SR) Receive Data Register Full (cleared by reading SPI_RDR) */ +#define QSPI_SR_TDRE (0x1u << 1) /**< \brief (QSPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR) */ +#define QSPI_SR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_SR) Transmission Registers Empty (cleared by writing SPI_TDR) */ +#define QSPI_SR_OVRES (0x1u << 3) /**< \brief (QSPI_SR) Overrun Error Status (cleared on read) */ +#define QSPI_SR_CSR (0x1u << 8) /**< \brief (QSPI_SR) Chip Select Rise */ +#define QSPI_SR_CSS (0x1u << 9) /**< \brief (QSPI_SR) Chip Select Status */ +#define QSPI_SR_INSTRE (0x1u << 10) /**< \brief (QSPI_SR) Instruction End Status */ +#define QSPI_SR_QSPIENS (0x1u << 24) /**< \brief (QSPI_SR) QSPI Enable Status */ +/* -------- QSPI_IER : (QSPI Offset: 0x14) Interrupt Enable Register -------- */ +#define QSPI_IER_RDRF (0x1u << 0) /**< \brief (QSPI_IER) Receive Data Register Full Interrupt Enable */ +#define QSPI_IER_TDRE (0x1u << 1) /**< \brief (QSPI_IER) Transmit Data Register Empty Interrupt Enable */ +#define QSPI_IER_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IER) Transmission Registers Empty Enable */ +#define QSPI_IER_OVRES (0x1u << 3) /**< \brief (QSPI_IER) Overrun Error Interrupt Enable */ +#define QSPI_IER_CSR (0x1u << 8) /**< \brief (QSPI_IER) Chip Select Rise Interrupt Enable */ +#define QSPI_IER_CSS (0x1u << 9) /**< \brief (QSPI_IER) Chip Select Status Interrupt Enable */ +#define QSPI_IER_INSTRE (0x1u << 10) /**< \brief (QSPI_IER) Instruction End Interrupt Enable */ +/* -------- QSPI_IDR : (QSPI Offset: 0x18) Interrupt Disable Register -------- */ +#define QSPI_IDR_RDRF (0x1u << 0) /**< \brief (QSPI_IDR) Receive Data Register Full Interrupt Disable */ +#define QSPI_IDR_TDRE (0x1u << 1) /**< \brief (QSPI_IDR) Transmit Data Register Empty Interrupt Disable */ +#define QSPI_IDR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IDR) Transmission Registers Empty Disable */ +#define QSPI_IDR_OVRES (0x1u << 3) /**< \brief (QSPI_IDR) Overrun Error Interrupt Disable */ +#define QSPI_IDR_CSR (0x1u << 8) /**< \brief (QSPI_IDR) Chip Select Rise Interrupt Disable */ +#define QSPI_IDR_CSS (0x1u << 9) /**< \brief (QSPI_IDR) Chip Select Status Interrupt Disable */ +#define QSPI_IDR_INSTRE (0x1u << 10) /**< \brief (QSPI_IDR) Instruction End Interrupt Disable */ +/* -------- QSPI_IMR : (QSPI Offset: 0x1C) Interrupt Mask Register -------- */ +#define QSPI_IMR_RDRF (0x1u << 0) /**< \brief (QSPI_IMR) Receive Data Register Full Interrupt Mask */ +#define QSPI_IMR_TDRE (0x1u << 1) /**< \brief (QSPI_IMR) Transmit Data Register Empty Interrupt Mask */ +#define QSPI_IMR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IMR) Transmission Registers Empty Mask */ +#define QSPI_IMR_OVRES (0x1u << 3) /**< \brief (QSPI_IMR) Overrun Error Interrupt Mask */ +#define QSPI_IMR_CSR (0x1u << 8) /**< \brief (QSPI_IMR) Chip Select Rise Interrupt Mask */ +#define QSPI_IMR_CSS (0x1u << 9) /**< \brief (QSPI_IMR) Chip Select Status Interrupt Mask */ +#define QSPI_IMR_INSTRE (0x1u << 10) /**< \brief (QSPI_IMR) Instruction End Interrupt Mask */ +/* -------- QSPI_SCR : (QSPI Offset: 0x20) Serial Clock Register -------- */ +#define QSPI_SCR_CPOL (0x1u << 0) /**< \brief (QSPI_SCR) Clock Polarity */ +#define QSPI_SCR_CPHA (0x1u << 1) /**< \brief (QSPI_SCR) Clock Phase */ +#define QSPI_SCR_SCBR_Pos 8 +#define QSPI_SCR_SCBR_Msk (0xffu << QSPI_SCR_SCBR_Pos) /**< \brief (QSPI_SCR) Serial Clock Baud Rate */ +#define QSPI_SCR_SCBR(value) ((QSPI_SCR_SCBR_Msk & ((value) << QSPI_SCR_SCBR_Pos))) +#define QSPI_SCR_DLYBS_Pos 16 +#define QSPI_SCR_DLYBS_Msk (0xffu << QSPI_SCR_DLYBS_Pos) /**< \brief (QSPI_SCR) Delay Before QSCK */ +#define QSPI_SCR_DLYBS(value) ((QSPI_SCR_DLYBS_Msk & ((value) << QSPI_SCR_DLYBS_Pos))) +/* -------- QSPI_IAR : (QSPI Offset: 0x30) Instruction Address Register -------- */ +#define QSPI_IAR_ADDR_Pos 0 +#define QSPI_IAR_ADDR_Msk (0xffffffffu << QSPI_IAR_ADDR_Pos) /**< \brief (QSPI_IAR) Address */ +#define QSPI_IAR_ADDR(value) ((QSPI_IAR_ADDR_Msk & ((value) << QSPI_IAR_ADDR_Pos))) +/* -------- QSPI_ICR : (QSPI Offset: 0x34) Instruction Code Register -------- */ +#define QSPI_ICR_INST_Pos 0 +#define QSPI_ICR_INST_Msk (0xffu << QSPI_ICR_INST_Pos) /**< \brief (QSPI_ICR) Instruction Code */ +#define QSPI_ICR_INST(value) ((QSPI_ICR_INST_Msk & ((value) << QSPI_ICR_INST_Pos))) +#define QSPI_ICR_OPT_Pos 16 +#define QSPI_ICR_OPT_Msk (0xffu << QSPI_ICR_OPT_Pos) /**< \brief (QSPI_ICR) Option Code */ +#define QSPI_ICR_OPT(value) ((QSPI_ICR_OPT_Msk & ((value) << QSPI_ICR_OPT_Pos))) +/* -------- QSPI_IFR : (QSPI Offset: 0x38) Instruction Frame Register -------- */ +#define QSPI_IFR_WIDTH_Pos 0 +#define QSPI_IFR_WIDTH_Msk (0x7u << QSPI_IFR_WIDTH_Pos) /**< \brief (QSPI_IFR) Width of Instruction Code, Address, Option Code and Data */ +#define QSPI_IFR_WIDTH(value) ((QSPI_IFR_WIDTH_Msk & ((value) << QSPI_IFR_WIDTH_Pos))) +#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0x0u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI */ +#define QSPI_IFR_WIDTH_DUAL_OUTPUT (0x1u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_OUTPUT (0x2u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI */ +#define QSPI_IFR_WIDTH_DUAL_IO (0x3u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_IO (0x4u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI */ +#define QSPI_IFR_WIDTH_DUAL_CMD (0x5u << 0) /**< \brief (QSPI_IFR) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_CMD (0x6u << 0) /**< \brief (QSPI_IFR) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI */ +#define QSPI_IFR_INSTEN (0x1u << 4) /**< \brief (QSPI_IFR) Instruction Enable */ +#define QSPI_IFR_ADDREN (0x1u << 5) /**< \brief (QSPI_IFR) Address Enable */ +#define QSPI_IFR_OPTEN (0x1u << 6) /**< \brief (QSPI_IFR) Option Enable */ +#define QSPI_IFR_DATAEN (0x1u << 7) /**< \brief (QSPI_IFR) Data Enable */ +#define QSPI_IFR_OPTL_Pos 8 +#define QSPI_IFR_OPTL_Msk (0x3u << QSPI_IFR_OPTL_Pos) /**< \brief (QSPI_IFR) Option Code Length */ +#define QSPI_IFR_OPTL(value) ((QSPI_IFR_OPTL_Msk & ((value) << QSPI_IFR_OPTL_Pos))) +#define QSPI_IFR_OPTL_OPTION_1BIT (0x0u << 8) /**< \brief (QSPI_IFR) The option code is 1 bit long. */ +#define QSPI_IFR_OPTL_OPTION_2BIT (0x1u << 8) /**< \brief (QSPI_IFR) The option code is 2 bits long. */ +#define QSPI_IFR_OPTL_OPTION_4BIT (0x2u << 8) /**< \brief (QSPI_IFR) The option code is 4 bits long. */ +#define QSPI_IFR_OPTL_OPTION_8BIT (0x3u << 8) /**< \brief (QSPI_IFR) The option code is 8 bits long. */ +#define QSPI_IFR_ADDRL (0x1u << 10) /**< \brief (QSPI_IFR) Address Length */ +#define QSPI_IFR_ADDRL_24_BIT (0x0u << 10) /**< \brief (QSPI_IFR) The address is 24 bits long. */ +#define QSPI_IFR_ADDRL_32_BIT (0x1u << 10) /**< \brief (QSPI_IFR) The address is 32 bits long. */ +#define QSPI_IFR_TFRTYP_Pos 12 +#define QSPI_IFR_TFRTYP_Msk (0x3u << QSPI_IFR_TFRTYP_Pos) /**< \brief (QSPI_IFR) Data Transfer Type */ +#define QSPI_IFR_TFRTYP(value) ((QSPI_IFR_TFRTYP_Msk & ((value) << QSPI_IFR_TFRTYP_Pos))) +#define QSPI_IFR_TFRTYP_TRSFR_READ (0x0u << 12) /**< \brief (QSPI_IFR) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial Flash memory is not possible. */ +#define QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY (0x1u << 12) /**< \brief (QSPI_IFR) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial Flash memory is possible. */ +#define QSPI_IFR_TFRTYP_TRSFR_WRITE (0x2u << 12) /**< \brief (QSPI_IFR) Write transfer into the serial memory.Scrambling is not performed. */ +#define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY (0x3u << 12) /**< \brief (QSPI_IFR) Write data transfer into the serial memory.If enabled, scrambling is performed. */ +#define QSPI_IFR_CRM (0x1u << 14) /**< \brief (QSPI_IFR) Continuous Read Mode */ +#define QSPI_IFR_CRM_DISABLED (0x0u << 14) /**< \brief (QSPI_IFR) The Continuous Read mode is disabled. */ +#define QSPI_IFR_CRM_ENABLED (0x1u << 14) /**< \brief (QSPI_IFR) The Continuous Read mode is enabled. */ +#define QSPI_IFR_NBDUM_Pos 16 +#define QSPI_IFR_NBDUM_Msk (0x1fu << QSPI_IFR_NBDUM_Pos) /**< \brief (QSPI_IFR) Number Of Dummy Cycles */ +#define QSPI_IFR_NBDUM(value) ((QSPI_IFR_NBDUM_Msk & ((value) << QSPI_IFR_NBDUM_Pos))) +/* -------- QSPI_SMR : (QSPI Offset: 0x40) Scrambling Mode Register -------- */ +#define QSPI_SMR_SCREN (0x1u << 0) /**< \brief (QSPI_SMR) Scrambling/Unscrambling Enable */ +#define QSPI_SMR_SCREN_DISABLED (0x0u << 0) /**< \brief (QSPI_SMR) The scrambling/unscrambling is disabled. */ +#define QSPI_SMR_SCREN_ENABLED (0x1u << 0) /**< \brief (QSPI_SMR) The scrambling/unscrambling is enabled. */ +#define QSPI_SMR_RVDIS (0x1u << 1) /**< \brief (QSPI_SMR) Scrambling/Unscrambling Random Value Disable */ +/* -------- QSPI_SKR : (QSPI Offset: 0x44) Scrambling Key Register -------- */ +#define QSPI_SKR_USRK_Pos 0 +#define QSPI_SKR_USRK_Msk (0xffffffffu << QSPI_SKR_USRK_Pos) /**< \brief (QSPI_SKR) Scrambling User Key */ +#define QSPI_SKR_USRK(value) ((QSPI_SKR_USRK_Msk & ((value) << QSPI_SKR_USRK_Pos))) +/* -------- QSPI_WPMR : (QSPI Offset: 0xE4) Write Protection Mode Register -------- */ +#define QSPI_WPMR_WPEN (0x1u << 0) /**< \brief (QSPI_WPMR) Write Protection Enable */ +#define QSPI_WPMR_WPKEY_Pos 8 +#define QSPI_WPMR_WPKEY_Msk (0xffffffu << QSPI_WPMR_WPKEY_Pos) /**< \brief (QSPI_WPMR) Write Protection Key */ +#define QSPI_WPMR_WPKEY(value) ((QSPI_WPMR_WPKEY_Msk & ((value) << QSPI_WPMR_WPKEY_Pos))) +#define QSPI_WPMR_WPKEY_PASSWD (0x515350u << 8) /**< \brief (QSPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- QSPI_WPSR : (QSPI Offset: 0xE8) Write Protection Status Register -------- */ +#define QSPI_WPSR_WPVS (0x1u << 0) /**< \brief (QSPI_WPSR) Write Protection Violation Status */ +#define QSPI_WPSR_WPVSRC_Pos 8 +#define QSPI_WPSR_WPVSRC_Msk (0xffu << QSPI_WPSR_WPVSRC_Pos) /**< \brief (QSPI_WPSR) Write Protection Violation Source */ +/* -------- QSPI_VERSION : (QSPI Offset: 0x00FC) Version Register -------- */ +#define QSPI_VERSION_VERSION_Pos 0 +#define QSPI_VERSION_VERSION_Msk (0xfffu << QSPI_VERSION_VERSION_Pos) /**< \brief (QSPI_VERSION) Hardware Module Version */ +#define QSPI_VERSION_MFN_Pos 16 +#define QSPI_VERSION_MFN_Msk (0x7u << QSPI_VERSION_MFN_Pos) /**< \brief (QSPI_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_QSPI_COMPONENT_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/rstc.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/rstc.h new file mode 100644 index 000000000..bd639b9cb --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/rstc.h @@ -0,0 +1,84 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_RSTC_COMPONENT_ +#define _SAME70_RSTC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Reset Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_RSTC Reset Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rstc hardware registers */ +typedef struct { + __O uint32_t RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */ + __I uint32_t RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */ + __IO uint32_t RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */ +} Rstc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */ +#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */ +#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */ +#define RSTC_CR_KEY_Pos 24 +#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) System Reset Key */ +#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos))) +#define RSTC_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_CR) Writing any other value in this field aborts the write operation. */ +/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */ +#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */ +#define RSTC_SR_RSTTYP_Pos 8 +#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */ +#define RSTC_SR_RSTTYP_GENERAL_RST (0x0u << 8) /**< \brief (RSTC_SR) First power-up reset */ +#define RSTC_SR_RSTTYP_BACKUP_RST (0x1u << 8) /**< \brief (RSTC_SR) Return from Backup Mode */ +#define RSTC_SR_RSTTYP_WDT_RST (0x2u << 8) /**< \brief (RSTC_SR) Watchdog fault occurred */ +#define RSTC_SR_RSTTYP_SOFT_RST (0x3u << 8) /**< \brief (RSTC_SR) Processor reset required by the software */ +#define RSTC_SR_RSTTYP_USER_RST (0x4u << 8) /**< \brief (RSTC_SR) NRST pin detected low */ +#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */ +#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */ +/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */ +#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */ +#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */ +#define RSTC_MR_ERSTL_Pos 8 +#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */ +#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos))) +#define RSTC_MR_KEY_Pos 24 +#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Write Access Password */ +#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos))) +#define RSTC_MR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_MR) Writing any other value in this field aborts the write operation.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAME70_RSTC_COMPONENT_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/rswdt.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/rswdt.h new file mode 100644 index 000000000..129c659e6 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/rswdt.h @@ -0,0 +1,77 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_RSWDT_COMPONENT_ +#define _SAME70_RSWDT_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Reinforced Safety Watchdog Timer */ +/* ============================================================================= */ +/** \addtogroup SAME70_RSWDT Reinforced Safety Watchdog Timer */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rswdt hardware registers */ +typedef struct { + __O uint32_t RSWDT_CR; /**< \brief (Rswdt Offset: 0x00) Control Register */ + __IO uint32_t RSWDT_MR; /**< \brief (Rswdt Offset: 0x04) Mode Register */ + __I uint32_t RSWDT_SR; /**< \brief (Rswdt Offset: 0x08) Status Register */ +} Rswdt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RSWDT_CR : (RSWDT Offset: 0x00) Control Register -------- */ +#define RSWDT_CR_WDRSTT (0x1u << 0) /**< \brief (RSWDT_CR) Watchdog Restart */ +#define RSWDT_CR_KEY_Pos 24 +#define RSWDT_CR_KEY_Msk (0xffu << RSWDT_CR_KEY_Pos) /**< \brief (RSWDT_CR) Password */ +#define RSWDT_CR_KEY(value) ((RSWDT_CR_KEY_Msk & ((value) << RSWDT_CR_KEY_Pos))) +#define RSWDT_CR_KEY_PASSWD (0xC4u << 24) /**< \brief (RSWDT_CR) Writing any other value in this field aborts the write operation. */ +/* -------- RSWDT_MR : (RSWDT Offset: 0x04) Mode Register -------- */ +#define RSWDT_MR_WDV_Pos 0 +#define RSWDT_MR_WDV_Msk (0xfffu << RSWDT_MR_WDV_Pos) /**< \brief (RSWDT_MR) Watchdog Counter Value */ +#define RSWDT_MR_WDV(value) ((RSWDT_MR_WDV_Msk & ((value) << RSWDT_MR_WDV_Pos))) +#define RSWDT_MR_WDFIEN (0x1u << 12) /**< \brief (RSWDT_MR) Watchdog Fault Interrupt Enable */ +#define RSWDT_MR_WDRSTEN (0x1u << 13) /**< \brief (RSWDT_MR) Watchdog Reset Enable */ +#define RSWDT_MR_WDRPROC (0x1u << 14) /**< \brief (RSWDT_MR) Watchdog Reset Processor */ +#define RSWDT_MR_WDDIS (0x1u << 15) /**< \brief (RSWDT_MR) Watchdog Disable */ +#define RSWDT_MR_ALLONES_Pos 16 +#define RSWDT_MR_ALLONES_Msk (0xfffu << RSWDT_MR_ALLONES_Pos) /**< \brief (RSWDT_MR) Must Always Be Written with 0xFFF */ +#define RSWDT_MR_ALLONES(value) ((RSWDT_MR_ALLONES_Msk & ((value) << RSWDT_MR_ALLONES_Pos))) +#define RSWDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (RSWDT_MR) Watchdog Debug Halt */ +#define RSWDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (RSWDT_MR) Watchdog Idle Halt */ +/* -------- RSWDT_SR : (RSWDT Offset: 0x08) Status Register -------- */ +#define RSWDT_SR_WDUNF (0x1u << 0) /**< \brief (RSWDT_SR) Watchdog Underflow */ + +/*@}*/ + + +#endif /* _SAME70_RSWDT_COMPONENT_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/rtc.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/rtc.h new file mode 100644 index 000000000..bdf892833 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/rtc.h @@ -0,0 +1,246 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_RTC_COMPONENT_ +#define _SAME70_RTC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Real-time Clock */ +/* ============================================================================= */ +/** \addtogroup SAME70_RTC Real-time Clock */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rtc hardware registers */ +typedef struct { + __IO uint32_t RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */ + __IO uint32_t RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */ + __IO uint32_t RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */ + __IO uint32_t RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */ + __IO uint32_t RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */ + __IO uint32_t RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */ + __I uint32_t RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */ + __O uint32_t RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */ + __O uint32_t RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */ + __O uint32_t RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */ + __I uint32_t RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */ + __I uint32_t RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */ + __I uint32_t Reserved1[45]; + __IO uint32_t RTC_WPMR; /**< \brief (Rtc Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t Reserved2[5]; + __I uint32_t RTC_VERSION; /**< \brief (Rtc Offset: 0xFC) Version Register */ +} Rtc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */ +#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */ +#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */ +#define RTC_CR_TIMEVSEL_Pos 8 +#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */ +#define RTC_CR_TIMEVSEL(value) ((RTC_CR_TIMEVSEL_Msk & ((value) << RTC_CR_TIMEVSEL_Pos))) +#define RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */ +#define RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */ +#define RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */ +#define RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */ +#define RTC_CR_CALEVSEL_Pos 16 +#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */ +#define RTC_CR_CALEVSEL(value) ((RTC_CR_CALEVSEL_Msk & ((value) << RTC_CR_CALEVSEL_Pos))) +#define RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */ +#define RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */ +#define RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */ +/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */ +#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */ +#define RTC_MR_PERSIAN (0x1u << 1) /**< \brief (RTC_MR) PERSIAN Calendar */ +#define RTC_MR_NEGPPM (0x1u << 4) /**< \brief (RTC_MR) NEGative PPM Correction */ +#define RTC_MR_CORRECTION_Pos 8 +#define RTC_MR_CORRECTION_Msk (0x7fu << RTC_MR_CORRECTION_Pos) /**< \brief (RTC_MR) Slow Clock Correction */ +#define RTC_MR_CORRECTION(value) ((RTC_MR_CORRECTION_Msk & ((value) << RTC_MR_CORRECTION_Pos))) +#define RTC_MR_HIGHPPM (0x1u << 15) /**< \brief (RTC_MR) HIGH PPM Correction */ +#define RTC_MR_OUT0_Pos 16 +#define RTC_MR_OUT0_Msk (0x7u << RTC_MR_OUT0_Pos) /**< \brief (RTC_MR) RTCOUT0 OutputSource Selection */ +#define RTC_MR_OUT0(value) ((RTC_MR_OUT0_Msk & ((value) << RTC_MR_OUT0_Pos))) +#define RTC_MR_OUT0_NO_WAVE (0x0u << 16) /**< \brief (RTC_MR) No waveform, stuck at '0' */ +#define RTC_MR_OUT0_FREQ1HZ (0x1u << 16) /**< \brief (RTC_MR) 1 Hz square wave */ +#define RTC_MR_OUT0_FREQ32HZ (0x2u << 16) /**< \brief (RTC_MR) 32 Hz square wave */ +#define RTC_MR_OUT0_FREQ64HZ (0x3u << 16) /**< \brief (RTC_MR) 64 Hz square wave */ +#define RTC_MR_OUT0_FREQ512HZ (0x4u << 16) /**< \brief (RTC_MR) 512 Hz square wave */ +#define RTC_MR_OUT0_ALARM_TOGGLE (0x5u << 16) /**< \brief (RTC_MR) Output toggles when alarm flag rises */ +#define RTC_MR_OUT0_ALARM_FLAG (0x6u << 16) /**< \brief (RTC_MR) Output is a copy of the alarm flag */ +#define RTC_MR_OUT0_PROG_PULSE (0x7u << 16) /**< \brief (RTC_MR) Duty cycle programmable pulse */ +#define RTC_MR_OUT1_Pos 20 +#define RTC_MR_OUT1_Msk (0x7u << RTC_MR_OUT1_Pos) /**< \brief (RTC_MR) RTCOUT1 Output Source Selection */ +#define RTC_MR_OUT1(value) ((RTC_MR_OUT1_Msk & ((value) << RTC_MR_OUT1_Pos))) +#define RTC_MR_OUT1_NO_WAVE (0x0u << 20) /**< \brief (RTC_MR) No waveform, stuck at '0' */ +#define RTC_MR_OUT1_FREQ1HZ (0x1u << 20) /**< \brief (RTC_MR) 1 Hz square wave */ +#define RTC_MR_OUT1_FREQ32HZ (0x2u << 20) /**< \brief (RTC_MR) 32 Hz square wave */ +#define RTC_MR_OUT1_FREQ64HZ (0x3u << 20) /**< \brief (RTC_MR) 64 Hz square wave */ +#define RTC_MR_OUT1_FREQ512HZ (0x4u << 20) /**< \brief (RTC_MR) 512 Hz square wave */ +#define RTC_MR_OUT1_ALARM_TOGGLE (0x5u << 20) /**< \brief (RTC_MR) Output toggles when alarm flag rises */ +#define RTC_MR_OUT1_ALARM_FLAG (0x6u << 20) /**< \brief (RTC_MR) Output is a copy of the alarm flag */ +#define RTC_MR_OUT1_PROG_PULSE (0x7u << 20) /**< \brief (RTC_MR) Duty cycle programmable pulse */ +#define RTC_MR_THIGH_Pos 24 +#define RTC_MR_THIGH_Msk (0x7u << RTC_MR_THIGH_Pos) /**< \brief (RTC_MR) High Duration of the Output Pulse */ +#define RTC_MR_THIGH(value) ((RTC_MR_THIGH_Msk & ((value) << RTC_MR_THIGH_Pos))) +#define RTC_MR_THIGH_H_31MS (0x0u << 24) /**< \brief (RTC_MR) 31.2 ms */ +#define RTC_MR_THIGH_H_16MS (0x1u << 24) /**< \brief (RTC_MR) 15.6 ms */ +#define RTC_MR_THIGH_H_4MS (0x2u << 24) /**< \brief (RTC_MR) 3.91 ms */ +#define RTC_MR_THIGH_H_976US (0x3u << 24) /**< \brief (RTC_MR) 976 us */ +#define RTC_MR_THIGH_H_488US (0x4u << 24) /**< \brief (RTC_MR) 488 us */ +#define RTC_MR_THIGH_H_122US (0x5u << 24) /**< \brief (RTC_MR) 122 us */ +#define RTC_MR_THIGH_H_30US (0x6u << 24) /**< \brief (RTC_MR) 30.5 us */ +#define RTC_MR_THIGH_H_15US (0x7u << 24) /**< \brief (RTC_MR) 15.2 us */ +#define RTC_MR_TPERIOD_Pos 28 +#define RTC_MR_TPERIOD_Msk (0x3u << RTC_MR_TPERIOD_Pos) /**< \brief (RTC_MR) Period of the Output Pulse */ +#define RTC_MR_TPERIOD(value) ((RTC_MR_TPERIOD_Msk & ((value) << RTC_MR_TPERIOD_Pos))) +#define RTC_MR_TPERIOD_P_1S (0x0u << 28) /**< \brief (RTC_MR) 1 second */ +#define RTC_MR_TPERIOD_P_500MS (0x1u << 28) /**< \brief (RTC_MR) 500 ms */ +#define RTC_MR_TPERIOD_P_250MS (0x2u << 28) /**< \brief (RTC_MR) 250 ms */ +#define RTC_MR_TPERIOD_P_125MS (0x3u << 28) /**< \brief (RTC_MR) 125 ms */ +/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */ +#define RTC_TIMR_SEC_Pos 0 +#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */ +#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos))) +#define RTC_TIMR_MIN_Pos 8 +#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */ +#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos))) +#define RTC_TIMR_HOUR_Pos 16 +#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */ +#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos))) +#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */ +/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */ +#define RTC_CALR_CENT_Pos 0 +#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */ +#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos))) +#define RTC_CALR_YEAR_Pos 8 +#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */ +#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos))) +#define RTC_CALR_MONTH_Pos 16 +#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */ +#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos))) +#define RTC_CALR_DAY_Pos 21 +#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */ +#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos))) +#define RTC_CALR_DATE_Pos 24 +#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */ +#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos))) +/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */ +#define RTC_TIMALR_SEC_Pos 0 +#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */ +#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos))) +#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */ +#define RTC_TIMALR_MIN_Pos 8 +#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */ +#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos))) +#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */ +#define RTC_TIMALR_HOUR_Pos 16 +#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */ +#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos))) +#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */ +#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */ +/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */ +#define RTC_CALALR_MONTH_Pos 16 +#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */ +#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos))) +#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */ +#define RTC_CALALR_DATE_Pos 24 +#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */ +#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos))) +#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */ +/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */ +#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */ +#define RTC_SR_ACKUPD_FREERUN (0x0u << 0) /**< \brief (RTC_SR) Time and calendar registers cannot be updated. */ +#define RTC_SR_ACKUPD_UPDATE (0x1u << 0) /**< \brief (RTC_SR) Time and calendar registers can be updated. */ +#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */ +#define RTC_SR_ALARM_NO_ALARMEVENT (0x0u << 1) /**< \brief (RTC_SR) No alarm matching condition occurred. */ +#define RTC_SR_ALARM_ALARMEVENT (0x1u << 1) /**< \brief (RTC_SR) An alarm matching condition has occurred. */ +#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */ +#define RTC_SR_SEC_NO_SECEVENT (0x0u << 2) /**< \brief (RTC_SR) No second event has occurred since the last clear. */ +#define RTC_SR_SEC_SECEVENT (0x1u << 2) /**< \brief (RTC_SR) At least one second event has occurred since the last clear. */ +#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */ +#define RTC_SR_TIMEV_NO_TIMEVENT (0x0u << 3) /**< \brief (RTC_SR) No time event has occurred since the last clear. */ +#define RTC_SR_TIMEV_TIMEVENT (0x1u << 3) /**< \brief (RTC_SR) At least one time event has occurred since the last clear. */ +#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */ +#define RTC_SR_CALEV_NO_CALEVENT (0x0u << 4) /**< \brief (RTC_SR) No calendar event has occurred since the last clear. */ +#define RTC_SR_CALEV_CALEVENT (0x1u << 4) /**< \brief (RTC_SR) At least one calendar event has occurred since the last clear. */ +#define RTC_SR_TDERR (0x1u << 5) /**< \brief (RTC_SR) Time and/or Date Free Running Error */ +#define RTC_SR_TDERR_CORRECT (0x0u << 5) /**< \brief (RTC_SR) The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR). */ +#define RTC_SR_TDERR_ERR_TIMEDATE (0x1u << 5) /**< \brief (RTC_SR) The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. */ +/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */ +#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */ +#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */ +#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */ +#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */ +#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */ +#define RTC_SCCR_TDERRCLR (0x1u << 5) /**< \brief (RTC_SCCR) Time and/or Date Free Running Error Clear */ +/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */ +#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */ +#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */ +#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */ +#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */ +#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */ +#define RTC_IER_TDERREN (0x1u << 5) /**< \brief (RTC_IER) Time and/or Date Error Interrupt Enable */ +/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */ +#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */ +#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */ +#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */ +#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */ +#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */ +#define RTC_IDR_TDERRDIS (0x1u << 5) /**< \brief (RTC_IDR) Time and/or Date Error Interrupt Disable */ +/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */ +#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */ +#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */ +#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */ +#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */ +#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */ +#define RTC_IMR_TDERR (0x1u << 5) /**< \brief (RTC_IMR) Time and/or Date Error Mask */ +/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */ +#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */ +#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */ +#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */ +#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */ +/* -------- RTC_WPMR : (RTC Offset: 0xE4) Write Protection Mode Register -------- */ +#define RTC_WPMR_WPEN (0x1u << 0) /**< \brief (RTC_WPMR) Write Protection Enable */ +#define RTC_WPMR_WPKEY_Pos 8 +#define RTC_WPMR_WPKEY_Msk (0xffffffu << RTC_WPMR_WPKEY_Pos) /**< \brief (RTC_WPMR) Write Protection Key */ +#define RTC_WPMR_WPKEY(value) ((RTC_WPMR_WPKEY_Msk & ((value) << RTC_WPMR_WPKEY_Pos))) +#define RTC_WPMR_WPKEY_PASSWD (0x525443u << 8) /**< \brief (RTC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- RTC_VERSION : (RTC Offset: 0xFC) Version Register -------- */ +#define RTC_VERSION_VERSION_Pos 0 +#define RTC_VERSION_VERSION_Msk (0xfffu << RTC_VERSION_VERSION_Pos) /**< \brief (RTC_VERSION) Version of the Hardware Module */ +#define RTC_VERSION_MFN_Pos 16 +#define RTC_VERSION_MFN_Msk (0x7u << RTC_VERSION_MFN_Pos) /**< \brief (RTC_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_RTC_COMPONENT_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/rtt.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/rtt.h new file mode 100644 index 000000000..8ceea2263 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/rtt.h @@ -0,0 +1,76 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_RTT_COMPONENT_ +#define _SAME70_RTT_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Real-time Timer */ +/* ============================================================================= */ +/** \addtogroup SAME70_RTT Real-time Timer */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rtt hardware registers */ +typedef struct { + __IO uint32_t RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */ + __IO uint32_t RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */ + __I uint32_t RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */ + __I uint32_t RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */ +} Rtt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */ +#define RTT_MR_RTPRES_Pos 0 +#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */ +#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos))) +#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */ +#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */ +#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */ +#define RTT_MR_RTTDIS (0x1u << 20) /**< \brief (RTT_MR) Real-time Timer Disable */ +#define RTT_MR_RTC1HZ (0x1u << 24) /**< \brief (RTT_MR) Real-Time Clock 1Hz Clock Selection */ +/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */ +#define RTT_AR_ALMV_Pos 0 +#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */ +#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos))) +/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */ +#define RTT_VR_CRTV_Pos 0 +#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */ +/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */ +#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status (cleared on read) */ +#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Prescaler Roll-over Status (cleared on read) */ + +/*@}*/ + + +#endif /* _SAME70_RTT_COMPONENT_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/sdramc.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/sdramc.h new file mode 100644 index 000000000..e9d0e3498 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/sdramc.h @@ -0,0 +1,185 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_SDRAMC_COMPONENT_ +#define _SAME70_SDRAMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR SDRAM Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_SDRAMC SDRAM Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Sdramc hardware registers */ +typedef struct { + __IO uint32_t SDRAMC_MR; /**< \brief (Sdramc Offset: 0x00) SDRAMC Mode Register */ + __IO uint32_t SDRAMC_TR; /**< \brief (Sdramc Offset: 0x04) SDRAMC Refresh Timer Register */ + __IO uint32_t SDRAMC_CR; /**< \brief (Sdramc Offset: 0x08) SDRAMC Configuration Register */ + __I uint32_t Reserved1[1]; + __IO uint32_t SDRAMC_LPR; /**< \brief (Sdramc Offset: 0x10) SDRAMC Low Power Register */ + __O uint32_t SDRAMC_IER; /**< \brief (Sdramc Offset: 0x14) SDRAMC Interrupt Enable Register */ + __O uint32_t SDRAMC_IDR; /**< \brief (Sdramc Offset: 0x18) SDRAMC Interrupt Disable Register */ + __I uint32_t SDRAMC_IMR; /**< \brief (Sdramc Offset: 0x1C) SDRAMC Interrupt Mask Register */ + __I uint32_t SDRAMC_ISR; /**< \brief (Sdramc Offset: 0x20) SDRAMC Interrupt Status Register */ + __IO uint32_t SDRAMC_MDR; /**< \brief (Sdramc Offset: 0x24) SDRAMC Memory Device Register */ + __IO uint32_t SDRAMC_CFR1; /**< \brief (Sdramc Offset: 0x28) SDRAMC Configuration Register 1 */ + __IO uint32_t SDRAMC_OCMS; /**< \brief (Sdramc Offset: 0x2C) SDRAMC OCMS Register */ + __O uint32_t SDRAMC_OCMS_KEY1; /**< \brief (Sdramc Offset: 0x30) SDRAMC OCMS KEY1 Register */ + __O uint32_t SDRAMC_OCMS_KEY2; /**< \brief (Sdramc Offset: 0x34) SDRAMC OCMS KEY2 Register */ + __I uint32_t Reserved2[49]; + __I uint32_t SDRAMC_VERSION; /**< \brief (Sdramc Offset: 0xFC) SDRAMC Version Register */ +} Sdramc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SDRAMC_MR : (SDRAMC Offset: 0x00) SDRAMC Mode Register -------- */ +#define SDRAMC_MR_MODE_Pos 0 +#define SDRAMC_MR_MODE_Msk (0x7u << SDRAMC_MR_MODE_Pos) /**< \brief (SDRAMC_MR) SDRAMC Command Mode */ +#define SDRAMC_MR_MODE(value) ((SDRAMC_MR_MODE_Msk & ((value) << SDRAMC_MR_MODE_Pos))) +#define SDRAMC_MR_MODE_NORMAL (0x0u << 0) /**< \brief (SDRAMC_MR) Normal mode. Any access to the SDRAM is decoded normally. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_NOP (0x1u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_ALLBANKS_PRECHARGE (0x2u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues an "All Banks Precharge" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_LOAD_MODEREG (0x3u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues a "Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_AUTO_REFRESH (0x4u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues an "Auto-Refresh" Command when the SDRAM device is accessed regardless of the cycle. Previously, an "All Banks Precharge" command must be issued. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_EXT_LOAD_MODEREG (0x5u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues an "Extended Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the "Extended Load Mode Register" command must be followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank; most low-power SDRAM devices use the bank 1. */ +#define SDRAMC_MR_MODE_DEEP_POWERDOWN (0x6u << 0) /**< \brief (SDRAMC_MR) Deep power-down mode. Enters deep power-down mode. */ +/* -------- SDRAMC_TR : (SDRAMC Offset: 0x04) SDRAMC Refresh Timer Register -------- */ +#define SDRAMC_TR_COUNT_Pos 0 +#define SDRAMC_TR_COUNT_Msk (0xfffu << SDRAMC_TR_COUNT_Pos) /**< \brief (SDRAMC_TR) SDRAMC Refresh Timer Count */ +#define SDRAMC_TR_COUNT(value) ((SDRAMC_TR_COUNT_Msk & ((value) << SDRAMC_TR_COUNT_Pos))) +/* -------- SDRAMC_CR : (SDRAMC Offset: 0x08) SDRAMC Configuration Register -------- */ +#define SDRAMC_CR_NC_Pos 0 +#define SDRAMC_CR_NC_Msk (0x3u << SDRAMC_CR_NC_Pos) /**< \brief (SDRAMC_CR) Number of Column Bits */ +#define SDRAMC_CR_NC(value) ((SDRAMC_CR_NC_Msk & ((value) << SDRAMC_CR_NC_Pos))) +#define SDRAMC_CR_NC_COL8 (0x0u << 0) /**< \brief (SDRAMC_CR) 8 column bits */ +#define SDRAMC_CR_NC_COL9 (0x1u << 0) /**< \brief (SDRAMC_CR) 9 column bits */ +#define SDRAMC_CR_NC_COL10 (0x2u << 0) /**< \brief (SDRAMC_CR) 10 column bits */ +#define SDRAMC_CR_NC_COL11 (0x3u << 0) /**< \brief (SDRAMC_CR) 11 column bits */ +#define SDRAMC_CR_NR_Pos 2 +#define SDRAMC_CR_NR_Msk (0x3u << SDRAMC_CR_NR_Pos) /**< \brief (SDRAMC_CR) Number of Row Bits */ +#define SDRAMC_CR_NR(value) ((SDRAMC_CR_NR_Msk & ((value) << SDRAMC_CR_NR_Pos))) +#define SDRAMC_CR_NR_ROW11 (0x0u << 2) /**< \brief (SDRAMC_CR) 11 row bits */ +#define SDRAMC_CR_NR_ROW12 (0x1u << 2) /**< \brief (SDRAMC_CR) 12 row bits */ +#define SDRAMC_CR_NR_ROW13 (0x2u << 2) /**< \brief (SDRAMC_CR) 13 row bits */ +#define SDRAMC_CR_NB (0x1u << 4) /**< \brief (SDRAMC_CR) Number of Banks */ +#define SDRAMC_CR_NB_BANK2 (0x0u << 4) /**< \brief (SDRAMC_CR) 2 banks */ +#define SDRAMC_CR_NB_BANK4 (0x1u << 4) /**< \brief (SDRAMC_CR) 4 banks */ +#define SDRAMC_CR_CAS_Pos 5 +#define SDRAMC_CR_CAS_Msk (0x3u << SDRAMC_CR_CAS_Pos) /**< \brief (SDRAMC_CR) CAS Latency */ +#define SDRAMC_CR_CAS(value) ((SDRAMC_CR_CAS_Msk & ((value) << SDRAMC_CR_CAS_Pos))) +#define SDRAMC_CR_CAS_LATENCY1 (0x1u << 5) /**< \brief (SDRAMC_CR) 1 cycle CAS latency */ +#define SDRAMC_CR_CAS_LATENCY2 (0x2u << 5) /**< \brief (SDRAMC_CR) 2 cycle CAS latency */ +#define SDRAMC_CR_CAS_LATENCY3 (0x3u << 5) /**< \brief (SDRAMC_CR) 3 cycle CAS latency */ +#define SDRAMC_CR_DBW (0x1u << 7) /**< \brief (SDRAMC_CR) Data Bus Width */ +#define SDRAMC_CR_TWR_Pos 8 +#define SDRAMC_CR_TWR_Msk (0xfu << SDRAMC_CR_TWR_Pos) /**< \brief (SDRAMC_CR) Write Recovery Delay */ +#define SDRAMC_CR_TWR(value) ((SDRAMC_CR_TWR_Msk & ((value) << SDRAMC_CR_TWR_Pos))) +#define SDRAMC_CR_TRC_TRFC_Pos 12 +#define SDRAMC_CR_TRC_TRFC_Msk (0xfu << SDRAMC_CR_TRC_TRFC_Pos) /**< \brief (SDRAMC_CR) Row Cycle Delay and Row Refresh Cycle */ +#define SDRAMC_CR_TRC_TRFC(value) ((SDRAMC_CR_TRC_TRFC_Msk & ((value) << SDRAMC_CR_TRC_TRFC_Pos))) +#define SDRAMC_CR_TRP_Pos 16 +#define SDRAMC_CR_TRP_Msk (0xfu << SDRAMC_CR_TRP_Pos) /**< \brief (SDRAMC_CR) Row Precharge Delay */ +#define SDRAMC_CR_TRP(value) ((SDRAMC_CR_TRP_Msk & ((value) << SDRAMC_CR_TRP_Pos))) +#define SDRAMC_CR_TRCD_Pos 20 +#define SDRAMC_CR_TRCD_Msk (0xfu << SDRAMC_CR_TRCD_Pos) /**< \brief (SDRAMC_CR) Row to Column Delay */ +#define SDRAMC_CR_TRCD(value) ((SDRAMC_CR_TRCD_Msk & ((value) << SDRAMC_CR_TRCD_Pos))) +#define SDRAMC_CR_TRAS_Pos 24 +#define SDRAMC_CR_TRAS_Msk (0xfu << SDRAMC_CR_TRAS_Pos) /**< \brief (SDRAMC_CR) Active to Precharge Delay */ +#define SDRAMC_CR_TRAS(value) ((SDRAMC_CR_TRAS_Msk & ((value) << SDRAMC_CR_TRAS_Pos))) +#define SDRAMC_CR_TXSR_Pos 28 +#define SDRAMC_CR_TXSR_Msk (0xfu << SDRAMC_CR_TXSR_Pos) /**< \brief (SDRAMC_CR) Exit Self Refresh to Active Delay */ +#define SDRAMC_CR_TXSR(value) ((SDRAMC_CR_TXSR_Msk & ((value) << SDRAMC_CR_TXSR_Pos))) +/* -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAMC Low Power Register -------- */ +#define SDRAMC_LPR_LPCB_Pos 0 +#define SDRAMC_LPR_LPCB_Msk (0x3u << SDRAMC_LPR_LPCB_Pos) /**< \brief (SDRAMC_LPR) Low-power Configuration Bits */ +#define SDRAMC_LPR_LPCB(value) ((SDRAMC_LPR_LPCB_Msk & ((value) << SDRAMC_LPR_LPCB_Pos))) +#define SDRAMC_LPR_LPCB_DISABLED (0x0u << 0) /**< \brief (SDRAMC_LPR) Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM device. */ +#define SDRAMC_LPR_LPCB_SELF_REFRESH (0x1u << 0) /**< \brief (SDRAMC_LPR) The SDRAMC issues a Self-refresh command to the SDRAM device, the SDCK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self Refresh Mode when accessed and enters it after the access. */ +#define SDRAMC_LPR_LPCB_POWER_DOWN (0x2u << 0) /**< \brief (SDRAMC_LPR) The SDRAMC issues a Power-down Command to the SDRAM device after each access, the SDCKE signal is set to low. The SDRAM device leaves the Power-down Mode when accessed and enters it after the access. */ +#define SDRAMC_LPR_LPCB_DEEP_POWER_DOWN (0x3u << 0) /**< \brief (SDRAMC_LPR) The SDRAMC issues a Deep Power-down command to the SDRAM device. This mode is unique to low-power SDRAM. */ +#define SDRAMC_LPR_PASR_Pos 4 +#define SDRAMC_LPR_PASR_Msk (0x7u << SDRAMC_LPR_PASR_Pos) /**< \brief (SDRAMC_LPR) Partial Array Self-refresh (only for low-power SDRAM) */ +#define SDRAMC_LPR_PASR(value) ((SDRAMC_LPR_PASR_Msk & ((value) << SDRAMC_LPR_PASR_Pos))) +#define SDRAMC_LPR_TCSR_Pos 8 +#define SDRAMC_LPR_TCSR_Msk (0x3u << SDRAMC_LPR_TCSR_Pos) /**< \brief (SDRAMC_LPR) Temperature Compensated Self-Refresh (only for low-power SDRAM) */ +#define SDRAMC_LPR_TCSR(value) ((SDRAMC_LPR_TCSR_Msk & ((value) << SDRAMC_LPR_TCSR_Pos))) +#define SDRAMC_LPR_DS_Pos 10 +#define SDRAMC_LPR_DS_Msk (0x3u << SDRAMC_LPR_DS_Pos) /**< \brief (SDRAMC_LPR) Drive Strength (only for low-power SDRAM) */ +#define SDRAMC_LPR_DS(value) ((SDRAMC_LPR_DS_Msk & ((value) << SDRAMC_LPR_DS_Pos))) +#define SDRAMC_LPR_TIMEOUT_Pos 12 +#define SDRAMC_LPR_TIMEOUT_Msk (0x3u << SDRAMC_LPR_TIMEOUT_Pos) /**< \brief (SDRAMC_LPR) Time to Define When Low-power Mode Is Enabled */ +#define SDRAMC_LPR_TIMEOUT(value) ((SDRAMC_LPR_TIMEOUT_Msk & ((value) << SDRAMC_LPR_TIMEOUT_Pos))) +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER (0x0u << 12) /**< \brief (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode immediately after the end of the last transfer. */ +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_64 (0x1u << 12) /**< \brief (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer. */ +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_128 (0x2u << 12) /**< \brief (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer. */ +/* -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAMC Interrupt Enable Register -------- */ +#define SDRAMC_IER_RES (0x1u << 0) /**< \brief (SDRAMC_IER) Refresh Error Status */ +/* -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAMC Interrupt Disable Register -------- */ +#define SDRAMC_IDR_RES (0x1u << 0) /**< \brief (SDRAMC_IDR) Refresh Error Status */ +/* -------- SDRAMC_IMR : (SDRAMC Offset: 0x1C) SDRAMC Interrupt Mask Register -------- */ +#define SDRAMC_IMR_RES (0x1u << 0) /**< \brief (SDRAMC_IMR) Refresh Error Status */ +/* -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAMC Interrupt Status Register -------- */ +#define SDRAMC_ISR_RES (0x1u << 0) /**< \brief (SDRAMC_ISR) Refresh Error Status (cleared on read) */ +/* -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAMC Memory Device Register -------- */ +#define SDRAMC_MDR_MD_Pos 0 +#define SDRAMC_MDR_MD_Msk (0x3u << SDRAMC_MDR_MD_Pos) /**< \brief (SDRAMC_MDR) Memory Device Type */ +#define SDRAMC_MDR_MD(value) ((SDRAMC_MDR_MD_Msk & ((value) << SDRAMC_MDR_MD_Pos))) +#define SDRAMC_MDR_MD_SDRAM (0x0u << 0) /**< \brief (SDRAMC_MDR) SDRAM */ +#define SDRAMC_MDR_MD_LPSDRAM (0x1u << 0) /**< \brief (SDRAMC_MDR) Low-power SDRAM */ +/* -------- SDRAMC_CFR1 : (SDRAMC Offset: 0x28) SDRAMC Configuration Register 1 -------- */ +#define SDRAMC_CFR1_TMRD_Pos 0 +#define SDRAMC_CFR1_TMRD_Msk (0xfu << SDRAMC_CFR1_TMRD_Pos) /**< \brief (SDRAMC_CFR1) Load Mode Register Command to Active or Refresh Command */ +#define SDRAMC_CFR1_TMRD(value) ((SDRAMC_CFR1_TMRD_Msk & ((value) << SDRAMC_CFR1_TMRD_Pos))) +#define SDRAMC_CFR1_UNAL (0x1u << 8) /**< \brief (SDRAMC_CFR1) Support Unaligned Access */ +#define SDRAMC_CFR1_UNAL_UNSUPPORTED (0x0u << 8) /**< \brief (SDRAMC_CFR1) Unaligned access is not supported. */ +#define SDRAMC_CFR1_UNAL_SUPPORTED (0x1u << 8) /**< \brief (SDRAMC_CFR1) Unaligned access is supported. */ +/* -------- SDRAMC_OCMS : (SDRAMC Offset: 0x2C) SDRAMC OCMS Register -------- */ +#define SDRAMC_OCMS_SDR_SE (0x1u << 0) /**< \brief (SDRAMC_OCMS) SDRAM Memory Controller Scrambling Enable */ +/* -------- SDRAMC_OCMS_KEY1 : (SDRAMC Offset: 0x30) SDRAMC OCMS KEY1 Register -------- */ +#define SDRAMC_OCMS_KEY1_KEY1_Pos 0 +#define SDRAMC_OCMS_KEY1_KEY1_Msk (0xffffffffu << SDRAMC_OCMS_KEY1_KEY1_Pos) /**< \brief (SDRAMC_OCMS_KEY1) Off-chip Memory Scrambling (OCMS) Key Part 1 */ +#define SDRAMC_OCMS_KEY1_KEY1(value) ((SDRAMC_OCMS_KEY1_KEY1_Msk & ((value) << SDRAMC_OCMS_KEY1_KEY1_Pos))) +/* -------- SDRAMC_OCMS_KEY2 : (SDRAMC Offset: 0x34) SDRAMC OCMS KEY2 Register -------- */ +#define SDRAMC_OCMS_KEY2_KEY2_Pos 0 +#define SDRAMC_OCMS_KEY2_KEY2_Msk (0xffffffffu << SDRAMC_OCMS_KEY2_KEY2_Pos) /**< \brief (SDRAMC_OCMS_KEY2) Off-chip Memory Scrambling (OCMS) Key Part 2 */ +#define SDRAMC_OCMS_KEY2_KEY2(value) ((SDRAMC_OCMS_KEY2_KEY2_Msk & ((value) << SDRAMC_OCMS_KEY2_KEY2_Pos))) +/* -------- SDRAMC_VERSION : (SDRAMC Offset: 0xFC) SDRAMC Version Register -------- */ +#define SDRAMC_VERSION_VERSION_Pos 0 +#define SDRAMC_VERSION_VERSION_Msk (0xfffu << SDRAMC_VERSION_VERSION_Pos) /**< \brief (SDRAMC_VERSION) Version of the Hardware Module */ +#define SDRAMC_VERSION_MFN_Pos 16 +#define SDRAMC_VERSION_MFN_Msk (0x7u << SDRAMC_VERSION_MFN_Pos) /**< \brief (SDRAMC_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_SDRAMC_COMPONENT_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/smc.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/smc.h new file mode 100644 index 000000000..d71158d04 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/smc.h @@ -0,0 +1,160 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_SMC_COMPONENT_ +#define _SAME70_SMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Static Memory Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_SMC Static Memory Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief SmcCs_number hardware registers */ +typedef struct { + __IO uint32_t SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */ + __IO uint32_t SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */ + __IO uint32_t SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */ + __IO uint32_t SMC_MODE; /**< \brief (SmcCs_number Offset: 0xC) SMC MODE Register */ +} SmcCs_number; +/** \brief Smc hardware registers */ +#define SMCCS_NUMBER_NUMBER 4 +typedef struct { + SmcCs_number SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x0) CS_number = 0 .. 3 */ + __I uint32_t Reserved1[16]; + __IO uint32_t SMC_OCMS; /**< \brief (Smc Offset: 0x80) SMC Off-Chip Memory Scrambling Register */ + __O uint32_t SMC_KEY1; /**< \brief (Smc Offset: 0x84) SMC Off-Chip Memory Scrambling KEY1 Register */ + __O uint32_t SMC_KEY2; /**< \brief (Smc Offset: 0x88) SMC Off-Chip Memory Scrambling KEY2 Register */ + __I uint32_t Reserved2[22]; + __IO uint32_t SMC_WPMR; /**< \brief (Smc Offset: 0xE4) SMC Write Protection Mode Register */ + __I uint32_t SMC_WPSR; /**< \brief (Smc Offset: 0xE8) SMC Write Protection Status Register */ + __I uint32_t Reserved3[4]; + __I uint32_t SMC_VERSION; /**< \brief (Smc Offset: 0xFC) SMC Version Register */ +} Smc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */ +#define SMC_SETUP_NWE_SETUP_Pos 0 +#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */ +#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos))) +#define SMC_SETUP_NCS_WR_SETUP_Pos 8 +#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in WRITE Access */ +#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos))) +#define SMC_SETUP_NRD_SETUP_Pos 16 +#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */ +#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos))) +#define SMC_SETUP_NCS_RD_SETUP_Pos 24 +#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in READ Access */ +#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos))) +/* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */ +#define SMC_PULSE_NWE_PULSE_Pos 0 +#define SMC_PULSE_NWE_PULSE_Msk (0x7fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */ +#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos))) +#define SMC_PULSE_NCS_WR_PULSE_Pos 8 +#define SMC_PULSE_NCS_WR_PULSE_Msk (0x7fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */ +#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos))) +#define SMC_PULSE_NRD_PULSE_Pos 16 +#define SMC_PULSE_NRD_PULSE_Msk (0x7fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */ +#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos))) +#define SMC_PULSE_NCS_RD_PULSE_Pos 24 +#define SMC_PULSE_NCS_RD_PULSE_Msk (0x7fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */ +#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos))) +/* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */ +#define SMC_CYCLE_NWE_CYCLE_Pos 0 +#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */ +#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos))) +#define SMC_CYCLE_NRD_CYCLE_Pos 16 +#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */ +#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos))) +/* -------- SMC_MODE : (SMC Offset: N/A) SMC MODE Register -------- */ +#define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE) Read Mode */ +#define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE) Write Mode */ +#define SMC_MODE_EXNW_MODE_Pos 4 +#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */ +#define SMC_MODE_EXNW_MODE(value) ((SMC_MODE_EXNW_MODE_Msk & ((value) << SMC_MODE_EXNW_MODE_Pos))) +#define SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled-The NWAIT input signal is ignored on the corresponding chip select. */ +#define SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode-If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped. */ +#define SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode-The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high. */ +#define SMC_MODE_BAT (0x1u << 8) /**< \brief (SMC_MODE) Byte Access Type */ +#define SMC_MODE_BAT_BYTE_SELECT (0x0u << 8) /**< \brief (SMC_MODE) Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1. */ +#define SMC_MODE_BAT_BYTE_WRITE (0x1u << 8) /**< \brief (SMC_MODE) Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD. */ +#define SMC_MODE_DBW (0x1u << 12) /**< \brief (SMC_MODE) Data Bus Width */ +#define SMC_MODE_DBW_8_BIT (0x0u << 12) /**< \brief (SMC_MODE) 8-bit Data Bus */ +#define SMC_MODE_DBW_16_BIT (0x1u << 12) /**< \brief (SMC_MODE) 16-bit Data Bus */ +#define SMC_MODE_TDF_CYCLES_Pos 16 +#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */ +#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos))) +#define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */ +#define SMC_MODE_PMEN (0x1u << 24) /**< \brief (SMC_MODE) Page Mode Enabled */ +#define SMC_MODE_PS_Pos 28 +#define SMC_MODE_PS_Msk (0x3u << SMC_MODE_PS_Pos) /**< \brief (SMC_MODE) Page Size */ +#define SMC_MODE_PS(value) ((SMC_MODE_PS_Msk & ((value) << SMC_MODE_PS_Pos))) +#define SMC_MODE_PS_4_BYTE (0x0u << 28) /**< \brief (SMC_MODE) 4-byte page */ +#define SMC_MODE_PS_8_BYTE (0x1u << 28) /**< \brief (SMC_MODE) 8-byte page */ +#define SMC_MODE_PS_16_BYTE (0x2u << 28) /**< \brief (SMC_MODE) 16-byte page */ +#define SMC_MODE_PS_32_BYTE (0x3u << 28) /**< \brief (SMC_MODE) 32-byte page */ +/* -------- SMC_OCMS : (SMC Offset: 0x80) SMC Off-Chip Memory Scrambling Register -------- */ +#define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */ +#define SMC_OCMS_CS0SE (0x1u << 8) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ +#define SMC_OCMS_CS1SE (0x1u << 9) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ +#define SMC_OCMS_CS2SE (0x1u << 10) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ +#define SMC_OCMS_CS3SE (0x1u << 11) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ +/* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC Off-Chip Memory Scrambling KEY1 Register -------- */ +#define SMC_KEY1_KEY1_Pos 0 +#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off-Chip Memory Scrambling (OCMS) Key Part 1 */ +#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos))) +/* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC Off-Chip Memory Scrambling KEY2 Register -------- */ +#define SMC_KEY2_KEY2_Pos 0 +#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off-Chip Memory Scrambling (OCMS) Key Part 2 */ +#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos))) +/* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protection Mode Register -------- */ +#define SMC_WPMR_WPEN (0x1u << 0) /**< \brief (SMC_WPMR) Write Protect Enable */ +#define SMC_WPMR_WPKEY_Pos 8 +#define SMC_WPMR_WPKEY_Msk (0xffffffu << SMC_WPMR_WPKEY_Pos) /**< \brief (SMC_WPMR) Write Protection Key */ +#define SMC_WPMR_WPKEY(value) ((SMC_WPMR_WPKEY_Msk & ((value) << SMC_WPMR_WPKEY_Pos))) +#define SMC_WPMR_WPKEY_PASSWD (0x534D43u << 8) /**< \brief (SMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protection Status Register -------- */ +#define SMC_WPSR_WPVS (0x1u << 0) /**< \brief (SMC_WPSR) Write Protection Violation Status */ +#define SMC_WPSR_WPVSRC_Pos 8 +#define SMC_WPSR_WPVSRC_Msk (0xffffu << SMC_WPSR_WPVSRC_Pos) /**< \brief (SMC_WPSR) Write Protection Violation Source */ +/* -------- SMC_VERSION : (SMC Offset: 0xFC) SMC Version Register -------- */ +#define SMC_VERSION_VERSION_Pos 0 +#define SMC_VERSION_VERSION_Msk (0xfffu << SMC_VERSION_VERSION_Pos) /**< \brief (SMC_VERSION) Hardware Module Version */ +#define SMC_VERSION_MFN_Pos 16 +#define SMC_VERSION_MFN_Msk (0x7u << SMC_VERSION_MFN_Pos) /**< \brief (SMC_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_SMC_COMPONENT_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/spi.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/spi.h new file mode 100644 index 000000000..79806a2dc --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/spi.h @@ -0,0 +1,178 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_SPI_COMPONENT_ +#define _SAME70_SPI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */ +/* ============================================================================= */ +/** \addtogroup SAME70_SPI Serial Peripheral Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Spi hardware registers */ +typedef struct { + __O uint32_t SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */ + __IO uint32_t SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */ + __I uint32_t SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */ + __O uint32_t SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */ + __I uint32_t SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */ + __O uint32_t SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */ + __O uint32_t SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */ + __I uint32_t SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */ + __I uint32_t Reserved1[4]; + __IO uint32_t SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register (CS_number = 0) */ + __I uint32_t Reserved2[41]; + __IO uint32_t SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved3[4]; + __I uint32_t SPI_VERSION; /**< \brief (Spi Offset: 0xFC) Version Register */ +} Spi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */ +#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */ +#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */ +#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */ +#define SPI_CR_REQCLR (0x1u << 12) /**< \brief (SPI_CR) Request to Clear the Comparison Trigger */ +#define SPI_CR_TXFCLR (0x1u << 16) /**< \brief (SPI_CR) Transmit FIFO Clear */ +#define SPI_CR_RXFCLR (0x1u << 17) /**< \brief (SPI_CR) Receive FIFO Clear */ +#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */ +#define SPI_CR_FIFOEN (0x1u << 30) /**< \brief (SPI_CR) FIFO Enable */ +#define SPI_CR_FIFODIS (0x1u << 31) /**< \brief (SPI_CR) FIFO Disable */ +/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */ +#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */ +#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */ +#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */ +#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */ +#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */ +#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */ +#define SPI_MR_PCS_Pos 16 +#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */ +#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos))) +#define SPI_MR_DLYBCS_Pos 24 +#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */ +#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos))) +/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */ +#define SPI_RDR_RD_Pos 0 +#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */ +#define SPI_RDR_PCS_Pos 16 +#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */ +/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */ +#define SPI_TDR_TD_Pos 0 +#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */ +#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos))) +#define SPI_TDR_PCS_Pos 16 +#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */ +#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos))) +#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */ +/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ +#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full (cleared by reading SPI_RDR) */ +#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR) */ +#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error (cleared on read) */ +#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status (cleared on read) */ +#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising (cleared on read) */ +#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty (cleared by writing SPI_TDR) */ +#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave mode only) (cleared on read) */ +#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */ +/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ +#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */ +#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */ +#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */ +#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */ +#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */ +#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */ +#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */ +/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */ +#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */ +#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */ +#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */ +#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */ +#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */ +#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */ +/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */ +#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */ +#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */ +#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */ +#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */ +#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */ +#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */ +#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */ +/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register (CS_number = 0) -------- */ +#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */ +#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */ +#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ +#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Active After Transfer */ +#define SPI_CSR_BITS_Pos 4 +#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */ +#define SPI_CSR_BITS(value) ((SPI_CSR_BITS_Msk & ((value) << SPI_CSR_BITS_Pos))) +#define SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */ +#define SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */ +#define SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */ +#define SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */ +#define SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */ +#define SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */ +#define SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */ +#define SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */ +#define SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */ +#define SPI_CSR_SCBR_Pos 8 +#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Bit Rate */ +#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos))) +#define SPI_CSR_DLYBS_Pos 16 +#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */ +#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos))) +#define SPI_CSR_DLYBCT_Pos 24 +#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */ +#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos))) +/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Mode Register -------- */ +#define SPI_WPMR_WPEN (0x1u << 0) /**< \brief (SPI_WPMR) Write Protection Enable */ +#define SPI_WPMR_WPKEY_Pos 8 +#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) /**< \brief (SPI_WPMR) Write Protection Key */ +#define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos))) +#define SPI_WPMR_WPKEY_PASSWD (0x535049u << 8) /**< \brief (SPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */ +#define SPI_WPSR_WPVS (0x1u << 0) /**< \brief (SPI_WPSR) Write Protection Violation Status */ +#define SPI_WPSR_WPVSRC_Pos 8 +#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Source */ +/* -------- SPI_VERSION : (SPI Offset: 0xFC) Version Register -------- */ +#define SPI_VERSION_VERSION_Pos 0 +#define SPI_VERSION_VERSION_Msk (0xfffu << SPI_VERSION_VERSION_Pos) /**< \brief (SPI_VERSION) Version of the Hardware Module */ +#define SPI_VERSION_MFN_Pos 16 +#define SPI_VERSION_MFN_Msk (0x7u << SPI_VERSION_MFN_Pos) /**< \brief (SPI_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_SPI_COMPONENT_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/ssc.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/ssc.h new file mode 100644 index 000000000..a0a89d6c9 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/ssc.h @@ -0,0 +1,292 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_SSC_COMPONENT_ +#define _SAME70_SSC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_SSC Synchronous Serial Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Ssc hardware registers */ +typedef struct { + __O uint32_t SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */ + __IO uint32_t SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */ + __I uint32_t Reserved1[2]; + __IO uint32_t SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */ + __IO uint32_t SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */ + __IO uint32_t SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */ + __IO uint32_t SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */ + __I uint32_t SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */ + __O uint32_t SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */ + __I uint32_t Reserved2[2]; + __I uint32_t SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */ + __IO uint32_t SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */ + __IO uint32_t SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */ + __IO uint32_t SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */ + __I uint32_t SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */ + __O uint32_t SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */ + __O uint32_t SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */ + __I uint32_t SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */ + __I uint32_t Reserved3[37]; + __IO uint32_t SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved4[4]; + __I uint32_t SSC_VERSION; /**< \brief (Ssc Offset: 0xFC) Version Register */ +} Ssc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */ +#define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */ +#define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */ +#define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */ +#define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */ +#define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */ +/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */ +#define SSC_CMR_DIV_Pos 0 +#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */ +#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos))) +/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */ +#define SSC_RCMR_CKS_Pos 0 +#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */ +#define SSC_RCMR_CKS(value) ((SSC_RCMR_CKS_Msk & ((value) << SSC_RCMR_CKS_Pos))) +#define SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */ +#define SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */ +#define SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */ +#define SSC_RCMR_CKO_Pos 2 +#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */ +#define SSC_RCMR_CKO(value) ((SSC_RCMR_CKO_Msk & ((value) << SSC_RCMR_CKO_Pos))) +#define SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None, RK pin is an input */ +#define SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock, RK pin is an output */ +#define SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers, RK pin is an output */ +#define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */ +#define SSC_RCMR_CKG_Pos 6 +#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */ +#define SSC_RCMR_CKG(value) ((SSC_RCMR_CKG_Msk & ((value) << SSC_RCMR_CKG_Pos))) +#define SSC_RCMR_CKG_CONTINUOUS (0x0u << 6) /**< \brief (SSC_RCMR) None */ +#define SSC_RCMR_CKG_EN_RF_LOW (0x1u << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF Low */ +#define SSC_RCMR_CKG_EN_RF_HIGH (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF High */ +#define SSC_RCMR_START_Pos 8 +#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */ +#define SSC_RCMR_START(value) ((SSC_RCMR_START_Msk & ((value) << SSC_RCMR_START_Pos))) +#define SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */ +#define SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */ +#define SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */ +#define SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */ +#define SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */ +#define SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */ +#define SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */ +#define SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */ +#define SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */ +#define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */ +#define SSC_RCMR_STTDLY_Pos 16 +#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */ +#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos))) +#define SSC_RCMR_PERIOD_Pos 24 +#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */ +#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos))) +/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */ +#define SSC_RFMR_DATLEN_Pos 0 +#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */ +#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos))) +#define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */ +#define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */ +#define SSC_RFMR_DATNB_Pos 8 +#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */ +#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos))) +#define SSC_RFMR_FSLEN_Pos 16 +#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */ +#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos))) +#define SSC_RFMR_FSOS_Pos 20 +#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */ +#define SSC_RFMR_FSOS(value) ((SSC_RFMR_FSOS_Msk & ((value) << SSC_RFMR_FSOS_Pos))) +#define SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None, RF pin is an input */ +#define SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse, RF pin is an output */ +#define SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse, RF pin is an output */ +#define SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer, RF pin is an output */ +#define SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer, RF pin is an output */ +#define SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer, RF pin is an output */ +#define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */ +#define SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */ +#define SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */ +#define SSC_RFMR_FSLEN_EXT_Pos 28 +#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */ +#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos))) +/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */ +#define SSC_TCMR_CKS_Pos 0 +#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */ +#define SSC_TCMR_CKS(value) ((SSC_TCMR_CKS_Msk & ((value) << SSC_TCMR_CKS_Pos))) +#define SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */ +#define SSC_TCMR_CKS_RK (0x1u << 0) /**< \brief (SSC_TCMR) RK Clock signal */ +#define SSC_TCMR_CKS_TK (0x2u << 0) /**< \brief (SSC_TCMR) TK pin */ +#define SSC_TCMR_CKO_Pos 2 +#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */ +#define SSC_TCMR_CKO(value) ((SSC_TCMR_CKO_Msk & ((value) << SSC_TCMR_CKO_Pos))) +#define SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None, TK pin is an input */ +#define SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Transmit Clock, TK pin is an output */ +#define SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers, TK pin is an output */ +#define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */ +#define SSC_TCMR_CKG_Pos 6 +#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */ +#define SSC_TCMR_CKG(value) ((SSC_TCMR_CKG_Msk & ((value) << SSC_TCMR_CKG_Pos))) +#define SSC_TCMR_CKG_CONTINUOUS (0x0u << 6) /**< \brief (SSC_TCMR) None */ +#define SSC_TCMR_CKG_EN_TF_LOW (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */ +#define SSC_TCMR_CKG_EN_TF_HIGH (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */ +#define SSC_TCMR_START_Pos 8 +#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */ +#define SSC_TCMR_START(value) ((SSC_TCMR_START_Msk & ((value) << SSC_TCMR_START_Pos))) +#define SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data */ +#define SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */ +#define SSC_TCMR_START_TF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */ +#define SSC_TCMR_START_TF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */ +#define SSC_TCMR_START_TF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */ +#define SSC_TCMR_START_TF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */ +#define SSC_TCMR_START_TF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */ +#define SSC_TCMR_START_TF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */ +#define SSC_TCMR_STTDLY_Pos 16 +#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */ +#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos))) +#define SSC_TCMR_PERIOD_Pos 24 +#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */ +#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos))) +/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */ +#define SSC_TFMR_DATLEN_Pos 0 +#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */ +#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos))) +#define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */ +#define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */ +#define SSC_TFMR_DATNB_Pos 8 +#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per Frame */ +#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos))) +#define SSC_TFMR_FSLEN_Pos 16 +#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */ +#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos))) +#define SSC_TFMR_FSOS_Pos 20 +#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */ +#define SSC_TFMR_FSOS(value) ((SSC_TFMR_FSOS_Msk & ((value) << SSC_TFMR_FSOS_Pos))) +#define SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None, TF pin is an input */ +#define SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse, TF pin is an output */ +#define SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse, TF pin is an output */ +#define SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */ +#define SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */ +#define SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */ +#define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */ +#define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */ +#define SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */ +#define SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */ +#define SSC_TFMR_FSLEN_EXT_Pos 28 +#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */ +#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos))) +/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */ +#define SSC_RHR_RDAT_Pos 0 +#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */ +/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */ +#define SSC_THR_TDAT_Pos 0 +#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */ +#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos))) +/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */ +#define SSC_RSHR_RSDAT_Pos 0 +#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */ +/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */ +#define SSC_TSHR_TSDAT_Pos 0 +#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */ +#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos))) +/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */ +#define SSC_RC0R_CP0_Pos 0 +#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */ +#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos))) +/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */ +#define SSC_RC1R_CP1_Pos 0 +#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */ +#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos))) +/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */ +#define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */ +#define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */ +#define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */ +#define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */ +#define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */ +#define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */ +#define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */ +#define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */ +#define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */ +#define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */ +/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */ +#define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */ +#define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */ +#define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */ +#define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */ +#define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */ +#define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */ +#define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */ +#define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */ +/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */ +#define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */ +#define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */ +#define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */ +#define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */ +#define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */ +#define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */ +#define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */ +#define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */ +/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */ +#define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */ +#define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */ +#define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */ +#define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */ +#define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */ +#define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */ +#define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */ +#define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */ +/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protection Mode Register -------- */ +#define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protection Enable */ +#define SSC_WPMR_WPKEY_Pos 8 +#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protection Key */ +#define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos))) +#define SSC_WPMR_WPKEY_PASSWD (0x535343u << 8) /**< \brief (SSC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protection Status Register -------- */ +#define SSC_WPSR_WPVS (0x1u << 0) /**< \brief (SSC_WPSR) Write Protection Violation Status */ +#define SSC_WPSR_WPVSRC_Pos 8 +#define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos) /**< \brief (SSC_WPSR) Write Protect Violation Source */ +/* -------- SSC_VERSION : (SSC Offset: 0xFC) Version Register -------- */ +#define SSC_VERSION_VERSION_Pos 0 +#define SSC_VERSION_VERSION_Msk (0xffffu << SSC_VERSION_VERSION_Pos) /**< \brief (SSC_VERSION) Version of the Hardware Module */ +#define SSC_VERSION_MFN_Pos 16 +#define SSC_VERSION_MFN_Msk (0x7u << SSC_VERSION_MFN_Pos) /**< \brief (SSC_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_SSC_COMPONENT_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/supc.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/supc.h new file mode 100644 index 000000000..a1d848692 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/supc.h @@ -0,0 +1,306 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef _SAME70_SUPC_COMPONENT_ +#define _SAME70_SUPC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Supply Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_SUPC Supply Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Supc hardware registers */ +typedef struct { + __O uint32_t SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */ + __IO uint32_t SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */ + __IO uint32_t SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */ + __IO uint32_t SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake-up Mode Register */ + __IO uint32_t SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake-up Inputs Register */ + __I uint32_t SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */ + __I uint32_t Reserved1[57]; + __I uint32_t SYSC_VERSION; /**< \brief (Supc Offset: 0xFC) Version Register */ +} Supc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */ +#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */ +#define SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) No effect. */ +#define SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) If KEY is correct, VROFF asserts the vddcore_nreset and stops the voltage regulator. */ +#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */ +#define SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) No effect. */ +#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) If KEY is correct, XTALSEL switches the slow clock on the crystal oscillator output. */ +#define SUPC_CR_KEY_Pos 24 +#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */ +#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos))) +#define SUPC_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (SUPC_CR) Writing any other value in this field aborts the write operation. */ +/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */ +#define SUPC_SMMR_SMTH_Pos 0 +#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */ +#define SUPC_SMMR_SMTH(value) ((SUPC_SMMR_SMTH_Msk & ((value) << SUPC_SMMR_SMTH_Pos))) +#define SUPC_SMMR_SMSMPL_Pos 8 +#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */ +#define SUPC_SMMR_SMSMPL(value) ((SUPC_SMMR_SMSMPL_Msk & ((value) << SUPC_SMMR_SMSMPL_Pos))) +#define SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */ +#define SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */ +#define SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */ +#define SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */ +#define SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */ +#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */ +#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) The core reset signal vddcore_nreset is not affected when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */ +#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) The SUPC interrupt signal is not affected when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) The SUPC interrupt signal is asserted when a supply monitor detection occurs. */ +/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */ +#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */ +#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) The core reset signal vddcore_nreset is not affected when a brownout detection occurs. */ +#define SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) The core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */ +#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */ +#define SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) The core brownout detector is enabled. */ +#define SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) The core brownout detector is disabled. */ +#define SUPC_MR_ONREG (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator Enable */ +#define SUPC_MR_ONREG_ONREG_UNUSED (0x0u << 14) /**< \brief (SUPC_MR) Internal voltage regulator is not used (external power supply is used). */ +#define SUPC_MR_ONREG_ONREG_USED (0x1u << 14) /**< \brief (SUPC_MR) Internal voltage regulator is used. */ +#define SUPC_MR_BKUPRETON (0x1u << 17) /**< \brief (SUPC_MR) SRAM On In Backup Mode */ +#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */ +#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) No effect. Clock selection depends on the value of XTALSEL (SUPC_CR). */ +#define SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) The 32 kHz crystal oscillator is bypassed if XTALSEL (SUPC_CR) is set. OSCBYPASS must be set prior to setting XTALSEL. */ +#define SUPC_MR_KEY_Pos 24 +#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */ +#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos))) +#define SUPC_MR_KEY_PASSWD (0xA5u << 24) /**< \brief (SUPC_MR) Writing any other value in this field aborts the write operation. */ +/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake-up Mode Register -------- */ +#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake-up Enable */ +#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) The supply monitor detection has no wake-up effect. */ +#define SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) The supply monitor detection forces the wake-up of the core power supply. */ +#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real-time Timer Wake-up Enable */ +#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) The RTT alarm signal has no wake-up effect. */ +#define SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) The RTT alarm signal forces the wake-up of the core power supply. */ +#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real-time Clock Wake-up Enable */ +#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) The RTC alarm signal has no wake-up effect. */ +#define SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) The RTC alarm signal forces the wake-up of the core power supply. */ +#define SUPC_WUMR_LPDBCEN0 (0x1u << 5) /**< \brief (SUPC_WUMR) Low-power Debouncer Enable WKUP0 */ +#define SUPC_WUMR_LPDBCEN0_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUMR) The WKUP0 input pin is not connected to the low-power debouncer. */ +#define SUPC_WUMR_LPDBCEN0_ENABLE (0x1u << 5) /**< \brief (SUPC_WUMR) The WKUP0 input pin is connected to the low-power debouncer and forces a system wake-up. */ +#define SUPC_WUMR_LPDBCEN1 (0x1u << 6) /**< \brief (SUPC_WUMR) Low-power Debouncer Enable WKUP1 */ +#define SUPC_WUMR_LPDBCEN1_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUMR) The WKUP1 input pin is not connected to the low-power debouncer. */ +#define SUPC_WUMR_LPDBCEN1_ENABLE (0x1u << 6) /**< \brief (SUPC_WUMR) The WKUP1 input pin is connected to the low-power debouncer and forces a system wake-up. */ +#define SUPC_WUMR_LPDBCCLR (0x1u << 7) /**< \brief (SUPC_WUMR) Low-power Debouncer Clear */ +#define SUPC_WUMR_LPDBCCLR_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUMR) A low-power debounce event does not create an immediate clear on the first half of GPBR registers. */ +#define SUPC_WUMR_LPDBCCLR_ENABLE (0x1u << 7) /**< \brief (SUPC_WUMR) A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR registers. */ +#define SUPC_WUMR_WKUPDBC_Pos 12 +#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake-up Inputs Debouncer Period */ +#define SUPC_WUMR_WKUPDBC(value) ((SUPC_WUMR_WKUPDBC_Msk & ((value) << SUPC_WUMR_WKUPDBC_Pos))) +#define SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */ +#define SUPC_WUMR_WKUPDBC_3_SLCK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_32_SLCK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_512_SLCK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_4096_SLCK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_32768_SLCK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */ +#define SUPC_WUMR_LPDBC_Pos 16 +#define SUPC_WUMR_LPDBC_Msk (0x7u << SUPC_WUMR_LPDBC_Pos) /**< \brief (SUPC_WUMR) Low-power Debouncer Period */ +#define SUPC_WUMR_LPDBC(value) ((SUPC_WUMR_LPDBC_Msk & ((value) << SUPC_WUMR_LPDBC_Pos))) +#define SUPC_WUMR_LPDBC_DISABLE (0x0u << 16) /**< \brief (SUPC_WUMR) Disable the low-power debouncers. */ +#define SUPC_WUMR_LPDBC_2_RTCOUT (0x1u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 2 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_3_RTCOUT (0x2u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 3 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_4_RTCOUT (0x3u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 4 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_5_RTCOUT (0x4u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 5 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_6_RTCOUT (0x5u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 6 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_7_RTCOUT (0x6u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 7 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_8_RTCOUT (0x7u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 8 RTCOUTx clock periods */ +/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake-up Inputs Register -------- */ +#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 0 */ +#define SUPC_WUIR_WKUPEN0_DISABLE (0x0u << 0) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 1 */ +#define SUPC_WUIR_WKUPEN1_DISABLE (0x0u << 1) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 2 */ +#define SUPC_WUIR_WKUPEN2_DISABLE (0x0u << 2) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 3 */ +#define SUPC_WUIR_WKUPEN3_DISABLE (0x0u << 3) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 4 */ +#define SUPC_WUIR_WKUPEN4_DISABLE (0x0u << 4) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 5 */ +#define SUPC_WUIR_WKUPEN5_DISABLE (0x0u << 5) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 6 */ +#define SUPC_WUIR_WKUPEN6_DISABLE (0x0u << 6) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 7 */ +#define SUPC_WUIR_WKUPEN7_DISABLE (0x0u << 7) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 8 */ +#define SUPC_WUIR_WKUPEN8_DISABLE (0x0u << 8) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 9 */ +#define SUPC_WUIR_WKUPEN9_DISABLE (0x0u << 9) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 10 */ +#define SUPC_WUIR_WKUPEN10_DISABLE (0x0u << 10) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 11 */ +#define SUPC_WUIR_WKUPEN11_DISABLE (0x0u << 11) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 12 */ +#define SUPC_WUIR_WKUPEN12_DISABLE (0x0u << 12) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 13 */ +#define SUPC_WUIR_WKUPEN13_DISABLE (0x0u << 13) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 0 */ +#define SUPC_WUIR_WKUPT0_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT0_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 1 */ +#define SUPC_WUIR_WKUPT1_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT1_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 2 */ +#define SUPC_WUIR_WKUPT2_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT2_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 3 */ +#define SUPC_WUIR_WKUPT3_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT3_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 4 */ +#define SUPC_WUIR_WKUPT4_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT4_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 5 */ +#define SUPC_WUIR_WKUPT5_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT5_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 6 */ +#define SUPC_WUIR_WKUPT6_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT6_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 7 */ +#define SUPC_WUIR_WKUPT7_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT7_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 8 */ +#define SUPC_WUIR_WKUPT8_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT8_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 9 */ +#define SUPC_WUIR_WKUPT9_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT9_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 10 */ +#define SUPC_WUIR_WKUPT10_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT10_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 11 */ +#define SUPC_WUIR_WKUPT11_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT11_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 12 */ +#define SUPC_WUIR_WKUPT12_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT12_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 13 */ +#define SUPC_WUIR_WKUPT13_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT13_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */ +#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake-up Status (cleared on read) */ +#define SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake-up Status (cleared on read) */ +#define SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) No wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) At least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status (cleared on read) */ +#define SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) No core brownout rising edge event has been detected since the last read of the SUPC_SR. */ +#define SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) At least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */ +#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status (cleared on read) */ +#define SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) No supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ +#define SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ +#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status (cleared on read) */ +#define SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) No supply monitor detection since the last read of SUPC_SR. */ +#define SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) At least one supply monitor detection since the last read of SUPC_SR. */ +#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */ +#define SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) The supply monitor detected VDDIO higher than its threshold at its last measurement. */ +#define SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) The supply monitor detected VDDIO lower than its threshold at its last measurement. */ +#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */ +#define SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) The slow clock, SLCK, is generated by the embedded 32 kHz RC oscillator. */ +#define SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) The slow clock, SLCK, is generated by the 32 kHz crystal oscillator. */ +#define SUPC_SR_LPDBCS0 (0x1u << 13) /**< \brief (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP0 (cleared on read) */ +#define SUPC_SR_LPDBCS0_NO (0x0u << 13) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS0_PRESENT (0x1u << 13) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS1 (0x1u << 14) /**< \brief (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP1 (cleared on read) */ +#define SUPC_SR_LPDBCS1_NO (0x0u << 14) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS1_PRESENT (0x1u << 14) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +/* -------- SYSC_VERSION : (SUPC Offset: 0xFC) Version Register -------- */ +#define SYSC_VERSION_VERSION_Pos 0 +#define SYSC_VERSION_VERSION_Msk (0xfffu << SYSC_VERSION_VERSION_Pos) /**< \brief (SYSC_VERSION) Version of the Hardware Module */ +#define SYSC_VERSION_MFN_Pos 16 +#define SYSC_VERSION_MFN_Msk (0x7u << SYSC_VERSION_MFN_Pos) /**< \brief (SYSC_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_SUPC_COMPONENT_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/tc.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/tc.h new file mode 100644 index 000000000..9f482776e --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/tc.h @@ -0,0 +1,358 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_TC_COMPONENT_ +#define _SAME70_TC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Timer Counter */ +/* ============================================================================= */ +/** \addtogroup SAME70_TC Timer Counter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief TcChannel hardware registers */ +typedef struct { + __O uint32_t TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */ + __IO uint32_t TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */ + __IO uint32_t TC_SMMR; /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */ + __I uint32_t TC_RAB; /**< \brief (TcChannel Offset: 0xC) Register AB */ + __I uint32_t TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */ + __IO uint32_t TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */ + __IO uint32_t TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */ + __IO uint32_t TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */ + __I uint32_t TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */ + __O uint32_t TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */ + __O uint32_t TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */ + __I uint32_t TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */ + __IO uint32_t TC_EMR; /**< \brief (TcChannel Offset: 0x30) Extended Mode Register */ + __I uint32_t Reserved1[3]; +} TcChannel; +/** \brief Tc hardware registers */ +#define TCCHANNEL_NUMBER 3 +typedef struct { + TcChannel TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */ + __O uint32_t TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */ + __IO uint32_t TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */ + __O uint32_t TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */ + __O uint32_t TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */ + __I uint32_t TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */ + __I uint32_t TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */ + __IO uint32_t TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */ + __I uint32_t Reserved1[2]; + __IO uint32_t TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t Reserved2[5]; + __I uint32_t TC_VER; /**< \brief (Tc Offset: 0xFC) Version Register */ +} Tc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */ +#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */ +#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */ +#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */ +/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */ +#define TC_CMR_TCCLKS_Pos 0 +#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */ +#define TC_CMR_TCCLKS(value) ((TC_CMR_TCCLKS_Msk & ((value) << TC_CMR_TCCLKS_Pos))) +#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: internal PCK6 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/8 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/32 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/128 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: internal SLCK clock signal (from PMC) */ +#define TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */ +#define TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */ +#define TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */ +#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */ +#define TC_CMR_BURST_Pos 4 +#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */ +#define TC_CMR_BURST(value) ((TC_CMR_BURST_Msk & ((value) << TC_CMR_BURST_Pos))) +#define TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ +#define TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */ +#define TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */ +#define TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */ +#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */ +#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */ +#define TC_CMR_ETRGEDG_Pos 8 +#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */ +#define TC_CMR_ETRGEDG(value) ((TC_CMR_ETRGEDG_Msk & ((value) << TC_CMR_ETRGEDG_Pos))) +#define TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ +#define TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ +#define TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ +#define TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ +#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */ +#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */ +#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */ +#define TC_CMR_LDRA_Pos 16 +#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */ +#define TC_CMR_LDRA(value) ((TC_CMR_LDRA_Msk & ((value) << TC_CMR_LDRA_Pos))) +#define TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ +#define TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */ +#define TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */ +#define TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */ +#define TC_CMR_LDRB_Pos 18 +#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */ +#define TC_CMR_LDRB(value) ((TC_CMR_LDRB_Msk & ((value) << TC_CMR_LDRB_Pos))) +#define TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ +#define TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */ +#define TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */ +#define TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */ +#define TC_CMR_SBSMPLR_Pos 20 +#define TC_CMR_SBSMPLR_Msk (0x7u << TC_CMR_SBSMPLR_Pos) /**< \brief (TC_CMR) Loading Edge Subsampling Ratio */ +#define TC_CMR_SBSMPLR(value) ((TC_CMR_SBSMPLR_Msk & ((value) << TC_CMR_SBSMPLR_Pos))) +#define TC_CMR_SBSMPLR_ONE (0x0u << 20) /**< \brief (TC_CMR) Load a Capture Register each selected edge */ +#define TC_CMR_SBSMPLR_HALF (0x1u << 20) /**< \brief (TC_CMR) Load a Capture Register every 2 selected edges */ +#define TC_CMR_SBSMPLR_FOURTH (0x2u << 20) /**< \brief (TC_CMR) Load a Capture Register every 4 selected edges */ +#define TC_CMR_SBSMPLR_EIGHTH (0x3u << 20) /**< \brief (TC_CMR) Load a Capture Register every 8 selected edges */ +#define TC_CMR_SBSMPLR_SIXTEENTH (0x4u << 20) /**< \brief (TC_CMR) Load a Capture Register every 16 selected edges */ +#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */ +#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */ +#define TC_CMR_EEVTEDG_Pos 8 +#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */ +#define TC_CMR_EEVTEDG(value) ((TC_CMR_EEVTEDG_Msk & ((value) << TC_CMR_EEVTEDG_Pos))) +#define TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */ +#define TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ +#define TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ +#define TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ +#define TC_CMR_EEVT_Pos 10 +#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */ +#define TC_CMR_EEVT(value) ((TC_CMR_EEVT_Msk & ((value) << TC_CMR_EEVT_Pos))) +#define TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */ +#define TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */ +#define TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */ +#define TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */ +#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */ +#define TC_CMR_WAVSEL_Pos 13 +#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */ +#define TC_CMR_WAVSEL(value) ((TC_CMR_WAVSEL_Msk & ((value) << TC_CMR_WAVSEL_Pos))) +#define TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */ +#define TC_CMR_ACPA_Pos 16 +#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */ +#define TC_CMR_ACPA(value) ((TC_CMR_ACPA_Msk & ((value) << TC_CMR_ACPA_Pos))) +#define TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ +#define TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_ACPC_Pos 18 +#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */ +#define TC_CMR_ACPC(value) ((TC_CMR_ACPC_Msk & ((value) << TC_CMR_ACPC_Pos))) +#define TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ +#define TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_AEEVT_Pos 20 +#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */ +#define TC_CMR_AEEVT(value) ((TC_CMR_AEEVT_Msk & ((value) << TC_CMR_AEEVT_Pos))) +#define TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */ +#define TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */ +#define TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_ASWTRG_Pos 22 +#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */ +#define TC_CMR_ASWTRG(value) ((TC_CMR_ASWTRG_Msk & ((value) << TC_CMR_ASWTRG_Pos))) +#define TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */ +#define TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BCPB_Pos 24 +#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */ +#define TC_CMR_BCPB(value) ((TC_CMR_BCPB_Msk & ((value) << TC_CMR_BCPB_Pos))) +#define TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */ +#define TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BCPC_Pos 26 +#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */ +#define TC_CMR_BCPC(value) ((TC_CMR_BCPC_Msk & ((value) << TC_CMR_BCPC_Pos))) +#define TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */ +#define TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BEEVT_Pos 28 +#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */ +#define TC_CMR_BEEVT(value) ((TC_CMR_BEEVT_Msk & ((value) << TC_CMR_BEEVT_Pos))) +#define TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */ +#define TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BSWTRG_Pos 30 +#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */ +#define TC_CMR_BSWTRG(value) ((TC_CMR_BSWTRG_Msk & ((value) << TC_CMR_BSWTRG_Pos))) +#define TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */ +#define TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */ +/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */ +#define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */ +#define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) Down Count */ +/* -------- TC_RAB : (TC Offset: N/A) Register AB -------- */ +#define TC_RAB_RAB_Pos 0 +#define TC_RAB_RAB_Msk (0xffffffffu << TC_RAB_RAB_Pos) /**< \brief (TC_RAB) Register A or Register B */ +/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */ +#define TC_CV_CV_Pos 0 +#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */ +/* -------- TC_RA : (TC Offset: N/A) Register A -------- */ +#define TC_RA_RA_Pos 0 +#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */ +#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos))) +/* -------- TC_RB : (TC Offset: N/A) Register B -------- */ +#define TC_RB_RB_Pos 0 +#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */ +#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos))) +/* -------- TC_RC : (TC Offset: N/A) Register C -------- */ +#define TC_RC_RC_Pos 0 +#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */ +#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos))) +/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */ +#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status (cleared on read) */ +#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status (cleared on read) */ +#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status (cleared on read) */ +#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status (cleared on read) */ +#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status (cleared on read) */ +#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status (cleared on read) */ +#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status (cleared on read) */ +#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status (cleared on read) */ +#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */ +#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */ +#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */ +/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */ +#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */ +#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */ +#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */ +#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */ +#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */ +#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */ +#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */ +#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */ +/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */ +#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */ +#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */ +#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */ +#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */ +#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */ +#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */ +#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */ +#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */ +/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */ +#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */ +#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */ +#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */ +#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */ +#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */ +#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */ +#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */ +#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */ +/* -------- TC_EMR : (TC Offset: N/A) Extended Mode Register -------- */ +#define TC_EMR_TRIGSRCA_Pos 0 +#define TC_EMR_TRIGSRCA_Msk (0x3u << TC_EMR_TRIGSRCA_Pos) /**< \brief (TC_EMR) Trigger Source for Input A */ +#define TC_EMR_TRIGSRCA(value) ((TC_EMR_TRIGSRCA_Msk & ((value) << TC_EMR_TRIGSRCA_Pos))) +#define TC_EMR_TRIGSRCA_EXTERNAL_TIOAx (0x0u << 0) /**< \brief (TC_EMR) The trigger/capture input A is driven by external pin TIOAx */ +#define TC_EMR_TRIGSRCA_PWMx (0x1u << 0) /**< \brief (TC_EMR) The trigger/capture input A is driven internally by PWMx */ +#define TC_EMR_TRIGSRCB_Pos 4 +#define TC_EMR_TRIGSRCB_Msk (0x3u << TC_EMR_TRIGSRCB_Pos) /**< \brief (TC_EMR) Trigger Source for Input B */ +#define TC_EMR_TRIGSRCB(value) ((TC_EMR_TRIGSRCB_Msk & ((value) << TC_EMR_TRIGSRCB_Pos))) +#define TC_EMR_TRIGSRCB_EXTERNAL_TIOBx (0x0u << 4) /**< \brief (TC_EMR) The trigger/capture input B is driven by external pin TIOBx */ +#define TC_EMR_TRIGSRCB_PWMx (0x1u << 4) /**< \brief (TC_EMR) The trigger/capture input B is driven internally by PWMx */ +#define TC_EMR_NODIVCLK (0x1u << 8) /**< \brief (TC_EMR) No Divided Clock */ +/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */ +#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */ +/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */ +#define TC_BMR_TC0XC0S_Pos 0 +#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */ +#define TC_BMR_TC0XC0S(value) ((TC_BMR_TC0XC0S_Msk & ((value) << TC_BMR_TC0XC0S_Pos))) +#define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */ +#define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */ +#define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */ +#define TC_BMR_TC1XC1S_Pos 2 +#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */ +#define TC_BMR_TC1XC1S(value) ((TC_BMR_TC1XC1S_Msk & ((value) << TC_BMR_TC1XC1S_Pos))) +#define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */ +#define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */ +#define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */ +#define TC_BMR_TC2XC2S_Pos 4 +#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */ +#define TC_BMR_TC2XC2S(value) ((TC_BMR_TC2XC2S_Msk & ((value) << TC_BMR_TC2XC2S_Pos))) +#define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */ +#define TC_BMR_TC2XC2S_TIOA0 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA0 */ +#define TC_BMR_TC2XC2S_TIOA1 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */ +#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder Enabled */ +#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) Position Enabled */ +#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) Speed Enabled */ +#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding Transparent */ +#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) Edge on PHA Count Mode */ +#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) Inverted PHA */ +#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) Inverted PHB */ +#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) Inverted Index */ +#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) Swap PHA and PHB */ +#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) Index Pin is PHB Pin */ +#define TC_BMR_MAXFILT_Pos 20 +#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) Maximum Filter */ +#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos))) +/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */ +#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) Index */ +#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) Direction Change */ +#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature Error */ +/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */ +#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) Index */ +#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) Direction Change */ +#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature Error */ +/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */ +#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) Index */ +#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) Direction Change */ +#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature Error */ +/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */ +#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) Index */ +#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) Direction Change */ +#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature Error */ +#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) Direction */ +/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */ +#define TC_FMR_ENCF0 (0x1u << 0) /**< \brief (TC_FMR) Enable Compare Fault Channel 0 */ +#define TC_FMR_ENCF1 (0x1u << 1) /**< \brief (TC_FMR) Enable Compare Fault Channel 1 */ +/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protection Mode Register -------- */ +#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protection Enable */ +#define TC_WPMR_WPKEY_Pos 8 +#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protection Key */ +#define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos))) +#define TC_WPMR_WPKEY_PASSWD (0x54494Du << 8) /**< \brief (TC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- TC_VER : (TC Offset: 0xFC) Version Register -------- */ +#define TC_VER_VERSION_Pos 0 +#define TC_VER_VERSION_Msk (0xfffu << TC_VER_VERSION_Pos) /**< \brief (TC_VER) Version of the Hardware Module */ +#define TC_VER_MFN_Pos 16 +#define TC_VER_MFN_Msk (0x7u << TC_VER_MFN_Pos) /**< \brief (TC_VER) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_TC_COMPONENT_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/trng.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/trng.h new file mode 100644 index 000000000..4ae37db96 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/trng.h @@ -0,0 +1,85 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_TRNG_COMPONENT_ +#define _SAME70_TRNG_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR True Random Number Generator */ +/* ============================================================================= */ +/** \addtogroup SAME70_TRNG True Random Number Generator */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Trng hardware registers */ +typedef struct { + __O uint32_t TRNG_CR; /**< \brief (Trng Offset: 0x00) Control Register */ + __I uint32_t Reserved1[3]; + __O uint32_t TRNG_IER; /**< \brief (Trng Offset: 0x10) Interrupt Enable Register */ + __O uint32_t TRNG_IDR; /**< \brief (Trng Offset: 0x14) Interrupt Disable Register */ + __I uint32_t TRNG_IMR; /**< \brief (Trng Offset: 0x18) Interrupt Mask Register */ + __I uint32_t TRNG_ISR; /**< \brief (Trng Offset: 0x1C) Interrupt Status Register */ + __I uint32_t Reserved2[12]; + __I uint32_t TRNG_ODATA; /**< \brief (Trng Offset: 0x50) Output Data Register */ + __I uint32_t Reserved3[42]; + __I uint32_t TRNG_VERSION; /**< \brief (Trng Offset: 0xFC) Version Register */ +} Trng; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TRNG_CR : (TRNG Offset: 0x00) Control Register -------- */ +#define TRNG_CR_ENABLE (0x1u << 0) /**< \brief (TRNG_CR) Enables the TRNG to provide random values */ +#define TRNG_CR_KEY_Pos 8 +#define TRNG_CR_KEY_Msk (0xffffffu << TRNG_CR_KEY_Pos) /**< \brief (TRNG_CR) Security Key. */ +#define TRNG_CR_KEY(value) ((TRNG_CR_KEY_Msk & ((value) << TRNG_CR_KEY_Pos))) +#define TRNG_CR_KEY_PASSWD (0x524E47u << 8) /**< \brief (TRNG_CR) Writing any other value in this field aborts the write operation. */ +/* -------- TRNG_IER : (TRNG Offset: 0x10) Interrupt Enable Register -------- */ +#define TRNG_IER_DATRDY (0x1u << 0) /**< \brief (TRNG_IER) Data Ready Interrupt Enable */ +/* -------- TRNG_IDR : (TRNG Offset: 0x14) Interrupt Disable Register -------- */ +#define TRNG_IDR_DATRDY (0x1u << 0) /**< \brief (TRNG_IDR) Data Ready Interrupt Disable */ +/* -------- TRNG_IMR : (TRNG Offset: 0x18) Interrupt Mask Register -------- */ +#define TRNG_IMR_DATRDY (0x1u << 0) /**< \brief (TRNG_IMR) Data Ready Interrupt Mask */ +/* -------- TRNG_ISR : (TRNG Offset: 0x1C) Interrupt Status Register -------- */ +#define TRNG_ISR_DATRDY (0x1u << 0) /**< \brief (TRNG_ISR) Data Ready */ +/* -------- TRNG_ODATA : (TRNG Offset: 0x50) Output Data Register -------- */ +#define TRNG_ODATA_ODATA_Pos 0 +#define TRNG_ODATA_ODATA_Msk (0xffffffffu << TRNG_ODATA_ODATA_Pos) /**< \brief (TRNG_ODATA) Output Data */ +/* -------- TRNG_VERSION : (TRNG Offset: 0xFC) Version Register -------- */ +#define TRNG_VERSION_VERSION_Pos 0 +#define TRNG_VERSION_VERSION_Msk (0xfffu << TRNG_VERSION_VERSION_Pos) /**< \brief (TRNG_VERSION) Version of the Hardware Module */ +#define TRNG_VERSION_MFN_Pos 16 +#define TRNG_VERSION_MFN_Msk (0x7u << TRNG_VERSION_MFN_Pos) /**< \brief (TRNG_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_TRNG_COMPONENT_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/twihs.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/twihs.h new file mode 100644 index 000000000..548854dc4 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/twihs.h @@ -0,0 +1,275 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_TWIHS_COMPONENT_ +#define _SAME70_TWIHS_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Two-wire Interface High Speed */ +/* ============================================================================= */ +/** \addtogroup SAME70_TWIHS Two-wire Interface High Speed */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Twihs hardware registers */ +typedef struct { + __O uint32_t TWIHS_CR; /**< \brief (Twihs Offset: 0x00) Control Register */ + __IO uint32_t TWIHS_MMR; /**< \brief (Twihs Offset: 0x04) Master Mode Register */ + __IO uint32_t TWIHS_SMR; /**< \brief (Twihs Offset: 0x08) Slave Mode Register */ + __IO uint32_t TWIHS_IADR; /**< \brief (Twihs Offset: 0x0C) Internal Address Register */ + __IO uint32_t TWIHS_CWGR; /**< \brief (Twihs Offset: 0x10) Clock Waveform Generator Register */ + __I uint32_t Reserved1[3]; + __I uint32_t TWIHS_SR; /**< \brief (Twihs Offset: 0x20) Status Register */ + __O uint32_t TWIHS_IER; /**< \brief (Twihs Offset: 0x24) Interrupt Enable Register */ + __O uint32_t TWIHS_IDR; /**< \brief (Twihs Offset: 0x28) Interrupt Disable Register */ + __I uint32_t TWIHS_IMR; /**< \brief (Twihs Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t TWIHS_RHR; /**< \brief (Twihs Offset: 0x30) Receive Holding Register */ + __O uint32_t TWIHS_THR; /**< \brief (Twihs Offset: 0x34) Transmit Holding Register */ + __IO uint32_t TWIHS_SMBTR; /**< \brief (Twihs Offset: 0x38) SMBus Timing Register */ + __I uint32_t Reserved2[2]; + __IO uint32_t TWIHS_FILTR; /**< \brief (Twihs Offset: 0x44) Filter Register */ + __I uint32_t Reserved3[1]; + __IO uint32_t TWIHS_SWMR; /**< \brief (Twihs Offset: 0x4C) SleepWalking Matching Register */ + __I uint32_t Reserved4[32]; + __I uint32_t TWIHS_DR; /**< \brief (Twihs Offset: 0xD0) Debug Register */ + __I uint32_t Reserved5[4]; + __IO uint32_t TWIHS_WPMR; /**< \brief (Twihs Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t TWIHS_WPSR; /**< \brief (Twihs Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved6[4]; + __I uint32_t TWIHS_VER; /**< \brief (Twihs Offset: 0xFC) Version Register */ +} Twihs; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TWIHS_CR : (TWIHS Offset: 0x00) Control Register -------- */ +#define TWIHS_CR_START (0x1u << 0) /**< \brief (TWIHS_CR) Send a START Condition */ +#define TWIHS_CR_STOP (0x1u << 1) /**< \brief (TWIHS_CR) Send a STOP Condition */ +#define TWIHS_CR_MSEN (0x1u << 2) /**< \brief (TWIHS_CR) TWIHS Master Mode Enabled */ +#define TWIHS_CR_MSDIS (0x1u << 3) /**< \brief (TWIHS_CR) TWIHS Master Mode Disabled */ +#define TWIHS_CR_SVEN (0x1u << 4) /**< \brief (TWIHS_CR) TWIHS Slave Mode Enabled */ +#define TWIHS_CR_SVDIS (0x1u << 5) /**< \brief (TWIHS_CR) TWIHS Slave Mode Disabled */ +#define TWIHS_CR_QUICK (0x1u << 6) /**< \brief (TWIHS_CR) SMBus Quick Command */ +#define TWIHS_CR_SWRST (0x1u << 7) /**< \brief (TWIHS_CR) Software Reset */ +#define TWIHS_CR_HSEN (0x1u << 8) /**< \brief (TWIHS_CR) TWIHS High-Speed Mode Enabled */ +#define TWIHS_CR_HSDIS (0x1u << 9) /**< \brief (TWIHS_CR) TWIHS High-Speed Mode Disabled */ +#define TWIHS_CR_SMBEN (0x1u << 10) /**< \brief (TWIHS_CR) SMBus Mode Enabled */ +#define TWIHS_CR_SMBDIS (0x1u << 11) /**< \brief (TWIHS_CR) SMBus Mode Disabled */ +#define TWIHS_CR_PECEN (0x1u << 12) /**< \brief (TWIHS_CR) Packet Error Checking Enable */ +#define TWIHS_CR_PECDIS (0x1u << 13) /**< \brief (TWIHS_CR) Packet Error Checking Disable */ +#define TWIHS_CR_PECRQ (0x1u << 14) /**< \brief (TWIHS_CR) PEC Request */ +#define TWIHS_CR_CLEAR (0x1u << 15) /**< \brief (TWIHS_CR) Bus CLEAR Command */ +#define TWIHS_CR_ACMEN (0x1u << 16) /**< \brief (TWIHS_CR) Alternative Command Mode Enable */ +#define TWIHS_CR_ACMDIS (0x1u << 17) /**< \brief (TWIHS_CR) Alternative Command Mode Disable */ +#define TWIHS_CR_THRCLR (0x1u << 24) /**< \brief (TWIHS_CR) Transmit Holding Register Clear */ +#define TWIHS_CR_LOCKCLR (0x1u << 26) /**< \brief (TWIHS_CR) Lock Clear */ +#define TWIHS_CR_FIFOEN (0x1u << 28) /**< \brief (TWIHS_CR) FIFO Enable */ +#define TWIHS_CR_FIFODIS (0x1u << 29) /**< \brief (TWIHS_CR) FIFO Disable */ +/* -------- TWIHS_MMR : (TWIHS Offset: 0x04) Master Mode Register -------- */ +#define TWIHS_MMR_IADRSZ_Pos 8 +#define TWIHS_MMR_IADRSZ_Msk (0x3u << TWIHS_MMR_IADRSZ_Pos) /**< \brief (TWIHS_MMR) Internal Device Address Size */ +#define TWIHS_MMR_IADRSZ(value) ((TWIHS_MMR_IADRSZ_Msk & ((value) << TWIHS_MMR_IADRSZ_Pos))) +#define TWIHS_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWIHS_MMR) No internal device address */ +#define TWIHS_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWIHS_MMR) One-byte internal device address */ +#define TWIHS_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWIHS_MMR) Two-byte internal device address */ +#define TWIHS_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWIHS_MMR) Three-byte internal device address */ +#define TWIHS_MMR_MREAD (0x1u << 12) /**< \brief (TWIHS_MMR) Master Read Direction */ +#define TWIHS_MMR_DADR_Pos 16 +#define TWIHS_MMR_DADR_Msk (0x7fu << TWIHS_MMR_DADR_Pos) /**< \brief (TWIHS_MMR) Device Address */ +#define TWIHS_MMR_DADR(value) ((TWIHS_MMR_DADR_Msk & ((value) << TWIHS_MMR_DADR_Pos))) +/* -------- TWIHS_SMR : (TWIHS Offset: 0x08) Slave Mode Register -------- */ +#define TWIHS_SMR_NACKEN (0x1u << 0) /**< \brief (TWIHS_SMR) Slave Receiver Data Phase NACK enable */ +#define TWIHS_SMR_SMDA (0x1u << 2) /**< \brief (TWIHS_SMR) SMBus Default Address */ +#define TWIHS_SMR_SMHH (0x1u << 3) /**< \brief (TWIHS_SMR) SMBus Host Header */ +#define TWIHS_SMR_SCLWSDIS (0x1u << 6) /**< \brief (TWIHS_SMR) Clock Wait State Disable */ +#define TWIHS_SMR_MASK_Pos 8 +#define TWIHS_SMR_MASK_Msk (0x7fu << TWIHS_SMR_MASK_Pos) /**< \brief (TWIHS_SMR) Slave Address Mask */ +#define TWIHS_SMR_MASK(value) ((TWIHS_SMR_MASK_Msk & ((value) << TWIHS_SMR_MASK_Pos))) +#define TWIHS_SMR_SADR_Pos 16 +#define TWIHS_SMR_SADR_Msk (0x7fu << TWIHS_SMR_SADR_Pos) /**< \brief (TWIHS_SMR) Slave Address */ +#define TWIHS_SMR_SADR(value) ((TWIHS_SMR_SADR_Msk & ((value) << TWIHS_SMR_SADR_Pos))) +#define TWIHS_SMR_SADR1EN (0x1u << 28) /**< \brief (TWIHS_SMR) Slave Address 1 Enable */ +#define TWIHS_SMR_SADR2EN (0x1u << 29) /**< \brief (TWIHS_SMR) Slave Address 2 Enable */ +#define TWIHS_SMR_SADR3EN (0x1u << 30) /**< \brief (TWIHS_SMR) Slave Address 3 Enable */ +#define TWIHS_SMR_DATAMEN (0x1u << 31) /**< \brief (TWIHS_SMR) Data Matching Enable */ +/* -------- TWIHS_IADR : (TWIHS Offset: 0x0C) Internal Address Register -------- */ +#define TWIHS_IADR_IADR_Pos 0 +#define TWIHS_IADR_IADR_Msk (0xffffffu << TWIHS_IADR_IADR_Pos) /**< \brief (TWIHS_IADR) Internal Address */ +#define TWIHS_IADR_IADR(value) ((TWIHS_IADR_IADR_Msk & ((value) << TWIHS_IADR_IADR_Pos))) +/* -------- TWIHS_CWGR : (TWIHS Offset: 0x10) Clock Waveform Generator Register -------- */ +#define TWIHS_CWGR_CLDIV_Pos 0 +#define TWIHS_CWGR_CLDIV_Msk (0xffu << TWIHS_CWGR_CLDIV_Pos) /**< \brief (TWIHS_CWGR) Clock Low Divider */ +#define TWIHS_CWGR_CLDIV(value) ((TWIHS_CWGR_CLDIV_Msk & ((value) << TWIHS_CWGR_CLDIV_Pos))) +#define TWIHS_CWGR_CHDIV_Pos 8 +#define TWIHS_CWGR_CHDIV_Msk (0xffu << TWIHS_CWGR_CHDIV_Pos) /**< \brief (TWIHS_CWGR) Clock High Divider */ +#define TWIHS_CWGR_CHDIV(value) ((TWIHS_CWGR_CHDIV_Msk & ((value) << TWIHS_CWGR_CHDIV_Pos))) +#define TWIHS_CWGR_CKDIV_Pos 16 +#define TWIHS_CWGR_CKDIV_Msk (0x7u << TWIHS_CWGR_CKDIV_Pos) /**< \brief (TWIHS_CWGR) Clock Divider */ +#define TWIHS_CWGR_CKDIV(value) ((TWIHS_CWGR_CKDIV_Msk & ((value) << TWIHS_CWGR_CKDIV_Pos))) +#define TWIHS_CWGR_HOLD_Pos 24 +#define TWIHS_CWGR_HOLD_Msk (0x3fu << TWIHS_CWGR_HOLD_Pos) /**< \brief (TWIHS_CWGR) TWD Hold Time Versus TWCK Falling */ +#define TWIHS_CWGR_HOLD(value) ((TWIHS_CWGR_HOLD_Msk & ((value) << TWIHS_CWGR_HOLD_Pos))) +/* -------- TWIHS_SR : (TWIHS Offset: 0x20) Status Register -------- */ +#define TWIHS_SR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_SR) Transmission Completed (cleared by writing TWIHS_THR) */ +#define TWIHS_SR_RXRDY (0x1u << 1) /**< \brief (TWIHS_SR) Receive Holding Register Ready (cleared by reading TWIHS_RHR) */ +#define TWIHS_SR_TXRDY (0x1u << 2) /**< \brief (TWIHS_SR) Transmit Holding Register Ready (cleared by writing TWIHS_THR) */ +#define TWIHS_SR_SVREAD (0x1u << 3) /**< \brief (TWIHS_SR) Slave Read */ +#define TWIHS_SR_SVACC (0x1u << 4) /**< \brief (TWIHS_SR) Slave Access */ +#define TWIHS_SR_GACC (0x1u << 5) /**< \brief (TWIHS_SR) General Call Access (cleared on read) */ +#define TWIHS_SR_OVRE (0x1u << 6) /**< \brief (TWIHS_SR) Overrun Error (cleared on read) */ +#define TWIHS_SR_UNRE (0x1u << 7) /**< \brief (TWIHS_SR) Underrun Error (cleared on read) */ +#define TWIHS_SR_NACK (0x1u << 8) /**< \brief (TWIHS_SR) Not Acknowledged (cleared on read) */ +#define TWIHS_SR_ARBLST (0x1u << 9) /**< \brief (TWIHS_SR) Arbitration Lost (cleared on read) */ +#define TWIHS_SR_SCLWS (0x1u << 10) /**< \brief (TWIHS_SR) Clock Wait State */ +#define TWIHS_SR_EOSACC (0x1u << 11) /**< \brief (TWIHS_SR) End Of Slave Access (cleared on read) */ +#define TWIHS_SR_MCACK (0x1u << 16) /**< \brief (TWIHS_SR) Master Code Acknowledge (cleared on read) */ +#define TWIHS_SR_TOUT (0x1u << 18) /**< \brief (TWIHS_SR) Timeout Error (cleared on read) */ +#define TWIHS_SR_PECERR (0x1u << 19) /**< \brief (TWIHS_SR) PEC Error (cleared on read) */ +#define TWIHS_SR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_SR) SMBus Default Address Match (cleared on read) */ +#define TWIHS_SR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_SR) SMBus Host Header Address Match (cleared on read) */ +#define TWIHS_SR_SCL (0x1u << 24) /**< \brief (TWIHS_SR) SCL line value */ +#define TWIHS_SR_SDA (0x1u << 25) /**< \brief (TWIHS_SR) SDA line value */ +/* -------- TWIHS_IER : (TWIHS Offset: 0x24) Interrupt Enable Register -------- */ +#define TWIHS_IER_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IER) Transmission Completed Interrupt Enable */ +#define TWIHS_IER_RXRDY (0x1u << 1) /**< \brief (TWIHS_IER) Receive Holding Register Ready Interrupt Enable */ +#define TWIHS_IER_TXRDY (0x1u << 2) /**< \brief (TWIHS_IER) Transmit Holding Register Ready Interrupt Enable */ +#define TWIHS_IER_SVACC (0x1u << 4) /**< \brief (TWIHS_IER) Slave Access Interrupt Enable */ +#define TWIHS_IER_GACC (0x1u << 5) /**< \brief (TWIHS_IER) General Call Access Interrupt Enable */ +#define TWIHS_IER_OVRE (0x1u << 6) /**< \brief (TWIHS_IER) Overrun Error Interrupt Enable */ +#define TWIHS_IER_UNRE (0x1u << 7) /**< \brief (TWIHS_IER) Underrun Error Interrupt Enable */ +#define TWIHS_IER_NACK (0x1u << 8) /**< \brief (TWIHS_IER) Not Acknowledge Interrupt Enable */ +#define TWIHS_IER_ARBLST (0x1u << 9) /**< \brief (TWIHS_IER) Arbitration Lost Interrupt Enable */ +#define TWIHS_IER_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IER) Clock Wait State Interrupt Enable */ +#define TWIHS_IER_EOSACC (0x1u << 11) /**< \brief (TWIHS_IER) End Of Slave Access Interrupt Enable */ +#define TWIHS_IER_MCACK (0x1u << 16) /**< \brief (TWIHS_IER) Master Code Acknowledge Interrupt Enable */ +#define TWIHS_IER_TOUT (0x1u << 18) /**< \brief (TWIHS_IER) Timeout Error Interrupt Enable */ +#define TWIHS_IER_PECERR (0x1u << 19) /**< \brief (TWIHS_IER) PEC Error Interrupt Enable */ +#define TWIHS_IER_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IER) SMBus Default Address Match Interrupt Enable */ +#define TWIHS_IER_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IER) SMBus Host Header Address Match Interrupt Enable */ +/* -------- TWIHS_IDR : (TWIHS Offset: 0x28) Interrupt Disable Register -------- */ +#define TWIHS_IDR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IDR) Transmission Completed Interrupt Disable */ +#define TWIHS_IDR_RXRDY (0x1u << 1) /**< \brief (TWIHS_IDR) Receive Holding Register Ready Interrupt Disable */ +#define TWIHS_IDR_TXRDY (0x1u << 2) /**< \brief (TWIHS_IDR) Transmit Holding Register Ready Interrupt Disable */ +#define TWIHS_IDR_SVACC (0x1u << 4) /**< \brief (TWIHS_IDR) Slave Access Interrupt Disable */ +#define TWIHS_IDR_GACC (0x1u << 5) /**< \brief (TWIHS_IDR) General Call Access Interrupt Disable */ +#define TWIHS_IDR_OVRE (0x1u << 6) /**< \brief (TWIHS_IDR) Overrun Error Interrupt Disable */ +#define TWIHS_IDR_UNRE (0x1u << 7) /**< \brief (TWIHS_IDR) Underrun Error Interrupt Disable */ +#define TWIHS_IDR_NACK (0x1u << 8) /**< \brief (TWIHS_IDR) Not Acknowledge Interrupt Disable */ +#define TWIHS_IDR_ARBLST (0x1u << 9) /**< \brief (TWIHS_IDR) Arbitration Lost Interrupt Disable */ +#define TWIHS_IDR_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IDR) Clock Wait State Interrupt Disable */ +#define TWIHS_IDR_EOSACC (0x1u << 11) /**< \brief (TWIHS_IDR) End Of Slave Access Interrupt Disable */ +#define TWIHS_IDR_MCACK (0x1u << 16) /**< \brief (TWIHS_IDR) Master Code Acknowledge Interrupt Disable */ +#define TWIHS_IDR_TOUT (0x1u << 18) /**< \brief (TWIHS_IDR) Timeout Error Interrupt Disable */ +#define TWIHS_IDR_PECERR (0x1u << 19) /**< \brief (TWIHS_IDR) PEC Error Interrupt Disable */ +#define TWIHS_IDR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IDR) SMBus Default Address Match Interrupt Disable */ +#define TWIHS_IDR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IDR) SMBus Host Header Address Match Interrupt Disable */ +/* -------- TWIHS_IMR : (TWIHS Offset: 0x2C) Interrupt Mask Register -------- */ +#define TWIHS_IMR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IMR) Transmission Completed Interrupt Mask */ +#define TWIHS_IMR_RXRDY (0x1u << 1) /**< \brief (TWIHS_IMR) Receive Holding Register Ready Interrupt Mask */ +#define TWIHS_IMR_TXRDY (0x1u << 2) /**< \brief (TWIHS_IMR) Transmit Holding Register Ready Interrupt Mask */ +#define TWIHS_IMR_SVACC (0x1u << 4) /**< \brief (TWIHS_IMR) Slave Access Interrupt Mask */ +#define TWIHS_IMR_GACC (0x1u << 5) /**< \brief (TWIHS_IMR) General Call Access Interrupt Mask */ +#define TWIHS_IMR_OVRE (0x1u << 6) /**< \brief (TWIHS_IMR) Overrun Error Interrupt Mask */ +#define TWIHS_IMR_UNRE (0x1u << 7) /**< \brief (TWIHS_IMR) Underrun Error Interrupt Mask */ +#define TWIHS_IMR_NACK (0x1u << 8) /**< \brief (TWIHS_IMR) Not Acknowledge Interrupt Mask */ +#define TWIHS_IMR_ARBLST (0x1u << 9) /**< \brief (TWIHS_IMR) Arbitration Lost Interrupt Mask */ +#define TWIHS_IMR_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IMR) Clock Wait State Interrupt Mask */ +#define TWIHS_IMR_EOSACC (0x1u << 11) /**< \brief (TWIHS_IMR) End Of Slave Access Interrupt Mask */ +#define TWIHS_IMR_MCACK (0x1u << 16) /**< \brief (TWIHS_IMR) Master Code Acknowledge Interrupt Mask */ +#define TWIHS_IMR_TOUT (0x1u << 18) /**< \brief (TWIHS_IMR) Timeout Error Interrupt Mask */ +#define TWIHS_IMR_PECERR (0x1u << 19) /**< \brief (TWIHS_IMR) PEC Error Interrupt Mask */ +#define TWIHS_IMR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IMR) SMBus Default Address Match Interrupt Mask */ +#define TWIHS_IMR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IMR) SMBus Host Header Address Match Interrupt Mask */ +/* -------- TWIHS_RHR : (TWIHS Offset: 0x30) Receive Holding Register -------- */ +#define TWIHS_RHR_RXDATA_Pos 0 +#define TWIHS_RHR_RXDATA_Msk (0xffu << TWIHS_RHR_RXDATA_Pos) /**< \brief (TWIHS_RHR) Master or Slave Receive Holding Data */ +/* -------- TWIHS_THR : (TWIHS Offset: 0x34) Transmit Holding Register -------- */ +#define TWIHS_THR_TXDATA_Pos 0 +#define TWIHS_THR_TXDATA_Msk (0xffu << TWIHS_THR_TXDATA_Pos) /**< \brief (TWIHS_THR) Master or Slave Transmit Holding Data */ +#define TWIHS_THR_TXDATA(value) ((TWIHS_THR_TXDATA_Msk & ((value) << TWIHS_THR_TXDATA_Pos))) +/* -------- TWIHS_SMBTR : (TWIHS Offset: 0x38) SMBus Timing Register -------- */ +#define TWIHS_SMBTR_PRESC_Pos 0 +#define TWIHS_SMBTR_PRESC_Msk (0xfu << TWIHS_SMBTR_PRESC_Pos) /**< \brief (TWIHS_SMBTR) SMBus Clock Prescaler */ +#define TWIHS_SMBTR_PRESC(value) ((TWIHS_SMBTR_PRESC_Msk & ((value) << TWIHS_SMBTR_PRESC_Pos))) +#define TWIHS_SMBTR_TLOWS_Pos 8 +#define TWIHS_SMBTR_TLOWS_Msk (0xffu << TWIHS_SMBTR_TLOWS_Pos) /**< \brief (TWIHS_SMBTR) Slave Clock Stretch Maximum Cycles */ +#define TWIHS_SMBTR_TLOWS(value) ((TWIHS_SMBTR_TLOWS_Msk & ((value) << TWIHS_SMBTR_TLOWS_Pos))) +#define TWIHS_SMBTR_TLOWM_Pos 16 +#define TWIHS_SMBTR_TLOWM_Msk (0xffu << TWIHS_SMBTR_TLOWM_Pos) /**< \brief (TWIHS_SMBTR) Master Clock Stretch Maximum Cycles */ +#define TWIHS_SMBTR_TLOWM(value) ((TWIHS_SMBTR_TLOWM_Msk & ((value) << TWIHS_SMBTR_TLOWM_Pos))) +#define TWIHS_SMBTR_THMAX_Pos 24 +#define TWIHS_SMBTR_THMAX_Msk (0xffu << TWIHS_SMBTR_THMAX_Pos) /**< \brief (TWIHS_SMBTR) Clock High Maximum Cycles */ +#define TWIHS_SMBTR_THMAX(value) ((TWIHS_SMBTR_THMAX_Msk & ((value) << TWIHS_SMBTR_THMAX_Pos))) +/* -------- TWIHS_FILTR : (TWIHS Offset: 0x44) Filter Register -------- */ +#define TWIHS_FILTR_FILT (0x1u << 0) /**< \brief (TWIHS_FILTR) RX Digital Filter */ +#define TWIHS_FILTR_PADFEN (0x1u << 1) /**< \brief (TWIHS_FILTR) PAD Filter Enable */ +#define TWIHS_FILTR_PADFCFG (0x1u << 2) /**< \brief (TWIHS_FILTR) PAD Filter Config */ +#define TWIHS_FILTR_THRES_Pos 8 +#define TWIHS_FILTR_THRES_Msk (0x7u << TWIHS_FILTR_THRES_Pos) /**< \brief (TWIHS_FILTR) Digital Filter Threshold */ +#define TWIHS_FILTR_THRES(value) ((TWIHS_FILTR_THRES_Msk & ((value) << TWIHS_FILTR_THRES_Pos))) +/* -------- TWIHS_SWMR : (TWIHS Offset: 0x4C) SleepWalking Matching Register -------- */ +#define TWIHS_SWMR_SADR1_Pos 0 +#define TWIHS_SWMR_SADR1_Msk (0x7fu << TWIHS_SWMR_SADR1_Pos) /**< \brief (TWIHS_SWMR) Slave Address 1 */ +#define TWIHS_SWMR_SADR1(value) ((TWIHS_SWMR_SADR1_Msk & ((value) << TWIHS_SWMR_SADR1_Pos))) +#define TWIHS_SWMR_SADR2_Pos 8 +#define TWIHS_SWMR_SADR2_Msk (0x7fu << TWIHS_SWMR_SADR2_Pos) /**< \brief (TWIHS_SWMR) Slave Address 2 */ +#define TWIHS_SWMR_SADR2(value) ((TWIHS_SWMR_SADR2_Msk & ((value) << TWIHS_SWMR_SADR2_Pos))) +#define TWIHS_SWMR_SADR3_Pos 16 +#define TWIHS_SWMR_SADR3_Msk (0x7fu << TWIHS_SWMR_SADR3_Pos) /**< \brief (TWIHS_SWMR) Slave Address 3 */ +#define TWIHS_SWMR_SADR3(value) ((TWIHS_SWMR_SADR3_Msk & ((value) << TWIHS_SWMR_SADR3_Pos))) +#define TWIHS_SWMR_DATAM_Pos 24 +#define TWIHS_SWMR_DATAM_Msk (0xffu << TWIHS_SWMR_DATAM_Pos) /**< \brief (TWIHS_SWMR) Data Match */ +#define TWIHS_SWMR_DATAM(value) ((TWIHS_SWMR_DATAM_Msk & ((value) << TWIHS_SWMR_DATAM_Pos))) +/* -------- TWIHS_DR : (TWIHS Offset: 0xD0) Debug Register -------- */ +#define TWIHS_DR_SWEN (0x1u << 0) /**< \brief (TWIHS_DR) SleepWalking Enable */ +#define TWIHS_DR_CLKRQ (0x1u << 1) /**< \brief (TWIHS_DR) Clock Request */ +#define TWIHS_DR_SWMATCH (0x1u << 2) /**< \brief (TWIHS_DR) SleepWalking Match */ +#define TWIHS_DR_TRP (0x1u << 3) /**< \brief (TWIHS_DR) Transfer Pending */ +/* -------- TWIHS_WPMR : (TWIHS Offset: 0xE4) Write Protection Mode Register -------- */ +#define TWIHS_WPMR_WPEN (0x1u << 0) /**< \brief (TWIHS_WPMR) Write Protection Enable */ +#define TWIHS_WPMR_WPKEY_Pos 8 +#define TWIHS_WPMR_WPKEY_Msk (0xffffffu << TWIHS_WPMR_WPKEY_Pos) /**< \brief (TWIHS_WPMR) Write Protection Key */ +#define TWIHS_WPMR_WPKEY(value) ((TWIHS_WPMR_WPKEY_Msk & ((value) << TWIHS_WPMR_WPKEY_Pos))) +#define TWIHS_WPMR_WPKEY_PASSWD (0x545749u << 8) /**< \brief (TWIHS_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 */ +/* -------- TWIHS_WPSR : (TWIHS Offset: 0xE8) Write Protection Status Register -------- */ +#define TWIHS_WPSR_WPVS (0x1u << 0) /**< \brief (TWIHS_WPSR) Write Protection Violation Status */ +#define TWIHS_WPSR_WPVSRC_Pos 8 +#define TWIHS_WPSR_WPVSRC_Msk (0xffffffu << TWIHS_WPSR_WPVSRC_Pos) /**< \brief (TWIHS_WPSR) Write Protection Violation Source */ +/* -------- TWIHS_VER : (TWIHS Offset: 0xFC) Version Register -------- */ +#define TWIHS_VER_VERSION_Pos 0 +#define TWIHS_VER_VERSION_Msk (0xfffu << TWIHS_VER_VERSION_Pos) /**< \brief (TWIHS_VER) Version of the Hardware Module */ +#define TWIHS_VER_MFN_Pos 16 +#define TWIHS_VER_MFN_Msk (0x7u << TWIHS_VER_MFN_Pos) /**< \brief (TWIHS_VER) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_TWIHS_COMPONENT_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/uart.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/uart.h new file mode 100644 index 000000000..b9d81010b --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/uart.h @@ -0,0 +1,167 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_UART_COMPONENT_ +#define _SAME70_UART_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */ +/* ============================================================================= */ +/** \addtogroup SAME70_UART Universal Asynchronous Receiver Transmitter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Uart hardware registers */ +typedef struct { + __O uint32_t UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */ + __IO uint32_t UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */ + __O uint32_t UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */ + __O uint32_t UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */ + __I uint32_t UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */ + __I uint32_t UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */ + __I uint32_t UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */ + __O uint32_t UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */ + __IO uint32_t UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */ + __IO uint32_t UART_CMPR; /**< \brief (Uart Offset: 0x0024) Comparison Register */ + __I uint32_t Reserved1[47]; + __IO uint32_t UART_WPMR; /**< \brief (Uart Offset: 0x00E4) Write Protection Mode Register */ + __I uint32_t Reserved2[5]; + __I uint32_t UART_VERSION; /**< \brief (Uart Offset: 0x00FC) Version Register */ +} Uart; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */ +#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */ +#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */ +#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */ +#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */ +#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */ +#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */ +#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status */ +#define UART_CR_REQCLR (0x1u << 12) /**< \brief (UART_CR) Request Clear */ +#define UART_CR_DBGE (0x1u << 15) /**< \brief (UART_CR) Debug Enable */ +/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */ +#define UART_MR_FILTER (0x1u << 4) /**< \brief (UART_MR) Receiver Digital Filter */ +#define UART_MR_FILTER_DISABLED (0x0u << 4) /**< \brief (UART_MR) UART does not filter the receive line. */ +#define UART_MR_FILTER_ENABLED (0x1u << 4) /**< \brief (UART_MR) UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). */ +#define UART_MR_PAR_Pos 9 +#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */ +#define UART_MR_PAR(value) ((UART_MR_PAR_Msk & ((value) << UART_MR_PAR_Pos))) +#define UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even Parity */ +#define UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd Parity */ +#define UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */ +#define UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */ +#define UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */ +#define UART_MR_BRSRCCK (0x1u << 12) /**< \brief (UART_MR) Baud Rate Source Clock */ +#define UART_MR_BRSRCCK_PERIPH_CLK (0x0u << 12) /**< \brief (UART_MR) The baud rate is driven by the peripheral clock */ +#define UART_MR_BRSRCCK_PMC_PCK (0x1u << 12) /**< \brief (UART_MR) The baud rate is driven by a PMC programmable clock PCK (see section Power Management Controller (PMC)). */ +#define UART_MR_CHMODE_Pos 14 +#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */ +#define UART_MR_CHMODE(value) ((UART_MR_CHMODE_Msk & ((value) << UART_MR_CHMODE_Pos))) +#define UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal mode */ +#define UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic echo */ +#define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local loopback */ +#define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote loopback */ +/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */ +#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */ +#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */ +#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */ +#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */ +#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */ +#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */ +#define UART_IER_CMP (0x1u << 15) /**< \brief (UART_IER) Enable Comparison Interrupt */ +/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */ +#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */ +#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */ +#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */ +#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */ +#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */ +#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */ +#define UART_IDR_CMP (0x1u << 15) /**< \brief (UART_IDR) Disable Comparison Interrupt */ +/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */ +#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */ +#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */ +#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */ +#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */ +#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */ +#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */ +#define UART_IMR_CMP (0x1u << 15) /**< \brief (UART_IMR) Mask Comparison Interrupt */ +/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */ +#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */ +#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */ +#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */ +#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */ +#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */ +#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */ +#define UART_SR_CMP (0x1u << 15) /**< \brief (UART_SR) Comparison Match */ +#define UART_SR_SWES (0x1u << 21) /**< \brief (UART_SR) SleepWalking Enable Status */ +#define UART_SR_CLKREQ (0x1u << 22) /**< \brief (UART_SR) Clock Request */ +#define UART_SR_WKUPREQ (0x1u << 23) /**< \brief (UART_SR) Wake-Up Request */ +/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */ +#define UART_RHR_RXCHR_Pos 0 +#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */ +/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */ +#define UART_THR_TXCHR_Pos 0 +#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */ +#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos))) +/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */ +#define UART_BRGR_CD_Pos 0 +#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */ +#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos))) +/* -------- UART_CMPR : (UART Offset: 0x0024) Comparison Register -------- */ +#define UART_CMPR_VAL1_Pos 0 +#define UART_CMPR_VAL1_Msk (0xffu << UART_CMPR_VAL1_Pos) /**< \brief (UART_CMPR) First Comparison Value for Received Character */ +#define UART_CMPR_VAL1(value) ((UART_CMPR_VAL1_Msk & ((value) << UART_CMPR_VAL1_Pos))) +#define UART_CMPR_CMPMODE (0x1u << 12) /**< \brief (UART_CMPR) Comparison Mode */ +#define UART_CMPR_CMPMODE_FLAG_ONLY (0x0u << 12) /**< \brief (UART_CMPR) Any character is received and comparison function drives CMP flag. */ +#define UART_CMPR_CMPMODE_START_CONDITION (0x1u << 12) /**< \brief (UART_CMPR) Comparison condition must be met to start reception. */ +#define UART_CMPR_CMPPAR (0x1u << 14) /**< \brief (UART_CMPR) Compare Parity */ +#define UART_CMPR_VAL2_Pos 16 +#define UART_CMPR_VAL2_Msk (0xffu << UART_CMPR_VAL2_Pos) /**< \brief (UART_CMPR) Second Comparison Value for Received Character */ +#define UART_CMPR_VAL2(value) ((UART_CMPR_VAL2_Msk & ((value) << UART_CMPR_VAL2_Pos))) +/* -------- UART_WPMR : (UART Offset: 0x00E4) Write Protection Mode Register -------- */ +#define UART_WPMR_WPEN (0x1u << 0) /**< \brief (UART_WPMR) Write Protection Enable */ +#define UART_WPMR_WPKEY_Pos 8 +#define UART_WPMR_WPKEY_Msk (0xffffffu << UART_WPMR_WPKEY_Pos) /**< \brief (UART_WPMR) Write Protection Key */ +#define UART_WPMR_WPKEY(value) ((UART_WPMR_WPKEY_Msk & ((value) << UART_WPMR_WPKEY_Pos))) +#define UART_WPMR_WPKEY_PASSWD (0x554152u << 8) /**< \brief (UART_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */ +/* -------- UART_VERSION : (UART Offset: 0x00FC) Version Register -------- */ +#define UART_VERSION_VERSION_Pos 0 +#define UART_VERSION_VERSION_Msk (0xfffu << UART_VERSION_VERSION_Pos) /**< \brief (UART_VERSION) Hardware Module Version */ +#define UART_VERSION_MFN_Pos 16 +#define UART_VERSION_MFN_Msk (0x7u << UART_VERSION_MFN_Pos) /**< \brief (UART_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_UART_COMPONENT_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/usart.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/usart.h new file mode 100644 index 000000000..6785c9b48 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/usart.h @@ -0,0 +1,492 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_USART_COMPONENT_ +#define _SAME70_USART_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */ +/* ============================================================================= */ +/** \addtogroup SAME70_USART Universal Synchronous Asynchronous Receiver Transmitter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Usart hardware registers */ +typedef struct { + __O uint32_t US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */ + __IO uint32_t US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */ + __O uint32_t US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */ + __O uint32_t US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */ + __I uint32_t US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */ + __I uint32_t US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */ + __I uint32_t US_RHR; /**< \brief (Usart Offset: 0x0018) Receive Holding Register */ + __O uint32_t US_THR; /**< \brief (Usart Offset: 0x001C) Transmit Holding Register */ + __IO uint32_t US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */ + __IO uint32_t US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */ + __IO uint32_t US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */ + __I uint32_t Reserved1[5]; + __IO uint32_t US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */ + __I uint32_t US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */ + __IO uint32_t US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Configuration Register */ + __IO uint32_t US_LINMR; /**< \brief (Usart Offset: 0x0054) LIN Mode Register */ + __IO uint32_t US_LINIR; /**< \brief (Usart Offset: 0x0058) LIN Identifier Register */ + __I uint32_t US_LINBRR; /**< \brief (Usart Offset: 0x005C) LIN Baud Rate Register */ + __IO uint32_t US_LONMR; /**< \brief (Usart Offset: 0x0060) LON Mode Register */ + __IO uint32_t US_LONPR; /**< \brief (Usart Offset: 0x0064) LON Preamble Register */ + __IO uint32_t US_LONDL; /**< \brief (Usart Offset: 0x0068) LON Data Length Register */ + __IO uint32_t US_LONL2HDR; /**< \brief (Usart Offset: 0x006C) LON L2HDR Register */ + __I uint32_t US_LONBL; /**< \brief (Usart Offset: 0x0070) LON Backlog Register */ + __IO uint32_t US_LONB1TX; /**< \brief (Usart Offset: 0x0074) LON Beta1 Tx Register */ + __IO uint32_t US_LONB1RX; /**< \brief (Usart Offset: 0x0078) LON Beta1 Rx Register */ + __IO uint32_t US_LONPRIO; /**< \brief (Usart Offset: 0x007C) LON Priority Register */ + __IO uint32_t US_IDTTX; /**< \brief (Usart Offset: 0x0080) LON IDT Tx Register */ + __IO uint32_t US_IDTRX; /**< \brief (Usart Offset: 0x0084) LON IDT Rx Register */ + __IO uint32_t US_ICDIFF; /**< \brief (Usart Offset: 0x0088) IC DIFF Register */ + __I uint32_t Reserved3[22]; + __IO uint32_t US_WPMR; /**< \brief (Usart Offset: 0x00E4) Write Protection Mode Register */ + __I uint32_t US_WPSR; /**< \brief (Usart Offset: 0x00E8) Write Protection Status Register */ + __I uint32_t Reserved4[4]; + __I uint32_t US_VERSION; /**< \brief (Usart Offset: 0x00FC) Version Register */ +} Usart; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */ +#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */ +#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */ +#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */ +#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */ +#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */ +#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */ +#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */ +#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */ +#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */ +#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Clear TIMEOUT Flag and Start Time-out After Next Character Received */ +#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */ +#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */ +#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */ +#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Start Time-out Immediately */ +#define US_CR_DTREN (0x1u << 16) /**< \brief (US_CR) Data Terminal Ready Enable */ +#define US_CR_DTRDIS (0x1u << 17) /**< \brief (US_CR) Data Terminal Ready Disable */ +#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Pin Control */ +#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Pin Control */ +#define US_CR_LINABT (0x1u << 20) /**< \brief (US_CR) Abort LIN Transmission */ +#define US_CR_LINWKUP (0x1u << 21) /**< \brief (US_CR) Send LIN Wakeup Signal */ +#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */ +#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */ +/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */ +#define US_MR_USART_MODE_Pos 0 +#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR) USART Mode of Operation */ +#define US_MR_USART_MODE(value) ((US_MR_USART_MODE_Msk & ((value) << US_MR_USART_MODE_Pos))) +#define US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */ +#define US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */ +#define US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */ +#define US_MR_USART_MODE_MODEM (0x3u << 0) /**< \brief (US_MR) Modem */ +#define US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */ +#define US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */ +#define US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */ +#define US_MR_USART_MODE_LON (0x9u << 0) /**< \brief (US_MR) LON */ +#define US_MR_USART_MODE_LIN_MASTER (0xAu << 0) /**< \brief (US_MR) LIN Master mode */ +#define US_MR_USART_MODE_LIN_SLAVE (0xBu << 0) /**< \brief (US_MR) LIN Slave mode */ +#define US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI master mode (CLKO must be written to 1 and USCLKS = 0, 1 or 2) */ +#define US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave mode */ +#define US_MR_USCLKS_Pos 4 +#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */ +#define US_MR_USCLKS(value) ((US_MR_USCLKS_Msk & ((value) << US_MR_USCLKS_Pos))) +#define US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Peripheral clock is selected */ +#define US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Peripheral clock divided (DIV=DIV=8) is selected */ +#define US_MR_USCLKS_PCK (0x2u << 4) /**< \brief (US_MR) PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1. */ +#define US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial clock (SCK) is selected */ +#define US_MR_CHRL_Pos 6 +#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length */ +#define US_MR_CHRL(value) ((US_MR_CHRL_Msk & ((value) << US_MR_CHRL_Pos))) +#define US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */ +#define US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */ +#define US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */ +#define US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */ +#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */ +#define US_MR_PAR_Pos 9 +#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */ +#define US_MR_PAR(value) ((US_MR_PAR_Msk & ((value) << US_MR_PAR_Pos))) +#define US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */ +#define US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */ +#define US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */ +#define US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */ +#define US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */ +#define US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */ +#define US_MR_NBSTOP_Pos 12 +#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */ +#define US_MR_NBSTOP(value) ((US_MR_NBSTOP_Msk & ((value) << US_MR_NBSTOP_Pos))) +#define US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */ +#define US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */ +#define US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */ +#define US_MR_CHMODE_Pos 14 +#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */ +#define US_MR_CHMODE(value) ((US_MR_CHMODE_Msk & ((value) << US_MR_CHMODE_Pos))) +#define US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal mode */ +#define US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */ +#define US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */ +#define US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */ +#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */ +#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */ +#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */ +#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */ +#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */ +#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */ +#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */ +#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) Inverted Data */ +#define US_MR_MAX_ITERATION_Pos 24 +#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR) Maximum Number of Automatic Iteration */ +#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos))) +#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Receive Line Filter */ +#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */ +#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */ +#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */ +#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */ +#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */ +#define US_MR_WRDBT (0x1u << 20) /**< \brief (US_MR) Wait Read Data Before Transfer */ +/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */ +#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */ +#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */ +#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */ +#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */ +#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */ +#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */ +#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */ +#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */ +#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached Interrupt Enable */ +#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non Acknowledge Interrupt Enable */ +#define US_IER_RIIC (0x1u << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */ +#define US_IER_DSRIC (0x1u << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */ +#define US_IER_DCDIC (0x1u << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */ +#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */ +#define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */ +#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error Interrupt Enable */ +#define US_IER_NSSE (0x1u << 19) /**< \brief (US_IER) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Enable */ +#define US_IER_LINBK (0x1u << 13) /**< \brief (US_IER) LIN Break Sent or LIN Break Received Interrupt Enable */ +#define US_IER_LINID (0x1u << 14) /**< \brief (US_IER) LIN Identifier Sent or LIN Identifier Received Interrupt Enable */ +#define US_IER_LINTC (0x1u << 15) /**< \brief (US_IER) LIN Transfer Completed Interrupt Enable */ +#define US_IER_LINBE (0x1u << 25) /**< \brief (US_IER) LIN Bus Error Interrupt Enable */ +#define US_IER_LINISFE (0x1u << 26) /**< \brief (US_IER) LIN Inconsistent Synch Field Error Interrupt Enable */ +#define US_IER_LINIPE (0x1u << 27) /**< \brief (US_IER) LIN Identifier Parity Interrupt Enable */ +#define US_IER_LINCE (0x1u << 28) /**< \brief (US_IER) LIN Checksum Error Interrupt Enable */ +#define US_IER_LINSNRE (0x1u << 29) /**< \brief (US_IER) LIN Slave Not Responding Error Interrupt Enable */ +#define US_IER_LINSTE (0x1u << 30) /**< \brief (US_IER) LIN Synch Tolerance Error Interrupt Enable */ +#define US_IER_LINHTE (0x1u << 31) /**< \brief (US_IER) LIN Header Timeout Error Interrupt Enable */ +#define US_IER_LSFE (0x1u << 6) /**< \brief (US_IER) LON Short Frame Error Interrupt Enable */ +#define US_IER_LCRCE (0x1u << 7) /**< \brief (US_IER) LON CRC Error Interrupt Enable */ +#define US_IER_LTXD (0x1u << 24) /**< \brief (US_IER) LON Transmission Done Interrupt Enable */ +#define US_IER_LCOL (0x1u << 25) /**< \brief (US_IER) LON Collision Interrupt Enable */ +#define US_IER_LFET (0x1u << 26) /**< \brief (US_IER) LON Frame Early Termination Interrupt Enable */ +#define US_IER_LRXD (0x1u << 27) /**< \brief (US_IER) LON Reception Done Interrupt Enable */ +#define US_IER_LBLOVFE (0x1u << 28) /**< \brief (US_IER) LON Backlog Overflow Error Interrupt Enable */ +/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */ +#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */ +#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */ +#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */ +#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Enable */ +#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */ +#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */ +#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */ +#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */ +#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max Number of Repetitions Reached Interrupt Disable */ +#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non Acknowledge Interrupt Disable */ +#define US_IDR_RIIC (0x1u << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */ +#define US_IDR_DSRIC (0x1u << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */ +#define US_IDR_DCDIC (0x1u << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */ +#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */ +#define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */ +#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Interrupt Disable */ +#define US_IDR_NSSE (0x1u << 19) /**< \brief (US_IDR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Disable */ +#define US_IDR_LINBK (0x1u << 13) /**< \brief (US_IDR) LIN Break Sent or LIN Break Received Interrupt Disable */ +#define US_IDR_LINID (0x1u << 14) /**< \brief (US_IDR) LIN Identifier Sent or LIN Identifier Received Interrupt Disable */ +#define US_IDR_LINTC (0x1u << 15) /**< \brief (US_IDR) LIN Transfer Completed Interrupt Disable */ +#define US_IDR_LINBE (0x1u << 25) /**< \brief (US_IDR) LIN Bus Error Interrupt Disable */ +#define US_IDR_LINISFE (0x1u << 26) /**< \brief (US_IDR) LIN Inconsistent Synch Field Error Interrupt Disable */ +#define US_IDR_LINIPE (0x1u << 27) /**< \brief (US_IDR) LIN Identifier Parity Interrupt Disable */ +#define US_IDR_LINCE (0x1u << 28) /**< \brief (US_IDR) LIN Checksum Error Interrupt Disable */ +#define US_IDR_LINSNRE (0x1u << 29) /**< \brief (US_IDR) LIN Slave Not Responding Error Interrupt Disable */ +#define US_IDR_LINSTE (0x1u << 30) /**< \brief (US_IDR) LIN Synch Tolerance Error Interrupt Disable */ +#define US_IDR_LINHTE (0x1u << 31) /**< \brief (US_IDR) LIN Header Timeout Error Interrupt Disable */ +#define US_IDR_LSFE (0x1u << 6) /**< \brief (US_IDR) LON Short Frame Error Interrupt Disable */ +#define US_IDR_LCRCE (0x1u << 7) /**< \brief (US_IDR) LON CRC Error Interrupt Disable */ +#define US_IDR_LTXD (0x1u << 24) /**< \brief (US_IDR) LON Transmission Done Interrupt Disable */ +#define US_IDR_LCOL (0x1u << 25) /**< \brief (US_IDR) LON Collision Interrupt Disable */ +#define US_IDR_LFET (0x1u << 26) /**< \brief (US_IDR) LON Frame Early Termination Interrupt Disable */ +#define US_IDR_LRXD (0x1u << 27) /**< \brief (US_IDR) LON Reception Done Interrupt Disable */ +#define US_IDR_LBLOVFE (0x1u << 28) /**< \brief (US_IDR) LON Backlog Overflow Error Interrupt Disable */ +/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */ +#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */ +#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */ +#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */ +#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */ +#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */ +#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */ +#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */ +#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */ +#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max Number of Repetitions Reached Interrupt Mask */ +#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non Acknowledge Interrupt Mask */ +#define US_IMR_RIIC (0x1u << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */ +#define US_IMR_DSRIC (0x1u << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */ +#define US_IMR_DCDIC (0x1u << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */ +#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */ +#define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */ +#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Interrupt Mask */ +#define US_IMR_NSSE (0x1u << 19) /**< \brief (US_IMR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Mask */ +#define US_IMR_LINBK (0x1u << 13) /**< \brief (US_IMR) LIN Break Sent or LIN Break Received Interrupt Mask */ +#define US_IMR_LINID (0x1u << 14) /**< \brief (US_IMR) LIN Identifier Sent or LIN Identifier Received Interrupt Mask */ +#define US_IMR_LINTC (0x1u << 15) /**< \brief (US_IMR) LIN Transfer Completed Interrupt Mask */ +#define US_IMR_LINBE (0x1u << 25) /**< \brief (US_IMR) LIN Bus Error Interrupt Mask */ +#define US_IMR_LINISFE (0x1u << 26) /**< \brief (US_IMR) LIN Inconsistent Synch Field Error Interrupt Mask */ +#define US_IMR_LINIPE (0x1u << 27) /**< \brief (US_IMR) LIN Identifier Parity Interrupt Mask */ +#define US_IMR_LINCE (0x1u << 28) /**< \brief (US_IMR) LIN Checksum Error Interrupt Mask */ +#define US_IMR_LINSNRE (0x1u << 29) /**< \brief (US_IMR) LIN Slave Not Responding Error Interrupt Mask */ +#define US_IMR_LINSTE (0x1u << 30) /**< \brief (US_IMR) LIN Synch Tolerance Error Interrupt Mask */ +#define US_IMR_LINHTE (0x1u << 31) /**< \brief (US_IMR) LIN Header Timeout Error Interrupt Mask */ +#define US_IMR_LSFE (0x1u << 6) /**< \brief (US_IMR) LON Short Frame Error Interrupt Mask */ +#define US_IMR_LCRCE (0x1u << 7) /**< \brief (US_IMR) LON CRC Error Interrupt Mask */ +#define US_IMR_LTXD (0x1u << 24) /**< \brief (US_IMR) LON Transmission Done Interrupt Mask */ +#define US_IMR_LCOL (0x1u << 25) /**< \brief (US_IMR) LON Collision Interrupt Mask */ +#define US_IMR_LFET (0x1u << 26) /**< \brief (US_IMR) LON Frame Early Termination Interrupt Mask */ +#define US_IMR_LRXD (0x1u << 27) /**< \brief (US_IMR) LON Reception Done Interrupt Mask */ +#define US_IMR_LBLOVFE (0x1u << 28) /**< \brief (US_IMR) LON Backlog Overflow Error Interrupt Mask */ +/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */ +#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready (cleared by reading US_RHR) */ +#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready (cleared by writing US_THR) */ +#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out (cleared by writing a one to bit US_CR.STTTO) */ +#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty (cleared by writing US_THR) */ +#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT) */ +#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK) */ +#define US_CSR_RIIC (0x1u << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag (cleared on read) */ +#define US_CSR_DSRIC (0x1u << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag (cleared on read) */ +#define US_CSR_DCDIC (0x1u << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag (cleared on read) */ +#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag (cleared on read) */ +#define US_CSR_RI (0x1u << 20) /**< \brief (US_CSR) Image of RI Input */ +#define US_CSR_DSR (0x1u << 21) /**< \brief (US_CSR) Image of DSR Input */ +#define US_CSR_DCD (0x1u << 22) /**< \brief (US_CSR) Image of DCD Input */ +#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */ +#define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) */ +#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) Underrun Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_NSSE (0x1u << 19) /**< \brief (US_CSR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read) */ +#define US_CSR_NSS (0x1u << 23) /**< \brief (US_CSR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read) */ +#define US_CSR_LINBK (0x1u << 13) /**< \brief (US_CSR) LIN Break Sent or LIN Break Received (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINID (0x1u << 14) /**< \brief (US_CSR) LIN Identifier Sent or LIN Identifier Received (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINTC (0x1u << 15) /**< \brief (US_CSR) LIN Transfer Completed (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINBLS (0x1u << 23) /**< \brief (US_CSR) LIN Bus Line Status */ +#define US_CSR_LINBE (0x1u << 25) /**< \brief (US_CSR) LIN Bit Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINISFE (0x1u << 26) /**< \brief (US_CSR) LIN Inconsistent Synch Field Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINIPE (0x1u << 27) /**< \brief (US_CSR) LIN Identifier Parity Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINCE (0x1u << 28) /**< \brief (US_CSR) LIN Checksum Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINSNRE (0x1u << 29) /**< \brief (US_CSR) LIN Slave Not Responding Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINSTE (0x1u << 30) /**< \brief (US_CSR) LIN Synch Tolerance Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINHTE (0x1u << 31) /**< \brief (US_CSR) LIN Header Timeout Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LSFE (0x1u << 6) /**< \brief (US_CSR) LON Short Frame Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LCRCE (0x1u << 7) /**< \brief (US_CSR) LON CRC Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LTXD (0x1u << 24) /**< \brief (US_CSR) LON Transmission End Flag (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LCOL (0x1u << 25) /**< \brief (US_CSR) LON Collision Detected Flag (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LFET (0x1u << 26) /**< \brief (US_CSR) LON Frame Early Termination (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LRXD (0x1u << 27) /**< \brief (US_CSR) LON Reception End Flag (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LBLOVFE (0x1u << 28) /**< \brief (US_CSR) LON Backlog Overflow Error (cleared by writing a one to bit US_CR.RSTSTA) */ +/* -------- US_RHR : (USART Offset: 0x0018) Receive Holding Register -------- */ +#define US_RHR_RXCHR_Pos 0 +#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */ +#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */ +/* -------- US_THR : (USART Offset: 0x001C) Transmit Holding Register -------- */ +#define US_THR_TXCHR_Pos 0 +#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */ +#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos))) +#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be Transmitted */ +/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */ +#define US_BRGR_CD_Pos 0 +#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */ +#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos))) +#define US_BRGR_FP_Pos 16 +#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */ +#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos))) +/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */ +#define US_RTOR_TO_Pos 0 +#define US_RTOR_TO_Msk (0x1ffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */ +#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos))) +/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */ +#define US_TTGR_TG_Pos 0 +#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */ +#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos))) +#define US_TTGR_PCYCLE_Pos 0 +#define US_TTGR_PCYCLE_Msk (0xffffffu << US_TTGR_PCYCLE_Pos) /**< \brief (US_TTGR) LON PCYCLE Length */ +#define US_TTGR_PCYCLE(value) ((US_TTGR_PCYCLE_Msk & ((value) << US_TTGR_PCYCLE_Pos))) +/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */ +#define US_FIDI_FI_DI_RATIO_Pos 0 +#define US_FIDI_FI_DI_RATIO_Msk (0xffffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */ +#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos))) +#define US_FIDI_BETA2_Pos 0 +#define US_FIDI_BETA2_Msk (0xffffffu << US_FIDI_BETA2_Pos) /**< \brief (US_FIDI) LON BETA2 Length */ +#define US_FIDI_BETA2(value) ((US_FIDI_BETA2_Msk & ((value) << US_FIDI_BETA2_Pos))) +/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */ +#define US_NER_NB_ERRORS_Pos 0 +#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */ +/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */ +#define US_IF_IRDA_FILTER_Pos 0 +#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */ +#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos))) +/* -------- US_MAN : (USART Offset: 0x0050) Manchester Configuration Register -------- */ +#define US_MAN_TX_PL_Pos 0 +#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */ +#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos))) +#define US_MAN_TX_PP_Pos 8 +#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */ +#define US_MAN_TX_PP(value) ((US_MAN_TX_PP_Msk & ((value) << US_MAN_TX_PP_Pos))) +#define US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */ +#define US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */ +#define US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */ +#define US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */ +#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */ +#define US_MAN_RX_PL_Pos 16 +#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */ +#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos))) +#define US_MAN_RX_PP_Pos 24 +#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */ +#define US_MAN_RX_PP(value) ((US_MAN_RX_PP_Msk & ((value) << US_MAN_RX_PP_Pos))) +#define US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */ +#define US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */ +#define US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */ +#define US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */ +#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */ +#define US_MAN_ONE (0x1u << 29) /**< \brief (US_MAN) Must Be Set to 1 */ +#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift Compensation */ +#define US_MAN_RXIDLEV (0x1u << 31) /**< \brief (US_MAN) */ +/* -------- US_LINMR : (USART Offset: 0x0054) LIN Mode Register -------- */ +#define US_LINMR_NACT_Pos 0 +#define US_LINMR_NACT_Msk (0x3u << US_LINMR_NACT_Pos) /**< \brief (US_LINMR) LIN Node Action */ +#define US_LINMR_NACT(value) ((US_LINMR_NACT_Msk & ((value) << US_LINMR_NACT_Pos))) +#define US_LINMR_NACT_PUBLISH (0x0u << 0) /**< \brief (US_LINMR) The USART transmits the response. */ +#define US_LINMR_NACT_SUBSCRIBE (0x1u << 0) /**< \brief (US_LINMR) The USART receives the response. */ +#define US_LINMR_NACT_IGNORE (0x2u << 0) /**< \brief (US_LINMR) The USART does not transmit and does not receive the response. */ +#define US_LINMR_PARDIS (0x1u << 2) /**< \brief (US_LINMR) Parity Disable */ +#define US_LINMR_CHKDIS (0x1u << 3) /**< \brief (US_LINMR) Checksum Disable */ +#define US_LINMR_CHKTYP (0x1u << 4) /**< \brief (US_LINMR) Checksum Type */ +#define US_LINMR_DLM (0x1u << 5) /**< \brief (US_LINMR) Data Length Mode */ +#define US_LINMR_FSDIS (0x1u << 6) /**< \brief (US_LINMR) Frame Slot Mode Disable */ +#define US_LINMR_WKUPTYP (0x1u << 7) /**< \brief (US_LINMR) Wakeup Signal Type */ +#define US_LINMR_DLC_Pos 8 +#define US_LINMR_DLC_Msk (0xffu << US_LINMR_DLC_Pos) /**< \brief (US_LINMR) Data Length Control */ +#define US_LINMR_DLC(value) ((US_LINMR_DLC_Msk & ((value) << US_LINMR_DLC_Pos))) +#define US_LINMR_PDCM (0x1u << 16) /**< \brief (US_LINMR) DMAC Mode */ +#define US_LINMR_SYNCDIS (0x1u << 17) /**< \brief (US_LINMR) Synchronization Disable */ +/* -------- US_LINIR : (USART Offset: 0x0058) LIN Identifier Register -------- */ +#define US_LINIR_IDCHR_Pos 0 +#define US_LINIR_IDCHR_Msk (0xffu << US_LINIR_IDCHR_Pos) /**< \brief (US_LINIR) Identifier Character */ +#define US_LINIR_IDCHR(value) ((US_LINIR_IDCHR_Msk & ((value) << US_LINIR_IDCHR_Pos))) +/* -------- US_LINBRR : (USART Offset: 0x005C) LIN Baud Rate Register -------- */ +#define US_LINBRR_LINCD_Pos 0 +#define US_LINBRR_LINCD_Msk (0xffffu << US_LINBRR_LINCD_Pos) /**< \brief (US_LINBRR) Clock Divider after Synchronization */ +#define US_LINBRR_LINFP_Pos 16 +#define US_LINBRR_LINFP_Msk (0x7u << US_LINBRR_LINFP_Pos) /**< \brief (US_LINBRR) Fractional Part after Synchronization */ +/* -------- US_LONMR : (USART Offset: 0x0060) LON Mode Register -------- */ +#define US_LONMR_COMMT (0x1u << 0) /**< \brief (US_LONMR) LON comm_type Parameter Value */ +#define US_LONMR_COLDET (0x1u << 1) /**< \brief (US_LONMR) LON Collision Detection Feature */ +#define US_LONMR_TCOL (0x1u << 2) /**< \brief (US_LONMR) Terminate Frame upon Collision Notification */ +#define US_LONMR_CDTAIL (0x1u << 3) /**< \brief (US_LONMR) LON Collision Detection on Frame Tail */ +#define US_LONMR_DMAM (0x1u << 4) /**< \brief (US_LONMR) LON DMA Mode */ +#define US_LONMR_LCDS (0x1u << 5) /**< \brief (US_LONMR) LON Collision Detection Source */ +#define US_LONMR_EOFS_Pos 16 +#define US_LONMR_EOFS_Msk (0xffu << US_LONMR_EOFS_Pos) /**< \brief (US_LONMR) End of Frame Condition Size */ +#define US_LONMR_EOFS(value) ((US_LONMR_EOFS_Msk & ((value) << US_LONMR_EOFS_Pos))) +/* -------- US_LONPR : (USART Offset: 0x0064) LON Preamble Register -------- */ +#define US_LONPR_LONPL_Pos 0 +#define US_LONPR_LONPL_Msk (0x3fffu << US_LONPR_LONPL_Pos) /**< \brief (US_LONPR) LON Preamble Length */ +#define US_LONPR_LONPL(value) ((US_LONPR_LONPL_Msk & ((value) << US_LONPR_LONPL_Pos))) +/* -------- US_LONDL : (USART Offset: 0x0068) LON Data Length Register -------- */ +#define US_LONDL_LONDL_Pos 0 +#define US_LONDL_LONDL_Msk (0xffu << US_LONDL_LONDL_Pos) /**< \brief (US_LONDL) LON Data Length */ +#define US_LONDL_LONDL(value) ((US_LONDL_LONDL_Msk & ((value) << US_LONDL_LONDL_Pos))) +/* -------- US_LONL2HDR : (USART Offset: 0x006C) LON L2HDR Register -------- */ +#define US_LONL2HDR_BLI_Pos 0 +#define US_LONL2HDR_BLI_Msk (0x3fu << US_LONL2HDR_BLI_Pos) /**< \brief (US_LONL2HDR) LON Backlog Increment */ +#define US_LONL2HDR_BLI(value) ((US_LONL2HDR_BLI_Msk & ((value) << US_LONL2HDR_BLI_Pos))) +#define US_LONL2HDR_ALTP (0x1u << 6) /**< \brief (US_LONL2HDR) LON Alternate Path Bit */ +#define US_LONL2HDR_PB (0x1u << 7) /**< \brief (US_LONL2HDR) LON Priority Bit */ +/* -------- US_LONBL : (USART Offset: 0x0070) LON Backlog Register -------- */ +#define US_LONBL_LONBL_Pos 0 +#define US_LONBL_LONBL_Msk (0x3fu << US_LONBL_LONBL_Pos) /**< \brief (US_LONBL) LON Node Backlog Value */ +/* -------- US_LONB1TX : (USART Offset: 0x0074) LON Beta1 Tx Register -------- */ +#define US_LONB1TX_BETA1TX_Pos 0 +#define US_LONB1TX_BETA1TX_Msk (0xffffffu << US_LONB1TX_BETA1TX_Pos) /**< \brief (US_LONB1TX) LON Beta1 Length after Transmission */ +#define US_LONB1TX_BETA1TX(value) ((US_LONB1TX_BETA1TX_Msk & ((value) << US_LONB1TX_BETA1TX_Pos))) +/* -------- US_LONB1RX : (USART Offset: 0x0078) LON Beta1 Rx Register -------- */ +#define US_LONB1RX_BETA1RX_Pos 0 +#define US_LONB1RX_BETA1RX_Msk (0xffffffu << US_LONB1RX_BETA1RX_Pos) /**< \brief (US_LONB1RX) LON Beta1 Length after Reception */ +#define US_LONB1RX_BETA1RX(value) ((US_LONB1RX_BETA1RX_Msk & ((value) << US_LONB1RX_BETA1RX_Pos))) +/* -------- US_LONPRIO : (USART Offset: 0x007C) LON Priority Register -------- */ +#define US_LONPRIO_PSNB_Pos 0 +#define US_LONPRIO_PSNB_Msk (0x7fu << US_LONPRIO_PSNB_Pos) /**< \brief (US_LONPRIO) LON Priority Slot Number */ +#define US_LONPRIO_PSNB(value) ((US_LONPRIO_PSNB_Msk & ((value) << US_LONPRIO_PSNB_Pos))) +#define US_LONPRIO_NPS_Pos 8 +#define US_LONPRIO_NPS_Msk (0x7fu << US_LONPRIO_NPS_Pos) /**< \brief (US_LONPRIO) LON Node Priority Slot */ +#define US_LONPRIO_NPS(value) ((US_LONPRIO_NPS_Msk & ((value) << US_LONPRIO_NPS_Pos))) +/* -------- US_IDTTX : (USART Offset: 0x0080) LON IDT Tx Register -------- */ +#define US_IDTTX_IDTTX_Pos 0 +#define US_IDTTX_IDTTX_Msk (0xffffffu << US_IDTTX_IDTTX_Pos) /**< \brief (US_IDTTX) LON Indeterminate Time after Transmission (comm_type = 1 mode only) */ +#define US_IDTTX_IDTTX(value) ((US_IDTTX_IDTTX_Msk & ((value) << US_IDTTX_IDTTX_Pos))) +/* -------- US_IDTRX : (USART Offset: 0x0084) LON IDT Rx Register -------- */ +#define US_IDTRX_IDTRX_Pos 0 +#define US_IDTRX_IDTRX_Msk (0xffffffu << US_IDTRX_IDTRX_Pos) /**< \brief (US_IDTRX) LON Indeterminate Time after Reception (comm_type = 1 mode only) */ +#define US_IDTRX_IDTRX(value) ((US_IDTRX_IDTRX_Msk & ((value) << US_IDTRX_IDTRX_Pos))) +/* -------- US_ICDIFF : (USART Offset: 0x0088) IC DIFF Register -------- */ +#define US_ICDIFF_ICDIFF_Pos 0 +#define US_ICDIFF_ICDIFF_Msk (0xfu << US_ICDIFF_ICDIFF_Pos) /**< \brief (US_ICDIFF) IC Differentiator Number */ +#define US_ICDIFF_ICDIFF(value) ((US_ICDIFF_ICDIFF_Msk & ((value) << US_ICDIFF_ICDIFF_Pos))) +/* -------- US_WPMR : (USART Offset: 0x00E4) Write Protection Mode Register -------- */ +#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protection Enable */ +#define US_WPMR_WPKEY_Pos 8 +#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protection Key */ +#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos))) +#define US_WPMR_WPKEY_PASSWD (0x555341u << 8) /**< \brief (US_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- US_WPSR : (USART Offset: 0x00E8) Write Protection Status Register -------- */ +#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protection Violation Status */ +#define US_WPSR_WPVSRC_Pos 8 +#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protection Violation Source */ +/* -------- US_VERSION : (USART Offset: 0x00FC) Version Register -------- */ +#define US_VERSION_VERSION_Pos 0 +#define US_VERSION_VERSION_Msk (0xfffu << US_VERSION_VERSION_Pos) /**< \brief (US_VERSION) Hardware Module Version */ +#define US_VERSION_MFN_Pos 16 +#define US_VERSION_MFN_Msk (0x7u << US_VERSION_MFN_Pos) /**< \brief (US_VERSION) Metal Fix Number */ + +/*@}*/ + + +#endif /* _SAME70_USART_COMPONENT_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/usbhs.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/usbhs.h new file mode 100644 index 000000000..b75cacd22 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/usbhs.h @@ -0,0 +1,952 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_USBHS_COMPONENT_ +#define _SAME70_USBHS_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR USB High-Speed Interface */ +/* ============================================================================= */ +/** \addtogroup SAME70_USBHS USB High-Speed Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief UsbhsDevdma hardware registers */ +typedef struct { + __IO uint32_t USBHS_DEVDMANXTDSC; /**< \brief (UsbhsDevdma Offset: 0x0) Device DMA Channel Next Descriptor Address Register */ + __IO uint32_t USBHS_DEVDMAADDRESS; /**< \brief (UsbhsDevdma Offset: 0x4) Device DMA Channel Address Register */ + __IO uint32_t USBHS_DEVDMACONTROL; /**< \brief (UsbhsDevdma Offset: 0x8) Device DMA Channel Control Register */ + __IO uint32_t USBHS_DEVDMASTATUS; /**< \brief (UsbhsDevdma Offset: 0xC) Device DMA Channel Status Register */ +} UsbhsDevdma; +/** \brief UsbhsHstdma hardware registers */ +typedef struct { + __IO uint32_t USBHS_HSTDMANXTDSC; /**< \brief (UsbhsHstdma Offset: 0x0) Host DMA Channel Next Descriptor Address Register */ + __IO uint32_t USBHS_HSTDMAADDRESS; /**< \brief (UsbhsHstdma Offset: 0x4) Host DMA Channel Address Register */ + __IO uint32_t USBHS_HSTDMACONTROL; /**< \brief (UsbhsHstdma Offset: 0x8) Host DMA Channel Control Register */ + __IO uint32_t USBHS_HSTDMASTATUS; /**< \brief (UsbhsHstdma Offset: 0xC) Host DMA Channel Status Register */ +} UsbhsHstdma; +/** \brief Usbhs hardware registers */ +#define USBHSDEVDMA_NUMBER 7 +#define USBHSHSTDMA_NUMBER 7 +typedef struct { + __IO uint32_t USBHS_DEVCTRL; /**< \brief (Usbhs Offset: 0x0000) Device General Control Register */ + __I uint32_t USBHS_DEVISR; /**< \brief (Usbhs Offset: 0x0004) Device Global Interrupt Status Register */ + __O uint32_t USBHS_DEVICR; /**< \brief (Usbhs Offset: 0x0008) Device Global Interrupt Clear Register */ + __O uint32_t USBHS_DEVIFR; /**< \brief (Usbhs Offset: 0x000C) Device Global Interrupt Set Register */ + __I uint32_t USBHS_DEVIMR; /**< \brief (Usbhs Offset: 0x0010) Device Global Interrupt Mask Register */ + __O uint32_t USBHS_DEVIDR; /**< \brief (Usbhs Offset: 0x0014) Device Global Interrupt Disable Register */ + __O uint32_t USBHS_DEVIER; /**< \brief (Usbhs Offset: 0x0018) Device Global Interrupt Enable Register */ + __IO uint32_t USBHS_DEVEPT; /**< \brief (Usbhs Offset: 0x001C) Device Endpoint Register */ + __I uint32_t USBHS_DEVFNUM; /**< \brief (Usbhs Offset: 0x0020) Device Frame Number Register */ + __I uint32_t Reserved1[55]; + __IO uint32_t USBHS_DEVEPTCFG[10]; /**< \brief (Usbhs Offset: 0x100) Device Endpoint Configuration Register (n = 0) */ + __I uint32_t Reserved2[2]; + __I uint32_t USBHS_DEVEPTISR[10]; /**< \brief (Usbhs Offset: 0x130) Device Endpoint Status Register (n = 0) */ + __I uint32_t Reserved3[2]; + __O uint32_t USBHS_DEVEPTICR[10]; /**< \brief (Usbhs Offset: 0x160) Device Endpoint Clear Register (n = 0) */ + __I uint32_t Reserved4[2]; + __O uint32_t USBHS_DEVEPTIFR[10]; /**< \brief (Usbhs Offset: 0x190) Device Endpoint Set Register (n = 0) */ + __I uint32_t Reserved5[2]; + __I uint32_t USBHS_DEVEPTIMR[10]; /**< \brief (Usbhs Offset: 0x1C0) Device Endpoint Mask Register (n = 0) */ + __I uint32_t Reserved6[2]; + __O uint32_t USBHS_DEVEPTIER[10]; /**< \brief (Usbhs Offset: 0x1F0) Device Endpoint Enable Register (n = 0) */ + __I uint32_t Reserved7[2]; + __O uint32_t USBHS_DEVEPTIDR[10]; /**< \brief (Usbhs Offset: 0x220) Device Endpoint Disable Register (n = 0) */ + __I uint32_t Reserved8[50]; + UsbhsDevdma USBHS_DEVDMA[USBHSDEVDMA_NUMBER]; /**< \brief (Usbhs Offset: 0x310) n = 1 .. 7 */ + __I uint32_t Reserved9[32]; + __IO uint32_t USBHS_HSTCTRL; /**< \brief (Usbhs Offset: 0x0400) Host General Control Register */ + __I uint32_t USBHS_HSTISR; /**< \brief (Usbhs Offset: 0x0404) Host Global Interrupt Status Register */ + __O uint32_t USBHS_HSTICR; /**< \brief (Usbhs Offset: 0x0408) Host Global Interrupt Clear Register */ + __O uint32_t USBHS_HSTIFR; /**< \brief (Usbhs Offset: 0x040C) Host Global Interrupt Set Register */ + __I uint32_t USBHS_HSTIMR; /**< \brief (Usbhs Offset: 0x0410) Host Global Interrupt Mask Register */ + __O uint32_t USBHS_HSTIDR; /**< \brief (Usbhs Offset: 0x0414) Host Global Interrupt Disable Register */ + __O uint32_t USBHS_HSTIER; /**< \brief (Usbhs Offset: 0x0418) Host Global Interrupt Enable Register */ + __IO uint32_t USBHS_HSTPIP; /**< \brief (Usbhs Offset: 0x0041C) Host Pipe Register */ + __IO uint32_t USBHS_HSTFNUM; /**< \brief (Usbhs Offset: 0x0420) Host Frame Number Register */ + __IO uint32_t USBHS_HSTADDR1; /**< \brief (Usbhs Offset: 0x0424) Host Address 1 Register */ + __IO uint32_t USBHS_HSTADDR2; /**< \brief (Usbhs Offset: 0x0428) Host Address 2 Register */ + __IO uint32_t USBHS_HSTADDR3; /**< \brief (Usbhs Offset: 0x042C) Host Address 3 Register */ + __I uint32_t Reserved10[52]; + __IO uint32_t USBHS_HSTPIPCFG[10]; /**< \brief (Usbhs Offset: 0x500) Host Pipe Configuration Register (n = 0) */ + __I uint32_t Reserved11[2]; + __I uint32_t USBHS_HSTPIPISR[10]; /**< \brief (Usbhs Offset: 0x530) Host Pipe Status Register (n = 0) */ + __I uint32_t Reserved12[2]; + __O uint32_t USBHS_HSTPIPICR[10]; /**< \brief (Usbhs Offset: 0x560) Host Pipe Clear Register (n = 0) */ + __I uint32_t Reserved13[2]; + __O uint32_t USBHS_HSTPIPIFR[10]; /**< \brief (Usbhs Offset: 0x590) Host Pipe Set Register (n = 0) */ + __I uint32_t Reserved14[2]; + __I uint32_t USBHS_HSTPIPIMR[10]; /**< \brief (Usbhs Offset: 0x5C0) Host Pipe Mask Register (n = 0) */ + __I uint32_t Reserved15[2]; + __O uint32_t USBHS_HSTPIPIER[10]; /**< \brief (Usbhs Offset: 0x5F0) Host Pipe Enable Register (n = 0) */ + __I uint32_t Reserved16[2]; + __O uint32_t USBHS_HSTPIPIDR[10]; /**< \brief (Usbhs Offset: 0x620) Host Pipe Disable Register (n = 0) */ + __I uint32_t Reserved17[2]; + __IO uint32_t USBHS_HSTPIPINRQ[10]; /**< \brief (Usbhs Offset: 0x650) Host Pipe IN Request Register (n = 0) */ + __I uint32_t Reserved18[2]; + __IO uint32_t USBHS_HSTPIPERR[10]; /**< \brief (Usbhs Offset: 0x680) Host Pipe Error Register (n = 0) */ + __I uint32_t Reserved19[26]; + UsbhsHstdma USBHS_HSTDMA[USBHSHSTDMA_NUMBER]; /**< \brief (Usbhs Offset: 0x710) n = 1 .. 7 */ + __I uint32_t Reserved20[32]; + __IO uint32_t USBHS_CTRL; /**< \brief (Usbhs Offset: 0x0800) General Control Register */ + __I uint32_t USBHS_SR; /**< \brief (Usbhs Offset: 0x0804) General Status Register */ + __O uint32_t USBHS_SCR; /**< \brief (Usbhs Offset: 0x0808) General Status Clear Register */ + __O uint32_t USBHS_SFR; /**< \brief (Usbhs Offset: 0x080C) General Status Set Register */ + __IO uint32_t USBHS_TSTA1; /**< \brief (Usbhs Offset: 0x0810) General Test A1 Register */ + __IO uint32_t USBHS_TSTA2; /**< \brief (Usbhs Offset: 0x0814) General Test A2 Register */ + __I uint32_t USBHS_VERSION; /**< \brief (Usbhs Offset: 0x0818) General Version Register */ + __I uint32_t Reserved21[4]; + __I uint32_t USBHS_FSM; /**< \brief (Usbhs Offset: 0x082C) General Finite State Machine Register */ +} Usbhs; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- USBHS_DEVCTRL : (USBHS Offset: 0x0000) Device General Control Register -------- */ +#define USBHS_DEVCTRL_UADD_Pos 0 +#define USBHS_DEVCTRL_UADD_Msk (0x7fu << USBHS_DEVCTRL_UADD_Pos) /**< \brief (USBHS_DEVCTRL) USB Address */ +#define USBHS_DEVCTRL_UADD(value) ((USBHS_DEVCTRL_UADD_Msk & ((value) << USBHS_DEVCTRL_UADD_Pos))) +#define USBHS_DEVCTRL_ADDEN (0x1u << 7) /**< \brief (USBHS_DEVCTRL) Address Enable */ +#define USBHS_DEVCTRL_DETACH (0x1u << 8) /**< \brief (USBHS_DEVCTRL) Detach */ +#define USBHS_DEVCTRL_RMWKUP (0x1u << 9) /**< \brief (USBHS_DEVCTRL) Remote Wake-Up */ +#define USBHS_DEVCTRL_SPDCONF_Pos 10 +#define USBHS_DEVCTRL_SPDCONF_Msk (0x3u << USBHS_DEVCTRL_SPDCONF_Pos) /**< \brief (USBHS_DEVCTRL) Mode Configuration */ +#define USBHS_DEVCTRL_SPDCONF(value) ((USBHS_DEVCTRL_SPDCONF_Msk & ((value) << USBHS_DEVCTRL_SPDCONF_Pos))) +#define USBHS_DEVCTRL_SPDCONF_NORMAL (0x0u << 10) /**< \brief (USBHS_DEVCTRL) The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable. */ +#define USBHS_DEVCTRL_SPDCONF_LOW_POWER (0x1u << 10) /**< \brief (USBHS_DEVCTRL) For a better consumption, if high speed is not needed. */ +#define USBHS_DEVCTRL_SPDCONF_HIGH_SPEED (0x2u << 10) /**< \brief (USBHS_DEVCTRL) Forced high speed. */ +#define USBHS_DEVCTRL_SPDCONF_FORCED_FS (0x3u << 10) /**< \brief (USBHS_DEVCTRL) The peripheral remains in Full-speed mode whatever the host speed capability. */ +#define USBHS_DEVCTRL_LS (0x1u << 12) /**< \brief (USBHS_DEVCTRL) Low-Speed Mode Force */ +#define USBHS_DEVCTRL_TSTJ (0x1u << 13) /**< \brief (USBHS_DEVCTRL) Test mode J */ +#define USBHS_DEVCTRL_TSTK (0x1u << 14) /**< \brief (USBHS_DEVCTRL) Test mode K */ +#define USBHS_DEVCTRL_TSTPCKT (0x1u << 15) /**< \brief (USBHS_DEVCTRL) Test packet mode */ +#define USBHS_DEVCTRL_OPMODE2 (0x1u << 16) /**< \brief (USBHS_DEVCTRL) Specific Operational mode */ +/* -------- USBHS_DEVISR : (USBHS Offset: 0x0004) Device Global Interrupt Status Register -------- */ +#define USBHS_DEVISR_SUSP (0x1u << 0) /**< \brief (USBHS_DEVISR) Suspend Interrupt */ +#define USBHS_DEVISR_MSOF (0x1u << 1) /**< \brief (USBHS_DEVISR) Micro Start of Frame Interrupt */ +#define USBHS_DEVISR_SOF (0x1u << 2) /**< \brief (USBHS_DEVISR) Start of Frame Interrupt */ +#define USBHS_DEVISR_EORST (0x1u << 3) /**< \brief (USBHS_DEVISR) End of Reset Interrupt */ +#define USBHS_DEVISR_WAKEUP (0x1u << 4) /**< \brief (USBHS_DEVISR) Wake-Up Interrupt */ +#define USBHS_DEVISR_EORSM (0x1u << 5) /**< \brief (USBHS_DEVISR) End of Resume Interrupt */ +#define USBHS_DEVISR_UPRSM (0x1u << 6) /**< \brief (USBHS_DEVISR) Upstream Resume Interrupt */ +#define USBHS_DEVISR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVISR) Endpoint 0 Interrupt */ +#define USBHS_DEVISR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVISR) Endpoint 1 Interrupt */ +#define USBHS_DEVISR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVISR) Endpoint 2 Interrupt */ +#define USBHS_DEVISR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVISR) Endpoint 3 Interrupt */ +#define USBHS_DEVISR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVISR) Endpoint 4 Interrupt */ +#define USBHS_DEVISR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVISR) Endpoint 5 Interrupt */ +#define USBHS_DEVISR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVISR) Endpoint 6 Interrupt */ +#define USBHS_DEVISR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVISR) Endpoint 7 Interrupt */ +#define USBHS_DEVISR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVISR) Endpoint 8 Interrupt */ +#define USBHS_DEVISR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVISR) Endpoint 9 Interrupt */ +#define USBHS_DEVISR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVISR) DMA Channel 1 Interrupt */ +#define USBHS_DEVISR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVISR) DMA Channel 2 Interrupt */ +#define USBHS_DEVISR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVISR) DMA Channel 3 Interrupt */ +#define USBHS_DEVISR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVISR) DMA Channel 4 Interrupt */ +#define USBHS_DEVISR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVISR) DMA Channel 5 Interrupt */ +#define USBHS_DEVISR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVISR) DMA Channel 6 Interrupt */ +#define USBHS_DEVISR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVISR) DMA Channel 7 Interrupt */ +/* -------- USBHS_DEVICR : (USBHS Offset: 0x0008) Device Global Interrupt Clear Register -------- */ +#define USBHS_DEVICR_SUSPC (0x1u << 0) /**< \brief (USBHS_DEVICR) Suspend Interrupt Clear */ +#define USBHS_DEVICR_MSOFC (0x1u << 1) /**< \brief (USBHS_DEVICR) Micro Start of Frame Interrupt Clear */ +#define USBHS_DEVICR_SOFC (0x1u << 2) /**< \brief (USBHS_DEVICR) Start of Frame Interrupt Clear */ +#define USBHS_DEVICR_EORSTC (0x1u << 3) /**< \brief (USBHS_DEVICR) End of Reset Interrupt Clear */ +#define USBHS_DEVICR_WAKEUPC (0x1u << 4) /**< \brief (USBHS_DEVICR) Wake-Up Interrupt Clear */ +#define USBHS_DEVICR_EORSMC (0x1u << 5) /**< \brief (USBHS_DEVICR) End of Resume Interrupt Clear */ +#define USBHS_DEVICR_UPRSMC (0x1u << 6) /**< \brief (USBHS_DEVICR) Upstream Resume Interrupt Clear */ +/* -------- USBHS_DEVIFR : (USBHS Offset: 0x000C) Device Global Interrupt Set Register -------- */ +#define USBHS_DEVIFR_SUSPS (0x1u << 0) /**< \brief (USBHS_DEVIFR) Suspend Interrupt Set */ +#define USBHS_DEVIFR_MSOFS (0x1u << 1) /**< \brief (USBHS_DEVIFR) Micro Start of Frame Interrupt Set */ +#define USBHS_DEVIFR_SOFS (0x1u << 2) /**< \brief (USBHS_DEVIFR) Start of Frame Interrupt Set */ +#define USBHS_DEVIFR_EORSTS (0x1u << 3) /**< \brief (USBHS_DEVIFR) End of Reset Interrupt Set */ +#define USBHS_DEVIFR_WAKEUPS (0x1u << 4) /**< \brief (USBHS_DEVIFR) Wake-Up Interrupt Set */ +#define USBHS_DEVIFR_EORSMS (0x1u << 5) /**< \brief (USBHS_DEVIFR) End of Resume Interrupt Set */ +#define USBHS_DEVIFR_UPRSMS (0x1u << 6) /**< \brief (USBHS_DEVIFR) Upstream Resume Interrupt Set */ +#define USBHS_DEVIFR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIFR) DMA Channel 1 Interrupt Set */ +#define USBHS_DEVIFR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIFR) DMA Channel 2 Interrupt Set */ +#define USBHS_DEVIFR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIFR) DMA Channel 3 Interrupt Set */ +#define USBHS_DEVIFR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIFR) DMA Channel 4 Interrupt Set */ +#define USBHS_DEVIFR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIFR) DMA Channel 5 Interrupt Set */ +#define USBHS_DEVIFR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIFR) DMA Channel 6 Interrupt Set */ +#define USBHS_DEVIFR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIFR) DMA Channel 7 Interrupt Set */ +/* -------- USBHS_DEVIMR : (USBHS Offset: 0x0010) Device Global Interrupt Mask Register -------- */ +#define USBHS_DEVIMR_SUSPE (0x1u << 0) /**< \brief (USBHS_DEVIMR) Suspend Interrupt Mask */ +#define USBHS_DEVIMR_MSOFE (0x1u << 1) /**< \brief (USBHS_DEVIMR) Micro Start of Frame Interrupt Mask */ +#define USBHS_DEVIMR_SOFE (0x1u << 2) /**< \brief (USBHS_DEVIMR) Start of Frame Interrupt Mask */ +#define USBHS_DEVIMR_EORSTE (0x1u << 3) /**< \brief (USBHS_DEVIMR) End of Reset Interrupt Mask */ +#define USBHS_DEVIMR_WAKEUPE (0x1u << 4) /**< \brief (USBHS_DEVIMR) Wake-Up Interrupt Mask */ +#define USBHS_DEVIMR_EORSME (0x1u << 5) /**< \brief (USBHS_DEVIMR) End of Resume Interrupt Mask */ +#define USBHS_DEVIMR_UPRSME (0x1u << 6) /**< \brief (USBHS_DEVIMR) Upstream Resume Interrupt Mask */ +#define USBHS_DEVIMR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIMR) Endpoint 0 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIMR) Endpoint 1 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIMR) Endpoint 2 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIMR) Endpoint 3 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIMR) Endpoint 4 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIMR) Endpoint 5 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIMR) Endpoint 6 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIMR) Endpoint 7 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIMR) Endpoint 8 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIMR) Endpoint 9 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIMR) DMA Channel 1 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIMR) DMA Channel 2 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIMR) DMA Channel 3 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIMR) DMA Channel 4 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIMR) DMA Channel 5 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIMR) DMA Channel 6 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIMR) DMA Channel 7 Interrupt Mask */ +/* -------- USBHS_DEVIDR : (USBHS Offset: 0x0014) Device Global Interrupt Disable Register -------- */ +#define USBHS_DEVIDR_SUSPEC (0x1u << 0) /**< \brief (USBHS_DEVIDR) Suspend Interrupt Disable */ +#define USBHS_DEVIDR_MSOFEC (0x1u << 1) /**< \brief (USBHS_DEVIDR) Micro Start of Frame Interrupt Disable */ +#define USBHS_DEVIDR_SOFEC (0x1u << 2) /**< \brief (USBHS_DEVIDR) Start of Frame Interrupt Disable */ +#define USBHS_DEVIDR_EORSTEC (0x1u << 3) /**< \brief (USBHS_DEVIDR) End of Reset Interrupt Disable */ +#define USBHS_DEVIDR_WAKEUPEC (0x1u << 4) /**< \brief (USBHS_DEVIDR) Wake-Up Interrupt Disable */ +#define USBHS_DEVIDR_EORSMEC (0x1u << 5) /**< \brief (USBHS_DEVIDR) End of Resume Interrupt Disable */ +#define USBHS_DEVIDR_UPRSMEC (0x1u << 6) /**< \brief (USBHS_DEVIDR) Upstream Resume Interrupt Disable */ +#define USBHS_DEVIDR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIDR) Endpoint 0 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIDR) Endpoint 1 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIDR) Endpoint 2 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIDR) Endpoint 3 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIDR) Endpoint 4 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIDR) Endpoint 5 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIDR) Endpoint 6 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIDR) Endpoint 7 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIDR) Endpoint 8 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIDR) Endpoint 9 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIDR) DMA Channel 1 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIDR) DMA Channel 2 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIDR) DMA Channel 3 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIDR) DMA Channel 4 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIDR) DMA Channel 5 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIDR) DMA Channel 6 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIDR) DMA Channel 7 Interrupt Disable */ +/* -------- USBHS_DEVIER : (USBHS Offset: 0x0018) Device Global Interrupt Enable Register -------- */ +#define USBHS_DEVIER_SUSPES (0x1u << 0) /**< \brief (USBHS_DEVIER) Suspend Interrupt Enable */ +#define USBHS_DEVIER_MSOFES (0x1u << 1) /**< \brief (USBHS_DEVIER) Micro Start of Frame Interrupt Enable */ +#define USBHS_DEVIER_SOFES (0x1u << 2) /**< \brief (USBHS_DEVIER) Start of Frame Interrupt Enable */ +#define USBHS_DEVIER_EORSTES (0x1u << 3) /**< \brief (USBHS_DEVIER) End of Reset Interrupt Enable */ +#define USBHS_DEVIER_WAKEUPES (0x1u << 4) /**< \brief (USBHS_DEVIER) Wake-Up Interrupt Enable */ +#define USBHS_DEVIER_EORSMES (0x1u << 5) /**< \brief (USBHS_DEVIER) End of Resume Interrupt Enable */ +#define USBHS_DEVIER_UPRSMES (0x1u << 6) /**< \brief (USBHS_DEVIER) Upstream Resume Interrupt Enable */ +#define USBHS_DEVIER_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIER) Endpoint 0 Interrupt Enable */ +#define USBHS_DEVIER_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIER) Endpoint 1 Interrupt Enable */ +#define USBHS_DEVIER_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIER) Endpoint 2 Interrupt Enable */ +#define USBHS_DEVIER_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIER) Endpoint 3 Interrupt Enable */ +#define USBHS_DEVIER_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIER) Endpoint 4 Interrupt Enable */ +#define USBHS_DEVIER_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIER) Endpoint 5 Interrupt Enable */ +#define USBHS_DEVIER_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIER) Endpoint 6 Interrupt Enable */ +#define USBHS_DEVIER_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIER) Endpoint 7 Interrupt Enable */ +#define USBHS_DEVIER_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIER) Endpoint 8 Interrupt Enable */ +#define USBHS_DEVIER_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIER) Endpoint 9 Interrupt Enable */ +#define USBHS_DEVIER_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIER) DMA Channel 1 Interrupt Enable */ +#define USBHS_DEVIER_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIER) DMA Channel 2 Interrupt Enable */ +#define USBHS_DEVIER_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIER) DMA Channel 3 Interrupt Enable */ +#define USBHS_DEVIER_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIER) DMA Channel 4 Interrupt Enable */ +#define USBHS_DEVIER_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIER) DMA Channel 5 Interrupt Enable */ +#define USBHS_DEVIER_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIER) DMA Channel 6 Interrupt Enable */ +#define USBHS_DEVIER_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIER) DMA Channel 7 Interrupt Enable */ +/* -------- USBHS_DEVEPT : (USBHS Offset: 0x001C) Device Endpoint Register -------- */ +#define USBHS_DEVEPT_EPEN0 (0x1u << 0) /**< \brief (USBHS_DEVEPT) Endpoint 0 Enable */ +#define USBHS_DEVEPT_EPEN1 (0x1u << 1) /**< \brief (USBHS_DEVEPT) Endpoint 1 Enable */ +#define USBHS_DEVEPT_EPEN2 (0x1u << 2) /**< \brief (USBHS_DEVEPT) Endpoint 2 Enable */ +#define USBHS_DEVEPT_EPEN3 (0x1u << 3) /**< \brief (USBHS_DEVEPT) Endpoint 3 Enable */ +#define USBHS_DEVEPT_EPEN4 (0x1u << 4) /**< \brief (USBHS_DEVEPT) Endpoint 4 Enable */ +#define USBHS_DEVEPT_EPEN5 (0x1u << 5) /**< \brief (USBHS_DEVEPT) Endpoint 5 Enable */ +#define USBHS_DEVEPT_EPEN6 (0x1u << 6) /**< \brief (USBHS_DEVEPT) Endpoint 6 Enable */ +#define USBHS_DEVEPT_EPEN7 (0x1u << 7) /**< \brief (USBHS_DEVEPT) Endpoint 7 Enable */ +#define USBHS_DEVEPT_EPEN8 (0x1u << 8) /**< \brief (USBHS_DEVEPT) Endpoint 8 Enable */ +#define USBHS_DEVEPT_EPEN9 (0x1u << 9) /**< \brief (USBHS_DEVEPT) Endpoint 9 Enable */ +#define USBHS_DEVEPT_EPRST0 (0x1u << 16) /**< \brief (USBHS_DEVEPT) Endpoint 0 Reset */ +#define USBHS_DEVEPT_EPRST1 (0x1u << 17) /**< \brief (USBHS_DEVEPT) Endpoint 1 Reset */ +#define USBHS_DEVEPT_EPRST2 (0x1u << 18) /**< \brief (USBHS_DEVEPT) Endpoint 2 Reset */ +#define USBHS_DEVEPT_EPRST3 (0x1u << 19) /**< \brief (USBHS_DEVEPT) Endpoint 3 Reset */ +#define USBHS_DEVEPT_EPRST4 (0x1u << 20) /**< \brief (USBHS_DEVEPT) Endpoint 4 Reset */ +#define USBHS_DEVEPT_EPRST5 (0x1u << 21) /**< \brief (USBHS_DEVEPT) Endpoint 5 Reset */ +#define USBHS_DEVEPT_EPRST6 (0x1u << 22) /**< \brief (USBHS_DEVEPT) Endpoint 6 Reset */ +#define USBHS_DEVEPT_EPRST7 (0x1u << 23) /**< \brief (USBHS_DEVEPT) Endpoint 7 Reset */ +#define USBHS_DEVEPT_EPRST8 (0x1u << 24) /**< \brief (USBHS_DEVEPT) Endpoint 8 Reset */ +#define USBHS_DEVEPT_EPRST9 (0x1u << 25) /**< \brief (USBHS_DEVEPT) Endpoint 9 Reset */ +/* -------- USBHS_DEVFNUM : (USBHS Offset: 0x0020) Device Frame Number Register -------- */ +#define USBHS_DEVFNUM_MFNUM_Pos 0 +#define USBHS_DEVFNUM_MFNUM_Msk (0x7u << USBHS_DEVFNUM_MFNUM_Pos) /**< \brief (USBHS_DEVFNUM) Micro Frame Number */ +#define USBHS_DEVFNUM_FNUM_Pos 3 +#define USBHS_DEVFNUM_FNUM_Msk (0x7ffu << USBHS_DEVFNUM_FNUM_Pos) /**< \brief (USBHS_DEVFNUM) Frame Number */ +#define USBHS_DEVFNUM_FNCERR (0x1u << 15) /**< \brief (USBHS_DEVFNUM) Frame Number CRC Error */ +/* -------- USBHS_DEVEPTCFG[10] : (USBHS Offset: 0x100) Device Endpoint Configuration Register (n = 0) -------- */ +#define USBHS_DEVEPTCFG_ALLOC (0x1u << 1) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Memory Allocate */ +#define USBHS_DEVEPTCFG_EPBK_Pos 2 +#define USBHS_DEVEPTCFG_EPBK_Msk (0x3u << USBHS_DEVEPTCFG_EPBK_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Banks */ +#define USBHS_DEVEPTCFG_EPBK(value) ((USBHS_DEVEPTCFG_EPBK_Msk & ((value) << USBHS_DEVEPTCFG_EPBK_Pos))) +#define USBHS_DEVEPTCFG_EPBK_1_BANK (0x0u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Single-bank endpoint */ +#define USBHS_DEVEPTCFG_EPBK_2_BANK (0x1u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Double-bank endpoint */ +#define USBHS_DEVEPTCFG_EPBK_3_BANK (0x2u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Triple-bank endpoint */ +#define USBHS_DEVEPTCFG_EPSIZE_Pos 4 +#define USBHS_DEVEPTCFG_EPSIZE_Msk (0x7u << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Size */ +#define USBHS_DEVEPTCFG_EPSIZE(value) ((USBHS_DEVEPTCFG_EPSIZE_Msk & ((value) << USBHS_DEVEPTCFG_EPSIZE_Pos))) +#define USBHS_DEVEPTCFG_EPSIZE_8_BYTE (0x0u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 8 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_16_BYTE (0x1u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 16 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_32_BYTE (0x2u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 32 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_64_BYTE (0x3u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 64 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_128_BYTE (0x4u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 128 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_256_BYTE (0x5u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 256 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_512_BYTE (0x6u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 512 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_1024_BYTE (0x7u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 1024 bytes */ +#define USBHS_DEVEPTCFG_EPDIR (0x1u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Direction */ +#define USBHS_DEVEPTCFG_EPDIR_OUT (0x0u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) The endpoint direction is OUT. */ +#define USBHS_DEVEPTCFG_EPDIR_IN (0x1u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) The endpoint direction is IN (nor for control endpoints). */ +#define USBHS_DEVEPTCFG_AUTOSW (0x1u << 9) /**< \brief (USBHS_DEVEPTCFG[10]) Automatic Switch */ +#define USBHS_DEVEPTCFG_EPTYPE_Pos 11 +#define USBHS_DEVEPTCFG_EPTYPE_Msk (0x3u << USBHS_DEVEPTCFG_EPTYPE_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Type */ +#define USBHS_DEVEPTCFG_EPTYPE(value) ((USBHS_DEVEPTCFG_EPTYPE_Msk & ((value) << USBHS_DEVEPTCFG_EPTYPE_Pos))) +#define USBHS_DEVEPTCFG_EPTYPE_CTRL (0x0u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Control */ +#define USBHS_DEVEPTCFG_EPTYPE_ISO (0x1u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Isochronous */ +#define USBHS_DEVEPTCFG_EPTYPE_BLK (0x2u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Bulk */ +#define USBHS_DEVEPTCFG_EPTYPE_INTRPT (0x3u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Interrupt */ +#define USBHS_DEVEPTCFG_NBTRANS_Pos 13 +#define USBHS_DEVEPTCFG_NBTRANS_Msk (0x3u << USBHS_DEVEPTCFG_NBTRANS_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Number of transactions per microframe for isochronous endpoint */ +#define USBHS_DEVEPTCFG_NBTRANS(value) ((USBHS_DEVEPTCFG_NBTRANS_Msk & ((value) << USBHS_DEVEPTCFG_NBTRANS_Pos))) +#define USBHS_DEVEPTCFG_NBTRANS_0_TRANS (0x0u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Reserved to endpoint that does not have the high-bandwidth isochronous capability. */ +#define USBHS_DEVEPTCFG_NBTRANS_1_TRANS (0x1u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Default value: one transaction per microframe. */ +#define USBHS_DEVEPTCFG_NBTRANS_2_TRANS (0x2u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Two transactions per microframe. This endpoint should be configured as double-bank. */ +#define USBHS_DEVEPTCFG_NBTRANS_3_TRANS (0x3u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Three transactions per microframe. This endpoint should be configured as triple-bank. */ +/* -------- USBHS_DEVEPTISR[10] : (USBHS Offset: 0x130) Device Endpoint Status Register (n = 0) -------- */ +#define USBHS_DEVEPTISR_TXINI (0x1u << 0) /**< \brief (USBHS_DEVEPTISR[10]) Transmitted IN Data Interrupt */ +#define USBHS_DEVEPTISR_RXOUTI (0x1u << 1) /**< \brief (USBHS_DEVEPTISR[10]) Received OUT Data Interrupt */ +#define USBHS_DEVEPTISR_RXSTPI (0x1u << 2) /**< \brief (USBHS_DEVEPTISR[10]) Received SETUP Interrupt */ +#define USBHS_DEVEPTISR_NAKOUTI (0x1u << 3) /**< \brief (USBHS_DEVEPTISR[10]) NAKed OUT Interrupt */ +#define USBHS_DEVEPTISR_NAKINI (0x1u << 4) /**< \brief (USBHS_DEVEPTISR[10]) NAKed IN Interrupt */ +#define USBHS_DEVEPTISR_OVERFI (0x1u << 5) /**< \brief (USBHS_DEVEPTISR[10]) Overflow Interrupt */ +#define USBHS_DEVEPTISR_STALLEDI (0x1u << 6) /**< \brief (USBHS_DEVEPTISR[10]) STALLed Interrupt */ +#define USBHS_DEVEPTISR_SHORTPACKET (0x1u << 7) /**< \brief (USBHS_DEVEPTISR[10]) Short Packet Interrupt */ +#define USBHS_DEVEPTISR_DTSEQ_Pos 8 +#define USBHS_DEVEPTISR_DTSEQ_Msk (0x3u << USBHS_DEVEPTISR_DTSEQ_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Data Toggle Sequence */ +#define USBHS_DEVEPTISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Data0 toggle sequence */ +#define USBHS_DEVEPTISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Data1 toggle sequence */ +#define USBHS_DEVEPTISR_DTSEQ_DATA2 (0x2u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Reserved for high-bandwidth isochronous endpoint */ +#define USBHS_DEVEPTISR_DTSEQ_MDATA (0x3u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Reserved for high-bandwidth isochronous endpoint */ +#define USBHS_DEVEPTISR_NBUSYBK_Pos 12 +#define USBHS_DEVEPTISR_NBUSYBK_Msk (0x3u << USBHS_DEVEPTISR_NBUSYBK_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Number of Busy Banks */ +#define USBHS_DEVEPTISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 0 busy bank (all banks free) */ +#define USBHS_DEVEPTISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 1 busy bank */ +#define USBHS_DEVEPTISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 2 busy banks */ +#define USBHS_DEVEPTISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 3 busy banks */ +#define USBHS_DEVEPTISR_CURRBK_Pos 14 +#define USBHS_DEVEPTISR_CURRBK_Msk (0x3u << USBHS_DEVEPTISR_CURRBK_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Current Bank */ +#define USBHS_DEVEPTISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank0 */ +#define USBHS_DEVEPTISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank1 */ +#define USBHS_DEVEPTISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank2 */ +#define USBHS_DEVEPTISR_RWALL (0x1u << 16) /**< \brief (USBHS_DEVEPTISR[10]) Read/Write Allowed */ +#define USBHS_DEVEPTISR_CTRLDIR (0x1u << 17) /**< \brief (USBHS_DEVEPTISR[10]) Control Direction */ +#define USBHS_DEVEPTISR_CFGOK (0x1u << 18) /**< \brief (USBHS_DEVEPTISR[10]) Configuration OK Status */ +#define USBHS_DEVEPTISR_BYCT_Pos 20 +#define USBHS_DEVEPTISR_BYCT_Msk (0x7ffu << USBHS_DEVEPTISR_BYCT_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Byte Count */ +#define USBHS_DEVEPTISR_UNDERFI (0x1u << 2) /**< \brief (USBHS_DEVEPTISR[10]) Underflow Interrupt */ +#define USBHS_DEVEPTISR_HBISOINERRI (0x1u << 3) /**< \brief (USBHS_DEVEPTISR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt */ +#define USBHS_DEVEPTISR_HBISOFLUSHI (0x1u << 4) /**< \brief (USBHS_DEVEPTISR[10]) High Bandwidth Isochronous IN Flush Interrupt */ +#define USBHS_DEVEPTISR_CRCERRI (0x1u << 6) /**< \brief (USBHS_DEVEPTISR[10]) CRC Error Interrupt */ +#define USBHS_DEVEPTISR_ERRORTRANS (0x1u << 10) /**< \brief (USBHS_DEVEPTISR[10]) High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt */ +/* -------- USBHS_DEVEPTICR[10] : (USBHS Offset: 0x160) Device Endpoint Clear Register (n = 0) -------- */ +#define USBHS_DEVEPTICR_TXINIC (0x1u << 0) /**< \brief (USBHS_DEVEPTICR[10]) Transmitted IN Data Interrupt Clear */ +#define USBHS_DEVEPTICR_RXOUTIC (0x1u << 1) /**< \brief (USBHS_DEVEPTICR[10]) Received OUT Data Interrupt Clear */ +#define USBHS_DEVEPTICR_RXSTPIC (0x1u << 2) /**< \brief (USBHS_DEVEPTICR[10]) Received SETUP Interrupt Clear */ +#define USBHS_DEVEPTICR_NAKOUTIC (0x1u << 3) /**< \brief (USBHS_DEVEPTICR[10]) NAKed OUT Interrupt Clear */ +#define USBHS_DEVEPTICR_NAKINIC (0x1u << 4) /**< \brief (USBHS_DEVEPTICR[10]) NAKed IN Interrupt Clear */ +#define USBHS_DEVEPTICR_OVERFIC (0x1u << 5) /**< \brief (USBHS_DEVEPTICR[10]) Overflow Interrupt Clear */ +#define USBHS_DEVEPTICR_STALLEDIC (0x1u << 6) /**< \brief (USBHS_DEVEPTICR[10]) STALLed Interrupt Clear */ +#define USBHS_DEVEPTICR_SHORTPACKETC (0x1u << 7) /**< \brief (USBHS_DEVEPTICR[10]) Short Packet Interrupt Clear */ +#define USBHS_DEVEPTICR_UNDERFIC (0x1u << 2) /**< \brief (USBHS_DEVEPTICR[10]) Underflow Interrupt Clear */ +#define USBHS_DEVEPTICR_HBISOINERRIC (0x1u << 3) /**< \brief (USBHS_DEVEPTICR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt Clear */ +#define USBHS_DEVEPTICR_HBISOFLUSHIC (0x1u << 4) /**< \brief (USBHS_DEVEPTICR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear */ +#define USBHS_DEVEPTICR_CRCERRIC (0x1u << 6) /**< \brief (USBHS_DEVEPTICR[10]) CRC Error Interrupt Clear */ +/* -------- USBHS_DEVEPTIFR[10] : (USBHS Offset: 0x190) Device Endpoint Set Register (n = 0) -------- */ +#define USBHS_DEVEPTIFR_TXINIS (0x1u << 0) /**< \brief (USBHS_DEVEPTIFR[10]) Transmitted IN Data Interrupt Set */ +#define USBHS_DEVEPTIFR_RXOUTIS (0x1u << 1) /**< \brief (USBHS_DEVEPTIFR[10]) Received OUT Data Interrupt Set */ +#define USBHS_DEVEPTIFR_RXSTPIS (0x1u << 2) /**< \brief (USBHS_DEVEPTIFR[10]) Received SETUP Interrupt Set */ +#define USBHS_DEVEPTIFR_NAKOUTIS (0x1u << 3) /**< \brief (USBHS_DEVEPTIFR[10]) NAKed OUT Interrupt Set */ +#define USBHS_DEVEPTIFR_NAKINIS (0x1u << 4) /**< \brief (USBHS_DEVEPTIFR[10]) NAKed IN Interrupt Set */ +#define USBHS_DEVEPTIFR_OVERFIS (0x1u << 5) /**< \brief (USBHS_DEVEPTIFR[10]) Overflow Interrupt Set */ +#define USBHS_DEVEPTIFR_STALLEDIS (0x1u << 6) /**< \brief (USBHS_DEVEPTIFR[10]) STALLed Interrupt Set */ +#define USBHS_DEVEPTIFR_SHORTPACKETS (0x1u << 7) /**< \brief (USBHS_DEVEPTIFR[10]) Short Packet Interrupt Set */ +#define USBHS_DEVEPTIFR_NBUSYBKS (0x1u << 12) /**< \brief (USBHS_DEVEPTIFR[10]) Number of Busy Banks Interrupt Set */ +#define USBHS_DEVEPTIFR_UNDERFIS (0x1u << 2) /**< \brief (USBHS_DEVEPTIFR[10]) Underflow Interrupt Set */ +#define USBHS_DEVEPTIFR_HBISOINERRIS (0x1u << 3) /**< \brief (USBHS_DEVEPTIFR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt Set */ +#define USBHS_DEVEPTIFR_HBISOFLUSHIS (0x1u << 4) /**< \brief (USBHS_DEVEPTIFR[10]) High Bandwidth Isochronous IN Flush Interrupt Set */ +#define USBHS_DEVEPTIFR_CRCERRIS (0x1u << 6) /**< \brief (USBHS_DEVEPTIFR[10]) CRC Error Interrupt Set */ +/* -------- USBHS_DEVEPTIMR[10] : (USBHS Offset: 0x1C0) Device Endpoint Mask Register (n = 0) -------- */ +#define USBHS_DEVEPTIMR_TXINE (0x1u << 0) /**< \brief (USBHS_DEVEPTIMR[10]) Transmitted IN Data Interrupt */ +#define USBHS_DEVEPTIMR_RXOUTE (0x1u << 1) /**< \brief (USBHS_DEVEPTIMR[10]) Received OUT Data Interrupt */ +#define USBHS_DEVEPTIMR_RXSTPE (0x1u << 2) /**< \brief (USBHS_DEVEPTIMR[10]) Received SETUP Interrupt */ +#define USBHS_DEVEPTIMR_NAKOUTE (0x1u << 3) /**< \brief (USBHS_DEVEPTIMR[10]) NAKed OUT Interrupt */ +#define USBHS_DEVEPTIMR_NAKINE (0x1u << 4) /**< \brief (USBHS_DEVEPTIMR[10]) NAKed IN Interrupt */ +#define USBHS_DEVEPTIMR_OVERFE (0x1u << 5) /**< \brief (USBHS_DEVEPTIMR[10]) Overflow Interrupt */ +#define USBHS_DEVEPTIMR_STALLEDE (0x1u << 6) /**< \brief (USBHS_DEVEPTIMR[10]) STALLed Interrupt */ +#define USBHS_DEVEPTIMR_SHORTPACKETE (0x1u << 7) /**< \brief (USBHS_DEVEPTIMR[10]) Short Packet Interrupt */ +#define USBHS_DEVEPTIMR_NBUSYBKE (0x1u << 12) /**< \brief (USBHS_DEVEPTIMR[10]) Number of Busy Banks Interrupt */ +#define USBHS_DEVEPTIMR_KILLBK (0x1u << 13) /**< \brief (USBHS_DEVEPTIMR[10]) Kill IN Bank */ +#define USBHS_DEVEPTIMR_FIFOCON (0x1u << 14) /**< \brief (USBHS_DEVEPTIMR[10]) FIFO Control */ +#define USBHS_DEVEPTIMR_EPDISHDMA (0x1u << 16) /**< \brief (USBHS_DEVEPTIMR[10]) Endpoint Interrupts Disable HDMA Request */ +#define USBHS_DEVEPTIMR_NYETDIS (0x1u << 17) /**< \brief (USBHS_DEVEPTIMR[10]) NYET Token Disable */ +#define USBHS_DEVEPTIMR_RSTDT (0x1u << 18) /**< \brief (USBHS_DEVEPTIMR[10]) Reset Data Toggle */ +#define USBHS_DEVEPTIMR_STALLRQ (0x1u << 19) /**< \brief (USBHS_DEVEPTIMR[10]) STALL Request */ +#define USBHS_DEVEPTIMR_UNDERFE (0x1u << 2) /**< \brief (USBHS_DEVEPTIMR[10]) Underflow Interrupt */ +#define USBHS_DEVEPTIMR_HBISOINERRE (0x1u << 3) /**< \brief (USBHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Error Interrupt */ +#define USBHS_DEVEPTIMR_HBISOFLUSHE (0x1u << 4) /**< \brief (USBHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Flush Interrupt */ +#define USBHS_DEVEPTIMR_CRCERRE (0x1u << 6) /**< \brief (USBHS_DEVEPTIMR[10]) CRC Error Interrupt */ +#define USBHS_DEVEPTIMR_MDATAE (0x1u << 8) /**< \brief (USBHS_DEVEPTIMR[10]) MData Interrupt */ +#define USBHS_DEVEPTIMR_DATAXE (0x1u << 9) /**< \brief (USBHS_DEVEPTIMR[10]) DataX Interrupt */ +#define USBHS_DEVEPTIMR_ERRORTRANSE (0x1u << 10) /**< \brief (USBHS_DEVEPTIMR[10]) Transaction Error Interrupt */ +/* -------- USBHS_DEVEPTIER[10] : (USBHS Offset: 0x1F0) Device Endpoint Enable Register (n = 0) -------- */ +#define USBHS_DEVEPTIER_TXINES (0x1u << 0) /**< \brief (USBHS_DEVEPTIER[10]) Transmitted IN Data Interrupt Enable */ +#define USBHS_DEVEPTIER_RXOUTES (0x1u << 1) /**< \brief (USBHS_DEVEPTIER[10]) Received OUT Data Interrupt Enable */ +#define USBHS_DEVEPTIER_RXSTPES (0x1u << 2) /**< \brief (USBHS_DEVEPTIER[10]) Received SETUP Interrupt Enable */ +#define USBHS_DEVEPTIER_NAKOUTES (0x1u << 3) /**< \brief (USBHS_DEVEPTIER[10]) NAKed OUT Interrupt Enable */ +#define USBHS_DEVEPTIER_NAKINES (0x1u << 4) /**< \brief (USBHS_DEVEPTIER[10]) NAKed IN Interrupt Enable */ +#define USBHS_DEVEPTIER_OVERFES (0x1u << 5) /**< \brief (USBHS_DEVEPTIER[10]) Overflow Interrupt Enable */ +#define USBHS_DEVEPTIER_STALLEDES (0x1u << 6) /**< \brief (USBHS_DEVEPTIER[10]) STALLed Interrupt Enable */ +#define USBHS_DEVEPTIER_SHORTPACKETES (0x1u << 7) /**< \brief (USBHS_DEVEPTIER[10]) Short Packet Interrupt Enable */ +#define USBHS_DEVEPTIER_NBUSYBKES (0x1u << 12) /**< \brief (USBHS_DEVEPTIER[10]) Number of Busy Banks Interrupt Enable */ +#define USBHS_DEVEPTIER_KILLBKS (0x1u << 13) /**< \brief (USBHS_DEVEPTIER[10]) Kill IN Bank */ +#define USBHS_DEVEPTIER_FIFOCONS (0x1u << 14) /**< \brief (USBHS_DEVEPTIER[10]) FIFO Control */ +#define USBHS_DEVEPTIER_EPDISHDMAS (0x1u << 16) /**< \brief (USBHS_DEVEPTIER[10]) Endpoint Interrupts Disable HDMA Request Enable */ +#define USBHS_DEVEPTIER_NYETDISS (0x1u << 17) /**< \brief (USBHS_DEVEPTIER[10]) NYET Token Disable Enable */ +#define USBHS_DEVEPTIER_RSTDTS (0x1u << 18) /**< \brief (USBHS_DEVEPTIER[10]) Reset Data Toggle Enable */ +#define USBHS_DEVEPTIER_STALLRQS (0x1u << 19) /**< \brief (USBHS_DEVEPTIER[10]) STALL Request Enable */ +#define USBHS_DEVEPTIER_UNDERFES (0x1u << 2) /**< \brief (USBHS_DEVEPTIER[10]) Underflow Interrupt Enable */ +#define USBHS_DEVEPTIER_HBISOINERRES (0x1u << 3) /**< \brief (USBHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Error Interrupt Enable */ +#define USBHS_DEVEPTIER_HBISOFLUSHES (0x1u << 4) /**< \brief (USBHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Flush Interrupt Enable */ +#define USBHS_DEVEPTIER_CRCERRES (0x1u << 6) /**< \brief (USBHS_DEVEPTIER[10]) CRC Error Interrupt Enable */ +#define USBHS_DEVEPTIER_MDATAES (0x1u << 8) /**< \brief (USBHS_DEVEPTIER[10]) MData Interrupt Enable */ +#define USBHS_DEVEPTIER_DATAXES (0x1u << 9) /**< \brief (USBHS_DEVEPTIER[10]) DataX Interrupt Enable */ +#define USBHS_DEVEPTIER_ERRORTRANSES (0x1u << 10) /**< \brief (USBHS_DEVEPTIER[10]) Transaction Error Interrupt Enable */ +/* -------- USBHS_DEVEPTIDR[10] : (USBHS Offset: 0x220) Device Endpoint Disable Register (n = 0) -------- */ +#define USBHS_DEVEPTIDR_TXINEC (0x1u << 0) /**< \brief (USBHS_DEVEPTIDR[10]) Transmitted IN Interrupt Clear */ +#define USBHS_DEVEPTIDR_RXOUTEC (0x1u << 1) /**< \brief (USBHS_DEVEPTIDR[10]) Received OUT Data Interrupt Clear */ +#define USBHS_DEVEPTIDR_RXSTPEC (0x1u << 2) /**< \brief (USBHS_DEVEPTIDR[10]) Received SETUP Interrupt Clear */ +#define USBHS_DEVEPTIDR_NAKOUTEC (0x1u << 3) /**< \brief (USBHS_DEVEPTIDR[10]) NAKed OUT Interrupt Clear */ +#define USBHS_DEVEPTIDR_NAKINEC (0x1u << 4) /**< \brief (USBHS_DEVEPTIDR[10]) NAKed IN Interrupt Clear */ +#define USBHS_DEVEPTIDR_OVERFEC (0x1u << 5) /**< \brief (USBHS_DEVEPTIDR[10]) Overflow Interrupt Clear */ +#define USBHS_DEVEPTIDR_STALLEDEC (0x1u << 6) /**< \brief (USBHS_DEVEPTIDR[10]) STALLed Interrupt Clear */ +#define USBHS_DEVEPTIDR_SHORTPACKETEC (0x1u << 7) /**< \brief (USBHS_DEVEPTIDR[10]) Shortpacket Interrupt Clear */ +#define USBHS_DEVEPTIDR_NBUSYBKEC (0x1u << 12) /**< \brief (USBHS_DEVEPTIDR[10]) Number of Busy Banks Interrupt Clear */ +#define USBHS_DEVEPTIDR_FIFOCONC (0x1u << 14) /**< \brief (USBHS_DEVEPTIDR[10]) FIFO Control Clear */ +#define USBHS_DEVEPTIDR_EPDISHDMAC (0x1u << 16) /**< \brief (USBHS_DEVEPTIDR[10]) Endpoint Interrupts Disable HDMA Request Clear */ +#define USBHS_DEVEPTIDR_NYETDISC (0x1u << 17) /**< \brief (USBHS_DEVEPTIDR[10]) NYET Token Disable Clear */ +#define USBHS_DEVEPTIDR_STALLRQC (0x1u << 19) /**< \brief (USBHS_DEVEPTIDR[10]) STALL Request Clear */ +#define USBHS_DEVEPTIDR_UNDERFEC (0x1u << 2) /**< \brief (USBHS_DEVEPTIDR[10]) Underflow Interrupt Clear */ +#define USBHS_DEVEPTIDR_HBISOINERREC (0x1u << 3) /**< \brief (USBHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Error Interrupt Clear */ +#define USBHS_DEVEPTIDR_HBISOFLUSHEC (0x1u << 4) /**< \brief (USBHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear */ +#define USBHS_DEVEPTIDR_CRCERREC (0x1u << 6) /**< \brief (USBHS_DEVEPTIDR[10]) CRC Error Interrupt Clear */ +#define USBHS_DEVEPTIDR_MDATEC (0x1u << 8) /**< \brief (USBHS_DEVEPTIDR[10]) MData Interrupt Clear */ +#define USBHS_DEVEPTIDR_DATAXEC (0x1u << 9) /**< \brief (USBHS_DEVEPTIDR[10]) DataX Interrupt Clear */ +#define USBHS_DEVEPTIDR_ERRORTRANSEC (0x1u << 10) /**< \brief (USBHS_DEVEPTIDR[10]) Transaction Error Interrupt Clear */ +/* -------- USBHS_DEVDMANXTDSC : (USBHS Offset: N/A) Device DMA Channel Next Descriptor Address Register -------- */ +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos 0 +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (USBHS_DEVDMANXTDSC) Next Descriptor Address */ +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD(value) ((USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos))) +/* -------- USBHS_DEVDMAADDRESS : (USBHS Offset: N/A) Device DMA Channel Address Register -------- */ +#define USBHS_DEVDMAADDRESS_BUFF_ADD_Pos 0 +#define USBHS_DEVDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos) /**< \brief (USBHS_DEVDMAADDRESS) Buffer Address */ +#define USBHS_DEVDMAADDRESS_BUFF_ADD(value) ((USBHS_DEVDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos))) +/* -------- USBHS_DEVDMACONTROL : (USBHS Offset: N/A) Device DMA Channel Control Register -------- */ +#define USBHS_DEVDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_DEVDMACONTROL) Channel Enable Command */ +#define USBHS_DEVDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (USBHS_DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */ +#define USBHS_DEVDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (USBHS_DEVDMACONTROL) End of Transfer Enable Control (OUT transfers only) */ +#define USBHS_DEVDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (USBHS_DEVDMACONTROL) End of Buffer Enable Control */ +#define USBHS_DEVDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (USBHS_DEVDMACONTROL) End of Transfer Interrupt Enable */ +#define USBHS_DEVDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (USBHS_DEVDMACONTROL) End of Buffer Interrupt Enable */ +#define USBHS_DEVDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (USBHS_DEVDMACONTROL) Descriptor Loaded Interrupt Enable */ +#define USBHS_DEVDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (USBHS_DEVDMACONTROL) Burst Lock Enable */ +#define USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos 16 +#define USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk (0xffffu << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (USBHS_DEVDMACONTROL) Buffer Byte Length (Write-only) */ +#define USBHS_DEVDMACONTROL_BUFF_LENGTH(value) ((USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos))) +/* -------- USBHS_DEVDMASTATUS : (USBHS Offset: N/A) Device DMA Channel Status Register -------- */ +#define USBHS_DEVDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_DEVDMASTATUS) Channel Enable Status */ +#define USBHS_DEVDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (USBHS_DEVDMASTATUS) Channel Active Status */ +#define USBHS_DEVDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (USBHS_DEVDMASTATUS) End of Channel Transfer Status */ +#define USBHS_DEVDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (USBHS_DEVDMASTATUS) End of Channel Buffer Status */ +#define USBHS_DEVDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (USBHS_DEVDMASTATUS) Descriptor Loaded Status */ +#define USBHS_DEVDMASTATUS_BUFF_COUNT_Pos 16 +#define USBHS_DEVDMASTATUS_BUFF_COUNT_Msk (0xffffu << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos) /**< \brief (USBHS_DEVDMASTATUS) Buffer Byte Count */ +#define USBHS_DEVDMASTATUS_BUFF_COUNT(value) ((USBHS_DEVDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos))) +/* -------- USBHS_HSTCTRL : (USBHS Offset: 0x0400) Host General Control Register -------- */ +#define USBHS_HSTCTRL_SOFE (0x1u << 8) /**< \brief (USBHS_HSTCTRL) Start of Frame Generation Enable */ +#define USBHS_HSTCTRL_RESET (0x1u << 9) /**< \brief (USBHS_HSTCTRL) Send USB Reset */ +#define USBHS_HSTCTRL_RESUME (0x1u << 10) /**< \brief (USBHS_HSTCTRL) Send USB Resume */ +#define USBHS_HSTCTRL_SPDCONF_Pos 12 +#define USBHS_HSTCTRL_SPDCONF_Msk (0x3u << USBHS_HSTCTRL_SPDCONF_Pos) /**< \brief (USBHS_HSTCTRL) Mode Configuration */ +#define USBHS_HSTCTRL_SPDCONF(value) ((USBHS_HSTCTRL_SPDCONF_Msk & ((value) << USBHS_HSTCTRL_SPDCONF_Pos))) +#define USBHS_HSTCTRL_SPDCONF_NORMAL (0x0u << 12) /**< \brief (USBHS_HSTCTRL) The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable. */ +#define USBHS_HSTCTRL_SPDCONF_LOW_POWER (0x1u << 12) /**< \brief (USBHS_HSTCTRL) For a better consumption, if high speed is not needed. */ +#define USBHS_HSTCTRL_SPDCONF_HIGH_SPEED (0x2u << 12) /**< \brief (USBHS_HSTCTRL) Forced high speed. */ +#define USBHS_HSTCTRL_SPDCONF_FORCED_FS (0x3u << 12) /**< \brief (USBHS_HSTCTRL) The host remains in Full-speed mode whatever the peripheral speed capability. */ +/* -------- USBHS_HSTISR : (USBHS Offset: 0x0404) Host Global Interrupt Status Register -------- */ +#define USBHS_HSTISR_DCONNI (0x1u << 0) /**< \brief (USBHS_HSTISR) Device Connection Interrupt */ +#define USBHS_HSTISR_DDISCI (0x1u << 1) /**< \brief (USBHS_HSTISR) Device Disconnection Interrupt */ +#define USBHS_HSTISR_RSTI (0x1u << 2) /**< \brief (USBHS_HSTISR) USB Reset Sent Interrupt */ +#define USBHS_HSTISR_RSMEDI (0x1u << 3) /**< \brief (USBHS_HSTISR) Downstream Resume Sent Interrupt */ +#define USBHS_HSTISR_RXRSMI (0x1u << 4) /**< \brief (USBHS_HSTISR) Upstream Resume Received Interrupt */ +#define USBHS_HSTISR_HSOFI (0x1u << 5) /**< \brief (USBHS_HSTISR) Host Start of Frame Interrupt */ +#define USBHS_HSTISR_HWUPI (0x1u << 6) /**< \brief (USBHS_HSTISR) Host Wake-Up Interrupt */ +#define USBHS_HSTISR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTISR) Pipe 0 Interrupt */ +#define USBHS_HSTISR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTISR) Pipe 1 Interrupt */ +#define USBHS_HSTISR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTISR) Pipe 2 Interrupt */ +#define USBHS_HSTISR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTISR) Pipe 3 Interrupt */ +#define USBHS_HSTISR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTISR) Pipe 4 Interrupt */ +#define USBHS_HSTISR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTISR) Pipe 5 Interrupt */ +#define USBHS_HSTISR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTISR) Pipe 6 Interrupt */ +#define USBHS_HSTISR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTISR) Pipe 7 Interrupt */ +#define USBHS_HSTISR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTISR) Pipe 8 Interrupt */ +#define USBHS_HSTISR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTISR) Pipe 9 Interrupt */ +#define USBHS_HSTISR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTISR) DMA Channel 1 Interrupt */ +#define USBHS_HSTISR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTISR) DMA Channel 2 Interrupt */ +#define USBHS_HSTISR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTISR) DMA Channel 3 Interrupt */ +#define USBHS_HSTISR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTISR) DMA Channel 4 Interrupt */ +#define USBHS_HSTISR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTISR) DMA Channel 5 Interrupt */ +#define USBHS_HSTISR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTISR) DMA Channel 6 Interrupt */ +#define USBHS_HSTISR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTISR) DMA Channel 7 Interrupt */ +/* -------- USBHS_HSTICR : (USBHS Offset: 0x0408) Host Global Interrupt Clear Register -------- */ +#define USBHS_HSTICR_DCONNIC (0x1u << 0) /**< \brief (USBHS_HSTICR) Device Connection Interrupt Clear */ +#define USBHS_HSTICR_DDISCIC (0x1u << 1) /**< \brief (USBHS_HSTICR) Device Disconnection Interrupt Clear */ +#define USBHS_HSTICR_RSTIC (0x1u << 2) /**< \brief (USBHS_HSTICR) USB Reset Sent Interrupt Clear */ +#define USBHS_HSTICR_RSMEDIC (0x1u << 3) /**< \brief (USBHS_HSTICR) Downstream Resume Sent Interrupt Clear */ +#define USBHS_HSTICR_RXRSMIC (0x1u << 4) /**< \brief (USBHS_HSTICR) Upstream Resume Received Interrupt Clear */ +#define USBHS_HSTICR_HSOFIC (0x1u << 5) /**< \brief (USBHS_HSTICR) Host Start of Frame Interrupt Clear */ +#define USBHS_HSTICR_HWUPIC (0x1u << 6) /**< \brief (USBHS_HSTICR) Host Wake-Up Interrupt Clear */ +/* -------- USBHS_HSTIFR : (USBHS Offset: 0x040C) Host Global Interrupt Set Register -------- */ +#define USBHS_HSTIFR_DCONNIS (0x1u << 0) /**< \brief (USBHS_HSTIFR) Device Connection Interrupt Set */ +#define USBHS_HSTIFR_DDISCIS (0x1u << 1) /**< \brief (USBHS_HSTIFR) Device Disconnection Interrupt Set */ +#define USBHS_HSTIFR_RSTIS (0x1u << 2) /**< \brief (USBHS_HSTIFR) USB Reset Sent Interrupt Set */ +#define USBHS_HSTIFR_RSMEDIS (0x1u << 3) /**< \brief (USBHS_HSTIFR) Downstream Resume Sent Interrupt Set */ +#define USBHS_HSTIFR_RXRSMIS (0x1u << 4) /**< \brief (USBHS_HSTIFR) Upstream Resume Received Interrupt Set */ +#define USBHS_HSTIFR_HSOFIS (0x1u << 5) /**< \brief (USBHS_HSTIFR) Host Start of Frame Interrupt Set */ +#define USBHS_HSTIFR_HWUPIS (0x1u << 6) /**< \brief (USBHS_HSTIFR) Host Wake-Up Interrupt Set */ +#define USBHS_HSTIFR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIFR) DMA Channel 1 Interrupt Set */ +#define USBHS_HSTIFR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIFR) DMA Channel 2 Interrupt Set */ +#define USBHS_HSTIFR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIFR) DMA Channel 3 Interrupt Set */ +#define USBHS_HSTIFR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIFR) DMA Channel 4 Interrupt Set */ +#define USBHS_HSTIFR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIFR) DMA Channel 5 Interrupt Set */ +#define USBHS_HSTIFR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIFR) DMA Channel 6 Interrupt Set */ +#define USBHS_HSTIFR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIFR) DMA Channel 7 Interrupt Set */ +/* -------- USBHS_HSTIMR : (USBHS Offset: 0x0410) Host Global Interrupt Mask Register -------- */ +#define USBHS_HSTIMR_DCONNIE (0x1u << 0) /**< \brief (USBHS_HSTIMR) Device Connection Interrupt Enable */ +#define USBHS_HSTIMR_DDISCIE (0x1u << 1) /**< \brief (USBHS_HSTIMR) Device Disconnection Interrupt Enable */ +#define USBHS_HSTIMR_RSTIE (0x1u << 2) /**< \brief (USBHS_HSTIMR) USB Reset Sent Interrupt Enable */ +#define USBHS_HSTIMR_RSMEDIE (0x1u << 3) /**< \brief (USBHS_HSTIMR) Downstream Resume Sent Interrupt Enable */ +#define USBHS_HSTIMR_RXRSMIE (0x1u << 4) /**< \brief (USBHS_HSTIMR) Upstream Resume Received Interrupt Enable */ +#define USBHS_HSTIMR_HSOFIE (0x1u << 5) /**< \brief (USBHS_HSTIMR) Host Start of Frame Interrupt Enable */ +#define USBHS_HSTIMR_HWUPIE (0x1u << 6) /**< \brief (USBHS_HSTIMR) Host Wake-Up Interrupt Enable */ +#define USBHS_HSTIMR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIMR) Pipe 0 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIMR) Pipe 1 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIMR) Pipe 2 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIMR) Pipe 3 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIMR) Pipe 4 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIMR) Pipe 5 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIMR) Pipe 6 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIMR) Pipe 7 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIMR) Pipe 8 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIMR) Pipe 9 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIMR) DMA Channel 1 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIMR) DMA Channel 2 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIMR) DMA Channel 3 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIMR) DMA Channel 4 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIMR) DMA Channel 5 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIMR) DMA Channel 6 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIMR) DMA Channel 7 Interrupt Enable */ +/* -------- USBHS_HSTIDR : (USBHS Offset: 0x0414) Host Global Interrupt Disable Register -------- */ +#define USBHS_HSTIDR_DCONNIEC (0x1u << 0) /**< \brief (USBHS_HSTIDR) Device Connection Interrupt Disable */ +#define USBHS_HSTIDR_DDISCIEC (0x1u << 1) /**< \brief (USBHS_HSTIDR) Device Disconnection Interrupt Disable */ +#define USBHS_HSTIDR_RSTIEC (0x1u << 2) /**< \brief (USBHS_HSTIDR) USB Reset Sent Interrupt Disable */ +#define USBHS_HSTIDR_RSMEDIEC (0x1u << 3) /**< \brief (USBHS_HSTIDR) Downstream Resume Sent Interrupt Disable */ +#define USBHS_HSTIDR_RXRSMIEC (0x1u << 4) /**< \brief (USBHS_HSTIDR) Upstream Resume Received Interrupt Disable */ +#define USBHS_HSTIDR_HSOFIEC (0x1u << 5) /**< \brief (USBHS_HSTIDR) Host Start of Frame Interrupt Disable */ +#define USBHS_HSTIDR_HWUPIEC (0x1u << 6) /**< \brief (USBHS_HSTIDR) Host Wake-Up Interrupt Disable */ +#define USBHS_HSTIDR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIDR) Pipe 0 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIDR) Pipe 1 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIDR) Pipe 2 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIDR) Pipe 3 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIDR) Pipe 4 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIDR) Pipe 5 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIDR) Pipe 6 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIDR) Pipe 7 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIDR) Pipe 8 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIDR) Pipe 9 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIDR) DMA Channel 1 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIDR) DMA Channel 2 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIDR) DMA Channel 3 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIDR) DMA Channel 4 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIDR) DMA Channel 5 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIDR) DMA Channel 6 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIDR) DMA Channel 7 Interrupt Disable */ +/* -------- USBHS_HSTIER : (USBHS Offset: 0x0418) Host Global Interrupt Enable Register -------- */ +#define USBHS_HSTIER_DCONNIES (0x1u << 0) /**< \brief (USBHS_HSTIER) Device Connection Interrupt Enable */ +#define USBHS_HSTIER_DDISCIES (0x1u << 1) /**< \brief (USBHS_HSTIER) Device Disconnection Interrupt Enable */ +#define USBHS_HSTIER_RSTIES (0x1u << 2) /**< \brief (USBHS_HSTIER) USB Reset Sent Interrupt Enable */ +#define USBHS_HSTIER_RSMEDIES (0x1u << 3) /**< \brief (USBHS_HSTIER) Downstream Resume Sent Interrupt Enable */ +#define USBHS_HSTIER_RXRSMIES (0x1u << 4) /**< \brief (USBHS_HSTIER) Upstream Resume Received Interrupt Enable */ +#define USBHS_HSTIER_HSOFIES (0x1u << 5) /**< \brief (USBHS_HSTIER) Host Start of Frame Interrupt Enable */ +#define USBHS_HSTIER_HWUPIES (0x1u << 6) /**< \brief (USBHS_HSTIER) Host Wake-Up Interrupt Enable */ +#define USBHS_HSTIER_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIER) Pipe 0 Interrupt Enable */ +#define USBHS_HSTIER_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIER) Pipe 1 Interrupt Enable */ +#define USBHS_HSTIER_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIER) Pipe 2 Interrupt Enable */ +#define USBHS_HSTIER_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIER) Pipe 3 Interrupt Enable */ +#define USBHS_HSTIER_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIER) Pipe 4 Interrupt Enable */ +#define USBHS_HSTIER_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIER) Pipe 5 Interrupt Enable */ +#define USBHS_HSTIER_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIER) Pipe 6 Interrupt Enable */ +#define USBHS_HSTIER_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIER) Pipe 7 Interrupt Enable */ +#define USBHS_HSTIER_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIER) Pipe 8 Interrupt Enable */ +#define USBHS_HSTIER_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIER) Pipe 9 Interrupt Enable */ +#define USBHS_HSTIER_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIER) DMA Channel 1 Interrupt Enable */ +#define USBHS_HSTIER_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIER) DMA Channel 2 Interrupt Enable */ +#define USBHS_HSTIER_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIER) DMA Channel 3 Interrupt Enable */ +#define USBHS_HSTIER_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIER) DMA Channel 4 Interrupt Enable */ +#define USBHS_HSTIER_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIER) DMA Channel 5 Interrupt Enable */ +#define USBHS_HSTIER_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIER) DMA Channel 6 Interrupt Enable */ +#define USBHS_HSTIER_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIER) DMA Channel 7 Interrupt Enable */ +/* -------- USBHS_HSTPIP : (USBHS Offset: 0x0041C) Host Pipe Register -------- */ +#define USBHS_HSTPIP_PEN0 (0x1u << 0) /**< \brief (USBHS_HSTPIP) Pipe 0 Enable */ +#define USBHS_HSTPIP_PEN1 (0x1u << 1) /**< \brief (USBHS_HSTPIP) Pipe 1 Enable */ +#define USBHS_HSTPIP_PEN2 (0x1u << 2) /**< \brief (USBHS_HSTPIP) Pipe 2 Enable */ +#define USBHS_HSTPIP_PEN3 (0x1u << 3) /**< \brief (USBHS_HSTPIP) Pipe 3 Enable */ +#define USBHS_HSTPIP_PEN4 (0x1u << 4) /**< \brief (USBHS_HSTPIP) Pipe 4 Enable */ +#define USBHS_HSTPIP_PEN5 (0x1u << 5) /**< \brief (USBHS_HSTPIP) Pipe 5 Enable */ +#define USBHS_HSTPIP_PEN6 (0x1u << 6) /**< \brief (USBHS_HSTPIP) Pipe 6 Enable */ +#define USBHS_HSTPIP_PEN7 (0x1u << 7) /**< \brief (USBHS_HSTPIP) Pipe 7 Enable */ +#define USBHS_HSTPIP_PEN8 (0x1u << 8) /**< \brief (USBHS_HSTPIP) Pipe 8 Enable */ +#define USBHS_HSTPIP_PRST0 (0x1u << 16) /**< \brief (USBHS_HSTPIP) Pipe 0 Reset */ +#define USBHS_HSTPIP_PRST1 (0x1u << 17) /**< \brief (USBHS_HSTPIP) Pipe 1 Reset */ +#define USBHS_HSTPIP_PRST2 (0x1u << 18) /**< \brief (USBHS_HSTPIP) Pipe 2 Reset */ +#define USBHS_HSTPIP_PRST3 (0x1u << 19) /**< \brief (USBHS_HSTPIP) Pipe 3 Reset */ +#define USBHS_HSTPIP_PRST4 (0x1u << 20) /**< \brief (USBHS_HSTPIP) Pipe 4 Reset */ +#define USBHS_HSTPIP_PRST5 (0x1u << 21) /**< \brief (USBHS_HSTPIP) Pipe 5 Reset */ +#define USBHS_HSTPIP_PRST6 (0x1u << 22) /**< \brief (USBHS_HSTPIP) Pipe 6 Reset */ +#define USBHS_HSTPIP_PRST7 (0x1u << 23) /**< \brief (USBHS_HSTPIP) Pipe 7 Reset */ +#define USBHS_HSTPIP_PRST8 (0x1u << 24) /**< \brief (USBHS_HSTPIP) Pipe 8 Reset */ +/* -------- USBHS_HSTFNUM : (USBHS Offset: 0x0420) Host Frame Number Register -------- */ +#define USBHS_HSTFNUM_MFNUM_Pos 0 +#define USBHS_HSTFNUM_MFNUM_Msk (0x7u << USBHS_HSTFNUM_MFNUM_Pos) /**< \brief (USBHS_HSTFNUM) Micro Frame Number */ +#define USBHS_HSTFNUM_MFNUM(value) ((USBHS_HSTFNUM_MFNUM_Msk & ((value) << USBHS_HSTFNUM_MFNUM_Pos))) +#define USBHS_HSTFNUM_FNUM_Pos 3 +#define USBHS_HSTFNUM_FNUM_Msk (0x7ffu << USBHS_HSTFNUM_FNUM_Pos) /**< \brief (USBHS_HSTFNUM) Frame Number */ +#define USBHS_HSTFNUM_FNUM(value) ((USBHS_HSTFNUM_FNUM_Msk & ((value) << USBHS_HSTFNUM_FNUM_Pos))) +#define USBHS_HSTFNUM_FLENHIGH_Pos 16 +#define USBHS_HSTFNUM_FLENHIGH_Msk (0xffu << USBHS_HSTFNUM_FLENHIGH_Pos) /**< \brief (USBHS_HSTFNUM) Frame Length */ +#define USBHS_HSTFNUM_FLENHIGH(value) ((USBHS_HSTFNUM_FLENHIGH_Msk & ((value) << USBHS_HSTFNUM_FLENHIGH_Pos))) +/* -------- USBHS_HSTADDR1 : (USBHS Offset: 0x0424) Host Address 1 Register -------- */ +#define USBHS_HSTADDR1_HSTADDRP0_Pos 0 +#define USBHS_HSTADDR1_HSTADDRP0_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP0_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP0(value) ((USBHS_HSTADDR1_HSTADDRP0_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP0_Pos))) +#define USBHS_HSTADDR1_HSTADDRP1_Pos 8 +#define USBHS_HSTADDR1_HSTADDRP1_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP1_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP1(value) ((USBHS_HSTADDR1_HSTADDRP1_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP1_Pos))) +#define USBHS_HSTADDR1_HSTADDRP2_Pos 16 +#define USBHS_HSTADDR1_HSTADDRP2_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP2_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP2(value) ((USBHS_HSTADDR1_HSTADDRP2_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP2_Pos))) +#define USBHS_HSTADDR1_HSTADDRP3_Pos 24 +#define USBHS_HSTADDR1_HSTADDRP3_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP3_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP3(value) ((USBHS_HSTADDR1_HSTADDRP3_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP3_Pos))) +/* -------- USBHS_HSTADDR2 : (USBHS Offset: 0x0428) Host Address 2 Register -------- */ +#define USBHS_HSTADDR2_HSTADDRP4_Pos 0 +#define USBHS_HSTADDR2_HSTADDRP4_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP4_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP4(value) ((USBHS_HSTADDR2_HSTADDRP4_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP4_Pos))) +#define USBHS_HSTADDR2_HSTADDRP5_Pos 8 +#define USBHS_HSTADDR2_HSTADDRP5_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP5_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP5(value) ((USBHS_HSTADDR2_HSTADDRP5_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP5_Pos))) +#define USBHS_HSTADDR2_HSTADDRP6_Pos 16 +#define USBHS_HSTADDR2_HSTADDRP6_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP6_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP6(value) ((USBHS_HSTADDR2_HSTADDRP6_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP6_Pos))) +#define USBHS_HSTADDR2_HSTADDRP7_Pos 24 +#define USBHS_HSTADDR2_HSTADDRP7_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP7_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP7(value) ((USBHS_HSTADDR2_HSTADDRP7_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP7_Pos))) +/* -------- USBHS_HSTADDR3 : (USBHS Offset: 0x042C) Host Address 3 Register -------- */ +#define USBHS_HSTADDR3_HSTADDRP8_Pos 0 +#define USBHS_HSTADDR3_HSTADDRP8_Msk (0x7fu << USBHS_HSTADDR3_HSTADDRP8_Pos) /**< \brief (USBHS_HSTADDR3) USB Host Address */ +#define USBHS_HSTADDR3_HSTADDRP8(value) ((USBHS_HSTADDR3_HSTADDRP8_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP8_Pos))) +#define USBHS_HSTADDR3_HSTADDRP9_Pos 8 +#define USBHS_HSTADDR3_HSTADDRP9_Msk (0x7fu << USBHS_HSTADDR3_HSTADDRP9_Pos) /**< \brief (USBHS_HSTADDR3) USB Host Address */ +#define USBHS_HSTADDR3_HSTADDRP9(value) ((USBHS_HSTADDR3_HSTADDRP9_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP9_Pos))) +/* -------- USBHS_HSTPIPCFG[10] : (USBHS Offset: 0x500) Host Pipe Configuration Register (n = 0) -------- */ +#define USBHS_HSTPIPCFG_ALLOC (0x1u << 1) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Memory Allocate */ +#define USBHS_HSTPIPCFG_PBK_Pos 2 +#define USBHS_HSTPIPCFG_PBK_Msk (0x3u << USBHS_HSTPIPCFG_PBK_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Banks */ +#define USBHS_HSTPIPCFG_PBK(value) ((USBHS_HSTPIPCFG_PBK_Msk & ((value) << USBHS_HSTPIPCFG_PBK_Pos))) +#define USBHS_HSTPIPCFG_PBK_1_BANK (0x0u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Single-bank pipe */ +#define USBHS_HSTPIPCFG_PBK_2_BANK (0x1u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Double-bank pipe */ +#define USBHS_HSTPIPCFG_PBK_3_BANK (0x2u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Triple-bank pipe */ +#define USBHS_HSTPIPCFG_PSIZE_Pos 4 +#define USBHS_HSTPIPCFG_PSIZE_Msk (0x7u << USBHS_HSTPIPCFG_PSIZE_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Size */ +#define USBHS_HSTPIPCFG_PSIZE(value) ((USBHS_HSTPIPCFG_PSIZE_Msk & ((value) << USBHS_HSTPIPCFG_PSIZE_Pos))) +#define USBHS_HSTPIPCFG_PSIZE_8_BYTE (0x0u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 8 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_16_BYTE (0x1u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 16 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_32_BYTE (0x2u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 32 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_64_BYTE (0x3u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 64 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_128_BYTE (0x4u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 128 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_256_BYTE (0x5u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 256 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_512_BYTE (0x6u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 512 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_1024_BYTE (0x7u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 1024 bytes */ +#define USBHS_HSTPIPCFG_PTOKEN_Pos 8 +#define USBHS_HSTPIPCFG_PTOKEN_Msk (0x3u << USBHS_HSTPIPCFG_PTOKEN_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Token */ +#define USBHS_HSTPIPCFG_PTOKEN(value) ((USBHS_HSTPIPCFG_PTOKEN_Msk & ((value) << USBHS_HSTPIPCFG_PTOKEN_Pos))) +#define USBHS_HSTPIPCFG_PTOKEN_SETUP (0x0u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) SETUP */ +#define USBHS_HSTPIPCFG_PTOKEN_IN (0x1u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) IN */ +#define USBHS_HSTPIPCFG_PTOKEN_OUT (0x2u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) OUT */ +#define USBHS_HSTPIPCFG_AUTOSW (0x1u << 10) /**< \brief (USBHS_HSTPIPCFG[10]) Automatic Switch */ +#define USBHS_HSTPIPCFG_PTYPE_Pos 12 +#define USBHS_HSTPIPCFG_PTYPE_Msk (0x3u << USBHS_HSTPIPCFG_PTYPE_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Type */ +#define USBHS_HSTPIPCFG_PTYPE(value) ((USBHS_HSTPIPCFG_PTYPE_Msk & ((value) << USBHS_HSTPIPCFG_PTYPE_Pos))) +#define USBHS_HSTPIPCFG_PTYPE_CTRL (0x0u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Control */ +#define USBHS_HSTPIPCFG_PTYPE_ISO (0x1u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Isochronous */ +#define USBHS_HSTPIPCFG_PTYPE_BLK (0x2u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Bulk */ +#define USBHS_HSTPIPCFG_PTYPE_INTRPT (0x3u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Interrupt */ +#define USBHS_HSTPIPCFG_PEPNUM_Pos 16 +#define USBHS_HSTPIPCFG_PEPNUM_Msk (0xfu << USBHS_HSTPIPCFG_PEPNUM_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Endpoint Number */ +#define USBHS_HSTPIPCFG_PEPNUM(value) ((USBHS_HSTPIPCFG_PEPNUM_Msk & ((value) << USBHS_HSTPIPCFG_PEPNUM_Pos))) +#define USBHS_HSTPIPCFG_INTFRQ_Pos 24 +#define USBHS_HSTPIPCFG_INTFRQ_Msk (0xffu << USBHS_HSTPIPCFG_INTFRQ_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Interrupt Request Frequency */ +#define USBHS_HSTPIPCFG_INTFRQ(value) ((USBHS_HSTPIPCFG_INTFRQ_Msk & ((value) << USBHS_HSTPIPCFG_INTFRQ_Pos))) +#define USBHS_HSTPIPCFG_PINGEN (0x1u << 20) /**< \brief (USBHS_HSTPIPCFG[10]) Ping Enable */ +#define USBHS_HSTPIPCFG_BINTERVAL_Pos 24 +#define USBHS_HSTPIPCFG_BINTERVAL_Msk (0xffu << USBHS_HSTPIPCFG_BINTERVAL_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Binterval Parameter for the Bulk-Out/Ping Transaction */ +#define USBHS_HSTPIPCFG_BINTERVAL(value) ((USBHS_HSTPIPCFG_BINTERVAL_Msk & ((value) << USBHS_HSTPIPCFG_BINTERVAL_Pos))) +/* -------- USBHS_HSTPIPISR[10] : (USBHS Offset: 0x530) Host Pipe Status Register (n = 0) -------- */ +#define USBHS_HSTPIPISR_RXINI (0x1u << 0) /**< \brief (USBHS_HSTPIPISR[10]) Received IN Data Interrupt */ +#define USBHS_HSTPIPISR_TXOUTI (0x1u << 1) /**< \brief (USBHS_HSTPIPISR[10]) Transmitted OUT Data Interrupt */ +#define USBHS_HSTPIPISR_TXSTPI (0x1u << 2) /**< \brief (USBHS_HSTPIPISR[10]) Transmitted SETUP Interrupt */ +#define USBHS_HSTPIPISR_PERRI (0x1u << 3) /**< \brief (USBHS_HSTPIPISR[10]) Pipe Error Interrupt */ +#define USBHS_HSTPIPISR_NAKEDI (0x1u << 4) /**< \brief (USBHS_HSTPIPISR[10]) NAKed Interrupt */ +#define USBHS_HSTPIPISR_OVERFI (0x1u << 5) /**< \brief (USBHS_HSTPIPISR[10]) Overflow Interrupt */ +#define USBHS_HSTPIPISR_RXSTALLDI (0x1u << 6) /**< \brief (USBHS_HSTPIPISR[10]) Received STALLed Interrupt */ +#define USBHS_HSTPIPISR_SHORTPACKETI (0x1u << 7) /**< \brief (USBHS_HSTPIPISR[10]) Short Packet Interrupt */ +#define USBHS_HSTPIPISR_DTSEQ_Pos 8 +#define USBHS_HSTPIPISR_DTSEQ_Msk (0x3u << USBHS_HSTPIPISR_DTSEQ_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Data Toggle Sequence */ +#define USBHS_HSTPIPISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (USBHS_HSTPIPISR[10]) Data0 toggle sequence */ +#define USBHS_HSTPIPISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (USBHS_HSTPIPISR[10]) Data1 toggle sequence */ +#define USBHS_HSTPIPISR_NBUSYBK_Pos 12 +#define USBHS_HSTPIPISR_NBUSYBK_Msk (0x3u << USBHS_HSTPIPISR_NBUSYBK_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Number of Busy Banks */ +#define USBHS_HSTPIPISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 0 busy bank (all banks free) */ +#define USBHS_HSTPIPISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 1 busy bank */ +#define USBHS_HSTPIPISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 2 busy banks */ +#define USBHS_HSTPIPISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 3 busy banks */ +#define USBHS_HSTPIPISR_CURRBK_Pos 14 +#define USBHS_HSTPIPISR_CURRBK_Msk (0x3u << USBHS_HSTPIPISR_CURRBK_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Current Bank */ +#define USBHS_HSTPIPISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank0 */ +#define USBHS_HSTPIPISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank1 */ +#define USBHS_HSTPIPISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank2 */ +#define USBHS_HSTPIPISR_RWALL (0x1u << 16) /**< \brief (USBHS_HSTPIPISR[10]) Read/Write Allowed */ +#define USBHS_HSTPIPISR_CFGOK (0x1u << 18) /**< \brief (USBHS_HSTPIPISR[10]) Configuration OK Status */ +#define USBHS_HSTPIPISR_PBYCT_Pos 20 +#define USBHS_HSTPIPISR_PBYCT_Msk (0x7ffu << USBHS_HSTPIPISR_PBYCT_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Pipe Byte Count */ +#define USBHS_HSTPIPISR_UNDERFI (0x1u << 2) /**< \brief (USBHS_HSTPIPISR[10]) Underflow Interrupt */ +#define USBHS_HSTPIPISR_CRCERRI (0x1u << 6) /**< \brief (USBHS_HSTPIPISR[10]) CRC Error Interrupt */ +/* -------- USBHS_HSTPIPICR[10] : (USBHS Offset: 0x560) Host Pipe Clear Register (n = 0) -------- */ +#define USBHS_HSTPIPICR_RXINIC (0x1u << 0) /**< \brief (USBHS_HSTPIPICR[10]) Received IN Data Interrupt Clear */ +#define USBHS_HSTPIPICR_TXOUTIC (0x1u << 1) /**< \brief (USBHS_HSTPIPICR[10]) Transmitted OUT Data Interrupt Clear */ +#define USBHS_HSTPIPICR_TXSTPIC (0x1u << 2) /**< \brief (USBHS_HSTPIPICR[10]) Transmitted SETUP Interrupt Clear */ +#define USBHS_HSTPIPICR_NAKEDIC (0x1u << 4) /**< \brief (USBHS_HSTPIPICR[10]) NAKed Interrupt Clear */ +#define USBHS_HSTPIPICR_OVERFIC (0x1u << 5) /**< \brief (USBHS_HSTPIPICR[10]) Overflow Interrupt Clear */ +#define USBHS_HSTPIPICR_RXSTALLDIC (0x1u << 6) /**< \brief (USBHS_HSTPIPICR[10]) Received STALLed Interrupt Clear */ +#define USBHS_HSTPIPICR_SHORTPACKETIC (0x1u << 7) /**< \brief (USBHS_HSTPIPICR[10]) Short Packet Interrupt Clear */ +#define USBHS_HSTPIPICR_UNDERFIC (0x1u << 2) /**< \brief (USBHS_HSTPIPICR[10]) Underflow Interrupt Clear */ +#define USBHS_HSTPIPICR_CRCERRIC (0x1u << 6) /**< \brief (USBHS_HSTPIPICR[10]) CRC Error Interrupt Clear */ +/* -------- USBHS_HSTPIPIFR[10] : (USBHS Offset: 0x590) Host Pipe Set Register (n = 0) -------- */ +#define USBHS_HSTPIPIFR_RXINIS (0x1u << 0) /**< \brief (USBHS_HSTPIPIFR[10]) Received IN Data Interrupt Set */ +#define USBHS_HSTPIPIFR_TXOUTIS (0x1u << 1) /**< \brief (USBHS_HSTPIPIFR[10]) Transmitted OUT Data Interrupt Set */ +#define USBHS_HSTPIPIFR_TXSTPIS (0x1u << 2) /**< \brief (USBHS_HSTPIPIFR[10]) Transmitted SETUP Interrupt Set */ +#define USBHS_HSTPIPIFR_PERRIS (0x1u << 3) /**< \brief (USBHS_HSTPIPIFR[10]) Pipe Error Interrupt Set */ +#define USBHS_HSTPIPIFR_NAKEDIS (0x1u << 4) /**< \brief (USBHS_HSTPIPIFR[10]) NAKed Interrupt Set */ +#define USBHS_HSTPIPIFR_OVERFIS (0x1u << 5) /**< \brief (USBHS_HSTPIPIFR[10]) Overflow Interrupt Set */ +#define USBHS_HSTPIPIFR_RXSTALLDIS (0x1u << 6) /**< \brief (USBHS_HSTPIPIFR[10]) Received STALLed Interrupt Set */ +#define USBHS_HSTPIPIFR_SHORTPACKETIS (0x1u << 7) /**< \brief (USBHS_HSTPIPIFR[10]) Short Packet Interrupt Set */ +#define USBHS_HSTPIPIFR_NBUSYBKS (0x1u << 12) /**< \brief (USBHS_HSTPIPIFR[10]) Number of Busy Banks Set */ +#define USBHS_HSTPIPIFR_UNDERFIS (0x1u << 2) /**< \brief (USBHS_HSTPIPIFR[10]) Underflow Interrupt Set */ +#define USBHS_HSTPIPIFR_CRCERRIS (0x1u << 6) /**< \brief (USBHS_HSTPIPIFR[10]) CRC Error Interrupt Set */ +/* -------- USBHS_HSTPIPIMR[10] : (USBHS Offset: 0x5C0) Host Pipe Mask Register (n = 0) -------- */ +#define USBHS_HSTPIPIMR_RXINE (0x1u << 0) /**< \brief (USBHS_HSTPIPIMR[10]) Received IN Data Interrupt Enable */ +#define USBHS_HSTPIPIMR_TXOUTE (0x1u << 1) /**< \brief (USBHS_HSTPIPIMR[10]) Transmitted OUT Data Interrupt Enable */ +#define USBHS_HSTPIPIMR_TXSTPE (0x1u << 2) /**< \brief (USBHS_HSTPIPIMR[10]) Transmitted SETUP Interrupt Enable */ +#define USBHS_HSTPIPIMR_PERRE (0x1u << 3) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Error Interrupt Enable */ +#define USBHS_HSTPIPIMR_NAKEDE (0x1u << 4) /**< \brief (USBHS_HSTPIPIMR[10]) NAKed Interrupt Enable */ +#define USBHS_HSTPIPIMR_OVERFIE (0x1u << 5) /**< \brief (USBHS_HSTPIPIMR[10]) Overflow Interrupt Enable */ +#define USBHS_HSTPIPIMR_RXSTALLDE (0x1u << 6) /**< \brief (USBHS_HSTPIPIMR[10]) Received STALLed Interrupt Enable */ +#define USBHS_HSTPIPIMR_SHORTPACKETIE (0x1u << 7) /**< \brief (USBHS_HSTPIPIMR[10]) Short Packet Interrupt Enable */ +#define USBHS_HSTPIPIMR_NBUSYBKE (0x1u << 12) /**< \brief (USBHS_HSTPIPIMR[10]) Number of Busy Banks Interrupt Enable */ +#define USBHS_HSTPIPIMR_FIFOCON (0x1u << 14) /**< \brief (USBHS_HSTPIPIMR[10]) FIFO Control */ +#define USBHS_HSTPIPIMR_PDISHDMA (0x1u << 16) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Interrupts Disable HDMA Request Enable */ +#define USBHS_HSTPIPIMR_PFREEZE (0x1u << 17) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Freeze */ +#define USBHS_HSTPIPIMR_RSTDT (0x1u << 18) /**< \brief (USBHS_HSTPIPIMR[10]) Reset Data Toggle */ +#define USBHS_HSTPIPIMR_UNDERFIE (0x1u << 2) /**< \brief (USBHS_HSTPIPIMR[10]) Underflow Interrupt Enable */ +#define USBHS_HSTPIPIMR_CRCERRE (0x1u << 6) /**< \brief (USBHS_HSTPIPIMR[10]) CRC Error Interrupt Enable */ +/* -------- USBHS_HSTPIPIER[10] : (USBHS Offset: 0x5F0) Host Pipe Enable Register (n = 0) -------- */ +#define USBHS_HSTPIPIER_RXINES (0x1u << 0) /**< \brief (USBHS_HSTPIPIER[10]) Received IN Data Interrupt Enable */ +#define USBHS_HSTPIPIER_TXOUTES (0x1u << 1) /**< \brief (USBHS_HSTPIPIER[10]) Transmitted OUT Data Interrupt Enable */ +#define USBHS_HSTPIPIER_TXSTPES (0x1u << 2) /**< \brief (USBHS_HSTPIPIER[10]) Transmitted SETUP Interrupt Enable */ +#define USBHS_HSTPIPIER_PERRES (0x1u << 3) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Error Interrupt Enable */ +#define USBHS_HSTPIPIER_NAKEDES (0x1u << 4) /**< \brief (USBHS_HSTPIPIER[10]) NAKed Interrupt Enable */ +#define USBHS_HSTPIPIER_OVERFIES (0x1u << 5) /**< \brief (USBHS_HSTPIPIER[10]) Overflow Interrupt Enable */ +#define USBHS_HSTPIPIER_RXSTALLDES (0x1u << 6) /**< \brief (USBHS_HSTPIPIER[10]) Received STALLed Interrupt Enable */ +#define USBHS_HSTPIPIER_SHORTPACKETIES (0x1u << 7) /**< \brief (USBHS_HSTPIPIER[10]) Short Packet Interrupt Enable */ +#define USBHS_HSTPIPIER_NBUSYBKES (0x1u << 12) /**< \brief (USBHS_HSTPIPIER[10]) Number of Busy Banks Enable */ +#define USBHS_HSTPIPIER_PDISHDMAS (0x1u << 16) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Interrupts Disable HDMA Request Enable */ +#define USBHS_HSTPIPIER_PFREEZES (0x1u << 17) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Freeze Enable */ +#define USBHS_HSTPIPIER_RSTDTS (0x1u << 18) /**< \brief (USBHS_HSTPIPIER[10]) Reset Data Toggle Enable */ +#define USBHS_HSTPIPIER_UNDERFIES (0x1u << 2) /**< \brief (USBHS_HSTPIPIER[10]) Underflow Interrupt Enable */ +#define USBHS_HSTPIPIER_CRCERRES (0x1u << 6) /**< \brief (USBHS_HSTPIPIER[10]) CRC Error Interrupt Enable */ +/* -------- USBHS_HSTPIPIDR[10] : (USBHS Offset: 0x620) Host Pipe Disable Register (n = 0) -------- */ +#define USBHS_HSTPIPIDR_RXINEC (0x1u << 0) /**< \brief (USBHS_HSTPIPIDR[10]) Received IN Data Interrupt Disable */ +#define USBHS_HSTPIPIDR_TXOUTEC (0x1u << 1) /**< \brief (USBHS_HSTPIPIDR[10]) Transmitted OUT Data Interrupt Disable */ +#define USBHS_HSTPIPIDR_TXSTPEC (0x1u << 2) /**< \brief (USBHS_HSTPIPIDR[10]) Transmitted SETUP Interrupt Disable */ +#define USBHS_HSTPIPIDR_PERREC (0x1u << 3) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Error Interrupt Disable */ +#define USBHS_HSTPIPIDR_NAKEDEC (0x1u << 4) /**< \brief (USBHS_HSTPIPIDR[10]) NAKed Interrupt Disable */ +#define USBHS_HSTPIPIDR_OVERFIEC (0x1u << 5) /**< \brief (USBHS_HSTPIPIDR[10]) Overflow Interrupt Disable */ +#define USBHS_HSTPIPIDR_RXSTALLDEC (0x1u << 6) /**< \brief (USBHS_HSTPIPIDR[10]) Received STALLed Interrupt Disable */ +#define USBHS_HSTPIPIDR_SHORTPACKETIEC (0x1u << 7) /**< \brief (USBHS_HSTPIPIDR[10]) Short Packet Interrupt Disable */ +#define USBHS_HSTPIPIDR_NBUSYBKEC (0x1u << 12) /**< \brief (USBHS_HSTPIPIDR[10]) Number of Busy Banks Disable */ +#define USBHS_HSTPIPIDR_FIFOCONC (0x1u << 14) /**< \brief (USBHS_HSTPIPIDR[10]) FIFO Control Disable */ +#define USBHS_HSTPIPIDR_PDISHDMAC (0x1u << 16) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Interrupts Disable HDMA Request Disable */ +#define USBHS_HSTPIPIDR_PFREEZEC (0x1u << 17) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Freeze Disable */ +#define USBHS_HSTPIPIDR_UNDERFIEC (0x1u << 2) /**< \brief (USBHS_HSTPIPIDR[10]) Underflow Interrupt Disable */ +#define USBHS_HSTPIPIDR_CRCERREC (0x1u << 6) /**< \brief (USBHS_HSTPIPIDR[10]) CRC Error Interrupt Disable */ +/* -------- USBHS_HSTPIPINRQ[10] : (USBHS Offset: 0x650) Host Pipe IN Request Register (n = 0) -------- */ +#define USBHS_HSTPIPINRQ_INRQ_Pos 0 +#define USBHS_HSTPIPINRQ_INRQ_Msk (0xffu << USBHS_HSTPIPINRQ_INRQ_Pos) /**< \brief (USBHS_HSTPIPINRQ[10]) IN Request Number before Freeze */ +#define USBHS_HSTPIPINRQ_INRQ(value) ((USBHS_HSTPIPINRQ_INRQ_Msk & ((value) << USBHS_HSTPIPINRQ_INRQ_Pos))) +#define USBHS_HSTPIPINRQ_INMODE (0x1u << 8) /**< \brief (USBHS_HSTPIPINRQ[10]) IN Request Mode */ +/* -------- USBHS_HSTPIPERR[10] : (USBHS Offset: 0x680) Host Pipe Error Register (n = 0) -------- */ +#define USBHS_HSTPIPERR_DATATGL (0x1u << 0) /**< \brief (USBHS_HSTPIPERR[10]) Data Toggle Error */ +#define USBHS_HSTPIPERR_DATAPID (0x1u << 1) /**< \brief (USBHS_HSTPIPERR[10]) Data PID Error */ +#define USBHS_HSTPIPERR_PID (0x1u << 2) /**< \brief (USBHS_HSTPIPERR[10]) Data PID Error */ +#define USBHS_HSTPIPERR_TIMEOUT (0x1u << 3) /**< \brief (USBHS_HSTPIPERR[10]) Time-Out Error */ +#define USBHS_HSTPIPERR_CRC16 (0x1u << 4) /**< \brief (USBHS_HSTPIPERR[10]) CRC16 Error */ +#define USBHS_HSTPIPERR_COUNTER_Pos 5 +#define USBHS_HSTPIPERR_COUNTER_Msk (0x3u << USBHS_HSTPIPERR_COUNTER_Pos) /**< \brief (USBHS_HSTPIPERR[10]) Error Counter */ +#define USBHS_HSTPIPERR_COUNTER(value) ((USBHS_HSTPIPERR_COUNTER_Msk & ((value) << USBHS_HSTPIPERR_COUNTER_Pos))) +/* -------- USBHS_HSTDMANXTDSC : (USBHS Offset: N/A) Host DMA Channel Next Descriptor Address Register -------- */ +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos 0 +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (USBHS_HSTDMANXTDSC) Next Descriptor Address */ +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD(value) ((USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos))) +/* -------- USBHS_HSTDMAADDRESS : (USBHS Offset: N/A) Host DMA Channel Address Register -------- */ +#define USBHS_HSTDMAADDRESS_BUFF_ADD_Pos 0 +#define USBHS_HSTDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos) /**< \brief (USBHS_HSTDMAADDRESS) Buffer Address */ +#define USBHS_HSTDMAADDRESS_BUFF_ADD(value) ((USBHS_HSTDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos))) +/* -------- USBHS_HSTDMACONTROL : (USBHS Offset: N/A) Host DMA Channel Control Register -------- */ +#define USBHS_HSTDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_HSTDMACONTROL) Channel Enable Command */ +#define USBHS_HSTDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (USBHS_HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */ +#define USBHS_HSTDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (USBHS_HSTDMACONTROL) End of Transfer Enable Control (OUT transfers only) */ +#define USBHS_HSTDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (USBHS_HSTDMACONTROL) End of Buffer Enable Control */ +#define USBHS_HSTDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (USBHS_HSTDMACONTROL) End of Transfer Interrupt Enable */ +#define USBHS_HSTDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (USBHS_HSTDMACONTROL) End of Buffer Interrupt Enable */ +#define USBHS_HSTDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (USBHS_HSTDMACONTROL) Descriptor Loaded Interrupt Enable */ +#define USBHS_HSTDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (USBHS_HSTDMACONTROL) Burst Lock Enable */ +#define USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos 16 +#define USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk (0xffffu << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (USBHS_HSTDMACONTROL) Buffer Byte Length (Write-only) */ +#define USBHS_HSTDMACONTROL_BUFF_LENGTH(value) ((USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos))) +/* -------- USBHS_HSTDMASTATUS : (USBHS Offset: N/A) Host DMA Channel Status Register -------- */ +#define USBHS_HSTDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_HSTDMASTATUS) Channel Enable Status */ +#define USBHS_HSTDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (USBHS_HSTDMASTATUS) Channel Active Status */ +#define USBHS_HSTDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (USBHS_HSTDMASTATUS) End of Channel Transfer Status */ +#define USBHS_HSTDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (USBHS_HSTDMASTATUS) End of Channel Buffer Status */ +#define USBHS_HSTDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (USBHS_HSTDMASTATUS) Descriptor Loaded Status */ +#define USBHS_HSTDMASTATUS_BUFF_COUNT_Pos 16 +#define USBHS_HSTDMASTATUS_BUFF_COUNT_Msk (0xffffu << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos) /**< \brief (USBHS_HSTDMASTATUS) Buffer Byte Count */ +#define USBHS_HSTDMASTATUS_BUFF_COUNT(value) ((USBHS_HSTDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos))) +/* -------- USBHS_CTRL : (USBHS Offset: 0x0800) General Control Register -------- */ +#define USBHS_CTRL_RDERRE (0x1u << 4) /**< \brief (USBHS_CTRL) Remote Device Connection Error Interrupt Enable */ +#define USBHS_CTRL_VBUSHWC (0x1u << 8) /**< \brief (USBHS_CTRL) VBUS Hardware Control */ +#define USBHS_CTRL_FRZCLK (0x1u << 14) /**< \brief (USBHS_CTRL) Freeze USB Clock */ +#define USBHS_CTRL_USBE (0x1u << 15) /**< \brief (USBHS_CTRL) USBHS Enable */ +#define USBHS_CTRL_UIMOD (0x1u << 25) /**< \brief (USBHS_CTRL) USBHS Mode */ +#define USBHS_CTRL_UIMOD_HOST (0x0u << 25) /**< \brief (USBHS_CTRL) The module is in USB Host mode. */ +#define USBHS_CTRL_UIMOD_DEVICE (0x1u << 25) /**< \brief (USBHS_CTRL) The module is in USB Device mode. */ +/* -------- USBHS_SR : (USBHS Offset: 0x0804) General Status Register -------- */ +#define USBHS_SR_RDERRI (0x1u << 4) /**< \brief (USBHS_SR) Remote Device Connection Error Interrupt (Host mode only) */ +#define USBHS_SR_VBUSRQ (0x1u << 9) /**< \brief (USBHS_SR) VBus Request (Host mode only) */ +#define USBHS_SR_SPEED_Pos 12 +#define USBHS_SR_SPEED_Msk (0x3u << USBHS_SR_SPEED_Pos) /**< \brief (USBHS_SR) Speed Status (Device mode only) */ +#define USBHS_SR_SPEED_FULL_SPEED (0x0u << 12) /**< \brief (USBHS_SR) Full-Speed mode */ +#define USBHS_SR_SPEED_HIGH_SPEED (0x1u << 12) /**< \brief (USBHS_SR) High-Speed mode */ +#define USBHS_SR_SPEED_LOW_SPEED (0x2u << 12) /**< \brief (USBHS_SR) Low-Speed mode */ +#define USBHS_SR_CLKUSABLE (0x1u << 14) /**< \brief (USBHS_SR) UTMI Clock Usable */ +/* -------- USBHS_SCR : (USBHS Offset: 0x0808) General Status Clear Register -------- */ +#define USBHS_SCR_RDERRIC (0x1u << 4) /**< \brief (USBHS_SCR) Remote Device Connection Error Interrupt Clear */ +#define USBHS_SCR_VBUSRQC (0x1u << 9) /**< \brief (USBHS_SCR) VBus Request Clear */ +/* -------- USBHS_SFR : (USBHS Offset: 0x080C) General Status Set Register -------- */ +#define USBHS_SFR_RDERRIS (0x1u << 4) /**< \brief (USBHS_SFR) Remote Device Connection Error Interrupt Set */ +#define USBHS_SFR_VBUSRQS (0x1u << 9) /**< \brief (USBHS_SFR) VBus Request Set */ +/* -------- USBHS_TSTA1 : (USBHS Offset: 0x0810) General Test A1 Register -------- */ +#define USBHS_TSTA1_CounterA_Pos 0 +#define USBHS_TSTA1_CounterA_Msk (0x7fffu << USBHS_TSTA1_CounterA_Pos) /**< \brief (USBHS_TSTA1) Counter A */ +#define USBHS_TSTA1_CounterA(value) ((USBHS_TSTA1_CounterA_Msk & ((value) << USBHS_TSTA1_CounterA_Pos))) +#define USBHS_TSTA1_LoadCntA (0x1u << 15) /**< \brief (USBHS_TSTA1) Load CounterA */ +#define USBHS_TSTA1_CounterB_Pos 16 +#define USBHS_TSTA1_CounterB_Msk (0x3fu << USBHS_TSTA1_CounterB_Pos) /**< \brief (USBHS_TSTA1) Counter B */ +#define USBHS_TSTA1_CounterB(value) ((USBHS_TSTA1_CounterB_Msk & ((value) << USBHS_TSTA1_CounterB_Pos))) +#define USBHS_TSTA1_LoadCntB (0x1u << 23) /**< \brief (USBHS_TSTA1) Load CounterB */ +#define USBHS_TSTA1_SOFCntMa1_Pos 24 +#define USBHS_TSTA1_SOFCntMa1_Msk (0x7fu << USBHS_TSTA1_SOFCntMa1_Pos) /**< \brief (USBHS_TSTA1) SOF Counter Max */ +#define USBHS_TSTA1_SOFCntMa1(value) ((USBHS_TSTA1_SOFCntMa1_Msk & ((value) << USBHS_TSTA1_SOFCntMa1_Pos))) +#define USBHS_TSTA1_LoadSOFCnt (0x1u << 31) /**< \brief (USBHS_TSTA1) Load SOF Counter */ +/* -------- USBHS_TSTA2 : (USBHS Offset: 0x0814) General Test A2 Register -------- */ +#define USBHS_TSTA2_FullDetachEn (0x1u << 0) /**< \brief (USBHS_TSTA2) Full Detach Enable */ +#define USBHS_TSTA2_HSSerialMode (0x1u << 1) /**< \brief (USBHS_TSTA2) HS Serial Mode */ +#define USBHS_TSTA2_LoopBackMode (0x1u << 2) /**< \brief (USBHS_TSTA2) Loop-back Mode */ +#define USBHS_TSTA2_DisableGatedClock (0x1u << 3) /**< \brief (USBHS_TSTA2) Disable Gated Clock */ +#define USBHS_TSTA2_ForceSuspendMTo1 (0x1u << 4) /**< \brief (USBHS_TSTA2) Force SuspendM to 1 */ +#define USBHS_TSTA2_ByPassDpll (0x1u << 5) /**< \brief (USBHS_TSTA2) Bypass DPLL */ +#define USBHS_TSTA2_HostHSDisconnectDisable (0x1u << 6) /**< \brief (USBHS_TSTA2) Host HS Disconnect Disable */ +#define USBHS_TSTA2_ForceHSRst_50ms (0x1u << 7) /**< \brief (USBHS_TSTA2) Force HS Reset to 50 ms */ +#define USBHS_TSTA2_RemovePUWhenTX (0x1u << 9) /**< \brief (USBHS_TSTA2) Remove Pull-up When TX */ +/* -------- USBHS_VERSION : (USBHS Offset: 0x0818) General Version Register -------- */ +#define USBHS_VERSION_VERSION_Pos 0 +#define USBHS_VERSION_VERSION_Msk (0xfffu << USBHS_VERSION_VERSION_Pos) /**< \brief (USBHS_VERSION) Version Number */ +#define USBHS_VERSION_MFN_Pos 16 +#define USBHS_VERSION_MFN_Msk (0xfu << USBHS_VERSION_MFN_Pos) /**< \brief (USBHS_VERSION) Metal Fix Number */ +/* -------- USBHS_FSM : (USBHS Offset: 0x082C) General Finite State Machine Register -------- */ +#define USBHS_FSM_DRDSTATE_Pos 0 +#define USBHS_FSM_DRDSTATE_Msk (0xfu << USBHS_FSM_DRDSTATE_Pos) /**< \brief (USBHS_FSM) Dual Role Device State */ +#define USBHS_FSM_DRDSTATE_A_IDLESTATE (0x0u << 0) /**< \brief (USBHS_FSM) This is the start state for A-devices (when the ID pin is 0) */ +#define USBHS_FSM_DRDSTATE_A_WAIT_VRISE (0x1u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for the voltage on VBus to rise above the A-device VBus Valid threshold (4.4 V). */ +#define USBHS_FSM_DRDSTATE_A_WAIT_BCON (0x2u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for the B-device to signal a connection. */ +#define USBHS_FSM_DRDSTATE_A_HOST (0x3u << 0) /**< \brief (USBHS_FSM) In this state, the A-device that operates in Host mode is operational. */ +#define USBHS_FSM_DRDSTATE_A_SUSPEND (0x4u << 0) /**< \brief (USBHS_FSM) The A-device operating as a host is in the Suspend mode. */ +#define USBHS_FSM_DRDSTATE_A_PERIPHERAL (0x5u << 0) /**< \brief (USBHS_FSM) The A-device operates as a peripheral. */ +#define USBHS_FSM_DRDSTATE_A_WAIT_VFALL (0x6u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for the voltage on VBus to drop below the A-device Session Valid threshold (1.4 V). */ +#define USBHS_FSM_DRDSTATE_A_VBUS_ERR (0x7u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for recovery of the over-current condition that caused it to enter this state. */ +#define USBHS_FSM_DRDSTATE_A_WAIT_DISCHARGE (0x8u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for the data USB line to discharge (100 us). */ +#define USBHS_FSM_DRDSTATE_B_IDLE (0x9u << 0) /**< \brief (USBHS_FSM) This is the start state for B-device (when the ID pin is 1). */ +#define USBHS_FSM_DRDSTATE_B_PERIPHERAL (0xAu << 0) /**< \brief (USBHS_FSM) In this state, the B-device acts as the peripheral. */ +#define USBHS_FSM_DRDSTATE_B_WAIT_BEGIN_HNP (0xBu << 0) /**< \brief (USBHS_FSM) In this state, the B-device is in Suspend mode and waits until 3 ms before initiating the HNP protocol if requested. */ +#define USBHS_FSM_DRDSTATE_B_WAIT_DISCHARGE (0xCu << 0) /**< \brief (USBHS_FSM) In this state, the B-device waits for the data USB line to discharge (100 us)) before becoming Host. */ +#define USBHS_FSM_DRDSTATE_B_WAIT_ACON (0xDu << 0) /**< \brief (USBHS_FSM) In this state, the B-device waits for the A-device to signal a connect before becoming B-Host. */ +#define USBHS_FSM_DRDSTATE_B_HOST (0xEu << 0) /**< \brief (USBHS_FSM) In this state, the B-device acts as the Host. */ +#define USBHS_FSM_DRDSTATE_B_SRP_INIT (0xFu << 0) /**< \brief (USBHS_FSM) In this state, the B-device attempts to start a session using the SRP protocol. */ + +/*@}*/ + + +#endif /* _SAME70_USBHS_COMPONENT_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/utmi.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/utmi.h new file mode 100644 index 000000000..89fcd7250 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/utmi.h @@ -0,0 +1,68 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_UTMI_COMPONENT_ +#define _SAME70_UTMI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR USB Transmitter Interface Macrocell */ +/* ============================================================================= */ +/** \addtogroup SAME70_UTMI USB Transmitter Interface Macrocell */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Utmi hardware registers */ +typedef struct { + __I uint32_t Reserved1[4]; + __IO uint32_t UTMI_OHCIICR; /**< \brief (Utmi Offset: 0x10) OHCI Interrupt Configuration Register */ + __I uint32_t Reserved2[7]; + __IO uint32_t UTMI_CKTRIM; /**< \brief (Utmi Offset: 0x30) UTMI Clock Trimming Register */ +} Utmi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- UTMI_OHCIICR : (UTMI Offset: 0x10) OHCI Interrupt Configuration Register -------- */ +#define UTMI_OHCIICR_RES0 (0x1u << 0) /**< \brief (UTMI_OHCIICR) USB PORTx Reset */ +#define UTMI_OHCIICR_ARIE (0x1u << 4) /**< \brief (UTMI_OHCIICR) OHCI Asynchronous Resume Interrupt Enable */ +#define UTMI_OHCIICR_APPSTART (0x1u << 5) /**< \brief (UTMI_OHCIICR) Reserved */ +#define UTMI_OHCIICR_UDPPUDIS (0x1u << 23) /**< \brief (UTMI_OHCIICR) USB Device Pull-up Disable */ +/* -------- UTMI_CKTRIM : (UTMI Offset: 0x30) UTMI Clock Trimming Register -------- */ +#define UTMI_CKTRIM_FREQ_Pos 0 +#define UTMI_CKTRIM_FREQ_Msk (0x3u << UTMI_CKTRIM_FREQ_Pos) /**< \brief (UTMI_CKTRIM) UTMI Reference Clock Frequency */ +#define UTMI_CKTRIM_FREQ(value) ((UTMI_CKTRIM_FREQ_Msk & ((value) << UTMI_CKTRIM_FREQ_Pos))) +#define UTMI_CKTRIM_FREQ_XTAL12 (0x0u << 0) /**< \brief (UTMI_CKTRIM) 12 MHz reference clock */ +#define UTMI_CKTRIM_FREQ_XTAL16 (0x1u << 0) /**< \brief (UTMI_CKTRIM) 16 MHz reference clock */ + +/*@}*/ + + +#endif /* _SAME70_UTMI_COMPONENT_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/wdt.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/wdt.h new file mode 100644 index 000000000..655c99346 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/wdt.h @@ -0,0 +1,77 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_WDT_COMPONENT_ +#define _SAME70_WDT_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Watchdog Timer */ +/* ============================================================================= */ +/** \addtogroup SAME70_WDT Watchdog Timer */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Wdt hardware registers */ +typedef struct { + __O uint32_t WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */ + __IO uint32_t WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */ + __I uint32_t WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */ +} Wdt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */ +#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */ +#define WDT_CR_KEY_Pos 24 +#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */ +#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos))) +#define WDT_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (WDT_CR) Writing any other value in this field aborts the write operation. */ +/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */ +#define WDT_MR_WDV_Pos 0 +#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */ +#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos))) +#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */ +#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */ +#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */ +#define WDT_MR_WDD_Pos 16 +#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */ +#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos))) +#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */ +#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */ +/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */ +#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow (cleared on read) */ +#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error (cleared on read) */ + +/*@}*/ + + +#endif /* _SAME70_WDT_COMPONENT_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/xdmac.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/xdmac.h new file mode 100644 index 000000000..9c8bd2117 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/component/xdmac.h @@ -0,0 +1,633 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_XDMAC_COMPONENT_ +#define _SAME70_XDMAC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Extensible DMA Controller */ +/* ============================================================================= */ +/** \addtogroup SAME70_XDMAC Extensible DMA Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief XdmacChid hardware registers */ +typedef struct { + __O uint32_t XDMAC_CIE; /**< \brief (XdmacChid Offset: 0x0) Channel Interrupt Enable Register */ + __O uint32_t XDMAC_CID; /**< \brief (XdmacChid Offset: 0x4) Channel Interrupt Disable Register */ + __I uint32_t XDMAC_CIM; /**< \brief (XdmacChid Offset: 0x8) Channel Interrupt Mask Register */ + __I uint32_t XDMAC_CIS; /**< \brief (XdmacChid Offset: 0xC) Channel Interrupt Status Register */ + __IO uint32_t XDMAC_CSA; /**< \brief (XdmacChid Offset: 0x10) Channel Source Address Register */ + __IO uint32_t XDMAC_CDA; /**< \brief (XdmacChid Offset: 0x14) Channel Destination Address Register */ + __IO uint32_t XDMAC_CNDA; /**< \brief (XdmacChid Offset: 0x18) Channel Next Descriptor Address Register */ + __IO uint32_t XDMAC_CNDC; /**< \brief (XdmacChid Offset: 0x1C) Channel Next Descriptor Control Register */ + __IO uint32_t XDMAC_CUBC; /**< \brief (XdmacChid Offset: 0x20) Channel Microblock Control Register */ + __IO uint32_t XDMAC_CBC; /**< \brief (XdmacChid Offset: 0x24) Channel Block Control Register */ + __IO uint32_t XDMAC_CC; /**< \brief (XdmacChid Offset: 0x28) Channel Configuration Register */ + __IO uint32_t XDMAC_CDS_MSP; /**< \brief (XdmacChid Offset: 0x2C) Channel Data Stride Memory Set Pattern */ + __IO uint32_t XDMAC_CSUS; /**< \brief (XdmacChid Offset: 0x30) Channel Source Microblock Stride */ + __IO uint32_t XDMAC_CDUS; /**< \brief (XdmacChid Offset: 0x34) Channel Destination Microblock Stride */ + __I uint32_t Reserved1[2]; +} XdmacChid; +/** \brief Xdmac hardware registers */ +#define XDMACCHID_NUMBER 24 +typedef struct { + __I uint32_t XDMAC_GTYPE; /**< \brief (Xdmac Offset: 0x00) Global Type Register */ + __IO uint32_t XDMAC_GCFG; /**< \brief (Xdmac Offset: 0x04) Global Configuration Register */ + __IO uint32_t XDMAC_GWAC; /**< \brief (Xdmac Offset: 0x08) Global Weighted Arbiter Configuration Register */ + __O uint32_t XDMAC_GIE; /**< \brief (Xdmac Offset: 0x0C) Global Interrupt Enable Register */ + __O uint32_t XDMAC_GID; /**< \brief (Xdmac Offset: 0x10) Global Interrupt Disable Register */ + __I uint32_t XDMAC_GIM; /**< \brief (Xdmac Offset: 0x14) Global Interrupt Mask Register */ + __I uint32_t XDMAC_GIS; /**< \brief (Xdmac Offset: 0x18) Global Interrupt Status Register */ + __O uint32_t XDMAC_GE; /**< \brief (Xdmac Offset: 0x1C) Global Channel Enable Register */ + __O uint32_t XDMAC_GD; /**< \brief (Xdmac Offset: 0x20) Global Channel Disable Register */ + __I uint32_t XDMAC_GS; /**< \brief (Xdmac Offset: 0x24) Global Channel Status Register */ + __IO uint32_t XDMAC_GRS; /**< \brief (Xdmac Offset: 0x28) Global Channel Read Suspend Register */ + __IO uint32_t XDMAC_GWS; /**< \brief (Xdmac Offset: 0x2C) Global Channel Write Suspend Register */ + __O uint32_t XDMAC_GRWS; /**< \brief (Xdmac Offset: 0x30) Global Channel Read Write Suspend Register */ + __O uint32_t XDMAC_GRWR; /**< \brief (Xdmac Offset: 0x34) Global Channel Read Write Resume Register */ + __O uint32_t XDMAC_GSWR; /**< \brief (Xdmac Offset: 0x38) Global Channel Software Request Register */ + __I uint32_t XDMAC_GSWS; /**< \brief (Xdmac Offset: 0x3C) Global Channel Software Request Status Register */ + __O uint32_t XDMAC_GSWF; /**< \brief (Xdmac Offset: 0x40) Global Channel Software Flush Request Register */ + __I uint32_t Reserved1[3]; + XdmacChid XDMAC_CHID[XDMACCHID_NUMBER]; /**< \brief (Xdmac Offset: 0x50) chid = 0 .. 23 */ + __I uint32_t Reserved2[619]; + __IO uint32_t XDMAC_VERSION; /**< \brief (Xdmac Offset: 0xFFC) XDMAC Version Register */ +} Xdmac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- XDMAC_GTYPE : (XDMAC Offset: 0x00) Global Type Register -------- */ +#define XDMAC_GTYPE_NB_CH_Pos 0 +#define XDMAC_GTYPE_NB_CH_Msk (0x1fu << XDMAC_GTYPE_NB_CH_Pos) /**< \brief (XDMAC_GTYPE) Number of Channels Minus One */ +#define XDMAC_GTYPE_NB_CH(value) ((XDMAC_GTYPE_NB_CH_Msk & ((value) << XDMAC_GTYPE_NB_CH_Pos))) +#define XDMAC_GTYPE_FIFO_SZ_Pos 5 +#define XDMAC_GTYPE_FIFO_SZ_Msk (0x7ffu << XDMAC_GTYPE_FIFO_SZ_Pos) /**< \brief (XDMAC_GTYPE) Number of Bytes */ +#define XDMAC_GTYPE_FIFO_SZ(value) ((XDMAC_GTYPE_FIFO_SZ_Msk & ((value) << XDMAC_GTYPE_FIFO_SZ_Pos))) +#define XDMAC_GTYPE_NB_REQ_Pos 16 +#define XDMAC_GTYPE_NB_REQ_Msk (0x7fu << XDMAC_GTYPE_NB_REQ_Pos) /**< \brief (XDMAC_GTYPE) Number of Peripheral Requests Minus One */ +#define XDMAC_GTYPE_NB_REQ(value) ((XDMAC_GTYPE_NB_REQ_Msk & ((value) << XDMAC_GTYPE_NB_REQ_Pos))) +/* -------- XDMAC_GCFG : (XDMAC Offset: 0x04) Global Configuration Register -------- */ +#define XDMAC_GCFG_CGDISREG (0x1u << 0) /**< \brief (XDMAC_GCFG) Configuration Registers Clock Gating Disable */ +#define XDMAC_GCFG_CGDISPIPE (0x1u << 1) /**< \brief (XDMAC_GCFG) Pipeline Clock Gating Disable */ +#define XDMAC_GCFG_CGDISFIFO (0x1u << 2) /**< \brief (XDMAC_GCFG) FIFO Clock Gating Disable */ +#define XDMAC_GCFG_CGDISIF (0x1u << 3) /**< \brief (XDMAC_GCFG) Bus Interface Clock Gating Disable */ +#define XDMAC_GCFG_BXKBEN (0x1u << 8) /**< \brief (XDMAC_GCFG) Boundary X Kilo byte Enable */ +/* -------- XDMAC_GWAC : (XDMAC Offset: 0x08) Global Weighted Arbiter Configuration Register -------- */ +#define XDMAC_GWAC_PW0_Pos 0 +#define XDMAC_GWAC_PW0_Msk (0xfu << XDMAC_GWAC_PW0_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 0 */ +#define XDMAC_GWAC_PW0(value) ((XDMAC_GWAC_PW0_Msk & ((value) << XDMAC_GWAC_PW0_Pos))) +#define XDMAC_GWAC_PW1_Pos 4 +#define XDMAC_GWAC_PW1_Msk (0xfu << XDMAC_GWAC_PW1_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 1 */ +#define XDMAC_GWAC_PW1(value) ((XDMAC_GWAC_PW1_Msk & ((value) << XDMAC_GWAC_PW1_Pos))) +#define XDMAC_GWAC_PW2_Pos 8 +#define XDMAC_GWAC_PW2_Msk (0xfu << XDMAC_GWAC_PW2_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 2 */ +#define XDMAC_GWAC_PW2(value) ((XDMAC_GWAC_PW2_Msk & ((value) << XDMAC_GWAC_PW2_Pos))) +#define XDMAC_GWAC_PW3_Pos 12 +#define XDMAC_GWAC_PW3_Msk (0xfu << XDMAC_GWAC_PW3_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 3 */ +#define XDMAC_GWAC_PW3(value) ((XDMAC_GWAC_PW3_Msk & ((value) << XDMAC_GWAC_PW3_Pos))) +/* -------- XDMAC_GIE : (XDMAC Offset: 0x0C) Global Interrupt Enable Register -------- */ +#define XDMAC_GIE_IE0 (0x1u << 0) /**< \brief (XDMAC_GIE) XDMAC Channel 0 Interrupt Enable Bit */ +#define XDMAC_GIE_IE1 (0x1u << 1) /**< \brief (XDMAC_GIE) XDMAC Channel 1 Interrupt Enable Bit */ +#define XDMAC_GIE_IE2 (0x1u << 2) /**< \brief (XDMAC_GIE) XDMAC Channel 2 Interrupt Enable Bit */ +#define XDMAC_GIE_IE3 (0x1u << 3) /**< \brief (XDMAC_GIE) XDMAC Channel 3 Interrupt Enable Bit */ +#define XDMAC_GIE_IE4 (0x1u << 4) /**< \brief (XDMAC_GIE) XDMAC Channel 4 Interrupt Enable Bit */ +#define XDMAC_GIE_IE5 (0x1u << 5) /**< \brief (XDMAC_GIE) XDMAC Channel 5 Interrupt Enable Bit */ +#define XDMAC_GIE_IE6 (0x1u << 6) /**< \brief (XDMAC_GIE) XDMAC Channel 6 Interrupt Enable Bit */ +#define XDMAC_GIE_IE7 (0x1u << 7) /**< \brief (XDMAC_GIE) XDMAC Channel 7 Interrupt Enable Bit */ +#define XDMAC_GIE_IE8 (0x1u << 8) /**< \brief (XDMAC_GIE) XDMAC Channel 8 Interrupt Enable Bit */ +#define XDMAC_GIE_IE9 (0x1u << 9) /**< \brief (XDMAC_GIE) XDMAC Channel 9 Interrupt Enable Bit */ +#define XDMAC_GIE_IE10 (0x1u << 10) /**< \brief (XDMAC_GIE) XDMAC Channel 10 Interrupt Enable Bit */ +#define XDMAC_GIE_IE11 (0x1u << 11) /**< \brief (XDMAC_GIE) XDMAC Channel 11 Interrupt Enable Bit */ +#define XDMAC_GIE_IE12 (0x1u << 12) /**< \brief (XDMAC_GIE) XDMAC Channel 12 Interrupt Enable Bit */ +#define XDMAC_GIE_IE13 (0x1u << 13) /**< \brief (XDMAC_GIE) XDMAC Channel 13 Interrupt Enable Bit */ +#define XDMAC_GIE_IE14 (0x1u << 14) /**< \brief (XDMAC_GIE) XDMAC Channel 14 Interrupt Enable Bit */ +#define XDMAC_GIE_IE15 (0x1u << 15) /**< \brief (XDMAC_GIE) XDMAC Channel 15 Interrupt Enable Bit */ +#define XDMAC_GIE_IE16 (0x1u << 16) /**< \brief (XDMAC_GIE) XDMAC Channel 16 Interrupt Enable Bit */ +#define XDMAC_GIE_IE17 (0x1u << 17) /**< \brief (XDMAC_GIE) XDMAC Channel 17 Interrupt Enable Bit */ +#define XDMAC_GIE_IE18 (0x1u << 18) /**< \brief (XDMAC_GIE) XDMAC Channel 18 Interrupt Enable Bit */ +#define XDMAC_GIE_IE19 (0x1u << 19) /**< \brief (XDMAC_GIE) XDMAC Channel 19 Interrupt Enable Bit */ +#define XDMAC_GIE_IE20 (0x1u << 20) /**< \brief (XDMAC_GIE) XDMAC Channel 20 Interrupt Enable Bit */ +#define XDMAC_GIE_IE21 (0x1u << 21) /**< \brief (XDMAC_GIE) XDMAC Channel 21 Interrupt Enable Bit */ +#define XDMAC_GIE_IE22 (0x1u << 22) /**< \brief (XDMAC_GIE) XDMAC Channel 22 Interrupt Enable Bit */ +#define XDMAC_GIE_IE23 (0x1u << 23) /**< \brief (XDMAC_GIE) XDMAC Channel 23 Interrupt Enable Bit */ +/* -------- XDMAC_GID : (XDMAC Offset: 0x10) Global Interrupt Disable Register -------- */ +#define XDMAC_GID_ID0 (0x1u << 0) /**< \brief (XDMAC_GID) XDMAC Channel 0 Interrupt Disable Bit */ +#define XDMAC_GID_ID1 (0x1u << 1) /**< \brief (XDMAC_GID) XDMAC Channel 1 Interrupt Disable Bit */ +#define XDMAC_GID_ID2 (0x1u << 2) /**< \brief (XDMAC_GID) XDMAC Channel 2 Interrupt Disable Bit */ +#define XDMAC_GID_ID3 (0x1u << 3) /**< \brief (XDMAC_GID) XDMAC Channel 3 Interrupt Disable Bit */ +#define XDMAC_GID_ID4 (0x1u << 4) /**< \brief (XDMAC_GID) XDMAC Channel 4 Interrupt Disable Bit */ +#define XDMAC_GID_ID5 (0x1u << 5) /**< \brief (XDMAC_GID) XDMAC Channel 5 Interrupt Disable Bit */ +#define XDMAC_GID_ID6 (0x1u << 6) /**< \brief (XDMAC_GID) XDMAC Channel 6 Interrupt Disable Bit */ +#define XDMAC_GID_ID7 (0x1u << 7) /**< \brief (XDMAC_GID) XDMAC Channel 7 Interrupt Disable Bit */ +#define XDMAC_GID_ID8 (0x1u << 8) /**< \brief (XDMAC_GID) XDMAC Channel 8 Interrupt Disable Bit */ +#define XDMAC_GID_ID9 (0x1u << 9) /**< \brief (XDMAC_GID) XDMAC Channel 9 Interrupt Disable Bit */ +#define XDMAC_GID_ID10 (0x1u << 10) /**< \brief (XDMAC_GID) XDMAC Channel 10 Interrupt Disable Bit */ +#define XDMAC_GID_ID11 (0x1u << 11) /**< \brief (XDMAC_GID) XDMAC Channel 11 Interrupt Disable Bit */ +#define XDMAC_GID_ID12 (0x1u << 12) /**< \brief (XDMAC_GID) XDMAC Channel 12 Interrupt Disable Bit */ +#define XDMAC_GID_ID13 (0x1u << 13) /**< \brief (XDMAC_GID) XDMAC Channel 13 Interrupt Disable Bit */ +#define XDMAC_GID_ID14 (0x1u << 14) /**< \brief (XDMAC_GID) XDMAC Channel 14 Interrupt Disable Bit */ +#define XDMAC_GID_ID15 (0x1u << 15) /**< \brief (XDMAC_GID) XDMAC Channel 15 Interrupt Disable Bit */ +#define XDMAC_GID_ID16 (0x1u << 16) /**< \brief (XDMAC_GID) XDMAC Channel 16 Interrupt Disable Bit */ +#define XDMAC_GID_ID17 (0x1u << 17) /**< \brief (XDMAC_GID) XDMAC Channel 17 Interrupt Disable Bit */ +#define XDMAC_GID_ID18 (0x1u << 18) /**< \brief (XDMAC_GID) XDMAC Channel 18 Interrupt Disable Bit */ +#define XDMAC_GID_ID19 (0x1u << 19) /**< \brief (XDMAC_GID) XDMAC Channel 19 Interrupt Disable Bit */ +#define XDMAC_GID_ID20 (0x1u << 20) /**< \brief (XDMAC_GID) XDMAC Channel 20 Interrupt Disable Bit */ +#define XDMAC_GID_ID21 (0x1u << 21) /**< \brief (XDMAC_GID) XDMAC Channel 21 Interrupt Disable Bit */ +#define XDMAC_GID_ID22 (0x1u << 22) /**< \brief (XDMAC_GID) XDMAC Channel 22 Interrupt Disable Bit */ +#define XDMAC_GID_ID23 (0x1u << 23) /**< \brief (XDMAC_GID) XDMAC Channel 23 Interrupt Disable Bit */ +/* -------- XDMAC_GIM : (XDMAC Offset: 0x14) Global Interrupt Mask Register -------- */ +#define XDMAC_GIM_IM0 (0x1u << 0) /**< \brief (XDMAC_GIM) XDMAC Channel 0 Interrupt Mask Bit */ +#define XDMAC_GIM_IM1 (0x1u << 1) /**< \brief (XDMAC_GIM) XDMAC Channel 1 Interrupt Mask Bit */ +#define XDMAC_GIM_IM2 (0x1u << 2) /**< \brief (XDMAC_GIM) XDMAC Channel 2 Interrupt Mask Bit */ +#define XDMAC_GIM_IM3 (0x1u << 3) /**< \brief (XDMAC_GIM) XDMAC Channel 3 Interrupt Mask Bit */ +#define XDMAC_GIM_IM4 (0x1u << 4) /**< \brief (XDMAC_GIM) XDMAC Channel 4 Interrupt Mask Bit */ +#define XDMAC_GIM_IM5 (0x1u << 5) /**< \brief (XDMAC_GIM) XDMAC Channel 5 Interrupt Mask Bit */ +#define XDMAC_GIM_IM6 (0x1u << 6) /**< \brief (XDMAC_GIM) XDMAC Channel 6 Interrupt Mask Bit */ +#define XDMAC_GIM_IM7 (0x1u << 7) /**< \brief (XDMAC_GIM) XDMAC Channel 7 Interrupt Mask Bit */ +#define XDMAC_GIM_IM8 (0x1u << 8) /**< \brief (XDMAC_GIM) XDMAC Channel 8 Interrupt Mask Bit */ +#define XDMAC_GIM_IM9 (0x1u << 9) /**< \brief (XDMAC_GIM) XDMAC Channel 9 Interrupt Mask Bit */ +#define XDMAC_GIM_IM10 (0x1u << 10) /**< \brief (XDMAC_GIM) XDMAC Channel 10 Interrupt Mask Bit */ +#define XDMAC_GIM_IM11 (0x1u << 11) /**< \brief (XDMAC_GIM) XDMAC Channel 11 Interrupt Mask Bit */ +#define XDMAC_GIM_IM12 (0x1u << 12) /**< \brief (XDMAC_GIM) XDMAC Channel 12 Interrupt Mask Bit */ +#define XDMAC_GIM_IM13 (0x1u << 13) /**< \brief (XDMAC_GIM) XDMAC Channel 13 Interrupt Mask Bit */ +#define XDMAC_GIM_IM14 (0x1u << 14) /**< \brief (XDMAC_GIM) XDMAC Channel 14 Interrupt Mask Bit */ +#define XDMAC_GIM_IM15 (0x1u << 15) /**< \brief (XDMAC_GIM) XDMAC Channel 15 Interrupt Mask Bit */ +#define XDMAC_GIM_IM16 (0x1u << 16) /**< \brief (XDMAC_GIM) XDMAC Channel 16 Interrupt Mask Bit */ +#define XDMAC_GIM_IM17 (0x1u << 17) /**< \brief (XDMAC_GIM) XDMAC Channel 17 Interrupt Mask Bit */ +#define XDMAC_GIM_IM18 (0x1u << 18) /**< \brief (XDMAC_GIM) XDMAC Channel 18 Interrupt Mask Bit */ +#define XDMAC_GIM_IM19 (0x1u << 19) /**< \brief (XDMAC_GIM) XDMAC Channel 19 Interrupt Mask Bit */ +#define XDMAC_GIM_IM20 (0x1u << 20) /**< \brief (XDMAC_GIM) XDMAC Channel 20 Interrupt Mask Bit */ +#define XDMAC_GIM_IM21 (0x1u << 21) /**< \brief (XDMAC_GIM) XDMAC Channel 21 Interrupt Mask Bit */ +#define XDMAC_GIM_IM22 (0x1u << 22) /**< \brief (XDMAC_GIM) XDMAC Channel 22 Interrupt Mask Bit */ +#define XDMAC_GIM_IM23 (0x1u << 23) /**< \brief (XDMAC_GIM) XDMAC Channel 23 Interrupt Mask Bit */ +/* -------- XDMAC_GIS : (XDMAC Offset: 0x18) Global Interrupt Status Register -------- */ +#define XDMAC_GIS_IS0 (0x1u << 0) /**< \brief (XDMAC_GIS) XDMAC Channel 0 Interrupt Status Bit */ +#define XDMAC_GIS_IS1 (0x1u << 1) /**< \brief (XDMAC_GIS) XDMAC Channel 1 Interrupt Status Bit */ +#define XDMAC_GIS_IS2 (0x1u << 2) /**< \brief (XDMAC_GIS) XDMAC Channel 2 Interrupt Status Bit */ +#define XDMAC_GIS_IS3 (0x1u << 3) /**< \brief (XDMAC_GIS) XDMAC Channel 3 Interrupt Status Bit */ +#define XDMAC_GIS_IS4 (0x1u << 4) /**< \brief (XDMAC_GIS) XDMAC Channel 4 Interrupt Status Bit */ +#define XDMAC_GIS_IS5 (0x1u << 5) /**< \brief (XDMAC_GIS) XDMAC Channel 5 Interrupt Status Bit */ +#define XDMAC_GIS_IS6 (0x1u << 6) /**< \brief (XDMAC_GIS) XDMAC Channel 6 Interrupt Status Bit */ +#define XDMAC_GIS_IS7 (0x1u << 7) /**< \brief (XDMAC_GIS) XDMAC Channel 7 Interrupt Status Bit */ +#define XDMAC_GIS_IS8 (0x1u << 8) /**< \brief (XDMAC_GIS) XDMAC Channel 8 Interrupt Status Bit */ +#define XDMAC_GIS_IS9 (0x1u << 9) /**< \brief (XDMAC_GIS) XDMAC Channel 9 Interrupt Status Bit */ +#define XDMAC_GIS_IS10 (0x1u << 10) /**< \brief (XDMAC_GIS) XDMAC Channel 10 Interrupt Status Bit */ +#define XDMAC_GIS_IS11 (0x1u << 11) /**< \brief (XDMAC_GIS) XDMAC Channel 11 Interrupt Status Bit */ +#define XDMAC_GIS_IS12 (0x1u << 12) /**< \brief (XDMAC_GIS) XDMAC Channel 12 Interrupt Status Bit */ +#define XDMAC_GIS_IS13 (0x1u << 13) /**< \brief (XDMAC_GIS) XDMAC Channel 13 Interrupt Status Bit */ +#define XDMAC_GIS_IS14 (0x1u << 14) /**< \brief (XDMAC_GIS) XDMAC Channel 14 Interrupt Status Bit */ +#define XDMAC_GIS_IS15 (0x1u << 15) /**< \brief (XDMAC_GIS) XDMAC Channel 15 Interrupt Status Bit */ +#define XDMAC_GIS_IS16 (0x1u << 16) /**< \brief (XDMAC_GIS) XDMAC Channel 16 Interrupt Status Bit */ +#define XDMAC_GIS_IS17 (0x1u << 17) /**< \brief (XDMAC_GIS) XDMAC Channel 17 Interrupt Status Bit */ +#define XDMAC_GIS_IS18 (0x1u << 18) /**< \brief (XDMAC_GIS) XDMAC Channel 18 Interrupt Status Bit */ +#define XDMAC_GIS_IS19 (0x1u << 19) /**< \brief (XDMAC_GIS) XDMAC Channel 19 Interrupt Status Bit */ +#define XDMAC_GIS_IS20 (0x1u << 20) /**< \brief (XDMAC_GIS) XDMAC Channel 20 Interrupt Status Bit */ +#define XDMAC_GIS_IS21 (0x1u << 21) /**< \brief (XDMAC_GIS) XDMAC Channel 21 Interrupt Status Bit */ +#define XDMAC_GIS_IS22 (0x1u << 22) /**< \brief (XDMAC_GIS) XDMAC Channel 22 Interrupt Status Bit */ +#define XDMAC_GIS_IS23 (0x1u << 23) /**< \brief (XDMAC_GIS) XDMAC Channel 23 Interrupt Status Bit */ +/* -------- XDMAC_GE : (XDMAC Offset: 0x1C) Global Channel Enable Register -------- */ +#define XDMAC_GE_EN0 (0x1u << 0) /**< \brief (XDMAC_GE) XDMAC Channel 0 Enable Bit */ +#define XDMAC_GE_EN1 (0x1u << 1) /**< \brief (XDMAC_GE) XDMAC Channel 1 Enable Bit */ +#define XDMAC_GE_EN2 (0x1u << 2) /**< \brief (XDMAC_GE) XDMAC Channel 2 Enable Bit */ +#define XDMAC_GE_EN3 (0x1u << 3) /**< \brief (XDMAC_GE) XDMAC Channel 3 Enable Bit */ +#define XDMAC_GE_EN4 (0x1u << 4) /**< \brief (XDMAC_GE) XDMAC Channel 4 Enable Bit */ +#define XDMAC_GE_EN5 (0x1u << 5) /**< \brief (XDMAC_GE) XDMAC Channel 5 Enable Bit */ +#define XDMAC_GE_EN6 (0x1u << 6) /**< \brief (XDMAC_GE) XDMAC Channel 6 Enable Bit */ +#define XDMAC_GE_EN7 (0x1u << 7) /**< \brief (XDMAC_GE) XDMAC Channel 7 Enable Bit */ +#define XDMAC_GE_EN8 (0x1u << 8) /**< \brief (XDMAC_GE) XDMAC Channel 8 Enable Bit */ +#define XDMAC_GE_EN9 (0x1u << 9) /**< \brief (XDMAC_GE) XDMAC Channel 9 Enable Bit */ +#define XDMAC_GE_EN10 (0x1u << 10) /**< \brief (XDMAC_GE) XDMAC Channel 10 Enable Bit */ +#define XDMAC_GE_EN11 (0x1u << 11) /**< \brief (XDMAC_GE) XDMAC Channel 11 Enable Bit */ +#define XDMAC_GE_EN12 (0x1u << 12) /**< \brief (XDMAC_GE) XDMAC Channel 12 Enable Bit */ +#define XDMAC_GE_EN13 (0x1u << 13) /**< \brief (XDMAC_GE) XDMAC Channel 13 Enable Bit */ +#define XDMAC_GE_EN14 (0x1u << 14) /**< \brief (XDMAC_GE) XDMAC Channel 14 Enable Bit */ +#define XDMAC_GE_EN15 (0x1u << 15) /**< \brief (XDMAC_GE) XDMAC Channel 15 Enable Bit */ +#define XDMAC_GE_EN16 (0x1u << 16) /**< \brief (XDMAC_GE) XDMAC Channel 16 Enable Bit */ +#define XDMAC_GE_EN17 (0x1u << 17) /**< \brief (XDMAC_GE) XDMAC Channel 17 Enable Bit */ +#define XDMAC_GE_EN18 (0x1u << 18) /**< \brief (XDMAC_GE) XDMAC Channel 18 Enable Bit */ +#define XDMAC_GE_EN19 (0x1u << 19) /**< \brief (XDMAC_GE) XDMAC Channel 19 Enable Bit */ +#define XDMAC_GE_EN20 (0x1u << 20) /**< \brief (XDMAC_GE) XDMAC Channel 20 Enable Bit */ +#define XDMAC_GE_EN21 (0x1u << 21) /**< \brief (XDMAC_GE) XDMAC Channel 21 Enable Bit */ +#define XDMAC_GE_EN22 (0x1u << 22) /**< \brief (XDMAC_GE) XDMAC Channel 22 Enable Bit */ +#define XDMAC_GE_EN23 (0x1u << 23) /**< \brief (XDMAC_GE) XDMAC Channel 23 Enable Bit */ +/* -------- XDMAC_GD : (XDMAC Offset: 0x20) Global Channel Disable Register -------- */ +#define XDMAC_GD_DI0 (0x1u << 0) /**< \brief (XDMAC_GD) XDMAC Channel 0 Disable Bit */ +#define XDMAC_GD_DI1 (0x1u << 1) /**< \brief (XDMAC_GD) XDMAC Channel 1 Disable Bit */ +#define XDMAC_GD_DI2 (0x1u << 2) /**< \brief (XDMAC_GD) XDMAC Channel 2 Disable Bit */ +#define XDMAC_GD_DI3 (0x1u << 3) /**< \brief (XDMAC_GD) XDMAC Channel 3 Disable Bit */ +#define XDMAC_GD_DI4 (0x1u << 4) /**< \brief (XDMAC_GD) XDMAC Channel 4 Disable Bit */ +#define XDMAC_GD_DI5 (0x1u << 5) /**< \brief (XDMAC_GD) XDMAC Channel 5 Disable Bit */ +#define XDMAC_GD_DI6 (0x1u << 6) /**< \brief (XDMAC_GD) XDMAC Channel 6 Disable Bit */ +#define XDMAC_GD_DI7 (0x1u << 7) /**< \brief (XDMAC_GD) XDMAC Channel 7 Disable Bit */ +#define XDMAC_GD_DI8 (0x1u << 8) /**< \brief (XDMAC_GD) XDMAC Channel 8 Disable Bit */ +#define XDMAC_GD_DI9 (0x1u << 9) /**< \brief (XDMAC_GD) XDMAC Channel 9 Disable Bit */ +#define XDMAC_GD_DI10 (0x1u << 10) /**< \brief (XDMAC_GD) XDMAC Channel 10 Disable Bit */ +#define XDMAC_GD_DI11 (0x1u << 11) /**< \brief (XDMAC_GD) XDMAC Channel 11 Disable Bit */ +#define XDMAC_GD_DI12 (0x1u << 12) /**< \brief (XDMAC_GD) XDMAC Channel 12 Disable Bit */ +#define XDMAC_GD_DI13 (0x1u << 13) /**< \brief (XDMAC_GD) XDMAC Channel 13 Disable Bit */ +#define XDMAC_GD_DI14 (0x1u << 14) /**< \brief (XDMAC_GD) XDMAC Channel 14 Disable Bit */ +#define XDMAC_GD_DI15 (0x1u << 15) /**< \brief (XDMAC_GD) XDMAC Channel 15 Disable Bit */ +#define XDMAC_GD_DI16 (0x1u << 16) /**< \brief (XDMAC_GD) XDMAC Channel 16 Disable Bit */ +#define XDMAC_GD_DI17 (0x1u << 17) /**< \brief (XDMAC_GD) XDMAC Channel 17 Disable Bit */ +#define XDMAC_GD_DI18 (0x1u << 18) /**< \brief (XDMAC_GD) XDMAC Channel 18 Disable Bit */ +#define XDMAC_GD_DI19 (0x1u << 19) /**< \brief (XDMAC_GD) XDMAC Channel 19 Disable Bit */ +#define XDMAC_GD_DI20 (0x1u << 20) /**< \brief (XDMAC_GD) XDMAC Channel 20 Disable Bit */ +#define XDMAC_GD_DI21 (0x1u << 21) /**< \brief (XDMAC_GD) XDMAC Channel 21 Disable Bit */ +#define XDMAC_GD_DI22 (0x1u << 22) /**< \brief (XDMAC_GD) XDMAC Channel 22 Disable Bit */ +#define XDMAC_GD_DI23 (0x1u << 23) /**< \brief (XDMAC_GD) XDMAC Channel 23 Disable Bit */ +/* -------- XDMAC_GS : (XDMAC Offset: 0x24) Global Channel Status Register -------- */ +#define XDMAC_GS_ST0 (0x1u << 0) /**< \brief (XDMAC_GS) XDMAC Channel 0 Status Bit */ +#define XDMAC_GS_ST1 (0x1u << 1) /**< \brief (XDMAC_GS) XDMAC Channel 1 Status Bit */ +#define XDMAC_GS_ST2 (0x1u << 2) /**< \brief (XDMAC_GS) XDMAC Channel 2 Status Bit */ +#define XDMAC_GS_ST3 (0x1u << 3) /**< \brief (XDMAC_GS) XDMAC Channel 3 Status Bit */ +#define XDMAC_GS_ST4 (0x1u << 4) /**< \brief (XDMAC_GS) XDMAC Channel 4 Status Bit */ +#define XDMAC_GS_ST5 (0x1u << 5) /**< \brief (XDMAC_GS) XDMAC Channel 5 Status Bit */ +#define XDMAC_GS_ST6 (0x1u << 6) /**< \brief (XDMAC_GS) XDMAC Channel 6 Status Bit */ +#define XDMAC_GS_ST7 (0x1u << 7) /**< \brief (XDMAC_GS) XDMAC Channel 7 Status Bit */ +#define XDMAC_GS_ST8 (0x1u << 8) /**< \brief (XDMAC_GS) XDMAC Channel 8 Status Bit */ +#define XDMAC_GS_ST9 (0x1u << 9) /**< \brief (XDMAC_GS) XDMAC Channel 9 Status Bit */ +#define XDMAC_GS_ST10 (0x1u << 10) /**< \brief (XDMAC_GS) XDMAC Channel 10 Status Bit */ +#define XDMAC_GS_ST11 (0x1u << 11) /**< \brief (XDMAC_GS) XDMAC Channel 11 Status Bit */ +#define XDMAC_GS_ST12 (0x1u << 12) /**< \brief (XDMAC_GS) XDMAC Channel 12 Status Bit */ +#define XDMAC_GS_ST13 (0x1u << 13) /**< \brief (XDMAC_GS) XDMAC Channel 13 Status Bit */ +#define XDMAC_GS_ST14 (0x1u << 14) /**< \brief (XDMAC_GS) XDMAC Channel 14 Status Bit */ +#define XDMAC_GS_ST15 (0x1u << 15) /**< \brief (XDMAC_GS) XDMAC Channel 15 Status Bit */ +#define XDMAC_GS_ST16 (0x1u << 16) /**< \brief (XDMAC_GS) XDMAC Channel 16 Status Bit */ +#define XDMAC_GS_ST17 (0x1u << 17) /**< \brief (XDMAC_GS) XDMAC Channel 17 Status Bit */ +#define XDMAC_GS_ST18 (0x1u << 18) /**< \brief (XDMAC_GS) XDMAC Channel 18 Status Bit */ +#define XDMAC_GS_ST19 (0x1u << 19) /**< \brief (XDMAC_GS) XDMAC Channel 19 Status Bit */ +#define XDMAC_GS_ST20 (0x1u << 20) /**< \brief (XDMAC_GS) XDMAC Channel 20 Status Bit */ +#define XDMAC_GS_ST21 (0x1u << 21) /**< \brief (XDMAC_GS) XDMAC Channel 21 Status Bit */ +#define XDMAC_GS_ST22 (0x1u << 22) /**< \brief (XDMAC_GS) XDMAC Channel 22 Status Bit */ +#define XDMAC_GS_ST23 (0x1u << 23) /**< \brief (XDMAC_GS) XDMAC Channel 23 Status Bit */ +/* -------- XDMAC_GRS : (XDMAC Offset: 0x28) Global Channel Read Suspend Register -------- */ +#define XDMAC_GRS_RS0 (0x1u << 0) /**< \brief (XDMAC_GRS) XDMAC Channel 0 Read Suspend Bit */ +#define XDMAC_GRS_RS1 (0x1u << 1) /**< \brief (XDMAC_GRS) XDMAC Channel 1 Read Suspend Bit */ +#define XDMAC_GRS_RS2 (0x1u << 2) /**< \brief (XDMAC_GRS) XDMAC Channel 2 Read Suspend Bit */ +#define XDMAC_GRS_RS3 (0x1u << 3) /**< \brief (XDMAC_GRS) XDMAC Channel 3 Read Suspend Bit */ +#define XDMAC_GRS_RS4 (0x1u << 4) /**< \brief (XDMAC_GRS) XDMAC Channel 4 Read Suspend Bit */ +#define XDMAC_GRS_RS5 (0x1u << 5) /**< \brief (XDMAC_GRS) XDMAC Channel 5 Read Suspend Bit */ +#define XDMAC_GRS_RS6 (0x1u << 6) /**< \brief (XDMAC_GRS) XDMAC Channel 6 Read Suspend Bit */ +#define XDMAC_GRS_RS7 (0x1u << 7) /**< \brief (XDMAC_GRS) XDMAC Channel 7 Read Suspend Bit */ +#define XDMAC_GRS_RS8 (0x1u << 8) /**< \brief (XDMAC_GRS) XDMAC Channel 8 Read Suspend Bit */ +#define XDMAC_GRS_RS9 (0x1u << 9) /**< \brief (XDMAC_GRS) XDMAC Channel 9 Read Suspend Bit */ +#define XDMAC_GRS_RS10 (0x1u << 10) /**< \brief (XDMAC_GRS) XDMAC Channel 10 Read Suspend Bit */ +#define XDMAC_GRS_RS11 (0x1u << 11) /**< \brief (XDMAC_GRS) XDMAC Channel 11 Read Suspend Bit */ +#define XDMAC_GRS_RS12 (0x1u << 12) /**< \brief (XDMAC_GRS) XDMAC Channel 12 Read Suspend Bit */ +#define XDMAC_GRS_RS13 (0x1u << 13) /**< \brief (XDMAC_GRS) XDMAC Channel 13 Read Suspend Bit */ +#define XDMAC_GRS_RS14 (0x1u << 14) /**< \brief (XDMAC_GRS) XDMAC Channel 14 Read Suspend Bit */ +#define XDMAC_GRS_RS15 (0x1u << 15) /**< \brief (XDMAC_GRS) XDMAC Channel 15 Read Suspend Bit */ +#define XDMAC_GRS_RS16 (0x1u << 16) /**< \brief (XDMAC_GRS) XDMAC Channel 16 Read Suspend Bit */ +#define XDMAC_GRS_RS17 (0x1u << 17) /**< \brief (XDMAC_GRS) XDMAC Channel 17 Read Suspend Bit */ +#define XDMAC_GRS_RS18 (0x1u << 18) /**< \brief (XDMAC_GRS) XDMAC Channel 18 Read Suspend Bit */ +#define XDMAC_GRS_RS19 (0x1u << 19) /**< \brief (XDMAC_GRS) XDMAC Channel 19 Read Suspend Bit */ +#define XDMAC_GRS_RS20 (0x1u << 20) /**< \brief (XDMAC_GRS) XDMAC Channel 20 Read Suspend Bit */ +#define XDMAC_GRS_RS21 (0x1u << 21) /**< \brief (XDMAC_GRS) XDMAC Channel 21 Read Suspend Bit */ +#define XDMAC_GRS_RS22 (0x1u << 22) /**< \brief (XDMAC_GRS) XDMAC Channel 22 Read Suspend Bit */ +#define XDMAC_GRS_RS23 (0x1u << 23) /**< \brief (XDMAC_GRS) XDMAC Channel 23 Read Suspend Bit */ +/* -------- XDMAC_GWS : (XDMAC Offset: 0x2C) Global Channel Write Suspend Register -------- */ +#define XDMAC_GWS_WS0 (0x1u << 0) /**< \brief (XDMAC_GWS) XDMAC Channel 0 Write Suspend Bit */ +#define XDMAC_GWS_WS1 (0x1u << 1) /**< \brief (XDMAC_GWS) XDMAC Channel 1 Write Suspend Bit */ +#define XDMAC_GWS_WS2 (0x1u << 2) /**< \brief (XDMAC_GWS) XDMAC Channel 2 Write Suspend Bit */ +#define XDMAC_GWS_WS3 (0x1u << 3) /**< \brief (XDMAC_GWS) XDMAC Channel 3 Write Suspend Bit */ +#define XDMAC_GWS_WS4 (0x1u << 4) /**< \brief (XDMAC_GWS) XDMAC Channel 4 Write Suspend Bit */ +#define XDMAC_GWS_WS5 (0x1u << 5) /**< \brief (XDMAC_GWS) XDMAC Channel 5 Write Suspend Bit */ +#define XDMAC_GWS_WS6 (0x1u << 6) /**< \brief (XDMAC_GWS) XDMAC Channel 6 Write Suspend Bit */ +#define XDMAC_GWS_WS7 (0x1u << 7) /**< \brief (XDMAC_GWS) XDMAC Channel 7 Write Suspend Bit */ +#define XDMAC_GWS_WS8 (0x1u << 8) /**< \brief (XDMAC_GWS) XDMAC Channel 8 Write Suspend Bit */ +#define XDMAC_GWS_WS9 (0x1u << 9) /**< \brief (XDMAC_GWS) XDMAC Channel 9 Write Suspend Bit */ +#define XDMAC_GWS_WS10 (0x1u << 10) /**< \brief (XDMAC_GWS) XDMAC Channel 10 Write Suspend Bit */ +#define XDMAC_GWS_WS11 (0x1u << 11) /**< \brief (XDMAC_GWS) XDMAC Channel 11 Write Suspend Bit */ +#define XDMAC_GWS_WS12 (0x1u << 12) /**< \brief (XDMAC_GWS) XDMAC Channel 12 Write Suspend Bit */ +#define XDMAC_GWS_WS13 (0x1u << 13) /**< \brief (XDMAC_GWS) XDMAC Channel 13 Write Suspend Bit */ +#define XDMAC_GWS_WS14 (0x1u << 14) /**< \brief (XDMAC_GWS) XDMAC Channel 14 Write Suspend Bit */ +#define XDMAC_GWS_WS15 (0x1u << 15) /**< \brief (XDMAC_GWS) XDMAC Channel 15 Write Suspend Bit */ +#define XDMAC_GWS_WS16 (0x1u << 16) /**< \brief (XDMAC_GWS) XDMAC Channel 16 Write Suspend Bit */ +#define XDMAC_GWS_WS17 (0x1u << 17) /**< \brief (XDMAC_GWS) XDMAC Channel 17 Write Suspend Bit */ +#define XDMAC_GWS_WS18 (0x1u << 18) /**< \brief (XDMAC_GWS) XDMAC Channel 18 Write Suspend Bit */ +#define XDMAC_GWS_WS19 (0x1u << 19) /**< \brief (XDMAC_GWS) XDMAC Channel 19 Write Suspend Bit */ +#define XDMAC_GWS_WS20 (0x1u << 20) /**< \brief (XDMAC_GWS) XDMAC Channel 20 Write Suspend Bit */ +#define XDMAC_GWS_WS21 (0x1u << 21) /**< \brief (XDMAC_GWS) XDMAC Channel 21 Write Suspend Bit */ +#define XDMAC_GWS_WS22 (0x1u << 22) /**< \brief (XDMAC_GWS) XDMAC Channel 22 Write Suspend Bit */ +#define XDMAC_GWS_WS23 (0x1u << 23) /**< \brief (XDMAC_GWS) XDMAC Channel 23 Write Suspend Bit */ +/* -------- XDMAC_GRWS : (XDMAC Offset: 0x30) Global Channel Read Write Suspend Register -------- */ +#define XDMAC_GRWS_RWS0 (0x1u << 0) /**< \brief (XDMAC_GRWS) XDMAC Channel 0 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS1 (0x1u << 1) /**< \brief (XDMAC_GRWS) XDMAC Channel 1 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS2 (0x1u << 2) /**< \brief (XDMAC_GRWS) XDMAC Channel 2 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS3 (0x1u << 3) /**< \brief (XDMAC_GRWS) XDMAC Channel 3 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS4 (0x1u << 4) /**< \brief (XDMAC_GRWS) XDMAC Channel 4 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS5 (0x1u << 5) /**< \brief (XDMAC_GRWS) XDMAC Channel 5 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS6 (0x1u << 6) /**< \brief (XDMAC_GRWS) XDMAC Channel 6 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS7 (0x1u << 7) /**< \brief (XDMAC_GRWS) XDMAC Channel 7 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS8 (0x1u << 8) /**< \brief (XDMAC_GRWS) XDMAC Channel 8 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS9 (0x1u << 9) /**< \brief (XDMAC_GRWS) XDMAC Channel 9 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS10 (0x1u << 10) /**< \brief (XDMAC_GRWS) XDMAC Channel 10 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS11 (0x1u << 11) /**< \brief (XDMAC_GRWS) XDMAC Channel 11 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS12 (0x1u << 12) /**< \brief (XDMAC_GRWS) XDMAC Channel 12 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS13 (0x1u << 13) /**< \brief (XDMAC_GRWS) XDMAC Channel 13 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS14 (0x1u << 14) /**< \brief (XDMAC_GRWS) XDMAC Channel 14 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS15 (0x1u << 15) /**< \brief (XDMAC_GRWS) XDMAC Channel 15 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS16 (0x1u << 16) /**< \brief (XDMAC_GRWS) XDMAC Channel 16 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS17 (0x1u << 17) /**< \brief (XDMAC_GRWS) XDMAC Channel 17 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS18 (0x1u << 18) /**< \brief (XDMAC_GRWS) XDMAC Channel 18 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS19 (0x1u << 19) /**< \brief (XDMAC_GRWS) XDMAC Channel 19 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS20 (0x1u << 20) /**< \brief (XDMAC_GRWS) XDMAC Channel 20 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS21 (0x1u << 21) /**< \brief (XDMAC_GRWS) XDMAC Channel 21 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS22 (0x1u << 22) /**< \brief (XDMAC_GRWS) XDMAC Channel 22 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS23 (0x1u << 23) /**< \brief (XDMAC_GRWS) XDMAC Channel 23 Read Write Suspend Bit */ +/* -------- XDMAC_GRWR : (XDMAC Offset: 0x34) Global Channel Read Write Resume Register -------- */ +#define XDMAC_GRWR_RWR0 (0x1u << 0) /**< \brief (XDMAC_GRWR) XDMAC Channel 0 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR1 (0x1u << 1) /**< \brief (XDMAC_GRWR) XDMAC Channel 1 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR2 (0x1u << 2) /**< \brief (XDMAC_GRWR) XDMAC Channel 2 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR3 (0x1u << 3) /**< \brief (XDMAC_GRWR) XDMAC Channel 3 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR4 (0x1u << 4) /**< \brief (XDMAC_GRWR) XDMAC Channel 4 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR5 (0x1u << 5) /**< \brief (XDMAC_GRWR) XDMAC Channel 5 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR6 (0x1u << 6) /**< \brief (XDMAC_GRWR) XDMAC Channel 6 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR7 (0x1u << 7) /**< \brief (XDMAC_GRWR) XDMAC Channel 7 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR8 (0x1u << 8) /**< \brief (XDMAC_GRWR) XDMAC Channel 8 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR9 (0x1u << 9) /**< \brief (XDMAC_GRWR) XDMAC Channel 9 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR10 (0x1u << 10) /**< \brief (XDMAC_GRWR) XDMAC Channel 10 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR11 (0x1u << 11) /**< \brief (XDMAC_GRWR) XDMAC Channel 11 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR12 (0x1u << 12) /**< \brief (XDMAC_GRWR) XDMAC Channel 12 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR13 (0x1u << 13) /**< \brief (XDMAC_GRWR) XDMAC Channel 13 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR14 (0x1u << 14) /**< \brief (XDMAC_GRWR) XDMAC Channel 14 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR15 (0x1u << 15) /**< \brief (XDMAC_GRWR) XDMAC Channel 15 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR16 (0x1u << 16) /**< \brief (XDMAC_GRWR) XDMAC Channel 16 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR17 (0x1u << 17) /**< \brief (XDMAC_GRWR) XDMAC Channel 17 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR18 (0x1u << 18) /**< \brief (XDMAC_GRWR) XDMAC Channel 18 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR19 (0x1u << 19) /**< \brief (XDMAC_GRWR) XDMAC Channel 19 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR20 (0x1u << 20) /**< \brief (XDMAC_GRWR) XDMAC Channel 20 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR21 (0x1u << 21) /**< \brief (XDMAC_GRWR) XDMAC Channel 21 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR22 (0x1u << 22) /**< \brief (XDMAC_GRWR) XDMAC Channel 22 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR23 (0x1u << 23) /**< \brief (XDMAC_GRWR) XDMAC Channel 23 Read Write Resume Bit */ +/* -------- XDMAC_GSWR : (XDMAC Offset: 0x38) Global Channel Software Request Register -------- */ +#define XDMAC_GSWR_SWREQ0 (0x1u << 0) /**< \brief (XDMAC_GSWR) XDMAC Channel 0 Software Request Bit */ +#define XDMAC_GSWR_SWREQ1 (0x1u << 1) /**< \brief (XDMAC_GSWR) XDMAC Channel 1 Software Request Bit */ +#define XDMAC_GSWR_SWREQ2 (0x1u << 2) /**< \brief (XDMAC_GSWR) XDMAC Channel 2 Software Request Bit */ +#define XDMAC_GSWR_SWREQ3 (0x1u << 3) /**< \brief (XDMAC_GSWR) XDMAC Channel 3 Software Request Bit */ +#define XDMAC_GSWR_SWREQ4 (0x1u << 4) /**< \brief (XDMAC_GSWR) XDMAC Channel 4 Software Request Bit */ +#define XDMAC_GSWR_SWREQ5 (0x1u << 5) /**< \brief (XDMAC_GSWR) XDMAC Channel 5 Software Request Bit */ +#define XDMAC_GSWR_SWREQ6 (0x1u << 6) /**< \brief (XDMAC_GSWR) XDMAC Channel 6 Software Request Bit */ +#define XDMAC_GSWR_SWREQ7 (0x1u << 7) /**< \brief (XDMAC_GSWR) XDMAC Channel 7 Software Request Bit */ +#define XDMAC_GSWR_SWREQ8 (0x1u << 8) /**< \brief (XDMAC_GSWR) XDMAC Channel 8 Software Request Bit */ +#define XDMAC_GSWR_SWREQ9 (0x1u << 9) /**< \brief (XDMAC_GSWR) XDMAC Channel 9 Software Request Bit */ +#define XDMAC_GSWR_SWREQ10 (0x1u << 10) /**< \brief (XDMAC_GSWR) XDMAC Channel 10 Software Request Bit */ +#define XDMAC_GSWR_SWREQ11 (0x1u << 11) /**< \brief (XDMAC_GSWR) XDMAC Channel 11 Software Request Bit */ +#define XDMAC_GSWR_SWREQ12 (0x1u << 12) /**< \brief (XDMAC_GSWR) XDMAC Channel 12 Software Request Bit */ +#define XDMAC_GSWR_SWREQ13 (0x1u << 13) /**< \brief (XDMAC_GSWR) XDMAC Channel 13 Software Request Bit */ +#define XDMAC_GSWR_SWREQ14 (0x1u << 14) /**< \brief (XDMAC_GSWR) XDMAC Channel 14 Software Request Bit */ +#define XDMAC_GSWR_SWREQ15 (0x1u << 15) /**< \brief (XDMAC_GSWR) XDMAC Channel 15 Software Request Bit */ +#define XDMAC_GSWR_SWREQ16 (0x1u << 16) /**< \brief (XDMAC_GSWR) XDMAC Channel 16 Software Request Bit */ +#define XDMAC_GSWR_SWREQ17 (0x1u << 17) /**< \brief (XDMAC_GSWR) XDMAC Channel 17 Software Request Bit */ +#define XDMAC_GSWR_SWREQ18 (0x1u << 18) /**< \brief (XDMAC_GSWR) XDMAC Channel 18 Software Request Bit */ +#define XDMAC_GSWR_SWREQ19 (0x1u << 19) /**< \brief (XDMAC_GSWR) XDMAC Channel 19 Software Request Bit */ +#define XDMAC_GSWR_SWREQ20 (0x1u << 20) /**< \brief (XDMAC_GSWR) XDMAC Channel 20 Software Request Bit */ +#define XDMAC_GSWR_SWREQ21 (0x1u << 21) /**< \brief (XDMAC_GSWR) XDMAC Channel 21 Software Request Bit */ +#define XDMAC_GSWR_SWREQ22 (0x1u << 22) /**< \brief (XDMAC_GSWR) XDMAC Channel 22 Software Request Bit */ +#define XDMAC_GSWR_SWREQ23 (0x1u << 23) /**< \brief (XDMAC_GSWR) XDMAC Channel 23 Software Request Bit */ +/* -------- XDMAC_GSWS : (XDMAC Offset: 0x3C) Global Channel Software Request Status Register -------- */ +#define XDMAC_GSWS_SWRS0 (0x1u << 0) /**< \brief (XDMAC_GSWS) XDMAC Channel 0 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS1 (0x1u << 1) /**< \brief (XDMAC_GSWS) XDMAC Channel 1 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS2 (0x1u << 2) /**< \brief (XDMAC_GSWS) XDMAC Channel 2 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS3 (0x1u << 3) /**< \brief (XDMAC_GSWS) XDMAC Channel 3 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS4 (0x1u << 4) /**< \brief (XDMAC_GSWS) XDMAC Channel 4 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS5 (0x1u << 5) /**< \brief (XDMAC_GSWS) XDMAC Channel 5 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS6 (0x1u << 6) /**< \brief (XDMAC_GSWS) XDMAC Channel 6 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS7 (0x1u << 7) /**< \brief (XDMAC_GSWS) XDMAC Channel 7 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS8 (0x1u << 8) /**< \brief (XDMAC_GSWS) XDMAC Channel 8 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS9 (0x1u << 9) /**< \brief (XDMAC_GSWS) XDMAC Channel 9 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS10 (0x1u << 10) /**< \brief (XDMAC_GSWS) XDMAC Channel 10 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS11 (0x1u << 11) /**< \brief (XDMAC_GSWS) XDMAC Channel 11 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS12 (0x1u << 12) /**< \brief (XDMAC_GSWS) XDMAC Channel 12 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS13 (0x1u << 13) /**< \brief (XDMAC_GSWS) XDMAC Channel 13 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS14 (0x1u << 14) /**< \brief (XDMAC_GSWS) XDMAC Channel 14 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS15 (0x1u << 15) /**< \brief (XDMAC_GSWS) XDMAC Channel 15 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS16 (0x1u << 16) /**< \brief (XDMAC_GSWS) XDMAC Channel 16 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS17 (0x1u << 17) /**< \brief (XDMAC_GSWS) XDMAC Channel 17 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS18 (0x1u << 18) /**< \brief (XDMAC_GSWS) XDMAC Channel 18 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS19 (0x1u << 19) /**< \brief (XDMAC_GSWS) XDMAC Channel 19 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS20 (0x1u << 20) /**< \brief (XDMAC_GSWS) XDMAC Channel 20 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS21 (0x1u << 21) /**< \brief (XDMAC_GSWS) XDMAC Channel 21 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS22 (0x1u << 22) /**< \brief (XDMAC_GSWS) XDMAC Channel 22 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS23 (0x1u << 23) /**< \brief (XDMAC_GSWS) XDMAC Channel 23 Software Request Status Bit */ +/* -------- XDMAC_GSWF : (XDMAC Offset: 0x40) Global Channel Software Flush Request Register -------- */ +#define XDMAC_GSWF_SWF0 (0x1u << 0) /**< \brief (XDMAC_GSWF) XDMAC Channel 0 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF1 (0x1u << 1) /**< \brief (XDMAC_GSWF) XDMAC Channel 1 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF2 (0x1u << 2) /**< \brief (XDMAC_GSWF) XDMAC Channel 2 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF3 (0x1u << 3) /**< \brief (XDMAC_GSWF) XDMAC Channel 3 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF4 (0x1u << 4) /**< \brief (XDMAC_GSWF) XDMAC Channel 4 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF5 (0x1u << 5) /**< \brief (XDMAC_GSWF) XDMAC Channel 5 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF6 (0x1u << 6) /**< \brief (XDMAC_GSWF) XDMAC Channel 6 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF7 (0x1u << 7) /**< \brief (XDMAC_GSWF) XDMAC Channel 7 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF8 (0x1u << 8) /**< \brief (XDMAC_GSWF) XDMAC Channel 8 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF9 (0x1u << 9) /**< \brief (XDMAC_GSWF) XDMAC Channel 9 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF10 (0x1u << 10) /**< \brief (XDMAC_GSWF) XDMAC Channel 10 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF11 (0x1u << 11) /**< \brief (XDMAC_GSWF) XDMAC Channel 11 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF12 (0x1u << 12) /**< \brief (XDMAC_GSWF) XDMAC Channel 12 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF13 (0x1u << 13) /**< \brief (XDMAC_GSWF) XDMAC Channel 13 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF14 (0x1u << 14) /**< \brief (XDMAC_GSWF) XDMAC Channel 14 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF15 (0x1u << 15) /**< \brief (XDMAC_GSWF) XDMAC Channel 15 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF16 (0x1u << 16) /**< \brief (XDMAC_GSWF) XDMAC Channel 16 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF17 (0x1u << 17) /**< \brief (XDMAC_GSWF) XDMAC Channel 17 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF18 (0x1u << 18) /**< \brief (XDMAC_GSWF) XDMAC Channel 18 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF19 (0x1u << 19) /**< \brief (XDMAC_GSWF) XDMAC Channel 19 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF20 (0x1u << 20) /**< \brief (XDMAC_GSWF) XDMAC Channel 20 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF21 (0x1u << 21) /**< \brief (XDMAC_GSWF) XDMAC Channel 21 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF22 (0x1u << 22) /**< \brief (XDMAC_GSWF) XDMAC Channel 22 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF23 (0x1u << 23) /**< \brief (XDMAC_GSWF) XDMAC Channel 23 Software Flush Request Bit */ +/* -------- XDMAC_CIE : (XDMAC Offset: N/A) Channel Interrupt Enable Register -------- */ +#define XDMAC_CIE_BIE (0x1u << 0) /**< \brief (XDMAC_CIE) End of Block Interrupt Enable Bit */ +#define XDMAC_CIE_LIE (0x1u << 1) /**< \brief (XDMAC_CIE) End of Linked List Interrupt Enable Bit */ +#define XDMAC_CIE_DIE (0x1u << 2) /**< \brief (XDMAC_CIE) End of Disable Interrupt Enable Bit */ +#define XDMAC_CIE_FIE (0x1u << 3) /**< \brief (XDMAC_CIE) End of Flush Interrupt Enable Bit */ +#define XDMAC_CIE_RBIE (0x1u << 4) /**< \brief (XDMAC_CIE) Read Bus Error Interrupt Enable Bit */ +#define XDMAC_CIE_WBIE (0x1u << 5) /**< \brief (XDMAC_CIE) Write Bus Error Interrupt Enable Bit */ +#define XDMAC_CIE_ROIE (0x1u << 6) /**< \brief (XDMAC_CIE) Request Overflow Error Interrupt Enable Bit */ +/* -------- XDMAC_CID : (XDMAC Offset: N/A) Channel Interrupt Disable Register -------- */ +#define XDMAC_CID_BID (0x1u << 0) /**< \brief (XDMAC_CID) End of Block Interrupt Disable Bit */ +#define XDMAC_CID_LID (0x1u << 1) /**< \brief (XDMAC_CID) End of Linked List Interrupt Disable Bit */ +#define XDMAC_CID_DID (0x1u << 2) /**< \brief (XDMAC_CID) End of Disable Interrupt Disable Bit */ +#define XDMAC_CID_FID (0x1u << 3) /**< \brief (XDMAC_CID) End of Flush Interrupt Disable Bit */ +#define XDMAC_CID_RBEID (0x1u << 4) /**< \brief (XDMAC_CID) Read Bus Error Interrupt Disable Bit */ +#define XDMAC_CID_WBEID (0x1u << 5) /**< \brief (XDMAC_CID) Write Bus Error Interrupt Disable Bit */ +#define XDMAC_CID_ROID (0x1u << 6) /**< \brief (XDMAC_CID) Request Overflow Error Interrupt Disable Bit */ +/* -------- XDMAC_CIM : (XDMAC Offset: N/A) Channel Interrupt Mask Register -------- */ +#define XDMAC_CIM_BIM (0x1u << 0) /**< \brief (XDMAC_CIM) End of Block Interrupt Mask Bit */ +#define XDMAC_CIM_LIM (0x1u << 1) /**< \brief (XDMAC_CIM) End of Linked List Interrupt Mask Bit */ +#define XDMAC_CIM_DIM (0x1u << 2) /**< \brief (XDMAC_CIM) End of Disable Interrupt Mask Bit */ +#define XDMAC_CIM_FIM (0x1u << 3) /**< \brief (XDMAC_CIM) End of Flush Interrupt Mask Bit */ +#define XDMAC_CIM_RBEIM (0x1u << 4) /**< \brief (XDMAC_CIM) Read Bus Error Interrupt Mask Bit */ +#define XDMAC_CIM_WBEIM (0x1u << 5) /**< \brief (XDMAC_CIM) Write Bus Error Interrupt Mask Bit */ +#define XDMAC_CIM_ROIM (0x1u << 6) /**< \brief (XDMAC_CIM) Request Overflow Error Interrupt Mask Bit */ +/* -------- XDMAC_CIS : (XDMAC Offset: N/A) Channel Interrupt Status Register -------- */ +#define XDMAC_CIS_BIS (0x1u << 0) /**< \brief (XDMAC_CIS) End of Block Interrupt Status Bit */ +#define XDMAC_CIS_LIS (0x1u << 1) /**< \brief (XDMAC_CIS) End of Linked List Interrupt Status Bit */ +#define XDMAC_CIS_DIS (0x1u << 2) /**< \brief (XDMAC_CIS) End of Disable Interrupt Status Bit */ +#define XDMAC_CIS_FIS (0x1u << 3) /**< \brief (XDMAC_CIS) End of Flush Interrupt Status Bit */ +#define XDMAC_CIS_RBEIS (0x1u << 4) /**< \brief (XDMAC_CIS) Read Bus Error Interrupt Status Bit */ +#define XDMAC_CIS_WBEIS (0x1u << 5) /**< \brief (XDMAC_CIS) Write Bus Error Interrupt Status Bit */ +#define XDMAC_CIS_ROIS (0x1u << 6) /**< \brief (XDMAC_CIS) Request Overflow Error Interrupt Status Bit */ +/* -------- XDMAC_CSA : (XDMAC Offset: N/A) Channel Source Address Register -------- */ +#define XDMAC_CSA_SA_Pos 0 +#define XDMAC_CSA_SA_Msk (0xffffffffu << XDMAC_CSA_SA_Pos) /**< \brief (XDMAC_CSA) Channel x Source Address */ +#define XDMAC_CSA_SA(value) ((XDMAC_CSA_SA_Msk & ((value) << XDMAC_CSA_SA_Pos))) +/* -------- XDMAC_CDA : (XDMAC Offset: N/A) Channel Destination Address Register -------- */ +#define XDMAC_CDA_DA_Pos 0 +#define XDMAC_CDA_DA_Msk (0xffffffffu << XDMAC_CDA_DA_Pos) /**< \brief (XDMAC_CDA) Channel x Destination Address */ +#define XDMAC_CDA_DA(value) ((XDMAC_CDA_DA_Msk & ((value) << XDMAC_CDA_DA_Pos))) +/* -------- XDMAC_CNDA : (XDMAC Offset: N/A) Channel Next Descriptor Address Register -------- */ +#define XDMAC_CNDA_NDAIF (0x1u << 0) /**< \brief (XDMAC_CNDA) Channel x Next Descriptor Interface */ +#define XDMAC_CNDA_NDA_Pos 2 +#define XDMAC_CNDA_NDA_Msk (0x3fffffffu << XDMAC_CNDA_NDA_Pos) /**< \brief (XDMAC_CNDA) Channel x Next Descriptor Address */ +#define XDMAC_CNDA_NDA(value) (XDMAC_CNDA_NDA_Msk & (value)) +/* -------- XDMAC_CNDC : (XDMAC Offset: N/A) Channel Next Descriptor Control Register -------- */ +#define XDMAC_CNDC_NDE (0x1u << 0) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Enable */ +#define XDMAC_CNDC_NDE_DSCR_FETCH_DIS (0x0u << 0) /**< \brief (XDMAC_CNDC) Descriptor fetch is disabled */ +#define XDMAC_CNDC_NDE_DSCR_FETCH_EN (0x1u << 0) /**< \brief (XDMAC_CNDC) Descriptor fetch is enabled */ +#define XDMAC_CNDC_NDSUP (0x1u << 1) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Source Update */ +#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UNCHANGED (0x0u << 1) /**< \brief (XDMAC_CNDC) Source parameters remain unchanged. */ +#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED (0x1u << 1) /**< \brief (XDMAC_CNDC) Source parameters are updated when the descriptor is retrieved. */ +#define XDMAC_CNDC_NDDUP (0x1u << 2) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Destination Update */ +#define XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED (0x0u << 2) /**< \brief (XDMAC_CNDC) Destination parameters remain unchanged. */ +#define XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED (0x1u << 2) /**< \brief (XDMAC_CNDC) Destination parameters are updated when the descriptor is retrieved. */ +#define XDMAC_CNDC_NDVIEW_Pos 3 +#define XDMAC_CNDC_NDVIEW_Msk (0x3u << XDMAC_CNDC_NDVIEW_Pos) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor View */ +#define XDMAC_CNDC_NDVIEW(value) ((XDMAC_CNDC_NDVIEW_Msk & ((value) << XDMAC_CNDC_NDVIEW_Pos))) +#define XDMAC_CNDC_NDVIEW_NDV0 (0x0u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 0 */ +#define XDMAC_CNDC_NDVIEW_NDV1 (0x1u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 1 */ +#define XDMAC_CNDC_NDVIEW_NDV2 (0x2u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 2 */ +#define XDMAC_CNDC_NDVIEW_NDV3 (0x3u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 3 */ +/* -------- XDMAC_CUBC : (XDMAC Offset: N/A) Channel Microblock Control Register -------- */ +#define XDMAC_CUBC_UBLEN_Pos 0 +#define XDMAC_CUBC_UBLEN_Msk (0xffffffu << XDMAC_CUBC_UBLEN_Pos) /**< \brief (XDMAC_CUBC) Channel x Microblock Length */ +#define XDMAC_CUBC_UBLEN(value) ((XDMAC_CUBC_UBLEN_Msk & ((value) << XDMAC_CUBC_UBLEN_Pos))) +/* -------- XDMAC_CBC : (XDMAC Offset: N/A) Channel Block Control Register -------- */ +#define XDMAC_CBC_BLEN_Pos 0 +#define XDMAC_CBC_BLEN_Msk (0xfffu << XDMAC_CBC_BLEN_Pos) /**< \brief (XDMAC_CBC) Channel x Block Length */ +#define XDMAC_CBC_BLEN(value) ((XDMAC_CBC_BLEN_Msk & ((value) << XDMAC_CBC_BLEN_Pos))) +/* -------- XDMAC_CC : (XDMAC Offset: N/A) Channel Configuration Register -------- */ +#define XDMAC_CC_TYPE (0x1u << 0) /**< \brief (XDMAC_CC) Channel x Transfer Type */ +#define XDMAC_CC_TYPE_MEM_TRAN (0x0u << 0) /**< \brief (XDMAC_CC) Self triggered mode (Memory to Memory Transfer). */ +#define XDMAC_CC_TYPE_PER_TRAN (0x1u << 0) /**< \brief (XDMAC_CC) Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). */ +#define XDMAC_CC_MBSIZE_Pos 1 +#define XDMAC_CC_MBSIZE_Msk (0x3u << XDMAC_CC_MBSIZE_Pos) /**< \brief (XDMAC_CC) Channel x Memory Burst Size */ +#define XDMAC_CC_MBSIZE(value) ((XDMAC_CC_MBSIZE_Msk & ((value) << XDMAC_CC_MBSIZE_Pos))) +#define XDMAC_CC_MBSIZE_SINGLE (0x0u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to one. */ +#define XDMAC_CC_MBSIZE_FOUR (0x1u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to four. */ +#define XDMAC_CC_MBSIZE_EIGHT (0x2u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to eight. */ +#define XDMAC_CC_MBSIZE_SIXTEEN (0x3u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to sixteen. */ +#define XDMAC_CC_DSYNC (0x1u << 4) /**< \brief (XDMAC_CC) Channel x Synchronization */ +#define XDMAC_CC_DSYNC_PER2MEM (0x0u << 4) /**< \brief (XDMAC_CC) Peripheral to Memory transfer */ +#define XDMAC_CC_DSYNC_MEM2PER (0x1u << 4) /**< \brief (XDMAC_CC) Memory to Peripheral transfer */ +#define XDMAC_CC_PROT (0x1u << 5) /**< \brief (XDMAC_CC) Channel x Protection */ +#define XDMAC_CC_PROT_SEC (0x0u << 5) /**< \brief (XDMAC_CC) Channel is secured */ +#define XDMAC_CC_PROT_UNSEC (0x1u << 5) /**< \brief (XDMAC_CC) Channel is unsecured */ +#define XDMAC_CC_SWREQ (0x1u << 6) /**< \brief (XDMAC_CC) Channel x Software Request Trigger */ +#define XDMAC_CC_SWREQ_HWR_CONNECTED (0x0u << 6) /**< \brief (XDMAC_CC) Hardware request line is connected to the peripheral request line. */ +#define XDMAC_CC_SWREQ_SWR_CONNECTED (0x1u << 6) /**< \brief (XDMAC_CC) Software request is connected to the peripheral request line. */ +#define XDMAC_CC_MEMSET (0x1u << 7) /**< \brief (XDMAC_CC) Channel x Fill Block of memory */ +#define XDMAC_CC_MEMSET_NORMAL_MODE (0x0u << 7) /**< \brief (XDMAC_CC) Memset is not activated */ +#define XDMAC_CC_MEMSET_HW_MODE (0x1u << 7) /**< \brief (XDMAC_CC) Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. */ +#define XDMAC_CC_CSIZE_Pos 8 +#define XDMAC_CC_CSIZE_Msk (0x7u << XDMAC_CC_CSIZE_Pos) /**< \brief (XDMAC_CC) Channel x Chunk Size */ +#define XDMAC_CC_CSIZE(value) ((XDMAC_CC_CSIZE_Msk & ((value) << XDMAC_CC_CSIZE_Pos))) +#define XDMAC_CC_CSIZE_CHK_1 (0x0u << 8) /**< \brief (XDMAC_CC) 1 data transferred */ +#define XDMAC_CC_CSIZE_CHK_2 (0x1u << 8) /**< \brief (XDMAC_CC) 2 data transferred */ +#define XDMAC_CC_CSIZE_CHK_4 (0x2u << 8) /**< \brief (XDMAC_CC) 4 data transferred */ +#define XDMAC_CC_CSIZE_CHK_8 (0x3u << 8) /**< \brief (XDMAC_CC) 8 data transferred */ +#define XDMAC_CC_CSIZE_CHK_16 (0x4u << 8) /**< \brief (XDMAC_CC) 16 data transferred */ +#define XDMAC_CC_DWIDTH_Pos 11 +#define XDMAC_CC_DWIDTH_Msk (0x3u << XDMAC_CC_DWIDTH_Pos) /**< \brief (XDMAC_CC) Channel x Data Width */ +#define XDMAC_CC_DWIDTH(value) ((XDMAC_CC_DWIDTH_Msk & ((value) << XDMAC_CC_DWIDTH_Pos))) +#define XDMAC_CC_DWIDTH_BYTE (0x0u << 11) /**< \brief (XDMAC_CC) The data size is set to 8 bits */ +#define XDMAC_CC_DWIDTH_HALFWORD (0x1u << 11) /**< \brief (XDMAC_CC) The data size is set to 16 bits */ +#define XDMAC_CC_DWIDTH_WORD (0x2u << 11) /**< \brief (XDMAC_CC) The data size is set to 32 bits */ +#define XDMAC_CC_SIF (0x1u << 13) /**< \brief (XDMAC_CC) Channel x Source Interface Identifier */ +#define XDMAC_CC_SIF_AHB_IF0 (0x0u << 13) /**< \brief (XDMAC_CC) The data is read through the system bus interface 0 */ +#define XDMAC_CC_SIF_AHB_IF1 (0x1u << 13) /**< \brief (XDMAC_CC) The data is read through the system bus interface 1 */ +#define XDMAC_CC_DIF (0x1u << 14) /**< \brief (XDMAC_CC) Channel x Destination Interface Identifier */ +#define XDMAC_CC_DIF_AHB_IF0 (0x0u << 14) /**< \brief (XDMAC_CC) The data is written through the system bus interface 0 */ +#define XDMAC_CC_DIF_AHB_IF1 (0x1u << 14) /**< \brief (XDMAC_CC) The data is written though the system bus interface 1 */ +#define XDMAC_CC_SAM_Pos 16 +#define XDMAC_CC_SAM_Msk (0x3u << XDMAC_CC_SAM_Pos) /**< \brief (XDMAC_CC) Channel x Source Addressing Mode */ +#define XDMAC_CC_SAM(value) ((XDMAC_CC_SAM_Msk & ((value) << XDMAC_CC_SAM_Pos))) +#define XDMAC_CC_SAM_FIXED_AM (0x0u << 16) /**< \brief (XDMAC_CC) The address remains unchanged. */ +#define XDMAC_CC_SAM_INCREMENTED_AM (0x1u << 16) /**< \brief (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */ +#define XDMAC_CC_SAM_UBS_AM (0x2u << 16) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary. */ +#define XDMAC_CC_SAM_UBS_DS_AM (0x3u << 16) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. */ +#define XDMAC_CC_DAM_Pos 18 +#define XDMAC_CC_DAM_Msk (0x3u << XDMAC_CC_DAM_Pos) /**< \brief (XDMAC_CC) Channel x Destination Addressing Mode */ +#define XDMAC_CC_DAM(value) ((XDMAC_CC_DAM_Msk & ((value) << XDMAC_CC_DAM_Pos))) +#define XDMAC_CC_DAM_FIXED_AM (0x0u << 18) /**< \brief (XDMAC_CC) The address remains unchanged. */ +#define XDMAC_CC_DAM_INCREMENTED_AM (0x1u << 18) /**< \brief (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */ +#define XDMAC_CC_DAM_UBS_AM (0x2u << 18) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary. */ +#define XDMAC_CC_DAM_UBS_DS_AM (0x3u << 18) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. */ +#define XDMAC_CC_INITD (0x1u << 21) /**< \brief (XDMAC_CC) Channel Initialization Terminated (this bit is read-only) */ +#define XDMAC_CC_INITD_IN_PROGRESS (0x0u << 21) /**< \brief (XDMAC_CC) Channel initialization is in progress. */ +#define XDMAC_CC_INITD_TERMINATED (0x1u << 21) /**< \brief (XDMAC_CC) Channel initialization is completed. */ +#define XDMAC_CC_RDIP (0x1u << 22) /**< \brief (XDMAC_CC) Read in Progress (this bit is read-only) */ +#define XDMAC_CC_RDIP_DONE (0x0u << 22) /**< \brief (XDMAC_CC) No Active read transaction on the bus. */ +#define XDMAC_CC_RDIP_IN_PROGRESS (0x1u << 22) /**< \brief (XDMAC_CC) A read transaction is in progress. */ +#define XDMAC_CC_WRIP (0x1u << 23) /**< \brief (XDMAC_CC) Write in Progress (this bit is read-only) */ +#define XDMAC_CC_WRIP_DONE (0x0u << 23) /**< \brief (XDMAC_CC) No Active write transaction on the bus. */ +#define XDMAC_CC_WRIP_IN_PROGRESS (0x1u << 23) /**< \brief (XDMAC_CC) A Write transaction is in progress. */ +#define XDMAC_CC_PERID_Pos 24 +#define XDMAC_CC_PERID_Msk (0x7fu << XDMAC_CC_PERID_Pos) /**< \brief (XDMAC_CC) Channel x Peripheral Identifier */ +#define XDMAC_CC_PERID(value) ((XDMAC_CC_PERID_Msk & ((value) << XDMAC_CC_PERID_Pos))) +/* -------- XDMAC_CDS_MSP : (XDMAC Offset: N/A) Channel Data Stride Memory Set Pattern -------- */ +#define XDMAC_CDS_MSP_SDS_MSP_Pos 0 +#define XDMAC_CDS_MSP_SDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_SDS_MSP_Pos) /**< \brief (XDMAC_CDS_MSP) Channel x Source Data stride or Memory Set Pattern */ +#define XDMAC_CDS_MSP_SDS_MSP(value) ((XDMAC_CDS_MSP_SDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_SDS_MSP_Pos))) +#define XDMAC_CDS_MSP_DDS_MSP_Pos 16 +#define XDMAC_CDS_MSP_DDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_DDS_MSP_Pos) /**< \brief (XDMAC_CDS_MSP) Channel x Destination Data Stride or Memory Set Pattern */ +#define XDMAC_CDS_MSP_DDS_MSP(value) ((XDMAC_CDS_MSP_DDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_DDS_MSP_Pos))) +/* -------- XDMAC_CSUS : (XDMAC Offset: N/A) Channel Source Microblock Stride -------- */ +#define XDMAC_CSUS_SUBS_Pos 0 +#define XDMAC_CSUS_SUBS_Msk (0xffffffu << XDMAC_CSUS_SUBS_Pos) /**< \brief (XDMAC_CSUS) Channel x Source Microblock Stride */ +#define XDMAC_CSUS_SUBS(value) ((XDMAC_CSUS_SUBS_Msk & ((value) << XDMAC_CSUS_SUBS_Pos))) +/* -------- XDMAC_CDUS : (XDMAC Offset: N/A) Channel Destination Microblock Stride -------- */ +#define XDMAC_CDUS_DUBS_Pos 0 +#define XDMAC_CDUS_DUBS_Msk (0xffffffu << XDMAC_CDUS_DUBS_Pos) /**< \brief (XDMAC_CDUS) Channel x Destination Microblock Stride */ +#define XDMAC_CDUS_DUBS(value) ((XDMAC_CDUS_DUBS_Msk & ((value) << XDMAC_CDUS_DUBS_Pos))) +/* -------- XDMAC_VERSION : (XDMAC Offset: 0xFFC) XDMAC Version Register -------- */ +#define XDMAC_VERSION_VERSION_Pos 0 +#define XDMAC_VERSION_VERSION_Msk (0xfffu << XDMAC_VERSION_VERSION_Pos) /**< \brief (XDMAC_VERSION) Version of the Hardware Module */ +#define XDMAC_VERSION_VERSION(value) ((XDMAC_VERSION_VERSION_Msk & ((value) << XDMAC_VERSION_VERSION_Pos))) +#define XDMAC_VERSION_MFN_Pos 16 +#define XDMAC_VERSION_MFN_Msk (0x7u << XDMAC_VERSION_MFN_Pos) /**< \brief (XDMAC_VERSION) Metal Fix Number */ +#define XDMAC_VERSION_MFN(value) ((XDMAC_VERSION_MFN_Msk & ((value) << XDMAC_VERSION_MFN_Pos))) + +/*@}*/ + + +#endif /* _SAME70_XDMAC_COMPONENT_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/acc.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/acc.h new file mode 100644 index 000000000..f447d25c3 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/acc.h @@ -0,0 +1,63 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_ACC_INSTANCE_ +#define _SAME70_ACC_INSTANCE_ + +/* ========== Register definition for ACC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_ACC_CR (0x40044000U) /**< \brief (ACC) Control Register */ + #define REG_ACC_MR (0x40044004U) /**< \brief (ACC) Mode Register */ + #define REG_ACC_IER (0x40044024U) /**< \brief (ACC) Interrupt Enable Register */ + #define REG_ACC_IDR (0x40044028U) /**< \brief (ACC) Interrupt Disable Register */ + #define REG_ACC_IMR (0x4004402CU) /**< \brief (ACC) Interrupt Mask Register */ + #define REG_ACC_ISR (0x40044030U) /**< \brief (ACC) Interrupt Status Register */ + #define REG_ACC_ACR (0x40044094U) /**< \brief (ACC) Analog Control Register */ + #define REG_ACC_WPMR (0x400440E4U) /**< \brief (ACC) Write Protection Mode Register */ + #define REG_ACC_WPSR (0x400440E8U) /**< \brief (ACC) Write Protection Status Register */ + #define REG_ACC_VER (0x400440FCU) /**< \brief (ACC) Version Register */ +#else + #define REG_ACC_CR (*(__O uint32_t*)0x40044000U) /**< \brief (ACC) Control Register */ + #define REG_ACC_MR (*(__IO uint32_t*)0x40044004U) /**< \brief (ACC) Mode Register */ + #define REG_ACC_IER (*(__O uint32_t*)0x40044024U) /**< \brief (ACC) Interrupt Enable Register */ + #define REG_ACC_IDR (*(__O uint32_t*)0x40044028U) /**< \brief (ACC) Interrupt Disable Register */ + #define REG_ACC_IMR (*(__I uint32_t*)0x4004402CU) /**< \brief (ACC) Interrupt Mask Register */ + #define REG_ACC_ISR (*(__I uint32_t*)0x40044030U) /**< \brief (ACC) Interrupt Status Register */ + #define REG_ACC_ACR (*(__IO uint32_t*)0x40044094U) /**< \brief (ACC) Analog Control Register */ + #define REG_ACC_WPMR (*(__IO uint32_t*)0x400440E4U) /**< \brief (ACC) Write Protection Mode Register */ + #define REG_ACC_WPSR (*(__I uint32_t*)0x400440E8U) /**< \brief (ACC) Write Protection Status Register */ + #define REG_ACC_VER (*(__I uint32_t*)0x400440FCU) /**< \brief (ACC) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_ACC_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/aes.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/aes.h new file mode 100644 index 000000000..713ced126 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/aes.h @@ -0,0 +1,77 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_AES_INSTANCE_ +#define _SAME70_AES_INSTANCE_ + +/* ========== Register definition for AES peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_AES_CR (0x4006C000U) /**< \brief (AES) Control Register */ + #define REG_AES_MR (0x4006C004U) /**< \brief (AES) Mode Register */ + #define REG_AES_IER (0x4006C010U) /**< \brief (AES) Interrupt Enable Register */ + #define REG_AES_IDR (0x4006C014U) /**< \brief (AES) Interrupt Disable Register */ + #define REG_AES_IMR (0x4006C018U) /**< \brief (AES) Interrupt Mask Register */ + #define REG_AES_ISR (0x4006C01CU) /**< \brief (AES) Interrupt Status Register */ + #define REG_AES_KEYWR (0x4006C020U) /**< \brief (AES) Key Word Register */ + #define REG_AES_IDATAR (0x4006C040U) /**< \brief (AES) Input Data Register */ + #define REG_AES_ODATAR (0x4006C050U) /**< \brief (AES) Output Data Register */ + #define REG_AES_IVR (0x4006C060U) /**< \brief (AES) Initialization Vector Register */ + #define REG_AES_AADLENR (0x4006C070U) /**< \brief (AES) Additional Authenticated Data Length Register */ + #define REG_AES_CLENR (0x4006C074U) /**< \brief (AES) Plaintext/Ciphertext Length Register */ + #define REG_AES_GHASHR (0x4006C078U) /**< \brief (AES) GCM Intermediate Hash Word Register */ + #define REG_AES_TAGR (0x4006C088U) /**< \brief (AES) GCM Authentication Tag Word Register */ + #define REG_AES_CTRR (0x4006C098U) /**< \brief (AES) GCM Encryption Counter Value Register */ + #define REG_AES_GCMHR (0x4006C09CU) /**< \brief (AES) GCM H Word Register */ + #define REG_AES_VERSION (0x4006C0FCU) /**< \brief (AES) Version Register */ +#else + #define REG_AES_CR (*(__O uint32_t*)0x4006C000U) /**< \brief (AES) Control Register */ + #define REG_AES_MR (*(__IO uint32_t*)0x4006C004U) /**< \brief (AES) Mode Register */ + #define REG_AES_IER (*(__O uint32_t*)0x4006C010U) /**< \brief (AES) Interrupt Enable Register */ + #define REG_AES_IDR (*(__O uint32_t*)0x4006C014U) /**< \brief (AES) Interrupt Disable Register */ + #define REG_AES_IMR (*(__I uint32_t*)0x4006C018U) /**< \brief (AES) Interrupt Mask Register */ + #define REG_AES_ISR (*(__I uint32_t*)0x4006C01CU) /**< \brief (AES) Interrupt Status Register */ + #define REG_AES_KEYWR (*(__O uint32_t*)0x4006C020U) /**< \brief (AES) Key Word Register */ + #define REG_AES_IDATAR (*(__O uint32_t*)0x4006C040U) /**< \brief (AES) Input Data Register */ + #define REG_AES_ODATAR (*(__I uint32_t*)0x4006C050U) /**< \brief (AES) Output Data Register */ + #define REG_AES_IVR (*(__O uint32_t*)0x4006C060U) /**< \brief (AES) Initialization Vector Register */ + #define REG_AES_AADLENR (*(__IO uint32_t*)0x4006C070U) /**< \brief (AES) Additional Authenticated Data Length Register */ + #define REG_AES_CLENR (*(__IO uint32_t*)0x4006C074U) /**< \brief (AES) Plaintext/Ciphertext Length Register */ + #define REG_AES_GHASHR (*(__IO uint32_t*)0x4006C078U) /**< \brief (AES) GCM Intermediate Hash Word Register */ + #define REG_AES_TAGR (*(__I uint32_t*)0x4006C088U) /**< \brief (AES) GCM Authentication Tag Word Register */ + #define REG_AES_CTRR (*(__I uint32_t*)0x4006C098U) /**< \brief (AES) GCM Encryption Counter Value Register */ + #define REG_AES_GCMHR (*(__IO uint32_t*)0x4006C09CU) /**< \brief (AES) GCM H Word Register */ + #define REG_AES_VERSION (*(__I uint32_t*)0x4006C0FCU) /**< \brief (AES) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_AES_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/afec0.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/afec0.h new file mode 100644 index 000000000..2bf7de215 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/afec0.h @@ -0,0 +1,103 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_AFEC0_INSTANCE_ +#define _SAME70_AFEC0_INSTANCE_ + +/* ========== Register definition for AFEC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_AFEC0_CR (0x4003C000U) /**< \brief (AFEC0) AFEC Control Register */ + #define REG_AFEC0_MR (0x4003C004U) /**< \brief (AFEC0) AFEC Mode Register */ + #define REG_AFEC0_EMR (0x4003C008U) /**< \brief (AFEC0) AFEC Extended Mode Register */ + #define REG_AFEC0_SEQ1R (0x4003C00CU) /**< \brief (AFEC0) AFEC Channel Sequence 1 Register */ + #define REG_AFEC0_SEQ2R (0x4003C010U) /**< \brief (AFEC0) AFEC Channel Sequence 2 Register */ + #define REG_AFEC0_CHER (0x4003C014U) /**< \brief (AFEC0) AFEC Channel Enable Register */ + #define REG_AFEC0_CHDR (0x4003C018U) /**< \brief (AFEC0) AFEC Channel Disable Register */ + #define REG_AFEC0_CHSR (0x4003C01CU) /**< \brief (AFEC0) AFEC Channel Status Register */ + #define REG_AFEC0_LCDR (0x4003C020U) /**< \brief (AFEC0) AFEC Last Converted Data Register */ + #define REG_AFEC0_IER (0x4003C024U) /**< \brief (AFEC0) AFEC Interrupt Enable Register */ + #define REG_AFEC0_IDR (0x4003C028U) /**< \brief (AFEC0) AFEC Interrupt Disable Register */ + #define REG_AFEC0_IMR (0x4003C02CU) /**< \brief (AFEC0) AFEC Interrupt Mask Register */ + #define REG_AFEC0_ISR (0x4003C030U) /**< \brief (AFEC0) AFEC Interrupt Status Register */ + #define REG_AFEC0_OVER (0x4003C04CU) /**< \brief (AFEC0) AFEC Overrun Status Register */ + #define REG_AFEC0_CWR (0x4003C050U) /**< \brief (AFEC0) AFEC Compare Window Register */ + #define REG_AFEC0_CGR (0x4003C054U) /**< \brief (AFEC0) AFEC Channel Gain Register */ + #define REG_AFEC0_DIFFR (0x4003C060U) /**< \brief (AFEC0) AFEC Channel Differential Register */ + #define REG_AFEC0_CSELR (0x4003C064U) /**< \brief (AFEC0) AFEC Channel Selection Register */ + #define REG_AFEC0_CDR (0x4003C068U) /**< \brief (AFEC0) AFEC Channel Data Register */ + #define REG_AFEC0_COCR (0x4003C06CU) /**< \brief (AFEC0) AFEC Channel Offset Compensation Register */ + #define REG_AFEC0_TEMPMR (0x4003C070U) /**< \brief (AFEC0) AFEC Temperature Sensor Mode Register */ + #define REG_AFEC0_TEMPCWR (0x4003C074U) /**< \brief (AFEC0) AFEC Temperature Compare Window Register */ + #define REG_AFEC0_ACR (0x4003C094U) /**< \brief (AFEC0) AFEC Analog Control Register */ + #define REG_AFEC0_SHMR (0x4003C0A0U) /**< \brief (AFEC0) AFEC Sample & Hold Mode Register */ + #define REG_AFEC0_COSR (0x4003C0D0U) /**< \brief (AFEC0) AFEC Correction Select Register */ + #define REG_AFEC0_CVR (0x4003C0D4U) /**< \brief (AFEC0) AFEC Correction Values Register */ + #define REG_AFEC0_CECR (0x4003C0D8U) /**< \brief (AFEC0) AFEC Channel Error Correction Register */ + #define REG_AFEC0_WPMR (0x4003C0E4U) /**< \brief (AFEC0) AFEC Write Protection Mode Register */ + #define REG_AFEC0_WPSR (0x4003C0E8U) /**< \brief (AFEC0) AFEC Write Protection Status Register */ + #define REG_AFEC0_VERSION (0x4003C0FCU) /**< \brief (AFEC0) AFEC Version Register */ +#else + #define REG_AFEC0_CR (*(__O uint32_t*)0x4003C000U) /**< \brief (AFEC0) AFEC Control Register */ + #define REG_AFEC0_MR (*(__IO uint32_t*)0x4003C004U) /**< \brief (AFEC0) AFEC Mode Register */ + #define REG_AFEC0_EMR (*(__IO uint32_t*)0x4003C008U) /**< \brief (AFEC0) AFEC Extended Mode Register */ + #define REG_AFEC0_SEQ1R (*(__IO uint32_t*)0x4003C00CU) /**< \brief (AFEC0) AFEC Channel Sequence 1 Register */ + #define REG_AFEC0_SEQ2R (*(__IO uint32_t*)0x4003C010U) /**< \brief (AFEC0) AFEC Channel Sequence 2 Register */ + #define REG_AFEC0_CHER (*(__O uint32_t*)0x4003C014U) /**< \brief (AFEC0) AFEC Channel Enable Register */ + #define REG_AFEC0_CHDR (*(__O uint32_t*)0x4003C018U) /**< \brief (AFEC0) AFEC Channel Disable Register */ + #define REG_AFEC0_CHSR (*(__I uint32_t*)0x4003C01CU) /**< \brief (AFEC0) AFEC Channel Status Register */ + #define REG_AFEC0_LCDR (*(__I uint32_t*)0x4003C020U) /**< \brief (AFEC0) AFEC Last Converted Data Register */ + #define REG_AFEC0_IER (*(__O uint32_t*)0x4003C024U) /**< \brief (AFEC0) AFEC Interrupt Enable Register */ + #define REG_AFEC0_IDR (*(__O uint32_t*)0x4003C028U) /**< \brief (AFEC0) AFEC Interrupt Disable Register */ + #define REG_AFEC0_IMR (*(__I uint32_t*)0x4003C02CU) /**< \brief (AFEC0) AFEC Interrupt Mask Register */ + #define REG_AFEC0_ISR (*(__I uint32_t*)0x4003C030U) /**< \brief (AFEC0) AFEC Interrupt Status Register */ + #define REG_AFEC0_OVER (*(__I uint32_t*)0x4003C04CU) /**< \brief (AFEC0) AFEC Overrun Status Register */ + #define REG_AFEC0_CWR (*(__IO uint32_t*)0x4003C050U) /**< \brief (AFEC0) AFEC Compare Window Register */ + #define REG_AFEC0_CGR (*(__IO uint32_t*)0x4003C054U) /**< \brief (AFEC0) AFEC Channel Gain Register */ + #define REG_AFEC0_DIFFR (*(__IO uint32_t*)0x4003C060U) /**< \brief (AFEC0) AFEC Channel Differential Register */ + #define REG_AFEC0_CSELR (*(__IO uint32_t*)0x4003C064U) /**< \brief (AFEC0) AFEC Channel Selection Register */ + #define REG_AFEC0_CDR (*(__I uint32_t*)0x4003C068U) /**< \brief (AFEC0) AFEC Channel Data Register */ + #define REG_AFEC0_COCR (*(__IO uint32_t*)0x4003C06CU) /**< \brief (AFEC0) AFEC Channel Offset Compensation Register */ + #define REG_AFEC0_TEMPMR (*(__IO uint32_t*)0x4003C070U) /**< \brief (AFEC0) AFEC Temperature Sensor Mode Register */ + #define REG_AFEC0_TEMPCWR (*(__IO uint32_t*)0x4003C074U) /**< \brief (AFEC0) AFEC Temperature Compare Window Register */ + #define REG_AFEC0_ACR (*(__IO uint32_t*)0x4003C094U) /**< \brief (AFEC0) AFEC Analog Control Register */ + #define REG_AFEC0_SHMR (*(__IO uint32_t*)0x4003C0A0U) /**< \brief (AFEC0) AFEC Sample & Hold Mode Register */ + #define REG_AFEC0_COSR (*(__IO uint32_t*)0x4003C0D0U) /**< \brief (AFEC0) AFEC Correction Select Register */ + #define REG_AFEC0_CVR (*(__IO uint32_t*)0x4003C0D4U) /**< \brief (AFEC0) AFEC Correction Values Register */ + #define REG_AFEC0_CECR (*(__IO uint32_t*)0x4003C0D8U) /**< \brief (AFEC0) AFEC Channel Error Correction Register */ + #define REG_AFEC0_WPMR (*(__IO uint32_t*)0x4003C0E4U) /**< \brief (AFEC0) AFEC Write Protection Mode Register */ + #define REG_AFEC0_WPSR (*(__I uint32_t*)0x4003C0E8U) /**< \brief (AFEC0) AFEC Write Protection Status Register */ + #define REG_AFEC0_VERSION (*(__I uint32_t*)0x4003C0FCU) /**< \brief (AFEC0) AFEC Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_AFEC0_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/afec1.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/afec1.h new file mode 100644 index 000000000..9713876a0 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/afec1.h @@ -0,0 +1,103 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_AFEC1_INSTANCE_ +#define _SAME70_AFEC1_INSTANCE_ + +/* ========== Register definition for AFEC1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_AFEC1_CR (0x40064000U) /**< \brief (AFEC1) AFEC Control Register */ + #define REG_AFEC1_MR (0x40064004U) /**< \brief (AFEC1) AFEC Mode Register */ + #define REG_AFEC1_EMR (0x40064008U) /**< \brief (AFEC1) AFEC Extended Mode Register */ + #define REG_AFEC1_SEQ1R (0x4006400CU) /**< \brief (AFEC1) AFEC Channel Sequence 1 Register */ + #define REG_AFEC1_SEQ2R (0x40064010U) /**< \brief (AFEC1) AFEC Channel Sequence 2 Register */ + #define REG_AFEC1_CHER (0x40064014U) /**< \brief (AFEC1) AFEC Channel Enable Register */ + #define REG_AFEC1_CHDR (0x40064018U) /**< \brief (AFEC1) AFEC Channel Disable Register */ + #define REG_AFEC1_CHSR (0x4006401CU) /**< \brief (AFEC1) AFEC Channel Status Register */ + #define REG_AFEC1_LCDR (0x40064020U) /**< \brief (AFEC1) AFEC Last Converted Data Register */ + #define REG_AFEC1_IER (0x40064024U) /**< \brief (AFEC1) AFEC Interrupt Enable Register */ + #define REG_AFEC1_IDR (0x40064028U) /**< \brief (AFEC1) AFEC Interrupt Disable Register */ + #define REG_AFEC1_IMR (0x4006402CU) /**< \brief (AFEC1) AFEC Interrupt Mask Register */ + #define REG_AFEC1_ISR (0x40064030U) /**< \brief (AFEC1) AFEC Interrupt Status Register */ + #define REG_AFEC1_OVER (0x4006404CU) /**< \brief (AFEC1) AFEC Overrun Status Register */ + #define REG_AFEC1_CWR (0x40064050U) /**< \brief (AFEC1) AFEC Compare Window Register */ + #define REG_AFEC1_CGR (0x40064054U) /**< \brief (AFEC1) AFEC Channel Gain Register */ + #define REG_AFEC1_DIFFR (0x40064060U) /**< \brief (AFEC1) AFEC Channel Differential Register */ + #define REG_AFEC1_CSELR (0x40064064U) /**< \brief (AFEC1) AFEC Channel Selection Register */ + #define REG_AFEC1_CDR (0x40064068U) /**< \brief (AFEC1) AFEC Channel Data Register */ + #define REG_AFEC1_COCR (0x4006406CU) /**< \brief (AFEC1) AFEC Channel Offset Compensation Register */ + #define REG_AFEC1_TEMPMR (0x40064070U) /**< \brief (AFEC1) AFEC Temperature Sensor Mode Register */ + #define REG_AFEC1_TEMPCWR (0x40064074U) /**< \brief (AFEC1) AFEC Temperature Compare Window Register */ + #define REG_AFEC1_ACR (0x40064094U) /**< \brief (AFEC1) AFEC Analog Control Register */ + #define REG_AFEC1_SHMR (0x400640A0U) /**< \brief (AFEC1) AFEC Sample & Hold Mode Register */ + #define REG_AFEC1_COSR (0x400640D0U) /**< \brief (AFEC1) AFEC Correction Select Register */ + #define REG_AFEC1_CVR (0x400640D4U) /**< \brief (AFEC1) AFEC Correction Values Register */ + #define REG_AFEC1_CECR (0x400640D8U) /**< \brief (AFEC1) AFEC Channel Error Correction Register */ + #define REG_AFEC1_WPMR (0x400640E4U) /**< \brief (AFEC1) AFEC Write Protection Mode Register */ + #define REG_AFEC1_WPSR (0x400640E8U) /**< \brief (AFEC1) AFEC Write Protection Status Register */ + #define REG_AFEC1_VERSION (0x400640FCU) /**< \brief (AFEC1) AFEC Version Register */ +#else + #define REG_AFEC1_CR (*(__O uint32_t*)0x40064000U) /**< \brief (AFEC1) AFEC Control Register */ + #define REG_AFEC1_MR (*(__IO uint32_t*)0x40064004U) /**< \brief (AFEC1) AFEC Mode Register */ + #define REG_AFEC1_EMR (*(__IO uint32_t*)0x40064008U) /**< \brief (AFEC1) AFEC Extended Mode Register */ + #define REG_AFEC1_SEQ1R (*(__IO uint32_t*)0x4006400CU) /**< \brief (AFEC1) AFEC Channel Sequence 1 Register */ + #define REG_AFEC1_SEQ2R (*(__IO uint32_t*)0x40064010U) /**< \brief (AFEC1) AFEC Channel Sequence 2 Register */ + #define REG_AFEC1_CHER (*(__O uint32_t*)0x40064014U) /**< \brief (AFEC1) AFEC Channel Enable Register */ + #define REG_AFEC1_CHDR (*(__O uint32_t*)0x40064018U) /**< \brief (AFEC1) AFEC Channel Disable Register */ + #define REG_AFEC1_CHSR (*(__I uint32_t*)0x4006401CU) /**< \brief (AFEC1) AFEC Channel Status Register */ + #define REG_AFEC1_LCDR (*(__I uint32_t*)0x40064020U) /**< \brief (AFEC1) AFEC Last Converted Data Register */ + #define REG_AFEC1_IER (*(__O uint32_t*)0x40064024U) /**< \brief (AFEC1) AFEC Interrupt Enable Register */ + #define REG_AFEC1_IDR (*(__O uint32_t*)0x40064028U) /**< \brief (AFEC1) AFEC Interrupt Disable Register */ + #define REG_AFEC1_IMR (*(__I uint32_t*)0x4006402CU) /**< \brief (AFEC1) AFEC Interrupt Mask Register */ + #define REG_AFEC1_ISR (*(__I uint32_t*)0x40064030U) /**< \brief (AFEC1) AFEC Interrupt Status Register */ + #define REG_AFEC1_OVER (*(__I uint32_t*)0x4006404CU) /**< \brief (AFEC1) AFEC Overrun Status Register */ + #define REG_AFEC1_CWR (*(__IO uint32_t*)0x40064050U) /**< \brief (AFEC1) AFEC Compare Window Register */ + #define REG_AFEC1_CGR (*(__IO uint32_t*)0x40064054U) /**< \brief (AFEC1) AFEC Channel Gain Register */ + #define REG_AFEC1_DIFFR (*(__IO uint32_t*)0x40064060U) /**< \brief (AFEC1) AFEC Channel Differential Register */ + #define REG_AFEC1_CSELR (*(__IO uint32_t*)0x40064064U) /**< \brief (AFEC1) AFEC Channel Selection Register */ + #define REG_AFEC1_CDR (*(__I uint32_t*)0x40064068U) /**< \brief (AFEC1) AFEC Channel Data Register */ + #define REG_AFEC1_COCR (*(__IO uint32_t*)0x4006406CU) /**< \brief (AFEC1) AFEC Channel Offset Compensation Register */ + #define REG_AFEC1_TEMPMR (*(__IO uint32_t*)0x40064070U) /**< \brief (AFEC1) AFEC Temperature Sensor Mode Register */ + #define REG_AFEC1_TEMPCWR (*(__IO uint32_t*)0x40064074U) /**< \brief (AFEC1) AFEC Temperature Compare Window Register */ + #define REG_AFEC1_ACR (*(__IO uint32_t*)0x40064094U) /**< \brief (AFEC1) AFEC Analog Control Register */ + #define REG_AFEC1_SHMR (*(__IO uint32_t*)0x400640A0U) /**< \brief (AFEC1) AFEC Sample & Hold Mode Register */ + #define REG_AFEC1_COSR (*(__IO uint32_t*)0x400640D0U) /**< \brief (AFEC1) AFEC Correction Select Register */ + #define REG_AFEC1_CVR (*(__IO uint32_t*)0x400640D4U) /**< \brief (AFEC1) AFEC Correction Values Register */ + #define REG_AFEC1_CECR (*(__IO uint32_t*)0x400640D8U) /**< \brief (AFEC1) AFEC Channel Error Correction Register */ + #define REG_AFEC1_WPMR (*(__IO uint32_t*)0x400640E4U) /**< \brief (AFEC1) AFEC Write Protection Mode Register */ + #define REG_AFEC1_WPSR (*(__I uint32_t*)0x400640E8U) /**< \brief (AFEC1) AFEC Write Protection Status Register */ + #define REG_AFEC1_VERSION (*(__I uint32_t*)0x400640FCU) /**< \brief (AFEC1) AFEC Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_AFEC1_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/chipid.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/chipid.h new file mode 100644 index 000000000..9062e1372 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/chipid.h @@ -0,0 +1,47 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_CHIPID_INSTANCE_ +#define _SAME70_CHIPID_INSTANCE_ + +/* ========== Register definition for CHIPID peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_CHIPID_CIDR (0x400E0940U) /**< \brief (CHIPID) Chip ID Register */ + #define REG_CHIPID_EXID (0x400E0944U) /**< \brief (CHIPID) Chip ID Extension Register */ +#else + #define REG_CHIPID_CIDR (*(__I uint32_t*)0x400E0940U) /**< \brief (CHIPID) Chip ID Register */ + #define REG_CHIPID_EXID (*(__I uint32_t*)0x400E0944U) /**< \brief (CHIPID) Chip ID Extension Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_CHIPID_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/dacc.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/dacc.h new file mode 100644 index 000000000..5f7d6827e --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/dacc.h @@ -0,0 +1,73 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_DACC_INSTANCE_ +#define _SAME70_DACC_INSTANCE_ + +/* ========== Register definition for DACC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_DACC_CR (0x40040000U) /**< \brief (DACC) Control Register */ + #define REG_DACC_MR (0x40040004U) /**< \brief (DACC) Mode Register */ + #define REG_DACC_TRIGR (0x40040008U) /**< \brief (DACC) Trigger Register */ + #define REG_DACC_CHER (0x40040010U) /**< \brief (DACC) Channel Enable Register */ + #define REG_DACC_CHDR (0x40040014U) /**< \brief (DACC) Channel Disable Register */ + #define REG_DACC_CHSR (0x40040018U) /**< \brief (DACC) Channel Status Register */ + #define REG_DACC_CDR (0x4004001CU) /**< \brief (DACC) Conversion Data Register */ + #define REG_DACC_IER (0x40040024U) /**< \brief (DACC) Interrupt Enable Register */ + #define REG_DACC_IDR (0x40040028U) /**< \brief (DACC) Interrupt Disable Register */ + #define REG_DACC_IMR (0x4004002CU) /**< \brief (DACC) Interrupt Mask Register */ + #define REG_DACC_ISR (0x40040030U) /**< \brief (DACC) Interrupt Status Register */ + #define REG_DACC_ACR (0x40040094U) /**< \brief (DACC) Analog Current Register */ + #define REG_DACC_WPMR (0x400400E4U) /**< \brief (DACC) Write Protection Mode Register */ + #define REG_DACC_WPSR (0x400400E8U) /**< \brief (DACC) Write Protection Status Register */ + #define REG_DACC_VERSION (0x400400FCU) /**< \brief (DACC) Version Register */ +#else + #define REG_DACC_CR (*(__O uint32_t*)0x40040000U) /**< \brief (DACC) Control Register */ + #define REG_DACC_MR (*(__IO uint32_t*)0x40040004U) /**< \brief (DACC) Mode Register */ + #define REG_DACC_TRIGR (*(__IO uint32_t*)0x40040008U) /**< \brief (DACC) Trigger Register */ + #define REG_DACC_CHER (*(__O uint32_t*)0x40040010U) /**< \brief (DACC) Channel Enable Register */ + #define REG_DACC_CHDR (*(__O uint32_t*)0x40040014U) /**< \brief (DACC) Channel Disable Register */ + #define REG_DACC_CHSR (*(__I uint32_t*)0x40040018U) /**< \brief (DACC) Channel Status Register */ + #define REG_DACC_CDR (*(__O uint32_t*)0x4004001CU) /**< \brief (DACC) Conversion Data Register */ + #define REG_DACC_IER (*(__O uint32_t*)0x40040024U) /**< \brief (DACC) Interrupt Enable Register */ + #define REG_DACC_IDR (*(__O uint32_t*)0x40040028U) /**< \brief (DACC) Interrupt Disable Register */ + #define REG_DACC_IMR (*(__I uint32_t*)0x4004002CU) /**< \brief (DACC) Interrupt Mask Register */ + #define REG_DACC_ISR (*(__I uint32_t*)0x40040030U) /**< \brief (DACC) Interrupt Status Register */ + #define REG_DACC_ACR (*(__IO uint32_t*)0x40040094U) /**< \brief (DACC) Analog Current Register */ + #define REG_DACC_WPMR (*(__IO uint32_t*)0x400400E4U) /**< \brief (DACC) Write Protection Mode Register */ + #define REG_DACC_WPSR (*(__I uint32_t*)0x400400E8U) /**< \brief (DACC) Write Protection Status Register */ + #define REG_DACC_VERSION (*(__I uint32_t*)0x400400FCU) /**< \brief (DACC) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_DACC_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/efc.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/efc.h new file mode 100644 index 000000000..966f2d2c7 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/efc.h @@ -0,0 +1,55 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_EFC_INSTANCE_ +#define _SAME70_EFC_INSTANCE_ + +/* ========== Register definition for EFC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_EFC_FMR (0x400E0C00U) /**< \brief (EFC) EEFC Flash Mode Register */ + #define REG_EFC_FCR (0x400E0C04U) /**< \brief (EFC) EEFC Flash Command Register */ + #define REG_EFC_FSR (0x400E0C08U) /**< \brief (EFC) EEFC Flash Status Register */ + #define REG_EFC_FRR (0x400E0C0CU) /**< \brief (EFC) EEFC Flash Result Register */ + #define REG_EFC_VERSION (0x400E0C14U) /**< \brief (EFC) EEFC Version Register */ + #define REG_EFC_WPMR (0x400E0CE4U) /**< \brief (EFC) Write Protection Mode Register */ +#else + #define REG_EFC_FMR (*(__IO uint32_t*)0x400E0C00U) /**< \brief (EFC) EEFC Flash Mode Register */ + #define REG_EFC_FCR (*(__O uint32_t*)0x400E0C04U) /**< \brief (EFC) EEFC Flash Command Register */ + #define REG_EFC_FSR (*(__I uint32_t*)0x400E0C08U) /**< \brief (EFC) EEFC Flash Status Register */ + #define REG_EFC_FRR (*(__I uint32_t*)0x400E0C0CU) /**< \brief (EFC) EEFC Flash Result Register */ + #define REG_EFC_VERSION (*(__I uint32_t*)0x400E0C14U) /**< \brief (EFC) EEFC Version Register */ + #define REG_EFC_WPMR (*(__IO uint32_t*)0x400E0CE4U) /**< \brief (EFC) Write Protection Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_EFC_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/gmac.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/gmac.h new file mode 100644 index 000000000..7da518b78 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/gmac.h @@ -0,0 +1,385 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_GMAC_INSTANCE_ +#define _SAME70_GMAC_INSTANCE_ + +/* ========== Register definition for GMAC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_GMAC_NCR (0x40050000U) /**< \brief (GMAC) Network Control Register */ + #define REG_GMAC_NCFGR (0x40050004U) /**< \brief (GMAC) Network Configuration Register */ + #define REG_GMAC_NSR (0x40050008U) /**< \brief (GMAC) Network Status Register */ + #define REG_GMAC_UR (0x4005000CU) /**< \brief (GMAC) User Register */ + #define REG_GMAC_DCFGR (0x40050010U) /**< \brief (GMAC) DMA Configuration Register */ + #define REG_GMAC_TSR (0x40050014U) /**< \brief (GMAC) Transmit Status Register */ + #define REG_GMAC_RBQB (0x40050018U) /**< \brief (GMAC) Receive Buffer Queue Base Address Register */ + #define REG_GMAC_TBQB (0x4005001CU) /**< \brief (GMAC) Transmit Buffer Queue Base Address Register */ + #define REG_GMAC_RSR (0x40050020U) /**< \brief (GMAC) Receive Status Register */ + #define REG_GMAC_ISR (0x40050024U) /**< \brief (GMAC) Interrupt Status Register */ + #define REG_GMAC_IER (0x40050028U) /**< \brief (GMAC) Interrupt Enable Register */ + #define REG_GMAC_IDR (0x4005002CU) /**< \brief (GMAC) Interrupt Disable Register */ + #define REG_GMAC_IMR (0x40050030U) /**< \brief (GMAC) Interrupt Mask Register */ + #define REG_GMAC_MAN (0x40050034U) /**< \brief (GMAC) PHY Maintenance Register */ + #define REG_GMAC_RPQ (0x40050038U) /**< \brief (GMAC) Received Pause Quantum Register */ + #define REG_GMAC_TPQ (0x4005003CU) /**< \brief (GMAC) Transmit Pause Quantum Register */ + #define REG_GMAC_TPSF (0x40050040U) /**< \brief (GMAC) TX Partial Store and Forward Register */ + #define REG_GMAC_RPSF (0x40050044U) /**< \brief (GMAC) RX Partial Store and Forward Register */ + #define REG_GMAC_RJFML (0x40050048U) /**< \brief (GMAC) RX Jumbo Frame Max Length Register */ + #define REG_GMAC_HRB (0x40050080U) /**< \brief (GMAC) Hash Register Bottom */ + #define REG_GMAC_HRT (0x40050084U) /**< \brief (GMAC) Hash Register Top */ + #define REG_GMAC_SAB1 (0x40050088U) /**< \brief (GMAC) Specific Address 1 Bottom Register */ + #define REG_GMAC_SAT1 (0x4005008CU) /**< \brief (GMAC) Specific Address 1 Top Register */ + #define REG_GMAC_SAB2 (0x40050090U) /**< \brief (GMAC) Specific Address 2 Bottom Register */ + #define REG_GMAC_SAT2 (0x40050094U) /**< \brief (GMAC) Specific Address 2 Top Register */ + #define REG_GMAC_SAB3 (0x40050098U) /**< \brief (GMAC) Specific Address 3 Bottom Register */ + #define REG_GMAC_SAT3 (0x4005009CU) /**< \brief (GMAC) Specific Address 3 Top Register */ + #define REG_GMAC_SAB4 (0x400500A0U) /**< \brief (GMAC) Specific Address 4 Bottom Register */ + #define REG_GMAC_SAT4 (0x400500A4U) /**< \brief (GMAC) Specific Address 4 Top Register */ + #define REG_GMAC_TIDM1 (0x400500A8U) /**< \brief (GMAC) Type ID Match 1 Register */ + #define REG_GMAC_TIDM2 (0x400500ACU) /**< \brief (GMAC) Type ID Match 2 Register */ + #define REG_GMAC_TIDM3 (0x400500B0U) /**< \brief (GMAC) Type ID Match 3 Register */ + #define REG_GMAC_TIDM4 (0x400500B4U) /**< \brief (GMAC) Type ID Match 4 Register */ + #define REG_GMAC_WOL (0x400500B8U) /**< \brief (GMAC) Wake on LAN Register */ + #define REG_GMAC_IPGS (0x400500BCU) /**< \brief (GMAC) IPG Stretch Register */ + #define REG_GMAC_SVLAN (0x400500C0U) /**< \brief (GMAC) Stacked VLAN Register */ + #define REG_GMAC_TPFCP (0x400500C4U) /**< \brief (GMAC) Transmit PFC Pause Register */ + #define REG_GMAC_SAMB1 (0x400500C8U) /**< \brief (GMAC) Specific Address 1 Mask Bottom Register */ + #define REG_GMAC_SAMT1 (0x400500CCU) /**< \brief (GMAC) Specific Address 1 Mask Top Register */ + #define REG_GMAC_NSC (0x400500DCU) /**< \brief (GMAC) 1588 Timer Nanosecond Comparison Register */ + #define REG_GMAC_SCL (0x400500E0U) /**< \brief (GMAC) 1588 Timer Second Comparison Low Register */ + #define REG_GMAC_SCH (0x400500E4U) /**< \brief (GMAC) 1588 Timer Second Comparison High Register */ + #define REG_GMAC_EFTSH (0x400500E8U) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds High Register */ + #define REG_GMAC_EFRSH (0x400500ECU) /**< \brief (GMAC) PTP Event Frame Received Seconds High Register */ + #define REG_GMAC_PEFTSH (0x400500F0U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds High Register */ + #define REG_GMAC_PEFRSH (0x400500F4U) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds High Register */ + #define REG_GMAC_MID (0x400500FCU) /**< \brief (GMAC) Module ID Register */ + #define REG_GMAC_OTLO (0x40050100U) /**< \brief (GMAC) Octets Transmitted Low Register */ + #define REG_GMAC_OTHI (0x40050104U) /**< \brief (GMAC) Octets Transmitted High Register */ + #define REG_GMAC_FT (0x40050108U) /**< \brief (GMAC) Frames Transmitted Register */ + #define REG_GMAC_BCFT (0x4005010CU) /**< \brief (GMAC) Broadcast Frames Transmitted Register */ + #define REG_GMAC_MFT (0x40050110U) /**< \brief (GMAC) Multicast Frames Transmitted Register */ + #define REG_GMAC_PFT (0x40050114U) /**< \brief (GMAC) Pause Frames Transmitted Register */ + #define REG_GMAC_BFT64 (0x40050118U) /**< \brief (GMAC) 64 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT127 (0x4005011CU) /**< \brief (GMAC) 65 to 127 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT255 (0x40050120U) /**< \brief (GMAC) 128 to 255 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT511 (0x40050124U) /**< \brief (GMAC) 256 to 511 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT1023 (0x40050128U) /**< \brief (GMAC) 512 to 1023 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT1518 (0x4005012CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Transmitted Register */ + #define REG_GMAC_GTBFT1518 (0x40050130U) /**< \brief (GMAC) Greater Than 1518 Byte Frames Transmitted Register */ + #define REG_GMAC_TUR (0x40050134U) /**< \brief (GMAC) Transmit Underruns Register */ + #define REG_GMAC_SCF (0x40050138U) /**< \brief (GMAC) Single Collision Frames Register */ + #define REG_GMAC_MCF (0x4005013CU) /**< \brief (GMAC) Multiple Collision Frames Register */ + #define REG_GMAC_EC (0x40050140U) /**< \brief (GMAC) Excessive Collisions Register */ + #define REG_GMAC_LC (0x40050144U) /**< \brief (GMAC) Late Collisions Register */ + #define REG_GMAC_DTF (0x40050148U) /**< \brief (GMAC) Deferred Transmission Frames Register */ + #define REG_GMAC_CSE (0x4005014CU) /**< \brief (GMAC) Carrier Sense Errors Register */ + #define REG_GMAC_ORLO (0x40050150U) /**< \brief (GMAC) Octets Received Low Received Register */ + #define REG_GMAC_ORHI (0x40050154U) /**< \brief (GMAC) Octets Received High Received Register */ + #define REG_GMAC_FR (0x40050158U) /**< \brief (GMAC) Frames Received Register */ + #define REG_GMAC_BCFR (0x4005015CU) /**< \brief (GMAC) Broadcast Frames Received Register */ + #define REG_GMAC_MFR (0x40050160U) /**< \brief (GMAC) Multicast Frames Received Register */ + #define REG_GMAC_PFR (0x40050164U) /**< \brief (GMAC) Pause Frames Received Register */ + #define REG_GMAC_BFR64 (0x40050168U) /**< \brief (GMAC) 64 Byte Frames Received Register */ + #define REG_GMAC_TBFR127 (0x4005016CU) /**< \brief (GMAC) 65 to 127 Byte Frames Received Register */ + #define REG_GMAC_TBFR255 (0x40050170U) /**< \brief (GMAC) 128 to 255 Byte Frames Received Register */ + #define REG_GMAC_TBFR511 (0x40050174U) /**< \brief (GMAC) 256 to 511 Byte Frames Received Register */ + #define REG_GMAC_TBFR1023 (0x40050178U) /**< \brief (GMAC) 512 to 1023 Byte Frames Received Register */ + #define REG_GMAC_TBFR1518 (0x4005017CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Received Register */ + #define REG_GMAC_TMXBFR (0x40050180U) /**< \brief (GMAC) 1519 to Maximum Byte Frames Received Register */ + #define REG_GMAC_UFR (0x40050184U) /**< \brief (GMAC) Undersize Frames Received Register */ + #define REG_GMAC_OFR (0x40050188U) /**< \brief (GMAC) Oversize Frames Received Register */ + #define REG_GMAC_JR (0x4005018CU) /**< \brief (GMAC) Jabbers Received Register */ + #define REG_GMAC_FCSE (0x40050190U) /**< \brief (GMAC) Frame Check Sequence Errors Register */ + #define REG_GMAC_LFFE (0x40050194U) /**< \brief (GMAC) Length Field Frame Errors Register */ + #define REG_GMAC_RSE (0x40050198U) /**< \brief (GMAC) Receive Symbol Errors Register */ + #define REG_GMAC_AE (0x4005019CU) /**< \brief (GMAC) Alignment Errors Register */ + #define REG_GMAC_RRE (0x400501A0U) /**< \brief (GMAC) Receive Resource Errors Register */ + #define REG_GMAC_ROE (0x400501A4U) /**< \brief (GMAC) Receive Overrun Register */ + #define REG_GMAC_IHCE (0x400501A8U) /**< \brief (GMAC) IP Header Checksum Errors Register */ + #define REG_GMAC_TCE (0x400501ACU) /**< \brief (GMAC) TCP Checksum Errors Register */ + #define REG_GMAC_UCE (0x400501B0U) /**< \brief (GMAC) UDP Checksum Errors Register */ + #define REG_GMAC_TISUBN (0x400501BCU) /**< \brief (GMAC) 1588 Timer Increment Sub-nanoseconds Register */ + #define REG_GMAC_TSH (0x400501C0U) /**< \brief (GMAC) 1588 Timer Seconds High Register */ + #define REG_GMAC_TSL (0x400501D0U) /**< \brief (GMAC) 1588 Timer Seconds Low Register */ + #define REG_GMAC_TN (0x400501D4U) /**< \brief (GMAC) 1588 Timer Nanoseconds Register */ + #define REG_GMAC_TA (0x400501D8U) /**< \brief (GMAC) 1588 Timer Adjust Register */ + #define REG_GMAC_TI (0x400501DCU) /**< \brief (GMAC) 1588 Timer Increment Register */ + #define REG_GMAC_EFTSL (0x400501E0U) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds Low Register */ + #define REG_GMAC_EFTN (0x400501E4U) /**< \brief (GMAC) PTP Event Frame Transmitted Nanoseconds Register */ + #define REG_GMAC_EFRSL (0x400501E8U) /**< \brief (GMAC) PTP Event Frame Received Seconds Low Register */ + #define REG_GMAC_EFRN (0x400501ECU) /**< \brief (GMAC) PTP Event Frame Received Nanoseconds Register */ + #define REG_GMAC_PEFTSL (0x400501F0U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds Low Register */ + #define REG_GMAC_PEFTN (0x400501F4U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Nanoseconds Register */ + #define REG_GMAC_PEFRSL (0x400501F8U) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds Low Register */ + #define REG_GMAC_PEFRN (0x400501FCU) /**< \brief (GMAC) PTP Peer Event Frame Received Nanoseconds Register */ + #define REG_GMAC_RXLPI (0x40050270U) /**< \brief (GMAC) Received LPI Transitions */ + #define REG_GMAC_RXLPITIME (0x40050274U) /**< \brief (GMAC) Received LPI Time */ + #define REG_GMAC_TXLPI (0x40050278U) /**< \brief (GMAC) Transmit LPI Transitions */ + #define REG_GMAC_TXLPITIME (0x4005027CU) /**< \brief (GMAC) Transmit LPI Time */ + #define REG_GMAC_ISRPQ (0x400503FCU) /**< \brief (GMAC) Interrupt Status Register Priority Queue (index = 1) */ + #define REG_GMAC_TBQBAPQ (0x4005043CU) /**< \brief (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) */ + #define REG_GMAC_RBQBAPQ (0x4005047CU) /**< \brief (GMAC) Receive Buffer Queue Base Address Register Priority Queue (index = 1) */ + #define REG_GMAC_RBSRPQ (0x4005049CU) /**< \brief (GMAC) Receive Buffer Size Register Priority Queue (index = 1) */ + #define REG_GMAC_CBSCR (0x400504BCU) /**< \brief (GMAC) Credit-Based Shaping Control Register */ + #define REG_GMAC_CBSISQA (0x400504C0U) /**< \brief (GMAC) Credit-Based Shaping IdleSlope Register for Queue A */ + #define REG_GMAC_CBSISQB (0x400504C4U) /**< \brief (GMAC) Credit-Based Shaping IdleSlope Register for Queue B */ + #define REG_GMAC_ST1RPQ (0x40050500U) /**< \brief (GMAC) Screening Type 1 Register Priority Queue (index = 0) */ + #define REG_GMAC_ST2RPQ (0x40050540U) /**< \brief (GMAC) Screening Type 2 Register Priority Queue (index = 0) */ + #define REG_GMAC_IERPQ (0x400505FCU) /**< \brief (GMAC) Interrupt Enable Register Priority Queue (index = 1) */ + #define REG_GMAC_IDRPQ (0x4005061CU) /**< \brief (GMAC) Interrupt Disable Register Priority Queue (index = 1) */ + #define REG_GMAC_IMRPQ (0x4005063CU) /**< \brief (GMAC) Interrupt Mask Register Priority Queue (index = 1) */ + #define REG_GMAC_ST2ER (0x400506E0U) /**< \brief (GMAC) Screening Type 2 Ethertype Register (index = 0) */ + #define REG_GMAC_ST2CW00 (0x40050700U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 0) */ + #define REG_GMAC_ST2CW10 (0x40050704U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 0) */ + #define REG_GMAC_ST2CW01 (0x40050708U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 1) */ + #define REG_GMAC_ST2CW11 (0x4005070CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 1) */ + #define REG_GMAC_ST2CW02 (0x40050710U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 2) */ + #define REG_GMAC_ST2CW12 (0x40050714U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 2) */ + #define REG_GMAC_ST2CW03 (0x40050718U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 3) */ + #define REG_GMAC_ST2CW13 (0x4005071CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 3) */ + #define REG_GMAC_ST2CW04 (0x40050720U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 4) */ + #define REG_GMAC_ST2CW14 (0x40050724U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 4) */ + #define REG_GMAC_ST2CW05 (0x40050728U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 5) */ + #define REG_GMAC_ST2CW15 (0x4005072CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 5) */ + #define REG_GMAC_ST2CW06 (0x40050730U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 6) */ + #define REG_GMAC_ST2CW16 (0x40050734U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 6) */ + #define REG_GMAC_ST2CW07 (0x40050738U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 7) */ + #define REG_GMAC_ST2CW17 (0x4005073CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 7) */ + #define REG_GMAC_ST2CW08 (0x40050740U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 8) */ + #define REG_GMAC_ST2CW18 (0x40050744U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 8) */ + #define REG_GMAC_ST2CW09 (0x40050748U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 9) */ + #define REG_GMAC_ST2CW19 (0x4005074CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 9) */ + #define REG_GMAC_ST2CW010 (0x40050750U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 10) */ + #define REG_GMAC_ST2CW110 (0x40050754U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 10) */ + #define REG_GMAC_ST2CW011 (0x40050758U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 11) */ + #define REG_GMAC_ST2CW111 (0x4005075CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 11) */ + #define REG_GMAC_ST2CW012 (0x40050760U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 12) */ + #define REG_GMAC_ST2CW112 (0x40050764U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 12) */ + #define REG_GMAC_ST2CW013 (0x40050768U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 13) */ + #define REG_GMAC_ST2CW113 (0x4005076CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 13) */ + #define REG_GMAC_ST2CW014 (0x40050770U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 14) */ + #define REG_GMAC_ST2CW114 (0x40050774U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 14) */ + #define REG_GMAC_ST2CW015 (0x40050778U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 15) */ + #define REG_GMAC_ST2CW115 (0x4005077CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 15) */ + #define REG_GMAC_ST2CW016 (0x40050780U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 16) */ + #define REG_GMAC_ST2CW116 (0x40050784U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 16) */ + #define REG_GMAC_ST2CW017 (0x40050788U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 17) */ + #define REG_GMAC_ST2CW117 (0x4005078CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 17) */ + #define REG_GMAC_ST2CW018 (0x40050790U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 18) */ + #define REG_GMAC_ST2CW118 (0x40050794U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 18) */ + #define REG_GMAC_ST2CW019 (0x40050798U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 19) */ + #define REG_GMAC_ST2CW119 (0x4005079CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 19) */ + #define REG_GMAC_ST2CW020 (0x400507A0U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 20) */ + #define REG_GMAC_ST2CW120 (0x400507A4U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 20) */ + #define REG_GMAC_ST2CW021 (0x400507A8U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 21) */ + #define REG_GMAC_ST2CW121 (0x400507ACU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 21) */ + #define REG_GMAC_ST2CW022 (0x400507B0U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 22) */ + #define REG_GMAC_ST2CW122 (0x400507B4U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 22) */ + #define REG_GMAC_ST2CW023 (0x400507B8U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 23) */ + #define REG_GMAC_ST2CW123 (0x400507BCU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 23) */ +#else + #define REG_GMAC_NCR (*(__IO uint32_t*)0x40050000U) /**< \brief (GMAC) Network Control Register */ + #define REG_GMAC_NCFGR (*(__IO uint32_t*)0x40050004U) /**< \brief (GMAC) Network Configuration Register */ + #define REG_GMAC_NSR (*(__I uint32_t*)0x40050008U) /**< \brief (GMAC) Network Status Register */ + #define REG_GMAC_UR (*(__IO uint32_t*)0x4005000CU) /**< \brief (GMAC) User Register */ + #define REG_GMAC_DCFGR (*(__IO uint32_t*)0x40050010U) /**< \brief (GMAC) DMA Configuration Register */ + #define REG_GMAC_TSR (*(__IO uint32_t*)0x40050014U) /**< \brief (GMAC) Transmit Status Register */ + #define REG_GMAC_RBQB (*(__IO uint32_t*)0x40050018U) /**< \brief (GMAC) Receive Buffer Queue Base Address Register */ + #define REG_GMAC_TBQB (*(__IO uint32_t*)0x4005001CU) /**< \brief (GMAC) Transmit Buffer Queue Base Address Register */ + #define REG_GMAC_RSR (*(__IO uint32_t*)0x40050020U) /**< \brief (GMAC) Receive Status Register */ + #define REG_GMAC_ISR (*(__I uint32_t*)0x40050024U) /**< \brief (GMAC) Interrupt Status Register */ + #define REG_GMAC_IER (*(__O uint32_t*)0x40050028U) /**< \brief (GMAC) Interrupt Enable Register */ + #define REG_GMAC_IDR (*(__O uint32_t*)0x4005002CU) /**< \brief (GMAC) Interrupt Disable Register */ + #define REG_GMAC_IMR (*(__IO uint32_t*)0x40050030U) /**< \brief (GMAC) Interrupt Mask Register */ + #define REG_GMAC_MAN (*(__IO uint32_t*)0x40050034U) /**< \brief (GMAC) PHY Maintenance Register */ + #define REG_GMAC_RPQ (*(__I uint32_t*)0x40050038U) /**< \brief (GMAC) Received Pause Quantum Register */ + #define REG_GMAC_TPQ (*(__IO uint32_t*)0x4005003CU) /**< \brief (GMAC) Transmit Pause Quantum Register */ + #define REG_GMAC_TPSF (*(__IO uint32_t*)0x40050040U) /**< \brief (GMAC) TX Partial Store and Forward Register */ + #define REG_GMAC_RPSF (*(__IO uint32_t*)0x40050044U) /**< \brief (GMAC) RX Partial Store and Forward Register */ + #define REG_GMAC_RJFML (*(__IO uint32_t*)0x40050048U) /**< \brief (GMAC) RX Jumbo Frame Max Length Register */ + #define REG_GMAC_HRB (*(__IO uint32_t*)0x40050080U) /**< \brief (GMAC) Hash Register Bottom */ + #define REG_GMAC_HRT (*(__IO uint32_t*)0x40050084U) /**< \brief (GMAC) Hash Register Top */ + #define REG_GMAC_SAB1 (*(__IO uint32_t*)0x40050088U) /**< \brief (GMAC) Specific Address 1 Bottom Register */ + #define REG_GMAC_SAT1 (*(__IO uint32_t*)0x4005008CU) /**< \brief (GMAC) Specific Address 1 Top Register */ + #define REG_GMAC_SAB2 (*(__IO uint32_t*)0x40050090U) /**< \brief (GMAC) Specific Address 2 Bottom Register */ + #define REG_GMAC_SAT2 (*(__IO uint32_t*)0x40050094U) /**< \brief (GMAC) Specific Address 2 Top Register */ + #define REG_GMAC_SAB3 (*(__IO uint32_t*)0x40050098U) /**< \brief (GMAC) Specific Address 3 Bottom Register */ + #define REG_GMAC_SAT3 (*(__IO uint32_t*)0x4005009CU) /**< \brief (GMAC) Specific Address 3 Top Register */ + #define REG_GMAC_SAB4 (*(__IO uint32_t*)0x400500A0U) /**< \brief (GMAC) Specific Address 4 Bottom Register */ + #define REG_GMAC_SAT4 (*(__IO uint32_t*)0x400500A4U) /**< \brief (GMAC) Specific Address 4 Top Register */ + #define REG_GMAC_TIDM1 (*(__IO uint32_t*)0x400500A8U) /**< \brief (GMAC) Type ID Match 1 Register */ + #define REG_GMAC_TIDM2 (*(__IO uint32_t*)0x400500ACU) /**< \brief (GMAC) Type ID Match 2 Register */ + #define REG_GMAC_TIDM3 (*(__IO uint32_t*)0x400500B0U) /**< \brief (GMAC) Type ID Match 3 Register */ + #define REG_GMAC_TIDM4 (*(__IO uint32_t*)0x400500B4U) /**< \brief (GMAC) Type ID Match 4 Register */ + #define REG_GMAC_WOL (*(__IO uint32_t*)0x400500B8U) /**< \brief (GMAC) Wake on LAN Register */ + #define REG_GMAC_IPGS (*(__IO uint32_t*)0x400500BCU) /**< \brief (GMAC) IPG Stretch Register */ + #define REG_GMAC_SVLAN (*(__IO uint32_t*)0x400500C0U) /**< \brief (GMAC) Stacked VLAN Register */ + #define REG_GMAC_TPFCP (*(__IO uint32_t*)0x400500C4U) /**< \brief (GMAC) Transmit PFC Pause Register */ + #define REG_GMAC_SAMB1 (*(__IO uint32_t*)0x400500C8U) /**< \brief (GMAC) Specific Address 1 Mask Bottom Register */ + #define REG_GMAC_SAMT1 (*(__IO uint32_t*)0x400500CCU) /**< \brief (GMAC) Specific Address 1 Mask Top Register */ + #define REG_GMAC_NSC (*(__IO uint32_t*)0x400500DCU) /**< \brief (GMAC) 1588 Timer Nanosecond Comparison Register */ + #define REG_GMAC_SCL (*(__IO uint32_t*)0x400500E0U) /**< \brief (GMAC) 1588 Timer Second Comparison Low Register */ + #define REG_GMAC_SCH (*(__IO uint32_t*)0x400500E4U) /**< \brief (GMAC) 1588 Timer Second Comparison High Register */ + #define REG_GMAC_EFTSH (*(__I uint32_t*)0x400500E8U) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds High Register */ + #define REG_GMAC_EFRSH (*(__I uint32_t*)0x400500ECU) /**< \brief (GMAC) PTP Event Frame Received Seconds High Register */ + #define REG_GMAC_PEFTSH (*(__I uint32_t*)0x400500F0U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds High Register */ + #define REG_GMAC_PEFRSH (*(__I uint32_t*)0x400500F4U) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds High Register */ + #define REG_GMAC_MID (*(__I uint32_t*)0x400500FCU) /**< \brief (GMAC) Module ID Register */ + #define REG_GMAC_OTLO (*(__I uint32_t*)0x40050100U) /**< \brief (GMAC) Octets Transmitted Low Register */ + #define REG_GMAC_OTHI (*(__I uint32_t*)0x40050104U) /**< \brief (GMAC) Octets Transmitted High Register */ + #define REG_GMAC_FT (*(__I uint32_t*)0x40050108U) /**< \brief (GMAC) Frames Transmitted Register */ + #define REG_GMAC_BCFT (*(__I uint32_t*)0x4005010CU) /**< \brief (GMAC) Broadcast Frames Transmitted Register */ + #define REG_GMAC_MFT (*(__I uint32_t*)0x40050110U) /**< \brief (GMAC) Multicast Frames Transmitted Register */ + #define REG_GMAC_PFT (*(__I uint32_t*)0x40050114U) /**< \brief (GMAC) Pause Frames Transmitted Register */ + #define REG_GMAC_BFT64 (*(__I uint32_t*)0x40050118U) /**< \brief (GMAC) 64 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT127 (*(__I uint32_t*)0x4005011CU) /**< \brief (GMAC) 65 to 127 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT255 (*(__I uint32_t*)0x40050120U) /**< \brief (GMAC) 128 to 255 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT511 (*(__I uint32_t*)0x40050124U) /**< \brief (GMAC) 256 to 511 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT1023 (*(__I uint32_t*)0x40050128U) /**< \brief (GMAC) 512 to 1023 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT1518 (*(__I uint32_t*)0x4005012CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Transmitted Register */ + #define REG_GMAC_GTBFT1518 (*(__I uint32_t*)0x40050130U) /**< \brief (GMAC) Greater Than 1518 Byte Frames Transmitted Register */ + #define REG_GMAC_TUR (*(__I uint32_t*)0x40050134U) /**< \brief (GMAC) Transmit Underruns Register */ + #define REG_GMAC_SCF (*(__I uint32_t*)0x40050138U) /**< \brief (GMAC) Single Collision Frames Register */ + #define REG_GMAC_MCF (*(__I uint32_t*)0x4005013CU) /**< \brief (GMAC) Multiple Collision Frames Register */ + #define REG_GMAC_EC (*(__I uint32_t*)0x40050140U) /**< \brief (GMAC) Excessive Collisions Register */ + #define REG_GMAC_LC (*(__I uint32_t*)0x40050144U) /**< \brief (GMAC) Late Collisions Register */ + #define REG_GMAC_DTF (*(__I uint32_t*)0x40050148U) /**< \brief (GMAC) Deferred Transmission Frames Register */ + #define REG_GMAC_CSE (*(__I uint32_t*)0x4005014CU) /**< \brief (GMAC) Carrier Sense Errors Register */ + #define REG_GMAC_ORLO (*(__I uint32_t*)0x40050150U) /**< \brief (GMAC) Octets Received Low Received Register */ + #define REG_GMAC_ORHI (*(__I uint32_t*)0x40050154U) /**< \brief (GMAC) Octets Received High Received Register */ + #define REG_GMAC_FR (*(__I uint32_t*)0x40050158U) /**< \brief (GMAC) Frames Received Register */ + #define REG_GMAC_BCFR (*(__I uint32_t*)0x4005015CU) /**< \brief (GMAC) Broadcast Frames Received Register */ + #define REG_GMAC_MFR (*(__I uint32_t*)0x40050160U) /**< \brief (GMAC) Multicast Frames Received Register */ + #define REG_GMAC_PFR (*(__I uint32_t*)0x40050164U) /**< \brief (GMAC) Pause Frames Received Register */ + #define REG_GMAC_BFR64 (*(__I uint32_t*)0x40050168U) /**< \brief (GMAC) 64 Byte Frames Received Register */ + #define REG_GMAC_TBFR127 (*(__I uint32_t*)0x4005016CU) /**< \brief (GMAC) 65 to 127 Byte Frames Received Register */ + #define REG_GMAC_TBFR255 (*(__I uint32_t*)0x40050170U) /**< \brief (GMAC) 128 to 255 Byte Frames Received Register */ + #define REG_GMAC_TBFR511 (*(__I uint32_t*)0x40050174U) /**< \brief (GMAC) 256 to 511 Byte Frames Received Register */ + #define REG_GMAC_TBFR1023 (*(__I uint32_t*)0x40050178U) /**< \brief (GMAC) 512 to 1023 Byte Frames Received Register */ + #define REG_GMAC_TBFR1518 (*(__I uint32_t*)0x4005017CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Received Register */ + #define REG_GMAC_TMXBFR (*(__I uint32_t*)0x40050180U) /**< \brief (GMAC) 1519 to Maximum Byte Frames Received Register */ + #define REG_GMAC_UFR (*(__I uint32_t*)0x40050184U) /**< \brief (GMAC) Undersize Frames Received Register */ + #define REG_GMAC_OFR (*(__I uint32_t*)0x40050188U) /**< \brief (GMAC) Oversize Frames Received Register */ + #define REG_GMAC_JR (*(__I uint32_t*)0x4005018CU) /**< \brief (GMAC) Jabbers Received Register */ + #define REG_GMAC_FCSE (*(__I uint32_t*)0x40050190U) /**< \brief (GMAC) Frame Check Sequence Errors Register */ + #define REG_GMAC_LFFE (*(__I uint32_t*)0x40050194U) /**< \brief (GMAC) Length Field Frame Errors Register */ + #define REG_GMAC_RSE (*(__I uint32_t*)0x40050198U) /**< \brief (GMAC) Receive Symbol Errors Register */ + #define REG_GMAC_AE (*(__I uint32_t*)0x4005019CU) /**< \brief (GMAC) Alignment Errors Register */ + #define REG_GMAC_RRE (*(__I uint32_t*)0x400501A0U) /**< \brief (GMAC) Receive Resource Errors Register */ + #define REG_GMAC_ROE (*(__I uint32_t*)0x400501A4U) /**< \brief (GMAC) Receive Overrun Register */ + #define REG_GMAC_IHCE (*(__I uint32_t*)0x400501A8U) /**< \brief (GMAC) IP Header Checksum Errors Register */ + #define REG_GMAC_TCE (*(__I uint32_t*)0x400501ACU) /**< \brief (GMAC) TCP Checksum Errors Register */ + #define REG_GMAC_UCE (*(__I uint32_t*)0x400501B0U) /**< \brief (GMAC) UDP Checksum Errors Register */ + #define REG_GMAC_TISUBN (*(__IO uint32_t*)0x400501BCU) /**< \brief (GMAC) 1588 Timer Increment Sub-nanoseconds Register */ + #define REG_GMAC_TSH (*(__IO uint32_t*)0x400501C0U) /**< \brief (GMAC) 1588 Timer Seconds High Register */ + #define REG_GMAC_TSL (*(__IO uint32_t*)0x400501D0U) /**< \brief (GMAC) 1588 Timer Seconds Low Register */ + #define REG_GMAC_TN (*(__IO uint32_t*)0x400501D4U) /**< \brief (GMAC) 1588 Timer Nanoseconds Register */ + #define REG_GMAC_TA (*(__O uint32_t*)0x400501D8U) /**< \brief (GMAC) 1588 Timer Adjust Register */ + #define REG_GMAC_TI (*(__IO uint32_t*)0x400501DCU) /**< \brief (GMAC) 1588 Timer Increment Register */ + #define REG_GMAC_EFTSL (*(__I uint32_t*)0x400501E0U) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds Low Register */ + #define REG_GMAC_EFTN (*(__I uint32_t*)0x400501E4U) /**< \brief (GMAC) PTP Event Frame Transmitted Nanoseconds Register */ + #define REG_GMAC_EFRSL (*(__I uint32_t*)0x400501E8U) /**< \brief (GMAC) PTP Event Frame Received Seconds Low Register */ + #define REG_GMAC_EFRN (*(__I uint32_t*)0x400501ECU) /**< \brief (GMAC) PTP Event Frame Received Nanoseconds Register */ + #define REG_GMAC_PEFTSL (*(__I uint32_t*)0x400501F0U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds Low Register */ + #define REG_GMAC_PEFTN (*(__I uint32_t*)0x400501F4U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Nanoseconds Register */ + #define REG_GMAC_PEFRSL (*(__I uint32_t*)0x400501F8U) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds Low Register */ + #define REG_GMAC_PEFRN (*(__I uint32_t*)0x400501FCU) /**< \brief (GMAC) PTP Peer Event Frame Received Nanoseconds Register */ + #define REG_GMAC_RXLPI (*(__I uint32_t*)0x40050270U) /**< \brief (GMAC) Received LPI Transitions */ + #define REG_GMAC_RXLPITIME (*(__I uint32_t*)0x40050274U) /**< \brief (GMAC) Received LPI Time */ + #define REG_GMAC_TXLPI (*(__I uint32_t*)0x40050278U) /**< \brief (GMAC) Transmit LPI Transitions */ + #define REG_GMAC_TXLPITIME (*(__I uint32_t*)0x4005027CU) /**< \brief (GMAC) Transmit LPI Time */ + #define REG_GMAC_ISRPQ (*(__I uint32_t*)0x400503FCU) /**< \brief (GMAC) Interrupt Status Register Priority Queue (index = 1) 0 */ + #define REG_GMAC_TBQBAPQ (*(__IO uint32_t*)0x4005043CU) /**< \brief (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) */ + #define REG_GMAC_RBQBAPQ (*(__IO uint32_t*)0x4005047CU) /**< \brief (GMAC) Receive Buffer Queue Base Address Register Priority Queue (index = 1) */ + #define REG_GMAC_RBSRPQ (*(__IO uint32_t*)0x4005049CU) /**< \brief (GMAC) Receive Buffer Size Register Priority Queue (index = 1) */ + #define REG_GMAC_CBSCR (*(__IO uint32_t*)0x400504BCU) /**< \brief (GMAC) Credit-Based Shaping Control Register */ + #define REG_GMAC_CBSISQA (*(__IO uint32_t*)0x400504C0U) /**< \brief (GMAC) Credit-Based Shaping IdleSlope Register for Queue A */ + #define REG_GMAC_CBSISQB (*(__IO uint32_t*)0x400504C4U) /**< \brief (GMAC) Credit-Based Shaping IdleSlope Register for Queue B */ + #define REG_GMAC_ST1RPQ (*(__IO uint32_t*)0x40050500U) /**< \brief (GMAC) Screening Type 1 Register Priority Queue (index = 0) */ + #define REG_GMAC_ST2RPQ (*(__IO uint32_t*)0x40050540U) /**< \brief (GMAC) Screening Type 2 Register Priority Queue (index = 0) */ + #define REG_GMAC_IERPQ (*(__O uint32_t*)0x400505FCU) /**< \brief (GMAC) Interrupt Enable Register Priority Queue (index = 1) */ + #define REG_GMAC_IDRPQ (*(__O uint32_t*)0x4005061CU) /**< \brief (GMAC) Interrupt Disable Register Priority Queue (index = 1) */ + #define REG_GMAC_IMRPQ (*(__IO uint32_t*)0x4005063CU) /**< \brief (GMAC) Interrupt Mask Register Priority Queue (index = 1) */ + #define REG_GMAC_ST2ER (*(__IO uint32_t*)0x400506E0U) /**< \brief (GMAC) Screening Type 2 Ethertype Register (index = 0) */ + #define REG_GMAC_ST2CW00 (*(__IO uint32_t*)0x40050700U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 0) */ + #define REG_GMAC_ST2CW10 (*(__IO uint32_t*)0x40050704U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 0) */ + #define REG_GMAC_ST2CW01 (*(__IO uint32_t*)0x40050708U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 1) */ + #define REG_GMAC_ST2CW11 (*(__IO uint32_t*)0x4005070CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 1) */ + #define REG_GMAC_ST2CW02 (*(__IO uint32_t*)0x40050710U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 2) */ + #define REG_GMAC_ST2CW12 (*(__IO uint32_t*)0x40050714U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 2) */ + #define REG_GMAC_ST2CW03 (*(__IO uint32_t*)0x40050718U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 3) */ + #define REG_GMAC_ST2CW13 (*(__IO uint32_t*)0x4005071CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 3) */ + #define REG_GMAC_ST2CW04 (*(__IO uint32_t*)0x40050720U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 4) */ + #define REG_GMAC_ST2CW14 (*(__IO uint32_t*)0x40050724U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 4) */ + #define REG_GMAC_ST2CW05 (*(__IO uint32_t*)0x40050728U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 5) */ + #define REG_GMAC_ST2CW15 (*(__IO uint32_t*)0x4005072CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 5) */ + #define REG_GMAC_ST2CW06 (*(__IO uint32_t*)0x40050730U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 6) */ + #define REG_GMAC_ST2CW16 (*(__IO uint32_t*)0x40050734U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 6) */ + #define REG_GMAC_ST2CW07 (*(__IO uint32_t*)0x40050738U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 7) */ + #define REG_GMAC_ST2CW17 (*(__IO uint32_t*)0x4005073CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 7) */ + #define REG_GMAC_ST2CW08 (*(__IO uint32_t*)0x40050740U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 8) */ + #define REG_GMAC_ST2CW18 (*(__IO uint32_t*)0x40050744U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 8) */ + #define REG_GMAC_ST2CW09 (*(__IO uint32_t*)0x40050748U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 9) */ + #define REG_GMAC_ST2CW19 (*(__IO uint32_t*)0x4005074CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 9) */ + #define REG_GMAC_ST2CW010 (*(__IO uint32_t*)0x40050750U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 10) */ + #define REG_GMAC_ST2CW110 (*(__IO uint32_t*)0x40050754U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 10) */ + #define REG_GMAC_ST2CW011 (*(__IO uint32_t*)0x40050758U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 11) */ + #define REG_GMAC_ST2CW111 (*(__IO uint32_t*)0x4005075CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 11) */ + #define REG_GMAC_ST2CW012 (*(__IO uint32_t*)0x40050760U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 12) */ + #define REG_GMAC_ST2CW112 (*(__IO uint32_t*)0x40050764U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 12) */ + #define REG_GMAC_ST2CW013 (*(__IO uint32_t*)0x40050768U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 13) */ + #define REG_GMAC_ST2CW113 (*(__IO uint32_t*)0x4005076CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 13) */ + #define REG_GMAC_ST2CW014 (*(__IO uint32_t*)0x40050770U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 14) */ + #define REG_GMAC_ST2CW114 (*(__IO uint32_t*)0x40050774U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 14) */ + #define REG_GMAC_ST2CW015 (*(__IO uint32_t*)0x40050778U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 15) */ + #define REG_GMAC_ST2CW115 (*(__IO uint32_t*)0x4005077CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 15) */ + #define REG_GMAC_ST2CW016 (*(__IO uint32_t*)0x40050780U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 16) */ + #define REG_GMAC_ST2CW116 (*(__IO uint32_t*)0x40050784U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 16) */ + #define REG_GMAC_ST2CW017 (*(__IO uint32_t*)0x40050788U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 17) */ + #define REG_GMAC_ST2CW117 (*(__IO uint32_t*)0x4005078CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 17) */ + #define REG_GMAC_ST2CW018 (*(__IO uint32_t*)0x40050790U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 18) */ + #define REG_GMAC_ST2CW118 (*(__IO uint32_t*)0x40050794U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 18) */ + #define REG_GMAC_ST2CW019 (*(__IO uint32_t*)0x40050798U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 19) */ + #define REG_GMAC_ST2CW119 (*(__IO uint32_t*)0x4005079CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 19) */ + #define REG_GMAC_ST2CW020 (*(__IO uint32_t*)0x400507A0U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 20) */ + #define REG_GMAC_ST2CW120 (*(__IO uint32_t*)0x400507A4U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 20) */ + #define REG_GMAC_ST2CW021 (*(__IO uint32_t*)0x400507A8U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 21) */ + #define REG_GMAC_ST2CW121 (*(__IO uint32_t*)0x400507ACU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 21) */ + #define REG_GMAC_ST2CW022 (*(__IO uint32_t*)0x400507B0U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 22) */ + #define REG_GMAC_ST2CW122 (*(__IO uint32_t*)0x400507B4U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 22) */ + #define REG_GMAC_ST2CW023 (*(__IO uint32_t*)0x400507B8U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 23) */ + #define REG_GMAC_ST2CW123 (*(__IO uint32_t*)0x400507BCU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 23) */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_GMAC_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/gpbr.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/gpbr.h new file mode 100644 index 000000000..5ac6c8a91 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/gpbr.h @@ -0,0 +1,45 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_GPBR_INSTANCE_ +#define _SAME70_GPBR_INSTANCE_ + +/* ========== Register definition for GPBR peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_GPBR_GPBR (0x400E1890U) /**< \brief (GPBR) General Purpose Backup Register */ +#else + #define REG_GPBR_GPBR (*(__IO uint32_t*)0x400E1890U) /**< \brief (GPBR) General Purpose Backup Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_GPBR_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/hsmci.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/hsmci.h new file mode 100644 index 000000000..f52aeab27 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/hsmci.h @@ -0,0 +1,85 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_HSMCI_INSTANCE_ +#define _SAME70_HSMCI_INSTANCE_ + +/* ========== Register definition for HSMCI peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_HSMCI_CR (0x40000000U) /**< \brief (HSMCI) Control Register */ + #define REG_HSMCI_MR (0x40000004U) /**< \brief (HSMCI) Mode Register */ + #define REG_HSMCI_DTOR (0x40000008U) /**< \brief (HSMCI) Data Timeout Register */ + #define REG_HSMCI_SDCR (0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */ + #define REG_HSMCI_ARGR (0x40000010U) /**< \brief (HSMCI) Argument Register */ + #define REG_HSMCI_CMDR (0x40000014U) /**< \brief (HSMCI) Command Register */ + #define REG_HSMCI_BLKR (0x40000018U) /**< \brief (HSMCI) Block Register */ + #define REG_HSMCI_CSTOR (0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */ + #define REG_HSMCI_RSPR (0x40000020U) /**< \brief (HSMCI) Response Register */ + #define REG_HSMCI_RDR (0x40000030U) /**< \brief (HSMCI) Receive Data Register */ + #define REG_HSMCI_TDR (0x40000034U) /**< \brief (HSMCI) Transmit Data Register */ + #define REG_HSMCI_SR (0x40000040U) /**< \brief (HSMCI) Status Register */ + #define REG_HSMCI_IER (0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */ + #define REG_HSMCI_IDR (0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */ + #define REG_HSMCI_IMR (0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */ + #define REG_HSMCI_DMA (0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */ + #define REG_HSMCI_CFG (0x40000054U) /**< \brief (HSMCI) Configuration Register */ + #define REG_HSMCI_WPMR (0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */ + #define REG_HSMCI_WPSR (0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */ + #define REG_HSMCI_VERSION (0x400000FCU) /**< \brief (HSMCI) Version Register */ + #define REG_HSMCI_FIFO (0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */ +#else + #define REG_HSMCI_CR (*(__O uint32_t*)0x40000000U) /**< \brief (HSMCI) Control Register */ + #define REG_HSMCI_MR (*(__IO uint32_t*)0x40000004U) /**< \brief (HSMCI) Mode Register */ + #define REG_HSMCI_DTOR (*(__IO uint32_t*)0x40000008U) /**< \brief (HSMCI) Data Timeout Register */ + #define REG_HSMCI_SDCR (*(__IO uint32_t*)0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */ + #define REG_HSMCI_ARGR (*(__IO uint32_t*)0x40000010U) /**< \brief (HSMCI) Argument Register */ + #define REG_HSMCI_CMDR (*(__O uint32_t*)0x40000014U) /**< \brief (HSMCI) Command Register */ + #define REG_HSMCI_BLKR (*(__IO uint32_t*)0x40000018U) /**< \brief (HSMCI) Block Register */ + #define REG_HSMCI_CSTOR (*(__IO uint32_t*)0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */ + #define REG_HSMCI_RSPR (*(__I uint32_t*)0x40000020U) /**< \brief (HSMCI) Response Register */ + #define REG_HSMCI_RDR (*(__I uint32_t*)0x40000030U) /**< \brief (HSMCI) Receive Data Register */ + #define REG_HSMCI_TDR (*(__O uint32_t*)0x40000034U) /**< \brief (HSMCI) Transmit Data Register */ + #define REG_HSMCI_SR (*(__I uint32_t*)0x40000040U) /**< \brief (HSMCI) Status Register */ + #define REG_HSMCI_IER (*(__O uint32_t*)0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */ + #define REG_HSMCI_IDR (*(__O uint32_t*)0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */ + #define REG_HSMCI_IMR (*(__I uint32_t*)0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */ + #define REG_HSMCI_DMA (*(__IO uint32_t*)0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */ + #define REG_HSMCI_CFG (*(__IO uint32_t*)0x40000054U) /**< \brief (HSMCI) Configuration Register */ + #define REG_HSMCI_WPMR (*(__IO uint32_t*)0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */ + #define REG_HSMCI_WPSR (*(__I uint32_t*)0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */ + #define REG_HSMCI_VERSION (*(__I uint32_t*)0x400000FCU) /**< \brief (HSMCI) Version Register */ + #define REG_HSMCI_FIFO (*(__IO uint32_t*)0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_HSMCI_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/i2sc0.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/i2sc0.h new file mode 100644 index 000000000..3f12dac61 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/i2sc0.h @@ -0,0 +1,65 @@ +/** + * \file + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_I2SC0_INSTANCE_ +#define _SAME70_I2SC0_INSTANCE_ + +/* ========== Register definition for I2SC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_I2SC0_CR (0x4008C000U) /**< \brief (I2SC0) Control Register */ + #define REG_I2SC0_MR (0x4008C004U) /**< \brief (I2SC0) Mode Register */ + #define REG_I2SC0_SR (0x4008C008U) /**< \brief (I2SC0) Status Register */ + #define REG_I2SC0_SCR (0x4008C00CU) /**< \brief (I2SC0) Status Clear Register */ + #define REG_I2SC0_SSR (0x4008C010U) /**< \brief (I2SC0) Status Set Register */ + #define REG_I2SC0_IER (0x4008C014U) /**< \brief (I2SC0) Interrupt Enable Register */ + #define REG_I2SC0_IDR (0x4008C018U) /**< \brief (I2SC0) Interrupt Disable Register */ + #define REG_I2SC0_IMR (0x4008C01CU) /**< \brief (I2SC0) Interrupt Mask Register */ + #define REG_I2SC0_RHR (0x4008C020U) /**< \brief (I2SC0) Receiver Holding Register */ + #define REG_I2SC0_THR (0x4008C024U) /**< \brief (I2SC0) Transmitter Holding Register */ + #define REG_I2SC0_VERSION (0x4008C028U) /**< \brief (I2SC0) Version Register */ +#else + #define REG_I2SC0_CR (*(__O uint32_t*)0x4008C000U) /**< \brief (I2SC0) Control Register */ + #define REG_I2SC0_MR (*(__IO uint32_t*)0x4008C004U) /**< \brief (I2SC0) Mode Register */ + #define REG_I2SC0_SR (*(__I uint32_t*)0x4008C008U) /**< \brief (I2SC0) Status Register */ + #define REG_I2SC0_SCR (*(__O uint32_t*)0x4008C00CU) /**< \brief (I2SC0) Status Clear Register */ + #define REG_I2SC0_SSR (*(__O uint32_t*)0x4008C010U) /**< \brief (I2SC0) Status Set Register */ + #define REG_I2SC0_IER (*(__O uint32_t*)0x4008C014U) /**< \brief (I2SC0) Interrupt Enable Register */ + #define REG_I2SC0_IDR (*(__O uint32_t*)0x4008C018U) /**< \brief (I2SC0) Interrupt Disable Register */ + #define REG_I2SC0_IMR (*(__I uint32_t*)0x4008C01CU) /**< \brief (I2SC0) Interrupt Mask Register */ + #define REG_I2SC0_RHR (*(__I uint32_t*)0x4008C020U) /**< \brief (I2SC0) Receiver Holding Register */ + #define REG_I2SC0_THR (*(__O uint32_t*)0x4008C024U) /**< \brief (I2SC0) Transmitter Holding Register */ + #define REG_I2SC0_VERSION (*(__I uint32_t*)0x4008C028U) /**< \brief (I2SC0) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_I2SC0_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/i2sc1.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/i2sc1.h new file mode 100644 index 000000000..32d403b54 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/i2sc1.h @@ -0,0 +1,65 @@ +/** + * \file + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_I2SC1_INSTANCE_ +#define _SAME70_I2SC1_INSTANCE_ + +/* ========== Register definition for I2SC1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_I2SC1_CR (0x40090000U) /**< \brief (I2SC1) Control Register */ + #define REG_I2SC1_MR (0x40090004U) /**< \brief (I2SC1) Mode Register */ + #define REG_I2SC1_SR (0x40090008U) /**< \brief (I2SC1) Status Register */ + #define REG_I2SC1_SCR (0x4009000CU) /**< \brief (I2SC1) Status Clear Register */ + #define REG_I2SC1_SSR (0x40090010U) /**< \brief (I2SC1) Status Set Register */ + #define REG_I2SC1_IER (0x40090014U) /**< \brief (I2SC1) Interrupt Enable Register */ + #define REG_I2SC1_IDR (0x40090018U) /**< \brief (I2SC1) Interrupt Disable Register */ + #define REG_I2SC1_IMR (0x4009001CU) /**< \brief (I2SC1) Interrupt Mask Register */ + #define REG_I2SC1_RHR (0x40090020U) /**< \brief (I2SC1) Receiver Holding Register */ + #define REG_I2SC1_THR (0x40090024U) /**< \brief (I2SC1) Transmitter Holding Register */ + #define REG_I2SC1_VERSION (0x40090028U) /**< \brief (I2SC1) Version Register */ +#else + #define REG_I2SC1_CR (*(__O uint32_t*)0x40090000U) /**< \brief (I2SC1) Control Register */ + #define REG_I2SC1_MR (*(__IO uint32_t*)0x40090004U) /**< \brief (I2SC1) Mode Register */ + #define REG_I2SC1_SR (*(__I uint32_t*)0x40090008U) /**< \brief (I2SC1) Status Register */ + #define REG_I2SC1_SCR (*(__O uint32_t*)0x4009000CU) /**< \brief (I2SC1) Status Clear Register */ + #define REG_I2SC1_SSR (*(__O uint32_t*)0x40090010U) /**< \brief (I2SC1) Status Set Register */ + #define REG_I2SC1_IER (*(__O uint32_t*)0x40090014U) /**< \brief (I2SC1) Interrupt Enable Register */ + #define REG_I2SC1_IDR (*(__O uint32_t*)0x40090018U) /**< \brief (I2SC1) Interrupt Disable Register */ + #define REG_I2SC1_IMR (*(__I uint32_t*)0x4009001CU) /**< \brief (I2SC1) Interrupt Mask Register */ + #define REG_I2SC1_RHR (*(__I uint32_t*)0x40090020U) /**< \brief (I2SC1) Receiver Holding Register */ + #define REG_I2SC1_THR (*(__O uint32_t*)0x40090024U) /**< \brief (I2SC1) Transmitter Holding Register */ + #define REG_I2SC1_VERSION (*(__I uint32_t*)0x40090028U) /**< \brief (I2SC1) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_I2SC1_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/icm.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/icm.h new file mode 100644 index 000000000..7225400a0 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/icm.h @@ -0,0 +1,73 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_ICM_INSTANCE_ +#define _SAME70_ICM_INSTANCE_ + +/* ========== Register definition for ICM peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_ICM_CFG (0x40048000U) /**< \brief (ICM) Configuration Register */ + #define REG_ICM_CTRL (0x40048004U) /**< \brief (ICM) Control Register */ + #define REG_ICM_SR (0x40048008U) /**< \brief (ICM) Status Register */ + #define REG_ICM_IER (0x40048010U) /**< \brief (ICM) Interrupt Enable Register */ + #define REG_ICM_IDR (0x40048014U) /**< \brief (ICM) Interrupt Disable Register */ + #define REG_ICM_IMR (0x40048018U) /**< \brief (ICM) Interrupt Mask Register */ + #define REG_ICM_ISR (0x4004801CU) /**< \brief (ICM) Interrupt Status Register */ + #define REG_ICM_UASR (0x40048020U) /**< \brief (ICM) Undefined Access Status Register */ + #define REG_ICM_DSCR (0x40048030U) /**< \brief (ICM) Region Descriptor Area Start Address Register */ + #define REG_ICM_HASH (0x40048034U) /**< \brief (ICM) Region Hash Area Start Address Register */ + #define REG_ICM_UIHVAL (0x40048038U) /**< \brief (ICM) User Initial Hash Value 0 Register */ + #define REG_ICM_ADDRSIZE (0x400480ECU) /**< \brief (ICM) Address Size Register */ + #define REG_ICM_IPNAME (0x400480F0U) /**< \brief (ICM) IP Name 1 Register */ + #define REG_ICM_FEATURES (0x400480F8U) /**< \brief (ICM) Feature Register */ + #define REG_ICM_VERSION (0x400480FCU) /**< \brief (ICM) Version Register */ +#else + #define REG_ICM_CFG (*(__IO uint32_t*)0x40048000U) /**< \brief (ICM) Configuration Register */ + #define REG_ICM_CTRL (*(__O uint32_t*)0x40048004U) /**< \brief (ICM) Control Register */ + #define REG_ICM_SR (*(__I uint32_t*)0x40048008U) /**< \brief (ICM) Status Register */ + #define REG_ICM_IER (*(__O uint32_t*)0x40048010U) /**< \brief (ICM) Interrupt Enable Register */ + #define REG_ICM_IDR (*(__O uint32_t*)0x40048014U) /**< \brief (ICM) Interrupt Disable Register */ + #define REG_ICM_IMR (*(__I uint32_t*)0x40048018U) /**< \brief (ICM) Interrupt Mask Register */ + #define REG_ICM_ISR (*(__I uint32_t*)0x4004801CU) /**< \brief (ICM) Interrupt Status Register */ + #define REG_ICM_UASR (*(__I uint32_t*)0x40048020U) /**< \brief (ICM) Undefined Access Status Register */ + #define REG_ICM_DSCR (*(__IO uint32_t*)0x40048030U) /**< \brief (ICM) Region Descriptor Area Start Address Register */ + #define REG_ICM_HASH (*(__IO uint32_t*)0x40048034U) /**< \brief (ICM) Region Hash Area Start Address Register */ + #define REG_ICM_UIHVAL (*(__O uint32_t*)0x40048038U) /**< \brief (ICM) User Initial Hash Value 0 Register */ + #define REG_ICM_ADDRSIZE (*(__I uint32_t*)0x400480ECU) /**< \brief (ICM) Address Size Register */ + #define REG_ICM_IPNAME (*(__I uint32_t*)0x400480F0U) /**< \brief (ICM) IP Name 1 Register */ + #define REG_ICM_FEATURES (*(__I uint32_t*)0x400480F8U) /**< \brief (ICM) Feature Register */ + #define REG_ICM_VERSION (*(__I uint32_t*)0x400480FCU) /**< \brief (ICM) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_ICM_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/isi.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/isi.h new file mode 100644 index 000000000..e35ba5d01 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/isi.h @@ -0,0 +1,95 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_ISI_INSTANCE_ +#define _SAME70_ISI_INSTANCE_ + +/* ========== Register definition for ISI peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_ISI_CFG1 (0x4004C000U) /**< \brief (ISI) ISI Configuration 1 Register */ + #define REG_ISI_CFG2 (0x4004C004U) /**< \brief (ISI) ISI Configuration 2 Register */ + #define REG_ISI_PSIZE (0x4004C008U) /**< \brief (ISI) ISI Preview Size Register */ + #define REG_ISI_PDECF (0x4004C00CU) /**< \brief (ISI) ISI Preview Decimation Factor Register */ + #define REG_ISI_Y2R_SET0 (0x4004C010U) /**< \brief (ISI) ISI Color Space Conversion YCrCb To RGB Set 0 Register */ + #define REG_ISI_Y2R_SET1 (0x4004C014U) /**< \brief (ISI) ISI Color Space Conversion YCrCb To RGB Set 1 Register */ + #define REG_ISI_R2Y_SET0 (0x4004C018U) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 0 Register */ + #define REG_ISI_R2Y_SET1 (0x4004C01CU) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 1 Register */ + #define REG_ISI_R2Y_SET2 (0x4004C020U) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 2 Register */ + #define REG_ISI_CR (0x4004C024U) /**< \brief (ISI) ISI Control Register */ + #define REG_ISI_SR (0x4004C028U) /**< \brief (ISI) ISI Status Register */ + #define REG_ISI_IER (0x4004C02CU) /**< \brief (ISI) ISI Interrupt Enable Register */ + #define REG_ISI_IDR (0x4004C030U) /**< \brief (ISI) ISI Interrupt Disable Register */ + #define REG_ISI_IMR (0x4004C034U) /**< \brief (ISI) ISI Interrupt Mask Register */ + #define REG_ISI_DMA_CHER (0x4004C038U) /**< \brief (ISI) DMA Channel Enable Register */ + #define REG_ISI_DMA_CHDR (0x4004C03CU) /**< \brief (ISI) DMA Channel Disable Register */ + #define REG_ISI_DMA_CHSR (0x4004C040U) /**< \brief (ISI) DMA Channel Status Register */ + #define REG_ISI_DMA_P_ADDR (0x4004C044U) /**< \brief (ISI) DMA Preview Base Address Register */ + #define REG_ISI_DMA_P_CTRL (0x4004C048U) /**< \brief (ISI) DMA Preview Control Register */ + #define REG_ISI_DMA_P_DSCR (0x4004C04CU) /**< \brief (ISI) DMA Preview Descriptor Address Register */ + #define REG_ISI_DMA_C_ADDR (0x4004C050U) /**< \brief (ISI) DMA Codec Base Address Register */ + #define REG_ISI_DMA_C_CTRL (0x4004C054U) /**< \brief (ISI) DMA Codec Control Register */ + #define REG_ISI_DMA_C_DSCR (0x4004C058U) /**< \brief (ISI) DMA Codec Descriptor Address Register */ + #define REG_ISI_WPMR (0x4004C0E4U) /**< \brief (ISI) Write Protection Mode Register */ + #define REG_ISI_WPSR (0x4004C0E8U) /**< \brief (ISI) Write Protection Status Register */ + #define REG_ISI_VERSION (0x4004C0FCU) /**< \brief (ISI) Version Register */ +#else + #define REG_ISI_CFG1 (*(__IO uint32_t*)0x4004C000U) /**< \brief (ISI) ISI Configuration 1 Register */ + #define REG_ISI_CFG2 (*(__IO uint32_t*)0x4004C004U) /**< \brief (ISI) ISI Configuration 2 Register */ + #define REG_ISI_PSIZE (*(__IO uint32_t*)0x4004C008U) /**< \brief (ISI) ISI Preview Size Register */ + #define REG_ISI_PDECF (*(__IO uint32_t*)0x4004C00CU) /**< \brief (ISI) ISI Preview Decimation Factor Register */ + #define REG_ISI_Y2R_SET0 (*(__IO uint32_t*)0x4004C010U) /**< \brief (ISI) ISI Color Space Conversion YCrCb To RGB Set 0 Register */ + #define REG_ISI_Y2R_SET1 (*(__IO uint32_t*)0x4004C014U) /**< \brief (ISI) ISI Color Space Conversion YCrCb To RGB Set 1 Register */ + #define REG_ISI_R2Y_SET0 (*(__IO uint32_t*)0x4004C018U) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 0 Register */ + #define REG_ISI_R2Y_SET1 (*(__IO uint32_t*)0x4004C01CU) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 1 Register */ + #define REG_ISI_R2Y_SET2 (*(__IO uint32_t*)0x4004C020U) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 2 Register */ + #define REG_ISI_CR (*(__O uint32_t*)0x4004C024U) /**< \brief (ISI) ISI Control Register */ + #define REG_ISI_SR (*(__I uint32_t*)0x4004C028U) /**< \brief (ISI) ISI Status Register */ + #define REG_ISI_IER (*(__O uint32_t*)0x4004C02CU) /**< \brief (ISI) ISI Interrupt Enable Register */ + #define REG_ISI_IDR (*(__O uint32_t*)0x4004C030U) /**< \brief (ISI) ISI Interrupt Disable Register */ + #define REG_ISI_IMR (*(__I uint32_t*)0x4004C034U) /**< \brief (ISI) ISI Interrupt Mask Register */ + #define REG_ISI_DMA_CHER (*(__O uint32_t*)0x4004C038U) /**< \brief (ISI) DMA Channel Enable Register */ + #define REG_ISI_DMA_CHDR (*(__O uint32_t*)0x4004C03CU) /**< \brief (ISI) DMA Channel Disable Register */ + #define REG_ISI_DMA_CHSR (*(__I uint32_t*)0x4004C040U) /**< \brief (ISI) DMA Channel Status Register */ + #define REG_ISI_DMA_P_ADDR (*(__IO uint32_t*)0x4004C044U) /**< \brief (ISI) DMA Preview Base Address Register */ + #define REG_ISI_DMA_P_CTRL (*(__IO uint32_t*)0x4004C048U) /**< \brief (ISI) DMA Preview Control Register */ + #define REG_ISI_DMA_P_DSCR (*(__IO uint32_t*)0x4004C04CU) /**< \brief (ISI) DMA Preview Descriptor Address Register */ + #define REG_ISI_DMA_C_ADDR (*(__IO uint32_t*)0x4004C050U) /**< \brief (ISI) DMA Codec Base Address Register */ + #define REG_ISI_DMA_C_CTRL (*(__IO uint32_t*)0x4004C054U) /**< \brief (ISI) DMA Codec Control Register */ + #define REG_ISI_DMA_C_DSCR (*(__IO uint32_t*)0x4004C058U) /**< \brief (ISI) DMA Codec Descriptor Address Register */ + #define REG_ISI_WPMR (*(__IO uint32_t*)0x4004C0E4U) /**< \brief (ISI) Write Protection Mode Register */ + #define REG_ISI_WPSR (*(__I uint32_t*)0x4004C0E8U) /**< \brief (ISI) Write Protection Status Register */ + #define REG_ISI_VERSION (*(__I uint32_t*)0x4004C0FCU) /**< \brief (ISI) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_ISI_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/matrix.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/matrix.h new file mode 100644 index 000000000..fdae66e16 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/matrix.h @@ -0,0 +1,123 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_MATRIX_INSTANCE_ +#define _SAME70_MATRIX_INSTANCE_ + +/* ========== Register definition for MATRIX peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_MATRIX_MCFG0 (0x40088000U) /**< \brief (MATRIX) Master Configuration Register 0 */ + #define REG_MATRIX_MCFG1 (0x40088004U) /**< \brief (MATRIX) Master Configuration Register 1 */ + #define REG_MATRIX_MCFG2 (0x40088008U) /**< \brief (MATRIX) Master Configuration Register 2 */ + #define REG_MATRIX_MCFG3 (0x4008800CU) /**< \brief (MATRIX) Master Configuration Register 3 */ + #define REG_MATRIX_MCFG4 (0x40088010U) /**< \brief (MATRIX) Master Configuration Register 4 */ + #define REG_MATRIX_MCFG5 (0x40088014U) /**< \brief (MATRIX) Master Configuration Register 5 */ + #define REG_MATRIX_MCFG6 (0x40088018U) /**< \brief (MATRIX) Master Configuration Register 6 */ + #define REG_MATRIX_MCFG8 (0x40088020U) /**< \brief (MATRIX) Master Configuration Register 8 */ + #define REG_MATRIX_MCFG9 (0x40088024U) /**< \brief (MATRIX) Master Configuration Register 9 */ + #define REG_MATRIX_MCFG10 (0x40088028U) /**< \brief (MATRIX) Master Configuration Register 10 */ + #define REG_MATRIX_MCFG11 (0x4008802CU) /**< \brief (MATRIX) Master Configuration Register 11 */ + #define REG_MATRIX_MCFG12 (0x40088030U) /**< \brief (MATRIX) Master Configuration Register 12 */ + #define REG_MATRIX_SCFG (0x40088040U) /**< \brief (MATRIX) Slave Configuration Register */ + #define REG_MATRIX_PRAS0 (0x40088080U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ + #define REG_MATRIX_PRBS0 (0x40088084U) /**< \brief (MATRIX) Priority Register B for Slave 0 */ + #define REG_MATRIX_PRAS1 (0x40088088U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ + #define REG_MATRIX_PRBS1 (0x4008808CU) /**< \brief (MATRIX) Priority Register B for Slave 1 */ + #define REG_MATRIX_PRAS2 (0x40088090U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ + #define REG_MATRIX_PRBS2 (0x40088094U) /**< \brief (MATRIX) Priority Register B for Slave 2 */ + #define REG_MATRIX_PRAS3 (0x40088098U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ + #define REG_MATRIX_PRBS3 (0x4008809CU) /**< \brief (MATRIX) Priority Register B for Slave 3 */ + #define REG_MATRIX_PRAS4 (0x400880A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ + #define REG_MATRIX_PRBS4 (0x400880A4U) /**< \brief (MATRIX) Priority Register B for Slave 4 */ + #define REG_MATRIX_PRAS5 (0x400880A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */ + #define REG_MATRIX_PRBS5 (0x400880ACU) /**< \brief (MATRIX) Priority Register B for Slave 5 */ + #define REG_MATRIX_PRAS6 (0x400880B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */ + #define REG_MATRIX_PRBS6 (0x400880B4U) /**< \brief (MATRIX) Priority Register B for Slave 6 */ + #define REG_MATRIX_PRAS7 (0x400880B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */ + #define REG_MATRIX_PRBS7 (0x400880BCU) /**< \brief (MATRIX) Priority Register B for Slave 7 */ + #define REG_MATRIX_PRAS8 (0x400880C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */ + #define REG_MATRIX_PRBS8 (0x400880C4U) /**< \brief (MATRIX) Priority Register B for Slave 8 */ + #define REG_MATRIX_MRCR (0x40088100U) /**< \brief (MATRIX) Master Remap Control Register */ + #define REG_CCFG_CAN0 (0x40088110U) /**< \brief (MATRIX) CAN0 Configuration Register */ + #define REG_CCFG_SYSIO (0x40088114U) /**< \brief (MATRIX) System I/O and CAN1 Configuration Register */ + #define REG_CCFG_PCCR (0x40088118U) /**< \brief (MATRIX) Peripheral Clock Configuration Register */ + #define REG_CCFG_DYNCKG (0x4008811CU) /**< \brief (MATRIX) Dynamic Clock Gating Register */ + #define REG_CCFG_SMCNFCS (0x40088124U) /**< \brief (MATRIX) SMC NAND Flash Chip Select Configuration Register */ + #define REG_MATRIX_WPMR (0x400881E4U) /**< \brief (MATRIX) Write Protection Mode Register */ + #define REG_MATRIX_WPSR (0x400881E8U) /**< \brief (MATRIX) Write Protection Status Register */ + #define REG_MATRIX_VERSION (0x400881FCU) /**< \brief (MATRIX) Version Register */ +#else + #define REG_MATRIX_MCFG0 (*(__IO uint32_t*)0x40088000U) /**< \brief (MATRIX) Master Configuration Register 0 */ + #define REG_MATRIX_MCFG1 (*(__IO uint32_t*)0x40088004U) /**< \brief (MATRIX) Master Configuration Register 1 */ + #define REG_MATRIX_MCFG2 (*(__IO uint32_t*)0x40088008U) /**< \brief (MATRIX) Master Configuration Register 2 */ + #define REG_MATRIX_MCFG3 (*(__IO uint32_t*)0x4008800CU) /**< \brief (MATRIX) Master Configuration Register 3 */ + #define REG_MATRIX_MCFG4 (*(__IO uint32_t*)0x40088010U) /**< \brief (MATRIX) Master Configuration Register 4 */ + #define REG_MATRIX_MCFG5 (*(__IO uint32_t*)0x40088014U) /**< \brief (MATRIX) Master Configuration Register 5 */ + #define REG_MATRIX_MCFG6 (*(__IO uint32_t*)0x40088018U) /**< \brief (MATRIX) Master Configuration Register 6 */ + #define REG_MATRIX_MCFG8 (*(__IO uint32_t*)0x40088020U) /**< \brief (MATRIX) Master Configuration Register 8 */ + #define REG_MATRIX_MCFG9 (*(__IO uint32_t*)0x40088024U) /**< \brief (MATRIX) Master Configuration Register 9 */ + #define REG_MATRIX_MCFG10 (*(__IO uint32_t*)0x40088028U) /**< \brief (MATRIX) Master Configuration Register 10 */ + #define REG_MATRIX_MCFG11 (*(__IO uint32_t*)0x4008802CU) /**< \brief (MATRIX) Master Configuration Register 11 */ + #define REG_MATRIX_MCFG12 (*(__IO uint32_t*)0x40088030U) /**< \brief (MATRIX) Master Configuration Register 12 */ + #define REG_MATRIX_SCFG (*(__IO uint32_t*)0x40088040U) /**< \brief (MATRIX) Slave Configuration Register */ + #define REG_MATRIX_PRAS0 (*(__IO uint32_t*)0x40088080U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ + #define REG_MATRIX_PRBS0 (*(__IO uint32_t*)0x40088084U) /**< \brief (MATRIX) Priority Register B for Slave 0 */ + #define REG_MATRIX_PRAS1 (*(__IO uint32_t*)0x40088088U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ + #define REG_MATRIX_PRBS1 (*(__IO uint32_t*)0x4008808CU) /**< \brief (MATRIX) Priority Register B for Slave 1 */ + #define REG_MATRIX_PRAS2 (*(__IO uint32_t*)0x40088090U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ + #define REG_MATRIX_PRBS2 (*(__IO uint32_t*)0x40088094U) /**< \brief (MATRIX) Priority Register B for Slave 2 */ + #define REG_MATRIX_PRAS3 (*(__IO uint32_t*)0x40088098U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ + #define REG_MATRIX_PRBS3 (*(__IO uint32_t*)0x4008809CU) /**< \brief (MATRIX) Priority Register B for Slave 3 */ + #define REG_MATRIX_PRAS4 (*(__IO uint32_t*)0x400880A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ + #define REG_MATRIX_PRBS4 (*(__IO uint32_t*)0x400880A4U) /**< \brief (MATRIX) Priority Register B for Slave 4 */ + #define REG_MATRIX_PRAS5 (*(__IO uint32_t*)0x400880A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */ + #define REG_MATRIX_PRBS5 (*(__IO uint32_t*)0x400880ACU) /**< \brief (MATRIX) Priority Register B for Slave 5 */ + #define REG_MATRIX_PRAS6 (*(__IO uint32_t*)0x400880B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */ + #define REG_MATRIX_PRBS6 (*(__IO uint32_t*)0x400880B4U) /**< \brief (MATRIX) Priority Register B for Slave 6 */ + #define REG_MATRIX_PRAS7 (*(__IO uint32_t*)0x400880B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */ + #define REG_MATRIX_PRBS7 (*(__IO uint32_t*)0x400880BCU) /**< \brief (MATRIX) Priority Register B for Slave 7 */ + #define REG_MATRIX_PRAS8 (*(__IO uint32_t*)0x400880C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */ + #define REG_MATRIX_PRBS8 (*(__IO uint32_t*)0x400880C4U) /**< \brief (MATRIX) Priority Register B for Slave 8 */ + #define REG_MATRIX_MRCR (*(__IO uint32_t*)0x40088100U) /**< \brief (MATRIX) Master Remap Control Register */ + #define REG_CCFG_CAN0 (*(__IO uint32_t*)0x40088110U) /**< \brief (MATRIX) CAN0 Configuration Register */ + #define REG_CCFG_SYSIO (*(__IO uint32_t*)0x40088114U) /**< \brief (MATRIX) System I/O and CAN1 Configuration Register */ + #define REG_CCFG_PCCR (*(__IO uint32_t*)0x40088118U) /**< \brief (MATRIX) Peripheral Clock Configuration Register */ + #define REG_CCFG_DYNCKG (*(__IO uint32_t*)0x4008811CU) /**< \brief (MATRIX) Dynamic Clock Gating Register */ + #define REG_CCFG_SMCNFCS (*(__IO uint32_t*)0x40088124U) /**< \brief (MATRIX) SMC NAND Flash Chip Select Configuration Register */ + #define REG_MATRIX_WPMR (*(__IO uint32_t*)0x400881E4U) /**< \brief (MATRIX) Write Protection Mode Register */ + #define REG_MATRIX_WPSR (*(__I uint32_t*)0x400881E8U) /**< \brief (MATRIX) Write Protection Status Register */ + #define REG_MATRIX_VERSION (*(__I uint32_t*)0x400881FCU) /**< \brief (MATRIX) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_MATRIX_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/mcan0.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/mcan0.h new file mode 100644 index 000000000..c8819b342 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/mcan0.h @@ -0,0 +1,141 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_MCAN0_INSTANCE_ +#define _SAME70_MCAN0_INSTANCE_ + +/* ========== Register definition for MCAN0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_MCAN0_CREL (0x40030000U) /**< \brief (MCAN0) Core Release Register */ + #define REG_MCAN0_ENDN (0x40030004U) /**< \brief (MCAN0) Endian Register */ + #define REG_MCAN0_CUST (0x40030008U) /**< \brief (MCAN0) Customer Register */ + #define REG_MCAN0_FBTP (0x4003000CU) /**< \brief (MCAN0) Fast Bit Timing and Prescaler Register */ + #define REG_MCAN0_DBTP (0x4003000CU) /**< \brief (MCAN0) Data Bit Timing and Prescaler Register */ + #define REG_MCAN0_TEST (0x40030010U) /**< \brief (MCAN0) Test Register */ + #define REG_MCAN0_RWD (0x40030014U) /**< \brief (MCAN0) RAM Watchdog Register */ + #define REG_MCAN0_CCCR (0x40030018U) /**< \brief (MCAN0) CC Control Register */ + #define REG_MCAN0_BTP (0x4003001CU) /**< \brief (MCAN0) Bit Timing and Prescaler Register */ + #define REG_MCAN0_NBTP (0x4003001CU) /**< \brief (MCAN0) Nominal Bit Timing and Prescaler Register */ + #define REG_MCAN0_TSCC (0x40030020U) /**< \brief (MCAN0) Timestamp Counter Configuration Register */ + #define REG_MCAN0_TSCV (0x40030024U) /**< \brief (MCAN0) Timestamp Counter Value Register */ + #define REG_MCAN0_TOCC (0x40030028U) /**< \brief (MCAN0) Timeout Counter Configuration Register */ + #define REG_MCAN0_TOCV (0x4003002CU) /**< \brief (MCAN0) Timeout Counter Value Register */ + #define REG_MCAN0_ECR (0x40030040U) /**< \brief (MCAN0) Error Counter Register */ + #define REG_MCAN0_PSR (0x40030044U) /**< \brief (MCAN0) Protocol Status Register */ + #define REG_MCAN0_TDCR (0x40030048U) /**< \brief (MCAN0) Transmit Delay Compensation Register */ + #define REG_MCAN0_IR (0x40030050U) /**< \brief (MCAN0) Interrupt Register */ + #define REG_MCAN0_IE (0x40030054U) /**< \brief (MCAN0) Interrupt Enable Register */ + #define REG_MCAN0_ILS (0x40030058U) /**< \brief (MCAN0) Interrupt Line Select Register */ + #define REG_MCAN0_ILE (0x4003005CU) /**< \brief (MCAN0) Interrupt Line Enable Register */ + #define REG_MCAN0_GFC (0x40030080U) /**< \brief (MCAN0) Global Filter Configuration Register */ + #define REG_MCAN0_SIDFC (0x40030084U) /**< \brief (MCAN0) Standard ID Filter Configuration Register */ + #define REG_MCAN0_XIDFC (0x40030088U) /**< \brief (MCAN0) Extended ID Filter Configuration Register */ + #define REG_MCAN0_XIDAM (0x40030090U) /**< \brief (MCAN0) Extended ID AND Mask Register */ + #define REG_MCAN0_HPMS (0x40030094U) /**< \brief (MCAN0) High Priority Message Status Register */ + #define REG_MCAN0_NDAT1 (0x40030098U) /**< \brief (MCAN0) New Data 1 Register */ + #define REG_MCAN0_NDAT2 (0x4003009CU) /**< \brief (MCAN0) New Data 2 Register */ + #define REG_MCAN0_RXF0C (0x400300A0U) /**< \brief (MCAN0) Receive FIFO 0 Configuration Register */ + #define REG_MCAN0_RXF0S (0x400300A4U) /**< \brief (MCAN0) Receive FIFO 0 Status Register */ + #define REG_MCAN0_RXF0A (0x400300A8U) /**< \brief (MCAN0) Receive FIFO 0 Acknowledge Register */ + #define REG_MCAN0_RXBC (0x400300ACU) /**< \brief (MCAN0) Receive Rx Buffer Configuration Register */ + #define REG_MCAN0_RXF1C (0x400300B0U) /**< \brief (MCAN0) Receive FIFO 1 Configuration Register */ + #define REG_MCAN0_RXF1S (0x400300B4U) /**< \brief (MCAN0) Receive FIFO 1 Status Register */ + #define REG_MCAN0_RXF1A (0x400300B8U) /**< \brief (MCAN0) Receive FIFO 1 Acknowledge Register */ + #define REG_MCAN0_RXESC (0x400300BCU) /**< \brief (MCAN0) Receive Buffer / FIFO Element Size Configuration Register */ + #define REG_MCAN0_TXBC (0x400300C0U) /**< \brief (MCAN0) Transmit Buffer Configuration Register */ + #define REG_MCAN0_TXFQS (0x400300C4U) /**< \brief (MCAN0) Transmit FIFO/Queue Status Register */ + #define REG_MCAN0_TXESC (0x400300C8U) /**< \brief (MCAN0) Transmit Buffer Element Size Configuration Register */ + #define REG_MCAN0_TXBRP (0x400300CCU) /**< \brief (MCAN0) Transmit Buffer Request Pending Register */ + #define REG_MCAN0_TXBAR (0x400300D0U) /**< \brief (MCAN0) Transmit Buffer Add Request Register */ + #define REG_MCAN0_TXBCR (0x400300D4U) /**< \brief (MCAN0) Transmit Buffer Cancellation Request Register */ + #define REG_MCAN0_TXBTO (0x400300D8U) /**< \brief (MCAN0) Transmit Buffer Transmission Occurred Register */ + #define REG_MCAN0_TXBCF (0x400300DCU) /**< \brief (MCAN0) Transmit Buffer Cancellation Finished Register */ + #define REG_MCAN0_TXBTIE (0x400300E0U) /**< \brief (MCAN0) Transmit Buffer Transmission Interrupt Enable Register */ + #define REG_MCAN0_TXBCIE (0x400300E4U) /**< \brief (MCAN0) Transmit Buffer Cancellation Finished Interrupt Enable Register */ + #define REG_MCAN0_TXEFC (0x400300F0U) /**< \brief (MCAN0) Transmit Event FIFO Configuration Register */ + #define REG_MCAN0_TXEFS (0x400300F4U) /**< \brief (MCAN0) Transmit Event FIFO Status Register */ + #define REG_MCAN0_TXEFA (0x400300F8U) /**< \brief (MCAN0) Transmit Event FIFO Acknowledge Register */ +#else + #define REG_MCAN0_CREL (*(__I uint32_t*)0x40030000U) /**< \brief (MCAN0) Core Release Register */ + #define REG_MCAN0_ENDN (*(__I uint32_t*)0x40030004U) /**< \brief (MCAN0) Endian Register */ + #define REG_MCAN0_CUST (*(__IO uint32_t*)0x40030008U) /**< \brief (MCAN0) Customer Register */ + #define REG_MCAN0_FBTP (*(__IO uint32_t*)0x4003000CU) /**< \brief (MCAN0) Fast Bit Timing and Prescaler Register */ + #define REG_MCAN0_DBTP (*(__IO uint32_t*)0x4003000CU) /**< \brief (MCAN0) Data Bit Timing and Prescaler Register */ + #define REG_MCAN0_TEST (*(__IO uint32_t*)0x40030010U) /**< \brief (MCAN0) Test Register */ + #define REG_MCAN0_RWD (*(__IO uint32_t*)0x40030014U) /**< \brief (MCAN0) RAM Watchdog Register */ + #define REG_MCAN0_CCCR (*(__IO uint32_t*)0x40030018U) /**< \brief (MCAN0) CC Control Register */ + #define REG_MCAN0_BTP (*(__IO uint32_t*)0x4003001CU) /**< \brief (MCAN0) Bit Timing and Prescaler Register */ + #define REG_MCAN0_NBTP (*(__IO uint32_t*)0x4003001CU) /**< \brief (MCAN0) Nominal Bit Timing and Prescaler Register */ + #define REG_MCAN0_TSCC (*(__IO uint32_t*)0x40030020U) /**< \brief (MCAN0) Timestamp Counter Configuration Register */ + #define REG_MCAN0_TSCV (*(__IO uint32_t*)0x40030024U) /**< \brief (MCAN0) Timestamp Counter Value Register */ + #define REG_MCAN0_TOCC (*(__IO uint32_t*)0x40030028U) /**< \brief (MCAN0) Timeout Counter Configuration Register */ + #define REG_MCAN0_TOCV (*(__IO uint32_t*)0x4003002CU) /**< \brief (MCAN0) Timeout Counter Value Register */ + #define REG_MCAN0_ECR (*(__I uint32_t*)0x40030040U) /**< \brief (MCAN0) Error Counter Register */ + #define REG_MCAN0_PSR (*(__I uint32_t*)0x40030044U) /**< \brief (MCAN0) Protocol Status Register */ + #define REG_MCAN0_TDCR (*(__IO uint32_t*)0x40030048U) /**< \brief (MCAN0) Transmit Delay Compensation Register */ + #define REG_MCAN0_IR (*(__IO uint32_t*)0x40030050U) /**< \brief (MCAN0) Interrupt Register */ + #define REG_MCAN0_IE (*(__IO uint32_t*)0x40030054U) /**< \brief (MCAN0) Interrupt Enable Register */ + #define REG_MCAN0_ILS (*(__IO uint32_t*)0x40030058U) /**< \brief (MCAN0) Interrupt Line Select Register */ + #define REG_MCAN0_ILE (*(__IO uint32_t*)0x4003005CU) /**< \brief (MCAN0) Interrupt Line Enable Register */ + #define REG_MCAN0_GFC (*(__IO uint32_t*)0x40030080U) /**< \brief (MCAN0) Global Filter Configuration Register */ + #define REG_MCAN0_SIDFC (*(__IO uint32_t*)0x40030084U) /**< \brief (MCAN0) Standard ID Filter Configuration Register */ + #define REG_MCAN0_XIDFC (*(__IO uint32_t*)0x40030088U) /**< \brief (MCAN0) Extended ID Filter Configuration Register */ + #define REG_MCAN0_XIDAM (*(__IO uint32_t*)0x40030090U) /**< \brief (MCAN0) Extended ID AND Mask Register */ + #define REG_MCAN0_HPMS (*(__I uint32_t*)0x40030094U) /**< \brief (MCAN0) High Priority Message Status Register */ + #define REG_MCAN0_NDAT1 (*(__IO uint32_t*)0x40030098U) /**< \brief (MCAN0) New Data 1 Register */ + #define REG_MCAN0_NDAT2 (*(__IO uint32_t*)0x4003009CU) /**< \brief (MCAN0) New Data 2 Register */ + #define REG_MCAN0_RXF0C (*(__IO uint32_t*)0x400300A0U) /**< \brief (MCAN0) Receive FIFO 0 Configuration Register */ + #define REG_MCAN0_RXF0S (*(__I uint32_t*)0x400300A4U) /**< \brief (MCAN0) Receive FIFO 0 Status Register */ + #define REG_MCAN0_RXF0A (*(__IO uint32_t*)0x400300A8U) /**< \brief (MCAN0) Receive FIFO 0 Acknowledge Register */ + #define REG_MCAN0_RXBC (*(__IO uint32_t*)0x400300ACU) /**< \brief (MCAN0) Receive Rx Buffer Configuration Register */ + #define REG_MCAN0_RXF1C (*(__IO uint32_t*)0x400300B0U) /**< \brief (MCAN0) Receive FIFO 1 Configuration Register */ + #define REG_MCAN0_RXF1S (*(__I uint32_t*)0x400300B4U) /**< \brief (MCAN0) Receive FIFO 1 Status Register */ + #define REG_MCAN0_RXF1A (*(__IO uint32_t*)0x400300B8U) /**< \brief (MCAN0) Receive FIFO 1 Acknowledge Register */ + #define REG_MCAN0_RXESC (*(__IO uint32_t*)0x400300BCU) /**< \brief (MCAN0) Receive Buffer / FIFO Element Size Configuration Register */ + #define REG_MCAN0_TXBC (*(__IO uint32_t*)0x400300C0U) /**< \brief (MCAN0) Transmit Buffer Configuration Register */ + #define REG_MCAN0_TXFQS (*(__I uint32_t*)0x400300C4U) /**< \brief (MCAN0) Transmit FIFO/Queue Status Register */ + #define REG_MCAN0_TXESC (*(__IO uint32_t*)0x400300C8U) /**< \brief (MCAN0) Transmit Buffer Element Size Configuration Register */ + #define REG_MCAN0_TXBRP (*(__I uint32_t*)0x400300CCU) /**< \brief (MCAN0) Transmit Buffer Request Pending Register */ + #define REG_MCAN0_TXBAR (*(__IO uint32_t*)0x400300D0U) /**< \brief (MCAN0) Transmit Buffer Add Request Register */ + #define REG_MCAN0_TXBCR (*(__IO uint32_t*)0x400300D4U) /**< \brief (MCAN0) Transmit Buffer Cancellation Request Register */ + #define REG_MCAN0_TXBTO (*(__I uint32_t*)0x400300D8U) /**< \brief (MCAN0) Transmit Buffer Transmission Occurred Register */ + #define REG_MCAN0_TXBCF (*(__I uint32_t*)0x400300DCU) /**< \brief (MCAN0) Transmit Buffer Cancellation Finished Register */ + #define REG_MCAN0_TXBTIE (*(__IO uint32_t*)0x400300E0U) /**< \brief (MCAN0) Transmit Buffer Transmission Interrupt Enable Register */ + #define REG_MCAN0_TXBCIE (*(__IO uint32_t*)0x400300E4U) /**< \brief (MCAN0) Transmit Buffer Cancellation Finished Interrupt Enable Register */ + #define REG_MCAN0_TXEFC (*(__IO uint32_t*)0x400300F0U) /**< \brief (MCAN0) Transmit Event FIFO Configuration Register */ + #define REG_MCAN0_TXEFS (*(__I uint32_t*)0x400300F4U) /**< \brief (MCAN0) Transmit Event FIFO Status Register */ + #define REG_MCAN0_TXEFA (*(__IO uint32_t*)0x400300F8U) /**< \brief (MCAN0) Transmit Event FIFO Acknowledge Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_MCAN0_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/mcan1.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/mcan1.h new file mode 100644 index 000000000..2c81491ae --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/mcan1.h @@ -0,0 +1,141 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_MCAN1_INSTANCE_ +#define _SAME70_MCAN1_INSTANCE_ + +/* ========== Register definition for MCAN1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_MCAN1_CREL (0x40034000U) /**< \brief (MCAN1) Core Release Register */ + #define REG_MCAN1_ENDN (0x40034004U) /**< \brief (MCAN1) Endian Register */ + #define REG_MCAN1_CUST (0x40034008U) /**< \brief (MCAN1) Customer Register */ + #define REG_MCAN1_FBTP (0x4003400CU) /**< \brief (MCAN1) Fast Bit Timing and Prescaler Register */ + #define REG_MCAN1_DBTP (0x4003400CU) /**< \brief (MCAN1) Data Bit Timing and Prescaler Register */ + #define REG_MCAN1_TEST (0x40034010U) /**< \brief (MCAN1) Test Register */ + #define REG_MCAN1_RWD (0x40034014U) /**< \brief (MCAN1) RAM Watchdog Register */ + #define REG_MCAN1_CCCR (0x40034018U) /**< \brief (MCAN1) CC Control Register */ + #define REG_MCAN1_BTP (0x4003401CU) /**< \brief (MCAN1) Bit Timing and Prescaler Register */ + #define REG_MCAN1_NBTP (0x4003401CU) /**< \brief (MCAN1) Nominal Bit Timing and Prescaler Register */ + #define REG_MCAN1_TSCC (0x40034020U) /**< \brief (MCAN1) Timestamp Counter Configuration Register */ + #define REG_MCAN1_TSCV (0x40034024U) /**< \brief (MCAN1) Timestamp Counter Value Register */ + #define REG_MCAN1_TOCC (0x40034028U) /**< \brief (MCAN1) Timeout Counter Configuration Register */ + #define REG_MCAN1_TOCV (0x4003402CU) /**< \brief (MCAN1) Timeout Counter Value Register */ + #define REG_MCAN1_ECR (0x40034040U) /**< \brief (MCAN1) Error Counter Register */ + #define REG_MCAN1_PSR (0x40034044U) /**< \brief (MCAN1) Protocol Status Register */ + #define REG_MCAN1_TDCR (0x40034048U) /**< \brief (MCAN1) Transmit Delay Compensation Register */ + #define REG_MCAN1_IR (0x40034050U) /**< \brief (MCAN1) Interrupt Register */ + #define REG_MCAN1_IE (0x40034054U) /**< \brief (MCAN1) Interrupt Enable Register */ + #define REG_MCAN1_ILS (0x40034058U) /**< \brief (MCAN1) Interrupt Line Select Register */ + #define REG_MCAN1_ILE (0x4003405CU) /**< \brief (MCAN1) Interrupt Line Enable Register */ + #define REG_MCAN1_GFC (0x40034080U) /**< \brief (MCAN1) Global Filter Configuration Register */ + #define REG_MCAN1_SIDFC (0x40034084U) /**< \brief (MCAN1) Standard ID Filter Configuration Register */ + #define REG_MCAN1_XIDFC (0x40034088U) /**< \brief (MCAN1) Extended ID Filter Configuration Register */ + #define REG_MCAN1_XIDAM (0x40034090U) /**< \brief (MCAN1) Extended ID AND Mask Register */ + #define REG_MCAN1_HPMS (0x40034094U) /**< \brief (MCAN1) High Priority Message Status Register */ + #define REG_MCAN1_NDAT1 (0x40034098U) /**< \brief (MCAN1) New Data 1 Register */ + #define REG_MCAN1_NDAT2 (0x4003409CU) /**< \brief (MCAN1) New Data 2 Register */ + #define REG_MCAN1_RXF0C (0x400340A0U) /**< \brief (MCAN1) Receive FIFO 0 Configuration Register */ + #define REG_MCAN1_RXF0S (0x400340A4U) /**< \brief (MCAN1) Receive FIFO 0 Status Register */ + #define REG_MCAN1_RXF0A (0x400340A8U) /**< \brief (MCAN1) Receive FIFO 0 Acknowledge Register */ + #define REG_MCAN1_RXBC (0x400340ACU) /**< \brief (MCAN1) Receive Rx Buffer Configuration Register */ + #define REG_MCAN1_RXF1C (0x400340B0U) /**< \brief (MCAN1) Receive FIFO 1 Configuration Register */ + #define REG_MCAN1_RXF1S (0x400340B4U) /**< \brief (MCAN1) Receive FIFO 1 Status Register */ + #define REG_MCAN1_RXF1A (0x400340B8U) /**< \brief (MCAN1) Receive FIFO 1 Acknowledge Register */ + #define REG_MCAN1_RXESC (0x400340BCU) /**< \brief (MCAN1) Receive Buffer / FIFO Element Size Configuration Register */ + #define REG_MCAN1_TXBC (0x400340C0U) /**< \brief (MCAN1) Transmit Buffer Configuration Register */ + #define REG_MCAN1_TXFQS (0x400340C4U) /**< \brief (MCAN1) Transmit FIFO/Queue Status Register */ + #define REG_MCAN1_TXESC (0x400340C8U) /**< \brief (MCAN1) Transmit Buffer Element Size Configuration Register */ + #define REG_MCAN1_TXBRP (0x400340CCU) /**< \brief (MCAN1) Transmit Buffer Request Pending Register */ + #define REG_MCAN1_TXBAR (0x400340D0U) /**< \brief (MCAN1) Transmit Buffer Add Request Register */ + #define REG_MCAN1_TXBCR (0x400340D4U) /**< \brief (MCAN1) Transmit Buffer Cancellation Request Register */ + #define REG_MCAN1_TXBTO (0x400340D8U) /**< \brief (MCAN1) Transmit Buffer Transmission Occurred Register */ + #define REG_MCAN1_TXBCF (0x400340DCU) /**< \brief (MCAN1) Transmit Buffer Cancellation Finished Register */ + #define REG_MCAN1_TXBTIE (0x400340E0U) /**< \brief (MCAN1) Transmit Buffer Transmission Interrupt Enable Register */ + #define REG_MCAN1_TXBCIE (0x400340E4U) /**< \brief (MCAN1) Transmit Buffer Cancellation Finished Interrupt Enable Register */ + #define REG_MCAN1_TXEFC (0x400340F0U) /**< \brief (MCAN1) Transmit Event FIFO Configuration Register */ + #define REG_MCAN1_TXEFS (0x400340F4U) /**< \brief (MCAN1) Transmit Event FIFO Status Register */ + #define REG_MCAN1_TXEFA (0x400340F8U) /**< \brief (MCAN1) Transmit Event FIFO Acknowledge Register */ +#else + #define REG_MCAN1_CREL (*(__I uint32_t*)0x40034000U) /**< \brief (MCAN1) Core Release Register */ + #define REG_MCAN1_ENDN (*(__I uint32_t*)0x40034004U) /**< \brief (MCAN1) Endian Register */ + #define REG_MCAN1_CUST (*(__IO uint32_t*)0x40034008U) /**< \brief (MCAN1) Customer Register */ + #define REG_MCAN1_FBTP (*(__IO uint32_t*)0x4003400CU) /**< \brief (MCAN1) Fast Bit Timing and Prescaler Register */ + #define REG_MCAN1_DBTP (*(__IO uint32_t*)0x4003400CU) /**< \brief (MCAN1) Data Bit Timing and Prescaler Register */ + #define REG_MCAN1_TEST (*(__IO uint32_t*)0x40034010U) /**< \brief (MCAN1) Test Register */ + #define REG_MCAN1_RWD (*(__IO uint32_t*)0x40034014U) /**< \brief (MCAN1) RAM Watchdog Register */ + #define REG_MCAN1_CCCR (*(__IO uint32_t*)0x40034018U) /**< \brief (MCAN1) CC Control Register */ + #define REG_MCAN1_BTP (*(__IO uint32_t*)0x4003401CU) /**< \brief (MCAN1) Bit Timing and Prescaler Register */ + #define REG_MCAN1_NBTP (*(__IO uint32_t*)0x4003401CU) /**< \brief (MCAN1) Nominal Bit Timing and Prescaler Register */ + #define REG_MCAN1_TSCC (*(__IO uint32_t*)0x40034020U) /**< \brief (MCAN1) Timestamp Counter Configuration Register */ + #define REG_MCAN1_TSCV (*(__IO uint32_t*)0x40034024U) /**< \brief (MCAN1) Timestamp Counter Value Register */ + #define REG_MCAN1_TOCC (*(__IO uint32_t*)0x40034028U) /**< \brief (MCAN1) Timeout Counter Configuration Register */ + #define REG_MCAN1_TOCV (*(__IO uint32_t*)0x4003402CU) /**< \brief (MCAN1) Timeout Counter Value Register */ + #define REG_MCAN1_ECR (*(__I uint32_t*)0x40034040U) /**< \brief (MCAN1) Error Counter Register */ + #define REG_MCAN1_PSR (*(__I uint32_t*)0x40034044U) /**< \brief (MCAN1) Protocol Status Register */ + #define REG_MCAN1_TDCR (*(__IO uint32_t*)0x40034048U) /**< \brief (MCAN1) Transmit Delay Compensation Register */ + #define REG_MCAN1_IR (*(__IO uint32_t*)0x40034050U) /**< \brief (MCAN1) Interrupt Register */ + #define REG_MCAN1_IE (*(__IO uint32_t*)0x40034054U) /**< \brief (MCAN1) Interrupt Enable Register */ + #define REG_MCAN1_ILS (*(__IO uint32_t*)0x40034058U) /**< \brief (MCAN1) Interrupt Line Select Register */ + #define REG_MCAN1_ILE (*(__IO uint32_t*)0x4003405CU) /**< \brief (MCAN1) Interrupt Line Enable Register */ + #define REG_MCAN1_GFC (*(__IO uint32_t*)0x40034080U) /**< \brief (MCAN1) Global Filter Configuration Register */ + #define REG_MCAN1_SIDFC (*(__IO uint32_t*)0x40034084U) /**< \brief (MCAN1) Standard ID Filter Configuration Register */ + #define REG_MCAN1_XIDFC (*(__IO uint32_t*)0x40034088U) /**< \brief (MCAN1) Extended ID Filter Configuration Register */ + #define REG_MCAN1_XIDAM (*(__IO uint32_t*)0x40034090U) /**< \brief (MCAN1) Extended ID AND Mask Register */ + #define REG_MCAN1_HPMS (*(__I uint32_t*)0x40034094U) /**< \brief (MCAN1) High Priority Message Status Register */ + #define REG_MCAN1_NDAT1 (*(__IO uint32_t*)0x40034098U) /**< \brief (MCAN1) New Data 1 Register */ + #define REG_MCAN1_NDAT2 (*(__IO uint32_t*)0x4003409CU) /**< \brief (MCAN1) New Data 2 Register */ + #define REG_MCAN1_RXF0C (*(__IO uint32_t*)0x400340A0U) /**< \brief (MCAN1) Receive FIFO 0 Configuration Register */ + #define REG_MCAN1_RXF0S (*(__I uint32_t*)0x400340A4U) /**< \brief (MCAN1) Receive FIFO 0 Status Register */ + #define REG_MCAN1_RXF0A (*(__IO uint32_t*)0x400340A8U) /**< \brief (MCAN1) Receive FIFO 0 Acknowledge Register */ + #define REG_MCAN1_RXBC (*(__IO uint32_t*)0x400340ACU) /**< \brief (MCAN1) Receive Rx Buffer Configuration Register */ + #define REG_MCAN1_RXF1C (*(__IO uint32_t*)0x400340B0U) /**< \brief (MCAN1) Receive FIFO 1 Configuration Register */ + #define REG_MCAN1_RXF1S (*(__I uint32_t*)0x400340B4U) /**< \brief (MCAN1) Receive FIFO 1 Status Register */ + #define REG_MCAN1_RXF1A (*(__IO uint32_t*)0x400340B8U) /**< \brief (MCAN1) Receive FIFO 1 Acknowledge Register */ + #define REG_MCAN1_RXESC (*(__IO uint32_t*)0x400340BCU) /**< \brief (MCAN1) Receive Buffer / FIFO Element Size Configuration Register */ + #define REG_MCAN1_TXBC (*(__IO uint32_t*)0x400340C0U) /**< \brief (MCAN1) Transmit Buffer Configuration Register */ + #define REG_MCAN1_TXFQS (*(__I uint32_t*)0x400340C4U) /**< \brief (MCAN1) Transmit FIFO/Queue Status Register */ + #define REG_MCAN1_TXESC (*(__IO uint32_t*)0x400340C8U) /**< \brief (MCAN1) Transmit Buffer Element Size Configuration Register */ + #define REG_MCAN1_TXBRP (*(__I uint32_t*)0x400340CCU) /**< \brief (MCAN1) Transmit Buffer Request Pending Register */ + #define REG_MCAN1_TXBAR (*(__IO uint32_t*)0x400340D0U) /**< \brief (MCAN1) Transmit Buffer Add Request Register */ + #define REG_MCAN1_TXBCR (*(__IO uint32_t*)0x400340D4U) /**< \brief (MCAN1) Transmit Buffer Cancellation Request Register */ + #define REG_MCAN1_TXBTO (*(__I uint32_t*)0x400340D8U) /**< \brief (MCAN1) Transmit Buffer Transmission Occurred Register */ + #define REG_MCAN1_TXBCF (*(__I uint32_t*)0x400340DCU) /**< \brief (MCAN1) Transmit Buffer Cancellation Finished Register */ + #define REG_MCAN1_TXBTIE (*(__IO uint32_t*)0x400340E0U) /**< \brief (MCAN1) Transmit Buffer Transmission Interrupt Enable Register */ + #define REG_MCAN1_TXBCIE (*(__IO uint32_t*)0x400340E4U) /**< \brief (MCAN1) Transmit Buffer Cancellation Finished Interrupt Enable Register */ + #define REG_MCAN1_TXEFC (*(__IO uint32_t*)0x400340F0U) /**< \brief (MCAN1) Transmit Event FIFO Configuration Register */ + #define REG_MCAN1_TXEFS (*(__I uint32_t*)0x400340F4U) /**< \brief (MCAN1) Transmit Event FIFO Status Register */ + #define REG_MCAN1_TXEFA (*(__IO uint32_t*)0x400340F8U) /**< \brief (MCAN1) Transmit Event FIFO Acknowledge Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_MCAN1_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/pioa.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/pioa.h new file mode 100644 index 000000000..8aac50ffe --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/pioa.h @@ -0,0 +1,171 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_PIOA_INSTANCE_ +#define _SAME70_PIOA_INSTANCE_ + +/* ========== Register definition for PIOA peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PIOA_PER (0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */ + #define REG_PIOA_PDR (0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */ + #define REG_PIOA_PSR (0x400E0E08U) /**< \brief (PIOA) PIO Status Register */ + #define REG_PIOA_OER (0x400E0E10U) /**< \brief (PIOA) Output Enable Register */ + #define REG_PIOA_ODR (0x400E0E14U) /**< \brief (PIOA) Output Disable Register */ + #define REG_PIOA_OSR (0x400E0E18U) /**< \brief (PIOA) Output Status Register */ + #define REG_PIOA_IFER (0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ + #define REG_PIOA_IFDR (0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ + #define REG_PIOA_IFSR (0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ + #define REG_PIOA_SODR (0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */ + #define REG_PIOA_CODR (0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */ + #define REG_PIOA_ODSR (0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */ + #define REG_PIOA_PDSR (0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */ + #define REG_PIOA_IER (0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */ + #define REG_PIOA_IDR (0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */ + #define REG_PIOA_IMR (0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */ + #define REG_PIOA_ISR (0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */ + #define REG_PIOA_MDER (0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */ + #define REG_PIOA_MDDR (0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */ + #define REG_PIOA_MDSR (0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */ + #define REG_PIOA_PUDR (0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */ + #define REG_PIOA_PUER (0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */ + #define REG_PIOA_PUSR (0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */ + #define REG_PIOA_ABCDSR (0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */ + #define REG_PIOA_IFSCDR (0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */ + #define REG_PIOA_IFSCER (0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */ + #define REG_PIOA_IFSCSR (0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */ + #define REG_PIOA_SCDR (0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ + #define REG_PIOA_PPDDR (0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */ + #define REG_PIOA_PPDER (0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */ + #define REG_PIOA_PPDSR (0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */ + #define REG_PIOA_OWER (0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */ + #define REG_PIOA_OWDR (0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */ + #define REG_PIOA_OWSR (0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */ + #define REG_PIOA_AIMER (0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ + #define REG_PIOA_AIMDR (0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disable Register */ + #define REG_PIOA_AIMMR (0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ + #define REG_PIOA_ESR (0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */ + #define REG_PIOA_LSR (0x400E0EC4U) /**< \brief (PIOA) Level Select Register */ + #define REG_PIOA_ELSR (0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */ + #define REG_PIOA_FELLSR (0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low-Level Select Register */ + #define REG_PIOA_REHLSR (0x400E0ED4U) /**< \brief (PIOA) Rising Edge/High-Level Select Register */ + #define REG_PIOA_FRLHSR (0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ + #define REG_PIOA_LOCKSR (0x400E0EE0U) /**< \brief (PIOA) Lock Status */ + #define REG_PIOA_WPMR (0x400E0EE4U) /**< \brief (PIOA) Write Protection Mode Register */ + #define REG_PIOA_WPSR (0x400E0EE8U) /**< \brief (PIOA) Write Protection Status Register */ + #define REG_PIOA_VERSION (0x400E0EFCU) /**< \brief (PIOA) Version Register */ + #define REG_PIOA_SCHMITT (0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */ + #define REG_PIOA_DRIVER (0x400E0F18U) /**< \brief (PIOA) PIO I/O Drive Register */ + #define REG_PIOA_KER (0x400E0F20U) /**< \brief (PIOA) Keypad Controller Enable Register */ + #define REG_PIOA_KRCR (0x400E0F24U) /**< \brief (PIOA) Keypad Controller Row Column Register */ + #define REG_PIOA_KDR (0x400E0F28U) /**< \brief (PIOA) Keypad Controller Debouncing Register */ + #define REG_PIOA_KIER (0x400E0F30U) /**< \brief (PIOA) Keypad Controller Interrupt Enable Register */ + #define REG_PIOA_KIDR (0x400E0F34U) /**< \brief (PIOA) Keypad Controller Interrupt Disable Register */ + #define REG_PIOA_KIMR (0x400E0F38U) /**< \brief (PIOA) Keypad Controller Interrupt Mask Register */ + #define REG_PIOA_KSR (0x400E0F3CU) /**< \brief (PIOA) Keypad Controller Status Register */ + #define REG_PIOA_KKPR (0x400E0F40U) /**< \brief (PIOA) Keypad Controller Key Press Register */ + #define REG_PIOA_KKRR (0x400E0F44U) /**< \brief (PIOA) Keypad Controller Key Release Register */ + #define REG_PIOA_PCMR (0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */ + #define REG_PIOA_PCIER (0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */ + #define REG_PIOA_PCIDR (0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */ + #define REG_PIOA_PCIMR (0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */ + #define REG_PIOA_PCISR (0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */ + #define REG_PIOA_PCRHR (0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */ +#else + #define REG_PIOA_PER (*(__O uint32_t*)0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */ + #define REG_PIOA_PDR (*(__O uint32_t*)0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */ + #define REG_PIOA_PSR (*(__I uint32_t*)0x400E0E08U) /**< \brief (PIOA) PIO Status Register */ + #define REG_PIOA_OER (*(__O uint32_t*)0x400E0E10U) /**< \brief (PIOA) Output Enable Register */ + #define REG_PIOA_ODR (*(__O uint32_t*)0x400E0E14U) /**< \brief (PIOA) Output Disable Register */ + #define REG_PIOA_OSR (*(__I uint32_t*)0x400E0E18U) /**< \brief (PIOA) Output Status Register */ + #define REG_PIOA_IFER (*(__O uint32_t*)0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ + #define REG_PIOA_IFDR (*(__O uint32_t*)0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ + #define REG_PIOA_IFSR (*(__I uint32_t*)0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ + #define REG_PIOA_SODR (*(__O uint32_t*)0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */ + #define REG_PIOA_CODR (*(__O uint32_t*)0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */ + #define REG_PIOA_ODSR (*(__IO uint32_t*)0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */ + #define REG_PIOA_PDSR (*(__I uint32_t*)0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */ + #define REG_PIOA_IER (*(__O uint32_t*)0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */ + #define REG_PIOA_IDR (*(__O uint32_t*)0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */ + #define REG_PIOA_IMR (*(__I uint32_t*)0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */ + #define REG_PIOA_ISR (*(__I uint32_t*)0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */ + #define REG_PIOA_MDER (*(__O uint32_t*)0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */ + #define REG_PIOA_MDDR (*(__O uint32_t*)0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */ + #define REG_PIOA_MDSR (*(__I uint32_t*)0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */ + #define REG_PIOA_PUDR (*(__O uint32_t*)0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */ + #define REG_PIOA_PUER (*(__O uint32_t*)0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */ + #define REG_PIOA_PUSR (*(__I uint32_t*)0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */ + #define REG_PIOA_ABCDSR (*(__IO uint32_t*)0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */ + #define REG_PIOA_IFSCDR (*(__O uint32_t*)0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */ + #define REG_PIOA_IFSCER (*(__O uint32_t*)0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */ + #define REG_PIOA_IFSCSR (*(__I uint32_t*)0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */ + #define REG_PIOA_SCDR (*(__IO uint32_t*)0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ + #define REG_PIOA_PPDDR (*(__O uint32_t*)0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */ + #define REG_PIOA_PPDER (*(__O uint32_t*)0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */ + #define REG_PIOA_PPDSR (*(__I uint32_t*)0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */ + #define REG_PIOA_OWER (*(__O uint32_t*)0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */ + #define REG_PIOA_OWDR (*(__O uint32_t*)0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */ + #define REG_PIOA_OWSR (*(__I uint32_t*)0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */ + #define REG_PIOA_AIMER (*(__O uint32_t*)0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ + #define REG_PIOA_AIMDR (*(__O uint32_t*)0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disable Register */ + #define REG_PIOA_AIMMR (*(__I uint32_t*)0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ + #define REG_PIOA_ESR (*(__O uint32_t*)0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */ + #define REG_PIOA_LSR (*(__O uint32_t*)0x400E0EC4U) /**< \brief (PIOA) Level Select Register */ + #define REG_PIOA_ELSR (*(__I uint32_t*)0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */ + #define REG_PIOA_FELLSR (*(__O uint32_t*)0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low-Level Select Register */ + #define REG_PIOA_REHLSR (*(__O uint32_t*)0x400E0ED4U) /**< \brief (PIOA) Rising Edge/High-Level Select Register */ + #define REG_PIOA_FRLHSR (*(__I uint32_t*)0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ + #define REG_PIOA_LOCKSR (*(__I uint32_t*)0x400E0EE0U) /**< \brief (PIOA) Lock Status */ + #define REG_PIOA_WPMR (*(__IO uint32_t*)0x400E0EE4U) /**< \brief (PIOA) Write Protection Mode Register */ + #define REG_PIOA_WPSR (*(__I uint32_t*)0x400E0EE8U) /**< \brief (PIOA) Write Protection Status Register */ + #define REG_PIOA_VERSION (*(__I uint32_t*)0x400E0EFCU) /**< \brief (PIOA) Version Register */ + #define REG_PIOA_SCHMITT (*(__IO uint32_t*)0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */ + #define REG_PIOA_DRIVER (*(__IO uint32_t*)0x400E0F18U) /**< \brief (PIOA) PIO I/O Drive Register */ + #define REG_PIOA_KER (*(__IO uint32_t*)0x400E0F20U) /**< \brief (PIOA) Keypad Controller Enable Register */ + #define REG_PIOA_KRCR (*(__IO uint32_t*)0x400E0F24U) /**< \brief (PIOA) Keypad Controller Row Column Register */ + #define REG_PIOA_KDR (*(__IO uint32_t*)0x400E0F28U) /**< \brief (PIOA) Keypad Controller Debouncing Register */ + #define REG_PIOA_KIER (*(__O uint32_t*)0x400E0F30U) /**< \brief (PIOA) Keypad Controller Interrupt Enable Register */ + #define REG_PIOA_KIDR (*(__O uint32_t*)0x400E0F34U) /**< \brief (PIOA) Keypad Controller Interrupt Disable Register */ + #define REG_PIOA_KIMR (*(__I uint32_t*)0x400E0F38U) /**< \brief (PIOA) Keypad Controller Interrupt Mask Register */ + #define REG_PIOA_KSR (*(__I uint32_t*)0x400E0F3CU) /**< \brief (PIOA) Keypad Controller Status Register */ + #define REG_PIOA_KKPR (*(__I uint32_t*)0x400E0F40U) /**< \brief (PIOA) Keypad Controller Key Press Register */ + #define REG_PIOA_KKRR (*(__I uint32_t*)0x400E0F44U) /**< \brief (PIOA) Keypad Controller Key Release Register */ + #define REG_PIOA_PCMR (*(__IO uint32_t*)0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */ + #define REG_PIOA_PCIER (*(__O uint32_t*)0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */ + #define REG_PIOA_PCIDR (*(__O uint32_t*)0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */ + #define REG_PIOA_PCIMR (*(__I uint32_t*)0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */ + #define REG_PIOA_PCISR (*(__I uint32_t*)0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */ + #define REG_PIOA_PCRHR (*(__I uint32_t*)0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_PIOA_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/piob.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/piob.h new file mode 100644 index 000000000..20f6e283a --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/piob.h @@ -0,0 +1,171 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_PIOB_INSTANCE_ +#define _SAME70_PIOB_INSTANCE_ + +/* ========== Register definition for PIOB peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PIOB_PER (0x400E1000U) /**< \brief (PIOB) PIO Enable Register */ + #define REG_PIOB_PDR (0x400E1004U) /**< \brief (PIOB) PIO Disable Register */ + #define REG_PIOB_PSR (0x400E1008U) /**< \brief (PIOB) PIO Status Register */ + #define REG_PIOB_OER (0x400E1010U) /**< \brief (PIOB) Output Enable Register */ + #define REG_PIOB_ODR (0x400E1014U) /**< \brief (PIOB) Output Disable Register */ + #define REG_PIOB_OSR (0x400E1018U) /**< \brief (PIOB) Output Status Register */ + #define REG_PIOB_IFER (0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ + #define REG_PIOB_IFDR (0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ + #define REG_PIOB_IFSR (0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */ + #define REG_PIOB_SODR (0x400E1030U) /**< \brief (PIOB) Set Output Data Register */ + #define REG_PIOB_CODR (0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */ + #define REG_PIOB_ODSR (0x400E1038U) /**< \brief (PIOB) Output Data Status Register */ + #define REG_PIOB_PDSR (0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */ + #define REG_PIOB_IER (0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */ + #define REG_PIOB_IDR (0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */ + #define REG_PIOB_IMR (0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */ + #define REG_PIOB_ISR (0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */ + #define REG_PIOB_MDER (0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */ + #define REG_PIOB_MDDR (0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */ + #define REG_PIOB_MDSR (0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */ + #define REG_PIOB_PUDR (0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */ + #define REG_PIOB_PUER (0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */ + #define REG_PIOB_PUSR (0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */ + #define REG_PIOB_ABCDSR (0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */ + #define REG_PIOB_IFSCDR (0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */ + #define REG_PIOB_IFSCER (0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */ + #define REG_PIOB_IFSCSR (0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */ + #define REG_PIOB_SCDR (0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ + #define REG_PIOB_PPDDR (0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */ + #define REG_PIOB_PPDER (0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */ + #define REG_PIOB_PPDSR (0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */ + #define REG_PIOB_OWER (0x400E10A0U) /**< \brief (PIOB) Output Write Enable */ + #define REG_PIOB_OWDR (0x400E10A4U) /**< \brief (PIOB) Output Write Disable */ + #define REG_PIOB_OWSR (0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */ + #define REG_PIOB_AIMER (0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ + #define REG_PIOB_AIMDR (0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disable Register */ + #define REG_PIOB_AIMMR (0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ + #define REG_PIOB_ESR (0x400E10C0U) /**< \brief (PIOB) Edge Select Register */ + #define REG_PIOB_LSR (0x400E10C4U) /**< \brief (PIOB) Level Select Register */ + #define REG_PIOB_ELSR (0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */ + #define REG_PIOB_FELLSR (0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low-Level Select Register */ + #define REG_PIOB_REHLSR (0x400E10D4U) /**< \brief (PIOB) Rising Edge/High-Level Select Register */ + #define REG_PIOB_FRLHSR (0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ + #define REG_PIOB_LOCKSR (0x400E10E0U) /**< \brief (PIOB) Lock Status */ + #define REG_PIOB_WPMR (0x400E10E4U) /**< \brief (PIOB) Write Protection Mode Register */ + #define REG_PIOB_WPSR (0x400E10E8U) /**< \brief (PIOB) Write Protection Status Register */ + #define REG_PIOB_VERSION (0x400E10FCU) /**< \brief (PIOB) Version Register */ + #define REG_PIOB_SCHMITT (0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */ + #define REG_PIOB_DRIVER (0x400E1118U) /**< \brief (PIOB) PIO I/O Drive Register */ + #define REG_PIOB_KER (0x400E1120U) /**< \brief (PIOB) Keypad Controller Enable Register */ + #define REG_PIOB_KRCR (0x400E1124U) /**< \brief (PIOB) Keypad Controller Row Column Register */ + #define REG_PIOB_KDR (0x400E1128U) /**< \brief (PIOB) Keypad Controller Debouncing Register */ + #define REG_PIOB_KIER (0x400E1130U) /**< \brief (PIOB) Keypad Controller Interrupt Enable Register */ + #define REG_PIOB_KIDR (0x400E1134U) /**< \brief (PIOB) Keypad Controller Interrupt Disable Register */ + #define REG_PIOB_KIMR (0x400E1138U) /**< \brief (PIOB) Keypad Controller Interrupt Mask Register */ + #define REG_PIOB_KSR (0x400E113CU) /**< \brief (PIOB) Keypad Controller Status Register */ + #define REG_PIOB_KKPR (0x400E1140U) /**< \brief (PIOB) Keypad Controller Key Press Register */ + #define REG_PIOB_KKRR (0x400E1144U) /**< \brief (PIOB) Keypad Controller Key Release Register */ + #define REG_PIOB_PCMR (0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */ + #define REG_PIOB_PCIER (0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */ + #define REG_PIOB_PCIDR (0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */ + #define REG_PIOB_PCIMR (0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */ + #define REG_PIOB_PCISR (0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */ + #define REG_PIOB_PCRHR (0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */ +#else + #define REG_PIOB_PER (*(__O uint32_t*)0x400E1000U) /**< \brief (PIOB) PIO Enable Register */ + #define REG_PIOB_PDR (*(__O uint32_t*)0x400E1004U) /**< \brief (PIOB) PIO Disable Register */ + #define REG_PIOB_PSR (*(__I uint32_t*)0x400E1008U) /**< \brief (PIOB) PIO Status Register */ + #define REG_PIOB_OER (*(__O uint32_t*)0x400E1010U) /**< \brief (PIOB) Output Enable Register */ + #define REG_PIOB_ODR (*(__O uint32_t*)0x400E1014U) /**< \brief (PIOB) Output Disable Register */ + #define REG_PIOB_OSR (*(__I uint32_t*)0x400E1018U) /**< \brief (PIOB) Output Status Register */ + #define REG_PIOB_IFER (*(__O uint32_t*)0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ + #define REG_PIOB_IFDR (*(__O uint32_t*)0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ + #define REG_PIOB_IFSR (*(__I uint32_t*)0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */ + #define REG_PIOB_SODR (*(__O uint32_t*)0x400E1030U) /**< \brief (PIOB) Set Output Data Register */ + #define REG_PIOB_CODR (*(__O uint32_t*)0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */ + #define REG_PIOB_ODSR (*(__IO uint32_t*)0x400E1038U) /**< \brief (PIOB) Output Data Status Register */ + #define REG_PIOB_PDSR (*(__I uint32_t*)0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */ + #define REG_PIOB_IER (*(__O uint32_t*)0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */ + #define REG_PIOB_IDR (*(__O uint32_t*)0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */ + #define REG_PIOB_IMR (*(__I uint32_t*)0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */ + #define REG_PIOB_ISR (*(__I uint32_t*)0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */ + #define REG_PIOB_MDER (*(__O uint32_t*)0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */ + #define REG_PIOB_MDDR (*(__O uint32_t*)0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */ + #define REG_PIOB_MDSR (*(__I uint32_t*)0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */ + #define REG_PIOB_PUDR (*(__O uint32_t*)0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */ + #define REG_PIOB_PUER (*(__O uint32_t*)0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */ + #define REG_PIOB_PUSR (*(__I uint32_t*)0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */ + #define REG_PIOB_ABCDSR (*(__IO uint32_t*)0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */ + #define REG_PIOB_IFSCDR (*(__O uint32_t*)0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */ + #define REG_PIOB_IFSCER (*(__O uint32_t*)0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */ + #define REG_PIOB_IFSCSR (*(__I uint32_t*)0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */ + #define REG_PIOB_SCDR (*(__IO uint32_t*)0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ + #define REG_PIOB_PPDDR (*(__O uint32_t*)0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */ + #define REG_PIOB_PPDER (*(__O uint32_t*)0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */ + #define REG_PIOB_PPDSR (*(__I uint32_t*)0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */ + #define REG_PIOB_OWER (*(__O uint32_t*)0x400E10A0U) /**< \brief (PIOB) Output Write Enable */ + #define REG_PIOB_OWDR (*(__O uint32_t*)0x400E10A4U) /**< \brief (PIOB) Output Write Disable */ + #define REG_PIOB_OWSR (*(__I uint32_t*)0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */ + #define REG_PIOB_AIMER (*(__O uint32_t*)0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ + #define REG_PIOB_AIMDR (*(__O uint32_t*)0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disable Register */ + #define REG_PIOB_AIMMR (*(__I uint32_t*)0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ + #define REG_PIOB_ESR (*(__O uint32_t*)0x400E10C0U) /**< \brief (PIOB) Edge Select Register */ + #define REG_PIOB_LSR (*(__O uint32_t*)0x400E10C4U) /**< \brief (PIOB) Level Select Register */ + #define REG_PIOB_ELSR (*(__I uint32_t*)0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */ + #define REG_PIOB_FELLSR (*(__O uint32_t*)0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low-Level Select Register */ + #define REG_PIOB_REHLSR (*(__O uint32_t*)0x400E10D4U) /**< \brief (PIOB) Rising Edge/High-Level Select Register */ + #define REG_PIOB_FRLHSR (*(__I uint32_t*)0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ + #define REG_PIOB_LOCKSR (*(__I uint32_t*)0x400E10E0U) /**< \brief (PIOB) Lock Status */ + #define REG_PIOB_WPMR (*(__IO uint32_t*)0x400E10E4U) /**< \brief (PIOB) Write Protection Mode Register */ + #define REG_PIOB_WPSR (*(__I uint32_t*)0x400E10E8U) /**< \brief (PIOB) Write Protection Status Register */ + #define REG_PIOB_VERSION (*(__I uint32_t*)0x400E10FCU) /**< \brief (PIOB) Version Register */ + #define REG_PIOB_SCHMITT (*(__IO uint32_t*)0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */ + #define REG_PIOB_DRIVER (*(__IO uint32_t*)0x400E1118U) /**< \brief (PIOB) PIO I/O Drive Register */ + #define REG_PIOB_KER (*(__IO uint32_t*)0x400E1120U) /**< \brief (PIOB) Keypad Controller Enable Register */ + #define REG_PIOB_KRCR (*(__IO uint32_t*)0x400E1124U) /**< \brief (PIOB) Keypad Controller Row Column Register */ + #define REG_PIOB_KDR (*(__IO uint32_t*)0x400E1128U) /**< \brief (PIOB) Keypad Controller Debouncing Register */ + #define REG_PIOB_KIER (*(__O uint32_t*)0x400E1130U) /**< \brief (PIOB) Keypad Controller Interrupt Enable Register */ + #define REG_PIOB_KIDR (*(__O uint32_t*)0x400E1134U) /**< \brief (PIOB) Keypad Controller Interrupt Disable Register */ + #define REG_PIOB_KIMR (*(__I uint32_t*)0x400E1138U) /**< \brief (PIOB) Keypad Controller Interrupt Mask Register */ + #define REG_PIOB_KSR (*(__I uint32_t*)0x400E113CU) /**< \brief (PIOB) Keypad Controller Status Register */ + #define REG_PIOB_KKPR (*(__I uint32_t*)0x400E1140U) /**< \brief (PIOB) Keypad Controller Key Press Register */ + #define REG_PIOB_KKRR (*(__I uint32_t*)0x400E1144U) /**< \brief (PIOB) Keypad Controller Key Release Register */ + #define REG_PIOB_PCMR (*(__IO uint32_t*)0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */ + #define REG_PIOB_PCIER (*(__O uint32_t*)0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */ + #define REG_PIOB_PCIDR (*(__O uint32_t*)0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */ + #define REG_PIOB_PCIMR (*(__I uint32_t*)0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */ + #define REG_PIOB_PCISR (*(__I uint32_t*)0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */ + #define REG_PIOB_PCRHR (*(__I uint32_t*)0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_PIOB_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/pioc.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/pioc.h new file mode 100644 index 000000000..802bd831d --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/pioc.h @@ -0,0 +1,171 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_PIOC_INSTANCE_ +#define _SAME70_PIOC_INSTANCE_ + +/* ========== Register definition for PIOC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PIOC_PER (0x400E1200U) /**< \brief (PIOC) PIO Enable Register */ + #define REG_PIOC_PDR (0x400E1204U) /**< \brief (PIOC) PIO Disable Register */ + #define REG_PIOC_PSR (0x400E1208U) /**< \brief (PIOC) PIO Status Register */ + #define REG_PIOC_OER (0x400E1210U) /**< \brief (PIOC) Output Enable Register */ + #define REG_PIOC_ODR (0x400E1214U) /**< \brief (PIOC) Output Disable Register */ + #define REG_PIOC_OSR (0x400E1218U) /**< \brief (PIOC) Output Status Register */ + #define REG_PIOC_IFER (0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */ + #define REG_PIOC_IFDR (0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */ + #define REG_PIOC_IFSR (0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */ + #define REG_PIOC_SODR (0x400E1230U) /**< \brief (PIOC) Set Output Data Register */ + #define REG_PIOC_CODR (0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */ + #define REG_PIOC_ODSR (0x400E1238U) /**< \brief (PIOC) Output Data Status Register */ + #define REG_PIOC_PDSR (0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */ + #define REG_PIOC_IER (0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */ + #define REG_PIOC_IDR (0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */ + #define REG_PIOC_IMR (0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */ + #define REG_PIOC_ISR (0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */ + #define REG_PIOC_MDER (0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */ + #define REG_PIOC_MDDR (0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */ + #define REG_PIOC_MDSR (0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */ + #define REG_PIOC_PUDR (0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */ + #define REG_PIOC_PUER (0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */ + #define REG_PIOC_PUSR (0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */ + #define REG_PIOC_ABCDSR (0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */ + #define REG_PIOC_IFSCDR (0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */ + #define REG_PIOC_IFSCER (0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */ + #define REG_PIOC_IFSCSR (0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */ + #define REG_PIOC_SCDR (0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */ + #define REG_PIOC_PPDDR (0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */ + #define REG_PIOC_PPDER (0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */ + #define REG_PIOC_PPDSR (0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */ + #define REG_PIOC_OWER (0x400E12A0U) /**< \brief (PIOC) Output Write Enable */ + #define REG_PIOC_OWDR (0x400E12A4U) /**< \brief (PIOC) Output Write Disable */ + #define REG_PIOC_OWSR (0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */ + #define REG_PIOC_AIMER (0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */ + #define REG_PIOC_AIMDR (0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disable Register */ + #define REG_PIOC_AIMMR (0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */ + #define REG_PIOC_ESR (0x400E12C0U) /**< \brief (PIOC) Edge Select Register */ + #define REG_PIOC_LSR (0x400E12C4U) /**< \brief (PIOC) Level Select Register */ + #define REG_PIOC_ELSR (0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */ + #define REG_PIOC_FELLSR (0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low-Level Select Register */ + #define REG_PIOC_REHLSR (0x400E12D4U) /**< \brief (PIOC) Rising Edge/High-Level Select Register */ + #define REG_PIOC_FRLHSR (0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */ + #define REG_PIOC_LOCKSR (0x400E12E0U) /**< \brief (PIOC) Lock Status */ + #define REG_PIOC_WPMR (0x400E12E4U) /**< \brief (PIOC) Write Protection Mode Register */ + #define REG_PIOC_WPSR (0x400E12E8U) /**< \brief (PIOC) Write Protection Status Register */ + #define REG_PIOC_VERSION (0x400E12FCU) /**< \brief (PIOC) Version Register */ + #define REG_PIOC_SCHMITT (0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */ + #define REG_PIOC_DRIVER (0x400E1318U) /**< \brief (PIOC) PIO I/O Drive Register */ + #define REG_PIOC_KER (0x400E1320U) /**< \brief (PIOC) Keypad Controller Enable Register */ + #define REG_PIOC_KRCR (0x400E1324U) /**< \brief (PIOC) Keypad Controller Row Column Register */ + #define REG_PIOC_KDR (0x400E1328U) /**< \brief (PIOC) Keypad Controller Debouncing Register */ + #define REG_PIOC_KIER (0x400E1330U) /**< \brief (PIOC) Keypad Controller Interrupt Enable Register */ + #define REG_PIOC_KIDR (0x400E1334U) /**< \brief (PIOC) Keypad Controller Interrupt Disable Register */ + #define REG_PIOC_KIMR (0x400E1338U) /**< \brief (PIOC) Keypad Controller Interrupt Mask Register */ + #define REG_PIOC_KSR (0x400E133CU) /**< \brief (PIOC) Keypad Controller Status Register */ + #define REG_PIOC_KKPR (0x400E1340U) /**< \brief (PIOC) Keypad Controller Key Press Register */ + #define REG_PIOC_KKRR (0x400E1344U) /**< \brief (PIOC) Keypad Controller Key Release Register */ + #define REG_PIOC_PCMR (0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */ + #define REG_PIOC_PCIER (0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */ + #define REG_PIOC_PCIDR (0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */ + #define REG_PIOC_PCIMR (0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */ + #define REG_PIOC_PCISR (0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */ + #define REG_PIOC_PCRHR (0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */ +#else + #define REG_PIOC_PER (*(__O uint32_t*)0x400E1200U) /**< \brief (PIOC) PIO Enable Register */ + #define REG_PIOC_PDR (*(__O uint32_t*)0x400E1204U) /**< \brief (PIOC) PIO Disable Register */ + #define REG_PIOC_PSR (*(__I uint32_t*)0x400E1208U) /**< \brief (PIOC) PIO Status Register */ + #define REG_PIOC_OER (*(__O uint32_t*)0x400E1210U) /**< \brief (PIOC) Output Enable Register */ + #define REG_PIOC_ODR (*(__O uint32_t*)0x400E1214U) /**< \brief (PIOC) Output Disable Register */ + #define REG_PIOC_OSR (*(__I uint32_t*)0x400E1218U) /**< \brief (PIOC) Output Status Register */ + #define REG_PIOC_IFER (*(__O uint32_t*)0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */ + #define REG_PIOC_IFDR (*(__O uint32_t*)0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */ + #define REG_PIOC_IFSR (*(__I uint32_t*)0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */ + #define REG_PIOC_SODR (*(__O uint32_t*)0x400E1230U) /**< \brief (PIOC) Set Output Data Register */ + #define REG_PIOC_CODR (*(__O uint32_t*)0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */ + #define REG_PIOC_ODSR (*(__IO uint32_t*)0x400E1238U) /**< \brief (PIOC) Output Data Status Register */ + #define REG_PIOC_PDSR (*(__I uint32_t*)0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */ + #define REG_PIOC_IER (*(__O uint32_t*)0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */ + #define REG_PIOC_IDR (*(__O uint32_t*)0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */ + #define REG_PIOC_IMR (*(__I uint32_t*)0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */ + #define REG_PIOC_ISR (*(__I uint32_t*)0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */ + #define REG_PIOC_MDER (*(__O uint32_t*)0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */ + #define REG_PIOC_MDDR (*(__O uint32_t*)0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */ + #define REG_PIOC_MDSR (*(__I uint32_t*)0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */ + #define REG_PIOC_PUDR (*(__O uint32_t*)0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */ + #define REG_PIOC_PUER (*(__O uint32_t*)0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */ + #define REG_PIOC_PUSR (*(__I uint32_t*)0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */ + #define REG_PIOC_ABCDSR (*(__IO uint32_t*)0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */ + #define REG_PIOC_IFSCDR (*(__O uint32_t*)0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */ + #define REG_PIOC_IFSCER (*(__O uint32_t*)0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */ + #define REG_PIOC_IFSCSR (*(__I uint32_t*)0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */ + #define REG_PIOC_SCDR (*(__IO uint32_t*)0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */ + #define REG_PIOC_PPDDR (*(__O uint32_t*)0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */ + #define REG_PIOC_PPDER (*(__O uint32_t*)0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */ + #define REG_PIOC_PPDSR (*(__I uint32_t*)0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */ + #define REG_PIOC_OWER (*(__O uint32_t*)0x400E12A0U) /**< \brief (PIOC) Output Write Enable */ + #define REG_PIOC_OWDR (*(__O uint32_t*)0x400E12A4U) /**< \brief (PIOC) Output Write Disable */ + #define REG_PIOC_OWSR (*(__I uint32_t*)0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */ + #define REG_PIOC_AIMER (*(__O uint32_t*)0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */ + #define REG_PIOC_AIMDR (*(__O uint32_t*)0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disable Register */ + #define REG_PIOC_AIMMR (*(__I uint32_t*)0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */ + #define REG_PIOC_ESR (*(__O uint32_t*)0x400E12C0U) /**< \brief (PIOC) Edge Select Register */ + #define REG_PIOC_LSR (*(__O uint32_t*)0x400E12C4U) /**< \brief (PIOC) Level Select Register */ + #define REG_PIOC_ELSR (*(__I uint32_t*)0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */ + #define REG_PIOC_FELLSR (*(__O uint32_t*)0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low-Level Select Register */ + #define REG_PIOC_REHLSR (*(__O uint32_t*)0x400E12D4U) /**< \brief (PIOC) Rising Edge/High-Level Select Register */ + #define REG_PIOC_FRLHSR (*(__I uint32_t*)0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */ + #define REG_PIOC_LOCKSR (*(__I uint32_t*)0x400E12E0U) /**< \brief (PIOC) Lock Status */ + #define REG_PIOC_WPMR (*(__IO uint32_t*)0x400E12E4U) /**< \brief (PIOC) Write Protection Mode Register */ + #define REG_PIOC_WPSR (*(__I uint32_t*)0x400E12E8U) /**< \brief (PIOC) Write Protection Status Register */ + #define REG_PIOC_VERSION (*(__I uint32_t*)0x400E12FCU) /**< \brief (PIOC) Version Register */ + #define REG_PIOC_SCHMITT (*(__IO uint32_t*)0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */ + #define REG_PIOC_DRIVER (*(__IO uint32_t*)0x400E1318U) /**< \brief (PIOC) PIO I/O Drive Register */ + #define REG_PIOC_KER (*(__IO uint32_t*)0x400E1320U) /**< \brief (PIOC) Keypad Controller Enable Register */ + #define REG_PIOC_KRCR (*(__IO uint32_t*)0x400E1324U) /**< \brief (PIOC) Keypad Controller Row Column Register */ + #define REG_PIOC_KDR (*(__IO uint32_t*)0x400E1328U) /**< \brief (PIOC) Keypad Controller Debouncing Register */ + #define REG_PIOC_KIER (*(__O uint32_t*)0x400E1330U) /**< \brief (PIOC) Keypad Controller Interrupt Enable Register */ + #define REG_PIOC_KIDR (*(__O uint32_t*)0x400E1334U) /**< \brief (PIOC) Keypad Controller Interrupt Disable Register */ + #define REG_PIOC_KIMR (*(__I uint32_t*)0x400E1338U) /**< \brief (PIOC) Keypad Controller Interrupt Mask Register */ + #define REG_PIOC_KSR (*(__I uint32_t*)0x400E133CU) /**< \brief (PIOC) Keypad Controller Status Register */ + #define REG_PIOC_KKPR (*(__I uint32_t*)0x400E1340U) /**< \brief (PIOC) Keypad Controller Key Press Register */ + #define REG_PIOC_KKRR (*(__I uint32_t*)0x400E1344U) /**< \brief (PIOC) Keypad Controller Key Release Register */ + #define REG_PIOC_PCMR (*(__IO uint32_t*)0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */ + #define REG_PIOC_PCIER (*(__O uint32_t*)0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */ + #define REG_PIOC_PCIDR (*(__O uint32_t*)0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */ + #define REG_PIOC_PCIMR (*(__I uint32_t*)0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */ + #define REG_PIOC_PCISR (*(__I uint32_t*)0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */ + #define REG_PIOC_PCRHR (*(__I uint32_t*)0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_PIOC_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/piod.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/piod.h new file mode 100644 index 000000000..850bcf04e --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/piod.h @@ -0,0 +1,171 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_PIOD_INSTANCE_ +#define _SAME70_PIOD_INSTANCE_ + +/* ========== Register definition for PIOD peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PIOD_PER (0x400E1400U) /**< \brief (PIOD) PIO Enable Register */ + #define REG_PIOD_PDR (0x400E1404U) /**< \brief (PIOD) PIO Disable Register */ + #define REG_PIOD_PSR (0x400E1408U) /**< \brief (PIOD) PIO Status Register */ + #define REG_PIOD_OER (0x400E1410U) /**< \brief (PIOD) Output Enable Register */ + #define REG_PIOD_ODR (0x400E1414U) /**< \brief (PIOD) Output Disable Register */ + #define REG_PIOD_OSR (0x400E1418U) /**< \brief (PIOD) Output Status Register */ + #define REG_PIOD_IFER (0x400E1420U) /**< \brief (PIOD) Glitch Input Filter Enable Register */ + #define REG_PIOD_IFDR (0x400E1424U) /**< \brief (PIOD) Glitch Input Filter Disable Register */ + #define REG_PIOD_IFSR (0x400E1428U) /**< \brief (PIOD) Glitch Input Filter Status Register */ + #define REG_PIOD_SODR (0x400E1430U) /**< \brief (PIOD) Set Output Data Register */ + #define REG_PIOD_CODR (0x400E1434U) /**< \brief (PIOD) Clear Output Data Register */ + #define REG_PIOD_ODSR (0x400E1438U) /**< \brief (PIOD) Output Data Status Register */ + #define REG_PIOD_PDSR (0x400E143CU) /**< \brief (PIOD) Pin Data Status Register */ + #define REG_PIOD_IER (0x400E1440U) /**< \brief (PIOD) Interrupt Enable Register */ + #define REG_PIOD_IDR (0x400E1444U) /**< \brief (PIOD) Interrupt Disable Register */ + #define REG_PIOD_IMR (0x400E1448U) /**< \brief (PIOD) Interrupt Mask Register */ + #define REG_PIOD_ISR (0x400E144CU) /**< \brief (PIOD) Interrupt Status Register */ + #define REG_PIOD_MDER (0x400E1450U) /**< \brief (PIOD) Multi-driver Enable Register */ + #define REG_PIOD_MDDR (0x400E1454U) /**< \brief (PIOD) Multi-driver Disable Register */ + #define REG_PIOD_MDSR (0x400E1458U) /**< \brief (PIOD) Multi-driver Status Register */ + #define REG_PIOD_PUDR (0x400E1460U) /**< \brief (PIOD) Pull-up Disable Register */ + #define REG_PIOD_PUER (0x400E1464U) /**< \brief (PIOD) Pull-up Enable Register */ + #define REG_PIOD_PUSR (0x400E1468U) /**< \brief (PIOD) Pad Pull-up Status Register */ + #define REG_PIOD_ABCDSR (0x400E1470U) /**< \brief (PIOD) Peripheral Select Register */ + #define REG_PIOD_IFSCDR (0x400E1480U) /**< \brief (PIOD) Input Filter Slow Clock Disable Register */ + #define REG_PIOD_IFSCER (0x400E1484U) /**< \brief (PIOD) Input Filter Slow Clock Enable Register */ + #define REG_PIOD_IFSCSR (0x400E1488U) /**< \brief (PIOD) Input Filter Slow Clock Status Register */ + #define REG_PIOD_SCDR (0x400E148CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */ + #define REG_PIOD_PPDDR (0x400E1490U) /**< \brief (PIOD) Pad Pull-down Disable Register */ + #define REG_PIOD_PPDER (0x400E1494U) /**< \brief (PIOD) Pad Pull-down Enable Register */ + #define REG_PIOD_PPDSR (0x400E1498U) /**< \brief (PIOD) Pad Pull-down Status Register */ + #define REG_PIOD_OWER (0x400E14A0U) /**< \brief (PIOD) Output Write Enable */ + #define REG_PIOD_OWDR (0x400E14A4U) /**< \brief (PIOD) Output Write Disable */ + #define REG_PIOD_OWSR (0x400E14A8U) /**< \brief (PIOD) Output Write Status Register */ + #define REG_PIOD_AIMER (0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */ + #define REG_PIOD_AIMDR (0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Modes Disable Register */ + #define REG_PIOD_AIMMR (0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */ + #define REG_PIOD_ESR (0x400E14C0U) /**< \brief (PIOD) Edge Select Register */ + #define REG_PIOD_LSR (0x400E14C4U) /**< \brief (PIOD) Level Select Register */ + #define REG_PIOD_ELSR (0x400E14C8U) /**< \brief (PIOD) Edge/Level Status Register */ + #define REG_PIOD_FELLSR (0x400E14D0U) /**< \brief (PIOD) Falling Edge/Low-Level Select Register */ + #define REG_PIOD_REHLSR (0x400E14D4U) /**< \brief (PIOD) Rising Edge/High-Level Select Register */ + #define REG_PIOD_FRLHSR (0x400E14D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */ + #define REG_PIOD_LOCKSR (0x400E14E0U) /**< \brief (PIOD) Lock Status */ + #define REG_PIOD_WPMR (0x400E14E4U) /**< \brief (PIOD) Write Protection Mode Register */ + #define REG_PIOD_WPSR (0x400E14E8U) /**< \brief (PIOD) Write Protection Status Register */ + #define REG_PIOD_VERSION (0x400E14FCU) /**< \brief (PIOD) Version Register */ + #define REG_PIOD_SCHMITT (0x400E1500U) /**< \brief (PIOD) Schmitt Trigger Register */ + #define REG_PIOD_DRIVER (0x400E1518U) /**< \brief (PIOD) PIO I/O Drive Register */ + #define REG_PIOD_KER (0x400E1520U) /**< \brief (PIOD) Keypad Controller Enable Register */ + #define REG_PIOD_KRCR (0x400E1524U) /**< \brief (PIOD) Keypad Controller Row Column Register */ + #define REG_PIOD_KDR (0x400E1528U) /**< \brief (PIOD) Keypad Controller Debouncing Register */ + #define REG_PIOD_KIER (0x400E1530U) /**< \brief (PIOD) Keypad Controller Interrupt Enable Register */ + #define REG_PIOD_KIDR (0x400E1534U) /**< \brief (PIOD) Keypad Controller Interrupt Disable Register */ + #define REG_PIOD_KIMR (0x400E1538U) /**< \brief (PIOD) Keypad Controller Interrupt Mask Register */ + #define REG_PIOD_KSR (0x400E153CU) /**< \brief (PIOD) Keypad Controller Status Register */ + #define REG_PIOD_KKPR (0x400E1540U) /**< \brief (PIOD) Keypad Controller Key Press Register */ + #define REG_PIOD_KKRR (0x400E1544U) /**< \brief (PIOD) Keypad Controller Key Release Register */ + #define REG_PIOD_PCMR (0x400E1550U) /**< \brief (PIOD) Parallel Capture Mode Register */ + #define REG_PIOD_PCIER (0x400E1554U) /**< \brief (PIOD) Parallel Capture Interrupt Enable Register */ + #define REG_PIOD_PCIDR (0x400E1558U) /**< \brief (PIOD) Parallel Capture Interrupt Disable Register */ + #define REG_PIOD_PCIMR (0x400E155CU) /**< \brief (PIOD) Parallel Capture Interrupt Mask Register */ + #define REG_PIOD_PCISR (0x400E1560U) /**< \brief (PIOD) Parallel Capture Interrupt Status Register */ + #define REG_PIOD_PCRHR (0x400E1564U) /**< \brief (PIOD) Parallel Capture Reception Holding Register */ +#else + #define REG_PIOD_PER (*(__O uint32_t*)0x400E1400U) /**< \brief (PIOD) PIO Enable Register */ + #define REG_PIOD_PDR (*(__O uint32_t*)0x400E1404U) /**< \brief (PIOD) PIO Disable Register */ + #define REG_PIOD_PSR (*(__I uint32_t*)0x400E1408U) /**< \brief (PIOD) PIO Status Register */ + #define REG_PIOD_OER (*(__O uint32_t*)0x400E1410U) /**< \brief (PIOD) Output Enable Register */ + #define REG_PIOD_ODR (*(__O uint32_t*)0x400E1414U) /**< \brief (PIOD) Output Disable Register */ + #define REG_PIOD_OSR (*(__I uint32_t*)0x400E1418U) /**< \brief (PIOD) Output Status Register */ + #define REG_PIOD_IFER (*(__O uint32_t*)0x400E1420U) /**< \brief (PIOD) Glitch Input Filter Enable Register */ + #define REG_PIOD_IFDR (*(__O uint32_t*)0x400E1424U) /**< \brief (PIOD) Glitch Input Filter Disable Register */ + #define REG_PIOD_IFSR (*(__I uint32_t*)0x400E1428U) /**< \brief (PIOD) Glitch Input Filter Status Register */ + #define REG_PIOD_SODR (*(__O uint32_t*)0x400E1430U) /**< \brief (PIOD) Set Output Data Register */ + #define REG_PIOD_CODR (*(__O uint32_t*)0x400E1434U) /**< \brief (PIOD) Clear Output Data Register */ + #define REG_PIOD_ODSR (*(__IO uint32_t*)0x400E1438U) /**< \brief (PIOD) Output Data Status Register */ + #define REG_PIOD_PDSR (*(__I uint32_t*)0x400E143CU) /**< \brief (PIOD) Pin Data Status Register */ + #define REG_PIOD_IER (*(__O uint32_t*)0x400E1440U) /**< \brief (PIOD) Interrupt Enable Register */ + #define REG_PIOD_IDR (*(__O uint32_t*)0x400E1444U) /**< \brief (PIOD) Interrupt Disable Register */ + #define REG_PIOD_IMR (*(__I uint32_t*)0x400E1448U) /**< \brief (PIOD) Interrupt Mask Register */ + #define REG_PIOD_ISR (*(__I uint32_t*)0x400E144CU) /**< \brief (PIOD) Interrupt Status Register */ + #define REG_PIOD_MDER (*(__O uint32_t*)0x400E1450U) /**< \brief (PIOD) Multi-driver Enable Register */ + #define REG_PIOD_MDDR (*(__O uint32_t*)0x400E1454U) /**< \brief (PIOD) Multi-driver Disable Register */ + #define REG_PIOD_MDSR (*(__I uint32_t*)0x400E1458U) /**< \brief (PIOD) Multi-driver Status Register */ + #define REG_PIOD_PUDR (*(__O uint32_t*)0x400E1460U) /**< \brief (PIOD) Pull-up Disable Register */ + #define REG_PIOD_PUER (*(__O uint32_t*)0x400E1464U) /**< \brief (PIOD) Pull-up Enable Register */ + #define REG_PIOD_PUSR (*(__I uint32_t*)0x400E1468U) /**< \brief (PIOD) Pad Pull-up Status Register */ + #define REG_PIOD_ABCDSR (*(__IO uint32_t*)0x400E1470U) /**< \brief (PIOD) Peripheral Select Register */ + #define REG_PIOD_IFSCDR (*(__O uint32_t*)0x400E1480U) /**< \brief (PIOD) Input Filter Slow Clock Disable Register */ + #define REG_PIOD_IFSCER (*(__O uint32_t*)0x400E1484U) /**< \brief (PIOD) Input Filter Slow Clock Enable Register */ + #define REG_PIOD_IFSCSR (*(__I uint32_t*)0x400E1488U) /**< \brief (PIOD) Input Filter Slow Clock Status Register */ + #define REG_PIOD_SCDR (*(__IO uint32_t*)0x400E148CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */ + #define REG_PIOD_PPDDR (*(__O uint32_t*)0x400E1490U) /**< \brief (PIOD) Pad Pull-down Disable Register */ + #define REG_PIOD_PPDER (*(__O uint32_t*)0x400E1494U) /**< \brief (PIOD) Pad Pull-down Enable Register */ + #define REG_PIOD_PPDSR (*(__I uint32_t*)0x400E1498U) /**< \brief (PIOD) Pad Pull-down Status Register */ + #define REG_PIOD_OWER (*(__O uint32_t*)0x400E14A0U) /**< \brief (PIOD) Output Write Enable */ + #define REG_PIOD_OWDR (*(__O uint32_t*)0x400E14A4U) /**< \brief (PIOD) Output Write Disable */ + #define REG_PIOD_OWSR (*(__I uint32_t*)0x400E14A8U) /**< \brief (PIOD) Output Write Status Register */ + #define REG_PIOD_AIMER (*(__O uint32_t*)0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */ + #define REG_PIOD_AIMDR (*(__O uint32_t*)0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Modes Disable Register */ + #define REG_PIOD_AIMMR (*(__I uint32_t*)0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */ + #define REG_PIOD_ESR (*(__O uint32_t*)0x400E14C0U) /**< \brief (PIOD) Edge Select Register */ + #define REG_PIOD_LSR (*(__O uint32_t*)0x400E14C4U) /**< \brief (PIOD) Level Select Register */ + #define REG_PIOD_ELSR (*(__I uint32_t*)0x400E14C8U) /**< \brief (PIOD) Edge/Level Status Register */ + #define REG_PIOD_FELLSR (*(__O uint32_t*)0x400E14D0U) /**< \brief (PIOD) Falling Edge/Low-Level Select Register */ + #define REG_PIOD_REHLSR (*(__O uint32_t*)0x400E14D4U) /**< \brief (PIOD) Rising Edge/High-Level Select Register */ + #define REG_PIOD_FRLHSR (*(__I uint32_t*)0x400E14D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */ + #define REG_PIOD_LOCKSR (*(__I uint32_t*)0x400E14E0U) /**< \brief (PIOD) Lock Status */ + #define REG_PIOD_WPMR (*(__IO uint32_t*)0x400E14E4U) /**< \brief (PIOD) Write Protection Mode Register */ + #define REG_PIOD_WPSR (*(__I uint32_t*)0x400E14E8U) /**< \brief (PIOD) Write Protection Status Register */ + #define REG_PIOD_VERSION (*(__I uint32_t*)0x400E14FCU) /**< \brief (PIOD) Version Register */ + #define REG_PIOD_SCHMITT (*(__IO uint32_t*)0x400E1500U) /**< \brief (PIOD) Schmitt Trigger Register */ + #define REG_PIOD_DRIVER (*(__IO uint32_t*)0x400E1518U) /**< \brief (PIOD) PIO I/O Drive Register */ + #define REG_PIOD_KER (*(__IO uint32_t*)0x400E1520U) /**< \brief (PIOD) Keypad Controller Enable Register */ + #define REG_PIOD_KRCR (*(__IO uint32_t*)0x400E1524U) /**< \brief (PIOD) Keypad Controller Row Column Register */ + #define REG_PIOD_KDR (*(__IO uint32_t*)0x400E1528U) /**< \brief (PIOD) Keypad Controller Debouncing Register */ + #define REG_PIOD_KIER (*(__O uint32_t*)0x400E1530U) /**< \brief (PIOD) Keypad Controller Interrupt Enable Register */ + #define REG_PIOD_KIDR (*(__O uint32_t*)0x400E1534U) /**< \brief (PIOD) Keypad Controller Interrupt Disable Register */ + #define REG_PIOD_KIMR (*(__I uint32_t*)0x400E1538U) /**< \brief (PIOD) Keypad Controller Interrupt Mask Register */ + #define REG_PIOD_KSR (*(__I uint32_t*)0x400E153CU) /**< \brief (PIOD) Keypad Controller Status Register */ + #define REG_PIOD_KKPR (*(__I uint32_t*)0x400E1540U) /**< \brief (PIOD) Keypad Controller Key Press Register */ + #define REG_PIOD_KKRR (*(__I uint32_t*)0x400E1544U) /**< \brief (PIOD) Keypad Controller Key Release Register */ + #define REG_PIOD_PCMR (*(__IO uint32_t*)0x400E1550U) /**< \brief (PIOD) Parallel Capture Mode Register */ + #define REG_PIOD_PCIER (*(__O uint32_t*)0x400E1554U) /**< \brief (PIOD) Parallel Capture Interrupt Enable Register */ + #define REG_PIOD_PCIDR (*(__O uint32_t*)0x400E1558U) /**< \brief (PIOD) Parallel Capture Interrupt Disable Register */ + #define REG_PIOD_PCIMR (*(__I uint32_t*)0x400E155CU) /**< \brief (PIOD) Parallel Capture Interrupt Mask Register */ + #define REG_PIOD_PCISR (*(__I uint32_t*)0x400E1560U) /**< \brief (PIOD) Parallel Capture Interrupt Status Register */ + #define REG_PIOD_PCRHR (*(__I uint32_t*)0x400E1564U) /**< \brief (PIOD) Parallel Capture Reception Holding Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_PIOD_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/pioe.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/pioe.h new file mode 100644 index 000000000..5291dac73 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/pioe.h @@ -0,0 +1,171 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_PIOE_INSTANCE_ +#define _SAME70_PIOE_INSTANCE_ + +/* ========== Register definition for PIOE peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PIOE_PER (0x400E1600U) /**< \brief (PIOE) PIO Enable Register */ + #define REG_PIOE_PDR (0x400E1604U) /**< \brief (PIOE) PIO Disable Register */ + #define REG_PIOE_PSR (0x400E1608U) /**< \brief (PIOE) PIO Status Register */ + #define REG_PIOE_OER (0x400E1610U) /**< \brief (PIOE) Output Enable Register */ + #define REG_PIOE_ODR (0x400E1614U) /**< \brief (PIOE) Output Disable Register */ + #define REG_PIOE_OSR (0x400E1618U) /**< \brief (PIOE) Output Status Register */ + #define REG_PIOE_IFER (0x400E1620U) /**< \brief (PIOE) Glitch Input Filter Enable Register */ + #define REG_PIOE_IFDR (0x400E1624U) /**< \brief (PIOE) Glitch Input Filter Disable Register */ + #define REG_PIOE_IFSR (0x400E1628U) /**< \brief (PIOE) Glitch Input Filter Status Register */ + #define REG_PIOE_SODR (0x400E1630U) /**< \brief (PIOE) Set Output Data Register */ + #define REG_PIOE_CODR (0x400E1634U) /**< \brief (PIOE) Clear Output Data Register */ + #define REG_PIOE_ODSR (0x400E1638U) /**< \brief (PIOE) Output Data Status Register */ + #define REG_PIOE_PDSR (0x400E163CU) /**< \brief (PIOE) Pin Data Status Register */ + #define REG_PIOE_IER (0x400E1640U) /**< \brief (PIOE) Interrupt Enable Register */ + #define REG_PIOE_IDR (0x400E1644U) /**< \brief (PIOE) Interrupt Disable Register */ + #define REG_PIOE_IMR (0x400E1648U) /**< \brief (PIOE) Interrupt Mask Register */ + #define REG_PIOE_ISR (0x400E164CU) /**< \brief (PIOE) Interrupt Status Register */ + #define REG_PIOE_MDER (0x400E1650U) /**< \brief (PIOE) Multi-driver Enable Register */ + #define REG_PIOE_MDDR (0x400E1654U) /**< \brief (PIOE) Multi-driver Disable Register */ + #define REG_PIOE_MDSR (0x400E1658U) /**< \brief (PIOE) Multi-driver Status Register */ + #define REG_PIOE_PUDR (0x400E1660U) /**< \brief (PIOE) Pull-up Disable Register */ + #define REG_PIOE_PUER (0x400E1664U) /**< \brief (PIOE) Pull-up Enable Register */ + #define REG_PIOE_PUSR (0x400E1668U) /**< \brief (PIOE) Pad Pull-up Status Register */ + #define REG_PIOE_ABCDSR (0x400E1670U) /**< \brief (PIOE) Peripheral Select Register */ + #define REG_PIOE_IFSCDR (0x400E1680U) /**< \brief (PIOE) Input Filter Slow Clock Disable Register */ + #define REG_PIOE_IFSCER (0x400E1684U) /**< \brief (PIOE) Input Filter Slow Clock Enable Register */ + #define REG_PIOE_IFSCSR (0x400E1688U) /**< \brief (PIOE) Input Filter Slow Clock Status Register */ + #define REG_PIOE_SCDR (0x400E168CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */ + #define REG_PIOE_PPDDR (0x400E1690U) /**< \brief (PIOE) Pad Pull-down Disable Register */ + #define REG_PIOE_PPDER (0x400E1694U) /**< \brief (PIOE) Pad Pull-down Enable Register */ + #define REG_PIOE_PPDSR (0x400E1698U) /**< \brief (PIOE) Pad Pull-down Status Register */ + #define REG_PIOE_OWER (0x400E16A0U) /**< \brief (PIOE) Output Write Enable */ + #define REG_PIOE_OWDR (0x400E16A4U) /**< \brief (PIOE) Output Write Disable */ + #define REG_PIOE_OWSR (0x400E16A8U) /**< \brief (PIOE) Output Write Status Register */ + #define REG_PIOE_AIMER (0x400E16B0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */ + #define REG_PIOE_AIMDR (0x400E16B4U) /**< \brief (PIOE) Additional Interrupt Modes Disable Register */ + #define REG_PIOE_AIMMR (0x400E16B8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */ + #define REG_PIOE_ESR (0x400E16C0U) /**< \brief (PIOE) Edge Select Register */ + #define REG_PIOE_LSR (0x400E16C4U) /**< \brief (PIOE) Level Select Register */ + #define REG_PIOE_ELSR (0x400E16C8U) /**< \brief (PIOE) Edge/Level Status Register */ + #define REG_PIOE_FELLSR (0x400E16D0U) /**< \brief (PIOE) Falling Edge/Low-Level Select Register */ + #define REG_PIOE_REHLSR (0x400E16D4U) /**< \brief (PIOE) Rising Edge/High-Level Select Register */ + #define REG_PIOE_FRLHSR (0x400E16D8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */ + #define REG_PIOE_LOCKSR (0x400E16E0U) /**< \brief (PIOE) Lock Status */ + #define REG_PIOE_WPMR (0x400E16E4U) /**< \brief (PIOE) Write Protection Mode Register */ + #define REG_PIOE_WPSR (0x400E16E8U) /**< \brief (PIOE) Write Protection Status Register */ + #define REG_PIOE_VERSION (0x400E16FCU) /**< \brief (PIOE) Version Register */ + #define REG_PIOE_SCHMITT (0x400E1700U) /**< \brief (PIOE) Schmitt Trigger Register */ + #define REG_PIOE_DRIVER (0x400E1718U) /**< \brief (PIOE) PIO I/O Drive Register */ + #define REG_PIOE_KER (0x400E1720U) /**< \brief (PIOE) Keypad Controller Enable Register */ + #define REG_PIOE_KRCR (0x400E1724U) /**< \brief (PIOE) Keypad Controller Row Column Register */ + #define REG_PIOE_KDR (0x400E1728U) /**< \brief (PIOE) Keypad Controller Debouncing Register */ + #define REG_PIOE_KIER (0x400E1730U) /**< \brief (PIOE) Keypad Controller Interrupt Enable Register */ + #define REG_PIOE_KIDR (0x400E1734U) /**< \brief (PIOE) Keypad Controller Interrupt Disable Register */ + #define REG_PIOE_KIMR (0x400E1738U) /**< \brief (PIOE) Keypad Controller Interrupt Mask Register */ + #define REG_PIOE_KSR (0x400E173CU) /**< \brief (PIOE) Keypad Controller Status Register */ + #define REG_PIOE_KKPR (0x400E1740U) /**< \brief (PIOE) Keypad Controller Key Press Register */ + #define REG_PIOE_KKRR (0x400E1744U) /**< \brief (PIOE) Keypad Controller Key Release Register */ + #define REG_PIOE_PCMR (0x400E1750U) /**< \brief (PIOE) Parallel Capture Mode Register */ + #define REG_PIOE_PCIER (0x400E1754U) /**< \brief (PIOE) Parallel Capture Interrupt Enable Register */ + #define REG_PIOE_PCIDR (0x400E1758U) /**< \brief (PIOE) Parallel Capture Interrupt Disable Register */ + #define REG_PIOE_PCIMR (0x400E175CU) /**< \brief (PIOE) Parallel Capture Interrupt Mask Register */ + #define REG_PIOE_PCISR (0x400E1760U) /**< \brief (PIOE) Parallel Capture Interrupt Status Register */ + #define REG_PIOE_PCRHR (0x400E1764U) /**< \brief (PIOE) Parallel Capture Reception Holding Register */ +#else + #define REG_PIOE_PER (*(__O uint32_t*)0x400E1600U) /**< \brief (PIOE) PIO Enable Register */ + #define REG_PIOE_PDR (*(__O uint32_t*)0x400E1604U) /**< \brief (PIOE) PIO Disable Register */ + #define REG_PIOE_PSR (*(__I uint32_t*)0x400E1608U) /**< \brief (PIOE) PIO Status Register */ + #define REG_PIOE_OER (*(__O uint32_t*)0x400E1610U) /**< \brief (PIOE) Output Enable Register */ + #define REG_PIOE_ODR (*(__O uint32_t*)0x400E1614U) /**< \brief (PIOE) Output Disable Register */ + #define REG_PIOE_OSR (*(__I uint32_t*)0x400E1618U) /**< \brief (PIOE) Output Status Register */ + #define REG_PIOE_IFER (*(__O uint32_t*)0x400E1620U) /**< \brief (PIOE) Glitch Input Filter Enable Register */ + #define REG_PIOE_IFDR (*(__O uint32_t*)0x400E1624U) /**< \brief (PIOE) Glitch Input Filter Disable Register */ + #define REG_PIOE_IFSR (*(__I uint32_t*)0x400E1628U) /**< \brief (PIOE) Glitch Input Filter Status Register */ + #define REG_PIOE_SODR (*(__O uint32_t*)0x400E1630U) /**< \brief (PIOE) Set Output Data Register */ + #define REG_PIOE_CODR (*(__O uint32_t*)0x400E1634U) /**< \brief (PIOE) Clear Output Data Register */ + #define REG_PIOE_ODSR (*(__IO uint32_t*)0x400E1638U) /**< \brief (PIOE) Output Data Status Register */ + #define REG_PIOE_PDSR (*(__I uint32_t*)0x400E163CU) /**< \brief (PIOE) Pin Data Status Register */ + #define REG_PIOE_IER (*(__O uint32_t*)0x400E1640U) /**< \brief (PIOE) Interrupt Enable Register */ + #define REG_PIOE_IDR (*(__O uint32_t*)0x400E1644U) /**< \brief (PIOE) Interrupt Disable Register */ + #define REG_PIOE_IMR (*(__I uint32_t*)0x400E1648U) /**< \brief (PIOE) Interrupt Mask Register */ + #define REG_PIOE_ISR (*(__I uint32_t*)0x400E164CU) /**< \brief (PIOE) Interrupt Status Register */ + #define REG_PIOE_MDER (*(__O uint32_t*)0x400E1650U) /**< \brief (PIOE) Multi-driver Enable Register */ + #define REG_PIOE_MDDR (*(__O uint32_t*)0x400E1654U) /**< \brief (PIOE) Multi-driver Disable Register */ + #define REG_PIOE_MDSR (*(__I uint32_t*)0x400E1658U) /**< \brief (PIOE) Multi-driver Status Register */ + #define REG_PIOE_PUDR (*(__O uint32_t*)0x400E1660U) /**< \brief (PIOE) Pull-up Disable Register */ + #define REG_PIOE_PUER (*(__O uint32_t*)0x400E1664U) /**< \brief (PIOE) Pull-up Enable Register */ + #define REG_PIOE_PUSR (*(__I uint32_t*)0x400E1668U) /**< \brief (PIOE) Pad Pull-up Status Register */ + #define REG_PIOE_ABCDSR (*(__IO uint32_t*)0x400E1670U) /**< \brief (PIOE) Peripheral Select Register */ + #define REG_PIOE_IFSCDR (*(__O uint32_t*)0x400E1680U) /**< \brief (PIOE) Input Filter Slow Clock Disable Register */ + #define REG_PIOE_IFSCER (*(__O uint32_t*)0x400E1684U) /**< \brief (PIOE) Input Filter Slow Clock Enable Register */ + #define REG_PIOE_IFSCSR (*(__I uint32_t*)0x400E1688U) /**< \brief (PIOE) Input Filter Slow Clock Status Register */ + #define REG_PIOE_SCDR (*(__IO uint32_t*)0x400E168CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */ + #define REG_PIOE_PPDDR (*(__O uint32_t*)0x400E1690U) /**< \brief (PIOE) Pad Pull-down Disable Register */ + #define REG_PIOE_PPDER (*(__O uint32_t*)0x400E1694U) /**< \brief (PIOE) Pad Pull-down Enable Register */ + #define REG_PIOE_PPDSR (*(__I uint32_t*)0x400E1698U) /**< \brief (PIOE) Pad Pull-down Status Register */ + #define REG_PIOE_OWER (*(__O uint32_t*)0x400E16A0U) /**< \brief (PIOE) Output Write Enable */ + #define REG_PIOE_OWDR (*(__O uint32_t*)0x400E16A4U) /**< \brief (PIOE) Output Write Disable */ + #define REG_PIOE_OWSR (*(__I uint32_t*)0x400E16A8U) /**< \brief (PIOE) Output Write Status Register */ + #define REG_PIOE_AIMER (*(__O uint32_t*)0x400E16B0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */ + #define REG_PIOE_AIMDR (*(__O uint32_t*)0x400E16B4U) /**< \brief (PIOE) Additional Interrupt Modes Disable Register */ + #define REG_PIOE_AIMMR (*(__I uint32_t*)0x400E16B8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */ + #define REG_PIOE_ESR (*(__O uint32_t*)0x400E16C0U) /**< \brief (PIOE) Edge Select Register */ + #define REG_PIOE_LSR (*(__O uint32_t*)0x400E16C4U) /**< \brief (PIOE) Level Select Register */ + #define REG_PIOE_ELSR (*(__I uint32_t*)0x400E16C8U) /**< \brief (PIOE) Edge/Level Status Register */ + #define REG_PIOE_FELLSR (*(__O uint32_t*)0x400E16D0U) /**< \brief (PIOE) Falling Edge/Low-Level Select Register */ + #define REG_PIOE_REHLSR (*(__O uint32_t*)0x400E16D4U) /**< \brief (PIOE) Rising Edge/High-Level Select Register */ + #define REG_PIOE_FRLHSR (*(__I uint32_t*)0x400E16D8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */ + #define REG_PIOE_LOCKSR (*(__I uint32_t*)0x400E16E0U) /**< \brief (PIOE) Lock Status */ + #define REG_PIOE_WPMR (*(__IO uint32_t*)0x400E16E4U) /**< \brief (PIOE) Write Protection Mode Register */ + #define REG_PIOE_WPSR (*(__I uint32_t*)0x400E16E8U) /**< \brief (PIOE) Write Protection Status Register */ + #define REG_PIOE_VERSION (*(__I uint32_t*)0x400E16FCU) /**< \brief (PIOE) Version Register */ + #define REG_PIOE_SCHMITT (*(__IO uint32_t*)0x400E1700U) /**< \brief (PIOE) Schmitt Trigger Register */ + #define REG_PIOE_DRIVER (*(__IO uint32_t*)0x400E1718U) /**< \brief (PIOE) PIO I/O Drive Register */ + #define REG_PIOE_KER (*(__IO uint32_t*)0x400E1720U) /**< \brief (PIOE) Keypad Controller Enable Register */ + #define REG_PIOE_KRCR (*(__IO uint32_t*)0x400E1724U) /**< \brief (PIOE) Keypad Controller Row Column Register */ + #define REG_PIOE_KDR (*(__IO uint32_t*)0x400E1728U) /**< \brief (PIOE) Keypad Controller Debouncing Register */ + #define REG_PIOE_KIER (*(__O uint32_t*)0x400E1730U) /**< \brief (PIOE) Keypad Controller Interrupt Enable Register */ + #define REG_PIOE_KIDR (*(__O uint32_t*)0x400E1734U) /**< \brief (PIOE) Keypad Controller Interrupt Disable Register */ + #define REG_PIOE_KIMR (*(__I uint32_t*)0x400E1738U) /**< \brief (PIOE) Keypad Controller Interrupt Mask Register */ + #define REG_PIOE_KSR (*(__I uint32_t*)0x400E173CU) /**< \brief (PIOE) Keypad Controller Status Register */ + #define REG_PIOE_KKPR (*(__I uint32_t*)0x400E1740U) /**< \brief (PIOE) Keypad Controller Key Press Register */ + #define REG_PIOE_KKRR (*(__I uint32_t*)0x400E1744U) /**< \brief (PIOE) Keypad Controller Key Release Register */ + #define REG_PIOE_PCMR (*(__IO uint32_t*)0x400E1750U) /**< \brief (PIOE) Parallel Capture Mode Register */ + #define REG_PIOE_PCIER (*(__O uint32_t*)0x400E1754U) /**< \brief (PIOE) Parallel Capture Interrupt Enable Register */ + #define REG_PIOE_PCIDR (*(__O uint32_t*)0x400E1758U) /**< \brief (PIOE) Parallel Capture Interrupt Disable Register */ + #define REG_PIOE_PCIMR (*(__I uint32_t*)0x400E175CU) /**< \brief (PIOE) Parallel Capture Interrupt Mask Register */ + #define REG_PIOE_PCISR (*(__I uint32_t*)0x400E1760U) /**< \brief (PIOE) Parallel Capture Interrupt Status Register */ + #define REG_PIOE_PCRHR (*(__I uint32_t*)0x400E1764U) /**< \brief (PIOE) Parallel Capture Reception Holding Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_PIOE_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/pmc.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/pmc.h new file mode 100644 index 000000000..540942172 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/pmc.h @@ -0,0 +1,123 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_PMC_INSTANCE_ +#define _SAME70_PMC_INSTANCE_ + +/* ========== Register definition for PMC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PMC_SCER (0x400E0600U) /**< \brief (PMC) System Clock Enable Register */ + #define REG_PMC_SCDR (0x400E0604U) /**< \brief (PMC) System Clock Disable Register */ + #define REG_PMC_SCSR (0x400E0608U) /**< \brief (PMC) System Clock Status Register */ + #define REG_PMC_PCER0 (0x400E0610U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ + #define REG_PMC_PCDR0 (0x400E0614U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ + #define REG_PMC_PCSR0 (0x400E0618U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ + #define REG_CKGR_UCKR (0x400E061CU) /**< \brief (PMC) UTMI Clock Register */ + #define REG_CKGR_MOR (0x400E0620U) /**< \brief (PMC) Main Oscillator Register */ + #define REG_CKGR_MCFR (0x400E0624U) /**< \brief (PMC) Main Clock Frequency Register */ + #define REG_CKGR_PLLAR (0x400E0628U) /**< \brief (PMC) PLLA Register */ + #define REG_PMC_MCKR (0x400E0630U) /**< \brief (PMC) Master Clock Register */ + #define REG_PMC_USB (0x400E0638U) /**< \brief (PMC) USB Clock Register */ + #define REG_PMC_PCK (0x400E0640U) /**< \brief (PMC) Programmable Clock 0 Register */ + #define REG_PMC_IER (0x400E0660U) /**< \brief (PMC) Interrupt Enable Register */ + #define REG_PMC_IDR (0x400E0664U) /**< \brief (PMC) Interrupt Disable Register */ + #define REG_PMC_SR (0x400E0668U) /**< \brief (PMC) Status Register */ + #define REG_PMC_IMR (0x400E066CU) /**< \brief (PMC) Interrupt Mask Register */ + #define REG_PMC_FSMR (0x400E0670U) /**< \brief (PMC) Fast Startup Mode Register */ + #define REG_PMC_FSPR (0x400E0674U) /**< \brief (PMC) Fast Startup Polarity Register */ + #define REG_PMC_FOCR (0x400E0678U) /**< \brief (PMC) Fault Output Clear Register */ + #define REG_PMC_WPMR (0x400E06E4U) /**< \brief (PMC) Write Protection Mode Register */ + #define REG_PMC_WPSR (0x400E06E8U) /**< \brief (PMC) Write Protection Status Register */ + #define REG_PMC_VERSION (0x400E06FCU) /**< \brief (PMC) Version Register */ + #define REG_PMC_PCER1 (0x400E0700U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */ + #define REG_PMC_PCDR1 (0x400E0704U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ + #define REG_PMC_PCSR1 (0x400E0708U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ + #define REG_PMC_PCR (0x400E070CU) /**< \brief (PMC) Peripheral Control Register */ + #define REG_PMC_OCR (0x400E0710U) /**< \brief (PMC) Oscillator Calibration Register */ + #define REG_PMC_SLPWK_ER0 (0x400E0714U) /**< \brief (PMC) SleepWalking Enable Register 0 */ + #define REG_PMC_SLPWK_DR0 (0x400E0718U) /**< \brief (PMC) SleepWalking Disable Register 0 */ + #define REG_PMC_SLPWK_SR0 (0x400E071CU) /**< \brief (PMC) SleepWalking Status Register 0 */ + #define REG_PMC_SLPWK_ASR0 (0x400E0720U) /**< \brief (PMC) SleepWalking Activity Status Register 0 */ + #define REG_PMC_PMMR (0x400E0730U) /**< \brief (PMC) PLL Maximum Multiplier Value Register */ + #define REG_PMC_SLPWK_ER1 (0x400E0734U) /**< \brief (PMC) SleepWalking Enable Register 1 */ + #define REG_PMC_SLPWK_DR1 (0x400E0738U) /**< \brief (PMC) SleepWalking Disable Register 1 */ + #define REG_PMC_SLPWK_SR1 (0x400E073CU) /**< \brief (PMC) SleepWalking Status Register 1 */ + #define REG_PMC_SLPWK_ASR1 (0x400E0740U) /**< \brief (PMC) SleepWalking Activity Status Register 1 */ + #define REG_PMC_SLPWK_AIPR (0x400E0744U) /**< \brief (PMC) SleepWalking Activity In Progress Register */ + #define REG_PMC_APLLACR (0x400E0758U) /**< \brief (PMC) Audio PLL Analog Configuration Register */ + #define REG_PMC_WMST (0x400E075CU) /**< \brief (PMC) Wait Mode Startup Time Register */ +#else + #define REG_PMC_SCER (*(__O uint32_t*)0x400E0600U) /**< \brief (PMC) System Clock Enable Register */ + #define REG_PMC_SCDR (*(__O uint32_t*)0x400E0604U) /**< \brief (PMC) System Clock Disable Register */ + #define REG_PMC_SCSR (*(__I uint32_t*)0x400E0608U) /**< \brief (PMC) System Clock Status Register */ + #define REG_PMC_PCER0 (*(__O uint32_t*)0x400E0610U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ + #define REG_PMC_PCDR0 (*(__O uint32_t*)0x400E0614U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ + #define REG_PMC_PCSR0 (*(__I uint32_t*)0x400E0618U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ + #define REG_CKGR_UCKR (*(__IO uint32_t*)0x400E061CU) /**< \brief (PMC) UTMI Clock Register */ + #define REG_CKGR_MOR (*(__IO uint32_t*)0x400E0620U) /**< \brief (PMC) Main Oscillator Register */ + #define REG_CKGR_MCFR (*(__IO uint32_t*)0x400E0624U) /**< \brief (PMC) Main Clock Frequency Register */ + #define REG_CKGR_PLLAR (*(__IO uint32_t*)0x400E0628U) /**< \brief (PMC) PLLA Register */ + #define REG_PMC_MCKR (*(__IO uint32_t*)0x400E0630U) /**< \brief (PMC) Master Clock Register */ + #define REG_PMC_USB (*(__IO uint32_t*)0x400E0638U) /**< \brief (PMC) USB Clock Register */ + #define REG_PMC_PCK (*(__IO uint32_t*)0x400E0640U) /**< \brief (PMC) Programmable Clock 0 Register */ + #define REG_PMC_IER (*(__O uint32_t*)0x400E0660U) /**< \brief (PMC) Interrupt Enable Register */ + #define REG_PMC_IDR (*(__O uint32_t*)0x400E0664U) /**< \brief (PMC) Interrupt Disable Register */ + #define REG_PMC_SR (*(__I uint32_t*)0x400E0668U) /**< \brief (PMC) Status Register */ + #define REG_PMC_IMR (*(__I uint32_t*)0x400E066CU) /**< \brief (PMC) Interrupt Mask Register */ + #define REG_PMC_FSMR (*(__IO uint32_t*)0x400E0670U) /**< \brief (PMC) Fast Startup Mode Register */ + #define REG_PMC_FSPR (*(__IO uint32_t*)0x400E0674U) /**< \brief (PMC) Fast Startup Polarity Register */ + #define REG_PMC_FOCR (*(__O uint32_t*)0x400E0678U) /**< \brief (PMC) Fault Output Clear Register */ + #define REG_PMC_WPMR (*(__IO uint32_t*)0x400E06E4U) /**< \brief (PMC) Write Protection Mode Register */ + #define REG_PMC_WPSR (*(__I uint32_t*)0x400E06E8U) /**< \brief (PMC) Write Protection Status Register */ + #define REG_PMC_VERSION (*(__I uint32_t*)0x400E06FCU) /**< \brief (PMC) Version Register */ + #define REG_PMC_PCER1 (*(__O uint32_t*)0x400E0700U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */ + #define REG_PMC_PCDR1 (*(__O uint32_t*)0x400E0704U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ + #define REG_PMC_PCSR1 (*(__I uint32_t*)0x400E0708U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ + #define REG_PMC_PCR (*(__IO uint32_t*)0x400E070CU) /**< \brief (PMC) Peripheral Control Register */ + #define REG_PMC_OCR (*(__IO uint32_t*)0x400E0710U) /**< \brief (PMC) Oscillator Calibration Register */ + #define REG_PMC_SLPWK_ER0 (*(__O uint32_t*)0x400E0714U) /**< \brief (PMC) SleepWalking Enable Register 0 */ + #define REG_PMC_SLPWK_DR0 (*(__O uint32_t*)0x400E0718U) /**< \brief (PMC) SleepWalking Disable Register 0 */ + #define REG_PMC_SLPWK_SR0 (*(__I uint32_t*)0x400E071CU) /**< \brief (PMC) SleepWalking Status Register 0 */ + #define REG_PMC_SLPWK_ASR0 (*(__I uint32_t*)0x400E0720U) /**< \brief (PMC) SleepWalking Activity Status Register 0 */ + #define REG_PMC_PMMR (*(__IO uint32_t*)0x400E0730U) /**< \brief (PMC) PLL Maximum Multiplier Value Register */ + #define REG_PMC_SLPWK_ER1 (*(__O uint32_t*)0x400E0734U) /**< \brief (PMC) SleepWalking Enable Register 1 */ + #define REG_PMC_SLPWK_DR1 (*(__O uint32_t*)0x400E0738U) /**< \brief (PMC) SleepWalking Disable Register 1 */ + #define REG_PMC_SLPWK_SR1 (*(__I uint32_t*)0x400E073CU) /**< \brief (PMC) SleepWalking Status Register 1 */ + #define REG_PMC_SLPWK_ASR1 (*(__I uint32_t*)0x400E0740U) /**< \brief (PMC) SleepWalking Activity Status Register 1 */ + #define REG_PMC_SLPWK_AIPR (*(__I uint32_t*)0x400E0744U) /**< \brief (PMC) SleepWalking Activity In Progress Register */ + #define REG_PMC_APLLACR (*(__IO uint32_t*)0x400E0758U) /**< \brief (PMC) Audio PLL Analog Configuration Register */ + #define REG_PMC_WMST (*(__IO uint32_t*)0x400E075CU) /**< \brief (PMC) Wait Mode Startup Time Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_PMC_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/pwm0.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/pwm0.h new file mode 100644 index 000000000..27c1b9061 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/pwm0.h @@ -0,0 +1,259 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_PWM0_INSTANCE_ +#define _SAME70_PWM0_INSTANCE_ + +/* ========== Register definition for PWM0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PWM0_CLK (0x40020000U) /**< \brief (PWM0) PWM Clock Register */ + #define REG_PWM0_ENA (0x40020004U) /**< \brief (PWM0) PWM Enable Register */ + #define REG_PWM0_DIS (0x40020008U) /**< \brief (PWM0) PWM Disable Register */ + #define REG_PWM0_SR (0x4002000CU) /**< \brief (PWM0) PWM Status Register */ + #define REG_PWM0_IER1 (0x40020010U) /**< \brief (PWM0) PWM Interrupt Enable Register 1 */ + #define REG_PWM0_IDR1 (0x40020014U) /**< \brief (PWM0) PWM Interrupt Disable Register 1 */ + #define REG_PWM0_IMR1 (0x40020018U) /**< \brief (PWM0) PWM Interrupt Mask Register 1 */ + #define REG_PWM0_ISR1 (0x4002001CU) /**< \brief (PWM0) PWM Interrupt Status Register 1 */ + #define REG_PWM0_SCM (0x40020020U) /**< \brief (PWM0) PWM Sync Channels Mode Register */ + #define REG_PWM0_DMAR (0x40020024U) /**< \brief (PWM0) PWM DMA Register */ + #define REG_PWM0_SCUC (0x40020028U) /**< \brief (PWM0) PWM Sync Channels Update Control Register */ + #define REG_PWM0_SCUP (0x4002002CU) /**< \brief (PWM0) PWM Sync Channels Update Period Register */ + #define REG_PWM0_SCUPUPD (0x40020030U) /**< \brief (PWM0) PWM Sync Channels Update Period Update Register */ + #define REG_PWM0_IER2 (0x40020034U) /**< \brief (PWM0) PWM Interrupt Enable Register 2 */ + #define REG_PWM0_IDR2 (0x40020038U) /**< \brief (PWM0) PWM Interrupt Disable Register 2 */ + #define REG_PWM0_IMR2 (0x4002003CU) /**< \brief (PWM0) PWM Interrupt Mask Register 2 */ + #define REG_PWM0_ISR2 (0x40020040U) /**< \brief (PWM0) PWM Interrupt Status Register 2 */ + #define REG_PWM0_OOV (0x40020044U) /**< \brief (PWM0) PWM Output Override Value Register */ + #define REG_PWM0_OS (0x40020048U) /**< \brief (PWM0) PWM Output Selection Register */ + #define REG_PWM0_OSS (0x4002004CU) /**< \brief (PWM0) PWM Output Selection Set Register */ + #define REG_PWM0_OSC (0x40020050U) /**< \brief (PWM0) PWM Output Selection Clear Register */ + #define REG_PWM0_OSSUPD (0x40020054U) /**< \brief (PWM0) PWM Output Selection Set Update Register */ + #define REG_PWM0_OSCUPD (0x40020058U) /**< \brief (PWM0) PWM Output Selection Clear Update Register */ + #define REG_PWM0_FMR (0x4002005CU) /**< \brief (PWM0) PWM Fault Mode Register */ + #define REG_PWM0_FSR (0x40020060U) /**< \brief (PWM0) PWM Fault Status Register */ + #define REG_PWM0_FCR (0x40020064U) /**< \brief (PWM0) PWM Fault Clear Register */ + #define REG_PWM0_FPV1 (0x40020068U) /**< \brief (PWM0) PWM Fault Protection Value Register 1 */ + #define REG_PWM0_FPE (0x4002006CU) /**< \brief (PWM0) PWM Fault Protection Enable Register */ + #define REG_PWM0_ELMR (0x4002007CU) /**< \brief (PWM0) PWM Event Line 0 Mode Register */ + #define REG_PWM0_SSPR (0x400200A0U) /**< \brief (PWM0) PWM Spread Spectrum Register */ + #define REG_PWM0_SSPUP (0x400200A4U) /**< \brief (PWM0) PWM Spread Spectrum Update Register */ + #define REG_PWM0_SMMR (0x400200B0U) /**< \brief (PWM0) PWM Stepper Motor Mode Register */ + #define REG_PWM0_FPV2 (0x400200C0U) /**< \brief (PWM0) PWM Fault Protection Value 2 Register */ + #define REG_PWM0_WPCR (0x400200E4U) /**< \brief (PWM0) PWM Write Protection Control Register */ + #define REG_PWM0_WPSR (0x400200E8U) /**< \brief (PWM0) PWM Write Protection Status Register */ + #define REG_PWM0_VERSION (0x400200FCU) /**< \brief (PWM0) Version Register */ + #define REG_PWM0_CMPV0 (0x40020130U) /**< \brief (PWM0) PWM Comparison 0 Value Register */ + #define REG_PWM0_CMPVUPD0 (0x40020134U) /**< \brief (PWM0) PWM Comparison 0 Value Update Register */ + #define REG_PWM0_CMPM0 (0x40020138U) /**< \brief (PWM0) PWM Comparison 0 Mode Register */ + #define REG_PWM0_CMPMUPD0 (0x4002013CU) /**< \brief (PWM0) PWM Comparison 0 Mode Update Register */ + #define REG_PWM0_CMPV1 (0x40020140U) /**< \brief (PWM0) PWM Comparison 1 Value Register */ + #define REG_PWM0_CMPVUPD1 (0x40020144U) /**< \brief (PWM0) PWM Comparison 1 Value Update Register */ + #define REG_PWM0_CMPM1 (0x40020148U) /**< \brief (PWM0) PWM Comparison 1 Mode Register */ + #define REG_PWM0_CMPMUPD1 (0x4002014CU) /**< \brief (PWM0) PWM Comparison 1 Mode Update Register */ + #define REG_PWM0_CMPV2 (0x40020150U) /**< \brief (PWM0) PWM Comparison 2 Value Register */ + #define REG_PWM0_CMPVUPD2 (0x40020154U) /**< \brief (PWM0) PWM Comparison 2 Value Update Register */ + #define REG_PWM0_CMPM2 (0x40020158U) /**< \brief (PWM0) PWM Comparison 2 Mode Register */ + #define REG_PWM0_CMPMUPD2 (0x4002015CU) /**< \brief (PWM0) PWM Comparison 2 Mode Update Register */ + #define REG_PWM0_CMPV3 (0x40020160U) /**< \brief (PWM0) PWM Comparison 3 Value Register */ + #define REG_PWM0_CMPVUPD3 (0x40020164U) /**< \brief (PWM0) PWM Comparison 3 Value Update Register */ + #define REG_PWM0_CMPM3 (0x40020168U) /**< \brief (PWM0) PWM Comparison 3 Mode Register */ + #define REG_PWM0_CMPMUPD3 (0x4002016CU) /**< \brief (PWM0) PWM Comparison 3 Mode Update Register */ + #define REG_PWM0_CMPV4 (0x40020170U) /**< \brief (PWM0) PWM Comparison 4 Value Register */ + #define REG_PWM0_CMPVUPD4 (0x40020174U) /**< \brief (PWM0) PWM Comparison 4 Value Update Register */ + #define REG_PWM0_CMPM4 (0x40020178U) /**< \brief (PWM0) PWM Comparison 4 Mode Register */ + #define REG_PWM0_CMPMUPD4 (0x4002017CU) /**< \brief (PWM0) PWM Comparison 4 Mode Update Register */ + #define REG_PWM0_CMPV5 (0x40020180U) /**< \brief (PWM0) PWM Comparison 5 Value Register */ + #define REG_PWM0_CMPVUPD5 (0x40020184U) /**< \brief (PWM0) PWM Comparison 5 Value Update Register */ + #define REG_PWM0_CMPM5 (0x40020188U) /**< \brief (PWM0) PWM Comparison 5 Mode Register */ + #define REG_PWM0_CMPMUPD5 (0x4002018CU) /**< \brief (PWM0) PWM Comparison 5 Mode Update Register */ + #define REG_PWM0_CMPV6 (0x40020190U) /**< \brief (PWM0) PWM Comparison 6 Value Register */ + #define REG_PWM0_CMPVUPD6 (0x40020194U) /**< \brief (PWM0) PWM Comparison 6 Value Update Register */ + #define REG_PWM0_CMPM6 (0x40020198U) /**< \brief (PWM0) PWM Comparison 6 Mode Register */ + #define REG_PWM0_CMPMUPD6 (0x4002019CU) /**< \brief (PWM0) PWM Comparison 6 Mode Update Register */ + #define REG_PWM0_CMPV7 (0x400201A0U) /**< \brief (PWM0) PWM Comparison 7 Value Register */ + #define REG_PWM0_CMPVUPD7 (0x400201A4U) /**< \brief (PWM0) PWM Comparison 7 Value Update Register */ + #define REG_PWM0_CMPM7 (0x400201A8U) /**< \brief (PWM0) PWM Comparison 7 Mode Register */ + #define REG_PWM0_CMPMUPD7 (0x400201ACU) /**< \brief (PWM0) PWM Comparison 7 Mode Update Register */ + #define REG_PWM0_CMR0 (0x40020200U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 0) */ + #define REG_PWM0_CDTY0 (0x40020204U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 0) */ + #define REG_PWM0_CDTYUPD0 (0x40020208U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 0) */ + #define REG_PWM0_CPRD0 (0x4002020CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 0) */ + #define REG_PWM0_CPRDUPD0 (0x40020210U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 0) */ + #define REG_PWM0_CCNT0 (0x40020214U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 0) */ + #define REG_PWM0_DT0 (0x40020218U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 0) */ + #define REG_PWM0_DTUPD0 (0x4002021CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 0) */ + #define REG_PWM0_CMR1 (0x40020220U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 1) */ + #define REG_PWM0_CDTY1 (0x40020224U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 1) */ + #define REG_PWM0_CDTYUPD1 (0x40020228U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 1) */ + #define REG_PWM0_CPRD1 (0x4002022CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 1) */ + #define REG_PWM0_CPRDUPD1 (0x40020230U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 1) */ + #define REG_PWM0_CCNT1 (0x40020234U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 1) */ + #define REG_PWM0_DT1 (0x40020238U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 1) */ + #define REG_PWM0_DTUPD1 (0x4002023CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 1) */ + #define REG_PWM0_CMR2 (0x40020240U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 2) */ + #define REG_PWM0_CDTY2 (0x40020244U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 2) */ + #define REG_PWM0_CDTYUPD2 (0x40020248U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 2) */ + #define REG_PWM0_CPRD2 (0x4002024CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 2) */ + #define REG_PWM0_CPRDUPD2 (0x40020250U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 2) */ + #define REG_PWM0_CCNT2 (0x40020254U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 2) */ + #define REG_PWM0_DT2 (0x40020258U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 2) */ + #define REG_PWM0_DTUPD2 (0x4002025CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 2) */ + #define REG_PWM0_CMR3 (0x40020260U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 3) */ + #define REG_PWM0_CDTY3 (0x40020264U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 3) */ + #define REG_PWM0_CDTYUPD3 (0x40020268U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 3) */ + #define REG_PWM0_CPRD3 (0x4002026CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 3) */ + #define REG_PWM0_CPRDUPD3 (0x40020270U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 3) */ + #define REG_PWM0_CCNT3 (0x40020274U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 3) */ + #define REG_PWM0_DT3 (0x40020278U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 3) */ + #define REG_PWM0_DTUPD3 (0x4002027CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 3) */ + #define REG_PWM0_CMUPD0 (0x40020400U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 0) */ + #define REG_PWM0_CMUPD1 (0x40020420U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 1) */ + #define REG_PWM0_ETRG1 (0x4002042CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 1) */ + #define REG_PWM0_LEBR1 (0x40020430U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 1) */ + #define REG_PWM0_CMUPD2 (0x40020440U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 2) */ + #define REG_PWM0_ETRG2 (0x4002044CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 2) */ + #define REG_PWM0_LEBR2 (0x40020450U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 2) */ + #define REG_PWM0_CMUPD3 (0x40020460U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 3) */ +#else + #define REG_PWM0_CLK (*(__IO uint32_t*)0x40020000U) /**< \brief (PWM0) PWM Clock Register */ + #define REG_PWM0_ENA (*(__O uint32_t*)0x40020004U) /**< \brief (PWM0) PWM Enable Register */ + #define REG_PWM0_DIS (*(__O uint32_t*)0x40020008U) /**< \brief (PWM0) PWM Disable Register */ + #define REG_PWM0_SR (*(__I uint32_t*)0x4002000CU) /**< \brief (PWM0) PWM Status Register */ + #define REG_PWM0_IER1 (*(__O uint32_t*)0x40020010U) /**< \brief (PWM0) PWM Interrupt Enable Register 1 */ + #define REG_PWM0_IDR1 (*(__O uint32_t*)0x40020014U) /**< \brief (PWM0) PWM Interrupt Disable Register 1 */ + #define REG_PWM0_IMR1 (*(__I uint32_t*)0x40020018U) /**< \brief (PWM0) PWM Interrupt Mask Register 1 */ + #define REG_PWM0_ISR1 (*(__I uint32_t*)0x4002001CU) /**< \brief (PWM0) PWM Interrupt Status Register 1 */ + #define REG_PWM0_SCM (*(__IO uint32_t*)0x40020020U) /**< \brief (PWM0) PWM Sync Channels Mode Register */ + #define REG_PWM0_DMAR (*(__O uint32_t*)0x40020024U) /**< \brief (PWM0) PWM DMA Register */ + #define REG_PWM0_SCUC (*(__IO uint32_t*)0x40020028U) /**< \brief (PWM0) PWM Sync Channels Update Control Register */ + #define REG_PWM0_SCUP (*(__IO uint32_t*)0x4002002CU) /**< \brief (PWM0) PWM Sync Channels Update Period Register */ + #define REG_PWM0_SCUPUPD (*(__O uint32_t*)0x40020030U) /**< \brief (PWM0) PWM Sync Channels Update Period Update Register */ + #define REG_PWM0_IER2 (*(__O uint32_t*)0x40020034U) /**< \brief (PWM0) PWM Interrupt Enable Register 2 */ + #define REG_PWM0_IDR2 (*(__O uint32_t*)0x40020038U) /**< \brief (PWM0) PWM Interrupt Disable Register 2 */ + #define REG_PWM0_IMR2 (*(__I uint32_t*)0x4002003CU) /**< \brief (PWM0) PWM Interrupt Mask Register 2 */ + #define REG_PWM0_ISR2 (*(__I uint32_t*)0x40020040U) /**< \brief (PWM0) PWM Interrupt Status Register 2 */ + #define REG_PWM0_OOV (*(__IO uint32_t*)0x40020044U) /**< \brief (PWM0) PWM Output Override Value Register */ + #define REG_PWM0_OS (*(__IO uint32_t*)0x40020048U) /**< \brief (PWM0) PWM Output Selection Register */ + #define REG_PWM0_OSS (*(__O uint32_t*)0x4002004CU) /**< \brief (PWM0) PWM Output Selection Set Register */ + #define REG_PWM0_OSC (*(__O uint32_t*)0x40020050U) /**< \brief (PWM0) PWM Output Selection Clear Register */ + #define REG_PWM0_OSSUPD (*(__O uint32_t*)0x40020054U) /**< \brief (PWM0) PWM Output Selection Set Update Register */ + #define REG_PWM0_OSCUPD (*(__O uint32_t*)0x40020058U) /**< \brief (PWM0) PWM Output Selection Clear Update Register */ + #define REG_PWM0_FMR (*(__IO uint32_t*)0x4002005CU) /**< \brief (PWM0) PWM Fault Mode Register */ + #define REG_PWM0_FSR (*(__I uint32_t*)0x40020060U) /**< \brief (PWM0) PWM Fault Status Register */ + #define REG_PWM0_FCR (*(__O uint32_t*)0x40020064U) /**< \brief (PWM0) PWM Fault Clear Register */ + #define REG_PWM0_FPV1 (*(__IO uint32_t*)0x40020068U) /**< \brief (PWM0) PWM Fault Protection Value Register 1 */ + #define REG_PWM0_FPE (*(__IO uint32_t*)0x4002006CU) /**< \brief (PWM0) PWM Fault Protection Enable Register */ + #define REG_PWM0_ELMR (*(__IO uint32_t*)0x4002007CU) /**< \brief (PWM0) PWM Event Line 0 Mode Register */ + #define REG_PWM0_SSPR (*(__IO uint32_t*)0x400200A0U) /**< \brief (PWM0) PWM Spread Spectrum Register */ + #define REG_PWM0_SSPUP (*(__O uint32_t*)0x400200A4U) /**< \brief (PWM0) PWM Spread Spectrum Update Register */ + #define REG_PWM0_SMMR (*(__IO uint32_t*)0x400200B0U) /**< \brief (PWM0) PWM Stepper Motor Mode Register */ + #define REG_PWM0_FPV2 (*(__IO uint32_t*)0x400200C0U) /**< \brief (PWM0) PWM Fault Protection Value 2 Register */ + #define REG_PWM0_WPCR (*(__O uint32_t*)0x400200E4U) /**< \brief (PWM0) PWM Write Protection Control Register */ + #define REG_PWM0_WPSR (*(__I uint32_t*)0x400200E8U) /**< \brief (PWM0) PWM Write Protection Status Register */ + #define REG_PWM0_VERSION (*(__I uint32_t*)0x400200FCU) /**< \brief (PWM0) Version Register */ + #define REG_PWM0_CMPV0 (*(__IO uint32_t*)0x40020130U) /**< \brief (PWM0) PWM Comparison 0 Value Register */ + #define REG_PWM0_CMPVUPD0 (*(__O uint32_t*)0x40020134U) /**< \brief (PWM0) PWM Comparison 0 Value Update Register */ + #define REG_PWM0_CMPM0 (*(__IO uint32_t*)0x40020138U) /**< \brief (PWM0) PWM Comparison 0 Mode Register */ + #define REG_PWM0_CMPMUPD0 (*(__O uint32_t*)0x4002013CU) /**< \brief (PWM0) PWM Comparison 0 Mode Update Register */ + #define REG_PWM0_CMPV1 (*(__IO uint32_t*)0x40020140U) /**< \brief (PWM0) PWM Comparison 1 Value Register */ + #define REG_PWM0_CMPVUPD1 (*(__O uint32_t*)0x40020144U) /**< \brief (PWM0) PWM Comparison 1 Value Update Register */ + #define REG_PWM0_CMPM1 (*(__IO uint32_t*)0x40020148U) /**< \brief (PWM0) PWM Comparison 1 Mode Register */ + #define REG_PWM0_CMPMUPD1 (*(__O uint32_t*)0x4002014CU) /**< \brief (PWM0) PWM Comparison 1 Mode Update Register */ + #define REG_PWM0_CMPV2 (*(__IO uint32_t*)0x40020150U) /**< \brief (PWM0) PWM Comparison 2 Value Register */ + #define REG_PWM0_CMPVUPD2 (*(__O uint32_t*)0x40020154U) /**< \brief (PWM0) PWM Comparison 2 Value Update Register */ + #define REG_PWM0_CMPM2 (*(__IO uint32_t*)0x40020158U) /**< \brief (PWM0) PWM Comparison 2 Mode Register */ + #define REG_PWM0_CMPMUPD2 (*(__O uint32_t*)0x4002015CU) /**< \brief (PWM0) PWM Comparison 2 Mode Update Register */ + #define REG_PWM0_CMPV3 (*(__IO uint32_t*)0x40020160U) /**< \brief (PWM0) PWM Comparison 3 Value Register */ + #define REG_PWM0_CMPVUPD3 (*(__O uint32_t*)0x40020164U) /**< \brief (PWM0) PWM Comparison 3 Value Update Register */ + #define REG_PWM0_CMPM3 (*(__IO uint32_t*)0x40020168U) /**< \brief (PWM0) PWM Comparison 3 Mode Register */ + #define REG_PWM0_CMPMUPD3 (*(__O uint32_t*)0x4002016CU) /**< \brief (PWM0) PWM Comparison 3 Mode Update Register */ + #define REG_PWM0_CMPV4 (*(__IO uint32_t*)0x40020170U) /**< \brief (PWM0) PWM Comparison 4 Value Register */ + #define REG_PWM0_CMPVUPD4 (*(__O uint32_t*)0x40020174U) /**< \brief (PWM0) PWM Comparison 4 Value Update Register */ + #define REG_PWM0_CMPM4 (*(__IO uint32_t*)0x40020178U) /**< \brief (PWM0) PWM Comparison 4 Mode Register */ + #define REG_PWM0_CMPMUPD4 (*(__O uint32_t*)0x4002017CU) /**< \brief (PWM0) PWM Comparison 4 Mode Update Register */ + #define REG_PWM0_CMPV5 (*(__IO uint32_t*)0x40020180U) /**< \brief (PWM0) PWM Comparison 5 Value Register */ + #define REG_PWM0_CMPVUPD5 (*(__O uint32_t*)0x40020184U) /**< \brief (PWM0) PWM Comparison 5 Value Update Register */ + #define REG_PWM0_CMPM5 (*(__IO uint32_t*)0x40020188U) /**< \brief (PWM0) PWM Comparison 5 Mode Register */ + #define REG_PWM0_CMPMUPD5 (*(__O uint32_t*)0x4002018CU) /**< \brief (PWM0) PWM Comparison 5 Mode Update Register */ + #define REG_PWM0_CMPV6 (*(__IO uint32_t*)0x40020190U) /**< \brief (PWM0) PWM Comparison 6 Value Register */ + #define REG_PWM0_CMPVUPD6 (*(__O uint32_t*)0x40020194U) /**< \brief (PWM0) PWM Comparison 6 Value Update Register */ + #define REG_PWM0_CMPM6 (*(__IO uint32_t*)0x40020198U) /**< \brief (PWM0) PWM Comparison 6 Mode Register */ + #define REG_PWM0_CMPMUPD6 (*(__O uint32_t*)0x4002019CU) /**< \brief (PWM0) PWM Comparison 6 Mode Update Register */ + #define REG_PWM0_CMPV7 (*(__IO uint32_t*)0x400201A0U) /**< \brief (PWM0) PWM Comparison 7 Value Register */ + #define REG_PWM0_CMPVUPD7 (*(__O uint32_t*)0x400201A4U) /**< \brief (PWM0) PWM Comparison 7 Value Update Register */ + #define REG_PWM0_CMPM7 (*(__IO uint32_t*)0x400201A8U) /**< \brief (PWM0) PWM Comparison 7 Mode Register */ + #define REG_PWM0_CMPMUPD7 (*(__O uint32_t*)0x400201ACU) /**< \brief (PWM0) PWM Comparison 7 Mode Update Register */ + #define REG_PWM0_CMR0 (*(__IO uint32_t*)0x40020200U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 0) */ + #define REG_PWM0_CDTY0 (*(__IO uint32_t*)0x40020204U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 0) */ + #define REG_PWM0_CDTYUPD0 (*(__O uint32_t*)0x40020208U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 0) */ + #define REG_PWM0_CPRD0 (*(__IO uint32_t*)0x4002020CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 0) */ + #define REG_PWM0_CPRDUPD0 (*(__O uint32_t*)0x40020210U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 0) */ + #define REG_PWM0_CCNT0 (*(__I uint32_t*)0x40020214U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 0) */ + #define REG_PWM0_DT0 (*(__IO uint32_t*)0x40020218U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 0) */ + #define REG_PWM0_DTUPD0 (*(__O uint32_t*)0x4002021CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 0) */ + #define REG_PWM0_CMR1 (*(__IO uint32_t*)0x40020220U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 1) */ + #define REG_PWM0_CDTY1 (*(__IO uint32_t*)0x40020224U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 1) */ + #define REG_PWM0_CDTYUPD1 (*(__O uint32_t*)0x40020228U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 1) */ + #define REG_PWM0_CPRD1 (*(__IO uint32_t*)0x4002022CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 1) */ + #define REG_PWM0_CPRDUPD1 (*(__O uint32_t*)0x40020230U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 1) */ + #define REG_PWM0_CCNT1 (*(__I uint32_t*)0x40020234U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 1) */ + #define REG_PWM0_DT1 (*(__IO uint32_t*)0x40020238U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 1) */ + #define REG_PWM0_DTUPD1 (*(__O uint32_t*)0x4002023CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 1) */ + #define REG_PWM0_CMR2 (*(__IO uint32_t*)0x40020240U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 2) */ + #define REG_PWM0_CDTY2 (*(__IO uint32_t*)0x40020244U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 2) */ + #define REG_PWM0_CDTYUPD2 (*(__O uint32_t*)0x40020248U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 2) */ + #define REG_PWM0_CPRD2 (*(__IO uint32_t*)0x4002024CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 2) */ + #define REG_PWM0_CPRDUPD2 (*(__O uint32_t*)0x40020250U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 2) */ + #define REG_PWM0_CCNT2 (*(__I uint32_t*)0x40020254U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 2) */ + #define REG_PWM0_DT2 (*(__IO uint32_t*)0x40020258U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 2) */ + #define REG_PWM0_DTUPD2 (*(__O uint32_t*)0x4002025CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 2) */ + #define REG_PWM0_CMR3 (*(__IO uint32_t*)0x40020260U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 3) */ + #define REG_PWM0_CDTY3 (*(__IO uint32_t*)0x40020264U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 3) */ + #define REG_PWM0_CDTYUPD3 (*(__O uint32_t*)0x40020268U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 3) */ + #define REG_PWM0_CPRD3 (*(__IO uint32_t*)0x4002026CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 3) */ + #define REG_PWM0_CPRDUPD3 (*(__O uint32_t*)0x40020270U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 3) */ + #define REG_PWM0_CCNT3 (*(__I uint32_t*)0x40020274U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 3) */ + #define REG_PWM0_DT3 (*(__IO uint32_t*)0x40020278U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 3) */ + #define REG_PWM0_DTUPD3 (*(__O uint32_t*)0x4002027CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 3) */ + #define REG_PWM0_CMUPD0 (*(__O uint32_t*)0x40020400U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 0) */ + #define REG_PWM0_CMUPD1 (*(__O uint32_t*)0x40020420U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 1) */ + #define REG_PWM0_ETRG1 (*(__IO uint32_t*)0x4002042CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 1) */ + #define REG_PWM0_LEBR1 (*(__IO uint32_t*)0x40020430U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 1) */ + #define REG_PWM0_CMUPD2 (*(__O uint32_t*)0x40020440U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 2) */ + #define REG_PWM0_ETRG2 (*(__IO uint32_t*)0x4002044CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 2) */ + #define REG_PWM0_LEBR2 (*(__IO uint32_t*)0x40020450U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 2) */ + #define REG_PWM0_CMUPD3 (*(__O uint32_t*)0x40020460U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 3) */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_PWM0_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/pwm1.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/pwm1.h new file mode 100644 index 000000000..0e308d782 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/pwm1.h @@ -0,0 +1,259 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_PWM1_INSTANCE_ +#define _SAME70_PWM1_INSTANCE_ + +/* ========== Register definition for PWM1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PWM1_CLK (0x4005C000U) /**< \brief (PWM1) PWM Clock Register */ + #define REG_PWM1_ENA (0x4005C004U) /**< \brief (PWM1) PWM Enable Register */ + #define REG_PWM1_DIS (0x4005C008U) /**< \brief (PWM1) PWM Disable Register */ + #define REG_PWM1_SR (0x4005C00CU) /**< \brief (PWM1) PWM Status Register */ + #define REG_PWM1_IER1 (0x4005C010U) /**< \brief (PWM1) PWM Interrupt Enable Register 1 */ + #define REG_PWM1_IDR1 (0x4005C014U) /**< \brief (PWM1) PWM Interrupt Disable Register 1 */ + #define REG_PWM1_IMR1 (0x4005C018U) /**< \brief (PWM1) PWM Interrupt Mask Register 1 */ + #define REG_PWM1_ISR1 (0x4005C01CU) /**< \brief (PWM1) PWM Interrupt Status Register 1 */ + #define REG_PWM1_SCM (0x4005C020U) /**< \brief (PWM1) PWM Sync Channels Mode Register */ + #define REG_PWM1_DMAR (0x4005C024U) /**< \brief (PWM1) PWM DMA Register */ + #define REG_PWM1_SCUC (0x4005C028U) /**< \brief (PWM1) PWM Sync Channels Update Control Register */ + #define REG_PWM1_SCUP (0x4005C02CU) /**< \brief (PWM1) PWM Sync Channels Update Period Register */ + #define REG_PWM1_SCUPUPD (0x4005C030U) /**< \brief (PWM1) PWM Sync Channels Update Period Update Register */ + #define REG_PWM1_IER2 (0x4005C034U) /**< \brief (PWM1) PWM Interrupt Enable Register 2 */ + #define REG_PWM1_IDR2 (0x4005C038U) /**< \brief (PWM1) PWM Interrupt Disable Register 2 */ + #define REG_PWM1_IMR2 (0x4005C03CU) /**< \brief (PWM1) PWM Interrupt Mask Register 2 */ + #define REG_PWM1_ISR2 (0x4005C040U) /**< \brief (PWM1) PWM Interrupt Status Register 2 */ + #define REG_PWM1_OOV (0x4005C044U) /**< \brief (PWM1) PWM Output Override Value Register */ + #define REG_PWM1_OS (0x4005C048U) /**< \brief (PWM1) PWM Output Selection Register */ + #define REG_PWM1_OSS (0x4005C04CU) /**< \brief (PWM1) PWM Output Selection Set Register */ + #define REG_PWM1_OSC (0x4005C050U) /**< \brief (PWM1) PWM Output Selection Clear Register */ + #define REG_PWM1_OSSUPD (0x4005C054U) /**< \brief (PWM1) PWM Output Selection Set Update Register */ + #define REG_PWM1_OSCUPD (0x4005C058U) /**< \brief (PWM1) PWM Output Selection Clear Update Register */ + #define REG_PWM1_FMR (0x4005C05CU) /**< \brief (PWM1) PWM Fault Mode Register */ + #define REG_PWM1_FSR (0x4005C060U) /**< \brief (PWM1) PWM Fault Status Register */ + #define REG_PWM1_FCR (0x4005C064U) /**< \brief (PWM1) PWM Fault Clear Register */ + #define REG_PWM1_FPV1 (0x4005C068U) /**< \brief (PWM1) PWM Fault Protection Value Register 1 */ + #define REG_PWM1_FPE (0x4005C06CU) /**< \brief (PWM1) PWM Fault Protection Enable Register */ + #define REG_PWM1_ELMR (0x4005C07CU) /**< \brief (PWM1) PWM Event Line 0 Mode Register */ + #define REG_PWM1_SSPR (0x4005C0A0U) /**< \brief (PWM1) PWM Spread Spectrum Register */ + #define REG_PWM1_SSPUP (0x4005C0A4U) /**< \brief (PWM1) PWM Spread Spectrum Update Register */ + #define REG_PWM1_SMMR (0x4005C0B0U) /**< \brief (PWM1) PWM Stepper Motor Mode Register */ + #define REG_PWM1_FPV2 (0x4005C0C0U) /**< \brief (PWM1) PWM Fault Protection Value 2 Register */ + #define REG_PWM1_WPCR (0x4005C0E4U) /**< \brief (PWM1) PWM Write Protection Control Register */ + #define REG_PWM1_WPSR (0x4005C0E8U) /**< \brief (PWM1) PWM Write Protection Status Register */ + #define REG_PWM1_VERSION (0x4005C0FCU) /**< \brief (PWM1) Version Register */ + #define REG_PWM1_CMPV0 (0x4005C130U) /**< \brief (PWM1) PWM Comparison 0 Value Register */ + #define REG_PWM1_CMPVUPD0 (0x4005C134U) /**< \brief (PWM1) PWM Comparison 0 Value Update Register */ + #define REG_PWM1_CMPM0 (0x4005C138U) /**< \brief (PWM1) PWM Comparison 0 Mode Register */ + #define REG_PWM1_CMPMUPD0 (0x4005C13CU) /**< \brief (PWM1) PWM Comparison 0 Mode Update Register */ + #define REG_PWM1_CMPV1 (0x4005C140U) /**< \brief (PWM1) PWM Comparison 1 Value Register */ + #define REG_PWM1_CMPVUPD1 (0x4005C144U) /**< \brief (PWM1) PWM Comparison 1 Value Update Register */ + #define REG_PWM1_CMPM1 (0x4005C148U) /**< \brief (PWM1) PWM Comparison 1 Mode Register */ + #define REG_PWM1_CMPMUPD1 (0x4005C14CU) /**< \brief (PWM1) PWM Comparison 1 Mode Update Register */ + #define REG_PWM1_CMPV2 (0x4005C150U) /**< \brief (PWM1) PWM Comparison 2 Value Register */ + #define REG_PWM1_CMPVUPD2 (0x4005C154U) /**< \brief (PWM1) PWM Comparison 2 Value Update Register */ + #define REG_PWM1_CMPM2 (0x4005C158U) /**< \brief (PWM1) PWM Comparison 2 Mode Register */ + #define REG_PWM1_CMPMUPD2 (0x4005C15CU) /**< \brief (PWM1) PWM Comparison 2 Mode Update Register */ + #define REG_PWM1_CMPV3 (0x4005C160U) /**< \brief (PWM1) PWM Comparison 3 Value Register */ + #define REG_PWM1_CMPVUPD3 (0x4005C164U) /**< \brief (PWM1) PWM Comparison 3 Value Update Register */ + #define REG_PWM1_CMPM3 (0x4005C168U) /**< \brief (PWM1) PWM Comparison 3 Mode Register */ + #define REG_PWM1_CMPMUPD3 (0x4005C16CU) /**< \brief (PWM1) PWM Comparison 3 Mode Update Register */ + #define REG_PWM1_CMPV4 (0x4005C170U) /**< \brief (PWM1) PWM Comparison 4 Value Register */ + #define REG_PWM1_CMPVUPD4 (0x4005C174U) /**< \brief (PWM1) PWM Comparison 4 Value Update Register */ + #define REG_PWM1_CMPM4 (0x4005C178U) /**< \brief (PWM1) PWM Comparison 4 Mode Register */ + #define REG_PWM1_CMPMUPD4 (0x4005C17CU) /**< \brief (PWM1) PWM Comparison 4 Mode Update Register */ + #define REG_PWM1_CMPV5 (0x4005C180U) /**< \brief (PWM1) PWM Comparison 5 Value Register */ + #define REG_PWM1_CMPVUPD5 (0x4005C184U) /**< \brief (PWM1) PWM Comparison 5 Value Update Register */ + #define REG_PWM1_CMPM5 (0x4005C188U) /**< \brief (PWM1) PWM Comparison 5 Mode Register */ + #define REG_PWM1_CMPMUPD5 (0x4005C18CU) /**< \brief (PWM1) PWM Comparison 5 Mode Update Register */ + #define REG_PWM1_CMPV6 (0x4005C190U) /**< \brief (PWM1) PWM Comparison 6 Value Register */ + #define REG_PWM1_CMPVUPD6 (0x4005C194U) /**< \brief (PWM1) PWM Comparison 6 Value Update Register */ + #define REG_PWM1_CMPM6 (0x4005C198U) /**< \brief (PWM1) PWM Comparison 6 Mode Register */ + #define REG_PWM1_CMPMUPD6 (0x4005C19CU) /**< \brief (PWM1) PWM Comparison 6 Mode Update Register */ + #define REG_PWM1_CMPV7 (0x4005C1A0U) /**< \brief (PWM1) PWM Comparison 7 Value Register */ + #define REG_PWM1_CMPVUPD7 (0x4005C1A4U) /**< \brief (PWM1) PWM Comparison 7 Value Update Register */ + #define REG_PWM1_CMPM7 (0x4005C1A8U) /**< \brief (PWM1) PWM Comparison 7 Mode Register */ + #define REG_PWM1_CMPMUPD7 (0x4005C1ACU) /**< \brief (PWM1) PWM Comparison 7 Mode Update Register */ + #define REG_PWM1_CMR0 (0x4005C200U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 0) */ + #define REG_PWM1_CDTY0 (0x4005C204U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 0) */ + #define REG_PWM1_CDTYUPD0 (0x4005C208U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 0) */ + #define REG_PWM1_CPRD0 (0x4005C20CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 0) */ + #define REG_PWM1_CPRDUPD0 (0x4005C210U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 0) */ + #define REG_PWM1_CCNT0 (0x4005C214U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 0) */ + #define REG_PWM1_DT0 (0x4005C218U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 0) */ + #define REG_PWM1_DTUPD0 (0x4005C21CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 0) */ + #define REG_PWM1_CMR1 (0x4005C220U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 1) */ + #define REG_PWM1_CDTY1 (0x4005C224U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 1) */ + #define REG_PWM1_CDTYUPD1 (0x4005C228U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 1) */ + #define REG_PWM1_CPRD1 (0x4005C22CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 1) */ + #define REG_PWM1_CPRDUPD1 (0x4005C230U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 1) */ + #define REG_PWM1_CCNT1 (0x4005C234U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 1) */ + #define REG_PWM1_DT1 (0x4005C238U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 1) */ + #define REG_PWM1_DTUPD1 (0x4005C23CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 1) */ + #define REG_PWM1_CMR2 (0x4005C240U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 2) */ + #define REG_PWM1_CDTY2 (0x4005C244U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 2) */ + #define REG_PWM1_CDTYUPD2 (0x4005C248U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 2) */ + #define REG_PWM1_CPRD2 (0x4005C24CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 2) */ + #define REG_PWM1_CPRDUPD2 (0x4005C250U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 2) */ + #define REG_PWM1_CCNT2 (0x4005C254U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 2) */ + #define REG_PWM1_DT2 (0x4005C258U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 2) */ + #define REG_PWM1_DTUPD2 (0x4005C25CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 2) */ + #define REG_PWM1_CMR3 (0x4005C260U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 3) */ + #define REG_PWM1_CDTY3 (0x4005C264U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 3) */ + #define REG_PWM1_CDTYUPD3 (0x4005C268U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 3) */ + #define REG_PWM1_CPRD3 (0x4005C26CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 3) */ + #define REG_PWM1_CPRDUPD3 (0x4005C270U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 3) */ + #define REG_PWM1_CCNT3 (0x4005C274U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 3) */ + #define REG_PWM1_DT3 (0x4005C278U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 3) */ + #define REG_PWM1_DTUPD3 (0x4005C27CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 3) */ + #define REG_PWM1_CMUPD0 (0x4005C400U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 0) */ + #define REG_PWM1_CMUPD1 (0x4005C420U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 1) */ + #define REG_PWM1_ETRG1 (0x4005C42CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 1) */ + #define REG_PWM1_LEBR1 (0x4005C430U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 1) */ + #define REG_PWM1_CMUPD2 (0x4005C440U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 2) */ + #define REG_PWM1_ETRG2 (0x4005C44CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 2) */ + #define REG_PWM1_LEBR2 (0x4005C450U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 2) */ + #define REG_PWM1_CMUPD3 (0x4005C460U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 3) */ +#else + #define REG_PWM1_CLK (*(__IO uint32_t*)0x4005C000U) /**< \brief (PWM1) PWM Clock Register */ + #define REG_PWM1_ENA (*(__O uint32_t*)0x4005C004U) /**< \brief (PWM1) PWM Enable Register */ + #define REG_PWM1_DIS (*(__O uint32_t*)0x4005C008U) /**< \brief (PWM1) PWM Disable Register */ + #define REG_PWM1_SR (*(__I uint32_t*)0x4005C00CU) /**< \brief (PWM1) PWM Status Register */ + #define REG_PWM1_IER1 (*(__O uint32_t*)0x4005C010U) /**< \brief (PWM1) PWM Interrupt Enable Register 1 */ + #define REG_PWM1_IDR1 (*(__O uint32_t*)0x4005C014U) /**< \brief (PWM1) PWM Interrupt Disable Register 1 */ + #define REG_PWM1_IMR1 (*(__I uint32_t*)0x4005C018U) /**< \brief (PWM1) PWM Interrupt Mask Register 1 */ + #define REG_PWM1_ISR1 (*(__I uint32_t*)0x4005C01CU) /**< \brief (PWM1) PWM Interrupt Status Register 1 */ + #define REG_PWM1_SCM (*(__IO uint32_t*)0x4005C020U) /**< \brief (PWM1) PWM Sync Channels Mode Register */ + #define REG_PWM1_DMAR (*(__O uint32_t*)0x4005C024U) /**< \brief (PWM1) PWM DMA Register */ + #define REG_PWM1_SCUC (*(__IO uint32_t*)0x4005C028U) /**< \brief (PWM1) PWM Sync Channels Update Control Register */ + #define REG_PWM1_SCUP (*(__IO uint32_t*)0x4005C02CU) /**< \brief (PWM1) PWM Sync Channels Update Period Register */ + #define REG_PWM1_SCUPUPD (*(__O uint32_t*)0x4005C030U) /**< \brief (PWM1) PWM Sync Channels Update Period Update Register */ + #define REG_PWM1_IER2 (*(__O uint32_t*)0x4005C034U) /**< \brief (PWM1) PWM Interrupt Enable Register 2 */ + #define REG_PWM1_IDR2 (*(__O uint32_t*)0x4005C038U) /**< \brief (PWM1) PWM Interrupt Disable Register 2 */ + #define REG_PWM1_IMR2 (*(__I uint32_t*)0x4005C03CU) /**< \brief (PWM1) PWM Interrupt Mask Register 2 */ + #define REG_PWM1_ISR2 (*(__I uint32_t*)0x4005C040U) /**< \brief (PWM1) PWM Interrupt Status Register 2 */ + #define REG_PWM1_OOV (*(__IO uint32_t*)0x4005C044U) /**< \brief (PWM1) PWM Output Override Value Register */ + #define REG_PWM1_OS (*(__IO uint32_t*)0x4005C048U) /**< \brief (PWM1) PWM Output Selection Register */ + #define REG_PWM1_OSS (*(__O uint32_t*)0x4005C04CU) /**< \brief (PWM1) PWM Output Selection Set Register */ + #define REG_PWM1_OSC (*(__O uint32_t*)0x4005C050U) /**< \brief (PWM1) PWM Output Selection Clear Register */ + #define REG_PWM1_OSSUPD (*(__O uint32_t*)0x4005C054U) /**< \brief (PWM1) PWM Output Selection Set Update Register */ + #define REG_PWM1_OSCUPD (*(__O uint32_t*)0x4005C058U) /**< \brief (PWM1) PWM Output Selection Clear Update Register */ + #define REG_PWM1_FMR (*(__IO uint32_t*)0x4005C05CU) /**< \brief (PWM1) PWM Fault Mode Register */ + #define REG_PWM1_FSR (*(__I uint32_t*)0x4005C060U) /**< \brief (PWM1) PWM Fault Status Register */ + #define REG_PWM1_FCR (*(__O uint32_t*)0x4005C064U) /**< \brief (PWM1) PWM Fault Clear Register */ + #define REG_PWM1_FPV1 (*(__IO uint32_t*)0x4005C068U) /**< \brief (PWM1) PWM Fault Protection Value Register 1 */ + #define REG_PWM1_FPE (*(__IO uint32_t*)0x4005C06CU) /**< \brief (PWM1) PWM Fault Protection Enable Register */ + #define REG_PWM1_ELMR (*(__IO uint32_t*)0x4005C07CU) /**< \brief (PWM1) PWM Event Line 0 Mode Register */ + #define REG_PWM1_SSPR (*(__IO uint32_t*)0x4005C0A0U) /**< \brief (PWM1) PWM Spread Spectrum Register */ + #define REG_PWM1_SSPUP (*(__O uint32_t*)0x4005C0A4U) /**< \brief (PWM1) PWM Spread Spectrum Update Register */ + #define REG_PWM1_SMMR (*(__IO uint32_t*)0x4005C0B0U) /**< \brief (PWM1) PWM Stepper Motor Mode Register */ + #define REG_PWM1_FPV2 (*(__IO uint32_t*)0x4005C0C0U) /**< \brief (PWM1) PWM Fault Protection Value 2 Register */ + #define REG_PWM1_WPCR (*(__O uint32_t*)0x4005C0E4U) /**< \brief (PWM1) PWM Write Protection Control Register */ + #define REG_PWM1_WPSR (*(__I uint32_t*)0x4005C0E8U) /**< \brief (PWM1) PWM Write Protection Status Register */ + #define REG_PWM1_VERSION (*(__I uint32_t*)0x4005C0FCU) /**< \brief (PWM1) Version Register */ + #define REG_PWM1_CMPV0 (*(__IO uint32_t*)0x4005C130U) /**< \brief (PWM1) PWM Comparison 0 Value Register */ + #define REG_PWM1_CMPVUPD0 (*(__O uint32_t*)0x4005C134U) /**< \brief (PWM1) PWM Comparison 0 Value Update Register */ + #define REG_PWM1_CMPM0 (*(__IO uint32_t*)0x4005C138U) /**< \brief (PWM1) PWM Comparison 0 Mode Register */ + #define REG_PWM1_CMPMUPD0 (*(__O uint32_t*)0x4005C13CU) /**< \brief (PWM1) PWM Comparison 0 Mode Update Register */ + #define REG_PWM1_CMPV1 (*(__IO uint32_t*)0x4005C140U) /**< \brief (PWM1) PWM Comparison 1 Value Register */ + #define REG_PWM1_CMPVUPD1 (*(__O uint32_t*)0x4005C144U) /**< \brief (PWM1) PWM Comparison 1 Value Update Register */ + #define REG_PWM1_CMPM1 (*(__IO uint32_t*)0x4005C148U) /**< \brief (PWM1) PWM Comparison 1 Mode Register */ + #define REG_PWM1_CMPMUPD1 (*(__O uint32_t*)0x4005C14CU) /**< \brief (PWM1) PWM Comparison 1 Mode Update Register */ + #define REG_PWM1_CMPV2 (*(__IO uint32_t*)0x4005C150U) /**< \brief (PWM1) PWM Comparison 2 Value Register */ + #define REG_PWM1_CMPVUPD2 (*(__O uint32_t*)0x4005C154U) /**< \brief (PWM1) PWM Comparison 2 Value Update Register */ + #define REG_PWM1_CMPM2 (*(__IO uint32_t*)0x4005C158U) /**< \brief (PWM1) PWM Comparison 2 Mode Register */ + #define REG_PWM1_CMPMUPD2 (*(__O uint32_t*)0x4005C15CU) /**< \brief (PWM1) PWM Comparison 2 Mode Update Register */ + #define REG_PWM1_CMPV3 (*(__IO uint32_t*)0x4005C160U) /**< \brief (PWM1) PWM Comparison 3 Value Register */ + #define REG_PWM1_CMPVUPD3 (*(__O uint32_t*)0x4005C164U) /**< \brief (PWM1) PWM Comparison 3 Value Update Register */ + #define REG_PWM1_CMPM3 (*(__IO uint32_t*)0x4005C168U) /**< \brief (PWM1) PWM Comparison 3 Mode Register */ + #define REG_PWM1_CMPMUPD3 (*(__O uint32_t*)0x4005C16CU) /**< \brief (PWM1) PWM Comparison 3 Mode Update Register */ + #define REG_PWM1_CMPV4 (*(__IO uint32_t*)0x4005C170U) /**< \brief (PWM1) PWM Comparison 4 Value Register */ + #define REG_PWM1_CMPVUPD4 (*(__O uint32_t*)0x4005C174U) /**< \brief (PWM1) PWM Comparison 4 Value Update Register */ + #define REG_PWM1_CMPM4 (*(__IO uint32_t*)0x4005C178U) /**< \brief (PWM1) PWM Comparison 4 Mode Register */ + #define REG_PWM1_CMPMUPD4 (*(__O uint32_t*)0x4005C17CU) /**< \brief (PWM1) PWM Comparison 4 Mode Update Register */ + #define REG_PWM1_CMPV5 (*(__IO uint32_t*)0x4005C180U) /**< \brief (PWM1) PWM Comparison 5 Value Register */ + #define REG_PWM1_CMPVUPD5 (*(__O uint32_t*)0x4005C184U) /**< \brief (PWM1) PWM Comparison 5 Value Update Register */ + #define REG_PWM1_CMPM5 (*(__IO uint32_t*)0x4005C188U) /**< \brief (PWM1) PWM Comparison 5 Mode Register */ + #define REG_PWM1_CMPMUPD5 (*(__O uint32_t*)0x4005C18CU) /**< \brief (PWM1) PWM Comparison 5 Mode Update Register */ + #define REG_PWM1_CMPV6 (*(__IO uint32_t*)0x4005C190U) /**< \brief (PWM1) PWM Comparison 6 Value Register */ + #define REG_PWM1_CMPVUPD6 (*(__O uint32_t*)0x4005C194U) /**< \brief (PWM1) PWM Comparison 6 Value Update Register */ + #define REG_PWM1_CMPM6 (*(__IO uint32_t*)0x4005C198U) /**< \brief (PWM1) PWM Comparison 6 Mode Register */ + #define REG_PWM1_CMPMUPD6 (*(__O uint32_t*)0x4005C19CU) /**< \brief (PWM1) PWM Comparison 6 Mode Update Register */ + #define REG_PWM1_CMPV7 (*(__IO uint32_t*)0x4005C1A0U) /**< \brief (PWM1) PWM Comparison 7 Value Register */ + #define REG_PWM1_CMPVUPD7 (*(__O uint32_t*)0x4005C1A4U) /**< \brief (PWM1) PWM Comparison 7 Value Update Register */ + #define REG_PWM1_CMPM7 (*(__IO uint32_t*)0x4005C1A8U) /**< \brief (PWM1) PWM Comparison 7 Mode Register */ + #define REG_PWM1_CMPMUPD7 (*(__O uint32_t*)0x4005C1ACU) /**< \brief (PWM1) PWM Comparison 7 Mode Update Register */ + #define REG_PWM1_CMR0 (*(__IO uint32_t*)0x4005C200U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 0) */ + #define REG_PWM1_CDTY0 (*(__IO uint32_t*)0x4005C204U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 0) */ + #define REG_PWM1_CDTYUPD0 (*(__O uint32_t*)0x4005C208U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 0) */ + #define REG_PWM1_CPRD0 (*(__IO uint32_t*)0x4005C20CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 0) */ + #define REG_PWM1_CPRDUPD0 (*(__O uint32_t*)0x4005C210U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 0) */ + #define REG_PWM1_CCNT0 (*(__I uint32_t*)0x4005C214U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 0) */ + #define REG_PWM1_DT0 (*(__IO uint32_t*)0x4005C218U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 0) */ + #define REG_PWM1_DTUPD0 (*(__O uint32_t*)0x4005C21CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 0) */ + #define REG_PWM1_CMR1 (*(__IO uint32_t*)0x4005C220U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 1) */ + #define REG_PWM1_CDTY1 (*(__IO uint32_t*)0x4005C224U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 1) */ + #define REG_PWM1_CDTYUPD1 (*(__O uint32_t*)0x4005C228U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 1) */ + #define REG_PWM1_CPRD1 (*(__IO uint32_t*)0x4005C22CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 1) */ + #define REG_PWM1_CPRDUPD1 (*(__O uint32_t*)0x4005C230U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 1) */ + #define REG_PWM1_CCNT1 (*(__I uint32_t*)0x4005C234U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 1) */ + #define REG_PWM1_DT1 (*(__IO uint32_t*)0x4005C238U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 1) */ + #define REG_PWM1_DTUPD1 (*(__O uint32_t*)0x4005C23CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 1) */ + #define REG_PWM1_CMR2 (*(__IO uint32_t*)0x4005C240U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 2) */ + #define REG_PWM1_CDTY2 (*(__IO uint32_t*)0x4005C244U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 2) */ + #define REG_PWM1_CDTYUPD2 (*(__O uint32_t*)0x4005C248U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 2) */ + #define REG_PWM1_CPRD2 (*(__IO uint32_t*)0x4005C24CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 2) */ + #define REG_PWM1_CPRDUPD2 (*(__O uint32_t*)0x4005C250U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 2) */ + #define REG_PWM1_CCNT2 (*(__I uint32_t*)0x4005C254U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 2) */ + #define REG_PWM1_DT2 (*(__IO uint32_t*)0x4005C258U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 2) */ + #define REG_PWM1_DTUPD2 (*(__O uint32_t*)0x4005C25CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 2) */ + #define REG_PWM1_CMR3 (*(__IO uint32_t*)0x4005C260U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 3) */ + #define REG_PWM1_CDTY3 (*(__IO uint32_t*)0x4005C264U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 3) */ + #define REG_PWM1_CDTYUPD3 (*(__O uint32_t*)0x4005C268U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 3) */ + #define REG_PWM1_CPRD3 (*(__IO uint32_t*)0x4005C26CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 3) */ + #define REG_PWM1_CPRDUPD3 (*(__O uint32_t*)0x4005C270U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 3) */ + #define REG_PWM1_CCNT3 (*(__I uint32_t*)0x4005C274U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 3) */ + #define REG_PWM1_DT3 (*(__IO uint32_t*)0x4005C278U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 3) */ + #define REG_PWM1_DTUPD3 (*(__O uint32_t*)0x4005C27CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 3) */ + #define REG_PWM1_CMUPD0 (*(__O uint32_t*)0x4005C400U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 0) */ + #define REG_PWM1_CMUPD1 (*(__O uint32_t*)0x4005C420U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 1) */ + #define REG_PWM1_ETRG1 (*(__IO uint32_t*)0x4005C42CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 1) */ + #define REG_PWM1_LEBR1 (*(__IO uint32_t*)0x4005C430U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 1) */ + #define REG_PWM1_CMUPD2 (*(__O uint32_t*)0x4005C440U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 2) */ + #define REG_PWM1_ETRG2 (*(__IO uint32_t*)0x4005C44CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 2) */ + #define REG_PWM1_LEBR2 (*(__IO uint32_t*)0x4005C450U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 2) */ + #define REG_PWM1_CMUPD3 (*(__O uint32_t*)0x4005C460U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 3) */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_PWM1_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/qspi.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/qspi.h new file mode 100644 index 000000000..0705e815d --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/qspi.h @@ -0,0 +1,77 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_QSPI_INSTANCE_ +#define _SAME70_QSPI_INSTANCE_ + +/* ========== Register definition for QSPI peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_QSPI_CR (0x4007C000U) /**< \brief (QSPI) Control Register */ + #define REG_QSPI_MR (0x4007C004U) /**< \brief (QSPI) Mode Register */ + #define REG_QSPI_RDR (0x4007C008U) /**< \brief (QSPI) Receive Data Register */ + #define REG_QSPI_TDR (0x4007C00CU) /**< \brief (QSPI) Transmit Data Register */ + #define REG_QSPI_SR (0x4007C010U) /**< \brief (QSPI) Status Register */ + #define REG_QSPI_IER (0x4007C014U) /**< \brief (QSPI) Interrupt Enable Register */ + #define REG_QSPI_IDR (0x4007C018U) /**< \brief (QSPI) Interrupt Disable Register */ + #define REG_QSPI_IMR (0x4007C01CU) /**< \brief (QSPI) Interrupt Mask Register */ + #define REG_QSPI_SCR (0x4007C020U) /**< \brief (QSPI) Serial Clock Register */ + #define REG_QSPI_IAR (0x4007C030U) /**< \brief (QSPI) Instruction Address Register */ + #define REG_QSPI_ICR (0x4007C034U) /**< \brief (QSPI) Instruction Code Register */ + #define REG_QSPI_IFR (0x4007C038U) /**< \brief (QSPI) Instruction Frame Register */ + #define REG_QSPI_SMR (0x4007C040U) /**< \brief (QSPI) Scrambling Mode Register */ + #define REG_QSPI_SKR (0x4007C044U) /**< \brief (QSPI) Scrambling Key Register */ + #define REG_QSPI_WPMR (0x4007C0E4U) /**< \brief (QSPI) Write Protection Mode Register */ + #define REG_QSPI_WPSR (0x4007C0E8U) /**< \brief (QSPI) Write Protection Status Register */ + #define REG_QSPI_VERSION (0x4007C0FCU) /**< \brief (QSPI) Version Register */ +#else + #define REG_QSPI_CR (*(__O uint32_t*)0x4007C000U) /**< \brief (QSPI) Control Register */ + #define REG_QSPI_MR (*(__IO uint32_t*)0x4007C004U) /**< \brief (QSPI) Mode Register */ + #define REG_QSPI_RDR (*(__I uint32_t*)0x4007C008U) /**< \brief (QSPI) Receive Data Register */ + #define REG_QSPI_TDR (*(__O uint32_t*)0x4007C00CU) /**< \brief (QSPI) Transmit Data Register */ + #define REG_QSPI_SR (*(__I uint32_t*)0x4007C010U) /**< \brief (QSPI) Status Register */ + #define REG_QSPI_IER (*(__O uint32_t*)0x4007C014U) /**< \brief (QSPI) Interrupt Enable Register */ + #define REG_QSPI_IDR (*(__O uint32_t*)0x4007C018U) /**< \brief (QSPI) Interrupt Disable Register */ + #define REG_QSPI_IMR (*(__I uint32_t*)0x4007C01CU) /**< \brief (QSPI) Interrupt Mask Register */ + #define REG_QSPI_SCR (*(__IO uint32_t*)0x4007C020U) /**< \brief (QSPI) Serial Clock Register */ + #define REG_QSPI_IAR (*(__IO uint32_t*)0x4007C030U) /**< \brief (QSPI) Instruction Address Register */ + #define REG_QSPI_ICR (*(__IO uint32_t*)0x4007C034U) /**< \brief (QSPI) Instruction Code Register */ + #define REG_QSPI_IFR (*(__IO uint32_t*)0x4007C038U) /**< \brief (QSPI) Instruction Frame Register */ + #define REG_QSPI_SMR (*(__IO uint32_t*)0x4007C040U) /**< \brief (QSPI) Scrambling Mode Register */ + #define REG_QSPI_SKR (*(__O uint32_t*)0x4007C044U) /**< \brief (QSPI) Scrambling Key Register */ + #define REG_QSPI_WPMR (*(__IO uint32_t*)0x4007C0E4U) /**< \brief (QSPI) Write Protection Mode Register */ + #define REG_QSPI_WPSR (*(__I uint32_t*)0x4007C0E8U) /**< \brief (QSPI) Write Protection Status Register */ + #define REG_QSPI_VERSION (*(__I uint32_t*)0x4007C0FCU) /**< \brief (QSPI) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_QSPI_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/rstc.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/rstc.h new file mode 100644 index 000000000..d9a2e52bb --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/rstc.h @@ -0,0 +1,49 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_RSTC_INSTANCE_ +#define _SAME70_RSTC_INSTANCE_ + +/* ========== Register definition for RSTC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_RSTC_CR (0x400E1800U) /**< \brief (RSTC) Control Register */ + #define REG_RSTC_SR (0x400E1804U) /**< \brief (RSTC) Status Register */ + #define REG_RSTC_MR (0x400E1808U) /**< \brief (RSTC) Mode Register */ +#else + #define REG_RSTC_CR (*(__O uint32_t*)0x400E1800U) /**< \brief (RSTC) Control Register */ + #define REG_RSTC_SR (*(__I uint32_t*)0x400E1804U) /**< \brief (RSTC) Status Register */ + #define REG_RSTC_MR (*(__IO uint32_t*)0x400E1808U) /**< \brief (RSTC) Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_RSTC_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/rswdt.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/rswdt.h new file mode 100644 index 000000000..572d024df --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/rswdt.h @@ -0,0 +1,48 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef _SAME70_RSWDT_INSTANCE_ +#define _SAME70_RSWDT_INSTANCE_ + +/* ========== Register definition for RSWDT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_RSWDT_CR (0x400E1900U) /**< \brief (RSWDT) Control Register */ + #define REG_RSWDT_MR (0x400E1904U) /**< \brief (RSWDT) Mode Register */ + #define REG_RSWDT_SR (0x400E1908U) /**< \brief (RSWDT) Status Register */ +#else + #define REG_RSWDT_CR (*(__O uint32_t*)0x400E1900U) /**< \brief (RSWDT) Control Register */ + #define REG_RSWDT_MR (*(__IO uint32_t*)0x400E1904U) /**< \brief (RSWDT) Mode Register */ + #define REG_RSWDT_SR (*(__I uint32_t*)0x400E1908U) /**< \brief (RSWDT) Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_RSWDT_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/rtc.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/rtc.h new file mode 100644 index 000000000..cdbd2bee6 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/rtc.h @@ -0,0 +1,71 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_RTC_INSTANCE_ +#define _SAME70_RTC_INSTANCE_ + +/* ========== Register definition for RTC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_RTC_CR (0x400E1860U) /**< \brief (RTC) Control Register */ + #define REG_RTC_MR (0x400E1864U) /**< \brief (RTC) Mode Register */ + #define REG_RTC_TIMR (0x400E1868U) /**< \brief (RTC) Time Register */ + #define REG_RTC_CALR (0x400E186CU) /**< \brief (RTC) Calendar Register */ + #define REG_RTC_TIMALR (0x400E1870U) /**< \brief (RTC) Time Alarm Register */ + #define REG_RTC_CALALR (0x400E1874U) /**< \brief (RTC) Calendar Alarm Register */ + #define REG_RTC_SR (0x400E1878U) /**< \brief (RTC) Status Register */ + #define REG_RTC_SCCR (0x400E187CU) /**< \brief (RTC) Status Clear Command Register */ + #define REG_RTC_IER (0x400E1880U) /**< \brief (RTC) Interrupt Enable Register */ + #define REG_RTC_IDR (0x400E1884U) /**< \brief (RTC) Interrupt Disable Register */ + #define REG_RTC_IMR (0x400E1888U) /**< \brief (RTC) Interrupt Mask Register */ + #define REG_RTC_VER (0x400E188CU) /**< \brief (RTC) Valid Entry Register */ + #define REG_RTC_WPMR (0x400E1944U) /**< \brief (RTC) Write Protection Mode Register */ + #define REG_RTC_VERSION (0x400E195CU) /**< \brief (RTC) Version Register */ +#else + #define REG_RTC_CR (*(__IO uint32_t*)0x400E1860U) /**< \brief (RTC) Control Register */ + #define REG_RTC_MR (*(__IO uint32_t*)0x400E1864U) /**< \brief (RTC) Mode Register */ + #define REG_RTC_TIMR (*(__IO uint32_t*)0x400E1868U) /**< \brief (RTC) Time Register */ + #define REG_RTC_CALR (*(__IO uint32_t*)0x400E186CU) /**< \brief (RTC) Calendar Register */ + #define REG_RTC_TIMALR (*(__IO uint32_t*)0x400E1870U) /**< \brief (RTC) Time Alarm Register */ + #define REG_RTC_CALALR (*(__IO uint32_t*)0x400E1874U) /**< \brief (RTC) Calendar Alarm Register */ + #define REG_RTC_SR (*(__I uint32_t*)0x400E1878U) /**< \brief (RTC) Status Register */ + #define REG_RTC_SCCR (*(__O uint32_t*)0x400E187CU) /**< \brief (RTC) Status Clear Command Register */ + #define REG_RTC_IER (*(__O uint32_t*)0x400E1880U) /**< \brief (RTC) Interrupt Enable Register */ + #define REG_RTC_IDR (*(__O uint32_t*)0x400E1884U) /**< \brief (RTC) Interrupt Disable Register */ + #define REG_RTC_IMR (*(__I uint32_t*)0x400E1888U) /**< \brief (RTC) Interrupt Mask Register */ + #define REG_RTC_VER (*(__I uint32_t*)0x400E188CU) /**< \brief (RTC) Valid Entry Register */ + #define REG_RTC_WPMR (*(__IO uint32_t*)0x400E1944U) /**< \brief (RTC) Write Protection Mode Register */ + #define REG_RTC_VERSION (*(__I uint32_t*)0x400E195CU) /**< \brief (RTC) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_RTC_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/rtt.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/rtt.h new file mode 100644 index 000000000..d156c84fa --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/rtt.h @@ -0,0 +1,51 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_RTT_INSTANCE_ +#define _SAME70_RTT_INSTANCE_ + +/* ========== Register definition for RTT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_RTT_MR (0x400E1830U) /**< \brief (RTT) Mode Register */ + #define REG_RTT_AR (0x400E1834U) /**< \brief (RTT) Alarm Register */ + #define REG_RTT_VR (0x400E1838U) /**< \brief (RTT) Value Register */ + #define REG_RTT_SR (0x400E183CU) /**< \brief (RTT) Status Register */ +#else + #define REG_RTT_MR (*(__IO uint32_t*)0x400E1830U) /**< \brief (RTT) Mode Register */ + #define REG_RTT_AR (*(__IO uint32_t*)0x400E1834U) /**< \brief (RTT) Alarm Register */ + #define REG_RTT_VR (*(__I uint32_t*)0x400E1838U) /**< \brief (RTT) Value Register */ + #define REG_RTT_SR (*(__I uint32_t*)0x400E183CU) /**< \brief (RTT) Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_RTT_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/sdramc.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/sdramc.h new file mode 100644 index 000000000..ee2294080 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/sdramc.h @@ -0,0 +1,71 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_SDRAMC_INSTANCE_ +#define _SAME70_SDRAMC_INSTANCE_ + +/* ========== Register definition for SDRAMC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_SDRAMC_MR (0x40084000U) /**< \brief (SDRAMC) SDRAMC Mode Register */ + #define REG_SDRAMC_TR (0x40084004U) /**< \brief (SDRAMC) SDRAMC Refresh Timer Register */ + #define REG_SDRAMC_CR (0x40084008U) /**< \brief (SDRAMC) SDRAMC Configuration Register */ + #define REG_SDRAMC_LPR (0x40084010U) /**< \brief (SDRAMC) SDRAMC Low Power Register */ + #define REG_SDRAMC_IER (0x40084014U) /**< \brief (SDRAMC) SDRAMC Interrupt Enable Register */ + #define REG_SDRAMC_IDR (0x40084018U) /**< \brief (SDRAMC) SDRAMC Interrupt Disable Register */ + #define REG_SDRAMC_IMR (0x4008401CU) /**< \brief (SDRAMC) SDRAMC Interrupt Mask Register */ + #define REG_SDRAMC_ISR (0x40084020U) /**< \brief (SDRAMC) SDRAMC Interrupt Status Register */ + #define REG_SDRAMC_MDR (0x40084024U) /**< \brief (SDRAMC) SDRAMC Memory Device Register */ + #define REG_SDRAMC_CFR1 (0x40084028U) /**< \brief (SDRAMC) SDRAMC Configuration Register 1 */ + #define REG_SDRAMC_OCMS (0x4008402CU) /**< \brief (SDRAMC) SDRAMC OCMS Register */ + #define REG_SDRAMC_OCMS_KEY1 (0x40084030U) /**< \brief (SDRAMC) SDRAMC OCMS KEY1 Register */ + #define REG_SDRAMC_OCMS_KEY2 (0x40084034U) /**< \brief (SDRAMC) SDRAMC OCMS KEY2 Register */ + #define REG_SDRAMC_VERSION (0x400840FCU) /**< \brief (SDRAMC) SDRAMC Version Register */ +#else + #define REG_SDRAMC_MR (*(__IO uint32_t*)0x40084000U) /**< \brief (SDRAMC) SDRAMC Mode Register */ + #define REG_SDRAMC_TR (*(__IO uint32_t*)0x40084004U) /**< \brief (SDRAMC) SDRAMC Refresh Timer Register */ + #define REG_SDRAMC_CR (*(__IO uint32_t*)0x40084008U) /**< \brief (SDRAMC) SDRAMC Configuration Register */ + #define REG_SDRAMC_LPR (*(__IO uint32_t*)0x40084010U) /**< \brief (SDRAMC) SDRAMC Low Power Register */ + #define REG_SDRAMC_IER (*(__O uint32_t*)0x40084014U) /**< \brief (SDRAMC) SDRAMC Interrupt Enable Register */ + #define REG_SDRAMC_IDR (*(__O uint32_t*)0x40084018U) /**< \brief (SDRAMC) SDRAMC Interrupt Disable Register */ + #define REG_SDRAMC_IMR (*(__I uint32_t*)0x4008401CU) /**< \brief (SDRAMC) SDRAMC Interrupt Mask Register */ + #define REG_SDRAMC_ISR (*(__I uint32_t*)0x40084020U) /**< \brief (SDRAMC) SDRAMC Interrupt Status Register */ + #define REG_SDRAMC_MDR (*(__IO uint32_t*)0x40084024U) /**< \brief (SDRAMC) SDRAMC Memory Device Register */ + #define REG_SDRAMC_CFR1 (*(__IO uint32_t*)0x40084028U) /**< \brief (SDRAMC) SDRAMC Configuration Register 1 */ + #define REG_SDRAMC_OCMS (*(__IO uint32_t*)0x4008402CU) /**< \brief (SDRAMC) SDRAMC OCMS Register */ + #define REG_SDRAMC_OCMS_KEY1 (*(__O uint32_t*)0x40084030U) /**< \brief (SDRAMC) SDRAMC OCMS KEY1 Register */ + #define REG_SDRAMC_OCMS_KEY2 (*(__O uint32_t*)0x40084034U) /**< \brief (SDRAMC) SDRAMC OCMS KEY2 Register */ + #define REG_SDRAMC_VERSION (*(__I uint32_t*)0x400840FCU) /**< \brief (SDRAMC) SDRAMC Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_SDRAMC_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/smc.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/smc.h new file mode 100644 index 000000000..9a5c87766 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/smc.h @@ -0,0 +1,87 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_SMC_INSTANCE_ +#define _SAME70_SMC_INSTANCE_ + +/* ========== Register definition for SMC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_SMC_SETUP0 (0x40080000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */ + #define REG_SMC_PULSE0 (0x40080004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */ + #define REG_SMC_CYCLE0 (0x40080008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */ + #define REG_SMC_MODE0 (0x4008000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */ + #define REG_SMC_SETUP1 (0x40080010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */ + #define REG_SMC_PULSE1 (0x40080014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */ + #define REG_SMC_CYCLE1 (0x40080018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */ + #define REG_SMC_MODE1 (0x4008001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */ + #define REG_SMC_SETUP2 (0x40080020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */ + #define REG_SMC_PULSE2 (0x40080024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */ + #define REG_SMC_CYCLE2 (0x40080028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */ + #define REG_SMC_MODE2 (0x4008002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */ + #define REG_SMC_SETUP3 (0x40080030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */ + #define REG_SMC_PULSE3 (0x40080034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */ + #define REG_SMC_CYCLE3 (0x40080038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */ + #define REG_SMC_MODE3 (0x4008003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */ + #define REG_SMC_OCMS (0x40080080U) /**< \brief (SMC) SMC Off-Chip Memory Scrambling Register */ + #define REG_SMC_KEY1 (0x40080084U) /**< \brief (SMC) SMC Off-Chip Memory Scrambling KEY1 Register */ + #define REG_SMC_KEY2 (0x40080088U) /**< \brief (SMC) SMC Off-Chip Memory Scrambling KEY2 Register */ + #define REG_SMC_WPMR (0x400800E4U) /**< \brief (SMC) SMC Write Protection Mode Register */ + #define REG_SMC_WPSR (0x400800E8U) /**< \brief (SMC) SMC Write Protection Status Register */ + #define REG_SMC_VERSION (0x400800FCU) /**< \brief (SMC) SMC Version Register */ +#else + #define REG_SMC_SETUP0 (*(__IO uint32_t*)0x40080000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */ + #define REG_SMC_PULSE0 (*(__IO uint32_t*)0x40080004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */ + #define REG_SMC_CYCLE0 (*(__IO uint32_t*)0x40080008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */ + #define REG_SMC_MODE0 (*(__IO uint32_t*)0x4008000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */ + #define REG_SMC_SETUP1 (*(__IO uint32_t*)0x40080010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */ + #define REG_SMC_PULSE1 (*(__IO uint32_t*)0x40080014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */ + #define REG_SMC_CYCLE1 (*(__IO uint32_t*)0x40080018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */ + #define REG_SMC_MODE1 (*(__IO uint32_t*)0x4008001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */ + #define REG_SMC_SETUP2 (*(__IO uint32_t*)0x40080020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */ + #define REG_SMC_PULSE2 (*(__IO uint32_t*)0x40080024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */ + #define REG_SMC_CYCLE2 (*(__IO uint32_t*)0x40080028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */ + #define REG_SMC_MODE2 (*(__IO uint32_t*)0x4008002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */ + #define REG_SMC_SETUP3 (*(__IO uint32_t*)0x40080030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */ + #define REG_SMC_PULSE3 (*(__IO uint32_t*)0x40080034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */ + #define REG_SMC_CYCLE3 (*(__IO uint32_t*)0x40080038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */ + #define REG_SMC_MODE3 (*(__IO uint32_t*)0x4008003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */ + #define REG_SMC_OCMS (*(__IO uint32_t*)0x40080080U) /**< \brief (SMC) SMC Off-Chip Memory Scrambling Register */ + #define REG_SMC_KEY1 (*(__O uint32_t*)0x40080084U) /**< \brief (SMC) SMC Off-Chip Memory Scrambling KEY1 Register */ + #define REG_SMC_KEY2 (*(__O uint32_t*)0x40080088U) /**< \brief (SMC) SMC Off-Chip Memory Scrambling KEY2 Register */ + #define REG_SMC_WPMR (*(__IO uint32_t*)0x400800E4U) /**< \brief (SMC) SMC Write Protection Mode Register */ + #define REG_SMC_WPSR (*(__I uint32_t*)0x400800E8U) /**< \brief (SMC) SMC Write Protection Status Register */ + #define REG_SMC_VERSION (*(__I uint32_t*)0x400800FCU) /**< \brief (SMC) SMC Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_SMC_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/spi0.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/spi0.h new file mode 100644 index 000000000..52c70284d --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/spi0.h @@ -0,0 +1,67 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_SPI0_INSTANCE_ +#define _SAME70_SPI0_INSTANCE_ + +/* ========== Register definition for SPI0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_SPI0_CR (0x40008000U) /**< \brief (SPI0) Control Register */ + #define REG_SPI0_MR (0x40008004U) /**< \brief (SPI0) Mode Register */ + #define REG_SPI0_RDR (0x40008008U) /**< \brief (SPI0) Receive Data Register */ + #define REG_SPI0_TDR (0x4000800CU) /**< \brief (SPI0) Transmit Data Register */ + #define REG_SPI0_SR (0x40008010U) /**< \brief (SPI0) Status Register */ + #define REG_SPI0_IER (0x40008014U) /**< \brief (SPI0) Interrupt Enable Register */ + #define REG_SPI0_IDR (0x40008018U) /**< \brief (SPI0) Interrupt Disable Register */ + #define REG_SPI0_IMR (0x4000801CU) /**< \brief (SPI0) Interrupt Mask Register */ + #define REG_SPI0_CSR (0x40008030U) /**< \brief (SPI0) Chip Select Register (CS_number = 0) */ + #define REG_SPI0_WPMR (0x400080E4U) /**< \brief (SPI0) Write Protection Mode Register */ + #define REG_SPI0_WPSR (0x400080E8U) /**< \brief (SPI0) Write Protection Status Register */ + #define REG_SPI0_VERSION (0x400080FCU) /**< \brief (SPI0) Version Register */ +#else + #define REG_SPI0_CR (*(__O uint32_t*)0x40008000U) /**< \brief (SPI0) Control Register */ + #define REG_SPI0_MR (*(__IO uint32_t*)0x40008004U) /**< \brief (SPI0) Mode Register */ + #define REG_SPI0_RDR (*(__I uint32_t*)0x40008008U) /**< \brief (SPI0) Receive Data Register */ + #define REG_SPI0_TDR (*(__O uint32_t*)0x4000800CU) /**< \brief (SPI0) Transmit Data Register */ + #define REG_SPI0_SR (*(__I uint32_t*)0x40008010U) /**< \brief (SPI0) Status Register */ + #define REG_SPI0_IER (*(__O uint32_t*)0x40008014U) /**< \brief (SPI0) Interrupt Enable Register */ + #define REG_SPI0_IDR (*(__O uint32_t*)0x40008018U) /**< \brief (SPI0) Interrupt Disable Register */ + #define REG_SPI0_IMR (*(__I uint32_t*)0x4000801CU) /**< \brief (SPI0) Interrupt Mask Register */ + #define REG_SPI0_CSR (*(__IO uint32_t*)0x40008030U) /**< \brief (SPI0) Chip Select Register (CS_number = 0) */ + #define REG_SPI0_WPMR (*(__IO uint32_t*)0x400080E4U) /**< \brief (SPI0) Write Protection Mode Register */ + #define REG_SPI0_WPSR (*(__I uint32_t*)0x400080E8U) /**< \brief (SPI0) Write Protection Status Register */ + #define REG_SPI0_VERSION (*(__I uint32_t*)0x400080FCU) /**< \brief (SPI0) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_SPI0_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/spi1.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/spi1.h new file mode 100644 index 000000000..d7db3d071 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/spi1.h @@ -0,0 +1,67 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_SPI1_INSTANCE_ +#define _SAME70_SPI1_INSTANCE_ + +/* ========== Register definition for SPI1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_SPI1_CR (0x40058000U) /**< \brief (SPI1) Control Register */ + #define REG_SPI1_MR (0x40058004U) /**< \brief (SPI1) Mode Register */ + #define REG_SPI1_RDR (0x40058008U) /**< \brief (SPI1) Receive Data Register */ + #define REG_SPI1_TDR (0x4005800CU) /**< \brief (SPI1) Transmit Data Register */ + #define REG_SPI1_SR (0x40058010U) /**< \brief (SPI1) Status Register */ + #define REG_SPI1_IER (0x40058014U) /**< \brief (SPI1) Interrupt Enable Register */ + #define REG_SPI1_IDR (0x40058018U) /**< \brief (SPI1) Interrupt Disable Register */ + #define REG_SPI1_IMR (0x4005801CU) /**< \brief (SPI1) Interrupt Mask Register */ + #define REG_SPI1_CSR (0x40058030U) /**< \brief (SPI1) Chip Select Register (CS_number = 0) */ + #define REG_SPI1_WPMR (0x400580E4U) /**< \brief (SPI1) Write Protection Mode Register */ + #define REG_SPI1_WPSR (0x400580E8U) /**< \brief (SPI1) Write Protection Status Register */ + #define REG_SPI1_VERSION (0x400580FCU) /**< \brief (SPI1) Version Register */ +#else + #define REG_SPI1_CR (*(__O uint32_t*)0x40058000U) /**< \brief (SPI1) Control Register */ + #define REG_SPI1_MR (*(__IO uint32_t*)0x40058004U) /**< \brief (SPI1) Mode Register */ + #define REG_SPI1_RDR (*(__I uint32_t*)0x40058008U) /**< \brief (SPI1) Receive Data Register */ + #define REG_SPI1_TDR (*(__O uint32_t*)0x4005800CU) /**< \brief (SPI1) Transmit Data Register */ + #define REG_SPI1_SR (*(__I uint32_t*)0x40058010U) /**< \brief (SPI1) Status Register */ + #define REG_SPI1_IER (*(__O uint32_t*)0x40058014U) /**< \brief (SPI1) Interrupt Enable Register */ + #define REG_SPI1_IDR (*(__O uint32_t*)0x40058018U) /**< \brief (SPI1) Interrupt Disable Register */ + #define REG_SPI1_IMR (*(__I uint32_t*)0x4005801CU) /**< \brief (SPI1) Interrupt Mask Register */ + #define REG_SPI1_CSR (*(__IO uint32_t*)0x40058030U) /**< \brief (SPI1) Chip Select Register (CS_number = 0) */ + #define REG_SPI1_WPMR (*(__IO uint32_t*)0x400580E4U) /**< \brief (SPI1) Write Protection Mode Register */ + #define REG_SPI1_WPSR (*(__I uint32_t*)0x400580E8U) /**< \brief (SPI1) Write Protection Status Register */ + #define REG_SPI1_VERSION (*(__I uint32_t*)0x400580FCU) /**< \brief (SPI1) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_SPI1_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/ssc.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/ssc.h new file mode 100644 index 000000000..706f13dd3 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/ssc.h @@ -0,0 +1,81 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_SSC_INSTANCE_ +#define _SAME70_SSC_INSTANCE_ + +/* ========== Register definition for SSC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_SSC_CR (0x40004000U) /**< \brief (SSC) Control Register */ + #define REG_SSC_CMR (0x40004004U) /**< \brief (SSC) Clock Mode Register */ + #define REG_SSC_RCMR (0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */ + #define REG_SSC_RFMR (0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */ + #define REG_SSC_TCMR (0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */ + #define REG_SSC_TFMR (0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */ + #define REG_SSC_RHR (0x40004020U) /**< \brief (SSC) Receive Holding Register */ + #define REG_SSC_THR (0x40004024U) /**< \brief (SSC) Transmit Holding Register */ + #define REG_SSC_RSHR (0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */ + #define REG_SSC_TSHR (0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */ + #define REG_SSC_RC0R (0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */ + #define REG_SSC_RC1R (0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */ + #define REG_SSC_SR (0x40004040U) /**< \brief (SSC) Status Register */ + #define REG_SSC_IER (0x40004044U) /**< \brief (SSC) Interrupt Enable Register */ + #define REG_SSC_IDR (0x40004048U) /**< \brief (SSC) Interrupt Disable Register */ + #define REG_SSC_IMR (0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */ + #define REG_SSC_WPMR (0x400040E4U) /**< \brief (SSC) Write Protection Mode Register */ + #define REG_SSC_WPSR (0x400040E8U) /**< \brief (SSC) Write Protection Status Register */ + #define REG_SSC_VERSION (0x400040FCU) /**< \brief (SSC) Version Register */ +#else + #define REG_SSC_CR (*(__O uint32_t*)0x40004000U) /**< \brief (SSC) Control Register */ + #define REG_SSC_CMR (*(__IO uint32_t*)0x40004004U) /**< \brief (SSC) Clock Mode Register */ + #define REG_SSC_RCMR (*(__IO uint32_t*)0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */ + #define REG_SSC_RFMR (*(__IO uint32_t*)0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */ + #define REG_SSC_TCMR (*(__IO uint32_t*)0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */ + #define REG_SSC_TFMR (*(__IO uint32_t*)0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */ + #define REG_SSC_RHR (*(__I uint32_t*)0x40004020U) /**< \brief (SSC) Receive Holding Register */ + #define REG_SSC_THR (*(__O uint32_t*)0x40004024U) /**< \brief (SSC) Transmit Holding Register */ + #define REG_SSC_RSHR (*(__I uint32_t*)0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */ + #define REG_SSC_TSHR (*(__IO uint32_t*)0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */ + #define REG_SSC_RC0R (*(__IO uint32_t*)0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */ + #define REG_SSC_RC1R (*(__IO uint32_t*)0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */ + #define REG_SSC_SR (*(__I uint32_t*)0x40004040U) /**< \brief (SSC) Status Register */ + #define REG_SSC_IER (*(__O uint32_t*)0x40004044U) /**< \brief (SSC) Interrupt Enable Register */ + #define REG_SSC_IDR (*(__O uint32_t*)0x40004048U) /**< \brief (SSC) Interrupt Disable Register */ + #define REG_SSC_IMR (*(__I uint32_t*)0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */ + #define REG_SSC_WPMR (*(__IO uint32_t*)0x400040E4U) /**< \brief (SSC) Write Protection Mode Register */ + #define REG_SSC_WPSR (*(__I uint32_t*)0x400040E8U) /**< \brief (SSC) Write Protection Status Register */ + #define REG_SSC_VERSION (*(__I uint32_t*)0x400040FCU) /**< \brief (SSC) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_SSC_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/supc.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/supc.h new file mode 100644 index 000000000..dee9e81b6 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/supc.h @@ -0,0 +1,57 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_SUPC_INSTANCE_ +#define _SAME70_SUPC_INSTANCE_ + +/* ========== Register definition for SUPC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_SUPC_CR (0x400E1810U) /**< \brief (SUPC) Supply Controller Control Register */ + #define REG_SUPC_SMMR (0x400E1814U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */ + #define REG_SUPC_MR (0x400E1818U) /**< \brief (SUPC) Supply Controller Mode Register */ + #define REG_SUPC_WUMR (0x400E181CU) /**< \brief (SUPC) Supply Controller Wake-up Mode Register */ + #define REG_SUPC_WUIR (0x400E1820U) /**< \brief (SUPC) Supply Controller Wake-up Inputs Register */ + #define REG_SUPC_SR (0x400E1824U) /**< \brief (SUPC) Supply Controller Status Register */ + #define REG_SYSC_VERSION (0x400E190CU) /**< \brief (SUPC) Version Register */ +#else + #define REG_SUPC_CR (*(__O uint32_t*)0x400E1810U) /**< \brief (SUPC) Supply Controller Control Register */ + #define REG_SUPC_SMMR (*(__IO uint32_t*)0x400E1814U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */ + #define REG_SUPC_MR (*(__IO uint32_t*)0x400E1818U) /**< \brief (SUPC) Supply Controller Mode Register */ + #define REG_SUPC_WUMR (*(__IO uint32_t*)0x400E181CU) /**< \brief (SUPC) Supply Controller Wake-up Mode Register */ + #define REG_SUPC_WUIR (*(__IO uint32_t*)0x400E1820U) /**< \brief (SUPC) Supply Controller Wake-up Inputs Register */ + #define REG_SUPC_SR (*(__I uint32_t*)0x400E1824U) /**< \brief (SUPC) Supply Controller Status Register */ + #define REG_SYSC_VERSION (*(__I uint32_t*)0x400E190CU) /**< \brief (SUPC) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_SUPC_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/tc0.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/tc0.h new file mode 100644 index 000000000..e2cc24618 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/tc0.h @@ -0,0 +1,139 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_TC0_INSTANCE_ +#define _SAME70_TC0_INSTANCE_ + +/* ========== Register definition for TC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TC0_CCR0 (0x4000C000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ + #define REG_TC0_CMR0 (0x4000C004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ + #define REG_TC0_SMMR0 (0x4000C008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC0_RAB0 (0x4000C00CU) /**< \brief (TC0) Register AB (channel = 0) */ + #define REG_TC0_CV0 (0x4000C010U) /**< \brief (TC0) Counter Value (channel = 0) */ + #define REG_TC0_RA0 (0x4000C014U) /**< \brief (TC0) Register A (channel = 0) */ + #define REG_TC0_RB0 (0x4000C018U) /**< \brief (TC0) Register B (channel = 0) */ + #define REG_TC0_RC0 (0x4000C01CU) /**< \brief (TC0) Register C (channel = 0) */ + #define REG_TC0_SR0 (0x4000C020U) /**< \brief (TC0) Status Register (channel = 0) */ + #define REG_TC0_IER0 (0x4000C024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ + #define REG_TC0_IDR0 (0x4000C028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ + #define REG_TC0_IMR0 (0x4000C02CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ + #define REG_TC0_EMR0 (0x4000C030U) /**< \brief (TC0) Extended Mode Register (channel = 0) */ + #define REG_TC0_CCR1 (0x4000C040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ + #define REG_TC0_CMR1 (0x4000C044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ + #define REG_TC0_SMMR1 (0x4000C048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC0_RAB1 (0x4000C04CU) /**< \brief (TC0) Register AB (channel = 1) */ + #define REG_TC0_CV1 (0x4000C050U) /**< \brief (TC0) Counter Value (channel = 1) */ + #define REG_TC0_RA1 (0x4000C054U) /**< \brief (TC0) Register A (channel = 1) */ + #define REG_TC0_RB1 (0x4000C058U) /**< \brief (TC0) Register B (channel = 1) */ + #define REG_TC0_RC1 (0x4000C05CU) /**< \brief (TC0) Register C (channel = 1) */ + #define REG_TC0_SR1 (0x4000C060U) /**< \brief (TC0) Status Register (channel = 1) */ + #define REG_TC0_IER1 (0x4000C064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ + #define REG_TC0_IDR1 (0x4000C068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ + #define REG_TC0_IMR1 (0x4000C06CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ + #define REG_TC0_EMR1 (0x4000C070U) /**< \brief (TC0) Extended Mode Register (channel = 1) */ + #define REG_TC0_CCR2 (0x4000C080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ + #define REG_TC0_CMR2 (0x4000C084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ + #define REG_TC0_SMMR2 (0x4000C088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC0_RAB2 (0x4000C08CU) /**< \brief (TC0) Register AB (channel = 2) */ + #define REG_TC0_CV2 (0x4000C090U) /**< \brief (TC0) Counter Value (channel = 2) */ + #define REG_TC0_RA2 (0x4000C094U) /**< \brief (TC0) Register A (channel = 2) */ + #define REG_TC0_RB2 (0x4000C098U) /**< \brief (TC0) Register B (channel = 2) */ + #define REG_TC0_RC2 (0x4000C09CU) /**< \brief (TC0) Register C (channel = 2) */ + #define REG_TC0_SR2 (0x4000C0A0U) /**< \brief (TC0) Status Register (channel = 2) */ + #define REG_TC0_IER2 (0x4000C0A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ + #define REG_TC0_IDR2 (0x4000C0A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ + #define REG_TC0_IMR2 (0x4000C0ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ + #define REG_TC0_EMR2 (0x4000C0B0U) /**< \brief (TC0) Extended Mode Register (channel = 2) */ + #define REG_TC0_BCR (0x4000C0C0U) /**< \brief (TC0) Block Control Register */ + #define REG_TC0_BMR (0x4000C0C4U) /**< \brief (TC0) Block Mode Register */ + #define REG_TC0_QIER (0x4000C0C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */ + #define REG_TC0_QIDR (0x4000C0CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */ + #define REG_TC0_QIMR (0x4000C0D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */ + #define REG_TC0_QISR (0x4000C0D4U) /**< \brief (TC0) QDEC Interrupt Status Register */ + #define REG_TC0_FMR (0x4000C0D8U) /**< \brief (TC0) Fault Mode Register */ + #define REG_TC0_WPMR (0x4000C0E4U) /**< \brief (TC0) Write Protection Mode Register */ + #define REG_TC0_VER (0x4000C0FCU) /**< \brief (TC0) Version Register */ +#else + #define REG_TC0_CCR0 (*(__O uint32_t*)0x4000C000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ + #define REG_TC0_CMR0 (*(__IO uint32_t*)0x4000C004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ + #define REG_TC0_SMMR0 (*(__IO uint32_t*)0x4000C008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC0_RAB0 (*(__I uint32_t*)0x4000C00CU) /**< \brief (TC0) Register AB (channel = 0) */ + #define REG_TC0_CV0 (*(__I uint32_t*)0x4000C010U) /**< \brief (TC0) Counter Value (channel = 0) */ + #define REG_TC0_RA0 (*(__IO uint32_t*)0x4000C014U) /**< \brief (TC0) Register A (channel = 0) */ + #define REG_TC0_RB0 (*(__IO uint32_t*)0x4000C018U) /**< \brief (TC0) Register B (channel = 0) */ + #define REG_TC0_RC0 (*(__IO uint32_t*)0x4000C01CU) /**< \brief (TC0) Register C (channel = 0) */ + #define REG_TC0_SR0 (*(__I uint32_t*)0x4000C020U) /**< \brief (TC0) Status Register (channel = 0) */ + #define REG_TC0_IER0 (*(__O uint32_t*)0x4000C024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ + #define REG_TC0_IDR0 (*(__O uint32_t*)0x4000C028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ + #define REG_TC0_IMR0 (*(__I uint32_t*)0x4000C02CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ + #define REG_TC0_EMR0 (*(__IO uint32_t*)0x4000C030U) /**< \brief (TC0) Extended Mode Register (channel = 0) */ + #define REG_TC0_CCR1 (*(__O uint32_t*)0x4000C040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ + #define REG_TC0_CMR1 (*(__IO uint32_t*)0x4000C044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ + #define REG_TC0_SMMR1 (*(__IO uint32_t*)0x4000C048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC0_RAB1 (*(__I uint32_t*)0x4000C04CU) /**< \brief (TC0) Register AB (channel = 1) */ + #define REG_TC0_CV1 (*(__I uint32_t*)0x4000C050U) /**< \brief (TC0) Counter Value (channel = 1) */ + #define REG_TC0_RA1 (*(__IO uint32_t*)0x4000C054U) /**< \brief (TC0) Register A (channel = 1) */ + #define REG_TC0_RB1 (*(__IO uint32_t*)0x4000C058U) /**< \brief (TC0) Register B (channel = 1) */ + #define REG_TC0_RC1 (*(__IO uint32_t*)0x4000C05CU) /**< \brief (TC0) Register C (channel = 1) */ + #define REG_TC0_SR1 (*(__I uint32_t*)0x4000C060U) /**< \brief (TC0) Status Register (channel = 1) */ + #define REG_TC0_IER1 (*(__O uint32_t*)0x4000C064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ + #define REG_TC0_IDR1 (*(__O uint32_t*)0x4000C068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ + #define REG_TC0_IMR1 (*(__I uint32_t*)0x4000C06CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ + #define REG_TC0_EMR1 (*(__IO uint32_t*)0x4000C070U) /**< \brief (TC0) Extended Mode Register (channel = 1) */ + #define REG_TC0_CCR2 (*(__O uint32_t*)0x4000C080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ + #define REG_TC0_CMR2 (*(__IO uint32_t*)0x4000C084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ + #define REG_TC0_SMMR2 (*(__IO uint32_t*)0x4000C088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC0_RAB2 (*(__I uint32_t*)0x4000C08CU) /**< \brief (TC0) Register AB (channel = 2) */ + #define REG_TC0_CV2 (*(__I uint32_t*)0x4000C090U) /**< \brief (TC0) Counter Value (channel = 2) */ + #define REG_TC0_RA2 (*(__IO uint32_t*)0x4000C094U) /**< \brief (TC0) Register A (channel = 2) */ + #define REG_TC0_RB2 (*(__IO uint32_t*)0x4000C098U) /**< \brief (TC0) Register B (channel = 2) */ + #define REG_TC0_RC2 (*(__IO uint32_t*)0x4000C09CU) /**< \brief (TC0) Register C (channel = 2) */ + #define REG_TC0_SR2 (*(__I uint32_t*)0x4000C0A0U) /**< \brief (TC0) Status Register (channel = 2) */ + #define REG_TC0_IER2 (*(__O uint32_t*)0x4000C0A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ + #define REG_TC0_IDR2 (*(__O uint32_t*)0x4000C0A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ + #define REG_TC0_IMR2 (*(__I uint32_t*)0x4000C0ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ + #define REG_TC0_EMR2 (*(__IO uint32_t*)0x4000C0B0U) /**< \brief (TC0) Extended Mode Register (channel = 2) */ + #define REG_TC0_BCR (*(__O uint32_t*)0x4000C0C0U) /**< \brief (TC0) Block Control Register */ + #define REG_TC0_BMR (*(__IO uint32_t*)0x4000C0C4U) /**< \brief (TC0) Block Mode Register */ + #define REG_TC0_QIER (*(__O uint32_t*)0x4000C0C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */ + #define REG_TC0_QIDR (*(__O uint32_t*)0x4000C0CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */ + #define REG_TC0_QIMR (*(__I uint32_t*)0x4000C0D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */ + #define REG_TC0_QISR (*(__I uint32_t*)0x4000C0D4U) /**< \brief (TC0) QDEC Interrupt Status Register */ + #define REG_TC0_FMR (*(__IO uint32_t*)0x4000C0D8U) /**< \brief (TC0) Fault Mode Register */ + #define REG_TC0_WPMR (*(__IO uint32_t*)0x4000C0E4U) /**< \brief (TC0) Write Protection Mode Register */ + #define REG_TC0_VER (*(__I uint32_t*)0x4000C0FCU) /**< \brief (TC0) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_TC0_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/tc1.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/tc1.h new file mode 100644 index 000000000..d8f78fcd6 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/tc1.h @@ -0,0 +1,139 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_TC1_INSTANCE_ +#define _SAME70_TC1_INSTANCE_ + +/* ========== Register definition for TC1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TC1_CCR0 (0x40010000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ + #define REG_TC1_CMR0 (0x40010004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ + #define REG_TC1_SMMR0 (0x40010008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC1_RAB0 (0x4001000CU) /**< \brief (TC1) Register AB (channel = 0) */ + #define REG_TC1_CV0 (0x40010010U) /**< \brief (TC1) Counter Value (channel = 0) */ + #define REG_TC1_RA0 (0x40010014U) /**< \brief (TC1) Register A (channel = 0) */ + #define REG_TC1_RB0 (0x40010018U) /**< \brief (TC1) Register B (channel = 0) */ + #define REG_TC1_RC0 (0x4001001CU) /**< \brief (TC1) Register C (channel = 0) */ + #define REG_TC1_SR0 (0x40010020U) /**< \brief (TC1) Status Register (channel = 0) */ + #define REG_TC1_IER0 (0x40010024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ + #define REG_TC1_IDR0 (0x40010028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ + #define REG_TC1_IMR0 (0x4001002CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ + #define REG_TC1_EMR0 (0x40010030U) /**< \brief (TC1) Extended Mode Register (channel = 0) */ + #define REG_TC1_CCR1 (0x40010040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ + #define REG_TC1_CMR1 (0x40010044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ + #define REG_TC1_SMMR1 (0x40010048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC1_RAB1 (0x4001004CU) /**< \brief (TC1) Register AB (channel = 1) */ + #define REG_TC1_CV1 (0x40010050U) /**< \brief (TC1) Counter Value (channel = 1) */ + #define REG_TC1_RA1 (0x40010054U) /**< \brief (TC1) Register A (channel = 1) */ + #define REG_TC1_RB1 (0x40010058U) /**< \brief (TC1) Register B (channel = 1) */ + #define REG_TC1_RC1 (0x4001005CU) /**< \brief (TC1) Register C (channel = 1) */ + #define REG_TC1_SR1 (0x40010060U) /**< \brief (TC1) Status Register (channel = 1) */ + #define REG_TC1_IER1 (0x40010064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ + #define REG_TC1_IDR1 (0x40010068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ + #define REG_TC1_IMR1 (0x4001006CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ + #define REG_TC1_EMR1 (0x40010070U) /**< \brief (TC1) Extended Mode Register (channel = 1) */ + #define REG_TC1_CCR2 (0x40010080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ + #define REG_TC1_CMR2 (0x40010084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ + #define REG_TC1_SMMR2 (0x40010088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC1_RAB2 (0x4001008CU) /**< \brief (TC1) Register AB (channel = 2) */ + #define REG_TC1_CV2 (0x40010090U) /**< \brief (TC1) Counter Value (channel = 2) */ + #define REG_TC1_RA2 (0x40010094U) /**< \brief (TC1) Register A (channel = 2) */ + #define REG_TC1_RB2 (0x40010098U) /**< \brief (TC1) Register B (channel = 2) */ + #define REG_TC1_RC2 (0x4001009CU) /**< \brief (TC1) Register C (channel = 2) */ + #define REG_TC1_SR2 (0x400100A0U) /**< \brief (TC1) Status Register (channel = 2) */ + #define REG_TC1_IER2 (0x400100A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ + #define REG_TC1_IDR2 (0x400100A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ + #define REG_TC1_IMR2 (0x400100ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ + #define REG_TC1_EMR2 (0x400100B0U) /**< \brief (TC1) Extended Mode Register (channel = 2) */ + #define REG_TC1_BCR (0x400100C0U) /**< \brief (TC1) Block Control Register */ + #define REG_TC1_BMR (0x400100C4U) /**< \brief (TC1) Block Mode Register */ + #define REG_TC1_QIER (0x400100C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */ + #define REG_TC1_QIDR (0x400100CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */ + #define REG_TC1_QIMR (0x400100D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */ + #define REG_TC1_QISR (0x400100D4U) /**< \brief (TC1) QDEC Interrupt Status Register */ + #define REG_TC1_FMR (0x400100D8U) /**< \brief (TC1) Fault Mode Register */ + #define REG_TC1_WPMR (0x400100E4U) /**< \brief (TC1) Write Protection Mode Register */ + #define REG_TC1_VER (0x400100FCU) /**< \brief (TC1) Version Register */ +#else + #define REG_TC1_CCR0 (*(__O uint32_t*)0x40010000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ + #define REG_TC1_CMR0 (*(__IO uint32_t*)0x40010004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ + #define REG_TC1_SMMR0 (*(__IO uint32_t*)0x40010008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC1_RAB0 (*(__I uint32_t*)0x4001000CU) /**< \brief (TC1) Register AB (channel = 0) */ + #define REG_TC1_CV0 (*(__I uint32_t*)0x40010010U) /**< \brief (TC1) Counter Value (channel = 0) */ + #define REG_TC1_RA0 (*(__IO uint32_t*)0x40010014U) /**< \brief (TC1) Register A (channel = 0) */ + #define REG_TC1_RB0 (*(__IO uint32_t*)0x40010018U) /**< \brief (TC1) Register B (channel = 0) */ + #define REG_TC1_RC0 (*(__IO uint32_t*)0x4001001CU) /**< \brief (TC1) Register C (channel = 0) */ + #define REG_TC1_SR0 (*(__I uint32_t*)0x40010020U) /**< \brief (TC1) Status Register (channel = 0) */ + #define REG_TC1_IER0 (*(__O uint32_t*)0x40010024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ + #define REG_TC1_IDR0 (*(__O uint32_t*)0x40010028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ + #define REG_TC1_IMR0 (*(__I uint32_t*)0x4001002CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ + #define REG_TC1_EMR0 (*(__IO uint32_t*)0x40010030U) /**< \brief (TC1) Extended Mode Register (channel = 0) */ + #define REG_TC1_CCR1 (*(__O uint32_t*)0x40010040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ + #define REG_TC1_CMR1 (*(__IO uint32_t*)0x40010044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ + #define REG_TC1_SMMR1 (*(__IO uint32_t*)0x40010048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC1_RAB1 (*(__I uint32_t*)0x4001004CU) /**< \brief (TC1) Register AB (channel = 1) */ + #define REG_TC1_CV1 (*(__I uint32_t*)0x40010050U) /**< \brief (TC1) Counter Value (channel = 1) */ + #define REG_TC1_RA1 (*(__IO uint32_t*)0x40010054U) /**< \brief (TC1) Register A (channel = 1) */ + #define REG_TC1_RB1 (*(__IO uint32_t*)0x40010058U) /**< \brief (TC1) Register B (channel = 1) */ + #define REG_TC1_RC1 (*(__IO uint32_t*)0x4001005CU) /**< \brief (TC1) Register C (channel = 1) */ + #define REG_TC1_SR1 (*(__I uint32_t*)0x40010060U) /**< \brief (TC1) Status Register (channel = 1) */ + #define REG_TC1_IER1 (*(__O uint32_t*)0x40010064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ + #define REG_TC1_IDR1 (*(__O uint32_t*)0x40010068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ + #define REG_TC1_IMR1 (*(__I uint32_t*)0x4001006CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ + #define REG_TC1_EMR1 (*(__IO uint32_t*)0x40010070U) /**< \brief (TC1) Extended Mode Register (channel = 1) */ + #define REG_TC1_CCR2 (*(__O uint32_t*)0x40010080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ + #define REG_TC1_CMR2 (*(__IO uint32_t*)0x40010084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ + #define REG_TC1_SMMR2 (*(__IO uint32_t*)0x40010088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC1_RAB2 (*(__I uint32_t*)0x4001008CU) /**< \brief (TC1) Register AB (channel = 2) */ + #define REG_TC1_CV2 (*(__I uint32_t*)0x40010090U) /**< \brief (TC1) Counter Value (channel = 2) */ + #define REG_TC1_RA2 (*(__IO uint32_t*)0x40010094U) /**< \brief (TC1) Register A (channel = 2) */ + #define REG_TC1_RB2 (*(__IO uint32_t*)0x40010098U) /**< \brief (TC1) Register B (channel = 2) */ + #define REG_TC1_RC2 (*(__IO uint32_t*)0x4001009CU) /**< \brief (TC1) Register C (channel = 2) */ + #define REG_TC1_SR2 (*(__I uint32_t*)0x400100A0U) /**< \brief (TC1) Status Register (channel = 2) */ + #define REG_TC1_IER2 (*(__O uint32_t*)0x400100A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ + #define REG_TC1_IDR2 (*(__O uint32_t*)0x400100A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ + #define REG_TC1_IMR2 (*(__I uint32_t*)0x400100ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ + #define REG_TC1_EMR2 (*(__IO uint32_t*)0x400100B0U) /**< \brief (TC1) Extended Mode Register (channel = 2) */ + #define REG_TC1_BCR (*(__O uint32_t*)0x400100C0U) /**< \brief (TC1) Block Control Register */ + #define REG_TC1_BMR (*(__IO uint32_t*)0x400100C4U) /**< \brief (TC1) Block Mode Register */ + #define REG_TC1_QIER (*(__O uint32_t*)0x400100C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */ + #define REG_TC1_QIDR (*(__O uint32_t*)0x400100CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */ + #define REG_TC1_QIMR (*(__I uint32_t*)0x400100D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */ + #define REG_TC1_QISR (*(__I uint32_t*)0x400100D4U) /**< \brief (TC1) QDEC Interrupt Status Register */ + #define REG_TC1_FMR (*(__IO uint32_t*)0x400100D8U) /**< \brief (TC1) Fault Mode Register */ + #define REG_TC1_WPMR (*(__IO uint32_t*)0x400100E4U) /**< \brief (TC1) Write Protection Mode Register */ + #define REG_TC1_VER (*(__I uint32_t*)0x400100FCU) /**< \brief (TC1) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_TC1_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/tc2.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/tc2.h new file mode 100644 index 000000000..8d4a950cb --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/tc2.h @@ -0,0 +1,139 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_TC2_INSTANCE_ +#define _SAME70_TC2_INSTANCE_ + +/* ========== Register definition for TC2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TC2_CCR0 (0x40014000U) /**< \brief (TC2) Channel Control Register (channel = 0) */ + #define REG_TC2_CMR0 (0x40014004U) /**< \brief (TC2) Channel Mode Register (channel = 0) */ + #define REG_TC2_SMMR0 (0x40014008U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC2_RAB0 (0x4001400CU) /**< \brief (TC2) Register AB (channel = 0) */ + #define REG_TC2_CV0 (0x40014010U) /**< \brief (TC2) Counter Value (channel = 0) */ + #define REG_TC2_RA0 (0x40014014U) /**< \brief (TC2) Register A (channel = 0) */ + #define REG_TC2_RB0 (0x40014018U) /**< \brief (TC2) Register B (channel = 0) */ + #define REG_TC2_RC0 (0x4001401CU) /**< \brief (TC2) Register C (channel = 0) */ + #define REG_TC2_SR0 (0x40014020U) /**< \brief (TC2) Status Register (channel = 0) */ + #define REG_TC2_IER0 (0x40014024U) /**< \brief (TC2) Interrupt Enable Register (channel = 0) */ + #define REG_TC2_IDR0 (0x40014028U) /**< \brief (TC2) Interrupt Disable Register (channel = 0) */ + #define REG_TC2_IMR0 (0x4001402CU) /**< \brief (TC2) Interrupt Mask Register (channel = 0) */ + #define REG_TC2_EMR0 (0x40014030U) /**< \brief (TC2) Extended Mode Register (channel = 0) */ + #define REG_TC2_CCR1 (0x40014040U) /**< \brief (TC2) Channel Control Register (channel = 1) */ + #define REG_TC2_CMR1 (0x40014044U) /**< \brief (TC2) Channel Mode Register (channel = 1) */ + #define REG_TC2_SMMR1 (0x40014048U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC2_RAB1 (0x4001404CU) /**< \brief (TC2) Register AB (channel = 1) */ + #define REG_TC2_CV1 (0x40014050U) /**< \brief (TC2) Counter Value (channel = 1) */ + #define REG_TC2_RA1 (0x40014054U) /**< \brief (TC2) Register A (channel = 1) */ + #define REG_TC2_RB1 (0x40014058U) /**< \brief (TC2) Register B (channel = 1) */ + #define REG_TC2_RC1 (0x4001405CU) /**< \brief (TC2) Register C (channel = 1) */ + #define REG_TC2_SR1 (0x40014060U) /**< \brief (TC2) Status Register (channel = 1) */ + #define REG_TC2_IER1 (0x40014064U) /**< \brief (TC2) Interrupt Enable Register (channel = 1) */ + #define REG_TC2_IDR1 (0x40014068U) /**< \brief (TC2) Interrupt Disable Register (channel = 1) */ + #define REG_TC2_IMR1 (0x4001406CU) /**< \brief (TC2) Interrupt Mask Register (channel = 1) */ + #define REG_TC2_EMR1 (0x40014070U) /**< \brief (TC2) Extended Mode Register (channel = 1) */ + #define REG_TC2_CCR2 (0x40014080U) /**< \brief (TC2) Channel Control Register (channel = 2) */ + #define REG_TC2_CMR2 (0x40014084U) /**< \brief (TC2) Channel Mode Register (channel = 2) */ + #define REG_TC2_SMMR2 (0x40014088U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC2_RAB2 (0x4001408CU) /**< \brief (TC2) Register AB (channel = 2) */ + #define REG_TC2_CV2 (0x40014090U) /**< \brief (TC2) Counter Value (channel = 2) */ + #define REG_TC2_RA2 (0x40014094U) /**< \brief (TC2) Register A (channel = 2) */ + #define REG_TC2_RB2 (0x40014098U) /**< \brief (TC2) Register B (channel = 2) */ + #define REG_TC2_RC2 (0x4001409CU) /**< \brief (TC2) Register C (channel = 2) */ + #define REG_TC2_SR2 (0x400140A0U) /**< \brief (TC2) Status Register (channel = 2) */ + #define REG_TC2_IER2 (0x400140A4U) /**< \brief (TC2) Interrupt Enable Register (channel = 2) */ + #define REG_TC2_IDR2 (0x400140A8U) /**< \brief (TC2) Interrupt Disable Register (channel = 2) */ + #define REG_TC2_IMR2 (0x400140ACU) /**< \brief (TC2) Interrupt Mask Register (channel = 2) */ + #define REG_TC2_EMR2 (0x400140B0U) /**< \brief (TC2) Extended Mode Register (channel = 2) */ + #define REG_TC2_BCR (0x400140C0U) /**< \brief (TC2) Block Control Register */ + #define REG_TC2_BMR (0x400140C4U) /**< \brief (TC2) Block Mode Register */ + #define REG_TC2_QIER (0x400140C8U) /**< \brief (TC2) QDEC Interrupt Enable Register */ + #define REG_TC2_QIDR (0x400140CCU) /**< \brief (TC2) QDEC Interrupt Disable Register */ + #define REG_TC2_QIMR (0x400140D0U) /**< \brief (TC2) QDEC Interrupt Mask Register */ + #define REG_TC2_QISR (0x400140D4U) /**< \brief (TC2) QDEC Interrupt Status Register */ + #define REG_TC2_FMR (0x400140D8U) /**< \brief (TC2) Fault Mode Register */ + #define REG_TC2_WPMR (0x400140E4U) /**< \brief (TC2) Write Protection Mode Register */ + #define REG_TC2_VER (0x400140FCU) /**< \brief (TC2) Version Register */ +#else + #define REG_TC2_CCR0 (*(__O uint32_t*)0x40014000U) /**< \brief (TC2) Channel Control Register (channel = 0) */ + #define REG_TC2_CMR0 (*(__IO uint32_t*)0x40014004U) /**< \brief (TC2) Channel Mode Register (channel = 0) */ + #define REG_TC2_SMMR0 (*(__IO uint32_t*)0x40014008U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC2_RAB0 (*(__I uint32_t*)0x4001400CU) /**< \brief (TC2) Register AB (channel = 0) */ + #define REG_TC2_CV0 (*(__I uint32_t*)0x40014010U) /**< \brief (TC2) Counter Value (channel = 0) */ + #define REG_TC2_RA0 (*(__IO uint32_t*)0x40014014U) /**< \brief (TC2) Register A (channel = 0) */ + #define REG_TC2_RB0 (*(__IO uint32_t*)0x40014018U) /**< \brief (TC2) Register B (channel = 0) */ + #define REG_TC2_RC0 (*(__IO uint32_t*)0x4001401CU) /**< \brief (TC2) Register C (channel = 0) */ + #define REG_TC2_SR0 (*(__I uint32_t*)0x40014020U) /**< \brief (TC2) Status Register (channel = 0) */ + #define REG_TC2_IER0 (*(__O uint32_t*)0x40014024U) /**< \brief (TC2) Interrupt Enable Register (channel = 0) */ + #define REG_TC2_IDR0 (*(__O uint32_t*)0x40014028U) /**< \brief (TC2) Interrupt Disable Register (channel = 0) */ + #define REG_TC2_IMR0 (*(__I uint32_t*)0x4001402CU) /**< \brief (TC2) Interrupt Mask Register (channel = 0) */ + #define REG_TC2_EMR0 (*(__IO uint32_t*)0x40014030U) /**< \brief (TC2) Extended Mode Register (channel = 0) */ + #define REG_TC2_CCR1 (*(__O uint32_t*)0x40014040U) /**< \brief (TC2) Channel Control Register (channel = 1) */ + #define REG_TC2_CMR1 (*(__IO uint32_t*)0x40014044U) /**< \brief (TC2) Channel Mode Register (channel = 1) */ + #define REG_TC2_SMMR1 (*(__IO uint32_t*)0x40014048U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC2_RAB1 (*(__I uint32_t*)0x4001404CU) /**< \brief (TC2) Register AB (channel = 1) */ + #define REG_TC2_CV1 (*(__I uint32_t*)0x40014050U) /**< \brief (TC2) Counter Value (channel = 1) */ + #define REG_TC2_RA1 (*(__IO uint32_t*)0x40014054U) /**< \brief (TC2) Register A (channel = 1) */ + #define REG_TC2_RB1 (*(__IO uint32_t*)0x40014058U) /**< \brief (TC2) Register B (channel = 1) */ + #define REG_TC2_RC1 (*(__IO uint32_t*)0x4001405CU) /**< \brief (TC2) Register C (channel = 1) */ + #define REG_TC2_SR1 (*(__I uint32_t*)0x40014060U) /**< \brief (TC2) Status Register (channel = 1) */ + #define REG_TC2_IER1 (*(__O uint32_t*)0x40014064U) /**< \brief (TC2) Interrupt Enable Register (channel = 1) */ + #define REG_TC2_IDR1 (*(__O uint32_t*)0x40014068U) /**< \brief (TC2) Interrupt Disable Register (channel = 1) */ + #define REG_TC2_IMR1 (*(__I uint32_t*)0x4001406CU) /**< \brief (TC2) Interrupt Mask Register (channel = 1) */ + #define REG_TC2_EMR1 (*(__IO uint32_t*)0x40014070U) /**< \brief (TC2) Extended Mode Register (channel = 1) */ + #define REG_TC2_CCR2 (*(__O uint32_t*)0x40014080U) /**< \brief (TC2) Channel Control Register (channel = 2) */ + #define REG_TC2_CMR2 (*(__IO uint32_t*)0x40014084U) /**< \brief (TC2) Channel Mode Register (channel = 2) */ + #define REG_TC2_SMMR2 (*(__IO uint32_t*)0x40014088U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC2_RAB2 (*(__I uint32_t*)0x4001408CU) /**< \brief (TC2) Register AB (channel = 2) */ + #define REG_TC2_CV2 (*(__I uint32_t*)0x40014090U) /**< \brief (TC2) Counter Value (channel = 2) */ + #define REG_TC2_RA2 (*(__IO uint32_t*)0x40014094U) /**< \brief (TC2) Register A (channel = 2) */ + #define REG_TC2_RB2 (*(__IO uint32_t*)0x40014098U) /**< \brief (TC2) Register B (channel = 2) */ + #define REG_TC2_RC2 (*(__IO uint32_t*)0x4001409CU) /**< \brief (TC2) Register C (channel = 2) */ + #define REG_TC2_SR2 (*(__I uint32_t*)0x400140A0U) /**< \brief (TC2) Status Register (channel = 2) */ + #define REG_TC2_IER2 (*(__O uint32_t*)0x400140A4U) /**< \brief (TC2) Interrupt Enable Register (channel = 2) */ + #define REG_TC2_IDR2 (*(__O uint32_t*)0x400140A8U) /**< \brief (TC2) Interrupt Disable Register (channel = 2) */ + #define REG_TC2_IMR2 (*(__I uint32_t*)0x400140ACU) /**< \brief (TC2) Interrupt Mask Register (channel = 2) */ + #define REG_TC2_EMR2 (*(__IO uint32_t*)0x400140B0U) /**< \brief (TC2) Extended Mode Register (channel = 2) */ + #define REG_TC2_BCR (*(__O uint32_t*)0x400140C0U) /**< \brief (TC2) Block Control Register */ + #define REG_TC2_BMR (*(__IO uint32_t*)0x400140C4U) /**< \brief (TC2) Block Mode Register */ + #define REG_TC2_QIER (*(__O uint32_t*)0x400140C8U) /**< \brief (TC2) QDEC Interrupt Enable Register */ + #define REG_TC2_QIDR (*(__O uint32_t*)0x400140CCU) /**< \brief (TC2) QDEC Interrupt Disable Register */ + #define REG_TC2_QIMR (*(__I uint32_t*)0x400140D0U) /**< \brief (TC2) QDEC Interrupt Mask Register */ + #define REG_TC2_QISR (*(__I uint32_t*)0x400140D4U) /**< \brief (TC2) QDEC Interrupt Status Register */ + #define REG_TC2_FMR (*(__IO uint32_t*)0x400140D8U) /**< \brief (TC2) Fault Mode Register */ + #define REG_TC2_WPMR (*(__IO uint32_t*)0x400140E4U) /**< \brief (TC2) Write Protection Mode Register */ + #define REG_TC2_VER (*(__I uint32_t*)0x400140FCU) /**< \brief (TC2) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_TC2_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/tc3.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/tc3.h new file mode 100644 index 000000000..29351ce47 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/tc3.h @@ -0,0 +1,139 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_TC3_INSTANCE_ +#define _SAME70_TC3_INSTANCE_ + +/* ========== Register definition for TC3 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TC3_CCR0 (0x40054000U) /**< \brief (TC3) Channel Control Register (channel = 0) */ + #define REG_TC3_CMR0 (0x40054004U) /**< \brief (TC3) Channel Mode Register (channel = 0) */ + #define REG_TC3_SMMR0 (0x40054008U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC3_RAB0 (0x4005400CU) /**< \brief (TC3) Register AB (channel = 0) */ + #define REG_TC3_CV0 (0x40054010U) /**< \brief (TC3) Counter Value (channel = 0) */ + #define REG_TC3_RA0 (0x40054014U) /**< \brief (TC3) Register A (channel = 0) */ + #define REG_TC3_RB0 (0x40054018U) /**< \brief (TC3) Register B (channel = 0) */ + #define REG_TC3_RC0 (0x4005401CU) /**< \brief (TC3) Register C (channel = 0) */ + #define REG_TC3_SR0 (0x40054020U) /**< \brief (TC3) Status Register (channel = 0) */ + #define REG_TC3_IER0 (0x40054024U) /**< \brief (TC3) Interrupt Enable Register (channel = 0) */ + #define REG_TC3_IDR0 (0x40054028U) /**< \brief (TC3) Interrupt Disable Register (channel = 0) */ + #define REG_TC3_IMR0 (0x4005402CU) /**< \brief (TC3) Interrupt Mask Register (channel = 0) */ + #define REG_TC3_EMR0 (0x40054030U) /**< \brief (TC3) Extended Mode Register (channel = 0) */ + #define REG_TC3_CCR1 (0x40054040U) /**< \brief (TC3) Channel Control Register (channel = 1) */ + #define REG_TC3_CMR1 (0x40054044U) /**< \brief (TC3) Channel Mode Register (channel = 1) */ + #define REG_TC3_SMMR1 (0x40054048U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC3_RAB1 (0x4005404CU) /**< \brief (TC3) Register AB (channel = 1) */ + #define REG_TC3_CV1 (0x40054050U) /**< \brief (TC3) Counter Value (channel = 1) */ + #define REG_TC3_RA1 (0x40054054U) /**< \brief (TC3) Register A (channel = 1) */ + #define REG_TC3_RB1 (0x40054058U) /**< \brief (TC3) Register B (channel = 1) */ + #define REG_TC3_RC1 (0x4005405CU) /**< \brief (TC3) Register C (channel = 1) */ + #define REG_TC3_SR1 (0x40054060U) /**< \brief (TC3) Status Register (channel = 1) */ + #define REG_TC3_IER1 (0x40054064U) /**< \brief (TC3) Interrupt Enable Register (channel = 1) */ + #define REG_TC3_IDR1 (0x40054068U) /**< \brief (TC3) Interrupt Disable Register (channel = 1) */ + #define REG_TC3_IMR1 (0x4005406CU) /**< \brief (TC3) Interrupt Mask Register (channel = 1) */ + #define REG_TC3_EMR1 (0x40054070U) /**< \brief (TC3) Extended Mode Register (channel = 1) */ + #define REG_TC3_CCR2 (0x40054080U) /**< \brief (TC3) Channel Control Register (channel = 2) */ + #define REG_TC3_CMR2 (0x40054084U) /**< \brief (TC3) Channel Mode Register (channel = 2) */ + #define REG_TC3_SMMR2 (0x40054088U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC3_RAB2 (0x4005408CU) /**< \brief (TC3) Register AB (channel = 2) */ + #define REG_TC3_CV2 (0x40054090U) /**< \brief (TC3) Counter Value (channel = 2) */ + #define REG_TC3_RA2 (0x40054094U) /**< \brief (TC3) Register A (channel = 2) */ + #define REG_TC3_RB2 (0x40054098U) /**< \brief (TC3) Register B (channel = 2) */ + #define REG_TC3_RC2 (0x4005409CU) /**< \brief (TC3) Register C (channel = 2) */ + #define REG_TC3_SR2 (0x400540A0U) /**< \brief (TC3) Status Register (channel = 2) */ + #define REG_TC3_IER2 (0x400540A4U) /**< \brief (TC3) Interrupt Enable Register (channel = 2) */ + #define REG_TC3_IDR2 (0x400540A8U) /**< \brief (TC3) Interrupt Disable Register (channel = 2) */ + #define REG_TC3_IMR2 (0x400540ACU) /**< \brief (TC3) Interrupt Mask Register (channel = 2) */ + #define REG_TC3_EMR2 (0x400540B0U) /**< \brief (TC3) Extended Mode Register (channel = 2) */ + #define REG_TC3_BCR (0x400540C0U) /**< \brief (TC3) Block Control Register */ + #define REG_TC3_BMR (0x400540C4U) /**< \brief (TC3) Block Mode Register */ + #define REG_TC3_QIER (0x400540C8U) /**< \brief (TC3) QDEC Interrupt Enable Register */ + #define REG_TC3_QIDR (0x400540CCU) /**< \brief (TC3) QDEC Interrupt Disable Register */ + #define REG_TC3_QIMR (0x400540D0U) /**< \brief (TC3) QDEC Interrupt Mask Register */ + #define REG_TC3_QISR (0x400540D4U) /**< \brief (TC3) QDEC Interrupt Status Register */ + #define REG_TC3_FMR (0x400540D8U) /**< \brief (TC3) Fault Mode Register */ + #define REG_TC3_WPMR (0x400540E4U) /**< \brief (TC3) Write Protection Mode Register */ + #define REG_TC3_VER (0x400540FCU) /**< \brief (TC3) Version Register */ +#else + #define REG_TC3_CCR0 (*(__O uint32_t*)0x40054000U) /**< \brief (TC3) Channel Control Register (channel = 0) */ + #define REG_TC3_CMR0 (*(__IO uint32_t*)0x40054004U) /**< \brief (TC3) Channel Mode Register (channel = 0) */ + #define REG_TC3_SMMR0 (*(__IO uint32_t*)0x40054008U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC3_RAB0 (*(__I uint32_t*)0x4005400CU) /**< \brief (TC3) Register AB (channel = 0) */ + #define REG_TC3_CV0 (*(__I uint32_t*)0x40054010U) /**< \brief (TC3) Counter Value (channel = 0) */ + #define REG_TC3_RA0 (*(__IO uint32_t*)0x40054014U) /**< \brief (TC3) Register A (channel = 0) */ + #define REG_TC3_RB0 (*(__IO uint32_t*)0x40054018U) /**< \brief (TC3) Register B (channel = 0) */ + #define REG_TC3_RC0 (*(__IO uint32_t*)0x4005401CU) /**< \brief (TC3) Register C (channel = 0) */ + #define REG_TC3_SR0 (*(__I uint32_t*)0x40054020U) /**< \brief (TC3) Status Register (channel = 0) */ + #define REG_TC3_IER0 (*(__O uint32_t*)0x40054024U) /**< \brief (TC3) Interrupt Enable Register (channel = 0) */ + #define REG_TC3_IDR0 (*(__O uint32_t*)0x40054028U) /**< \brief (TC3) Interrupt Disable Register (channel = 0) */ + #define REG_TC3_IMR0 (*(__I uint32_t*)0x4005402CU) /**< \brief (TC3) Interrupt Mask Register (channel = 0) */ + #define REG_TC3_EMR0 (*(__IO uint32_t*)0x40054030U) /**< \brief (TC3) Extended Mode Register (channel = 0) */ + #define REG_TC3_CCR1 (*(__O uint32_t*)0x40054040U) /**< \brief (TC3) Channel Control Register (channel = 1) */ + #define REG_TC3_CMR1 (*(__IO uint32_t*)0x40054044U) /**< \brief (TC3) Channel Mode Register (channel = 1) */ + #define REG_TC3_SMMR1 (*(__IO uint32_t*)0x40054048U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC3_RAB1 (*(__I uint32_t*)0x4005404CU) /**< \brief (TC3) Register AB (channel = 1) */ + #define REG_TC3_CV1 (*(__I uint32_t*)0x40054050U) /**< \brief (TC3) Counter Value (channel = 1) */ + #define REG_TC3_RA1 (*(__IO uint32_t*)0x40054054U) /**< \brief (TC3) Register A (channel = 1) */ + #define REG_TC3_RB1 (*(__IO uint32_t*)0x40054058U) /**< \brief (TC3) Register B (channel = 1) */ + #define REG_TC3_RC1 (*(__IO uint32_t*)0x4005405CU) /**< \brief (TC3) Register C (channel = 1) */ + #define REG_TC3_SR1 (*(__I uint32_t*)0x40054060U) /**< \brief (TC3) Status Register (channel = 1) */ + #define REG_TC3_IER1 (*(__O uint32_t*)0x40054064U) /**< \brief (TC3) Interrupt Enable Register (channel = 1) */ + #define REG_TC3_IDR1 (*(__O uint32_t*)0x40054068U) /**< \brief (TC3) Interrupt Disable Register (channel = 1) */ + #define REG_TC3_IMR1 (*(__I uint32_t*)0x4005406CU) /**< \brief (TC3) Interrupt Mask Register (channel = 1) */ + #define REG_TC3_EMR1 (*(__IO uint32_t*)0x40054070U) /**< \brief (TC3) Extended Mode Register (channel = 1) */ + #define REG_TC3_CCR2 (*(__O uint32_t*)0x40054080U) /**< \brief (TC3) Channel Control Register (channel = 2) */ + #define REG_TC3_CMR2 (*(__IO uint32_t*)0x40054084U) /**< \brief (TC3) Channel Mode Register (channel = 2) */ + #define REG_TC3_SMMR2 (*(__IO uint32_t*)0x40054088U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC3_RAB2 (*(__I uint32_t*)0x4005408CU) /**< \brief (TC3) Register AB (channel = 2) */ + #define REG_TC3_CV2 (*(__I uint32_t*)0x40054090U) /**< \brief (TC3) Counter Value (channel = 2) */ + #define REG_TC3_RA2 (*(__IO uint32_t*)0x40054094U) /**< \brief (TC3) Register A (channel = 2) */ + #define REG_TC3_RB2 (*(__IO uint32_t*)0x40054098U) /**< \brief (TC3) Register B (channel = 2) */ + #define REG_TC3_RC2 (*(__IO uint32_t*)0x4005409CU) /**< \brief (TC3) Register C (channel = 2) */ + #define REG_TC3_SR2 (*(__I uint32_t*)0x400540A0U) /**< \brief (TC3) Status Register (channel = 2) */ + #define REG_TC3_IER2 (*(__O uint32_t*)0x400540A4U) /**< \brief (TC3) Interrupt Enable Register (channel = 2) */ + #define REG_TC3_IDR2 (*(__O uint32_t*)0x400540A8U) /**< \brief (TC3) Interrupt Disable Register (channel = 2) */ + #define REG_TC3_IMR2 (*(__I uint32_t*)0x400540ACU) /**< \brief (TC3) Interrupt Mask Register (channel = 2) */ + #define REG_TC3_EMR2 (*(__IO uint32_t*)0x400540B0U) /**< \brief (TC3) Extended Mode Register (channel = 2) */ + #define REG_TC3_BCR (*(__O uint32_t*)0x400540C0U) /**< \brief (TC3) Block Control Register */ + #define REG_TC3_BMR (*(__IO uint32_t*)0x400540C4U) /**< \brief (TC3) Block Mode Register */ + #define REG_TC3_QIER (*(__O uint32_t*)0x400540C8U) /**< \brief (TC3) QDEC Interrupt Enable Register */ + #define REG_TC3_QIDR (*(__O uint32_t*)0x400540CCU) /**< \brief (TC3) QDEC Interrupt Disable Register */ + #define REG_TC3_QIMR (*(__I uint32_t*)0x400540D0U) /**< \brief (TC3) QDEC Interrupt Mask Register */ + #define REG_TC3_QISR (*(__I uint32_t*)0x400540D4U) /**< \brief (TC3) QDEC Interrupt Status Register */ + #define REG_TC3_FMR (*(__IO uint32_t*)0x400540D8U) /**< \brief (TC3) Fault Mode Register */ + #define REG_TC3_WPMR (*(__IO uint32_t*)0x400540E4U) /**< \brief (TC3) Write Protection Mode Register */ + #define REG_TC3_VER (*(__I uint32_t*)0x400540FCU) /**< \brief (TC3) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_TC3_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/trng.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/trng.h new file mode 100644 index 000000000..e0f1b062a --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/trng.h @@ -0,0 +1,57 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_TRNG_INSTANCE_ +#define _SAME70_TRNG_INSTANCE_ + +/* ========== Register definition for TRNG peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TRNG_CR (0x40070000U) /**< \brief (TRNG) Control Register */ + #define REG_TRNG_IER (0x40070010U) /**< \brief (TRNG) Interrupt Enable Register */ + #define REG_TRNG_IDR (0x40070014U) /**< \brief (TRNG) Interrupt Disable Register */ + #define REG_TRNG_IMR (0x40070018U) /**< \brief (TRNG) Interrupt Mask Register */ + #define REG_TRNG_ISR (0x4007001CU) /**< \brief (TRNG) Interrupt Status Register */ + #define REG_TRNG_ODATA (0x40070050U) /**< \brief (TRNG) Output Data Register */ + #define REG_TRNG_VERSION (0x400700FCU) /**< \brief (TRNG) Version Register */ +#else + #define REG_TRNG_CR (*(__O uint32_t*)0x40070000U) /**< \brief (TRNG) Control Register */ + #define REG_TRNG_IER (*(__O uint32_t*)0x40070010U) /**< \brief (TRNG) Interrupt Enable Register */ + #define REG_TRNG_IDR (*(__O uint32_t*)0x40070014U) /**< \brief (TRNG) Interrupt Disable Register */ + #define REG_TRNG_IMR (*(__I uint32_t*)0x40070018U) /**< \brief (TRNG) Interrupt Mask Register */ + #define REG_TRNG_ISR (*(__I uint32_t*)0x4007001CU) /**< \brief (TRNG) Interrupt Status Register */ + #define REG_TRNG_ODATA (*(__I uint32_t*)0x40070050U) /**< \brief (TRNG) Output Data Register */ + #define REG_TRNG_VERSION (*(__I uint32_t*)0x400700FCU) /**< \brief (TRNG) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_TRNG_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/twihs0.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/twihs0.h new file mode 100644 index 000000000..35504a31c --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/twihs0.h @@ -0,0 +1,79 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_TWIHS0_INSTANCE_ +#define _SAME70_TWIHS0_INSTANCE_ + +/* ========== Register definition for TWIHS0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TWIHS0_CR (0x40018000U) /**< \brief (TWIHS0) Control Register */ + #define REG_TWIHS0_MMR (0x40018004U) /**< \brief (TWIHS0) Master Mode Register */ + #define REG_TWIHS0_SMR (0x40018008U) /**< \brief (TWIHS0) Slave Mode Register */ + #define REG_TWIHS0_IADR (0x4001800CU) /**< \brief (TWIHS0) Internal Address Register */ + #define REG_TWIHS0_CWGR (0x40018010U) /**< \brief (TWIHS0) Clock Waveform Generator Register */ + #define REG_TWIHS0_SR (0x40018020U) /**< \brief (TWIHS0) Status Register */ + #define REG_TWIHS0_IER (0x40018024U) /**< \brief (TWIHS0) Interrupt Enable Register */ + #define REG_TWIHS0_IDR (0x40018028U) /**< \brief (TWIHS0) Interrupt Disable Register */ + #define REG_TWIHS0_IMR (0x4001802CU) /**< \brief (TWIHS0) Interrupt Mask Register */ + #define REG_TWIHS0_RHR (0x40018030U) /**< \brief (TWIHS0) Receive Holding Register */ + #define REG_TWIHS0_THR (0x40018034U) /**< \brief (TWIHS0) Transmit Holding Register */ + #define REG_TWIHS0_SMBTR (0x40018038U) /**< \brief (TWIHS0) SMBus Timing Register */ + #define REG_TWIHS0_FILTR (0x40018044U) /**< \brief (TWIHS0) Filter Register */ + #define REG_TWIHS0_SWMR (0x4001804CU) /**< \brief (TWIHS0) SleepWalking Matching Register */ + #define REG_TWIHS0_DR (0x400180D0U) /**< \brief (TWIHS0) Debug Register */ + #define REG_TWIHS0_WPMR (0x400180E4U) /**< \brief (TWIHS0) Write Protection Mode Register */ + #define REG_TWIHS0_WPSR (0x400180E8U) /**< \brief (TWIHS0) Write Protection Status Register */ + #define REG_TWIHS0_VER (0x400180FCU) /**< \brief (TWIHS0) Version Register */ +#else + #define REG_TWIHS0_CR (*(__O uint32_t*)0x40018000U) /**< \brief (TWIHS0) Control Register */ + #define REG_TWIHS0_MMR (*(__IO uint32_t*)0x40018004U) /**< \brief (TWIHS0) Master Mode Register */ + #define REG_TWIHS0_SMR (*(__IO uint32_t*)0x40018008U) /**< \brief (TWIHS0) Slave Mode Register */ + #define REG_TWIHS0_IADR (*(__IO uint32_t*)0x4001800CU) /**< \brief (TWIHS0) Internal Address Register */ + #define REG_TWIHS0_CWGR (*(__IO uint32_t*)0x40018010U) /**< \brief (TWIHS0) Clock Waveform Generator Register */ + #define REG_TWIHS0_SR (*(__I uint32_t*)0x40018020U) /**< \brief (TWIHS0) Status Register */ + #define REG_TWIHS0_IER (*(__O uint32_t*)0x40018024U) /**< \brief (TWIHS0) Interrupt Enable Register */ + #define REG_TWIHS0_IDR (*(__O uint32_t*)0x40018028U) /**< \brief (TWIHS0) Interrupt Disable Register */ + #define REG_TWIHS0_IMR (*(__I uint32_t*)0x4001802CU) /**< \brief (TWIHS0) Interrupt Mask Register */ + #define REG_TWIHS0_RHR (*(__I uint32_t*)0x40018030U) /**< \brief (TWIHS0) Receive Holding Register */ + #define REG_TWIHS0_THR (*(__O uint32_t*)0x40018034U) /**< \brief (TWIHS0) Transmit Holding Register */ + #define REG_TWIHS0_SMBTR (*(__IO uint32_t*)0x40018038U) /**< \brief (TWIHS0) SMBus Timing Register */ + #define REG_TWIHS0_FILTR (*(__IO uint32_t*)0x40018044U) /**< \brief (TWIHS0) Filter Register */ + #define REG_TWIHS0_SWMR (*(__IO uint32_t*)0x4001804CU) /**< \brief (TWIHS0) SleepWalking Matching Register */ + #define REG_TWIHS0_DR (*(__I uint32_t*)0x400180D0U) /**< \brief (TWIHS0) Debug Register */ + #define REG_TWIHS0_WPMR (*(__IO uint32_t*)0x400180E4U) /**< \brief (TWIHS0) Write Protection Mode Register */ + #define REG_TWIHS0_WPSR (*(__I uint32_t*)0x400180E8U) /**< \brief (TWIHS0) Write Protection Status Register */ + #define REG_TWIHS0_VER (*(__I uint32_t*)0x400180FCU) /**< \brief (TWIHS0) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_TWIHS0_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/twihs1.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/twihs1.h new file mode 100644 index 000000000..f76e761a0 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/twihs1.h @@ -0,0 +1,79 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_TWIHS1_INSTANCE_ +#define _SAME70_TWIHS1_INSTANCE_ + +/* ========== Register definition for TWIHS1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TWIHS1_CR (0x4001C000U) /**< \brief (TWIHS1) Control Register */ + #define REG_TWIHS1_MMR (0x4001C004U) /**< \brief (TWIHS1) Master Mode Register */ + #define REG_TWIHS1_SMR (0x4001C008U) /**< \brief (TWIHS1) Slave Mode Register */ + #define REG_TWIHS1_IADR (0x4001C00CU) /**< \brief (TWIHS1) Internal Address Register */ + #define REG_TWIHS1_CWGR (0x4001C010U) /**< \brief (TWIHS1) Clock Waveform Generator Register */ + #define REG_TWIHS1_SR (0x4001C020U) /**< \brief (TWIHS1) Status Register */ + #define REG_TWIHS1_IER (0x4001C024U) /**< \brief (TWIHS1) Interrupt Enable Register */ + #define REG_TWIHS1_IDR (0x4001C028U) /**< \brief (TWIHS1) Interrupt Disable Register */ + #define REG_TWIHS1_IMR (0x4001C02CU) /**< \brief (TWIHS1) Interrupt Mask Register */ + #define REG_TWIHS1_RHR (0x4001C030U) /**< \brief (TWIHS1) Receive Holding Register */ + #define REG_TWIHS1_THR (0x4001C034U) /**< \brief (TWIHS1) Transmit Holding Register */ + #define REG_TWIHS1_SMBTR (0x4001C038U) /**< \brief (TWIHS1) SMBus Timing Register */ + #define REG_TWIHS1_FILTR (0x4001C044U) /**< \brief (TWIHS1) Filter Register */ + #define REG_TWIHS1_SWMR (0x4001C04CU) /**< \brief (TWIHS1) SleepWalking Matching Register */ + #define REG_TWIHS1_DR (0x4001C0D0U) /**< \brief (TWIHS1) Debug Register */ + #define REG_TWIHS1_WPMR (0x4001C0E4U) /**< \brief (TWIHS1) Write Protection Mode Register */ + #define REG_TWIHS1_WPSR (0x4001C0E8U) /**< \brief (TWIHS1) Write Protection Status Register */ + #define REG_TWIHS1_VER (0x4001C0FCU) /**< \brief (TWIHS1) Version Register */ +#else + #define REG_TWIHS1_CR (*(__O uint32_t*)0x4001C000U) /**< \brief (TWIHS1) Control Register */ + #define REG_TWIHS1_MMR (*(__IO uint32_t*)0x4001C004U) /**< \brief (TWIHS1) Master Mode Register */ + #define REG_TWIHS1_SMR (*(__IO uint32_t*)0x4001C008U) /**< \brief (TWIHS1) Slave Mode Register */ + #define REG_TWIHS1_IADR (*(__IO uint32_t*)0x4001C00CU) /**< \brief (TWIHS1) Internal Address Register */ + #define REG_TWIHS1_CWGR (*(__IO uint32_t*)0x4001C010U) /**< \brief (TWIHS1) Clock Waveform Generator Register */ + #define REG_TWIHS1_SR (*(__I uint32_t*)0x4001C020U) /**< \brief (TWIHS1) Status Register */ + #define REG_TWIHS1_IER (*(__O uint32_t*)0x4001C024U) /**< \brief (TWIHS1) Interrupt Enable Register */ + #define REG_TWIHS1_IDR (*(__O uint32_t*)0x4001C028U) /**< \brief (TWIHS1) Interrupt Disable Register */ + #define REG_TWIHS1_IMR (*(__I uint32_t*)0x4001C02CU) /**< \brief (TWIHS1) Interrupt Mask Register */ + #define REG_TWIHS1_RHR (*(__I uint32_t*)0x4001C030U) /**< \brief (TWIHS1) Receive Holding Register */ + #define REG_TWIHS1_THR (*(__O uint32_t*)0x4001C034U) /**< \brief (TWIHS1) Transmit Holding Register */ + #define REG_TWIHS1_SMBTR (*(__IO uint32_t*)0x4001C038U) /**< \brief (TWIHS1) SMBus Timing Register */ + #define REG_TWIHS1_FILTR (*(__IO uint32_t*)0x4001C044U) /**< \brief (TWIHS1) Filter Register */ + #define REG_TWIHS1_SWMR (*(__IO uint32_t*)0x4001C04CU) /**< \brief (TWIHS1) SleepWalking Matching Register */ + #define REG_TWIHS1_DR (*(__I uint32_t*)0x4001C0D0U) /**< \brief (TWIHS1) Debug Register */ + #define REG_TWIHS1_WPMR (*(__IO uint32_t*)0x4001C0E4U) /**< \brief (TWIHS1) Write Protection Mode Register */ + #define REG_TWIHS1_WPSR (*(__I uint32_t*)0x4001C0E8U) /**< \brief (TWIHS1) Write Protection Status Register */ + #define REG_TWIHS1_VER (*(__I uint32_t*)0x4001C0FCU) /**< \brief (TWIHS1) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_TWIHS1_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/twihs2.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/twihs2.h new file mode 100644 index 000000000..bedb4b912 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/twihs2.h @@ -0,0 +1,79 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_TWIHS2_INSTANCE_ +#define _SAME70_TWIHS2_INSTANCE_ + +/* ========== Register definition for TWIHS2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TWIHS2_CR (0x40060000U) /**< \brief (TWIHS2) Control Register */ + #define REG_TWIHS2_MMR (0x40060004U) /**< \brief (TWIHS2) Master Mode Register */ + #define REG_TWIHS2_SMR (0x40060008U) /**< \brief (TWIHS2) Slave Mode Register */ + #define REG_TWIHS2_IADR (0x4006000CU) /**< \brief (TWIHS2) Internal Address Register */ + #define REG_TWIHS2_CWGR (0x40060010U) /**< \brief (TWIHS2) Clock Waveform Generator Register */ + #define REG_TWIHS2_SR (0x40060020U) /**< \brief (TWIHS2) Status Register */ + #define REG_TWIHS2_IER (0x40060024U) /**< \brief (TWIHS2) Interrupt Enable Register */ + #define REG_TWIHS2_IDR (0x40060028U) /**< \brief (TWIHS2) Interrupt Disable Register */ + #define REG_TWIHS2_IMR (0x4006002CU) /**< \brief (TWIHS2) Interrupt Mask Register */ + #define REG_TWIHS2_RHR (0x40060030U) /**< \brief (TWIHS2) Receive Holding Register */ + #define REG_TWIHS2_THR (0x40060034U) /**< \brief (TWIHS2) Transmit Holding Register */ + #define REG_TWIHS2_SMBTR (0x40060038U) /**< \brief (TWIHS2) SMBus Timing Register */ + #define REG_TWIHS2_FILTR (0x40060044U) /**< \brief (TWIHS2) Filter Register */ + #define REG_TWIHS2_SWMR (0x4006004CU) /**< \brief (TWIHS2) SleepWalking Matching Register */ + #define REG_TWIHS2_DR (0x400600D0U) /**< \brief (TWIHS2) Debug Register */ + #define REG_TWIHS2_WPMR (0x400600E4U) /**< \brief (TWIHS2) Write Protection Mode Register */ + #define REG_TWIHS2_WPSR (0x400600E8U) /**< \brief (TWIHS2) Write Protection Status Register */ + #define REG_TWIHS2_VER (0x400600FCU) /**< \brief (TWIHS2) Version Register */ +#else + #define REG_TWIHS2_CR (*(__O uint32_t*)0x40060000U) /**< \brief (TWIHS2) Control Register */ + #define REG_TWIHS2_MMR (*(__IO uint32_t*)0x40060004U) /**< \brief (TWIHS2) Master Mode Register */ + #define REG_TWIHS2_SMR (*(__IO uint32_t*)0x40060008U) /**< \brief (TWIHS2) Slave Mode Register */ + #define REG_TWIHS2_IADR (*(__IO uint32_t*)0x4006000CU) /**< \brief (TWIHS2) Internal Address Register */ + #define REG_TWIHS2_CWGR (*(__IO uint32_t*)0x40060010U) /**< \brief (TWIHS2) Clock Waveform Generator Register */ + #define REG_TWIHS2_SR (*(__I uint32_t*)0x40060020U) /**< \brief (TWIHS2) Status Register */ + #define REG_TWIHS2_IER (*(__O uint32_t*)0x40060024U) /**< \brief (TWIHS2) Interrupt Enable Register */ + #define REG_TWIHS2_IDR (*(__O uint32_t*)0x40060028U) /**< \brief (TWIHS2) Interrupt Disable Register */ + #define REG_TWIHS2_IMR (*(__I uint32_t*)0x4006002CU) /**< \brief (TWIHS2) Interrupt Mask Register */ + #define REG_TWIHS2_RHR (*(__I uint32_t*)0x40060030U) /**< \brief (TWIHS2) Receive Holding Register */ + #define REG_TWIHS2_THR (*(__O uint32_t*)0x40060034U) /**< \brief (TWIHS2) Transmit Holding Register */ + #define REG_TWIHS2_SMBTR (*(__IO uint32_t*)0x40060038U) /**< \brief (TWIHS2) SMBus Timing Register */ + #define REG_TWIHS2_FILTR (*(__IO uint32_t*)0x40060044U) /**< \brief (TWIHS2) Filter Register */ + #define REG_TWIHS2_SWMR (*(__IO uint32_t*)0x4006004CU) /**< \brief (TWIHS2) SleepWalking Matching Register */ + #define REG_TWIHS2_DR (*(__I uint32_t*)0x400600D0U) /**< \brief (TWIHS2) Debug Register */ + #define REG_TWIHS2_WPMR (*(__IO uint32_t*)0x400600E4U) /**< \brief (TWIHS2) Write Protection Mode Register */ + #define REG_TWIHS2_WPSR (*(__I uint32_t*)0x400600E8U) /**< \brief (TWIHS2) Write Protection Status Register */ + #define REG_TWIHS2_VER (*(__I uint32_t*)0x400600FCU) /**< \brief (TWIHS2) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_TWIHS2_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/uart0.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/uart0.h new file mode 100644 index 000000000..e3f2d2ad8 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/uart0.h @@ -0,0 +1,67 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_UART0_INSTANCE_ +#define _SAME70_UART0_INSTANCE_ + +/* ========== Register definition for UART0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_UART0_CR (0x400E0800U) /**< \brief (UART0) Control Register */ + #define REG_UART0_MR (0x400E0804U) /**< \brief (UART0) Mode Register */ + #define REG_UART0_IER (0x400E0808U) /**< \brief (UART0) Interrupt Enable Register */ + #define REG_UART0_IDR (0x400E080CU) /**< \brief (UART0) Interrupt Disable Register */ + #define REG_UART0_IMR (0x400E0810U) /**< \brief (UART0) Interrupt Mask Register */ + #define REG_UART0_SR (0x400E0814U) /**< \brief (UART0) Status Register */ + #define REG_UART0_RHR (0x400E0818U) /**< \brief (UART0) Receive Holding Register */ + #define REG_UART0_THR (0x400E081CU) /**< \brief (UART0) Transmit Holding Register */ + #define REG_UART0_BRGR (0x400E0820U) /**< \brief (UART0) Baud Rate Generator Register */ + #define REG_UART0_CMPR (0x400E0824U) /**< \brief (UART0) Comparison Register */ + #define REG_UART0_WPMR (0x400E08E4U) /**< \brief (UART0) Write Protection Mode Register */ + #define REG_UART0_VERSION (0x400E08FCU) /**< \brief (UART0) Version Register */ +#else + #define REG_UART0_CR (*(__O uint32_t*)0x400E0800U) /**< \brief (UART0) Control Register */ + #define REG_UART0_MR (*(__IO uint32_t*)0x400E0804U) /**< \brief (UART0) Mode Register */ + #define REG_UART0_IER (*(__O uint32_t*)0x400E0808U) /**< \brief (UART0) Interrupt Enable Register */ + #define REG_UART0_IDR (*(__O uint32_t*)0x400E080CU) /**< \brief (UART0) Interrupt Disable Register */ + #define REG_UART0_IMR (*(__I uint32_t*)0x400E0810U) /**< \brief (UART0) Interrupt Mask Register */ + #define REG_UART0_SR (*(__I uint32_t*)0x400E0814U) /**< \brief (UART0) Status Register */ + #define REG_UART0_RHR (*(__I uint32_t*)0x400E0818U) /**< \brief (UART0) Receive Holding Register */ + #define REG_UART0_THR (*(__O uint32_t*)0x400E081CU) /**< \brief (UART0) Transmit Holding Register */ + #define REG_UART0_BRGR (*(__IO uint32_t*)0x400E0820U) /**< \brief (UART0) Baud Rate Generator Register */ + #define REG_UART0_CMPR (*(__IO uint32_t*)0x400E0824U) /**< \brief (UART0) Comparison Register */ + #define REG_UART0_WPMR (*(__IO uint32_t*)0x400E08E4U) /**< \brief (UART0) Write Protection Mode Register */ + #define REG_UART0_VERSION (*(__I uint32_t*)0x400E08FCU) /**< \brief (UART0) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_UART0_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/uart1.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/uart1.h new file mode 100644 index 000000000..b1c2be7c1 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/uart1.h @@ -0,0 +1,67 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_UART1_INSTANCE_ +#define _SAME70_UART1_INSTANCE_ + +/* ========== Register definition for UART1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_UART1_CR (0x400E0A00U) /**< \brief (UART1) Control Register */ + #define REG_UART1_MR (0x400E0A04U) /**< \brief (UART1) Mode Register */ + #define REG_UART1_IER (0x400E0A08U) /**< \brief (UART1) Interrupt Enable Register */ + #define REG_UART1_IDR (0x400E0A0CU) /**< \brief (UART1) Interrupt Disable Register */ + #define REG_UART1_IMR (0x400E0A10U) /**< \brief (UART1) Interrupt Mask Register */ + #define REG_UART1_SR (0x400E0A14U) /**< \brief (UART1) Status Register */ + #define REG_UART1_RHR (0x400E0A18U) /**< \brief (UART1) Receive Holding Register */ + #define REG_UART1_THR (0x400E0A1CU) /**< \brief (UART1) Transmit Holding Register */ + #define REG_UART1_BRGR (0x400E0A20U) /**< \brief (UART1) Baud Rate Generator Register */ + #define REG_UART1_CMPR (0x400E0A24U) /**< \brief (UART1) Comparison Register */ + #define REG_UART1_WPMR (0x400E0AE4U) /**< \brief (UART1) Write Protection Mode Register */ + #define REG_UART1_VERSION (0x400E0AFCU) /**< \brief (UART1) Version Register */ +#else + #define REG_UART1_CR (*(__O uint32_t*)0x400E0A00U) /**< \brief (UART1) Control Register */ + #define REG_UART1_MR (*(__IO uint32_t*)0x400E0A04U) /**< \brief (UART1) Mode Register */ + #define REG_UART1_IER (*(__O uint32_t*)0x400E0A08U) /**< \brief (UART1) Interrupt Enable Register */ + #define REG_UART1_IDR (*(__O uint32_t*)0x400E0A0CU) /**< \brief (UART1) Interrupt Disable Register */ + #define REG_UART1_IMR (*(__I uint32_t*)0x400E0A10U) /**< \brief (UART1) Interrupt Mask Register */ + #define REG_UART1_SR (*(__I uint32_t*)0x400E0A14U) /**< \brief (UART1) Status Register */ + #define REG_UART1_RHR (*(__I uint32_t*)0x400E0A18U) /**< \brief (UART1) Receive Holding Register */ + #define REG_UART1_THR (*(__O uint32_t*)0x400E0A1CU) /**< \brief (UART1) Transmit Holding Register */ + #define REG_UART1_BRGR (*(__IO uint32_t*)0x400E0A20U) /**< \brief (UART1) Baud Rate Generator Register */ + #define REG_UART1_CMPR (*(__IO uint32_t*)0x400E0A24U) /**< \brief (UART1) Comparison Register */ + #define REG_UART1_WPMR (*(__IO uint32_t*)0x400E0AE4U) /**< \brief (UART1) Write Protection Mode Register */ + #define REG_UART1_VERSION (*(__I uint32_t*)0x400E0AFCU) /**< \brief (UART1) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_UART1_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/uart2.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/uart2.h new file mode 100644 index 000000000..70fefd058 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/uart2.h @@ -0,0 +1,67 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_UART2_INSTANCE_ +#define _SAME70_UART2_INSTANCE_ + +/* ========== Register definition for UART2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_UART2_CR (0x400E1A00U) /**< \brief (UART2) Control Register */ + #define REG_UART2_MR (0x400E1A04U) /**< \brief (UART2) Mode Register */ + #define REG_UART2_IER (0x400E1A08U) /**< \brief (UART2) Interrupt Enable Register */ + #define REG_UART2_IDR (0x400E1A0CU) /**< \brief (UART2) Interrupt Disable Register */ + #define REG_UART2_IMR (0x400E1A10U) /**< \brief (UART2) Interrupt Mask Register */ + #define REG_UART2_SR (0x400E1A14U) /**< \brief (UART2) Status Register */ + #define REG_UART2_RHR (0x400E1A18U) /**< \brief (UART2) Receive Holding Register */ + #define REG_UART2_THR (0x400E1A1CU) /**< \brief (UART2) Transmit Holding Register */ + #define REG_UART2_BRGR (0x400E1A20U) /**< \brief (UART2) Baud Rate Generator Register */ + #define REG_UART2_CMPR (0x400E1A24U) /**< \brief (UART2) Comparison Register */ + #define REG_UART2_WPMR (0x400E1AE4U) /**< \brief (UART2) Write Protection Mode Register */ + #define REG_UART2_VERSION (0x400E1AFCU) /**< \brief (UART2) Version Register */ +#else + #define REG_UART2_CR (*(__O uint32_t*)0x400E1A00U) /**< \brief (UART2) Control Register */ + #define REG_UART2_MR (*(__IO uint32_t*)0x400E1A04U) /**< \brief (UART2) Mode Register */ + #define REG_UART2_IER (*(__O uint32_t*)0x400E1A08U) /**< \brief (UART2) Interrupt Enable Register */ + #define REG_UART2_IDR (*(__O uint32_t*)0x400E1A0CU) /**< \brief (UART2) Interrupt Disable Register */ + #define REG_UART2_IMR (*(__I uint32_t*)0x400E1A10U) /**< \brief (UART2) Interrupt Mask Register */ + #define REG_UART2_SR (*(__I uint32_t*)0x400E1A14U) /**< \brief (UART2) Status Register */ + #define REG_UART2_RHR (*(__I uint32_t*)0x400E1A18U) /**< \brief (UART2) Receive Holding Register */ + #define REG_UART2_THR (*(__O uint32_t*)0x400E1A1CU) /**< \brief (UART2) Transmit Holding Register */ + #define REG_UART2_BRGR (*(__IO uint32_t*)0x400E1A20U) /**< \brief (UART2) Baud Rate Generator Register */ + #define REG_UART2_CMPR (*(__IO uint32_t*)0x400E1A24U) /**< \brief (UART2) Comparison Register */ + #define REG_UART2_WPMR (*(__IO uint32_t*)0x400E1AE4U) /**< \brief (UART2) Write Protection Mode Register */ + #define REG_UART2_VERSION (*(__I uint32_t*)0x400E1AFCU) /**< \brief (UART2) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_UART2_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/uart3.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/uart3.h new file mode 100644 index 000000000..1f932b141 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/uart3.h @@ -0,0 +1,66 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef _SAME70_UART3_INSTANCE_ +#define _SAME70_UART3_INSTANCE_ + +/* ========== Register definition for UART3 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_UART3_CR (0x400E1C00U) /**< \brief (UART3) Control Register */ + #define REG_UART3_MR (0x400E1C04U) /**< \brief (UART3) Mode Register */ + #define REG_UART3_IER (0x400E1C08U) /**< \brief (UART3) Interrupt Enable Register */ + #define REG_UART3_IDR (0x400E1C0CU) /**< \brief (UART3) Interrupt Disable Register */ + #define REG_UART3_IMR (0x400E1C10U) /**< \brief (UART3) Interrupt Mask Register */ + #define REG_UART3_SR (0x400E1C14U) /**< \brief (UART3) Status Register */ + #define REG_UART3_RHR (0x400E1C18U) /**< \brief (UART3) Receive Holding Register */ + #define REG_UART3_THR (0x400E1C1CU) /**< \brief (UART3) Transmit Holding Register */ + #define REG_UART3_BRGR (0x400E1C20U) /**< \brief (UART3) Baud Rate Generator Register */ + #define REG_UART3_CMPR (0x400E1C24U) /**< \brief (UART3) Comparison Register */ + #define REG_UART3_WPMR (0x400E1CE4U) /**< \brief (UART3) Write Protection Mode Register */ + #define REG_UART3_VERSION (0x400E1CFCU) /**< \brief (UART3) Version Register */ +#else + #define REG_UART3_CR (*(__O uint32_t*)0x400E1C00U) /**< \brief (UART3) Control Register */ + #define REG_UART3_MR (*(__IO uint32_t*)0x400E1C04U) /**< \brief (UART3) Mode Register */ + #define REG_UART3_IER (*(__O uint32_t*)0x400E1C08U) /**< \brief (UART3) Interrupt Enable Register */ + #define REG_UART3_IDR (*(__O uint32_t*)0x400E1C0CU) /**< \brief (UART3) Interrupt Disable Register */ + #define REG_UART3_IMR (*(__I uint32_t*)0x400E1C10U) /**< \brief (UART3) Interrupt Mask Register */ + #define REG_UART3_SR (*(__I uint32_t*)0x400E1C14U) /**< \brief (UART3) Status Register */ + #define REG_UART3_RHR (*(__I uint32_t*)0x400E1C18U) /**< \brief (UART3) Receive Holding Register */ + #define REG_UART3_THR (*(__O uint32_t*)0x400E1C1CU) /**< \brief (UART3) Transmit Holding Register */ + #define REG_UART3_BRGR (*(__IO uint32_t*)0x400E1C20U) /**< \brief (UART3) Baud Rate Generator Register */ + #define REG_UART3_CMPR (*(__IO uint32_t*)0x400E1C24U) /**< \brief (UART3) Comparison Register */ + #define REG_UART3_WPMR (*(__IO uint32_t*)0x400E1CE4U) /**< \brief (UART3) Write Protection Mode Register */ + #define REG_UART3_VERSION (*(__I uint32_t*)0x400E1CFCU) /**< \brief (UART3) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_UART3_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/uart4.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/uart4.h new file mode 100644 index 000000000..ba51c9478 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/uart4.h @@ -0,0 +1,67 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_UART4_INSTANCE_ +#define _SAME70_UART4_INSTANCE_ + +/* ========== Register definition for UART4 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_UART4_CR (0x400E1E00U) /**< \brief (UART4) Control Register */ + #define REG_UART4_MR (0x400E1E04U) /**< \brief (UART4) Mode Register */ + #define REG_UART4_IER (0x400E1E08U) /**< \brief (UART4) Interrupt Enable Register */ + #define REG_UART4_IDR (0x400E1E0CU) /**< \brief (UART4) Interrupt Disable Register */ + #define REG_UART4_IMR (0x400E1E10U) /**< \brief (UART4) Interrupt Mask Register */ + #define REG_UART4_SR (0x400E1E14U) /**< \brief (UART4) Status Register */ + #define REG_UART4_RHR (0x400E1E18U) /**< \brief (UART4) Receive Holding Register */ + #define REG_UART4_THR (0x400E1E1CU) /**< \brief (UART4) Transmit Holding Register */ + #define REG_UART4_BRGR (0x400E1E20U) /**< \brief (UART4) Baud Rate Generator Register */ + #define REG_UART4_CMPR (0x400E1E24U) /**< \brief (UART4) Comparison Register */ + #define REG_UART4_WPMR (0x400E1EE4U) /**< \brief (UART4) Write Protection Mode Register */ + #define REG_UART4_VERSION (0x400E1EFCU) /**< \brief (UART4) Version Register */ +#else + #define REG_UART4_CR (*(__O uint32_t*)0x400E1E00U) /**< \brief (UART4) Control Register */ + #define REG_UART4_MR (*(__IO uint32_t*)0x400E1E04U) /**< \brief (UART4) Mode Register */ + #define REG_UART4_IER (*(__O uint32_t*)0x400E1E08U) /**< \brief (UART4) Interrupt Enable Register */ + #define REG_UART4_IDR (*(__O uint32_t*)0x400E1E0CU) /**< \brief (UART4) Interrupt Disable Register */ + #define REG_UART4_IMR (*(__I uint32_t*)0x400E1E10U) /**< \brief (UART4) Interrupt Mask Register */ + #define REG_UART4_SR (*(__I uint32_t*)0x400E1E14U) /**< \brief (UART4) Status Register */ + #define REG_UART4_RHR (*(__I uint32_t*)0x400E1E18U) /**< \brief (UART4) Receive Holding Register */ + #define REG_UART4_THR (*(__O uint32_t*)0x400E1E1CU) /**< \brief (UART4) Transmit Holding Register */ + #define REG_UART4_BRGR (*(__IO uint32_t*)0x400E1E20U) /**< \brief (UART4) Baud Rate Generator Register */ + #define REG_UART4_CMPR (*(__IO uint32_t*)0x400E1E24U) /**< \brief (UART4) Comparison Register */ + #define REG_UART4_WPMR (*(__IO uint32_t*)0x400E1EE4U) /**< \brief (UART4) Write Protection Mode Register */ + #define REG_UART4_VERSION (*(__I uint32_t*)0x400E1EFCU) /**< \brief (UART4) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_UART4_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/usart0.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/usart0.h new file mode 100644 index 000000000..3f523ae0b --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/usart0.h @@ -0,0 +1,107 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_USART0_INSTANCE_ +#define _SAME70_USART0_INSTANCE_ + +/* ========== Register definition for USART0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_USART0_CR (0x40024000U) /**< \brief (USART0) Control Register */ + #define REG_USART0_MR (0x40024004U) /**< \brief (USART0) Mode Register */ + #define REG_USART0_IER (0x40024008U) /**< \brief (USART0) Interrupt Enable Register */ + #define REG_USART0_IDR (0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */ + #define REG_USART0_IMR (0x40024010U) /**< \brief (USART0) Interrupt Mask Register */ + #define REG_USART0_CSR (0x40024014U) /**< \brief (USART0) Channel Status Register */ + #define REG_USART0_RHR (0x40024018U) /**< \brief (USART0) Receive Holding Register */ + #define REG_USART0_THR (0x4002401CU) /**< \brief (USART0) Transmit Holding Register */ + #define REG_USART0_BRGR (0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */ + #define REG_USART0_RTOR (0x40024024U) /**< \brief (USART0) Receiver Time-out Register */ + #define REG_USART0_TTGR (0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */ + #define REG_USART0_FIDI (0x40024040U) /**< \brief (USART0) FI DI Ratio Register */ + #define REG_USART0_NER (0x40024044U) /**< \brief (USART0) Number of Errors Register */ + #define REG_USART0_IF (0x4002404CU) /**< \brief (USART0) IrDA Filter Register */ + #define REG_USART0_MAN (0x40024050U) /**< \brief (USART0) Manchester Configuration Register */ + #define REG_USART0_LINMR (0x40024054U) /**< \brief (USART0) LIN Mode Register */ + #define REG_USART0_LINIR (0x40024058U) /**< \brief (USART0) LIN Identifier Register */ + #define REG_USART0_LINBRR (0x4002405CU) /**< \brief (USART0) LIN Baud Rate Register */ + #define REG_USART0_LONMR (0x40024060U) /**< \brief (USART0) LON Mode Register */ + #define REG_USART0_LONPR (0x40024064U) /**< \brief (USART0) LON Preamble Register */ + #define REG_USART0_LONDL (0x40024068U) /**< \brief (USART0) LON Data Length Register */ + #define REG_USART0_LONL2HDR (0x4002406CU) /**< \brief (USART0) LON L2HDR Register */ + #define REG_USART0_LONBL (0x40024070U) /**< \brief (USART0) LON Backlog Register */ + #define REG_USART0_LONB1TX (0x40024074U) /**< \brief (USART0) LON Beta1 Tx Register */ + #define REG_USART0_LONB1RX (0x40024078U) /**< \brief (USART0) LON Beta1 Rx Register */ + #define REG_USART0_LONPRIO (0x4002407CU) /**< \brief (USART0) LON Priority Register */ + #define REG_USART0_IDTTX (0x40024080U) /**< \brief (USART0) LON IDT Tx Register */ + #define REG_USART0_IDTRX (0x40024084U) /**< \brief (USART0) LON IDT Rx Register */ + #define REG_USART0_ICDIFF (0x40024088U) /**< \brief (USART0) IC DIFF Register */ + #define REG_USART0_WPMR (0x400240E4U) /**< \brief (USART0) Write Protection Mode Register */ + #define REG_USART0_WPSR (0x400240E8U) /**< \brief (USART0) Write Protection Status Register */ + #define REG_USART0_VERSION (0x400240FCU) /**< \brief (USART0) Version Register */ +#else + #define REG_USART0_CR (*(__O uint32_t*)0x40024000U) /**< \brief (USART0) Control Register */ + #define REG_USART0_MR (*(__IO uint32_t*)0x40024004U) /**< \brief (USART0) Mode Register */ + #define REG_USART0_IER (*(__O uint32_t*)0x40024008U) /**< \brief (USART0) Interrupt Enable Register */ + #define REG_USART0_IDR (*(__O uint32_t*)0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */ + #define REG_USART0_IMR (*(__I uint32_t*)0x40024010U) /**< \brief (USART0) Interrupt Mask Register */ + #define REG_USART0_CSR (*(__I uint32_t*)0x40024014U) /**< \brief (USART0) Channel Status Register */ + #define REG_USART0_RHR (*(__I uint32_t*)0x40024018U) /**< \brief (USART0) Receive Holding Register */ + #define REG_USART0_THR (*(__O uint32_t*)0x4002401CU) /**< \brief (USART0) Transmit Holding Register */ + #define REG_USART0_BRGR (*(__IO uint32_t*)0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */ + #define REG_USART0_RTOR (*(__IO uint32_t*)0x40024024U) /**< \brief (USART0) Receiver Time-out Register */ + #define REG_USART0_TTGR (*(__IO uint32_t*)0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */ + #define REG_USART0_FIDI (*(__IO uint32_t*)0x40024040U) /**< \brief (USART0) FI DI Ratio Register */ + #define REG_USART0_NER (*(__I uint32_t*)0x40024044U) /**< \brief (USART0) Number of Errors Register */ + #define REG_USART0_IF (*(__IO uint32_t*)0x4002404CU) /**< \brief (USART0) IrDA Filter Register */ + #define REG_USART0_MAN (*(__IO uint32_t*)0x40024050U) /**< \brief (USART0) Manchester Configuration Register */ + #define REG_USART0_LINMR (*(__IO uint32_t*)0x40024054U) /**< \brief (USART0) LIN Mode Register */ + #define REG_USART0_LINIR (*(__IO uint32_t*)0x40024058U) /**< \brief (USART0) LIN Identifier Register */ + #define REG_USART0_LINBRR (*(__I uint32_t*)0x4002405CU) /**< \brief (USART0) LIN Baud Rate Register */ + #define REG_USART0_LONMR (*(__IO uint32_t*)0x40024060U) /**< \brief (USART0) LON Mode Register */ + #define REG_USART0_LONPR (*(__IO uint32_t*)0x40024064U) /**< \brief (USART0) LON Preamble Register */ + #define REG_USART0_LONDL (*(__IO uint32_t*)0x40024068U) /**< \brief (USART0) LON Data Length Register */ + #define REG_USART0_LONL2HDR (*(__IO uint32_t*)0x4002406CU) /**< \brief (USART0) LON L2HDR Register */ + #define REG_USART0_LONBL (*(__I uint32_t*)0x40024070U) /**< \brief (USART0) LON Backlog Register */ + #define REG_USART0_LONB1TX (*(__IO uint32_t*)0x40024074U) /**< \brief (USART0) LON Beta1 Tx Register */ + #define REG_USART0_LONB1RX (*(__IO uint32_t*)0x40024078U) /**< \brief (USART0) LON Beta1 Rx Register */ + #define REG_USART0_LONPRIO (*(__IO uint32_t*)0x4002407CU) /**< \brief (USART0) LON Priority Register */ + #define REG_USART0_IDTTX (*(__IO uint32_t*)0x40024080U) /**< \brief (USART0) LON IDT Tx Register */ + #define REG_USART0_IDTRX (*(__IO uint32_t*)0x40024084U) /**< \brief (USART0) LON IDT Rx Register */ + #define REG_USART0_ICDIFF (*(__IO uint32_t*)0x40024088U) /**< \brief (USART0) IC DIFF Register */ + #define REG_USART0_WPMR (*(__IO uint32_t*)0x400240E4U) /**< \brief (USART0) Write Protection Mode Register */ + #define REG_USART0_WPSR (*(__I uint32_t*)0x400240E8U) /**< \brief (USART0) Write Protection Status Register */ + #define REG_USART0_VERSION (*(__I uint32_t*)0x400240FCU) /**< \brief (USART0) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_USART0_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/usart1.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/usart1.h new file mode 100644 index 000000000..5b0fe493e --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/usart1.h @@ -0,0 +1,107 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_USART1_INSTANCE_ +#define _SAME70_USART1_INSTANCE_ + +/* ========== Register definition for USART1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_USART1_CR (0x40028000U) /**< \brief (USART1) Control Register */ + #define REG_USART1_MR (0x40028004U) /**< \brief (USART1) Mode Register */ + #define REG_USART1_IER (0x40028008U) /**< \brief (USART1) Interrupt Enable Register */ + #define REG_USART1_IDR (0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */ + #define REG_USART1_IMR (0x40028010U) /**< \brief (USART1) Interrupt Mask Register */ + #define REG_USART1_CSR (0x40028014U) /**< \brief (USART1) Channel Status Register */ + #define REG_USART1_RHR (0x40028018U) /**< \brief (USART1) Receive Holding Register */ + #define REG_USART1_THR (0x4002801CU) /**< \brief (USART1) Transmit Holding Register */ + #define REG_USART1_BRGR (0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */ + #define REG_USART1_RTOR (0x40028024U) /**< \brief (USART1) Receiver Time-out Register */ + #define REG_USART1_TTGR (0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */ + #define REG_USART1_FIDI (0x40028040U) /**< \brief (USART1) FI DI Ratio Register */ + #define REG_USART1_NER (0x40028044U) /**< \brief (USART1) Number of Errors Register */ + #define REG_USART1_IF (0x4002804CU) /**< \brief (USART1) IrDA Filter Register */ + #define REG_USART1_MAN (0x40028050U) /**< \brief (USART1) Manchester Configuration Register */ + #define REG_USART1_LINMR (0x40028054U) /**< \brief (USART1) LIN Mode Register */ + #define REG_USART1_LINIR (0x40028058U) /**< \brief (USART1) LIN Identifier Register */ + #define REG_USART1_LINBRR (0x4002805CU) /**< \brief (USART1) LIN Baud Rate Register */ + #define REG_USART1_LONMR (0x40028060U) /**< \brief (USART1) LON Mode Register */ + #define REG_USART1_LONPR (0x40028064U) /**< \brief (USART1) LON Preamble Register */ + #define REG_USART1_LONDL (0x40028068U) /**< \brief (USART1) LON Data Length Register */ + #define REG_USART1_LONL2HDR (0x4002806CU) /**< \brief (USART1) LON L2HDR Register */ + #define REG_USART1_LONBL (0x40028070U) /**< \brief (USART1) LON Backlog Register */ + #define REG_USART1_LONB1TX (0x40028074U) /**< \brief (USART1) LON Beta1 Tx Register */ + #define REG_USART1_LONB1RX (0x40028078U) /**< \brief (USART1) LON Beta1 Rx Register */ + #define REG_USART1_LONPRIO (0x4002807CU) /**< \brief (USART1) LON Priority Register */ + #define REG_USART1_IDTTX (0x40028080U) /**< \brief (USART1) LON IDT Tx Register */ + #define REG_USART1_IDTRX (0x40028084U) /**< \brief (USART1) LON IDT Rx Register */ + #define REG_USART1_ICDIFF (0x40028088U) /**< \brief (USART1) IC DIFF Register */ + #define REG_USART1_WPMR (0x400280E4U) /**< \brief (USART1) Write Protection Mode Register */ + #define REG_USART1_WPSR (0x400280E8U) /**< \brief (USART1) Write Protection Status Register */ + #define REG_USART1_VERSION (0x400280FCU) /**< \brief (USART1) Version Register */ +#else + #define REG_USART1_CR (*(__O uint32_t*)0x40028000U) /**< \brief (USART1) Control Register */ + #define REG_USART1_MR (*(__IO uint32_t*)0x40028004U) /**< \brief (USART1) Mode Register */ + #define REG_USART1_IER (*(__O uint32_t*)0x40028008U) /**< \brief (USART1) Interrupt Enable Register */ + #define REG_USART1_IDR (*(__O uint32_t*)0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */ + #define REG_USART1_IMR (*(__I uint32_t*)0x40028010U) /**< \brief (USART1) Interrupt Mask Register */ + #define REG_USART1_CSR (*(__I uint32_t*)0x40028014U) /**< \brief (USART1) Channel Status Register */ + #define REG_USART1_RHR (*(__I uint32_t*)0x40028018U) /**< \brief (USART1) Receive Holding Register */ + #define REG_USART1_THR (*(__O uint32_t*)0x4002801CU) /**< \brief (USART1) Transmit Holding Register */ + #define REG_USART1_BRGR (*(__IO uint32_t*)0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */ + #define REG_USART1_RTOR (*(__IO uint32_t*)0x40028024U) /**< \brief (USART1) Receiver Time-out Register */ + #define REG_USART1_TTGR (*(__IO uint32_t*)0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */ + #define REG_USART1_FIDI (*(__IO uint32_t*)0x40028040U) /**< \brief (USART1) FI DI Ratio Register */ + #define REG_USART1_NER (*(__I uint32_t*)0x40028044U) /**< \brief (USART1) Number of Errors Register */ + #define REG_USART1_IF (*(__IO uint32_t*)0x4002804CU) /**< \brief (USART1) IrDA Filter Register */ + #define REG_USART1_MAN (*(__IO uint32_t*)0x40028050U) /**< \brief (USART1) Manchester Configuration Register */ + #define REG_USART1_LINMR (*(__IO uint32_t*)0x40028054U) /**< \brief (USART1) LIN Mode Register */ + #define REG_USART1_LINIR (*(__IO uint32_t*)0x40028058U) /**< \brief (USART1) LIN Identifier Register */ + #define REG_USART1_LINBRR (*(__I uint32_t*)0x4002805CU) /**< \brief (USART1) LIN Baud Rate Register */ + #define REG_USART1_LONMR (*(__IO uint32_t*)0x40028060U) /**< \brief (USART1) LON Mode Register */ + #define REG_USART1_LONPR (*(__IO uint32_t*)0x40028064U) /**< \brief (USART1) LON Preamble Register */ + #define REG_USART1_LONDL (*(__IO uint32_t*)0x40028068U) /**< \brief (USART1) LON Data Length Register */ + #define REG_USART1_LONL2HDR (*(__IO uint32_t*)0x4002806CU) /**< \brief (USART1) LON L2HDR Register */ + #define REG_USART1_LONBL (*(__I uint32_t*)0x40028070U) /**< \brief (USART1) LON Backlog Register */ + #define REG_USART1_LONB1TX (*(__IO uint32_t*)0x40028074U) /**< \brief (USART1) LON Beta1 Tx Register */ + #define REG_USART1_LONB1RX (*(__IO uint32_t*)0x40028078U) /**< \brief (USART1) LON Beta1 Rx Register */ + #define REG_USART1_LONPRIO (*(__IO uint32_t*)0x4002807CU) /**< \brief (USART1) LON Priority Register */ + #define REG_USART1_IDTTX (*(__IO uint32_t*)0x40028080U) /**< \brief (USART1) LON IDT Tx Register */ + #define REG_USART1_IDTRX (*(__IO uint32_t*)0x40028084U) /**< \brief (USART1) LON IDT Rx Register */ + #define REG_USART1_ICDIFF (*(__IO uint32_t*)0x40028088U) /**< \brief (USART1) IC DIFF Register */ + #define REG_USART1_WPMR (*(__IO uint32_t*)0x400280E4U) /**< \brief (USART1) Write Protection Mode Register */ + #define REG_USART1_WPSR (*(__I uint32_t*)0x400280E8U) /**< \brief (USART1) Write Protection Status Register */ + #define REG_USART1_VERSION (*(__I uint32_t*)0x400280FCU) /**< \brief (USART1) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_USART1_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/usart2.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/usart2.h new file mode 100644 index 000000000..575c10c8c --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/usart2.h @@ -0,0 +1,107 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_USART2_INSTANCE_ +#define _SAME70_USART2_INSTANCE_ + +/* ========== Register definition for USART2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_USART2_CR (0x4002C000U) /**< \brief (USART2) Control Register */ + #define REG_USART2_MR (0x4002C004U) /**< \brief (USART2) Mode Register */ + #define REG_USART2_IER (0x4002C008U) /**< \brief (USART2) Interrupt Enable Register */ + #define REG_USART2_IDR (0x4002C00CU) /**< \brief (USART2) Interrupt Disable Register */ + #define REG_USART2_IMR (0x4002C010U) /**< \brief (USART2) Interrupt Mask Register */ + #define REG_USART2_CSR (0x4002C014U) /**< \brief (USART2) Channel Status Register */ + #define REG_USART2_RHR (0x4002C018U) /**< \brief (USART2) Receive Holding Register */ + #define REG_USART2_THR (0x4002C01CU) /**< \brief (USART2) Transmit Holding Register */ + #define REG_USART2_BRGR (0x4002C020U) /**< \brief (USART2) Baud Rate Generator Register */ + #define REG_USART2_RTOR (0x4002C024U) /**< \brief (USART2) Receiver Time-out Register */ + #define REG_USART2_TTGR (0x4002C028U) /**< \brief (USART2) Transmitter Timeguard Register */ + #define REG_USART2_FIDI (0x4002C040U) /**< \brief (USART2) FI DI Ratio Register */ + #define REG_USART2_NER (0x4002C044U) /**< \brief (USART2) Number of Errors Register */ + #define REG_USART2_IF (0x4002C04CU) /**< \brief (USART2) IrDA Filter Register */ + #define REG_USART2_MAN (0x4002C050U) /**< \brief (USART2) Manchester Configuration Register */ + #define REG_USART2_LINMR (0x4002C054U) /**< \brief (USART2) LIN Mode Register */ + #define REG_USART2_LINIR (0x4002C058U) /**< \brief (USART2) LIN Identifier Register */ + #define REG_USART2_LINBRR (0x4002C05CU) /**< \brief (USART2) LIN Baud Rate Register */ + #define REG_USART2_LONMR (0x4002C060U) /**< \brief (USART2) LON Mode Register */ + #define REG_USART2_LONPR (0x4002C064U) /**< \brief (USART2) LON Preamble Register */ + #define REG_USART2_LONDL (0x4002C068U) /**< \brief (USART2) LON Data Length Register */ + #define REG_USART2_LONL2HDR (0x4002C06CU) /**< \brief (USART2) LON L2HDR Register */ + #define REG_USART2_LONBL (0x4002C070U) /**< \brief (USART2) LON Backlog Register */ + #define REG_USART2_LONB1TX (0x4002C074U) /**< \brief (USART2) LON Beta1 Tx Register */ + #define REG_USART2_LONB1RX (0x4002C078U) /**< \brief (USART2) LON Beta1 Rx Register */ + #define REG_USART2_LONPRIO (0x4002C07CU) /**< \brief (USART2) LON Priority Register */ + #define REG_USART2_IDTTX (0x4002C080U) /**< \brief (USART2) LON IDT Tx Register */ + #define REG_USART2_IDTRX (0x4002C084U) /**< \brief (USART2) LON IDT Rx Register */ + #define REG_USART2_ICDIFF (0x4002C088U) /**< \brief (USART2) IC DIFF Register */ + #define REG_USART2_WPMR (0x4002C0E4U) /**< \brief (USART2) Write Protection Mode Register */ + #define REG_USART2_WPSR (0x4002C0E8U) /**< \brief (USART2) Write Protection Status Register */ + #define REG_USART2_VERSION (0x4002C0FCU) /**< \brief (USART2) Version Register */ +#else + #define REG_USART2_CR (*(__O uint32_t*)0x4002C000U) /**< \brief (USART2) Control Register */ + #define REG_USART2_MR (*(__IO uint32_t*)0x4002C004U) /**< \brief (USART2) Mode Register */ + #define REG_USART2_IER (*(__O uint32_t*)0x4002C008U) /**< \brief (USART2) Interrupt Enable Register */ + #define REG_USART2_IDR (*(__O uint32_t*)0x4002C00CU) /**< \brief (USART2) Interrupt Disable Register */ + #define REG_USART2_IMR (*(__I uint32_t*)0x4002C010U) /**< \brief (USART2) Interrupt Mask Register */ + #define REG_USART2_CSR (*(__I uint32_t*)0x4002C014U) /**< \brief (USART2) Channel Status Register */ + #define REG_USART2_RHR (*(__I uint32_t*)0x4002C018U) /**< \brief (USART2) Receive Holding Register */ + #define REG_USART2_THR (*(__O uint32_t*)0x4002C01CU) /**< \brief (USART2) Transmit Holding Register */ + #define REG_USART2_BRGR (*(__IO uint32_t*)0x4002C020U) /**< \brief (USART2) Baud Rate Generator Register */ + #define REG_USART2_RTOR (*(__IO uint32_t*)0x4002C024U) /**< \brief (USART2) Receiver Time-out Register */ + #define REG_USART2_TTGR (*(__IO uint32_t*)0x4002C028U) /**< \brief (USART2) Transmitter Timeguard Register */ + #define REG_USART2_FIDI (*(__IO uint32_t*)0x4002C040U) /**< \brief (USART2) FI DI Ratio Register */ + #define REG_USART2_NER (*(__I uint32_t*)0x4002C044U) /**< \brief (USART2) Number of Errors Register */ + #define REG_USART2_IF (*(__IO uint32_t*)0x4002C04CU) /**< \brief (USART2) IrDA Filter Register */ + #define REG_USART2_MAN (*(__IO uint32_t*)0x4002C050U) /**< \brief (USART2) Manchester Configuration Register */ + #define REG_USART2_LINMR (*(__IO uint32_t*)0x4002C054U) /**< \brief (USART2) LIN Mode Register */ + #define REG_USART2_LINIR (*(__IO uint32_t*)0x4002C058U) /**< \brief (USART2) LIN Identifier Register */ + #define REG_USART2_LINBRR (*(__I uint32_t*)0x4002C05CU) /**< \brief (USART2) LIN Baud Rate Register */ + #define REG_USART2_LONMR (*(__IO uint32_t*)0x4002C060U) /**< \brief (USART2) LON Mode Register */ + #define REG_USART2_LONPR (*(__IO uint32_t*)0x4002C064U) /**< \brief (USART2) LON Preamble Register */ + #define REG_USART2_LONDL (*(__IO uint32_t*)0x4002C068U) /**< \brief (USART2) LON Data Length Register */ + #define REG_USART2_LONL2HDR (*(__IO uint32_t*)0x4002C06CU) /**< \brief (USART2) LON L2HDR Register */ + #define REG_USART2_LONBL (*(__I uint32_t*)0x4002C070U) /**< \brief (USART2) LON Backlog Register */ + #define REG_USART2_LONB1TX (*(__IO uint32_t*)0x4002C074U) /**< \brief (USART2) LON Beta1 Tx Register */ + #define REG_USART2_LONB1RX (*(__IO uint32_t*)0x4002C078U) /**< \brief (USART2) LON Beta1 Rx Register */ + #define REG_USART2_LONPRIO (*(__IO uint32_t*)0x4002C07CU) /**< \brief (USART2) LON Priority Register */ + #define REG_USART2_IDTTX (*(__IO uint32_t*)0x4002C080U) /**< \brief (USART2) LON IDT Tx Register */ + #define REG_USART2_IDTRX (*(__IO uint32_t*)0x4002C084U) /**< \brief (USART2) LON IDT Rx Register */ + #define REG_USART2_ICDIFF (*(__IO uint32_t*)0x4002C088U) /**< \brief (USART2) IC DIFF Register */ + #define REG_USART2_WPMR (*(__IO uint32_t*)0x4002C0E4U) /**< \brief (USART2) Write Protection Mode Register */ + #define REG_USART2_WPSR (*(__I uint32_t*)0x4002C0E8U) /**< \brief (USART2) Write Protection Status Register */ + #define REG_USART2_VERSION (*(__I uint32_t*)0x4002C0FCU) /**< \brief (USART2) Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_USART2_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h new file mode 100644 index 000000000..3ae80f036 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/usbhs.h @@ -0,0 +1,245 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_USBHS_INSTANCE_ +#define _SAME70_USBHS_INSTANCE_ + +/* ========== Register definition for USBHS peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_USBHS_DEVCTRL (0x40038000U) /**< \brief (USBHS) Device General Control Register */ + #define REG_USBHS_DEVISR (0x40038004U) /**< \brief (USBHS) Device Global Interrupt Status Register */ + #define REG_USBHS_DEVICR (0x40038008U) /**< \brief (USBHS) Device Global Interrupt Clear Register */ + #define REG_USBHS_DEVIFR (0x4003800CU) /**< \brief (USBHS) Device Global Interrupt Set Register */ + #define REG_USBHS_DEVIMR (0x40038010U) /**< \brief (USBHS) Device Global Interrupt Mask Register */ + #define REG_USBHS_DEVIDR (0x40038014U) /**< \brief (USBHS) Device Global Interrupt Disable Register */ + #define REG_USBHS_DEVIER (0x40038018U) /**< \brief (USBHS) Device Global Interrupt Enable Register */ + #define REG_USBHS_DEVEPT (0x4003801CU) /**< \brief (USBHS) Device Endpoint Register */ + #define REG_USBHS_DEVFNUM (0x40038020U) /**< \brief (USBHS) Device Frame Number Register */ + #define REG_USBHS_DEVEPTCFG (0x40038100U) /**< \brief (USBHS) Device Endpoint Configuration Register (n = 0) */ + #define REG_USBHS_DEVEPTISR (0x40038130U) /**< \brief (USBHS) Device Endpoint Status Register (n = 0) */ + #define REG_USBHS_DEVEPTICR (0x40038160U) /**< \brief (USBHS) Device Endpoint Clear Register (n = 0) */ + #define REG_USBHS_DEVEPTIFR (0x40038190U) /**< \brief (USBHS) Device Endpoint Set Register (n = 0) */ + #define REG_USBHS_DEVEPTIMR (0x400381C0U) /**< \brief (USBHS) Device Endpoint Mask Register (n = 0) */ + #define REG_USBHS_DEVEPTIER (0x400381F0U) /**< \brief (USBHS) Device Endpoint Enable Register (n = 0) */ + #define REG_USBHS_DEVEPTIDR (0x40038220U) /**< \brief (USBHS) Device Endpoint Disable Register (n = 0) */ + #define REG_USBHS_DEVDMANXTDSC1 (0x40038310U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) */ + #define REG_USBHS_DEVDMAADDRESS1 (0x40038314U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 1) */ + #define REG_USBHS_DEVDMACONTROL1 (0x40038318U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 1) */ + #define REG_USBHS_DEVDMASTATUS1 (0x4003831CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 1) */ + #define REG_USBHS_DEVDMANXTDSC2 (0x40038320U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 2) */ + #define REG_USBHS_DEVDMAADDRESS2 (0x40038324U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 2) */ + #define REG_USBHS_DEVDMACONTROL2 (0x40038328U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 2) */ + #define REG_USBHS_DEVDMASTATUS2 (0x4003832CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 2) */ + #define REG_USBHS_DEVDMANXTDSC3 (0x40038330U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 3) */ + #define REG_USBHS_DEVDMAADDRESS3 (0x40038334U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 3) */ + #define REG_USBHS_DEVDMACONTROL3 (0x40038338U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 3) */ + #define REG_USBHS_DEVDMASTATUS3 (0x4003833CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 3) */ + #define REG_USBHS_DEVDMANXTDSC4 (0x40038340U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 4) */ + #define REG_USBHS_DEVDMAADDRESS4 (0x40038344U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 4) */ + #define REG_USBHS_DEVDMACONTROL4 (0x40038348U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 4) */ + #define REG_USBHS_DEVDMASTATUS4 (0x4003834CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 4) */ + #define REG_USBHS_DEVDMANXTDSC5 (0x40038350U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 5) */ + #define REG_USBHS_DEVDMAADDRESS5 (0x40038354U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 5) */ + #define REG_USBHS_DEVDMACONTROL5 (0x40038358U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 5) */ + #define REG_USBHS_DEVDMASTATUS5 (0x4003835CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 5) */ + #define REG_USBHS_DEVDMANXTDSC6 (0x40038360U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 6) */ + #define REG_USBHS_DEVDMAADDRESS6 (0x40038364U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 6) */ + #define REG_USBHS_DEVDMACONTROL6 (0x40038368U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 6) */ + #define REG_USBHS_DEVDMASTATUS6 (0x4003836CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 6) */ + #define REG_USBHS_DEVDMANXTDSC7 (0x40038370U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 7) */ + #define REG_USBHS_DEVDMAADDRESS7 (0x40038374U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 7) */ + #define REG_USBHS_DEVDMACONTROL7 (0x40038378U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 7) */ + #define REG_USBHS_DEVDMASTATUS7 (0x4003837CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 7) */ + #define REG_USBHS_HSTCTRL (0x40038400U) /**< \brief (USBHS) Host General Control Register */ + #define REG_USBHS_HSTISR (0x40038404U) /**< \brief (USBHS) Host Global Interrupt Status Register */ + #define REG_USBHS_HSTICR (0x40038408U) /**< \brief (USBHS) Host Global Interrupt Clear Register */ + #define REG_USBHS_HSTIFR (0x4003840CU) /**< \brief (USBHS) Host Global Interrupt Set Register */ + #define REG_USBHS_HSTIMR (0x40038410U) /**< \brief (USBHS) Host Global Interrupt Mask Register */ + #define REG_USBHS_HSTIDR (0x40038414U) /**< \brief (USBHS) Host Global Interrupt Disable Register */ + #define REG_USBHS_HSTIER (0x40038418U) /**< \brief (USBHS) Host Global Interrupt Enable Register */ + #define REG_USBHS_HSTPIP (0x4003841CU) /**< \brief (USBHS) Host Pipe Register */ + #define REG_USBHS_HSTFNUM (0x40038420U) /**< \brief (USBHS) Host Frame Number Register */ + #define REG_USBHS_HSTADDR1 (0x40038424U) /**< \brief (USBHS) Host Address 1 Register */ + #define REG_USBHS_HSTADDR2 (0x40038428U) /**< \brief (USBHS) Host Address 2 Register */ + #define REG_USBHS_HSTADDR3 (0x4003842CU) /**< \brief (USBHS) Host Address 3 Register */ + #define REG_USBHS_HSTPIPCFG (0x40038500U) /**< \brief (USBHS) Host Pipe Configuration Register (n = 0) */ + #define REG_USBHS_HSTPIPISR (0x40038530U) /**< \brief (USBHS) Host Pipe Status Register (n = 0) */ + #define REG_USBHS_HSTPIPICR (0x40038560U) /**< \brief (USBHS) Host Pipe Clear Register (n = 0) */ + #define REG_USBHS_HSTPIPIFR (0x40038590U) /**< \brief (USBHS) Host Pipe Set Register (n = 0) */ + #define REG_USBHS_HSTPIPIMR (0x400385C0U) /**< \brief (USBHS) Host Pipe Mask Register (n = 0) */ + #define REG_USBHS_HSTPIPIER (0x400385F0U) /**< \brief (USBHS) Host Pipe Enable Register (n = 0) */ + #define REG_USBHS_HSTPIPIDR (0x40038620U) /**< \brief (USBHS) Host Pipe Disable Register (n = 0) */ + #define REG_USBHS_HSTPIPINRQ (0x40038650U) /**< \brief (USBHS) Host Pipe IN Request Register (n = 0) */ + #define REG_USBHS_HSTPIPERR (0x40038680U) /**< \brief (USBHS) Host Pipe Error Register (n = 0) */ + #define REG_USBHS_HSTDMANXTDSC1 (0x40038710U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) */ + #define REG_USBHS_HSTDMAADDRESS1 (0x40038714U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 1) */ + #define REG_USBHS_HSTDMACONTROL1 (0x40038718U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 1) */ + #define REG_USBHS_HSTDMASTATUS1 (0x4003871CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 1) */ + #define REG_USBHS_HSTDMANXTDSC2 (0x40038720U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 2) */ + #define REG_USBHS_HSTDMAADDRESS2 (0x40038724U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 2) */ + #define REG_USBHS_HSTDMACONTROL2 (0x40038728U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 2) */ + #define REG_USBHS_HSTDMASTATUS2 (0x4003872CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 2) */ + #define REG_USBHS_HSTDMANXTDSC3 (0x40038730U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 3) */ + #define REG_USBHS_HSTDMAADDRESS3 (0x40038734U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 3) */ + #define REG_USBHS_HSTDMACONTROL3 (0x40038738U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 3) */ + #define REG_USBHS_HSTDMASTATUS3 (0x4003873CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 3) */ + #define REG_USBHS_HSTDMANXTDSC4 (0x40038740U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 4) */ + #define REG_USBHS_HSTDMAADDRESS4 (0x40038744U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 4) */ + #define REG_USBHS_HSTDMACONTROL4 (0x40038748U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 4) */ + #define REG_USBHS_HSTDMASTATUS4 (0x4003874CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 4) */ + #define REG_USBHS_HSTDMANXTDSC5 (0x40038750U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 5) */ + #define REG_USBHS_HSTDMAADDRESS5 (0x40038754U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 5) */ + #define REG_USBHS_HSTDMACONTROL5 (0x40038758U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 5) */ + #define REG_USBHS_HSTDMASTATUS5 (0x4003875CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 5) */ + #define REG_USBHS_HSTDMANXTDSC6 (0x40038760U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 6) */ + #define REG_USBHS_HSTDMAADDRESS6 (0x40038764U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 6) */ + #define REG_USBHS_HSTDMACONTROL6 (0x40038768U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 6) */ + #define REG_USBHS_HSTDMASTATUS6 (0x4003876CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 6) */ + #define REG_USBHS_HSTDMANXTDSC7 (0x40038770U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 7) */ + #define REG_USBHS_HSTDMAADDRESS7 (0x40038774U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 7) */ + #define REG_USBHS_HSTDMACONTROL7 (0x40038778U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 7) */ + #define REG_USBHS_HSTDMASTATUS7 (0x4003877CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 7) */ + #define REG_USBHS_CTRL (0x40038800U) /**< \brief (USBHS) General Control Register */ + #define REG_USBHS_SR (0x40038804U) /**< \brief (USBHS) General Status Register */ + #define REG_USBHS_SCR (0x40038808U) /**< \brief (USBHS) General Status Clear Register */ + #define REG_USBHS_SFR (0x4003880CU) /**< \brief (USBHS) General Status Set Register */ + #define REG_USBHS_TSTA1 (0x40038810U) /**< \brief (USBHS) General Test A1 Register */ + #define REG_USBHS_TSTA2 (0x40038814U) /**< \brief (USBHS) General Test A2 Register */ + #define REG_USBHS_VERSION (0x40038818U) /**< \brief (USBHS) General Version Register */ + #define REG_USBHS_FSM (0x4003882CU) /**< \brief (USBHS) General Finite State Machine Register */ +#else + #define REG_USBHS_DEVCTRL (*(__IO uint32_t*)0x40038000U) /**< \brief (USBHS) Device General Control Register */ + #define REG_USBHS_DEVISR (*(__I uint32_t*)0x40038004U) /**< \brief (USBHS) Device Global Interrupt Status Register */ + #define REG_USBHS_DEVICR (*(__O uint32_t*)0x40038008U) /**< \brief (USBHS) Device Global Interrupt Clear Register */ + #define REG_USBHS_DEVIFR (*(__O uint32_t*)0x4003800CU) /**< \brief (USBHS) Device Global Interrupt Set Register */ + #define REG_USBHS_DEVIMR (*(__I uint32_t*)0x40038010U) /**< \brief (USBHS) Device Global Interrupt Mask Register */ + #define REG_USBHS_DEVIDR (*(__O uint32_t*)0x40038014U) /**< \brief (USBHS) Device Global Interrupt Disable Register */ + #define REG_USBHS_DEVIER (*(__O uint32_t*)0x40038018U) /**< \brief (USBHS) Device Global Interrupt Enable Register */ + #define REG_USBHS_DEVEPT (*(__IO uint32_t*)0x4003801CU) /**< \brief (USBHS) Device Endpoint Register */ + #define REG_USBHS_DEVFNUM (*(__I uint32_t*)0x40038020U) /**< \brief (USBHS) Device Frame Number Register */ + #define REG_USBHS_DEVEPTCFG (*(__IO uint32_t*)0x40038100U) /**< \brief (USBHS) Device Endpoint Configuration Register (n = 0) */ + #define REG_USBHS_DEVEPTISR (*(__I uint32_t*)0x40038130U) /**< \brief (USBHS) Device Endpoint Status Register (n = 0) */ + #define REG_USBHS_DEVEPTICR (*(__O uint32_t*)0x40038160U) /**< \brief (USBHS) Device Endpoint Clear Register (n = 0) */ + #define REG_USBHS_DEVEPTIFR (*(__O uint32_t*)0x40038190U) /**< \brief (USBHS) Device Endpoint Set Register (n = 0) */ + #define REG_USBHS_DEVEPTIMR (*(__I uint32_t*)0x400381C0U) /**< \brief (USBHS) Device Endpoint Mask Register (n = 0) */ + #define REG_USBHS_DEVEPTIER (*(__O uint32_t*)0x400381F0U) /**< \brief (USBHS) Device Endpoint Enable Register (n = 0) */ + #define REG_USBHS_DEVEPTIDR (*(__O uint32_t*)0x40038220U) /**< \brief (USBHS) Device Endpoint Disable Register (n = 0) */ + #define REG_USBHS_DEVDMANXTDSC1 (*(__IO uint32_t*)0x40038310U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) */ + #define REG_USBHS_DEVDMAADDRESS1 (*(__IO uint32_t*)0x40038314U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 1) */ + #define REG_USBHS_DEVDMACONTROL1 (*(__IO uint32_t*)0x40038318U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 1) */ + #define REG_USBHS_DEVDMASTATUS1 (*(__IO uint32_t*)0x4003831CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 1) */ + #define REG_USBHS_DEVDMANXTDSC2 (*(__IO uint32_t*)0x40038320U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 2) */ + #define REG_USBHS_DEVDMAADDRESS2 (*(__IO uint32_t*)0x40038324U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 2) */ + #define REG_USBHS_DEVDMACONTROL2 (*(__IO uint32_t*)0x40038328U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 2) */ + #define REG_USBHS_DEVDMASTATUS2 (*(__IO uint32_t*)0x4003832CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 2) */ + #define REG_USBHS_DEVDMANXTDSC3 (*(__IO uint32_t*)0x40038330U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 3) */ + #define REG_USBHS_DEVDMAADDRESS3 (*(__IO uint32_t*)0x40038334U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 3) */ + #define REG_USBHS_DEVDMACONTROL3 (*(__IO uint32_t*)0x40038338U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 3) */ + #define REG_USBHS_DEVDMASTATUS3 (*(__IO uint32_t*)0x4003833CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 3) */ + #define REG_USBHS_DEVDMANXTDSC4 (*(__IO uint32_t*)0x40038340U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 4) */ + #define REG_USBHS_DEVDMAADDRESS4 (*(__IO uint32_t*)0x40038344U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 4) */ + #define REG_USBHS_DEVDMACONTROL4 (*(__IO uint32_t*)0x40038348U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 4) */ + #define REG_USBHS_DEVDMASTATUS4 (*(__IO uint32_t*)0x4003834CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 4) */ + #define REG_USBHS_DEVDMANXTDSC5 (*(__IO uint32_t*)0x40038350U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 5) */ + #define REG_USBHS_DEVDMAADDRESS5 (*(__IO uint32_t*)0x40038354U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 5) */ + #define REG_USBHS_DEVDMACONTROL5 (*(__IO uint32_t*)0x40038358U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 5) */ + #define REG_USBHS_DEVDMASTATUS5 (*(__IO uint32_t*)0x4003835CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 5) */ + #define REG_USBHS_DEVDMANXTDSC6 (*(__IO uint32_t*)0x40038360U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 6) */ + #define REG_USBHS_DEVDMAADDRESS6 (*(__IO uint32_t*)0x40038364U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 6) */ + #define REG_USBHS_DEVDMACONTROL6 (*(__IO uint32_t*)0x40038368U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 6) */ + #define REG_USBHS_DEVDMASTATUS6 (*(__IO uint32_t*)0x4003836CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 6) */ + #define REG_USBHS_DEVDMANXTDSC7 (*(__IO uint32_t*)0x40038370U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 7) */ + #define REG_USBHS_DEVDMAADDRESS7 (*(__IO uint32_t*)0x40038374U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 7) */ + #define REG_USBHS_DEVDMACONTROL7 (*(__IO uint32_t*)0x40038378U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 7) */ + #define REG_USBHS_DEVDMASTATUS7 (*(__IO uint32_t*)0x4003837CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 7) */ + #define REG_USBHS_HSTCTRL (*(__IO uint32_t*)0x40038400U) /**< \brief (USBHS) Host General Control Register */ + #define REG_USBHS_HSTISR (*(__I uint32_t*)0x40038404U) /**< \brief (USBHS) Host Global Interrupt Status Register */ + #define REG_USBHS_HSTICR (*(__O uint32_t*)0x40038408U) /**< \brief (USBHS) Host Global Interrupt Clear Register */ + #define REG_USBHS_HSTIFR (*(__O uint32_t*)0x4003840CU) /**< \brief (USBHS) Host Global Interrupt Set Register */ + #define REG_USBHS_HSTIMR (*(__I uint32_t*)0x40038410U) /**< \brief (USBHS) Host Global Interrupt Mask Register */ + #define REG_USBHS_HSTIDR (*(__O uint32_t*)0x40038414U) /**< \brief (USBHS) Host Global Interrupt Disable Register */ + #define REG_USBHS_HSTIER (*(__O uint32_t*)0x40038418U) /**< \brief (USBHS) Host Global Interrupt Enable Register */ + #define REG_USBHS_HSTPIP (*(__IO uint32_t*)0x4003841CU) /**< \brief (USBHS) Host Pipe Register */ + #define REG_USBHS_HSTFNUM (*(__IO uint32_t*)0x40038420U) /**< \brief (USBHS) Host Frame Number Register */ + #define REG_USBHS_HSTADDR1 (*(__IO uint32_t*)0x40038424U) /**< \brief (USBHS) Host Address 1 Register */ + #define REG_USBHS_HSTADDR2 (*(__IO uint32_t*)0x40038428U) /**< \brief (USBHS) Host Address 2 Register */ + #define REG_USBHS_HSTADDR3 (*(__IO uint32_t*)0x4003842CU) /**< \brief (USBHS) Host Address 3 Register */ + #define REG_USBHS_HSTPIPCFG (*(__IO uint32_t*)0x40038500U) /**< \brief (USBHS) Host Pipe Configuration Register (n = 0) */ + #define REG_USBHS_HSTPIPISR (*(__I uint32_t*)0x40038530U) /**< \brief (USBHS) Host Pipe Status Register (n = 0) */ + #define REG_USBHS_HSTPIPICR (*(__O uint32_t*)0x40038560U) /**< \brief (USBHS) Host Pipe Clear Register (n = 0) */ + #define REG_USBHS_HSTPIPIFR (*(__O uint32_t*)0x40038590U) /**< \brief (USBHS) Host Pipe Set Register (n = 0) */ + #define REG_USBHS_HSTPIPIMR (*(__I uint32_t*)0x400385C0U) /**< \brief (USBHS) Host Pipe Mask Register (n = 0) */ + #define REG_USBHS_HSTPIPIER (*(__O uint32_t*)0x400385F0U) /**< \brief (USBHS) Host Pipe Enable Register (n = 0) */ + #define REG_USBHS_HSTPIPIDR (*(__O uint32_t*)0x40038620U) /**< \brief (USBHS) Host Pipe Disable Register (n = 0) */ + #define REG_USBHS_HSTPIPINRQ (*(__IO uint32_t*)0x40038650U) /**< \brief (USBHS) Host Pipe IN Request Register (n = 0) */ + #define REG_USBHS_HSTPIPERR (*(__IO uint32_t*)0x40038680U) /**< \brief (USBHS) Host Pipe Error Register (n = 0) */ + #define REG_USBHS_HSTDMANXTDSC1 (*(__IO uint32_t*)0x40038710U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) */ + #define REG_USBHS_HSTDMAADDRESS1 (*(__IO uint32_t*)0x40038714U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 1) */ + #define REG_USBHS_HSTDMACONTROL1 (*(__IO uint32_t*)0x40038718U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 1) */ + #define REG_USBHS_HSTDMASTATUS1 (*(__IO uint32_t*)0x4003871CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 1) */ + #define REG_USBHS_HSTDMANXTDSC2 (*(__IO uint32_t*)0x40038720U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 2) */ + #define REG_USBHS_HSTDMAADDRESS2 (*(__IO uint32_t*)0x40038724U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 2) */ + #define REG_USBHS_HSTDMACONTROL2 (*(__IO uint32_t*)0x40038728U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 2) */ + #define REG_USBHS_HSTDMASTATUS2 (*(__IO uint32_t*)0x4003872CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 2) */ + #define REG_USBHS_HSTDMANXTDSC3 (*(__IO uint32_t*)0x40038730U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 3) */ + #define REG_USBHS_HSTDMAADDRESS3 (*(__IO uint32_t*)0x40038734U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 3) */ + #define REG_USBHS_HSTDMACONTROL3 (*(__IO uint32_t*)0x40038738U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 3) */ + #define REG_USBHS_HSTDMASTATUS3 (*(__IO uint32_t*)0x4003873CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 3) */ + #define REG_USBHS_HSTDMANXTDSC4 (*(__IO uint32_t*)0x40038740U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 4) */ + #define REG_USBHS_HSTDMAADDRESS4 (*(__IO uint32_t*)0x40038744U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 4) */ + #define REG_USBHS_HSTDMACONTROL4 (*(__IO uint32_t*)0x40038748U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 4) */ + #define REG_USBHS_HSTDMASTATUS4 (*(__IO uint32_t*)0x4003874CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 4) */ + #define REG_USBHS_HSTDMANXTDSC5 (*(__IO uint32_t*)0x40038750U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 5) */ + #define REG_USBHS_HSTDMAADDRESS5 (*(__IO uint32_t*)0x40038754U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 5) */ + #define REG_USBHS_HSTDMACONTROL5 (*(__IO uint32_t*)0x40038758U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 5) */ + #define REG_USBHS_HSTDMASTATUS5 (*(__IO uint32_t*)0x4003875CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 5) */ + #define REG_USBHS_HSTDMANXTDSC6 (*(__IO uint32_t*)0x40038760U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 6) */ + #define REG_USBHS_HSTDMAADDRESS6 (*(__IO uint32_t*)0x40038764U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 6) */ + #define REG_USBHS_HSTDMACONTROL6 (*(__IO uint32_t*)0x40038768U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 6) */ + #define REG_USBHS_HSTDMASTATUS6 (*(__IO uint32_t*)0x4003876CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 6) */ + #define REG_USBHS_HSTDMANXTDSC7 (*(__IO uint32_t*)0x40038770U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 7) */ + #define REG_USBHS_HSTDMAADDRESS7 (*(__IO uint32_t*)0x40038774U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 7) */ + #define REG_USBHS_HSTDMACONTROL7 (*(__IO uint32_t*)0x40038778U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 7) */ + #define REG_USBHS_HSTDMASTATUS7 (*(__IO uint32_t*)0x4003877CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 7) */ + #define REG_USBHS_CTRL (*(__IO uint32_t*)0x40038800U) /**< \brief (USBHS) General Control Register */ + #define REG_USBHS_SR (*(__I uint32_t*)0x40038804U) /**< \brief (USBHS) General Status Register */ + #define REG_USBHS_SCR (*(__O uint32_t*)0x40038808U) /**< \brief (USBHS) General Status Clear Register */ + #define REG_USBHS_SFR (*(__O uint32_t*)0x4003880CU) /**< \brief (USBHS) General Status Set Register */ + #define REG_USBHS_TSTA1 (*(__IO uint32_t*)0x40038810U) /**< \brief (USBHS) General Test A1 Register */ + #define REG_USBHS_TSTA2 (*(__IO uint32_t*)0x40038814U) /**< \brief (USBHS) General Test A2 Register */ + #define REG_USBHS_VERSION (*(__I uint32_t*)0x40038818U) /**< \brief (USBHS) General Version Register */ + #define REG_USBHS_FSM (*(__I uint32_t*)0x4003882CU) /**< \brief (USBHS) General Finite State Machine Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_USBHS_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/utmi.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/utmi.h new file mode 100644 index 000000000..0b4a61ee6 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/utmi.h @@ -0,0 +1,47 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_UTMI_INSTANCE_ +#define _SAME70_UTMI_INSTANCE_ + +/* ========== Register definition for UTMI peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_UTMI_OHCIICR (0x400E0410U) /**< \brief (UTMI) OHCI Interrupt Configuration Register */ + #define REG_UTMI_CKTRIM (0x400E0430U) /**< \brief (UTMI) UTMI Clock Trimming Register */ +#else + #define REG_UTMI_OHCIICR (*(__IO uint32_t*)0x400E0410U) /**< \brief (UTMI) OHCI Interrupt Configuration Register */ + #define REG_UTMI_CKTRIM (*(__IO uint32_t*)0x400E0430U) /**< \brief (UTMI) UTMI Clock Trimming Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_UTMI_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/wdt.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/wdt.h new file mode 100644 index 000000000..d92669caf --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/wdt.h @@ -0,0 +1,49 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_WDT_INSTANCE_ +#define _SAME70_WDT_INSTANCE_ + +/* ========== Register definition for WDT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_WDT_CR (0x400E1850U) /**< \brief (WDT) Control Register */ + #define REG_WDT_MR (0x400E1854U) /**< \brief (WDT) Mode Register */ + #define REG_WDT_SR (0x400E1858U) /**< \brief (WDT) Status Register */ +#else + #define REG_WDT_CR (*(__O uint32_t*)0x400E1850U) /**< \brief (WDT) Control Register */ + #define REG_WDT_MR (*(__IO uint32_t*)0x400E1854U) /**< \brief (WDT) Mode Register */ + #define REG_WDT_SR (*(__I uint32_t*)0x400E1858U) /**< \brief (WDT) Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_WDT_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/xdmac.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/xdmac.h new file mode 100644 index 000000000..535e6bc32 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/instance/xdmac.h @@ -0,0 +1,751 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70_XDMAC_INSTANCE_ +#define _SAME70_XDMAC_INSTANCE_ + +/* ========== Register definition for XDMAC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_XDMAC_GTYPE (0x40078000U) /**< \brief (XDMAC) Global Type Register */ + #define REG_XDMAC_GCFG (0x40078004U) /**< \brief (XDMAC) Global Configuration Register */ + #define REG_XDMAC_GWAC (0x40078008U) /**< \brief (XDMAC) Global Weighted Arbiter Configuration Register */ + #define REG_XDMAC_GIE (0x4007800CU) /**< \brief (XDMAC) Global Interrupt Enable Register */ + #define REG_XDMAC_GID (0x40078010U) /**< \brief (XDMAC) Global Interrupt Disable Register */ + #define REG_XDMAC_GIM (0x40078014U) /**< \brief (XDMAC) Global Interrupt Mask Register */ + #define REG_XDMAC_GIS (0x40078018U) /**< \brief (XDMAC) Global Interrupt Status Register */ + #define REG_XDMAC_GE (0x4007801CU) /**< \brief (XDMAC) Global Channel Enable Register */ + #define REG_XDMAC_GD (0x40078020U) /**< \brief (XDMAC) Global Channel Disable Register */ + #define REG_XDMAC_GS (0x40078024U) /**< \brief (XDMAC) Global Channel Status Register */ + #define REG_XDMAC_GRS (0x40078028U) /**< \brief (XDMAC) Global Channel Read Suspend Register */ + #define REG_XDMAC_GWS (0x4007802CU) /**< \brief (XDMAC) Global Channel Write Suspend Register */ + #define REG_XDMAC_GRWS (0x40078030U) /**< \brief (XDMAC) Global Channel Read Write Suspend Register */ + #define REG_XDMAC_GRWR (0x40078034U) /**< \brief (XDMAC) Global Channel Read Write Resume Register */ + #define REG_XDMAC_GSWR (0x40078038U) /**< \brief (XDMAC) Global Channel Software Request Register */ + #define REG_XDMAC_GSWS (0x4007803CU) /**< \brief (XDMAC) Global Channel Software Request Status Register */ + #define REG_XDMAC_GSWF (0x40078040U) /**< \brief (XDMAC) Global Channel Software Flush Request Register */ + #define REG_XDMAC_CIE0 (0x40078050U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 0) */ + #define REG_XDMAC_CID0 (0x40078054U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 0) */ + #define REG_XDMAC_CIM0 (0x40078058U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 0) */ + #define REG_XDMAC_CIS0 (0x4007805CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 0) */ + #define REG_XDMAC_CSA0 (0x40078060U) /**< \brief (XDMAC) Channel Source Address Register (chid = 0) */ + #define REG_XDMAC_CDA0 (0x40078064U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 0) */ + #define REG_XDMAC_CNDA0 (0x40078068U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 0) */ + #define REG_XDMAC_CNDC0 (0x4007806CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 0) */ + #define REG_XDMAC_CUBC0 (0x40078070U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 0) */ + #define REG_XDMAC_CBC0 (0x40078074U) /**< \brief (XDMAC) Channel Block Control Register (chid = 0) */ + #define REG_XDMAC_CC0 (0x40078078U) /**< \brief (XDMAC) Channel Configuration Register (chid = 0) */ + #define REG_XDMAC_CDS_MSP0 (0x4007807CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) */ + #define REG_XDMAC_CSUS0 (0x40078080U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 0) */ + #define REG_XDMAC_CDUS0 (0x40078084U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 0) */ + #define REG_XDMAC_CIE1 (0x40078090U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 1) */ + #define REG_XDMAC_CID1 (0x40078094U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 1) */ + #define REG_XDMAC_CIM1 (0x40078098U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 1) */ + #define REG_XDMAC_CIS1 (0x4007809CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 1) */ + #define REG_XDMAC_CSA1 (0x400780A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 1) */ + #define REG_XDMAC_CDA1 (0x400780A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 1) */ + #define REG_XDMAC_CNDA1 (0x400780A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 1) */ + #define REG_XDMAC_CNDC1 (0x400780ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 1) */ + #define REG_XDMAC_CUBC1 (0x400780B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 1) */ + #define REG_XDMAC_CBC1 (0x400780B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 1) */ + #define REG_XDMAC_CC1 (0x400780B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 1) */ + #define REG_XDMAC_CDS_MSP1 (0x400780BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 1) */ + #define REG_XDMAC_CSUS1 (0x400780C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 1) */ + #define REG_XDMAC_CDUS1 (0x400780C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 1) */ + #define REG_XDMAC_CIE2 (0x400780D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 2) */ + #define REG_XDMAC_CID2 (0x400780D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 2) */ + #define REG_XDMAC_CIM2 (0x400780D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 2) */ + #define REG_XDMAC_CIS2 (0x400780DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 2) */ + #define REG_XDMAC_CSA2 (0x400780E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 2) */ + #define REG_XDMAC_CDA2 (0x400780E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 2) */ + #define REG_XDMAC_CNDA2 (0x400780E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 2) */ + #define REG_XDMAC_CNDC2 (0x400780ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 2) */ + #define REG_XDMAC_CUBC2 (0x400780F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 2) */ + #define REG_XDMAC_CBC2 (0x400780F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 2) */ + #define REG_XDMAC_CC2 (0x400780F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 2) */ + #define REG_XDMAC_CDS_MSP2 (0x400780FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 2) */ + #define REG_XDMAC_CSUS2 (0x40078100U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 2) */ + #define REG_XDMAC_CDUS2 (0x40078104U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 2) */ + #define REG_XDMAC_CIE3 (0x40078110U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 3) */ + #define REG_XDMAC_CID3 (0x40078114U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 3) */ + #define REG_XDMAC_CIM3 (0x40078118U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 3) */ + #define REG_XDMAC_CIS3 (0x4007811CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 3) */ + #define REG_XDMAC_CSA3 (0x40078120U) /**< \brief (XDMAC) Channel Source Address Register (chid = 3) */ + #define REG_XDMAC_CDA3 (0x40078124U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 3) */ + #define REG_XDMAC_CNDA3 (0x40078128U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 3) */ + #define REG_XDMAC_CNDC3 (0x4007812CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 3) */ + #define REG_XDMAC_CUBC3 (0x40078130U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 3) */ + #define REG_XDMAC_CBC3 (0x40078134U) /**< \brief (XDMAC) Channel Block Control Register (chid = 3) */ + #define REG_XDMAC_CC3 (0x40078138U) /**< \brief (XDMAC) Channel Configuration Register (chid = 3) */ + #define REG_XDMAC_CDS_MSP3 (0x4007813CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 3) */ + #define REG_XDMAC_CSUS3 (0x40078140U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 3) */ + #define REG_XDMAC_CDUS3 (0x40078144U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 3) */ + #define REG_XDMAC_CIE4 (0x40078150U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 4) */ + #define REG_XDMAC_CID4 (0x40078154U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 4) */ + #define REG_XDMAC_CIM4 (0x40078158U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 4) */ + #define REG_XDMAC_CIS4 (0x4007815CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 4) */ + #define REG_XDMAC_CSA4 (0x40078160U) /**< \brief (XDMAC) Channel Source Address Register (chid = 4) */ + #define REG_XDMAC_CDA4 (0x40078164U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 4) */ + #define REG_XDMAC_CNDA4 (0x40078168U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 4) */ + #define REG_XDMAC_CNDC4 (0x4007816CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 4) */ + #define REG_XDMAC_CUBC4 (0x40078170U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 4) */ + #define REG_XDMAC_CBC4 (0x40078174U) /**< \brief (XDMAC) Channel Block Control Register (chid = 4) */ + #define REG_XDMAC_CC4 (0x40078178U) /**< \brief (XDMAC) Channel Configuration Register (chid = 4) */ + #define REG_XDMAC_CDS_MSP4 (0x4007817CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 4) */ + #define REG_XDMAC_CSUS4 (0x40078180U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 4) */ + #define REG_XDMAC_CDUS4 (0x40078184U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 4) */ + #define REG_XDMAC_CIE5 (0x40078190U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 5) */ + #define REG_XDMAC_CID5 (0x40078194U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 5) */ + #define REG_XDMAC_CIM5 (0x40078198U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 5) */ + #define REG_XDMAC_CIS5 (0x4007819CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 5) */ + #define REG_XDMAC_CSA5 (0x400781A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 5) */ + #define REG_XDMAC_CDA5 (0x400781A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 5) */ + #define REG_XDMAC_CNDA5 (0x400781A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 5) */ + #define REG_XDMAC_CNDC5 (0x400781ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 5) */ + #define REG_XDMAC_CUBC5 (0x400781B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 5) */ + #define REG_XDMAC_CBC5 (0x400781B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 5) */ + #define REG_XDMAC_CC5 (0x400781B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 5) */ + #define REG_XDMAC_CDS_MSP5 (0x400781BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 5) */ + #define REG_XDMAC_CSUS5 (0x400781C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 5) */ + #define REG_XDMAC_CDUS5 (0x400781C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 5) */ + #define REG_XDMAC_CIE6 (0x400781D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 6) */ + #define REG_XDMAC_CID6 (0x400781D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 6) */ + #define REG_XDMAC_CIM6 (0x400781D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 6) */ + #define REG_XDMAC_CIS6 (0x400781DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 6) */ + #define REG_XDMAC_CSA6 (0x400781E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 6) */ + #define REG_XDMAC_CDA6 (0x400781E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 6) */ + #define REG_XDMAC_CNDA6 (0x400781E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 6) */ + #define REG_XDMAC_CNDC6 (0x400781ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 6) */ + #define REG_XDMAC_CUBC6 (0x400781F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 6) */ + #define REG_XDMAC_CBC6 (0x400781F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 6) */ + #define REG_XDMAC_CC6 (0x400781F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 6) */ + #define REG_XDMAC_CDS_MSP6 (0x400781FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 6) */ + #define REG_XDMAC_CSUS6 (0x40078200U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 6) */ + #define REG_XDMAC_CDUS6 (0x40078204U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 6) */ + #define REG_XDMAC_CIE7 (0x40078210U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 7) */ + #define REG_XDMAC_CID7 (0x40078214U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 7) */ + #define REG_XDMAC_CIM7 (0x40078218U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 7) */ + #define REG_XDMAC_CIS7 (0x4007821CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 7) */ + #define REG_XDMAC_CSA7 (0x40078220U) /**< \brief (XDMAC) Channel Source Address Register (chid = 7) */ + #define REG_XDMAC_CDA7 (0x40078224U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 7) */ + #define REG_XDMAC_CNDA7 (0x40078228U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 7) */ + #define REG_XDMAC_CNDC7 (0x4007822CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 7) */ + #define REG_XDMAC_CUBC7 (0x40078230U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 7) */ + #define REG_XDMAC_CBC7 (0x40078234U) /**< \brief (XDMAC) Channel Block Control Register (chid = 7) */ + #define REG_XDMAC_CC7 (0x40078238U) /**< \brief (XDMAC) Channel Configuration Register (chid = 7) */ + #define REG_XDMAC_CDS_MSP7 (0x4007823CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 7) */ + #define REG_XDMAC_CSUS7 (0x40078240U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 7) */ + #define REG_XDMAC_CDUS7 (0x40078244U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 7) */ + #define REG_XDMAC_CIE8 (0x40078250U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 8) */ + #define REG_XDMAC_CID8 (0x40078254U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 8) */ + #define REG_XDMAC_CIM8 (0x40078258U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 8) */ + #define REG_XDMAC_CIS8 (0x4007825CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 8) */ + #define REG_XDMAC_CSA8 (0x40078260U) /**< \brief (XDMAC) Channel Source Address Register (chid = 8) */ + #define REG_XDMAC_CDA8 (0x40078264U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 8) */ + #define REG_XDMAC_CNDA8 (0x40078268U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 8) */ + #define REG_XDMAC_CNDC8 (0x4007826CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 8) */ + #define REG_XDMAC_CUBC8 (0x40078270U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 8) */ + #define REG_XDMAC_CBC8 (0x40078274U) /**< \brief (XDMAC) Channel Block Control Register (chid = 8) */ + #define REG_XDMAC_CC8 (0x40078278U) /**< \brief (XDMAC) Channel Configuration Register (chid = 8) */ + #define REG_XDMAC_CDS_MSP8 (0x4007827CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 8) */ + #define REG_XDMAC_CSUS8 (0x40078280U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 8) */ + #define REG_XDMAC_CDUS8 (0x40078284U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 8) */ + #define REG_XDMAC_CIE9 (0x40078290U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 9) */ + #define REG_XDMAC_CID9 (0x40078294U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 9) */ + #define REG_XDMAC_CIM9 (0x40078298U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 9) */ + #define REG_XDMAC_CIS9 (0x4007829CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 9) */ + #define REG_XDMAC_CSA9 (0x400782A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 9) */ + #define REG_XDMAC_CDA9 (0x400782A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 9) */ + #define REG_XDMAC_CNDA9 (0x400782A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 9) */ + #define REG_XDMAC_CNDC9 (0x400782ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 9) */ + #define REG_XDMAC_CUBC9 (0x400782B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 9) */ + #define REG_XDMAC_CBC9 (0x400782B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 9) */ + #define REG_XDMAC_CC9 (0x400782B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 9) */ + #define REG_XDMAC_CDS_MSP9 (0x400782BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 9) */ + #define REG_XDMAC_CSUS9 (0x400782C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 9) */ + #define REG_XDMAC_CDUS9 (0x400782C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 9) */ + #define REG_XDMAC_CIE10 (0x400782D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 10) */ + #define REG_XDMAC_CID10 (0x400782D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 10) */ + #define REG_XDMAC_CIM10 (0x400782D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 10) */ + #define REG_XDMAC_CIS10 (0x400782DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 10) */ + #define REG_XDMAC_CSA10 (0x400782E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 10) */ + #define REG_XDMAC_CDA10 (0x400782E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 10) */ + #define REG_XDMAC_CNDA10 (0x400782E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 10) */ + #define REG_XDMAC_CNDC10 (0x400782ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 10) */ + #define REG_XDMAC_CUBC10 (0x400782F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 10) */ + #define REG_XDMAC_CBC10 (0x400782F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 10) */ + #define REG_XDMAC_CC10 (0x400782F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 10) */ + #define REG_XDMAC_CDS_MSP10 (0x400782FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 10) */ + #define REG_XDMAC_CSUS10 (0x40078300U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 10) */ + #define REG_XDMAC_CDUS10 (0x40078304U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 10) */ + #define REG_XDMAC_CIE11 (0x40078310U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 11) */ + #define REG_XDMAC_CID11 (0x40078314U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 11) */ + #define REG_XDMAC_CIM11 (0x40078318U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 11) */ + #define REG_XDMAC_CIS11 (0x4007831CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 11) */ + #define REG_XDMAC_CSA11 (0x40078320U) /**< \brief (XDMAC) Channel Source Address Register (chid = 11) */ + #define REG_XDMAC_CDA11 (0x40078324U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 11) */ + #define REG_XDMAC_CNDA11 (0x40078328U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 11) */ + #define REG_XDMAC_CNDC11 (0x4007832CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 11) */ + #define REG_XDMAC_CUBC11 (0x40078330U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 11) */ + #define REG_XDMAC_CBC11 (0x40078334U) /**< \brief (XDMAC) Channel Block Control Register (chid = 11) */ + #define REG_XDMAC_CC11 (0x40078338U) /**< \brief (XDMAC) Channel Configuration Register (chid = 11) */ + #define REG_XDMAC_CDS_MSP11 (0x4007833CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 11) */ + #define REG_XDMAC_CSUS11 (0x40078340U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 11) */ + #define REG_XDMAC_CDUS11 (0x40078344U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 11) */ + #define REG_XDMAC_CIE12 (0x40078350U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 12) */ + #define REG_XDMAC_CID12 (0x40078354U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 12) */ + #define REG_XDMAC_CIM12 (0x40078358U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 12) */ + #define REG_XDMAC_CIS12 (0x4007835CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 12) */ + #define REG_XDMAC_CSA12 (0x40078360U) /**< \brief (XDMAC) Channel Source Address Register (chid = 12) */ + #define REG_XDMAC_CDA12 (0x40078364U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 12) */ + #define REG_XDMAC_CNDA12 (0x40078368U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 12) */ + #define REG_XDMAC_CNDC12 (0x4007836CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 12) */ + #define REG_XDMAC_CUBC12 (0x40078370U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 12) */ + #define REG_XDMAC_CBC12 (0x40078374U) /**< \brief (XDMAC) Channel Block Control Register (chid = 12) */ + #define REG_XDMAC_CC12 (0x40078378U) /**< \brief (XDMAC) Channel Configuration Register (chid = 12) */ + #define REG_XDMAC_CDS_MSP12 (0x4007837CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 12) */ + #define REG_XDMAC_CSUS12 (0x40078380U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 12) */ + #define REG_XDMAC_CDUS12 (0x40078384U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 12) */ + #define REG_XDMAC_CIE13 (0x40078390U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 13) */ + #define REG_XDMAC_CID13 (0x40078394U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 13) */ + #define REG_XDMAC_CIM13 (0x40078398U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 13) */ + #define REG_XDMAC_CIS13 (0x4007839CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 13) */ + #define REG_XDMAC_CSA13 (0x400783A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 13) */ + #define REG_XDMAC_CDA13 (0x400783A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 13) */ + #define REG_XDMAC_CNDA13 (0x400783A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 13) */ + #define REG_XDMAC_CNDC13 (0x400783ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 13) */ + #define REG_XDMAC_CUBC13 (0x400783B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 13) */ + #define REG_XDMAC_CBC13 (0x400783B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 13) */ + #define REG_XDMAC_CC13 (0x400783B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 13) */ + #define REG_XDMAC_CDS_MSP13 (0x400783BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 13) */ + #define REG_XDMAC_CSUS13 (0x400783C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 13) */ + #define REG_XDMAC_CDUS13 (0x400783C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 13) */ + #define REG_XDMAC_CIE14 (0x400783D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 14) */ + #define REG_XDMAC_CID14 (0x400783D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 14) */ + #define REG_XDMAC_CIM14 (0x400783D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 14) */ + #define REG_XDMAC_CIS14 (0x400783DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 14) */ + #define REG_XDMAC_CSA14 (0x400783E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 14) */ + #define REG_XDMAC_CDA14 (0x400783E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 14) */ + #define REG_XDMAC_CNDA14 (0x400783E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 14) */ + #define REG_XDMAC_CNDC14 (0x400783ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 14) */ + #define REG_XDMAC_CUBC14 (0x400783F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 14) */ + #define REG_XDMAC_CBC14 (0x400783F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 14) */ + #define REG_XDMAC_CC14 (0x400783F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 14) */ + #define REG_XDMAC_CDS_MSP14 (0x400783FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 14) */ + #define REG_XDMAC_CSUS14 (0x40078400U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 14) */ + #define REG_XDMAC_CDUS14 (0x40078404U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 14) */ + #define REG_XDMAC_CIE15 (0x40078410U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 15) */ + #define REG_XDMAC_CID15 (0x40078414U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 15) */ + #define REG_XDMAC_CIM15 (0x40078418U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 15) */ + #define REG_XDMAC_CIS15 (0x4007841CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 15) */ + #define REG_XDMAC_CSA15 (0x40078420U) /**< \brief (XDMAC) Channel Source Address Register (chid = 15) */ + #define REG_XDMAC_CDA15 (0x40078424U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 15) */ + #define REG_XDMAC_CNDA15 (0x40078428U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 15) */ + #define REG_XDMAC_CNDC15 (0x4007842CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 15) */ + #define REG_XDMAC_CUBC15 (0x40078430U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 15) */ + #define REG_XDMAC_CBC15 (0x40078434U) /**< \brief (XDMAC) Channel Block Control Register (chid = 15) */ + #define REG_XDMAC_CC15 (0x40078438U) /**< \brief (XDMAC) Channel Configuration Register (chid = 15) */ + #define REG_XDMAC_CDS_MSP15 (0x4007843CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 15) */ + #define REG_XDMAC_CSUS15 (0x40078440U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 15) */ + #define REG_XDMAC_CDUS15 (0x40078444U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 15) */ + #define REG_XDMAC_CIE16 (0x40078450U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 16) */ + #define REG_XDMAC_CID16 (0x40078454U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 16) */ + #define REG_XDMAC_CIM16 (0x40078458U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 16) */ + #define REG_XDMAC_CIS16 (0x4007845CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 16) */ + #define REG_XDMAC_CSA16 (0x40078460U) /**< \brief (XDMAC) Channel Source Address Register (chid = 16) */ + #define REG_XDMAC_CDA16 (0x40078464U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 16) */ + #define REG_XDMAC_CNDA16 (0x40078468U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 16) */ + #define REG_XDMAC_CNDC16 (0x4007846CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 16) */ + #define REG_XDMAC_CUBC16 (0x40078470U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 16) */ + #define REG_XDMAC_CBC16 (0x40078474U) /**< \brief (XDMAC) Channel Block Control Register (chid = 16) */ + #define REG_XDMAC_CC16 (0x40078478U) /**< \brief (XDMAC) Channel Configuration Register (chid = 16) */ + #define REG_XDMAC_CDS_MSP16 (0x4007847CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 16) */ + #define REG_XDMAC_CSUS16 (0x40078480U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 16) */ + #define REG_XDMAC_CDUS16 (0x40078484U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 16) */ + #define REG_XDMAC_CIE17 (0x40078490U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 17) */ + #define REG_XDMAC_CID17 (0x40078494U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 17) */ + #define REG_XDMAC_CIM17 (0x40078498U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 17) */ + #define REG_XDMAC_CIS17 (0x4007849CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 17) */ + #define REG_XDMAC_CSA17 (0x400784A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 17) */ + #define REG_XDMAC_CDA17 (0x400784A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 17) */ + #define REG_XDMAC_CNDA17 (0x400784A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 17) */ + #define REG_XDMAC_CNDC17 (0x400784ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 17) */ + #define REG_XDMAC_CUBC17 (0x400784B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 17) */ + #define REG_XDMAC_CBC17 (0x400784B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 17) */ + #define REG_XDMAC_CC17 (0x400784B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 17) */ + #define REG_XDMAC_CDS_MSP17 (0x400784BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 17) */ + #define REG_XDMAC_CSUS17 (0x400784C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 17) */ + #define REG_XDMAC_CDUS17 (0x400784C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 17) */ + #define REG_XDMAC_CIE18 (0x400784D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 18) */ + #define REG_XDMAC_CID18 (0x400784D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 18) */ + #define REG_XDMAC_CIM18 (0x400784D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 18) */ + #define REG_XDMAC_CIS18 (0x400784DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 18) */ + #define REG_XDMAC_CSA18 (0x400784E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 18) */ + #define REG_XDMAC_CDA18 (0x400784E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 18) */ + #define REG_XDMAC_CNDA18 (0x400784E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 18) */ + #define REG_XDMAC_CNDC18 (0x400784ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 18) */ + #define REG_XDMAC_CUBC18 (0x400784F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 18) */ + #define REG_XDMAC_CBC18 (0x400784F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 18) */ + #define REG_XDMAC_CC18 (0x400784F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 18) */ + #define REG_XDMAC_CDS_MSP18 (0x400784FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 18) */ + #define REG_XDMAC_CSUS18 (0x40078500U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 18) */ + #define REG_XDMAC_CDUS18 (0x40078504U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 18) */ + #define REG_XDMAC_CIE19 (0x40078510U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 19) */ + #define REG_XDMAC_CID19 (0x40078514U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 19) */ + #define REG_XDMAC_CIM19 (0x40078518U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 19) */ + #define REG_XDMAC_CIS19 (0x4007851CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 19) */ + #define REG_XDMAC_CSA19 (0x40078520U) /**< \brief (XDMAC) Channel Source Address Register (chid = 19) */ + #define REG_XDMAC_CDA19 (0x40078524U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 19) */ + #define REG_XDMAC_CNDA19 (0x40078528U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 19) */ + #define REG_XDMAC_CNDC19 (0x4007852CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 19) */ + #define REG_XDMAC_CUBC19 (0x40078530U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 19) */ + #define REG_XDMAC_CBC19 (0x40078534U) /**< \brief (XDMAC) Channel Block Control Register (chid = 19) */ + #define REG_XDMAC_CC19 (0x40078538U) /**< \brief (XDMAC) Channel Configuration Register (chid = 19) */ + #define REG_XDMAC_CDS_MSP19 (0x4007853CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 19) */ + #define REG_XDMAC_CSUS19 (0x40078540U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 19) */ + #define REG_XDMAC_CDUS19 (0x40078544U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 19) */ + #define REG_XDMAC_CIE20 (0x40078550U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 20) */ + #define REG_XDMAC_CID20 (0x40078554U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 20) */ + #define REG_XDMAC_CIM20 (0x40078558U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 20) */ + #define REG_XDMAC_CIS20 (0x4007855CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 20) */ + #define REG_XDMAC_CSA20 (0x40078560U) /**< \brief (XDMAC) Channel Source Address Register (chid = 20) */ + #define REG_XDMAC_CDA20 (0x40078564U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 20) */ + #define REG_XDMAC_CNDA20 (0x40078568U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 20) */ + #define REG_XDMAC_CNDC20 (0x4007856CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 20) */ + #define REG_XDMAC_CUBC20 (0x40078570U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 20) */ + #define REG_XDMAC_CBC20 (0x40078574U) /**< \brief (XDMAC) Channel Block Control Register (chid = 20) */ + #define REG_XDMAC_CC20 (0x40078578U) /**< \brief (XDMAC) Channel Configuration Register (chid = 20) */ + #define REG_XDMAC_CDS_MSP20 (0x4007857CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 20) */ + #define REG_XDMAC_CSUS20 (0x40078580U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 20) */ + #define REG_XDMAC_CDUS20 (0x40078584U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 20) */ + #define REG_XDMAC_CIE21 (0x40078590U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 21) */ + #define REG_XDMAC_CID21 (0x40078594U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 21) */ + #define REG_XDMAC_CIM21 (0x40078598U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 21) */ + #define REG_XDMAC_CIS21 (0x4007859CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 21) */ + #define REG_XDMAC_CSA21 (0x400785A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 21) */ + #define REG_XDMAC_CDA21 (0x400785A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 21) */ + #define REG_XDMAC_CNDA21 (0x400785A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 21) */ + #define REG_XDMAC_CNDC21 (0x400785ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 21) */ + #define REG_XDMAC_CUBC21 (0x400785B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 21) */ + #define REG_XDMAC_CBC21 (0x400785B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 21) */ + #define REG_XDMAC_CC21 (0x400785B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 21) */ + #define REG_XDMAC_CDS_MSP21 (0x400785BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 21) */ + #define REG_XDMAC_CSUS21 (0x400785C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 21) */ + #define REG_XDMAC_CDUS21 (0x400785C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 21) */ + #define REG_XDMAC_CIE22 (0x400785D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 22) */ + #define REG_XDMAC_CID22 (0x400785D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 22) */ + #define REG_XDMAC_CIM22 (0x400785D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 22) */ + #define REG_XDMAC_CIS22 (0x400785DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 22) */ + #define REG_XDMAC_CSA22 (0x400785E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 22) */ + #define REG_XDMAC_CDA22 (0x400785E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 22) */ + #define REG_XDMAC_CNDA22 (0x400785E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 22) */ + #define REG_XDMAC_CNDC22 (0x400785ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 22) */ + #define REG_XDMAC_CUBC22 (0x400785F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 22) */ + #define REG_XDMAC_CBC22 (0x400785F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 22) */ + #define REG_XDMAC_CC22 (0x400785F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 22) */ + #define REG_XDMAC_CDS_MSP22 (0x400785FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 22) */ + #define REG_XDMAC_CSUS22 (0x40078600U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 22) */ + #define REG_XDMAC_CDUS22 (0x40078604U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 22) */ + #define REG_XDMAC_CIE23 (0x40078610U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 23) */ + #define REG_XDMAC_CID23 (0x40078614U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 23) */ + #define REG_XDMAC_CIM23 (0x40078618U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 23) */ + #define REG_XDMAC_CIS23 (0x4007861CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 23) */ + #define REG_XDMAC_CSA23 (0x40078620U) /**< \brief (XDMAC) Channel Source Address Register (chid = 23) */ + #define REG_XDMAC_CDA23 (0x40078624U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 23) */ + #define REG_XDMAC_CNDA23 (0x40078628U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 23) */ + #define REG_XDMAC_CNDC23 (0x4007862CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 23) */ + #define REG_XDMAC_CUBC23 (0x40078630U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 23) */ + #define REG_XDMAC_CBC23 (0x40078634U) /**< \brief (XDMAC) Channel Block Control Register (chid = 23) */ + #define REG_XDMAC_CC23 (0x40078638U) /**< \brief (XDMAC) Channel Configuration Register (chid = 23) */ + #define REG_XDMAC_CDS_MSP23 (0x4007863CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 23) */ + #define REG_XDMAC_CSUS23 (0x40078640U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 23) */ + #define REG_XDMAC_CDUS23 (0x40078644U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 23) */ + #define REG_XDMAC_VERSION (0x40078FFCU) /**< \brief (XDMAC) XDMAC Version Register */ +#else + #define REG_XDMAC_GTYPE (*(__I uint32_t*)0x40078000U) /**< \brief (XDMAC) Global Type Register */ + #define REG_XDMAC_GCFG (*(__IO uint32_t*)0x40078004U) /**< \brief (XDMAC) Global Configuration Register */ + #define REG_XDMAC_GWAC (*(__I uint32_t*)0x40078008U) /**< \brief (XDMAC) Global Weighted Arbiter Configuration Register */ + #define REG_XDMAC_GIE (*(__O uint32_t*)0x4007800CU) /**< \brief (XDMAC) Global Interrupt Enable Register */ + #define REG_XDMAC_GID (*(__O uint32_t*)0x40078010U) /**< \brief (XDMAC) Global Interrupt Disable Register */ + #define REG_XDMAC_GIM (*(__I uint32_t*)0x40078014U) /**< \brief (XDMAC) Global Interrupt Mask Register */ + #define REG_XDMAC_GIS (*(__I uint32_t*)0x40078018U) /**< \brief (XDMAC) Global Interrupt Status Register */ + #define REG_XDMAC_GE (*(__O uint32_t*)0x4007801CU) /**< \brief (XDMAC) Global Channel Enable Register */ + #define REG_XDMAC_GD (*(__O uint32_t*)0x40078020U) /**< \brief (XDMAC) Global Channel Disable Register */ + #define REG_XDMAC_GS (*(__I uint32_t*)0x40078024U) /**< \brief (XDMAC) Global Channel Status Register */ + #define REG_XDMAC_GRS (*(__IO uint32_t*)0x40078028U) /**< \brief (XDMAC) Global Channel Read Suspend Register */ + #define REG_XDMAC_GWS (*(__IO uint32_t*)0x4007802CU) /**< \brief (XDMAC) Global Channel Write Suspend Register */ + #define REG_XDMAC_GRWS (*(__O uint32_t*)0x40078030U) /**< \brief (XDMAC) Global Channel Read Write Suspend Register */ + #define REG_XDMAC_GRWR (*(__O uint32_t*)0x40078034U) /**< \brief (XDMAC) Global Channel Read Write Resume Register */ + #define REG_XDMAC_GSWR (*(__O uint32_t*)0x40078038U) /**< \brief (XDMAC) Global Channel Software Request Register */ + #define REG_XDMAC_GSWS (*(__I uint32_t*)0x4007803CU) /**< \brief (XDMAC) Global Channel Software Request Status Register */ + #define REG_XDMAC_GSWF (*(__O uint32_t*)0x40078040U) /**< \brief (XDMAC) Global Channel Software Flush Request Register */ + #define REG_XDMAC_CIE0 (*(__O uint32_t*)0x40078050U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 0) */ + #define REG_XDMAC_CID0 (*(__O uint32_t*)0x40078054U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 0) */ + #define REG_XDMAC_CIM0 (*(__I uint32_t*)0x40078058U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 0) */ + #define REG_XDMAC_CIS0 (*(__I uint32_t*)0x4007805CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 0) */ + #define REG_XDMAC_CSA0 (*(__IO uint32_t*)0x40078060U) /**< \brief (XDMAC) Channel Source Address Register (chid = 0) */ + #define REG_XDMAC_CDA0 (*(__IO uint32_t*)0x40078064U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 0) */ + #define REG_XDMAC_CNDA0 (*(__IO uint32_t*)0x40078068U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 0) */ + #define REG_XDMAC_CNDC0 (*(__IO uint32_t*)0x4007806CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 0) */ + #define REG_XDMAC_CUBC0 (*(__IO uint32_t*)0x40078070U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 0) */ + #define REG_XDMAC_CBC0 (*(__IO uint32_t*)0x40078074U) /**< \brief (XDMAC) Channel Block Control Register (chid = 0) */ + #define REG_XDMAC_CC0 (*(__IO uint32_t*)0x40078078U) /**< \brief (XDMAC) Channel Configuration Register (chid = 0) */ + #define REG_XDMAC_CDS_MSP0 (*(__IO uint32_t*)0x4007807CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) */ + #define REG_XDMAC_CSUS0 (*(__IO uint32_t*)0x40078080U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 0) */ + #define REG_XDMAC_CDUS0 (*(__IO uint32_t*)0x40078084U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 0) */ + #define REG_XDMAC_CIE1 (*(__O uint32_t*)0x40078090U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 1) */ + #define REG_XDMAC_CID1 (*(__O uint32_t*)0x40078094U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 1) */ + #define REG_XDMAC_CIM1 (*(__I uint32_t*)0x40078098U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 1) */ + #define REG_XDMAC_CIS1 (*(__I uint32_t*)0x4007809CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 1) */ + #define REG_XDMAC_CSA1 (*(__IO uint32_t*)0x400780A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 1) */ + #define REG_XDMAC_CDA1 (*(__IO uint32_t*)0x400780A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 1) */ + #define REG_XDMAC_CNDA1 (*(__IO uint32_t*)0x400780A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 1) */ + #define REG_XDMAC_CNDC1 (*(__IO uint32_t*)0x400780ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 1) */ + #define REG_XDMAC_CUBC1 (*(__IO uint32_t*)0x400780B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 1) */ + #define REG_XDMAC_CBC1 (*(__IO uint32_t*)0x400780B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 1) */ + #define REG_XDMAC_CC1 (*(__IO uint32_t*)0x400780B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 1) */ + #define REG_XDMAC_CDS_MSP1 (*(__IO uint32_t*)0x400780BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 1) */ + #define REG_XDMAC_CSUS1 (*(__IO uint32_t*)0x400780C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 1) */ + #define REG_XDMAC_CDUS1 (*(__IO uint32_t*)0x400780C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 1) */ + #define REG_XDMAC_CIE2 (*(__O uint32_t*)0x400780D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 2) */ + #define REG_XDMAC_CID2 (*(__O uint32_t*)0x400780D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 2) */ + #define REG_XDMAC_CIM2 (*(__I uint32_t*)0x400780D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 2) */ + #define REG_XDMAC_CIS2 (*(__I uint32_t*)0x400780DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 2) */ + #define REG_XDMAC_CSA2 (*(__IO uint32_t*)0x400780E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 2) */ + #define REG_XDMAC_CDA2 (*(__IO uint32_t*)0x400780E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 2) */ + #define REG_XDMAC_CNDA2 (*(__IO uint32_t*)0x400780E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 2) */ + #define REG_XDMAC_CNDC2 (*(__IO uint32_t*)0x400780ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 2) */ + #define REG_XDMAC_CUBC2 (*(__IO uint32_t*)0x400780F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 2) */ + #define REG_XDMAC_CBC2 (*(__IO uint32_t*)0x400780F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 2) */ + #define REG_XDMAC_CC2 (*(__IO uint32_t*)0x400780F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 2) */ + #define REG_XDMAC_CDS_MSP2 (*(__IO uint32_t*)0x400780FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 2) */ + #define REG_XDMAC_CSUS2 (*(__IO uint32_t*)0x40078100U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 2) */ + #define REG_XDMAC_CDUS2 (*(__IO uint32_t*)0x40078104U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 2) */ + #define REG_XDMAC_CIE3 (*(__O uint32_t*)0x40078110U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 3) */ + #define REG_XDMAC_CID3 (*(__O uint32_t*)0x40078114U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 3) */ + #define REG_XDMAC_CIM3 (*(__I uint32_t*)0x40078118U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 3) */ + #define REG_XDMAC_CIS3 (*(__I uint32_t*)0x4007811CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 3) */ + #define REG_XDMAC_CSA3 (*(__IO uint32_t*)0x40078120U) /**< \brief (XDMAC) Channel Source Address Register (chid = 3) */ + #define REG_XDMAC_CDA3 (*(__IO uint32_t*)0x40078124U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 3) */ + #define REG_XDMAC_CNDA3 (*(__IO uint32_t*)0x40078128U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 3) */ + #define REG_XDMAC_CNDC3 (*(__IO uint32_t*)0x4007812CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 3) */ + #define REG_XDMAC_CUBC3 (*(__IO uint32_t*)0x40078130U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 3) */ + #define REG_XDMAC_CBC3 (*(__IO uint32_t*)0x40078134U) /**< \brief (XDMAC) Channel Block Control Register (chid = 3) */ + #define REG_XDMAC_CC3 (*(__IO uint32_t*)0x40078138U) /**< \brief (XDMAC) Channel Configuration Register (chid = 3) */ + #define REG_XDMAC_CDS_MSP3 (*(__IO uint32_t*)0x4007813CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 3) */ + #define REG_XDMAC_CSUS3 (*(__IO uint32_t*)0x40078140U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 3) */ + #define REG_XDMAC_CDUS3 (*(__IO uint32_t*)0x40078144U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 3) */ + #define REG_XDMAC_CIE4 (*(__O uint32_t*)0x40078150U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 4) */ + #define REG_XDMAC_CID4 (*(__O uint32_t*)0x40078154U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 4) */ + #define REG_XDMAC_CIM4 (*(__I uint32_t*)0x40078158U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 4) */ + #define REG_XDMAC_CIS4 (*(__I uint32_t*)0x4007815CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 4) */ + #define REG_XDMAC_CSA4 (*(__IO uint32_t*)0x40078160U) /**< \brief (XDMAC) Channel Source Address Register (chid = 4) */ + #define REG_XDMAC_CDA4 (*(__IO uint32_t*)0x40078164U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 4) */ + #define REG_XDMAC_CNDA4 (*(__IO uint32_t*)0x40078168U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 4) */ + #define REG_XDMAC_CNDC4 (*(__IO uint32_t*)0x4007816CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 4) */ + #define REG_XDMAC_CUBC4 (*(__IO uint32_t*)0x40078170U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 4) */ + #define REG_XDMAC_CBC4 (*(__IO uint32_t*)0x40078174U) /**< \brief (XDMAC) Channel Block Control Register (chid = 4) */ + #define REG_XDMAC_CC4 (*(__IO uint32_t*)0x40078178U) /**< \brief (XDMAC) Channel Configuration Register (chid = 4) */ + #define REG_XDMAC_CDS_MSP4 (*(__IO uint32_t*)0x4007817CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 4) */ + #define REG_XDMAC_CSUS4 (*(__IO uint32_t*)0x40078180U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 4) */ + #define REG_XDMAC_CDUS4 (*(__IO uint32_t*)0x40078184U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 4) */ + #define REG_XDMAC_CIE5 (*(__O uint32_t*)0x40078190U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 5) */ + #define REG_XDMAC_CID5 (*(__O uint32_t*)0x40078194U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 5) */ + #define REG_XDMAC_CIM5 (*(__I uint32_t*)0x40078198U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 5) */ + #define REG_XDMAC_CIS5 (*(__I uint32_t*)0x4007819CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 5) */ + #define REG_XDMAC_CSA5 (*(__IO uint32_t*)0x400781A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 5) */ + #define REG_XDMAC_CDA5 (*(__IO uint32_t*)0x400781A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 5) */ + #define REG_XDMAC_CNDA5 (*(__IO uint32_t*)0x400781A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 5) */ + #define REG_XDMAC_CNDC5 (*(__IO uint32_t*)0x400781ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 5) */ + #define REG_XDMAC_CUBC5 (*(__IO uint32_t*)0x400781B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 5) */ + #define REG_XDMAC_CBC5 (*(__IO uint32_t*)0x400781B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 5) */ + #define REG_XDMAC_CC5 (*(__IO uint32_t*)0x400781B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 5) */ + #define REG_XDMAC_CDS_MSP5 (*(__IO uint32_t*)0x400781BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 5) */ + #define REG_XDMAC_CSUS5 (*(__IO uint32_t*)0x400781C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 5) */ + #define REG_XDMAC_CDUS5 (*(__IO uint32_t*)0x400781C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 5) */ + #define REG_XDMAC_CIE6 (*(__O uint32_t*)0x400781D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 6) */ + #define REG_XDMAC_CID6 (*(__O uint32_t*)0x400781D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 6) */ + #define REG_XDMAC_CIM6 (*(__I uint32_t*)0x400781D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 6) */ + #define REG_XDMAC_CIS6 (*(__I uint32_t*)0x400781DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 6) */ + #define REG_XDMAC_CSA6 (*(__IO uint32_t*)0x400781E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 6) */ + #define REG_XDMAC_CDA6 (*(__IO uint32_t*)0x400781E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 6) */ + #define REG_XDMAC_CNDA6 (*(__IO uint32_t*)0x400781E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 6) */ + #define REG_XDMAC_CNDC6 (*(__IO uint32_t*)0x400781ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 6) */ + #define REG_XDMAC_CUBC6 (*(__IO uint32_t*)0x400781F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 6) */ + #define REG_XDMAC_CBC6 (*(__IO uint32_t*)0x400781F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 6) */ + #define REG_XDMAC_CC6 (*(__IO uint32_t*)0x400781F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 6) */ + #define REG_XDMAC_CDS_MSP6 (*(__IO uint32_t*)0x400781FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 6) */ + #define REG_XDMAC_CSUS6 (*(__IO uint32_t*)0x40078200U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 6) */ + #define REG_XDMAC_CDUS6 (*(__IO uint32_t*)0x40078204U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 6) */ + #define REG_XDMAC_CIE7 (*(__O uint32_t*)0x40078210U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 7) */ + #define REG_XDMAC_CID7 (*(__O uint32_t*)0x40078214U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 7) */ + #define REG_XDMAC_CIM7 (*(__I uint32_t*)0x40078218U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 7) */ + #define REG_XDMAC_CIS7 (*(__I uint32_t*)0x4007821CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 7) */ + #define REG_XDMAC_CSA7 (*(__IO uint32_t*)0x40078220U) /**< \brief (XDMAC) Channel Source Address Register (chid = 7) */ + #define REG_XDMAC_CDA7 (*(__IO uint32_t*)0x40078224U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 7) */ + #define REG_XDMAC_CNDA7 (*(__IO uint32_t*)0x40078228U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 7) */ + #define REG_XDMAC_CNDC7 (*(__IO uint32_t*)0x4007822CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 7) */ + #define REG_XDMAC_CUBC7 (*(__IO uint32_t*)0x40078230U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 7) */ + #define REG_XDMAC_CBC7 (*(__IO uint32_t*)0x40078234U) /**< \brief (XDMAC) Channel Block Control Register (chid = 7) */ + #define REG_XDMAC_CC7 (*(__IO uint32_t*)0x40078238U) /**< \brief (XDMAC) Channel Configuration Register (chid = 7) */ + #define REG_XDMAC_CDS_MSP7 (*(__IO uint32_t*)0x4007823CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 7) */ + #define REG_XDMAC_CSUS7 (*(__IO uint32_t*)0x40078240U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 7) */ + #define REG_XDMAC_CDUS7 (*(__IO uint32_t*)0x40078244U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 7) */ + #define REG_XDMAC_CIE8 (*(__O uint32_t*)0x40078250U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 8) */ + #define REG_XDMAC_CID8 (*(__O uint32_t*)0x40078254U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 8) */ + #define REG_XDMAC_CIM8 (*(__I uint32_t*)0x40078258U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 8) */ + #define REG_XDMAC_CIS8 (*(__I uint32_t*)0x4007825CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 8) */ + #define REG_XDMAC_CSA8 (*(__IO uint32_t*)0x40078260U) /**< \brief (XDMAC) Channel Source Address Register (chid = 8) */ + #define REG_XDMAC_CDA8 (*(__IO uint32_t*)0x40078264U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 8) */ + #define REG_XDMAC_CNDA8 (*(__IO uint32_t*)0x40078268U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 8) */ + #define REG_XDMAC_CNDC8 (*(__IO uint32_t*)0x4007826CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 8) */ + #define REG_XDMAC_CUBC8 (*(__IO uint32_t*)0x40078270U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 8) */ + #define REG_XDMAC_CBC8 (*(__IO uint32_t*)0x40078274U) /**< \brief (XDMAC) Channel Block Control Register (chid = 8) */ + #define REG_XDMAC_CC8 (*(__IO uint32_t*)0x40078278U) /**< \brief (XDMAC) Channel Configuration Register (chid = 8) */ + #define REG_XDMAC_CDS_MSP8 (*(__IO uint32_t*)0x4007827CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 8) */ + #define REG_XDMAC_CSUS8 (*(__IO uint32_t*)0x40078280U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 8) */ + #define REG_XDMAC_CDUS8 (*(__IO uint32_t*)0x40078284U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 8) */ + #define REG_XDMAC_CIE9 (*(__O uint32_t*)0x40078290U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 9) */ + #define REG_XDMAC_CID9 (*(__O uint32_t*)0x40078294U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 9) */ + #define REG_XDMAC_CIM9 (*(__I uint32_t*)0x40078298U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 9) */ + #define REG_XDMAC_CIS9 (*(__I uint32_t*)0x4007829CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 9) */ + #define REG_XDMAC_CSA9 (*(__IO uint32_t*)0x400782A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 9) */ + #define REG_XDMAC_CDA9 (*(__IO uint32_t*)0x400782A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 9) */ + #define REG_XDMAC_CNDA9 (*(__IO uint32_t*)0x400782A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 9) */ + #define REG_XDMAC_CNDC9 (*(__IO uint32_t*)0x400782ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 9) */ + #define REG_XDMAC_CUBC9 (*(__IO uint32_t*)0x400782B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 9) */ + #define REG_XDMAC_CBC9 (*(__IO uint32_t*)0x400782B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 9) */ + #define REG_XDMAC_CC9 (*(__IO uint32_t*)0x400782B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 9) */ + #define REG_XDMAC_CDS_MSP9 (*(__IO uint32_t*)0x400782BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 9) */ + #define REG_XDMAC_CSUS9 (*(__IO uint32_t*)0x400782C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 9) */ + #define REG_XDMAC_CDUS9 (*(__IO uint32_t*)0x400782C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 9) */ + #define REG_XDMAC_CIE10 (*(__O uint32_t*)0x400782D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 10) */ + #define REG_XDMAC_CID10 (*(__O uint32_t*)0x400782D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 10) */ + #define REG_XDMAC_CIM10 (*(__I uint32_t*)0x400782D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 10) */ + #define REG_XDMAC_CIS10 (*(__I uint32_t*)0x400782DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 10) */ + #define REG_XDMAC_CSA10 (*(__IO uint32_t*)0x400782E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 10) */ + #define REG_XDMAC_CDA10 (*(__IO uint32_t*)0x400782E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 10) */ + #define REG_XDMAC_CNDA10 (*(__IO uint32_t*)0x400782E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 10) */ + #define REG_XDMAC_CNDC10 (*(__IO uint32_t*)0x400782ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 10) */ + #define REG_XDMAC_CUBC10 (*(__IO uint32_t*)0x400782F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 10) */ + #define REG_XDMAC_CBC10 (*(__IO uint32_t*)0x400782F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 10) */ + #define REG_XDMAC_CC10 (*(__IO uint32_t*)0x400782F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 10) */ + #define REG_XDMAC_CDS_MSP10 (*(__IO uint32_t*)0x400782FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 10) */ + #define REG_XDMAC_CSUS10 (*(__IO uint32_t*)0x40078300U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 10) */ + #define REG_XDMAC_CDUS10 (*(__IO uint32_t*)0x40078304U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 10) */ + #define REG_XDMAC_CIE11 (*(__O uint32_t*)0x40078310U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 11) */ + #define REG_XDMAC_CID11 (*(__O uint32_t*)0x40078314U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 11) */ + #define REG_XDMAC_CIM11 (*(__I uint32_t*)0x40078318U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 11) */ + #define REG_XDMAC_CIS11 (*(__I uint32_t*)0x4007831CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 11) */ + #define REG_XDMAC_CSA11 (*(__IO uint32_t*)0x40078320U) /**< \brief (XDMAC) Channel Source Address Register (chid = 11) */ + #define REG_XDMAC_CDA11 (*(__IO uint32_t*)0x40078324U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 11) */ + #define REG_XDMAC_CNDA11 (*(__IO uint32_t*)0x40078328U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 11) */ + #define REG_XDMAC_CNDC11 (*(__IO uint32_t*)0x4007832CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 11) */ + #define REG_XDMAC_CUBC11 (*(__IO uint32_t*)0x40078330U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 11) */ + #define REG_XDMAC_CBC11 (*(__IO uint32_t*)0x40078334U) /**< \brief (XDMAC) Channel Block Control Register (chid = 11) */ + #define REG_XDMAC_CC11 (*(__IO uint32_t*)0x40078338U) /**< \brief (XDMAC) Channel Configuration Register (chid = 11) */ + #define REG_XDMAC_CDS_MSP11 (*(__IO uint32_t*)0x4007833CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 11) */ + #define REG_XDMAC_CSUS11 (*(__IO uint32_t*)0x40078340U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 11) */ + #define REG_XDMAC_CDUS11 (*(__IO uint32_t*)0x40078344U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 11) */ + #define REG_XDMAC_CIE12 (*(__O uint32_t*)0x40078350U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 12) */ + #define REG_XDMAC_CID12 (*(__O uint32_t*)0x40078354U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 12) */ + #define REG_XDMAC_CIM12 (*(__I uint32_t*)0x40078358U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 12) */ + #define REG_XDMAC_CIS12 (*(__I uint32_t*)0x4007835CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 12) */ + #define REG_XDMAC_CSA12 (*(__IO uint32_t*)0x40078360U) /**< \brief (XDMAC) Channel Source Address Register (chid = 12) */ + #define REG_XDMAC_CDA12 (*(__IO uint32_t*)0x40078364U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 12) */ + #define REG_XDMAC_CNDA12 (*(__IO uint32_t*)0x40078368U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 12) */ + #define REG_XDMAC_CNDC12 (*(__IO uint32_t*)0x4007836CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 12) */ + #define REG_XDMAC_CUBC12 (*(__IO uint32_t*)0x40078370U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 12) */ + #define REG_XDMAC_CBC12 (*(__IO uint32_t*)0x40078374U) /**< \brief (XDMAC) Channel Block Control Register (chid = 12) */ + #define REG_XDMAC_CC12 (*(__IO uint32_t*)0x40078378U) /**< \brief (XDMAC) Channel Configuration Register (chid = 12) */ + #define REG_XDMAC_CDS_MSP12 (*(__IO uint32_t*)0x4007837CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 12) */ + #define REG_XDMAC_CSUS12 (*(__IO uint32_t*)0x40078380U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 12) */ + #define REG_XDMAC_CDUS12 (*(__IO uint32_t*)0x40078384U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 12) */ + #define REG_XDMAC_CIE13 (*(__O uint32_t*)0x40078390U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 13) */ + #define REG_XDMAC_CID13 (*(__O uint32_t*)0x40078394U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 13) */ + #define REG_XDMAC_CIM13 (*(__I uint32_t*)0x40078398U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 13) */ + #define REG_XDMAC_CIS13 (*(__I uint32_t*)0x4007839CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 13) */ + #define REG_XDMAC_CSA13 (*(__IO uint32_t*)0x400783A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 13) */ + #define REG_XDMAC_CDA13 (*(__IO uint32_t*)0x400783A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 13) */ + #define REG_XDMAC_CNDA13 (*(__IO uint32_t*)0x400783A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 13) */ + #define REG_XDMAC_CNDC13 (*(__IO uint32_t*)0x400783ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 13) */ + #define REG_XDMAC_CUBC13 (*(__IO uint32_t*)0x400783B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 13) */ + #define REG_XDMAC_CBC13 (*(__IO uint32_t*)0x400783B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 13) */ + #define REG_XDMAC_CC13 (*(__IO uint32_t*)0x400783B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 13) */ + #define REG_XDMAC_CDS_MSP13 (*(__IO uint32_t*)0x400783BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 13) */ + #define REG_XDMAC_CSUS13 (*(__IO uint32_t*)0x400783C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 13) */ + #define REG_XDMAC_CDUS13 (*(__IO uint32_t*)0x400783C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 13) */ + #define REG_XDMAC_CIE14 (*(__O uint32_t*)0x400783D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 14) */ + #define REG_XDMAC_CID14 (*(__O uint32_t*)0x400783D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 14) */ + #define REG_XDMAC_CIM14 (*(__I uint32_t*)0x400783D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 14) */ + #define REG_XDMAC_CIS14 (*(__I uint32_t*)0x400783DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 14) */ + #define REG_XDMAC_CSA14 (*(__IO uint32_t*)0x400783E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 14) */ + #define REG_XDMAC_CDA14 (*(__IO uint32_t*)0x400783E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 14) */ + #define REG_XDMAC_CNDA14 (*(__IO uint32_t*)0x400783E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 14) */ + #define REG_XDMAC_CNDC14 (*(__IO uint32_t*)0x400783ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 14) */ + #define REG_XDMAC_CUBC14 (*(__IO uint32_t*)0x400783F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 14) */ + #define REG_XDMAC_CBC14 (*(__IO uint32_t*)0x400783F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 14) */ + #define REG_XDMAC_CC14 (*(__IO uint32_t*)0x400783F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 14) */ + #define REG_XDMAC_CDS_MSP14 (*(__IO uint32_t*)0x400783FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 14) */ + #define REG_XDMAC_CSUS14 (*(__IO uint32_t*)0x40078400U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 14) */ + #define REG_XDMAC_CDUS14 (*(__IO uint32_t*)0x40078404U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 14) */ + #define REG_XDMAC_CIE15 (*(__O uint32_t*)0x40078410U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 15) */ + #define REG_XDMAC_CID15 (*(__O uint32_t*)0x40078414U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 15) */ + #define REG_XDMAC_CIM15 (*(__I uint32_t*)0x40078418U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 15) */ + #define REG_XDMAC_CIS15 (*(__I uint32_t*)0x4007841CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 15) */ + #define REG_XDMAC_CSA15 (*(__IO uint32_t*)0x40078420U) /**< \brief (XDMAC) Channel Source Address Register (chid = 15) */ + #define REG_XDMAC_CDA15 (*(__IO uint32_t*)0x40078424U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 15) */ + #define REG_XDMAC_CNDA15 (*(__IO uint32_t*)0x40078428U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 15) */ + #define REG_XDMAC_CNDC15 (*(__IO uint32_t*)0x4007842CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 15) */ + #define REG_XDMAC_CUBC15 (*(__IO uint32_t*)0x40078430U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 15) */ + #define REG_XDMAC_CBC15 (*(__IO uint32_t*)0x40078434U) /**< \brief (XDMAC) Channel Block Control Register (chid = 15) */ + #define REG_XDMAC_CC15 (*(__IO uint32_t*)0x40078438U) /**< \brief (XDMAC) Channel Configuration Register (chid = 15) */ + #define REG_XDMAC_CDS_MSP15 (*(__IO uint32_t*)0x4007843CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 15) */ + #define REG_XDMAC_CSUS15 (*(__IO uint32_t*)0x40078440U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 15) */ + #define REG_XDMAC_CDUS15 (*(__IO uint32_t*)0x40078444U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 15) */ + #define REG_XDMAC_CIE16 (*(__O uint32_t*)0x40078450U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 16) */ + #define REG_XDMAC_CID16 (*(__O uint32_t*)0x40078454U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 16) */ + #define REG_XDMAC_CIM16 (*(__I uint32_t*)0x40078458U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 16) */ + #define REG_XDMAC_CIS16 (*(__I uint32_t*)0x4007845CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 16) */ + #define REG_XDMAC_CSA16 (*(__IO uint32_t*)0x40078460U) /**< \brief (XDMAC) Channel Source Address Register (chid = 16) */ + #define REG_XDMAC_CDA16 (*(__IO uint32_t*)0x40078464U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 16) */ + #define REG_XDMAC_CNDA16 (*(__IO uint32_t*)0x40078468U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 16) */ + #define REG_XDMAC_CNDC16 (*(__IO uint32_t*)0x4007846CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 16) */ + #define REG_XDMAC_CUBC16 (*(__IO uint32_t*)0x40078470U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 16) */ + #define REG_XDMAC_CBC16 (*(__IO uint32_t*)0x40078474U) /**< \brief (XDMAC) Channel Block Control Register (chid = 16) */ + #define REG_XDMAC_CC16 (*(__IO uint32_t*)0x40078478U) /**< \brief (XDMAC) Channel Configuration Register (chid = 16) */ + #define REG_XDMAC_CDS_MSP16 (*(__IO uint32_t*)0x4007847CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 16) */ + #define REG_XDMAC_CSUS16 (*(__IO uint32_t*)0x40078480U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 16) */ + #define REG_XDMAC_CDUS16 (*(__IO uint32_t*)0x40078484U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 16) */ + #define REG_XDMAC_CIE17 (*(__O uint32_t*)0x40078490U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 17) */ + #define REG_XDMAC_CID17 (*(__O uint32_t*)0x40078494U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 17) */ + #define REG_XDMAC_CIM17 (*(__I uint32_t*)0x40078498U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 17) */ + #define REG_XDMAC_CIS17 (*(__I uint32_t*)0x4007849CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 17) */ + #define REG_XDMAC_CSA17 (*(__IO uint32_t*)0x400784A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 17) */ + #define REG_XDMAC_CDA17 (*(__IO uint32_t*)0x400784A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 17) */ + #define REG_XDMAC_CNDA17 (*(__IO uint32_t*)0x400784A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 17) */ + #define REG_XDMAC_CNDC17 (*(__IO uint32_t*)0x400784ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 17) */ + #define REG_XDMAC_CUBC17 (*(__IO uint32_t*)0x400784B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 17) */ + #define REG_XDMAC_CBC17 (*(__IO uint32_t*)0x400784B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 17) */ + #define REG_XDMAC_CC17 (*(__IO uint32_t*)0x400784B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 17) */ + #define REG_XDMAC_CDS_MSP17 (*(__IO uint32_t*)0x400784BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 17) */ + #define REG_XDMAC_CSUS17 (*(__IO uint32_t*)0x400784C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 17) */ + #define REG_XDMAC_CDUS17 (*(__IO uint32_t*)0x400784C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 17) */ + #define REG_XDMAC_CIE18 (*(__O uint32_t*)0x400784D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 18) */ + #define REG_XDMAC_CID18 (*(__O uint32_t*)0x400784D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 18) */ + #define REG_XDMAC_CIM18 (*(__I uint32_t*)0x400784D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 18) */ + #define REG_XDMAC_CIS18 (*(__I uint32_t*)0x400784DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 18) */ + #define REG_XDMAC_CSA18 (*(__IO uint32_t*)0x400784E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 18) */ + #define REG_XDMAC_CDA18 (*(__IO uint32_t*)0x400784E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 18) */ + #define REG_XDMAC_CNDA18 (*(__IO uint32_t*)0x400784E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 18) */ + #define REG_XDMAC_CNDC18 (*(__IO uint32_t*)0x400784ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 18) */ + #define REG_XDMAC_CUBC18 (*(__IO uint32_t*)0x400784F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 18) */ + #define REG_XDMAC_CBC18 (*(__IO uint32_t*)0x400784F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 18) */ + #define REG_XDMAC_CC18 (*(__IO uint32_t*)0x400784F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 18) */ + #define REG_XDMAC_CDS_MSP18 (*(__IO uint32_t*)0x400784FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 18) */ + #define REG_XDMAC_CSUS18 (*(__IO uint32_t*)0x40078500U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 18) */ + #define REG_XDMAC_CDUS18 (*(__IO uint32_t*)0x40078504U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 18) */ + #define REG_XDMAC_CIE19 (*(__O uint32_t*)0x40078510U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 19) */ + #define REG_XDMAC_CID19 (*(__O uint32_t*)0x40078514U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 19) */ + #define REG_XDMAC_CIM19 (*(__I uint32_t*)0x40078518U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 19) */ + #define REG_XDMAC_CIS19 (*(__I uint32_t*)0x4007851CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 19) */ + #define REG_XDMAC_CSA19 (*(__IO uint32_t*)0x40078520U) /**< \brief (XDMAC) Channel Source Address Register (chid = 19) */ + #define REG_XDMAC_CDA19 (*(__IO uint32_t*)0x40078524U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 19) */ + #define REG_XDMAC_CNDA19 (*(__IO uint32_t*)0x40078528U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 19) */ + #define REG_XDMAC_CNDC19 (*(__IO uint32_t*)0x4007852CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 19) */ + #define REG_XDMAC_CUBC19 (*(__IO uint32_t*)0x40078530U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 19) */ + #define REG_XDMAC_CBC19 (*(__IO uint32_t*)0x40078534U) /**< \brief (XDMAC) Channel Block Control Register (chid = 19) */ + #define REG_XDMAC_CC19 (*(__IO uint32_t*)0x40078538U) /**< \brief (XDMAC) Channel Configuration Register (chid = 19) */ + #define REG_XDMAC_CDS_MSP19 (*(__IO uint32_t*)0x4007853CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 19) */ + #define REG_XDMAC_CSUS19 (*(__IO uint32_t*)0x40078540U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 19) */ + #define REG_XDMAC_CDUS19 (*(__IO uint32_t*)0x40078544U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 19) */ + #define REG_XDMAC_CIE20 (*(__O uint32_t*)0x40078550U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 20) */ + #define REG_XDMAC_CID20 (*(__O uint32_t*)0x40078554U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 20) */ + #define REG_XDMAC_CIM20 (*(__I uint32_t*)0x40078558U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 20) */ + #define REG_XDMAC_CIS20 (*(__I uint32_t*)0x4007855CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 20) */ + #define REG_XDMAC_CSA20 (*(__IO uint32_t*)0x40078560U) /**< \brief (XDMAC) Channel Source Address Register (chid = 20) */ + #define REG_XDMAC_CDA20 (*(__IO uint32_t*)0x40078564U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 20) */ + #define REG_XDMAC_CNDA20 (*(__IO uint32_t*)0x40078568U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 20) */ + #define REG_XDMAC_CNDC20 (*(__IO uint32_t*)0x4007856CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 20) */ + #define REG_XDMAC_CUBC20 (*(__IO uint32_t*)0x40078570U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 20) */ + #define REG_XDMAC_CBC20 (*(__IO uint32_t*)0x40078574U) /**< \brief (XDMAC) Channel Block Control Register (chid = 20) */ + #define REG_XDMAC_CC20 (*(__IO uint32_t*)0x40078578U) /**< \brief (XDMAC) Channel Configuration Register (chid = 20) */ + #define REG_XDMAC_CDS_MSP20 (*(__IO uint32_t*)0x4007857CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 20) */ + #define REG_XDMAC_CSUS20 (*(__IO uint32_t*)0x40078580U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 20) */ + #define REG_XDMAC_CDUS20 (*(__IO uint32_t*)0x40078584U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 20) */ + #define REG_XDMAC_CIE21 (*(__O uint32_t*)0x40078590U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 21) */ + #define REG_XDMAC_CID21 (*(__O uint32_t*)0x40078594U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 21) */ + #define REG_XDMAC_CIM21 (*(__I uint32_t*)0x40078598U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 21) */ + #define REG_XDMAC_CIS21 (*(__I uint32_t*)0x4007859CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 21) */ + #define REG_XDMAC_CSA21 (*(__IO uint32_t*)0x400785A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 21) */ + #define REG_XDMAC_CDA21 (*(__IO uint32_t*)0x400785A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 21) */ + #define REG_XDMAC_CNDA21 (*(__IO uint32_t*)0x400785A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 21) */ + #define REG_XDMAC_CNDC21 (*(__IO uint32_t*)0x400785ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 21) */ + #define REG_XDMAC_CUBC21 (*(__IO uint32_t*)0x400785B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 21) */ + #define REG_XDMAC_CBC21 (*(__IO uint32_t*)0x400785B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 21) */ + #define REG_XDMAC_CC21 (*(__IO uint32_t*)0x400785B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 21) */ + #define REG_XDMAC_CDS_MSP21 (*(__IO uint32_t*)0x400785BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 21) */ + #define REG_XDMAC_CSUS21 (*(__IO uint32_t*)0x400785C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 21) */ + #define REG_XDMAC_CDUS21 (*(__IO uint32_t*)0x400785C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 21) */ + #define REG_XDMAC_CIE22 (*(__O uint32_t*)0x400785D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 22) */ + #define REG_XDMAC_CID22 (*(__O uint32_t*)0x400785D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 22) */ + #define REG_XDMAC_CIM22 (*(__I uint32_t*)0x400785D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 22) */ + #define REG_XDMAC_CIS22 (*(__I uint32_t*)0x400785DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 22) */ + #define REG_XDMAC_CSA22 (*(__IO uint32_t*)0x400785E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 22) */ + #define REG_XDMAC_CDA22 (*(__IO uint32_t*)0x400785E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 22) */ + #define REG_XDMAC_CNDA22 (*(__IO uint32_t*)0x400785E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 22) */ + #define REG_XDMAC_CNDC22 (*(__IO uint32_t*)0x400785ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 22) */ + #define REG_XDMAC_CUBC22 (*(__IO uint32_t*)0x400785F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 22) */ + #define REG_XDMAC_CBC22 (*(__IO uint32_t*)0x400785F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 22) */ + #define REG_XDMAC_CC22 (*(__IO uint32_t*)0x400785F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 22) */ + #define REG_XDMAC_CDS_MSP22 (*(__IO uint32_t*)0x400785FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 22) */ + #define REG_XDMAC_CSUS22 (*(__IO uint32_t*)0x40078600U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 22) */ + #define REG_XDMAC_CDUS22 (*(__IO uint32_t*)0x40078604U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 22) */ + #define REG_XDMAC_CIE23 (*(__O uint32_t*)0x40078610U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 23) */ + #define REG_XDMAC_CID23 (*(__O uint32_t*)0x40078614U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 23) */ + #define REG_XDMAC_CIM23 (*(__I uint32_t*)0x40078618U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 23) */ + #define REG_XDMAC_CIS23 (*(__I uint32_t*)0x4007861CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 23) */ + #define REG_XDMAC_CSA23 (*(__IO uint32_t*)0x40078620U) /**< \brief (XDMAC) Channel Source Address Register (chid = 23) */ + #define REG_XDMAC_CDA23 (*(__IO uint32_t*)0x40078624U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 23) */ + #define REG_XDMAC_CNDA23 (*(__IO uint32_t*)0x40078628U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 23) */ + #define REG_XDMAC_CNDC23 (*(__IO uint32_t*)0x4007862CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 23) */ + #define REG_XDMAC_CUBC23 (*(__IO uint32_t*)0x40078630U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 23) */ + #define REG_XDMAC_CBC23 (*(__IO uint32_t*)0x40078634U) /**< \brief (XDMAC) Channel Block Control Register (chid = 23) */ + #define REG_XDMAC_CC23 (*(__IO uint32_t*)0x40078638U) /**< \brief (XDMAC) Channel Configuration Register (chid = 23) */ + #define REG_XDMAC_CDS_MSP23 (*(__IO uint32_t*)0x4007863CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 23) */ + #define REG_XDMAC_CSUS23 (*(__IO uint32_t*)0x40078640U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 23) */ + #define REG_XDMAC_CDUS23 (*(__IO uint32_t*)0x40078644U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 23) */ + #define REG_XDMAC_VERSION (*(__IO uint32_t*)0x40078FFCU) /**< \brief (XDMAC) XDMAC Version Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAME70_XDMAC_INSTANCE_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70j19.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70j19.h new file mode 100644 index 000000000..4710fa851 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70j19.h @@ -0,0 +1,398 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70J19_PIO_ +#define _SAME70J19_PIO_ + +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio indexes ========== */ +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA24_IDX 24 +#define PIO_PA27_IDX 27 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD31_IDX 127 + +#endif /* _SAME70J19_PIO_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70j19b.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70j19b.h new file mode 100644 index 000000000..5d40d1dd4 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70j19b.h @@ -0,0 +1,398 @@ +/** + * \file + * + * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70J19B_PIO_ +#define _SAME70J19B_PIO_ + +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio indexes ========== */ +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA24_IDX 24 +#define PIO_PA27_IDX 27 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD31_IDX 127 + +#endif /* _SAME70J19B_PIO_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70j20.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70j20.h new file mode 100644 index 000000000..e15510c54 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70j20.h @@ -0,0 +1,398 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70J20_PIO_ +#define _SAME70J20_PIO_ + +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio indexes ========== */ +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA24_IDX 24 +#define PIO_PA27_IDX 27 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD31_IDX 127 + +#endif /* _SAME70J20_PIO_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70j20b.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70j20b.h new file mode 100644 index 000000000..c3860b616 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70j20b.h @@ -0,0 +1,398 @@ +/** + * \file + * + * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70J20B_PIO_ +#define _SAME70J20B_PIO_ + +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio indexes ========== */ +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA24_IDX 24 +#define PIO_PA27_IDX 27 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD31_IDX 127 + +#endif /* _SAME70J20B_PIO_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70j21.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70j21.h new file mode 100644 index 000000000..ec9104a82 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70j21.h @@ -0,0 +1,398 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70J21_PIO_ +#define _SAME70J21_PIO_ + +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio indexes ========== */ +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA24_IDX 24 +#define PIO_PA27_IDX 27 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD31_IDX 127 + +#endif /* _SAME70J21_PIO_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70j21b.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70j21b.h new file mode 100644 index 000000000..dfcead662 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70j21b.h @@ -0,0 +1,398 @@ +/** + * \file + * + * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70J21B_PIO_ +#define _SAME70J21B_PIO_ + +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio indexes ========== */ +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA24_IDX 24 +#define PIO_PA27_IDX 27 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD31_IDX 127 + +#endif /* _SAME70J21B_PIO_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70n19.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70n19.h new file mode 100644 index 000000000..fe3589a11 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70n19.h @@ -0,0 +1,489 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70N19_PIO_ +#define _SAME70N19_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 + +#endif /* _SAME70N19_PIO_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70n19b.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70n19b.h new file mode 100644 index 000000000..3fec53943 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70n19b.h @@ -0,0 +1,495 @@ +/** + * \file + * + * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70N19B_PIO_ +#define _SAME70N19B_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for I2SC0 peripheral ========== */ +#define PIO_PA1D_I2SC0_CK (1u << 1) /**< \brief I2sc0 signal: I2SC0_CK */ +#define PIO_PA16D_I2SC0_DI0 (1u << 16) /**< \brief I2sc0 signal: I2SC0_DI0 */ +#define PIO_PA30D_I2SC0_DO0 (1u << 30) /**< \brief I2sc0 signal: I2SC0_DO0 */ +#define PIO_PA0D_I2SC0_MCK (1u << 0) /**< \brief I2sc0 signal: I2SC0_MCK */ +#define PIO_PA15D_I2SC0_WS (1u << 15) /**< \brief I2sc0 signal: I2SC0_WS */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 + +#endif /* _SAME70N19B_PIO_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70n20.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70n20.h new file mode 100644 index 000000000..8ec046f4f --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70n20.h @@ -0,0 +1,489 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70N20_PIO_ +#define _SAME70N20_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 + +#endif /* _SAME70N20_PIO_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70n20b.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70n20b.h new file mode 100644 index 000000000..a488317df --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70n20b.h @@ -0,0 +1,495 @@ +/** + * \file + * + * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70N20B_PIO_ +#define _SAME70N20B_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for I2SC0 peripheral ========== */ +#define PIO_PA1D_I2SC0_CK (1u << 1) /**< \brief I2sc0 signal: I2SC0_CK */ +#define PIO_PA16D_I2SC0_DI0 (1u << 16) /**< \brief I2sc0 signal: I2SC0_DI0 */ +#define PIO_PA30D_I2SC0_DO0 (1u << 30) /**< \brief I2sc0 signal: I2SC0_DO0 */ +#define PIO_PA0D_I2SC0_MCK (1u << 0) /**< \brief I2sc0 signal: I2SC0_MCK */ +#define PIO_PA15D_I2SC0_WS (1u << 15) /**< \brief I2sc0 signal: I2SC0_WS */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 + +#endif /* _SAME70N20B_PIO_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70n21.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70n21.h new file mode 100644 index 000000000..1743056c5 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70n21.h @@ -0,0 +1,489 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70N21_PIO_ +#define _SAME70N21_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 + +#endif /* _SAME70N21_PIO_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70n21b.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70n21b.h new file mode 100644 index 000000000..9c230da7a --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70n21b.h @@ -0,0 +1,495 @@ +/** + * \file + * + * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70N21B_PIO_ +#define _SAME70N21B_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for I2SC0 peripheral ========== */ +#define PIO_PA1D_I2SC0_CK (1u << 1) /**< \brief I2sc0 signal: I2SC0_CK */ +#define PIO_PA16D_I2SC0_DI0 (1u << 16) /**< \brief I2sc0 signal: I2SC0_DI0 */ +#define PIO_PA30D_I2SC0_DO0 (1u << 30) /**< \brief I2sc0 signal: I2SC0_DO0 */ +#define PIO_PA0D_I2SC0_MCK (1u << 0) /**< \brief I2sc0 signal: I2SC0_MCK */ +#define PIO_PA15D_I2SC0_WS (1u << 15) /**< \brief I2sc0 signal: I2SC0_WS */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 + +#endif /* _SAME70N21B_PIO_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70q19.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70q19.h new file mode 100644 index 000000000..6988dbe8e --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70q19.h @@ -0,0 +1,685 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70Q19_PIO_ +#define _SAME70Q19_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ +#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ +#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ +#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ +#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ +#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */ +#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */ +#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */ +#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */ +#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */ +#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */ +#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */ +#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */ +#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TC2 peripheral ========== */ +#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ +#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ +#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ +#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio definition for UTMI peripheral ========== */ +#define PIO_PC12D_UTMI_CDRBISTEN (1u << 12) /**< \brief Utmi signal: UTMI_CDRBISTEN */ +#define PIO_PC29D_UTMI_CDRCPDIVEN (1u << 29) /**< \brief Utmi signal: UTMI_CDRCPDIVEN */ +#define PIO_PC31D_UTMI_CDRCPSEL0 (1u << 31) /**< \brief Utmi signal: UTMI_CDRCPSEL0 */ +#define PIO_PC30D_UTMI_CDRCPSEL1 (1u << 30) /**< \brief Utmi signal: UTMI_CDRCPSEL1 */ +#define PIO_PC15D_UTMI_CDRCPSELDIV (1u << 15) /**< \brief Utmi signal: UTMI_CDRCPSELDIV */ +#define PIO_PC0D_UTMI_HDIS (1u << 0) /**< \brief Utmi signal: UTMI_HDIS */ +#define PIO_PC27D_UTMI_LS0 (1u << 27) /**< \brief Utmi signal: UTMI_LS0 */ +#define PIO_PC26D_UTMI_LS1 (1u << 26) /**< \brief Utmi signal: UTMI_LS1 */ +#define PIO_PE3D_UTMI_RXACT (1u << 3) /**< \brief Utmi signal: UTMI_RXACT */ +#define PIO_PE2D_UTMI_RXERR (1u << 2) /**< \brief Utmi signal: UTMI_RXERR */ +#define PIO_PE1D_UTMI_RXVAL (1u << 1) /**< \brief Utmi signal: UTMI_RXVAL */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD23_IDX 119 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD29_IDX 125 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 +#define PIO_PE0_IDX 128 +#define PIO_PE1_IDX 129 +#define PIO_PE2_IDX 130 +#define PIO_PE3_IDX 131 +#define PIO_PE4_IDX 132 +#define PIO_PE5_IDX 133 + +#endif /* _SAME70Q19_PIO_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70q19b.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70q19b.h new file mode 100644 index 000000000..763206938 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70q19b.h @@ -0,0 +1,697 @@ +/** + * \file + * + * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70Q19B_PIO_ +#define _SAME70Q19B_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ +#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ +#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ +#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ +#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ +#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */ +#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */ +#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */ +#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */ +#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */ +#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */ +#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */ +#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */ +#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for I2SC0 peripheral ========== */ +#define PIO_PA1D_I2SC0_CK (1u << 1) /**< \brief I2sc0 signal: I2SC0_CK */ +#define PIO_PA16D_I2SC0_DI0 (1u << 16) /**< \brief I2sc0 signal: I2SC0_DI0 */ +#define PIO_PA30D_I2SC0_DO0 (1u << 30) /**< \brief I2sc0 signal: I2SC0_DO0 */ +#define PIO_PA0D_I2SC0_MCK (1u << 0) /**< \brief I2sc0 signal: I2SC0_MCK */ +#define PIO_PA15D_I2SC0_WS (1u << 15) /**< \brief I2sc0 signal: I2SC0_WS */ +/* ========== Pio definition for I2SC1 peripheral ========== */ +#define PIO_PA20D_I2SC1_CK (1u << 20) /**< \brief I2sc1 signal: I2SC1_CK */ +#define PIO_PE2C_I2SC1_DI0 (1u << 2) /**< \brief I2sc1 signal: I2SC1_DI0 */ +#define PIO_PE1C_I2SC1_DO0 (1u << 1) /**< \brief I2sc1 signal: I2SC1_DO0 */ +#define PIO_PA19D_I2SC1_MCK (1u << 19) /**< \brief I2sc1 signal: I2SC1_MCK */ +#define PIO_PE0C_I2SC1_WS (1u << 0) /**< \brief I2sc1 signal: I2SC1_WS */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TC2 peripheral ========== */ +#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ +#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ +#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ +#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio definition for UTMI peripheral ========== */ +#define PIO_PC12D_UTMI_CDRBISTEN (1u << 12) /**< \brief Utmi signal: UTMI_CDRBISTEN */ +#define PIO_PC29D_UTMI_CDRCPDIVEN (1u << 29) /**< \brief Utmi signal: UTMI_CDRCPDIVEN */ +#define PIO_PC31D_UTMI_CDRCPSEL0 (1u << 31) /**< \brief Utmi signal: UTMI_CDRCPSEL0 */ +#define PIO_PC30D_UTMI_CDRCPSEL1 (1u << 30) /**< \brief Utmi signal: UTMI_CDRCPSEL1 */ +#define PIO_PC15D_UTMI_CDRCPSELDIV (1u << 15) /**< \brief Utmi signal: UTMI_CDRCPSELDIV */ +#define PIO_PC0D_UTMI_HDIS (1u << 0) /**< \brief Utmi signal: UTMI_HDIS */ +#define PIO_PC27D_UTMI_LS0 (1u << 27) /**< \brief Utmi signal: UTMI_LS0 */ +#define PIO_PC26D_UTMI_LS1 (1u << 26) /**< \brief Utmi signal: UTMI_LS1 */ +#define PIO_PE3D_UTMI_RXACT (1u << 3) /**< \brief Utmi signal: UTMI_RXACT */ +#define PIO_PE2D_UTMI_RXERR (1u << 2) /**< \brief Utmi signal: UTMI_RXERR */ +#define PIO_PE1D_UTMI_RXVAL (1u << 1) /**< \brief Utmi signal: UTMI_RXVAL */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD23_IDX 119 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD29_IDX 125 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 +#define PIO_PE0_IDX 128 +#define PIO_PE1_IDX 129 +#define PIO_PE2_IDX 130 +#define PIO_PE3_IDX 131 +#define PIO_PE4_IDX 132 +#define PIO_PE5_IDX 133 + +#endif /* _SAME70Q19B_PIO_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70q20.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70q20.h new file mode 100644 index 000000000..d4c304eae --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70q20.h @@ -0,0 +1,685 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70Q20_PIO_ +#define _SAME70Q20_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ +#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ +#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ +#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ +#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ +#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */ +#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */ +#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */ +#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */ +#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */ +#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */ +#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */ +#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */ +#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TC2 peripheral ========== */ +#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ +#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ +#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ +#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio definition for UTMI peripheral ========== */ +#define PIO_PC12D_UTMI_CDRBISTEN (1u << 12) /**< \brief Utmi signal: UTMI_CDRBISTEN */ +#define PIO_PC29D_UTMI_CDRCPDIVEN (1u << 29) /**< \brief Utmi signal: UTMI_CDRCPDIVEN */ +#define PIO_PC31D_UTMI_CDRCPSEL0 (1u << 31) /**< \brief Utmi signal: UTMI_CDRCPSEL0 */ +#define PIO_PC30D_UTMI_CDRCPSEL1 (1u << 30) /**< \brief Utmi signal: UTMI_CDRCPSEL1 */ +#define PIO_PC15D_UTMI_CDRCPSELDIV (1u << 15) /**< \brief Utmi signal: UTMI_CDRCPSELDIV */ +#define PIO_PC0D_UTMI_HDIS (1u << 0) /**< \brief Utmi signal: UTMI_HDIS */ +#define PIO_PC27D_UTMI_LS0 (1u << 27) /**< \brief Utmi signal: UTMI_LS0 */ +#define PIO_PC26D_UTMI_LS1 (1u << 26) /**< \brief Utmi signal: UTMI_LS1 */ +#define PIO_PE3D_UTMI_RXACT (1u << 3) /**< \brief Utmi signal: UTMI_RXACT */ +#define PIO_PE2D_UTMI_RXERR (1u << 2) /**< \brief Utmi signal: UTMI_RXERR */ +#define PIO_PE1D_UTMI_RXVAL (1u << 1) /**< \brief Utmi signal: UTMI_RXVAL */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD23_IDX 119 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD29_IDX 125 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 +#define PIO_PE0_IDX 128 +#define PIO_PE1_IDX 129 +#define PIO_PE2_IDX 130 +#define PIO_PE3_IDX 131 +#define PIO_PE4_IDX 132 +#define PIO_PE5_IDX 133 + +#endif /* _SAME70Q20_PIO_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70q20b.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70q20b.h new file mode 100644 index 000000000..8f2a63d91 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70q20b.h @@ -0,0 +1,697 @@ +/** + * \file + * + * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70Q20B_PIO_ +#define _SAME70Q20B_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ +#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ +#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ +#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ +#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ +#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */ +#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */ +#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */ +#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */ +#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */ +#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */ +#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */ +#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */ +#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for I2SC0 peripheral ========== */ +#define PIO_PA1D_I2SC0_CK (1u << 1) /**< \brief I2sc0 signal: I2SC0_CK */ +#define PIO_PA16D_I2SC0_DI0 (1u << 16) /**< \brief I2sc0 signal: I2SC0_DI0 */ +#define PIO_PA30D_I2SC0_DO0 (1u << 30) /**< \brief I2sc0 signal: I2SC0_DO0 */ +#define PIO_PA0D_I2SC0_MCK (1u << 0) /**< \brief I2sc0 signal: I2SC0_MCK */ +#define PIO_PA15D_I2SC0_WS (1u << 15) /**< \brief I2sc0 signal: I2SC0_WS */ +/* ========== Pio definition for I2SC1 peripheral ========== */ +#define PIO_PA20D_I2SC1_CK (1u << 20) /**< \brief I2sc1 signal: I2SC1_CK */ +#define PIO_PE2C_I2SC1_DI0 (1u << 2) /**< \brief I2sc1 signal: I2SC1_DI0 */ +#define PIO_PE1C_I2SC1_DO0 (1u << 1) /**< \brief I2sc1 signal: I2SC1_DO0 */ +#define PIO_PA19D_I2SC1_MCK (1u << 19) /**< \brief I2sc1 signal: I2SC1_MCK */ +#define PIO_PE0C_I2SC1_WS (1u << 0) /**< \brief I2sc1 signal: I2SC1_WS */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ // QDEC A +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ // QDEC B +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ // QDEC Index +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ // QDEC A +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ // QDEC B +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ // QDEC Index +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TC2 peripheral ========== */ +#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ // QDEC A +#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ // QDEC B +#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ // QDEC Index +#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ // QDEC A +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ // QDEC Index +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ // QDEC B +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio definition for UTMI peripheral ========== */ +#define PIO_PC12D_UTMI_CDRBISTEN (1u << 12) /**< \brief Utmi signal: UTMI_CDRBISTEN */ +#define PIO_PC29D_UTMI_CDRCPDIVEN (1u << 29) /**< \brief Utmi signal: UTMI_CDRCPDIVEN */ +#define PIO_PC31D_UTMI_CDRCPSEL0 (1u << 31) /**< \brief Utmi signal: UTMI_CDRCPSEL0 */ +#define PIO_PC30D_UTMI_CDRCPSEL1 (1u << 30) /**< \brief Utmi signal: UTMI_CDRCPSEL1 */ +#define PIO_PC15D_UTMI_CDRCPSELDIV (1u << 15) /**< \brief Utmi signal: UTMI_CDRCPSELDIV */ +#define PIO_PC0D_UTMI_HDIS (1u << 0) /**< \brief Utmi signal: UTMI_HDIS */ +#define PIO_PC27D_UTMI_LS0 (1u << 27) /**< \brief Utmi signal: UTMI_LS0 */ +#define PIO_PC26D_UTMI_LS1 (1u << 26) /**< \brief Utmi signal: UTMI_LS1 */ +#define PIO_PE3D_UTMI_RXACT (1u << 3) /**< \brief Utmi signal: UTMI_RXACT */ +#define PIO_PE2D_UTMI_RXERR (1u << 2) /**< \brief Utmi signal: UTMI_RXERR */ +#define PIO_PE1D_UTMI_RXVAL (1u << 1) /**< \brief Utmi signal: UTMI_RXVAL */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD23_IDX 119 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD29_IDX 125 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 +#define PIO_PE0_IDX 128 +#define PIO_PE1_IDX 129 +#define PIO_PE2_IDX 130 +#define PIO_PE3_IDX 131 +#define PIO_PE4_IDX 132 +#define PIO_PE5_IDX 133 + +#endif /* _SAME70Q20B_PIO_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70q21.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70q21.h new file mode 100644 index 000000000..9dec3f290 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70q21.h @@ -0,0 +1,685 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70Q21_PIO_ +#define _SAME70Q21_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ +#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ +#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ +#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ +#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ +#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */ +#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */ +#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */ +#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */ +#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */ +#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */ +#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */ +#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */ +#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TC2 peripheral ========== */ +#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ +#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ +#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ +#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio definition for UTMI peripheral ========== */ +#define PIO_PC12D_UTMI_CDRBISTEN (1u << 12) /**< \brief Utmi signal: UTMI_CDRBISTEN */ +#define PIO_PC29D_UTMI_CDRCPDIVEN (1u << 29) /**< \brief Utmi signal: UTMI_CDRCPDIVEN */ +#define PIO_PC31D_UTMI_CDRCPSEL0 (1u << 31) /**< \brief Utmi signal: UTMI_CDRCPSEL0 */ +#define PIO_PC30D_UTMI_CDRCPSEL1 (1u << 30) /**< \brief Utmi signal: UTMI_CDRCPSEL1 */ +#define PIO_PC15D_UTMI_CDRCPSELDIV (1u << 15) /**< \brief Utmi signal: UTMI_CDRCPSELDIV */ +#define PIO_PC0D_UTMI_HDIS (1u << 0) /**< \brief Utmi signal: UTMI_HDIS */ +#define PIO_PC27D_UTMI_LS0 (1u << 27) /**< \brief Utmi signal: UTMI_LS0 */ +#define PIO_PC26D_UTMI_LS1 (1u << 26) /**< \brief Utmi signal: UTMI_LS1 */ +#define PIO_PE3D_UTMI_RXACT (1u << 3) /**< \brief Utmi signal: UTMI_RXACT */ +#define PIO_PE2D_UTMI_RXERR (1u << 2) /**< \brief Utmi signal: UTMI_RXERR */ +#define PIO_PE1D_UTMI_RXVAL (1u << 1) /**< \brief Utmi signal: UTMI_RXVAL */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD23_IDX 119 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD29_IDX 125 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 +#define PIO_PE0_IDX 128 +#define PIO_PE1_IDX 129 +#define PIO_PE2_IDX 130 +#define PIO_PE3_IDX 131 +#define PIO_PE4_IDX 132 +#define PIO_PE5_IDX 133 + +#endif /* _SAME70Q21_PIO_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70q21b.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70q21b.h new file mode 100644 index 000000000..9512051f9 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/pio/same70q21b.h @@ -0,0 +1,697 @@ +/** + * \file + * + * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70Q21B_PIO_ +#define _SAME70Q21B_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ +#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ +#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ +#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ +#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ +#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */ +#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */ +#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */ +#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */ +#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */ +#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */ +#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */ +#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */ +#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for I2SC0 peripheral ========== */ +#define PIO_PA1D_I2SC0_CK (1u << 1) /**< \brief I2sc0 signal: I2SC0_CK */ +#define PIO_PA16D_I2SC0_DI0 (1u << 16) /**< \brief I2sc0 signal: I2SC0_DI0 */ +#define PIO_PA30D_I2SC0_DO0 (1u << 30) /**< \brief I2sc0 signal: I2SC0_DO0 */ +#define PIO_PA0D_I2SC0_MCK (1u << 0) /**< \brief I2sc0 signal: I2SC0_MCK */ +#define PIO_PA15D_I2SC0_WS (1u << 15) /**< \brief I2sc0 signal: I2SC0_WS */ +/* ========== Pio definition for I2SC1 peripheral ========== */ +#define PIO_PA20D_I2SC1_CK (1u << 20) /**< \brief I2sc1 signal: I2SC1_CK */ +#define PIO_PE2C_I2SC1_DI0 (1u << 2) /**< \brief I2sc1 signal: I2SC1_DI0 */ +#define PIO_PE1C_I2SC1_DO0 (1u << 1) /**< \brief I2sc1 signal: I2SC1_DO0 */ +#define PIO_PA19D_I2SC1_MCK (1u << 19) /**< \brief I2sc1 signal: I2SC1_MCK */ +#define PIO_PE0C_I2SC1_WS (1u << 0) /**< \brief I2sc1 signal: I2SC1_WS */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TC2 peripheral ========== */ +#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ +#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ +#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ +#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio definition for UTMI peripheral ========== */ +#define PIO_PC12D_UTMI_CDRBISTEN (1u << 12) /**< \brief Utmi signal: UTMI_CDRBISTEN */ +#define PIO_PC29D_UTMI_CDRCPDIVEN (1u << 29) /**< \brief Utmi signal: UTMI_CDRCPDIVEN */ +#define PIO_PC31D_UTMI_CDRCPSEL0 (1u << 31) /**< \brief Utmi signal: UTMI_CDRCPSEL0 */ +#define PIO_PC30D_UTMI_CDRCPSEL1 (1u << 30) /**< \brief Utmi signal: UTMI_CDRCPSEL1 */ +#define PIO_PC15D_UTMI_CDRCPSELDIV (1u << 15) /**< \brief Utmi signal: UTMI_CDRCPSELDIV */ +#define PIO_PC0D_UTMI_HDIS (1u << 0) /**< \brief Utmi signal: UTMI_HDIS */ +#define PIO_PC27D_UTMI_LS0 (1u << 27) /**< \brief Utmi signal: UTMI_LS0 */ +#define PIO_PC26D_UTMI_LS1 (1u << 26) /**< \brief Utmi signal: UTMI_LS1 */ +#define PIO_PE3D_UTMI_RXACT (1u << 3) /**< \brief Utmi signal: UTMI_RXACT */ +#define PIO_PE2D_UTMI_RXERR (1u << 2) /**< \brief Utmi signal: UTMI_RXERR */ +#define PIO_PE1D_UTMI_RXVAL (1u << 1) /**< \brief Utmi signal: UTMI_RXVAL */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD23_IDX 119 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD29_IDX 125 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 +#define PIO_PE0_IDX 128 +#define PIO_PE1_IDX 129 +#define PIO_PE2_IDX 130 +#define PIO_PE3_IDX 131 +#define PIO_PE4_IDX 132 +#define PIO_PE5_IDX 133 + +#endif /* _SAME70Q21B_PIO_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70.h new file mode 100644 index 000000000..de427fdf8 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70.h @@ -0,0 +1,77 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef _SAME70_ +#define _SAME70_ + +#if defined (__SAME70J19__) +#include "same70j19.h" +#elif defined (__SAME70J20__) +#include "same70j20.h" +#elif defined (__SAME70J21__) +#include "same70j21.h" +#elif defined (__SAME70N19__) +#include "same70n19.h" +#elif defined (__SAME70N20__) +#include "same70n20.h" +#elif defined (__SAME70N21__) +#include "same70n21.h" +#elif defined (__SAME70Q19__) +#include "same70q19.h" +#elif defined (__SAME70Q20__) +#include "same70q20.h" +#elif defined (__SAME70Q21__) +#include "same70q21.h" +#elif defined (__SAME70J19B__) +#include "same70j19b.h" +#elif defined (__SAME70J20B__) +#include "same70j20b.h" +#elif defined (__SAME70J21B__) +#include "same70j21b.h" +#elif defined (__SAME70N19B__) +#include "same70n19b.h" +#elif defined (__SAME70N20B__) +#include "same70n20b.h" +#elif defined (__SAME70N21B__) +#include "same70n21b.h" +#elif defined (__SAME70Q19B__) +#include "same70q19b.h" +#elif defined (__SAME70Q20B__) +#include "same70q20b.h" +#elif defined (__SAME70Q21B__) +#include "same70q21b.h" +#else + #error Library does not support the specified device. +#endif + +#endif /* _SAME70_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70j19.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70j19.h new file mode 100644 index 000000000..4e49a8d13 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70j19.h @@ -0,0 +1,611 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70J19_ +#define _SAME70J19_ + +/** \addtogroup SAME70J19_definitions SAME70J19 definitions + This file defines all structures and symbols for SAME70J19: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J19_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70J19 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70J19 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70J19 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70J19 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70J19 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70J19 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70J19 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70J19 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70J19 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70J19 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70J19 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70J19 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAME70J19 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70J19 USART 1 (USART1) */ + PIOD_IRQn = 16, /**< 16 SAME70J19 Parallel I/O Controller D (PIOD) */ + TWIHS0_IRQn = 19, /**< 19 SAME70J19 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70J19 Two Wire Interface 1 HS (TWIHS1) */ + SSC_IRQn = 22, /**< 22 SAME70J19 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70J19 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70J19 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70J19 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAME70J19 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70J19 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70J19 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70J19 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70J19 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70J19 USB Host / Device Controller (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 SAME70J19 Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 SAME70J19 Controller Area Network (MCAN0) */ + GMAC_IRQn = 39, /**< 39 SAME70J19 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70J19 Analog Front End 1 (AFEC1) */ + QSPI_IRQn = 43, /**< 43 SAME70J19 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70J19 UART 2 (UART2) */ + TC9_IRQn = 50, /**< 50 SAME70J19 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70J19 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70J19 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70J19 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70J19 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70J19 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70J19 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70J19 Pulse Width Modulation 1 (PWM1) */ + FPU_IRQn = 61, /**< 61 SAME70J19 Floating Point Unit Registers (FPU) */ + RSWDT_IRQn = 63, /**< 63 SAME70J19 Reinforced Secure Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 SAME70J19 System Control Registers (SystemControl) */ + CCF_IRQn = 65, /**< 65 SAME70J19 System Control Registers (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 SAME70J19 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 SAME70J19 Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 SAME70J19 Floating Point Unit Registers (FPU) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pvReserved15; + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pvReserved18; + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pvReserved21; + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pvReserved37; + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pvReserved41; + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pvReserved45; + void* pvReserved46; + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ + void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */ + void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */ + void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */ + void* pvReserved69; + void* pvReserved70; + void* pvReserved71; + void* pvReserved72; + void* pvReserved73; +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70J19 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70J19 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70J19 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70J19 does provide a FPU */ +#define __FPU_DP 1 /**< SAME70J19 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70J19 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70J19 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70J19 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70J19 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __SAM_M7_REVB 0 /**< SAME70J19 Revision A */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70J19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J19_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J19_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ssc.h" +#include "instance/tc0.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/pwm0.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/mcan0.h" +#include "instance/usbhs.h" +#include "instance/afec0.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/gmac.h" +#include "instance/tc3.h" +#include "instance/pwm1.h" +#include "instance/afec1.h" +#include "instance/aes.h" +#include "instance/trng.h" +#include "instance/xdmac.h" +#include "instance/qspi.h" +#include "instance/matrix.h" +#include "instance/utmi.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/piod.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +#include "instance/rswdt.h" +#include "instance/uart2.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J19_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ +#define ID_IXC (68) /**< \brief Floating Point Unit - IXC (ARM) */ + +#define ID_PERIPH_COUNT (74) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J19_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#else +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J19_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/same70j19.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x80000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (32u) +#define IRAM_SIZE (0x40000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA10D0A00UL) +#define CHIP_EXID (0x00000000UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (for Worst-Case Conditions) */ +#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70J19_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70j19b.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70j19b.h new file mode 100644 index 000000000..0f092299c --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70j19b.h @@ -0,0 +1,617 @@ +/** + * \file + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70J19B_ +#define _SAME70J19B_ + +/** \addtogroup SAME70J19B_definitions SAME70J19B definitions + This file defines all structures and symbols for SAME70J19B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70J19B */ +/* ************************************************************************** */ +/** \addtogroup SAME70J19B_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70J19B specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70J19B Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70J19B Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70J19B Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70J19B Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70J19B Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70J19B Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70J19B Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70J19B UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70J19B UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70J19B Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70J19B Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAME70J19B USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70J19B USART 1 (USART1) */ + PIOD_IRQn = 16, /**< 16 SAME70J19B Parallel I/O Controller D (PIOD) */ + TWIHS0_IRQn = 19, /**< 19 SAME70J19B Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70J19B Two Wire Interface 1 HS (TWIHS1) */ + SSC_IRQn = 22, /**< 22 SAME70J19B Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70J19B Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70J19B Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70J19B Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAME70J19B Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70J19B Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70J19B Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70J19B Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70J19B Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70J19B USB Host / Device Controller (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 SAME70J19B Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 SAME70J19B Controller Area Network (MCAN0) */ + GMAC_IRQn = 39, /**< 39 SAME70J19B Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70J19B Analog Front End 1 (AFEC1) */ + QSPI_IRQn = 43, /**< 43 SAME70J19B Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70J19B UART 2 (UART2) */ + TC9_IRQn = 50, /**< 50 SAME70J19B Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70J19B Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70J19B Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70J19B AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70J19B True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70J19B DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70J19B Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70J19B Pulse Width Modulation 1 (PWM1) */ + FPU_IRQn = 61, /**< 61 SAME70J19B Floating Point Unit Registers (FPU) */ + RSWDT_IRQn = 63, /**< 63 SAME70J19B Reinforced Secure Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 SAME70J19B System Control Registers (SystemControl) */ + CCF_IRQn = 65, /**< 65 SAME70J19B System Control Registers (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 SAME70J19B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 SAME70J19B Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 SAME70J19B Floating Point Unit Registers (FPU) */ + GMAC_Q3_IRQn = 71, /**< 71 SAME70J19B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q4_IRQn = 72, /**< 72 SAME70J19B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q5_IRQn = 73, /**< 73 SAME70J19B Gigabit Ethernet MAC (GMAC) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pvReserved15; + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pvReserved18; + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pvReserved21; + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pvReserved37; + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pvReserved41; + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pvReserved45; + void* pvReserved46; + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ + void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */ + void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */ + void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */ + void* pvReserved69; + void* pvReserved70; + void* pfnGMAC_Q3_Handler;/* 71 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q4_Handler;/* 72 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q5_Handler;/* 73 Gigabit Ethernet MAC (GMAC) */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void GMAC_Q3_Handler ( void ); +void GMAC_Q4_Handler ( void ); +void GMAC_Q5_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70J19B core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70J19B does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70J19B uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70J19B does provide a FPU */ +#define __FPU_DP 1 /**< SAME70J19B Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70J19B does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70J19B does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70J19B does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70J19B does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __SAM_M7_REVB 1 /**< SAME70J19 Revision B */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70J19B */ +/* ************************************************************************** */ +/** \addtogroup SAME70J19B_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70J19B */ +/* ************************************************************************** */ +/** \addtogroup SAME70J19B_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ssc.h" +#include "instance/tc0.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/pwm0.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/mcan0.h" +#include "instance/usbhs.h" +#include "instance/afec0.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/gmac.h" +#include "instance/tc3.h" +#include "instance/pwm1.h" +#include "instance/afec1.h" +#include "instance/aes.h" +#include "instance/trng.h" +#include "instance/xdmac.h" +#include "instance/qspi.h" +#include "instance/matrix.h" +#include "instance/utmi.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/piod.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +#include "instance/rswdt.h" +#include "instance/uart2.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70J19B */ +/* ************************************************************************** */ +/** \addtogroup SAME70J19B_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ +#define ID_IXC (68) /**< \brief Floating Point Unit - IXC (ARM) */ + +#define ID_PERIPH_COUNT (74) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70J19B */ +/* ************************************************************************** */ +/** \addtogroup SAME70J19B_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#else +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70J19B */ +/* ************************************************************************** */ +/** \addtogroup SAME70J19B_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/same70j19b.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70J19B */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x80000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (32u) +#define IRAM_SIZE (0x40000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70J19B */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA10D0A01UL) +#define CHIP_EXID (0x00000000UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70J19B */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (for Worst-Case Conditions) */ +#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70J19B_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70j20.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70j20.h new file mode 100644 index 000000000..d97fe83d4 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70j20.h @@ -0,0 +1,613 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70J20_ +#define _SAME70J20_ + +/** \addtogroup SAME70J20_definitions SAME70J20 definitions + This file defines all structures and symbols for SAME70J20: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J20_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70J20 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70J20 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70J20 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70J20 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70J20 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70J20 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70J20 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70J20 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70J20 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70J20 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70J20 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70J20 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAME70J20 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70J20 USART 1 (USART1) */ + PIOD_IRQn = 16, /**< 16 SAME70J20 Parallel I/O Controller D (PIOD) */ + TWIHS0_IRQn = 19, /**< 19 SAME70J20 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70J20 Two Wire Interface 1 HS (TWIHS1) */ + SSC_IRQn = 22, /**< 22 SAME70J20 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70J20 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70J20 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70J20 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAME70J20 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70J20 Digital-to-Analog Converter Controller (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70J20 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70J20 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70J20 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70J20 USB Host / Device Controller (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 SAME70J20 Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 SAME70J20 Controller Area Network (MCAN0) */ + GMAC_IRQn = 39, /**< 39 SAME70J20 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70J20 Analog Front End 1 (AFEC1) */ + QSPI_IRQn = 43, /**< 43 SAME70J20 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70J20 UART 2 (UART2) */ + TC9_IRQn = 50, /**< 50 SAME70J20 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70J20 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70J20 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70J20 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70J20 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70J20 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70J20 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70J20 Pulse Width Modulation 1 (PWM1) */ + FPU_IRQn = 61, /**< 61 SAME70J20 Floating Point Unit Registers (FPU) */ + RSWDT_IRQn = 63, /**< 63 SAME70J20 Reinforced Secure Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 SAME70J20 System Control Registers (SystemControl) */ + CCF_IRQn = 65, /**< 65 SAME70J20 System Control Registers (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 SAME70J20 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 SAME70J20 Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 SAME70J20 Floating Point Unit Registers (FPU) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pvReserved15; + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pvReserved18; + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pvReserved21; + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pvReserved37; + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pvReserved41; + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pvReserved45; + void* pvReserved46; + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ + void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */ + void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */ + void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */ + void* pvReserved69; + void* pvReserved70; + void* pvReserved71; + void* pvReserved72; + void* pvReserved73; +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70J20 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70J20 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70J20 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70J20 does provide a FPU */ +#define __FPU_DP 1 /**< SAME70J20 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70J20 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70J20 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70J20 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70J20 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __SAM_M7_REVB 0 /**< SAME70J20 Revision A */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70J20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J20_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J20_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ssc.h" +#include "instance/tc0.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/pwm0.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/mcan0.h" +#include "instance/usbhs.h" +#include "instance/afec0.h" +#include "instance/acc.h" +#include "instance/dacc.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/gmac.h" +#include "instance/tc3.h" +#include "instance/pwm1.h" +#include "instance/afec1.h" +#include "instance/aes.h" +#include "instance/trng.h" +#include "instance/xdmac.h" +#include "instance/qspi.h" +#include "instance/matrix.h" +#include "instance/utmi.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/piod.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +#include "instance/rswdt.h" +#include "instance/uart2.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J20_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital-to-Analog Converter Controller (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ +#define ID_IXC (68) /**< \brief Floating Point Unit - IXC (ARM) */ + +#define ID_PERIPH_COUNT (74) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J20_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#else +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J20_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/same70j20.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x100000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (2048u) +#define IFLASH_NB_OF_LOCK_BITS (64u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1020C00UL) +#define CHIP_EXID (0x00000000UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (for Worst-Case Conditions) */ +#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70J20_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70j20b.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70j20b.h new file mode 100644 index 000000000..bf82578b1 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70j20b.h @@ -0,0 +1,618 @@ +/** + * \file + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70J20B_ +#define _SAME70J20B_ + +/** \addtogroup SAME70J20B_definitions SAME70J20B definitions + This file defines all structures and symbols for SAME70J20B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70J20B */ +/* ************************************************************************** */ +/** \addtogroup SAME70J20B_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70J20B specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70J20B Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70J20B Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70J20B Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70J20B Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70J20B Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70J20B Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70J20B Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70J20B UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70J20B UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70J20B Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70J20B Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAME70J20B USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70J20B USART 1 (USART1) */ + PIOD_IRQn = 16, /**< 16 SAME70J20B Parallel I/O Controller D (PIOD) */ + TWIHS0_IRQn = 19, /**< 19 SAME70J20B Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70J20B Two Wire Interface 1 HS (TWIHS1) */ + SSC_IRQn = 22, /**< 22 SAME70J20B Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70J20B Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70J20B Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70J20B Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAME70J20B Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70J20B Digital-to-Analog Converter Controller (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70J20B Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70J20B Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70J20B Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70J20B USB Host / Device Controller (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 SAME70J20B Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 SAME70J20B Controller Area Network (MCAN0) */ + GMAC_IRQn = 39, /**< 39 SAME70J20B Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70J20B Analog Front End 1 (AFEC1) */ + QSPI_IRQn = 43, /**< 43 SAME70J20B Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70J20B UART 2 (UART2) */ + TC9_IRQn = 50, /**< 50 SAME70J20B Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70J20B Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70J20B Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70J20B AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70J20B True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70J20B DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70J20B Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70J20B Pulse Width Modulation 1 (PWM1) */ + FPU_IRQn = 61, /**< 61 SAME70J20B Floating Point Unit Registers (FPU) */ + RSWDT_IRQn = 63, /**< 63 SAME70J20B Reinforced Secure Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 SAME70J20B System Control Registers (SystemControl) */ + CCF_IRQn = 65, /**< 65 SAME70J20B System Control Registers (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 SAME70J20B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 SAME70J20B Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 SAME70J20B Floating Point Unit Registers (FPU) */ + GMAC_Q3_IRQn = 71, /**< 71 SAME70J20B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q4_IRQn = 72, /**< 72 SAME70J20B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q5_IRQn = 73, /**< 73 SAME70J20B Gigabit Ethernet MAC (GMAC) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pvReserved15; + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pvReserved18; + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pvReserved21; + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pvReserved37; + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pvReserved41; + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pvReserved45; + void* pvReserved46; + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ + void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */ + void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */ + void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */ + void* pvReserved69; + void* pvReserved70; + void* pfnGMAC_Q3_Handler;/* 71 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q4_Handler;/* 72 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q5_Handler;/* 73 Gigabit Ethernet MAC (GMAC) */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void GMAC_Q3_Handler ( void ); +void GMAC_Q4_Handler ( void ); +void GMAC_Q5_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70J20B core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70J20B does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70J20B uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70J20B does provide a FPU */ +#define __FPU_DP 1 /**< SAME70J20B Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70J20B does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70J20B does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70J20B does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70J20B does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __SAM_M7_REVB 1 /**< SAME70J20 Revision B */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70J20B */ +/* ************************************************************************** */ +/** \addtogroup SAME70J20B_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70J20B */ +/* ************************************************************************** */ +/** \addtogroup SAME70J20B_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ssc.h" +#include "instance/tc0.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/pwm0.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/mcan0.h" +#include "instance/usbhs.h" +#include "instance/afec0.h" +#include "instance/acc.h" +#include "instance/dacc.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/gmac.h" +#include "instance/tc3.h" +#include "instance/pwm1.h" +#include "instance/afec1.h" +#include "instance/aes.h" +#include "instance/trng.h" +#include "instance/xdmac.h" +#include "instance/qspi.h" +#include "instance/matrix.h" +#include "instance/utmi.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/piod.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +#include "instance/rswdt.h" +#include "instance/uart2.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70J20B */ +/* ************************************************************************** */ +/** \addtogroup SAME70J20B_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital-to-Analog Converter Controller (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ +#define ID_IXC (68) /**< \brief Floating Point Unit - IXC (ARM) */ + +#define ID_PERIPH_COUNT (74) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70J20B */ +/* ************************************************************************** */ +/** \addtogroup SAME70J20B_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#else +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70J20B */ +/* ************************************************************************** */ +/** \addtogroup SAME70J20B_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/same70j20b.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70J20B */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x100000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (2048u) +#define IFLASH_NB_OF_LOCK_BITS (64u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70J20B */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1020C01UL) +#define CHIP_EXID (0x00000000UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70J20B */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (for Worst-Case Conditions) */ +#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70J20B_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70j21.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70j21.h new file mode 100644 index 000000000..2fc89cdd9 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70j21.h @@ -0,0 +1,618 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70J21_ +#define _SAME70J21_ + +/** \addtogroup SAME70J21_definitions SAME70J21 definitions + This file defines all structures and symbols for SAME70J21: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J21_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70J21 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70J21 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70J21 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70J21 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70J21 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70J21 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70J21 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70J21 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70J21 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70J21 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70J21 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70J21 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAME70J20B USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70J20B USART 1 (USART1) */ + PIOD_IRQn = 16, /**< 16 SAME70J21 Parallel I/O Controller D (PIOD) */ + TWIHS0_IRQn = 19, /**< 19 SAME70J21 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70J21 Two Wire Interface 1 HS (TWIHS1) */ + SSC_IRQn = 22, /**< 22 SAME70J21 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70J21 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70J21 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70J21 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAME70J21 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70J21 Digital-to-Analog Converter Controller (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70J21 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70J21 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70J21 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70J21 USB Host / Device Controller (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 SAME70J21 Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 SAME70J21 Controller Area Network (MCAN0) */ + GMAC_IRQn = 39, /**< 39 SAME70J21 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70J21 Analog Front End 1 (AFEC1) */ + QSPI_IRQn = 43, /**< 43 SAME70J21 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70J21 UART 2 (UART2) */ + TC9_IRQn = 50, /**< 50 SAME70J21 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70J21 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70J21 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70J21 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70J21 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70J21 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70J21 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70J21 Pulse Width Modulation 1 (PWM1) */ + FPU_IRQn = 61, /**< 61 SAME70J21 Floating Point Unit Registers (FPU) */ + RSWDT_IRQn = 63, /**< 63 SAME70J21 Reinforced Secure Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 SAME70J21 System Control Registers (SystemControl) */ + CCF_IRQn = 65, /**< 65 SAME70J21 System Control Registers (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 SAME70J21 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 SAME70J21 Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 SAME70J21 Floating Point Unit Registers (FPU) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pvReserved15; + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pvReserved18; + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pvReserved21; + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pvReserved37; + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pvReserved41; + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pvReserved45; + void* pvReserved46; + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ + void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */ + void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */ + void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */ + void* pvReserved69; + void* pvReserved70; + void* pvReserved71; + void* pvReserved72; + void* pvReserved73; +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70J21 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70J21 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70J21 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70J21 does provide a FPU */ +#define __FPU_DP 1 /**< SAME70J21 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70J21 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70J21 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70J21 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70J21 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __SAM_M7_REVB 0 /**< SAME70J21 Revision A */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70J21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J21_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/dacc.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J21_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ssc.h" +#include "instance/tc0.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/pwm0.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/mcan0.h" +#include "instance/usbhs.h" +#include "instance/afec0.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/gmac.h" +#include "instance/tc3.h" +#include "instance/pwm1.h" +#include "instance/afec1.h" +#include "instance/aes.h" +#include "instance/trng.h" +#include "instance/xdmac.h" +#include "instance/qspi.h" +#include "instance/matrix.h" +#include "instance/utmi.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/piod.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +#include "instance/rswdt.h" +#include "instance/uart2.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J21_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital-to-Analog Converter Controller (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ +#define ID_IXC (68) /**< \brief Floating Point Unit - IXC (ARM) */ + +#define ID_PERIPH_COUNT (74) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J21_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#else +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70J21_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/same70j21.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x200000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (4096u) +#define IFLASH_NB_OF_LOCK_BITS (128u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1020E00UL) +#define CHIP_EXID (0x00000000UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (for Worst-Case Conditions) */ +#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70J21_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70j21b.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70j21b.h new file mode 100644 index 000000000..09f31b85e --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70j21b.h @@ -0,0 +1,625 @@ +/** + * \file + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70J21B_ +#define _SAME70J21B_ + +/** \addtogroup SAME70J21B_definitions SAME70J21B definitions + This file defines all structures and symbols for SAME70J21B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70J21B */ +/* ************************************************************************** */ +/** \addtogroup SAME70J21B_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70J21B specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70J21B Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70J21B Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70J21B Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70J21B Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70J21B Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70J21B Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70J21B Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70J21B UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70J21B UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70J21B Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70J21B Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAME70J20B USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70J20B USART 1 (USART1) */ + PIOD_IRQn = 16, /**< 16 SAME70J21B Parallel I/O Controller D (PIOD) */ + TWIHS0_IRQn = 19, /**< 19 SAME70J21B Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70J21B Two Wire Interface 1 HS (TWIHS1) */ + SSC_IRQn = 22, /**< 22 SAME70J21B Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70J21B Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70J21B Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70J21B Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAME70J21B Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70J21B Digital-to-Analog Converter Controller (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70J21B Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70J21B Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70J21B Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70J21B USB Host / Device Controller (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 SAME70J21B Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 SAME70J21B Controller Area Network (MCAN0) */ + GMAC_IRQn = 39, /**< 39 SAME70J21B Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70J21B Analog Front End 1 (AFEC1) */ + QSPI_IRQn = 43, /**< 43 SAME70J21B Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70J21B UART 2 (UART2) */ + TC9_IRQn = 50, /**< 50 SAME70J21B Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70J21B Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70J21B Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70J21B AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70J21B True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70J21B DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70J21B Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70J21B Pulse Width Modulation 1 (PWM1) */ + FPU_IRQn = 61, /**< 61 SAME70J21B Floating Point Unit Registers (FPU) */ + RSWDT_IRQn = 63, /**< 63 SAME70J21B Reinforced Secure Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 SAME70J21B System Control Registers (SystemControl) */ + CCF_IRQn = 65, /**< 65 SAME70J21B System Control Registers (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 SAME70J21B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 SAME70J21B Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 SAME70J21B Floating Point Unit Registers (FPU) */ + GMAC_Q3_IRQn = 71, /**< 71 SAME70J21B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q4_IRQn = 72, /**< 72 SAME70J21B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q5_IRQn = 73, /**< 73 SAME70J21B Gigabit Ethernet MAC (GMAC) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pvReserved15; + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pvReserved18; + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pvReserved21; + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pvReserved37; + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pvReserved41; + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pvReserved45; + void* pvReserved46; + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ + void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */ + void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */ + void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */ + void* pvReserved69; + void* pvReserved70; + void* pfnGMAC_Q3_Handler;/* 71 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q4_Handler;/* 72 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q5_Handler;/* 73 Gigabit Ethernet MAC (GMAC) */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void GMAC_Q3_Handler ( void ); +void GMAC_Q4_Handler ( void ); +void GMAC_Q5_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70J21B core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70J21B does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70J21B uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70J21B does provide a FPU */ +#define __FPU_DP 1 /**< SAME70J21B Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70J21B does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70J21B does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70J21B does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70J21B does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __SAM_M7_REVB 1 /**< SAME70J21 Revision B */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70J21B */ +/* ************************************************************************** */ +/** \addtogroup SAME70J21B_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/dacc.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70J21B */ +/* ************************************************************************** */ +/** \addtogroup SAME70J21B_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ssc.h" +#include "instance/tc0.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/pwm0.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/mcan0.h" +#include "instance/usbhs.h" +#include "instance/afec0.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/gmac.h" +#include "instance/tc3.h" +#include "instance/pwm1.h" +#include "instance/afec1.h" +#include "instance/aes.h" +#include "instance/trng.h" +#include "instance/xdmac.h" +#include "instance/qspi.h" +#include "instance/matrix.h" +#include "instance/utmi.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/piod.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +#include "instance/rswdt.h" +#include "instance/uart2.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70J21B */ +/* ************************************************************************** */ +/** \addtogroup SAME70J21B_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital-to-Analog Converter Controller (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ +#define ID_IXC (68) /**< \brief Floating Point Unit - IXC (ARM) */ + +#define ID_PERIPH_COUNT (74) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70J21B */ +/* ************************************************************************** */ +/** \addtogroup SAME70J21B_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#else +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70J21B */ +/* ************************************************************************** */ +/** \addtogroup SAME70J21B_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/same70j21b.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70J21B */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x200000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (4096u) +#define IFLASH_NB_OF_LOCK_BITS (128u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70J21B */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1020E01UL) +#define CHIP_EXID (0x00000000UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70J21B */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (for Worst-Case Conditions) */ +#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70J21B_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70n19.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70n19.h new file mode 100644 index 000000000..d2167035e --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70n19.h @@ -0,0 +1,657 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef _SAME70N19_ +#define _SAME70N19_ + +/** \addtogroup SAME70N19_definitions SAME70N19 definitions + This file defines all structures and symbols for SAME70N19: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N19_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70N19 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70N19 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70N19 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70N19 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70N19 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70N19 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70N19 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70N19 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70N19 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70N19 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70N19 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70N19 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAME70N19 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70N19 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70N19 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70N19 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAME70N19 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70N19 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70N19 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70N19 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70N19 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70N19 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70N19 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70N19 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAME70N19 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70N19 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70N19 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70N19 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70N19 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70N19 USB Host / Device Controller (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 SAME70N19 Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 SAME70N19 Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37, /**< 37 SAME70N19 Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38, /**< 38 SAME70N19 Controller Area Network (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70N19 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70N19 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAME70N19 Two Wire Interface 2 HS (TWIHS2) */ + QSPI_IRQn = 43, /**< 43 SAME70N19 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70N19 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70N19 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70N19 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAME70N19 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70N19 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70N19 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70N19 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70N19 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70N19 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70N19 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70N19 Pulse Width Modulation 1 (PWM1) */ + FPU_IRQn = 61, /**< 61 SAME70N19 Floating Point Unit Registers (FPU) */ + RSWDT_IRQn = 63, /**< 63 SAME70N19 Reinforced Secure Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 SAME70N19 System Control Registers (SystemControl) */ + CCF_IRQn = 65, /**< 65 SAME70N19 System Control Registers (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 SAME70N19 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 SAME70N19 Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 SAME70N19 Floating Point Unit Registers (FPU) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ + void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */ + void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */ + void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */ + void* pvReserved69; + void* pvReserved70; + void* pvReserved71; + void* pvReserved72; + void* pvReserved73; +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70N19 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70N19 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70N19 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70N19 does provide a FPU */ +#define __FPU_DP 1 /**< SAME70N19 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70N19 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70N19 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70N19 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70N19 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __SAM_M7_REVB 0 /**< SAME70N19 Revision A */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70N19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N19_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N19_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/hsmci.h" +#include "instance/ssc.h" +#include "instance/spi0.h" +#include "instance/tc0.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/pwm0.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/usart2.h" +#include "instance/mcan0.h" +#include "instance/mcan1.h" +#include "instance/usbhs.h" +#include "instance/afec0.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/gmac.h" +#include "instance/tc3.h" +#include "instance/pwm1.h" +#include "instance/twihs2.h" +#include "instance/afec1.h" +#include "instance/aes.h" +#include "instance/trng.h" +#include "instance/xdmac.h" +#include "instance/qspi.h" +#include "instance/matrix.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/piod.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +#include "instance/rswdt.h" +#include "instance/uart2.h" +#include "instance/uart3.h" +#include "instance/uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N19_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ +#define ID_IXC (68) /**< \brief Floating Point Unit - IXC (ARM) */ + +#define ID_PERIPH_COUNT (74) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N19_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N19_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/same70n19.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x80000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (32u) +#define IRAM_SIZE (0x40000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA10D0A00UL) +#define CHIP_EXID (0x00000001UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (for Worst-Case Conditions) */ +#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70N19_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70n19b.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70n19b.h new file mode 100644 index 000000000..d07ab6812 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70n19b.h @@ -0,0 +1,670 @@ +/** + * \file + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef _SAME70N19B_ +#define _SAME70N19B_ + +/** \addtogroup SAME70N19B_definitions SAME70N19B definitions + This file defines all structures and symbols for SAME70N19B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70N19B */ +/* ************************************************************************** */ +/** \addtogroup SAME70N19B_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70N19B specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70N19B Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70N19B Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70N19B Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70N19B Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70N19B Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70N19B Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70N19B Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70N19B UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70N19B UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70N19B Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70N19B Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAME70N19B USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70N19B USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70N19B USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70N19B Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAME70N19B Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70N19B Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70N19B Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70N19B Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70N19B Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70N19B Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70N19B Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70N19B Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAME70N19B Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70N19B Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70N19B Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70N19B Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70N19B Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70N19B USB Host / Device Controller (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 SAME70N19B Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 SAME70N19B Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37, /**< 37 SAME70N19B Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38, /**< 38 SAME70N19B Controller Area Network (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70N19B Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70N19B Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAME70N19B Two Wire Interface 2 HS (TWIHS2) */ + QSPI_IRQn = 43, /**< 43 SAME70N19B Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70N19B UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70N19B UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70N19B UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAME70N19B Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70N19B Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70N19B Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70N19B AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70N19B True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70N19B DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70N19B Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70N19B Pulse Width Modulation 1 (PWM1) */ + FPU_IRQn = 61, /**< 61 SAME70N19B Floating Point Unit Registers (FPU) */ + RSWDT_IRQn = 63, /**< 63 SAME70N19B Reinforced Secure Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 SAME70N19B System Control Registers (SystemControl) */ + CCF_IRQn = 65, /**< 65 SAME70N19B System Control Registers (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 SAME70N19B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 SAME70N19B Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 SAME70N19B Floating Point Unit Registers (FPU) */ + I2SC0_IRQn = 69, /**< 69 SAME70N19B Inter-IC Sound Controller (I2SC0) */ + GMAC_Q3_IRQn = 71, /**< 71 SAME70N19B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q4_IRQn = 72, /**< 72 SAME70N19B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q5_IRQn = 73, /**< 73 SAME70N19B Gigabit Ethernet MAC (GMAC) */ + + PERIPH_COUNT_IRQn = 71 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ + void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */ + void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */ + void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */ + void* pfnI2SC0_Handler; /* 69 Inter-IC Sound Controller (I2SC0) */ + void* pvReserved70; + void* pfnGMAC_Q3_Handler;/* 71 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q4_Handler;/* 72 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q5_Handler;/* 73 Gigabit Ethernet MAC (GMAC) */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void I2SC0_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void GMAC_Q3_Handler ( void ); +void GMAC_Q4_Handler ( void ); +void GMAC_Q5_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70N19B core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70N19B does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70N19B uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70N19B does provide a FPU */ +#define __FPU_DP 1 /**< SAME70N19B Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70N19B does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70N19B does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70N19B does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70N19B does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __SAM_M7_REVB 1 /**< SAME70N19 Revision B */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70N19B */ +/* ************************************************************************** */ +/** \addtogroup SAME70N19B_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/i2sc.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70N19B */ +/* ************************************************************************** */ +/** \addtogroup SAME70N19B_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/hsmci.h" +#include "instance/ssc.h" +#include "instance/spi0.h" +#include "instance/tc0.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/pwm0.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/usart2.h" +#include "instance/mcan0.h" +#include "instance/mcan1.h" +#include "instance/usbhs.h" +#include "instance/afec0.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/gmac.h" +#include "instance/tc3.h" +#include "instance/pwm1.h" +#include "instance/twihs2.h" +#include "instance/afec1.h" +#include "instance/aes.h" +#include "instance/trng.h" +#include "instance/xdmac.h" +#include "instance/qspi.h" +#include "instance/matrix.h" +#include "instance/i2sc0.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/piod.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +#include "instance/rswdt.h" +#include "instance/uart2.h" +#include "instance/uart3.h" +#include "instance/uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70N19B */ +/* ************************************************************************** */ +/** \addtogroup SAME70N19B_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ +#define ID_IXC (68) /**< \brief Floating Point Unit - IXC (ARM) */ +#define ID_I2SC0 (69) /**< \brief Inter-IC Sound controller (I2SC0) */ + +#define ID_PERIPH_COUNT (74) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70N19B */ +/* ************************************************************************** */ +/** \addtogroup SAME70N19B_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define I2SC0 (0x4008C000U) /**< \brief (I2SC0 ) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define I2SC0 ((I2sc *)0x4008C000U) /**< \brief (I2SC0 ) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70N19B */ +/* ************************************************************************** */ +/** \addtogroup SAME70N19B_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/same70n19b.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70N19B */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x80000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (32u) +#define IRAM_SIZE (0x40000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70N19B */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA10D0A01UL) +#define CHIP_EXID (0x00000001UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70N19B */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (for Worst-Case Conditions) */ +#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70N19B_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70n20.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70n20.h new file mode 100644 index 000000000..56eb89e4c --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70n20.h @@ -0,0 +1,659 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70N20_ +#define _SAME70N20_ + +/** \addtogroup SAME70N20_definitions SAME70N20 definitions + This file defines all structures and symbols for SAME70N20: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N20_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70N20 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70N20 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70N20 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70N20 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70N20 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70N20 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70N20 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70N20 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70N20 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70N20 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70N20 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70N20 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAME70N20 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70N20 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70N20 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70N20 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAME70N20 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70N20 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70N20 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70N20 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70N20 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70N20 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70N20 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70N20 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAME70N20 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70N20 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70N20 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70N20 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70N20 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70N20 USB Host / Device Controller (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 SAME70N20 Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 SAME70N20 Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37, /**< 37 SAME70N20 Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38, /**< 38 SAME70N20 Controller Area Network (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70N20 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70N20 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAME70N20 Two Wire Interface 2 HS (TWIHS2) */ + QSPI_IRQn = 43, /**< 43 SAME70N20 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70N20 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70N20 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70N20 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAME70N20 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70N20 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70N20 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70N20 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70N20 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70N20 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70N20 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70N20 Pulse Width Modulation 1 (PWM1) */ + FPU_IRQn = 61, /**< 61 SAME70N20 Floating Point Unit Registers (FPU) */ + RSWDT_IRQn = 63, /**< 63 SAME70N20 Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 SAME70N20 System Control Registers (SystemControl) */ + CCF_IRQn = 65, /**< 65 SAME70N20 System Control Registers (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 SAME70N20 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 SAME70N20 Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 SAME70N20 Floating Point Unit Registers (FPU) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */ + void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */ + void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */ + void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */ + void* pvReserved69; + void* pvReserved70; + void* pvReserved71; + void* pvReserved72; + void* pvReserved73; +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70N20 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70N20 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70N20 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70N20 does provide a FPU */ +#define __FPU_DP 1 /**< SAME70N20 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70N20 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70N20 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70N20 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70N20 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __SAM_M7_REVB 0 /**< SAME70N20 Revision A */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70N20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N20_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N20_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/hsmci.h" +#include "instance/ssc.h" +#include "instance/spi0.h" +#include "instance/tc0.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/pwm0.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/usart2.h" +#include "instance/mcan0.h" +#include "instance/mcan1.h" +#include "instance/usbhs.h" +#include "instance/afec0.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/gmac.h" +#include "instance/tc3.h" +#include "instance/pwm1.h" +#include "instance/twihs2.h" +#include "instance/afec1.h" +#include "instance/aes.h" +#include "instance/trng.h" +#include "instance/xdmac.h" +#include "instance/qspi.h" +#include "instance/matrix.h" +#include "instance/utmi.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/piod.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +#include "instance/rswdt.h" +#include "instance/uart2.h" +#include "instance/uart3.h" +#include "instance/uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N20_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ +#define ID_IXC (68) /**< \brief Floating Point Unit - IXC (ARM) */ + +#define ID_PERIPH_COUNT (74) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N20_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N20_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/same70n20.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x100000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (2048u) +#define IFLASH_NB_OF_LOCK_BITS (64u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1020C00UL) +#define CHIP_EXID (0x00000001UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (for Worst-Case Conditions) */ +#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70N20_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70n20b.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70n20b.h new file mode 100644 index 000000000..a509cc7dc --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70n20b.h @@ -0,0 +1,672 @@ +/** + * \file + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70N20B_ +#define _SAME70N20B_ + +/** \addtogroup SAME70N20B_definitions SAME70N20B definitions + This file defines all structures and symbols for SAME70N20B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70N20B */ +/* ************************************************************************** */ +/** \addtogroup SAME70N20B_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70N20B specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70N20B Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70N20B Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70N20B Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70N20B Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70N20B Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70N20B Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70N20B Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70N20B UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70N20B UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70N20B Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70N20B Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAME70N20B USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70N20B USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70N20B USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70N20B Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAME70N20B Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70N20B Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70N20B Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70N20B Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70N20B Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70N20B Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70N20B Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70N20B Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAME70N20B Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70N20B Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70N20B Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70N20B Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70N20B Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70N20B USB Host / Device Controller (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 SAME70N20B Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 SAME70N20B Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37, /**< 37 SAME70N20B Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38, /**< 38 SAME70N20B Controller Area Network (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70N20B Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70N20B Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAME70N20B Two Wire Interface 2 HS (TWIHS2) */ + QSPI_IRQn = 43, /**< 43 SAME70N20B Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70N20B UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70N20B UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70N20B UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAME70N20B Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70N20B Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70N20B Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70N20B AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70N20B True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70N20B DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70N20B Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70N20B Pulse Width Modulation 1 (PWM1) */ + FPU_IRQn = 61, /**< 61 SAME70N20B Floating Point Unit Registers (FPU) */ + RSWDT_IRQn = 63, /**< 63 SAME70N20B Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 SAME70N20B System Control Registers (SystemControl) */ + CCF_IRQn = 65, /**< 65 SAME70N20B System Control Registers (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 SAME70N20B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 SAME70N20B Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 SAME70N20B Floating Point Unit Registers (FPU) */ + I2SC0_IRQn = 69, /**< 69 SAME70N20B Inter-IC Sound Controller (I2SC0) */ + GMAC_Q3_IRQn = 71, /**< 71 SAME70N20B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q4_IRQn = 72, /**< 72 SAME70N20B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q5_IRQn = 73, /**< 73 SAME70N20B Gigabit Ethernet MAC (GMAC) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */ + void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */ + void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */ + void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */ + void* pfnI2SC0_Handler; /* 69 Inter-IC Sound Controller (I2SC0) */ + void* pvReserved70; + void* pfnGMAC_Q3_Handler;/* 71 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q4_Handler;/* 72 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q5_Handler;/* 73 Gigabit Ethernet MAC (GMAC) */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void I2SC0_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void GMAC_Q3_Handler ( void ); +void GMAC_Q4_Handler ( void ); +void GMAC_Q5_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70N20B core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70N20B does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70N20B uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70N20B does provide a FPU */ +#define __FPU_DP 1 /**< SAME70N20B Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70N20B does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70N20B does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70N20B does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70N20B does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __SAM_M7_REVB 1 /**< SAME70N20 Revision B */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70N20B */ +/* ************************************************************************** */ +/** \addtogroup SAME70N20B_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/i2sc.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70N20B */ +/* ************************************************************************** */ +/** \addtogroup SAME70N20B_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/hsmci.h" +#include "instance/ssc.h" +#include "instance/spi0.h" +#include "instance/tc0.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/pwm0.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/usart2.h" +#include "instance/mcan0.h" +#include "instance/mcan1.h" +#include "instance/usbhs.h" +#include "instance/afec0.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/gmac.h" +#include "instance/tc3.h" +#include "instance/pwm1.h" +#include "instance/twihs2.h" +#include "instance/afec1.h" +#include "instance/aes.h" +#include "instance/trng.h" +#include "instance/xdmac.h" +#include "instance/qspi.h" +#include "instance/matrix.h" +#include "instance/i2sc0.h" +#include "instance/utmi.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/piod.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +#include "instance/rswdt.h" +#include "instance/uart2.h" +#include "instance/uart3.h" +#include "instance/uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70N20B */ +/* ************************************************************************** */ +/** \addtogroup SAME70N20B_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ +#define ID_IXC (68) /**< \brief Floating Point Unit - IXC (ARM) */ +#define ID_I2SC0 (69) /**< \brief Inter-IC Sound controller (I2SC0) */ + +#define ID_PERIPH_COUNT (74) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70N20B */ +/* ************************************************************************** */ +/** \addtogroup SAME70N20B_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define I2SC0 (0x4008C000U) /**< \brief (I2SC0 ) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define I2SC0 ((I2sc *)0x4008C000U) /**< \brief (I2SC0 ) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70N20B */ +/* ************************************************************************** */ +/** \addtogroup SAME70N20B_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/same70n20b.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x100000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (2048u) +#define IFLASH_NB_OF_LOCK_BITS (64u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70N20B */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1020C01UL) +#define CHIP_EXID (0x00000001UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70N20B */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (for Worst-Case Conditions) */ +#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70N20B_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70n21.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70n21.h new file mode 100644 index 000000000..18a81d14f --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70n21.h @@ -0,0 +1,657 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70N21_ +#define _SAME70N21_ + +/** \addtogroup SAME70N21_definitions SAME70N21 definitions + This file defines all structures and symbols for SAME70N21: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N21_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70N21 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70N21 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70N21 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70N21 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70N21 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70N21 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70N21 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70N21 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70N21 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70N21 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70N21 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70N21 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAME70N21 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70N21 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70N21 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70N21 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAME70N21 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70N21 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70N21 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70N21 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70N21 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70N21 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70N21 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70N21 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAME70N21 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70N21 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70N21 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70N21 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70N21 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70N21 USB Host / Device Controller (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 SAME70N21 Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 SAME70N21 Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37, /**< 37 SAME70N21 Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38, /**< 38 SAME70N21 Controller Area Network (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70N21 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70N21 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAME70N21 Two Wire Interface 2 HS (TWIHS2) */ + QSPI_IRQn = 43, /**< 43 SAME70N21 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70N21 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70N21 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70N21 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAME70N21 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70N21 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70N21 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70N21 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70N21 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70N21 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70N21 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70N21 Pulse Width Modulation 1 (PWM1) */ + FPU_IRQn = 61, /**< 61 SAME70N21 Floating Point Unit Registers (FPU) */ + RSWDT_IRQn = 63, /**< 63 SAME70N21 Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 SAME70N21 System Control Registers (SystemControl) */ + CCF_IRQn = 65, /**< 65 SAME70N21 System Control Registers (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 SAME70N21 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 SAME70N21 Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 SAME70N21 Floating Point Unit Registers (FPU) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */ + void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */ + void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */ + void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */ + void* pvReserved69; + void* pvReserved70; + void* pvReserved71; + void* pvReserved72; + void* pvReserved73; +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70N21 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70N21 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70N21 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70N21 does provide a FPU */ +#define __FPU_DP 1 /**< SAME70N21 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70N21 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70N21 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70N21 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70N21 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __SAM_M7_REVB 0 /**< SAME70N21 Revision A */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70N21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N21_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N21_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/hsmci.h" +#include "instance/ssc.h" +#include "instance/spi0.h" +#include "instance/tc0.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/pwm0.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/usart2.h" +#include "instance/mcan0.h" +#include "instance/mcan1.h" +#include "instance/usbhs.h" +#include "instance/afec0.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/gmac.h" +#include "instance/tc3.h" +#include "instance/pwm1.h" +#include "instance/twihs2.h" +#include "instance/afec1.h" +#include "instance/aes.h" +#include "instance/trng.h" +#include "instance/xdmac.h" +#include "instance/qspi.h" +#include "instance/matrix.h" +#include "instance/utmi.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/piod.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +#include "instance/rswdt.h" +#include "instance/uart2.h" +#include "instance/uart3.h" +#include "instance/uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N21_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ +#define ID_IXC (68) /**< \brief Floating Point Unit - IXC (ARM) */ + +#define ID_PERIPH_COUNT (74) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N21_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70N21_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/same70n21.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x200000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (4096u) +#define IFLASH_NB_OF_LOCK_BITS (128u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1020E00UL) +#define CHIP_EXID (0x00000001UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (for Worst-Case Conditions) */ +#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70N21_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70n21b.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70n21b.h new file mode 100644 index 000000000..def3ded21 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70n21b.h @@ -0,0 +1,670 @@ +/** + * \file + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70N21B_ +#define _SAME70N21B_ + +/** \addtogroup SAME70N21B_definitions SAME70N21B definitions + This file defines all structures and symbols for SAME70N21B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70N21B */ +/* ************************************************************************** */ +/** \addtogroup SAME70N21B_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70N21B specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70N21B Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70N21B Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70N21B Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70N21B Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70N21B Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70N21B Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70N21B Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70N21B UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70N21B UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70N21B Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70N21B Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAME70N21B USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70N21B USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70N21B USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70N21B Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAME70N21B Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70N21B Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70N21B Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70N21B Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70N21B Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70N21B Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70N21B Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70N21B Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAME70N21B Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70N21B Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70N21B Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70N21B Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70N21B Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70N21B USB Host / Device Controller (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 SAME70N21B Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 SAME70N21B Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37, /**< 37 SAME70N21B Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38, /**< 38 SAME70N21B Controller Area Network (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70N21B Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70N21B Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAME70N21B Two Wire Interface 2 HS (TWIHS2) */ + QSPI_IRQn = 43, /**< 43 SAME70N21B Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70N21B UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70N21B UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70N21B UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAME70N21B Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70N21B Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70N21B Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70N21B AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70N21B True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70N21B DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70N21B Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70N21B Pulse Width Modulation 1 (PWM1) */ + FPU_IRQn = 61, /**< 61 SAME70N21B Floating Point Unit Registers (FPU) */ + RSWDT_IRQn = 63, /**< 63 SAME70N21B Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 SAME70N21B System Control Registers (SystemControl) */ + CCF_IRQn = 65, /**< 65 SAME70N21B System Control Registers (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 SAME70N21B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 SAME70N21B Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 SAME70N21B Floating Point Unit Registers (FPU) */ + I2SC0_IRQn = 69, /**< 69 SAME70N21B Inter-IC Sound Controller (I2SC0) */ + GMAC_Q3_IRQn = 71, /**< 71 SAME70N21B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q4_IRQn = 72, /**< 72 SAME70N21B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q5_IRQn = 73, /**< 73 SAME70N21B Gigabit Ethernet MAC (GMAC) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */ + void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */ + void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */ + void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */ + void* pfnI2SC0_Handler; /* 69 Inter-IC Sound Controller (I2SC0) */ + void* pvReserved70; + void* pfnGMAC_Q3_Handler;/* 71 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q4_Handler;/* 72 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q5_Handler;/* 73 Gigabit Ethernet MAC (GMAC) */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void I2SC0_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void GMAC_Q3_Handler ( void ); +void GMAC_Q4_Handler ( void ); +void GMAC_Q5_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70N21B core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70N21B does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70N21B uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70N21B does provide a FPU */ +#define __FPU_DP 1 /**< SAME70N21B Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70N21B does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70N21B does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70N21B does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70N21B does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __SAM_M7_REVB 1 /**< SAME70N21 Revision B */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70N21B */ +/* ************************************************************************** */ +/** \addtogroup SAME70N21B_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/i2sc.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70N21B */ +/* ************************************************************************** */ +/** \addtogroup SAME70N21B_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/hsmci.h" +#include "instance/ssc.h" +#include "instance/spi0.h" +#include "instance/tc0.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/pwm0.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/usart2.h" +#include "instance/mcan0.h" +#include "instance/mcan1.h" +#include "instance/usbhs.h" +#include "instance/afec0.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/gmac.h" +#include "instance/tc3.h" +#include "instance/pwm1.h" +#include "instance/twihs2.h" +#include "instance/afec1.h" +#include "instance/aes.h" +#include "instance/trng.h" +#include "instance/xdmac.h" +#include "instance/qspi.h" +#include "instance/matrix.h" +#include "instance/i2sc0.h" +#include "instance/utmi.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/piod.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +#include "instance/rswdt.h" +#include "instance/uart2.h" +#include "instance/uart3.h" +#include "instance/uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70N21B */ +/* ************************************************************************** */ +/** \addtogroup SAME70N21B_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ +#define ID_IXC (68) /**< \brief Floating Point Unit - IXC (ARM) */ +#define ID_I2SC0 (69) /**< \brief Inter-IC Sound controller (I2SC0) */ + +#define ID_PERIPH_COUNT (74) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70N21B */ +/* ************************************************************************** */ +/** \addtogroup SAME70N21B_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define I2SC0 (0x4008C000U) /**< \brief (I2SC0 ) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define I2SC0 ((I2sc *)0x4008C000U) /**< \brief (I2SC0 ) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70N21B */ +/* ************************************************************************** */ +/** \addtogroup SAME70N21B_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/same70n21b.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x200000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (4096u) +#define IFLASH_NB_OF_LOCK_BITS (128u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70N21B */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1020E01UL) +#define CHIP_EXID (0x00000001UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70N21B */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (for Worst-Case Conditions) */ +#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70N21B_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70q19.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70q19.h new file mode 100644 index 000000000..de5eb57b8 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70q19.h @@ -0,0 +1,715 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef _SAME70Q19_ +#define _SAME70Q19_ + +/** \addtogroup SAME70Q19_definitions SAME70Q19 definitions + This file defines all structures and symbols for SAME70Q19: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q19_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70Q19 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70Q19 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70Q19 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70Q19 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70Q19 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70Q19 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70Q19 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70Q19 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70Q19 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70Q19 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70Q19 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70Q19 Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 12, /**< 12 SAME70Q19 Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 13, /**< 13 SAME70Q19 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70Q19 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70Q19 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70Q19 Parallel I/O Controller D (PIOD) */ + PIOE_IRQn = 17, /**< 17 SAME70Q19 Parallel I/O Controller E (PIOE) */ + HSMCI_IRQn = 18, /**< 18 SAME70Q19 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70Q19 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70Q19 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70Q19 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70Q19 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70Q19 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70Q19 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70Q19 Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAME70Q19 Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAME70Q19 Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAME70Q19 Timer/Counter 5 (TC5) */ + AFEC0_IRQn = 29, /**< 29 SAME70Q19 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70Q19 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70Q19 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70Q19 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70Q19 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70Q19 USB Host / Device Controller (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 SAME70Q19 Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 SAME70Q19 Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37, /**< 37 SAME70Q19 Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38, /**< 38 SAME70Q19 Controller Area Network (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70Q19 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70Q19 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAME70Q19 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAME70Q19 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAME70Q19 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70Q19 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70Q19 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70Q19 UART 4 (UART4) */ + TC6_IRQn = 47, /**< 47 SAME70Q19 Timer/Counter 6 (TC6) */ + TC7_IRQn = 48, /**< 48 SAME70Q19 Timer/Counter 7 (TC7) */ + TC8_IRQn = 49, /**< 49 SAME70Q19 Timer/Counter 8 (TC8) */ + TC9_IRQn = 50, /**< 50 SAME70Q19 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70Q19 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70Q19 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70Q19 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70Q19 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70Q19 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70Q19 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70Q19 Pulse Width Modulation 1 (PWM1) */ + FPU_IRQn = 61, /**< 61 SAME70Q19 Floating Point Unit Registers (FPU) */ + SDRAMC_IRQn = 62, /**< 62 SAME70Q19 SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 SAME70Q19 Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 SAME70Q19 System Control Registers (SystemControl) */ + CCF_IRQn = 65, /**< 65 SAME70Q19 System Control Registers (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 SAME70Q19 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 SAME70Q19 Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 SAME70Q19 Floating Point Unit Registers (FPU) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */ + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pfnTC6_Handler; /* 47 Timer/Counter 6 */ + void* pfnTC7_Handler; /* 48 Timer/Counter 7 */ + void* pfnTC8_Handler; /* 49 Timer/Counter 8 */ + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */ + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller (SDRAMC) */ + void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */ + void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */ + void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */ + void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */ + void* pvReserved69; + void* pvReserved70; + void* pvReserved71; + void* pvReserved72; + void* pvReserved73; +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70Q19 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70Q19 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70Q19 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70Q19 does provide a FPU */ +#define __FPU_DP 1 /**< SAME70Q19 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70Q19 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70Q19 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70Q19 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70Q19 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __SAM_M7_REVB 0 /**< SAME70Q19 Revision A */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q19_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/sdramc.h" +#include "component/smc.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q19_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/hsmci.h" +#include "instance/ssc.h" +#include "instance/spi0.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/pwm0.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/usart2.h" +#include "instance/mcan0.h" +#include "instance/mcan1.h" +#include "instance/usbhs.h" +#include "instance/afec0.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/gmac.h" +#include "instance/tc3.h" +#include "instance/spi1.h" +#include "instance/pwm1.h" +#include "instance/twihs2.h" +#include "instance/afec1.h" +#include "instance/aes.h" +#include "instance/trng.h" +#include "instance/xdmac.h" +#include "instance/qspi.h" +#include "instance/smc.h" +#include "instance/sdramc.h" +#include "instance/matrix.h" +#include "instance/utmi.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/pioc.h" +#include "instance/piod.h" +#include "instance/pioe.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +#include "instance/rswdt.h" +#include "instance/uart2.h" +#include "instance/uart3.h" +#include "instance/uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q19_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */ +#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */ +#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ +#define ID_IXC (68) /**< \brief Floating Point Unit - IXC (ARM) */ + +#define ID_PERIPH_COUNT (74) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q19_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q19_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/same70q19.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x80000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (32u) +#define IRAM_SIZE (0x40000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA10D0A00UL) +#define CHIP_EXID (0x00000002UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (for Worst-Case Conditions) */ +#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70Q19_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70q19b.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70q19b.h new file mode 100644 index 000000000..6247670e8 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70q19b.h @@ -0,0 +1,734 @@ +/** + * \file + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ +#ifndef _SAME70Q19B_ +#define _SAME70Q19B_ + +/** \addtogroup SAME70Q19B_definitions SAME70Q19B definitions + This file defines all structures and symbols for SAME70Q19B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70Q19B */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q19B_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70Q19B specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70Q19B Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70Q19B Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70Q19B Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70Q19B Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70Q19B Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70Q19B Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70Q19B Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70Q19B UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70Q19B UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70Q19B Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70Q19B Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 12, /**< 12 SAME70Q19B Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 13, /**< 13 SAME70Q19B USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70Q19B USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70Q19B USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70Q19B Parallel I/O Controller D (PIOD) */ + PIOE_IRQn = 17, /**< 17 SAME70Q19B Parallel I/O Controller E (PIOE) */ + HSMCI_IRQn = 18, /**< 18 SAME70Q19B Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70Q19B Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70Q19B Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70Q19B Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70Q19B Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70Q19B Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70Q19B Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70Q19B Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAME70Q19B Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAME70Q19B Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAME70Q19B Timer/Counter 5 (TC5) */ + AFEC0_IRQn = 29, /**< 29 SAME70Q19B Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70Q19B Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70Q19B Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70Q19B Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70Q19B Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70Q19B USB Host / Device Controller (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 SAME70Q19B Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 SAME70Q19B Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37, /**< 37 SAME70Q19B Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38, /**< 38 SAME70Q19B Controller Area Network (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70Q19B Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70Q19B Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAME70Q19B Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAME70Q19B Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAME70Q19B Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70Q19B UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70Q19B UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70Q19B UART 4 (UART4) */ + TC6_IRQn = 47, /**< 47 SAME70Q19B Timer/Counter 6 (TC6) */ + TC7_IRQn = 48, /**< 48 SAME70Q19B Timer/Counter 7 (TC7) */ + TC8_IRQn = 49, /**< 49 SAME70Q19B Timer/Counter 8 (TC8) */ + TC9_IRQn = 50, /**< 50 SAME70Q19B Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70Q19B Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70Q19B Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70Q19B AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70Q19B True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70Q19B DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70Q19B Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70Q19B Pulse Width Modulation 1 (PWM1) */ + FPU_IRQn = 61, /**< 61 SAME70Q19B Floating Point Unit Registers (FPU) */ + SDRAMC_IRQn = 62, /**< 62 SAME70Q19B SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 SAME70Q19B Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 SAME70Q19B System Control Registers (SystemControl) */ + CCF_IRQn = 65, /**< 65 SAME70Q19B System Control Registers (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 SAME70Q19B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 SAME70Q19B Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 SAME70Q19B Floating Point Unit Registers (FPU) */ + I2SC0_IRQn = 69, /**< 69 SAME70Q19B Inter-IC Sound Controller (I2SC0) */ + I2SC1_IRQn = 70, /**< 70 SAME70Q19B Inter-IC Sound Controller (I2SC1) */ + GMAC_Q3_IRQn = 71, /**< 71 SAME70Q19B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q4_IRQn = 72, /**< 72 SAME70Q19B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q5_IRQn = 73, /**< 73 SAME70Q19B Gigabit Ethernet MAC (GMAC) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */ + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pfnTC6_Handler; /* 47 Timer/Counter 6 */ + void* pfnTC7_Handler; /* 48 Timer/Counter 7 */ + void* pfnTC8_Handler; /* 49 Timer/Counter 8 */ + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */ + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller (SDRAMC) */ + void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */ + void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */ + void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */ + void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */ + void* pfnI2SC0_Handler; /* 69 Inter-IC Sound Controller (I2SC0) */ + void* pfnI2SC1_Handler; /* 70 Inter-IC Sound Controller (I2SC1) */ + void* pfnGMAC_Q3_Handler;/* 71 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q4_Handler;/* 72 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q5_Handler;/* 73 Gigabit Ethernet MAC (GMAC) */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void I2SC0_Handler ( void ); +void I2SC1_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void GMAC_Q3_Handler ( void ); +void GMAC_Q4_Handler ( void ); +void GMAC_Q5_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70Q19B core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70Q19B does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70Q19B uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70Q19B does provide a FPU */ +#define __FPU_DP 1 /**< SAME70Q19B Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70Q19B does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70Q19B does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70Q19B does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70Q19B does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __SAM_M7_REVB 1 /**< SAME70Q19 Revision B */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70Q19B */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q19B_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/i2sc.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/sdramc.h" +#include "component/smc.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70Q19B */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q19B_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/hsmci.h" +#include "instance/ssc.h" +#include "instance/spi0.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/pwm0.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/usart2.h" +#include "instance/mcan0.h" +#include "instance/mcan1.h" +#include "instance/usbhs.h" +#include "instance/afec0.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/gmac.h" +#include "instance/tc3.h" +#include "instance/spi1.h" +#include "instance/pwm1.h" +#include "instance/twihs2.h" +#include "instance/afec1.h" +#include "instance/aes.h" +#include "instance/trng.h" +#include "instance/xdmac.h" +#include "instance/qspi.h" +#include "instance/smc.h" +#include "instance/sdramc.h" +#include "instance/matrix.h" +#include "instance/i2sc0.h" +#include "instance/i2sc1.h" +#include "instance/utmi.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/pioc.h" +#include "instance/piod.h" +#include "instance/pioe.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +#include "instance/rswdt.h" +#include "instance/uart2.h" +#include "instance/uart3.h" +#include "instance/uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70Q19B */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q19B_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */ +#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */ +#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ +#define ID_IXC (68) /**< \brief Floating Point Unit - IXC (ARM) */ +#define ID_I2SC0 (69) /**< \brief Inter-IC Sound controller (I2SC0) */ +#define ID_I2SC1 (70) /**< \brief Inter-IC Sound controller (I2SC1) */ + +#define ID_PERIPH_COUNT (74) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70Q19B */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q19B_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define I2SC0 (0x4008C000U) /**< \brief (I2SC0 ) Base Address */ +#define I2SC1 (0x40090000U) /**< \brief (I2SC1 ) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define I2SC0 ((I2sc *)0x4008C000U) /**< \brief (I2SC0 ) Base Address */ +#define I2SC1 ((I2sc *)0x40090000U) /**< \brief (I2SC1 ) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70Q19B */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q19B_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/same70q19b.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70Q19B */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x80000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (32u) +#define IRAM_SIZE (0x40000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70Q19B */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA10D0A01UL) +#define CHIP_EXID (0x00000002UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70Q19B */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (for Worst-Case Conditions) */ +#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70Q19B_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70q20.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70q20.h new file mode 100644 index 000000000..e75560e0f --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70q20.h @@ -0,0 +1,716 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70Q20_ +#define _SAME70Q20_ + +/** \addtogroup SAME70Q20_definitions SAME70Q20 definitions + This file defines all structures and symbols for SAME70Q20: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q20_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70Q20 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70Q20 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70Q20 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70Q20 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70Q20 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70Q20 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70Q20 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70Q20 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70Q20 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70Q20 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70Q20 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70Q20 Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 12, /**< 12 SAME70Q20 Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 13, /**< 13 SAME70Q20 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70Q20 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70Q20 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70Q20 Parallel I/O Controller D (PIOD) */ + PIOE_IRQn = 17, /**< 17 SAME70Q20 Parallel I/O Controller E (PIOE) */ + HSMCI_IRQn = 18, /**< 18 SAME70Q20 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70Q20 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70Q20 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70Q20 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70Q20 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70Q20 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70Q20 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70Q20 Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAME70Q20 Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAME70Q20 Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAME70Q20 Timer/Counter 5 (TC5) */ + AFEC0_IRQn = 29, /**< 29 SAME70Q20 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70Q20 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70Q20 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70Q20 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70Q20 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70Q20 USB Host / Device Controller (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 SAME70Q20 Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 SAME70Q20 Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37, /**< 37 SAME70Q20 Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38, /**< 38 SAME70Q20 Controller Area Network (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70Q20 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70Q20 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAME70Q20 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAME70Q20 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAME70Q20 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70Q20 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70Q20 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70Q20 UART 4 (UART4) */ + TC6_IRQn = 47, /**< 47 SAME70Q20 Timer/Counter 6 (TC6) */ + TC7_IRQn = 48, /**< 48 SAME70Q20 Timer/Counter 7 (TC7) */ + TC8_IRQn = 49, /**< 49 SAME70Q20 Timer/Counter 8 (TC8) */ + TC9_IRQn = 50, /**< 50 SAME70Q20 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70Q20 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70Q20 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70Q20 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70Q20 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70Q20 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70Q20 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70Q20 Pulse Width Modulation 1 (PWM1) */ + FPU_IRQn = 61, /**< 61 SAME70Q20 Floating Point Unit Registers (FPU) */ + SDRAMC_IRQn = 62, /**< 62 SAME70Q20 SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 SAME70Q20 Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 SAME70Q20 System Control Registers (SystemControl) */ + CCF_IRQn = 65, /**< 65 SAME70Q20 System Control Registers (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 SAME70Q20 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 SAME70Q20 Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 SAME70Q20 Floating Point Unit Registers (FPU) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */ + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pfnTC6_Handler; /* 47 Timer/Counter 6 */ + void* pfnTC7_Handler; /* 48 Timer/Counter 7 */ + void* pfnTC8_Handler; /* 49 Timer/Counter 8 */ + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */ + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller (SDRAMC) */ + void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */ + void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */ + void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */ + void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */ + void* pvReserved69; + void* pvReserved70; + void* pvReserved71; + void* pvReserved72; + void* pvReserved73; +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70Q20 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70Q20 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70Q20 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70Q20 does provide a FPU */ +#define __FPU_DP 1 /**< SAME70Q20 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70Q20 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70Q20 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70Q20 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70Q20 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __SAM_M7_REVB 0 /**< SAME70Q20 Revision A */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q20_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/sdramc.h" +#include "component/smc.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q20_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/hsmci.h" +#include "instance/ssc.h" +#include "instance/spi0.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/pwm0.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/usart2.h" +#include "instance/mcan0.h" +#include "instance/mcan1.h" +#include "instance/usbhs.h" +#include "instance/afec0.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/gmac.h" +#include "instance/tc3.h" +#include "instance/spi1.h" +#include "instance/pwm1.h" +#include "instance/twihs2.h" +#include "instance/afec1.h" +#include "instance/aes.h" +#include "instance/trng.h" +#include "instance/xdmac.h" +#include "instance/qspi.h" +#include "instance/smc.h" +#include "instance/sdramc.h" +#include "instance/matrix.h" +#include "instance/utmi.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/pioc.h" +#include "instance/piod.h" +#include "instance/pioe.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +#include "instance/rswdt.h" +#include "instance/uart2.h" +#include "instance/uart3.h" +#include "instance/uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q20_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */ +#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */ +#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ +#define ID_IXC (68) /**< \brief Floating Point Unit - IXC (ARM) */ + +#define ID_PERIPH_COUNT (74) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q20_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q20_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/same70q20.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x100000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (2048u) +#define IFLASH_NB_OF_LOCK_BITS (64u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1020C01UL) +#define CHIP_EXID (0x00000002UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (for Worst-Case Conditions) */ +#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70Q20_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70q20b.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70q20b.h new file mode 100644 index 000000000..f4803cb05 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70q20b.h @@ -0,0 +1,736 @@ +/** + * \file + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70Q20B_ +#define _SAME70Q20B_ + +/** \addtogroup SAME70Q20B_definitions SAME70Q20B definitions + This file defines all structures and symbols for SAME70Q20B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70Q20B */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q20B_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70Q20B specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70Q20B Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70Q20B Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70Q20B Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70Q20B Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70Q20B Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70Q20B Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70Q20B Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70Q20B UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70Q20B UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70Q20B Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70Q20B Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 12, /**< 12 SAME70Q20B Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 13, /**< 13 SAME70Q20B USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70Q20B USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70Q20B USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70Q20B Parallel I/O Controller D (PIOD) */ + PIOE_IRQn = 17, /**< 17 SAME70Q20B Parallel I/O Controller E (PIOE) */ + HSMCI_IRQn = 18, /**< 18 SAME70Q20B Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70Q20B Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70Q20B Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70Q20B Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70Q20B Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70Q20B Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70Q20B Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70Q20B Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAME70Q20B Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAME70Q20B Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAME70Q20B Timer/Counter 5 (TC5) */ + AFEC0_IRQn = 29, /**< 29 SAME70Q20B Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70Q20B Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70Q20B Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70Q20B Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70Q20B Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70Q20B USB Host / Device Controller (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 SAME70Q20B Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 SAME70Q20B Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37, /**< 37 SAME70Q20B Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38, /**< 38 SAME70Q20B Controller Area Network (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70Q20B Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70Q20B Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAME70Q20B Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAME70Q20B Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAME70Q20B Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70Q20B UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70Q20B UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70Q20B UART 4 (UART4) */ + TC6_IRQn = 47, /**< 47 SAME70Q20B Timer/Counter 6 (TC6) */ + TC7_IRQn = 48, /**< 48 SAME70Q20B Timer/Counter 7 (TC7) */ + TC8_IRQn = 49, /**< 49 SAME70Q20B Timer/Counter 8 (TC8) */ + TC9_IRQn = 50, /**< 50 SAME70Q20B Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70Q20B Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70Q20B Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70Q20B AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70Q20B True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70Q20B DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70Q20B Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70Q20B Pulse Width Modulation 1 (PWM1) */ + FPU_IRQn = 61, /**< 61 SAME70Q20B Floating Point Unit Registers (FPU) */ + SDRAMC_IRQn = 62, /**< 62 SAME70Q20B SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 SAME70Q20B Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 SAME70Q20B System Control Registers (SystemControl) */ + CCF_IRQn = 65, /**< 65 SAME70Q20B System Control Registers (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 SAME70Q20B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 SAME70Q20B Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 SAME70Q20B Floating Point Unit Registers (FPU) */ + I2SC0_IRQn = 69, /**< 69 SAME70Q20B Inter-IC Sound Controller (I2SC0) */ + I2SC1_IRQn = 70, /**< 70 SAME70Q20B Inter-IC Sound Controller (I2SC1) */ + GMAC_Q3_IRQn = 71, /**< 71 SAME70Q20B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q4_IRQn = 72, /**< 72 SAME70Q20B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q5_IRQn = 73, /**< 73 SAME70Q20B Gigabit Ethernet MAC (GMAC) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */ + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pfnTC6_Handler; /* 47 Timer/Counter 6 */ + void* pfnTC7_Handler; /* 48 Timer/Counter 7 */ + void* pfnTC8_Handler; /* 49 Timer/Counter 8 */ + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */ + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller (SDRAMC) */ + void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */ + void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */ + void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */ + void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */ + void* pfnI2SC0_Handler; /* 69 Inter-IC Sound Controller (I2SC0) */ + void* pfnI2SC1_Handler; /* 70 Inter-IC Sound Controller (I2SC1) */ + void* pfnGMAC_Q3_Handler;/* 71 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q4_Handler;/* 72 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q5_Handler;/* 73 Gigabit Ethernet MAC (GMAC) */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void I2SC0_Handler ( void ); +void I2SC1_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void GMAC_Q3_Handler ( void ); +void GMAC_Q4_Handler ( void ); +void GMAC_Q5_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70Q20B core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70Q20B does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70Q20B uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70Q20B does provide a FPU */ +#define __FPU_DP 1 /**< SAME70Q20B Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70Q20B does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70Q20B does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70Q20B does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70Q20B does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __SAM_M7_REVB 1 /**< SAME70Q20 Revision B */ + +/* + * \brief CMSIS includes + */ + +#include +#include // Added by Inertial Sense +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70Q20B */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q20B_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/i2sc.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/sdramc.h" +#include "component/smc.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70Q20B */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q20B_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/hsmci.h" +#include "instance/ssc.h" +#include "instance/spi0.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/pwm0.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/usart2.h" +#include "instance/mcan0.h" +#include "instance/mcan1.h" +#include "instance/usbhs.h" +#include "instance/afec0.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/gmac.h" +#include "instance/tc3.h" +#include "instance/spi1.h" +#include "instance/pwm1.h" +#include "instance/twihs2.h" +#include "instance/afec1.h" +#include "instance/aes.h" +#include "instance/trng.h" +#include "instance/xdmac.h" +#include "instance/qspi.h" +#include "instance/smc.h" +#include "instance/sdramc.h" +#include "instance/matrix.h" +#include "instance/i2sc0.h" +#include "instance/i2sc1.h" +#include "instance/utmi.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/pioc.h" +#include "instance/piod.h" +#include "instance/pioe.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +#include "instance/rswdt.h" +#include "instance/uart2.h" +#include "instance/uart3.h" +#include "instance/uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70Q20B */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q20B_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */ +#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */ +#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ +#define ID_IXC (68) /**< \brief Floating Point Unit - IXC (ARM) */ +#define ID_I2SC0 (69) /**< \brief Inter-IC Sound controller (I2SC0) */ +#define ID_I2SC1 (70) /**< \brief Inter-IC Sound controller (I2SC1) */ + +#define ID_PERIPH_COUNT (74) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70Q20B */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q20B_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define I2SC0 (0x4008C000U) /**< \brief (I2SC0 ) Base Address */ +#define I2SC1 (0x40090000U) /**< \brief (I2SC1 ) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define I2SC0 ((I2sc *)0x4008C000U) /**< \brief (I2SC0 ) Base Address */ +#define I2SC1 ((I2sc *)0x40090000U) /**< \brief (I2SC1 ) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70Q20B */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q20B_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/same70q20b.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70Q20B */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x100000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (2048u) +#define IFLASH_NB_OF_LOCK_BITS (64u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70Q20B */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1020C01UL) +#define CHIP_EXID (0x00000002UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70Q20B */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (for Worst-Case Conditions) */ +#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70Q20B_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70q21.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70q21.h new file mode 100644 index 000000000..c9c59d3f7 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70q21.h @@ -0,0 +1,716 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70Q21_ +#define _SAME70Q21_ + +/** \addtogroup SAME70Q21_definitions SAME70Q21 definitions + This file defines all structures and symbols for SAME70Q21: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q21_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70Q21 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70Q21 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70Q21 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70Q21 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70Q21 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70Q21 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70Q21 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70Q21 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70Q21 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70Q21 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70Q21 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70Q21 Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 12, /**< 12 SAME70Q21 Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 13, /**< 13 SAME70Q21 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70Q21 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70Q21 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70Q21 Parallel I/O Controller D (PIOD) */ + PIOE_IRQn = 17, /**< 17 SAME70Q21 Parallel I/O Controller E (PIOE) */ + HSMCI_IRQn = 18, /**< 18 SAME70Q21 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70Q21 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70Q21 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70Q21 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70Q21 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70Q21 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70Q21 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70Q21 Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAME70Q21 Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAME70Q21 Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAME70Q21 Timer/Counter 5 (TC5) */ + AFEC0_IRQn = 29, /**< 29 SAME70Q21 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70Q21 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70Q21 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70Q21 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70Q21 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70Q21 USB Host / Device Controller (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 SAME70Q21 Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 SAME70Q21 Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37, /**< 37 SAME70Q21 Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38, /**< 38 SAME70Q21 Controller Area Network (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70Q21 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70Q21 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAME70Q21 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAME70Q21 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAME70Q21 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70Q21 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70Q21 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70Q21 UART 4 (UART4) */ + TC6_IRQn = 47, /**< 47 SAME70Q21 Timer/Counter 6 (TC6) */ + TC7_IRQn = 48, /**< 48 SAME70Q21 Timer/Counter 7 (TC7) */ + TC8_IRQn = 49, /**< 49 SAME70Q21 Timer/Counter 8 (TC8) */ + TC9_IRQn = 50, /**< 50 SAME70Q21 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70Q21 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70Q21 Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70Q21 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70Q21 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70Q21 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70Q21 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70Q21 Pulse Width Modulation 1 (PWM1) */ + FPU_IRQn = 61, /**< 61 SAME70Q21 Floating Point Unit Registers (FPU) */ + SDRAMC_IRQn = 62, /**< 62 SAME70Q21 SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 SAME70Q21 Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 SAME70Q21 System Control Registers (SystemControl) */ + CCF_IRQn = 65, /**< 65 SAME70Q21 System Control Registers (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 SAME70Q21 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 SAME70Q21 Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 SAME70Q21 Floating Point Unit Registers (FPU) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */ + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pfnTC6_Handler; /* 47 Timer/Counter 6 */ + void* pfnTC7_Handler; /* 48 Timer/Counter 7 */ + void* pfnTC8_Handler; /* 49 Timer/Counter 8 */ + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */ + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller (SDRAMC) */ + void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */ + void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */ + void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */ + void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */ + void* pvReserved69; + void* pvReserved70; + void* pvReserved71; + void* pvReserved72; + void* pvReserved73; +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70Q21 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70Q21 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70Q21 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70Q21 does provide a FPU */ +#define __FPU_DP 1 /**< SAME70Q21 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70Q21 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70Q21 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70Q21 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70Q21 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __SAM_M7_REVB 0 /**< SAME70Q21 Revision A */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q21_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/sdramc.h" +#include "component/smc.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q21_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/hsmci.h" +#include "instance/ssc.h" +#include "instance/spi0.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/pwm0.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/usart2.h" +#include "instance/mcan0.h" +#include "instance/mcan1.h" +#include "instance/usbhs.h" +#include "instance/afec0.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/gmac.h" +#include "instance/tc3.h" +#include "instance/spi1.h" +#include "instance/pwm1.h" +#include "instance/twihs2.h" +#include "instance/afec1.h" +#include "instance/aes.h" +#include "instance/trng.h" +#include "instance/xdmac.h" +#include "instance/qspi.h" +#include "instance/smc.h" +#include "instance/sdramc.h" +#include "instance/matrix.h" +#include "instance/utmi.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/pioc.h" +#include "instance/piod.h" +#include "instance/pioe.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +#include "instance/rswdt.h" +#include "instance/uart2.h" +#include "instance/uart3.h" +#include "instance/uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q21_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */ +#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */ +#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ +#define ID_IXC (68) /**< \brief Floating Point Unit - IXC (ARM) */ + +#define ID_PERIPH_COUNT (74) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q21_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q21_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/same70q21.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x200000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (4096u) +#define IFLASH_NB_OF_LOCK_BITS (128u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1020E00UL) +#define CHIP_EXID (0x00000002UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (for Worst-Case Conditions) */ +#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70Q21_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70q21b.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70q21b.h new file mode 100644 index 000000000..e433f198c --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/include/same70q21b.h @@ -0,0 +1,735 @@ +/** + * \file + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAME70Q21B_ +#define _SAME70Q21B_ + +/** \addtogroup SAME70Q21B_definitions SAME70Q21B definitions + This file defines all structures and symbols for SAME70Q21B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70Q21B */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q21B_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAME70Q21B specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAME70Q21B Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAME70Q21B Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAME70Q21B Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAME70Q21B Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAME70Q21B Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAME70Q21B Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAME70Q21B Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAME70Q21B UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAME70Q21B UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAME70Q21B Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAME70Q21B Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 12, /**< 12 SAME70Q21B Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 13, /**< 13 SAME70Q21B USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAME70Q21B USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAME70Q21B USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAME70Q21B Parallel I/O Controller D (PIOD) */ + PIOE_IRQn = 17, /**< 17 SAME70Q21B Parallel I/O Controller E (PIOE) */ + HSMCI_IRQn = 18, /**< 18 SAME70Q21B Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAME70Q21B Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAME70Q21B Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAME70Q21B Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAME70Q21B Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAME70Q21B Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAME70Q21B Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAME70Q21B Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAME70Q21B Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAME70Q21B Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAME70Q21B Timer/Counter 5 (TC5) */ + AFEC0_IRQn = 29, /**< 29 SAME70Q21B Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAME70Q21B Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAME70Q21B Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAME70Q21B Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAME70Q21B Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAME70Q21B USB Host / Device Controller (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 SAME70Q21B Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 SAME70Q21B Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37, /**< 37 SAME70Q21B Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38, /**< 38 SAME70Q21B Controller Area Network (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAME70Q21B Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAME70Q21B Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAME70Q21B Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAME70Q21B Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAME70Q21B Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAME70Q21B UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAME70Q21B UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAME70Q21B UART 4 (UART4) */ + TC6_IRQn = 47, /**< 47 SAME70Q21B Timer/Counter 6 (TC6) */ + TC7_IRQn = 48, /**< 48 SAME70Q21B Timer/Counter 7 (TC7) */ + TC8_IRQn = 49, /**< 49 SAME70Q21B Timer/Counter 8 (TC8) */ + TC9_IRQn = 50, /**< 50 SAME70Q21B Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAME70Q21B Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAME70Q21B Timer/Counter 11 (TC11) */ + AES_IRQn = 56, /**< 56 SAME70Q21B AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAME70Q21B True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAME70Q21B DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAME70Q21B Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAME70Q21B Pulse Width Modulation 1 (PWM1) */ + FPU_IRQn = 61, /**< 61 SAME70Q21B Floating Point Unit Registers (FPU) */ + SDRAMC_IRQn = 62, /**< 62 SAME70Q21B SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 SAME70Q21B Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 SAME70Q21B System Control Registers (SystemControl) */ + CCF_IRQn = 65, /**< 65 SAME70Q21B System Control Registers (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 SAME70Q21B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 SAME70Q21B Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 SAME70Q21B Floating Point Unit Registers (FPU) */ + I2SC0_IRQn = 69, /**< 69 SAME70Q21B Inter-IC Sound Controller (I2SC0) */ + I2SC1_IRQn = 70, /**< 70 SAME70Q21B Inter-IC Sound Controller (I2SC1) */ + GMAC_Q3_IRQn = 71, /**< 71 SAME70Q21B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q4_IRQn = 72, /**< 72 SAME70Q21B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q5_IRQn = 73, /**< 73 SAME70Q21B Gigabit Ethernet MAC (GMAC) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */ + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pfnTC6_Handler; /* 47 Timer/Counter 6 */ + void* pfnTC7_Handler; /* 48 Timer/Counter 7 */ + void* pfnTC8_Handler; /* 49 Timer/Counter 8 */ + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pfnFPU_Handler; /* 61 Floating Point Unit Registers (FPU) */ + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller (SDRAMC) */ + void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */ + void* pfnCCW_Handler; /* 64 System Control Registers (SystemControl) */ + void* pfnCCF_Handler; /* 65 System Control Registers (SystemControl) */ + void* pfnGMAC_Q1_Handler;/* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler;/* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit Registers (FPU) */ + void* pfnI2SC0_Handler; /* 69 Inter-IC Sound Controller (I2SC0) */ + void* pfnI2SC1_Handler; /* 70 Inter-IC Sound Controller (I2SC1) */ + void* pfnGMAC_Q3_Handler;/* 71 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q4_Handler;/* 72 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q5_Handler;/* 73 Gigabit Ethernet MAC (GMAC) */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void I2SC0_Handler ( void ); +void I2SC1_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void GMAC_Q3_Handler ( void ); +void GMAC_Q4_Handler ( void ); +void GMAC_Q5_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAME70Q21B core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAME70Q21B does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAME70Q21B uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAME70Q21B does provide a FPU */ +#define __FPU_DP 1 /**< SAME70Q21B Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAME70Q21B does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAME70Q21B does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAME70Q21B does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAME70Q21B does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __SAM_M7_REVB 1 /**< SAME70Q21 Revision B */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70Q21B */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q21B_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/i2sc.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/sdramc.h" +#include "component/smc.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70Q21B */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q21B_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/hsmci.h" +#include "instance/ssc.h" +#include "instance/spi0.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/pwm0.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/usart2.h" +#include "instance/mcan0.h" +#include "instance/mcan1.h" +#include "instance/usbhs.h" +#include "instance/afec0.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/gmac.h" +#include "instance/tc3.h" +#include "instance/spi1.h" +#include "instance/pwm1.h" +#include "instance/twihs2.h" +#include "instance/afec1.h" +#include "instance/aes.h" +#include "instance/trng.h" +#include "instance/xdmac.h" +#include "instance/qspi.h" +#include "instance/smc.h" +#include "instance/sdramc.h" +#include "instance/matrix.h" +#include "instance/i2sc0.h" +#include "instance/i2sc1.h" +#include "instance/utmi.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/pioc.h" +#include "instance/piod.h" +#include "instance/pioe.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +#include "instance/rswdt.h" +#include "instance/uart2.h" +#include "instance/uart3.h" +#include "instance/uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70Q21B */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q21B_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */ +#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */ +#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ +#define ID_IXC (68) /**< \brief Floating Point Unit - IXC (ARM) */ +#define ID_I2SC0 (69) /**< \brief Inter-IC Sound controller (I2SC0) */ +#define ID_I2SC1 (70) /**< \brief Inter-IC Sound controller (I2SC1) */ + +#define ID_PERIPH_COUNT (74) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70Q21B */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q21B_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define I2SC0 (0x4008C000U) /**< \brief (I2SC0 ) Base Address */ +#define I2SC1 (0x40090000U) /**< \brief (I2SC1 ) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define I2SC0 ((I2sc *)0x4008C000U) /**< \brief (I2SC0 ) Base Address */ +#define I2SC1 ((I2sc *)0x40090000U) /**< \brief (I2SC1 ) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70Q21B */ +/* ************************************************************************** */ +/** \addtogroup SAME70Q21B_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/same70q21b.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70Q21B */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x200000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (8192u) +#define IFLASH_NB_OF_PAGES (4096u) +#define IFLASH_NB_OF_LOCK_BITS (128u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAME70Q21B */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1020E01UL) +#define CHIP_EXID (0x00000002UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME70Q21B */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (for Worst-Case Conditions) */ +#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAME70Q21B_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/source/templates/gcc/startup_same70.c b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/source/templates/gcc/startup_same70.c new file mode 100644 index 000000000..e8b360cba --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/source/templates/gcc/startup_same70.c @@ -0,0 +1,432 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "same70.h" + +#if __FPU_USED /* CMSIS defined value to indicate usage of FPU */ +#include "fpu.h" +#endif + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M7 core handlers */ +void NMI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemManage_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMon_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void SUPC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EFC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOA_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef _SAME70_PIOC_INSTANCE_ +void PIOC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_PIOC_INSTANCE_ */ +#ifdef _SAME70_USART0_INSTANCE_ +void USART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_USART0_INSTANCE_ */ +#ifdef _SAME70_USART1_INSTANCE_ +void USART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_USART1_INSTANCE_ */ +#ifdef _SAME70_USART2_INSTANCE_ +void USART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_USART2_INSTANCE_ */ +void PIOD_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef _SAME70_PIOE_INSTANCE_ +void PIOE_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_PIOE_INSTANCE_ */ +#ifdef _SAME70_HSMCI_INSTANCE_ +void HSMCI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_HSMCI_INSTANCE_ */ +void TWIHS0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef _SAME70_SPI0_INSTANCE_ +void SPI0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_SPI0_INSTANCE_ */ +void SSC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef _SAME70_TC1_INSTANCE_ +void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_TC1_INSTANCE_ */ +#ifdef _SAME70_TC1_INSTANCE_ +void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_TC1_INSTANCE_ */ +#ifdef _SAME70_TC1_INSTANCE_ +void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_TC1_INSTANCE_ */ +void AFEC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef _SAME70_DACC_INSTANCE_ +void DACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_DACC_INSTANCE_ */ +void PWM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USBHS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef _SAME70_MCAN1_INSTANCE_ +void MCAN1_INT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN1_INT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_MCAN1_INSTANCE_ */ +void GMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AFEC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef _SAME70_TWIHS2_INSTANCE_ +void TWIHS2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_TWIHS2_INSTANCE_ */ +#ifdef _SAME70_SPI1_INSTANCE_ +void SPI1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_SPI1_INSTANCE_ */ +void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef _SAME70_UART3_INSTANCE_ +void UART3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_UART3_INSTANCE_ */ +#ifdef _SAME70_UART4_INSTANCE_ +void UART4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_UART4_INSTANCE_ */ +#ifdef _SAME70_TC2_INSTANCE_ +void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_TC2_INSTANCE_ */ +#ifdef _SAME70_TC2_INSTANCE_ +void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_TC2_INSTANCE_ */ +#ifdef _SAME70_TC2_INSTANCE_ +void TC8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_TC2_INSTANCE_ */ +void TC9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void XDMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ISI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void FPU_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef _SAME70_SDRAMC_INSTANCE_ +void SDRAMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_SDRAMC_INSTANCE_ */ +void RSWDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void CCW_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void CCF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void IXC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef _SAME70_I2SC0_INSTANCE_ +void I2SC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_I2SC0_INSTANCE_ */ +#ifdef _SAME70_I2SC1_INSTANCE_ +void I2SC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAME70_I2SC1_INSTANCE_ */ +#if (__SAM_M7_REVB == 1) +void GMAC_Q3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNMI_Handler = (void*) NMI_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemManage_Handler = (void*) MemManage_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pfnReserved1_Handler = (void*) (0UL), /* Reserved */ + .pfnReserved2_Handler = (void*) (0UL), /* Reserved */ + .pfnReserved3_Handler = (void*) (0UL), /* Reserved */ + .pfnReserved4_Handler = (void*) (0UL), /* Reserved */ + .pfnSVC_Handler = (void*) SVC_Handler, + .pfnDebugMon_Handler = (void*) DebugMon_Handler, + .pfnReserved5_Handler = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnSUPC_Handler = (void*) SUPC_Handler, /* 0 Supply Controller */ + .pfnRSTC_Handler = (void*) RSTC_Handler, /* 1 Reset Controller */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 2 Real Time Clock */ + .pfnRTT_Handler = (void*) RTT_Handler, /* 3 Real Time Timer */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 4 Watchdog Timer */ + .pfnPMC_Handler = (void*) PMC_Handler, /* 5 Power Management Controller */ + .pfnEFC_Handler = (void*) EFC_Handler, /* 6 Enhanced Embedded Flash Controller */ + .pfnUART0_Handler = (void*) UART0_Handler, /* 7 UART 0 */ + .pfnUART1_Handler = (void*) UART1_Handler, /* 8 UART 1 */ + .pvReserved9 = (void*) (0UL), /* 9 Reserved */ + .pfnPIOA_Handler = (void*) PIOA_Handler, /* 10 Parallel I/O Controller A */ + .pfnPIOB_Handler = (void*) PIOB_Handler, /* 11 Parallel I/O Controller B */ +#ifdef _SAME70_PIOC_INSTANCE_ + .pfnPIOC_Handler = (void*) PIOC_Handler, /* 12 Parallel I/O Controller C */ +#else + .pvReserved12 = (void*) (0UL), /* 12 Reserved */ +#endif /* _SAME70_PIOC_INSTANCE_ */ +#ifdef _SAME70_USART0_INSTANCE_ + .pfnUSART0_Handler = (void*) USART0_Handler, /* 13 USART 0 */ +#else + .pvReserved13 = (void*) (0UL), /* 13 Reserved */ +#endif /* _SAME70_USART0_INSTANCE_ */ +#ifdef _SAME70_USART1_INSTANCE_ + .pfnUSART1_Handler = (void*) USART1_Handler, /* 14 USART 1 */ +#else + .pvReserved14 = (void*) (0UL), /* 14 Reserved */ +#endif /* _SAME70_USART1_INSTANCE_ */ +#ifdef _SAME70_USART2_INSTANCE_ + .pfnUSART2_Handler = (void*) USART2_Handler, /* 15 USART 2 */ +#else + .pvReserved15 = (void*) (0UL), /* 15 Reserved */ +#endif /* _SAME70_USART2_INSTANCE_ */ + .pfnPIOD_Handler = (void*) PIOD_Handler, /* 16 Parallel I/O Controller D */ +#ifdef _SAME70_PIOE_INSTANCE_ + .pfnPIOE_Handler = (void*) PIOE_Handler, /* 17 Parallel I/O Controller E */ +#else + .pvReserved17 = (void*) (0UL), /* 17 Reserved */ +#endif /* _SAME70_PIOE_INSTANCE_ */ +#ifdef _SAME70_HSMCI_INSTANCE_ + .pfnHSMCI_Handler = (void*) HSMCI_Handler, /* 18 Multimedia Card Interface */ +#else + .pvReserved18 = (void*) (0UL), /* 18 Reserved */ +#endif /* _SAME70_HSMCI_INSTANCE_ */ + .pfnTWIHS0_Handler = (void*) TWIHS0_Handler, /* 19 Two Wire Interface 0 HS */ + .pfnTWIHS1_Handler = (void*) TWIHS1_Handler, /* 20 Two Wire Interface 1 HS */ +#ifdef _SAME70_SPI0_INSTANCE_ + .pfnSPI0_Handler = (void*) SPI0_Handler, /* 21 Serial Peripheral Interface 0 */ +#else + .pvReserved21 = (void*) (0UL), /* 21 Reserved */ +#endif /* _SAME70_SPI0_INSTANCE_ */ + .pfnSSC_Handler = (void*) SSC_Handler, /* 22 Synchronous Serial Controller */ + .pfnTC0_Handler = (void*) TC0_Handler, /* 23 Timer/Counter 0 */ + .pfnTC1_Handler = (void*) TC1_Handler, /* 24 Timer/Counter 1 */ + .pfnTC2_Handler = (void*) TC2_Handler, /* 25 Timer/Counter 2 */ +#ifdef _SAME70_TC1_INSTANCE_ + .pfnTC3_Handler = (void*) TC3_Handler, /* 26 Timer/Counter 3 */ +#else + .pvReserved26 = (void*) (0UL), /* 26 Reserved */ +#endif /* _SAME70_TC1_INSTANCE_ */ +#ifdef _SAME70_TC1_INSTANCE_ + .pfnTC4_Handler = (void*) TC4_Handler, /* 27 Timer/Counter 4 */ +#else + .pvReserved27 = (void*) (0UL), /* 27 Reserved */ +#endif /* _SAME70_TC1_INSTANCE_ */ +#ifdef _SAME70_TC1_INSTANCE_ + .pfnTC5_Handler = (void*) TC5_Handler, /* 28 Timer/Counter 5 */ +#else + .pvReserved28 = (void*) (0UL), /* 28 Reserved */ +#endif /* _SAME70_TC1_INSTANCE_ */ + .pfnAFEC0_Handler = (void*) AFEC0_Handler, /* 29 Analog Front End 0 */ +#ifdef _SAME70_DACC_INSTANCE_ + .pfnDACC_Handler = (void*) DACC_Handler, /* 30 Digital To Analog Converter */ +#else + .pvReserved30 = (void*) (0UL), /* 30 Reserved */ +#endif /* _SAME70_DACC_INSTANCE_ */ + .pfnPWM0_Handler = (void*) PWM0_Handler, /* 31 Pulse Width Modulation 0 */ + .pfnICM_Handler = (void*) ICM_Handler, /* 32 Integrity Check Monitor */ + .pfnACC_Handler = (void*) ACC_Handler, /* 33 Analog Comparator */ + .pfnUSBHS_Handler = (void*) USBHS_Handler, /* 34 USB Host / Device Controller */ + .pfnMCAN0_INT0_Handler = (void*) MCAN0_INT0_Handler, /* 35 Controller Area Network */ + .pfnMCAN0_INT1_Handler = (void*) MCAN0_INT1_Handler, /* 36 Controller Area Network */ +#ifdef _SAME70_MCAN1_INSTANCE_ + .pfnMCAN1_INT0_Handler = (void*) MCAN1_INT0_Handler, /* 37 Controller Area Network */ + .pfnMCAN1_INT1_Handler = (void*) MCAN1_INT1_Handler, /* 38 Controller Area Network */ +#else + .pvReserved37 = (void*) (0UL), /* 37 Reserved */ + .pvReserved38 = (void*) (0UL), /* 38 Reserved */ +#endif /* _SAME70_MCAN1_INSTANCE_ */ + .pfnGMAC_Handler = (void*) GMAC_Handler, /* 39 Ethernet MAC */ + .pfnAFEC1_Handler = (void*) AFEC1_Handler, /* 40 Analog Front End 1 */ +#ifdef _SAME70_TWIHS2_INSTANCE_ + .pfnTWIHS2_Handler = (void*) TWIHS2_Handler, /* 41 Two Wire Interface 2 HS */ +#else + .pvReserved41 = (void*) (0UL), /* 41 Reserved */ +#endif /* _SAME70_TWIHS2_INSTANCE_ */ +#ifdef _SAME70_SPI1_INSTANCE_ + .pfnSPI1_Handler = (void*) SPI1_Handler, /* 42 Serial Peripheral Interface 1 */ +#else + .pvReserved42 = (void*) (0UL), /* 42 Reserved */ +#endif /* _SAME70_SPI1_INSTANCE_ */ + .pfnQSPI_Handler = (void*) QSPI_Handler, /* 43 Quad I/O Serial Peripheral Interface */ + .pfnUART2_Handler = (void*) UART2_Handler, /* 44 UART 2 */ +#ifdef _SAME70_UART3_INSTANCE_ + .pfnUART3_Handler = (void*) UART3_Handler, /* 45 UART 3 */ +#else + .pvReserved45 = (void*) (0UL), /* 45 Reserved */ +#endif /* _SAME70_UART3_INSTANCE_ */ +#ifdef _SAME70_UART4_INSTANCE_ + .pfnUART4_Handler = (void*) UART4_Handler, /* 46 UART 4 */ +#else + .pvReserved46 = (void*) (0UL), /* 46 Reserved */ +#endif /* _SAME70_UART4_INSTANCE_ */ +#ifdef _SAME70_TC2_INSTANCE_ + .pfnTC6_Handler = (void*) TC6_Handler, /* 47 Timer/Counter 6 */ +#else + .pvReserved47 = (void*) (0UL), /* 47 Reserved */ +#endif /* _SAME70_TC2_INSTANCE_ */ +#ifdef _SAME70_TC2_INSTANCE_ + .pfnTC7_Handler = (void*) TC7_Handler, /* 48 Timer/Counter 7 */ +#else + .pvReserved48 = (void*) (0UL), /* 48 Reserved */ +#endif /* _SAME70_TC2_INSTANCE_ */ +#ifdef _SAME70_TC2_INSTANCE_ + .pfnTC8_Handler = (void*) TC8_Handler, /* 49 Timer/Counter 8 */ +#else + .pvReserved49 = (void*) (0UL), /* 49 Reserved */ +#endif /* _SAME70_TC2_INSTANCE_ */ + .pfnTC9_Handler = (void*) TC9_Handler, /* 50 Timer/Counter 9 */ + .pfnTC10_Handler = (void*) TC10_Handler, /* 51 Timer/Counter 10 */ + .pfnTC11_Handler = (void*) TC11_Handler, /* 52 Timer/Counter 11 */ + .pvReserved53 = (void*) (0UL), /* 53 Reserved */ + .pvReserved54 = (void*) (0UL), /* 54 Reserved */ + .pvReserved55 = (void*) (0UL), /* 55 Reserved */ + .pfnAES_Handler = (void*) AES_Handler, /* 56 AES */ + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 57 True Random Generator */ + .pfnXDMAC_Handler = (void*) XDMAC_Handler, /* 58 DMA */ + .pfnISI_Handler = (void*) ISI_Handler, /* 59 Camera Interface */ + .pfnPWM1_Handler = (void*) PWM1_Handler, /* 60 Pulse Width Modulation 1 */ + .pfnFPU_Handler = (void*) FPU_Handler, /* 61 Floating Point Unit Registers */ +#ifdef _SAME70_SDRAMC_INSTANCE_ + .pfnSDRAMC_Handler = (void*) SDRAMC_Handler, /* 62 SDRAM Controller */ +#else + .pvReserved62 = (void*) (0UL), /* 62 Reserved */ +#endif /* _SAME70_SDRAMC_INSTANCE_ */ + .pfnRSWDT_Handler = (void*) RSWDT_Handler, /* 63 Reinforced Secure Watchdog Timer */ + .pfnCCW_Handler = (void*) CCW_Handler, /* 64 System Control Registers */ + .pfnCCF_Handler = (void*) CCF_Handler, /* 65 System Control Registers */ + .pfnGMAC_Q1_Handler= (void*) GMAC_Q1_Handler,/* 66 Gigabit Ethernet MAC */ + .pfnGMAC_Q2_Handler= (void*) GMAC_Q2_Handler,/* 67 Gigabit Ethernet MAC */ + .pfnIXC_Handler = (void*) IXC_Handler, /* 68 Floating Point Unit Registers */ +#ifdef _SAME70_I2SC0_INSTANCE_ + .pfnI2SC0_Handler = (void*) I2SC0_Handler, /* 69 Inter-IC Sound controller */ +#else + .pvReserved69 = (void*) (0UL), /* 69 Reserved */ +#endif /* _SAME70_I2SC0_INSTANCE_ */ +#ifdef _SAME70_I2SC1_INSTANCE_ + .pfnI2SC1_Handler = (void*) I2SC1_Handler, /* 70 Inter-IC Sound controller */ +#else + .pvReserved70 = (void*) (0UL), /* 70 Reserved */ +#endif /* _SAME70_I2SC1_INSTANCE_ */ +#if (__SAM_M7_REVB == 1) + .pfnGMAC_Q3_Handler= (void*) GMAC_Q3_Handler,/* 71 Gigabit Ethernet MAC */ + .pfnGMAC_Q4_Handler= (void*) GMAC_Q4_Handler,/* 72 Gigabit Ethernet MAC */ + .pfnGMAC_Q5_Handler= (void*) GMAC_Q5_Handler /* 73 Gigabit Ethernet MAC */ +#else + .pvReserved71 = (void*) (0UL), /* 71 Reserved */ + .pvReserved72 = (void*) (0UL), /* 72 Reserved */ + .pvReserved73 = (void*) (0UL) /* 73 Reserved */ +#endif +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + +#if __FPU_USED + fpu_enable(); +#endif + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/source/templates/system_same70.c b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/source/templates/system_same70.c new file mode 100644 index 000000000..ef0e99617 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/source/templates/system_same70.c @@ -0,0 +1,255 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "same70.h" + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/* @endcond */ + +/* %ATMEL_SYSTEM% */ +/* Clock Settings (600MHz PLL VDDIO 3.3V and VDDCORE 1.2V) */ +/* Clock Settings (300MHz HCLK, 150MHz MCK)=> PRESC = 2, MDIV = 2 */ +#define SYS_BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8U)) +#define SYS_BOARD_PLLAR (CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0x31U) | \ + CKGR_PLLAR_PLLACOUNT(0x3fU) | CKGR_PLLAR_DIVA(0x1U)) +#define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK | (1<<8)) + +uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; + +/** + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemFrequency variable. + */ + void SystemInit( void ) +{ + /* Set FWS according to SYS_BOARD_MCKR configuration */ + EFC->EEFC_FMR = EEFC_FMR_FWS(5); + + /* Initialize main oscillator */ + if ( !(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) ) + { + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | SYS_BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN; + + while ( !(PMC->PMC_SR & PMC_SR_MOSCXTS) ) + { + } + } + + /* Switch to 3-20MHz Xtal oscillator */ + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | SYS_BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL; + + while ( !(PMC->PMC_SR & PMC_SR_MOSCSELS) ) + { + } + + PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK; + + while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) ) + { + } + + /* Initialize PLLA */ + PMC->CKGR_PLLAR = SYS_BOARD_PLLAR; + while ( !(PMC->PMC_SR & PMC_SR_LOCKA) ) + { + } + + /* Switch to main clock */ + PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK; + while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) ) + { + } + + /* Switch to PLLA */ + PMC->PMC_MCKR = SYS_BOARD_MCKR; + while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) ) + { + } + + SystemCoreClock = CHIP_FREQ_CPU_MAX; +} + +void SystemCoreClockUpdate( void ) +{ + /* Determine clock frequency according to clock register values */ + switch (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk) + { + case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */ + if ( SUPC->SUPC_SR & SUPC_SR_OSCSEL ) + { + SystemCoreClock = CHIP_FREQ_XTAL_32K; + } + else + { + SystemCoreClock = CHIP_FREQ_SLCK_RC; + } + break; + + case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */ + if ( PMC->CKGR_MOR & CKGR_MOR_MOSCSEL ) + { + SystemCoreClock = CHIP_FREQ_XTAL_12M; + } + else + { + SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; + + switch ( PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk ) + { + case CKGR_MOR_MOSCRCF_4_MHz: + break; + + case CKGR_MOR_MOSCRCF_8_MHz: + SystemCoreClock *= 2U; + break; + + case CKGR_MOR_MOSCRCF_12_MHz: + SystemCoreClock *= 3U; + break; + + default: + break; + } + } + break; + + case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */ + if ( PMC->CKGR_MOR & CKGR_MOR_MOSCSEL ) + { + SystemCoreClock = CHIP_FREQ_XTAL_12M ; + } + else + { + SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; + + switch ( PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk ) + { + case CKGR_MOR_MOSCRCF_4_MHz: + break; + + case CKGR_MOR_MOSCRCF_8_MHz: + SystemCoreClock *= 2U; + break; + + case CKGR_MOR_MOSCRCF_12_MHz: + SystemCoreClock *= 3U; + break; + + default: + break; + } + } + + if ( (uint32_t) (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK ) + { + SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >> CKGR_PLLAR_MULA_Pos) + 1U); + SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >> CKGR_PLLAR_DIVA_Pos)); + } + break; + + default: + break; + } + + if ( (PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3 ) + { + SystemCoreClock /= 3U; + } + else + { + SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> PMC_MCKR_PRES_Pos); + } +} +/** + * Initialize flash. + */ +void system_init_flash( uint32_t ul_clk ) +{ + /* Set FWS for embedded Flash access according to operating frequency */ + if ( ul_clk < CHIP_FREQ_FWS_0 ) + { + EFC->EEFC_FMR = EEFC_FMR_FWS(0)|EEFC_FMR_CLOE; + } + else + { + if (ul_clk < CHIP_FREQ_FWS_1) + { + EFC->EEFC_FMR = EEFC_FMR_FWS(1)|EEFC_FMR_CLOE; + } + else + { + if (ul_clk < CHIP_FREQ_FWS_2) + { + EFC->EEFC_FMR = EEFC_FMR_FWS(2)|EEFC_FMR_CLOE; + } + else + { + if ( ul_clk < CHIP_FREQ_FWS_3 ) + { + EFC->EEFC_FMR = EEFC_FMR_FWS(3)|EEFC_FMR_CLOE; + } + else + { + if ( ul_clk < CHIP_FREQ_FWS_4 ) + { + EFC->EEFC_FMR = EEFC_FMR_FWS(4)|EEFC_FMR_CLOE; + } + else + { + if ( ul_clk < CHIP_FREQ_FWS_5 ) + { + EFC->EEFC_FMR = EEFC_FMR_FWS(5)|EEFC_FMR_CLOE; + } + else + { + EFC->EEFC_FMR = EEFC_FMR_FWS(6)|EEFC_FMR_CLOE; + } + } + } + } + } + } +} +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/* @endcond */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/source/templates/system_same70.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/source/templates/system_same70.h new file mode 100644 index 000000000..f605ccca8 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/cmsis/same70/source/templates/system_same70.h @@ -0,0 +1,75 @@ +/** + * \file + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef SYSTEM_SAME70_H_INCLUDED +#define SYSTEM_SAME70_H_INCLUDED + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/* @endcond */ + +#include + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + +/** + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void); + +/** + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void); + +/** + * Initialize flash. + */ +void system_init_flash(uint32_t dw_clk); + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/* @endcond */ + +#endif /* SYSTEM_SAME70_H_INCLUDED */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/compiler.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/compiler.h new file mode 100644 index 000000000..26f659ceb --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/compiler.h @@ -0,0 +1,1193 @@ +/** + * \file + * + * \brief Commonly used includes, types and macros. + * + * Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef UTILS_COMPILER_H +#define UTILS_COMPILER_H + +/** + * \defgroup group_sam_utils Compiler abstraction layer and code utilities + * + * Compiler abstraction layer and code utilities for AT91SAM. + * This module provides various abstraction layers and utilities to make code compatible between different compilers. + * + * \{ + */ +#include + +#if (defined __ICCARM__) +# include +#endif + +#include +#include "preprocessor.h" + +#include + +//_____ D E C L A R A T I O N S ____________________________________________ + +#ifndef __ASSEMBLY__ // Not defined for assembling. + +#include +#include +#include +#include + +#ifdef __ICCARM__ +/*! \name Compiler Keywords + * + * Port of some keywords from GCC to IAR Embedded Workbench. + */ +//! @{ +#define __asm__ asm +#define __inline__ inline +#define __volatile__ +//! @} + +#endif + +#define FUNC_PTR void * +/** + * \def UNUSED + * \brief Marking \a v as a unused parameter or value. + */ +#define UNUSED(v) (void)(v) + +/** + * \def unused + * \brief Marking \a v as a unused parameter or value. + */ +#define unused(v) do { (void)(v); } while(0) + +/** + * \def barrier + * \brief Memory barrier + */ +#define barrier() __DMB() + +/** + * \brief Emit the compiler pragma \a arg. + * + * \param arg The pragma directive as it would appear after \e \#pragma + * (i.e. not stringified). + */ +#define COMPILER_PRAGMA(arg) _Pragma(#arg) + +/** + * \def COMPILER_PACK_SET(alignment) + * \brief Set maximum alignment for subsequent struct and union + * definitions to \a alignment. + */ +#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment)) + +/** + * \def COMPILER_PACK_RESET() + * \brief Set default alignment for subsequent struct and union + * definitions. + */ +#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack()) + + +/** + * \brief Set aligned boundary. + */ +#if (defined __GNUC__) || (defined __CC_ARM) +# define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) +#elif (defined __ICCARM__) +# define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a) +#endif + +/** + * \brief Set word-aligned boundary. + */ +#if (defined __GNUC__) || defined(__CC_ARM) +#define COMPILER_WORD_ALIGNED __attribute__((__aligned__(4))) +#elif (defined __ICCARM__) +#define COMPILER_WORD_ALIGNED COMPILER_PRAGMA(data_alignment = 4) +#endif + +/** + * \def __always_inline + * \brief The function should always be inlined. + * + * This annotation instructs the compiler to ignore its inlining + * heuristics and inline the function no matter how big it thinks it + * becomes. + */ +#if defined(__CC_ARM) +# define __always_inline __forceinline +#elif (defined __GNUC__) +#ifdef __always_inline +# undef __always_inline +#endif +# define __always_inline inline __attribute__((__always_inline__)) +#elif (defined __ICCARM__) +# define __always_inline _Pragma("inline=forced") +#endif + +/** + * \def __no_inline + * \brief The function should not be inlined. + * + * This annotation instructs the compiler to ignore its inlining + * heuristics and not inline the function. + */ +#if defined(__CC_ARM) +# define __no_inline __attribute__((noinline)) +#elif (defined __GNUC__) +# define __no_inline __attribute__((__noinline__)) +#elif (defined __ICCARM__) +# define __no_inline _Pragma("inline=never") +#endif + +/*! \brief This macro is used to test fatal errors. + * + * The macro tests if the expression is false. If it is, a fatal error is + * detected and the application hangs up. If TEST_SUITE_DEFINE_ASSERT_MACRO + * is defined, a unit test version of the macro is used, to allow execution + * of further tests after a false expression. + * + * \param expr Expression to evaluate and supposed to be nonzero. + */ +#if defined(_ASSERT_ENABLE_) +# if defined(TEST_SUITE_DEFINE_ASSERT_MACRO) + // Assert() is defined in unit_test/suite.h +# include "unit_test/suite.h" +# else +#undef TEST_SUITE_DEFINE_ASSERT_MACRO +# define Assert(expr) \ + {\ + if (!(expr)) while (true);\ + } +# endif +#else +# define Assert(expr) ((void) 0) +#endif + +/* Define WEAK attribute */ +#if defined ( __CC_ARM ) /* Keil µVision 4 */ +# define WEAK __attribute__ ((weak)) +#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */ +# define WEAK __weak +#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */ +# define WEAK __attribute__ ((weak)) +#endif + +/* Define NO_INIT attribute */ +#if defined ( __CC_ARM ) +# define NO_INIT __attribute__((zero_init)) +#elif defined ( __ICCARM__ ) +# define NO_INIT __no_init +#elif defined ( __GNUC__ ) +# define NO_INIT __attribute__((section(".no_init"))) +#endif + +/* Define RAMFUNC attribute */ +#if defined ( __CC_ARM ) /* Keil µVision 4 */ +# define RAMFUNC __attribute__ ((section(".ramfunc"))) +#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */ +# define RAMFUNC __ramfunc +#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */ +# define RAMFUNC __attribute__ ((section(".ramfunc"))) +#endif + +/* Define OPTIMIZE_HIGH attribute */ +#if defined ( __CC_ARM ) /* Keil µVision 4 */ +# define OPTIMIZE_HIGH _Pragma("O3") +#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */ +# define OPTIMIZE_HIGH _Pragma("optimize=high") +#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */ +# define OPTIMIZE_HIGH __attribute__((optimize("s"))) +#endif + +#include "interrupt.h" + +/*! \name Usual Types + */ +//! @{ +typedef unsigned char Bool; //!< Boolean. +#ifndef __cplusplus +#if !defined(__bool_true_false_are_defined) +typedef unsigned char bool; //!< Boolean. +#endif +#endif +typedef int8_t S8 ; //!< 8-bit signed integer. +typedef uint8_t U8 ; //!< 8-bit unsigned integer. +typedef int16_t S16; //!< 16-bit signed integer. +typedef uint16_t U16; //!< 16-bit unsigned integer. +typedef uint16_t le16_t; +typedef uint16_t be16_t; +typedef int32_t S32; //!< 32-bit signed integer. +typedef uint32_t U32; //!< 32-bit unsigned integer. +typedef uint32_t le32_t; +typedef uint32_t be32_t; +typedef int64_t S64; //!< 64-bit signed integer. +typedef uint64_t U64; //!< 64-bit unsigned integer. +typedef float F32; //!< 32-bit floating-point number. +typedef double F64; //!< 64-bit floating-point number. +typedef uint32_t iram_size_t; +//! @} + + +/*! \name Status Types + */ +//! @{ +typedef bool Status_bool_t; //!< Boolean status. +typedef U8 Status_t; //!< 8-bit-coded status. +//! @} + + +/*! \name Aliasing Aggregate Types + */ +//! @{ + +//! 16-bit union. +typedef union +{ + S16 s16 ; + U16 u16 ; + S8 s8 [2]; + U8 u8 [2]; +} Union16; + +//! 32-bit union. +typedef union +{ + S32 s32 ; + U32 u32 ; + S16 s16[2]; + U16 u16[2]; + S8 s8 [4]; + U8 u8 [4]; +} Union32; + +//! 64-bit union. +typedef union +{ + S64 s64 ; + U64 u64 ; + S32 s32[2]; + U32 u32[2]; + S16 s16[4]; + U16 u16[4]; + S8 s8 [8]; + U8 u8 [8]; +} Union64; + +//! Union of pointers to 64-, 32-, 16- and 8-bit unsigned integers. +typedef union +{ + S64 *s64ptr; + U64 *u64ptr; + S32 *s32ptr; + U32 *u32ptr; + S16 *s16ptr; + U16 *u16ptr; + S8 *s8ptr ; + U8 *u8ptr ; +} UnionPtr; + +//! Union of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. +typedef union +{ + volatile S64 *s64ptr; + volatile U64 *u64ptr; + volatile S32 *s32ptr; + volatile U32 *u32ptr; + volatile S16 *s16ptr; + volatile U16 *u16ptr; + volatile S8 *s8ptr ; + volatile U8 *u8ptr ; +} UnionVPtr; + +//! Union of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. +typedef union +{ + const S64 *s64ptr; + const U64 *u64ptr; + const S32 *s32ptr; + const U32 *u32ptr; + const S16 *s16ptr; + const U16 *u16ptr; + const S8 *s8ptr ; + const U8 *u8ptr ; +} UnionCPtr; + +//! Union of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. +typedef union +{ + const volatile S64 *s64ptr; + const volatile U64 *u64ptr; + const volatile S32 *s32ptr; + const volatile U32 *u32ptr; + const volatile S16 *s16ptr; + const volatile U16 *u16ptr; + const volatile S8 *s8ptr ; + const volatile U8 *u8ptr ; +} UnionCVPtr; + +//! Structure of pointers to 64-, 32-, 16- and 8-bit unsigned integers. +typedef struct +{ + S64 *s64ptr; + U64 *u64ptr; + S32 *s32ptr; + U32 *u32ptr; + S16 *s16ptr; + U16 *u16ptr; + S8 *s8ptr ; + U8 *u8ptr ; +} StructPtr; + +//! Structure of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. +typedef struct +{ + volatile S64 *s64ptr; + volatile U64 *u64ptr; + volatile S32 *s32ptr; + volatile U32 *u32ptr; + volatile S16 *s16ptr; + volatile U16 *u16ptr; + volatile S8 *s8ptr ; + volatile U8 *u8ptr ; +} StructVPtr; + +//! Structure of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. +typedef struct +{ + const S64 *s64ptr; + const U64 *u64ptr; + const S32 *s32ptr; + const U32 *u32ptr; + const S16 *s16ptr; + const U16 *u16ptr; + const S8 *s8ptr ; + const U8 *u8ptr ; +} StructCPtr; + +//! Structure of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. +typedef struct +{ + const volatile S64 *s64ptr; + const volatile U64 *u64ptr; + const volatile S32 *s32ptr; + const volatile U32 *u32ptr; + const volatile S16 *s16ptr; + const volatile U16 *u16ptr; + const volatile S8 *s8ptr ; + const volatile U8 *u8ptr ; +} StructCVPtr; + +//! @} + +#endif // #ifndef __ASSEMBLY__ + +/*! \name Usual Constants + */ +//! @{ +#define DISABLE 0 +#define ENABLE 1 +#ifndef __cplusplus +#if !defined(__bool_true_false_are_defined) +#define false 0 +#define true 1 +#endif +#endif +#define PASS 0 +#define FAIL 1 +#define LOW 0 +#define HIGH 1 +//! @} + + +#ifndef __ASSEMBLY__ // not for assembling. + +//! \name Optimization Control +//@{ + +/** + * \def likely(exp) + * \brief The expression \a exp is likely to be true + */ +#ifndef likely +# define likely(exp) (exp) +#endif + +/** + * \def unlikely(exp) + * \brief The expression \a exp is unlikely to be true + */ +#ifndef unlikely +# define unlikely(exp) (exp) +#endif + +/** + * \def is_constant(exp) + * \brief Determine if an expression evaluates to a constant value. + * + * \param exp Any expression + * + * \return true if \a exp is constant, false otherwise. + */ +#if (defined __GNUC__) || (defined __CC_ARM) +# define is_constant(exp) __builtin_constant_p(exp) +#else +# define is_constant(exp) (0) +#endif + +//! @} + +/*! \name Bit-Field Handling + */ +//! @{ + +/*! \brief Reads the bits of a value specified by a given bit-mask. + * + * \param value Value to read bits from. + * \param mask Bit-mask indicating bits to read. + * + * \return Read bits. + */ +#define Rd_bits( value, mask) ((value) & (mask)) + +/*! \brief Writes the bits of a C lvalue specified by a given bit-mask. + * + * \param lvalue C lvalue to write bits to. + * \param mask Bit-mask indicating bits to write. + * \param bits Bits to write. + * + * \return Resulting value with written bits. + */ +#define Wr_bits(lvalue, mask, bits) ((lvalue) = ((lvalue) & ~(mask)) |\ + ((bits ) & (mask))) + +/*! \brief Tests the bits of a value specified by a given bit-mask. + * + * \param value Value of which to test bits. + * \param mask Bit-mask indicating bits to test. + * + * \return \c 1 if at least one of the tested bits is set, else \c 0. + */ +#define Tst_bits( value, mask) (Rd_bits(value, mask) != 0) + +/*! \brief Clears the bits of a C lvalue specified by a given bit-mask. + * + * \param lvalue C lvalue of which to clear bits. + * \param mask Bit-mask indicating bits to clear. + * + * \return Resulting value with cleared bits. + */ +#define Clr_bits(lvalue, mask) ((lvalue) &= ~(mask)) + +/*! \brief Sets the bits of a C lvalue specified by a given bit-mask. + * + * \param lvalue C lvalue of which to set bits. + * \param mask Bit-mask indicating bits to set. + * + * \return Resulting value with set bits. + */ +#define Set_bits(lvalue, mask) ((lvalue) |= (mask)) + +/*! \brief Toggles the bits of a C lvalue specified by a given bit-mask. + * + * \param lvalue C lvalue of which to toggle bits. + * \param mask Bit-mask indicating bits to toggle. + * + * \return Resulting value with toggled bits. + */ +#define Tgl_bits(lvalue, mask) ((lvalue) ^= (mask)) + +/*! \brief Reads the bit-field of a value specified by a given bit-mask. + * + * \param value Value to read a bit-field from. + * \param mask Bit-mask indicating the bit-field to read. + * + * \return Read bit-field. + */ +#define Rd_bitfield( value, mask) (Rd_bits( value, mask) >> ctz(mask)) + +/*! \brief Writes the bit-field of a C lvalue specified by a given bit-mask. + * + * \param lvalue C lvalue to write a bit-field to. + * \param mask Bit-mask indicating the bit-field to write. + * \param bitfield Bit-field to write. + * + * \return Resulting value with written bit-field. + */ +#define Wr_bitfield(lvalue, mask, bitfield) (Wr_bits(lvalue, mask, (U32)(bitfield) << ctz(mask))) + +//! @} + + +/*! \name Zero-Bit Counting + * + * Under GCC, __builtin_clz and __builtin_ctz behave like macros when + * applied to constant expressions (values known at compile time), so they are + * more optimized than the use of the corresponding assembly instructions and + * they can be used as constant expressions e.g. to initialize objects having + * static storage duration, and like the corresponding assembly instructions + * when applied to non-constant expressions (values unknown at compile time), so + * they are more optimized than an assembly periphrasis. Hence, clz and ctz + * ensure a possible and optimized behavior for both constant and non-constant + * expressions. + */ +//! @{ + +/*! \brief Counts the leading zero bits of the given value considered as a 32-bit integer. + * + * \param u Value of which to count the leading zero bits. + * + * \return The count of leading zero bits in \a u. + */ +#if (defined __GNUC__) || (defined __CC_ARM) +# define clz(u) ((u) ? __builtin_clz(u) : 32) +#elif (defined __ICCARM__) +# define clz(u) ((u) ? __CLZ(u) : 32) +#else +# define clz(u) (((u) == 0) ? 32 : \ + ((u) & (1ul << 31)) ? 0 : \ + ((u) & (1ul << 30)) ? 1 : \ + ((u) & (1ul << 29)) ? 2 : \ + ((u) & (1ul << 28)) ? 3 : \ + ((u) & (1ul << 27)) ? 4 : \ + ((u) & (1ul << 26)) ? 5 : \ + ((u) & (1ul << 25)) ? 6 : \ + ((u) & (1ul << 24)) ? 7 : \ + ((u) & (1ul << 23)) ? 8 : \ + ((u) & (1ul << 22)) ? 9 : \ + ((u) & (1ul << 21)) ? 10 : \ + ((u) & (1ul << 20)) ? 11 : \ + ((u) & (1ul << 19)) ? 12 : \ + ((u) & (1ul << 18)) ? 13 : \ + ((u) & (1ul << 17)) ? 14 : \ + ((u) & (1ul << 16)) ? 15 : \ + ((u) & (1ul << 15)) ? 16 : \ + ((u) & (1ul << 14)) ? 17 : \ + ((u) & (1ul << 13)) ? 18 : \ + ((u) & (1ul << 12)) ? 19 : \ + ((u) & (1ul << 11)) ? 20 : \ + ((u) & (1ul << 10)) ? 21 : \ + ((u) & (1ul << 9)) ? 22 : \ + ((u) & (1ul << 8)) ? 23 : \ + ((u) & (1ul << 7)) ? 24 : \ + ((u) & (1ul << 6)) ? 25 : \ + ((u) & (1ul << 5)) ? 26 : \ + ((u) & (1ul << 4)) ? 27 : \ + ((u) & (1ul << 3)) ? 28 : \ + ((u) & (1ul << 2)) ? 29 : \ + ((u) & (1ul << 1)) ? 30 : \ + 31) +#endif + +/*! \brief Counts the trailing zero bits of the given value considered as a 32-bit integer. + * + * \param u Value of which to count the trailing zero bits. + * + * \return The count of trailing zero bits in \a u. + */ +#if (defined __GNUC__) || (defined __CC_ARM) +# define ctz(u) ((u) ? __builtin_ctz(u) : 32) +#else +# define ctz(u) ((u) & (1ul << 0) ? 0 : \ + (u) & (1ul << 1) ? 1 : \ + (u) & (1ul << 2) ? 2 : \ + (u) & (1ul << 3) ? 3 : \ + (u) & (1ul << 4) ? 4 : \ + (u) & (1ul << 5) ? 5 : \ + (u) & (1ul << 6) ? 6 : \ + (u) & (1ul << 7) ? 7 : \ + (u) & (1ul << 8) ? 8 : \ + (u) & (1ul << 9) ? 9 : \ + (u) & (1ul << 10) ? 10 : \ + (u) & (1ul << 11) ? 11 : \ + (u) & (1ul << 12) ? 12 : \ + (u) & (1ul << 13) ? 13 : \ + (u) & (1ul << 14) ? 14 : \ + (u) & (1ul << 15) ? 15 : \ + (u) & (1ul << 16) ? 16 : \ + (u) & (1ul << 17) ? 17 : \ + (u) & (1ul << 18) ? 18 : \ + (u) & (1ul << 19) ? 19 : \ + (u) & (1ul << 20) ? 20 : \ + (u) & (1ul << 21) ? 21 : \ + (u) & (1ul << 22) ? 22 : \ + (u) & (1ul << 23) ? 23 : \ + (u) & (1ul << 24) ? 24 : \ + (u) & (1ul << 25) ? 25 : \ + (u) & (1ul << 26) ? 26 : \ + (u) & (1ul << 27) ? 27 : \ + (u) & (1ul << 28) ? 28 : \ + (u) & (1ul << 29) ? 29 : \ + (u) & (1ul << 30) ? 30 : \ + (u) & (1ul << 31) ? 31 : \ + 32) +#endif + +//! @} + + +/*! \name Bit Reversing + */ +//! @{ + +/*! \brief Reverses the bits of \a u8. + * + * \param u8 U8 of which to reverse the bits. + * + * \return Value resulting from \a u8 with reversed bits. + */ +#define bit_reverse8(u8) ((U8)(bit_reverse32((U8)(u8)) >> 24)) + +/*! \brief Reverses the bits of \a u16. + * + * \param u16 U16 of which to reverse the bits. + * + * \return Value resulting from \a u16 with reversed bits. + */ +#define bit_reverse16(u16) ((U16)(bit_reverse32((U16)(u16)) >> 16)) + +/*! \brief Reverses the bits of \a u32. + * + * \param u32 U32 of which to reverse the bits. + * + * \return Value resulting from \a u32 with reversed bits. + */ +#define bit_reverse32(u32) __RBIT(u32) + +/*! \brief Reverses the bits of \a u64. + * + * \param u64 U64 of which to reverse the bits. + * + * \return Value resulting from \a u64 with reversed bits. + */ +#define bit_reverse64(u64) ((U64)(((U64)bit_reverse32((U64)(u64) >> 32)) |\ + ((U64)bit_reverse32((U64)(u64)) << 32))) + +//! @} + + +/*! \name Alignment + */ +//! @{ + +/*! \brief Tests alignment of the number \a val with the \a n boundary. + * + * \param val Input value. + * \param n Boundary. + * + * \return \c 1 if the number \a val is aligned with the \a n boundary, else \c 0. + */ +#define Test_align(val, n ) (!Tst_bits( val, (n) - 1 ) ) + +/*! \brief Gets alignment of the number \a val with respect to the \a n boundary. + * + * \param val Input value. + * \param n Boundary. + * + * \return Alignment of the number \a val with respect to the \a n boundary. + */ +#define Get_align( val, n ) ( Rd_bits( val, (n) - 1 ) ) + +/*! \brief Sets alignment of the lvalue number \a lval to \a alg with respect to the \a n boundary. + * + * \param lval Input/output lvalue. + * \param n Boundary. + * \param alg Alignment. + * + * \return New value of \a lval resulting from its alignment set to \a alg with respect to the \a n boundary. + */ +#define Set_align(lval, n, alg) ( Wr_bits(lval, (n) - 1, alg) ) + +/*! \brief Aligns the number \a val with the upper \a n boundary. + * + * \param val Input value. + * \param n Boundary. + * + * \return Value resulting from the number \a val aligned with the upper \a n boundary. + */ +#define Align_up( val, n ) (((val) + ((n) - 1)) & ~((n) - 1)) + +/*! \brief Aligns the number \a val with the lower \a n boundary. + * + * \param val Input value. + * \param n Boundary. + * + * \return Value resulting from the number \a val aligned with the lower \a n boundary. + */ +#define Align_down(val, n ) ( (val) & ~((n) - 1)) + +//! @} + + +/*! \name Mathematics + * + * The same considerations as for clz and ctz apply here but GCC does not + * provide built-in functions to access the assembly instructions abs, min and + * max and it does not produce them by itself in most cases, so two sets of + * macros are defined here: + * - Abs, Min and Max to apply to constant expressions (values known at + * compile time); + * - abs, min and max to apply to non-constant expressions (values unknown at + * compile time), abs is found in stdlib.h. + */ +//! @{ + +/*! \brief Takes the absolute value of \a a. + * + * \param a Input value. + * + * \return Absolute value of \a a. + * + * \note More optimized if only used with values known at compile time. + */ +#define Abs(a) (((a) < 0 ) ? -(a) : (a)) + +/*! \brief Takes the minimal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Minimal value of \a a and \a b. + * + * \note More optimized if only used with values known at compile time. + */ +#define Min(a, b) (((a) < (b)) ? (a) : (b)) + +/*! \brief Takes the maximal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Maximal value of \a a and \a b. + * + * \note More optimized if only used with values known at compile time. + */ +#define Max(a, b) (((a) > (b)) ? (a) : (b)) + +#if !defined(__cplusplus) + +// abs() is already defined by stdlib.h + +/*! \brief Takes the minimal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Minimal value of \a a and \a b. + * + * \note More optimized if only used with values unknown at compile time. + */ +#define min(a, b) Min(a, b) + +/*! \brief Takes the maximal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Maximal value of \a a and \a b. + * + * \note More optimized if only used with values unknown at compile time. + */ +#define max(a, b) Max(a, b) + +#endif + +//! @} + + +/*! \brief Calls the routine at address \a addr. + * + * It generates a long call opcode. + * + * For example, `Long_call(0x80000000)' generates a software reset on a UC3 if + * it is invoked from the CPU supervisor mode. + * + * \param addr Address of the routine to call. + * + * \note It may be used as a long jump opcode in some special cases. + */ +#define Long_call(addr) ((*(void (*)(void))(addr))()) + + +/*! \name MCU Endianism Handling + * ARM is MCU little endianism. + */ +//! @{ +#define MSB(u16) (((U8 *)&(u16))[1]) //!< Most significant byte of \a u16. +#define LSB(u16) (((U8 *)&(u16))[0]) //!< Least significant byte of \a u16. + +#define MSH(u32) (((U16 *)&(u32))[1]) //!< Most significant half-word of \a u32. +#define LSH(u32) (((U16 *)&(u32))[0]) //!< Least significant half-word of \a u32. +#define MSB0W(u32) (((U8 *)&(u32))[3]) //!< Most significant byte of 1st rank of \a u32. +#define MSB1W(u32) (((U8 *)&(u32))[2]) //!< Most significant byte of 2nd rank of \a u32. +#define MSB2W(u32) (((U8 *)&(u32))[1]) //!< Most significant byte of 3rd rank of \a u32. +#define MSB3W(u32) (((U8 *)&(u32))[0]) //!< Most significant byte of 4th rank of \a u32. +#define LSB3W(u32) MSB0W(u32) //!< Least significant byte of 4th rank of \a u32. +#define LSB2W(u32) MSB1W(u32) //!< Least significant byte of 3rd rank of \a u32. +#define LSB1W(u32) MSB2W(u32) //!< Least significant byte of 2nd rank of \a u32. +#define LSB0W(u32) MSB3W(u32) //!< Least significant byte of 1st rank of \a u32. + +#define MSW(u64) (((U32 *)&(u64))[1]) //!< Most significant word of \a u64. +#define LSW(u64) (((U32 *)&(u64))[0]) //!< Least significant word of \a u64. +#define MSH0(u64) (((U16 *)&(u64))[3]) //!< Most significant half-word of 1st rank of \a u64. +#define MSH1(u64) (((U16 *)&(u64))[2]) //!< Most significant half-word of 2nd rank of \a u64. +#define MSH2(u64) (((U16 *)&(u64))[1]) //!< Most significant half-word of 3rd rank of \a u64. +#define MSH3(u64) (((U16 *)&(u64))[0]) //!< Most significant half-word of 4th rank of \a u64. +#define LSH3(u64) MSH0(u64) //!< Least significant half-word of 4th rank of \a u64. +#define LSH2(u64) MSH1(u64) //!< Least significant half-word of 3rd rank of \a u64. +#define LSH1(u64) MSH2(u64) //!< Least significant half-word of 2nd rank of \a u64. +#define LSH0(u64) MSH3(u64) //!< Least significant half-word of 1st rank of \a u64. +#define MSB0D(u64) (((U8 *)&(u64))[7]) //!< Most significant byte of 1st rank of \a u64. +#define MSB1D(u64) (((U8 *)&(u64))[6]) //!< Most significant byte of 2nd rank of \a u64. +#define MSB2D(u64) (((U8 *)&(u64))[5]) //!< Most significant byte of 3rd rank of \a u64. +#define MSB3D(u64) (((U8 *)&(u64))[4]) //!< Most significant byte of 4th rank of \a u64. +#define MSB4D(u64) (((U8 *)&(u64))[3]) //!< Most significant byte of 5th rank of \a u64. +#define MSB5D(u64) (((U8 *)&(u64))[2]) //!< Most significant byte of 6th rank of \a u64. +#define MSB6D(u64) (((U8 *)&(u64))[1]) //!< Most significant byte of 7th rank of \a u64. +#define MSB7D(u64) (((U8 *)&(u64))[0]) //!< Most significant byte of 8th rank of \a u64. +#define LSB7D(u64) MSB0D(u64) //!< Least significant byte of 8th rank of \a u64. +#define LSB6D(u64) MSB1D(u64) //!< Least significant byte of 7th rank of \a u64. +#define LSB5D(u64) MSB2D(u64) //!< Least significant byte of 6th rank of \a u64. +#define LSB4D(u64) MSB3D(u64) //!< Least significant byte of 5th rank of \a u64. +#define LSB3D(u64) MSB4D(u64) //!< Least significant byte of 4th rank of \a u64. +#define LSB2D(u64) MSB5D(u64) //!< Least significant byte of 3rd rank of \a u64. +#define LSB1D(u64) MSB6D(u64) //!< Least significant byte of 2nd rank of \a u64. +#define LSB0D(u64) MSB7D(u64) //!< Least significant byte of 1st rank of \a u64. + +#define BE16(x) swap16(x) +#define LE16(x) (x) + +#define le16_to_cpu(x) (x) +#define cpu_to_le16(x) (x) +#define LE16_TO_CPU(x) (x) +#define CPU_TO_LE16(x) (x) + +#define be16_to_cpu(x) swap16(x) +#define cpu_to_be16(x) swap16(x) +#define BE16_TO_CPU(x) swap16(x) +#define CPU_TO_BE16(x) swap16(x) + +#define le32_to_cpu(x) (x) +#define cpu_to_le32(x) (x) +#define LE32_TO_CPU(x) (x) +#define CPU_TO_LE32(x) (x) + +#define be32_to_cpu(x) swap32(x) +#define cpu_to_be32(x) swap32(x) +#define BE32_TO_CPU(x) swap32(x) +#define CPU_TO_BE32(x) swap32(x) +//! @} + + +/*! \name Endianism Conversion + * + * The same considerations as for clz and ctz apply here but GCC's + * __builtin_bswap_32 and __builtin_bswap_64 do not behave like macros when + * applied to constant expressions, so two sets of macros are defined here: + * - Swap16, Swap32 and Swap64 to apply to constant expressions (values known + * at compile time); + * - swap16, swap32 and swap64 to apply to non-constant expressions (values + * unknown at compile time). + */ +//! @{ + +/*! \brief Toggles the endianism of \a u16 (by swapping its bytes). + * + * \param u16 U16 of which to toggle the endianism. + * + * \return Value resulting from \a u16 with toggled endianism. + * + * \note More optimized if only used with values known at compile time. + */ +#define Swap16(u16) ((U16)(((U16)(u16) >> 8) |\ + ((U16)(u16) << 8))) + +/*! \brief Toggles the endianism of \a u32 (by swapping its bytes). + * + * \param u32 U32 of which to toggle the endianism. + * + * \return Value resulting from \a u32 with toggled endianism. + * + * \note More optimized if only used with values known at compile time. + */ +#define Swap32(u32) ((U32)(((U32)Swap16((U32)(u32) >> 16)) |\ + ((U32)Swap16((U32)(u32)) << 16))) + +/*! \brief Toggles the endianism of \a u64 (by swapping its bytes). + * + * \param u64 U64 of which to toggle the endianism. + * + * \return Value resulting from \a u64 with toggled endianism. + * + * \note More optimized if only used with values known at compile time. + */ +#define Swap64(u64) ((U64)(((U64)Swap32((U64)(u64) >> 32)) |\ + ((U64)Swap32((U64)(u64)) << 32))) + +/*! \brief Toggles the endianism of \a u16 (by swapping its bytes). + * + * \param u16 U16 of which to toggle the endianism. + * + * \return Value resulting from \a u16 with toggled endianism. + * + * \note More optimized if only used with values unknown at compile time. + */ +#define swap16(u16) Swap16(u16) + +/*! \brief Toggles the endianism of \a u32 (by swapping its bytes). + * + * \param u32 U32 of which to toggle the endianism. + * + * \return Value resulting from \a u32 with toggled endianism. + * + * \note More optimized if only used with values unknown at compile time. + */ +#if (defined __GNUC__) +# define swap32(u32) ((U32)__builtin_bswap32((U32)(u32))) +#else +# define swap32(u32) Swap32(u32) +#endif + +/*! \brief Toggles the endianism of \a u64 (by swapping its bytes). + * + * \param u64 U64 of which to toggle the endianism. + * + * \return Value resulting from \a u64 with toggled endianism. + * + * \note More optimized if only used with values unknown at compile time. + */ +#if (defined __GNUC__) +# define swap64(u64) ((U64)__builtin_bswap64((U64)(u64))) +#else +# define swap64(u64) ((U64)(((U64)swap32((U64)(u64) >> 32)) |\ + ((U64)swap32((U64)(u64)) << 32))) +#endif + +//! @} + + +/*! \name Target Abstraction + */ +//! @{ + +#define _GLOBEXT_ extern //!< extern storage-class specifier. +#define _CONST_TYPE_ const //!< const type qualifier. +#define _MEM_TYPE_SLOW_ //!< Slow memory type. +#define _MEM_TYPE_MEDFAST_ //!< Fairly fast memory type. +#define _MEM_TYPE_FAST_ //!< Fast memory type. + +typedef U8 Byte; //!< 8-bit unsigned integer. + +#define memcmp_ram2ram memcmp //!< Target-specific memcmp of RAM to RAM. +#define memcmp_code2ram memcmp //!< Target-specific memcmp of RAM to NVRAM. +#define memcpy_ram2ram memcpy //!< Target-specific memcpy from RAM to RAM. +#define memcpy_code2ram memcpy //!< Target-specific memcpy from NVRAM to RAM. + +#define LSB0(u32) LSB0W(u32) //!< Least significant byte of 1st rank of \a u32. +#define LSB1(u32) LSB1W(u32) //!< Least significant byte of 2nd rank of \a u32. +#define LSB2(u32) LSB2W(u32) //!< Least significant byte of 3rd rank of \a u32. +#define LSB3(u32) LSB3W(u32) //!< Least significant byte of 4th rank of \a u32. +#define MSB3(u32) MSB3W(u32) //!< Most significant byte of 4th rank of \a u32. +#define MSB2(u32) MSB2W(u32) //!< Most significant byte of 3rd rank of \a u32. +#define MSB1(u32) MSB1W(u32) //!< Most significant byte of 2nd rank of \a u32. +#define MSB0(u32) MSB0W(u32) //!< Most significant byte of 1st rank of \a u32. + +//! @} + +/** + * \brief Calculate \f$ \left\lceil \frac{a}{b} \right\rceil \f$ using + * integer arithmetic. + * + * \param a An integer + * \param b Another integer + * + * \return (\a a / \a b) rounded up to the nearest integer. + */ +#define div_ceil(a, b) (((a) + (b) - 1) / (b)) + +#endif // #ifndef __ASSEMBLY__ + + +#if defined(__ICCARM__) +#define SHORTENUM __packed +#elif defined(__GNUC__) +#define SHORTENUM __attribute__((packed)) +#endif + +/* No operation */ +#if defined(__ICCARM__) +#define nop() __no_operation() +#elif defined(__GNUC__) +#define nop() (__NOP()) +#endif + +#define FLASH_DECLARE(x) const x +#define FLASH_EXTERN(x) extern const x +#define PGM_READ_BYTE(x) *(x) +#define PGM_READ_WORD(x) *(x) +#define PGM_READ_DWORD(x) *(x) +#define MEMCPY_ENDIAN memcpy +#define PGM_READ_BLOCK(dst, src, len) memcpy((dst), (src), (len)) + +/*Defines the Flash Storage for the request and response of MAC*/ +#define CMD_ID_OCTET (0) + +/* Converting of values from CPU endian to little endian. */ +#define CPU_ENDIAN_TO_LE16(x) (x) +#define CPU_ENDIAN_TO_LE32(x) (x) +#define CPU_ENDIAN_TO_LE64(x) (x) + +/* Converting of values from little endian to CPU endian. */ +#define LE16_TO_CPU_ENDIAN(x) (x) +#define LE32_TO_CPU_ENDIAN(x) (x) +#define LE64_TO_CPU_ENDIAN(x) (x) + +/* Converting of constants from little endian to CPU endian. */ +#define CLE16_TO_CPU_ENDIAN(x) (x) +#define CLE32_TO_CPU_ENDIAN(x) (x) +#define CLE64_TO_CPU_ENDIAN(x) (x) + +/* Converting of constants from CPU endian to little endian. */ +#define CCPU_ENDIAN_TO_LE16(x) (x) +#define CCPU_ENDIAN_TO_LE32(x) (x) +#define CCPU_ENDIAN_TO_LE64(x) (x) + +#define ADDR_COPY_DST_SRC_16(dst, src) ((dst) = (src)) +#define ADDR_COPY_DST_SRC_64(dst, src) ((dst) = (src)) + +/** + * @brief Converts a 64-Bit value into a 8 Byte array + * + * @param[in] value 64-Bit value + * @param[out] data Pointer to the 8 Byte array to be updated with 64-Bit value + * @ingroup apiPalApi + */ +static inline void convert_64_bit_to_byte_array(uint64_t value, uint8_t *data) +{ + uint8_t val_index = 0; + + while (val_index < 8) + { + data[val_index++] = value & 0xFF; + value = value >> 8; + } +} + +/** + * @brief Converts a 16-Bit value into a 2 Byte array + * + * @param[in] value 16-Bit value + * @param[out] data Pointer to the 2 Byte array to be updated with 16-Bit value + * @ingroup apiPalApi + */ +static inline void convert_16_bit_to_byte_array(uint16_t value, uint8_t *data) +{ + data[0] = value & 0xFF; + data[1] = (value >> 8) & 0xFF; +} + +/* Converts a 16-Bit value into a 2 Byte array */ +static inline void convert_spec_16_bit_to_byte_array(uint16_t value, uint8_t *data) +{ + data[0] = value & 0xFF; + data[1] = (value >> 8) & 0xFF; +} + +/* Converts a 16-Bit value into a 2 Byte array */ +static inline void convert_16_bit_to_byte_address(uint16_t value, uint8_t *data) +{ + data[0] = value & 0xFF; + data[1] = (value >> 8) & 0xFF; +} + +/* + * @brief Converts a 2 Byte array into a 16-Bit value + * + * @param data Specifies the pointer to the 2 Byte array + * + * @return 16-Bit value + * @ingroup apiPalApi + */ +static inline uint16_t convert_byte_array_to_16_bit(uint8_t *data) +{ + return (data[0] | ((uint16_t)data[1] << 8)); +} + +/* Converts a 8 Byte array into a 32-Bit value */ +static inline uint32_t convert_byte_array_to_32_bit(uint8_t *data) +{ + union + { + uint32_t u32; + uint8_t u8[8]; + }long_addr; + uint8_t index; + for (index = 0; index < 4; index++) + { + long_addr.u8[index] = *data++; + } + return long_addr.u32; +} + +/** + * @brief Converts a 8 Byte array into a 64-Bit value + * + * @param data Specifies the pointer to the 8 Byte array + * + * @return 64-Bit value + * @ingroup apiPalApi + */ +static inline uint64_t convert_byte_array_to_64_bit(uint8_t *data) +{ + union + { + uint64_t u64; + uint8_t u8[8]; + } long_addr; + + uint8_t val_index; + + for (val_index = 0; val_index < 8; val_index++) + { + long_addr.u8[val_index] = *data++; + } + + return long_addr.u64; +} +/** + * \} + */ + +#endif /* UTILS_COMPILER_H */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/fpu/fpu.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/fpu/fpu.h new file mode 100644 index 000000000..76781e6d2 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/fpu/fpu.h @@ -0,0 +1,84 @@ +/** + * \file + * + * \brief FPU support for SAM. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _FPU_H_INCLUDED_ +#define _FPU_H_INCLUDED_ + +#include + +/** Address for ARM CPACR */ +#define ADDR_CPACR 0xE000ED88 + +/** CPACR Register */ +#define REG_CPACR (*((volatile uint32_t *)ADDR_CPACR)) + +/** + * \brief Enable FPU + */ +__always_inline static void fpu_enable(void) +{ + irqflags_t flags; + flags = cpu_irq_save(); + REG_CPACR |= (0xFu << 20); + __DSB(); + __ISB(); + cpu_irq_restore(flags); +} + +/** + * \brief Disable FPU + */ +__always_inline static void fpu_disable(void) +{ + irqflags_t flags; + flags = cpu_irq_save(); + REG_CPACR &= ~(0xFu << 20); + __DSB(); + __ISB(); + cpu_irq_restore(flags); +} + +/** + * \brief Check if FPU is enabled + * + * \return Return ture if FPU is enabled, otherwise return false. + */ +__always_inline static bool fpu_is_enabled(void) +{ + return (REG_CPACR & (0xFu << 20)); +} + +#endif /* _FPU_H_INCLUDED_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/header_files/io.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/header_files/io.h new file mode 100644 index 000000000..d2dc15572 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/header_files/io.h @@ -0,0 +1,148 @@ +/** + * \file + * + * \brief Arch file for SAM. + * + * This file defines common SAM series. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _SAM_IO_ +#define _SAM_IO_ + +/* SAM3 family */ + +/* SAM3S series */ +#if (SAM3S) +# if (SAM3S8 || SAM3SD8) +# include "sam3s8.h" +# else +# include "sam3s.h" +# endif +#endif + +/* SAM3U series */ +#if (SAM3U) +# include "sam3u.h" +#endif + +/* SAM3N series */ +#if (SAM3N) +# include "sam3n.h" +#endif + +/* SAM3XA series */ +#if (SAM3XA) +# include "sam3xa.h" +#endif + +/* SAM4S series */ +#if (SAM4S) +# include "sam4s.h" +#endif + +/* SAM4L series */ +#if (SAM4L) +# include "sam4l.h" +#endif + +/* SAM4E series */ +#if (SAM4E) +# include "sam4e.h" +#endif + +/* SAM4N series */ +#if (SAM4N) +# include "sam4n.h" +#endif + +/* SAM4C series */ +#if (SAM4C) +# include "sam4c.h" +#endif + +/* SAM4CM series */ +#if (SAM4CM) +# if (SAM4CMP32 || SAM4CMS32) +# include "sam4cm32.h" +# else +# include "sam4cm.h" +# endif +#endif + +/* SAM4CP series */ +#if (SAM4CP) +# include "sam4cp.h" +#endif + +/* SAMG51 series */ +#if (SAMG51) +# include "samg51.h" +#endif + +/* SAMG53 series */ +#if (SAMG53) +# include "samg53.h" +#endif + +/* SAMG54 series */ +#if (SAMG54) +# include "samg54.h" +#endif + +/* SAMG55 series */ +#if (SAMG55) +# include "samg55.h" +#endif + +/* SAMV71 series */ +#if (SAMV71) +# include "samv71.h" +#endif + +/* SAMV70 series */ +#if (SAMV70) +# include "samv70.h" +#endif + +/* SAME70 series */ +#if (SAME70) +# include "same70.h" +#endif + +/* SAMS70 series */ +#if (SAMS70) +# include "sams70.h" +#endif + + +#endif /* _SAM_IO_ */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/preprocessor/mrepeat.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/preprocessor/mrepeat.h new file mode 100644 index 000000000..7cacde3d0 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/preprocessor/mrepeat.h @@ -0,0 +1,329 @@ +/** + * \file + * + * \brief Preprocessor macro repeating utils. + * + * Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _MREPEAT_H_ +#define _MREPEAT_H_ + +/** + * \defgroup group_sam_utils_mrepeat Preprocessor - Macro Repeat + * + * \ingroup group_sam_utils + * + * \{ + */ + +#include "preprocessor.h" + + +//! Maximal number of repetitions supported by MREPEAT. +#define MREPEAT_LIMIT 256 + +/*! \brief Macro repeat. + * + * This macro represents a horizontal repetition construct. + * + * \param count The number of repetitious calls to macro. Valid values range from 0 to MREPEAT_LIMIT. + * \param macro A binary operation of the form macro(n, data). This macro is expanded by MREPEAT with + * the current repetition number and the auxiliary data argument. + * \param data Auxiliary data passed to macro. + * + * \return macro(0, data) macro(1, data) ... macro(count - 1, data) + */ +#define MREPEAT(count, macro, data) TPASTE2(MREPEAT, count)(macro, data) + +#define MREPEAT0( macro, data) +#define MREPEAT1( macro, data) MREPEAT0( macro, data) macro( 0, data) +#define MREPEAT2( macro, data) MREPEAT1( macro, data) macro( 1, data) +#define MREPEAT3( macro, data) MREPEAT2( macro, data) macro( 2, data) +#define MREPEAT4( macro, data) MREPEAT3( macro, data) macro( 3, data) +#define MREPEAT5( macro, data) MREPEAT4( macro, data) macro( 4, data) +#define MREPEAT6( macro, data) MREPEAT5( macro, data) macro( 5, data) +#define MREPEAT7( macro, data) MREPEAT6( macro, data) macro( 6, data) +#define MREPEAT8( macro, data) MREPEAT7( macro, data) macro( 7, data) +#define MREPEAT9( macro, data) MREPEAT8( macro, data) macro( 8, data) +#define MREPEAT10( macro, data) MREPEAT9( macro, data) macro( 9, data) +#define MREPEAT11( macro, data) MREPEAT10( macro, data) macro( 10, data) +#define MREPEAT12( macro, data) MREPEAT11( macro, data) macro( 11, data) +#define MREPEAT13( macro, data) MREPEAT12( macro, data) macro( 12, data) +#define MREPEAT14( macro, data) MREPEAT13( macro, data) macro( 13, data) +#define MREPEAT15( macro, data) MREPEAT14( macro, data) macro( 14, data) +#define MREPEAT16( macro, data) MREPEAT15( macro, data) macro( 15, data) +#define MREPEAT17( macro, data) MREPEAT16( macro, data) macro( 16, data) +#define MREPEAT18( macro, data) MREPEAT17( macro, data) macro( 17, data) +#define MREPEAT19( macro, data) MREPEAT18( macro, data) macro( 18, data) +#define MREPEAT20( macro, data) MREPEAT19( macro, data) macro( 19, data) +#define MREPEAT21( macro, data) MREPEAT20( macro, data) macro( 20, data) +#define MREPEAT22( macro, data) MREPEAT21( macro, data) macro( 21, data) +#define MREPEAT23( macro, data) MREPEAT22( macro, data) macro( 22, data) +#define MREPEAT24( macro, data) MREPEAT23( macro, data) macro( 23, data) +#define MREPEAT25( macro, data) MREPEAT24( macro, data) macro( 24, data) +#define MREPEAT26( macro, data) MREPEAT25( macro, data) macro( 25, data) +#define MREPEAT27( macro, data) MREPEAT26( macro, data) macro( 26, data) +#define MREPEAT28( macro, data) MREPEAT27( macro, data) macro( 27, data) +#define MREPEAT29( macro, data) MREPEAT28( macro, data) macro( 28, data) +#define MREPEAT30( macro, data) MREPEAT29( macro, data) macro( 29, data) +#define MREPEAT31( macro, data) MREPEAT30( macro, data) macro( 30, data) +#define MREPEAT32( macro, data) MREPEAT31( macro, data) macro( 31, data) +#define MREPEAT33( macro, data) MREPEAT32( macro, data) macro( 32, data) +#define MREPEAT34( macro, data) MREPEAT33( macro, data) macro( 33, data) +#define MREPEAT35( macro, data) MREPEAT34( macro, data) macro( 34, data) +#define MREPEAT36( macro, data) MREPEAT35( macro, data) macro( 35, data) +#define MREPEAT37( macro, data) MREPEAT36( macro, data) macro( 36, data) +#define MREPEAT38( macro, data) MREPEAT37( macro, data) macro( 37, data) +#define MREPEAT39( macro, data) MREPEAT38( macro, data) macro( 38, data) +#define MREPEAT40( macro, data) MREPEAT39( macro, data) macro( 39, data) +#define MREPEAT41( macro, data) MREPEAT40( macro, data) macro( 40, data) +#define MREPEAT42( macro, data) MREPEAT41( macro, data) macro( 41, data) +#define MREPEAT43( macro, data) MREPEAT42( macro, data) macro( 42, data) +#define MREPEAT44( macro, data) MREPEAT43( macro, data) macro( 43, data) +#define MREPEAT45( macro, data) MREPEAT44( macro, data) macro( 44, data) +#define MREPEAT46( macro, data) MREPEAT45( macro, data) macro( 45, data) +#define MREPEAT47( macro, data) MREPEAT46( macro, data) macro( 46, data) +#define MREPEAT48( macro, data) MREPEAT47( macro, data) macro( 47, data) +#define MREPEAT49( macro, data) MREPEAT48( macro, data) macro( 48, data) +#define MREPEAT50( macro, data) MREPEAT49( macro, data) macro( 49, data) +#define MREPEAT51( macro, data) MREPEAT50( macro, data) macro( 50, data) +#define MREPEAT52( macro, data) MREPEAT51( macro, data) macro( 51, data) +#define MREPEAT53( macro, data) MREPEAT52( macro, data) macro( 52, data) +#define MREPEAT54( macro, data) MREPEAT53( macro, data) macro( 53, data) +#define MREPEAT55( macro, data) MREPEAT54( macro, data) macro( 54, data) +#define MREPEAT56( macro, data) MREPEAT55( macro, data) macro( 55, data) +#define MREPEAT57( macro, data) MREPEAT56( macro, data) macro( 56, data) +#define MREPEAT58( macro, data) MREPEAT57( macro, data) macro( 57, data) +#define MREPEAT59( macro, data) MREPEAT58( macro, data) macro( 58, data) +#define MREPEAT60( macro, data) MREPEAT59( macro, data) macro( 59, data) +#define MREPEAT61( macro, data) MREPEAT60( macro, data) macro( 60, data) +#define MREPEAT62( macro, data) MREPEAT61( macro, data) macro( 61, data) +#define MREPEAT63( macro, data) MREPEAT62( macro, data) macro( 62, data) +#define MREPEAT64( macro, data) MREPEAT63( macro, data) macro( 63, data) +#define MREPEAT65( macro, data) MREPEAT64( macro, data) macro( 64, data) +#define MREPEAT66( macro, data) MREPEAT65( macro, data) macro( 65, data) +#define MREPEAT67( macro, data) MREPEAT66( macro, data) macro( 66, data) +#define MREPEAT68( macro, data) MREPEAT67( macro, data) macro( 67, data) +#define MREPEAT69( macro, data) MREPEAT68( macro, data) macro( 68, data) +#define MREPEAT70( macro, data) MREPEAT69( macro, data) macro( 69, data) +#define MREPEAT71( macro, data) MREPEAT70( macro, data) macro( 70, data) +#define MREPEAT72( macro, data) MREPEAT71( macro, data) macro( 71, data) +#define MREPEAT73( macro, data) MREPEAT72( macro, data) macro( 72, data) +#define MREPEAT74( macro, data) MREPEAT73( macro, data) macro( 73, data) +#define MREPEAT75( macro, data) MREPEAT74( macro, data) macro( 74, data) +#define MREPEAT76( macro, data) MREPEAT75( macro, data) macro( 75, data) +#define MREPEAT77( macro, data) MREPEAT76( macro, data) macro( 76, data) +#define MREPEAT78( macro, data) MREPEAT77( macro, data) macro( 77, data) +#define MREPEAT79( macro, data) MREPEAT78( macro, data) macro( 78, data) +#define MREPEAT80( macro, data) MREPEAT79( macro, data) macro( 79, data) +#define MREPEAT81( macro, data) MREPEAT80( macro, data) macro( 80, data) +#define MREPEAT82( macro, data) MREPEAT81( macro, data) macro( 81, data) +#define MREPEAT83( macro, data) MREPEAT82( macro, data) macro( 82, data) +#define MREPEAT84( macro, data) MREPEAT83( macro, data) macro( 83, data) +#define MREPEAT85( macro, data) MREPEAT84( macro, data) macro( 84, data) +#define MREPEAT86( macro, data) MREPEAT85( macro, data) macro( 85, data) +#define MREPEAT87( macro, data) MREPEAT86( macro, data) macro( 86, data) +#define MREPEAT88( macro, data) MREPEAT87( macro, data) macro( 87, data) +#define MREPEAT89( macro, data) MREPEAT88( macro, data) macro( 88, data) +#define MREPEAT90( macro, data) MREPEAT89( macro, data) macro( 89, data) +#define MREPEAT91( macro, data) MREPEAT90( macro, data) macro( 90, data) +#define MREPEAT92( macro, data) MREPEAT91( macro, data) macro( 91, data) +#define MREPEAT93( macro, data) MREPEAT92( macro, data) macro( 92, data) +#define MREPEAT94( macro, data) MREPEAT93( macro, data) macro( 93, data) +#define MREPEAT95( macro, data) MREPEAT94( macro, data) macro( 94, data) +#define MREPEAT96( macro, data) MREPEAT95( macro, data) macro( 95, data) +#define MREPEAT97( macro, data) MREPEAT96( macro, data) macro( 96, data) +#define MREPEAT98( macro, data) MREPEAT97( macro, data) macro( 97, data) +#define MREPEAT99( macro, data) MREPEAT98( macro, data) macro( 98, data) +#define MREPEAT100(macro, data) MREPEAT99( macro, data) macro( 99, data) +#define MREPEAT101(macro, data) MREPEAT100(macro, data) macro(100, data) +#define MREPEAT102(macro, data) MREPEAT101(macro, data) macro(101, data) +#define MREPEAT103(macro, data) MREPEAT102(macro, data) macro(102, data) +#define MREPEAT104(macro, data) MREPEAT103(macro, data) macro(103, data) +#define MREPEAT105(macro, data) MREPEAT104(macro, data) macro(104, data) +#define MREPEAT106(macro, data) MREPEAT105(macro, data) macro(105, data) +#define MREPEAT107(macro, data) MREPEAT106(macro, data) macro(106, data) +#define MREPEAT108(macro, data) MREPEAT107(macro, data) macro(107, data) +#define MREPEAT109(macro, data) MREPEAT108(macro, data) macro(108, data) +#define MREPEAT110(macro, data) MREPEAT109(macro, data) macro(109, data) +#define MREPEAT111(macro, data) MREPEAT110(macro, data) macro(110, data) +#define MREPEAT112(macro, data) MREPEAT111(macro, data) macro(111, data) +#define MREPEAT113(macro, data) MREPEAT112(macro, data) macro(112, data) +#define MREPEAT114(macro, data) MREPEAT113(macro, data) macro(113, data) +#define MREPEAT115(macro, data) MREPEAT114(macro, data) macro(114, data) +#define MREPEAT116(macro, data) MREPEAT115(macro, data) macro(115, data) +#define MREPEAT117(macro, data) MREPEAT116(macro, data) macro(116, data) +#define MREPEAT118(macro, data) MREPEAT117(macro, data) macro(117, data) +#define MREPEAT119(macro, data) MREPEAT118(macro, data) macro(118, data) +#define MREPEAT120(macro, data) MREPEAT119(macro, data) macro(119, data) +#define MREPEAT121(macro, data) MREPEAT120(macro, data) macro(120, data) +#define MREPEAT122(macro, data) MREPEAT121(macro, data) macro(121, data) +#define MREPEAT123(macro, data) MREPEAT122(macro, data) macro(122, data) +#define MREPEAT124(macro, data) MREPEAT123(macro, data) macro(123, data) +#define MREPEAT125(macro, data) MREPEAT124(macro, data) macro(124, data) +#define MREPEAT126(macro, data) MREPEAT125(macro, data) macro(125, data) +#define MREPEAT127(macro, data) MREPEAT126(macro, data) macro(126, data) +#define MREPEAT128(macro, data) MREPEAT127(macro, data) macro(127, data) +#define MREPEAT129(macro, data) MREPEAT128(macro, data) macro(128, data) +#define MREPEAT130(macro, data) MREPEAT129(macro, data) macro(129, data) +#define MREPEAT131(macro, data) MREPEAT130(macro, data) macro(130, data) +#define MREPEAT132(macro, data) MREPEAT131(macro, data) macro(131, data) +#define MREPEAT133(macro, data) MREPEAT132(macro, data) macro(132, data) +#define MREPEAT134(macro, data) MREPEAT133(macro, data) macro(133, data) +#define MREPEAT135(macro, data) MREPEAT134(macro, data) macro(134, data) +#define MREPEAT136(macro, data) MREPEAT135(macro, data) macro(135, data) +#define MREPEAT137(macro, data) MREPEAT136(macro, data) macro(136, data) +#define MREPEAT138(macro, data) MREPEAT137(macro, data) macro(137, data) +#define MREPEAT139(macro, data) MREPEAT138(macro, data) macro(138, data) +#define MREPEAT140(macro, data) MREPEAT139(macro, data) macro(139, data) +#define MREPEAT141(macro, data) MREPEAT140(macro, data) macro(140, data) +#define MREPEAT142(macro, data) MREPEAT141(macro, data) macro(141, data) +#define MREPEAT143(macro, data) MREPEAT142(macro, data) macro(142, data) +#define MREPEAT144(macro, data) MREPEAT143(macro, data) macro(143, data) +#define MREPEAT145(macro, data) MREPEAT144(macro, data) macro(144, data) +#define MREPEAT146(macro, data) MREPEAT145(macro, data) macro(145, data) +#define MREPEAT147(macro, data) MREPEAT146(macro, data) macro(146, data) +#define MREPEAT148(macro, data) MREPEAT147(macro, data) macro(147, data) +#define MREPEAT149(macro, data) MREPEAT148(macro, data) macro(148, data) +#define MREPEAT150(macro, data) MREPEAT149(macro, data) macro(149, data) +#define MREPEAT151(macro, data) MREPEAT150(macro, data) macro(150, data) +#define MREPEAT152(macro, data) MREPEAT151(macro, data) macro(151, data) +#define MREPEAT153(macro, data) MREPEAT152(macro, data) macro(152, data) +#define MREPEAT154(macro, data) MREPEAT153(macro, data) macro(153, data) +#define MREPEAT155(macro, data) MREPEAT154(macro, data) macro(154, data) +#define MREPEAT156(macro, data) MREPEAT155(macro, data) macro(155, data) +#define MREPEAT157(macro, data) MREPEAT156(macro, data) macro(156, data) +#define MREPEAT158(macro, data) MREPEAT157(macro, data) macro(157, data) +#define MREPEAT159(macro, data) MREPEAT158(macro, data) macro(158, data) +#define MREPEAT160(macro, data) MREPEAT159(macro, data) macro(159, data) +#define MREPEAT161(macro, data) MREPEAT160(macro, data) macro(160, data) +#define MREPEAT162(macro, data) MREPEAT161(macro, data) macro(161, data) +#define MREPEAT163(macro, data) MREPEAT162(macro, data) macro(162, data) +#define MREPEAT164(macro, data) MREPEAT163(macro, data) macro(163, data) +#define MREPEAT165(macro, data) MREPEAT164(macro, data) macro(164, data) +#define MREPEAT166(macro, data) MREPEAT165(macro, data) macro(165, data) +#define MREPEAT167(macro, data) MREPEAT166(macro, data) macro(166, data) +#define MREPEAT168(macro, data) MREPEAT167(macro, data) macro(167, data) +#define MREPEAT169(macro, data) MREPEAT168(macro, data) macro(168, data) +#define MREPEAT170(macro, data) MREPEAT169(macro, data) macro(169, data) +#define MREPEAT171(macro, data) MREPEAT170(macro, data) macro(170, data) +#define MREPEAT172(macro, data) MREPEAT171(macro, data) macro(171, data) +#define MREPEAT173(macro, data) MREPEAT172(macro, data) macro(172, data) +#define MREPEAT174(macro, data) MREPEAT173(macro, data) macro(173, data) +#define MREPEAT175(macro, data) MREPEAT174(macro, data) macro(174, data) +#define MREPEAT176(macro, data) MREPEAT175(macro, data) macro(175, data) +#define MREPEAT177(macro, data) MREPEAT176(macro, data) macro(176, data) +#define MREPEAT178(macro, data) MREPEAT177(macro, data) macro(177, data) +#define MREPEAT179(macro, data) MREPEAT178(macro, data) macro(178, data) +#define MREPEAT180(macro, data) MREPEAT179(macro, data) macro(179, data) +#define MREPEAT181(macro, data) MREPEAT180(macro, data) macro(180, data) +#define MREPEAT182(macro, data) MREPEAT181(macro, data) macro(181, data) +#define MREPEAT183(macro, data) MREPEAT182(macro, data) macro(182, data) +#define MREPEAT184(macro, data) MREPEAT183(macro, data) macro(183, data) +#define MREPEAT185(macro, data) MREPEAT184(macro, data) macro(184, data) +#define MREPEAT186(macro, data) MREPEAT185(macro, data) macro(185, data) +#define MREPEAT187(macro, data) MREPEAT186(macro, data) macro(186, data) +#define MREPEAT188(macro, data) MREPEAT187(macro, data) macro(187, data) +#define MREPEAT189(macro, data) MREPEAT188(macro, data) macro(188, data) +#define MREPEAT190(macro, data) MREPEAT189(macro, data) macro(189, data) +#define MREPEAT191(macro, data) MREPEAT190(macro, data) macro(190, data) +#define MREPEAT192(macro, data) MREPEAT191(macro, data) macro(191, data) +#define MREPEAT193(macro, data) MREPEAT192(macro, data) macro(192, data) +#define MREPEAT194(macro, data) MREPEAT193(macro, data) macro(193, data) +#define MREPEAT195(macro, data) MREPEAT194(macro, data) macro(194, data) +#define MREPEAT196(macro, data) MREPEAT195(macro, data) macro(195, data) +#define MREPEAT197(macro, data) MREPEAT196(macro, data) macro(196, data) +#define MREPEAT198(macro, data) MREPEAT197(macro, data) macro(197, data) +#define MREPEAT199(macro, data) MREPEAT198(macro, data) macro(198, data) +#define MREPEAT200(macro, data) MREPEAT199(macro, data) macro(199, data) +#define MREPEAT201(macro, data) MREPEAT200(macro, data) macro(200, data) +#define MREPEAT202(macro, data) MREPEAT201(macro, data) macro(201, data) +#define MREPEAT203(macro, data) MREPEAT202(macro, data) macro(202, data) +#define MREPEAT204(macro, data) MREPEAT203(macro, data) macro(203, data) +#define MREPEAT205(macro, data) MREPEAT204(macro, data) macro(204, data) +#define MREPEAT206(macro, data) MREPEAT205(macro, data) macro(205, data) +#define MREPEAT207(macro, data) MREPEAT206(macro, data) macro(206, data) +#define MREPEAT208(macro, data) MREPEAT207(macro, data) macro(207, data) +#define MREPEAT209(macro, data) MREPEAT208(macro, data) macro(208, data) +#define MREPEAT210(macro, data) MREPEAT209(macro, data) macro(209, data) +#define MREPEAT211(macro, data) MREPEAT210(macro, data) macro(210, data) +#define MREPEAT212(macro, data) MREPEAT211(macro, data) macro(211, data) +#define MREPEAT213(macro, data) MREPEAT212(macro, data) macro(212, data) +#define MREPEAT214(macro, data) MREPEAT213(macro, data) macro(213, data) +#define MREPEAT215(macro, data) MREPEAT214(macro, data) macro(214, data) +#define MREPEAT216(macro, data) MREPEAT215(macro, data) macro(215, data) +#define MREPEAT217(macro, data) MREPEAT216(macro, data) macro(216, data) +#define MREPEAT218(macro, data) MREPEAT217(macro, data) macro(217, data) +#define MREPEAT219(macro, data) MREPEAT218(macro, data) macro(218, data) +#define MREPEAT220(macro, data) MREPEAT219(macro, data) macro(219, data) +#define MREPEAT221(macro, data) MREPEAT220(macro, data) macro(220, data) +#define MREPEAT222(macro, data) MREPEAT221(macro, data) macro(221, data) +#define MREPEAT223(macro, data) MREPEAT222(macro, data) macro(222, data) +#define MREPEAT224(macro, data) MREPEAT223(macro, data) macro(223, data) +#define MREPEAT225(macro, data) MREPEAT224(macro, data) macro(224, data) +#define MREPEAT226(macro, data) MREPEAT225(macro, data) macro(225, data) +#define MREPEAT227(macro, data) MREPEAT226(macro, data) macro(226, data) +#define MREPEAT228(macro, data) MREPEAT227(macro, data) macro(227, data) +#define MREPEAT229(macro, data) MREPEAT228(macro, data) macro(228, data) +#define MREPEAT230(macro, data) MREPEAT229(macro, data) macro(229, data) +#define MREPEAT231(macro, data) MREPEAT230(macro, data) macro(230, data) +#define MREPEAT232(macro, data) MREPEAT231(macro, data) macro(231, data) +#define MREPEAT233(macro, data) MREPEAT232(macro, data) macro(232, data) +#define MREPEAT234(macro, data) MREPEAT233(macro, data) macro(233, data) +#define MREPEAT235(macro, data) MREPEAT234(macro, data) macro(234, data) +#define MREPEAT236(macro, data) MREPEAT235(macro, data) macro(235, data) +#define MREPEAT237(macro, data) MREPEAT236(macro, data) macro(236, data) +#define MREPEAT238(macro, data) MREPEAT237(macro, data) macro(237, data) +#define MREPEAT239(macro, data) MREPEAT238(macro, data) macro(238, data) +#define MREPEAT240(macro, data) MREPEAT239(macro, data) macro(239, data) +#define MREPEAT241(macro, data) MREPEAT240(macro, data) macro(240, data) +#define MREPEAT242(macro, data) MREPEAT241(macro, data) macro(241, data) +#define MREPEAT243(macro, data) MREPEAT242(macro, data) macro(242, data) +#define MREPEAT244(macro, data) MREPEAT243(macro, data) macro(243, data) +#define MREPEAT245(macro, data) MREPEAT244(macro, data) macro(244, data) +#define MREPEAT246(macro, data) MREPEAT245(macro, data) macro(245, data) +#define MREPEAT247(macro, data) MREPEAT246(macro, data) macro(246, data) +#define MREPEAT248(macro, data) MREPEAT247(macro, data) macro(247, data) +#define MREPEAT249(macro, data) MREPEAT248(macro, data) macro(248, data) +#define MREPEAT250(macro, data) MREPEAT249(macro, data) macro(249, data) +#define MREPEAT251(macro, data) MREPEAT250(macro, data) macro(250, data) +#define MREPEAT252(macro, data) MREPEAT251(macro, data) macro(251, data) +#define MREPEAT253(macro, data) MREPEAT252(macro, data) macro(252, data) +#define MREPEAT254(macro, data) MREPEAT253(macro, data) macro(253, data) +#define MREPEAT255(macro, data) MREPEAT254(macro, data) macro(254, data) +#define MREPEAT256(macro, data) MREPEAT255(macro, data) macro(255, data) + +/** + * \} + */ + +#endif // _MREPEAT_H_ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/preprocessor/preprocessor.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/preprocessor/preprocessor.h new file mode 100644 index 000000000..abf2c11eb --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/preprocessor/preprocessor.h @@ -0,0 +1,45 @@ +/** + * \file + * + * \brief Preprocessor utils. + * + * Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _PREPROCESSOR_H_ +#define _PREPROCESSOR_H_ + +#include "tpaste.h" +#include "stringz.h" +#include "mrepeat.h" + + +#endif // _PREPROCESSOR_H_ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/preprocessor/stringz.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/preprocessor/stringz.h new file mode 100644 index 000000000..8e9170411 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/preprocessor/stringz.h @@ -0,0 +1,75 @@ +/** + * \file + * + * \brief Preprocessor stringizing utils. + * + * Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _STRINGZ_H_ +#define _STRINGZ_H_ + +/** + * \defgroup group_sam_utils_stringz Preprocessor - Stringize + * + * \ingroup group_sam_utils + * + * \{ + */ + +/*! \brief Stringize. + * + * Stringize a preprocessing token, this token being allowed to be \#defined. + * + * May be used only within macros with the token passed as an argument if the token is \#defined. + * + * For example, writing STRINGZ(PIN) within a macro \#defined by PIN_NAME(PIN) + * and invoked as PIN_NAME(PIN0) with PIN0 \#defined as A0 is equivalent to + * writing "A0". + */ +#define STRINGZ(x) #x + +/*! \brief Absolute stringize. + * + * Stringize a preprocessing token, this token being allowed to be \#defined. + * + * No restriction of use if the token is \#defined. + * + * For example, writing ASTRINGZ(PIN0) anywhere with PIN0 \#defined as A0 is + * equivalent to writing "A0". + */ +#define ASTRINGZ(x) STRINGZ(x) + +/** + * \} + */ + +#endif // _STRINGZ_H_ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/preprocessor/tpaste.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/preprocessor/tpaste.h new file mode 100644 index 000000000..684992890 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/preprocessor/tpaste.h @@ -0,0 +1,95 @@ +/** + * \file + * + * \brief Preprocessor token pasting utils. + * + * Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef _TPASTE_H_ +#define _TPASTE_H_ + +/** + * \defgroup group_sam_utils_tpaste Preprocessor - Token Paste + * + * \ingroup group_sam_utils + * + * \{ + */ + +/*! \name Token Paste + * + * Paste N preprocessing tokens together, these tokens being allowed to be \#defined. + * + * May be used only within macros with the tokens passed as arguments if the tokens are \#defined. + * + * For example, writing TPASTE2(U, WIDTH) within a macro \#defined by + * UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH \#defined as 32 is + * equivalent to writing U32. + */ +//! @{ +#define TPASTE2( a, b) a##b +#define TPASTE3( a, b, c) a##b##c +#define TPASTE4( a, b, c, d) a##b##c##d +#define TPASTE5( a, b, c, d, e) a##b##c##d##e +#define TPASTE6( a, b, c, d, e, f) a##b##c##d##e##f +#define TPASTE7( a, b, c, d, e, f, g) a##b##c##d##e##f##g +#define TPASTE8( a, b, c, d, e, f, g, h) a##b##c##d##e##f##g##h +#define TPASTE9( a, b, c, d, e, f, g, h, i) a##b##c##d##e##f##g##h##i +#define TPASTE10(a, b, c, d, e, f, g, h, i, j) a##b##c##d##e##f##g##h##i##j +//! @} + +/*! \name Absolute Token Paste + * + * Paste N preprocessing tokens together, these tokens being allowed to be \#defined. + * + * No restriction of use if the tokens are \#defined. + * + * For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH \#defined + * as 32 is equivalent to writing U32. + */ +//! @{ +#define ATPASTE2( a, b) TPASTE2( a, b) +#define ATPASTE3( a, b, c) TPASTE3( a, b, c) +#define ATPASTE4( a, b, c, d) TPASTE4( a, b, c, d) +#define ATPASTE5( a, b, c, d, e) TPASTE5( a, b, c, d, e) +#define ATPASTE6( a, b, c, d, e, f) TPASTE6( a, b, c, d, e, f) +#define ATPASTE7( a, b, c, d, e, f, g) TPASTE7( a, b, c, d, e, f, g) +#define ATPASTE8( a, b, c, d, e, f, g, h) TPASTE8( a, b, c, d, e, f, g, h) +#define ATPASTE9( a, b, c, d, e, f, g, h, i) TPASTE9( a, b, c, d, e, f, g, h, i) +#define ATPASTE10(a, b, c, d, e, f, g, h, i, j) TPASTE10(a, b, c, d, e, f, g, h, i, j) +//! @} + +/** + * \} + */ + +#endif // _TPASTE_H_ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/status_codes.h b/hw-libs/drivers/SAMx70/ASF/sam/utils/status_codes.h new file mode 100644 index 000000000..225e751b5 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/status_codes.h @@ -0,0 +1,103 @@ +/** + * \file + * + * \brief Status code definitions. + * + * This file defines various status codes returned by functions, + * indicating success or failure as well as what kind of failure. + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef STATUS_CODES_H_INCLUDED +#define STATUS_CODES_H_INCLUDED + +/* Note: this is a local workaround to avoid a pre-processor clash due to the + * lwIP macro ERR_TIMEOUT. */ +#if (defined(LWIP_HDR_ERR_H) || defined(__LWIP_ERR_H__)) && defined(ERR_TIMEOUT) +#if (ERR_TIMEOUT != -3) + +/* Internal check to make sure that the later restore of lwIP's ERR_TIMEOUT + * macro is set to the correct value. Note that it is highly improbable that + * this value ever changes in lwIP. */ +#error ASF developers: check lwip err.h new value for ERR_TIMEOUT +#endif +#undef ERR_TIMEOUT +#endif + +/** + * Status code that may be returned by shell commands and protocol + * implementations. + * + * \note Any change to these status codes and the corresponding + * message strings is strictly forbidden. New codes can be added, + * however, but make sure that any message string tables are updated + * at the same time. + */ +enum status_code { + STATUS_OK = 0, //!< Success + STATUS_ERR_BUSY = 0x19, + STATUS_ERR_DENIED = 0x1C, + STATUS_ERR_TIMEOUT = 0x12, + ERR_IO_ERROR = -1, //!< I/O error + ERR_FLUSHED = -2, //!< Request flushed from queue + ERR_TIMEOUT = -3, //!< Operation timed out + ERR_BAD_DATA = -4, //!< Data integrity check failed + ERR_PROTOCOL = -5, //!< Protocol error + ERR_UNSUPPORTED_DEV = -6, //!< Unsupported device + ERR_NO_MEMORY = -7, //!< Insufficient memory + ERR_INVALID_ARG = -8, //!< Invalid argument + ERR_BAD_ADDRESS = -9, //!< Bad address + ERR_BUSY = -10, //!< Resource is busy + ERR_BAD_FORMAT = -11, //!< Data format not recognized + ERR_NO_TIMER = -12, //!< No timer available + ERR_TIMER_ALREADY_RUNNING = -13, //!< Timer already running + ERR_TIMER_NOT_RUNNING = -14, //!< Timer not running + ERR_ABORTED = -15, //!< Operation aborted by user + /** + * \brief Operation in progress + * + * This status code is for driver-internal use when an operation + * is currently being performed. + * + * \note Drivers should never return this status code to any + * callers. It is strictly for internal use. + */ + OPERATION_IN_PROGRESS = -128, +}; + +typedef enum status_code status_code_t; + +#if defined(LWIP_HDR_ERR_H) +#define ERR_TIMEOUT -3 +#endif + +#endif /* STATUS_CODES_H_INCLUDED */ diff --git a/hw-libs/drivers/SAMx70/ASF/sam/utils/syscalls/gcc/syscalls.c b/hw-libs/drivers/SAMx70/ASF/sam/utils/syscalls/gcc/syscalls.c new file mode 100644 index 000000000..d74ba7179 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/sam/utils/syscalls/gcc/syscalls.c @@ -0,0 +1,134 @@ +/** + * \file + * + * \brief Syscalls for SAM (GCC). + * + * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include +#include +#include +#include + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +#undef errno +extern int errno; +extern int _end; +extern int __ram_end__; + +extern caddr_t _sbrk(int incr); +extern int link(char *old, char *new); +extern int _close(int file); +extern int _fstat(int file, struct stat *st); +extern int _isatty(int file); +extern int _lseek(int file, int ptr, int dir); +extern void _exit(int status); +extern void _kill(int pid, int sig); +extern int _getpid(void); + +extern caddr_t _sbrk(int incr) +{ + static unsigned char *heap = NULL; + unsigned char *prev_heap; + int ramend = (int)&__ram_end__; + + if (heap == NULL) { + heap = (unsigned char *)&_end; + } + prev_heap = heap; + + if (((int)prev_heap + incr) > ramend) { + return (caddr_t) -1; + } + + heap += incr; + + return (caddr_t) prev_heap; +} + +extern int link(char *old, char *new) +{ + return -1; +} + +extern int _close(int file) +{ + return -1; +} + +extern int _fstat(int file, struct stat *st) +{ + st->st_mode = S_IFCHR; + + return 0; +} + +extern int _isatty(int file) +{ + return 1; +} + +extern int _lseek(int file, int ptr, int dir) +{ + return 0; +} + +extern void _exit(int status) +{ + asm("BKPT #0"); + for (;;); +} + +extern void _kill(int pid, int sig) +{ + return; +} + +extern int _getpid(void) +{ + return -1; +} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/ATMEL-disclaimer.txt b/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/ATMEL-disclaimer.txt new file mode 100644 index 000000000..422f7fe86 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/ATMEL-disclaimer.txt @@ -0,0 +1,20 @@ +/* + * Only the CMSIS required parts for ASF are included here, go to the below + * address for the full package: + * http://www.arm.com/products/processors/cortex-m/cortex-microcontroller-software-interface-standard.php + * + * The library file thirdparty/CMSIS/Lib/GCC/libarm_cortexM4lf_math_softfp.a was generated by ATMEL, which + * is support -mfloat-abi=softfp compiler flag, and this is also the default selection for device that + * have FPU module and enabled. + * If customer want to use -mfloat-abi=hard compiler flag, the project compile/link flag and link library + * should be manual modified. The library thirdparty/CMSIS/Lib/GCC/libarm_cortexM4lf_math.a is used for + * -mfloat-abi=hard configration. + * + * __CORTEX_SC is not defined for cortex-m0+, and may cause compiler warning, so the include file + * thirdparty/CMSIS/Include/core_cmInstr.h was modified to void such warning. + * Modified from: + * #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + * to: + * #if (__CORTEX_M >= 0x03) || ((defined(__CORTEX_SC)) && (__CORTEX_SC >= 300)) + * + */ diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf b/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf new file mode 100644 index 000000000..b37436693 Binary files /dev/null and b/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf differ diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/Include/arm_common_tables.h b/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/Include/arm_common_tables.h new file mode 100644 index 000000000..76aadca49 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/Include/arm_common_tables.h @@ -0,0 +1,136 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 31. July 2014 +* $Revision: V1.4.4 +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.h +* +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +//extern const q31_t realCoefAQ31[1024]; +//extern const q31_t realCoefBQ31[1024]; +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_4096_q15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + + +/* floating-point bit reversal tables */ +#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) +#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) +#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) +#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; + +/* fixed-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) +#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) +#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) +#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) +#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) +#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/Include/arm_const_structs.h b/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/Include/arm_const_structs.h new file mode 100644 index 000000000..217f1d50e --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/Include/arm_const_structs.h @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 31. July 2014 +* $Revision: V1.4.4 +* +* Project: CMSIS DSP Library +* Title: arm_const_structs.h +* +* Description: This file has constant structs that are initialized for +* user convenience. For example, some can be given as +* arguments to the arm_cfft_f32() function. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/Include/arm_math.h b/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/Include/arm_math.h new file mode 100644 index 000000000..f06a0713e --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/Include/arm_math.h @@ -0,0 +1,7538 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 12. March 2014 +* $Revision: V1.4.4 +* +* Project: CMSIS DSP Library +* Title: arm_math.h +* +* Description: Public header file for CMSIS DSP Library +* +* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) + * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) + * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) + * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) + * - arm_cortexM0l_math.lib (Little endian on Cortex-M0) + * - arm_cortexM0b_math.lib (Big endian on Cortex-M3) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK-ARM version 4.60. + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvproj + * + * + * The libraries can be built by opening the arm_cortexM_math.uvproj project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. + * + * Pre-processor Macros + * ------------ + * + * Each library project have differant pre-processor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2014 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + *
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * 
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + *
+ *     pData[i*numCols + j]
+ * 
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + *
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ * 
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + *
+ *     ARM_MATH_SIZE_MISMATCH
+ * 
+ * Otherwise the functions return + *
+ *     ARM_MATH_SUCCESS
+ * 
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + *
+ *     ARM_MATH_MATRIX_CHECK
+ * 
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" +#define ARM_MATH_CM0_FAMILY + #elif defined (ARM_MATH_CM0PLUS) +#include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI +#define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined __CC_ARM +#define __SIMD32_TYPE int32_t __packed +#define CMSIS_UNUSED __attribute__((unused)) +#elif defined __ICCARM__ +#define CMSIS_UNUSED +#define __SIMD32_TYPE int32_t __packed +#elif defined __GNUC__ +#define __SIMD32_TYPE int32_t +#define CMSIS_UNUSED __attribute__((unused)) +#elif defined __CSMC__ /* Cosmic */ +#define CMSIS_UNUSED +#define __SIMD32_TYPE int32_t +#else +#error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) + +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) + +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif + + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + static __INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + static __INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + static __INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + static __INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + static __INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + +#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) +#define __CLZ __clz +#endif + +#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) + + static __INLINE uint32_t __CLZ( + q31_t data); + + + static __INLINE uint32_t __CLZ( + q31_t data) + { + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } + + return (count); + + } + +#endif + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + static __INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + + uint32_t out, tempVal; + uint32_t index, i; + uint32_t signBits; + + if(in > 0) + { + signBits = __CLZ(in) - 1; + } + else + { + signBits = __CLZ(-in) - 1; + } + + /* Convert input sample to 1.31 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = (uint32_t) (in >> 24u); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (q31_t) (((q63_t) in * out) >> 31u); + tempVal = 0x7FFFFFFF - tempVal; + /* 1.31 with exp 1 */ + //out = (q31_t) (((q63_t) out * tempVal) >> 30u); + out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); + + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + static __INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + + uint32_t out = 0, tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if(in > 0) + { + signBits = __CLZ(in) - 17; + } + else + { + signBits = __CLZ(-in) - 17; + } + + /* Convert input sample to 1.15 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = in >> 8; + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0; i < 2; i++) + { + tempVal = (q15_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFF - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + + } + + + /* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0_FAMILY) + + static __INLINE q31_t __SSAT( + q31_t x, + uint32_t y) + { + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) + { + posMax = posMax * 2; + } + + if(x > 0) + { + posMax = (posMax - 1); + + if(x > posMax) + { + x = posMax; + } + } + else + { + negMin = -posMax; + + if(x < negMin) + { + x = negMin; + } + } + return (x); + + + } + +#endif /* end of ARM_MATH_CM0_FAMILY */ + + + + /* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + static __INLINE q31_t __QADD8( + q31_t x, + q31_t y) + { + + q31_t sum; + q7_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = __SSAT((q31_t) (r + s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); + t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); + u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); + + sum = + (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | + (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); + + return sum; + + } + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + static __INLINE q31_t __QSUB8( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = __SSAT((r - s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; + t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; + u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; + + sum = + (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & + 0x000000FF); + + return sum; + } + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + static __INLINE q31_t __QADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = __SSAT(r + s, 16); + s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + static __INLINE q31_t __SHADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) + (s >> 1)); + s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + static __INLINE q31_t __QSUB16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = __SSAT(r - s, 16); + s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + static __INLINE q31_t __SHSUB16( + q31_t x, + q31_t y) + { + + q31_t diff; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) - (s >> 1)); + s = (((x >> 17) - (y >> 17)) << 16); + + diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return diff; + } + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + static __INLINE q31_t __QASX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = + ((sum + + clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) + + clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + static __INLINE q31_t __SHASX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) - (y >> 17)); + s = (((x >> 17) + (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + static __INLINE q31_t __QSAX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = + ((sum + + clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) + + clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + static __INLINE q31_t __SHSAX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) + (y >> 17)); + s = (((x >> 17) - (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + static __INLINE q31_t __SMUSDX( + q31_t x, + q31_t y) + { + + return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) - + ((q15_t) (x >> 16) * (q15_t) y))); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + static __INLINE q31_t __SMUADX( + q31_t x, + q31_t y) + { + + return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) + + ((q15_t) (x >> 16) * (q15_t) y))); + } + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + static __INLINE q31_t __QADD( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x + y); + } + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + static __INLINE q31_t __QSUB( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x - y); + } + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + static __INLINE q31_t __SMLAD( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + + ((q15_t) x * (q15_t) y)); + } + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + static __INLINE q31_t __SMLADX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) + + ((q15_t) x * (q15_t) (y >> 16))); + } + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + static __INLINE q31_t __SMLSDX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) + + ((q15_t) x * (q15_t) (y >> 16))); + } + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + static __INLINE q63_t __SMLALD( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + + ((q15_t) x * (q15_t) y)); + } + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + static __INLINE q63_t __SMLALDX( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + + ((q15_t) x * (q15_t) (y >> 16)); + } + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + static __INLINE q31_t __SMUAD( + q31_t x, + q31_t y) + { + + return (((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + static __INLINE q31_t __SMUSD( + q31_t x, + q31_t y) + { + + return (-((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + static __INLINE q31_t __SXTB16( + q31_t x) + { + + return ((((x << 24) >> 24) & 0x0000FFFF) | + (((x << 8) >> 8) & 0xFFFF0000)); + } + + +#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] *S points to an instance of the Q7 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] *S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + * @return none + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] *S points to an instance of the Q15 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] *S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] *S points to an instance of the Q31 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] *S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] *S points to an instance of the floating-point FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] *S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q15; + + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + + + } arm_biquad_casd_df1_inst_f32; + + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q31; + + + + /** + * @brief Floating-point matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q31 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix scaling. + * @param[in] *pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] *pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + /** + * @brief Q15 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#ifdef ARM_MATH_CM0_FAMILY + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] *S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @return none + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @return none + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the q15 PID Control structure + * @return none + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + + + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q31 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q15 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + /** + * @brief Floating-point vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Dot product of floating-point vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + /** + * @brief Dot product of Q7 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + /** + * @brief Dot product of Q15 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Dot product of Q31 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + + + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_f32; + + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the Q15 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + * @return none. + */ + + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + + } arm_lms_instance_q31; + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Correlation of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. + */ + + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + /** + * @brief Correlation of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /* + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cos output. + * @return none. + */ + + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCcosVal); + + /* + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cosine output. + * @return none. + */ + + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + *
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd  
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + + + static __INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + + static __INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + + static __INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#ifndef ARM_MATH_CM0_FAMILY + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD(S->A0, in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = __SMLALD(S->A1, (q31_t) *vstate, acc); + +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; + +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] *src points to the instance of the input floating-point matrix structure. + * @param[out] *dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] *src points to the instance of the input floating-point matrix structure. + * @param[out] *dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + */ + + static __INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = + ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + + } + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + static __INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + */ + + + static __INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; + + } + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + + static __INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * The function implements the forward Park transform. + * + */ + + static __INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + + } + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + + + static __INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + */ + + static __INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + + static __INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + *
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * 
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + + static __INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if(i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] *pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + static __INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + + } + + } + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] *pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + static __INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20u); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (y >> 20); + } + + + } + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] *pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + + + static __INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + + if(index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (y >> 20u); + + } + + } + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + + float32_t arm_sin_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q31_t arm_sin_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q15_t arm_sin_q15( + q15_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + + float32_t arm_cos_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q31_t arm_cos_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + *
+   *      x1 = x0 - f(x0)/f'(x0)
+   * 
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + *
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   * 
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + + static __INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if(in > 0) + { + +// #if __FPU_USED +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + + + + + /** + * @brief floating-point Circular write function. + */ + + static __INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + static __INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + /** + * @brief Q15 Circular write function. + */ + + static __INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q15 Circular Read function. + */ + static __INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + + static __INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q7 Circular Read function. + */ + static __INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + /** + * @brief Mean value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Mean value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Floating-point complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + /** + * @brief Q31 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + /** + * @brief Floating-point complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[in] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + * @return none. + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + *
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   * 
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + *
+   *     XF = floor(x)
+   *     YF = floor(y)
+   * 
+ * \par + * The interpolated output point is computed as: + *
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * 
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + + + static __INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 + || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + + } + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20u); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20u); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return (acc << 2u); + + } + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return (acc >> 36); + + } + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return (acc >> 40); + + } + + /** + * @} end of BilinearInterpolate group + */ + + +//SMMLAR +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +//SMMLSR +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +//SMMULR +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +//SMMLA +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +//SMMLS +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +//SMMUL +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) //Keil + +//Enter low optimization region - place directly above function definition + #ifdef ARM_MATH_CM4 + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + +//Exit low optimization region - place directly after end of function definition + #ifdef ARM_MATH_CM4 + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + +//Enter low optimization region - place directly above function definition + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + +//Exit low optimization region - place directly after end of function definition + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ICCARM__) //IAR + +//Enter low optimization region - place directly above function definition + #ifdef ARM_MATH_CM4 + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + +//Exit low optimization region - place directly after end of function definition + #define LOW_OPTIMIZATION_EXIT + +//Enter low optimization region - place directly above function definition + #ifdef ARM_MATH_CM4 + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + +//Exit low optimization region - place directly after end of function definition + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__GNUC__) + + #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) + + #define LOW_OPTIMIZATION_EXIT + + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__CSMC__) // Cosmic + +#define LOW_OPTIMIZATION_ENTER +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/Include/core_cm7.h b/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/Include/core_cm7.h new file mode 100644 index 000000000..9ac91522f --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/Include/core_cm7.h @@ -0,0 +1,2223 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V4.00 + * @date 01. September 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ISBoards.h" + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M7 + @{ + */ + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x07) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ +#include /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000 + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0 + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0 + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0 + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0 + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x07) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x07) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1]; + __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93]; + __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15]; + __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ + uint32_t RESERVED5[1]; + __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1]; + __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __O uint32_t DCIMVAU; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6]; + __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1]; + __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/* Cache Level ID register */ +#define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* Cache Type register */ +#define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL << SCB_CTR_IMINLINE_Pos) /*!< SCB CTR: ImInLine Mask */ + +/* Cache Size ID Register */ +#define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL << SCB_CCSIDR_LINESIZE_Pos) /*!< SCB CCSIDR: LineSize Mask */ + +/* Cache Size Selection Register */ +#define SCB_CSSELR_LEVEL_Pos 0 /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (1UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL << SCB_CSSELR_IND_Pos) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register */ +#define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL << SCB_STIR_INTID_Pos) /*!< SCB STIR: INTID Mask */ + +/* Instruction Tightly-Coupled Memory Control Register*/ +#define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (0x1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (0x1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (0x1UL << SCB_ITCMCR_EN_Pos) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Registers */ +#define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL << SCB_DTCMCR_EN_Pos) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register */ +#define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL << SCB_AHBPCR_EN_Pos) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register */ +#define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL << SCB_CACR_SIWT_Pos) /*!< SCB CACR: SIWT Mask */ + +/* AHBS control register */ +#define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL << SCB_AHBPCR_CTL_Pos) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register */ +#define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL << SCB_ABFSR_ITCM_Pos) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ +/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## Cache functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) +#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) >> SCB_CCSIDR_LINESIZE_Pos ) + + +/** \brief Enable I-Cache + + The function turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache(void) +{ + #if (__ICACHE_PRESENT == 1) + __DSB(); + __ISB(); + SCB->ICIALLU = 0; // invalidate I-Cache + SCB->CCR |= SCB_CCR_IC_Msk; // enable I-Cache + __DSB(); + __ISB(); + #endif +} + + +/** \brief Disable I-Cache + + The function turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache(void) +{ + #if (__ICACHE_PRESENT == 1) + __DSB(); + __ISB(); + SCB->CCR &= ~SCB_CCR_IC_Msk; // disable I-Cache + SCB->ICIALLU = 0; // invalidate I-Cache + __DSB(); + __ISB(); + #endif +} + + +/** \brief Invalidate I-Cache + + The function invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache(void) +{ + #if (__ICACHE_PRESENT == 1) + __DSB(); + __ISB(); + SCB->ICIALLU = 0; + __DSB(); + __ISB(); + #endif +} + + +/** \brief Enable D-Cache + + The function turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache(void) +{ + #if (__DCACHE_PRESENT == 1) && (CONF_BOARD_ENABLE_DCACHE==1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do { // invalidate D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCISW = sw; + } while(tmpways--); + } while(sets--); + __DSB(); + + SCB->CCR |= SCB_CCR_DC_Msk; // enable D-Cache + + __DSB(); + __ISB(); + #endif +} + + +/** \brief Disable D-Cache + + The function turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache(void) +{ + #if (__DCACHE_PRESENT == 1) && (CONF_BOARD_ENABLE_DCACHE==1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + SCB->CCR &= ~SCB_CCR_DC_Msk; // disable D-Cache + + do { // clean & invalidate D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCCISW = sw; + } while(tmpways--); + } while(sets--); + + + __DSB(); + __ISB(); + #endif +} + + +/** \brief Invalidate D-Cache + + The function invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache(void) +{ + #if (__DCACHE_PRESENT == 1) && (CONF_BOARD_ENABLE_DCACHE==1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do { // invalidate D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCISW = sw; + } while(tmpways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** \brief Clean D-Cache + + The function cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache(void) +{ + #if (__DCACHE_PRESENT == 1) && (CONF_BOARD_ENABLE_DCACHE==1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do { // clean D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCCSW = sw; + } while(tmpways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** \brief Clean & Invalidate D-Cache + + The function cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache(void) +{ + #if (__DCACHE_PRESENT == 1) && (CONF_BOARD_ENABLE_DCACHE==1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do { // clean & invalidate D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCCISW = sw; + } while(tmpways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/Include/core_cmFunc.h b/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/Include/core_cmFunc.h new file mode 100644 index 000000000..01089f133 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/Include/core_cmFunc.h @@ -0,0 +1,637 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.00 + * @date 28. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/Include/core_cmInstr.h b/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/Include/core_cmInstr.h new file mode 100644 index 000000000..2e3bb0eab --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/Include/core_cmInstr.h @@ -0,0 +1,880 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.00 + * @date 28. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function executes a exclusive LDR instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function executes a exclusive LDR instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function executes a exclusive LDR instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function executes a exclusive STR instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function executes a exclusive STR instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function executes a exclusive STR instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +/** \brief Rotate Right with Extend (32 bit) + + This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. + + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constrant "l" + * Otherwise, use general registers, specified by constrant "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + uint32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32 - op2)); +} + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +#if (__CORTEX_M >= 0x03) || ((defined(__CORTEX_SC)) && (__CORTEX_SC >= 300)) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function executes a exclusive LDR instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (16 bit) + + This function executes a exclusive LDR instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (32 bit) + + This function executes a exclusive LDR instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function executes a exclusive STR instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function executes a exclusive STR instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function executes a exclusive STR instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief Rotate Right with Extend (32 bit) + + This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. + + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/Include/core_cmSimd.h b/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/Include/core_cmSimd.h new file mode 100644 index 000000000..ee58eee56 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/Include/core_cmSimd.h @@ -0,0 +1,697 @@ +/**************************************************************************//** + * @file core_cmSimd.h + * @brief CMSIS Cortex-M SIMD Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CMSIMD_H +#define __CORE_CMSIMD_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32) ) >> 32)) + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* not yet supported */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CMSIMD_H */ diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/Lib/GCC/libarm_cortexM7lfsp_math.a b/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/Lib/GCC/libarm_cortexM7lfsp_math.a new file mode 100644 index 000000000..b01e81b5a Binary files /dev/null and b/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/Lib/GCC/libarm_cortexM7lfsp_math.a differ diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/Lib/GCC/libarm_cortexM7lfsp_math_softfp.a b/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/Lib/GCC/libarm_cortexM7lfsp_math_softfp.a new file mode 100644 index 000000000..98266c910 Binary files /dev/null and b/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/Lib/GCC/libarm_cortexM7lfsp_math_softfp.a differ diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/Lib/license.txt b/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/Lib/license.txt new file mode 100644 index 000000000..139c1ff8d --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/Lib/license.txt @@ -0,0 +1,28 @@ +All pre-build libraries contained in the folders "ARM" and "GCC" +are guided by the following license: + +Copyright (C) 2009-2014 ARM Limited. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/README.txt b/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/README.txt new file mode 100644 index 000000000..e42a54334 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/CMSIS/README.txt @@ -0,0 +1,42 @@ +* ------------------------------------------------------------------- +* Copyright (C) 2011-2014 ARM Limited. All rights reserved. +* +* Date: 17 February 2014 +* Revision: V4.00 +* +* Project: Cortex Microcontroller Software Interface Standard (CMSIS) +* Title: Release Note for CMSIS +* +* ------------------------------------------------------------------- + + +NOTE - Open the index.html file to access CMSIS documentation + + +The Cortex Microcontroller Software Interface Standard (CMSIS) provides a single standard across all +Cortex-Mx processor series vendors. It enables code re-use and code sharing across software projects +and reduces time-to-market for new embedded applications. + +CMSIS is released under the terms of the end user license agreement ("CMSIS_END_USER_LICENCE_AGREEMENT.pdf"). +Any user of the software package is bound to the terms and conditions of the end user license agreement. + + +You will find the following sub-directories: + +Documentation - Contains CMSIS documentation. + +DSP_Lib - MDK project files, Examples and source files etc.. to build the + CMSIS DSP Software Library for Cortex-M0, Cortex-M3, Cortex-M4 processors. + +Include - CMSIS Core Support and CMSIS DSP Include Files. + +Lib - CMSIS DSP Libraries. + +RTOS - CMSIS RTOS API template header file. + +Driver - CMSIS Peripheral Driver Interface. + +Pack - CMSIS Software Packs. + Mechanism to install software, device support, APIs, and example projects. + +SVD - CMSIS SVD Schema files and Conversion Utility. diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/ATMEL-disclaimer.txt b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/ATMEL-disclaimer.txt new file mode 100644 index 000000000..d13657c66 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/ATMEL-disclaimer.txt @@ -0,0 +1,4 @@ +/* + * The fatfs folder contains a modified image of the FatFS r0.09 to + * fit with the Atmel Software Framework release. + */ diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-port-r0.09/diskio.c b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-port-r0.09/diskio.c new file mode 100644 index 000000000..b3c150078 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-port-r0.09/diskio.c @@ -0,0 +1,363 @@ +/** + * \file + * + * \brief Implementation of low level disk I/O module skeleton for FatFS. + * + * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +#include "compiler.h" +#include "diskio.h" +#include "ctrl_access.h" + +#include +#include +#include + +#if (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4N) +# include +#endif + +#if (SAM0) +# include +struct rtc_module rtc_instance; + +static void configure_rtc_calendar(void) +{ + /* Initialize RTC in calendar mode. */ + struct rtc_calendar_config config_rtc_calendar; + + rtc_calendar_get_config_defaults(&config_rtc_calendar); + + struct rtc_calendar_time init_time; + rtc_calendar_get_time_defaults(&init_time); + init_time.year = 2014; + init_time.month = 1; + init_time.day = 1; + init_time.hour = 0; + init_time.minute = 0; + init_time.second = 4; + + config_rtc_calendar.clock_24h = true; + config_rtc_calendar.alarm[0].time = init_time; + config_rtc_calendar.alarm[0].mask = RTC_CALENDAR_ALARM_MASK_YEAR; + + rtc_calendar_init(&rtc_instance, RTC, &config_rtc_calendar); + + rtc_calendar_enable(&rtc_instance); +} +#endif + +/** + * \defgroup thirdparty_fatfs_port_group Port of low level driver for FatFS + * + * Low level driver for FatFS. The driver is based on the ctrl access module + * of the specific MCU device. + * + * @{ + */ + +/** Default sector size */ +#define SECTOR_SIZE_DEFAULT 512 + +/** Supported sector size. These values are based on the LUN function: + * mem_sector_size(). */ +#define SECTOR_SIZE_512 1 +#define SECTOR_SIZE_1024 2 +#define SECTOR_SIZE_2048 4 +#define SECTOR_SIZE_4096 8 + +/** + * \brief Initialize a disk. + * + * \param drv Physical drive number (0..). + * + * \return 0 or disk status in combination of DSTATUS bits + * (STA_NOINIT, STA_PROTECT). + */ +DSTATUS disk_initialize(BYTE drv) +{ + int i; + Ctrl_status mem_status; + +#if (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S) + /* Default RTC configuration, 24-hour mode */ + rtc_set_hour_mode(RTC, 0); +#endif + +#if (SAMD20 || SAMD21 || SAMR21) + configure_rtc_calendar(); +#endif + +#if LUN_USB + /* USB disk with multiple LUNs */ + if (drv > LUN_ID_USB + Lun_usb_get_lun()) { + return STA_NOINIT; + } +#else + if (drv > MAX_LUN) { + /* At least one of the LUN should be defined */ + return STA_NOINIT; + } +#endif + /* Check LUN ready (USB disk report CTRL_BUSY then CTRL_GOOD) */ + for (i = 0; i < 2; i ++) { + mem_status = mem_test_unit_ready(drv); + if (CTRL_BUSY != mem_status) { + break; + } + } + if (mem_status != CTRL_GOOD) { + return STA_NOINIT; + } + + /* Check Write Protection Status */ + if (mem_wr_protect(drv)) { + return STA_PROTECT; + } + + /* The memory should already be initialized */ + return 0; +} + +/** + * \brief Return disk status. + * + * \param drv Physical drive number (0..). + * + * \return 0 or disk status in combination of DSTATUS bits + * (STA_NOINIT, STA_NODISK, STA_PROTECT). + */ +DSTATUS disk_status(BYTE drv) +{ + switch (mem_test_unit_ready(drv)) { + case CTRL_GOOD: + return 0; + case CTRL_NO_PRESENT: + return STA_NOINIT | STA_NODISK; + default: + return STA_NOINIT; + } +} + +/** + * \brief Read sector(s). + * + * \param drv Physical drive number (0..). + * \param buff Data buffer to store read data. + * \param sector Sector address (LBA). + * \param count Number of sectors to read (1..255). + * + * \return RES_OK for success, otherwise DRESULT error code. + */ +DRESULT disk_read(BYTE drv, BYTE *buff, DWORD sector, BYTE count) +{ +#if ACCESS_MEM_TO_RAM + uint8_t uc_sector_size = mem_sector_size(drv); + uint32_t i; + uint32_t ul_last_sector_num; + + if (uc_sector_size == 0) { + return RES_ERROR; + } + + /* Check valid address */ + mem_read_capacity(drv, &ul_last_sector_num); + if ((sector + count * uc_sector_size) > + (ul_last_sector_num + 1) * uc_sector_size) { + return RES_PARERR; + } + + /* Read the data */ + for (i = 0; i < count; i++) { + if (memory_2_ram(drv, sector + uc_sector_size * i, + buff + uc_sector_size * SECTOR_SIZE_DEFAULT * i) != + CTRL_GOOD) { + return RES_ERROR; + } + } + + return RES_OK; + +#else + return RES_ERROR; +#endif +} + +/** + * \brief Write sector(s). + * + * The FatFs module will issue multiple sector transfer request (count > 1) to + * the disk I/O layer. The disk function should process the multiple sector + * transfer properly. Do not translate it into multiple sector transfers to the + * media, or the data read/write performance may be drastically decreased. + * + * \param drv Physical drive number (0..). + * \param buff Data buffer to store read data. + * \param sector Sector address (LBA). + * \param count Number of sectors to read (1..255). + * + * \return RES_OK for success, otherwise DRESULT error code. + */ +#if _READONLY == 0 +DRESULT disk_write(BYTE drv, BYTE const *buff, DWORD sector, BYTE count) +{ +#if ACCESS_MEM_TO_RAM + uint8_t uc_sector_size = mem_sector_size(drv); + uint32_t i; + uint32_t ul_last_sector_num; + + if (uc_sector_size == 0) { + return RES_ERROR; + } + + /* Check valid address */ + mem_read_capacity(drv, &ul_last_sector_num); + if ((sector + count * uc_sector_size) > + (ul_last_sector_num + 1) * uc_sector_size) { + return RES_PARERR; + } + + /* Write the data */ + for (i = 0; i < count; i++) { + if (ram_2_memory(drv, sector + uc_sector_size * i, + buff + uc_sector_size * SECTOR_SIZE_DEFAULT * i) != + CTRL_GOOD) { + return RES_ERROR; + } + } + + return RES_OK; + +#else + return RES_ERROR; +#endif +} + +#endif /* _READONLY */ + +/** + * \brief Miscellaneous functions, which support the following commands: + * + * CTRL_SYNC Make sure that the disk drive has finished pending write + * process. When the disk I/O module has a write back cache, flush the + * dirty sector immediately. + * In read-only configuration, this command is not needed. + * + * GET_SECTOR_COUNT Return total sectors on the drive into the DWORD variable + * pointed by buffer. + * This command is used only in f_mkfs function. + * + * GET_BLOCK_SIZE Return erase block size of the memory array in unit + * of sector into the DWORD variable pointed by Buffer. + * When the erase block size is unknown or magnetic disk device, return 1. + * This command is used only in f_mkfs function. + * + * GET_SECTOR_SIZE Return sector size of the memory array. + * + * \param drv Physical drive number (0..). + * \param ctrl Control code. + * \param buff Buffer to send/receive control data. + * + * \return RES_OK for success, otherwise DRESULT error code. + */ +DRESULT disk_ioctl(BYTE drv, BYTE ctrl, void *buff) +{ + DRESULT res = RES_PARERR; + + switch (ctrl) { + case GET_BLOCK_SIZE: + *(DWORD *)buff = 1; + res = RES_OK; + break; + + /* Get the number of sectors on the disk (DWORD) */ + case GET_SECTOR_COUNT: + { + uint32_t ul_last_sector_num; + + /* Check valid address */ + mem_read_capacity(drv, &ul_last_sector_num); + + *(DWORD *)buff = ul_last_sector_num + 1; + + res = RES_OK; + } + break; + + /* Get sectors on the disk (WORD) */ + case GET_SECTOR_SIZE: + { + uint8_t uc_sector_size = mem_sector_size(drv); + + if ((uc_sector_size != SECTOR_SIZE_512) && + (uc_sector_size != SECTOR_SIZE_1024) && + (uc_sector_size != SECTOR_SIZE_2048) && + (uc_sector_size != SECTOR_SIZE_4096)) { + /* The sector size is not supported by the FatFS */ + return RES_ERROR; + } + + *(U8 *)buff = uc_sector_size * SECTOR_SIZE_DEFAULT; + + res = RES_OK; + } + break; + + /* Make sure that data has been written */ + case CTRL_SYNC: + if (mem_test_unit_ready(drv) == CTRL_GOOD) { + res = RES_OK; + } else { + res = RES_NOTRDY; + } + break; + + default: + res = RES_PARERR; + } + + return res; +} + +//@} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-port-r0.09/sam/fattime_rtc.c b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-port-r0.09/sam/fattime_rtc.c new file mode 100644 index 000000000..d0b8a6f41 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-port-r0.09/sam/fattime_rtc.c @@ -0,0 +1,84 @@ +/** + * \file + * + * \brief Implementation of low level disk I/O module skeleton for FatFS. + * + * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include "compiler.h" +#include "rtc.h" +#include "globals.h" + +uint32_t get_fattime(void); +/** + * \brief Current time returned is packed into a DWORD value. + * + * The bit field is as follows: + * + * bit31:25 Year from 1980 (0..127) + * + * bit24:21 Month (1..12) + * + * bit20:16 Day in month(1..31) + * + * bit15:11 Hour (0..23) + * + * bit10:5 Minute (0..59) + * + * bit4:0 Second (0..29) + * + * \return Current time. + */ +uint32_t get_fattime(void) +{ + uint32_t ul_time; + uint32_t ul_hour, ul_minute, ul_second; + uint32_t ul_year, ul_month, ul_day, ul_week; + +#if USE_RTC_DATE_TIME + /* Retrieve date and time */ + rtc_get_time(RTC, &ul_hour, &ul_minute, &ul_second); + rtc_get_date(RTC, &ul_year, &ul_month, &ul_day, &ul_week); +#else + ul_year = g_gps_date_time.year; + ul_month = g_gps_date_time.month; + ul_day = g_gps_date_time.day; + ul_hour = g_gps_date_time.hour; + ul_minute = g_gps_date_time.minute; + ul_second = g_gps_date_time.second; +#endif + ul_time = ((ul_year - 1980) << 25) + | (ul_month << 21) + | (ul_day << 16) + | (ul_hour << 11) + | (ul_minute << 5) + | ((ul_second >> 1) << 0); + + return ul_time; +} + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/00index_e.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/00index_e.html new file mode 100644 index 000000000..f3b9373a3 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/00index_e.html @@ -0,0 +1,114 @@ + + + + + + + + + + +ELM - FatFs Generic FAT File System Module + + + +

FatFs Generic FAT File System Module

+
+ +
+layer +

FatFs is a generic FAT file system module for small embedded systems. The FatFs is written in compliance with ANSI C and completely separated from the disk I/O layer. Therefore it is independent of hardware architecture. It can be incorporated into low cost microcontrollers, such as AVR, 8051, PIC, ARM, Z80, 68k and etc..., without any change. Petit FatFs module is also available here.

+ +

Features

+
    +
  • Windows compatible FAT file system.
  • +
  • Platform independent. Easy to port.
  • +
  • Very small footprint for code and work area.
  • +
  • Various configuration options: +
      +
    • Multiple volumes (physical drives and partitions).
    • +
    • Multiple ANSI/OEM code pages including DBCS.
    • +
    • Long file name support in ANSI/OEM or Unicode.
    • +
    • RTOS support.
    • +
    • Multiple sector size support.
    • +
    • Read-only, minimized API, I/O buffer and etc...
    • +
    +
  • +
+
+ + +
+

Application Interface

+

FatFs module provides following functions to the applications. In other words, this list describes what FatFs can do to access the FAT volumes.

+ +
+ + +
+

Disk I/O Interface

+

Since the FatFs module is completely separated from disk I/O layer, it requires following functions at least to access the physical media. When O/S related feature is enabled, it will require process/memory functions in addition. However the low level disk I/O module is not a part of FatFs module so that it must be provided by user. The sample drivers are also available in the resources.

+ +
+ + +
+

Resources

+

The FatFs module is a free software opened for education, research and development. You can use, modify and/or redistribute it for personal projects or commercial products without any restriction under your responsibility. For further information, refer to the application note.

+ +
+ + +
+

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/00index_j.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/00index_j.html new file mode 100644 index 000000000..bf8ffbd98 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/00index_j.html @@ -0,0 +1,113 @@ + + + + + + + + + + +ELM - FatFs ėpFATt@CVXeEW[ + + + +

FatFs ėpFATt@CVXeEW[

+
+ +
+layer +

FatFs͏K͂ȑgݍ݃VXe̔ėpFATt@CVXeEW[łBANSI CŃn[hEFAEA[LeN`ɂ͈ˑȂ̂ŁAKvȃ[NEGAmۂł΁A8051, PIC, AVR, SH, Z80, 68k, H8, ARMȂLjȃ}CRłgp”\łBFatFsVNՂFatFs܂B

+

FatFsW[̓

+
    +
  • Windows݊ FATt@CEVXe
  • +
  • vbgtH[ˑ
  • +
  • RpNgȃR[hRAMgp
  • +
  • ̍\IvV: +
      +
    • ̃{[(hCuE)
    • +
    • DBCS܂ޕANSI/OEMR[hEy[W
    • +
    • t@C(LFN) (Unicode APII)
    • +
    • }`^XN֘A
    • +
    • }`EZN^ETCY
    • +
    • [hEI[\AꕔAPI̍폜Aobt@\Ȃc
    • +
    +
  • +
+
+ + +
+

ʃCEC^[tF[X

+

FatFsW[́Ãt@C֐(API)񋟂܂B‚܂ÃXgFatFsɂł邱ƂVvɎĂ܂B

+ +
+ + +
+

ʃCEC^[tF[X

+

FatFsW[́AhCuւ̃ANZX̂߁AʃCɏȂƂ̃C^[tF[Xv܂BgpL^fBAɑΉfBXNI/OW[́A[UɂėpӂKv܂BOS֘A@\LɂƂ́AăvZXE֘A֐KvɂȂ܂BɃhCo܂ރTvEvWFNgB

+ +
+ + +
+

+

FatFsW[̓t[E\tgEFAƂċEEJpɌJĂ܂Bǂ̂悤ȗpړIilp珤p܂ŁjłgpEρEzzɂ‚Ĉ؂̐͂܂񂪁ASėp҂̐ӔC̉ł̗pƂ܂Bڂ̓AvP[VEm[gQƂĂB

+ +
+ + +
+

߂

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/css_e.css b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/css_e.css new file mode 100644 index 000000000..674d4e52a --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/css_e.css @@ -0,0 +1,59 @@ +* {margin: 0; padding: 0; border-width: 0;} +body {margin: 8px; background-color: #e0ffff; font-color: black; font-family: serif; line-height: 133%; max-width: 1024px;} +a:link {color: blue;} +a:visited {color: darkmagenta;} +a:hover {background-color: #a0ffff;} +a:active {color: darkmagenta; position: relative; top: 1px; left: 1px;} +abbr {border-width: 1px;} + +p {margin: 0 0 0.3em 1em;} +em {font-style: normal; font-weight: bold; margin: 0 0.1em;} +pre em {font-style: italic; font-weight: normal;} +strong {} +pre {border: 1px dashed gray; margin: 0.5em 1em; padding: 0.5em; line-height: 1.2em; font-family: monospace; background-color: white;} +pre span.c {color: green;} +pre span.k {color: blue;} +tt {margin: 0 0.2em; font-family: monospace; } +ol {margin: 0 2.5em;} +ul {margin: 0 2em;} +dl {margin: 0 1em;} +dt {font-family: monospace;} +dl.par dt {margin: 0.5em 0 0 0 ; font-style: italic; } +dl.ret dt {margin: 0.5em 0 0 0 ; font-weight: bold;} +dd {margin: 0 2em;} +hr {border-width: 1px; margin: 1em;} +div.abst {font-family: sans-serif;} +div.para {clear: both; font-family: serif;} +div.ret a {font-family: monospace; } +.equ {text-indent: 0; margin: 1em 2em 1em;} +.indent {margin-left: 2em;} +.rset {float: right; margin: 0 0 0.5em 0.5em;} +.lset {float: left; margin: 0 0.5em 0.5em 0.5em;} +ul.flat li {list-style-type: none; margin: 0;} +a.imglnk img {border: 1px solid;} +.iequ {white-space: nowrap; font-weight: bold;} +.clr {clear: both;} +.it {font-style: italic;} +.mfd {font-size: 0.7em; padding: 0 1px; border: 1px solid; white-space : nowrap} + +h1 {line-height: 1em; font-size: 2em; font-family: sans-serif; padding: 0.3em 0 0.3em;} +p.hdd {float: right; text-align: right; margin-top: 0.5em;} +hr.hds {clear: both; margin-bottom: 1em;} + +h2 {font-size: 1.6em; font-family: sans-serif; background-color: #d8d8FF; padding: 0.2em 0.5em; margin: 0 0 0.5em;} +h3 {font-size: 1.5em; font-family: sans-serif; margin: 1.5em 0 0.5em;} +h4 {font-size: 1.2em; font-family: sans-serif; margin: 1em 0 0.2em;} +h5 {font-size: 1em; font-family: sans-serif; margin: 0.5em 0 0em;} +small {font-size: 80%;} +.indent {margin-left: 2em;} + +/* Tables */ +table {margin: 0.5em 1em; border-collapse: collapse; border: 2px solid black; } +th {background-color: white; border-style: solid; border-width: 1px 1px 2px; border-color: black; padding: 0 3px; vertical-align: top; white-space: nowrap;} +td {background-color: white; border: 1px solid black; padding: 0 3px; vertical-align: top; line-height: 1.3em;} +table.lst td:first-child {font-family: monospace;} +table.lst2 td {font-family: monospace;} +table caption {font-family: sans-serif; font-weight: bold;} +tr.lst3 td { border-width: 2px 1px 1px; } + +p.foot {clear: both; text-indent: 0; margin: 1em 0.5em 1em;} diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/css_j.css b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/css_j.css new file mode 100644 index 000000000..93f56a0c1 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/css_j.css @@ -0,0 +1,62 @@ +@charset "Shift_JIS"; +/* Common style sheet for Tech Notes */ + +* {margin: 0; padding: 0; border-width: 0;} +body {margin: 8px; background-color: #e0ffff; font-color: black; font-family:"lr o", serif; line-height: 150%; letter-spacing: 1px; max-width: 1024px;} +a:link {color: blue;} +a:visited {color: darkmagenta;} +a:hover {background-color: #a0ffff;} +a:active {color: darkmagenta; position: relative; top: 1px; left: 1px;} +abbr {border-width: 1px;} + +p {text-indent: 1em; margin: 0 0 0.3em 0.5em;} +em {font-style: normal; font-weight: bold; margin: 0 0.1em;} +pre em {font-style: italic; font-weight: normal;} +strong {} +pre {border: 1px dashed gray; margin: 0.5em 1em; padding: 0.5em; line-height: 1.2em; letter-spacing: 0; font-family: monospace; background-color: white;} +pre span.c {color: green;} +pre span.k {color: blue;} +tt {margin: 0 0.2em; letter-spacing: 0; font-family: monospace; } +ol {margin: 0 2.5em;} +ul {margin: 0 2em;} +dl {margin: 0 1em;} +dt {font-family: monospace;} +dl.par dt {margin: 0.5em 0 0 0 ; font-style: italic; letter-spacing: 0;} +dl.ret dt {margin: 0.5em 0 0 0 ; font-family: monospace; letter-spacing: 0; font-weight: bold;} +dd {margin: 0 2em;} +hr {border-width: 1px; margin: 1em;} +div.abst {font-family: "lr oSVbN",sans-serif;} +div.para {clear: both; font-family: "lr o",serif;} +div.ret a {font-family: monospace; } +.equ {text-indent: 0; margin: 1em 2em 1em;} +.indent {margin-left: 2em;} +.rset {float: right; margin: 0 0 0.5em 0.5em;} +.lset {float: left; margin: 0 0.5em 0.5em 0.5em;} +ul.flat li {list-style-type: none; margin: 0;} +a.imglnk img {border: 1px solid;} +.iequ {white-space: nowrap; font-weight: bold;} +.clr {clear: both;} +.it {font-style: italic;} +.mfd {font-size: 0.7em; padding: 0 1px; border: 1px solid; white-space : nowrap} + +h1 {line-height: 1em; font-size: 2em; font-family: sans-serif; padding: 0.3em 0 0.3em;} +p.hdd {float: right; text-align: right; margin-top: 0.5em;} +hr.hds {clear: both; margin-bottom: 1em;} + +h2 {font-size: 1.6em; font-family: "lr oSVbN",sans-serif; background-color: #d8d8FF; padding: 0.2em 0.5em; margin: 0 0 0.5em;} +h3 {font-size: 1.5em; font-family: "lr oSVbN",sans-serif; margin: 1.5em 0 0.5em;} +h4 {font-size: 1.2em; font-family: "lr oSVbN",sans-serif; margin: 1em 0 0.2em;} +h5 {font-size: 1em; font-family: "lr oSVbN",sans-serif; margin: 0.5em 0 0em;} +small {font-size: 80%;} +.indent {margin-left: 2em;} + +/* Tables */ +table {margin: 0.5em 1em; border-collapse: collapse; border: 2px solid black; letter-spacing: 0;} +th {background-color: white; border-style: solid; border-width: 1px 1px 2px; border-color: black; padding: 0 3px; vertical-align: top;} +td {background-color: white; border: 1px solid black; padding: 0 3px; vertical-align: top; line-height: 1.3em;} +table.lst td:first-child {font-family: monospace; white-space: nowrap;} +table.lst2 td {font-family: monospace; white-space: nowrap;} +table caption {font-family: sans-serif; font-weight: bold;} +tr.lst3 td { border-width: 2px 1px 1px; } + +p.foot {clear: both; text-indent: 0; margin: 1em 0.5em 1em;} diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/appnote.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/appnote.html new file mode 100644 index 000000000..41140c479 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/appnote.html @@ -0,0 +1,250 @@ + + + + + + + + +FatFs Module Application Note + + + +

FatFs Module Application Note

+
    +
  1. How to Port
  2. +
  3. Limits
  4. +
  5. Memory Usage
  6. +
  7. Module Size Reduction
  8. +
  9. Long File Name
  10. +
  11. Unicode API
  12. +
  13. Re-entrancy
  14. +
  15. Duplicated File Access
  16. +
  17. Performance Effective File Access
  18. +
  19. Considerations on Flash Memory Media
  20. +
  21. Critical Section
  22. +
  23. About FatFs License
  24. +
+
+ +
+

How to Port

+ +

Basic considerations

+

The FatFs module is assuming following conditions on portability.

+
    +
  • ANSI C
    +The FatFs module is a middleware which is written in ANSI C (C89). There is no platform dependence, so long as the compiler is in compliance with ANSI C.
  • +
  • Size of integer types
    +The FatFs module assumes that size of char/short/long are 8/16/32 bit and int is 16 or 32 bit. These correspondence are defined in integer.h. This will not be a problem on most compilers. When any conflict with existing definitions is occured, you must resolve it with care.
  • +
+ +

Which function is required?

+

You need to provide only low level disk I/O functions that required by FatFs module and nothing else. If a working disk module for the target is already existing, you need to write only glue functions to attach it to the FatFs module. If not, you need to port any other disk module or write it from scratch. All defined functions are not that always required. For example, disk write function is not required in read-only configuration. Following table shows which function is required depends on configuration options.

+ + + + + + + + + + +
FunctionRequired when:Note
disk_initialize
disk_status
disk_read
AlwaysDisk I/O functions.
Samples available in ffsample.zip.
There are many implementations on the web.
disk_write
get_fattime
disk_ioctl (CTRL_SYNC)
_FS_READONLY == 0
disk_ioctl (GET_SECTOR_COUNT)
disk_ioctl (GET_BLOCK_SIZE)
_USE_MKFS == 1
disk_ioctl (GET_SECTOR_SIZE)_MAX_SS > 512
disk_ioctl (CTRL_ERASE_SECTOR)_USE_ERASE == 1
ff_convert
ff_wtoupper
_USE_LFN >= 1Unicode support functions.
Available in option/cc*.c.
ff_cre_syncobj
ff_del_syncobj
ff_req_grant
ff_rel_grant
_FS_REENTRANT == 1O/S dependent functions.
Samples available in option/syscall.c.
ff_mem_alloc
ff_mem_free
_USE_LFN == 3
+
+ +
+

Limits

+
    +
  • FAT sub-types: FAT12, FAT16 and FAT32.
  • +
  • Number of open files: Unlimited, depends on available memory.
  • +
  • Number of volumes: Upto 10.
  • +
  • File size: Depends on FAT specs. (upto 4G-1 bytes)
  • +
  • Volume size: Depends on FAT specs. (upto 2T bytes on 512 bytes/sector)
  • +
  • Cluster size: Depends on FAT specs. (upto 64K bytes on 512 bytes/sector)
  • +
  • Sector size: Depends on FAT specs. (upto 4K bytes)
  • +
+
+ +
+

Memory Usage (R0.09)

+ + + + + + + + + + + +
ARM7
32bit
ARM7
Thumb
Cortex-M3
Thumb-2
AVRH8/300HPIC24RL78V850ESSH-2ARX62NIA-32
CompilerGCCGCCGCCGCCCH38C30CC78K0RCA850SHCRXCVC6
_WORD_ACCESS00010001011
text (Full, R/W)1045972016623126461068611466129677732875257477545
text (Min, R/W)65034745429783066986744087454938557637464923
text (Full, R/O)45353181286959604876528660603554380426593450
text (Min, R/O)33032493217143663770398446042684294020252664
bssD*4 + 2D*4 + 2D*4 + 2D*2 + 2D*4 + 2D*2 + 2D*2 + 2D*4 + 2D*4 + 2D*4 + 2D*4 + 2
Work area
(_FS_TINY == 0)
V*560 +
F*550
V*560 +
F*550
V*560 +
F*550
V*560 +
F*544
V*560 +
F*550
V*560 +
F*544
V*560 +
F*544
V*560 +
F*544
V*560 +
F*550
V*560 +
F*550
V*560 +
F*550
Work area
(_FS_TINY == 1)
V*560 +
F*36
V*560 +
F*36
V*560 +
F*36
V*560 +
F*32
V*560 +
F*36
V*560 +
F*32
V*560 +
F*32
V*560 +
F*36
V*560 +
F*36
V*560 +
F*36
V*560 +
F*36
+

These are the memory usage on some target systems with following condition. The memory sizes are in unit of byte, V means number of mounted volumes and F means number of open files. All samples are optimezed in code size.

+
+_FS_READONLY     0 (R/W), 1 (R/O)
+_FS_MINIMIZE     0 (Full function), 3 (Minimized function)
+_USE_STRFUNC     0 (Disable string functions)
+_USE_MKFS        0 (Disable f_mkfs function)
+_USE_FORWARD     0 (Disable f_forward function)
+_USE_FASTSEEK    0 (Disable fast seek feature)
+_CODE_PAGE       932 (Japanese Shift-JIS)
+_USE_LFN         0 (Disable LFN)
+_MAX_SS          512 (Fixed sector size)
+_FS_RPATH        0 (Disable relative path)
+_VOLUMES         D (Number of logical drives to be used)
+_MULTI_PARTITION 0 (Single partition per drive)
+_FS_REENTRANT    0 (Disable reentrancy)
+_FS_SHARE        0 (Disable shareing control)
+
+
+ +
+

Module Size Reduction

+

Follwing table shows which API function is removed by configuration options for the module size reduction.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Function_FS_MINIMIZE_FS_READONLY_USE_STRFUNC_FS_RPATH_USE_MKFS_USE_FORWARD_MULTI_PARTITION
0123010  1/201201010/12
f_mount
f_open
f_close
f_read
f_writex
f_syncx
f_lseekx
f_opendirxx
f_readdirxx
f_statxxx
f_getfreexxxx
f_truncatexxxx
f_unlinkxxxx
f_mkdirxxxx
f_chmodxxxx
f_utimexxxx
f_renamexxxx
f_chdirx
f_chdrivex
f_getcwdxx
f_mkfsxx
f_fdiskxxx
f_forwardx
f_putcxx
f_putsxx
f_printfxx
f_getsx
+
+ +
+

Long File Name

+

The FatFs module has started to support long file name (LFN) at revision 0.07. The two different file names, SFN and LFN, of a file is transparent in the file functions except for f_readdir function. To enable LFN feature, set _USE_LFN to 1, 2 or 3, and add a Unicode code conversion function ff_convert() and ff_wtoupper() to the project. The LFN feature requiers a certain working buffer in addition. The buffer size can be configured by _MAX_LFN corresponding to the available memory size. The size of long file name will reach up to 255 characters so that the _MAX_LFN should be set to 255 for full featured LFN operation. If the size of working buffer is insufficient for the given file name, the file function fails with FR_INVALID_NAME. When enable the LFN feature with re-entrant feature, _USE_LFN must be set to 2 or 3. In this case, the file function allocates the working buffer on the stack or heap. The working buffer occupies (_MAX_LFN + 1) * 2 bytes.

+ + + + + + + + +
LFN cfg on ARM7
Code pageProgram size
SBCS+3.7K
932(Shift-JIS)+62K
936(GBK)+177K
949(Korean)+139K
950(Big5)+111K
+

When the LFN feature is enabled, the module size will be increased depends on the selected code page. Right table shows how many bytes increased when LFN feature is enabled with some code pages. We are the East-Asians have tens of thousands of characters. Unfortunately, it requires a huge OEM-Unicode bidirectional conversion table and the module size will be drastically increased that shown in the table. As the result, the FatFs with LFN feature with DBCS will not able to be implemented to most 8-bit microcontrollers. This is the reason why I had not been interested in implementing the LFN feature for a long time :-)

+

Note that the LFN feature on the FAT file system is a patent of Microsoft Corporation. This is not the case on FAT32 but most FAT32 drivers include the LFN feature. FatFs can swich the LFN feature by configuration option. When enable LFN feature on the commercial products, a license from Microsoft may be required depends on the final destination.

+
+ +
+

Unicode API

+

FatFs supports ANSI/OEM code set on the API in default but FatFs can also switch the code set to Unicode. For more information, refer to the description in the file name.

+
+ +
+

Re-entrancy

+

The file operations to the different volume is always re-entrant and can work simultaneously. The file operations to the same volume is not re-entrant but it can also be configured to thread-safe with _FS_REENTRANT option. In this case, also the OS dependent synchronization object control functions, ff_cre_syncobj, ff_del_syncobj, ff_req_grant and ff_rel_grant must be added to the project.

+

When a file function is called while the volume is in use by any other task, the file function is suspended until that task leaves file function. If wait time exceeded a period defined by _TIMEOUT, the file function will abort with FR_TIMEOUT. The timeout feature might not be supported on some RTOS.

+

There is an exception on f_mount and f_mkfs function. These functions are not re-entrant to the same volume. When use these functions, all other task must close the corresponding file on the volume and avoid to access the volume.

+

Note that this section describes on the re-entrancy of the FatFs module itself but also the low level disk I/O layer must be re-entrant.

+
+ +
+

Duplicated File Access

+

FatFs module does not support the shareing controls of duplicated file access in default. It is permitted when open method to a file is only read mode. The duplicated open in write mode to a file is always prohibited and open file must not be renamed, deleted, or the FAT structure on the volume can be collapted.

+

The file shareing control can also be available when _FS_SHARE is set to 1 or grater. The value specifies the number of files to manage simultaneously. In this case, if any open, rename or remove that violating the file shareing rule that described above is attempted, the file function will fail with FR_LOCKED. If number of open files gets larger than _FS_SHARE, the f_open function will fail with FR_TOO_MANY_OPEN_FILES.

+
+ +
+

Performance Effective File Access

+

For good performance on reading/writing files on the small embedded system, application programmer should consider what process is done in the FatFs module. The file data on the disk is transferred in following sequence by f_read function.

+

Figure 1. Sector miss-aligned read (short)
+ +

+

Figure 2. Sector miss-aligned read (long)
+ +

+

Figure 3. Sector aligned read
+ +

+

The file I/O buffer means a sector buffer to read/write a partial data on the sector. The sector buffer is either file private sector buffer on each file object or shared sector buffer on the file system object. The buffer configuration option _FS_TINY determins which sector buffer is used for the file data transfer. When tiny buffer (1) is selected, data memory consumption is reduced 512 bytes each file object. In this case, FatFs module uses only a sector buffer on the file system object for file data transfer and FAT/directory access. The disadvantage of the tiny buffer configuration is: the FAT data cached in the sector buffer will be lost by file data transfer and it must be reloaded at every cluster boundary. However it will be suitable for most application from view point of the decent performance and low memory comsumption.

+

Figure 1 shows that partial sector data is transferred via the file I/O buffer. On long data transfer shown in Figure 2, middle of transfer data that covers one or more sector is transferred to application buffer directly. Figure 3 shows that the case of entier transfer data is aligned to the sector boundary. In this case, file I/O buffer is not used. On the direct transfer, the maximum extent of sectors are read with disk_read function at a time but the multi sector transfer never across the cluster boundary even if it is contiguous.

+

Therefore taking effort to sector aligned read/write accesss avoids buffered data transfer and the read/write performance will be improved. Besides the effect, cached FAT data will not be flushed by file data transfer on the tiny configuration so that it can achieve same performance as non-tiny configuration with small memory footprint.

+
+ +
+

Considerations on Flash Memory Media

+

To maximize the write performance of flash memory media, such as SDC and CFC, it must be controlled in consideration of its characteristitcs.

+

Using Mutiple-Sector Write

+
+Figure 6. Comparison between Multiple/Single Sector Write
+fig.6 +
+

The write throughput of the flash memory media becomes the worst at single sector write and it increases proportional to the number of sectors per a write transaction. This effect more appers at more fast bus clock and its ratio often becomes grater than ten. The number of write transaction also affects the life time of the media. Therefore the application program should write the data in large block as possible. The ideal block size is cluster size or power of 2 bytes and the byte offset should be aligned to the block. Of course all layers between the application and the media must support multiple sector write feature, however most of open-source disk drivers lack it. Do not split a multiple sector write request into single sector writes or the write throughput gets poor. Note that FatFs module and its sample disk drivers supprt multiple sector read/write.

+

Forcing Memory Erase

+

When remove a file via f_remove function, the data clusters occupied by the file are marked 'free' on the FAT. But the data sectors containing the file data are not that applied any process so that the file data left occupies a part of the media as live blocks. If the file data is forced erased on removing the file, the number of free blocks on the media will be increased. This may skip internal block erase operation to the data block on next write. As the result the write performance might be improved. To enable this feature, set _USE_ERASE to 1. Note that this is a feature with expectation of internal process of the flash memory media. It may not always effective and f_remove function will take a time on removing a large file.

+
+ +
+

Critical Section

+

If a write operation to the FAT file system is interrupted due to any accidental failure, such as sudden blackout, incorrect disk removal and unrecoverable disk error, the FAT structure can be collapted. Following images shows the critical section on the FatFs application.

+
+Figure 4. Long critical section
+fig.4 +
+
+Figure 5. Minimized critical section
+fig.5 +
+
+

An interruption in the red section can cause a cross link; as a result, the object being changed may be lost. There is one or more possibility listed below when an interruption in the yellow section is occured.

+
    +
  • File data being rewrited is collapted.
  • +
  • A file being appended returns initial state.
  • +
  • A file created as new is gone.
  • +
  • A file created as new or in overwritten remains with no content.
  • +
  • Efficiency of disk use gets worse due to lost clusters.
  • +
+

Each case does not affect the files that not in write mode open. To minimize risk of data loss, the critical section can be minimized like shown in Figure 5 by minimizing the time that file is opened in write mode or using f_sync function properly.

+
+ +
+

About FatFs License

+

This is a copy of the FatFs license document that included in the source codes.

+
/*----------------------------------------------------------------------------/
+/  FatFs - FAT file system module  R0.09                     (C)ChaN, 2011
+/-----------------------------------------------------------------------------/
+/ FatFs module is a generic FAT file system module for small embedded systems.
+/ This is a free software that opened for education, research and commercial
+/ developments under license policy of following trems.
+/
+/  Copyright (C) 2011, ChaN, all right reserved.
+/
+/ * The FatFs module is a free software and there is NO WARRANTY.
+/ * No restriction on use. You can use, modify and redistribute it for
+/   personal, non-profit or commercial products UNDER YOUR RESPONSIBILITY.
+/ * Redistributions of source code must retain the above copyright notice.
+/
+/-----------------------------------------------------------------------------/
+

Therefore FatFs license is one of the BSD-style license but there is a big difference. Because FatFs is for embedded projects, the conditions for redistributions in binary form, such as embedded code, hex file and binary library, are not specified to increase its usability. The documentation of the distributions need not include about FatFs and its license document, and it may also. Of course FatFs is compatible with the projects under GNU GPL. When redistribute it with any modification, the license can also be changed to GNU GPL or BSD-style license.

+
+ +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/chdir.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/chdir.html new file mode 100644 index 000000000..f94199ecf --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/chdir.html @@ -0,0 +1,81 @@ + + + + + + + + +FatFs - f_chdir + + + + +
+

f_chdir

+

The f_chdir function changes the current directory of a drive.

+
+FRESULT f_chdir (
+  const TCHAR* Path /* Pointer to the path name */
+);
+
+
+ +
+

Parameters

+
+
Path
+
Pointer to the null-terminated string that specifies a directory to go.
+
+
+ + + + + +
+

Description

+

The f_chdir function changes the current directory of the logical drive. The current directory of a drive is initialized to the root directory when the drive is auto-mounted. Note that the current directory is retained in the each file system object so that it also affects other tasks that using the drive.

+
+ + +
+

QuickInfo

+

Available when _FS_RPATH >= 1.

+
+ + +
+

Example

+
+    /* Change current direcoty of the current drive (dir1 under root dir) */
+    f_chdir("/dir1");
+
+    /* Change current direcoty of drive 2 (parent dir) */
+    f_chdir("2:..");
+
+
+ +
+

See Also

+

f_chdrive, f_getcwd

+
+ +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/chdrive.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/chdrive.html new file mode 100644 index 000000000..c5d81b2b9 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/chdrive.html @@ -0,0 +1,60 @@ + + + + + + + + +FatFs - f_chdrive + + + + +
+

f_chdrive

+

The f_chdrive function changes the current drive.

+
+FRESULT f_chdrive (
+  BYTE Drive /* Logical drive number */
+);
+
+
+ +
+

Parameters

+
+
Drive
+
Specifies the logical drive number to be set as the current drive.
+
+
+ + +
+

Return Values

+

+FR_OK, +FR_INVALID_DRIVE +

+
+ + +
+

Description

+

The f_chdrive function changes the current drive. The initial value of the current drive number is 0. Note that the current drive is retained in a static variable so that it also affects other tasks that using the file functions.

+
+ +
+

QuickInfo

+

Available when _FS_RPATH >= 1.

+
+ + +
+

See Also

+

f_chdir, f_getcwd

+
+ +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/chmod.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/chmod.html new file mode 100644 index 000000000..8c0504499 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/chmod.html @@ -0,0 +1,89 @@ + + + + + + + + +FatFs - f_chmod + + + + +
+

f_chmod

+

The f_chmod function changes the attribute of a file or directory.

+
+FRESULT f_chmod (
+  const TCHAR* FileName, /* Pointer to the file or directory */
+  BYTE Attribute,        /* Attribute flags */
+  BYTE AttributeMask     /* Attribute masks */
+);
+
+
+ +
+

Parameters

+
+
FileName
+
Pointer to the null-terminated string that specifies a file or directory to be changed
+
Attribute
+
Attribute flags to be set in one or more combination of the following flags. The specified flags are set and others are cleard.
+ + + + + + +
AttributeDescription
AM_RDORead only
AM_ARCArchive
AM_SYSSystem
AM_HIDHidden
+
+
AttributeMask
+
Attribute mask that specifies which attribute is changed. The specified aattributes are set or cleard.
+
+
+ + + + + +
+

Description

+

The f_chmod function changes the attribute of a file or directory.

+
+ + +
+

QuickInfo

+

Available when _FS_READONLY == 0 and _FS_MINIMIZE == 0.

+
+ + +
+

Example

+
+    /* Set read-only flag, clear archive flag and others are retained. */
+    f_chmod("file.txt", AR_RDO, AR_RDO | AR_ARC);
+
+
+ +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/close.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/close.html new file mode 100644 index 000000000..49c62b547 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/close.html @@ -0,0 +1,65 @@ + + + + + + + + +FatFs - f_close + + + + +
+

f_close

+

The f_close function closes an open file.

+
+FRESULT f_close (
+  FIL* FileObject     /* Pointer to the file object structure */
+);
+
+
+ +
+

Parameter

+
+
FileObject
+
Pointer to the open file object structure to be closed.
+
+
+ + + + + +
+

Description

+

The f_close function closes an open file object. If any data has been written to the file, the cached information of the file is written back to the disk. After the function succeeded, the file object is no longer valid and it can be discarded.

+
+ + +
+

QuickInfo

+

Always available.

+
+ + +
+

See Also

+

f_open, f_read, f_write, f_sync, FIL, FATFS

+
+ +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/dinit.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/dinit.html new file mode 100644 index 000000000..f7ac0bd38 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/dinit.html @@ -0,0 +1,46 @@ + + + + + + + + +FatFs - disk_initialize + + + + +
+

disk_initialize

+

The disk_initialize function initializes the disk drive.

+
+DSTATUS disk_initialize (
+  BYTE Drive           /* Physical drive number */
+);
+
+
+ +
+

Parameter

+
+
Drive
+
Specifies the physical drive number to initialize.
+
+
+ + +
+

Return Values

+

This function returns a disk status as the result. For details of the disk status, refer to the disk_status function.

+
+ +
+

Description

+

The disk_initialize function initializes a physical drive and put it ready to read/write. When the function succeeded, STA_NOINIT flag in the return value is cleard.

+

Application program MUST NOT call this function, or FAT structure on the volume can be corrapted. To re-initialize the file system, use f_mount function.This function is called on volume mount process in the FatFs module to manage the media change.

+
+ +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/dioctl.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/dioctl.html new file mode 100644 index 000000000..436516688 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/dioctl.html @@ -0,0 +1,69 @@ + + + + + + + + +FatFs - disk_ioctl + + + + +
+

disk_ioctl

+

The disk_ioctl function cntrols device specified features and miscellaneous functions other than disk read/write.

+
+DRESULT disk_ioctl (
+  BYTE Drive,      /* Drive number */
+  BYTE Command,    /* Control command code */
+  void* Buffer     /* Parameter and data buffer */
+);
+
+
+ +
+

Parameters

+
+
Drive
+
Specifies the drive number (0-9).
+
Command
+
Specifies the command code.
+
Buffer
+
Pointer to the parameter buffer depends on the command code. When it is not used, specify a NULL pointer.
+
+
+ + +
+

Return Value

+
+
RES_OK (0)
+
The function succeeded.
+
RES_ERROR
+
Any error occured.
+
RES_PARERR
+
Invalid command code.
+
RES_NOTRDY
+
The disk drive has not been initialized.
+
+
+ + +
+

Description

+

The FatFs module uses only device independent commands described below. Any device dependent function is not used.

+ + + + + + + +
CommandDescription
CTRL_SYNCMake sure that the disk drive has finished pending write process. When the disk I/O module has a write back cache, flush the dirty sector immediately. This command is not used in read-only configuration.
GET_SECTOR_SIZEReturns sector size of the drive into the WORD variable pointed by Buffer. This command is not used in fixed sector size configuration, _MAX_SS is 512.
GET_SECTOR_COUNTReturns number of available sectors on the drive into the DWORD variable pointed by Buffer. This command is used by only f_mkfs function to determine the volume size to be created.
GET_BLOCK_SIZEReturns erase block size of the flash memory in unit of sector into the DWORD variable pointed by Buffer. The allowable value is 1 to 32768 in power of 2. Return 1 if the erase block size is unknown or disk devices. This command is used by only f_mkfs function and it attempts to align data area to the erase block boundary.
CTRL_ERASE_SECTORErases a part of the flash memory specified by a DWORD array {<start sector>, <end sector>} pointed by Buffer. When this feature is not supported or not a flash memory media, this command has no effect. The FatFs does not check the result code and the file function is not affected even if the sectors are not erased well. This command is called on removing a cluster chain when _USE_ERASE is 1.
+
+ +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/dread.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/dread.html new file mode 100644 index 000000000..833a04210 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/dread.html @@ -0,0 +1,59 @@ + + + + + + + + +FatFs - disk_read + + + + +
+

disk_read

+

The disk_read function reads sector(s) from the disk drive.

+
+DRESULT disk_read (
+  BYTE Drive,          /* Physical drive number */
+  BYTE* Buffer,        /* Pointer to the read data buffer */
+  DWORD SectorNumber,  /* Start sector number */
+  BYTE SectorCount     /* Number of sectros to read */
+);
+
+
+ +
+

Parameters

+
+
Drive
+
Specifies the physical drive number.
+
Buffer
+
Pointer to the byte array to store the read data. The buffer size of number of bytes to be read, sector size * sector count, is required. Note that the specified memory address is not that always aligned to word boundary. If the hardware does not support misaligned data transfer, it must be solved in this function.
+
SectorNumber
+
Specifies the start sector number in logical block address (LBA).
+
SectorCount
+
Specifies number of sectors to read. The value can be 1 to 128. Generally, a multiple sector transfer request must not be split into single sector transactions to the device, or you may not get good read performance.
+
+
+ + +
+

Return Value

+
+
RES_OK (0)
+
The function succeeded.
+
RES_ERROR
+
Any hard error occured during the read operation and could not recover it.
+
RES_PARERR
+
Invalid parameter.
+
RES_NOTRDY
+
The disk drive has not been initialized.
+
+
+ + +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/dstat.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/dstat.html new file mode 100644 index 000000000..fa68f4ae8 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/dstat.html @@ -0,0 +1,48 @@ + + + + + + + + +FatFs - disk_status + + + + +
+

disk_status

+

The disk_status function returns the current disk status.

+
+DSTATUS disk_status (
+  BYTE Drive     /* Physical drive number */
+);
+
+
+ +
+

Parameter

+
+
Drive
+
Specifies the physical drive number to be confirmed.
+
+
+ + +
+

Return Values

+

The disk status is returned in combination of following flags. FatFs refers only STA_NOINIT and STA_PROTECTED.

+
+
STA_NOINIT
+
Indicates that the disk drive has not been initialized. This flag is set on: system reset, disk removal and disk_initialize function failed, and cleared on: disk_initialize function succeeded.
+
STA_NODISK
+
Indicates that no medium in the drive. This is always cleared on fixed disk drive.
+
STA_PROTECTED
+
Indicates that the medium is write protected. This is always cleared on the drive that does not support write protect notch. Not valid when STA_NODISK is set.
+
+
+ +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/dwrite.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/dwrite.html new file mode 100644 index 000000000..c808cff1b --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/dwrite.html @@ -0,0 +1,67 @@ + + + + + + + + +FatFs - disk_write + + + + +
+

disk_write

+

The disk_write writes sector(s) to the disk.

+
+DRESULT disk_write (
+  BYTE Drive,          /* Physical drive number */
+  const BYTE* Buffer,  /* Pointer to the write data (may be non aligned) */
+  DWORD SectorNumber,  /* Sector number to write */
+  BYTE SectorCount     /* Number of sectors to write */
+);
+
+
+ +
+

Parameters

+
+
Drive
+
Specifies the physical drive number.
+
Buffer
+
Pointer to the byte array to be written. Note that the specified memory address is not that always aligned to word boundary. If the hardware does not support misaligned data transfer, it must be solved in this function.
+
SectorNumber
+
Specifies the start sector number in logical block address (LBA).
+
SectorCount
+
Specifies the number of sectors to write. The value can be 1 to 128. Generally, a multiple sector transfer request must not be split into single sector transactions to the device, or you will never get good write performance.
+
+
+ + +
+

Return Values

+
+
RES_OK (0)
+
The function succeeded.
+
RES_ERROR
+
Any hard error occured during the write operation and could not recover it.
+
RES_WRPRT
+
The medium is write protected.
+
RES_PARERR
+
Invalid parameter.
+
RES_NOTRDY
+
The disk drive has not been initialized.
+
+
+ + +
+

Description

+

This function is not required in read only configuration.

+
+ + +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/eof.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/eof.html new file mode 100644 index 000000000..856075745 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/eof.html @@ -0,0 +1,62 @@ + + + + + + + + +FatFs - f_eof + + + + +
+

f_eof

+

The f_eof function tests for end-of-file on a file.

+
+int f_eof (
+  FIL* FileObject   /* File object */
+);
+
+
+ + +
+

Parameters

+
+
FileObject
+
Pointer to the open file object structure.
+
+
+ + +
+

Return Values

+

The f_eof function returns a non-zero value if the read/write pointer has reached end of the file; otherwise it returns a zero.

+
+ + +
+

Description

+

In this revision, the f_eof function is implemented as a macro.

+
+#define f_eof(fp) (((fp)->fptr) == ((fp)->fsize) ? 1 : 0)
+
+
+ + +
+

QuickInfo

+

Always available.

+
+ + +
+

See Also

+

f_open, f_lseek, FIL

+
+ +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/error.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/error.html new file mode 100644 index 000000000..e7d25a7fc --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/error.html @@ -0,0 +1,62 @@ + + + + + + + + +FatFs - f_error + + + + +
+

f_error

+

The f_error tests for an error on a file.

+
+int f_error (
+  FIL* FileObject   /* File object */
+);
+
+
+ + +
+

Parameters

+
+
FileObject
+
Pointer to the open file object structure.
+
+
+ + +
+

Return Values

+

Returns a non-zero value if an error has occured; otherwise it returns a zero.

+
+ + +
+

Description

+

In this revision, the f_error function is implemented as a macro.

+
+#define f_error(fp) (((fp)->flag & FA__ERROR) ? 1 : 0)
+
+
+ + +
+

QuickInfo

+

Always available.

+
+ + +
+

See Also

+

f_open, FIL

+
+ +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/fattime.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/fattime.html new file mode 100644 index 000000000..0a996c9b5 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/fattime.html @@ -0,0 +1,51 @@ + + + + + + + + +FatFs - get_fattime + + + + +
+

get_fattime

+

The get_fattime function gets current time.

+
+DWORD get_fattime (void);
+
+
+ + +
+

Return Value

+

Currnet time is returned with packed into a DWORD value. The bit field is as follows:

+
+
bit31:25
+
Year from 1980 (0..127)
+
bit24:21
+
Month (1..12)
+
bit20:16
+
Day in month(1..31)
+
bit15:11
+
Hour (0..23)
+
bit10:5
+
Minute (0..59)
+
bit4:0
+
Second / 2 (0..29)
+
+
+ + +
+

Description

+

The get_fattime function must return any valid time even if the system does not support a real time clock. If a zero is returned, the file will not have a valid time. This fucntion is not required in read only configuration.

+
+ + +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/fdisk.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/fdisk.html new file mode 100644 index 000000000..1adf94370 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/fdisk.html @@ -0,0 +1,97 @@ + + + + + + + + +FatFs - f_fdisk + + + + +
+

f_fdisk

+

The f_fdisk fucntion divides a physical drive.

+
+FRESULT f_fdisk (
+  BYTE  Drive,              /* Physical drive number */
+  const DWORD Partitions[], /* Partition size */
+  void* Work                /* Work area */
+);
+
+
+ +
+

Parameters

+
+
Drive
+
Specifies the physical drive to be divided.
+
Partitions[]
+
Partition map table. It must have four items.
+
Work
+
Pointer to the function work area. The size must be at least _MAX_SS bytes.
+
+
+ + + +
+

Description

+

The f_fdisk function creates a partition table into the MBR of the physical drive. The partitioning rule is in generic FDISK format so that it can create upto four primary partitions. Extended partition is not supported. The Partitions[] specifies how to divide the physical drive. The first item specifies the size of first primary partition and fourth item specifies the fourth primary partition. If the value is less than or equal to 100, it means percentage of the partition in the entire disk space. If it is larger than 100, it means partition size in unit of sector.

+
+ +
+

QuickInfo

+

Available when _FS_READOLNY == 0, _USE_MKFS == 1 and _MULTI_PARTITION == 2.

+
+ +
+

Example

+
+    /* Volume management table defined by user (required when _MULTI_PARTITION != 0) */
+
+    PARTITION VolToPart[] = {
+        {0, 1},    /* Logical drive 0 ==> Physical drive 0, 1st partition */
+        {0, 2},    /* Logical drive 1 ==> Physical drive 0, 2nd partition */
+        {1, 0}     /* Logical drive 2 ==> Physical drive 1, auto detection */
+    };
+
+
+    /* Initialize a brand-new disk drive mapped to physical drive 0 */
+
+    FATFS Fatfs;
+    DWORD plist[] = {50, 50, 0, 0};  /* Divide drive into two partitions */
+    BYTE work[_MAX_SS];
+
+    f_fdisk(0, plist, work);  /* Divide physical drive 0 */
+
+    f_mount(0, &Fatfs);
+    f_mkfs(0, 0, 0);          /* Create an FAT volume on the logical drive 0. 2nd argument is ignored. */
+    f_mount(0, 0);
+
+    f_mount(1, &Fatfs);
+    f_mkfs(1, 0, 0);
+    f_mount(1, 0);
+
+
+
+ +
+

See Also

+

Volume management, f_mkfs

+
+ +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/filename.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/filename.html new file mode 100644 index 000000000..a60bb1ce3 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/filename.html @@ -0,0 +1,74 @@ + + + + + + + + +FatFs - Path Names + + + +

Path Names

+ +
+

Format of the path names

+

The path name format on the FatFs module is similer to the filename specs of DOS/Windos as follows:

+

"[drive#:][/]directory/file"

+

The FatFs module supports long file name (LFN) and 8.3 format file name (SFN). The LFN can be used when LFN feature is enabled (_USE_LFN > 0). The sub directories are separated with a \ or / in the same way as DOS/Windows API. Duplicated separators are skipped and ignored. Only a difference is that the logical drive is specified in a numeral with a colon. When the drive number is omitted, it is assumed as default drive (0 or current drive).

+

Control characters (\0 to \x1F) are recognized as end of the path name. Leading/embedded spaces in the path name are valid as a part of the name on LFN configuration but they are recognized as end of the path name on non-LFN configuration. Trailing spaces and dots are ignored.

+

In default configuration (_FS_RPATH == 0), it does not have a concept of current directory like OS oriented file system. All objects on the volume are always specified in full path name that follows from the root directory. Dot directory names are not allowed. Heading separator is ignored and it can be exist or omitted. The default drive number is fixed to 0.

+

When relative path feature is enabled (_FS_RPATH == 1), specified path is followed from the root directory if a heading separator is exist. If not, it is followed from the current directory set with f_chdir function. Dot names are also allowed for the path name. The default drive is the current drive set with f_chdrive function.

+ + + + + + + + + + + + + + +
Path name_FS_RPATH == 0_FS_RPATH == 1
file.txtA file in the root directory of the drive 0A file in the current directory of the current drive
/file.txtA file in the root directory of the drive 0A file in the root directory of the current drive
The root directory of the drive 0The current directory of the current drive
/The root directory of the drive 0The root directory of the current drive
2:The root directory of the drive 2The current directory of the drive 2
2:/The root directory of the drive 2The root directory of the drive 2
2:file.txtA file in the root directory of the drive 2A file in the current directory of the drive 2
../file.txtInvalid nameA file in the parent directory
.Invalid nameThis directory
..Invalid nameParent directory of the current directory
dir1/..Invalid nameThe current directory
/..Invalid nameThe root directory (sticks the top level)
+
+ +


+
+

Unicode API

+

The path names are input/output in either ANSI/OEM code (SBCS/DBCS) or Unicode depends on the configuration options. The type of arguments that specifies the file names are defined as TCHAR which is an alias of char in default. The code set of the file name string is the ANSI/OEM code set specifid by _CODE_PAGE. When _LFN_UNICODE is set to 1 under LFN configuration, the type of the TCHAR is switched to unsigned short (UCS-2 character) to support Unicode. In this case, the LFN feature is fully supported and the Unicode specific characters, such as ✝☪✡☸☭, can also be used for the path name. It also affects data types and encoding of the string I/O functions. To define literal strings, _T(s) and _TEXT(s) macro are available to select either ANSI/OEM or Unicode automatically. The code shown below is an example to define the literal strings.

+
+ f_open(fp, "filename.txt", FA_READ);      /* ANSI/OEM only */
+ f_open(fp, L"filename.txt", FA_READ);     /* Unicode only */
+ f_open(fp, _T("filename.txt"), FA_READ);  /* Changed automatically */
+
+
+ +


+
+

Correspondence between logical and physical drives

+

The FatFs module has work areas that called file system object for each volume (logical drive). In default, each logical drive is bound to the physical drive that has same drive number. It attempts to mount a volume as SFD format and first FDISK partition. When _MULTI_PARTITION >= 1 is specified in configuration option, each individual logical drive is bound to any physical drive/partition. In this case, a volume management table must be defined by user. It is used to resolve relationship between logical drives and partitions as follows:

+
+Example: Logical drive 0-2 are assigned to three pri-partitions on the physical drive 0 (fixed disk)
+         Logical drive 3 is assigned to physical drive 1 (removable disk)
+
+PARTITION VolToPart[] = {
+    {0, 1},     /* Logical drive 0 ==> Physical drive 0, 1st partition */
+    {0, 2},     /* Logical drive 1 ==> Physical drive 0, 2nd partition */
+    {0, 3},     /* Logical drive 2 ==> Physical drive 0, 3rd partition */
+    {1, 0}      /* Logical drive 3 ==> Physical drive 1 (auto detection) */
+};
+
+

There are some considerations when use _MULTI_PARTITION configuration.

+
    +
  • Only four pri-partitions can be mounted. Extended partition is not supported.
  • +
  • The physical drive that has two or more partitions must be non-removable class.
  • +
+
+ + + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/forward.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/forward.html new file mode 100644 index 000000000..01fb0e935 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/forward.html @@ -0,0 +1,139 @@ + + + + + + + + +FatFs - f_forward + + + + +
+

f_forward

+

The f_forward function reads the file data and forward it to the data streaming device.

+
+FRESULT f_forward (
+  FIL* FileObject,                 /* File object */
+  UINT (*Func)(const BYTE*,UINT),  /* Data streaming function */
+  UINT ByteToFwd,                  /* Number of bytes to forward */
+  UINT* ByteFwd                    /* Number of bytes forwarded */
+);
+
+
+ +
+

Parameters

+
+
FileObject
+
Pointer to the open file object.
+
Func
+
Pointer to the user-defined data streaming function. For details, refer to the sample code.
+
ByteToFwd
+
Number of bytes to forward in range of UINT.
+
ByteFwd
+
Pointer to the UINT variable to return number of bytes forwarded.
+
+
+ + + + + +
+

Description

+

The f_forward function reads the data from the file and forward it to the outgoing stream without data buffer. This is suitable for small memory system because it does not require any data buffer at application module. The file pointer of the file object increases in number of bytes forwarded. In case of *ByteFwd < ByteToFwd without error, it means the requested bytes could not be transferred due to end of file or stream goes busy during data transfer.

+
+ + +
+

QuickInfo

+

Available when _USE_FORWARD == 1 and _FS_TINY == 1.

+
+ + +
+

Example (Audio playback)

+
+/*------------------------------------------------------------------------*/
+/* Sample code of data transfer function to be called back from f_forward */
+/*------------------------------------------------------------------------*/
+
+UINT out_stream (   /* Returns number of bytes sent or stream status */
+    const BYTE *p,  /* Pointer to the data block to be sent */
+    UINT btf        /* >0: Transfer call (Number of bytes to be sent). 0: Sense call */
+)
+{
+    UINT cnt = 0;
+
+
+    if (btf == 0) {     /* Sense call */
+        /* Return stream status (0: Busy, 1: Ready) */
+        /* When once it returned ready to sense call, it must accept a byte at least */
+        /* at subsequent transfer call, or f_forward will fail with FR_INT_ERR. */
+        if (FIFO_READY) cnt = 1;
+    }
+    else {              /* Transfer call */
+        do {    /* Repeat while there is any data to be sent and the stream is ready */
+            FIFO_PORT = *p++;
+            cnt++;
+        } while (cnt < btf && FIFO_READY);
+    }
+
+    return cnt;
+}
+
+
+/*------------------------------------------------------------------------*/
+/* Sample code using f_forward function                                   */
+/*------------------------------------------------------------------------*/
+
+FRESULT play_file (
+    char *fn        /* Pointer to the audio file name to be played */
+)
+{
+    FRESULT rc;
+    FIL fil;
+    UINT dmy;
+
+    /* Open the audio file in read only mode */
+    rc = f_open(&fil, fn, FA_READ);
+    if (rc) return rc;
+
+    /* Repeat until the file pointer reaches end of the file */
+    while (rc == FR_OK && fil.fptr < fil.fsize) {
+
+        /* any other processes... */
+
+        /* Fill output stream periodicaly or on-demand */
+        rc = f_forward(&fil, out_stream, 1000, &dmy);
+    }
+
+    /* Close the file and return */
+    f_close(&fil);
+    return rc;
+}
+
+
+ + +
+

See Also

+

f_open, fgets, f_write, f_close, FIL

+
+ +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/getcwd.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/getcwd.html new file mode 100644 index 000000000..eaec9b9f0 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/getcwd.html @@ -0,0 +1,70 @@ + + + + + + + + +FatFs - f_getcwd + + + + +
+

f_getcwd

+

The f_getcwd function retrieves the current directory.

+
+FRESULT f_getcwd (
+  TCHAR* Buffer,  /* Pointer to the buffer */
+  UINT BufferLen  /* The length of the buffer */
+);
+
+
+ +
+

Parameters

+
+
Buffer
+
Pointer to the buffer to receive the current directory string.
+
BufferLen
+
Size of the buffer in unit of TCHAR.
+
+
+ + + + + +
+

Description

+

The f_getcwd function retrieves the current directory of the current drive in full path string including drive number.

+
+ + +
+

QuickInfo

+

Available when _FS_RPATH == 2.

+
+ + +
+

See Also

+

f_chdrive, f_chdir

+
+ +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/getfree.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/getfree.html new file mode 100644 index 000000000..8876ec10d --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/getfree.html @@ -0,0 +1,96 @@ + + + + + + + + +FatFs - f_getfree + + + + +
+

f_getfree

+

The f_getfree function gets number of the free clusters.

+
+FRESULT f_getfree (
+  const TCHAR* Path,        /* Logical drive number */
+  DWORD* Clusters,          /* Pointer to the variable to store number of free clusters */
+  FATFS** FileSystemObject  /* Pointer to pointer to file system object */
+);
+
+
+ +
+

Parameters

+
+
Path
+
Pinter to the null-terminated string that specifies the logical drive.
+
Clusters
+
Pointer to the DWORD variable to store number of free clusters.
+
FileSystemObject
+
Pointer to pointer that to store a pointer to the corresponding file system object.
+
+
+ + + + + +
+

Descriptions

+

The f_getfree function gets number of free clusters on the drive. The member csize in the file system object is refrecting number of sectors per cluster, so that the free space in unit of sector can be calcurated with this. When FSInfo structure on FAT32 volume is not in sync, this function can return an incorrect free cluster count.

+
+ + +
+

QuickInfo

+

Available when _FS_READONLY == 0 and _FS_MINIMIZE == 0.

+
+ + +
+

Example

+
+    FATFS *fs;
+    DWORD fre_clust, fre_sect, tot_sect;
+
+
+    /* Get volume information and free clusters of drive 1 */
+    res = f_getfree("1:", &fre_clust, &fs);
+    if (res) die(res);
+
+    /* Get total sectors and free sectors */
+    tot_sect = (fs->n_fatent - 2) * fs->csize;
+    fre_sect = fre_clust * fs->csize;
+
+    /* Print free space in unit of KB (assuming 512 bytes/sector) */
+    printf("%lu KB total drive space.\n"
+           "%lu KB available.\n",
+           fre_sect / 2, tot_sect / 2);
+
+
+ + +
+

See Also

+

FATFS

+
+ +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/gets.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/gets.html new file mode 100644 index 000000000..f0864a53e --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/gets.html @@ -0,0 +1,65 @@ + + + + + + + + +FatFs - f_gets + + + + +
+

f_gets

+

The f_gets reads a string from the file.

+
+TCHAR* f_gets (
+  TCHAR* Str,       /* Read buffer */
+  int Size,         /* Size of the read buffer */
+  FIL* FileObject   /* File object */
+);
+
+
+ +
+

Parameters

+
+
Str
+
Pointer to read buffer to store the read string.
+
Size
+
Size of the read buffer in unit of character.
+
FileObject
+
Pointer to the open file object structure.
+
+
+ + +
+

Return Values

+

When the function succeeded, Str will be returuned.

+
+ + +
+

Description

+

The f_gets() is a wrapper function of f_read(). The read operation continues until a '\n' is stored, reached end of the file or the buffer is filled with Size - 1 characters. The read string is terminated with a '\0'. When no character to read or any error occured during read operation, f_gets() returns a null pointer. The end of file and error status can be examined with f_eof() and f_error() macros.

+

When the FatFs is configured to Unicode API (_LFN_UNICODE == 1), the file is read in UTF-8 encoding and stored it to the buffer in UCS-2. If not the case, the file will be read in one byte per character without any code conversion.

+
+ + +
+

QuickInfo

+

Available when _USE_STRFUNC is 1 or 2. When it is set to 2, '\r's contained in the file are stripped out.

+
+ + + + +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/lseek.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/lseek.html new file mode 100644 index 000000000..8505579da --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/lseek.html @@ -0,0 +1,128 @@ + + + + + + + + +FatFs - f_lseek + + + + +
+

f_lseek

+

The f_lseek function moves the file read/write pointer of an open file object. It can also be used to increase the file size (cluster pre-allocation).

+ +
+FRESULT f_lseek (
+  FIL* FileObject,   /* Pointer to the file object structure */
+  DWORD Offset       /* File offset in unit of byte */
+);
+
+
+ +
+

Parameters

+
+
FileObject
+
Pointer to the open file object.
+
Offset
+
Number of bytes where from start of the file
+
+
+ + + + + +
+

Description

+

The f_lseek function moves the file read/write pointer of an open file. The offset can be specified in only origin from top of the file. When an offset above the file size is specified in write mode, the file size is increased to the offset and the data in the expanded area is undefined. This is suitable to create a large file quickly, for fast write operation. After the f_lseek function succeeded, current read/write pointer (member fptr in the file object) should be checked in order to make sure the read/write pointer has been moved correctry. In case of the current read/write pointer is not the expected value, either of followings has been occured.

+
    +
  • End of file. The specified Offset was clipped at the file size because the file has been opened in read-only mode.
  • +
  • Disk full. There is insufficient free space on the volume to expand the file size.
  • +
+

Fast seek mode is enabled when _USE_FASTSEEK is set to 1 and the member cltbl in the file object is not NULL. This feature enables fast backward/long seek operations without FAT access by cluster link map table (CLMT) stored in the user defined table. It is also applied to f_read/f_write functions. In this mode, the file size cannot be increased by f_write/f_lseek functions.

+

The CLMT must be created in the user defined DWORD array prior to use fast seek feature. To create the CLMT, set pointer to the DWORD array to the member cltbl in the file object, set the array size in unit of items into the first item and call the f_lseek function with Offset = CREATE_LINKMAP. After the function succeeded and CLMT is created, no FAT access is occured in subsequent f_read/f_write/f_lseek functions to the file. If the function failed with FR_NOT_ENOUGH_CORE, the given array size is insufficient for the file and the required items is returned into the first item of the array. The required array size is (number of fragments + 1) * 2 items. For example, when the file is fragmented in 5, 12 items will be required for the CLMT.

+
+ + +
+

QuickInfo

+

Available when _FS_MINIMIZE <= 2.

+
+ + +
+

Example

+
+    /* Open file */
+    file = malloc(sizeof(FIL));
+    if (!file) ...
+    res = f_open(file, "file.dat", FA_READ|FA_WRITE);
+    if (res) ...
+
+    /* Move to offset of 5000 from top of the file */
+    res = f_lseek(file, 5000);
+
+    /* Move to end of the file to append data */
+    res = f_lseek(file, f_size(file));
+
+    /* Forward 3000 bytes */
+    res = f_lseek(file, f_tell(file) + 3000);
+
+    /* Rewind 2000 bytes (take care on overflow) */
+    res = f_lseek(file, f_tell(file) - 2000);
+
+
    /* Cluster pre-allocation (to prevent buffer overrun on streaming write) */
+
+    res = f_open(file, recfile, FA_CREATE_NEW | FA_WRITE); /* Create a file */
+
+    res = f_lseek(file, PRE_SIZE);           /* Pre-allocate clusters */
+    if (res || f_tell(file) != PRE_SIZE) ... /* Check if the file size has been increased correctly */
+
+    res = f_lseek(file, DATA_START);         /* Record data stream without cluster allocation delay */
+    ...
+
+    res = f_truncate(file);                  /* Truncate unused area */
+    res = f_lseek(file, 0);                  /* Put file header */
+    ...
+
+    res = f_close(file);
+
+
    /* Using fast seek feature */
+
+    DWORD lktbl[SZ_TBL];                   /* Link map table buffer */
+
+    res = f_lseek(file, ofs1);             /* This is normal seek (file.cltbl is nulled on file open) */
+
+    file.cltbl = lktbl;                    /* Enable fast seek feature */
+    lktbl[0] = SZ_TBL;                     /* Set table size to the first item */
+    res = f_lseek(file, CREATE_LINKMAP);   /* Create CLMT */
+    ...
+
+    res = f_lseek(file, ofs2);             /* This is fast seek (file.cltbl != NULL) */
+
+
+ + +
+

See Also

+

f_open, f_truncate, FIL

+
+ +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/mkdir.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/mkdir.html new file mode 100644 index 000000000..bd9d43517 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/mkdir.html @@ -0,0 +1,80 @@ + + + + + + + + +FatFs - f_mkdir + + + + +
+

f_mkdir

+

The f_mkdir function creates a new directory.

+
+FRESULT f_mkdir (
+  const TCHAR* DirName /* Pointer to the directory name */
+);
+
+
+ +
+

Parameter

+
+
DirName
+
Pointer to the null-terminated string that specifies the directory name to create.
+
+
+ + + + + +
+

Description

+

The f_mkdir function creates a new directory.

+
+ + +
+

QuickInfo

+

Available when _FS_READONLY == 0 and _FS_MINIMIZE == 0.

+
+ + +
+

Example

+
+    res = f_mkdir("sub1");
+    if (res) die(res);
+    res = f_mkdir("sub1/sub2");
+    if (res) die(res);
+    res = f_mkdir("sub1/sub2/sub3");
+    if (res) die(res);
+
+
+ +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/mkfs.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/mkfs.html new file mode 100644 index 000000000..86753a237 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/mkfs.html @@ -0,0 +1,73 @@ + + + + + + + + +FatFs - f_mkfs + + + + +
+

f_mkfs

+

The f_mkfs fucntion creates an FAT file system on the logical drive.

+
+FRESULT f_mkfs (
+  BYTE  Drive,            /* Logical drive number */
+  BYTE  PartitioningRule, /* Partitioning rule */
+  UINT  AllocSize         /* Size of the allocation unit */
+);
+
+
+ +
+

Parameters

+
+
Drive
+
Logical drive number (0-9) to be formatted.
+
PartitioningRule
+
Specifies partitioning rule, FDISK(0) or SFD(1). This argument is ignored on some case.
+
AllocSize
+
Force the allocation unit (cluter) size in unit of byte. The value must be power of 2 and between the sector size and 128 * sector size. When a zero is given, the cluster size is determined depends on the volume size.
+
+
+ + + +
+

Description

+

The f_mkfs function creates an FAT volume on the logical drive. When FDISK is specified, a primary partition occupies the entire disk space is created and then an FAT volume is created on the partition. When SFD is specified, the FAT volume starts from the first sector of the physical drive.

+

If the logical drive is being bound to any partition (1-4) by multiple partition feature (_MULTI_PARTITION), the FAT volume is created into the specified partition. In this case, the second argument is ignored. The physical drive must be partitioned with f_fdisk function or any other partitioning tool prior to use this function.

+

Note that there are two partitioning rules, FDISK and SFD. The FDISK format is usually used for harddisk, MMC, SDC and CFC. It can divide a physical drive into one or more partitions with a partition table on the MBR. The SFD format is non-partitioned method. The FAT volume starts from the first sector on the physical drive without partition table. It is used for floppy disk, Microdrive, optical disk and super-floppy media.

+

The FAT sub-type, FAT12/FAT16/FAT32, is determined by number of clusters on the volume and nothing else, according to the FAT specification issued by Microsoft. Thus which FAT sub-type is selected, is depends on the volume size and the specified cluster size. The cluster size affects performance of the file system and large cluster increases the performance.

+

When the number of clusters gets near the FAT sub-type boundaries, the function can fail with FR_MKFS_ABORTED.

+
+ +
+

QuickInfo

+

Available when _FS_READOLNY == 0 and _USE_MKFS == 1.

+
+ +
+

See Also

+

Volume management, f_fdisk

+
+ +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/mount.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/mount.html new file mode 100644 index 000000000..ea3c3a83c --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/mount.html @@ -0,0 +1,64 @@ + + + + + + + + +FatFs - f_mount + + + + +
+

f_mount

+

The f_mount fucntion registers/unregisters a work area to the FatFs module.

+
+FRESULT f_mount (
+  BYTE  Drive,              /* Logical drive number */
+  FATFS*  FileSystemObject  /* Pointer to the work area */
+);
+
+
+ +
+

Parameters

+
+
Drive
+
Logical drive number (0-9) to register/unregister the work area.
+
FileSystemObject
+
Pointer to the work area (file system object) to be registered.
+
+
+ +
+

Return Values

+

+FR_OK, +FR_INVALID_DRIVE +

+
+ + +
+

Description

+

The f_mount function registers/unregisters a work area to the FatFs module. The work area must be given to the each volume with this function prior to use any other file function. To unregister a work area, specify a NULL to the FileSystemObject, and then the work area can be discarded.

+

This function always succeeds regardless of the drive status. No media access is occured in this function. It only initializes the given work area and registers its address to the internal table. The volume mount process is performed on first file access after f_mount function or media change.

+
+ + +
+

QuickInfo

+

Always available.

+
+ + +
+

See Also

+

FATFS

+
+ +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/open.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/open.html new file mode 100644 index 000000000..a2c739d7f --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/open.html @@ -0,0 +1,139 @@ + + + + + + + + +FatFs - f_open + + + + +
+

f_open

+

The f_open function creates a file object to be used to access the file.

+
+FRESULT f_open (
+  FIL* FileObject,       /* Pointer to the blank file object structure */
+  const TCHAR* FileName, /* Pointer to the file neme */
+  BYTE ModeFlags         /* Mode flags */
+);
+
+
+ +
+

Parameters

+
+
FileObject
+
Pointer to the file object structure to be created.
+
FileName
+
Pointer to a null-terminated string that specifies the file name to create or open.
+
ModeFlags
+
Specifies the type of access and open method for the file. It is specified by a combination of following flags.
+ + + + + + + + +
ValueDescription
FA_READSpecifies read access to the object. Data can be read from the file.
Combine with FA_WRITE for read-write access.
FA_WRITESpecifies write access to the object. Data can be written to the file.
Combine with FA_READ for read-write access.
FA_OPEN_EXISTINGOpens the file. The function fails if the file is not existing. (Default)
FA_OPEN_ALWAYSOpens the file if it is existing. If not, a new file is created.
+To append data to the file, use f_lseek function after file open in this method.
FA_CREATE_NEWCreates a new file. The function fails with FR_EXIST if the file is existing.
FA_CREATE_ALWAYSCreates a new file. If the file is existing, it is truncated and overwritten.
+
+
+
+ + + + + +
+

Description

+

After f_open function succeeded, the file object is valid. The file object is used for subsequent read/write functions to identify the file. When close an open file object, use f_close function. If the modified file is not closed, the file data can be collapsed.

+

If duplicated file open is needed, read here carefully.

+

Before using any file function, a work area (file system object) must be registered to the logical drive with f_mount function. All API functions except for f_fdisk function can work after this procedure.

+
+ + +
+

QuickInfo

+

Always available. The mode flags, FA_WRITE, FA_CREATE_ALWAYS, FA_CREATE_NEW and FA_OPEN_ALWAYS, are not available when _FS_READONLY == 1.

+
+ + +
+

Example (File Copy)

+
+void main (void)
+{
+    FATFS fs[2];         /* Work area (file system object) for logical drives */
+    FIL fsrc, fdst;      /* file objects */
+    BYTE buffer[4096];   /* file copy buffer */
+    FRESULT res;         /* FatFs function common result code */
+    UINT br, bw;         /* File read/write count */
+
+
+    /* Register work area for each volume (Always succeeds regardless of disk status) */
+    f_mount(0, &fs[0]);
+    f_mount(1, &fs[1]);
+
+    /* Open source file on the drive 1 */
+    res = f_open(&fsrc, "1:srcfile.dat", FA_OPEN_EXISTING | FA_READ);
+    if (res) die(res);
+
+    /* Create destination file on the drive 0 */
+    res = f_open(&fdst, "0:dstfile.dat", FA_CREATE_ALWAYS | FA_WRITE);
+    if (res) die(res);
+
+    /* Copy source to destination */
+    for (;;) {
+        res = f_read(&fsrc, buffer, sizeof buffer, &br);     /* Read a chunk of src file */
+        if (res || br == 0) break; /* error or eof */
+        res = f_write(&fdst, buffer, br, &bw);               /* Write it to the dst file */
+        if (res || bw < br) break; /* error or disk full */
+    }
+
+    /* Close open files */
+    f_close(&fsrc);
+    f_close(&fdst);
+
+    /* Unregister work area prior to discard it */
+    f_mount(0, NULL);
+    f_mount(1, NULL);
+}
+
+
+ + +
+

See Also

+

f_read, f_write, f_close, FIL, FATFS

+
+ +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/opendir.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/opendir.html new file mode 100644 index 000000000..ed68cfc8d --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/opendir.html @@ -0,0 +1,73 @@ + + + + + + + + +FatFs - f_opendir + + + + +
+

f_opendir

+

The f_opendir function opens a directory.

+
+FRESULT f_opendir (
+  DIR* DirObject,       /* Pointer to the blank directory object structure */
+  const TCHAR* DirName  /* Pointer to the directory name */
+);
+
+
+ +
+

Parameters

+
+
DirObject
+
Pointer to the blank directory object to be created.
+
DirName
+
Pinter to the null-terminated string that specifies the directory name to be opened.
+
+
+ + + + + +
+

Description

+

The f_opendir function opens an exsisting directory and creates the directory object for subsequent calls. The directory object structure can be discarded at any time without any procedure.

+
+ + +
+

QuickInfo

+

Available when _FS_MINIMIZE <= 1.

+
+ + +
+

See Also

+

f_readdir, DIR

+
+ +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/printf.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/printf.html new file mode 100644 index 000000000..5d153265f --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/printf.html @@ -0,0 +1,90 @@ + + + + + + + + +FatFs - f_printf + + + + +
+

f_printf

+

The f_printf function writes formatted string to the file.

+
+int f_printf (
+  FIL* FileObject,      /* File object */
+  const TCHAR* Foramt,  /* Format stirng */
+  ...
+);
+
+
+ +
+

Parameters

+
+
FileObject
+
Pointer to the open file object structure.
+
Format
+
Pointer to the null terminated format string.
+
...
+
Optional arguments.
+ +
+
+ + +
+

Return Values

+

When the function succeeded, number of characters written is returned. When the function failed due to disk full or any error, an EOF (-1) will be returned.

+
+ + +
+

Description

+

The f_printf() is a wrapper function of f_putc() and f_puts(). The format control directive is a sub-set of standard library shown as follos:

+
    +
  • Type: c C s S d D u U x X b B
  • +
  • Size: l L
  • +
  • Flag: 0 -
  • +
+
+ + +
+

QuickInfo

+

Available when _FS_READONLY == 0 and _USE_STRFUNC is 1 or 2. When it is set to 2, '\n's contained in the output are converted to "\r\n".

+

When the FatFs is configured to Unicode API (_LFN_UNICODE == 1), the generated UCS-2 characters are written to the file in UTF-8 encoding. If not the case, the byte characters will be written directly.

+
+ + +
+

Example

+
+    f_printf(&fil, "%d", 1234);            /* "1234" */
+    f_printf(&fil, "%6d,%3d%%", -200, 5);  /* "  -200,  5%" */
+    f_printf(&fil, "%-6u", 100);           /* "100   " */
+    f_printf(&fil, "%ld", 12345678L);      /* "12345678" */
+    f_printf(&fil, "%04x", 0xA3);          /* "00a3" */
+    f_printf(&fil, "%08LX", 0x123ABC);     /* "00123ABC" */
+    f_printf(&fil, "%016b", 0x550F);       /* "0101010100001111" */
+    f_printf(&fil, "%s", "String");        /* "String" */
+    f_printf(&fil, "%-4s", "abc");         /* "abc " */
+    f_printf(&fil, "%4s", "abc");          /* " abc" */
+    f_printf(&fil, "%c", 'a');             /* "a" */
+    f_printf(&fil, "%f", 10.0);            /* f_printf lacks floating point support */
+
+
+ + +
+

See Also

+

f_open, f_putc, f_puts, f_gets, f_close, FIL

+
+ +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/putc.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/putc.html new file mode 100644 index 000000000..4cabcb044 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/putc.html @@ -0,0 +1,62 @@ + + + + + + + + +FatFs - f_putc + + + + +
+

f_putc

+

The f_putc funciton puts a character to the file.

+
+int f_putc (
+  TCHAR Chr,        /* A character to put */
+  FIL* FileObject   /* File object */
+);
+
+
+ +
+

Parameters

+
+
Chr
+
A character to be put.
+
FileObject
+
Pointer to the open file object structuer.
+
+
+ + +
+

Return Values

+

When the character was written successfuly, the function returns 1. When the function failed due to disk full or any error, an EOF (-1) will be returned.

+

When the FatFs is configured to Unicode API (_LFN_UNICODE == 1), the UTF-16 character is written to the file in UTF-8 encoding. If not the case, the byte will be written directly.

+
+ + +
+

Description

+

The f_putc() is a wrapper function of f_write().

+
+ + +
+

QuickInfo

+

Available when _FS_READONLY == 0 and _USE_STRFUNC is 1 or 2. When it is set to 2, a '\n' is converted to "\r\n".

+
+ + +
+

See Also

+

f_open, f_puts, f_printf, f_gets, f_close, FIL

+
+ +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/puts.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/puts.html new file mode 100644 index 000000000..6fa733fbe --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/puts.html @@ -0,0 +1,62 @@ + + + + + + + + +FatFs - f_puts + + + + +
+

f_puts

+

The f_puts function writes a string to the file.

+
+int f_puts (
+  const TCHAR* Str,  /* String */
+  FIL* FileObject    /* File object */
+);
+
+
+ +
+

Parameters

+
+
Str
+
Pointer to the null terminated string to be written. The null character will not be written.
+
FileObject
+
Pointer to the open file object structure.
+
+
+ + +
+

Return Value

+

When the function succeeded, number of characters written that is not minus value is returned. When the write operation is aborted due to disk full or any error, an EOF (-1) will be returned.

+

When the FatFs is configured to Unicode API (_LFN_UNICODE == 1), the UTF-16 string is written to the file in UTF-8 encoding. If not the case, the byte stream will be written directly.

+
+ + +
+

Description

+

The f_puts() is a wrapper function of f_putc().

+
+ + +
+

QuickInfo

+

Available when _FS_READONLY == 0 and _USE_STRFUNC is 1 or 2. When it is set to 2, '\n's contained in the string are converted to "\r\n".

+
+ + +
+

See Also

+

f_open, f_putc, f_printf, f_gets, f_close, FIL

+
+ +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/rc.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/rc.html new file mode 100644 index 000000000..c6d9dd6ce --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/rc.html @@ -0,0 +1,85 @@ + + + + + + + + +FatFs - Return Codes + + + +

Return Code of the File Functions

+

On the FatFs API, most of file functions return common result code as enum type. When a function succeeded, it returns zero, otherwise returns non-zero value that indicates type of error.

+ +
+
FR_OK (0)
+
The function succeeded.
+
FR_DISK_ERR
+
An unrecoverable error occured in the lower layer (disk I/O functions).
+
FR_INT_ERR
+
Assertion failed. An insanity is detected in the internal process. One of the following possibilities are suspected. +
    +
  • There is any error of the FAT structure on the volume.
  • +
  • Work area (file system object, file object or etc...) is broken by stack overflow or any other application. This is the reason in most case.
  • +
+
+
FR_NOT_READY
+
The disk drive cannot work due to incorrect medium removal or disk_initialize function failed.
+
FR_NO_FILE
+
Could not find the file.
+
FR_NO_PATH
+
Could not find the path.
+
FR_INVALID_NAME
+
The given string is invalid as the path name.
+
FR_DENIED
+
The required access was denied due to one of the following reasons: +
    +
  • Write mode open against the file with read-only attribute.
  • +
  • Deleting the file or directory with read-only attribute.
  • +
  • Deleting the non-empty directory or current directory.
  • +
  • Reading the file opened without FA_READ flag.
  • +
  • Any modification to the file opened without FA_WRITE flag.
  • +
  • Could not create the file or directory due to the directory table is full.
  • +
  • Could not create the directory due to the volume is full.
  • +
+
+
FR_EXIST
+
Any object that has the same name is already existing.
+
FR_INVALID_OBJECT
+
The given file/directory object structure is invalid.
+
FR_WRITE_PROTECTED
+
Any write mode action against write-protected media.
+
FR_INVALID_DRIVE
+
Invalid drive number is specified. (Related option: _VOLUMES)
+
FR_NOT_ENABLED
+
Work area for the logical drive has not been registered by f_mount function.
+
FR_NO_FILESYSTEM
+
There is no valid FAT volume on the drive.
+
FR_MKFS_ABORTED
+
The f_mkfs function aborted before start in format due to a reason as follows: +
    +
  • The disk size is too small.
  • +
  • Not allowable cluster size for this disk. This can occure when number of clusters gets near the 0xFF7 and 0xFFF7.
  • +
+
+
FR_TIMEOUT
+
The function canceled due to a timeout of thread-safe control. (Related option: _TIMEOUT)
+
FR_LOCKED
+
The file access is rejected by file sharing control. (Related option: _FS_SHARE)
+
FR_NOT_ENOUGH_CORE
+
Not enough memory for the operation. There is one of the following reasons: +
    +
  • Could not allocate a memory for LFN working buffer. (Related option: _USE_LFN)
  • +
  • Given table size is insufficient for the required size.
  • +
+
+
FR_TOO_MANY_OPEN_FILES
+
Number of open files has been reached maximum value and no more file can be opened. (Related option: _FS_SHARE)
+
FR_INVALID_PARAMETER
+
The given parameter is invalid or there is any inconsistent.
+
+ + + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/read.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/read.html new file mode 100644 index 000000000..52f824d5a --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/read.html @@ -0,0 +1,74 @@ + + + + + + + + +FatFs - f_read + + + + +
+

f_read

+

The f_read function reads data from a file.

+
+FRESULT f_read (
+  FIL* FileObject,    /* Pointer to the file object structure */
+  void* Buffer,       /* Pointer to the buffer to store read data */
+  UINT ByteToRead,    /* Number of bytes to read */
+  UINT* ByteRead      /* Pointer to the variable to return number of bytes read */
+);
+
+
+ +
+

Parameters

+
+
FileObject
+
Pointer to the open file object.
+
Buffer
+
Pointer to the buffer to store read data
+
ByteToRead
+
Number of bytes to read in range of UINT.
+
ByteRead
+
Pointer to the UINT variable to return number of bytes read. The value is always valid after the function call regardless of the result.
+
+
+ + + + + +
+

Description

+

The file pointer of the file object increases in number of bytes read. After the function succeeded, *ByteRead should be checked to detect the end of file. In case of *ByteRead < ByteToRead, it means the read/write pointer reached end of the file during read operation.

+
+ + +
+

QuickInfo

+

Always available.

+
+ + +
+

See Also

+

f_open, fgets, f_write, f_close, FIL

+
+ +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/readdir.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/readdir.html new file mode 100644 index 000000000..267facf96 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/readdir.html @@ -0,0 +1,119 @@ + + + + + + + + +FatFs - f_readdir + + + + +
+

f_readdir

+

The f_readdir function reads directory entries.

+
+FRESULT f_readdir (
+  DIR* DirObject,    /* Pointer to the open directory object */
+  FILINFO* FileInfo  /* Pointer to the file information structure */
+);
+
+
+ +
+

Parameters

+
+
DirObject
+
Pointer to the open directory object.
+
FileInfo
+
Pointer to the file information structure to store the read item.
+
+
+ + + + + +
+

Description

+

The f_readdir function reads directory entries in sequence. All items in the directory can be read by calling f_readdir function repeatedly. When all directory entries have been read and no item to read, the function returns a null string into f_name[] member without any error. When a null pointer is given to the FileInfo, the read index of the directory object will be rewinded.

+

When LFN feature is enabled, lfname and lfsize in the file information structure must be initialized with valid value prior to use the f_readdir function. The lfname is a pointer to the string buffer to return the long file name. The lfsize is the size of the string buffer in unit of TCHAR. If either the size of read buffer or LFN working buffer is insufficient for the LFN or the object has no LFN, a null string will be returned to the LFN read buffer. If the LFN contains any charactrer that cannot be converted to OEM code, a null string will be returned but this is not the case on Unicode API configuration. When lfname is a NULL, nothing of the LFN is returned. When the object has no LFN, some small capitals can be contained in the SFN.

+

When relative path feature is enabled (_FS_RPATH == 1), "." and ".." entries are not filtered out and it will appear in the read entries.

+
+ + +
+

QuickInfo

+

Available when _FS_MINIMIZE <= 1.

+
+ + +
+

Sample Code

+
+FRESULT scan_files (
+    char* path        /* Start node to be scanned (also used as work area) */
+)
+{
+    FRESULT res;
+    FILINFO fno;
+    DIR dir;
+    int i;
+    char *fn;   /* This function is assuming non-Unicode cfg. */
+#if _USE_LFN
+    static char lfn[_MAX_LFN + 1];
+    fno.lfname = lfn;
+    fno.lfsize = sizeof(lfn);
+#endif
+
+
+    res = f_opendir(&dir, path);                       /* Open the directory */
+    if (res == FR_OK) {
+        i = strlen(path);
+        for (;;) {
+            res = f_readdir(&dir, &fno);                   /* Read a directory item */
+            if (res != FR_OK || fno.fname[0] == 0) break;  /* Break on error or end of dir */
+            if (fno.fname[0] == '.') continue;             /* Ignore dot entry */
+#if _USE_LFN
+            fn = *fno.lfname ? fno.lfname : fno.fname;
+#else
+            fn = fno.fname;
+#endif
+            if (fno.fattrib & AM_DIR) {                    /* It is a directory */
+                sprintf(&path[i], "/%s", fn);
+                res = scan_files(path);
+                if (res != FR_OK) break;
+                path[i] = 0;
+            } else {                                       /* It is a file. */
+                printf("%s/%s\n", path, fn);
+            }
+        }
+    }
+
+    return res;
+}
+
+
+ + +
+

See Also

+

f_opendir, f_stat, FILINFO, DIR

+
+ +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/rename.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/rename.html new file mode 100644 index 000000000..cc07ef911 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/rename.html @@ -0,0 +1,84 @@ + + + + + + + + +FatFs - f_rename + + + + +
+

f_rename

+

Renames an object.

+
+FRESULT f_rename (
+  const TCHAR* OldName, /* Pointer to old object name */
+  const TCHAR* NewName  /* Pointer to new object name */
+);
+
+
+ +
+

Parameters

+
+
OldName
+
Pointer to a null-terminated string specifies the old object name to be renamed.
+
NewName
+
Pointer to a null-terminated string specifies the new object name without drive number.
+
+
+ + + + + +
+

Description

+

Renames an object (file or directory) and can also move it to other directory. The logical drive number is determined by old name, new name must not contain a logical drive number. Do not rename open objects.

+
+ + +
+

QuickInfo

+

Available when _FS_READONLY == 0 and _FS_MINIMIZE == 0.

+
+ + +
+

Example

+
+    /* Rename an object */
+    f_rename("oldname.txt", "newname.txt");
+
+    /* Rename and move an object to other directory */
+    f_rename("oldname.txt", "dir1/newname.txt");
+
+
+ +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/sdir.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/sdir.html new file mode 100644 index 000000000..a127270e2 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/sdir.html @@ -0,0 +1,37 @@ + + + + + + + + +FatFs - DIR + + + + +
+

DIR

+

The DIR structure is used for the work area to read a directory by f_oepndir, f_readdir function. There is no member that can be changed by application.

+
+typedef struct {
+    FATFS*  fs;         /* Pointer to the owner file system object */
+    WORD    id;         /* Owner file system mount ID */
+    WORD    index;      /* Directory index number to be read/write next */
+    DWORD   sclust;     /* Table start cluster (0:Root dir) */
+    DWORD   clust;      /* Current cluster */
+    DWORD   sect;       /* Current sector */
+    BYTE*   dir;        /* Pointer to the current SFN entry in the win[] */
+    BYTE*   fn;         /* Pointer to the SFN (in/out) {file[8],ext[3],status[1]} */
+#if _USE_LFN
+    WCHAR*  lfn;        /* Pointer to the LFN working buffer */
+    WORD    lfn_idx;    /* Last matched LFN index (0xFFFF:No LFN) */
+#endif
+} DIR;
+
+
+ +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/sfatfs.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/sfatfs.html new file mode 100644 index 000000000..81659ae01 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/sfatfs.html @@ -0,0 +1,54 @@ + + + + + + + + +FatFs - FATFS + + + + +
+

FATFS

+

The FATFS structure (file system object) holds dynamic work area of individual logical drives. It is given by application program and registerd/unregisterd to the FatFs module with f_mount function. Initialization is done on first file access after f_mount or media change. There is no member that can be changed from the application program.

+
+typedef struct {
+    BYTE    fs_type;      /* FAT sub-type (0:Not mounted) */
+    BYTE    drv;          /* Physical drive number */
+    BYTE    csize;        /* Sectors per cluster (1,2,4...128) */
+    BYTE    n_fats;       /* Number of FAT copies (1,2) */
+    BYTE    wflag;        /* win[] dirty flag */
+    BYTE    fsi_flag;     /* fsinfo dirty flag */
+    WORD    id;           /* File system mount ID */
+    WORD    n_rootdir;    /* Number of root directory entries (FAT12/16) */
+#if _MAX_SS != 512
+    WORD    ssize;        /* Sector size (512,1024,2048,4096) */
+#endif
+#if _FS_REENTRANT
+    _SYNC_t sobj;         /* Identifier of sync object */
+#endif
+#if !_FS_READONLY
+    DWORD   last_clust;   /* Last allocated cluster */
+    DWORD   free_clust;   /* Number of free clusters */
+    DWORD   fsi_sector;   /* fsinfo sector (FAT32) */
+#endif
+#if _FS_RPATH
+    DWORD   cdir;         /* Current directory cluster (0:root) */
+#endif
+    DWORD   n_fatent;     /* Number of FAT entries (= number of clusters + 2) */
+    DWORD   fsize;        /* Sectors per FAT */
+    DWORD   fatbase;      /* FAT area start sector */
+    DWORD   dirbase;      /* Root directory area start sector (FAT32: cluster#) */
+    DWORD   database;     /* Data area start sector */
+    DWORD   winsect;      /* Current sector appearing in the win[] */
+    BYTE    win[_MAX_SS]; /* Disk access window for Directory, FAT (and Data on tiny cfg) */
+} FATFS;
+
+
+ +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/sfile.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/sfile.html new file mode 100644 index 000000000..0a29ddcd5 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/sfile.html @@ -0,0 +1,49 @@ + + + + + + + + +FatFs - FIL + + + + +
+

FIL

+

The FIL structure (file object) holds state of an open file. It is created by f_open function and discarded by f_close function. There is no member that can be changed by the application program except for cltbl. Note that a sector buffer is defined in this structure under non-tiny configuration so that the FIL structures should not be defined as auto variable.

+ +
+typedef struct {
+    FATFS*  fs;           /* Pointer to the owner file system object */
+    WORD    id;           /* Owner file system mount ID */
+    BYTE    flag;         /* File status flags */
+    BYTE    pad1;
+    DWORD   fptr;         /* File read/write pointer (Byte offset origin from top of the file) */
+    DWORD   fsize;        /* File size */
+    DWORD   sclust;       /* File start cluster */
+    DWORD   clust;        /* Current cluster */
+    DWORD   dsect;        /* Current data sector */
+#if !_FS_READONLY
+    DWORD   dir_sect;     /* Sector containing the directory entry */
+    BYTE*   dir_ptr;      /* Ponter to the directory entry in the window */
+#endif
+#if _USE_FASTSEEK
+    DWORD*  cltbl;        /* Pointer to the cluster link map table (Nulled on file open) */
+#endif
+#if _FS_SHARE
+    UINT    lockid;       /* File lock ID */
+#endif
+#if !_FS_TINY
+    BYTE    buf[_MAX_SS]; /* Data read/write buffer */
+#endif
+} FIL;
+
+ +
+ +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/sfileinfo.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/sfileinfo.html new file mode 100644 index 000000000..ef1752dbe --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/sfileinfo.html @@ -0,0 +1,70 @@ + + + + + + + + +FatFs - FILINFO + + + + +
+

FILINFO

+

The FILINFO structure holds a file information returned by f_stat and f_readdir function.

+
+typedef struct {
+    DWORD fsize;      /* File size */
+    WORD  fdate;      /* Last modified date */
+    WORD  ftime;      /* Last modified time */
+    BYTE  fattrib;    /* Attribute */
+    TCHAR fname[13];  /* Short file name (8.3 format) */
+#if _USE_LFN
+    TCHAR* lfname;    /* Pointer to the LFN buffer */
+    int   lfsize;     /* Size of the LFN buffer in unit of TCHAR */
+#endif
+} FILINFO;
+
+
+ +

Members

+
+
fsize
+
Indicates size of the file in unit of byte. Always zero for directories.
+
fdate
+
Indicates the date that the file was modified or the directory was created.
+
+
bit15:9
+
Year origin from 1980 (0..127)
+
bit8:5
+
Month (1..12)
+
bit4:0
+
Day (1..31)
+
+
+
ftime
+
Indicates the time that the file was modified or the directory was created.
+
+
bit15:11
+
Hour (0..23)
+
bit10:5
+
Minute (0..59)
+
bit4:0
+
Second / 2 (0..29)
+
+
+
fattrib
+
Indicates the file/directory attribute in combination of AM_DIR, AM_RDO, AM_HID, AM_SYS and AM_ARC.
+
fname[]
+
Indicates the file/directory name in 8.3 format null-terminated string. It is always returnd with upper case on non-LFN configuration but it can be returned with lower case on LFN configuration.
+
lfname
+
Pointer to the LFN buffer to store the read LFN. This member must be initialized by application prior to use this structure. Not available on non-LFN configuration.
+
lfsize
+
Size of the LFN buffer in unit of TCHAR. This member must be initialized by application prior to use this structure. Not available on non-LFN configuration.
+
+ +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/size.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/size.html new file mode 100644 index 000000000..9325c9b07 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/size.html @@ -0,0 +1,62 @@ + + + + + + + + +FatFs - f_size + + + + +
+

f_size

+

The f_size function gets the size of a file.

+
+DWORD f_size (
+  FIL* FileObject   /* File object */
+);
+
+
+ + +
+

Parameters

+
+
FileObject
+
Pointer to the open file object structure.
+
+
+ + +
+

Return Values

+

Returns the size of the file in unit of byte.

+
+ + +
+

Description

+

In this revision, the f_size function is implemented as a macro.

+
+#define f_size(fp) ((fp)->fsize)
+
+
+ + +
+

QuickInfo

+

Always available.

+
+ + +
+

See Also

+

f_open, f_lseek, FIL

+
+ +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/stat.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/stat.html new file mode 100644 index 000000000..5b51190e7 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/stat.html @@ -0,0 +1,68 @@ + + + + + + + + +FatFs - f_stat + + + + +
+

f_stat

+

The f_stat gets the file status.

+
+FRESULT f_stat (
+  const TCHAR* FileName,  /* Pointer to the file or directory name */
+  FILINFO* FileInfo       /* Pointer to the FILINFO structure */
+);
+
+
+ +
+

Parameters

+
+
FileName
+
Pointer to the null-terminated string that specifies the file or directory to get its information.
+
FileInfo
+
Pointer to the blank FILINFO structure to store the information.
+
+
+ + + + + +
+

Description

+

The f_stat gets the information of a file or directory. For details of the infomation, refer to the FILINFO structure and f_readdir function. This function is not supported in minimization level of >= 1.

+
+ + +
+

References

+

f_opendir, f_readdir, FILINFO

+
+ +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/sync.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/sync.html new file mode 100644 index 000000000..6af2850c1 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/sync.html @@ -0,0 +1,65 @@ + + + + + + + + +FatFs - f_sync + + + + +
+

f_sync

+

The f_sync function flushes the cached information of a writing file.

+
+FRESULT f_sync (
+  FIL* FileObject     /* Pointer to the file object */
+);
+
+
+ +
+

Parameter

+
+
FileObject
+
Pointer to the open file object to be flushed.
+
+
+ + + + + +
+

Description

+

The f_sync function performs the same process as f_close function but the file is left opened and can continue read/write/seek operations to the file. This is suitable for the applications that open files for a long time in write mode, such as data logger. Performing f_sync of periodic or immediataly after f_write can minimize the risk of data loss due to a sudden blackout or an unintentional disk removal. However f_sync immediataly before f_close has no advantage because f_close performs f_sync in it. In other words, the differnce between those functions is that the file object is invalidated or not.

+
+ + +
+

QuickInfo

+

Available when _FS_READONLY == 0.

+
+ + +
+

See Also

+

f_close

+
+ +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/tell.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/tell.html new file mode 100644 index 000000000..acf4fcede --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/tell.html @@ -0,0 +1,62 @@ + + + + + + + + +FatFs - f_tell + + + + +
+

f_tell

+

The f_tell function gets the current read/write pointer of a file.

+
+DWORD f_tell (
+  FIL* FileObject   /* File object */
+);
+
+
+ + +
+

Parameters

+
+
FileObject
+
Pointer to the open file object structure.
+
+
+ + +
+

Return Values

+

Returns current read/write pointer of the file.

+
+ + +
+

Description

+

In this revision, the f_tell function is implemented as a macro.

+
+#define f_tell(fp) ((fp)->fptr)
+
+
+ + +
+

QuickInfo

+

Always available.

+
+ + +
+

See Also

+

f_open, f_lseek, FIL

+
+ +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/truncate.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/truncate.html new file mode 100644 index 000000000..65fc524a6 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/truncate.html @@ -0,0 +1,66 @@ + + + + + + + + +FatFs - f_truncate + + + + +
+

f_truncate

+

The f_truncate function truncates the file size.

+
+FRESULT f_truncate (
+  FIL* FileObject     /* Pointer to the file object */
+);
+
+
+ +
+

Parameter

+
+
FileObject
+
Pointer to the open file object to be truncated.
+
+
+ + + + + +
+

Description

+

The f_truncate function truncates the file size to the current file read/write point. This function has no effect if the file read/write pointer is already pointing end of the file.

+
+ + +
+

QuickInfo

+

Available when _FS_READONLY == 0 and _FS_MINIMIZE == 0.

+
+ + +
+

See Also

+

f_open, f_lseek, FIL

+
+ + +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/unlink.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/unlink.html new file mode 100644 index 000000000..86929dd46 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/unlink.html @@ -0,0 +1,76 @@ + + + + + + + + +FatFs - f_unlink + + + + +
+

f_unlink

+

The f_unlink function removes a file or directory.

+
+FRESULT f_unlink (
+  const TCHAR* FileName  /* Pointer to the object name */
+);
+
+
+ +
+

Parameter

+
+
FileName
+
Pointer to the null-terminated string that specifies an object to be removed.
+
+
+ + + + + +
+

Description

+

+If condition of the object to be removed is applicable to the following terms, the function will fail with error. +

    +
  • The object must not have read-only attribute (AM_RDO) or the function will be rejected with FR_DENIED.
  • +
  • The directory must be empty and must not be current directory or the function will be rejected with FR_DENIED.
  • +
  • The file must not have been opened or the FAT volume can be collapted. It will able to be rejected with FR_LOCKED when file shareing control is enabled.
  • +
+
+ + +
+

QuickInfo

+

Available when _FS_READONLY == 0 and _FS_MINIMIZE == 0.

+
+ + +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/utime.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/utime.html new file mode 100644 index 000000000..83e582fa5 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/utime.html @@ -0,0 +1,99 @@ + + + + + + + + +FatFs - f_utime + + + + +
+

f_utime

+

The f_utime function changes the timestamp of a file or directory.

+
+FRESULT f_utime (
+  const TCHAR* FileName,   /* Pointer to the file or directory path */
+  const FILINFO* TimeDate  /* Time and data to be set */
+);
+
+
+ +
+

Parameters

+
+
FileName
+
Pointer to the null-terminated string that specifies a file or directory to be changed.
+
TimeDate
+
Pointer to the file information structure that has a timestamp to be set in member fdate and ftime. Do not care any other members.
+
+
+ + + + + +
+

Description

+

The f_utime function changes the timestamp of a file or directory

+
+ + +
+

Example

+
+FRESULT set_timestamp (
+    char *obj,     /* Pointer to the file name */
+    int year,
+    int month,
+    int mday,
+    int hour,
+    int min,
+    int sec
+)
+{
+    FILINFO fno;
+
+    fno.fdate = (WORD)(((year - 1980) * 512U) | month * 32U | mday);
+    fno.ftime = (WORD)(hour * 2048U | min * 32U | sec / 2U);
+
+    return f_utime(obj, &fno);
+}
+
+
+ + +
+

QuickInfo

+

Available when _FS_READONLY == 0 and _FS_MINIMIZE == 0.

+
+ + +
+

See Also

+

f_stat, FILINFO

+
+ +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/write.html b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/write.html new file mode 100644 index 000000000..42ae73b2e --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/en/write.html @@ -0,0 +1,74 @@ + + + + + + + + +FatFs - f_write + + + + +
+

f_write

+

The f_write writes data to a file.

+
+FRESULT f_write (
+  FIL* FileObject,     /* Pointer to the file object structure */
+  const void* Buffer,  /* Pointer to the data to be written */
+  UINT ByteToWrite,    /* Number of bytes to write */
+  UINT* ByteWritten    /* Pointer to the variable to return number of bytes written */
+);
+
+
+ +
+

Parameters

+
+
FileObject
+
Pointer to the open file object structure.
+
Buffer
+
Pointer to the data to be written.
+
ByteToWrite
+
Specifies number of bytes to write in range of UINT.
+
ByteWritten
+
Pointer to the UINT variable to return the number of bytes written. The value is always valid after the function call regardless of the result.
+
+
+ + + + + +
+

Description

+

The read/write pointer in the file object is increased in number of bytes written. After the function succeeded, *ByteWritten should be checked to detect the disk full. In case of *ByteWritten < ByteToWrite, it means the volume got full during the write operation. The function can take a time when the volume is full or close to full.

+
+ + +
+

QuickInfo

+

Available when _FS_READONLY == 0.

+
+ + +
+

See Also

+

f_open, f_read, fputc, fputs, fprintf, f_close, FIL

+
+ +

Return

+ + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/img/f1.png b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/img/f1.png new file mode 100644 index 000000000..5191700fd Binary files /dev/null and b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/img/f1.png differ diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/img/f2.png b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/img/f2.png new file mode 100644 index 000000000..8ef0ec241 Binary files /dev/null and b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/img/f2.png differ diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/img/f3.png b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/img/f3.png new file mode 100644 index 000000000..9111bfc97 Binary files /dev/null and b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/img/f3.png differ diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/img/f4.png b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/img/f4.png new file mode 100644 index 000000000..f9a6b4648 Binary files /dev/null and b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/img/f4.png differ diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/img/f5.png b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/img/f5.png new file mode 100644 index 000000000..b110b291e Binary files /dev/null and b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/img/f5.png differ diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/img/f6.png b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/img/f6.png new file mode 100644 index 000000000..a7b0d71ed Binary files /dev/null and b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/img/f6.png differ diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/img/layers.png b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/img/layers.png new file mode 100644 index 000000000..d485d6b60 Binary files /dev/null and b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/img/layers.png differ diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/img/layers3.png b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/img/layers3.png new file mode 100644 index 000000000..ac439b0b1 Binary files /dev/null and b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/img/layers3.png differ diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/img/rwtest.png b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/img/rwtest.png new file mode 100644 index 000000000..a34bf0621 Binary files /dev/null and b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/img/rwtest.png differ diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/img/rwtest2.png b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/img/rwtest2.png new file mode 100644 index 000000000..41a8c1f55 Binary files /dev/null and b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/img/rwtest2.png differ diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/img/rwtest3.png b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/img/rwtest3.png new file mode 100644 index 000000000..cbaa3d118 Binary files /dev/null and b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/img/rwtest3.png differ diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/updates.txt b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/updates.txt new file mode 100644 index 000000000..a592ff23e --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/doc/updates.txt @@ -0,0 +1,114 @@ +R0.09, Sep 6, 2011 + f_mkfs() supports multiple partition to finish the multiple partition feature. + Added f_fdisk(). (_MULTI_PARTITION = 2) + +R0.08b, Jan 15, 2011 + Fast seek feature is also applied to f_read() and f_write(). + f_lseek() reports required table size on creating CLMP. + Extended format syntax of f_printf function. + Ignores duplicated directory separators in given path names. + +R0.08a, Aug 16, 2010 + Added f_getcwd(). (_FS_RPATH = 2) + Added sector erase feature. (_USE_ERASE) + Moved file lock semaphore table from fs object to the bss. + Fixed a wrong directory entry is created on non-LFN cfg when the given name contains ';'. + Fixed f_mkfs() creates wrong FAT32 volume. + +R0.08, May 15, 2010 + Added a memory configuration option. (_USE_LFN) + Added file lock feature. (_FS_SHARE) + Added fast seek feature. (_USE_FASTSEEK) + Changed some types on the API, XCHAR->TCHAR. + Changed fname member in the FILINFO structure on Unicode cfg. + String functions support UTF-8 encoding files on Unicode cfg. + +R0.07e, Nov 3, 2009 + Separated out configuration options from ff.h to ffconf.h. + Added a configuration option, _LFN_UNICODE. + Fixed f_unlink() fails to remove a sub-dir on _FS_RPATH. + Fixed name matching error on the 13 char boundary. + Changed f_readdir() to return the SFN with always upper case on non-LFN cfg. + +R0.07c, Jun 21, 2009 + Fixed f_unlink() may return FR_OK on error. + Fixed wrong cache control in f_lseek(). + Added relative path feature. + Added f_chdir(). + Added f_chdrive(). + Added proper case conversion to extended characters. + +R0.07a, Apr 14, 2009 + Separated out OS dependent code on re-entrant configuration. + Added multiple sector size support. + +R0.07, Apr 01, 2009 + Merged Tiny-FatFs into FatFs as a buffer configuration option. + Added long file name support. + Added multiple code page support. + Added re-entrancy for multitask operation. + Added auto cluster size selection to f_mkfs(). + Added rewind option to f_readdir(). + Changed result code of critical errors. + Renamed string functions to avoid name collision. + +R0.06, Apr 01, 2008 + Added f_forward. (Tiny-FatFs) + Added string functions: fgets, fputc, fputs and fprintf. + Improved performance of f_lseek on moving to the same or following cluster. + +R0.05a, Feb 03, 2008 + Added f_truncate. + Added f_utime. + Fixed off by one error at FAT sub-type determination. + Fixed btr in f_read can be mistruncated. + Fixed cached sector is left not flushed when create and close without write. + +R0.05, Aug 26, 2007 + Changed arguments of f_read, f_write. + Changed arguments of f_mkfs. (FatFs) + Fixed f_mkfs on FAT32 creates incorrect FSInfo. (FatFs) + Fixed f_mkdir on FAT32 creates incorrect directory. (FatFs) + +R0.04b, May 05, 2007 + Added _USE_NTFLAG option. + Added FSInfo support. + Fixed some problems corresponds to FAT32. (Tiny-FatFs) + Fixed DBCS name can result FR_INVALID_NAME. + Fixed short seek (<= csize) collapses the file object. + +R0.04a, Apr 01, 2007 + Supported multiple partitions on a plysical drive. (FatFs) + Added minimization level 3. + Added a capability of extending file size to f_lseek. + Fixed an endian sensitive code in f_mkfs. (FatFs) + Fixed a problem corresponds to FAT32 support. (Tiny-FatFs) + +R0.04, Feb 04, 2007 + Supported multiple drive system. (FatFs) + Changed some APIs for multiple drive system. + Added f_mkfs. (FatFs) + Added _USE_FAT32 option. (Tiny-FatFs) + +R0.03a, Dec 11, 2006 + Improved cluster scan algolithm to write files fast. + Fixed f_mkdir creates incorrect directory on FAT32. + +R0.03, Sep 22, 2006 + Added f_rename. + Changed option _FS_MINIMUM to _FS_MINIMIZE. + +R0.02a, Jun 10, 2006 + Added a configuration option _FS_MINIMUM. + +R0.02, Jun 01, 2006 + Added FAT12. + Removed unbuffered mode. + Fixed a problem on small (<32M) patition. + +R0.01, Apr 29, 2006 + First release + +R0.00, Feb 26, 2006 + Prototype (not released) + diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/src/00readme.txt b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/src/00readme.txt new file mode 100644 index 000000000..cfcdd4a24 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/src/00readme.txt @@ -0,0 +1,130 @@ +FatFs Module Source Files R0.09 (C)ChaN, 2011 + + +FILES + + ffconf.h Configuration file for FatFs module. + ff.h Common include file for FatFs and application module. + ff.c FatFs module. + diskio.h Common include file for FatFs and disk I/O module. + integer.h Alternative type definitions for integer variables. + option Optional external functions. + + Low level disk I/O module is not included in this archive because the FatFs + module is only a generic file system layer and not depend on any specific + storage device. You have to provide a low level disk I/O module that written + to control your storage device. + + + +AGREEMENTS + + FatFs module is an open source software to implement FAT file system to + small embedded systems. This is a free software and is opened for education, + research and commercial developments under license policy of following trems. + + Copyright (C) 2011, ChaN, all right reserved. + + * The FatFs module is a free software and there is NO WARRANTY. + * No restriction on use. You can use, modify and redistribute it for + personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY. + * Redistributions of source code must retain the above copyright notice. + + + +REVISION HISTORY + + Feb 26, 2006 R0.00 Prototype + + Apr 29, 2006 R0.01 First release. + + Jun 01, 2006 R0.02 Added FAT12. + Removed unbuffered mode. + Fixed a problem on small (<32M) patition. + + Jun 10, 2006 R0.02a Added a configuration option _FS_MINIMUM. + + Sep 22, 2006 R0.03 Added f_rename. + Changed option _FS_MINIMUM to _FS_MINIMIZE. + + Dec 11, 2006 R0.03a Improved cluster scan algolithm to write files fast. + Fixed f_mkdir creates incorrect directory on FAT32. + + Feb 04, 2007 R0.04 Supported multiple drive system. (FatFs) + Changed some APIs for multiple drive system. + Added f_mkfs. (FatFs) + Added _USE_FAT32 option. (Tiny-FatFs) + + Apr 01, 2007 R0.04a Supported multiple partitions on a plysical drive. (FatFs) + Fixed an endian sensitive code in f_mkfs. (FatFs) + Added a capability of extending the file size to f_lseek. + Added minimization level 3. + Fixed a problem that can collapse a sector when recreate an + existing file in any sub-directory at non FAT32 cfg. (Tiny-FatFs) + + May 05, 2007 R0.04b Added _USE_NTFLAG option. + Added FSInfo support. + Fixed some problems corresponds to FAT32. (Tiny-FatFs) + Fixed DBCS name can result FR_INVALID_NAME. + Fixed short seek (0 < ofs <= csize) collapses the file object. + + Aug 25, 2007 R0.05 Changed arguments of f_read, f_write. + Changed arguments of f_mkfs. (FatFs) + Fixed f_mkfs on FAT32 creates incorrect FSInfo. (FatFs) + Fixed f_mkdir on FAT32 creates incorrect directory. (FatFs) + + Feb 03, 2008 R0.05a Added f_truncate(). + Added f_utime(). + Fixed off by one error at FAT sub-type determination. + Fixed btr in f_read() can be mistruncated. + Fixed cached sector is not flushed when create and close without write. + + Apr 01, 2008 R0.06 Added f_forward(). (Tiny-FatFs) + Added string functions: fputc(), fputs(), fprintf() and fgets(). + Improved performance of f_lseek() on move to the same or following cluster. + + Apr 01, 2009, R0.07 Merged Tiny-FatFs as a buffer configuration option. + Added long file name support. + Added multiple code page support. + Added re-entrancy for multitask operation. + Added auto cluster size selection to f_mkfs(). + Added rewind option to f_readdir(). + Changed result code of critical errors. + Renamed string functions to avoid name collision. + + Apr 14, 2009, R0.07a Separated out OS dependent code on reentrant cfg. + Added multiple sector size support. + + Jun 21, 2009, R0.07c Fixed f_unlink() may return FR_OK on error. + Fixed wrong cache control in f_lseek(). + Added relative path feature. + Added f_chdir(). + Added f_chdrive(). + Added proper case conversion for extended characters. + + Nov 03, 2009 R0.07e Separated out configuration options from ff.h to ffconf.h. + Added a configuration option, _LFN_UNICODE. + Fixed f_unlink() fails to remove a sub-dir on _FS_RPATH. + Fixed name matching error on the 13 char boundary. + Changed f_readdir() to return the SFN with always upper case on non-LFN cfg. + + May 15, 2010, R0.08 Added a memory configuration option. (_USE_LFN) + Added file lock feature. (_FS_SHARE) + Added fast seek feature. (_USE_FASTSEEK) + Changed some types on the API, XCHAR->TCHAR. + Changed fname member in the FILINFO structure on Unicode cfg. + String functions support UTF-8 encoding files on Unicode cfg. + + Aug 16,'10 R0.08a Added f_getcwd(). (_FS_RPATH = 2) + Added sector erase feature. (_USE_ERASE) + Moved file lock semaphore table from fs object to the bss. + Fixed a wrong directory entry is created on non-LFN cfg when the given name contains ';'. + Fixed f_mkfs() creates wrong FAT32 volume. + + Jan 15,'11 R0.08b Fast seek feature is also applied to f_read() and f_write(). + f_lseek() reports required table size on creating CLMP. + Extended format syntax of f_printf function. + Ignores duplicated directory separators in given path names. + + Sep 06,'11 R0.09 f_mkfs() supports multiple partition to finish the multiple partition feature. + Added f_fdisk(). (_MULTI_PARTITION = 2) diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/src/diskio.h b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/src/diskio.h new file mode 100644 index 000000000..9573e6ecc --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/src/diskio.h @@ -0,0 +1,78 @@ +/*----------------------------------------------------------------------- +/ Low level disk interface modlue include file +/-----------------------------------------------------------------------*/ + +#ifndef _DISKIO + +#define _READONLY 0 /* 1: Remove write functions */ +#define _USE_IOCTL 1 /* 1: Use disk_ioctl fucntion */ + +#include "integer.h" + + +/* Status of Disk Functions */ +typedef BYTE DSTATUS; + +/* Results of Disk Functions */ +typedef enum { + RES_OK = 0, /* 0: Successful */ + RES_ERROR, /* 1: R/W Error */ + RES_WRPRT, /* 2: Write Protected */ + RES_NOTRDY, /* 3: Not Ready */ + RES_PARERR /* 4: Invalid Parameter */ +} DRESULT; + + +/*---------------------------------------*/ +/* Prototypes for disk control functions */ + +int assign_drives (int, int); +DSTATUS disk_initialize (BYTE); +DSTATUS disk_status (BYTE); +DRESULT disk_read (BYTE, BYTE*, DWORD, BYTE); +#if _READONLY == 0 +DRESULT disk_write (BYTE, const BYTE*, DWORD, BYTE); +#endif +DRESULT disk_ioctl (BYTE, BYTE, void*); + + + +/* Disk Status Bits (DSTATUS) */ + +#define STA_NOINIT 0x01 /* Drive not initialized */ +#define STA_NODISK 0x02 /* No medium in the drive */ +#define STA_PROTECT 0x04 /* Write protected */ + + +/* Command code for disk_ioctrl fucntion */ + +/* Generic command (defined for FatFs) */ +#define CTRL_SYNC 0 /* Flush disk cache (for write functions) */ +#define GET_SECTOR_COUNT 1 /* Get media size (for only f_mkfs()) */ +#define GET_SECTOR_SIZE 2 /* Get sector size (for multiple sector size (_MAX_SS >= 1024)) */ +#define GET_BLOCK_SIZE 3 /* Get erase block size (for only f_mkfs()) */ +#define CTRL_ERASE_SECTOR 4 /* Force erased a block of sectors (for only _USE_ERASE) */ + +/* Generic command */ +#define CTRL_POWER 5 /* Get/Set power status */ +#define CTRL_LOCK 6 /* Lock/Unlock media removal */ +#define CTRL_EJECT 7 /* Eject media */ + +/* MMC/SDC specific ioctl command */ +#define MMC_GET_TYPE 10 /* Get card type */ +#define MMC_GET_CSD 11 /* Get CSD */ +#define MMC_GET_CID 12 /* Get CID */ +#define MMC_GET_OCR 13 /* Get OCR */ +#define MMC_GET_SDSTAT 14 /* Get SD status */ + +/* ATA/CF specific ioctl command */ +#define ATA_GET_REV 20 /* Get F/W revision */ +#define ATA_GET_MODEL 21 /* Get model name */ +#define ATA_GET_SN 22 /* Get serial number */ + +/* NAND specific ioctl command */ +#define NAND_FORMAT 30 /* Create physical format */ + + +#define _DISKIO +#endif diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/src/ff.c b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/src/ff.c new file mode 100644 index 000000000..1a972eaca --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/src/ff.c @@ -0,0 +1,4098 @@ +/*----------------------------------------------------------------------------/ +/ FatFs - FAT file system module R0.09 (C)ChaN, 2011 +/-----------------------------------------------------------------------------/ +/ FatFs module is a generic FAT file system module for small embedded systems. +/ This is a free software that opened for education, research and commercial +/ developments under license policy of following terms. +/ +/ Copyright (C) 2011, ChaN, all right reserved. +/ +/ * The FatFs module is a free software and there is NO WARRANTY. +/ * No restriction on use. You can use, modify and redistribute it for +/ personal, non-profit or commercial products UNDER YOUR RESPONSIBILITY. +/ * Redistributions of source code must retain the above copyright notice. +/ +/-----------------------------------------------------------------------------/ +/ Feb 26,'06 R0.00 Prototype. +/ +/ Apr 29,'06 R0.01 First stable version. +/ +/ Jun 01,'06 R0.02 Added FAT12 support. +/ Removed unbuffered mode. +/ Fixed a problem on small (<32M) partition. +/ Jun 10,'06 R0.02a Added a configuration option (_FS_MINIMUM). +/ +/ Sep 22,'06 R0.03 Added f_rename(). +/ Changed option _FS_MINIMUM to _FS_MINIMIZE. +/ Dec 11,'06 R0.03a Improved cluster scan algorithm to write files fast. +/ Fixed f_mkdir() creates incorrect directory on FAT32. +/ +/ Feb 04,'07 R0.04 Supported multiple drive system. +/ Changed some interfaces for multiple drive system. +/ Changed f_mountdrv() to f_mount(). +/ Added f_mkfs(). +/ Apr 01,'07 R0.04a Supported multiple partitions on a physical drive. +/ Added a capability of extending file size to f_lseek(). +/ Added minimization level 3. +/ Fixed an endian sensitive code in f_mkfs(). +/ May 05,'07 R0.04b Added a configuration option _USE_NTFLAG. +/ Added FSInfo support. +/ Fixed DBCS name can result FR_INVALID_NAME. +/ Fixed short seek (<= csize) collapses the file object. +/ +/ Aug 25,'07 R0.05 Changed arguments of f_read(), f_write() and f_mkfs(). +/ Fixed f_mkfs() on FAT32 creates incorrect FSInfo. +/ Fixed f_mkdir() on FAT32 creates incorrect directory. +/ Feb 03,'08 R0.05a Added f_truncate() and f_utime(). +/ Fixed off by one error at FAT sub-type determination. +/ Fixed btr in f_read() can be mistruncated. +/ Fixed cached sector is not flushed when create and close without write. +/ +/ Apr 01,'08 R0.06 Added fputc(), fputs(), fprintf() and fgets(). +/ Improved performance of f_lseek() on moving to the same or following cluster. +/ +/ Apr 01,'09 R0.07 Merged Tiny-FatFs as a configuration option. (_FS_TINY) +/ Added long file name feature. +/ Added multiple code page feature. +/ Added re-entrancy for multitask operation. +/ Added auto cluster size selection to f_mkfs(). +/ Added rewind option to f_readdir(). +/ Changed result code of critical errors. +/ Renamed string functions to avoid name collision. +/ Apr 14,'09 R0.07a Separated out OS dependent code on reentrant cfg. +/ Added multiple sector size feature. +/ Jun 21,'09 R0.07c Fixed f_unlink() can return FR_OK on error. +/ Fixed wrong cache control in f_lseek(). +/ Added relative path feature. +/ Added f_chdir() and f_chdrive(). +/ Added proper case conversion to extended char. +/ Nov 03,'09 R0.07e Separated out configuration options from ff.h to ffconf.h. +/ Fixed f_unlink() fails to remove a sub-dir on _FS_RPATH. +/ Fixed name matching error on the 13 char boundary. +/ Added a configuration option, _LFN_UNICODE. +/ Changed f_readdir() to return the SFN with always upper case on non-LFN cfg. +/ +/ May 15,'10 R0.08 Added a memory configuration option. (_USE_LFN = 3) +/ Added file lock feature. (_FS_SHARE) +/ Added fast seek feature. (_USE_FASTSEEK) +/ Changed some types on the API, XCHAR->TCHAR. +/ Changed fname member in the FILINFO structure on Unicode cfg. +/ String functions support UTF-8 encoding files on Unicode cfg. +/ Aug 16,'10 R0.08a Added f_getcwd(). (_FS_RPATH = 2) +/ Added sector erase feature. (_USE_ERASE) +/ Moved file lock semaphore table from fs object to the bss. +/ Fixed a wrong directory entry is created on non-LFN cfg when the given name contains ';'. +/ Fixed f_mkfs() creates wrong FAT32 volume. +/ Jan 15,'11 R0.08b Fast seek feature is also applied to f_read() and f_write(). +/ f_lseek() reports required table size on creating CLMP. +/ Extended format syntax of f_printf function. +/ Ignores duplicated directory separators in given path names. +/ +/ Sep 06,'11 R0.09 f_mkfs() supports multiple partition to finish the multiple partition feature. +/ Added f_fdisk(). (_MULTI_PARTITION = 2) +/---------------------------------------------------------------------------*/ + +#include "ff.h" /* FatFs configurations and declarations */ +#include "diskio.h" /* Declarations of low level disk I/O functions */ + +/** + * \defgroup thirdparty_fatfs_group FatFS file system service + * + * Service of FatFS file system. This service provides a generic FAT file + * system module for the ASF systems. + * + * @{ + */ + +/*-------------------------------------------------------------------------- + + Module Private Definitions + +---------------------------------------------------------------------------*/ + +#if _FATFS != 6502 /* Revision ID */ +#error Wrong include file (ff.h). +#endif + + +/* Definitions on sector size */ +#if _MAX_SS != 512 && _MAX_SS != 1024 && _MAX_SS != 2048 && _MAX_SS != 4096 +#error Wrong sector size. +#endif +#if _MAX_SS != 512 +#define SS(fs) ((fs)->ssize) /* Variable sector size */ +#else +#define SS(fs) 512U /* Fixed sector size */ +#endif + + +/* Reentrancy related */ +#if _FS_REENTRANT +#if _USE_LFN == 1 +#error Static LFN work area must not be used in re-entrant configuration. +#endif +#define ENTER_FF(fs) { if (!lock_fs(fs)) return FR_TIMEOUT; } +#define LEAVE_FF(fs, res) { unlock_fs(fs, res); return res; } +#else +#define ENTER_FF(fs) +#define LEAVE_FF(fs, res) return res +#endif + +#define ABORT(fs, res) { fp->flag |= FA__ERROR; LEAVE_FF(fs, res); } + + +/* File shareing feature */ +#if _FS_SHARE +#if _FS_READONLY +#error _FS_SHARE must be 0 on read-only cfg. +#endif +typedef struct { + FATFS *fs; /* File ID 1, volume (NULL:blank entry) */ + DWORD clu; /* File ID 2, directory */ + WORD idx; /* File ID 3, directory index */ + WORD ctr; /* File open counter, 0:none, 0x01..0xFF:read open count, 0x100:write mode */ +} FILESEM; +#endif + + +/* Misc definitions */ +#define LD_CLUST(dir) (((DWORD)LD_WORD(dir+DIR_FstClusHI)<<16) | LD_WORD(dir+DIR_FstClusLO)) +#define ST_CLUST(dir,cl) {ST_WORD(dir+DIR_FstClusLO, cl); ST_WORD(dir+DIR_FstClusHI, (DWORD)cl>>16);} + + +/* DBCS code ranges and SBCS extend char conversion table */ + +#if _CODE_PAGE == 932 /* Japanese Shift-JIS */ +#define _DF1S 0x81 /* DBC 1st byte range 1 start */ +#define _DF1E 0x9F /* DBC 1st byte range 1 end */ +#define _DF2S 0xE0 /* DBC 1st byte range 2 start */ +#define _DF2E 0xFC /* DBC 1st byte range 2 end */ +#define _DS1S 0x40 /* DBC 2nd byte range 1 start */ +#define _DS1E 0x7E /* DBC 2nd byte range 1 end */ +#define _DS2S 0x80 /* DBC 2nd byte range 2 start */ +#define _DS2E 0xFC /* DBC 2nd byte range 2 end */ + +#elif _CODE_PAGE == 936 /* Simplified Chinese GBK */ +#define _DF1S 0x81 +#define _DF1E 0xFE +#define _DS1S 0x40 +#define _DS1E 0x7E +#define _DS2S 0x80 +#define _DS2E 0xFE + +#elif _CODE_PAGE == 949 /* Korean */ +#define _DF1S 0x81 +#define _DF1E 0xFE +#define _DS1S 0x41 +#define _DS1E 0x5A +#define _DS2S 0x61 +#define _DS2E 0x7A +#define _DS3S 0x81 +#define _DS3E 0xFE + +#elif _CODE_PAGE == 950 /* Traditional Chinese Big5 */ +#define _DF1S 0x81 +#define _DF1E 0xFE +#define _DS1S 0x40 +#define _DS1E 0x7E +#define _DS2S 0xA1 +#define _DS2E 0xFE + +#elif _CODE_PAGE == 437 /* U.S. (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F,0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 720 /* Arabic (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x45,0x41,0x84,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x49,0x49,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 737 /* Greek (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \ + 0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xE7,0xE8,0xF1,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 775 /* Baltic (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 850 /* Multilingual Latin 1 (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ + 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 852 /* Latin 2 (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F,0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0x9F, \ + 0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF} + +#elif _CODE_PAGE == 855 /* Cyrillic (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F,0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \ + 0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \ + 0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 857 /* Turkish (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x98,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \ + 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0x59,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 858 /* Multilingual Latin 1 + Euro (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ + 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 862 /* Hebrew (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 866 /* Russian (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0x90,0x91,0x92,0x93,0x9d,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F,0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 874 /* Thai (OEM, Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 1250 /* Central Europe (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xA3,0xB4,0xB5,0xB6,0xB7,0xB8,0xA5,0xAA,0xBB,0xBC,0xBD,0xBC,0xAF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF} + +#elif _CODE_PAGE == 1251 /* Cyrillic (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x82,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x80,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \ + 0xA0,0xA2,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB2,0xA5,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xA3,0xBD,0xBD,0xAF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF} + +#elif _CODE_PAGE == 1252 /* Latin 1 (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0xAd,0x9B,0x8C,0x9D,0xAE,0x9F, \ + 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F} + +#elif _CODE_PAGE == 1253 /* Greek (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xA2,0xB8,0xB9,0xBA, \ + 0xE0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xFB,0xBC,0xFD,0xBF,0xFF} + +#elif _CODE_PAGE == 1254 /* Turkish (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x9D,0x9E,0x9F, \ + 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F} + +#elif _CODE_PAGE == 1255 /* Hebrew (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 1256 /* Arabic (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x8C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0x41,0xE1,0x41,0xE3,0xE4,0xE5,0xE6,0x43,0x45,0x45,0x45,0x45,0xEC,0xED,0x49,0x49,0xF0,0xF1,0xF2,0xF3,0x4F,0xF5,0xF6,0xF7,0xF8,0x55,0xFA,0x55,0x55,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 1257 /* Baltic (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xBC,0xBD,0xBE,0xAF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF} + +#elif _CODE_PAGE == 1258 /* Vietnam (OEM, Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0xAC,0x9D,0x9E,0x9F, \ + 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xEC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xFE,0x9F} + +#elif _CODE_PAGE == 1 /* ASCII (for only non-LFN cfg) */ +#if _USE_LFN +#error Cannot use LFN feature without valid code page. +#endif +#define _DF1S 0 + +#else +#error Unknown code page + +#endif + + +/* Character code support macros */ +#define IsUpper(c) (((c)>='A')&&((c)<='Z')) +#define IsLower(c) (((c)>='a')&&((c)<='z')) +#define IsDigit(c) (((c)>='0')&&((c)<='9')) + +#if _DF1S /* Code page is DBCS */ + +#ifdef _DF2S /* Two 1st byte areas */ +#define IsDBCS1(c) (((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) || ((BYTE)(c) >= _DF2S && (BYTE)(c) <= _DF2E)) +#else /* One 1st byte area */ +#define IsDBCS1(c) ((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) +#endif + +#ifdef _DS3S /* Three 2nd byte areas */ +#define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E) || ((BYTE)(c) >= _DS3S && (BYTE)(c) <= _DS3E)) +#else /* Two 2nd byte areas */ +#define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E)) +#endif + +#else /* Code page is SBCS */ + +#define IsDBCS1(c) 0 +#define IsDBCS2(c) 0 + +#endif /* _DF1S */ + + +/* Name status flags */ +#define NS 11 /* Index of name status byte in fn[] */ +#define NS_LOSS 0x01 /* Out of 8.3 format */ +#define NS_LFN 0x02 /* Force to create LFN entry */ +#define NS_LAST 0x04 /* Last segment */ +#define NS_BODY 0x08 /* Lower case flag (body) */ +#define NS_EXT 0x10 /* Lower case flag (ext) */ +#define NS_DOT 0x20 /* Dot entry */ + + +/* FAT sub-type boundaries */ +/* Note that the FAT spec by Microsoft says 4085 but Windows works with 4087! */ +#define MIN_FAT16 4086 /* Minimum number of clusters for FAT16 */ +#define MIN_FAT32 65526 /* Minimum number of clusters for FAT32 */ + + +/* FatFs refers the members in the FAT structures as byte array instead of +/ structure member because the structure is not binary compatible between +/ different platforms */ + +#define BS_jmpBoot 0 /* Jump instruction (3) */ +#define BS_OEMName 3 /* OEM name (8) */ +#define BPB_BytsPerSec 11 /* Sector size [byte] (2) */ +#define BPB_SecPerClus 13 /* Cluster size [sector] (1) */ +#define BPB_RsvdSecCnt 14 /* Size of reserved area [sector] (2) */ +#define BPB_NumFATs 16 /* Number of FAT copies (1) */ +#define BPB_RootEntCnt 17 /* Number of root dir entries for FAT12/16 (2) */ +#define BPB_TotSec16 19 /* Volume size [sector] (2) */ +#define BPB_Media 21 /* Media descriptor (1) */ +#define BPB_FATSz16 22 /* FAT size [sector] (2) */ +#define BPB_SecPerTrk 24 /* Track size [sector] (2) */ +#define BPB_NumHeads 26 /* Number of heads (2) */ +#define BPB_HiddSec 28 /* Number of special hidden sectors (4) */ +#define BPB_TotSec32 32 /* Volume size [sector] (4) */ +#define BS_DrvNum 36 /* Physical drive number (2) */ +#define BS_BootSig 38 /* Extended boot signature (1) */ +#define BS_VolID 39 /* Volume serial number (4) */ +#define BS_VolLab 43 /* Volume label (8) */ +#define BS_FilSysType 54 /* File system type (1) */ +#define BPB_FATSz32 36 /* FAT size [sector] (4) */ +#define BPB_ExtFlags 40 /* Extended flags (2) */ +#define BPB_FSVer 42 /* File system version (2) */ +#define BPB_RootClus 44 /* Root dir first cluster (4) */ +#define BPB_FSInfo 48 /* Offset of FSInfo sector (2) */ +#define BPB_BkBootSec 50 /* Offset of backup boot sectot (2) */ +#define BS_DrvNum32 64 /* Physical drive number (2) */ +#define BS_BootSig32 66 /* Extended boot signature (1) */ +#define BS_VolID32 67 /* Volume serial number (4) */ +#define BS_VolLab32 71 /* Volume label (8) */ +#define BS_FilSysType32 82 /* File system type (1) */ +#define FSI_LeadSig 0 /* FSI: Leading signature (4) */ +#define FSI_StrucSig 484 /* FSI: Structure signature (4) */ +#define FSI_Free_Count 488 /* FSI: Number of free clusters (4) */ +#define FSI_Nxt_Free 492 /* FSI: Last allocated cluster (4) */ +#define MBR_Table 446 /* MBR: Partition table offset (2) */ +#define SZ_PTE 16 /* MBR: Size of a partition table entry */ +#define BS_55AA 510 /* Boot sector signature (2) */ + +#define DIR_Name 0 /* Short file name (11) */ +#define DIR_Attr 11 /* Attribute (1) */ +#define DIR_NTres 12 /* NT flag (1) */ +#define DIR_CrtTime 14 /* Created time (2) */ +#define DIR_CrtDate 16 /* Created date (2) */ +#define DIR_FstClusHI 20 /* Higher 16-bit of first cluster (2) */ +#define DIR_WrtTime 22 /* Modified time (2) */ +#define DIR_WrtDate 24 /* Modified date (2) */ +#define DIR_FstClusLO 26 /* Lower 16-bit of first cluster (2) */ +#define DIR_FileSize 28 /* File size (4) */ +#define LDIR_Ord 0 /* LFN entry order and LLE flag (1) */ +#define LDIR_Attr 11 /* LFN attribute (1) */ +#define LDIR_Type 12 /* LFN type (1) */ +#define LDIR_Chksum 13 /* Sum of corresponding SFN entry */ +#define LDIR_FstClusLO 26 /* Filled by zero (0) */ +#define SZ_DIR 32 /* Size of a directory entry */ +#define LLE 0x40 /* Last long entry flag in LDIR_Ord */ +#define DDE 0xE5 /* Deleted directory enrty mark in DIR_Name[0] */ +#define NDDE 0x05 /* Replacement of a character collides with DDE */ + + +/*------------------------------------------------------------*/ +/* Module private work area */ +/*------------------------------------------------------------*/ +/* Note that uninitialized variables with static duration are +/ zeroed/nulled at start-up. If not, the compiler or start-up +/ routine is out of ANSI-C standard. +*/ + +#if _VOLUMES +static +FATFS *FatFs[_VOLUMES]; /* Pointer to the file system objects (logical drives) */ +#else +#error Number of volumes must not be 0. +#endif + +static +WORD Fsid; /* File system mount ID */ + +#if _FS_RPATH +static +BYTE CurrVol; /* Current drive */ +#endif + +#if _FS_SHARE +static +FILESEM Files[_FS_SHARE]; /* File lock semaphores */ +#endif + +#if _USE_LFN == 0 /* No LFN feature */ +#define DEF_NAMEBUF BYTE sfn[12] +#define INIT_BUF(dobj) (dobj).fn = sfn +#define FREE_BUF() + +#elif _USE_LFN == 1 /* LFN feature with static working buffer */ +static WCHAR LfnBuf[_MAX_LFN+1]; +#define DEF_NAMEBUF BYTE sfn[12] +#define INIT_BUF(dobj) { (dobj).fn = sfn; (dobj).lfn = LfnBuf; } +#define FREE_BUF() + +#elif _USE_LFN == 2 /* LFN feature with dynamic working buffer on the stack */ +#define DEF_NAMEBUF BYTE sfn[12]; WCHAR lbuf[_MAX_LFN+1] +#define INIT_BUF(dobj) { (dobj).fn = sfn; (dobj).lfn = lbuf; } +#define FREE_BUF() + +#elif _USE_LFN == 3 /* LFN feature with dynamic working buffer on the heap */ +#define DEF_NAMEBUF BYTE sfn[12]; WCHAR *lfn +#define INIT_BUF(dobj) { lfn = ff_memalloc((_MAX_LFN + 1) * 2); \ + if (!lfn) LEAVE_FF((dobj).fs, FR_NOT_ENOUGH_CORE); \ + (dobj).lfn = lfn; (dobj).fn = sfn; } +#define FREE_BUF() ff_memfree(lfn) + +#else +#error Wrong LFN configuration. +#endif + + + + +/*-------------------------------------------------------------------------- + + Module Private Functions + +---------------------------------------------------------------------------*/ + + +/*-----------------------------------------------------------------------*/ +/* String functions */ +/*-----------------------------------------------------------------------*/ + +/* Copy memory to memory */ +static +void mem_cpy (void* dst, const void* src, UINT cnt) { + BYTE *d = (BYTE*)dst; + const BYTE *s = (const BYTE*)src; + +#if _WORD_ACCESS == 1 + while (cnt >= sizeof(int)) { + *(int*)d = *(int*)s; + d += sizeof(int); s += sizeof(int); + cnt -= sizeof(int); + } +#endif + while (cnt--) + *d++ = *s++; +} + +/* Fill memory */ +static +void mem_set (void* dst, int val, UINT cnt) { + BYTE *d = (BYTE*)dst; + + while (cnt--) + *d++ = (BYTE)val; +} + +/* Compare memory to memory */ +static +int mem_cmp (const void* dst, const void* src, UINT cnt) { + const BYTE *d = (const BYTE *)dst, *s = (const BYTE *)src; + int r = 0; + + while (cnt-- && (r = *d++ - *s++) == 0) ; + return r; +} + +/* Check if chr is contained in the string */ +static +int chk_chr (const char* str, int chr) { + while (*str && *str != chr) str++; + return *str; +} + + + +/*-----------------------------------------------------------------------*/ +/* Request/Release grant to access the volume */ +/*-----------------------------------------------------------------------*/ +#if _FS_REENTRANT + +static +int lock_fs ( + FATFS *fs /* File system object */ +) +{ + return ff_req_grant(fs->sobj); +} + + +static +void unlock_fs ( + FATFS *fs, /* File system object */ + FRESULT res /* Result code to be returned */ +) +{ + if (res != FR_NOT_ENABLED && + res != FR_INVALID_DRIVE && + res != FR_INVALID_OBJECT && + res != FR_TIMEOUT) { + ff_rel_grant(fs->sobj); + } +} +#endif + + + +/*-----------------------------------------------------------------------*/ +/* File shareing control functions */ +/*-----------------------------------------------------------------------*/ +#if _FS_SHARE + +static +FRESULT chk_lock ( /* Check if the file can be accessed */ + DIR* dj, /* Directory object pointing the file to be checked */ + int acc /* Desired access (0:Read, 1:Write, 2:Delete/Rename) */ +) +{ + UINT i, be; + + /* Search file semaphore table */ + for (i = be = 0; i < _FS_SHARE; i++) { + if (Files[i].fs) { /* Existing entry */ + if (Files[i].fs == dj->fs && /* Check if the file matched with an open file */ + Files[i].clu == dj->sclust && + Files[i].idx == dj->index) break; + } else { /* Blank entry */ + be++; + } + } + if (i == _FS_SHARE) /* The file is not opened */ + return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES; /* Is there a blank entry for new file? */ + + /* The file has been opened. Reject any open against writing file and all write mode open */ + return (acc || Files[i].ctr == 0x100) ? FR_LOCKED : FR_OK; +} + + +static +int enq_lock (void) /* Check if an entry is available for a new file */ +{ + UINT i; + + for (i = 0; i < _FS_SHARE && Files[i].fs; i++) ; + return (i == _FS_SHARE) ? 0 : 1; +} + + +static +UINT inc_lock ( /* Increment file open counter and returns its index (0:int error) */ + DIR* dj, /* Directory object pointing the file to register or increment */ + int acc /* Desired access mode (0:Read, !0:Write) */ +) +{ + UINT i; + + + for (i = 0; i < _FS_SHARE; i++) { /* Find the file */ + if (Files[i].fs == dj->fs && + Files[i].clu == dj->sclust && + Files[i].idx == dj->index) break; + } + + if (i == _FS_SHARE) { /* Not opened. Register it as new. */ + for (i = 0; i < _FS_SHARE && Files[i].fs; i++) ; + if (i == _FS_SHARE) return 0; /* No space to register (int err) */ + Files[i].fs = dj->fs; + Files[i].clu = dj->sclust; + Files[i].idx = dj->index; + Files[i].ctr = 0; + } + + if (acc && Files[i].ctr) return 0; /* Access violation (int err) */ + + Files[i].ctr = acc ? 0x100 : Files[i].ctr + 1; /* Set semaphore value */ + + return i + 1; +} + + +static +FRESULT dec_lock ( /* Decrement file open counter */ + UINT i /* Semaphore index */ +) +{ + WORD n; + FRESULT res; + + + if (--i < _FS_SHARE) { + n = Files[i].ctr; + if (n == 0x100) n = 0; + if (n) n--; + Files[i].ctr = n; + if (!n) Files[i].fs = 0; + res = FR_OK; + } else { + res = FR_INT_ERR; + } + return res; +} + + +static +void clear_lock ( /* Clear lock entries of the volume */ + FATFS *fs +) +{ + UINT i; + + for (i = 0; i < _FS_SHARE; i++) { + if (Files[i].fs == fs) Files[i].fs = 0; + } +} +#endif + + + +/*-----------------------------------------------------------------------*/ +/* Change window offset */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT move_window ( + FATFS *fs, /* File system object */ + DWORD sector /* Sector number to make appearance in the fs->win[] */ +) /* Move to zero only writes back dirty window */ +{ + DWORD wsect; + + + wsect = fs->winsect; + if (wsect != sector) { /* Changed current window */ +#if !_FS_READONLY + if (fs->wflag) { /* Write back dirty window if needed */ + if (disk_write(fs->drv, fs->win, wsect, 1) != RES_OK) + return FR_DISK_ERR; + fs->wflag = 0; + if (wsect < (fs->fatbase + fs->fsize)) { /* In FAT area */ + BYTE nf; + for (nf = fs->n_fats; nf > 1; nf--) { /* Reflect the change to all FAT copies */ + wsect += fs->fsize; + disk_write(fs->drv, fs->win, wsect, 1); + } + } + } +#endif + if (sector) { + if (disk_read(fs->drv, fs->win, sector, 1) != RES_OK) + return FR_DISK_ERR; + fs->winsect = sector; + } + } + + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Clean-up cached data */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY +static +FRESULT sync ( /* FR_OK: successful, FR_DISK_ERR: failed */ + FATFS *fs /* File system object */ +) +{ + FRESULT res; + + + res = move_window(fs, 0); + if (res == FR_OK) { + /* Update FSInfo sector if needed */ + if (fs->fs_type == FS_FAT32 && fs->fsi_flag) { + fs->winsect = 0; + /* Create FSInfo structure */ + mem_set(fs->win, 0, 512); + ST_WORD(fs->win+BS_55AA, 0xAA55); + ST_DWORD(fs->win+FSI_LeadSig, 0x41615252); + ST_DWORD(fs->win+FSI_StrucSig, 0x61417272); + ST_DWORD(fs->win+FSI_Free_Count, fs->free_clust); + ST_DWORD(fs->win+FSI_Nxt_Free, fs->last_clust); + /* Write it into the FSInfo sector */ + disk_write(fs->drv, fs->win, fs->fsi_sector, 1); + fs->fsi_flag = 0; + } + /* Make sure that no pending write process in the physical drive */ + if (disk_ioctl(fs->drv, CTRL_SYNC, 0) != RES_OK) + res = FR_DISK_ERR; + } + + return res; +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* Get sector# from cluster# */ +/*-----------------------------------------------------------------------*/ + + +static DWORD clust2sect ( /* !=0: Sector number, 0: Failed - invalid cluster# */ + FATFS *fs, /* File system object */ + DWORD clst /* Cluster# to be converted */ +) +{ + clst -= 2; + if (clst >= (fs->n_fatent - 2)) return 0; /* Invalid cluster# */ + return clst * fs->csize + fs->database; +} + + + + +/*-----------------------------------------------------------------------*/ +/* FAT access - Read value of a FAT entry */ +/*-----------------------------------------------------------------------*/ + + +static DWORD get_fat ( /* 0xFFFFFFFF:Disk error, 1:Internal error, Else:Cluster status */ + FATFS *fs, /* File system object */ + DWORD clst /* Cluster# to get the link information */ +) +{ + UINT wc, bc; + BYTE *p; + + + if (clst < 2 || clst >= fs->n_fatent) /* Chack range */ + return 1; + + switch (fs->fs_type) { + case FS_FAT12 : + bc = (UINT)clst; bc += bc / 2; + if (move_window(fs, fs->fatbase + (bc / SS(fs)))) break; + wc = fs->win[bc % SS(fs)]; bc++; + if (move_window(fs, fs->fatbase + (bc / SS(fs)))) break; + wc |= fs->win[bc % SS(fs)] << 8; + return (clst & 1) ? (wc >> 4) : (wc & 0xFFF); + + case FS_FAT16 : + if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2)))) break; + p = &fs->win[clst * 2 % SS(fs)]; + return LD_WORD(p); + + case FS_FAT32 : + if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4)))) break; + p = &fs->win[clst * 4 % SS(fs)]; + return LD_DWORD(p) & 0x0FFFFFFF; + } + + return 0xFFFFFFFF; /* An error occurred at the disk I/O layer */ +} + + + + +/*-----------------------------------------------------------------------*/ +/* FAT access - Change value of a FAT entry */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY + +static FRESULT put_fat ( + FATFS *fs, /* File system object */ + DWORD clst, /* Cluster# to be changed in range of 2 to fs->n_fatent - 1 */ + DWORD val /* New value to mark the cluster */ +) +{ + UINT bc; + BYTE *p; + FRESULT res; + + + if (clst < 2 || clst >= fs->n_fatent) { /* Check range */ + res = FR_INT_ERR; + + } else { + switch (fs->fs_type) { + case FS_FAT12 : + bc = clst; bc += bc / 2; + res = move_window(fs, fs->fatbase + (bc / SS(fs))); + if (res != FR_OK) break; + p = &fs->win[bc % SS(fs)]; + *p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val; + bc++; + fs->wflag = 1; + res = move_window(fs, fs->fatbase + (bc / SS(fs))); + if (res != FR_OK) break; + p = &fs->win[bc % SS(fs)]; + *p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F)); + break; + + case FS_FAT16 : + res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))); + if (res != FR_OK) break; + p = &fs->win[clst * 2 % SS(fs)]; + ST_WORD(p, (WORD)val); + break; + + case FS_FAT32 : + res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))); + if (res != FR_OK) break; + p = &fs->win[clst * 4 % SS(fs)]; + val |= LD_DWORD(p) & 0xF0000000; + ST_DWORD(p, val); + break; + + default : + res = FR_INT_ERR; + } + fs->wflag = 1; + } + + return res; +} +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* FAT handling - Remove a cluster chain */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY +static +FRESULT remove_chain ( + FATFS *fs, /* File system object */ + DWORD clst /* Cluster# to remove a chain from */ +) +{ + FRESULT res; + DWORD nxt; +#if _USE_ERASE + DWORD scl = clst, ecl = clst, resion[2]; +#endif + + if (clst < 2 || clst >= fs->n_fatent) { /* Check range */ + res = FR_INT_ERR; + + } else { + res = FR_OK; + while (clst < fs->n_fatent) { /* Not a last link? */ + nxt = get_fat(fs, clst); /* Get cluster status */ + if (nxt == 0) break; /* Empty cluster? */ + if (nxt == 1) { res = FR_INT_ERR; break; } /* Internal error? */ + if (nxt == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } /* Disk error? */ + res = put_fat(fs, clst, 0); /* Mark the cluster "empty" */ + if (res != FR_OK) break; + if (fs->free_clust != 0xFFFFFFFF) { /* Update FSInfo */ + fs->free_clust++; + fs->fsi_flag = 1; + } +#if _USE_ERASE + if (ecl + 1 == nxt) { /* Next cluster is contiguous */ + ecl = nxt; + } else { /* End of contiguous clusters */ + resion[0] = clust2sect(fs, scl); /* Start sector */ + resion[1] = clust2sect(fs, ecl) + fs->csize - 1; /* End sector */ + disk_ioctl(fs->drv, CTRL_ERASE_SECTOR, resion); /* Erase the block */ + scl = ecl = nxt; + } +#endif + clst = nxt; /* Next cluster */ + } + } + + return res; +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* FAT handling - Stretch or Create a cluster chain */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY +static +DWORD create_chain ( /* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster# */ + FATFS *fs, /* File system object */ + DWORD clst /* Cluster# to stretch. 0 means create a new chain. */ +) +{ + DWORD cs, ncl, scl; + FRESULT res; + + + if (clst == 0) { /* Create a new chain */ + scl = fs->last_clust; /* Get suggested start point */ + if (!scl || scl >= fs->n_fatent) scl = 1; + } + else { /* Stretch the current chain */ + cs = get_fat(fs, clst); /* Check the cluster status */ + if (cs < 2) return 1; /* It is an invalid cluster */ + if (cs < fs->n_fatent) return cs; /* It is already followed by next cluster */ + scl = clst; + } + + ncl = scl; /* Start cluster */ + for (;;) { + ncl++; /* Next cluster */ + if (ncl >= fs->n_fatent) { /* Wrap around */ + ncl = 2; + if (ncl > scl) return 0; /* No free cluster */ + } + cs = get_fat(fs, ncl); /* Get the cluster status */ + if (cs == 0) break; /* Found a free cluster */ + if (cs == 0xFFFFFFFF || cs == 1)/* An error occurred */ + return cs; + if (ncl == scl) return 0; /* No free cluster */ + } + + res = put_fat(fs, ncl, 0x0FFFFFFF); /* Mark the new cluster "last link" */ + if (res == FR_OK && clst != 0) { + res = put_fat(fs, clst, ncl); /* Link it to the previous one if needed */ + } + if (res == FR_OK) { + fs->last_clust = ncl; /* Update FSINFO */ + if (fs->free_clust != 0xFFFFFFFF) { + fs->free_clust--; + fs->fsi_flag = 1; + } + } else { + ncl = (res == FR_DISK_ERR) ? 0xFFFFFFFF : 1; + } + + return ncl; /* Return new cluster number or error code */ +} +#endif /* !_FS_READONLY */ + + + +/*-----------------------------------------------------------------------*/ +/* FAT handling - Convert offset into cluster with link map table */ +/*-----------------------------------------------------------------------*/ + +#if _USE_FASTSEEK +static +DWORD clmt_clust ( /* <2:Error, >=2:Cluster number */ + FIL* fp, /* Pointer to the file object */ + DWORD ofs /* File offset to be converted to cluster# */ +) +{ + DWORD cl, ncl, *tbl; + + + tbl = fp->cltbl + 1; /* Top of CLMT */ + cl = ofs / SS(fp->fs) / fp->fs->csize; /* Cluster order from top of the file */ + for (;;) { + ncl = *tbl++; /* Number of cluters in the fragment */ + if (!ncl) return 0; /* End of table? (error) */ + if (cl < ncl) break; /* In this fragment? */ + cl -= ncl; tbl++; /* Next fragment */ + } + return cl + *tbl; /* Return the cluster number */ +} +#endif /* _USE_FASTSEEK */ + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Set directory index */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT dir_sdi ( + DIR *dj, /* Pointer to directory object */ + WORD idx /* Directory index number */ +) +{ + DWORD clst; + WORD ic; + + + dj->index = idx; + clst = dj->sclust; + if (clst == 1 || clst >= dj->fs->n_fatent) /* Check start cluster range */ + return FR_INT_ERR; + if (!clst && dj->fs->fs_type == FS_FAT32) /* Replace cluster# 0 with root cluster# if in FAT32 */ + clst = dj->fs->dirbase; + + if (clst == 0) { /* Static table (root-dir in FAT12/16) */ + dj->clust = clst; + if (idx >= dj->fs->n_rootdir) /* Index is out of range */ + return FR_INT_ERR; + dj->sect = dj->fs->dirbase + idx / (SS(dj->fs) / SZ_DIR); /* Sector# */ + } + else { /* Dynamic table (sub-dirs or root-dir in FAT32) */ + ic = SS(dj->fs) / SZ_DIR * dj->fs->csize; /* Entries per cluster */ + while (idx >= ic) { /* Follow cluster chain */ + clst = get_fat(dj->fs, clst); /* Get next cluster */ + if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ + if (clst < 2 || clst >= dj->fs->n_fatent) /* Reached to end of table or int error */ + return FR_INT_ERR; + idx -= ic; + } + dj->clust = clst; + dj->sect = clust2sect(dj->fs, clst) + idx / (SS(dj->fs) / SZ_DIR); /* Sector# */ + } + + dj->dir = dj->fs->win + (idx % (SS(dj->fs) / SZ_DIR)) * SZ_DIR; /* Ptr to the entry in the sector */ + + return FR_OK; /* Seek succeeded */ +} + + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Move directory index next */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT dir_next ( /* FR_OK:Succeeded, FR_NO_FILE:End of table, FR_DENIED:EOT and could not stretch */ + DIR *dj, /* Pointer to directory object */ + int stretch /* 0: Do not stretch table, 1: Stretch table if needed */ +) +{ + DWORD clst; + WORD i; + + + stretch = stretch; /* To suppress warning on read-only cfg. */ + i = dj->index + 1; + if (!i || !dj->sect) /* Report EOT when index has reached 65535 */ + return FR_NO_FILE; + + if (!(i % (SS(dj->fs) / SZ_DIR))) { /* Sector changed? */ + dj->sect++; /* Next sector */ + + if (dj->clust == 0) { /* Static table */ + if (i >= dj->fs->n_rootdir) /* Report EOT when end of table */ + return FR_NO_FILE; + } + else { /* Dynamic table */ + if (((i / (SS(dj->fs) / SZ_DIR)) & (dj->fs->csize - 1)) == 0) { /* Cluster changed? */ + clst = get_fat(dj->fs, dj->clust); /* Get next cluster */ + if (clst <= 1) return FR_INT_ERR; + if (clst == 0xFFFFFFFF) return FR_DISK_ERR; + if (clst >= dj->fs->n_fatent) { /* When it reached end of dynamic table */ +#if !_FS_READONLY + BYTE c; + if (!stretch) return FR_NO_FILE; /* When do not stretch, report EOT */ + clst = create_chain(dj->fs, dj->clust); /* Stretch cluster chain */ + if (clst == 0) return FR_DENIED; /* No free cluster */ + if (clst == 1) return FR_INT_ERR; + if (clst == 0xFFFFFFFF) return FR_DISK_ERR; + /* Clean-up stretched table */ + if (move_window(dj->fs, 0)) return FR_DISK_ERR; /* Flush active window */ + mem_set(dj->fs->win, 0, SS(dj->fs)); /* Clear window buffer */ + dj->fs->winsect = clust2sect(dj->fs, clst); /* Cluster start sector */ + for (c = 0; c < dj->fs->csize; c++) { /* Fill the new cluster with 0 */ + dj->fs->wflag = 1; + if (move_window(dj->fs, 0)) return FR_DISK_ERR; + dj->fs->winsect++; + } + dj->fs->winsect -= c; /* Rewind window address */ +#else + return FR_NO_FILE; /* Report EOT */ +#endif + } + dj->clust = clst; /* Initialize data for new cluster */ + dj->sect = clust2sect(dj->fs, clst); + } + } + } + + dj->index = i; + dj->dir = dj->fs->win + (i % (SS(dj->fs) / SZ_DIR)) * SZ_DIR; + + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* LFN handling - Test/Pick/Fit an LFN segment from/to directory entry */ +/*-----------------------------------------------------------------------*/ +#if _USE_LFN +static +const BYTE LfnOfs[] = {1,3,5,7,9,14,16,18,20,22,24,28,30}; /* Offset of LFN chars in the directory entry */ + + +static +int cmp_lfn ( /* 1:Matched, 0:Not matched */ + WCHAR *lfnbuf, /* Pointer to the LFN to be compared */ + BYTE *dir /* Pointer to the directory entry containing a part of LFN */ +) +{ + UINT i, s; + WCHAR wc, uc; + + + i = ((dir[LDIR_Ord] & ~LLE) - 1) * 13; /* Get offset in the LFN buffer */ + s = 0; wc = 1; + do { + uc = LD_WORD(dir+LfnOfs[s]); /* Pick an LFN character from the entry */ + if (wc) { /* Last char has not been processed */ + wc = ff_wtoupper(uc); /* Convert it to upper case */ + if (i >= _MAX_LFN || wc != ff_wtoupper(lfnbuf[i++])) /* Compare it */ + return 0; /* Not matched */ + } else { + if (uc != 0xFFFF) return 0; /* Check filler */ + } + } while (++s < 13); /* Repeat until all chars in the entry are checked */ + + if ((dir[LDIR_Ord] & LLE) && wc && lfnbuf[i]) /* Last segment matched but different length */ + return 0; + + return 1; /* The part of LFN matched */ +} + + + +static +int pick_lfn ( /* 1:Succeeded, 0:Buffer overflow */ + WCHAR *lfnbuf, /* Pointer to the Unicode-LFN buffer */ + BYTE *dir /* Pointer to the directory entry */ +) +{ + UINT i, s; + WCHAR wc, uc; + + + i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13; /* Offset in the LFN buffer */ + + s = 0; wc = 1; + do { + uc = LD_WORD(dir+LfnOfs[s]); /* Pick an LFN character from the entry */ + if (wc) { /* Last char has not been processed */ + if (i >= _MAX_LFN) return 0; /* Buffer overflow? */ + lfnbuf[i++] = wc = uc; /* Store it */ + } else { + if (uc != 0xFFFF) return 0; /* Check filler */ + } + } while (++s < 13); /* Read all character in the entry */ + + if (dir[LDIR_Ord] & LLE) { /* Put terminator if it is the last LFN part */ + if (i >= _MAX_LFN) return 0; /* Buffer overflow? */ + lfnbuf[i] = 0; + } + + return 1; +} + + +#if !_FS_READONLY +static +void fit_lfn ( + const WCHAR *lfnbuf, /* Pointer to the LFN buffer */ + BYTE *dir, /* Pointer to the directory entry */ + BYTE ord, /* LFN order (1-20) */ + BYTE sum /* SFN sum */ +) +{ + UINT i, s; + WCHAR wc; + + + dir[LDIR_Chksum] = sum; /* Set check sum */ + dir[LDIR_Attr] = AM_LFN; /* Set attribute. LFN entry */ + dir[LDIR_Type] = 0; + ST_WORD(dir+LDIR_FstClusLO, 0); + + i = (ord - 1) * 13; /* Get offset in the LFN buffer */ + s = wc = 0; + do { + if (wc != 0xFFFF) wc = lfnbuf[i++]; /* Get an effective char */ + ST_WORD(dir+LfnOfs[s], wc); /* Put it */ + if (!wc) wc = 0xFFFF; /* Padding chars following last char */ + } while (++s < 13); + if (wc == 0xFFFF || !lfnbuf[i]) ord |= LLE; /* Bottom LFN part is the start of LFN sequence */ + dir[LDIR_Ord] = ord; /* Set the LFN order */ +} + +#endif +#endif + + + +/*-----------------------------------------------------------------------*/ +/* Create numbered name */ +/*-----------------------------------------------------------------------*/ +#if _USE_LFN +static void gen_numname ( + BYTE *dst, /* Pointer to generated SFN */ + const BYTE *src, /* Pointer to source SFN to be modified */ + const WCHAR *lfn, /* Pointer to LFN */ + WORD seq /* Sequence number */ +) +{ + BYTE ns[8], c; + UINT i, j; + + + mem_cpy(dst, src, 11); + + if (seq > 5) { /* On many collisions, generate a hash number instead of sequential number */ + do seq = (seq >> 1) + (seq << 15) + (WORD)*lfn++; while (*lfn); + } + + /* itoa (hexdecimal) */ + i = 7; + do { + c = (seq % 16) + '0'; + if (c > '9') c += 7; + ns[i--] = c; + seq /= 16; + } while (seq); + ns[i] = '~'; + + /* Append the number */ + for (j = 0; j < i && dst[j] != ' '; j++) { + if (IsDBCS1(dst[j])) { + if (j == i - 1) break; + j++; + } + } + do { + dst[j++] = (i < 8) ? ns[i++] : ' '; + } while (j < 8); +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* Calculate sum of an SFN */ +/*-----------------------------------------------------------------------*/ +#if _USE_LFN +static +BYTE sum_sfn ( + const BYTE *dir /* Ptr to directory entry */ +) +{ + BYTE sum = 0; + UINT n = 11; + + do sum = (sum >> 1) + (sum << 7) + *dir++; while (--n); + return sum; +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Find an object in the directory */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT dir_find ( + DIR *dj /* Pointer to the directory object linked to the file name */ +) +{ + FRESULT res; + BYTE c, *dir; +#if _USE_LFN + BYTE a, ord, sum; +#endif + + res = dir_sdi(dj, 0); /* Rewind directory object */ + if (res != FR_OK) return res; + +#if _USE_LFN + ord = sum = 0xFF; +#endif + do { + res = move_window(dj->fs, dj->sect); + if (res != FR_OK) break; + dir = dj->dir; /* Ptr to the directory entry of current index */ + c = dir[DIR_Name]; + if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */ +#if _USE_LFN /* LFN configuration */ + a = dir[DIR_Attr] & AM_MASK; + if (c == DDE || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */ + ord = 0xFF; + } else { + if (a == AM_LFN) { /* An LFN entry is found */ + if (dj->lfn) { + if (c & LLE) { /* Is it start of LFN sequence? */ + sum = dir[LDIR_Chksum]; + c &= ~LLE; ord = c; /* LFN start order */ + dj->lfn_idx = dj->index; + } + /* Check validity of the LFN entry and compare it with given name */ + ord = (c == ord && sum == dir[LDIR_Chksum] && cmp_lfn(dj->lfn, dir)) ? ord - 1 : 0xFF; + } + } else { /* An SFN entry is found */ + if (!ord && sum == sum_sfn(dir)) break; /* LFN matched? */ + ord = 0xFF; dj->lfn_idx = 0xFFFF; /* Reset LFN sequence */ + if (!(dj->fn[NS] & NS_LOSS) && !mem_cmp(dir, dj->fn, 11)) break; /* SFN matched? */ + } + } +#else /* Non LFN configuration */ + if (!(dir[DIR_Attr] & AM_VOL) && !mem_cmp(dir, dj->fn, 11)) /* Is it a valid entry? */ + break; +#endif + res = dir_next(dj, 0); /* Next entry */ + } while (res == FR_OK); + + return res; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Read an object from the directory */ +/*-----------------------------------------------------------------------*/ +#if _FS_MINIMIZE <= 1 +static +FRESULT dir_read ( + DIR *dj /* Pointer to the directory object that pointing the entry to be read */ +) +{ + FRESULT res; + BYTE c, *dir; +#if _USE_LFN + BYTE a, ord = 0xFF, sum = 0xFF; +#endif + + res = FR_NO_FILE; + while (dj->sect) { + res = move_window(dj->fs, dj->sect); + if (res != FR_OK) break; + dir = dj->dir; /* Ptr to the directory entry of current index */ + c = dir[DIR_Name]; + if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */ +#if _USE_LFN /* LFN configuration */ + a = dir[DIR_Attr] & AM_MASK; + if (c == DDE || (!_FS_RPATH && c == '.') || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */ + ord = 0xFF; + } else { + if (a == AM_LFN) { /* An LFN entry is found */ + if (c & LLE) { /* Is it start of LFN sequence? */ + sum = dir[LDIR_Chksum]; + c &= ~LLE; ord = c; + dj->lfn_idx = dj->index; + } + /* Check LFN validity and capture it */ + ord = (c == ord && sum == dir[LDIR_Chksum] && pick_lfn(dj->lfn, dir)) ? ord - 1 : 0xFF; + } else { /* An SFN entry is found */ + if (ord || sum != sum_sfn(dir)) /* Is there a valid LFN? */ + dj->lfn_idx = 0xFFFF; /* It has no LFN. */ + break; + } + } +#else /* Non LFN configuration */ + if (c != DDE && (_FS_RPATH || c != '.') && !(dir[DIR_Attr] & AM_VOL)) /* Is it a valid entry? */ + break; +#endif + res = dir_next(dj, 0); /* Next entry */ + if (res != FR_OK) break; + } + + if (res != FR_OK) dj->sect = 0; + + return res; +} +#endif + + + +/*-----------------------------------------------------------------------*/ +/* Register an object to the directory */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY +static +FRESULT dir_register ( /* FR_OK:Successful, FR_DENIED:No free entry or too many SFN collision, FR_DISK_ERR:Disk error */ + DIR *dj /* Target directory with object name to be created */ +) +{ + FRESULT res; + BYTE c, *dir; +#if _USE_LFN /* LFN configuration */ + WORD n, ne, is; + BYTE sn[12], *fn, sum; + WCHAR *lfn; + + + fn = dj->fn; lfn = dj->lfn; + mem_cpy(sn, fn, 12); + + if (_FS_RPATH && (sn[NS] & NS_DOT)) /* Cannot create dot entry */ + return FR_INVALID_NAME; + + if (sn[NS] & NS_LOSS) { /* When LFN is out of 8.3 format, generate a numbered name */ + fn[NS] = 0; dj->lfn = 0; /* Find only SFN */ + for (n = 1; n < 100; n++) { + gen_numname(fn, sn, lfn, n); /* Generate a numbered name */ + res = dir_find(dj); /* Check if the name collides with existing SFN */ + if (res != FR_OK) break; + } + if (n == 100) return FR_DENIED; /* Abort if too many collisions */ + if (res != FR_NO_FILE) return res; /* Abort if the result is other than 'not collided' */ + fn[NS] = sn[NS]; dj->lfn = lfn; + } + + if (sn[NS] & NS_LFN) { /* When LFN is to be created, reserve an SFN + LFN entries. */ + for (ne = 0; lfn[ne]; ne++) ; + ne = (ne + 25) / 13; + } else { /* Otherwise reserve only an SFN entry. */ + ne = 1; + } + + /* Reserve contiguous entries */ + res = dir_sdi(dj, 0); + if (res != FR_OK) return res; + n = is = 0; + do { + res = move_window(dj->fs, dj->sect); + if (res != FR_OK) break; + c = *dj->dir; /* Check the entry status */ + if (c == DDE || c == 0) { /* Is it a blank entry? */ + if (n == 0) is = dj->index; /* First index of the contiguous entry */ + if (++n == ne) break; /* A contiguous entry that required count is found */ + } else { + n = 0; /* Not a blank entry. Restart to search */ + } + res = dir_next(dj, 1); /* Next entry with table stretch */ + } while (res == FR_OK); + + if (res == FR_OK && ne > 1) { /* Initialize LFN entry if needed */ + res = dir_sdi(dj, is); + if (res == FR_OK) { + sum = sum_sfn(dj->fn); /* Sum of the SFN tied to the LFN */ + ne--; + do { /* Store LFN entries in bottom first */ + res = move_window(dj->fs, dj->sect); + if (res != FR_OK) break; + fit_lfn(dj->lfn, dj->dir, (BYTE)ne, sum); + dj->fs->wflag = 1; + res = dir_next(dj, 0); /* Next entry */ + } while (res == FR_OK && --ne); + } + } + +#else /* Non LFN configuration */ + res = dir_sdi(dj, 0); + if (res == FR_OK) { + do { /* Find a blank entry for the SFN */ + res = move_window(dj->fs, dj->sect); + if (res != FR_OK) break; + c = *dj->dir; + if (c == DDE || c == 0) break; /* Is it a blank entry? */ + res = dir_next(dj, 1); /* Next entry with table stretch */ + } while (res == FR_OK); + } +#endif + + if (res == FR_OK) { /* Initialize the SFN entry */ + res = move_window(dj->fs, dj->sect); + if (res == FR_OK) { + dir = dj->dir; + mem_set(dir, 0, SZ_DIR); /* Clean the entry */ + mem_cpy(dir, dj->fn, 11); /* Put SFN */ +#if _USE_LFN + dir[DIR_NTres] = *(dj->fn+NS) & (NS_BODY | NS_EXT); /* Put NT flag */ +#endif + dj->fs->wflag = 1; + } + } + + return res; +} +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Remove an object from the directory */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY && !_FS_MINIMIZE +static +FRESULT dir_remove ( /* FR_OK: Successful, FR_DISK_ERR: A disk error */ + DIR *dj /* Directory object pointing the entry to be removed */ +) +{ + FRESULT res; +#if _USE_LFN /* LFN configuration */ + WORD i; + + i = dj->index; /* SFN index */ + res = dir_sdi(dj, (WORD)((dj->lfn_idx == 0xFFFF) ? i : dj->lfn_idx)); /* Goto the SFN or top of the LFN entries */ + if (res == FR_OK) { + do { + res = move_window(dj->fs, dj->sect); + if (res != FR_OK) break; + *dj->dir = DDE; /* Mark the entry "deleted" */ + dj->fs->wflag = 1; + if (dj->index >= i) break; /* When reached SFN, all entries of the object has been deleted. */ + res = dir_next(dj, 0); /* Next entry */ + } while (res == FR_OK); + if (res == FR_NO_FILE) res = FR_INT_ERR; + } + +#else /* Non LFN configuration */ + res = dir_sdi(dj, dj->index); + if (res == FR_OK) { + res = move_window(dj->fs, dj->sect); + if (res == FR_OK) { + *dj->dir = DDE; /* Mark the entry "deleted" */ + dj->fs->wflag = 1; + } + } +#endif + + return res; +} +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Pick a segment and create the object name in directory form */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT create_name ( + DIR *dj, /* Pointer to the directory object */ + const TCHAR **path /* Pointer to pointer to the segment in the path string */ +) +{ +#ifdef _EXCVT + static const BYTE excvt[] = _EXCVT; /* Upper conversion table for extended chars */ +#endif + +#if _USE_LFN /* LFN configuration */ + BYTE b, cf; + WCHAR w, *lfn; + UINT i, ni, si, di; + const TCHAR *p; + + /* Create LFN in Unicode */ + for (p = *path; *p == '/' || *p == '\\'; p++) ; /* Strip duplicated separator */ + lfn = dj->lfn; + si = di = 0; + for (;;) { + w = p[si++]; /* Get a character */ + if (w < ' ' || w == '/' || w == '\\') break; /* Break on end of segment */ + if (di >= _MAX_LFN) /* Reject too long name */ + return FR_INVALID_NAME; +#if !_LFN_UNICODE + w &= 0xFF; + if (IsDBCS1(w)) { /* Check if it is a DBC 1st byte (always false on SBCS cfg) */ + b = (BYTE)p[si++]; /* Get 2nd byte */ + if (!IsDBCS2(b)) + return FR_INVALID_NAME; /* Reject invalid sequence */ + w = (w << 8) + b; /* Create a DBC */ + } + w = ff_convert(w, 1); /* Convert ANSI/OEM to Unicode */ + if (!w) return FR_INVALID_NAME; /* Reject invalid code */ +#endif + if (w < 0x80 && chk_chr("\"*:<>\?|\x7F", w)) /* Reject illegal chars for LFN */ + return FR_INVALID_NAME; + lfn[di++] = w; /* Store the Unicode char */ + } + *path = &p[si]; /* Return pointer to the next segment */ + cf = (w < ' ') ? NS_LAST : 0; /* Set last segment flag if end of path */ +#if _FS_RPATH + if ((di == 1 && lfn[di-1] == '.') || /* Is this a dot entry? */ + (di == 2 && lfn[di-1] == '.' && lfn[di-2] == '.')) { + lfn[di] = 0; + for (i = 0; i < 11; i++) + dj->fn[i] = (i < di) ? '.' : ' '; + dj->fn[i] = cf | NS_DOT; /* This is a dot entry */ + return FR_OK; + } +#endif + while (di) { /* Strip trailing spaces and dots */ + w = lfn[di-1]; + if (w != ' ' && w != '.') break; + di--; + } + if (!di) return FR_INVALID_NAME; /* Reject nul string */ + + lfn[di] = 0; /* LFN is created */ + + /* Create SFN in directory form */ + mem_set(dj->fn, ' ', 11); + for (si = 0; lfn[si] == ' ' || lfn[si] == '.'; si++) ; /* Strip leading spaces and dots */ + if (si) cf |= NS_LOSS | NS_LFN; + while (di && lfn[di - 1] != '.') di--; /* Find extension (di<=si: no extension) */ + + b = i = 0; ni = 8; + for (;;) { + w = lfn[si++]; /* Get an LFN char */ + if (!w) break; /* Break on end of the LFN */ + if (w == ' ' || (w == '.' && si != di)) { /* Remove spaces and dots */ + cf |= NS_LOSS | NS_LFN; continue; + } + + if (i >= ni || si == di) { /* Extension or end of SFN */ + if (ni == 11) { /* Long extension */ + cf |= NS_LOSS | NS_LFN; break; + } + if (si != di) cf |= NS_LOSS | NS_LFN; /* Out of 8.3 format */ + if (si > di) break; /* No extension */ + si = di; i = 8; ni = 11; /* Enter extension section */ + b <<= 2; continue; + } + + if (w >= 0x80) { /* Non ASCII char */ +#ifdef _EXCVT + w = ff_convert(w, 0); /* Unicode -> OEM code */ + if (w) w = excvt[w - 0x80]; /* Convert extended char to upper (SBCS) */ +#else + w = ff_convert(ff_wtoupper(w), 0); /* Upper converted Unicode -> OEM code */ +#endif + cf |= NS_LFN; /* Force create LFN entry */ + } + + if (_DF1S && w >= 0x100) { /* Double byte char (always false on SBCS cfg) */ + if (i >= ni - 1) { + cf |= NS_LOSS | NS_LFN; i = ni; continue; + } + dj->fn[i++] = (BYTE)(w >> 8); + } else { /* Single byte char */ + if (!w || chk_chr("+,;=[]", w)) { /* Replace illegal chars for SFN */ + w = '_'; cf |= NS_LOSS | NS_LFN;/* Lossy conversion */ + } else { + if (IsUpper(w)) { /* ASCII large capital */ + b |= 2; + } else { + if (IsLower(w)) { /* ASCII small capital */ + b |= 1; w -= 0x20; + } + } + } + } + dj->fn[i++] = (BYTE)w; + } + + if (dj->fn[0] == DDE) dj->fn[0] = NDDE; /* If the first char collides with deleted mark, replace it with 0x05 */ + + if (ni == 8) b <<= 2; + if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03) /* Create LFN entry when there are composite capitals */ + cf |= NS_LFN; + if (!(cf & NS_LFN)) { /* When LFN is in 8.3 format without extended char, NT flags are created */ + if ((b & 0x03) == 0x01) cf |= NS_EXT; /* NT flag (Extension has only small capital) */ + if ((b & 0x0C) == 0x04) cf |= NS_BODY; /* NT flag (Filename has only small capital) */ + } + + dj->fn[NS] = cf; /* SFN is created */ + + return FR_OK; + + +#else /* Non-LFN configuration */ + BYTE b, c, d, *sfn; + UINT ni, si, i; + const char *p; + + /* Create file name in directory form */ + for (p = *path; *p == '/' || *p == '\\'; p++) ; /* Strip duplicated separator */ + sfn = dj->fn; + mem_set(sfn, ' ', 11); + si = i = b = 0; ni = 8; +#if _FS_RPATH + if (p[si] == '.') { /* Is this a dot entry? */ + for (;;) { + c = (BYTE)p[si++]; + if (c != '.' || si >= 3) break; + sfn[i++] = c; + } + if (c != '/' && c != '\\' && c > ' ') return FR_INVALID_NAME; + *path = &p[si]; /* Return pointer to the next segment */ + sfn[NS] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT; /* Set last segment flag if end of path */ + return FR_OK; + } +#endif + for (;;) { + c = (BYTE)p[si++]; + if (c <= ' ' || c == '/' || c == '\\') break; /* Break on end of segment */ + if (c == '.' || i >= ni) { + if (ni != 8 || c != '.') return FR_INVALID_NAME; + i = 8; ni = 11; + b <<= 2; continue; + } + if (c >= 0x80) { /* Extended char? */ + b |= 3; /* Eliminate NT flag */ +#ifdef _EXCVT + c = excvt[c-0x80]; /* Upper conversion (SBCS) */ +#else +#if !_DF1S /* ASCII only cfg */ + return FR_INVALID_NAME; +#endif +#endif + } + if (IsDBCS1(c)) { /* Check if it is a DBC 1st byte (always false on SBCS cfg) */ + d = (BYTE)p[si++]; /* Get 2nd byte */ + if (!IsDBCS2(d) || i >= ni - 1) /* Reject invalid DBC */ + return FR_INVALID_NAME; + sfn[i++] = c; + sfn[i++] = d; + } else { /* Single byte code */ + if (chk_chr("\"*+,:;<=>\?[]|\x7F", c)) /* Reject illegal chrs for SFN */ + return FR_INVALID_NAME; + if (IsUpper(c)) { /* ASCII large capital? */ + b |= 2; + } else { + if (IsLower(c)) { /* ASCII small capital? */ + b |= 1; c -= 0x20; + } + } + sfn[i++] = c; + } + } + *path = &p[si]; /* Return pointer to the next segment */ + c = (c <= ' ') ? NS_LAST : 0; /* Set last segment flag if end of path */ + + if (!i) return FR_INVALID_NAME; /* Reject nul string */ + if (sfn[0] == DDE) sfn[0] = NDDE; /* When first char collides with DDE, replace it with 0x05 */ + + if (ni == 8) b <<= 2; + if ((b & 0x03) == 0x01) c |= NS_EXT; /* NT flag (Name extension has only small capital) */ + if ((b & 0x0C) == 0x04) c |= NS_BODY; /* NT flag (Name body has only small capital) */ + + sfn[NS] = c; /* Store NT flag, File name is created */ + + return FR_OK; +#endif +} + + + + +/*-----------------------------------------------------------------------*/ +/* Get file information from directory entry */ +/*-----------------------------------------------------------------------*/ +#if _FS_MINIMIZE <= 1 +static +void get_fileinfo ( /* No return code */ + DIR *dj, /* Pointer to the directory object */ + FILINFO *fno /* Pointer to the file information to be filled */ +) +{ + UINT i; + BYTE nt, *dir; + TCHAR *p, c; + + + p = fno->fname; + if (dj->sect) { + dir = dj->dir; + nt = dir[DIR_NTres]; /* NT flag */ + for (i = 0; i < 8; i++) { /* Copy name body */ + c = dir[i]; + if (c == ' ') break; + if (c == NDDE) c = (TCHAR)DDE; + if (_USE_LFN && (nt & NS_BODY) && IsUpper(c)) c += 0x20; +#if _LFN_UNICODE + if (IsDBCS1(c) && i < 7 && IsDBCS2(dir[i+1])) + c = (c << 8) | dir[++i]; + c = ff_convert(c, 1); + if (!c) c = '?'; +#endif + *p++ = c; + } + if (dir[8] != ' ') { /* Copy name extension */ + *p++ = '.'; + for (i = 8; i < 11; i++) { + c = dir[i]; + if (c == ' ') break; + if (_USE_LFN && (nt & NS_EXT) && IsUpper(c)) c += 0x20; +#if _LFN_UNICODE + if (IsDBCS1(c) && i < 10 && IsDBCS2(dir[i+1])) + c = (c << 8) | dir[++i]; + c = ff_convert(c, 1); + if (!c) c = '?'; +#endif + *p++ = c; + } + } + fno->fattrib = dir[DIR_Attr]; /* Attribute */ + fno->fsize = LD_DWORD(dir+DIR_FileSize); /* Size */ + fno->fdate = LD_WORD(dir+DIR_WrtDate); /* Date */ + fno->ftime = LD_WORD(dir+DIR_WrtTime); /* Time */ + } + *p = 0; /* Terminate SFN str by a \0 */ + +#if _USE_LFN + if (fno->lfname && fno->lfsize) { + TCHAR *tp = fno->lfname; + WCHAR w, *lfn; + + i = 0; + if (dj->sect && dj->lfn_idx != 0xFFFF) {/* Get LFN if available */ + lfn = dj->lfn; + while ((w = *lfn++) != 0) { /* Get an LFN char */ +#if !_LFN_UNICODE + w = ff_convert(w, 0); /* Unicode -> OEM conversion */ + if (!w) { i = 0; break; } /* Could not convert, no LFN */ + if (_DF1S && w >= 0x100) /* Put 1st byte if it is a DBC (always false on SBCS cfg) */ + tp[i++] = (TCHAR)(w >> 8); +#endif + if (i >= fno->lfsize - 1) { i = 0; break; } /* Buffer overflow, no LFN */ + tp[i++] = (TCHAR)w; + } + } + tp[i] = 0; /* Terminate the LFN str by a \0 */ + } +#endif +} +#endif /* _FS_MINIMIZE <= 1 */ + + + + +/*-----------------------------------------------------------------------*/ +/* Follow a file path */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT follow_path ( /* FR_OK(0): successful, !=0: error code */ + DIR *dj, /* Directory object to return last directory and found object */ + const TCHAR *path /* Full-path string to find a file or directory */ +) +{ + FRESULT res; + BYTE *dir, ns; + + +#if _FS_RPATH + if (*path == '/' || *path == '\\') { /* There is a heading separator */ + path++; dj->sclust = 0; /* Strip it and start from the root dir */ + } else { /* No heading separator */ + dj->sclust = dj->fs->cdir; /* Start from the current dir */ + } +#else + if (*path == '/' || *path == '\\') /* Strip heading separator if exist */ + path++; + dj->sclust = 0; /* Start from the root dir */ +#endif + + if ((UINT)*path < ' ') { /* Nul path means the start directory itself */ + res = dir_sdi(dj, 0); + dj->dir = 0; + + } else { /* Follow path */ + for (;;) { + res = create_name(dj, &path); /* Get a segment */ + if (res != FR_OK) break; + res = dir_find(dj); /* Find it */ + ns = *(dj->fn+NS); + if (res != FR_OK) { /* Failed to find the object */ + if (res != FR_NO_FILE) break; /* Abort if any hard error occured */ + /* Object not found */ + if (_FS_RPATH && (ns & NS_DOT)) { /* If dot entry is not exit */ + dj->sclust = 0; dj->dir = 0; /* It is the root dir */ + res = FR_OK; + if (!(ns & NS_LAST)) continue; + } else { /* Could not find the object */ + if (!(ns & NS_LAST)) res = FR_NO_PATH; + } + break; + } + if (ns & NS_LAST) break; /* Last segment match. Function completed. */ + dir = dj->dir; /* There is next segment. Follow the sub directory */ + if (!(dir[DIR_Attr] & AM_DIR)) { /* Cannot follow because it is a file */ + res = FR_NO_PATH; break; + } + dj->sclust = LD_CLUST(dir); + } + } + + return res; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Load a sector and check if it is an FAT Volume Boot Record */ +/*-----------------------------------------------------------------------*/ + +static +BYTE check_fs ( /* 0:FAT-VBR, 1:Valid BR but not FAT, 2:Not a BR, 3:Disk error */ + FATFS *fs, /* File system object */ + DWORD sect /* Sector# (lba) to check if it is an FAT boot record or not */ +) +{ + if (disk_read(fs->drv, fs->win, sect, 1) != RES_OK) /* Load boot record */ + return 3; + if (LD_WORD(&fs->win[BS_55AA]) != 0xAA55) /* Check record signature (always placed at offset 510 even if the sector size is >512) */ + return 2; + + if ((LD_DWORD(&fs->win[BS_FilSysType]) & 0xFFFFFF) == 0x544146) /* Check "FAT" string */ + return 0; + if ((LD_DWORD(&fs->win[BS_FilSysType32]) & 0xFFFFFF) == 0x544146) + return 0; + + return 1; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Check if the file system object is valid or not */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT chk_mounted ( /* FR_OK(0): successful, !=0: any error occurred */ + const TCHAR **path, /* Pointer to pointer to the path name (drive number) */ + FATFS **rfs, /* Pointer to pointer to the found file system object */ + BYTE chk_wp /* !=0: Check media write protection for write access */ +) +{ + BYTE fmt, b, pi, *tbl; + UINT vol; + DSTATUS stat; + DWORD bsect, fasize, tsect, sysect, nclst, szbfat; + WORD nrsv; + const TCHAR *p = *path; + FATFS *fs; + + /* Get logical drive number from the path name */ + vol = p[0] - '0'; /* Is there a drive number? */ + if (vol <= 9 && p[1] == ':') { /* Found a drive number, get and strip it */ + p += 2; *path = p; /* Return pointer to the path name */ + } else { /* No drive number is given */ +#if _FS_RPATH + vol = CurrVol; /* Use current drive */ +#else + vol = 0; /* Use drive 0 */ +#endif + } + + /* Check if the file system object is valid or not */ + if (vol >= _VOLUMES) /* Is the drive number valid? */ + return FR_INVALID_DRIVE; + *rfs = fs = FatFs[vol]; /* Return pointer to the corresponding file system object */ + if (!fs) return FR_NOT_ENABLED; /* Is the file system object available? */ + + ENTER_FF(fs); /* Lock file system */ + + if (fs->fs_type) { /* If the logical drive has been mounted */ + stat = disk_status(fs->drv); + if (!(stat & STA_NOINIT)) { /* and the physical drive is kept initialized (has not been changed), */ + if (!_FS_READONLY && chk_wp && (stat & STA_PROTECT)) /* Check write protection if needed */ + return FR_WRITE_PROTECTED; + return FR_OK; /* The file system object is valid */ + } + } + + /* The file system object is not valid. */ + /* Following code attempts to mount the volume. (analyze BPB and initialize the fs object) */ + + fs->fs_type = 0; /* Clear the file system object */ + fs->drv = LD2PD(vol); /* Bind the logical drive and a physical drive */ + stat = disk_initialize(fs->drv); /* Initialize low level disk I/O layer */ + if (stat & STA_NOINIT) /* Check if the initialization succeeded */ + return FR_NOT_READY; /* Failed to initialize due to no media or hard error */ + if (!_FS_READONLY && chk_wp && (stat & STA_PROTECT)) /* Check disk write protection if needed */ + return FR_WRITE_PROTECTED; +#if _MAX_SS != 512 /* Get disk sector size (variable sector size cfg only) */ + if (disk_ioctl(fs->drv, GET_SECTOR_SIZE, &fs->ssize) != RES_OK) + return FR_DISK_ERR; +#endif + /* Search FAT partition on the drive. Supports only generic partitionings, FDISK and SFD. */ + fmt = check_fs(fs, bsect = 0); /* Load sector 0 and check if it is an FAT-VBR (in SFD) */ + if (LD2PT(vol) && !fmt) fmt = 1; /* Force non-SFD if the volume is forced partition */ + if (fmt == 1) { /* Not an FAT-VBR, the physical drive can be partitioned */ + /* Check the partition listed in the partition table */ + pi = LD2PT(vol); + if (pi) pi--; + tbl = &fs->win[MBR_Table + pi * SZ_PTE];/* Partition table */ + if (tbl[4]) { /* Is the partition existing? */ + bsect = LD_DWORD(&tbl[8]); /* Partition offset in LBA */ + fmt = check_fs(fs, bsect); /* Check the partition */ + } + } + if (fmt == 3) return FR_DISK_ERR; + if (fmt) return FR_NO_FILESYSTEM; /* No FAT volume is found */ + + /* An FAT volume is found. Following code initializes the file system object */ + + if (LD_WORD(fs->win+BPB_BytsPerSec) != SS(fs)) /* (BPB_BytsPerSec must be equal to the physical sector size) */ + return FR_NO_FILESYSTEM; + + fasize = LD_WORD(fs->win+BPB_FATSz16); /* Number of sectors per FAT */ + if (!fasize) fasize = LD_DWORD(fs->win+BPB_FATSz32); + fs->fsize = fasize; + + fs->n_fats = b = fs->win[BPB_NumFATs]; /* Number of FAT copies */ + if (b != 1 && b != 2) return FR_NO_FILESYSTEM; /* (Must be 1 or 2) */ + fasize *= b; /* Number of sectors for FAT area */ + + fs->csize = b = fs->win[BPB_SecPerClus]; /* Number of sectors per cluster */ + if (!b || (b & (b - 1))) return FR_NO_FILESYSTEM; /* (Must be power of 2) */ + + fs->n_rootdir = LD_WORD(fs->win+BPB_RootEntCnt); /* Number of root directory entries */ + if (fs->n_rootdir % (SS(fs) / SZ_DIR)) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be sector aligned) */ + + tsect = LD_WORD(fs->win+BPB_TotSec16); /* Number of sectors on the volume */ + if (!tsect) tsect = LD_DWORD(fs->win+BPB_TotSec32); + + nrsv = LD_WORD(fs->win+BPB_RsvdSecCnt); /* Number of reserved sectors */ + if (!nrsv) return FR_NO_FILESYSTEM; /* (BPB_RsvdSecCnt must not be 0) */ + + /* Determine the FAT sub type */ + sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / SZ_DIR); /* RSV+FAT+DIR */ + if (tsect < sysect) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ + nclst = (tsect - sysect) / fs->csize; /* Number of clusters */ + if (!nclst) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ + fmt = FS_FAT12; + if (nclst >= MIN_FAT16) fmt = FS_FAT16; + if (nclst >= MIN_FAT32) fmt = FS_FAT32; + + /* Boundaries and Limits */ + fs->n_fatent = nclst + 2; /* Number of FAT entries */ + fs->database = bsect + sysect; /* Data start sector */ + fs->fatbase = bsect + nrsv; /* FAT start sector */ + if (fmt == FS_FAT32) { + if (fs->n_rootdir) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be 0) */ + fs->dirbase = LD_DWORD(fs->win+BPB_RootClus); /* Root directory start cluster */ + szbfat = fs->n_fatent * 4; /* (Required FAT size) */ + } else { + if (!fs->n_rootdir) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must not be 0) */ + fs->dirbase = fs->fatbase + fasize; /* Root directory start sector */ + szbfat = (fmt == FS_FAT16) ? /* (Required FAT size) */ + fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1); + } + if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs)) /* (BPB_FATSz must not be less than required) */ + return FR_NO_FILESYSTEM; + +#if !_FS_READONLY + /* Initialize cluster allocation information */ + fs->free_clust = 0xFFFFFFFF; + fs->last_clust = 0; + + /* Get fsinfo if available */ + if (fmt == FS_FAT32) { + fs->fsi_flag = 0; + fs->fsi_sector = bsect + LD_WORD(fs->win+BPB_FSInfo); + if (disk_read(fs->drv, fs->win, fs->fsi_sector, 1) == RES_OK && + LD_WORD(fs->win+BS_55AA) == 0xAA55 && + LD_DWORD(fs->win+FSI_LeadSig) == 0x41615252 && + LD_DWORD(fs->win+FSI_StrucSig) == 0x61417272) { + fs->last_clust = LD_DWORD(fs->win+FSI_Nxt_Free); + fs->free_clust = LD_DWORD(fs->win+FSI_Free_Count); + } + } +#endif + fs->fs_type = fmt; /* FAT sub-type */ + fs->id = ++Fsid; /* File system mount ID */ + fs->winsect = 0; /* Invalidate sector cache */ + fs->wflag = 0; +#if _FS_RPATH + fs->cdir = 0; /* Current directory (root dir) */ +#endif +#if _FS_SHARE /* Clear file lock semaphores */ + clear_lock(fs); +#endif + + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Check if the file/dir object is valid or not */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT validate ( /* FR_OK(0): The object is valid, !=0: Invalid */ + FATFS *fs, /* Pointer to the file system object */ + WORD id /* Member id of the target object to be checked */ +) +{ + if (!fs || !fs->fs_type || fs->id != id) + return FR_INVALID_OBJECT; + + ENTER_FF(fs); /* Lock file system */ + + if (disk_status(fs->drv) & STA_NOINIT) + return FR_NOT_READY; + + return FR_OK; +} + + + + +/*-------------------------------------------------------------------------- + + Public Functions + +--------------------------------------------------------------------------*/ + + + +/*-----------------------------------------------------------------------*/ +/* Mount/Unmount a Logical Drive */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_mount ( + BYTE vol, /* Logical drive number to be mounted/unmounted */ + FATFS *fs /* Pointer to new file system object (NULL for unmount)*/ +) +{ + FATFS *rfs; + + + if (vol >= _VOLUMES) /* Check if the drive number is valid */ + return FR_INVALID_DRIVE; + rfs = FatFs[vol]; /* Get current fs object */ + + if (rfs) { +#if _FS_SHARE + clear_lock(rfs); +#endif +#if _FS_REENTRANT /* Discard sync object of the current volume */ + if (!ff_del_syncobj(rfs->sobj)) return FR_INT_ERR; +#endif + rfs->fs_type = 0; /* Clear old fs object */ + } + + if (fs) { + fs->fs_type = 0; /* Clear new fs object */ +#if _FS_REENTRANT /* Create sync object for the new volume */ + if (!ff_cre_syncobj(vol, &fs->sobj)) return FR_INT_ERR; +#endif + } + FatFs[vol] = fs; /* Register new fs object */ + + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Open or Create a File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_open ( + FIL *fp, /* Pointer to the blank file object */ + const TCHAR *path, /* Pointer to the file name */ + BYTE mode /* Access mode and file open mode flags */ +) +{ + FRESULT res; + DIR dj; + BYTE *dir; + DEF_NAMEBUF; + + + fp->fs = 0; /* Clear file object */ + +#if !_FS_READONLY + mode &= FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW; + res = chk_mounted(&path, &dj.fs, (BYTE)(mode & ~FA_READ)); +#else + mode &= FA_READ; + res = chk_mounted(&path, &dj.fs, 0); +#endif + INIT_BUF(dj); + if (res == FR_OK) + res = follow_path(&dj, path); /* Follow the file path */ + dir = dj.dir; + +#if !_FS_READONLY /* R/W configuration */ + if (res == FR_OK) { + if (!dir) /* Current dir itself */ + res = FR_INVALID_NAME; +#if _FS_SHARE + else + res = chk_lock(&dj, (mode & ~FA_READ) ? 1 : 0); +#endif + } + /* Create or Open a file */ + if (mode & (FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW)) { + DWORD dw, cl; + + if (res != FR_OK) { /* No file, create new */ + if (res == FR_NO_FILE) /* There is no file to open, create a new entry */ +#if _FS_SHARE + res = enq_lock() ? dir_register(&dj) : FR_TOO_MANY_OPEN_FILES; +#else + res = dir_register(&dj); +#endif + mode |= FA_CREATE_ALWAYS; /* File is created */ + dir = dj.dir; /* New entry */ + } + else { /* Any object is already existing */ + if (dir[DIR_Attr] & (AM_RDO | AM_DIR)) { /* Cannot overwrite it (R/O or DIR) */ + res = FR_DENIED; + } else { + if (mode & FA_CREATE_NEW) /* Cannot create as new file */ + res = FR_EXIST; + } + } + if (res == FR_OK && (mode & FA_CREATE_ALWAYS)) { /* Truncate it if overwrite mode */ + dw = get_fattime(); /* Created time */ + ST_DWORD(dir+DIR_CrtTime, dw); + dir[DIR_Attr] = 0; /* Reset attribute */ + ST_DWORD(dir+DIR_FileSize, 0); /* size = 0 */ + cl = LD_CLUST(dir); /* Get start cluster */ + ST_CLUST(dir, 0); /* cluster = 0 */ + dj.fs->wflag = 1; + if (cl) { /* Remove the cluster chain if exist */ + dw = dj.fs->winsect; + res = remove_chain(dj.fs, cl); + if (res == FR_OK) { + dj.fs->last_clust = cl - 1; /* Reuse the cluster hole */ + res = move_window(dj.fs, dw); + } + } + } + } + else { /* Open an existing file */ + if (res == FR_OK) { /* Follow succeeded */ + if (dir[DIR_Attr] & AM_DIR) { /* It is a directory */ + res = FR_NO_FILE; + } else { + if ((mode & FA_WRITE) && (dir[DIR_Attr] & AM_RDO)) /* R/O violation */ + res = FR_DENIED; + } + } + } + if (res == FR_OK) { + if (mode & FA_CREATE_ALWAYS) /* Set file change flag if created or overwritten */ + mode |= FA__WRITTEN; + fp->dir_sect = dj.fs->winsect; /* Pointer to the directory entry */ + fp->dir_ptr = dir; +#if _FS_SHARE + fp->lockid = inc_lock(&dj, (mode & ~FA_READ) ? 1 : 0); + if (!fp->lockid) res = FR_INT_ERR; +#endif + } + +#else /* R/O configuration */ + if (res == FR_OK) { /* Follow succeeded */ + if (!dir) { /* Current dir itself */ + res = FR_INVALID_NAME; + } else { + if (dir[DIR_Attr] & AM_DIR) /* It is a directory */ + res = FR_NO_FILE; + } + } +#endif + FREE_BUF(); + + if (res == FR_OK) { + fp->flag = mode; /* File access mode */ + fp->sclust = LD_CLUST(dir); /* File start cluster */ + fp->fsize = LD_DWORD(dir+DIR_FileSize); /* File size */ + fp->fptr = 0; /* File pointer */ + fp->dsect = 0; +#if _USE_FASTSEEK + fp->cltbl = 0; /* Normal seek mode */ +#endif + fp->fs = dj.fs; fp->id = dj.fs->id; /* Validate file object */ + } + + LEAVE_FF(dj.fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Read File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_read ( + FIL *fp, /* Pointer to the file object */ + void *buff, /* Pointer to data buffer */ + UINT btr, /* Number of bytes to read */ + UINT *br /* Pointer to number of bytes read */ +) +{ + FRESULT res; + DWORD clst, sect, remain; + UINT rcnt, cc; + BYTE csect, *rbuff = buff; + + + *br = 0; /* Initialize byte counter */ + + res = validate(fp->fs, fp->id); /* Check validity */ + if (res != FR_OK) LEAVE_FF(fp->fs, res); + if (fp->flag & FA__ERROR) /* Aborted file? */ + LEAVE_FF(fp->fs, FR_INT_ERR); + if (!(fp->flag & FA_READ)) /* Check access mode */ + LEAVE_FF(fp->fs, FR_DENIED); + remain = fp->fsize - fp->fptr; + if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */ + + for ( ; btr; /* Repeat until all data read */ + rbuff += rcnt, fp->fptr += rcnt, *br += rcnt, btr -= rcnt) { + if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ + csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */ + if (!csect) { /* On the cluster boundary? */ + if (fp->fptr == 0) { /* On the top of the file? */ + clst = fp->sclust; /* Follow from the origin */ + } else { /* Middle or end of the file */ +#if _USE_FASTSEEK + if (fp->cltbl) + clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */ + else +#endif + clst = get_fat(fp->fs, fp->clust); /* Follow cluster chain on the FAT */ + } + if (clst < 2) ABORT(fp->fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + fp->clust = clst; /* Update current cluster */ + } + sect = clust2sect(fp->fs, fp->clust); /* Get current sector */ + if (!sect) ABORT(fp->fs, FR_INT_ERR); + sect += csect; + cc = btr / SS(fp->fs); /* When remaining bytes >= sector size, */ + if (cc) { /* Read maximum contiguous sectors directly */ + if (csect + cc > fp->fs->csize) /* Clip at cluster boundary */ + cc = fp->fs->csize - csect; + if (disk_read(fp->fs->drv, rbuff, sect, (BYTE)cc) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); +#if !_FS_READONLY && _FS_MINIMIZE <= 2 /* Replace one of the read sectors with cached data if it contains a dirty sector */ +#if _FS_TINY + if (fp->fs->wflag && fp->fs->winsect - sect < cc) + mem_cpy(rbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), fp->fs->win, SS(fp->fs)); +#else + if ((fp->flag & FA__DIRTY) && fp->dsect - sect < cc) + mem_cpy(rbuff + ((fp->dsect - sect) * SS(fp->fs)), fp->buf, SS(fp->fs)); +#endif +#endif + rcnt = SS(fp->fs) * cc; /* Number of bytes transferred */ + continue; + } +#if !_FS_TINY + if (fp->dsect != sect) { /* Load data sector if not in cache */ +#if !_FS_READONLY + if (fp->flag & FA__DIRTY) { /* Write-back dirty sector cache */ + if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); + fp->flag &= ~FA__DIRTY; + } +#endif + if (disk_read(fp->fs->drv, fp->buf, sect, 1) != RES_OK) /* Fill sector cache */ + ABORT(fp->fs, FR_DISK_ERR); + } +#endif + fp->dsect = sect; + } + rcnt = SS(fp->fs) - (fp->fptr % SS(fp->fs)); /* Get partial sector data from sector buffer */ + if (rcnt > btr) rcnt = btr; +#if _FS_TINY + if (move_window(fp->fs, fp->dsect)) /* Move sector window */ + ABORT(fp->fs, FR_DISK_ERR); + mem_cpy(rbuff, &fp->fs->win[fp->fptr % SS(fp->fs)], rcnt); /* Pick partial sector */ +#else + mem_cpy(rbuff, &fp->buf[fp->fptr % SS(fp->fs)], rcnt); /* Pick partial sector */ +#endif + } + + LEAVE_FF(fp->fs, FR_OK); +} + + + + +#if !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Write File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_write ( + FIL *fp, /* Pointer to the file object */ + const void *buff, /* Pointer to the data to be written */ + UINT btw, /* Number of bytes to write */ + UINT *bw /* Pointer to number of bytes written */ +) +{ + FRESULT res; + DWORD clst, sect; + UINT wcnt, cc; + const BYTE *wbuff = buff; + BYTE csect; + + + *bw = 0; /* Initialize byte counter */ + + res = validate(fp->fs, fp->id); /* Check validity */ + if (res != FR_OK) LEAVE_FF(fp->fs, res); + if (fp->flag & FA__ERROR) /* Aborted file? */ + LEAVE_FF(fp->fs, FR_INT_ERR); + if (!(fp->flag & FA_WRITE)) /* Check access mode */ + LEAVE_FF(fp->fs, FR_DENIED); + if ((DWORD)(fp->fsize + btw) < fp->fsize) btw = 0; /* File size cannot reach 4GB */ + + for ( ; btw; /* Repeat until all data written */ + wbuff += wcnt, fp->fptr += wcnt, *bw += wcnt, btw -= wcnt) { + if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ + csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */ + if (!csect) { /* On the cluster boundary? */ + if (fp->fptr == 0) { /* On the top of the file? */ + clst = fp->sclust; /* Follow from the origin */ + if (clst == 0) /* When no cluster is allocated, */ + fp->sclust = clst = create_chain(fp->fs, 0); /* Create a new cluster chain */ + } else { /* Middle or end of the file */ +#if _USE_FASTSEEK + if (fp->cltbl) + clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */ + else +#endif + clst = create_chain(fp->fs, fp->clust); /* Follow or stretch cluster chain on the FAT */ + } + if (clst == 0) break; /* Could not allocate a new cluster (disk full) */ + if (clst == 1) ABORT(fp->fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + fp->clust = clst; /* Update current cluster */ + } +#if _FS_TINY + if (fp->fs->winsect == fp->dsect && move_window(fp->fs, 0)) /* Write-back sector cache */ + ABORT(fp->fs, FR_DISK_ERR); +#else + if (fp->flag & FA__DIRTY) { /* Write-back sector cache */ + if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); + fp->flag &= ~FA__DIRTY; + } +#endif + sect = clust2sect(fp->fs, fp->clust); /* Get current sector */ + if (!sect) ABORT(fp->fs, FR_INT_ERR); + sect += csect; + cc = btw / SS(fp->fs); /* When remaining bytes >= sector size, */ + if (cc) { /* Write maximum contiguous sectors directly */ + if (csect + cc > fp->fs->csize) /* Clip at cluster boundary */ + cc = fp->fs->csize - csect; + if (disk_write(fp->fs->drv, wbuff, sect, (BYTE)cc) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); +#if _FS_TINY + if (fp->fs->winsect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */ + mem_cpy(fp->fs->win, wbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), SS(fp->fs)); + fp->fs->wflag = 0; + } +#else + if (fp->dsect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */ + mem_cpy(fp->buf, wbuff + ((fp->dsect - sect) * SS(fp->fs)), SS(fp->fs)); + fp->flag &= ~FA__DIRTY; + } +#endif + wcnt = SS(fp->fs) * cc; /* Number of bytes transferred */ + continue; + } +#if _FS_TINY + if (fp->fptr >= fp->fsize) { /* Avoid silly cache filling at growing edge */ + if (move_window(fp->fs, 0)) ABORT(fp->fs, FR_DISK_ERR); + fp->fs->winsect = sect; + } +#else + if (fp->dsect != sect) { /* Fill sector cache with file data */ + if (fp->fptr < fp->fsize && + disk_read(fp->fs->drv, fp->buf, sect, 1) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); + } +#endif + fp->dsect = sect; + } + wcnt = SS(fp->fs) - (fp->fptr % SS(fp->fs));/* Put partial sector into file I/O buffer */ + if (wcnt > btw) wcnt = btw; +#if _FS_TINY + if (move_window(fp->fs, fp->dsect)) /* Move sector window */ + ABORT(fp->fs, FR_DISK_ERR); + mem_cpy(&fp->fs->win[fp->fptr % SS(fp->fs)], wbuff, wcnt); /* Fit partial sector */ + fp->fs->wflag = 1; +#else + mem_cpy(&fp->buf[fp->fptr % SS(fp->fs)], wbuff, wcnt); /* Fit partial sector */ + fp->flag |= FA__DIRTY; +#endif + } + + if (fp->fptr > fp->fsize) fp->fsize = fp->fptr; /* Update file size if needed */ + fp->flag |= FA__WRITTEN; /* Set file change flag */ + + LEAVE_FF(fp->fs, FR_OK); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Synchronize the File Object */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_sync ( + FIL *fp /* Pointer to the file object */ +) +{ + FRESULT res; + DWORD tim; + BYTE *dir; + + + res = validate(fp->fs, fp->id); /* Check validity of the object */ + if (res == FR_OK) { + if (fp->flag & FA__WRITTEN) { /* Has the file been written? */ +#if !_FS_TINY /* Write-back dirty buffer */ + if (fp->flag & FA__DIRTY) { + if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK) + LEAVE_FF(fp->fs, FR_DISK_ERR); + fp->flag &= ~FA__DIRTY; + } +#endif + /* Update the directory entry */ + res = move_window(fp->fs, fp->dir_sect); + if (res == FR_OK) { + dir = fp->dir_ptr; + dir[DIR_Attr] |= AM_ARC; /* Set archive bit */ + ST_DWORD(dir+DIR_FileSize, fp->fsize); /* Update file size */ + ST_CLUST(dir, fp->sclust); /* Update start cluster */ + tim = get_fattime(); /* Update updated time */ + ST_DWORD(dir+DIR_WrtTime, tim); + fp->flag &= ~FA__WRITTEN; + fp->fs->wflag = 1; + res = sync(fp->fs); + } + } + } + + LEAVE_FF(fp->fs, res); +} + +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Close File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_close ( + FIL *fp /* Pointer to the file object to be closed */ +) +{ + FRESULT res; + +#if _FS_READONLY + FATFS *fs = fp->fs; + res = validate(fs, fp->id); + if (res == FR_OK) fp->fs = 0; /* Discard file object */ + LEAVE_FF(fs, res); + +#else + res = f_sync(fp); /* Flush cached data */ +#if _FS_SHARE + if (res == FR_OK) { /* Decrement open counter */ +#if _FS_REENTRANT + res = validate(fp->fs, fp->id); + if (res == FR_OK) { + res = dec_lock(fp->lockid); + unlock_fs(fp->fs, FR_OK); + } +#else + res = dec_lock(fp->lockid); +#endif + } +#endif + if (res == FR_OK) fp->fs = 0; /* Discard file object */ + return res; +#endif +} + + + + +/*-----------------------------------------------------------------------*/ +/* Current Drive/Directory Handlings */ +/*-----------------------------------------------------------------------*/ + +#if _FS_RPATH >= 1 + +FRESULT f_chdrive ( + BYTE drv /* Drive number */ +) +{ + if (drv >= _VOLUMES) return FR_INVALID_DRIVE; + + CurrVol = drv; + + return FR_OK; +} + + + +FRESULT f_chdir ( + const TCHAR *path /* Pointer to the directory path */ +) +{ + FRESULT res; + DIR dj; + DEF_NAMEBUF; + + + res = chk_mounted(&path, &dj.fs, 0); + if (res == FR_OK) { + INIT_BUF(dj); + res = follow_path(&dj, path); /* Follow the path */ + FREE_BUF(); + if (res == FR_OK) { /* Follow completed */ + if (!dj.dir) { + dj.fs->cdir = dj.sclust; /* Start directory itself */ + } else { + if (dj.dir[DIR_Attr] & AM_DIR) /* Reached to the directory */ + dj.fs->cdir = LD_CLUST(dj.dir); + else + res = FR_NO_PATH; /* Reached but a file */ + } + } + if (res == FR_NO_FILE) res = FR_NO_PATH; + } + + LEAVE_FF(dj.fs, res); +} + + +#if _FS_RPATH >= 2 +FRESULT f_getcwd ( + TCHAR *path, /* Pointer to the directory path */ + UINT sz_path /* Size of path */ +) +{ + FRESULT res; + DIR dj; + UINT i, n; + DWORD ccl; + TCHAR *tp; + FILINFO fno; + DEF_NAMEBUF; + + + *path = 0; + res = chk_mounted((const TCHAR**)&path, &dj.fs, 0); /* Get current volume */ + if (res == FR_OK) { + INIT_BUF(dj); + i = sz_path; /* Bottom of buffer (dir stack base) */ + dj.sclust = dj.fs->cdir; /* Start to follow upper dir from current dir */ + while ((ccl = dj.sclust) != 0) { /* Repeat while current dir is a sub-dir */ + res = dir_sdi(&dj, 1); /* Get parent dir */ + if (res != FR_OK) break; + res = dir_read(&dj); + if (res != FR_OK) break; + dj.sclust = LD_CLUST(dj.dir); /* Goto parent dir */ + res = dir_sdi(&dj, 0); + if (res != FR_OK) break; + do { /* Find the entry links to the child dir */ + res = dir_read(&dj); + if (res != FR_OK) break; + if (ccl == LD_CLUST(dj.dir)) break; /* Found the entry */ + res = dir_next(&dj, 0); + } while (res == FR_OK); + if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */ + if (res != FR_OK) break; +#if _USE_LFN + fno.lfname = path; + fno.lfsize = i; +#endif + get_fileinfo(&dj, &fno); /* Get the dir name and push it to the buffer */ + tp = fno.fname; + if (_USE_LFN && *path) tp = path; + for (n = 0; tp[n]; n++) ; + if (i < n + 3) { + res = FR_NOT_ENOUGH_CORE; break; + } + while (n) path[--i] = tp[--n]; + path[--i] = '/'; + } + tp = path; + if (res == FR_OK) { + *tp++ = '0' + CurrVol; /* Put drive number */ + *tp++ = ':'; + if (i == sz_path) { /* Root-dir */ + *tp++ = '/'; + } else { /* Sub-dir */ + do /* Add stacked path str */ + *tp++ = path[i++]; + while (i < sz_path); + } + } + *tp = 0; + FREE_BUF(); + } + + LEAVE_FF(dj.fs, res); +} +#endif /* _FS_RPATH >= 2 */ +#endif /* _FS_RPATH >= 1 */ + + + +#if _FS_MINIMIZE <= 2 +/*-----------------------------------------------------------------------*/ +/* Seek File R/W Pointer */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_lseek ( + FIL *fp, /* Pointer to the file object */ + DWORD ofs /* File pointer from top of file */ +) +{ + FRESULT res; + + + res = validate(fp->fs, fp->id); /* Check validity of the object */ + if (res != FR_OK) LEAVE_FF(fp->fs, res); + if (fp->flag & FA__ERROR) /* Check abort flag */ + LEAVE_FF(fp->fs, FR_INT_ERR); + +#if _USE_FASTSEEK + if (fp->cltbl) { /* Fast seek */ + DWORD cl, pcl, ncl, tcl, dsc, tlen, ulen, *tbl; + + if (ofs == CREATE_LINKMAP) { /* Create CLMT */ + tbl = fp->cltbl; + tlen = *tbl++; ulen = 2; /* Given table size and required table size */ + cl = fp->sclust; /* Top of the chain */ + if (cl) { + do { + /* Get a fragment */ + tcl = cl; ncl = 0; ulen += 2; /* Top, length and used items */ + do { + pcl = cl; ncl++; + cl = get_fat(fp->fs, cl); + if (cl <= 1) ABORT(fp->fs, FR_INT_ERR); + if (cl == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + } while (cl == pcl + 1); + if (ulen <= tlen) { /* Store the length and top of the fragment */ + *tbl++ = ncl; *tbl++ = tcl; + } + } while (cl < fp->fs->n_fatent); /* Repeat until end of chain */ + } + *fp->cltbl = ulen; /* Number of items used */ + if (ulen <= tlen) + *tbl = 0; /* Terminate table */ + else + res = FR_NOT_ENOUGH_CORE; /* Given table size is smaller than required */ + + } else { /* Fast seek */ + if (ofs > fp->fsize) /* Clip offset at the file size */ + ofs = fp->fsize; + fp->fptr = ofs; /* Set file pointer */ + if (ofs) { + fp->clust = clmt_clust(fp, ofs - 1); + dsc = clust2sect(fp->fs, fp->clust); + if (!dsc) ABORT(fp->fs, FR_INT_ERR); + dsc += (ofs - 1) / SS(fp->fs) & (fp->fs->csize - 1); + if (fp->fptr % SS(fp->fs) && dsc != fp->dsect) { /* Refill sector cache if needed */ +#if !_FS_TINY +#if !_FS_READONLY + if (fp->flag & FA__DIRTY) { /* Write-back dirty sector cache */ + if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); + fp->flag &= ~FA__DIRTY; + } +#endif + if (disk_read(fp->fs->drv, fp->buf, dsc, 1) != RES_OK) /* Load current sector */ + ABORT(fp->fs, FR_DISK_ERR); +#endif + fp->dsect = dsc; + } + } + } + } else +#endif + + /* Normal Seek */ + { + DWORD clst, bcs, nsect, ifptr; + + if (ofs > fp->fsize /* In read-only mode, clip offset with the file size */ +#if !_FS_READONLY + && !(fp->flag & FA_WRITE) +#endif + ) ofs = fp->fsize; + + ifptr = fp->fptr; + fp->fptr = nsect = 0; + if (ofs) { + bcs = (DWORD)fp->fs->csize * SS(fp->fs); /* Cluster size (byte) */ + if (ifptr > 0 && + (ofs - 1) / bcs >= (ifptr - 1) / bcs) { /* When seek to same or following cluster, */ + fp->fptr = (ifptr - 1) & ~(bcs - 1); /* start from the current cluster */ + ofs -= fp->fptr; + clst = fp->clust; + } else { /* When seek to back cluster, */ + clst = fp->sclust; /* start from the first cluster */ +#if !_FS_READONLY + if (clst == 0) { /* If no cluster chain, create a new chain */ + clst = create_chain(fp->fs, 0); + if (clst == 1) ABORT(fp->fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + fp->sclust = clst; + } +#endif + fp->clust = clst; + } + if (clst != 0) { + while (ofs > bcs) { /* Cluster following loop */ +#if !_FS_READONLY + if (fp->flag & FA_WRITE) { /* Check if in write mode or not */ + clst = create_chain(fp->fs, clst); /* Force stretch if in write mode */ + if (clst == 0) { /* When disk gets full, clip file size */ + ofs = bcs; break; + } + } else +#endif + clst = get_fat(fp->fs, clst); /* Follow cluster chain if not in write mode */ + if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + if (clst <= 1 || clst >= fp->fs->n_fatent) ABORT(fp->fs, FR_INT_ERR); + fp->clust = clst; + fp->fptr += bcs; + ofs -= bcs; + } + fp->fptr += ofs; + if (ofs % SS(fp->fs)) { + nsect = clust2sect(fp->fs, clst); /* Current sector */ + if (!nsect) ABORT(fp->fs, FR_INT_ERR); + nsect += ofs / SS(fp->fs); + } + } + } + if (fp->fptr % SS(fp->fs) && nsect != fp->dsect) { /* Fill sector cache if needed */ +#if !_FS_TINY +#if !_FS_READONLY + if (fp->flag & FA__DIRTY) { /* Write-back dirty sector cache */ + if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); + fp->flag &= ~FA__DIRTY; + } +#endif + if (disk_read(fp->fs->drv, fp->buf, nsect, 1) != RES_OK) /* Fill sector cache */ + ABORT(fp->fs, FR_DISK_ERR); +#endif + fp->dsect = nsect; + } +#if !_FS_READONLY + if (fp->fptr > fp->fsize) { /* Set file change flag if the file size is extended */ + fp->fsize = fp->fptr; + fp->flag |= FA__WRITTEN; + } +#endif + } + + LEAVE_FF(fp->fs, res); +} + + + +#if _FS_MINIMIZE <= 1 +/*-----------------------------------------------------------------------*/ +/* Create a Directroy Object */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_opendir ( + DIR *dj, /* Pointer to directory object to create */ + const TCHAR *path /* Pointer to the directory path */ +) +{ + FRESULT res; + DEF_NAMEBUF; + + + res = chk_mounted(&path, &dj->fs, 0); + if (res == FR_OK) { + INIT_BUF(*dj); + res = follow_path(dj, path); /* Follow the path to the directory */ + FREE_BUF(); + if (res == FR_OK) { /* Follow completed */ + if (dj->dir) { /* It is not the root dir */ + if (dj->dir[DIR_Attr] & AM_DIR) { /* The object is a directory */ + dj->sclust = LD_CLUST(dj->dir); + } else { /* The object is not a directory */ + res = FR_NO_PATH; + } + } + if (res == FR_OK) { + dj->id = dj->fs->id; + res = dir_sdi(dj, 0); /* Rewind dir */ + } + } + if (res == FR_NO_FILE) res = FR_NO_PATH; + } + + LEAVE_FF(dj->fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Read Directory Entry in Sequense */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_readdir ( + DIR *dj, /* Pointer to the open directory object */ + FILINFO *fno /* Pointer to file information to return */ +) +{ + FRESULT res; + DEF_NAMEBUF; + + + res = validate(dj->fs, dj->id); /* Check validity of the object */ + if (res == FR_OK) { + if (!fno) { + res = dir_sdi(dj, 0); /* Rewind the directory object */ + } else { + INIT_BUF(*dj); + res = dir_read(dj); /* Read an directory item */ + if (res == FR_NO_FILE) { /* Reached end of dir */ + dj->sect = 0; + res = FR_OK; + } + if (res == FR_OK) { /* A valid entry is found */ + get_fileinfo(dj, fno); /* Get the object information */ + res = dir_next(dj, 0); /* Increment index for next */ + if (res == FR_NO_FILE) { + dj->sect = 0; + res = FR_OK; + } + } + FREE_BUF(); + } + } + + LEAVE_FF(dj->fs, res); +} + + + +#if _FS_MINIMIZE == 0 +/*-----------------------------------------------------------------------*/ +/* Get File Status */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_stat ( + const TCHAR *path, /* Pointer to the file path */ + FILINFO *fno /* Pointer to file information to return */ +) +{ + FRESULT res; + DIR dj; + DEF_NAMEBUF; + + + res = chk_mounted(&path, &dj.fs, 0); + if (res == FR_OK) { + INIT_BUF(dj); + res = follow_path(&dj, path); /* Follow the file path */ + if (res == FR_OK) { /* Follow completed */ + if (dj.dir) /* Found an object */ + get_fileinfo(&dj, fno); + else /* It is root dir */ + res = FR_INVALID_NAME; + } + FREE_BUF(); + } + + LEAVE_FF(dj.fs, res); +} + + + +#if !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Get Number of Free Clusters */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_getfree ( + const TCHAR *path, /* Pointer to the logical drive number (root dir) */ + DWORD *nclst, /* Pointer to the variable to return number of free clusters */ + FATFS **fatfs /* Pointer to pointer to corresponding file system object to return */ +) +{ + FRESULT res; + DWORD n, clst, sect, stat; + UINT i; + BYTE fat, *p; + + + /* Get drive number */ + res = chk_mounted(&path, fatfs, 0); + if (res == FR_OK) { + /* If free_clust is valid, return it without full cluster scan */ + if ((*fatfs)->free_clust <= (*fatfs)->n_fatent - 2) { + *nclst = (*fatfs)->free_clust; + } else { + /* Get number of free clusters */ + fat = (*fatfs)->fs_type; + n = 0; + if (fat == FS_FAT12) { + clst = 2; + do { + stat = get_fat(*fatfs, clst); + if (stat == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } + if (stat == 1) { res = FR_INT_ERR; break; } + if (stat == 0) n++; + } while (++clst < (*fatfs)->n_fatent); + } else { + clst = (*fatfs)->n_fatent; + sect = (*fatfs)->fatbase; + i = 0; p = 0; + do { + if (!i) { + res = move_window(*fatfs, sect++); + if (res != FR_OK) break; + p = (*fatfs)->win; + i = SS(*fatfs); + } + if (fat == FS_FAT16) { + if (LD_WORD(p) == 0) n++; + p += 2; i -= 2; + } else { + if ((LD_DWORD(p) & 0x0FFFFFFF) == 0) n++; + p += 4; i -= 4; + } + } while (--clst); + } + (*fatfs)->free_clust = n; + if (fat == FS_FAT32) (*fatfs)->fsi_flag = 1; + *nclst = n; + } + } + LEAVE_FF(*fatfs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Truncate File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_truncate ( + FIL *fp /* Pointer to the file object */ +) +{ + FRESULT res; + DWORD ncl; + + + res = validate(fp->fs, fp->id); /* Check validity of the object */ + if (res == FR_OK) { + if (fp->flag & FA__ERROR) { /* Check abort flag */ + res = FR_INT_ERR; + } else { + if (!(fp->flag & FA_WRITE)) /* Check access mode */ + res = FR_DENIED; + } + } + if (res == FR_OK) { + if (fp->fsize > fp->fptr) { + fp->fsize = fp->fptr; /* Set file size to current R/W point */ + fp->flag |= FA__WRITTEN; + if (fp->fptr == 0) { /* When set file size to zero, remove entire cluster chain */ + res = remove_chain(fp->fs, fp->sclust); + fp->sclust = 0; + } else { /* When truncate a part of the file, remove remaining clusters */ + ncl = get_fat(fp->fs, fp->clust); + res = FR_OK; + if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR; + if (ncl == 1) res = FR_INT_ERR; + if (res == FR_OK && ncl < fp->fs->n_fatent) { + res = put_fat(fp->fs, fp->clust, 0x0FFFFFFF); + if (res == FR_OK) res = remove_chain(fp->fs, ncl); + } + } + } + if (res != FR_OK) fp->flag |= FA__ERROR; + } + + LEAVE_FF(fp->fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Delete a File or Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_unlink ( + const TCHAR *path /* Pointer to the file or directory path */ +) +{ + FRESULT res; + DIR dj, sdj; + BYTE *dir; + DWORD dclst; + DEF_NAMEBUF; + + + res = chk_mounted(&path, &dj.fs, 1); + if (res == FR_OK) { + INIT_BUF(dj); + res = follow_path(&dj, path); /* Follow the file path */ + if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT)) + res = FR_INVALID_NAME; /* Cannot remove dot entry */ +#if _FS_SHARE + if (res == FR_OK) res = chk_lock(&dj, 2); /* Cannot remove open file */ +#endif + if (res == FR_OK) { /* The object is accessible */ + dir = dj.dir; + if (!dir) { + res = FR_INVALID_NAME; /* Cannot remove the start directory */ + } else { + if (dir[DIR_Attr] & AM_RDO) + res = FR_DENIED; /* Cannot remove R/O object */ + } + dclst = LD_CLUST(dir); + if (res == FR_OK && (dir[DIR_Attr] & AM_DIR)) { /* Is it a sub-dir? */ + if (dclst < 2) { + res = FR_INT_ERR; + } else { + mem_cpy(&sdj, &dj, sizeof(DIR)); /* Check if the sub-dir is empty or not */ + sdj.sclust = dclst; + res = dir_sdi(&sdj, 2); /* Exclude dot entries */ + if (res == FR_OK) { + res = dir_read(&sdj); + if (res == FR_OK /* Not empty dir */ +#if _FS_RPATH + || dclst == sdj.fs->cdir /* Current dir */ +#endif + ) res = FR_DENIED; + if (res == FR_NO_FILE) res = FR_OK; /* Empty */ + } + } + } + if (res == FR_OK) { + res = dir_remove(&dj); /* Remove the directory entry */ + if (res == FR_OK) { + if (dclst) /* Remove the cluster chain if exist */ + res = remove_chain(dj.fs, dclst); + if (res == FR_OK) res = sync(dj.fs); + } + } + } + FREE_BUF(); + } + LEAVE_FF(dj.fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Create a Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_mkdir ( + const TCHAR *path /* Pointer to the directory path */ +) +{ + FRESULT res; + DIR dj; + BYTE *dir, n; + DWORD dsc, dcl, pcl, tim = get_fattime(); + DEF_NAMEBUF; + + + res = chk_mounted(&path, &dj.fs, 1); + if (res == FR_OK) { + INIT_BUF(dj); + res = follow_path(&dj, path); /* Follow the file path */ + if (res == FR_OK) res = FR_EXIST; /* Any object with same name is already existing */ + if (_FS_RPATH && res == FR_NO_FILE && (dj.fn[NS] & NS_DOT)) + res = FR_INVALID_NAME; + if (res == FR_NO_FILE) { /* Can create a new directory */ + dcl = create_chain(dj.fs, 0); /* Allocate a cluster for the new directory table */ + res = FR_OK; + if (dcl == 0) res = FR_DENIED; /* No space to allocate a new cluster */ + if (dcl == 1) res = FR_INT_ERR; + if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR; + if (res == FR_OK) /* Flush FAT */ + res = move_window(dj.fs, 0); + if (res == FR_OK) { /* Initialize the new directory table */ + dsc = clust2sect(dj.fs, dcl); + dir = dj.fs->win; + mem_set(dir, 0, SS(dj.fs)); + mem_set(dir+DIR_Name, ' ', 8+3); /* Create "." entry */ + dir[DIR_Name] = '.'; + dir[DIR_Attr] = AM_DIR; + ST_DWORD(dir+DIR_WrtTime, tim); + ST_CLUST(dir, dcl); + mem_cpy(dir+SZ_DIR, dir, SZ_DIR); /* Create ".." entry */ + dir[33] = '.'; pcl = dj.sclust; + if (dj.fs->fs_type == FS_FAT32 && pcl == dj.fs->dirbase) + pcl = 0; + ST_CLUST(dir+SZ_DIR, pcl); + for (n = dj.fs->csize; n; n--) { /* Write dot entries and clear following sectors */ + dj.fs->winsect = dsc++; + dj.fs->wflag = 1; + res = move_window(dj.fs, 0); + if (res != FR_OK) break; + mem_set(dir, 0, SS(dj.fs)); + } + } + if (res == FR_OK) res = dir_register(&dj); /* Register the object to the directoy */ + if (res != FR_OK) { + remove_chain(dj.fs, dcl); /* Could not register, remove cluster chain */ + } else { + dir = dj.dir; + dir[DIR_Attr] = AM_DIR; /* Attribute */ + ST_DWORD(dir+DIR_WrtTime, tim); /* Created time */ + ST_CLUST(dir, dcl); /* Table start cluster */ + dj.fs->wflag = 1; + res = sync(dj.fs); + } + } + FREE_BUF(); + } + + LEAVE_FF(dj.fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Change Attribute */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_chmod ( + const TCHAR *path, /* Pointer to the file path */ + BYTE value, /* Attribute bits */ + BYTE mask /* Attribute mask to change */ +) +{ + FRESULT res; + DIR dj; + BYTE *dir; + DEF_NAMEBUF; + + + res = chk_mounted(&path, &dj.fs, 1); + if (res == FR_OK) { + INIT_BUF(dj); + res = follow_path(&dj, path); /* Follow the file path */ + FREE_BUF(); + if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT)) + res = FR_INVALID_NAME; + if (res == FR_OK) { + dir = dj.dir; + if (!dir) { /* Is it a root directory? */ + res = FR_INVALID_NAME; + } else { /* File or sub directory */ + mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC; /* Valid attribute mask */ + dir[DIR_Attr] = (value & mask) | (dir[DIR_Attr] & (BYTE)~mask); /* Apply attribute change */ + dj.fs->wflag = 1; + res = sync(dj.fs); + } + } + } + + LEAVE_FF(dj.fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Change Timestamp */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_utime ( + const TCHAR *path, /* Pointer to the file/directory name */ + const FILINFO *fno /* Pointer to the time stamp to be set */ +) +{ + FRESULT res; + DIR dj; + BYTE *dir; + DEF_NAMEBUF; + + + res = chk_mounted(&path, &dj.fs, 1); + if (res == FR_OK) { + INIT_BUF(dj); + res = follow_path(&dj, path); /* Follow the file path */ + FREE_BUF(); + if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT)) + res = FR_INVALID_NAME; + if (res == FR_OK) { + dir = dj.dir; + if (!dir) { /* Root directory */ + res = FR_INVALID_NAME; + } else { /* File or sub-directory */ + ST_WORD(dir+DIR_WrtTime, fno->ftime); + ST_WORD(dir+DIR_WrtDate, fno->fdate); + dj.fs->wflag = 1; + res = sync(dj.fs); + } + } + } + + LEAVE_FF(dj.fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Rename File/Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_rename ( + const TCHAR *path_old, /* Pointer to the old name */ + const TCHAR *path_new /* Pointer to the new name */ +) +{ + FRESULT res; + DIR djo, djn; + BYTE buf[21], *dir; + DWORD dw; + DEF_NAMEBUF; + + + res = chk_mounted(&path_old, &djo.fs, 1); + if (res == FR_OK) { + djn.fs = djo.fs; + INIT_BUF(djo); + res = follow_path(&djo, path_old); /* Check old object */ + if (_FS_RPATH && res == FR_OK && (djo.fn[NS] & NS_DOT)) + res = FR_INVALID_NAME; +#if _FS_SHARE + if (res == FR_OK) res = chk_lock(&djo, 2); +#endif + if (res == FR_OK) { /* Old object is found */ + if (!djo.dir) { /* Is root dir? */ + res = FR_NO_FILE; + } else { + mem_cpy(buf, djo.dir+DIR_Attr, 21); /* Save the object information except for name */ + mem_cpy(&djn, &djo, sizeof(DIR)); /* Check new object */ + res = follow_path(&djn, path_new); + if (res == FR_OK) res = FR_EXIST; /* The new object name is already existing */ + if (res == FR_NO_FILE) { /* Is it a valid path and no name collision? */ +/* Start critical section that any interruption or error can cause cross-link */ + res = dir_register(&djn); /* Register the new entry */ + if (res == FR_OK) { + dir = djn.dir; /* Copy object information except for name */ + mem_cpy(dir+13, buf+2, 19); + dir[DIR_Attr] = buf[0] | AM_ARC; + djo.fs->wflag = 1; + if (djo.sclust != djn.sclust && (dir[DIR_Attr] & AM_DIR)) { /* Update .. entry in the directory if needed */ + dw = clust2sect(djn.fs, LD_CLUST(dir)); + if (!dw) { + res = FR_INT_ERR; + } else { + res = move_window(djn.fs, dw); + dir = djn.fs->win+SZ_DIR; /* .. entry */ + if (res == FR_OK && dir[1] == '.') { + dw = (djn.fs->fs_type == FS_FAT32 && djn.sclust == djn.fs->dirbase) ? 0 : djn.sclust; + ST_CLUST(dir, dw); + djn.fs->wflag = 1; + } + } + } + if (res == FR_OK) { + res = dir_remove(&djo); /* Remove old entry */ + if (res == FR_OK) + res = sync(djo.fs); + } + } +/* End critical section */ + } + } + } + FREE_BUF(); + } + LEAVE_FF(djo.fs, res); +} + +#endif /* !_FS_READONLY */ +#endif /* _FS_MINIMIZE == 0 */ +#endif /* _FS_MINIMIZE <= 1 */ +#endif /* _FS_MINIMIZE <= 2 */ + + + +/*-----------------------------------------------------------------------*/ +/* Forward data to the stream directly (available on only tiny cfg) */ +/*-----------------------------------------------------------------------*/ +#if _USE_FORWARD && _FS_TINY + +FRESULT f_forward ( + FIL *fp, /* Pointer to the file object */ + UINT (*func)(const BYTE*,UINT), /* Pointer to the streaming function */ + UINT btr, /* Number of bytes to forward */ + UINT *bf /* Pointer to number of bytes forwarded */ +) +{ + FRESULT res; + DWORD remain, clst, sect; + UINT rcnt; + BYTE csect; + + + *bf = 0; /* Initialize byte counter */ + + res = validate(fp->fs, fp->id); /* Check validity of the object */ + if (res != FR_OK) LEAVE_FF(fp->fs, res); + if (fp->flag & FA__ERROR) /* Check error flag */ + LEAVE_FF(fp->fs, FR_INT_ERR); + if (!(fp->flag & FA_READ)) /* Check access mode */ + LEAVE_FF(fp->fs, FR_DENIED); + + remain = fp->fsize - fp->fptr; + if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */ + + for ( ; btr && (*func)(0, 0); /* Repeat until all data transferred or stream becomes busy */ + fp->fptr += rcnt, *bf += rcnt, btr -= rcnt) { + csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */ + if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ + if (!csect) { /* On the cluster boundary? */ + clst = (fp->fptr == 0) ? /* On the top of the file? */ + fp->sclust : get_fat(fp->fs, fp->clust); + if (clst <= 1) ABORT(fp->fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + fp->clust = clst; /* Update current cluster */ + } + } + sect = clust2sect(fp->fs, fp->clust); /* Get current data sector */ + if (!sect) ABORT(fp->fs, FR_INT_ERR); + sect += csect; + if (move_window(fp->fs, sect)) /* Move sector window */ + ABORT(fp->fs, FR_DISK_ERR); + fp->dsect = sect; + rcnt = SS(fp->fs) - (WORD)(fp->fptr % SS(fp->fs)); /* Forward data from sector window */ + if (rcnt > btr) rcnt = btr; + rcnt = (*func)(&fp->fs->win[(WORD)fp->fptr % SS(fp->fs)], rcnt); + if (!rcnt) ABORT(fp->fs, FR_INT_ERR); + } + + LEAVE_FF(fp->fs, FR_OK); +} +#endif /* _USE_FORWARD */ + + + +#if _USE_MKFS && !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Create File System on the Drive */ +/*-----------------------------------------------------------------------*/ +#define N_ROOTDIR 512 /* Number of root dir entries for FAT12/16 */ +#define N_FATS 1 /* Number of FAT copies (1 or 2) */ + + +FRESULT f_mkfs ( + BYTE drv, /* Logical drive number */ + BYTE sfd, /* Partitioning rule 0:FDISK, 1:SFD */ + UINT au /* Allocation unit size [bytes] */ +) +{ + static const WORD vst[] = { 1024, 512, 256, 128, 64, 32, 16, 8, 4, 2, 0}; + static const WORD cst[] = {32768, 16384, 8192, 4096, 2048, 16384, 8192, 4096, 2048, 1024, 512}; + BYTE fmt, md, sys, *tbl, pdrv, part; + DWORD n_clst, vs, n, wsect; + UINT i; + DWORD b_vol, b_fat, b_dir, b_data; /* LBA */ + DWORD n_vol, n_rsv, n_fat, n_dir; /* Size */ + FATFS *fs; + DSTATUS stat; + + + /* Check mounted drive and clear work area */ + if (drv >= _VOLUMES) return FR_INVALID_DRIVE; + if (sfd > 1) return FR_INVALID_PARAMETER; + if (au & (au - 1)) return FR_INVALID_PARAMETER; + fs = FatFs[drv]; + if (!fs) return FR_NOT_ENABLED; + fs->fs_type = 0; + pdrv = LD2PD(drv); /* Physical drive */ + part = LD2PT(drv); /* Partition (0:auto detect, 1-4:get from partition table)*/ + + /* Get disk statics */ + stat = disk_initialize(pdrv); + if (stat & STA_NOINIT) return FR_NOT_READY; + if (stat & STA_PROTECT) return FR_WRITE_PROTECTED; +#if _MAX_SS != 512 /* Get disk sector size */ + if (disk_ioctl(pdrv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK || SS(fs) > _MAX_SS) + return FR_DISK_ERR; +#endif + if (_MULTI_PARTITION && part) { + /* Get partition information from partition table in the MBR */ + if (disk_read(pdrv, fs->win, 0, 1) != RES_OK) return FR_DISK_ERR; + if (LD_WORD(fs->win+BS_55AA) != 0xAA55) return FR_MKFS_ABORTED; + tbl = &fs->win[MBR_Table + (part - 1) * SZ_PTE]; + if (!tbl[4]) return FR_MKFS_ABORTED; /* No partition? */ + b_vol = LD_DWORD(tbl+8); /* Volume start sector */ + n_vol = LD_DWORD(tbl+12); /* Volume size */ + } else { + /* Create a partition in this function */ + if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &n_vol) != RES_OK || n_vol < 128) + return FR_DISK_ERR; + b_vol = (sfd) ? 0 : 63; /* Volume start sector */ + n_vol -= b_vol; /* Volume size */ + } + + if (!au) { /* AU auto selection */ + vs = n_vol / (2000 / (SS(fs) / 512)); + for (i = 0; vs < vst[i]; i++) ; + au = cst[i]; + } + au /= SS(fs); /* Number of sectors per cluster */ + if (au == 0) au = 1; + if (au > 128) au = 128; + + /* Pre-compute number of clusters and FAT syb-type */ + n_clst = n_vol / au; + fmt = FS_FAT12; + if (n_clst >= MIN_FAT16) fmt = FS_FAT16; + if (n_clst >= MIN_FAT32) fmt = FS_FAT32; + + /* Determine offset and size of FAT structure */ + if (fmt == FS_FAT32) { + n_fat = ((n_clst * 4) + 8 + SS(fs) - 1) / SS(fs); + n_rsv = 32; + n_dir = 0; + } else { + n_fat = (fmt == FS_FAT12) ? (n_clst * 3 + 1) / 2 + 3 : (n_clst * 2) + 4; + n_fat = (n_fat + SS(fs) - 1) / SS(fs); + n_rsv = 1; + n_dir = (DWORD)N_ROOTDIR * SZ_DIR / SS(fs); + } + b_fat = b_vol + n_rsv; /* FAT area start sector */ + b_dir = b_fat + n_fat * N_FATS; /* Directory area start sector */ + b_data = b_dir + n_dir; /* Data area start sector */ + if (n_vol < b_data + au - b_vol) return FR_MKFS_ABORTED; /* Too small volume */ + + /* Align data start sector to erase block boundary (for flash memory media) */ + if (disk_ioctl(pdrv, GET_BLOCK_SIZE, &n) != RES_OK || !n || n > 32768) n = 1; + n = (b_data + n - 1) & ~(n - 1); /* Next nearest erase block from current data start */ + n = (n - b_data) / N_FATS; + if (fmt == FS_FAT32) { /* FAT32: Move FAT offset */ + n_rsv += n; + b_fat += n; + } else { /* FAT12/16: Expand FAT size */ + n_fat += n; + } + + /* Determine number of clusters and final check of validity of the FAT sub-type */ + n_clst = (n_vol - n_rsv - n_fat * N_FATS - n_dir) / au; + if ( (fmt == FS_FAT16 && n_clst < MIN_FAT16) + || (fmt == FS_FAT32 && n_clst < MIN_FAT32)) + return FR_MKFS_ABORTED; + + switch (fmt) { /* Determine system ID for partition table */ + case FS_FAT12: sys = 0x01; break; + case FS_FAT16: sys = (n_vol < 0x10000) ? 0x04 : 0x06; break; + default: sys = 0x0C; + } + + if (_MULTI_PARTITION && part) { + /* Update system ID in the partition table */ + tbl = &fs->win[MBR_Table + (part - 1) * SZ_PTE]; + tbl[4] = sys; + if (disk_write(pdrv, fs->win, 0, 1) != RES_OK) return FR_DISK_ERR; + md = 0xF8; + } else { + if (sfd) { /* No patition table (SFD) */ + md = 0xF0; + } else { /* Create partition table (FDISK) */ + mem_set(fs->win, 0, SS(fs)); + tbl = fs->win+MBR_Table; /* Create partiton table for single partition in the drive */ + tbl[1] = 1; /* Partition start head */ + tbl[2] = 1; /* Partition start sector */ + tbl[3] = 0; /* Partition start cylinder */ + tbl[4] = sys; /* System type */ + tbl[5] = 254; /* Partition end head */ + n = (b_vol + n_vol) / 63 / 255; + tbl[6] = (BYTE)((n >> 2) | 63); /* Partiiton end sector */ + tbl[7] = (BYTE)n; /* End cylinder */ + ST_DWORD(tbl+8, 63); /* Partition start in LBA */ + ST_DWORD(tbl+12, n_vol); /* Partition size in LBA */ + ST_WORD(fs->win+BS_55AA, 0xAA55); /* MBR signature */ + if (disk_write(pdrv, fs->win, 0, 1) != RES_OK) /* Write it to the MBR sector */ + return FR_DISK_ERR; + md = 0xF8; + } + } + + /* Create BPB in the VBR */ + tbl = fs->win; /* Clear sector */ + mem_set(tbl, 0, SS(fs)); + mem_cpy(tbl, "\xEB\xFE\x90" "MSDOS5.0", 11);/* Boot jump code, OEM name */ + i = SS(fs); /* Sector size */ + ST_WORD(tbl+BPB_BytsPerSec, i); + tbl[BPB_SecPerClus] = (BYTE)au; /* Sectors per cluster */ + ST_WORD(tbl+BPB_RsvdSecCnt, n_rsv); /* Reserved sectors */ + tbl[BPB_NumFATs] = N_FATS; /* Number of FATs */ + i = (fmt == FS_FAT32) ? 0 : N_ROOTDIR; /* Number of rootdir entries */ + ST_WORD(tbl+BPB_RootEntCnt, i); + if (n_vol < 0x10000) { /* Number of total sectors */ + ST_WORD(tbl+BPB_TotSec16, n_vol); + } else { + ST_DWORD(tbl+BPB_TotSec32, n_vol); + } + tbl[BPB_Media] = md; /* Media descriptor */ + ST_WORD(tbl+BPB_SecPerTrk, 63); /* Number of sectors per track */ + ST_WORD(tbl+BPB_NumHeads, 255); /* Number of heads */ + ST_DWORD(tbl+BPB_HiddSec, b_vol); /* Hidden sectors */ + n = get_fattime(); /* Use current time as VSN */ + if (fmt == FS_FAT32) { + ST_DWORD(tbl+BS_VolID32, n); /* VSN */ + ST_DWORD(tbl+BPB_FATSz32, n_fat); /* Number of sectors per FAT */ + ST_DWORD(tbl+BPB_RootClus, 2); /* Root directory start cluster (2) */ + ST_WORD(tbl+BPB_FSInfo, 1); /* FSInfo record offset (VBR+1) */ + ST_WORD(tbl+BPB_BkBootSec, 6); /* Backup boot record offset (VBR+6) */ + tbl[BS_DrvNum32] = 0x80; /* Drive number */ + tbl[BS_BootSig32] = 0x29; /* Extended boot signature */ + mem_cpy(tbl+BS_VolLab32, "NO NAME " "FAT32 ", 19); /* Volume label, FAT signature */ + } else { + ST_DWORD(tbl+BS_VolID, n); /* VSN */ + ST_WORD(tbl+BPB_FATSz16, n_fat); /* Number of sectors per FAT */ + tbl[BS_DrvNum] = 0x80; /* Drive number */ + tbl[BS_BootSig] = 0x29; /* Extended boot signature */ + mem_cpy(tbl+BS_VolLab, "NO NAME " "FAT ", 19); /* Volume label, FAT signature */ + } + ST_WORD(tbl+BS_55AA, 0xAA55); /* Signature (Offset is fixed here regardless of sector size) */ + if (disk_write(pdrv, tbl, b_vol, 1) != RES_OK) /* Write it to the VBR sector */ + return FR_DISK_ERR; + if (fmt == FS_FAT32) /* Write backup VBR if needed (VBR+6) */ + disk_write(pdrv, tbl, b_vol + 6, 1); + + /* Initialize FAT area */ + wsect = b_fat; + for (i = 0; i < N_FATS; i++) { /* Initialize each FAT copy */ + mem_set(tbl, 0, SS(fs)); /* 1st sector of the FAT */ + n = md; /* Media descriptor byte */ + if (fmt != FS_FAT32) { + n |= (fmt == FS_FAT12) ? 0x00FFFF00 : 0xFFFFFF00; + ST_DWORD(tbl+0, n); /* Reserve cluster #0-1 (FAT12/16) */ + } else { + n |= 0xFFFFFF00; + ST_DWORD(tbl+0, n); /* Reserve cluster #0-1 (FAT32) */ + ST_DWORD(tbl+4, 0xFFFFFFFF); + ST_DWORD(tbl+8, 0x0FFFFFFF); /* Reserve cluster #2 for root dir */ + } + if (disk_write(pdrv, tbl, wsect++, 1) != RES_OK) + return FR_DISK_ERR; + mem_set(tbl, 0, SS(fs)); /* Fill following FAT entries with zero */ + for (n = 1; n < n_fat; n++) { /* This loop may take a time on FAT32 volume due to many single sector writes */ + if (disk_write(pdrv, tbl, wsect++, 1) != RES_OK) + return FR_DISK_ERR; + } + } + + /* Initialize root directory */ + i = (fmt == FS_FAT32) ? au : n_dir; + do { + if (disk_write(pdrv, tbl, wsect++, 1) != RES_OK) + return FR_DISK_ERR; + } while (--i); + +#if _USE_ERASE /* Erase data area if needed */ + { + DWORD eb[2]; + + eb[0] = wsect; eb[1] = wsect + (n_clst - ((fmt == FS_FAT32) ? 1 : 0)) * au - 1; + disk_ioctl(pdrv, CTRL_ERASE_SECTOR, eb); + } +#endif + + /* Create FSInfo if needed */ + if (fmt == FS_FAT32) { + ST_DWORD(tbl+FSI_LeadSig, 0x41615252); + ST_DWORD(tbl+FSI_StrucSig, 0x61417272); + ST_DWORD(tbl+FSI_Free_Count, n_clst - 1); /* Number of free clusters */ + ST_DWORD(tbl+FSI_Nxt_Free, 2); /* Last allocated cluster# */ + ST_WORD(tbl+BS_55AA, 0xAA55); + disk_write(pdrv, tbl, b_vol + 1, 1); /* Write original (VBR+1) */ + disk_write(pdrv, tbl, b_vol + 7, 1); /* Write backup (VBR+7) */ + } + + return (disk_ioctl(pdrv, CTRL_SYNC, 0) == RES_OK) ? FR_OK : FR_DISK_ERR; +} + + +#if _MULTI_PARTITION == 2 +/*-----------------------------------------------------------------------*/ +/* Divide Physical Drive */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_fdisk ( + BYTE pdrv, /* Physical drive number */ + const DWORD szt[], /* Pointer to the size table for each partitions */ + void* work /* Pointer to the working buffer */ +) +{ + UINT i, n, sz_cyl, tot_cyl, b_cyl, e_cyl, p_cyl; + BYTE s_hd, e_hd, *p, *buf = (BYTE*)work; + DSTATUS stat; + DWORD sz_disk, sz_part, s_part; + + + stat = disk_initialize(pdrv); + if (stat & STA_NOINIT) return FR_NOT_READY; + if (stat & STA_PROTECT) return FR_WRITE_PROTECTED; + if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_disk)) return FR_DISK_ERR; + + /* Determine CHS in the table regardless of the drive geometry */ + for (n = 16; n < 256 && sz_disk / n / 63 > 1024; n *= 2) ; + if (n == 256) n--; + e_hd = n - 1; + sz_cyl = 63 * n; + tot_cyl = sz_disk / sz_cyl; + + /* Create partition table */ + mem_set(buf, 0, _MAX_SS); + p = buf + MBR_Table; b_cyl = 0; + for (i = 0; i < 4; i++, p += SZ_PTE) { + p_cyl = (szt[i] <= 100) ? (DWORD)tot_cyl * szt[i] / 100 : szt[i] / sz_cyl; + if (!p_cyl) continue; + s_part = (DWORD)sz_cyl * b_cyl; + sz_part = (DWORD)sz_cyl * p_cyl; + if (i == 0) { /* Exclude first track of cylinder 0 */ + s_hd = 1; + s_part += 63; sz_part -= 63; + } else { + s_hd = 0; + } + e_cyl = b_cyl + p_cyl - 1; + if (e_cyl >= tot_cyl) return FR_INVALID_PARAMETER; + + /* Set partition table */ + p[1] = s_hd; /* Start head */ + p[2] = (BYTE)((b_cyl >> 2) + 1); /* Start sector */ + p[3] = (BYTE)b_cyl; /* Start cylinder */ + p[4] = 0x06; /* System type (temporary setting) */ + p[5] = e_hd; /* End head */ + p[6] = (BYTE)((e_cyl >> 2) + 63); /* End sector */ + p[7] = (BYTE)e_cyl; /* End cylinder */ + ST_DWORD(p + 8, s_part); /* Start sector in LBA */ + ST_DWORD(p + 12, sz_part); /* Partition size */ + + /* Next partition */ + b_cyl += p_cyl; + } + ST_WORD(p, 0xAA55); + + /* Write it to the MBR */ + return (disk_write(pdrv, buf, 0, 1) || disk_ioctl(pdrv, CTRL_SYNC, 0)) ? FR_DISK_ERR : FR_OK; +} + + +#endif /* _MULTI_PARTITION == 2 */ +#endif /* _USE_MKFS && !_FS_READONLY */ + + + + +#if _USE_STRFUNC +/*-----------------------------------------------------------------------*/ +/* Get a string from the file */ +/*-----------------------------------------------------------------------*/ +TCHAR* f_gets ( + TCHAR* buff, /* Pointer to the string buffer to read */ + int len, /* Size of string buffer (characters) */ + FIL* fil /* Pointer to the file object */ +) +{ + int n = 0; + TCHAR c, *p = buff; + BYTE s[2]; + UINT rc; + + + while (n < len - 1) { /* Read bytes until buffer gets filled */ + f_read(fil, s, 1, &rc); + if (rc != 1) break; /* Break on EOF or error */ + c = s[0]; +#if _LFN_UNICODE /* Read a character in UTF-8 encoding */ + if (c >= 0x80) { + if (c < 0xC0) continue; /* Skip stray trailer */ + if (c < 0xE0) { /* Two-byte sequense */ + f_read(fil, s, 1, &rc); + if (rc != 1) break; + c = ((c & 0x1F) << 6) | (s[0] & 0x3F); + if (c < 0x80) c = '?'; + } else { + if (c < 0xF0) { /* Three-byte sequense */ + f_read(fil, s, 2, &rc); + if (rc != 2) break; + c = (c << 12) | ((s[0] & 0x3F) << 6) | (s[1] & 0x3F); + if (c < 0x800) c = '?'; + } else { /* Reject four-byte sequense */ + c = '?'; + } + } + } +#endif +#if _USE_STRFUNC >= 2 + if (c == '\r') continue; /* Strip '\r' */ +#endif + *p++ = c; + n++; + if (c == '\n') break; /* Break on EOL */ + } + *p = 0; + return n ? buff : 0; /* When no data read (eof or error), return with error. */ +} + + + +#if !_FS_READONLY +#include +/*-----------------------------------------------------------------------*/ +/* Put a character to the file */ +/*-----------------------------------------------------------------------*/ +int f_putc ( + TCHAR c, /* A character to be output */ + FIL* fil /* Pointer to the file object */ +) +{ + UINT bw, btw; + BYTE s[3]; + + +#if _USE_STRFUNC >= 2 + if (c == '\n') f_putc ('\r', fil); /* LF -> CRLF conversion */ +#endif + +#if _LFN_UNICODE /* Write the character in UTF-8 encoding */ + if (c < 0x80) { /* 7-bit */ + s[0] = (BYTE)c; + btw = 1; + } else { + if (c < 0x800) { /* 11-bit */ + s[0] = (BYTE)(0xC0 | (c >> 6)); + s[1] = (BYTE)(0x80 | (c & 0x3F)); + btw = 2; + } else { /* 16-bit */ + s[0] = (BYTE)(0xE0 | (c >> 12)); + s[1] = (BYTE)(0x80 | ((c >> 6) & 0x3F)); + s[2] = (BYTE)(0x80 | (c & 0x3F)); + btw = 3; + } + } +#else /* Write the character without conversion */ + s[0] = (BYTE)c; + btw = 1; +#endif + f_write(fil, s, btw, &bw); /* Write the char to the file */ + return (bw == btw) ? 1 : EOF; /* Return the result */ +} + + + + +/*-----------------------------------------------------------------------*/ +/* Put a string to the file */ +/*-----------------------------------------------------------------------*/ +int f_puts ( + const TCHAR* str, /* Pointer to the string to be output */ + FIL* fil /* Pointer to the file object */ +) +{ + int n; + + + for (n = 0; *str; str++, n++) { + if (f_putc(*str, fil) == EOF) return EOF; + } + return n; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Put a formatted string to the file */ +/*-----------------------------------------------------------------------*/ +int f_printf ( + FIL* fil, /* Pointer to the file object */ + const TCHAR* str, /* Pointer to the format string */ + ... /* Optional arguments... */ +) +{ + va_list arp; + int result; + + va_start(arp, str); + result = f_vprintf(fil, str, arp); + va_end(arp); + + return result; +} + +int f_vprintf( + FIL* fil, /* Pointer to the file object */ + const TCHAR* str, /* Pointer to the format string */ + va_list arp /* Variable argument list containing the data to print*/ +) +{ + BYTE f, r; + UINT i, j, w; + ULONG v; + TCHAR c, d, s[16], *p; + int res, chc, cc; + + for (cc = res = 0; cc != EOF; res += cc) { + c = *str++; + if (c == 0) break; /* End of string */ + if (c != '%') { /* Non escape character */ + cc = f_putc(c, fil); + if (cc != EOF) cc = 1; + continue; + } + w = f = 0; + c = *str++; + if (c == '0') { /* Flag: '0' padding */ + f = 1; c = *str++; + } else { + if (c == '-') { /* Flag: left justified */ + f = 2; c = *str++; + } + } + while (IsDigit(c)) { /* Precision */ + w = w * 10 + c - '0'; + c = *str++; + } + if (c == 'l' || c == 'L') { /* Prefix: Size is long int */ + f |= 4; c = *str++; + } + if (!c) break; + d = c; + if (IsLower(d)) d -= 0x20; + switch (d) { /* Type is... */ + case 'S' : /* String */ + p = va_arg(arp, TCHAR*); + for (j = 0; p[j]; j++) ; + chc = 0; + if (!(f & 2)) { + while (j++ < w) chc += (cc = f_putc(' ', fil)); + } + chc += (cc = f_puts(p, fil)); + while (j++ < w) chc += (cc = f_putc(' ', fil)); + if (cc != EOF) cc = chc; + continue; + case 'C' : /* Character */ + cc = f_putc((TCHAR)va_arg(arp, int), fil); continue; + case 'B' : /* Binary */ + r = 2; break; + case 'O' : /* Octal */ + r = 8; break; + case 'D' : /* Signed decimal */ + case 'U' : /* Unsigned decimal */ + r = 10; break; + case 'X' : /* Hexdecimal */ + r = 16; break; + default: /* Unknown type (passthrough) */ + cc = f_putc(c, fil); continue; + } + + /* Get an argument and put it in numeral */ + v = (f & 4) ? (ULONG)va_arg(arp, long) : ((d == 'D') ? (ULONG)(long)va_arg(arp, int) : (ULONG)va_arg(arp, unsigned int)); + if (d == 'D' && (v & 0x80000000)) { + v = 0 - v; + f |= 8; + } + i = 0; + do { + d = (TCHAR)(v % r); v /= r; + if (d > 9) d += (c == 'x') ? 0x27 : 0x07; + s[i++] = d + '0'; + } while (v && i < sizeof(s) / sizeof(s[0])); + if (f & 8) s[i++] = '-'; + j = i; d = (f & 1) ? '0' : ' '; + res = 0; + while (!(f & 2) && j++ < w) res += (cc = f_putc(d, fil)); + do res += (cc = f_putc(s[--i], fil)); while(i); + while (j++ < w) res += (cc = f_putc(' ', fil)); + if (cc != EOF) cc = res; + } + + return (cc == EOF) ? cc : res; +} + +#endif /* !_FS_READONLY */ +#endif /* _USE_STRFUNC */ + +//@} diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/src/ff.h b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/src/ff.h new file mode 100644 index 000000000..5644d6d5f --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/src/ff.h @@ -0,0 +1,339 @@ +/*---------------------------------------------------------------------------/ +/ FatFs - FAT file system module include file R0.09 (C)ChaN, 2011 +/----------------------------------------------------------------------------/ +/ FatFs module is a generic FAT file system module for small embedded systems. +/ This is a free software that opened for education, research and commercial +/ developments under license policy of following trems. +/ +/ Copyright (C) 2011, ChaN, all right reserved. +/ +/ * The FatFs module is a free software and there is NO WARRANTY. +/ * No restriction on use. You can use, modify and redistribute it for +/ personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY. +/ * Redistributions of source code must retain the above copyright notice. +/ +/----------------------------------------------------------------------------*/ +#include + +#ifndef _FATFS +#define _FATFS 6502 /* Revision ID */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "integer.h" /* Basic integer types */ +#include "ffconf.h" /* FatFs configuration options */ + +#if _FATFS != _FFCONF +#error Wrong configuration file (ffconf.h). +#endif + + + +/* Definitions of volume management */ + +#if _MULTI_PARTITION /* Multiple partition configuration */ +typedef struct { + BYTE pd; /* Physical drive number */ + BYTE pt; /* Partition: 0:Auto detect, 1-4:Forced partition) */ +} PARTITION; +extern PARTITION VolToPart[]; /* Volume - Partition resolution table */ +#define LD2PD(vol) (VolToPart[vol].pd) /* Get physical drive number */ +#define LD2PT(vol) (VolToPart[vol].pt) /* Get partition index */ + +#else /* Single partition configuration */ +#define LD2PD(vol) (vol) /* Each logical drive is bound to the same physical drive number */ +#define LD2PT(vol) 0 /* Always mounts the 1st partition or in SFD */ + +#endif + + + +/* Type of path name strings on FatFs API */ + +#if _LFN_UNICODE /* Unicode string */ +#if !_USE_LFN +#error _LFN_UNICODE must be 0 in non-LFN cfg. +#endif +#ifndef _INC_TCHAR +typedef WCHAR TCHAR; +#define _T(x) L ## x +#define _TEXT(x) L ## x +#endif + +#else /* ANSI/OEM string */ +#ifndef _INC_TCHAR +typedef char TCHAR; +#define _T(x) x +#define _TEXT(x) x +#endif + +#endif + + + +/* File system object structure (FATFS) */ + +typedef struct { + BYTE fs_type; /* FAT sub-type (0:Not mounted) */ + BYTE drv; /* Physical drive number */ + BYTE csize; /* Sectors per cluster (1,2,4...128) */ + BYTE n_fats; /* Number of FAT copies (1,2) */ + BYTE wflag; /* win[] dirty flag (1:must be written back) */ + BYTE fsi_flag; /* fsinfo dirty flag (1:must be written back) */ + WORD id; /* File system mount ID */ + WORD n_rootdir; /* Number of root directory entries (FAT12/16) */ +#if _MAX_SS != 512 + WORD ssize; /* Bytes per sector (512, 1024, 2048 or 4096) */ +#endif +#if _FS_REENTRANT + _SYNC_t sobj; /* Identifier of sync object */ +#endif +#if !_FS_READONLY + DWORD last_clust; /* Last allocated cluster */ + DWORD free_clust; /* Number of free clusters */ + DWORD fsi_sector; /* fsinfo sector (FAT32) */ +#endif +#if _FS_RPATH + DWORD cdir; /* Current directory start cluster (0:root) */ +#endif + DWORD n_fatent; /* Number of FAT entries (= number of clusters + 2) */ + DWORD fsize; /* Sectors per FAT */ + DWORD fatbase; /* FAT start sector */ + DWORD dirbase; /* Root directory start sector (FAT32:Cluster#) */ + DWORD database; /* Data start sector */ + DWORD winsect; /* Current sector appearing in the win[] */ + BYTE win[_MAX_SS]; /* Disk access window for Directory, FAT (and Data on tiny cfg) */ +} FATFS; + + + +/* File object structure (FIL) */ + +typedef struct { + FATFS* fs; /* Pointer to the owner file system object */ + WORD id; /* Owner file system mount ID */ + BYTE flag; /* File status flags */ + BYTE pad1; + DWORD fptr; /* File read/write pointer (0 on file open) */ + DWORD fsize; /* File size */ + DWORD sclust; /* File start cluster (0 when fsize==0) */ + DWORD clust; /* Current cluster */ + DWORD dsect; /* Current data sector */ +#if !_FS_READONLY + DWORD dir_sect; /* Sector containing the directory entry */ + BYTE* dir_ptr; /* Ponter to the directory entry in the window */ +#endif +#if _USE_FASTSEEK + DWORD* cltbl; /* Pointer to the cluster link map table (null on file open) */ +#endif +#if _FS_SHARE + UINT lockid; /* File lock ID (index of file semaphore table) */ +#endif +#if !_FS_TINY + BYTE buf[_MAX_SS]; /* File data read/write buffer */ +#endif +} FIL; + + + +/* Directory object structure (DIR) */ + +typedef struct { + FATFS* fs; /* Pointer to the owner file system object */ + WORD id; /* Owner file system mount ID */ + WORD index; /* Current read/write index number */ + DWORD sclust; /* Table start cluster (0:Root dir) */ + DWORD clust; /* Current cluster */ + DWORD sect; /* Current sector */ + BYTE* dir; /* Pointer to the current SFN entry in the win[] */ + BYTE* fn; /* Pointer to the SFN (in/out) {file[8],ext[3],status[1]} */ +#if _USE_LFN + WCHAR* lfn; /* Pointer to the LFN working buffer */ + WORD lfn_idx; /* Last matched LFN index number (0xFFFF:No LFN) */ +#endif +} DIR; + + + +/* File status structure (FILINFO) */ + +typedef struct { + DWORD fsize; /* File size */ + WORD fdate; /* Last modified date */ + WORD ftime; /* Last modified time */ + BYTE fattrib; /* Attribute */ + TCHAR fname[13]; /* Short file name (8.3 format) */ +#if _USE_LFN + TCHAR* lfname; /* Pointer to the LFN buffer */ + UINT lfsize; /* Size of LFN buffer in TCHAR */ +#endif +} FILINFO; + + + +/* File function return code (FRESULT) */ + +typedef enum { + FR_OK = 0, /* (0) Succeeded */ + FR_DISK_ERR, /* (1) A hard error occured in the low level disk I/O layer */ + FR_INT_ERR, /* (2) Assertion failed */ + FR_NOT_READY, /* (3) The physical drive cannot work */ + FR_NO_FILE, /* (4) Could not find the file */ + FR_NO_PATH, /* (5) Could not find the path */ + FR_INVALID_NAME, /* (6) The path name format is invalid */ + FR_DENIED, /* (7) Acces denied due to prohibited access or directory full */ + FR_EXIST, /* (8) Acces denied due to prohibited access */ + FR_INVALID_OBJECT, /* (9) The file/directory object is invalid */ + FR_WRITE_PROTECTED, /* (10) The physical drive is write protected */ + FR_INVALID_DRIVE, /* (11) The logical drive number is invalid */ + FR_NOT_ENABLED, /* (12) The volume has no work area */ + FR_NO_FILESYSTEM, /* (13) There is no valid FAT volume */ + FR_MKFS_ABORTED, /* (14) The f_mkfs() aborted due to any parameter error */ + FR_TIMEOUT, /* (15) Could not get a grant to access the volume within defined period */ + FR_LOCKED, /* (16) The operation is rejected according to the file shareing policy */ + FR_NOT_ENOUGH_CORE, /* (17) LFN working buffer could not be allocated */ + FR_TOO_MANY_OPEN_FILES, /* (18) Number of open files > _FS_SHARE */ + FR_INVALID_PARAMETER /* (19) Given parameter is invalid */ +} FRESULT; + + + +/*--------------------------------------------------------------*/ +/* FatFs module application interface */ + +FRESULT f_mount (BYTE, FATFS*); /* Mount/Unmount a logical drive */ +FRESULT f_open (FIL*, const TCHAR*, BYTE); /* Open or create a file */ +FRESULT f_read (FIL*, void*, UINT, UINT*); /* Read data from a file */ +FRESULT f_lseek (FIL*, DWORD); /* Move file pointer of a file object */ +FRESULT f_close (FIL*); /* Close an open file object */ +FRESULT f_opendir (DIR*, const TCHAR*); /* Open an existing directory */ +FRESULT f_readdir (DIR*, FILINFO*); /* Read a directory item */ +FRESULT f_stat (const TCHAR*, FILINFO*); /* Get file status */ +FRESULT f_write (FIL*, const void*, UINT, UINT*); /* Write data to a file */ +FRESULT f_getfree (const TCHAR*, DWORD*, FATFS**); /* Get number of free clusters on the drive */ +FRESULT f_truncate (FIL*); /* Truncate file */ +FRESULT f_sync (FIL*); /* Flush cached data of a writing file */ +FRESULT f_unlink (const TCHAR*); /* Delete an existing file or directory */ +FRESULT f_mkdir (const TCHAR*); /* Create a new directory */ +FRESULT f_chmod (const TCHAR*, BYTE, BYTE); /* Change attriburte of the file/dir */ +FRESULT f_utime (const TCHAR*, const FILINFO*); /* Change timestamp of the file/dir */ +FRESULT f_rename (const TCHAR*, const TCHAR*); /* Rename/Move a file or directory */ +FRESULT f_chdrive (BYTE); /* Change current drive */ +FRESULT f_chdir (const TCHAR*); /* Change current directory */ +FRESULT f_getcwd (TCHAR*, UINT); /* Get current directory */ +FRESULT f_forward (FIL*, UINT(*)(const BYTE*,UINT), UINT, UINT*); /* Forward data to the stream */ +FRESULT f_mkfs (BYTE, BYTE, UINT); /* Create a file system on the drive */ +FRESULT f_fdisk (BYTE, const DWORD[], void*); /* Divide a physical drive into some partitions */ +int f_putc (TCHAR, FIL*); /* Put a character to the file */ +int f_puts (const TCHAR*, FIL*); /* Put a string to the file */ +int f_printf (FIL*, const TCHAR*, ...); /* Put a formatted string to the file */ +int f_vprintf (FIL*, const TCHAR*, va_list arp); /* Put a formatted string to the file, passing a va_list (for var arg functions to forward their arguments. */ +TCHAR* f_gets (TCHAR*, int, FIL*); /* Get a string from the file */ + +#define f_eof(fp) (((fp)->fptr == (fp)->fsize) ? 1 : 0) +#define f_error(fp) (((fp)->flag & FA__ERROR) ? 1 : 0) +#define f_tell(fp) ((fp)->fptr) +#define f_size(fp) ((fp)->fsize) + +#ifndef EOF +#define EOF (-1) +#endif + + + + +/*--------------------------------------------------------------*/ +/* Additional user defined functions */ + +/* RTC function */ +#if !_FS_READONLY +DWORD get_fattime (void); +#endif + +/* Unicode support functions */ +#if _USE_LFN /* Unicode - OEM code conversion */ +WCHAR ff_convert (WCHAR, UINT); /* OEM-Unicode bidirectional conversion */ +WCHAR ff_wtoupper (WCHAR); /* Unicode upper-case conversion */ +#if _USE_LFN == 3 /* Memory functions */ +void* ff_memalloc (UINT); /* Allocate memory block */ +void ff_memfree (void*); /* Free memory block */ +#endif +#endif + +/* Sync functions */ +#if _FS_REENTRANT +int ff_cre_syncobj (BYTE, _SYNC_t*);/* Create a sync object */ +int ff_req_grant (_SYNC_t); /* Lock sync object */ +void ff_rel_grant (_SYNC_t); /* Unlock sync object */ +int ff_del_syncobj (_SYNC_t); /* Delete a sync object */ +#endif + + + + +/*--------------------------------------------------------------*/ +/* Flags and offset address */ + + +/* File access control and file status flags (FIL.flag) */ + +#define FA_READ 0x01 +#define FA_OPEN_EXISTING 0x00 +#define FA__ERROR 0x80 + +#if !_FS_READONLY +#define FA_WRITE 0x02 +#define FA_CREATE_NEW 0x04 +#define FA_CREATE_ALWAYS 0x08 +#define FA_OPEN_ALWAYS 0x10 +#define FA__WRITTEN 0x20 +#define FA__DIRTY 0x40 +#endif + + +/* FAT sub type (FATFS.fs_type) */ + +#define FS_FAT12 1 +#define FS_FAT16 2 +#define FS_FAT32 3 + + +/* File attribute bits for directory entry */ + +#define AM_RDO 0x01 /* Read only */ +#define AM_HID 0x02 /* Hidden */ +#define AM_SYS 0x04 /* System */ +#define AM_VOL 0x08 /* Volume label */ +#define AM_LFN 0x0F /* LFN entry */ +#define AM_DIR 0x10 /* Directory */ +#define AM_ARC 0x20 /* Archive */ +#define AM_MASK 0x3F /* Mask of defined bits */ + + +/* Fast seek feature */ +#define CREATE_LINKMAP 0xFFFFFFFF + + + +/*--------------------------------*/ +/* Multi-byte word access macros */ + +#if _WORD_ACCESS == 1 /* Enable word access to the FAT structure */ +#define LD_WORD(ptr) (WORD)(*(WORD*)(BYTE*)(ptr)) +#define LD_DWORD(ptr) (DWORD)(*(DWORD*)(BYTE*)(ptr)) +#define ST_WORD(ptr,val) *(WORD*)(BYTE*)(ptr)=(WORD)(val) +#define ST_DWORD(ptr,val) *(DWORD*)(BYTE*)(ptr)=(DWORD)(val) +#else /* Use byte-by-byte access to the FAT structure */ +#define LD_WORD(ptr) (WORD)(((WORD)*((BYTE*)(ptr)+1)<<8)|(WORD)*(BYTE*)(ptr)) +#define LD_DWORD(ptr) (DWORD)(((DWORD)*((BYTE*)(ptr)+3)<<24)|((DWORD)*((BYTE*)(ptr)+2)<<16)|((WORD)*((BYTE*)(ptr)+1)<<8)|*(BYTE*)(ptr)) +#define ST_WORD(ptr,val) *(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8) +#define ST_DWORD(ptr,val) *(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8); *((BYTE*)(ptr)+2)=(BYTE)((DWORD)(val)>>16); *((BYTE*)(ptr)+3)=(BYTE)((DWORD)(val)>>24) +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _FATFS */ diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/src/ffconf.h b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/src/ffconf.h new file mode 100644 index 000000000..31f992708 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/src/ffconf.h @@ -0,0 +1,192 @@ +/*---------------------------------------------------------------------------/ +/ FatFs - FAT file system module configuration file R0.09 (C)ChaN, 2011 +/----------------------------------------------------------------------------/ +/ +/ CAUTION! Do not forget to make clean the project after any changes to +/ the configuration options. +/ +/----------------------------------------------------------------------------*/ +#include "conf_fatfs.h" + +#ifndef _FFCONF +#define _FFCONF 6502 /* Revision ID */ + + +/*---------------------------------------------------------------------------/ +/ Functions and Buffer Configurations +/----------------------------------------------------------------------------*/ + +#define _FS_TINY 0 /* 0:Normal or 1:Tiny */ +/* When _FS_TINY is set to 1, FatFs uses the sector buffer in the file system +/ object instead of the sector buffer in the individual file object for file +/ data transfer. This reduces memory consumption 512 bytes each file object. */ + + +#define _FS_READONLY 0 /* 0:Read/Write or 1:Read only */ +/* Setting _FS_READONLY to 1 defines read only configuration. This removes +/ writing functions, f_write, f_sync, f_unlink, f_mkdir, f_chmod, f_rename, +/ f_truncate and useless f_getfree. */ + + +#define _FS_MINIMIZE 0 /* 0 to 3 */ +/* The _FS_MINIMIZE option defines minimization level to remove some functions. +/ +/ 0: Full function. +/ 1: f_stat, f_getfree, f_unlink, f_mkdir, f_chmod, f_truncate and f_rename +/ are removed. +/ 2: f_opendir and f_readdir are removed in addition to 1. +/ 3: f_lseek is removed in addition to 2. */ + + +#define _USE_STRFUNC 0 /* 0:Disable or 1-2:Enable */ +/* To enable string functions, set _USE_STRFUNC to 1 or 2. */ + + +#define _USE_MKFS 0 /* 0:Disable or 1:Enable */ +/* To enable f_mkfs function, set _USE_MKFS to 1 and set _FS_READONLY to 0 */ + + +#define _USE_FORWARD 0 /* 0:Disable or 1:Enable */ +/* To enable f_forward function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */ + + +#define _USE_FASTSEEK 0 /* 0:Disable or 1:Enable */ +/* To enable fast seek feature, set _USE_FASTSEEK to 1. */ + + + +/*---------------------------------------------------------------------------/ +/ Locale and Namespace Configurations +/----------------------------------------------------------------------------*/ + +#define _CODE_PAGE 1252 +/* The _CODE_PAGE specifies the OEM code page to be used on the target system. +/ Incorrect setting of the code page can cause a file open failure. +/ +/ 932 - Japanese Shift-JIS (DBCS, OEM, Windows) +/ 936 - Simplified Chinese GBK (DBCS, OEM, Windows) +/ 949 - Korean (DBCS, OEM, Windows) +/ 950 - Traditional Chinese Big5 (DBCS, OEM, Windows) +/ 1250 - Central Europe (Windows) +/ 1251 - Cyrillic (Windows) +/ 1252 - Latin 1 (Windows) +/ 1253 - Greek (Windows) +/ 1254 - Turkish (Windows) +/ 1255 - Hebrew (Windows) +/ 1256 - Arabic (Windows) +/ 1257 - Baltic (Windows) +/ 1258 - Vietnam (OEM, Windows) +/ 437 - U.S. (OEM) +/ 720 - Arabic (OEM) +/ 737 - Greek (OEM) +/ 775 - Baltic (OEM) +/ 850 - Multilingual Latin 1 (OEM) +/ 858 - Multilingual Latin 1 + Euro (OEM) +/ 852 - Latin 2 (OEM) +/ 855 - Cyrillic (OEM) +/ 866 - Russian (OEM) +/ 857 - Turkish (OEM) +/ 862 - Hebrew (OEM) +/ 874 - Thai (OEM, Windows) +/ 1 - ASCII only (Valid for non LFN cfg.) +*/ + + +#define _USE_LFN 2 /* 0 to 3 */ +#define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */ +/* The _USE_LFN option switches the LFN support. +/ +/ 0: Disable LFN feature. _MAX_LFN and _LFN_UNICODE have no effect. +/ 1: Enable LFN with static working buffer on the BSS. Always NOT reentrant. +/ 2: Enable LFN with dynamic working buffer on the STACK. +/ 3: Enable LFN with dynamic working buffer on the HEAP. +/ +/ The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. To enable LFN, +/ Unicode handling functions ff_convert() and ff_wtoupper() must be added +/ to the project. When enable to use heap, memory control functions +/ ff_memalloc() and ff_memfree() must be added to the project. */ + + +#define _LFN_UNICODE 0 /* 0:ANSI/OEM or 1:Unicode */ +/* To switch the character code set on FatFs API to Unicode, +/ enable LFN feature and set _LFN_UNICODE to 1. */ + + +#define _FS_RPATH 0 /* 0 to 2 */ +/* The _FS_RPATH option configures relative path feature. +/ +/ 0: Disable relative path feature and remove related functions. +/ 1: Enable relative path. f_chdrive() and f_chdir() are available. +/ 2: f_getcwd() is available in addition to 1. +/ +/ Note that output of the f_readdir fnction is affected by this option. */ + + + +/*---------------------------------------------------------------------------/ +/ Physical Drive Configurations +/----------------------------------------------------------------------------*/ + +#define _VOLUMES 1 +/* Number of volumes (logical drives) to be used. */ + + +#define _MAX_SS 512 /* 512, 1024, 2048 or 4096 */ +/* Maximum sector size to be handled. +/ Always set 512 for memory card and hard disk but a larger value may be +/ required for on-board flash memory, floppy disk and optical disk. +/ When _MAX_SS is larger than 512, it configures FatFs to variable sector size +/ and GET_SECTOR_SIZE command must be implememted to the disk_ioctl function. */ + + +#define _MULTI_PARTITION 0 /* 0:Single partition, 1/2:Enable multiple partition */ +/* When set to 0, each volume is bound to the same physical drive number and +/ it can mount only first primaly partition. When it is set to 1, each volume +/ is tied to the partitions listed in VolToPart[]. */ + + +#define _USE_ERASE 0 /* 0:Disable or 1:Enable */ +/* To enable sector erase feature, set _USE_ERASE to 1. CTRL_ERASE_SECTOR command +/ should be added to the disk_ioctl functio. */ + + + +/*---------------------------------------------------------------------------/ +/ System Configurations +/----------------------------------------------------------------------------*/ + +#define _WORD_ACCESS 0 /* 0 or 1 */ +/* Set 0 first and it is always compatible with all platforms. The _WORD_ACCESS +/ option defines which access method is used to the word data on the FAT volume. +/ +/ 0: Byte-by-byte access. +/ 1: Word access. Do not choose this unless following condition is met. +/ +/ When the byte order on the memory is big-endian or address miss-aligned word +/ access results incorrect behavior, the _WORD_ACCESS must be set to 0. +/ If it is not the case, the value can also be set to 1 to improve the +/ performance and code size. +*/ + + +/* A header file that defines sync object types on the O/S, such as +/ windows.h, ucos_ii.h and semphr.h, must be included prior to ff.h. */ + +#define _FS_REENTRANT 0 /* 0:Disable or 1:Enable */ +#define _FS_TIMEOUT 1000 /* Timeout period in unit of time ticks */ +#define _SYNC_t HANDLE /* O/S dependent type of sync object. e.g. HANDLE, OS_EVENT*, ID and etc.. */ + +/* The _FS_REENTRANT option switches the reentrancy (thread safe) of the FatFs module. +/ +/ 0: Disable reentrancy. _SYNC_t and _FS_TIMEOUT have no effect. +/ 1: Enable reentrancy. Also user provided synchronization handlers, +/ ff_req_grant, ff_rel_grant, ff_del_syncobj and ff_cre_syncobj +/ function must be added to the project. */ + + +#define _FS_SHARE 0 /* 0:Disable or >=1:Enable */ +/* To enable file shareing feature, set _FS_SHARE to 1 or greater. The value + defines how many files can be opened simultaneously. */ + + +#endif /* _FFCONFIG */ diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/src/integer.h b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/src/integer.h new file mode 100644 index 000000000..16ad40823 --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/src/integer.h @@ -0,0 +1,37 @@ +/*-------------------------------------------*/ +/* Integer type definitions for FatFs module */ +/*-------------------------------------------*/ + +#ifndef _INTEGER +#define _INTEGER + +#ifdef _WIN32 /* FatFs development platform */ + +#include +#include + +#else /* Embedded platform */ + +/* These types must be 16-bit, 32-bit or larger integer */ +typedef int INT; +typedef unsigned int UINT; + +/* These types must be 8-bit integer */ +typedef char CHAR; +typedef unsigned char UCHAR; +typedef unsigned char BYTE; + +/* These types must be 16-bit integer */ +typedef short SHORT; +typedef unsigned short USHORT; +typedef unsigned short WORD; +typedef unsigned short WCHAR; + +/* These types must be 32-bit integer */ +typedef long LONG; +typedef unsigned long ULONG; +typedef unsigned long DWORD; + +#endif + +#endif diff --git a/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/src/option/ccsbcs.c b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/src/option/ccsbcs.c new file mode 100644 index 000000000..2a505891b --- /dev/null +++ b/hw-libs/drivers/SAMx70/ASF/thirdparty/fatfs/fatfs-r0.09/src/option/ccsbcs.c @@ -0,0 +1,540 @@ +/*------------------------------------------------------------------------*/ +/* Unicode - Local code bidirectional converter (C)ChaN, 2009 */ +/* (SBCS code pages) */ +/*------------------------------------------------------------------------*/ +/* 437 U.S. (OEM) +/ 720 Arabic (OEM) +/ 1256 Arabic (Windows) +/ 737 Greek (OEM) +/ 1253 Greek (Windows) +/ 1250 Central Europe (Windows) +/ 775 Baltic (OEM) +/ 1257 Baltic (Windows) +/ 850 Multilingual Latin 1 (OEM) +/ 852 Latin 2 (OEM) +/ 1252 Latin 1 (Windows) +/ 855 Cyrillic (OEM) +/ 1251 Cyrillic (Windows) +/ 866 Russian (OEM) +/ 857 Turkish (OEM) +/ 1254 Turkish (Windows) +/ 858 Multilingual Latin 1 + Euro (OEM) +/ 862 Hebrew (OEM) +/ 1255 Hebrew (Windows) +/ 874 Thai (OEM, Windows) +/ 1258 Vietnam (OEM, Windows) +*/ + +#include "../ff.h" + + +#if _CODE_PAGE == 437 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP437(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, + 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, + 0x00FF, 0x00D6, 0x00DC, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, + 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, + 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, + 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, + 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, + 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, + 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 720 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP720(0x80-0xFF) to Unicode conversion table */ + 0x0000, 0x0000, 0x00E9, 0x00E2, 0x0000, 0x00E0, 0x0000, 0x00E7, + 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0651, 0x0652, 0x00F4, 0x00A4, 0x0640, 0x00FB, 0x00F9, + 0x0621, 0x0622, 0x0623, 0x0624, 0x00A3, 0x0625, 0x0626, 0x0627, + 0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F, + 0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, + 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, + 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x0636, 0x0637, 0x0638, 0x0639, 0x063A, 0x0641, 0x00B5, 0x0642, + 0x0643, 0x0644, 0x0645, 0x0646, 0x0647, 0x0648, 0x0649, 0x064A, + 0x2261, 0x064B, 0x064C, 0x064D, 0x064E, 0x064F, 0xO650, 0x2248, + 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 737 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP737(0x80-0xFF) to Unicode conversion table */ + 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x0398, + 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F, 0x03A0, + 0x03A1, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9, + 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, 0x03B8, + 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0, + 0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x03C5, 0x03C6, 0x03C7, 0x03C8, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, + 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, + 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03C9, 0x03AC, 0x03AD, 0x03AE, 0x03CA, 0x03AF, 0x03CC, 0x03CD, + 0x03CB, 0x03CE, 0x0386, 0x0388, 0x0389, 0x038A, 0x038C, 0x038E, + 0x038F, 0x00B1, 0x2265, 0x2264, 0x03AA, 0x03AB, 0x00F7, 0x2248, + 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 775 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP775(0x80-0xFF) to Unicode conversion table */ + 0x0106, 0x00FC, 0x00E9, 0x0101, 0x00E4, 0x0123, 0x00E5, 0x0107, + 0x0142, 0x0113, 0x0156, 0x0157, 0x012B, 0x0179, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x014D, 0x00F6, 0x0122, 0x00A2, 0x015A, + 0x015B, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x00A4, + 0x0100, 0x012A, 0x00F3, 0x017B, 0x017C, 0x017A, 0x201D, 0x00A6, + 0x00A9, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x0141, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0104, 0x010C, 0x0118, + 0x0116, 0x2563, 0x2551, 0x2557, 0x255D, 0x012E, 0x0160, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0172, 0x016A, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x017D, + 0x0105, 0x010D, 0x0119, 0x0117, 0x012F, 0x0161, 0x0173, 0x016B, + 0x017E, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x00D3, 0x00DF, 0x014C, 0x0143, 0x00F5, 0x00D5, 0x00B5, 0x0144, + 0x0136, 0x0137, 0x013B, 0x013C, 0x0146, 0x0112, 0x0145, 0x2019, + 0x00AD, 0x00B1, 0x201C, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x201E, + 0x00B0, 0x2219, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 850 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP850(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, + 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, + 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, + 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, + 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x0131, 0x00CD, 0x00CE, + 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580, + 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE, + 0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4, + 0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, + 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 852 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP852(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x016F, 0x0107, 0x00E7, + 0x0142, 0x00EB, 0x0150, 0x0151, 0x00EE, 0x0179, 0x00C4, 0x0106, + 0x00C9, 0x0139, 0x013A, 0x00F4, 0x00F6, 0x013D, 0x013E, 0x015A, + 0x015B, 0x00D6, 0x00DC, 0x0164, 0x0165, 0x0141, 0x00D7, 0x010D, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x0104, 0x0105, 0x017D, 0x017E, + 0x0118, 0x0119, 0x00AC, 0x017A, 0x010C, 0x015F, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x011A, + 0x015E, 0x2563, 0x2551, 0x2557, 0x255D, 0x017B, 0x017C, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0102, 0x0103, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x0111, 0x0110, 0x010E, 0x00CB, 0x010F, 0x0147, 0x00CD, 0x00CE, + 0x011B, 0x2518, 0x250C, 0x2588, 0x2584, 0x0162, 0x016E, 0x2580, + 0x00D3, 0x00DF, 0x00D4, 0x0143, 0x0144, 0x0148, 0x0160, 0x0161, + 0x0154, 0x00DA, 0x0155, 0x0170, 0x00FD, 0x00DD, 0x0163, 0x00B4, + 0x00AD, 0x02DD, 0x02DB, 0x02C7, 0x02D8, 0x00A7, 0x00F7, 0x00B8, + 0x00B0, 0x00A8, 0x02D9, 0x0171, 0x0158, 0x0159, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 855 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP855(0x80-0xFF) to Unicode conversion table */ + 0x0452, 0x0402, 0x0453, 0x0403, 0x0451, 0x0401, 0x0454, 0x0404, + 0x0455, 0x0405, 0x0456, 0x0406, 0x0457, 0x0407, 0x0458, 0x0408, + 0x0459, 0x0409, 0x045A, 0x040A, 0x045B, 0x040B, 0x045C, 0x040C, + 0x045E, 0x040E, 0x045F, 0x040F, 0x044E, 0x042E, 0x044A, 0x042A, + 0x0430, 0x0410, 0x0431, 0x0411, 0x0446, 0x0426, 0x0434, 0x0414, + 0x0435, 0x0415, 0x0444, 0x0424, 0x0433, 0x0413, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0445, 0x0425, 0x0438, + 0x0418, 0x2563, 0x2551, 0x2557, 0x255D, 0x0439, 0x0419, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x043A, 0x041A, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x043B, 0x041B, 0x043C, 0x041C, 0x043D, 0x041D, 0x043E, 0x041E, + 0x043F, 0x2518, 0x250C, 0x2588, 0x2584, 0x041F, 0x044F, 0x2580, + 0x042F, 0x0440, 0x0420, 0x0441, 0x0421, 0x0442, 0x0422, 0x0443, + 0x0423, 0x0436, 0x0416, 0x0432, 0x0412, 0x044C, 0x042C, 0x2116, + 0x00AD, 0x044B, 0x042B, 0x0437, 0x0417, 0x0448, 0x0428, 0x044D, + 0x042D, 0x0449, 0x0429, 0x0447, 0x0427, 0x00A7, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 857 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP857(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, + 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0131, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, + 0x0130, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x015E, 0x015F, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x011E, 0x011F, + 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, + 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x00BA, 0x00AA, 0x00CA, 0x00CB, 0x00C8, 0x0000, 0x00CD, 0x00CE, + 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580, + 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x0000, + 0x00D7, 0x00DA, 0x00DB, 0x00D9, 0x00EC, 0x00FF, 0x00AF, 0x00B4, + 0x00AD, 0x00B1, 0x0000, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, + 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 858 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP858(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, + 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, + 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, + 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, + 0x00A9, 0x2563, 0x2551, 0x2557, 0x2550, 0x00A2, 0x00A5, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x20AC, 0x00CD, 0x00CE, + 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00C6, 0x00CC, 0x2580, + 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE, + 0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4, + 0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, + 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 862 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP862(0x80-0xFF) to Unicode conversion table */ + 0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7, + 0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF, + 0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7, + 0x05E8, 0x05E9, 0x05EA, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, + 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, + 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, + 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, + 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, + 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, + 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 866 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP866(0x80-0xFF) to Unicode conversion table */ + 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, + 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F, + 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, + 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F, + 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, + 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, + 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, + 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, + 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F, + 0x0401, 0x0451, 0x0404, 0x0454, 0x0407, 0x0457, 0x040E, 0x045E, + 0x00B0, 0x2219, 0x00B7, 0x221A, 0x2116, 0x00A4, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 874 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP874(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x0000, 0x0000, 0x0000, 0x2026, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x00A0, 0x0E01, 0x0E02, 0x0E03, 0x0E04, 0x0E05, 0x0E06, 0x0E07, + 0x0E08, 0x0E09, 0x0E0A, 0x0E0B, 0x0E0C, 0x0E0D, 0x0E0E, 0x0E0F, + 0x0E10, 0x0E11, 0x0E12, 0x0E13, 0x0E14, 0x0E15, 0x0E16, 0x0E17, + 0x0E18, 0x0E19, 0x0E1A, 0x0E1B, 0x0E1C, 0x0E1D, 0x0E1E, 0x0E1F, + 0x0E20, 0x0E21, 0x0E22, 0x0E23, 0x0E24, 0x0E25, 0x0E26, 0x0E27, + 0x0E28, 0x0E29, 0x0E2A, 0x0E2B, 0x0E2C, 0x0E2D, 0x0E2E, 0x0E2F, + 0x0E30, 0x0E31, 0x0E32, 0x0E33, 0x0E34, 0x0E35, 0x0E36, 0x0E37, + 0x0E38, 0x0E39, 0x0E3A, 0x0000, 0x0000, 0x0000, 0x0000, 0x0E3F, + 0x0E40, 0x0E41, 0x0E42, 0x0E43, 0x0E44, 0x0E45, 0x0E46, 0x0E47, + 0x0E48, 0x0E49, 0x0E4A, 0x0E4B, 0x0E4C, 0x0E4D, 0x0E4E, 0x0E4F, + 0x0E50, 0x0E51, 0x0E52, 0x0E53, 0x0E54, 0x0E55, 0x0E56, 0x0E57, + 0x0E58, 0x0E59, 0x0E5A, 0x0E5B, 0x0000, 0x0000, 0x0000, 0x0000 +}; + +#elif _CODE_PAGE == 1250 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1250(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x201A, 0x0000, 0x201E, 0x2026, 0x2020, 0x2021, + 0x0000, 0x2030, 0x0160, 0x2039, 0x015A, 0x0164, 0x017D, 0x0179, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x0000, 0x2122, 0x0161, 0x203A, 0x015B, 0x0165, 0x017E, 0x017A, + 0x00A0, 0x02C7, 0x02D8, 0x0141, 0x00A4, 0x0104, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x015E, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x017B, + 0x00B0, 0x00B1, 0x02DB, 0x0142, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x0105, 0x015F, 0x00BB, 0x013D, 0x02DD, 0x013E, 0x017C, + 0x0154, 0x00C1, 0x00C2, 0x0102, 0x00C4, 0x0139, 0x0106, 0x00C7, + 0x010C, 0x00C9, 0x0118, 0x00CB, 0x011A, 0x00CD, 0x00CE, 0x010E, + 0x0110, 0x0143, 0x0147, 0x00D3, 0x00D4, 0x0150, 0x00D6, 0x00D7, + 0x0158, 0x016E, 0x00DA, 0x0170, 0x00DC, 0x00DD, 0x0162, 0x00DF, + 0x0155, 0x00E1, 0x00E2, 0x0103, 0x00E4, 0x013A, 0x0107, 0x00E7, + 0x010D, 0x00E9, 0x0119, 0x00EB, 0x011B, 0x00ED, 0x00EE, 0x010F, + 0x0111, 0x0144, 0x0148, 0x00F3, 0x00F4, 0x0151, 0x00F6, 0x00F7, + 0x0159, 0x016F, 0x00FA, 0x0171, 0x00FC, 0x00FD, 0x0163, 0x02D9 +}; + +#elif _CODE_PAGE == 1251 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1251(0x80-0xFF) to Unicode conversion table */ + 0x0402, 0x0403, 0x201A, 0x0453, 0x201E, 0x2026, 0x2020, 0x2021, + 0x20AC, 0x2030, 0x0409, 0x2039, 0x040A, 0x040C, 0x040B, 0x040F, + 0x0452, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x0000, 0x2111, 0x0459, 0x203A, 0x045A, 0x045C, 0x045B, 0x045F, + 0x00A0, 0x040E, 0x045E, 0x0408, 0x00A4, 0x0490, 0x00A6, 0x00A7, + 0x0401, 0x00A9, 0x0404, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x0407, + 0x00B0, 0x00B1, 0x0406, 0x0456, 0x0491, 0x00B5, 0x00B6, 0x00B7, + 0x0451, 0x2116, 0x0454, 0x00BB, 0x0458, 0x0405, 0x0455, 0x0457, + 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, + 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F, + 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, + 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F, + 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, + 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F, + 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, + 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F +}; + +#elif _CODE_PAGE == 1252 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1252(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, + 0x02C6, 0x2030, 0x0160, 0x2039, 0x0152, 0x0000, 0x017D, 0x0000, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x02DC, 0x2122, 0x0161, 0x203A, 0x0153, 0x0000, 0x017E, 0x0178, + 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, + 0x00C0, 0x00C1, 0x00C2, 0x00C3, 0x00C4, 0x00C5, 0x00C6, 0x00C7, + 0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x00CC, 0x00CD, 0x00CE, 0x00CF, + 0x00D0, 0x00D1, 0x00D2, 0x00D3, 0x00D4, 0x00D5, 0x00D6, 0x00D7, + 0x00D8, 0x00D9, 0x00DA, 0x00DB, 0x00DC, 0x00DD, 0x00DE, 0x00DF, + 0x00E0, 0x00E1, 0x00E2, 0x00E3, 0x00E4, 0x00E5, 0x00E6, 0x00E7, + 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x00EC, 0x00ED, 0x00EE, 0x00EF, + 0x00F0, 0x00F1, 0x00F2, 0x00F3, 0x00F4, 0x00F5, 0x00F6, 0x00F7, + 0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x00FD, 0x00FE, 0x00FF +}; + +#elif _CODE_PAGE == 1253 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1253(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, + 0x0000, 0x2030, 0x0000, 0x2039, 0x000C, 0x0000, 0x0000, 0x0000, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x0000, 0x2122, 0x0000, 0x203A, 0x0000, 0x0000, 0x0000, 0x0000, + 0x00A0, 0x0385, 0x0386, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x0000, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x2015, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x0384, 0x00B5, 0x00B6, 0x00B7, + 0x0388, 0x0389, 0x038A, 0x00BB, 0x038C, 0x00BD, 0x038E, 0x038F, + 0x0390, 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, + 0x0398, 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F, + 0x03A0, 0x03A1, 0x0000, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, + 0x03A8, 0x03A9, 0x03AA, 0x03AD, 0x03AC, 0x03AD, 0x03AE, 0x03AF, + 0x03B0, 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, + 0x03B8, 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, + 0x03C0, 0x03C1, 0x03C2, 0x03C3, 0x03C4, 0x03C5, 0x03C6, 0x03C7, + 0x03C8, 0x03C9, 0x03CA, 0x03CB, 0x03CC, 0x03CD, 0x03CE, 0x0000 +}; + +#elif _CODE_PAGE == 1254 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1254(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x210A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, + 0x02C6, 0x2030, 0x0160, 0x2039, 0x0152, 0x0000, 0x0000, 0x0000, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x02DC, 0x2122, 0x0161, 0x203A, 0x0153, 0x0000, 0x0000, 0x0178, + 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, + 0x00C0, 0x00C1, 0x00C2, 0x00C3, 0x00C4, 0x00C5, 0x00C6, 0x00C7, + 0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x00CC, 0x00CD, 0x00CE, 0x00CF, + 0x011E, 0x00D1, 0x00D2, 0x00D3, 0x00D4, 0x00D5, 0x00D6, 0x00D7, + 0x00D8, 0x00D9, 0x00DA, 0x00BD, 0x00DC, 0x0130, 0x015E, 0x00DF, + 0x00E0, 0x00E1, 0x00E2, 0x00E3, 0x00E4, 0x00E5, 0x00E6, 0x00E7, + 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x00EC, 0x00ED, 0x00EE, 0x00EF, + 0x011F, 0x00F1, 0x00F2, 0x00F3, 0x00F4, 0x00F5, 0x00F6, 0x00F7, + 0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x0131, 0x015F, 0x00FF +}; + +#elif _CODE_PAGE == 1255 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1255(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, + 0x02C6, 0x2030, 0x0000, 0x2039, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x02DC, 0x2122, 0x0000, 0x203A, 0x0000, 0x0000, 0x0000, 0x0000, + 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x00D7, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x00B9, 0x00F7, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, + 0x05B0, 0x05B1, 0x05B2, 0x05B3, 0x05B4, 0x05B5, 0x05B6, 0x05B7, + 0x05B8, 0x05B9, 0x0000, 0x05BB, 0x05BC, 0x05BD, 0x05BE, 0x05BF, + 0x05C0, 0x05C1, 0x05C2, 0x05C3, 0x05F0, 0x05F1, 0x05F2, 0x05F3, + 0x05F4, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7, + 0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF, + 0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7, + 0x05E8, 0x05E9, 0x05EA, 0x0000, 0x0000, 0x200E, 0x200F, 0x0000 +}; + +#elif _CODE_PAGE == 1256 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1256(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x067E, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, + 0x02C6, 0x2030, 0x0679, 0x2039, 0x0152, 0x0686, 0x0698, 0x0688, + 0x06AF, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x06A9, 0x2122, 0x0691, 0x203A, 0x0153, 0x200C, 0x200D, 0x06BA, + 0x00A0, 0x060C, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x06BE, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x00B9, 0x061B, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x061F, + 0x06C1, 0x0621, 0x0622, 0x0623, 0x0624, 0x0625, 0x0626, 0x0627, + 0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F, + 0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x0636, 0x00D7, + 0x0637, 0x0638, 0x0639, 0x063A, 0x0640, 0x0640, 0x0642, 0x0643, + 0x00E0, 0x0644, 0x00E2, 0x0645, 0x0646, 0x0647, 0x0648, 0x00E7, + 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x0649, 0x064A, 0x00EE, 0x00EF, + 0x064B, 0x064C, 0x064D, 0x064E, 0x00F4, 0x064F, 0x0650, 0x00F7, + 0x0651, 0x00F9, 0x0652, 0x00FB, 0x00FC, 0x200E, 0x200F, 0x06D2 +} + +#elif _CODE_PAGE == 1257 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1257(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x201A, 0x0000, 0x201E, 0x2026, 0x2020, 0x2021, + 0x0000, 0x2030, 0x0000, 0x2039, 0x0000, 0x00A8, 0x02C7, 0x00B8, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x0000, 0x2122, 0x0000, 0x203A, 0x0000, 0x00AF, 0x02DB, 0x0000, + 0x00A0, 0x0000, 0x00A2, 0x00A3, 0x00A4, 0x0000, 0x00A6, 0x00A7, + 0x00D8, 0x00A9, 0x0156, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x00B9, 0x0157, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00E6, + 0x0104, 0x012E, 0x0100, 0x0106, 0x00C4, 0x00C5, 0x0118, 0x0112, + 0x010C, 0x00C9, 0x0179, 0x0116, 0x0122, 0x0136, 0x012A, 0x013B, + 0x0160, 0x0143, 0x0145, 0x00D3, 0x014C, 0x00D5, 0x00D6, 0x00D7, + 0x0172, 0x0141, 0x015A, 0x016A, 0x00DC, 0x017B, 0x017D, 0x00DF, + 0x0105, 0x012F, 0x0101, 0x0107, 0x00E4, 0x00E5, 0x0119, 0x0113, + 0x010D, 0x00E9, 0x017A, 0x0117, 0x0123, 0x0137, 0x012B, 0x013C, + 0x0161, 0x0144, 0x0146, 0x00F3, 0x014D, 0x00F5, 0x00F6, 0x00F7, + 0x0173, 0x014E, 0x015B, 0x016B, 0x00FC, 0x017C, 0x017E, 0x02D9 +}; + +#elif _CODE_PAGE == 1258 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1258(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, + 0x02C6, 0x2030, 0x0000, 0x2039, 0x0152, 0x0000, 0x0000, 0x0000, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x02DC, 0x2122, 0x0000, 0x203A, 0x0153, 0x0000, 0x0000, 0x0178, + 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, + 0x00C0, 0x00C1, 0x00C2, 0x0102, 0x00C4, 0x00C5, 0x00C6, 0x00C7, + 0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x0300, 0x00CD, 0x00CE, 0x00CF, + 0x0110, 0x00D1, 0x0309, 0x00D3, 0x00D4, 0x01A0, 0x00D6, 0x00D7, + 0x00D8, 0x00D9, 0x00DA, 0x00DB, 0x00DC, 0x01AF, 0x0303, 0x00DF, + 0x00E0, 0x00E1, 0x00E2, 0x0103, 0x00E4, 0x00E5, 0x00E6, 0x00E7, + 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x0301, 0x00ED, 0x00EE, 0x00EF, + 0x0111, 0x00F1, 0x0323, 0x00F3, 0x00F4, 0x01A1, 0x00F6, 0x00F7, + 0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x01B0, 0x20AB, 0x00FF +}; + +#endif + + +#if !_TBLDEF || !_USE_LFN +#error This file is not needed in current configuration. Remove from the project. +#endif + + +WCHAR ff_convert ( /* Converted character, Returns zero on error */ + WCHAR src, /* Character code to be converted */ + UINT dir /* 0: Unicode to OEMCP, 1: OEMCP to Unicode */ +) +{ + WCHAR c; + + + if (src < 0x80) { /* ASCII */ + c = src; + + } else { + if (dir) { /* OEMCP to Unicode */ + c = (src >= 0x100) ? 0 : Tbl[src - 0x80]; + + } else { /* Unicode to OEMCP */ + for (c = 0; c < 0x80; c++) { + if (src == Tbl[c]) break; + } + c = (c + 0x80) & 0xFF; + } + } + + return c; +} + + +WCHAR ff_wtoupper ( /* Upper converted character */ + WCHAR chr /* Input character */ +) +{ + static const WCHAR tbl_lower[] = { 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0xA1, 0x00A2, 0x00A3, 0x00A5, 0x00AC, 0x00AF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0x0FF, 0x101, 0x103, 0x105, 0x107, 0x109, 0x10B, 0x10D, 0x10F, 0x111, 0x113, 0x115, 0x117, 0x119, 0x11B, 0x11D, 0x11F, 0x121, 0x123, 0x125, 0x127, 0x129, 0x12B, 0x12D, 0x12F, 0x131, 0x133, 0x135, 0x137, 0x13A, 0x13C, 0x13E, 0x140, 0x142, 0x144, 0x146, 0x148, 0x14B, 0x14D, 0x14F, 0x151, 0x153, 0x155, 0x157, 0x159, 0x15B, 0x15D, 0x15F, 0x161, 0x163, 0x165, 0x167, 0x169, 0x16B, 0x16D, 0x16F, 0x171, 0x173, 0x175, 0x177, 0x17A, 0x17C, 0x17E, 0x192, 0x3B1, 0x3B2, 0x3B3, 0x3B4, 0x3B5, 0x3B6, 0x3B7, 0x3B8, 0x3B9, 0x3BA, 0x3BB, 0x3BC, 0x3BD, 0x3BE, 0x3BF, 0x3C0, 0x3C1, 0x3C3, 0x3C4, 0x3C5, 0x3C6, 0x3C7, 0x3C8, 0x3C9, 0x3CA, 0x430, 0x431, 0x432, 0x433, 0x434, 0x435, 0x436, 0x437, 0x438, 0x439, 0x43A, 0x43B, 0x43C, 0x43D, 0x43E, 0x43F, 0x440, 0x441, 0x442, 0x443, 0x444, 0x445, 0x446, 0x447, 0x448, 0x449, 0x44A, 0x44B, 0x44C, 0x44D, 0x44E, 0x44F, 0x451, 0x452, 0x453, 0x454, 0x455, 0x456, 0x457, 0x458, 0x459, 0x45A, 0x45B, 0x45C, 0x45E, 0x45F, 0x2170, 0x2171, 0x2172, 0x2173, 0x2174, 0x2175, 0x2176, 0x2177, 0x2178, 0x2179, 0x217A, 0x217B, 0x217C, 0x217D, 0x217E, 0x217F, 0xFF41, 0xFF42, 0xFF43, 0xFF44, 0xFF45, 0xFF46, 0xFF47, 0xFF48, 0xFF49, 0xFF4A, 0xFF4B, 0xFF4C, 0xFF4D, 0xFF4E, 0xFF4F, 0xFF50, 0xFF51, 0xFF52, 0xFF53, 0xFF54, 0xFF55, 0xFF56, 0xFF57, 0xFF58, 0xFF59, 0xFF5A, 0 }; + static const WCHAR tbl_upper[] = { 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x21, 0xFFE0, 0xFFE1, 0xFFE5, 0xFFE2, 0xFFE3, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0x178, 0x100, 0x102, 0x104, 0x106, 0x108, 0x10A, 0x10C, 0x10E, 0x110, 0x112, 0x114, 0x116, 0x118, 0x11A, 0x11C, 0x11E, 0x120, 0x122, 0x124, 0x126, 0x128, 0x12A, 0x12C, 0x12E, 0x130, 0x132, 0x134, 0x136, 0x139, 0x13B, 0x13D, 0x13F, 0x141, 0x143, 0x145, 0x147, 0x14A, 0x14C, 0x14E, 0x150, 0x152, 0x154, 0x156, 0x158, 0x15A, 0x15C, 0x15E, 0x160, 0x162, 0x164, 0x166, 0x168, 0x16A, 0x16C, 0x16E, 0x170, 0x172, 0x174, 0x176, 0x179, 0x17B, 0x17D, 0x191, 0x391, 0x392, 0x393, 0x394, 0x395, 0x396, 0x397, 0x398, 0x399, 0x39A, 0x39B, 0x39C, 0x39D, 0x39E, 0x39F, 0x3A0, 0x3A1, 0x3A3, 0x3A4, 0x3A5, 0x3A6, 0x3A7, 0x3A8, 0x3A9, 0x3AA, 0x410, 0x411, 0x412, 0x413, 0x414, 0x415, 0x416, 0x417, 0x418, 0x419, 0x41A, 0x41B, 0x41C, 0x41D, 0x41E, 0x41F, 0x420, 0x421, 0x422, 0x423, 0x424, 0x425, 0x426, 0x427, 0x428, 0x429, 0x42A, 0x42B, 0x42C, 0x42D, 0x42E, 0x42F, 0x401, 0x402, 0x403, 0x404, 0x405, 0x406, 0x407, 0x408, 0x409, 0x40A, 0x40B, 0x40C, 0x40E, 0x40F, 0x2160, 0x2161, 0x2162, 0x2163, 0x2164, 0x2165, 0x2166, 0x2167, 0x2168, 0x2169, 0x216A, 0x216B, 0x216C, 0x216D, 0x216E, 0x216F, 0xFF21, 0xFF22, 0xFF23, 0xFF24, 0xFF25, 0xFF26, 0xFF27, 0xFF28, 0xFF29, 0xFF2A, 0xFF2B, 0xFF2C, 0xFF2D, 0xFF2E, 0xFF2F, 0xFF30, 0xFF31, 0xFF32, 0xFF33, 0xFF34, 0xFF35, 0xFF36, 0xFF37, 0xFF38, 0xFF39, 0xFF3A, 0 }; + int i; + + + for (i = 0; tbl_lower[i] && chr != tbl_lower[i]; i++) ; + + return tbl_lower[i] ? tbl_upper[i] : chr; +} diff --git a/hw-libs/drivers/SAMx70/CAN.c b/hw-libs/drivers/SAMx70/CAN.c new file mode 100644 index 000000000..4e47e2922 --- /dev/null +++ b/hw-libs/drivers/SAMx70/CAN.c @@ -0,0 +1,313 @@ +/* +MIT LICENSE + +Copyright 2014-2019 Inertial Sense, Inc. - http://inertialsense.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions : + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +/* module_inst */ + +#include "asf.h" +#include "CAN.h" +#include "globals.h" + +#define MCAN_TEST_SEND_ID_STD 0x125 +#define MCAN_TEST_SEND_ID_EXT 0x100000A5 +#define MCAN_TEST_RECV_ID_STD 0x126 +#define MCAN_TEST_RECV_ID_EXT 0x100000A6 + +struct mcan_module mcan_instance; + +void CAN_init(uint32_t baudrate, uint32_t rx_address) +{ + mcan_stop(&mcan_instance); + /* Initialize the module. */ + struct mcan_config config_mcan; + mcan_get_config_defaults(&config_mcan); + config_mcan.rx_fifo_0_overwrite = true; + config_mcan.tx_queue_mode = true; + config_mcan.automatic_retransmission = false; + mcan_init(&mcan_instance, MCAN1, &config_mcan); +// #warning "TODO: Add CAN data rate and address to settings stored in flash" + mcan_set_baudrate(mcan_instance.hw, baudrate); + //mcan_set_baudrate(mcan_instance.hw, 1000000); + mcan_set_rx_filter(rx_address); + //mcan_set_rx_filter(0x100); + + mcan_start(&mcan_instance); +} + +bool mcan_send_message(uint32_t id_value, uint8_t *data, uint32_t data_length) +{ + uint32_t status = mcan_tx_get_fifo_queue_status(&mcan_instance); + + //check if fifo is full + if(status & MCAN_TXFQS_TFQF) { + return false; + } + + //Prevent sending more data than buffer size + if(data_length > CONF_MCAN_ELEMENT_DATA_SIZE) + data_length = CONF_MCAN_ELEMENT_DATA_SIZE; + + //get the put index where we put the next packet + uint32_t put_index = (status & MCAN_TXFQS_TFQPI_Msk) >> MCAN_TXFQS_TFQPI_Pos; + + struct mcan_tx_element tx_element = {}; + mcan_get_tx_buffer_element_defaults(&tx_element); + + if(id_value >= 0x800) + tx_element.T0.reg |= MCAN_TX_ELEMENT_T0_EXTENDED_ID(id_value) | MCAN_TX_ELEMENT_T0_XTD; + else + tx_element.T0.reg |= MCAN_TX_ELEMENT_T0_STANDARD_ID(id_value); + + tx_element.T1.bit.DLC = data_length; + + for (uint32_t i = 0; i < data_length; i++) { + tx_element.data[i] = data[i]; + } + + mcan_set_tx_buffer_element(&mcan_instance, &tx_element, put_index); + mcan_tx_transfer_request(&mcan_instance, (1 << put_index)); + + return true; +} + +bool mcan_send_message_rtr(uint32_t id_value, uint8_t *data, uint32_t data_length) +{ + uint32_t status = mcan_tx_get_fifo_queue_status(&mcan_instance); + + //check if fifo is full + if(status & MCAN_TXFQS_TFQF) { + return false; + } + + //Prevent sending more data than buffer size + if(data_length > CONF_MCAN_ELEMENT_DATA_SIZE) + data_length = CONF_MCAN_ELEMENT_DATA_SIZE; + + //get the put index where we put the next packet + uint32_t put_index = (status & MCAN_TXFQS_TFQPI_Msk) >> MCAN_TXFQS_TFQPI_Pos; + + struct mcan_tx_element tx_element = {}; + mcan_get_tx_buffer_element_defaults(&tx_element); + + if(id_value >= 0x800) + tx_element.T0.reg |= MCAN_TX_ELEMENT_T0_EXTENDED_ID(id_value) | MCAN_TX_ELEMENT_T0_XTD; + else + tx_element.T0.reg |= MCAN_TX_ELEMENT_T0_STANDARD_ID(id_value) | MCAN_TX_ELEMENT_T0_RTR; + + tx_element.T1.bit.DLC = data_length; + + for (uint32_t i = 0; i < data_length; i++) { + tx_element.data[i] = data[i]; + } + + mcan_set_tx_buffer_element(&mcan_instance, &tx_element, put_index); + mcan_tx_transfer_request(&mcan_instance, (1 << put_index)); + + return true; +} + +/* Returns data length received or zero for no messages available. +*/ +uint8_t mcan_receive_message(uint32_t *id_value, uint8_t *data) +{ + uint32_t fifo_status; + + //Check standard message fifo + fifo_status = mcan_rx_get_fifo_status(&mcan_instance, 0); + if (fifo_status & MCAN_RXF0S_F0FL_Msk) + { + struct mcan_rx_element_fifo_0 rx_element_buffer; + uint32_t rx_fifo_index = (fifo_status >> MCAN_RXF0S_F0GI_Pos ) & 0x3fu; + + mcan_get_rx_fifo_0_element(&mcan_instance, &rx_element_buffer, rx_fifo_index); + mcan_rx_fifo_acknowledge(&mcan_instance, 0, rx_fifo_index); + + //Read out data + *id_value = rx_element_buffer.R0.bit.ID >> 18; + for(int i=0; i> MCAN_RXF1S_F1GI_Pos ) & 0x3fu; + + mcan_get_rx_fifo_1_element(&mcan_instance, &rx_element_buffer, rx_fifo_index); + mcan_rx_fifo_acknowledge(&mcan_instance, 1, rx_fifo_index); + + //Read out data + *id_value = rx_element_buffer.R0.bit.ID; + for(int i=0; i= 0x800) + { //extended id + struct mcan_extended_message_filter_element et_filter; + + if(extended_filter_count >= CONF_MCAN1_RX_EXTENDED_ID_FILTER_NUM) + return -1; + + mcan_get_extended_message_filter_element_default(&et_filter); + et_filter.F0.bit.EFID1 = id_value; + + mcan_set_rx_extended_filter(&mcan_instance, &et_filter, extended_filter_count); + + return extended_filter_count++; + } + else + { //standard id + struct mcan_standard_message_filter_element sd_filter; + + if(standard_filter_count >= CONF_MCAN1_RX_STANDARD_ID_FILTER_NUM) + return -1; + + mcan_get_standard_message_filter_element_default(&sd_filter); + sd_filter.S0.bit.SFID1 = id_value; + + mcan_set_rx_standard_filter(&mcan_instance, &sd_filter, standard_filter_count); + + return standard_filter_count++; + } +} + +#ifdef CONF_BOARD_CAN_TEST +/* Master device for CAN test + * This unit sends a message out the CAN bus then receives the return message and checks that it is valid. + */ +void mcan_test_master(void) +{ + uint8_t msg_cnt = 0; + + uint32_t success_count = 0; + uint32_t failure_count = 0; + + //Setup receive + mcan_set_rx_filter(MCAN_TEST_RECV_ID_STD); + mcan_set_rx_filter(MCAN_TEST_RECV_ID_EXT); + + while(1) + { + uint8_t can_tx_message[CONF_MCAN_ELEMENT_DATA_SIZE] = {}; + uint8_t can_rx_message[CONF_MCAN_ELEMENT_DATA_SIZE] = {}; + uint8_t len; + + //Create message + msg_cnt++; + len = 2 + rand() % 7; + + for(int i=0; i 0) + vTaskDelay(1); + + //Check return message + int i; + for(i=0; i 0) + { + //Change data and send back + for(int i=0; i 0) { +#if (__CM7_CMSIS_VERSION_SUB == 0x00) + SCB->DCIMVAU = op_addr; // 4.00 typo +#else + SCB->DCIMVAC = op_addr; +#endif // (__CM7_CMSIS_VERSION_SUB == 0x00) + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1) && (CONF_BOARD_ENABLE_DCACHE==1) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1U) && (CONF_BOARD_ENABLE_DCACHE==1) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + +#if CONF_BOARD_ENABLE_DCACHE == 1 + // move address back until it is 32 byte aligned, add to size the amount that address was moved back + #define SCB_CLEANINVALIDATE_DCACHE_BY_ADDR_32BYTE_ALIGNED(addr,size) SCB_CleanInvalidateDCache_by_Addr((uint32_t*)(((uint32_t)(addr))&0xFFFFFFE0), (size) + (((uint32_t)(addr))&0x0000001F)) + //This one can be unsafe + //#define SCB_INVALIDATE_DCACHE_BY_ADDR_32BYTE_ALIGNED(addr,size) SCB_InvalidateDCache_by_Addr((uint32_t*)(((uint32_t)(addr))&0xFFFFFFE0), (size) + (((uint32_t)(addr))&0x0000001F)) + #define SCB_CLEAN_DCACHE_BY_ADDR_32BYTE_ALIGNED(addr,size) SCB_CleanDCache_by_Addr((uint32_t*)(((uint32_t)(addr))&0xFFFFFFE0), (size) + (((uint32_t)(addr))&0x0000001F)) +#else + #define SCB_CLEANINVALIDATE_DCACHE_BY_ADDR_32BYTE_ALIGNED(addr,size) + #define SCB_CLEAN_DCACHE_BY_ADDR_32BYTE_ALIGNED(addr,size) +#endif + +#ifdef __cplusplus +} +#endif +#endif // __CORE_CM7_4_30_H diff --git a/hw-libs/drivers/SAMx70/d_dma.c b/hw-libs/drivers/SAMx70/d_dma.c new file mode 100644 index 000000000..c5e3e706c --- /dev/null +++ b/hw-libs/drivers/SAMx70/d_dma.c @@ -0,0 +1,223 @@ +#include +#include + +#ifdef ENABLE_DMA_INTERRUPTS +#include "conf_interrupts.h" +#endif // ENABLE_DMA_INTERRUPTS + +#ifdef DEBUG +//#define DMA_DEBUG +//#define DMA_SPI_DEBUG +//#define DMA_CACHE_DEBUG +#endif // DEBUG + +#ifdef __INERTIAL_SENSE_EVB_2__ +#include "spiTouINS.h" +#endif + +#include "d_dma.h" +#include "d_serial.h" + +#ifndef TESTBED +#include "d_i2c.h" +#endif + +#include "xdmac.h" + +static volatile uint8_t s_xfer_done[DMA_CHAN_COUNT] = {0}; + +void XDMAC_Handler(void) +{ + XDMAC_usartDMA_Handler(); + +#ifndef TESTBED + + XDMAC_i2c_Handler(); + +#ifdef __INERTIAL_SENSE_EVB_2__ + + #ifdef CONF_BOARD_SPI_UINS + //Forward for spiTouINS + XDMAC_spiTouINS_Handler(); + #endif + +#else // uINS-3 + + #ifdef ENABLE_SPI_COMM_INTERRUPTS + uint32_t status; + + // receive status + status = xdmac_channel_get_interrupt_status(XDMAC, DMA_CH_SPI_COMM_RX); + if (status & XDMAC_CIS_BIS) + { + NVIC_ClearPendingIRQ(XDMAC_IRQn); + NVIC_DisableIRQ(XDMAC_IRQn); + _handler(); + xdmac_channel_enable(XDMAC, DMA_CH_SPI_COMM_RX); + } + #endif // ENABLE_SPI_COMM_INTERRUPTS + +#endif // __INERTIAL_SENSE_EVB_2__ + +#endif // #ifndef TESTBED + +} + +#ifdef ENABLE_DMA_INTERRUPTS +void XDMAC_Handler(void) // We can't just merge this with the above function because reading status erases the interrupt flags. +{ + uint32_t i; + uint32_t status; + + for (i = 0; i < DMA_CHAN_COUNT; i++) + { + status = xdmac_channel_get_interrupt_status(XDMAC, i); + if (status & XDMAC_CIS_BIS) + { + s_xfer_done[i] = 1; + } + } +} +#endif // ENABLE_DMA_INTERRUPTS + + +#ifdef DMA_CACHE_DEBUG +static inline int verify_32byte_aligned(dma_channel_config_t *cc) +{ + int retval = 0; + if (cc->xdmac.mbr_cfg & XDMAC_CC_TYPE_PER_TRAN) + { + if (cc->xdmac.mbr_cfg & XDMAC_CC_DSYNC_MEM2PER) + { + if (!IS_32B_ALIGNED(cc->xdmac.mbr_sa)) + retval |= -1; + if (cc->next.len && !IS_32B_ALIGNED(cc->next.sa)) + retval |= -1; + } + else + { + if (!IS_32B_ALIGNED(cc->xdmac.mbr_da)) + retval |= -1; + if (cc->next.len && !IS_32B_ALIGNED(cc->next.da)) + retval |= -1; + } + } + else + { + if (!IS_32B_ALIGNED(cc->xdmac.mbr_da)) + retval |= -1; + if (!IS_32B_ALIGNED(cc->xdmac.mbr_sa)) + retval |= -1; + if (cc->next.len && !IS_32B_ALIGNED(cc->next.da)) + retval |= -1; + if (cc->next.len && !IS_32B_ALIGNED(cc->next.sa)) + retval |= -1; + } + return retval; +} +#endif // DMA_CACHE_DEBUG + + +inline int dma_configure(dma_channel_config_t* cc, lld_view1* lld) +{ + static xdmac_channel_config_t xdmac = {0}; + xdmac = cc->xdmac; // copy + +#ifdef DMA_CACHE_DEBUG + if (verify_32byte_aligned(cc) != 0) + { + halt(3); + } +#endif // DMA_CACHE_DEBUG + + // initialize channel config + xdmac.mbr_ubc = XDMAC_UBC_UBLEN(xdmac.mbr_ubc); + xdmac_configure_transfer(XDMAC, cc->chan, &xdmac); + + if (cc->next.len) + { + // initialize linked list descriptor + lld[0].mbr_nda = (uint32_t)(&lld[1]); + lld[0].mbr_ubc = XDMAC_UBC_NVIEW_NDV1 | + XDMAC_UBC_NDE_FETCH_EN | + XDMAC_UBC_NSEN | + XDMAC_UBC_NDEN | + cc->xdmac.mbr_ubc; + lld[0].mbr_sa = cc->xdmac.mbr_sa; + lld[0].mbr_da = cc->xdmac.mbr_da; + lld[1].mbr_nda = 0; + lld[1].mbr_ubc = XDMAC_UBC_UBLEN(cc->next.len); + lld[1].mbr_sa = cc->next.sa; + lld[1].mbr_da = cc->next.da; + + xdmac_channel_set_descriptor_control(XDMAC, cc->chan, + XDMAC_CNDC_NDVIEW_NDV1 | + XDMAC_CNDC_NDE_DSCR_FETCH_EN | + XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED | + XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED); + xdmac_channel_set_descriptor_addr(XDMAC, cc->chan, (uint32_t)lld, 0); + } + else + { + xdmac_channel_set_descriptor_control(XDMAC, cc->chan, 0); + } + + return 0; +} + + +void dma_init(void) +{ + // initialize and enable DMA controller + pmc_enable_periph_clk(ID_XDMAC); + +#ifdef ENABLE_DMA_INTERRUPTS + + // enable xdma interrupt + NVIC_DisableIRQ(XDMAC_IRQn); + NVIC_ClearPendingIRQ(XDMAC_IRQn); + NVIC_SetPriority(XDMAC_IRQn, INT_PRIORITY_DMA); + NVIC_EnableIRQ(XDMAC_IRQn); + +#endif // ENABLE_DMA_INTERRUPTS + +} + + +inline void dma_chan_disable(uint32_t ch) +{ + if (ch >= DMA_CHAN_COUNT) { return; } + +#ifndef ENABLE_DMA_INTERRUPTS + __DSB(); + s_xfer_done[ch] = !DMA_CHAN_BUSY(ch); +#endif // ENABLE_DMA_INTERRUPTS + + DMA_INT_DISABLE(ch); + xdmac_channel_disable(XDMAC, ch); +} + + +inline int dma_chan_enable(uint32_t ch) +{ + if (ch >= DMA_CHAN_COUNT) { return false; } + while (DMA_CHAN_BUSY(ch)) {} + s_xfer_done[ch] = 0; + DMA_INT_ENABLE(ch); + xdmac_channel_enable(XDMAC, ch); + + return 0; +} + + +int dma_transfer_is_complete(uint32_t ch) +{ + if (ch >= DMA_CHAN_COUNT) { return false; } + + #ifndef ENABLE_DMA_INTERRUPTS + __DSB(); + s_xfer_done[ch] = !DMA_CHAN_BUSY(ch); + #endif // ENABLE_DMA_INTERRUPTS + + return s_xfer_done[ch]; +} diff --git a/hw-libs/drivers/SAMx70/d_dma.h b/hw-libs/drivers/SAMx70/d_dma.h new file mode 100644 index 000000000..dc7fc04c2 --- /dev/null +++ b/hw-libs/drivers/SAMx70/d_dma.h @@ -0,0 +1,196 @@ +#ifndef _D_DMA_H_ +#define _D_DMA_H_ +#ifdef __cplusplus +extern "C" { +#endif // __cplusplus + +// includes +#include +#include "core_cm7_4p30.h" + +#if defined(__INERTIAL_SENSE_EVB_2__) || 1 + +#define MEMCPY_DCACHE_CLEAN(dst, src, size) \ +memcpy((void*)(dst), (const void*)(src), (size)); \ +SCB_CLEAN_DCACHE_BY_ADDR_32BYTE_ALIGNED((dst), (size)); + +// Memcpy then clear Data Cache to memory for before DMA starts +#define MEMCPY_DCACHE_CLEAN_INVALIDATE(dst, src, size) \ +memcpy((void*)(dst), (const void*)(src), (size)); \ +SCB_CLEANINVALIDATE_DCACHE_BY_ADDR_32BYTE_ALIGNED((dst), (size)); + +// Ensure data cache has valid Rx data prior to memcpy +#define DCACHE_CLEAN_INVALIDATE_MEMCPY(dst, src, size) \ +SCB_CLEANINVALIDATE_DCACHE_BY_ADDR_32BYTE_ALIGNED((src), (size)); \ +memcpy((void*)(dst), (const void*)(src), (size)); + +#else + +// Memcpy then clean Data Cache to memory for before DMA starts +#define MEMCPY_DCACHE_CLEAN(dst, src, size) \ +memcpy((void*)(dst), (const void*)(src), (size)); \ +DBGPIO_START(DBG_TX_DCACHE_CLEAN_PIN); \ +SCB_CLEAN_DCACHE_BY_ADDR_32BYTE_ALIGNED((dst), (size)); \ +DBGPIO_END(DBG_TX_DCACHE_CLEAN_PIN); + +// Memcpy then clear Data Cache to memory for before DMA starts +#define MEMCPY_DCACHE_CLEAN_INVALIDATE(dst, src, size) \ +memcpy((void*)(dst), (const void*)(src), (size)); \ +DBGPIO_START(DBG_TX_DCACHE_CLEAN_PIN); \ +SCB_CLEANINVALIDATE_DCACHE_BY_ADDR_32BYTE_ALIGNED((dst), (size)); \ +DBGPIO_END(DBG_TX_DCACHE_CLEAN_PIN); + +// Ensure data cache has valid Rx data prior to memcpy +#define DCACHE_CLEAN_INVALIDATE_MEMCPY(dst, src, size) \ +DBGPIO_START( DBG_RX_DCACHE_CLEAN_PIN ); \ +SCB_CLEANINVALIDATE_DCACHE_BY_ADDR_32BYTE_ALIGNED((src), (size)); \ +DBGPIO_END( DBG_RX_DCACHE_CLEAN_PIN ); \ +memcpy((void*)(dst), (const void*)(src), (size)); + +#endif + + +// defines +//#define ENABLE_DMA_INTERRUPTS // TODO: This will enable a duplicate XDMAC_Handler in d_dma.c. Might just remove this? +#ifdef ENABLE_DMA_INTERRUPTS +#define DMA_INT_ENABLE(_ch_) \ + xdmac_enable_interrupt(XDMAC, _ch_); \ + xdmac_channel_enable_interrupt(XDMAC, _ch_, XDMAC_CIE_BIE); +#define DMA_INT_DISABLE(_ch_) \ + xdmac_disable_interrupt(XDMAC, _ch_); \ + xdmac_channel_disable_interrupt(XDMAC, _ch_, XDMAC_CIE_BIE); +#else +#define DMA_INT_ENABLE(_ch_) +#define DMA_INT_DISABLE(_ch_) +#endif // ENABLE_DMA_INTERRUPTS + +// XDMAC channel HW Interface number for peripherals; refer to datasheet +#define XDMAC_PERID_SPI0_TX 1 +#define XDMAC_PERID_SPI0_RX 2 +#define XDMAC_PERID_SPI1_TX 3 +#define XDMAC_PERID_SPI1_RX 4 +#define XDMAC_PERID_USART0_TX 7 +#define XDMAC_PERID_USART0_RX 8 +#define XDMAC_PERID_USART1_TX 9 +#define XDMAC_PERID_USART1_RX 10 +#define XDMAC_PERID_USART2_TX 11 +#define XDMAC_PERID_USART2_RX 12 +#define XDMAC_PERID_TWIHS0_TX 14 +#define XDMAC_PERID_TWIHS0_RX 15 +#define XDMAC_PERID_TWIHS1_TX 16 +#define XDMAC_PERID_TWIHS1_RX 17 +#define XDMAC_PERID_TWIHS2_TX 18 +#define XDMAC_PERID_TWIHS2_RX 19 +#define XDMAC_PERID_UART0_TX 20 +#define XDMAC_PERID_UART0_RX 21 +#define XDMAC_PERID_UART1_TX 22 +#define XDMAC_PERID_UART1_RX 23 +#define XDMAC_PERID_UART2_TX 24 +#define XDMAC_PERID_UART2_RX 25 +#define XDMAC_PERID_UART3_TX 26 +#define XDMAC_PERID_UART3_RX 27 +#define XDMAC_PERID_UART4_TX 28 +#define XDMAC_PERID_UART4_RX 29 + +// cache specific +#define ALIGN_32B_MASK 0xffffffe0 +#define IS_32B_ALIGNED(_addr_) !(((uint32_t)(_addr_)) & 0x0000001f) +#define ALIGN_32B(_bytes_) ((_bytes_) + (sizeof(uint32_t) - ((_bytes_) % sizeof(uint32_t)))) + +// enums +enum +{ + // uINS specific + DMA_CH_SPI_SENSORS_TX = 0, + DMA_CH_SPI_SENSORS_RX, + DMA_CH_SPI_COMM_TX, + DMA_CH_SPI_COMM_RX, + DMA_CH_USART_SERIAL0_TX, + DMA_CH_USART_SERIAL0_RX, + DMA_CH_USART_SERIAL1_TX, // Also used for SPI on uINS + DMA_CH_USART_SERIAL1_RX, // Also used for SPI on uINS + DMA_CH_USART_SERIAL2_TX, + DMA_CH_USART_SERIAL2_RX, + DMA_CH_USART_GPS1_TX, + DMA_CH_USART_GPS1_RX, + DMA_CH_USART_GPS2_TX, + DMA_CH_USART_GPS2_RX, + DMA_CH_I2C_SENSORS_TX, + DMA_CH_I2C_SENSORS_RX, + // add more channels before this line + DMA_CHAN_COUNT, + DMA_CHAN_MAX = 24 +}; + +// enums +enum +{ + // EVB-2 specific + DMA_CH_EVB_SPI_SENSORS_TX = 0, + DMA_CH_EVB_SPI_SENSORS_RX, + DMA_CH_EVB_SPI_COMM_TX, + DMA_CH_EVB_SPI_COMM_RX, + DMA_CH_EVB_UART_UINS0_TX, + DMA_CH_EVB_UART_UINS0_RX, + DMA_CH_EVB_UART_UINS1_TX, + DMA_CH_EVB_UART_UINS1_RX, + DMA_CH_EVB_UART_XBEE_TX, + DMA_CH_EVB_UART_XBEE_RX, + DMA_CH_EVB_UART_XRADIO_TX, + DMA_CH_EVB_UART_XRADIO_RX, + DMA_CH_EVB_UART_WINC_BLE_TX, + DMA_CH_EVB_UART_WINC_BLE_RX, + DMA_CH_EVB_UART_SP330_TX, + DMA_CH_EVB_UART_SP330_RX, + DMA_CH_EVB_UART_GPIO_TTL_TX, + DMA_CH_EVB_UART_GPIO_TTL_RX, + DMA_CH_EVB_SD_CARD, + DMA_CH_EVB_SPI_INS_TX, + DMA_CH_EVB_SPI_INS_RX, + DMA_CH_EVB_I2C_SENSORS_TX, + DMA_CH_EVB_I2C_SENSORS_RX, + // add more channels before this line + DMA_EVB_CHAN_COUNT, + DMA_EVB_CHAN_MAX = 24 +}; + +// enums +enum +{ + // testbed specific + DMA_CH_TESTBED_UINS_TX = 0, + DMA_CH_TESTBED_UINS_RX, // Unused + DMA_CH_TESTBED_SENSONOR_TX, + DMA_CH_TESTBED_SENSONOR_RX, + // add more channels before this line + DMA_TESTBED_CHAN_COUNT, + DMA_TESTBED_CHAN_MAX = 24 +}; + +// structs +typedef struct +{ + uint32_t len : 24; + uint32_t sa; + uint32_t da; +} dma_transfer_info_t; + +typedef struct +{ + uint32_t chan; + xdmac_channel_config_t xdmac; + dma_transfer_info_t next; +} dma_channel_config_t; + +// prototypes +void dma_init(void); + +int dma_configure(dma_channel_config_t* hd, lld_view1* lld); +void dma_chan_disable(uint32_t ch); +int dma_chan_enable(uint32_t ch); +int dma_transfer_is_complete(uint32_t ch); + +#ifdef __cplusplus +} +#endif // __cplusplus +#endif // _D_DMA_H_ diff --git a/hw-libs/drivers/SAMx70/d_flash.c b/hw-libs/drivers/SAMx70/d_flash.c new file mode 100644 index 000000000..09f47c66e --- /dev/null +++ b/hw-libs/drivers/SAMx70/d_flash.c @@ -0,0 +1,198 @@ +/* +MIT LICENSE + +Copyright 2014-2019 Inertial Sense, Inc. - http://inertialsense.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions : + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +#include +#include +#include "globals.h" +#include "bootloaderShared.h" +#include "rtos.h" +#include "d_flash.h" +#include "ISBoards.h" + +static int s_flashWriteInProgress; + +uint32_t flash_update_block(uint32_t address, const void* newData, int dataSize, int noPageErase) +{ + uint32_t result; + + if (address < BOOTLOADER_FLASH_USER_DATA_START_ADDRESS || + address >= BOOTLOADER_FLASH_USER_DATA_END_ADDRESS || + (noPageErase==0 && address % BOOTLOADER_FLASH_BLOCK_SIZE != 0) || + dataSize > (int)BOOTLOADER_FLASH_BLOCK_SIZE ) + { + result = FLASH_RC_INVALID; + } + else if (memcmp((const void*)address, newData, dataSize) == 0) + { + // memory is identical, do not write + result = FLASH_RC_OK; + } + else // if contents are different, perform the flash write + { + // assume failure unless we succeed + result = FLASH_RC_ERROR; + + // http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11242-32-bit-Cortex-M7-Microcontroller-SAM-S70Q-SAM-S70N-SAM-S70J_Datasheet.pdf + // page 45 + + // unlock the block + s_flashWriteInProgress = 1; + flash_unlock(address, address + dataSize - 1, 0, 0); + + // try up to 10 times to write flash, recommended by Atmel + for (int i = 0; i < 10; i++) + { + if(!noPageErase) + { // erase flash - Only works for 16 pages (8192 bytes) and NOT less. + result = flash_erase_page(address, IFLASH_ERASE_PAGES_16); + } + else + { // skip flash erase + result = FLASH_RC_OK; + } + + // erase flash - Only works for 16 pages (8192 bytes) and NOT less. + if (result == FLASH_RC_OK) + { + // write new flash + result = flash_write(address, newData, dataSize, 0); + + if (result == FLASH_RC_OK && memcmp((const void*)address, newData, dataSize) == 0) + { + result = FLASH_RC_OK; + break; + } + } + time_delay_msec(2); + } + + // lock the block + flash_lock(address, address + dataSize - 1, 0, 0); + + s_flashWriteInProgress = 0; + } + + return result; +} + +uint32_t flash_erase_block(uint32_t address) +{ + if (address < BOOTLOADER_FLASH_USER_DATA_START_ADDRESS || address >= BOOTLOADER_FLASH_USER_DATA_END_ADDRESS || address % BOOTLOADER_FLASH_BLOCK_SIZE != 0) + { + return FLASH_RC_INVALID; + } + +#ifdef ENABLE_WDT + WDT->WDT_CR = 0xA5000000 | WDT_CR_WDRSTT; // restart watchdog +#endif + + flash_unlock(address, address + BOOTLOADER_FLASH_BLOCK_SIZE - 1, 0, 0); + return flash_erase_page(address, IFLASH_ERASE_PAGES_16); +} + +#ifdef ENABLE_WDT +#define UPDATE_WATCHDOG() { WDT->WDT_CR = 0xA5000000 | WDT_CR_WDRSTT; } +#else +#define UPDATE_WATCHDOG() {} +#endif + +extern uint32_t efc_perform_fcr(Efc *p_efc, uint32_t ul_fcr); +__no_inline RAMFUNC void flash_reboot_down(int chip_erase) +{ + LED_COLOR_RED(); + + cpu_irq_disable(); + UPDATE_WATCHDOG(); + + // Make sure all blocks are unlocked + flash_unlock(IFLASH_ADDR, IFLASH_ADDR + IFLASH_SIZE, NULL, NULL); + + if (chip_erase) + { // Issue erase - After this we cannot access any functions in flash as it will be gone. + EFC->EEFC_FCR = EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FCMD(EFC_FCMD_EA); + while ((EFC->EEFC_FSR & EEFC_FSR_FRDY) != EEFC_FSR_FRDY) + UPDATE_WATCHDOG(); + } + + //Clear GPNVM Bits + EFC->EEFC_FCR = EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FARG(0) | EEFC_FCR_FCMD(EFC_FCMD_CGPB); //Protect bit + while ((EFC->EEFC_FSR & EEFC_FSR_FRDY) != EEFC_FSR_FRDY) + UPDATE_WATCHDOG(); + + EFC->EEFC_FCR = EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FARG(1) | EEFC_FCR_FCMD(EFC_FCMD_CGPB); //Enter SAM-BA + while ((EFC->EEFC_FSR & EEFC_FSR_FRDY) != EEFC_FSR_FRDY) + UPDATE_WATCHDOG(); + + EFC->EEFC_FCR = EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FARG(7) | EEFC_FCR_FCMD(EFC_FCMD_CGPB); //TCM config + while ((EFC->EEFC_FSR & EEFC_FSR_FRDY) != EEFC_FSR_FRDY) + UPDATE_WATCHDOG(); + + EFC->EEFC_FCR = EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FARG(8) | EEFC_FCR_FCMD(EFC_FCMD_CGPB); //TCM config + while ((EFC->EEFC_FSR & EEFC_FSR_FRDY) != EEFC_FSR_FRDY) + UPDATE_WATCHDOG(); + + LEDS_ALL_OFF(); + + //Reset Device + RSTC->RSTC_CR = RSTC_CR_KEY_PASSWD | RSTC_CR_PROCRST; + while(1); +} + +extern uint32_t efc_perform_fcr(Efc *p_efc, uint32_t ul_fcr); +__no_inline RAMFUNC void flash_rom_bootloader(void) +{ + // Reboot into ROM bootloader mode + flash_reboot_down(0); +} + +extern uint32_t efc_perform_fcr(Efc *p_efc, uint32_t ul_fcr); +__no_inline RAMFUNC void flash_erase_chip(void) +{ + // chip erase and reboot into ROM bootloader mode + flash_reboot_down(1); +} + +uint32_t flash_get_user_signature(volatile void* ptr, uint32_t size) +{ + BEGIN_CRITICAL_SECTION + + uint32_t ret = flash_read_user_signature((uint32_t*)ptr, size / sizeof(uint32_t)); + + END_CRITICAL_SECTION + + return ret; +} + +uint32_t flash_set_user_signature(const volatile void *ptr, uint32_t size) +{ + // get copy of user signature in critical section + BEGIN_CRITICAL_SECTION + + uint32_t* ptrCopy = (uint32_t*)pvPortMalloc(size); + memcpy(ptrCopy, (const void*)ptr, size); + + END_CRITICAL_SECTION + + // erase user signature first + flash_erase_user_signature(); + + // perform flash write with copy of data outside critical section, size for this function is + // number of 32 bit words. + uint32_t result = flash_write_user_signature(ptrCopy, size / sizeof(uint32_t)); + vPortFree(ptrCopy); + return result; +} + +int flash_write_in_progress(void) +{ + return s_flashWriteInProgress; +} diff --git a/hw-libs/drivers/SAMx70/d_flash.h b/hw-libs/drivers/SAMx70/d_flash.h new file mode 100644 index 000000000..04e071652 --- /dev/null +++ b/hw-libs/drivers/SAMx70/d_flash.h @@ -0,0 +1,56 @@ +/* +MIT LICENSE + +Copyright 2014-2019 Inertial Sense, Inc. - http://inertialsense.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions : + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +#ifndef D_FLASH_H_ +#define D_FLASH_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define FLASH_BLOCK_SIZE BOOTLOADER_FLASH_BLOCK_SIZE +#define FLASH_CALIB_BASE_ADDRESS BOOTLOADER_FLASH_CALIB_BASE_ADDRESS +#define FLASH_CONFIG_BASE_ADDRESS BOOTLOADER_FLASH_CONFIG_BASE_ADDRESS +#define FLASH_CONFIG_MIRROR_BASE_ADDRESS BOOTLOADER_FLASH_CONFIG_MIRROR_BASE_ADDRESS + +#define FLASH_GPNVM_SECURITY_BIT 0 +#define FLASH_GPNVM_BOOTMODE_BIT 1 // clear:ROM, set:Flash + +// uINS-3 flash layout - uINS Flash Memory Map at top of bootloaderShared.h + +// write data at the given 8KB aligned flash address +// address the 8KB aligned flash address to write at +// newData is the new bytes to put in the block starting at offset - must be exactly 8K (flash block size) in size +// return FLASH_RC_OK if success, otherwise error code +uint32_t flash_update_block(uint32_t address, const void* newData, int dataSize, int noPageErase); + +// erase the flash block at the 8K aligned address +uint32_t flash_erase_block(uint32_t address); + +// Reboot into SAM-BA (ROM bootloader) - Since it is a RAM function, it needs 'extern' declaration. +extern void flash_rom_bootloader(void); + +// Erase chip - Since it is a RAM function, it needs 'extern' declaration. +extern void flash_erase_chip(void); + +// read the user signature, size must be multiple of 4 and less than or equal to 512 +uint32_t flash_get_user_signature(volatile void* ptr, uint32_t size); + +// write the user signature, size must be multiple of 4 and less than or equal to 512 +uint32_t flash_set_user_signature(const volatile void* ptr, uint32_t size); + +// is a flash write in progress? 0 = no, 1 = yes +int flash_write_in_progress(void); + +#ifdef __cplusplus +} +#endif +#endif // D_FLASH_H_ diff --git a/hw-libs/drivers/SAMx70/d_i2c.c b/hw-libs/drivers/SAMx70/d_i2c.c new file mode 100644 index 000000000..f88b66bab --- /dev/null +++ b/hw-libs/drivers/SAMx70/d_i2c.c @@ -0,0 +1,409 @@ +/* +MIT LICENSE + +Copyright 2014-2019 Inertial Sense, Inc. - http://inertialsense.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions : + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + + +#include +#include +#include + +#include "d_i2c.h" + +#ifdef __INERTIAL_SENSE_EVB_2__ +i2c_t sn_i2c = {.instance_id = ID_TWIHS0, .instance = TWIHS0}; +#else +i2c_t sn_i2c = {.instance_id = ID_TWIHS1, .instance = TWIHS1}; +i2c_t ext_i2c_1 = {.instance_id = ID_TWIHS1, .instance = TWIHS1 }; +#endif + +//Configuration for TWI instance +#define TWI_CLK 400000 // EVB-2 uses below parameters to manually set the clock waveform + +#define I2C_HOLD 0x3F // Valid values 0x0 to 0x3F +#define I2C_CKDIV 0x6 // Valid values 0x1 to 0x7 +#define I2C_CHDIV 0xF // Valid values 0x0 to 0xFF +#define I2C_CLDIV 0xF // Valid values 0x0 to 0xFF + +#ifndef INT_PRIORITY_DMA +#define INT_PRIORITY_DMA 3 +#endif + +#define INT_PRIORITY_I2C INT_PRIORITY_DMA + +static const uint32_t _xdmaint = XDMAC_CIE_BIE; // End of Block Interrupt Enable + +static const uint32_t _i2cint = + TWIHS_IER_RXRDY | + TWIHS_IER_TXRDY; + +int i2c_master_get_defaults(i2c_t *i2c_init) +{ + i2c_init->cfg.master_clk = sysclk_get_peripheral_hz(); + i2c_init->cfg.speed = TWI_CLK; + i2c_init->cfg.chip = 0x40; + i2c_init->cfg.smbus = 0; + + i2c_init->tx_status = I2C_TXSTATUS_IDLE; + i2c_init->rx_status = I2C_RXSTATUS_IDLE; + +#ifdef __INERTIAL_SENSE_EVB_2__ + i2c_init->rx_dma.chan = DMA_CH_EVB_I2C_SENSORS_RX; + i2c_init->tx_dma.chan = DMA_CH_EVB_I2C_SENSORS_TX; +#else + i2c_init->rx_dma.chan = DMA_CH_I2C_SENSORS_RX; + i2c_init->tx_dma.chan = DMA_CH_I2C_SENSORS_TX; +#endif + + i2c_init->rx_dma.xdmac.mbr_sa = (uint32_t)&(i2c_init->instance->TWIHS_RHR); + i2c_init->rx_dma.xdmac.mbr_cfg = + XDMAC_CC_TYPE_PER_TRAN | + XDMAC_CC_MBSIZE_SINGLE | + XDMAC_CC_DSYNC_PER2MEM | + XDMAC_CC_MEMSET_NORMAL_MODE | + XDMAC_CC_CSIZE_CHK_1 | + XDMAC_CC_DWIDTH_BYTE | + XDMAC_CC_SIF_AHB_IF1 | + XDMAC_CC_DIF_AHB_IF0 | + XDMAC_CC_SAM_FIXED_AM | + XDMAC_CC_DAM_INCREMENTED_AM; + i2c_init->rx_dma.xdmac.mbr_ubc = 0; + + i2c_init->tx_dma.xdmac.mbr_da = (uint32_t)&(i2c_init->instance->TWIHS_THR); + i2c_init->tx_dma.xdmac.mbr_sa = (uint32_t)i2c_init->tx_buf; + i2c_init->tx_dma.xdmac.mbr_cfg = + XDMAC_CC_TYPE_PER_TRAN | + XDMAC_CC_MBSIZE_SINGLE | + XDMAC_CC_DSYNC_MEM2PER | + XDMAC_CC_MEMSET_NORMAL_MODE | + XDMAC_CC_CSIZE_CHK_1 | + XDMAC_CC_DWIDTH_BYTE | + XDMAC_CC_SIF_AHB_IF0 | + XDMAC_CC_DIF_AHB_IF1 | + XDMAC_CC_SAM_INCREMENTED_AM | + XDMAC_CC_DAM_FIXED_AM; + i2c_init->tx_dma.xdmac.mbr_ubc = 0; + + if(i2c_init->instance == TWIHS0) + { + i2c_init->tx_dma.xdmac.mbr_cfg |= XDMAC_CC_PERID(XDMAC_PERID_TWIHS0_TX); + i2c_init->rx_dma.xdmac.mbr_cfg |= XDMAC_CC_PERID(XDMAC_PERID_TWIHS0_RX); + } + else if(i2c_init->instance == TWIHS1) + { + i2c_init->tx_dma.xdmac.mbr_cfg |= XDMAC_CC_PERID(XDMAC_PERID_TWIHS1_TX); + i2c_init->rx_dma.xdmac.mbr_cfg |= XDMAC_CC_PERID(XDMAC_PERID_TWIHS1_RX); + } + else if(i2c_init->instance == TWIHS2) + { + i2c_init->tx_dma.xdmac.mbr_cfg |= XDMAC_CC_PERID(XDMAC_PERID_TWIHS2_TX); + i2c_init->rx_dma.xdmac.mbr_cfg |= XDMAC_CC_PERID(XDMAC_PERID_TWIHS2_RX); + } + + return STATUS_OK; +} + + +static void i2c_master_dma_init_rx(i2c_t *i2c_init) +{ + xdmac_configure_transfer(XDMAC, i2c_init->rx_dma.chan, &i2c_init->rx_dma.xdmac); + + xdmac_channel_set_descriptor_control(XDMAC, i2c_init->rx_dma.chan, 0); + + xdmac_enable_interrupt(XDMAC, i2c_init->rx_dma.chan); + xdmac_channel_enable_interrupt(XDMAC, i2c_init->rx_dma.chan, _xdmaint); + + NVIC_DisableIRQ(XDMAC_IRQn); + NVIC_ClearPendingIRQ(XDMAC_IRQn); + NVIC_SetPriority(XDMAC_IRQn, INT_PRIORITY_DMA); + NVIC_EnableIRQ(XDMAC_IRQn); +} + +static void i2c_master_dma_config_rx(i2c_t *i2c_init, uint8_t *buf, uint32_t len) +{ + i2c_init->rx_dma.xdmac.mbr_da = (uint32_t)buf; + i2c_init->rx_dma.xdmac.mbr_ubc = len; + + xdmac_configure_transfer(XDMAC, i2c_init->rx_dma.chan, &i2c_init->rx_dma.xdmac); +} + +static void i2c_master_dma_start_rx(i2c_t *i2c_init) +{ + xdmac_channel_enable_no_cache(XDMAC, i2c_init->rx_dma.chan); +} + +static void i2c_master_dma_stop_rx(i2c_t *i2c_init) +{ + xdmac_channel_disable(XDMAC, i2c_init->rx_dma.chan); + + SCB_InvalidateDCache_by_Addr((uint32_t *)i2c_init + (I2C_BUF_SIZE_TX / sizeof(uint32_t)), (i2c_init->rx_len)); +} + +static void i2c_master_dma_init_tx(i2c_t *i2c_init) +{ + xdmac_configure_transfer(XDMAC, i2c_init->tx_dma.chan, &i2c_init->tx_dma.xdmac); + + xdmac_channel_set_descriptor_control(XDMAC, i2c_init->tx_dma.chan, 0); + + xdmac_enable_interrupt(XDMAC, i2c_init->tx_dma.chan); + xdmac_channel_enable_interrupt(XDMAC, i2c_init->tx_dma.chan, _xdmaint); + NVIC_DisableIRQ(XDMAC_IRQn); + NVIC_ClearPendingIRQ(XDMAC_IRQn); + NVIC_SetPriority(XDMAC_IRQn, INT_PRIORITY_DMA); + NVIC_EnableIRQ(XDMAC_IRQn); +} + +static void i2c_master_dma_config_tx(i2c_t *i2c_init, uint8_t *buf, uint32_t len) +{ + if(len > I2C_BUF_SIZE_TX) + len = I2C_BUF_SIZE_TX; + + memcpy((uint8_t*)i2c_init->tx_buf, buf, len); + i2c_init->tx_dma.xdmac.mbr_ubc = len; + xdmac_configure_transfer(XDMAC, i2c_init->tx_dma.chan, &i2c_init->tx_dma.xdmac); +} + +static void i2c_master_dma_start_tx(i2c_t *i2c_init) +{ + SCB_CleanDCache_by_Addr((uint32_t *)i2c_init, I2C_BUF_SIZE_TX); + xdmac_channel_enable_no_cache(XDMAC, i2c_init->tx_dma.chan); +} + +static void i2c_master_dma_stop_tx(i2c_t *i2c_init) +{ + xdmac_channel_disable(XDMAC, i2c_init->tx_dma.chan); +} + + +/* + * Make sure to call i2c_get_defaults() first + */ +int i2c_master_init(i2c_t *i2c_init) // TODO: Rewrite this so it can be used for any instance of I2C +{ + // Configure pins (done in common location on uINS-3) + // TODO: Move out of this function and into EVB-2 project +#ifdef __INERTIAL_SENSE_EVB_2__ + ioport_set_pin_peripheral_mode(I2C_0_SDA_PIN, I2C_0_SDA_FLAGS); + ioport_set_pin_peripheral_mode(I2C_0_SCL_PIN, I2C_0_SCL_FLAGS); +#endif + + sysclk_enable_peripheral_clock(i2c_init->instance_id); + + i2c_init->instance->TWIHS_CR |= TWIHS_CR_SWRST; + + if(twihs_master_init(i2c_init->instance, &i2c_init->cfg) != TWIHS_SUCCESS) + return -1; + +#ifdef __INERTIAL_SENSE_EVB_2__ // Set the clock waveform generator register manually on the EVB2 + i2c_init->instance->TWIHS_FILTR |= TWIHS_FILTR_FILT | 0x7 << TWIHS_FILTR_THRES_Pos; + i2c_init->instance->TWIHS_CWGR = + I2C_HOLD << TWIHS_CWGR_HOLD_Pos + | I2C_CKDIV << TWIHS_CWGR_CKDIV_Pos + | I2C_CHDIV << TWIHS_CWGR_CHDIV_Pos + | I2C_CLDIV << TWIHS_CWGR_CLDIV_Pos; +#endif + + if(i2c_init->instance == TWIHS0) + { + NVIC_DisableIRQ(TWIHS0_IRQn); + NVIC_ClearPendingIRQ(TWIHS0_IRQn); + NVIC_SetPriority(TWIHS0_IRQn, INT_PRIORITY_I2C); + NVIC_EnableIRQ(TWIHS0_IRQn); + } + else if(i2c_init->instance == TWIHS1) + { + NVIC_DisableIRQ(TWIHS1_IRQn); + NVIC_ClearPendingIRQ(TWIHS1_IRQn); + NVIC_SetPriority(TWIHS1_IRQn, INT_PRIORITY_I2C); + NVIC_EnableIRQ(TWIHS1_IRQn); + } + else if(i2c_init->instance == TWIHS2) + { + NVIC_DisableIRQ(TWIHS2_IRQn); + NVIC_ClearPendingIRQ(TWIHS2_IRQn); + NVIC_SetPriority(TWIHS2_IRQn, INT_PRIORITY_I2C); + NVIC_EnableIRQ(TWIHS2_IRQn); + } + + i2c_master_dma_init_rx(i2c_init); + i2c_master_dma_init_tx(i2c_init); + + twihs_enable_interrupt(i2c_init->instance, TWIHS_IER_ARBLST); // Arbitration lost interrupt enable + + return 0; +} + +int i2c_master_write(i2c_t *i2c_init, uint16_t addr, uint8_t *buf, uint8_t len) +{ + /* Check argument */ + if (len == 0) { + return -1; + } + + if(!(i2c_init->instance->TWIHS_SR & TWIHS_SR_TXRDY)) + { + return -1; + } + + // Bypass DMA + if (len == 1) { + i2c_init->instance->TWIHS_MMR = TWIHS_MMR_DADR(addr); + i2c_init->instance->TWIHS_THR = buf[0]; + i2c_init->instance->TWIHS_CR = TWIHS_CR_STOP; + return 0; + } + + i2c_master_dma_config_tx(i2c_init, buf, len-1); // Datasheet says we have to transmit last byte manually + i2c_init->tx_last_byte = buf[len-1]; // Last byte gets stored + + /* Set write mode, slave address and 3 internal address byte lengths */ + i2c_init->instance->TWIHS_MMR = TWIHS_MMR_DADR(addr); + + i2c_init->tx_status = I2C_TXSTATUS_TRANSMIT_DMA; + + i2c_master_dma_start_tx(i2c_init); + + return 0; +} + +int i2c_master_read(i2c_t *i2c_init, uint16_t addr, uint8_t *buf, uint8_t len) +{ + /* Check argument */ + if (len == 0) { + return -1; + } + + i2c_init->rx_len = len; + i2c_init->rx_buf_dest = buf; + + if (len == 1) { + i2c_init->rx_status = I2C_RXSTATUS_READ_PENULTIMATE; + i2c_init->instance->TWIHS_MMR = TWIHS_MMR_DADR(addr) | TWIHS_MMR_MREAD; + twihs_enable_interrupt(sn_i2c.instance, TWIHS_IER_RXRDY); + i2c_init->instance->TWIHS_CR |= TWIHS_CR_START | TWIHS_CR_STOP; + return 0; + } + + if (len == 2) { + i2c_init->rx_status = I2C_RXSTATUS_READ_DMA_WAIT_RXRDY; + i2c_init->instance->TWIHS_MMR = TWIHS_MMR_DADR(addr) | TWIHS_MMR_MREAD; + twihs_enable_interrupt(sn_i2c.instance, TWIHS_IER_RXRDY); + i2c_init->instance->TWIHS_CR |= TWIHS_CR_START; + return 0; + } + + i2c_master_dma_config_rx(i2c_init, i2c_init->rx_buf, len-2); // Datasheet says we have to read last 2 bytes manually + + /* Set write mode, slave address and 3 internal address byte lengths */ + i2c_init->instance->TWIHS_MMR = TWIHS_MMR_DADR(addr) | TWIHS_MMR_MREAD; + + i2c_init->rx_status = I2C_RXSTATUS_READ_DMA; + + i2c_master_dma_start_rx(i2c_init); + + i2c_init->instance->TWIHS_CR |= TWIHS_CR_START; + + return 0; +} + +uint8_t i2c_get_status(i2c_t *i2c_init) +{ + uint8_t status = 0; + + if(i2c_init->rx_status != I2C_RXSTATUS_IDLE) + status |= I2C_STATUS_RXBUSY; + if(i2c_init->tx_status != I2C_TXSTATUS_IDLE) + status |= I2C_STATUS_TXBUSY; + + return status; +} + +static void TWIHS_Handler(i2c_t *i2c_init) +{ + uint32_t status = i2c_init->instance->TWIHS_SR; + if(status & TWIHS_SR_ARBLST) + { + + } + + if(status & TWIHS_SR_TXRDY && i2c_init->tx_status != I2C_TXSTATUS_IDLE) + { + twihs_disable_interrupt(i2c_init->instance, TWIHS_IDR_TXRDY); // Without this we get spammed by the interrupt + + if(i2c_init->tx_status == I2C_TXSTATUS_TRANSMIT_DMA_WAIT_TXRDY) + { + i2c_init->instance->TWIHS_CR |= TWIHS_CR_STOP; + i2c_init->instance->TWIHS_THR = i2c_init->tx_last_byte; + + i2c_init->tx_status = I2C_TXSTATUS_IDLE; + } + } + + if(status & TWIHS_SR_RXRDY) + { + if(i2c_init->rx_status == I2C_RXSTATUS_READ_DMA_WAIT_RXRDY) + { + i2c_init->instance->TWIHS_CR |= TWIHS_CR_STOP; + + i2c_init->rx_buf[i2c_init->rx_len - 2] = i2c_init->instance->TWIHS_RHR; + + i2c_init->rx_status = I2C_RXSTATUS_READ_PENULTIMATE; + } + else if(i2c_init->rx_status == I2C_RXSTATUS_READ_PENULTIMATE) + { + i2c_init->rx_buf[i2c_init->rx_len - 1] = i2c_init->instance->TWIHS_RHR; + + twihs_disable_interrupt(i2c_init->instance, TWIHS_IDR_RXRDY); + + memcpy(i2c_init->rx_buf_dest, i2c_init->rx_buf, i2c_init->rx_len); + + i2c_init->rx_status = I2C_RXSTATUS_IDLE; + } + } +} + +#ifdef __INERTIAL_SENSE_EVB_2__ +void TWIHS0_Handler(void) +{ + TWIHS_Handler(&sn_i2c); +} +#else +void TWIHS1_Handler(void) +{ + TWIHS_Handler(&sn_i2c); +} +#endif + +/* + * Sub-handler that is called from the XDMAC_Handler() in d_dma.c + */ +void XDMAC_i2c_Handler(void) +{ + uint32_t status = XDMAC->XDMAC_CHID[sn_i2c.rx_dma.chan].XDMAC_CIS; + + if((status & XDMAC_CIS_BIS) && (sn_i2c.rx_status == I2C_RXSTATUS_READ_DMA)) + { + //DBGPIO_START(DBG_MISC_DEBUG_PIN); + i2c_master_dma_stop_rx(&sn_i2c); + //DBGPIO_END(DBG_MISC_DEBUG_PIN); + sn_i2c.rx_status = I2C_RXSTATUS_READ_DMA_WAIT_RXRDY; + twihs_enable_interrupt(sn_i2c.instance, TWIHS_IER_RXRDY); + } + + status = XDMAC->XDMAC_CHID[sn_i2c.tx_dma.chan].XDMAC_CIS; + + if((status & XDMAC_CIS_BIS) && (sn_i2c.tx_status == I2C_TXSTATUS_TRANSMIT_DMA)) + { + i2c_master_dma_stop_tx(&sn_i2c); + + sn_i2c.tx_status = I2C_TXSTATUS_TRANSMIT_DMA_WAIT_TXRDY; + twihs_enable_interrupt(sn_i2c.instance, TWIHS_IER_TXRDY); + } +} diff --git a/hw-libs/drivers/SAMx70/d_i2c.h b/hw-libs/drivers/SAMx70/d_i2c.h new file mode 100644 index 000000000..883ba49c5 --- /dev/null +++ b/hw-libs/drivers/SAMx70/d_i2c.h @@ -0,0 +1,87 @@ +/* +MIT LICENSE + +Copyright 2014-2019 Inertial Sense, Inc. - http://inertialsense.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions : + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +#ifndef D_I2C_H_ +#define D_I2C_H_ + +#include "compiler.h" +#include "d_dma.h" +#include "twihs.h" +//#include "debug_gpio.h" + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define I2C_BUF_SIZE_TX 256 // MUST be a multiple of 4 (8-bit writes have to fit into 32-bit blocks for pre-tx cache clear to work) +#define I2C_BUF_SIZE_RX 256 // MUST be a multiple of 4 (8-bit reads have to fit into 32-bit blocks for post-rx cache invalidate to work) + +enum +{ + I2C_TXSTATUS_IDLE = 0, + I2C_TXSTATUS_TRANSMIT_DMA, + I2C_TXSTATUS_TRANSMIT_DMA_WAIT_TXRDY, + I2C_TXSTATUS_ERROR, +}; + +enum +{ + I2C_RXSTATUS_IDLE = 0, + I2C_RXSTATUS_READ_DMA, + I2C_RXSTATUS_READ_DMA_WAIT_RXRDY, + I2C_RXSTATUS_READ_PENULTIMATE, + I2C_RXSTATUS_READ_LAST, + I2C_RXSTATUS_ERROR, +}; + +enum +{ + I2C_STATUS_RXBUSY = 0b00000001, + I2C_STATUS_TXBUSY = 0b00000010, +}; + +typedef struct +{ + uint8_t tx_buf[I2C_BUF_SIZE_TX]; // MUST BE FIRST for cache stuff + uint8_t rx_buf[I2C_BUF_SIZE_RX]; // MUST BE SECOND for cache stuff + Twihs *instance; + uint32_t instance_id; + dma_channel_config_t rx_dma; + dma_channel_config_t tx_dma; + twihs_options_t cfg; + uint8_t tx_last_byte; + volatile uint8_t tx_status; + volatile uint8_t rx_status; + uint8_t *rx_buf_dest; // Destination for data to be copied to after read + uint8_t rx_len; +} i2c_t; + +extern i2c_t __attribute__((aligned(4))) sn_i2c; +extern i2c_t __attribute__((aligned(4))) ext_i2c_1; + +int i2c_master_get_defaults(i2c_t *init); +int i2c_master_init(i2c_t *init); + +int i2c_master_write(i2c_t *init, uint16_t addr, uint8_t *buf, uint8_t len); +int i2c_master_read(i2c_t *init, uint16_t addr, uint8_t *buf, uint8_t len); + +uint8_t i2c_get_status(i2c_t *init); + +void XDMAC_i2c_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif // D_I2C_H_ diff --git a/hw-libs/drivers/SAMx70/d_serial.c b/hw-libs/drivers/SAMx70/d_serial.c new file mode 100644 index 000000000..a3bd2164f --- /dev/null +++ b/hw-libs/drivers/SAMx70/d_serial.c @@ -0,0 +1,1728 @@ +/* +MIT LICENSE + +Copyright 2014-2019 Inertial Sense, Inc. - http://inertialsense.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions : + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + + +#include +#include +#include + +#include "d_serial.h" + +#ifdef CONF_BOARD_SPI_UINS + #include "spiTouINS.h" +#endif + +#include "d_dma.h" +#include "usart.h" +#include "../../src/ISComm.h" +#include "ISBoards.h" +#include "globals.h" +#include "FreeRTOSConfig.h" +#include "FreeRTOS.h" +#include "task.h" + +#ifdef TESTBED +// #define mbr_ta mbr_da +#endif + +//Structures for driver +#define DMA_LLD_COUNT 32 //Must be 2^x in size +#define DMA_LLD_MASK (DMA_LLD_COUNT - 1) + +typedef struct +{ + volatile XdmacChid *dmaChId; // Pointer to XDMA channel id + volatile uint8_t dmaChNumber; // DMA channel number + volatile uint32_t size; // DMA total buffer size + + // DMA buffer pointers: + volatile uint8_t *buf; // start + volatile uint8_t *end; // end + volatile uint8_t *ptr; // current location + + //Pointers for the lld_view0 array + volatile uint32_t lld_fptr; + volatile uint32_t lld_bptr; + + // DMA linked list descriptor used for reload + COMPILER_WORD_ALIGNED volatile lld_view0 lld[DMA_LLD_COUNT]; + + // Items for SPI mode + COMPILER_WORD_ALIGNED volatile lld_view0 lld_spi_noData[DMA_LLD_COUNT]; + +} dmaBuffer_tx_t; + +typedef struct +{ + volatile XdmacChid *dmaChId; // Pointer to XDMA channel id + volatile uint8_t dmaChNumber; // DMA channel number + volatile uint32_t size; // DMA total buffer size + volatile uint32_t lastUsedRx; // Track last used rx + volatile uint32_t timestampRx; // Timestamp of last data read + + // DMA buffer pointers: + volatile uint8_t *buf; // start + volatile uint8_t *end; // end + volatile uint8_t *ptr; // current location + + // DMA linked list descriptor used for reload + COMPILER_WORD_ALIGNED volatile lld_view0 lld; +} dmaBuffer_rx_t; + +typedef struct +{ + uint32_t ul_id; + uint32_t usartTxTHR; + uint32_t usartRxRHR; + uint32_t xdmacUsartTxPerId; // XDMAC channel "HW Interface Number (XDMAC_CC.PERID)". Refer to datasheet. + uint32_t xdmacUsartRxPerId; + uint8_t isUsartNotUart; + uint8_t isSpi; +} usart_info_t; + +typedef struct +{ + volatile void *peripheral; + sam_usart_opt_t usart_options; // Ignore on pure SPI peripheral (USART as SPI uses this) + dmaBuffer_tx_t dmaTx; + dmaBuffer_rx_t dmaRx; + usart_info_t uinfo; +} usartDMA_t; + +//Helper macros for port settings +#define CONCAT(A,B) A ## B +#define ARGN(N, LIST) CONCAT(ARG_, N) LIST +#define ARG_0(A0, ...) A0 +#define ARG_1(A0, A1, ...) A1 +#define ARG_2(A0, A1, A2, ...) A2 +#define ARG_3(A0, A1, A2, A3, ...) A3 +#define ARG_4(A0, A1, A2, A3, A4, ...) A4 + +//Buffers for serial ports +#if MAX_NUMBER_SERIAL_PORTS >= 1 + COMPILER_ALIGNED(32) static uint8_t g_serTxDmaBuf_port0[ARGN(2, PORT0_CONFIG)]; + COMPILER_ALIGNED(32) static uint8_t g_serRxDmaBuf_port0[ARGN(4, PORT0_CONFIG)]; +#endif + +#if MAX_NUMBER_SERIAL_PORTS >= 2 + COMPILER_ALIGNED(32) static uint8_t g_serTxDmaBuf_port1[ARGN(2, PORT1_CONFIG)]; + COMPILER_ALIGNED(32) static uint8_t g_serRxDmaBuf_port1[ARGN(4, PORT1_CONFIG)]; +#endif + +#if MAX_NUMBER_SERIAL_PORTS >= 3 + COMPILER_ALIGNED(32) static uint8_t g_serTxDmaBuf_port2[ARGN(2, PORT2_CONFIG)]; + COMPILER_ALIGNED(32) static uint8_t g_serRxDmaBuf_port2[ARGN(4, PORT2_CONFIG)]; +#endif + +#if MAX_NUMBER_SERIAL_PORTS >= 4 // USB + COMPILER_ALIGNED(32) static uint8_t g_serTxDmaBuf_port3[ARGN(2, PORT3_CONFIG)]; + COMPILER_ALIGNED(32) static uint8_t g_serRxDmaBuf_port3[ARGN(4, PORT3_CONFIG)]; +#endif + +#if MAX_NUMBER_SERIAL_PORTS >= 5 + COMPILER_ALIGNED(32) static uint8_t g_serTxDmaBuf_port4[ARGN(2, PORT4_CONFIG)]; + COMPILER_ALIGNED(32) static uint8_t g_serRxDmaBuf_port4[ARGN(4, PORT4_CONFIG)]; +#endif + +#if MAX_NUMBER_SERIAL_PORTS >= 6 + COMPILER_ALIGNED(32) static uint8_t g_serTxDmaBuf_port5[ARGN(2, PORT5_CONFIG)]; + COMPILER_ALIGNED(32) static uint8_t g_serRxDmaBuf_port5[ARGN(4, PORT5_CONFIG)]; +#endif + +#if MAX_NUMBER_SERIAL_PORTS >= 7 + COMPILER_ALIGNED(32) static uint8_t g_serTxDmaBuf_port6[ARGN(2, PORT6_CONFIG)]; + COMPILER_ALIGNED(32) static uint8_t g_serRxDmaBuf_port6[ARGN(4, PORT6_CONFIG)]; +#endif + +#if MAX_NUMBER_SERIAL_PORTS >= 8 + COMPILER_ALIGNED(32) static uint8_t g_serTxDmaBuf_port7[ARGN(2, PORT7_CONFIG)]; + COMPILER_ALIGNED(32) static uint8_t g_serRxDmaBuf_port7[ARGN(4, PORT7_CONFIG)]; +#endif + +#if MAX_NUMBER_SERIAL_PORTS >= 9 + #error "Need to add more support" +#endif + +//Variables for general use +COMPILER_ALIGNED(32) static uint8_t noData_indicator[1] = {0}; +static volatile usartDMA_t g_usartDMA[MAX_NUMBER_SERIAL_PORTS]; +static uint8_t s_txBufferOverrun=false; +port_monitor_helper_t g_portMonitorHelper[MAX_NUMBER_SERIAL_PORTS] = {0}; + + + +/********************************* USB CDC ********************************************************************************************************/ +static bool usb_cdc_open = false; + +bool d_usartDMA_callback_cdc_enable(void) +{ + usb_cdc_open = true; + return true; +} + +void d_usartDMA_callback_cdc_disable(void) +{ + usb_cdc_open = false; +} + +void d_usartDMA_callback_cdc_tx_empty_notify(void) +{ +#ifdef USB_PORT_NUM + dmaBuffer_tx_t *dma = (dmaBuffer_tx_t*)&g_usartDMA[USB_PORT_NUM].dmaTx; + + if(dma->ptr != dma->end) + { + //Get how much data is buffered + int data_avail; + if(dma->ptr >= dma->end) + data_avail = dma->ptr - dma->end; + else + data_avail = dma->ptr - dma->end + dma->size; + + //Prevent race conditions with interrupt + NVIC_DisableIRQ((IRQn_Type) ID_USBHS); + + //Get how much USB can take + int usb_avail = udi_cdc_get_free_tx_buffer(); + if(usb_avail) + { + int bytesToEnd = dma->buf + dma->size - dma->end; + int bytesToSend = Min(data_avail, usb_avail); + + if(bytesToSend < bytesToEnd) + { + udi_cdc_write_buf((void*)dma->end, bytesToSend); + dma->end += bytesToSend; + } + else + { + udi_cdc_write_buf((void*)dma->end, bytesToEnd); + dma->end = dma->buf; + } + } + + NVIC_EnableIRQ((IRQn_Type) ID_USBHS); + } +#endif +} + + +/********************************* INTERNAL BUFFER FUCTIONS ***************************************************************************************************/ +static inline const uint8_t* getCurrentTxDmaAddress( dmaBuffer_tx_t *dma ) +{ + //Check to see if we are using the no data array + if(dma->dmaChId->XDMAC_CSA >= (uint32_t)noData_indicator && dma->dmaChId->XDMAC_CSA <= ((uint32_t)noData_indicator+sizeof(noData_indicator))) + { + //We are not sending data. Send back pointer location. + return (const uint8_t*)dma->ptr; + } + + return (const uint8_t*)_CLAMP(dma->dmaChId->XDMAC_CSA, (uint32_t)dma->buf, (uint32_t)dma->end); +} + +static inline const uint8_t* getCurrentRxDmaAddress( dmaBuffer_rx_t *dma ) +{ + return (const uint8_t*)_CLAMP(dma->dmaChId->XDMAC_CDA, (uint32_t)dma->buf, (uint32_t)dma->end); +} + +static inline dmaBuffer_tx_t * getTxDma( uint32_t serialNum ) +{ + // Get the DMA buffer pointer + if (serialNum >= MAX_NUMBER_SERIAL_PORTS || !g_usartDMA[serialNum].peripheral) + return 0; + + return (dmaBuffer_tx_t*)&(g_usartDMA[serialNum].dmaTx); +} + +static inline dmaBuffer_rx_t * getRxDma( uint32_t serialNum ) +{ + // Get the DMA buffer pointer + if (serialNum >= MAX_NUMBER_SERIAL_PORTS || !g_usartDMA[serialNum].peripheral) + return 0; + + return (dmaBuffer_rx_t*)&(g_usartDMA[serialNum].dmaRx); +} + +static inline int serTxUsedDma( dmaBuffer_tx_t *dma) +{ + const uint8_t* curDmaAddr = getCurrentTxDmaAddress(dma); + + // not using int with abs value because we want full 32 bit memory addresses + if (dma->ptr < curDmaAddr) + { + // handle wrap + return (int)(dma->size - (curDmaAddr - dma->ptr)); + } + return (int)(dma->ptr - curDmaAddr); +} + +static inline int serRxUsedDma( dmaBuffer_rx_t *dma ) +{ + const uint8_t* curDmaAddr = getCurrentRxDmaAddress(dma); + + // not using int with abs value because we want full 32 bit memory addresses + if (curDmaAddr < dma->ptr) + { + // handle wrap + return (int)(dma->size - (dma->ptr - curDmaAddr)); + } + return (int)(curDmaAddr - dma->ptr); +} + +static inline int serTxFreeDma( dmaBuffer_tx_t *dma ) +{ + return dma->size - serTxUsedDma(dma); +} + +static inline int serRxFreeDma( dmaBuffer_rx_t *dma ) +{ + return dma->size - serRxUsedDma(dma); +} + +/********************************* EXTERNAL FUCTIONS ***************************************************************************************************/ +/** + * \brief Returns number of bytes used in Tx buffer. + */ +int serTxUsed( int serialNum ) +{ + // Get the DMA buffer pointer + dmaBuffer_tx_t *dma = getTxDma(serialNum); + if( !dma ) return 0; + + return serTxUsedDma(dma); +} + +/** + * \brief Returns number of bytes used in Rx buffer. + */ +int serRxUsed( int serialNum ) +{ + // Get the DMA buffer pointer + dmaBuffer_rx_t *dma = getRxDma(serialNum); + if( !dma ) return 0; + + return serRxUsedDma(dma); +} + +/** + * \brief Returns number of bytes available in Tx buffer. + */ +int serTxFree( int serialNum ) +{ +#ifdef USB_PORT_NUM + if(serialNum == USB_PORT_NUM) + { + return udi_cdc_get_free_tx_buffer(); + } +#endif + + // Get the DMA buffer pointer + dmaBuffer_tx_t *dma = getTxDma(serialNum); + if( !dma ) return 0; + + return serTxFreeDma(dma); +} + +/** + * \brief Returns number of bytes available in Rx buffer. + */ +int serRxFree( int serialNum ) +{ + // Get the DMA buffer pointer + dmaBuffer_rx_t *dma = getRxDma(serialNum); + if( !dma ) return 0; + + return serRxFreeDma(dma); +} + +/** + * \brief Clear the entire Tx buffer + */ +int serTxClear( int serialNum ) +{ + // Get the DMA buffer pointer + dmaBuffer_tx_t *dma = getTxDma(serialNum); + if( !dma ) return 0; + + // disable channel + xdmac_disable_interrupt(XDMAC, dma->dmaChNumber); + xdmac_channel_disable(XDMAC, dma->dmaChNumber); + + // save how much data we are discarding to return from function + int used = serTxUsedDma(dma); + + // Clear all + dma->ptr = dma->buf; + dma->lld_fptr = 0; + dma->lld_bptr = 0; + + //Check to see if we are in SPI mode + usartDMA_t *ser = (usartDMA_t*)&g_usartDMA[serialNum]; + if (ser->uinfo.isSpi) + { + xdmac_channel_config_t cfg = {0}; + cfg.mbr_sa = (uint32_t)noData_indicator; + cfg.mbr_da = (uint32_t)ser->uinfo.usartTxTHR; + cfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | + XDMAC_CC_MEMSET_NORMAL_MODE | + XDMAC_CC_DSYNC_MEM2PER | + XDMAC_CC_MBSIZE_SINGLE | + XDMAC_CC_DWIDTH_BYTE | + XDMAC_CC_SIF_AHB_IF1 | + XDMAC_CC_DIF_AHB_IF1 | + XDMAC_CC_SAM_INCREMENTED_AM | + XDMAC_CC_DAM_FIXED_AM | + XDMAC_CC_PERID(ser->uinfo.xdmacUsartTxPerId); + cfg.mbr_ubc = 0; + xdmac_configure_transfer(XDMAC, ser->dmaTx.dmaChNumber, &cfg); + + ser->dmaTx.lld_spi_noData[0].mbr_nda = (uint32_t)&(ser->dmaTx.lld_spi_noData[0]); + + xdmac_channel_set_descriptor_control(XDMAC, ser->dmaTx.dmaChNumber, XDMAC_CNDC_NDVIEW_NDV0 | XDMAC_CNDC_NDE_DSCR_FETCH_EN | XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED); + xdmac_channel_set_descriptor_addr(XDMAC, ser->dmaTx.dmaChNumber, (uint32_t)&(ser->dmaTx.lld_spi_noData[0]), 0); + dma->lld_fptr = 1; + + // Flush cached memory changes out to main memory + SCB_CLEAN_DCACHE_BY_ADDR_32BYTE_ALIGNED(dma->lld_spi_noData, sizeof(dma->lld_spi_noData)); + + // Re-enable DMA + xdmac_channel_enable_no_cache(XDMAC, dma->dmaChNumber); + } + + return used; +} + +int serRxClear( int serialNum, int size) +{ + // Get the DMA buffer pointer + dmaBuffer_rx_t *dma = getRxDma(serialNum); + if( !dma ) return 0; + + int used = serRxUsedDma(dma); + + // Flush FIFO, content of the FIFO is written to memory + xdmac_channel_software_flush_request(XDMAC, dma->dmaChNumber); + + // Disable transfer + xdmac_channel_disable(XDMAC, dma->dmaChNumber); + + // Reset + dma->ptr = dma->buf; + + // Configure Rx linked list descriptor (only uses one) + dma->lld.mbr_ta = (uint32_t)dma->buf; + dma->lld.mbr_nda = (uint32_t)&(dma->lld); // point to self + dma->lld.mbr_ubc = + XDMAC_UBC_NVIEW_NDV0 | + XDMAC_UBC_NDE_FETCH_EN | + XDMAC_UBC_NDEN_UPDATED | + dma->size; + + xdmac_channel_set_descriptor_control(XDMAC, dma->dmaChNumber, + XDMAC_CNDC_NDVIEW_NDV0 | + XDMAC_CNDC_NDE_DSCR_FETCH_EN | + XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED | + XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED ); + + xdmac_channel_set_descriptor_addr(XDMAC, dma->dmaChNumber, (uint32_t)&(dma->lld), 0); + +// DBGPIO_START(DBG_TX_DCACHE_CLEAN_PIN); + SCB_CLEAN_DCACHE_BY_ADDR_32BYTE_ALIGNED(dma, sizeof(dmaBuffer_rx_t)); +// DBGPIO_END(DBG_TX_DCACHE_CLEAN_PIN); + + xdmac_channel_enable_no_cache(XDMAC, dma->dmaChNumber); + + return used; +} + +uint8_t serTxBufferOverrun(void) +{ + if (s_txBufferOverrun) + { + s_txBufferOverrun = false; + return true; + } + + return false; +} + +// We assume worst case scenario, USART is writing data... +// Add new data to buffer that is not being written from. +int serWrite(int serialNum, const unsigned char *buf, int size) +{ + if (size <= 0 || serialNum < 0 || serialNum >= MAX_NUMBER_SERIAL_PORTS) + { + return 0; + } + +#ifdef USB_PORT_NUM + if(serialNum == USB_PORT_NUM) + { + if (usb_cdc_open) + { + dmaBuffer_tx_t *dma = (dmaBuffer_tx_t*)&g_usartDMA[USB_PORT_NUM].dmaTx; + + //NOTE: We are not preventing overflow at this time, it will just happen and data will be lost/corrupted + // (It shouldn't happen as USB moves data pretty fast.) + + //Prevent loading more data than buffer size + if ((uint32_t)size > dma->size) + { + // Buffer overrun + s_txBufferOverrun = true; + return 0; + } + + taskENTER_CRITICAL(); + + //Check for data in buffer, if nothing buffered, USB is ready, and data fits, don't double buffer + if(dma->ptr == dma->end && ((uint32_t)size <= udi_cdc_get_free_tx_buffer())) + { + udi_cdc_write_buf(buf, size); + } + else //We are sending more data than USB buffer will hold or there is already data in external buffer. + { + //Store data in the external buffer + int bytesToEnd = dma->buf + dma->size - dma->ptr; + if (size <= bytesToEnd) + { + // Don't need to wrap + memcpy((void*)dma->ptr, buf, size); + + // Increment buffer pointer + dma->ptr += size; + } + else // Need to wrap + { + // Bytes to write at buffer start + int bytesWrapped = size - bytesToEnd; + + //Write out data needed to fill the end of the buffer + if (bytesToEnd) + { + // Not already at buffer end. Fill buffer to end. + memcpy((void*)dma->ptr, buf, bytesToEnd); + } + + // Copy data into DMA buffer start & update pointer + memcpy((void*)dma->buf, buf + bytesToEnd, bytesWrapped); + + // Increment buffer pointer + dma->ptr = dma->buf + bytesWrapped; + } + + //Send what fits to USB immediately (also makes sure external buffer didn't empty while we were in here) + d_usartDMA_callback_cdc_tx_empty_notify(); + } + + taskEXIT_CRITICAL(); + + g_portMonitorHelper[serialNum].txByteCount += size; + return size; + } + return 0; + } +#endif // #ifdef USB_PORT_NUM + + // Get the DMA buffer pointer + dmaBuffer_tx_t *dma = getTxDma(serialNum); + if (!dma || (uint32_t)size > dma->size) return 0; + + // Bytes free in DMA buffer + int dmaFreeBytes = serTxFreeDma(dma); + + // Limit size + if (size > dmaFreeBytes || ((dma->lld_fptr + 1) & DMA_LLD_MASK) == dma->lld_bptr ) + { + // tx overrun + serTxClear(serialNum); + s_txBufferOverrun = true; +#if !defined(__INERTIAL_SENSE_EVB_2__) && !defined(TESTBED) + g_internal_diagnostic.txOverflowCount[serialNum]++; +#endif + } + + ////////////////////////////////////////////////////////////////////////// + // Copy into DMA buffer + + // Get ser struct to see if we are in SPI mode + usartDMA_t *ser = (usartDMA_t*)&g_usartDMA[serialNum]; + + taskENTER_CRITICAL(); + + // Bytes before end of DMA buffer + int bytesToEnd = dma->end - dma->ptr; + + // Add data to ring buffer + if (size <= bytesToEnd) + { + // Don't need to wrap + // Copy data into DMA buffer + MEMCPY_DCACHE_CLEAN(dma->ptr, buf, size); + + // Setup DMA + dma->lld[dma->lld_fptr].mbr_ta = (uint32_t)dma->ptr; + if (ser->uinfo.isSpi) + { + dma->lld[dma->lld_fptr].mbr_ubc = XDMAC_UBC_NVIEW_NDV0 | XDMAC_UBC_NDE_FETCH_EN | XDMAC_UBC_NSEN_UPDATED | XDMAC_UBC_UBLEN(size); + dma->lld[dma->lld_fptr].mbr_nda = (uint32_t)&(ser->dmaTx.lld_spi_noData[dma->lld_fptr]); //Data lld points to noData lld + dma->lld_spi_noData[dma->lld_fptr].mbr_nda = (uint32_t)&(ser->dmaTx.lld_spi_noData[dma->lld_fptr]); //noData lld wraps around on itself + } + else + { + dma->lld[dma->lld_fptr].mbr_ubc = XDMAC_UBC_UBLEN(size); + } + + // Increment buffer pointer + dma->ptr = dma->ptr + size; + + // Move to next lld + dma->lld_fptr = (dma->lld_fptr + 1) & DMA_LLD_MASK; + } + else // Need to wrap + { + // Bytes to write at buffer start + int bytesWrapped = size - bytesToEnd; + uint32_t bufptr = dma->lld_fptr; + int count = 1; + + //Write out data needed to fill the end of the buffer + if (bytesToEnd) + { + // Not already at buffer end. Fill buffer to end. + // Copy data into DMA buffer & update transfer size + MEMCPY_DCACHE_CLEAN(dma->ptr, buf, bytesToEnd); + + // Setup DMA for end + dma->lld[bufptr].mbr_ta = (uint32_t)dma->ptr; + if (ser->uinfo.isSpi) + { + dma->lld[bufptr].mbr_ubc = XDMAC_UBC_NVIEW_NDV0 | XDMAC_UBC_NDE_FETCH_EN | XDMAC_UBC_NSEN_UPDATED | XDMAC_UBC_UBLEN(bytesToEnd); + dma->lld[bufptr].mbr_nda = (uint32_t)&(ser->dmaTx.lld[(bufptr + 1) & DMA_LLD_MASK]); //Data lld points to next data lld + } + else + { + dma->lld[bufptr].mbr_ubc = XDMAC_UBC_UBLEN(bytesToEnd); + } + + // Move to next lld + bufptr = (bufptr + 1) & DMA_LLD_MASK; + count++; + } + + // Copy data into DMA buffer start & update pointer + MEMCPY_DCACHE_CLEAN(dma->buf, buf + bytesToEnd, bytesWrapped); + + // Setup DMA for beginning + dma->lld[bufptr].mbr_ta = (uint32_t)dma->buf; + if (ser->uinfo.isSpi) + { + dma->lld[bufptr].mbr_ubc = XDMAC_UBC_NVIEW_NDV0 | XDMAC_UBC_NDE_FETCH_EN | XDMAC_UBC_NSEN_UPDATED | XDMAC_UBC_UBLEN(bytesWrapped); + dma->lld[bufptr].mbr_nda = (uint32_t)&(ser->dmaTx.lld_spi_noData[bufptr]); //Data lld points to noData lld + dma->lld_spi_noData[bufptr].mbr_nda = (uint32_t)&(ser->dmaTx.lld_spi_noData[bufptr]); //noData lld wraps around on itself + } + else + { + dma->lld[bufptr].mbr_ubc = XDMAC_UBC_UBLEN(bytesWrapped); + } + + // Increment buffer pointer + dma->ptr = dma->buf + bytesWrapped; + + // Move to next lld + dma->lld_fptr = (dma->lld_fptr + count) & DMA_LLD_MASK; + } + + ////////////////////////////////////////////////////////////////////////// + // Transfer out of DMA buffer + + // Indicate Transmit + SER_INDICATE_TX(); + + if (ser->uinfo.isSpi) + { +#if CONF_BOARD_USART_SPI_DATAREADY_ENABLE == 1 + //Block interrupt handler from running while we add data so there isn't a race condition on the data ready pin + NVIC_DisableIRQ(XDMAC_IRQn); +#endif + //Connect up the new lld nodes + uint32_t newLld = (dma->lld_bptr + 1) & DMA_LLD_MASK; + ser->dmaTx.lld_spi_noData[dma->lld_bptr].mbr_nda = (uint32_t)&(ser->dmaTx.lld[newLld]); + + //Move back pointer manually in SPI mode + dma->lld_bptr = (dma->lld_fptr - 1) & DMA_LLD_MASK; + + //Write data out to main memory + SCB_CLEAN_DCACHE_BY_ADDR_32BYTE_ALIGNED(dma->lld, sizeof(dma->lld)); + SCB_CLEAN_DCACHE_BY_ADDR_32BYTE_ALIGNED(dma->lld_spi_noData, sizeof(dma->lld_spi_noData)); + +#if CONF_BOARD_USART_SPI_DATAREADY_ENABLE == 1 + // Enable DMA interrupt + xdmac_enable_interrupt(XDMAC, dma->dmaChNumber); + xdmac_channel_enable_interrupt(XDMAC, dma->dmaChNumber, XDMAC_CIE_BIE); + + //Set data ready pin for SPI mode + ioport_set_pin_level(SPI_DATAREADY_GPIO, IOPORT_PIN_LEVEL_HIGH); + + //Enable interrupt on completion of linked list node so we can watch for the end of the data + NVIC_EnableIRQ(XDMAC_IRQn); +#endif + } + else + { + //Block interrupt handler from running and causing a double configure + NVIC_DisableIRQ(XDMAC_IRQn); + + //Enable DMA if it isn't running + if((XDMAC->XDMAC_GS & (XDMAC_GS_ST0 << (dma->dmaChNumber))) == 0) + { + if(dma->lld_bptr != dma->lld_fptr) + { + //Setup TX DMA + xdmac_channel_set_source_addr(XDMAC, dma->dmaChNumber, dma->lld[dma->lld_bptr].mbr_ta); + xdmac_channel_set_microblock_control(XDMAC, dma->dmaChNumber, dma->lld[dma->lld_bptr].mbr_ubc); + + //Move pointer + dma->lld_bptr = (dma->lld_bptr + 1) & DMA_LLD_MASK; + + // Enable DMA interrupt + xdmac_enable_interrupt(XDMAC, dma->dmaChNumber); + xdmac_channel_enable_interrupt(XDMAC, dma->dmaChNumber, XDMAC_CIE_BIE); + + //Enable - cache should have already been cleaned + XDMAC->XDMAC_GE = (XDMAC_GE_EN0 << (dma->dmaChNumber)); + } + } + + NVIC_EnableIRQ(XDMAC_IRQn); + } + + taskEXIT_CRITICAL(); + + g_portMonitorHelper[serialNum].txByteCount += size; + return size; +} + +void XDMAC_usartDMA_Handler(void) +{ + static volatile int xdmacSPICount = 0; + + for(int i=0;idmaChId->XDMAC_CIS & XDMAC_CIS_BIS) && (dma->dmaChId->XDMAC_CIM & XDMAC_CIM_BIM)) + { +#if CONF_BOARD_USART_SPI_DATAREADY_ENABLE == 1 + //See if we are in SPI mode on this USART + if (g_usartDMA[i].uinfo.isSpi) + { + //See if we are at the end of the list + if((uint32_t)(dma->lld_spi_noData[dma->lld_bptr].mbr_nda) == dma->dmaChId->XDMAC_CNDA) + { + //See if we are transmitting the no data indicator + if(dma->dmaChId->XDMAC_CSA >= (uint32_t)noData_indicator && dma->dmaChId->XDMAC_CSA <= (uint32_t)(noData_indicator+sizeof(noData_indicator))) + { + //Delay number of "no data" transmissions (characters) to get the last bytes out of the port before lowering the data ready indicator. + if(2 <= xdmacSPICount) + { + ioport_set_pin_level(SPI_DATAREADY_GPIO, IOPORT_PIN_LEVEL_LOW); + xdmac_channel_disable_interrupt(XDMAC, dma->dmaChNumber, XDMAC_CIE_BIE); + } + else + { + xdmacSPICount++; + } + } + else + { + xdmacSPICount = 0; + } + } + else + { + xdmacSPICount = 0; + } + } + else //This "else" makes the following "if" an "else if" +#endif + //Check to see if DMA is finished (as indicated by channel becoming disabled + if ((XDMAC->XDMAC_GS & (XDMAC_GS_ST0 << (dma->dmaChNumber))) == 0) + { + if(dma->lld_bptr != dma->lld_fptr) + { + //Setup TX DMA + xdmac_channel_set_source_addr(XDMAC, dma->dmaChNumber, dma->lld[dma->lld_bptr].mbr_ta); + xdmac_channel_set_microblock_control(XDMAC, dma->dmaChNumber, dma->lld[dma->lld_bptr].mbr_ubc); + + //Move pointer + dma->lld_bptr = (dma->lld_bptr + 1) & DMA_LLD_MASK; + + //Enable - We don't need to clean cache as DMA data is already flushed to main memory + XDMAC->XDMAC_GE = (XDMAC_GE_EN0 << (dma->dmaChNumber)); + } + else + { + //Turn off interrupt when done + xdmac_channel_disable_interrupt(XDMAC, dma->dmaChNumber, XDMAC_CIE_BIE); + } + } + } + } +} + +int serRead(int serialNum, unsigned char *buf, int size) +{ + if (size <= 0 || serialNum < 0 || serialNum >= MAX_NUMBER_SERIAL_PORTS) + { + return 0; + } + +#ifdef USB_PORT_NUM + if(serialNum == USB_PORT_NUM) + { + if(usb_cdc_open) + { + return udi_cdc_read_no_polling(buf, size); + } + else + { + return 0; + } + } +#endif + + // Get the DMA buffer pointer + dmaBuffer_rx_t *dma = getRxDma(serialNum); + if (!dma) return 0; + + // Flush FIFO, content of the FIFO is written to memory + xdmac_channel_software_flush_request(XDMAC, dma->dmaChNumber); + + // Bytes in DMA buffer + uint32_t dmaUsed = serRxUsedDma(dma); + + if (dmaUsed < dma->lastUsedRx) + { + // rx overrun + serRxClear(serialNum, -1); + dma->lastUsedRx = 0; + s_txBufferOverrun = true; +#if !defined(__INERTIAL_SENSE_EVB_2__) && !defined(TESTBED) + g_internal_diagnostic.rxOverflowCount[serialNum]++; +#endif + size = 0; + } + else + { + // Limit to bytes available + size = Min((uint32_t)size, dmaUsed); + + if (size > 0) + { + // Bytes before end of DMA buffer + int bytesToEnd = dma->end - dma->ptr; + + if (size >= bytesToEnd) + { + // Handle wrapping + // Copy data into DMA buffer & update transfer size + DCACHE_CLEAN_INVALIDATE_MEMCPY(buf, dma->ptr, bytesToEnd); + + int bytesWrapped = size - bytesToEnd; + if (bytesWrapped) + { + // Copy data into DMA buffer + DCACHE_CLEAN_INVALIDATE_MEMCPY(&buf[bytesToEnd], dma->buf, bytesWrapped); + } + dma->ptr = dma->buf + bytesWrapped; + } + else + { + // Not wrapping + // Copy data into DMA buffer + DCACHE_CLEAN_INVALIDATE_MEMCPY(buf, dma->ptr, size); + dma->ptr += size; + } + + // Indicate Read + SER_INDICATE_RX(); + } + + dma->lastUsedRx = dmaUsed - size; + } + +#if !defined(__INERTIAL_SENSE_EVB_2__) && !defined(TESTBED) + if (size > 0) + { + uint32_t currentTime = time_msec(); + uint32_t gap = UINT32_TIME_DIFF(currentTime, dma->timestampRx); + if (gap > 500) + { + g_internal_diagnostic.gapCountSerialDriver[serialNum]++; + } + dma->timestampRx = currentTime; + } +#endif + + // Increment port monitor count + g_portMonitorHelper[serialNum].rxByteCount += size; + return size; +} + +int serFindCharacter( int serialNum, uint8_t ch) +{ +#ifdef USB_PORT_NUM + + //No support for USB port at this time + if(serialNum == USB_PORT_NUM) + return 0; + +#endif + + // Get the DMA buffer pointer + dmaBuffer_rx_t *dma = getRxDma(serialNum); + if (!dma) return 0; + + // Bytes in DMA buffer + uint32_t dmaUsed = serRxUsedDma(dma); + + // Return if no data is available + if(dmaUsed == 0) return 0; + + // Flush FIFO, content of the FIFO is written to memory + xdmac_channel_software_flush_request(XDMAC, dma->dmaChNumber); + + // Clean & invalidate memory so we can see what is there + SCB_CLEANINVALIDATE_DCACHE_BY_ADDR_32BYTE_ALIGNED(dma->buf, dma->size); + + //Look for character + uint32_t chCount = 0; + volatile uint8_t *ptr = dma->ptr; + while(++chCount <= dmaUsed) + { + if(*ptr == ch) + return (int)chCount; + + //move pointer + ptr++; + if(ptr >= dma->end) //Roll over to beginning if we reach the end + ptr = dma->buf; + } + + //Not found, return zero + return 0; +} + +static int serEnable(int serialNum) +{ + usartDMA_t *ser = (usartDMA_t*)&g_usartDMA[serialNum]; + + // Re-init UART + if (ser->uinfo.isUsartNotUart) + { // Initialize USART + if (ser->uinfo.isSpi) + { // Initialize the USART in SPI slave mode. + usart_spi_opt_t opt = { + .baudrate = 3000000, // ignored when configuring for slave mode + .char_length = US_MR_CHRL_8_BIT, + .spi_mode = SPI_MODE_3, + .channel_mode = US_MR_CHMODE_NORMAL + }; + usart_init_spi_slave((Usart*)ser->peripheral, &opt); + } + else + { // Initialize the USART in RS232 mode. + usart_init_rs232((Usart*)ser->peripheral, &(ser->usart_options), sysclk_get_peripheral_hz()); + } + + // Enable the receiver and transmitter. + usart_enable_tx((Usart*)ser->peripheral); + usart_enable_rx((Usart*)ser->peripheral); + } + else + { // Initialize UART + sam_uart_opt_t p_uart_opt = + { + .ul_mck = sysclk_get_peripheral_hz(), + .ul_baudrate = ser->usart_options.baudrate, // baudrate = sysclk / (16 * UART_BRGR). Example: 150000000 Hz / (16 * 10) = 937500 bps + .ul_mode = // Mode register: + UART_MR_PAR_NO | // No parity. + UART_MR_FILTER_DISABLED | // Don't filter Rx line. + UART_MR_BRSRCCK_PERIPH_CLK | // Use peripheral clock. Not PMC clock. + UART_MR_CHMODE_NORMAL // Normal channel mode. No loopback. + }; + + // Initialize the UART in normal mode. + uart_init((Uart*)ser->peripheral, &p_uart_opt); + + // Enable the receiver and transmitter. + uart_enable((Uart*)ser->peripheral); + } + + return 0; +} + +#if !defined(__INERTIAL_SENSE_EVB_2__) && !defined(TESTBED) + +static int spiEnable(int serialNum) +{ + usartDMA_t *ser = (usartDMA_t*)&g_usartDMA[serialNum]; + + if (!ser->uinfo.isSpi) + { + return -1; + } + + uint32_t chip_select = spi_get_pcs(0); + + /* Configure an SPI peripheral. */ + // spi_enable_clock(SPI_SLAVE_BASE); // We already do this in the parent function. + spi_disable((Spi*)ser->peripheral); + spi_reset((Spi*)ser->peripheral); + spi_set_slave_mode((Spi*)ser->peripheral); + spi_disable_mode_fault_detect((Spi*)ser->peripheral); + spi_set_peripheral_chip_select_value((Spi*)ser->peripheral, chip_select); // TODO: Make configurable. Currently hard coded to NPCS0 + spi_set_clock_polarity((Spi*)ser->peripheral, 0, SPI_SLAVE_CLK_POLARITY); // TODO: Make configurable. Currently hard coded to NPCS0 + spi_set_clock_phase((Spi*)ser->peripheral, 0, SPI_SLAVE_CLK_PHASE); // TODO: Make configurable. Currently hard coded to NPCS0 + spi_set_bits_per_transfer((Spi*)ser->peripheral, 0, SPI_CSR_BITS_8_BIT); // TODO: Make configurable. Currently hard coded to NPCS0 + spi_enable((Spi*)ser->peripheral); + + return 0; +} +#endif + +/** + * \brief Set USART baudrate. Return value is 0 on success or -1 on failure. + */ +int serSetBaudRate( int serialNum, int baudrate ) +{ + usartDMA_t *ser = (usartDMA_t*)&g_usartDMA[serialNum]; + if( !ser->peripheral ) return -1; + + // If we are not SPI, update baudrate + if (ser->uinfo.isSpi == 0) + { + // Update baudrate setting +#ifndef __INERTIAL_SENSE_EVB_2__ + if (0 == validateBaudRate(baudrate)) +#endif + ser->usart_options.baudrate = baudrate; + } + + return serEnable(serialNum); +} + +/** + * \brief Set USART baudrate. Return value is 0 on success or -1 on failure. Parameter 'baudRate' returns actual baud rate in hardware if non-standard (>921600). + */ +int serSyncBaudRate(int serialNum, uint32_t *baudRate) +{ + if (baudRate == NULL) + return -1; + + if (serSetBaudRate(serialNum, *baudRate) == 0) + { // Success + if (*baudRate > IS_BAUDRATE_STANDARD_MAX) + { // Report back actual non-standard baudrate + *baudRate = serBaudRate(serialNum); + } + + return 0; + } + + // Failure + return -1; +} + +/** + * \brief Read USART baudrate. Return value is the baudrate or -1 on failure. + */ +int serBaudRate( int serialNum ) +{ + usartDMA_t *ser = (usartDMA_t*)&g_usartDMA[serialNum]; + if( !ser ) return -1; + + // Baudrate setting + return uart_baud_rate((Uart*)ser->peripheral, sysclk_get_peripheral_hz()); +} + +/********************************* INITIALIZATION ROUTINES ***************************************************************************************************/ +//The optimizer seems to allow the use of the lld array before it is completely configured. No optimization prevents that from happening. +__attribute__((optimize("O0"))) +static void serDmaRxInit(usartDMA_t *ser) +{ + xdmac_channel_config_t cfg = {0}; + cfg.mbr_sa = (uint32_t)ser->uinfo.usartRxRHR; + cfg.mbr_da = (uint32_t)ser->dmaRx.buf; + cfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | + XDMAC_CC_MEMSET_NORMAL_MODE | + XDMAC_CC_DSYNC_PER2MEM | + XDMAC_CC_MBSIZE_SINGLE | + XDMAC_CC_DWIDTH_BYTE | + XDMAC_CC_SIF_AHB_IF1 | + XDMAC_CC_DIF_AHB_IF1 | + XDMAC_CC_SAM_FIXED_AM | + XDMAC_CC_DAM_INCREMENTED_AM | + XDMAC_CC_PERID(ser->uinfo.xdmacUsartRxPerId); + cfg.mbr_ubc = ser->dmaRx.size; + xdmac_configure_transfer(XDMAC, ser->dmaRx.dmaChNumber, &cfg); + + // Configure linked list descriptor (only uses one) + ser->dmaRx.lld.mbr_ta = (uint32_t)ser->dmaRx.buf; + ser->dmaRx.lld.mbr_nda = (uint32_t)&(ser->dmaRx.lld); // point to self + ser->dmaRx.lld.mbr_ubc = + XDMAC_UBC_NVIEW_NDV0 | + XDMAC_UBC_NDE_FETCH_EN | + XDMAC_UBC_NDEN_UPDATED | + ser->dmaRx.size; + + // Set initial descriptor control + xdmac_channel_set_descriptor_control(XDMAC, ser->dmaRx.dmaChNumber, //Updates CNDC register + XDMAC_CNDC_NDVIEW_NDV0 | + XDMAC_CNDC_NDE_DSCR_FETCH_EN | + XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED); + xdmac_channel_set_descriptor_addr(XDMAC, ser->dmaRx.dmaChNumber, (uint32_t)&(ser->dmaRx.lld), 0); //Updates CNDA register +} + +//The optimizer seems to allow the use of the lld array before it is completely configured. No optimization prevents that from happening. +__attribute__((optimize("O0"))) +static void serDmaTxInit(usartDMA_t *ser) +{ + xdmac_channel_config_t cfg = {0}; + cfg.mbr_sa = (uint32_t)noData_indicator; + cfg.mbr_da = (uint32_t)ser->uinfo.usartTxTHR; + cfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | + XDMAC_CC_MEMSET_NORMAL_MODE | + XDMAC_CC_DSYNC_MEM2PER | + XDMAC_CC_MBSIZE_SINGLE | + XDMAC_CC_DWIDTH_BYTE | + XDMAC_CC_SIF_AHB_IF1 | + XDMAC_CC_DIF_AHB_IF1 | + XDMAC_CC_SAM_INCREMENTED_AM | + XDMAC_CC_DAM_FIXED_AM | + XDMAC_CC_PERID(ser->uinfo.xdmacUsartTxPerId); + cfg.mbr_ubc = 0; + xdmac_configure_transfer(XDMAC, ser->dmaTx.dmaChNumber, &cfg); + + //Setup pointers to lld array + ser->dmaTx.lld_fptr = 0; + ser->dmaTx.lld_bptr = 0; + + + if (ser->uinfo.isSpi) + { + // The datasheet says that when a transfer happens and there is no data in the TX buffer, it will send a 0xFF. Its true right after reset, it will send 0xFF. + // But that appears to be not true after data has been sent. If the last bit sent was high, the line stays high and will send a 0xFF, if the last bit was low, it will stay low and send 0x00. + // But... can we guarantee that will hold true if they do a chip rev? Maybe not, so we will just guarantee it by keeping the TX DMA running + // This is done by having the lld loop back on itself with 0x00 data. + + for(int i=0; idmaTx.lld[i].mbr_nda = (uint32_t)&(ser->dmaTx.lld_spi_noData[i]); + + // Configure the DMA descriptors that handle transmission when there is no data to be sent. These will be configured to loop back on themselves. + ser->dmaTx.lld_spi_noData[i].mbr_nda = (uint32_t)&(ser->dmaTx.lld_spi_noData[i]); + + // The data to send comes from the noData_indicator array + ser->dmaTx.lld_spi_noData[i].mbr_ta = (uint32_t)noData_indicator; + + //Setup microblock control member - this will never change for the no data indicators. + ser->dmaTx.lld_spi_noData[i].mbr_ubc = XDMAC_UBC_NVIEW_NDV0 | XDMAC_UBC_NDE_FETCH_EN | XDMAC_UBC_NSEN_UPDATED | sizeof(noData_indicator); + } + + // Set initial descriptor control + xdmac_channel_set_descriptor_control(XDMAC, ser->dmaTx.dmaChNumber, XDMAC_CNDC_NDVIEW_NDV0 | XDMAC_CNDC_NDE_DSCR_FETCH_EN | XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED); + xdmac_channel_set_descriptor_addr(XDMAC, ser->dmaTx.dmaChNumber, (uint32_t)&(ser->dmaTx.lld_spi_noData[0]), 0); + ser->dmaTx.lld_fptr = 1; + +#if CONF_BOARD_USART_SPI_DATAREADY_ENABLE == 1 + //Setup interrupts for data ready pin for SPI mode + NVIC_ClearPendingIRQ(XDMAC_IRQn); + NVIC_SetPriority(XDMAC_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); //Must not be higher than RTOS allows + NVIC_EnableIRQ(XDMAC_IRQn); +#endif + } + else + { + //Setup interrupts for DMA for UART mode (gets multiple setups as this routine is called for multiple USARTs) + NVIC_ClearPendingIRQ(XDMAC_IRQn); + NVIC_SetPriority(XDMAC_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); //Must not be higher than RTOS allows + NVIC_EnableIRQ(XDMAC_IRQn); + } +} + + +#if (ENABLE_COMM_LOOPBACK_DRIVER > 0) +static void serLoopback(int portNum) +{ + if (CONF_LOOPBACK_PORT != portNum) + return; + +#define RX_BUF_SIZE 256 + static unsigned char rxBuf[RX_BUF_SIZE] = {0}; + int bytesRead = 0; + int timeout = 0; + +#if ENABLE_COMM_LOOPBACK_DRIVER==1 // Loop back test - simple + while (1) + { + // Read data +// bytesRead = serRead(portNum, rxBuf, 1, 0); + bytesRead = serRead(portNum, rxBuf, RX_BUF_SIZE, 0); + + // Write data + if (bytesRead) + { + if (g_usartDMA[portNum].uinfo.isSpi) + { + //we need to omit zero data for the test + int i, cnt = 0; + for(i=0;i=10 || ++timeout >= 100000) + { + if(bytesRead) + { + int bytesSend1 = bytesRead/2; // split transmission into two serWrite calls + int bytesSend2 = bytesRead - bytesSend1; + serWrite(portNum, rxBuf, bytesSend1, 0); + serWrite(portNum, &rxBuf[bytesSend1], bytesSend2, 0); + bytesRead = 0; + + // Toggle LED for Tx + LED_TOGGLE(LED_RED); + } + + timeout = 0; + } + + watchdog_maintenance_force(); // ensure watch dog does not kill us + } +#endif // ENABLE_COMM_LOOPBACK_DRIVER==2 + +#if ENABLE_COMM_LOOPBACK_DRIVER == 3 // Raw read/write test + //Turn off DMA + usartDMA_t *ser = (usartDMA_t*)&g_usartDMA[portNum]; + xdmac_channel_disable(XDMAC, ser->dmaTx.dmaChNumber); + xdmac_channel_disable(XDMAC, ser->dmaRx.dmaChNumber); + + // For SPI mode, preload data for transmit + if (ser->uinfo.isSpi) + { + ((Usart*)ser->peripheral)->US_THR = 0; + } + + while(1) + { + uint32_t status = usart_get_status((Usart*)ser->peripheral); + + if(status & US_CSR_RXRDY && status & US_CSR_TXRDY) + { + ((Usart*)ser->peripheral)->US_THR = ((Usart*)ser->peripheral)->US_RHR; + } + + watchdog_maintenance_force(); // ensure watch dog does not kill us + } +#endif // ENABLE_COMM_LOOPBACK_DRIVER==3 + +#if ENABLE_COMM_LOOPBACK_DRIVER==4 //Assembles a packet before sending back + LEDS_ALL_OFF(); + ((Usart*)g_usartDMA[portNum].peripheral)->US_THR = 0; + + while (1) + { + bool inpacket = false; + bytesRead = 0; + + while(1) + { + if (serRead(portNum, &(rxBuf[bytesRead]), 1, 0)) + { + if(inpacket) + { + ++bytesRead; + + if(0xFE == rxBuf[bytesRead - 1]) + break; + } + else + { + if( 0xFF == rxBuf[bytesRead]) + { + ++bytesRead; + inpacket = true; + } + } + + // Toggle LED for Rx + LED_TOGGLE(LED_GRN); + } + + watchdog_maintenance_force(); // ensure watch dog does not kill us + } + + if(bytesRead) + { + for(int j=2;j 0 + +static int setup_usart_info(usartDMA_t *ser, int serialNumber, uint32_t baudRate, sam_usart_opt_t *options) +{ + // Setup Baud Rate + if(baudRate == 0) + { + ser->usart_options.baudrate = DEFAULT_BAUDRATE; + } + else if(options != NULL) + { + if(options->baudrate == 0) + ser->usart_options.baudrate = DEFAULT_BAUDRATE; + else + ser->usart_options.baudrate = options->baudrate; + } + else + { + ser->usart_options.baudrate = baudRate; + } + + // Setup other port options + if(options == NULL) + { + //Use defaults + ser->usart_options.char_length = US_MR_CHRL_8_BIT; + ser->usart_options.parity_type = US_MR_PAR_NO; + ser->usart_options.stop_bits = US_MR_NBSTOP_1_BIT; + ser->usart_options.channel_mode = US_MR_CHMODE_NORMAL; + } + else + { + //Use custom settings + ser->usart_options.char_length = options->char_length; + ser->usart_options.parity_type = options->parity_type; + ser->usart_options.stop_bits = options->stop_bits; + ser->usart_options.channel_mode = options->channel_mode; + } + + return 0; +} + +static int serBufferInit(usartDMA_t *ser, int serialNumber) +{ + //Configure DMA & Buffer + switch(serialNumber) + { + default: + break; +#if MAX_NUMBER_SERIAL_PORTS >= 1 + case 0: + ser->peripheral = ARGN(0, PORT0_CONFIG); + ser->dmaTx.size = ARGN(2, PORT0_CONFIG); + ser->dmaRx.size = ARGN(4, PORT0_CONFIG); + ser->dmaTx.dmaChNumber = ARGN(1, PORT0_CONFIG); + ser->dmaRx.dmaChNumber = ARGN(3, PORT0_CONFIG); + ser->dmaTx.buf = g_serTxDmaBuf_port0; + ser->dmaRx.buf = g_serRxDmaBuf_port0; + break; +#endif +#if MAX_NUMBER_SERIAL_PORTS >= 2 + case 1: + ser->peripheral = ARGN(0, PORT1_CONFIG); + ser->dmaTx.size = ARGN(2, PORT1_CONFIG); + ser->dmaRx.size = ARGN(4, PORT1_CONFIG); + ser->dmaTx.dmaChNumber = ARGN(1, PORT1_CONFIG); + ser->dmaRx.dmaChNumber = ARGN(3, PORT1_CONFIG); + ser->dmaTx.buf = g_serTxDmaBuf_port1; + ser->dmaRx.buf = g_serRxDmaBuf_port1; + break; +#endif +#if MAX_NUMBER_SERIAL_PORTS >= 3 + case 2: + ser->peripheral = ARGN(0, PORT2_CONFIG); + ser->dmaTx.size = ARGN(2, PORT2_CONFIG); + ser->dmaRx.size = ARGN(4, PORT2_CONFIG); + ser->dmaTx.dmaChNumber = ARGN(1, PORT2_CONFIG); + ser->dmaRx.dmaChNumber = ARGN(3, PORT2_CONFIG); + ser->dmaTx.buf = g_serTxDmaBuf_port2; + ser->dmaRx.buf = g_serRxDmaBuf_port2; + break; +#endif +#if MAX_NUMBER_SERIAL_PORTS >= 4 + case 3: + ser->peripheral = ARGN(0, PORT3_CONFIG); + ser->dmaTx.size = ARGN(2, PORT3_CONFIG); + ser->dmaRx.size = ARGN(4, PORT3_CONFIG); + ser->dmaTx.dmaChNumber = ARGN(1, PORT3_CONFIG); + ser->dmaRx.dmaChNumber = ARGN(3, PORT3_CONFIG); + ser->dmaTx.buf = g_serTxDmaBuf_port3; + ser->dmaRx.buf = g_serRxDmaBuf_port3; + break; +#endif +#if MAX_NUMBER_SERIAL_PORTS >= 5 + case 4: + ser->peripheral = ARGN(0, PORT4_CONFIG); + ser->dmaTx.size = ARGN(2, PORT4_CONFIG); + ser->dmaRx.size = ARGN(4, PORT4_CONFIG); + ser->dmaTx.dmaChNumber = ARGN(1, PORT4_CONFIG); + ser->dmaRx.dmaChNumber = ARGN(3, PORT4_CONFIG); + ser->dmaTx.buf = g_serTxDmaBuf_port4; + ser->dmaRx.buf = g_serRxDmaBuf_port4; + break; +#endif +#if MAX_NUMBER_SERIAL_PORTS >= 6 + case 5: + ser->peripheral = ARGN(0, PORT5_CONFIG); + ser->dmaTx.size = ARGN(2, PORT5_CONFIG); + ser->dmaRx.size = ARGN(4, PORT5_CONFIG); + ser->dmaTx.dmaChNumber = ARGN(1, PORT5_CONFIG); + ser->dmaRx.dmaChNumber = ARGN(3, PORT5_CONFIG); + ser->dmaTx.buf = g_serTxDmaBuf_port5; + ser->dmaRx.buf = g_serRxDmaBuf_port5; + break; +#endif +#if MAX_NUMBER_SERIAL_PORTS >= 7 + case 6: + ser->peripheral = ARGN(0, PORT6_CONFIG); + ser->dmaTx.size = ARGN(2, PORT6_CONFIG); + ser->dmaRx.size = ARGN(4, PORT6_CONFIG); + ser->dmaTx.dmaChNumber = ARGN(1, PORT6_CONFIG); + ser->dmaRx.dmaChNumber = ARGN(3, PORT6_CONFIG); + ser->dmaTx.buf = g_serTxDmaBuf_port6; + ser->dmaRx.buf = g_serRxDmaBuf_port6; + break; +#endif +#if MAX_NUMBER_SERIAL_PORTS >= 8 + case 7: + ser->peripheral = ARGN(0, PORT7_CONFIG); + ser->dmaTx.size = ARGN(2, PORT7_CONFIG); + ser->dmaRx.size = ARGN(4, PORT7_CONFIG); + ser->dmaTx.dmaChNumber = ARGN(1, PORT7_CONFIG); + ser->dmaRx.dmaChNumber = ARGN(3, PORT7_CONFIG); + ser->dmaTx.buf = g_serTxDmaBuf_port7; + ser->dmaRx.buf = g_serRxDmaBuf_port7; + break; +#endif + } + + // Setup hardware specific items + if( ser->peripheral == USART0 ) + { + ser->uinfo.ul_id = ID_USART0; + ser->uinfo.usartTxTHR = (uint32_t)&(USART0->US_THR); + ser->uinfo.usartRxRHR = (uint32_t)&(USART0->US_RHR); + ser->uinfo.xdmacUsartTxPerId = XDMAC_PERID_USART0_TX; + ser->uinfo.xdmacUsartRxPerId = XDMAC_PERID_USART0_RX; + ser->uinfo.isUsartNotUart = true; + ser->uinfo.isSpi = false; + } + else if( ser->peripheral == USART1 ) + { + ser->uinfo.ul_id = ID_USART1; + ser->uinfo.usartTxTHR = (uint32_t)&(USART1->US_THR); + ser->uinfo.usartRxRHR = (uint32_t)&(USART1->US_RHR); + ser->uinfo.xdmacUsartTxPerId = XDMAC_PERID_USART1_TX; + ser->uinfo.xdmacUsartRxPerId = XDMAC_PERID_USART1_RX; + ser->uinfo.isUsartNotUart = true; + ser->uinfo.isSpi = false; + } + else if( ser->peripheral == USART2 ) + { + ser->uinfo.ul_id = ID_USART2; + ser->uinfo.usartTxTHR = (uint32_t)&(USART2->US_THR); + ser->uinfo.usartRxRHR = (uint32_t)&(USART2->US_RHR); + ser->uinfo.xdmacUsartTxPerId = XDMAC_PERID_USART2_TX; + ser->uinfo.xdmacUsartRxPerId = XDMAC_PERID_USART2_RX; + ser->uinfo.isUsartNotUart = true; +#ifndef __INERTIAL_SENSE_EVB_2__ // Only allow this on the uINS for now + ser->uinfo.isSpi = g_spi_comm_select; +#else + ser->uinfo.isSpi = false; +#endif + } + else if( ser->peripheral == UART0 ) + { + ser->uinfo.ul_id = ID_UART0; + ser->uinfo.usartTxTHR = (uint32_t)&(UART0->UART_THR); + ser->uinfo.usartRxRHR = (uint32_t)&(UART0->UART_RHR); + ser->uinfo.xdmacUsartTxPerId = XDMAC_PERID_UART0_TX; + ser->uinfo.xdmacUsartRxPerId = XDMAC_PERID_UART0_RX; + ser->uinfo.isUsartNotUart = false; + ser->uinfo.isSpi = false; + } + else if( ser->peripheral == UART1 ) + { + ser->uinfo.ul_id = ID_UART1; + ser->uinfo.usartTxTHR = (uint32_t)&(UART1->UART_THR); + ser->uinfo.usartRxRHR = (uint32_t)&(UART1->UART_RHR); + ser->uinfo.xdmacUsartTxPerId = XDMAC_PERID_UART1_TX; + ser->uinfo.xdmacUsartRxPerId = XDMAC_PERID_UART1_RX; + ser->uinfo.isUsartNotUart = false; + ser->uinfo.isSpi = false; + } + else if( ser->peripheral == UART2 ) + { + ser->uinfo.ul_id = ID_UART2; + ser->uinfo.usartTxTHR = (uint32_t)&(UART2->UART_THR); + ser->uinfo.usartRxRHR = (uint32_t)&(UART2->UART_RHR); + ser->uinfo.xdmacUsartTxPerId = XDMAC_PERID_UART2_TX; + ser->uinfo.xdmacUsartRxPerId = XDMAC_PERID_UART2_RX; + ser->uinfo.isUsartNotUart = false; + ser->uinfo.isSpi = false; + } + else if( ser->peripheral == UART3 ) + { + ser->uinfo.ul_id = ID_UART3; + ser->uinfo.usartTxTHR = (uint32_t)&(UART3->UART_THR); + ser->uinfo.usartRxRHR = (uint32_t)&(UART3->UART_RHR); + ser->uinfo.xdmacUsartTxPerId = XDMAC_PERID_UART3_TX; + ser->uinfo.xdmacUsartRxPerId = XDMAC_PERID_UART3_RX; + ser->uinfo.isUsartNotUart = false; + ser->uinfo.isSpi = false; + } + else if( ser->peripheral == UART4 ) + { + ser->uinfo.ul_id = ID_UART4; + ser->uinfo.usartTxTHR = (uint32_t)&(UART4->UART_THR); + ser->uinfo.usartRxRHR = (uint32_t)&(UART4->UART_RHR); + ser->uinfo.xdmacUsartTxPerId = XDMAC_PERID_UART4_TX; + ser->uinfo.xdmacUsartRxPerId = XDMAC_PERID_UART4_RX; + ser->uinfo.isUsartNotUart = false; + ser->uinfo.isSpi = false; + } +#if !defined(__INERTIAL_SENSE_EVB_2__) && !defined(TESTBED) + else if( ser->peripheral == SPI1 ) + { + ser->uinfo.ul_id = ID_SPI1; + ser->uinfo.usartTxTHR = (uint32_t)&(SPI1->SPI_TDR); + ser->uinfo.usartRxRHR = (uint32_t)&(SPI1->SPI_RDR); + ser->uinfo.xdmacUsartTxPerId = XDMAC_PERID_SPI1_TX; + ser->uinfo.xdmacUsartRxPerId = XDMAC_PERID_SPI1_RX; + ser->uinfo.isUsartNotUart = false; + ser->uinfo.isSpi = true; + } +#endif + else + { +#ifdef USB_PORT_NUM + if( serialNumber != USB_PORT_NUM ) +#endif + { + // "Invalid peripheral selected!!!" + return -1; + } + } + + if (ser->dmaTx.buf == NULL || ser->dmaRx.buf == NULL || !IS_32B_ALIGNED(ser->dmaTx.buf) || !IS_32B_ALIGNED(ser->dmaRx.buf)) + { +// #ifndef __INERTIAL_SENSE_EVB_2__ +// extern void soft_reset_backup_register(uint32_t value, uint32_t subValue); +// soft_reset_backup_register(CRASH_INFO_INVALID_CODE_OPERATION, 0); +// #endif + } + + // Set pointer to start of buffer + ser->dmaTx.ptr = ser->dmaTx.buf; + ser->dmaRx.ptr = ser->dmaRx.buf; + + // Set pointer to end of buffer + ser->dmaTx.end = ser->dmaTx.buf + ser->dmaTx.size; + ser->dmaRx.end = ser->dmaRx.buf + ser->dmaRx.size; + +#ifdef USB_PORT_NUM + if( serialNumber == USB_PORT_NUM ) + { + ser->dmaTx.end = ser->dmaTx.ptr; + } +#endif + + return 0; +} + +int serInit(int serialNum, uint32_t baudRate, sam_usart_opt_t *options) +{ +#ifdef USB_PORT_NUM + if(serialNum == USB_PORT_NUM) + { + // Setup pointers for additional USB buffer + if (serBufferInit((usartDMA_t *)&g_usartDMA[USB_PORT_NUM], serialNum) != 0) + return -1; + + udc_start(); + + #if (ENABLE_COMM_LOOPBACK_DRIVER==1 || ENABLE_COMM_LOOPBACK_DRIVER==2) + serLoopback(serialNum); + #endif // ENABLE_COMM_LOOPBACK_DRIVER == 1 || 2 + + return 0; + } +#endif + + // Validate port number + while( serialNum >= MAX_NUMBER_SERIAL_PORTS ) { /* Invalid port number */ } + + usartDMA_t *ser = (usartDMA_t *)&g_usartDMA[serialNum]; + + // Setup UART + if (setup_usart_info(ser, serialNum, baudRate, options) != 0) + while(1); + + // Setup buffers + if (serBufferInit(ser, serialNum) != 0) + return -1; + + // Enable the peripheral clock in the PMC + sysclk_enable_peripheral_clock(ser->uinfo.ul_id); + +#if !defined(__INERTIAL_SENSE_EVB_2__) && !defined(TESTBED) + if(ser->uinfo.isSpi && g_hdw_detect >= HDW_DETECT_VER_IMX_3_2_4) // uINS-3.2 and above use dedicated SPI peripheral + { + // Initialize the SPI + spiEnable(serialNum); + + // Turn on error interrupts + spi_enable_interrupt((Spi*) ser->peripheral, SPI_IER_MODF | SPI_IER_OVRES | SPI_IER_NSSR | SPI_IER_UNDES); + NVIC_EnableIRQ(ser->uinfo.ul_id); + } + else // uINS-3.1 and below use USART in SPI mode +#endif + { + // Re-init UART + serSetBaudRate(serialNum, ser->usart_options.baudrate); + + // Enable interrupt for errors + usart_enable_interrupt((Usart *)ser->peripheral, UART_IER_OVRE | UART_IER_FRAME | UART_IER_PARE); + NVIC_EnableIRQ(ser->uinfo.ul_id); + } + + /* Initialize and enable DMA controller */ + pmc_enable_periph_clk(ID_XDMAC); + + /* Get pointer to XDMA channel id */ + Assert(XDMAC); + Assert(ser->dmaTx.dmaChNumber < XDMACCHID_NUMBER); + Assert(ser->dmaRx.dmaChNumber < XDMACCHID_NUMBER); + ser->dmaTx.dmaChId = &(XDMAC->XDMAC_CHID[ser->dmaTx.dmaChNumber]); + ser->dmaRx.dmaChId = &(XDMAC->XDMAC_CHID[ser->dmaRx.dmaChNumber]); + + serDmaTxInit(ser); + serDmaRxInit(ser); + + // Enable Rx, only enable Tx when ready to transmit data. + // flush descriptors, etc. so that dma enable reads fresh values +#if CONF_BOARD_ENABLE_DCACHE == 1 + SCB_CleanInvalidateDCache(); +#endif + XDMAC->XDMAC_GE = (XDMAC_GE_EN0 << (ser->dmaRx.dmaChNumber)); + + // For SPI mode, TX DMA needs to run all the time + if (ser->uinfo.isSpi) + { + XDMAC->XDMAC_GE = (XDMAC_GE_EN0 << (ser->dmaTx.dmaChNumber)); + } + +#if (ENABLE_COMM_LOOPBACK_DRIVER > 0) + serLoopback(serialNum); +#endif + + return 0; +} + +int serInitSyncBaudrate(int serialNum, uint32_t *baudrate, sam_usart_opt_t *options) +{ + if (serInit(serialNum, *baudrate, options) == 0) + { + if (*baudrate > IS_BAUDRATE_STANDARD_MAX) + { // Report back actual non-standard baud rate + *baudrate = serBaudRate(serialNum); + } + // Success + return 0; + } + + // Failure + return -1; +} + +//Interrupts get enabled for errors. Clear error in interrupt. +void UART0_Handler(void) { UART0->UART_CR = UART_CR_RSTSTA; } +void UART1_Handler(void) { UART1->UART_CR = UART_CR_RSTSTA; } +void UART2_Handler(void) { UART2->UART_CR = UART_CR_RSTSTA; } +void UART3_Handler(void) { UART3->UART_CR = UART_CR_RSTSTA; } +void UART4_Handler(void) { UART4->UART_CR = UART_CR_RSTSTA; } +void USART0_Handler(void) { USART0->US_CR = US_CR_RSTSTA; } +void USART1_Handler(void) { USART1->US_CR = US_CR_RSTSTA; } +void USART2_Handler(void) { USART2->US_CR = US_CR_RSTSTA; } +#if !defined(TESTBED) +void SPI1_Handler(void) { volatile uint32_t sr = SPI1->SPI_SR; } // Errors cleared by reading SR +#endif diff --git a/hw-libs/drivers/SAMx70/d_serial.h b/hw-libs/drivers/SAMx70/d_serial.h new file mode 100644 index 000000000..2164e27e2 --- /dev/null +++ b/hw-libs/drivers/SAMx70/d_serial.h @@ -0,0 +1,131 @@ +/* +MIT LICENSE + +Copyright 2014-2019 Inertial Sense, Inc. - http://inertialsense.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions : + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +#ifndef _D_SERIAL_H_ +#define _D_SERIAL_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "conf_comm.h" + +// This is a mirror of port_monitor_helper_t in d_usart.h in the IMX-5 project +typedef struct +{ + uint32_t timeMsLast; + uint32_t txByteCount; + uint32_t rxByteCount; + uint32_t txBytesPerS; + uint32_t rxBytesPerS; + uint32_t status; +} port_monitor_helper_t; + +extern port_monitor_helper_t g_portMonitorHelper[MAX_NUMBER_SERIAL_PORTS]; + + +//_____ P R O T O T Y P E S ________________________________________________ + +bool d_usartDMA_callback_cdc_enable(void); +void d_usartDMA_callback_cdc_disable(void); +void d_usartDMA_callback_cdc_tx_empty_notify(void); + +void XDMAC_usartDMA_Handler(void); + +/** + * \brief Write data on USART. Returns number of bytes written. + */ +int serWrite( int serialNum, const unsigned char *buf, int size ); + +/** + * \brief Read data on USART. Returns number of bytes read. With use of the PDCA ring buffer, + * buffer overrun may occur if bytes are received is greater than bytes read plus buffer size. + */ +// Buffer overrun can be detected when serRxUsed decreases outside of a serRead(), because +// the Rx PDCA (DMA) wrote past the read pointer. +int serRead( int serialNum, unsigned char *buf, int size ); + +/** + * \brief Removes removes data from USART Rx buffer. Returns number of bytes removed. Length + * of -1 removes all data from USART buffer + */ +int serRxClear( int serialNum, int len ); + +/** + * \brief Returns number of bytes used in Rx buffer. + */ +int serRxUsed( int serialNum ); + +/** + * \brief Clear the entire Tx buffer, returns how much was cleared + */ +int serTxClear( int serialNum ); + +/** + * \brief Returns number of bytes used in Tx buffer. + */ +int serTxUsed( int serialNum ); + +/** + * \brief Returns number of bytes available in Rx buffer. + */ +int serRxFree( int serialNum ); + +/** + * \brief Returns number of bytes available in Tx buffer. + */ +int serTxFree( int serialNum ); + +/* + * Tx buffer was limited on one of the serial ports. Data was lost due to too much data being + * passed into serWrite(). + */ +uint8_t serTxBufferOverrun(void); + +/** + * \brief Returns number of characters in buffer before specified character. + */ +int serFindCharacter( int serialNum, uint8_t ch); + +/** + * \brief Change USART baudrate. 0 on success, -1 on failure. + */ +int serSetBaudRate( int serialNum, int baudrate ); + +/** + * \brief Change USART baudrate. 0 on success, -1 on failure. Parameter 'baudRate' returns actual baud rate in hardware if non-standard (>921600). + */ +int serSyncBaudRate(int serialNum, uint32_t *baudRate); + +/** + * \brief Read USART baudrate. Return value is the baudrate or -1 on failure. + */ +int serBaudRate( int serialNum ); + +/** + * \brief Initialize serial port with specific USART/UART and DMA settings. If not NULL, the overrun status will have bits HDW_STATUS_ERR_COM_TX_LIMITED and HDW_STATUS_ERR_COM_RX_OVERRUN set during buffer limitation. + */ +int serInit( int serialNum, uint32_t baudrate, sam_usart_opt_t *options); + +/** + * \brief Initialize serial port with specific USART/UART and DMA settings. If not NULL, the overrun status will have bits HDW_STATUS_ERR_COM_TX_LIMITED and HDW_STATUS_ERR_COM_RX_OVERRUN set during buffer limitation. + * \param baudrate Returns the actual baud rate in hardware if non-standard (>921600). + */ +int serInitSyncBaudrate(int serialNum, uint32_t *baudrate, sam_usart_opt_t *options); + +#ifdef __cplusplus +} +#endif + +#endif // _D_SERIAL_H_ + diff --git a/hw-libs/drivers/SAMx70/d_time.c b/hw-libs/drivers/SAMx70/d_time.c new file mode 100644 index 000000000..fea26c405 --- /dev/null +++ b/hw-libs/drivers/SAMx70/d_time.c @@ -0,0 +1,175 @@ +/* +MIT LICENSE + +Copyright 2014-2019 Inertial Sense, Inc. - http://inertialsense.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions : + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +#include "rtt.h" +#include "d_time.h" +#include "conf_interrupts.h" + +#if USE_TIMER_DRIVER +#include "d_timer.h" +#endif + +#if USE_FREERTOS +#include "rtos.h" +#endif + +static union { + struct { + uint32_t tim; + uint32_t rollcnt; + }; + uint64_t u64; +} g_ticks = {0}; + +void RTT_Handler(void) +{ + // alarm + if (RTT->RTT_SR & RTT_SR_ALMS) + { +#if USE_FREERTOS + rtosResetTaskCounters(); +#endif + g_ticks.rollcnt++; + } +} + +void time_init(void) +{ + // Only allow init once every reset + static bool inited = false; + if (inited) return; + inited = true; + +#if USE_TIMER_DRIVER + timer_time_init(); +#endif + + // Increment as frequently as possible + rtt_sel_source(RTT, false); + + rtt_init(RTT, TIM_PRESC); + + // Interrupt on 32bit rollover + rtt_write_alarm_time(RTT, 0); + rtt_enable_interrupt(RTT, RTT_MR_ALMIEN); + + NVIC_DisableIRQ(RTT_IRQn); + NVIC_ClearPendingIRQ(RTT_IRQn); + NVIC_SetPriority(RTT_IRQn, INT_PRIORITY_RTT); + NVIC_EnableIRQ(RTT_IRQn); +} + +inline volatile uint64_t time_ticks_u64(void) +{ + // Time must be read until two consecutive reads match so we don't get a partially updated value + do { + g_ticks.tim = RTT->RTT_VR; + } while (g_ticks.tim != RTT->RTT_VR); + + return g_ticks.u64; // Return uint64_t value; g_ticks.rollcnt is updated in interrupt +} + +inline volatile uint32_t time_ticks_u32(void) +{ + // Time must be read until two consecutive reads match so we don't get a partially updated value + do { + g_ticks.tim = RTT->RTT_VR; + } while (g_ticks.tim != RTT->RTT_VR); + + return g_ticks.tim; +} + +inline uint32_t time_ticks_to_usec(uint32_t ticks) +{ + return ((ticks / TIME_TICKS_PER_MS) * 1000U); // Tick rate is slower on this processor than 1us +} + +inline uint32_t time_usec_to_ticks(uint32_t usec) +{ + return ((usec * TIME_TICKS_PER_MS) / 1000U); // Tick rate is slower on this processor than 1us +} + +inline float time_ticksf_to_usecf(float ticks) +{ + return (ticks * TIME_US_PER_TICK_F); +} + +inline float time_usecf_to_ticksf(float usec) +{ + return (usec / TIME_US_PER_TICK_F); +} + +void time_delay_msec(uint32_t ms) +{ + if (ms != 0) + { + uint32_t start = time_ticks_u32(); // Rollover is automatically handled even without 64 bit rollover value + uint32_t ticktarget = ms * TIME_TICKS_PER_MS; + while (time_ticks_u32() - start < ticktarget); + } +} + +void time_delay_usec(uint32_t us) +{ + if (us != 0) + { + uint32_t start = time_ticks_u32(); // Rollover is automatically handled even without 64 bit rollover value + uint32_t ticktarget = us * TIME_TICKS_PER_MS / 1000U; // Tick rate is slower on this processor than 1us + while (time_ticks_u32() - start < ticktarget); + } +} + +inline uint32_t time_msec(void) +{ + return (uint32_t)((uint64_t)(time_ticks_u64() * TIME_MS_PER_TICK_LF) & 0x00000000FFFFFFFF); +} + +inline uint32_t time_usec(void) +{ + return (uint32_t)((uint64_t)(time_ticks_u64() * TIME_US_PER_TICK_LF) & 0x00000000FFFFFFFF); +} + +inline float time_secf(void) +{ + uint64_t ticks = time_ticks_u64(); + return TIME_SECS_PER_TICK_F * (float)ticks; +} + +inline float time_msecf(void) +{ + uint64_t ticks = time_ticks_u64(); + return TIME_MS_PER_TICK_F * (float)ticks; +} + +inline float time_usecf(void) +{ + uint64_t ticks = time_ticks_u64(); + return TIME_US_PER_TICK_F * (float)ticks; +} + +double time_seclf(void) +{ + uint64_t ticks = time_ticks_u64(); + return TIME_SECS_PER_TICK_LF * (double)ticks; +} + +inline double time_mseclf(void) +{ + uint64_t ticks = time_ticks_u64(); + return TIME_MS_PER_TICK_LF * (double)ticks; +} + +inline double time_useclf(void) +{ + uint64_t ticks = time_ticks_u64(); + return TIME_US_PER_TICK_LF * (double)ticks; +} diff --git a/hw-libs/drivers/SAMx70/d_time.h b/hw-libs/drivers/SAMx70/d_time.h new file mode 100644 index 000000000..8d3eb40ab --- /dev/null +++ b/hw-libs/drivers/SAMx70/d_time.h @@ -0,0 +1,169 @@ +/* +MIT LICENSE + +Copyright 2014-2019 Inertial Sense, Inc. - http://inertialsense.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions : + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +#ifndef D_TIME_H +#define D_TIME_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ISBoards.h" + +#include + +#if !defined(TIM_CLK_FREQ) || !defined(TIM_PRESC) +#error TIM_CLK_FREQ and TIM_PRESC must be set in ISBoards.h or its dependencies +#endif + +#define TIME_TICKS_PER_SEC (TIM_CLK_FREQ/TIM_PRESC) +#define TIME_TICKS_PER_MS (TIME_TICKS_PER_SEC/1000U) +#define TIME_TICKS_PER_US (TIME_TICKS_PER_SEC/1000000U) + +#define TIME_SECS_PER_TICK_F ((float)TIM_PRESC/(float)TIM_CLK_FREQ) +#define TIME_MS_PER_TICK_F (TIME_SECS_PER_TICK_F*1000.0f) +#define TIME_US_PER_TICK_F (TIME_SECS_PER_TICK_F*1000000.0f) + +#if !defined(BOOTLOADER) || !defined(IMX_5) // Don't use doubles in IMX-5 bootloader +#define TIME_SECS_PER_TICK_LF ((double)TIM_PRESC/(double)TIM_CLK_FREQ) +#define TIME_MS_PER_TICK_LF (TIME_SECS_PER_TICK_LF*(double)1000.0) +#define TIME_US_PER_TICK_LF (TIME_SECS_PER_TICK_LF*(double)1000000.0) +#endif + +/** + * @brief Initialize the timebase peripheral + * + */ +void time_init(void); + +/** + * @brief Get the number of ticks since timebase was started as uint64_t + * + * @return uint64_t number of ticks + */ +volatile uint64_t time_ticks_u64(void); + +/** + * @brief Get the number of ticks since timebase was started as uint32_t + * @see time_ticks_u64() if you need a timer that will run for a long time + * + * @return uint32_t number of ticks + */ +volatile uint32_t time_ticks_u32(void); + +/** + * @brief Convert ticks into microseconds + * + * @param ticks number of ticks to convert + * @return uint32_t usec count output, if > 2^32 will wrap to 0 + */ +uint32_t time_ticks_to_usec(uint32_t ticks); + +/** + * @brief Convert usec into ticks + * + * @param usec number of microseconds to convert + * @return uint32_t tick count output, if > 2^32 will wrap to 0 + */ +uint32_t time_usec_to_ticks(uint32_t usec); + +/** + * @brief Convert ticks into microseconds (float-to-float implementation) + * + * @param ticks number of ticks to convert + * @return float usec count output + */ +float time_ticksf_to_usecf(float ticks); + +/** + * @brief Convert ticks into microseconds (float-to-float implementation) + * + * @param ticks number of microseconds to convert + * @return float tick count output + */ +float time_usecf_to_ticksf(float usec); + +/** + * @brief Delay for a number of milliseconds + * + * @param ms number of milliseconds to delay for + */ +void time_delay_msec(uint32_t ms); + +/** + * @brief Delay for a number of microseconds + * + * @param us number of microseconds to delay for + */ +void time_delay_usec(uint32_t us); + +/** + * @brief Get current number of seconds since init as a float + * + * @return float number of seconds + */ +float time_secf(void); + +/** + * @brief Get current number of seconds since init as a double + * + * @return double number of seconds + */ +double time_seclf(void); + +/** + * @brief Get current number of milliseconds since init as a uint32_t + * + * @return uint32_t number of milliseconds (truncated to fit 32-bit datatype) + */ +uint32_t time_msec(void); + +/** + * @brief Get current number of milliseconds since init as a float + * + * @return float number of milliseconds + */ +float time_msecf(void); + +/** + * @brief Get current number of milliseconds since init as a double (64 bit float) + * + * @return double number of milliseconds + */ +double time_mseclf(void); + +/** + * @brief Get current number of microseconds since init as a uint32_t + * + * @return uint32_t number of microseconds (truncated to fit 32-bit datatype) + */ +uint32_t time_usec(void); + +/** + * @brief Get current number of microseconds since init as a float + * + * @return float number of microseconds + */ +float time_usecf(void); + +/** + * @brief Get current number of microseconds since init as a double (64 bit float) + * + * @return double number of microseconds + */ +double time_useclf(void); + +#ifdef __cplusplus +} +#endif // __cplusplus + +#endif // D_TIME_H diff --git a/hw-libs/freertos/croutine.c b/hw-libs/freertos/croutine.c new file mode 100644 index 000000000..d9bce9b03 --- /dev/null +++ b/hw-libs/freertos/croutine.c @@ -0,0 +1,363 @@ +/* + * FreeRTOS Kernel V10.4.6 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include "FreeRTOS.h" +#include "task.h" +#include "croutine.h" + +/* Remove the whole file is co-routines are not being used. */ +#if ( configUSE_CO_ROUTINES != 0 ) + +/* + * Some kernel aware debuggers require data to be viewed to be global, rather + * than file scope. + */ + #ifdef portREMOVE_STATIC_QUALIFIER + #define static + #endif + + +/* Lists for ready and blocked co-routines. --------------------*/ + static List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /*< Prioritised ready co-routines. */ + static List_t xDelayedCoRoutineList1; /*< Delayed co-routines. */ + static List_t xDelayedCoRoutineList2; /*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */ + static List_t * pxDelayedCoRoutineList = NULL; /*< Points to the delayed co-routine list currently being used. */ + static List_t * pxOverflowDelayedCoRoutineList = NULL; /*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */ + static List_t xPendingReadyCoRoutineList; /*< Holds co-routines that have been readied by an external event. They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */ + +/* Other file private variables. --------------------------------*/ + CRCB_t * pxCurrentCoRoutine = NULL; + static UBaseType_t uxTopCoRoutineReadyPriority = 0; + static TickType_t xCoRoutineTickCount = 0, xLastTickCount = 0, xPassedTicks = 0; + +/* The initial state of the co-routine when it is created. */ + #define corINITIAL_STATE ( 0 ) + +/* + * Place the co-routine represented by pxCRCB into the appropriate ready queue + * for the priority. It is inserted at the end of the list. + * + * This macro accesses the co-routine ready lists and therefore must not be + * used from within an ISR. + */ + #define prvAddCoRoutineToReadyQueue( pxCRCB ) \ + { \ + if( pxCRCB->uxPriority > uxTopCoRoutineReadyPriority ) \ + { \ + uxTopCoRoutineReadyPriority = pxCRCB->uxPriority; \ + } \ + vListInsertEnd( ( List_t * ) &( pxReadyCoRoutineLists[ pxCRCB->uxPriority ] ), &( pxCRCB->xGenericListItem ) ); \ + } + +/* + * Utility to ready all the lists used by the scheduler. This is called + * automatically upon the creation of the first co-routine. + */ + static void prvInitialiseCoRoutineLists( void ); + +/* + * Co-routines that are readied by an interrupt cannot be placed directly into + * the ready lists (there is no mutual exclusion). Instead they are placed in + * in the pending ready list in order that they can later be moved to the ready + * list by the co-routine scheduler. + */ + static void prvCheckPendingReadyList( void ); + +/* + * Macro that looks at the list of co-routines that are currently delayed to + * see if any require waking. + * + * Co-routines are stored in the queue in the order of their wake time - + * meaning once one co-routine has been found whose timer has not expired + * we need not look any further down the list. + */ + static void prvCheckDelayedList( void ); + +/*-----------------------------------------------------------*/ + + BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, + UBaseType_t uxPriority, + UBaseType_t uxIndex ) + { + BaseType_t xReturn; + CRCB_t * pxCoRoutine; + + /* Allocate the memory that will store the co-routine control block. */ + pxCoRoutine = ( CRCB_t * ) pvPortMalloc( sizeof( CRCB_t ) ); + + if( pxCoRoutine ) + { + /* If pxCurrentCoRoutine is NULL then this is the first co-routine to + * be created and the co-routine data structures need initialising. */ + if( pxCurrentCoRoutine == NULL ) + { + pxCurrentCoRoutine = pxCoRoutine; + prvInitialiseCoRoutineLists(); + } + + /* Check the priority is within limits. */ + if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES ) + { + uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1; + } + + /* Fill out the co-routine control block from the function parameters. */ + pxCoRoutine->uxState = corINITIAL_STATE; + pxCoRoutine->uxPriority = uxPriority; + pxCoRoutine->uxIndex = uxIndex; + pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode; + + /* Initialise all the other co-routine control block parameters. */ + vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) ); + vListInitialiseItem( &( pxCoRoutine->xEventListItem ) ); + + /* Set the co-routine control block as a link back from the ListItem_t. + * This is so we can get back to the containing CRCB from a generic item + * in a list. */ + listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine ); + listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine ); + + /* Event lists are always in priority order. */ + listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), ( ( TickType_t ) configMAX_CO_ROUTINE_PRIORITIES - ( TickType_t ) uxPriority ) ); + + /* Now the co-routine has been initialised it can be added to the ready + * list at the correct priority. */ + prvAddCoRoutineToReadyQueue( pxCoRoutine ); + + xReturn = pdPASS; + } + else + { + xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, + List_t * pxEventList ) + { + TickType_t xTimeToWake; + + /* Calculate the time to wake - this may overflow but this is + * not a problem. */ + xTimeToWake = xCoRoutineTickCount + xTicksToDelay; + + /* We must remove ourselves from the ready list before adding + * ourselves to the blocked list as the same list item is used for + * both lists. */ + ( void ) uxListRemove( ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) ); + + /* The list item will be inserted in wake time order. */ + listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake ); + + if( xTimeToWake < xCoRoutineTickCount ) + { + /* Wake time has overflowed. Place this item in the + * overflow list. */ + vListInsert( ( List_t * ) pxOverflowDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) ); + } + else + { + /* The wake time has not overflowed, so we can use the + * current block list. */ + vListInsert( ( List_t * ) pxDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) ); + } + + if( pxEventList ) + { + /* Also add the co-routine to an event list. If this is done then the + * function must be called with interrupts disabled. */ + vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) ); + } + } +/*-----------------------------------------------------------*/ + + static void prvCheckPendingReadyList( void ) + { + /* Are there any co-routines waiting to get moved to the ready list? These + * are co-routines that have been readied by an ISR. The ISR cannot access + * the ready lists itself. */ + while( listLIST_IS_EMPTY( &xPendingReadyCoRoutineList ) == pdFALSE ) + { + CRCB_t * pxUnblockedCRCB; + + /* The pending ready list can be accessed by an ISR. */ + portDISABLE_INTERRUPTS(); + { + pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyCoRoutineList ) ); + ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) ); + } + portENABLE_INTERRUPTS(); + + ( void ) uxListRemove( &( pxUnblockedCRCB->xGenericListItem ) ); + prvAddCoRoutineToReadyQueue( pxUnblockedCRCB ); + } + } +/*-----------------------------------------------------------*/ + + static void prvCheckDelayedList( void ) + { + CRCB_t * pxCRCB; + + xPassedTicks = xTaskGetTickCount() - xLastTickCount; + + while( xPassedTicks ) + { + xCoRoutineTickCount++; + xPassedTicks--; + + /* If the tick count has overflowed we need to swap the ready lists. */ + if( xCoRoutineTickCount == 0 ) + { + List_t * pxTemp; + + /* Tick count has overflowed so we need to swap the delay lists. If there are + * any items in pxDelayedCoRoutineList here then there is an error! */ + pxTemp = pxDelayedCoRoutineList; + pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList; + pxOverflowDelayedCoRoutineList = pxTemp; + } + + /* See if this tick has made a timeout expire. */ + while( listLIST_IS_EMPTY( pxDelayedCoRoutineList ) == pdFALSE ) + { + pxCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList ); + + if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) ) + { + /* Timeout not yet expired. */ + break; + } + + portDISABLE_INTERRUPTS(); + { + /* The event could have occurred just before this critical + * section. If this is the case then the generic list item will + * have been moved to the pending ready list and the following + * line is still valid. Also the pvContainer parameter will have + * been set to NULL so the following lines are also valid. */ + ( void ) uxListRemove( &( pxCRCB->xGenericListItem ) ); + + /* Is the co-routine waiting on an event also? */ + if( pxCRCB->xEventListItem.pxContainer ) + { + ( void ) uxListRemove( &( pxCRCB->xEventListItem ) ); + } + } + portENABLE_INTERRUPTS(); + + prvAddCoRoutineToReadyQueue( pxCRCB ); + } + } + + xLastTickCount = xCoRoutineTickCount; + } +/*-----------------------------------------------------------*/ + + void vCoRoutineSchedule( void ) + { + /* Only run a co-routine after prvInitialiseCoRoutineLists() has been + * called. prvInitialiseCoRoutineLists() is called automatically when a + * co-routine is created. */ + if( pxDelayedCoRoutineList != NULL ) + { + /* See if any co-routines readied by events need moving to the ready lists. */ + prvCheckPendingReadyList(); + + /* See if any delayed co-routines have timed out. */ + prvCheckDelayedList(); + + /* Find the highest priority queue that contains ready co-routines. */ + while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) ) + { + if( uxTopCoRoutineReadyPriority == 0 ) + { + /* No more co-routines to check. */ + return; + } + + --uxTopCoRoutineReadyPriority; + } + + /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines + * of the same priority get an equal share of the processor time. */ + listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ); + + /* Call the co-routine. */ + ( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex ); + } + } +/*-----------------------------------------------------------*/ + + static void prvInitialiseCoRoutineLists( void ) + { + UBaseType_t uxPriority; + + for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ ) + { + vListInitialise( ( List_t * ) &( pxReadyCoRoutineLists[ uxPriority ] ) ); + } + + vListInitialise( ( List_t * ) &xDelayedCoRoutineList1 ); + vListInitialise( ( List_t * ) &xDelayedCoRoutineList2 ); + vListInitialise( ( List_t * ) &xPendingReadyCoRoutineList ); + + /* Start with pxDelayedCoRoutineList using list1 and the + * pxOverflowDelayedCoRoutineList using list2. */ + pxDelayedCoRoutineList = &xDelayedCoRoutineList1; + pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2; + } +/*-----------------------------------------------------------*/ + + BaseType_t xCoRoutineRemoveFromEventList( const List_t * pxEventList ) + { + CRCB_t * pxUnblockedCRCB; + BaseType_t xReturn; + + /* This function is called from within an interrupt. It can only access + * event lists and the pending ready list. This function assumes that a + * check has already been made to ensure pxEventList is not empty. */ + pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); + ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) ); + vListInsertEnd( ( List_t * ) &( xPendingReadyCoRoutineList ), &( pxUnblockedCRCB->xEventListItem ) ); + + if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; + } + +#endif /* configUSE_CO_ROUTINES == 0 */ diff --git a/hw-libs/freertos/event_groups.c b/hw-libs/freertos/event_groups.c new file mode 100644 index 000000000..93d9d0d76 --- /dev/null +++ b/hw-libs/freertos/event_groups.c @@ -0,0 +1,777 @@ +/* + * FreeRTOS Kernel V10.4.6 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "event_groups.h" + +/* Lint e961, e750 and e9021 are suppressed as a MISRA exception justified + * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined + * for the header files above, but not in this file, in order to generate the + * correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021 See comment above. */ + +/* The following bit fields convey control information in a task's event list + * item value. It is important they don't clash with the + * taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */ +#if configUSE_16_BIT_TICKS == 1 + #define eventCLEAR_EVENTS_ON_EXIT_BIT 0x0100U + #define eventUNBLOCKED_DUE_TO_BIT_SET 0x0200U + #define eventWAIT_FOR_ALL_BITS 0x0400U + #define eventEVENT_BITS_CONTROL_BYTES 0xff00U +#else + #define eventCLEAR_EVENTS_ON_EXIT_BIT 0x01000000UL + #define eventUNBLOCKED_DUE_TO_BIT_SET 0x02000000UL + #define eventWAIT_FOR_ALL_BITS 0x04000000UL + #define eventEVENT_BITS_CONTROL_BYTES 0xff000000UL +#endif + +typedef struct EventGroupDef_t +{ + EventBits_t uxEventBits; + List_t xTasksWaitingForBits; /*< List of tasks waiting for a bit to be set. */ + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxEventGroupNumber; + #endif + + #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the event group is statically allocated to ensure no attempt is made to free the memory. */ + #endif +} EventGroup_t; + +/*-----------------------------------------------------------*/ + +/* + * Test the bits set in uxCurrentEventBits to see if the wait condition is met. + * The wait condition is defined by xWaitForAllBits. If xWaitForAllBits is + * pdTRUE then the wait condition is met if all the bits set in uxBitsToWaitFor + * are also set in uxCurrentEventBits. If xWaitForAllBits is pdFALSE then the + * wait condition is met if any of the bits set in uxBitsToWait for are also set + * in uxCurrentEventBits. + */ +static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, + const EventBits_t uxBitsToWaitFor, + const BaseType_t xWaitForAllBits ) PRIVILEGED_FUNCTION; + +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + + EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) + { + EventGroup_t * pxEventBits; + + /* A StaticEventGroup_t object must be provided. */ + configASSERT( pxEventGroupBuffer ); + + #if ( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + * variable of type StaticEventGroup_t equals the size of the real + * event group structure. */ + volatile size_t xSize = sizeof( StaticEventGroup_t ); + configASSERT( xSize == sizeof( EventGroup_t ) ); + } /*lint !e529 xSize is referenced if configASSERT() is defined. */ + #endif /* configASSERT_DEFINED */ + + /* The user has provided a statically allocated event group - use it. */ + pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; /*lint !e740 !e9087 EventGroup_t and StaticEventGroup_t are deliberately aliased for data hiding purposes and guaranteed to have the same size and alignment requirement - checked by configASSERT(). */ + + if( pxEventBits != NULL ) + { + pxEventBits->uxEventBits = 0; + vListInitialise( &( pxEventBits->xTasksWaitingForBits ) ); + + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + /* Both static and dynamic allocation can be used, so note that + * this event group was created statically in case the event group + * is later deleted. */ + pxEventBits->ucStaticallyAllocated = pdTRUE; + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + + traceEVENT_GROUP_CREATE( pxEventBits ); + } + else + { + /* xEventGroupCreateStatic should only ever be called with + * pxEventGroupBuffer pointing to a pre-allocated (compile time + * allocated) StaticEventGroup_t variable. */ + traceEVENT_GROUP_CREATE_FAILED(); + } + + return pxEventBits; + } + +#endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + EventGroupHandle_t xEventGroupCreate( void ) + { + EventGroup_t * pxEventBits; + + /* Allocate the event group. Justification for MISRA deviation as + * follows: pvPortMalloc() always ensures returned memory blocks are + * aligned per the requirements of the MCU stack. In this case + * pvPortMalloc() must return a pointer that is guaranteed to meet the + * alignment requirements of the EventGroup_t structure - which (if you + * follow it through) is the alignment requirements of the TickType_t type + * (EventBits_t being of TickType_t itself). Therefore, whenever the + * stack alignment requirements are greater than or equal to the + * TickType_t alignment requirements the cast is safe. In other cases, + * where the natural word size of the architecture is less than + * sizeof( TickType_t ), the TickType_t variables will be accessed in two + * or more reads operations, and the alignment requirements is only that + * of each individual read. */ + pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) ); /*lint !e9087 !e9079 see comment above. */ + + if( pxEventBits != NULL ) + { + pxEventBits->uxEventBits = 0; + vListInitialise( &( pxEventBits->xTasksWaitingForBits ) ); + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + /* Both static and dynamic allocation can be used, so note this + * event group was allocated statically in case the event group is + * later deleted. */ + pxEventBits->ucStaticallyAllocated = pdFALSE; + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ + + traceEVENT_GROUP_CREATE( pxEventBits ); + } + else + { + traceEVENT_GROUP_CREATE_FAILED(); /*lint !e9063 Else branch only exists to allow tracing and does not generate code if trace macros are not defined. */ + } + + return pxEventBits; + } + +#endif /* configSUPPORT_DYNAMIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) +{ + EventBits_t uxOriginalBitValue, uxReturn; + EventGroup_t * pxEventBits = xEventGroup; + BaseType_t xAlreadyYielded; + BaseType_t xTimeoutOccurred = pdFALSE; + + configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + configASSERT( uxBitsToWaitFor != 0 ); + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + vTaskSuspendAll(); + { + uxOriginalBitValue = pxEventBits->uxEventBits; + + ( void ) xEventGroupSetBits( xEventGroup, uxBitsToSet ); + + if( ( ( uxOriginalBitValue | uxBitsToSet ) & uxBitsToWaitFor ) == uxBitsToWaitFor ) + { + /* All the rendezvous bits are now set - no need to block. */ + uxReturn = ( uxOriginalBitValue | uxBitsToSet ); + + /* Rendezvous always clear the bits. They will have been cleared + * already unless this is the only task in the rendezvous. */ + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + + xTicksToWait = 0; + } + else + { + if( xTicksToWait != ( TickType_t ) 0 ) + { + traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor ); + + /* Store the bits that the calling task is waiting for in the + * task's event list item so the kernel knows when a match is + * found. Then enter the blocked state. */ + vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | eventCLEAR_EVENTS_ON_EXIT_BIT | eventWAIT_FOR_ALL_BITS ), xTicksToWait ); + + /* This assignment is obsolete as uxReturn will get set after + * the task unblocks, but some compilers mistakenly generate a + * warning about uxReturn being returned without being set if the + * assignment is omitted. */ + uxReturn = 0; + } + else + { + /* The rendezvous bits were not set, but no block time was + * specified - just return the current event bit value. */ + uxReturn = pxEventBits->uxEventBits; + xTimeoutOccurred = pdTRUE; + } + } + } + xAlreadyYielded = xTaskResumeAll(); + + if( xTicksToWait != ( TickType_t ) 0 ) + { + if( xAlreadyYielded == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The task blocked to wait for its required bits to be set - at this + * point either the required bits were set or the block time expired. If + * the required bits were set they will have been stored in the task's + * event list item, and they should now be retrieved then cleared. */ + uxReturn = uxTaskResetEventItemValue(); + + if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 ) + { + /* The task timed out, just return the current event bit value. */ + taskENTER_CRITICAL(); + { + uxReturn = pxEventBits->uxEventBits; + + /* Although the task got here because it timed out before the + * bits it was waiting for were set, it is possible that since it + * unblocked another task has set the bits. If this is the case + * then it needs to clear the bits before exiting. */ + if( ( uxReturn & uxBitsToWaitFor ) == uxBitsToWaitFor ) + { + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + xTimeoutOccurred = pdTRUE; + } + else + { + /* The task unblocked because the bits were set. */ + } + + /* Control bits might be set as the task had blocked should not be + * returned. */ + uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES; + } + + traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xTimeoutOccurred; + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToWaitFor, + const BaseType_t xClearOnExit, + const BaseType_t xWaitForAllBits, + TickType_t xTicksToWait ) +{ + EventGroup_t * pxEventBits = xEventGroup; + EventBits_t uxReturn, uxControlBits = 0; + BaseType_t xWaitConditionMet, xAlreadyYielded; + BaseType_t xTimeoutOccurred = pdFALSE; + + /* Check the user is not attempting to wait on the bits used by the kernel + * itself, and that at least one bit is being requested. */ + configASSERT( xEventGroup ); + configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + configASSERT( uxBitsToWaitFor != 0 ); + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + vTaskSuspendAll(); + { + const EventBits_t uxCurrentEventBits = pxEventBits->uxEventBits; + + /* Check to see if the wait condition is already met or not. */ + xWaitConditionMet = prvTestWaitCondition( uxCurrentEventBits, uxBitsToWaitFor, xWaitForAllBits ); + + if( xWaitConditionMet != pdFALSE ) + { + /* The wait condition has already been met so there is no need to + * block. */ + uxReturn = uxCurrentEventBits; + xTicksToWait = ( TickType_t ) 0; + + /* Clear the wait bits if requested to do so. */ + if( xClearOnExit != pdFALSE ) + { + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else if( xTicksToWait == ( TickType_t ) 0 ) + { + /* The wait condition has not been met, but no block time was + * specified, so just return the current value. */ + uxReturn = uxCurrentEventBits; + xTimeoutOccurred = pdTRUE; + } + else + { + /* The task is going to block to wait for its required bits to be + * set. uxControlBits are used to remember the specified behaviour of + * this call to xEventGroupWaitBits() - for use when the event bits + * unblock the task. */ + if( xClearOnExit != pdFALSE ) + { + uxControlBits |= eventCLEAR_EVENTS_ON_EXIT_BIT; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xWaitForAllBits != pdFALSE ) + { + uxControlBits |= eventWAIT_FOR_ALL_BITS; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Store the bits that the calling task is waiting for in the + * task's event list item so the kernel knows when a match is + * found. Then enter the blocked state. */ + vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | uxControlBits ), xTicksToWait ); + + /* This is obsolete as it will get set after the task unblocks, but + * some compilers mistakenly generate a warning about the variable + * being returned without being set if it is not done. */ + uxReturn = 0; + + traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor ); + } + } + xAlreadyYielded = xTaskResumeAll(); + + if( xTicksToWait != ( TickType_t ) 0 ) + { + if( xAlreadyYielded == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The task blocked to wait for its required bits to be set - at this + * point either the required bits were set or the block time expired. If + * the required bits were set they will have been stored in the task's + * event list item, and they should now be retrieved then cleared. */ + uxReturn = uxTaskResetEventItemValue(); + + if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 ) + { + taskENTER_CRITICAL(); + { + /* The task timed out, just return the current event bit value. */ + uxReturn = pxEventBits->uxEventBits; + + /* It is possible that the event bits were updated between this + * task leaving the Blocked state and running again. */ + if( prvTestWaitCondition( uxReturn, uxBitsToWaitFor, xWaitForAllBits ) != pdFALSE ) + { + if( xClearOnExit != pdFALSE ) + { + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xTimeoutOccurred = pdTRUE; + } + taskEXIT_CRITICAL(); + } + else + { + /* The task unblocked because the bits were set. */ + } + + /* The task blocked so control bits may have been set. */ + uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES; + } + + traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xTimeoutOccurred; + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) +{ + EventGroup_t * pxEventBits = xEventGroup; + EventBits_t uxReturn; + + /* Check the user is not attempting to clear the bits used by the kernel + * itself. */ + configASSERT( xEventGroup ); + configASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + + taskENTER_CRITICAL(); + { + traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear ); + + /* The value returned is the event group value prior to the bits being + * cleared. */ + uxReturn = pxEventBits->uxEventBits; + + /* Clear the bits. */ + pxEventBits->uxEventBits &= ~uxBitsToClear; + } + taskEXIT_CRITICAL(); + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) + + BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) + { + BaseType_t xReturn; + + traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear ); + xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */ + + return xReturn; + } + +#endif /* if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */ +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) +{ + UBaseType_t uxSavedInterruptStatus; + EventGroup_t const * const pxEventBits = xEventGroup; + EventBits_t uxReturn; + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + uxReturn = pxEventBits->uxEventBits; + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return uxReturn; +} /*lint !e818 EventGroupHandle_t is a typedef used in other functions to so can't be pointer to const. */ +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) +{ + ListItem_t * pxListItem, * pxNext; + ListItem_t const * pxListEnd; + List_t const * pxList; + EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits; + EventGroup_t * pxEventBits = xEventGroup; + BaseType_t xMatchFound = pdFALSE; + + /* Check the user is not attempting to set the bits used by the kernel + * itself. */ + configASSERT( xEventGroup ); + configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + + pxList = &( pxEventBits->xTasksWaitingForBits ); + pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + vTaskSuspendAll(); + { + traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet ); + + pxListItem = listGET_HEAD_ENTRY( pxList ); + + /* Set the bits. */ + pxEventBits->uxEventBits |= uxBitsToSet; + + /* See if the new bit value should unblock any tasks. */ + while( pxListItem != pxListEnd ) + { + pxNext = listGET_NEXT( pxListItem ); + uxBitsWaitedFor = listGET_LIST_ITEM_VALUE( pxListItem ); + xMatchFound = pdFALSE; + + /* Split the bits waited for from the control bits. */ + uxControlBits = uxBitsWaitedFor & eventEVENT_BITS_CONTROL_BYTES; + uxBitsWaitedFor &= ~eventEVENT_BITS_CONTROL_BYTES; + + if( ( uxControlBits & eventWAIT_FOR_ALL_BITS ) == ( EventBits_t ) 0 ) + { + /* Just looking for single bit being set. */ + if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) != ( EventBits_t ) 0 ) + { + xMatchFound = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) == uxBitsWaitedFor ) + { + /* All bits are set. */ + xMatchFound = pdTRUE; + } + else + { + /* Need all bits to be set, but not all the bits were set. */ + } + + if( xMatchFound != pdFALSE ) + { + /* The bits match. Should the bits be cleared on exit? */ + if( ( uxControlBits & eventCLEAR_EVENTS_ON_EXIT_BIT ) != ( EventBits_t ) 0 ) + { + uxBitsToClear |= uxBitsWaitedFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Store the actual event flag value in the task's event list + * item before removing the task from the event list. The + * eventUNBLOCKED_DUE_TO_BIT_SET bit is set so the task knows + * that is was unblocked due to its required bits matching, rather + * than because it timed out. */ + vTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET ); + } + + /* Move onto the next list item. Note pxListItem->pxNext is not + * used here as the list item may have been removed from the event list + * and inserted into the ready/pending reading list. */ + pxListItem = pxNext; + } + + /* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT + * bit was set in the control word. */ + pxEventBits->uxEventBits &= ~uxBitsToClear; + } + ( void ) xTaskResumeAll(); + + return pxEventBits->uxEventBits; +} +/*-----------------------------------------------------------*/ + +void vEventGroupDelete( EventGroupHandle_t xEventGroup ) +{ + EventGroup_t * pxEventBits = xEventGroup; + const List_t * pxTasksWaitingForBits; + + configASSERT( pxEventBits ); + + pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits ); + + vTaskSuspendAll(); + { + traceEVENT_GROUP_DELETE( xEventGroup ); + + while( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 ) + { + /* Unblock the task, returning 0 as the event list is being deleted + * and cannot therefore have any bits set. */ + configASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( const ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) ); + vTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET ); + } + + #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) ) + { + /* The event group can only have been allocated dynamically - free + * it again. */ + vPortFree( pxEventBits ); + } + #elif ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + { + /* The event group could have been allocated statically or + * dynamically, so check before attempting to free the memory. */ + if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdFALSE ) + { + vPortFree( pxEventBits ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + } + ( void ) xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +/* For internal use only - execute a 'set bits' command that was pended from + * an interrupt. */ +void vEventGroupSetBitsCallback( void * pvEventGroup, + const uint32_t ulBitsToSet ) +{ + ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */ +} +/*-----------------------------------------------------------*/ + +/* For internal use only - execute a 'clear bits' command that was pended from + * an interrupt. */ +void vEventGroupClearBitsCallback( void * pvEventGroup, + const uint32_t ulBitsToClear ) +{ + ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */ +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, + const EventBits_t uxBitsToWaitFor, + const BaseType_t xWaitForAllBits ) +{ + BaseType_t xWaitConditionMet = pdFALSE; + + if( xWaitForAllBits == pdFALSE ) + { + /* Task only has to wait for one bit within uxBitsToWaitFor to be + * set. Is one already set? */ + if( ( uxCurrentEventBits & uxBitsToWaitFor ) != ( EventBits_t ) 0 ) + { + xWaitConditionMet = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* Task has to wait for all the bits in uxBitsToWaitFor to be set. + * Are they set already? */ + if( ( uxCurrentEventBits & uxBitsToWaitFor ) == uxBitsToWaitFor ) + { + xWaitConditionMet = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + return xWaitConditionMet; +} +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) + + BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + BaseType_t * pxHigherPriorityTaskWoken ) + { + BaseType_t xReturn; + + traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet ); + xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */ + + return xReturn; + } + +#endif /* if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t uxEventGroupGetNumber( void * xEventGroup ) + { + UBaseType_t xReturn; + EventGroup_t const * pxEventBits = ( EventGroup_t * ) xEventGroup; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */ + + if( xEventGroup == NULL ) + { + xReturn = 0; + } + else + { + xReturn = pxEventBits->uxEventGroupNumber; + } + + return xReturn; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + void vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) + { + ( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */ + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ diff --git a/hw-libs/freertos/include/FreeRTOS.h b/hw-libs/freertos/include/FreeRTOS.h new file mode 100644 index 000000000..383f04a70 --- /dev/null +++ b/hw-libs/freertos/include/FreeRTOS.h @@ -0,0 +1,1362 @@ +/* + * FreeRTOS Kernel V10.4.6 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef INC_FREERTOS_H +#define INC_FREERTOS_H + +/* + * Include the generic headers required for the FreeRTOS port being used. + */ +#include + +/* + * If stdint.h cannot be located then: + * + If using GCC ensure the -nostdint options is *not* being used. + * + Ensure the project's include path includes the directory in which your + * compiler stores stdint.h. + * + Set any compiler options necessary for it to support C99, as technically + * stdint.h is only mandatory with C99 (FreeRTOS does not require C99 in any + * other way). + * + The FreeRTOS download includes a simple stdint.h definition that can be + * used in cases where none is provided by the compiler. The files only + * contains the typedefs required to build FreeRTOS. Read the instructions + * in FreeRTOS/source/stdint.readme for more information. + */ +#include /* READ COMMENT ABOVE. */ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* Application specific configuration options. */ +#include "FreeRTOSConfig.h" + +/* Basic FreeRTOS definitions. */ +#include "projdefs.h" + +/* Definitions specific to the port being used. */ +#include "portable.h" + +/* Must be defaulted before configUSE_NEWLIB_REENTRANT is used below. */ +#ifndef configUSE_NEWLIB_REENTRANT + #define configUSE_NEWLIB_REENTRANT 0 +#endif + +/* Required if struct _reent is used. */ +#if ( configUSE_NEWLIB_REENTRANT == 1 ) + #include +#endif + +/* + * Check all the required application specific macros have been defined. + * These macros are application specific and (as downloaded) are defined + * within FreeRTOSConfig.h. + */ + +#ifndef configMINIMAL_STACK_SIZE + #error Missing definition: configMINIMAL_STACK_SIZE must be defined in FreeRTOSConfig.h. configMINIMAL_STACK_SIZE defines the size (in words) of the stack allocated to the idle task. Refer to the demo project provided for your port for a suitable value. +#endif + +#ifndef configMAX_PRIORITIES + #error Missing definition: configMAX_PRIORITIES must be defined in FreeRTOSConfig.h. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#if configMAX_PRIORITIES < 1 + #error configMAX_PRIORITIES must be defined to be greater than or equal to 1. +#endif + +#ifndef configUSE_PREEMPTION + #error Missing definition: configUSE_PREEMPTION must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_IDLE_HOOK + #error Missing definition: configUSE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_TICK_HOOK + #error Missing definition: configUSE_TICK_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_16_BIT_TICKS + #error Missing definition: configUSE_16_BIT_TICKS must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_CO_ROUTINES + #define configUSE_CO_ROUTINES 0 +#endif + +#ifndef INCLUDE_vTaskPrioritySet + #define INCLUDE_vTaskPrioritySet 0 +#endif + +#ifndef INCLUDE_uxTaskPriorityGet + #define INCLUDE_uxTaskPriorityGet 0 +#endif + +#ifndef INCLUDE_vTaskDelete + #define INCLUDE_vTaskDelete 0 +#endif + +#ifndef INCLUDE_vTaskSuspend + #define INCLUDE_vTaskSuspend 0 +#endif + +#ifdef INCLUDE_xTaskDelayUntil + #ifdef INCLUDE_vTaskDelayUntil + +/* INCLUDE_vTaskDelayUntil was replaced by INCLUDE_xTaskDelayUntil. Backward + * compatibility is maintained if only one or the other is defined, but + * there is a conflict if both are defined. */ + #error INCLUDE_vTaskDelayUntil and INCLUDE_xTaskDelayUntil are both defined. INCLUDE_vTaskDelayUntil is no longer required and should be removed + #endif +#endif + +#ifndef INCLUDE_xTaskDelayUntil + #ifdef INCLUDE_vTaskDelayUntil + +/* If INCLUDE_vTaskDelayUntil is set but INCLUDE_xTaskDelayUntil is not then + * the project's FreeRTOSConfig.h probably pre-dates the introduction of + * xTaskDelayUntil and setting INCLUDE_xTaskDelayUntil to whatever + * INCLUDE_vTaskDelayUntil is set to will ensure backward compatibility. + */ + #define INCLUDE_xTaskDelayUntil INCLUDE_vTaskDelayUntil + #endif +#endif + +#ifndef INCLUDE_xTaskDelayUntil + #define INCLUDE_xTaskDelayUntil 0 +#endif + +#ifndef INCLUDE_vTaskDelay + #define INCLUDE_vTaskDelay 0 +#endif + +#ifndef INCLUDE_xTaskGetIdleTaskHandle + #define INCLUDE_xTaskGetIdleTaskHandle 0 +#endif + +#ifndef INCLUDE_xTaskAbortDelay + #define INCLUDE_xTaskAbortDelay 0 +#endif + +#ifndef INCLUDE_xQueueGetMutexHolder + #define INCLUDE_xQueueGetMutexHolder 0 +#endif + +#ifndef INCLUDE_xSemaphoreGetMutexHolder + #define INCLUDE_xSemaphoreGetMutexHolder INCLUDE_xQueueGetMutexHolder +#endif + +#ifndef INCLUDE_xTaskGetHandle + #define INCLUDE_xTaskGetHandle 0 +#endif + +#ifndef INCLUDE_uxTaskGetStackHighWaterMark + #define INCLUDE_uxTaskGetStackHighWaterMark 0 +#endif + +#ifndef INCLUDE_uxTaskGetStackHighWaterMark2 + #define INCLUDE_uxTaskGetStackHighWaterMark2 0 +#endif + +#ifndef INCLUDE_eTaskGetState + #define INCLUDE_eTaskGetState 0 +#endif + +#ifndef INCLUDE_xTaskResumeFromISR + #define INCLUDE_xTaskResumeFromISR 1 +#endif + +#ifndef INCLUDE_xTimerPendFunctionCall + #define INCLUDE_xTimerPendFunctionCall 0 +#endif + +#ifndef INCLUDE_xTaskGetSchedulerState + #define INCLUDE_xTaskGetSchedulerState 0 +#endif + +#ifndef INCLUDE_xTaskGetCurrentTaskHandle + #define INCLUDE_xTaskGetCurrentTaskHandle 0 +#endif + +#if configUSE_CO_ROUTINES != 0 + #ifndef configMAX_CO_ROUTINE_PRIORITIES + #error configMAX_CO_ROUTINE_PRIORITIES must be greater than or equal to 1. + #endif +#endif + +#ifndef configUSE_DAEMON_TASK_STARTUP_HOOK + #define configUSE_DAEMON_TASK_STARTUP_HOOK 0 +#endif + +#ifndef configUSE_APPLICATION_TASK_TAG + #define configUSE_APPLICATION_TASK_TAG 0 +#endif + +#ifndef configNUM_THREAD_LOCAL_STORAGE_POINTERS + #define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0 +#endif + +#ifndef configUSE_RECURSIVE_MUTEXES + #define configUSE_RECURSIVE_MUTEXES 0 +#endif + +#ifndef configUSE_MUTEXES + #define configUSE_MUTEXES 0 +#endif + +#ifndef configUSE_TIMERS + #define configUSE_TIMERS 0 +#endif + +#ifndef configUSE_COUNTING_SEMAPHORES + #define configUSE_COUNTING_SEMAPHORES 0 +#endif + +#ifndef configUSE_ALTERNATIVE_API + #define configUSE_ALTERNATIVE_API 0 +#endif + +#ifndef portCRITICAL_NESTING_IN_TCB + #define portCRITICAL_NESTING_IN_TCB 0 +#endif + +#ifndef configMAX_TASK_NAME_LEN + #define configMAX_TASK_NAME_LEN 16 +#endif + +#ifndef configIDLE_SHOULD_YIELD + #define configIDLE_SHOULD_YIELD 1 +#endif + +#if configMAX_TASK_NAME_LEN < 1 + #error configMAX_TASK_NAME_LEN must be set to a minimum of 1 in FreeRTOSConfig.h +#endif + +#ifndef configASSERT + #define configASSERT( x ) + #define configASSERT_DEFINED 0 +#else + #define configASSERT_DEFINED 1 +#endif + +/* configPRECONDITION should be defined as configASSERT. + * The CBMC proofs need a way to track assumptions and assertions. + * A configPRECONDITION statement should express an implicit invariant or + * assumption made. A configASSERT statement should express an invariant that must + * hold explicit before calling the code. */ +#ifndef configPRECONDITION + #define configPRECONDITION( X ) configASSERT( X ) + #define configPRECONDITION_DEFINED 0 +#else + #define configPRECONDITION_DEFINED 1 +#endif + +#ifndef portMEMORY_BARRIER + #define portMEMORY_BARRIER() +#endif + +#ifndef portSOFTWARE_BARRIER + #define portSOFTWARE_BARRIER() +#endif + +/* The timers module relies on xTaskGetSchedulerState(). */ +#if configUSE_TIMERS == 1 + + #ifndef configTIMER_TASK_PRIORITY + #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_PRIORITY must also be defined. + #endif /* configTIMER_TASK_PRIORITY */ + + #ifndef configTIMER_QUEUE_LENGTH + #error If configUSE_TIMERS is set to 1 then configTIMER_QUEUE_LENGTH must also be defined. + #endif /* configTIMER_QUEUE_LENGTH */ + + #ifndef configTIMER_TASK_STACK_DEPTH + #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_STACK_DEPTH must also be defined. + #endif /* configTIMER_TASK_STACK_DEPTH */ + +#endif /* configUSE_TIMERS */ + +#ifndef portSET_INTERRUPT_MASK_FROM_ISR + #define portSET_INTERRUPT_MASK_FROM_ISR() 0 +#endif + +#ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue +#endif + +#ifndef portCLEAN_UP_TCB + #define portCLEAN_UP_TCB( pxTCB ) ( void ) pxTCB +#endif + +#ifndef portPRE_TASK_DELETE_HOOK + #define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxYieldPending ) +#endif + +#ifndef portSETUP_TCB + #define portSETUP_TCB( pxTCB ) ( void ) pxTCB +#endif + +#ifndef configQUEUE_REGISTRY_SIZE + #define configQUEUE_REGISTRY_SIZE 0U +#endif + +#if ( configQUEUE_REGISTRY_SIZE < 1 ) + #define vQueueAddToRegistry( xQueue, pcName ) + #define vQueueUnregisterQueue( xQueue ) + #define pcQueueGetName( xQueue ) +#endif + +#ifndef portPOINTER_SIZE_TYPE + #define portPOINTER_SIZE_TYPE uint32_t +#endif + +/* Remove any unused trace macros. */ +#ifndef traceSTART + +/* Used to perform any necessary initialisation - for example, open a file + * into which trace is to be written. */ + #define traceSTART() +#endif + +#ifndef traceEND + +/* Use to close a trace, for example close a file into which trace has been + * written. */ + #define traceEND() +#endif + +#ifndef traceTASK_SWITCHED_IN + +/* Called after a task has been selected to run. pxCurrentTCB holds a pointer + * to the task control block of the selected task. */ + #define traceTASK_SWITCHED_IN() +#endif + +#ifndef traceINCREASE_TICK_COUNT + +/* Called before stepping the tick count after waking from tickless idle + * sleep. */ + #define traceINCREASE_TICK_COUNT( x ) +#endif + +#ifndef traceLOW_POWER_IDLE_BEGIN + /* Called immediately before entering tickless idle. */ + #define traceLOW_POWER_IDLE_BEGIN() +#endif + +#ifndef traceLOW_POWER_IDLE_END + /* Called when returning to the Idle task after a tickless idle. */ + #define traceLOW_POWER_IDLE_END() +#endif + +#ifndef traceTASK_SWITCHED_OUT + +/* Called before a task has been selected to run. pxCurrentTCB holds a pointer + * to the task control block of the task being switched out. */ + #define traceTASK_SWITCHED_OUT() +#endif + +#ifndef traceTASK_PRIORITY_INHERIT + +/* Called when a task attempts to take a mutex that is already held by a + * lower priority task. pxTCBOfMutexHolder is a pointer to the TCB of the task + * that holds the mutex. uxInheritedPriority is the priority the mutex holder + * will inherit (the priority of the task that is attempting to obtain the + * muted. */ + #define traceTASK_PRIORITY_INHERIT( pxTCBOfMutexHolder, uxInheritedPriority ) +#endif + +#ifndef traceTASK_PRIORITY_DISINHERIT + +/* Called when a task releases a mutex, the holding of which had resulted in + * the task inheriting the priority of a higher priority task. + * pxTCBOfMutexHolder is a pointer to the TCB of the task that is releasing the + * mutex. uxOriginalPriority is the task's configured (base) priority. */ + #define traceTASK_PRIORITY_DISINHERIT( pxTCBOfMutexHolder, uxOriginalPriority ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_RECEIVE + +/* Task is about to block because it cannot read from a + * queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + * upon which the read was attempted. pxCurrentTCB points to the TCB of the + * task that attempted the read. */ + #define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_PEEK + +/* Task is about to block because it cannot read from a + * queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + * upon which the read was attempted. pxCurrentTCB points to the TCB of the + * task that attempted the read. */ + #define traceBLOCKING_ON_QUEUE_PEEK( pxQueue ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_SEND + +/* Task is about to block because it cannot write to a + * queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + * upon which the write was attempted. pxCurrentTCB points to the TCB of the + * task that attempted the write. */ + #define traceBLOCKING_ON_QUEUE_SEND( pxQueue ) +#endif + +#ifndef configCHECK_FOR_STACK_OVERFLOW + #define configCHECK_FOR_STACK_OVERFLOW 0 +#endif + +#ifndef configRECORD_STACK_HIGH_ADDRESS + #define configRECORD_STACK_HIGH_ADDRESS 0 +#endif + +#ifndef configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H + #define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 0 +#endif + +/* The following event macros are embedded in the kernel API calls. */ + +#ifndef traceMOVED_TASK_TO_READY_STATE + #define traceMOVED_TASK_TO_READY_STATE( pxTCB ) +#endif + +#ifndef tracePOST_MOVED_TASK_TO_READY_STATE + #define tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB ) +#endif + +#ifndef traceQUEUE_CREATE + #define traceQUEUE_CREATE( pxNewQueue ) +#endif + +#ifndef traceQUEUE_CREATE_FAILED + #define traceQUEUE_CREATE_FAILED( ucQueueType ) +#endif + +#ifndef traceCREATE_MUTEX + #define traceCREATE_MUTEX( pxNewQueue ) +#endif + +#ifndef traceCREATE_MUTEX_FAILED + #define traceCREATE_MUTEX_FAILED() +#endif + +#ifndef traceGIVE_MUTEX_RECURSIVE + #define traceGIVE_MUTEX_RECURSIVE( pxMutex ) +#endif + +#ifndef traceGIVE_MUTEX_RECURSIVE_FAILED + #define traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex ) +#endif + +#ifndef traceTAKE_MUTEX_RECURSIVE + #define traceTAKE_MUTEX_RECURSIVE( pxMutex ) +#endif + +#ifndef traceTAKE_MUTEX_RECURSIVE_FAILED + #define traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex ) +#endif + +#ifndef traceCREATE_COUNTING_SEMAPHORE + #define traceCREATE_COUNTING_SEMAPHORE() +#endif + +#ifndef traceCREATE_COUNTING_SEMAPHORE_FAILED + #define traceCREATE_COUNTING_SEMAPHORE_FAILED() +#endif + +#ifndef traceQUEUE_SET_SEND + #define traceQUEUE_SET_SEND traceQUEUE_SEND +#endif + +#ifndef traceQUEUE_SEND + #define traceQUEUE_SEND( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FAILED + #define traceQUEUE_SEND_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE + #define traceQUEUE_RECEIVE( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK + #define traceQUEUE_PEEK( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FAILED + #define traceQUEUE_PEEK_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FROM_ISR + #define traceQUEUE_PEEK_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FAILED + #define traceQUEUE_RECEIVE_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FROM_ISR + #define traceQUEUE_SEND_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FROM_ISR_FAILED + #define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FROM_ISR + #define traceQUEUE_RECEIVE_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FROM_ISR_FAILED + #define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FROM_ISR_FAILED + #define traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_DELETE + #define traceQUEUE_DELETE( pxQueue ) +#endif + +#ifndef traceTASK_CREATE + #define traceTASK_CREATE( pxNewTCB ) +#endif + +#ifndef traceTASK_CREATE_FAILED + #define traceTASK_CREATE_FAILED() +#endif + +#ifndef traceTASK_DELETE + #define traceTASK_DELETE( pxTaskToDelete ) +#endif + +#ifndef traceTASK_DELAY_UNTIL + #define traceTASK_DELAY_UNTIL( x ) +#endif + +#ifndef traceTASK_DELAY + #define traceTASK_DELAY() +#endif + +#ifndef traceTASK_PRIORITY_SET + #define traceTASK_PRIORITY_SET( pxTask, uxNewPriority ) +#endif + +#ifndef traceTASK_SUSPEND + #define traceTASK_SUSPEND( pxTaskToSuspend ) +#endif + +#ifndef traceTASK_RESUME + #define traceTASK_RESUME( pxTaskToResume ) +#endif + +#ifndef traceTASK_RESUME_FROM_ISR + #define traceTASK_RESUME_FROM_ISR( pxTaskToResume ) +#endif + +#ifndef traceTASK_INCREMENT_TICK + #define traceTASK_INCREMENT_TICK( xTickCount ) +#endif + +#ifndef traceTIMER_CREATE + #define traceTIMER_CREATE( pxNewTimer ) +#endif + +#ifndef traceTIMER_CREATE_FAILED + #define traceTIMER_CREATE_FAILED() +#endif + +#ifndef traceTIMER_COMMAND_SEND + #define traceTIMER_COMMAND_SEND( xTimer, xMessageID, xMessageValueValue, xReturn ) +#endif + +#ifndef traceTIMER_EXPIRED + #define traceTIMER_EXPIRED( pxTimer ) +#endif + +#ifndef traceTIMER_COMMAND_RECEIVED + #define traceTIMER_COMMAND_RECEIVED( pxTimer, xMessageID, xMessageValue ) +#endif + +#ifndef traceMALLOC + #define traceMALLOC( pvAddress, uiSize ) +#endif + +#ifndef traceFREE + #define traceFREE( pvAddress, uiSize ) +#endif + +#ifndef traceEVENT_GROUP_CREATE + #define traceEVENT_GROUP_CREATE( xEventGroup ) +#endif + +#ifndef traceEVENT_GROUP_CREATE_FAILED + #define traceEVENT_GROUP_CREATE_FAILED() +#endif + +#ifndef traceEVENT_GROUP_SYNC_BLOCK + #define traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor ) +#endif + +#ifndef traceEVENT_GROUP_SYNC_END + #define traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred +#endif + +#ifndef traceEVENT_GROUP_WAIT_BITS_BLOCK + #define traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor ) +#endif + +#ifndef traceEVENT_GROUP_WAIT_BITS_END + #define traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred +#endif + +#ifndef traceEVENT_GROUP_CLEAR_BITS + #define traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear ) +#endif + +#ifndef traceEVENT_GROUP_CLEAR_BITS_FROM_ISR + #define traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear ) +#endif + +#ifndef traceEVENT_GROUP_SET_BITS + #define traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet ) +#endif + +#ifndef traceEVENT_GROUP_SET_BITS_FROM_ISR + #define traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet ) +#endif + +#ifndef traceEVENT_GROUP_DELETE + #define traceEVENT_GROUP_DELETE( xEventGroup ) +#endif + +#ifndef tracePEND_FUNC_CALL + #define tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, ret ) +#endif + +#ifndef tracePEND_FUNC_CALL_FROM_ISR + #define tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, ret ) +#endif + +#ifndef traceQUEUE_REGISTRY_ADD + #define traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName ) +#endif + +#ifndef traceTASK_NOTIFY_TAKE_BLOCK + #define traceTASK_NOTIFY_TAKE_BLOCK( uxIndexToWait ) +#endif + +#ifndef traceTASK_NOTIFY_TAKE + #define traceTASK_NOTIFY_TAKE( uxIndexToWait ) +#endif + +#ifndef traceTASK_NOTIFY_WAIT_BLOCK + #define traceTASK_NOTIFY_WAIT_BLOCK( uxIndexToWait ) +#endif + +#ifndef traceTASK_NOTIFY_WAIT + #define traceTASK_NOTIFY_WAIT( uxIndexToWait ) +#endif + +#ifndef traceTASK_NOTIFY + #define traceTASK_NOTIFY( uxIndexToNotify ) +#endif + +#ifndef traceTASK_NOTIFY_FROM_ISR + #define traceTASK_NOTIFY_FROM_ISR( uxIndexToNotify ) +#endif + +#ifndef traceTASK_NOTIFY_GIVE_FROM_ISR + #define traceTASK_NOTIFY_GIVE_FROM_ISR( uxIndexToNotify ) +#endif + +#ifndef traceSTREAM_BUFFER_CREATE_FAILED + #define traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_CREATE_STATIC_FAILED + #define traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_CREATE + #define traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_DELETE + #define traceSTREAM_BUFFER_DELETE( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RESET + #define traceSTREAM_BUFFER_RESET( xStreamBuffer ) +#endif + +#ifndef traceBLOCKING_ON_STREAM_BUFFER_SEND + #define traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND + #define traceSTREAM_BUFFER_SEND( xStreamBuffer, xBytesSent ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND_FAILED + #define traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND_FROM_ISR + #define traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xBytesSent ) +#endif + +#ifndef traceBLOCKING_ON_STREAM_BUFFER_RECEIVE + #define traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE + #define traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE_FAILED + #define traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE_FROM_ISR + #define traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength ) +#endif + +#ifndef configGENERATE_RUN_TIME_STATS + #define configGENERATE_RUN_TIME_STATS 0 +#endif + +#if ( configGENERATE_RUN_TIME_STATS == 1 ) + + #ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS + #error If configGENERATE_RUN_TIME_STATS is defined then portCONFIGURE_TIMER_FOR_RUN_TIME_STATS must also be defined. portCONFIGURE_TIMER_FOR_RUN_TIME_STATS should call a port layer function to setup a peripheral timer/counter that can then be used as the run time counter time base. + #endif /* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS */ + + #ifndef portGET_RUN_TIME_COUNTER_VALUE + #ifndef portALT_GET_RUN_TIME_COUNTER_VALUE + #error If configGENERATE_RUN_TIME_STATS is defined then either portGET_RUN_TIME_COUNTER_VALUE or portALT_GET_RUN_TIME_COUNTER_VALUE must also be defined. See the examples provided and the FreeRTOS web site for more information. + #endif /* portALT_GET_RUN_TIME_COUNTER_VALUE */ + #endif /* portGET_RUN_TIME_COUNTER_VALUE */ + +#endif /* configGENERATE_RUN_TIME_STATS */ + +#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS + #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() +#endif + +#ifndef configUSE_MALLOC_FAILED_HOOK + #define configUSE_MALLOC_FAILED_HOOK 0 +#endif + +#ifndef portPRIVILEGE_BIT + #define portPRIVILEGE_BIT ( ( UBaseType_t ) 0x00 ) +#endif + +#ifndef portYIELD_WITHIN_API + #define portYIELD_WITHIN_API portYIELD +#endif + +#ifndef portSUPPRESS_TICKS_AND_SLEEP + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) +#endif + +#ifndef configEXPECTED_IDLE_TIME_BEFORE_SLEEP + #define configEXPECTED_IDLE_TIME_BEFORE_SLEEP 2 +#endif + +#if configEXPECTED_IDLE_TIME_BEFORE_SLEEP < 2 + #error configEXPECTED_IDLE_TIME_BEFORE_SLEEP must not be less than 2 +#endif + +#ifndef configUSE_TICKLESS_IDLE + #define configUSE_TICKLESS_IDLE 0 +#endif + +#ifndef configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING + #define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( x ) +#endif + +#ifndef configPRE_SLEEP_PROCESSING + #define configPRE_SLEEP_PROCESSING( x ) +#endif + +#ifndef configPOST_SLEEP_PROCESSING + #define configPOST_SLEEP_PROCESSING( x ) +#endif + +#ifndef configUSE_QUEUE_SETS + #define configUSE_QUEUE_SETS 0 +#endif + +#ifndef portTASK_USES_FLOATING_POINT + #define portTASK_USES_FLOATING_POINT() +#endif + +#ifndef portALLOCATE_SECURE_CONTEXT + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) +#endif + +#ifndef portDONT_DISCARD + #define portDONT_DISCARD +#endif + +#ifndef configUSE_TIME_SLICING + #define configUSE_TIME_SLICING 1 +#endif + +#ifndef configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS + #define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0 +#endif + +#ifndef configUSE_STATS_FORMATTING_FUNCTIONS + #define configUSE_STATS_FORMATTING_FUNCTIONS 0 +#endif + +#ifndef portASSERT_IF_INTERRUPT_PRIORITY_INVALID + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() +#endif + +#ifndef configUSE_TRACE_FACILITY + #define configUSE_TRACE_FACILITY 0 +#endif + +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +#ifndef mtCOVERAGE_TEST_DELAY + #define mtCOVERAGE_TEST_DELAY() +#endif + +#ifndef portASSERT_IF_IN_ISR + #define portASSERT_IF_IN_ISR() +#endif + +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#endif + +#ifndef configAPPLICATION_ALLOCATED_HEAP + #define configAPPLICATION_ALLOCATED_HEAP 0 +#endif + +#ifndef configUSE_TASK_NOTIFICATIONS + #define configUSE_TASK_NOTIFICATIONS 1 +#endif + +#ifndef configTASK_NOTIFICATION_ARRAY_ENTRIES + #define configTASK_NOTIFICATION_ARRAY_ENTRIES 1 +#endif + +#if configTASK_NOTIFICATION_ARRAY_ENTRIES < 1 + #error configTASK_NOTIFICATION_ARRAY_ENTRIES must be at least 1 +#endif + +#ifndef configUSE_POSIX_ERRNO + #define configUSE_POSIX_ERRNO 0 +#endif + +#ifndef portTICK_TYPE_IS_ATOMIC + #define portTICK_TYPE_IS_ATOMIC 0 +#endif + +#ifndef configSUPPORT_STATIC_ALLOCATION + /* Defaults to 0 for backward compatibility. */ + #define configSUPPORT_STATIC_ALLOCATION 0 +#endif + +#ifndef configSUPPORT_DYNAMIC_ALLOCATION + /* Defaults to 1 for backward compatibility. */ + #define configSUPPORT_DYNAMIC_ALLOCATION 1 +#endif + +#ifndef configSTACK_DEPTH_TYPE + +/* Defaults to uint16_t for backward compatibility, but can be overridden + * in FreeRTOSConfig.h if uint16_t is too restrictive. */ + #define configSTACK_DEPTH_TYPE uint16_t +#endif + +#ifndef configRUN_TIME_COUNTER_TYPE + +/* Defaults to uint32_t for backward compatibility, but can be overridden in + * FreeRTOSConfig.h if uint32_t is too restrictive. */ + + #define configRUN_TIME_COUNTER_TYPE uint32_t +#endif + +#ifndef configMESSAGE_BUFFER_LENGTH_TYPE + +/* Defaults to size_t for backward compatibility, but can be overridden + * in FreeRTOSConfig.h if lengths will always be less than the number of bytes + * in a size_t. */ + #define configMESSAGE_BUFFER_LENGTH_TYPE size_t +#endif + +/* Sanity check the configuration. */ +#if ( configUSE_TICKLESS_IDLE != 0 ) + #if ( INCLUDE_vTaskSuspend != 1 ) + #error INCLUDE_vTaskSuspend must be set to 1 if configUSE_TICKLESS_IDLE is not set to 0 + #endif /* INCLUDE_vTaskSuspend */ +#endif /* configUSE_TICKLESS_IDLE */ + +#if ( ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) ) + #error configSUPPORT_STATIC_ALLOCATION and configSUPPORT_DYNAMIC_ALLOCATION cannot both be 0, but can both be 1. +#endif + +#if ( ( configUSE_RECURSIVE_MUTEXES == 1 ) && ( configUSE_MUTEXES != 1 ) ) + #error configUSE_MUTEXES must be set to 1 to use recursive mutexes +#endif + +#ifndef configINITIAL_TICK_COUNT + #define configINITIAL_TICK_COUNT 0 +#endif + +#if ( portTICK_TYPE_IS_ATOMIC == 0 ) + +/* Either variables of tick type cannot be read atomically, or + * portTICK_TYPE_IS_ATOMIC was not set - map the critical sections used when + * the tick count is returned to the standard critical section macros. */ + #define portTICK_TYPE_ENTER_CRITICAL() portENTER_CRITICAL() + #define portTICK_TYPE_EXIT_CRITICAL() portEXIT_CRITICAL() + #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR() + #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( ( x ) ) +#else + +/* The tick type can be read atomically, so critical sections used when the + * tick count is returned can be defined away. */ + #define portTICK_TYPE_ENTER_CRITICAL() + #define portTICK_TYPE_EXIT_CRITICAL() + #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() 0 + #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) ( void ) x +#endif /* if ( portTICK_TYPE_IS_ATOMIC == 0 ) */ + +/* Definitions to allow backward compatibility with FreeRTOS versions prior to + * V8 if desired. */ +#ifndef configENABLE_BACKWARD_COMPATIBILITY + #define configENABLE_BACKWARD_COMPATIBILITY 1 +#endif + +#ifndef configPRINTF + +/* configPRINTF() was not defined, so define it away to nothing. To use + * configPRINTF() then define it as follows (where MyPrintFunction() is + * provided by the application writer): + * + * void MyPrintFunction(const char *pcFormat, ... ); + #define configPRINTF( X ) MyPrintFunction X + * + * Then call like a standard printf() function, but placing brackets around + * all parameters so they are passed as a single parameter. For example: + * configPRINTF( ("Value = %d", MyVariable) ); */ + #define configPRINTF( X ) +#endif + +#ifndef configMAX + +/* The application writer has not provided their own MAX macro, so define + * the following generic implementation. */ + #define configMAX( a, b ) ( ( ( a ) > ( b ) ) ? ( a ) : ( b ) ) +#endif + +#ifndef configMIN + +/* The application writer has not provided their own MIN macro, so define + * the following generic implementation. */ + #define configMIN( a, b ) ( ( ( a ) < ( b ) ) ? ( a ) : ( b ) ) +#endif + +#if configENABLE_BACKWARD_COMPATIBILITY == 1 + #define eTaskStateGet eTaskGetState + #define portTickType TickType_t + #define xTaskHandle TaskHandle_t + #define xQueueHandle QueueHandle_t + #define xSemaphoreHandle SemaphoreHandle_t + #define xQueueSetHandle QueueSetHandle_t + #define xQueueSetMemberHandle QueueSetMemberHandle_t + #define xTimeOutType TimeOut_t + #define xMemoryRegion MemoryRegion_t + #define xTaskParameters TaskParameters_t + #define xTaskStatusType TaskStatus_t + #define xTimerHandle TimerHandle_t + #define xCoRoutineHandle CoRoutineHandle_t + #define pdTASK_HOOK_CODE TaskHookFunction_t + #define portTICK_RATE_MS portTICK_PERIOD_MS + #define pcTaskGetTaskName pcTaskGetName + #define pcTimerGetTimerName pcTimerGetName + #define pcQueueGetQueueName pcQueueGetName + #define vTaskGetTaskInfo vTaskGetInfo + #define xTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounter + +/* Backward compatibility within the scheduler code only - these definitions + * are not really required but are included for completeness. */ + #define tmrTIMER_CALLBACK TimerCallbackFunction_t + #define pdTASK_CODE TaskFunction_t + #define xListItem ListItem_t + #define xList List_t + +/* For libraries that break the list data hiding, and access list structure + * members directly (which is not supposed to be done). */ + #define pxContainer pvContainer +#endif /* configENABLE_BACKWARD_COMPATIBILITY */ + +#if ( configUSE_ALTERNATIVE_API != 0 ) + #error The alternative API was deprecated some time ago, and was removed in FreeRTOS V9.0 0 +#endif + +/* Set configUSE_TASK_FPU_SUPPORT to 0 to omit floating point support even + * if floating point hardware is otherwise supported by the FreeRTOS port in use. + * This constant is not supported by all FreeRTOS ports that include floating + * point support. */ +#ifndef configUSE_TASK_FPU_SUPPORT + #define configUSE_TASK_FPU_SUPPORT 1 +#endif + +/* Set configENABLE_MPU to 1 to enable MPU support and 0 to disable it. This is + * currently used in ARMv8M ports. */ +#ifndef configENABLE_MPU + #define configENABLE_MPU 0 +#endif + +/* Set configENABLE_FPU to 1 to enable FPU support and 0 to disable it. This is + * currently used in ARMv8M ports. */ +#ifndef configENABLE_FPU + #define configENABLE_FPU 1 +#endif + +/* Set configENABLE_TRUSTZONE to 1 enable TrustZone support and 0 to disable it. + * This is currently used in ARMv8M ports. */ +#ifndef configENABLE_TRUSTZONE + #define configENABLE_TRUSTZONE 1 +#endif + +/* Set configRUN_FREERTOS_SECURE_ONLY to 1 to run the FreeRTOS ARMv8M port on + * the Secure Side only. */ +#ifndef configRUN_FREERTOS_SECURE_ONLY + #define configRUN_FREERTOS_SECURE_ONLY 0 +#endif + +#ifndef configRUN_ADDITIONAL_TESTS + #define configRUN_ADDITIONAL_TESTS 0 +#endif + + +/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using + * dynamically allocated RAM, in which case when any task is deleted it is known + * that both the task's stack and TCB need to be freed. Sometimes the + * FreeRTOSConfig.h settings only allow a task to be created using statically + * allocated RAM, in which case when any task is deleted it is known that neither + * the task's stack or TCB should be freed. Sometimes the FreeRTOSConfig.h + * settings allow a task to be created using either statically or dynamically + * allocated RAM, in which case a member of the TCB is used to record whether the + * stack and/or TCB were allocated statically or dynamically, so when a task is + * deleted the RAM that was allocated dynamically is freed again and no attempt is + * made to free the RAM that was allocated statically. + * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is only true if it is possible for a + * task to be created using either statically or dynamically allocated RAM. Note + * that if portUSING_MPU_WRAPPERS is 1 then a protected task can be created with + * a statically allocated stack and a dynamically allocated TCB. + * + * The following table lists various combinations of portUSING_MPU_WRAPPERS, + * configSUPPORT_DYNAMIC_ALLOCATION and configSUPPORT_STATIC_ALLOCATION and + * when it is possible to have both static and dynamic allocation: + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + * | MPU | Dynamic | Static | Available Functions | Possible Allocations | Both Dynamic and | Need Free | + * | | | | | | Static Possible | | + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + * | 0 | 0 | 1 | xTaskCreateStatic | TCB - Static, Stack - Static | No | No | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 0 | 1 | 0 | xTaskCreate | TCB - Dynamic, Stack - Dynamic | No | Yes | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 0 | 1 | 1 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateStatic | 2. TCB - Static, Stack - Static | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 0 | 1 | xTaskCreateStatic, | TCB - Static, Stack - Static | No | No | + * | | | | xTaskCreateRestrictedStatic | | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 1 | 0 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateRestricted | 2. TCB - Dynamic, Stack - Static | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 1 | 1 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateStatic, | 2. TCB - Dynamic, Stack - Static | | | + * | | | | xTaskCreateRestricted, | 3. TCB - Static, Stack - Static | | | + * | | | | xTaskCreateRestrictedStatic | | | | + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + */ +#define tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE \ + ( ( ( portUSING_MPU_WRAPPERS == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) || \ + ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) ) + +/* + * In line with software engineering best practice, FreeRTOS implements a strict + * data hiding policy, so the real structures used by FreeRTOS to maintain the + * state of tasks, queues, semaphores, etc. are not accessible to the application + * code. However, if the application writer wants to statically allocate such + * an object then the size of the object needs to be known. Dummy structures + * that are guaranteed to have the same size and alignment requirements of the + * real objects are used for this purpose. The dummy list and list item + * structures below are used for inclusion in such a dummy structure. + */ +struct xSTATIC_LIST_ITEM +{ + #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + TickType_t xDummy2; + void * pvDummy3[ 4 ]; + #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy4; + #endif +}; +typedef struct xSTATIC_LIST_ITEM StaticListItem_t; + +/* See the comments above the struct xSTATIC_LIST_ITEM definition. */ +struct xSTATIC_MINI_LIST_ITEM +{ + #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + TickType_t xDummy2; + void * pvDummy3[ 2 ]; +}; +typedef struct xSTATIC_MINI_LIST_ITEM StaticMiniListItem_t; + +/* See the comments above the struct xSTATIC_LIST_ITEM definition. */ +typedef struct xSTATIC_LIST +{ + #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + UBaseType_t uxDummy2; + void * pvDummy3; + StaticMiniListItem_t xDummy4; + #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy5; + #endif +} StaticList_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the Task structure used internally by + * FreeRTOS is not accessible to application code. However, if the application + * writer wants to statically allocate the memory required to create a task then + * the size of the task object needs to be known. The StaticTask_t structure + * below is provided for this purpose. Its sizes and alignment requirements are + * guaranteed to match those of the genuine structure, no matter which + * architecture is being used, and no matter how the values in FreeRTOSConfig.h + * are set. Its contents are somewhat obfuscated in the hope users will + * recognise that it would be unwise to make direct use of the structure members. + */ +typedef struct xSTATIC_TCB +{ + void * pxDummy1; + #if ( portUSING_MPU_WRAPPERS == 1 ) + xMPU_SETTINGS xDummy2; + #endif + StaticListItem_t xDummy3[ 2 ]; + UBaseType_t uxDummy5; + void * pxDummy6; + uint8_t ucDummy7[ configMAX_TASK_NAME_LEN ]; + #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) + void * pxDummy8; + #endif + #if ( portCRITICAL_NESTING_IN_TCB == 1 ) + UBaseType_t uxDummy9; + #endif + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy10[ 2 ]; + #endif + #if ( configUSE_MUTEXES == 1 ) + UBaseType_t uxDummy12[ 2 ]; + #endif + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + void * pxDummy14; + #endif + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 ) + void * pvDummy15[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ]; + #endif + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + configRUN_TIME_COUNTER_TYPE ulDummy16; + #endif + #if ( configUSE_NEWLIB_REENTRANT == 1 ) + struct _reent xDummy17; + #endif + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + uint32_t ulDummy18[ configTASK_NOTIFICATION_ARRAY_ENTRIES ]; + uint8_t ucDummy19[ configTASK_NOTIFICATION_ARRAY_ENTRIES ]; + #endif + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) + uint8_t uxDummy20; + #endif + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + uint8_t ucDummy21; + #endif + #if ( configUSE_POSIX_ERRNO == 1 ) + int iDummy22; + #endif +} StaticTask_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the Queue structure used internally by + * FreeRTOS is not accessible to application code. However, if the application + * writer wants to statically allocate the memory required to create a queue + * then the size of the queue object needs to be known. The StaticQueue_t + * structure below is provided for this purpose. Its sizes and alignment + * requirements are guaranteed to match those of the genuine structure, no + * matter which architecture is being used, and no matter how the values in + * FreeRTOSConfig.h are set. Its contents are somewhat obfuscated in the hope + * users will recognise that it would be unwise to make direct use of the + * structure members. + */ +typedef struct xSTATIC_QUEUE +{ + void * pvDummy1[ 3 ]; + + union + { + void * pvDummy2; + UBaseType_t uxDummy2; + } u; + + StaticList_t xDummy3[ 2 ]; + UBaseType_t uxDummy4[ 3 ]; + uint8_t ucDummy5[ 2 ]; + + #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucDummy6; + #endif + + #if ( configUSE_QUEUE_SETS == 1 ) + void * pvDummy7; + #endif + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy8; + uint8_t ucDummy9; + #endif +} StaticQueue_t; +typedef StaticQueue_t StaticSemaphore_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the event group structure used + * internally by FreeRTOS is not accessible to application code. However, if + * the application writer wants to statically allocate the memory required to + * create an event group then the size of the event group object needs to be + * know. The StaticEventGroup_t structure below is provided for this purpose. + * Its sizes and alignment requirements are guaranteed to match those of the + * genuine structure, no matter which architecture is being used, and no matter + * how the values in FreeRTOSConfig.h are set. Its contents are somewhat + * obfuscated in the hope users will recognise that it would be unwise to make + * direct use of the structure members. + */ +typedef struct xSTATIC_EVENT_GROUP +{ + TickType_t xDummy1; + StaticList_t xDummy2; + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy3; + #endif + + #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucDummy4; + #endif +} StaticEventGroup_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the software timer structure used + * internally by FreeRTOS is not accessible to application code. However, if + * the application writer wants to statically allocate the memory required to + * create a software timer then the size of the queue object needs to be known. + * The StaticTimer_t structure below is provided for this purpose. Its sizes + * and alignment requirements are guaranteed to match those of the genuine + * structure, no matter which architecture is being used, and no matter how the + * values in FreeRTOSConfig.h are set. Its contents are somewhat obfuscated in + * the hope users will recognise that it would be unwise to make direct use of + * the structure members. + */ +typedef struct xSTATIC_TIMER +{ + void * pvDummy1; + StaticListItem_t xDummy2; + TickType_t xDummy3; + void * pvDummy5; + TaskFunction_t pvDummy6; + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy7; + #endif + uint8_t ucDummy8; +} StaticTimer_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the stream buffer structure used + * internally by FreeRTOS is not accessible to application code. However, if + * the application writer wants to statically allocate the memory required to + * create a stream buffer then the size of the stream buffer object needs to be + * known. The StaticStreamBuffer_t structure below is provided for this + * purpose. Its size and alignment requirements are guaranteed to match those + * of the genuine structure, no matter which architecture is being used, and + * no matter how the values in FreeRTOSConfig.h are set. Its contents are + * somewhat obfuscated in the hope users will recognise that it would be unwise + * to make direct use of the structure members. + */ +typedef struct xSTATIC_STREAM_BUFFER +{ + size_t uxDummy1[ 4 ]; + void * pvDummy2[ 3 ]; + uint8_t ucDummy3; + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy4; + #endif +} StaticStreamBuffer_t; + +/* Message buffers are built on stream buffers. */ +typedef StaticStreamBuffer_t StaticMessageBuffer_t; + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* INC_FREERTOS_H */ diff --git a/hw-libs/freertos/include/StackMacros.h b/hw-libs/freertos/include/StackMacros.h new file mode 100644 index 000000000..6ddeb3a95 --- /dev/null +++ b/hw-libs/freertos/include/StackMacros.h @@ -0,0 +1,34 @@ +/* + * FreeRTOS Kernel V10.4.6 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef _MSC_VER /* Visual Studio doesn't support #warning. */ + #warning The name of this file has changed to stack_macros.h. Please update your code accordingly. This source file (which has the original name) will be removed in future released. +#endif + +#include "stack_macros.h" diff --git a/hw-libs/freertos/include/atomic.h b/hw-libs/freertos/include/atomic.h new file mode 100644 index 000000000..8d7c1076f --- /dev/null +++ b/hw-libs/freertos/include/atomic.h @@ -0,0 +1,419 @@ +/* + * FreeRTOS Kernel V10.4.6 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/** + * @file atomic.h + * @brief FreeRTOS atomic operation support. + * + * This file implements atomic functions by disabling interrupts globally. + * Implementations with architecture specific atomic instructions can be + * provided under each compiler directory. + */ + +#ifndef ATOMIC_H +#define ATOMIC_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include atomic.h" +#endif + +/* Standard includes. */ +#include + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* + * Port specific definitions -- entering/exiting critical section. + * Refer template -- ./lib/FreeRTOS/portable/Compiler/Arch/portmacro.h + * + * Every call to ATOMIC_EXIT_CRITICAL() must be closely paired with + * ATOMIC_ENTER_CRITICAL(). + * + */ +#if defined( portSET_INTERRUPT_MASK_FROM_ISR ) + +/* Nested interrupt scheme is supported in this port. */ + #define ATOMIC_ENTER_CRITICAL() \ + UBaseType_t uxCriticalSectionType = portSET_INTERRUPT_MASK_FROM_ISR() + + #define ATOMIC_EXIT_CRITICAL() \ + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxCriticalSectionType ) + +#else + +/* Nested interrupt scheme is NOT supported in this port. */ + #define ATOMIC_ENTER_CRITICAL() portENTER_CRITICAL() + #define ATOMIC_EXIT_CRITICAL() portEXIT_CRITICAL() + +#endif /* portSET_INTERRUPT_MASK_FROM_ISR() */ + +/* + * Port specific definition -- "always inline". + * Inline is compiler specific, and may not always get inlined depending on your + * optimization level. Also, inline is considered as performance optimization + * for atomic. Thus, if portFORCE_INLINE is not provided by portmacro.h, + * instead of resulting error, simply define it away. + */ +#ifndef portFORCE_INLINE + #define portFORCE_INLINE +#endif + +#define ATOMIC_COMPARE_AND_SWAP_SUCCESS 0x1U /**< Compare and swap succeeded, swapped. */ +#define ATOMIC_COMPARE_AND_SWAP_FAILURE 0x0U /**< Compare and swap failed, did not swap. */ + +/*----------------------------- Swap && CAS ------------------------------*/ + +/** + * Atomic compare-and-swap + * + * @brief Performs an atomic compare-and-swap operation on the specified values. + * + * @param[in, out] pulDestination Pointer to memory location from where value is + * to be loaded and checked. + * @param[in] ulExchange If condition meets, write this value to memory. + * @param[in] ulComparand Swap condition. + * + * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped. + * + * @note This function only swaps *pulDestination with ulExchange, if previous + * *pulDestination value equals ulComparand. + */ +static portFORCE_INLINE uint32_t Atomic_CompareAndSwap_u32( uint32_t volatile * pulDestination, + uint32_t ulExchange, + uint32_t ulComparand ) +{ + uint32_t ulReturnValue; + + ATOMIC_ENTER_CRITICAL(); + { + if( *pulDestination == ulComparand ) + { + *pulDestination = ulExchange; + ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS; + } + else + { + ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE; + } + } + ATOMIC_EXIT_CRITICAL(); + + return ulReturnValue; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic swap (pointers) + * + * @brief Atomically sets the address pointed to by *ppvDestination to the value + * of *pvExchange. + * + * @param[in, out] ppvDestination Pointer to memory location from where a pointer + * value is to be loaded and written back to. + * @param[in] pvExchange Pointer value to be written to *ppvDestination. + * + * @return The initial value of *ppvDestination. + */ +static portFORCE_INLINE void * Atomic_SwapPointers_p32( void * volatile * ppvDestination, + void * pvExchange ) +{ + void * pReturnValue; + + ATOMIC_ENTER_CRITICAL(); + { + pReturnValue = *ppvDestination; + *ppvDestination = pvExchange; + } + ATOMIC_EXIT_CRITICAL(); + + return pReturnValue; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic compare-and-swap (pointers) + * + * @brief Performs an atomic compare-and-swap operation on the specified pointer + * values. + * + * @param[in, out] ppvDestination Pointer to memory location from where a pointer + * value is to be loaded and checked. + * @param[in] pvExchange If condition meets, write this value to memory. + * @param[in] pvComparand Swap condition. + * + * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped. + * + * @note This function only swaps *ppvDestination with pvExchange, if previous + * *ppvDestination value equals pvComparand. + */ +static portFORCE_INLINE uint32_t Atomic_CompareAndSwapPointers_p32( void * volatile * ppvDestination, + void * pvExchange, + void * pvComparand ) +{ + uint32_t ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE; + + ATOMIC_ENTER_CRITICAL(); + { + if( *ppvDestination == pvComparand ) + { + *ppvDestination = pvExchange; + ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS; + } + } + ATOMIC_EXIT_CRITICAL(); + + return ulReturnValue; +} + + +/*----------------------------- Arithmetic ------------------------------*/ + +/** + * Atomic add + * + * @brief Atomically adds count to the value of the specified pointer points to. + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * @param[in] ulCount Value to be added to *pulAddend. + * + * @return previous *pulAddend value. + */ +static portFORCE_INLINE uint32_t Atomic_Add_u32( uint32_t volatile * pulAddend, + uint32_t ulCount ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend += ulCount; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic subtract + * + * @brief Atomically subtracts count from the value of the specified pointer + * pointers to. + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * @param[in] ulCount Value to be subtract from *pulAddend. + * + * @return previous *pulAddend value. + */ +static portFORCE_INLINE uint32_t Atomic_Subtract_u32( uint32_t volatile * pulAddend, + uint32_t ulCount ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend -= ulCount; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic increment + * + * @brief Atomically increments the value of the specified pointer points to. + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * + * @return *pulAddend value before increment. + */ +static portFORCE_INLINE uint32_t Atomic_Increment_u32( uint32_t volatile * pulAddend ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend += 1; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic decrement + * + * @brief Atomically decrements the value of the specified pointer points to + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * + * @return *pulAddend value before decrement. + */ +static portFORCE_INLINE uint32_t Atomic_Decrement_u32( uint32_t volatile * pulAddend ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend -= 1; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} + +/*----------------------------- Bitwise Logical ------------------------------*/ + +/** + * Atomic OR + * + * @brief Performs an atomic OR operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be ORed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_OR_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination |= ulValue; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic AND + * + * @brief Performs an atomic AND operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be ANDed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_AND_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination &= ulValue; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic NAND + * + * @brief Performs an atomic NAND operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be NANDed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_NAND_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination = ~( ulCurrent & ulValue ); + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic XOR + * + * @brief Performs an atomic XOR operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be XORed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_XOR_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination ^= ulValue; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* ATOMIC_H */ diff --git a/hw-libs/freertos/include/croutine.h b/hw-libs/freertos/include/croutine.h new file mode 100644 index 000000000..51bdd4f3d --- /dev/null +++ b/hw-libs/freertos/include/croutine.h @@ -0,0 +1,753 @@ +/* + * FreeRTOS Kernel V10.4.6 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef CO_ROUTINE_H +#define CO_ROUTINE_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include croutine.h" +#endif + +#include "list.h" + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* Used to hide the implementation of the co-routine control block. The + * control block structure however has to be included in the header due to + * the macro implementation of the co-routine functionality. */ +typedef void * CoRoutineHandle_t; + +/* Defines the prototype to which co-routine functions must conform. */ +typedef void (* crCOROUTINE_CODE)( CoRoutineHandle_t, + UBaseType_t ); + +typedef struct corCoRoutineControlBlock +{ + crCOROUTINE_CODE pxCoRoutineFunction; + ListItem_t xGenericListItem; /*< List item used to place the CRCB in ready and blocked queues. */ + ListItem_t xEventListItem; /*< List item used to place the CRCB in event lists. */ + UBaseType_t uxPriority; /*< The priority of the co-routine in relation to other co-routines. */ + UBaseType_t uxIndex; /*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */ + uint16_t uxState; /*< Used internally by the co-routine implementation. */ +} CRCB_t; /* Co-routine control block. Note must be identical in size down to uxPriority with TCB_t. */ + +/** + * croutine. h + * @code{c} + * BaseType_t xCoRoutineCreate( + * crCOROUTINE_CODE pxCoRoutineCode, + * UBaseType_t uxPriority, + * UBaseType_t uxIndex + * ); + * @endcode + * + * Create a new co-routine and add it to the list of co-routines that are + * ready to run. + * + * @param pxCoRoutineCode Pointer to the co-routine function. Co-routine + * functions require special syntax - see the co-routine section of the WEB + * documentation for more information. + * + * @param uxPriority The priority with respect to other co-routines at which + * the co-routine will run. + * + * @param uxIndex Used to distinguish between different co-routines that + * execute the same function. See the example below and the co-routine section + * of the WEB documentation for further information. + * + * @return pdPASS if the co-routine was successfully created and added to a ready + * list, otherwise an error code defined with ProjDefs.h. + * + * Example usage: + * @code{c} + * // Co-routine to be created. + * void vFlashCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex ) + * { + * // Variables in co-routines must be declared static if they must maintain value across a blocking call. + * // This may not be necessary for const variables. + * static const char cLedToFlash[ 2 ] = { 5, 6 }; + * static const TickType_t uxFlashRates[ 2 ] = { 200, 400 }; + * + * // Must start every co-routine with a call to crSTART(); + * crSTART( xHandle ); + * + * for( ;; ) + * { + * // This co-routine just delays for a fixed period, then toggles + * // an LED. Two co-routines are created using this function, so + * // the uxIndex parameter is used to tell the co-routine which + * // LED to flash and how int32_t to delay. This assumes xQueue has + * // already been created. + * vParTestToggleLED( cLedToFlash[ uxIndex ] ); + * crDELAY( xHandle, uxFlashRates[ uxIndex ] ); + * } + * + * // Must end every co-routine with a call to crEND(); + * crEND(); + * } + * + * // Function that creates two co-routines. + * void vOtherFunction( void ) + * { + * uint8_t ucParameterToPass; + * TaskHandle_t xHandle; + * + * // Create two co-routines at priority 0. The first is given index 0 + * // so (from the code above) toggles LED 5 every 200 ticks. The second + * // is given index 1 so toggles LED 6 every 400 ticks. + * for( uxIndex = 0; uxIndex < 2; uxIndex++ ) + * { + * xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex ); + * } + * } + * @endcode + * \defgroup xCoRoutineCreate xCoRoutineCreate + * \ingroup Tasks + */ +BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, + UBaseType_t uxPriority, + UBaseType_t uxIndex ); + + +/** + * croutine. h + * @code{c} + * void vCoRoutineSchedule( void ); + * @endcode + * + * Run a co-routine. + * + * vCoRoutineSchedule() executes the highest priority co-routine that is able + * to run. The co-routine will execute until it either blocks, yields or is + * preempted by a task. Co-routines execute cooperatively so one + * co-routine cannot be preempted by another, but can be preempted by a task. + * + * If an application comprises of both tasks and co-routines then + * vCoRoutineSchedule should be called from the idle task (in an idle task + * hook). + * + * Example usage: + * @code{c} + * // This idle task hook will schedule a co-routine each time it is called. + * // The rest of the idle task will execute between co-routine calls. + * void vApplicationIdleHook( void ) + * { + * vCoRoutineSchedule(); + * } + * + * // Alternatively, if you do not require any other part of the idle task to + * // execute, the idle task hook can call vCoRoutineSchedule() within an + * // infinite loop. + * void vApplicationIdleHook( void ) + * { + * for( ;; ) + * { + * vCoRoutineSchedule(); + * } + * } + * @endcode + * \defgroup vCoRoutineSchedule vCoRoutineSchedule + * \ingroup Tasks + */ +void vCoRoutineSchedule( void ); + +/** + * croutine. h + * @code{c} + * crSTART( CoRoutineHandle_t xHandle ); + * @endcode + * + * This macro MUST always be called at the start of a co-routine function. + * + * Example usage: + * @code{c} + * // Co-routine to be created. + * void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex ) + * { + * // Variables in co-routines must be declared static if they must maintain value across a blocking call. + * static int32_t ulAVariable; + * + * // Must start every co-routine with a call to crSTART(); + * crSTART( xHandle ); + * + * for( ;; ) + * { + * // Co-routine functionality goes here. + * } + * + * // Must end every co-routine with a call to crEND(); + * crEND(); + * } + * @endcode + * \defgroup crSTART crSTART + * \ingroup Tasks + */ +#define crSTART( pxCRCB ) \ + switch( ( ( CRCB_t * ) ( pxCRCB ) )->uxState ) { \ + case 0: + +/** + * croutine. h + * @code{c} + * crEND(); + * @endcode + * + * This macro MUST always be called at the end of a co-routine function. + * + * Example usage: + * @code{c} + * // Co-routine to be created. + * void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex ) + * { + * // Variables in co-routines must be declared static if they must maintain value across a blocking call. + * static int32_t ulAVariable; + * + * // Must start every co-routine with a call to crSTART(); + * crSTART( xHandle ); + * + * for( ;; ) + * { + * // Co-routine functionality goes here. + * } + * + * // Must end every co-routine with a call to crEND(); + * crEND(); + * } + * @endcode + * \defgroup crSTART crSTART + * \ingroup Tasks + */ +#define crEND() } + +/* + * These macros are intended for internal use by the co-routine implementation + * only. The macros should not be used directly by application writers. + */ +#define crSET_STATE0( xHandle ) \ + ( ( CRCB_t * ) ( xHandle ) )->uxState = ( __LINE__ * 2 ); return; \ + case ( __LINE__ * 2 ): +#define crSET_STATE1( xHandle ) \ + ( ( CRCB_t * ) ( xHandle ) )->uxState = ( ( __LINE__ * 2 ) + 1 ); return; \ + case ( ( __LINE__ * 2 ) + 1 ): + +/** + * croutine. h + * @code{c} + * crDELAY( CoRoutineHandle_t xHandle, TickType_t xTicksToDelay ); + * @endcode + * + * Delay a co-routine for a fixed period of time. + * + * crDELAY can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * @param xHandle The handle of the co-routine to delay. This is the xHandle + * parameter of the co-routine function. + * + * @param xTickToDelay The number of ticks that the co-routine should delay + * for. The actual amount of time this equates to is defined by + * configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant portTICK_PERIOD_MS + * can be used to convert ticks to milliseconds. + * + * Example usage: + * @code{c} + * // Co-routine to be created. + * void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex ) + * { + * // Variables in co-routines must be declared static if they must maintain value across a blocking call. + * // This may not be necessary for const variables. + * // We are to delay for 200ms. + * static const xTickType xDelayTime = 200 / portTICK_PERIOD_MS; + * + * // Must start every co-routine with a call to crSTART(); + * crSTART( xHandle ); + * + * for( ;; ) + * { + * // Delay for 200ms. + * crDELAY( xHandle, xDelayTime ); + * + * // Do something here. + * } + * + * // Must end every co-routine with a call to crEND(); + * crEND(); + * } + * @endcode + * \defgroup crDELAY crDELAY + * \ingroup Tasks + */ +#define crDELAY( xHandle, xTicksToDelay ) \ + if( ( xTicksToDelay ) > 0 ) \ + { \ + vCoRoutineAddToDelayedList( ( xTicksToDelay ), NULL ); \ + } \ + crSET_STATE0( ( xHandle ) ); + +/** + * @code{c} + * crQUEUE_SEND( + * CoRoutineHandle_t xHandle, + * QueueHandle_t pxQueue, + * void *pvItemToQueue, + * TickType_t xTicksToWait, + * BaseType_t *pxResult + * ) + * @endcode + * + * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine + * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. + * + * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas + * xQueueSend() and xQueueReceive() can only be used from tasks. + * + * crQUEUE_SEND can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xHandle The handle of the calling co-routine. This is the xHandle + * parameter of the co-routine function. + * + * @param pxQueue The handle of the queue on which the data will be posted. + * The handle is obtained as the return value when the queue is created using + * the xQueueCreate() API function. + * + * @param pvItemToQueue A pointer to the data being posted onto the queue. + * The number of bytes of each queued item is specified when the queue is + * created. This number of bytes is copied from pvItemToQueue into the queue + * itself. + * + * @param xTickToDelay The number of ticks that the co-routine should block + * to wait for space to become available on the queue, should space not be + * available immediately. The actual amount of time this equates to is defined + * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant + * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see example + * below). + * + * @param pxResult The variable pointed to by pxResult will be set to pdPASS if + * data was successfully posted onto the queue, otherwise it will be set to an + * error defined within ProjDefs.h. + * + * Example usage: + * @code{c} + * // Co-routine function that blocks for a fixed period then posts a number onto + * // a queue. + * static void prvCoRoutineFlashTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex ) + * { + * // Variables in co-routines must be declared static if they must maintain value across a blocking call. + * static BaseType_t xNumberToPost = 0; + * static BaseType_t xResult; + * + * // Co-routines must begin with a call to crSTART(). + * crSTART( xHandle ); + * + * for( ;; ) + * { + * // This assumes the queue has already been created. + * crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult ); + * + * if( xResult != pdPASS ) + * { + * // The message was not posted! + * } + * + * // Increment the number to be posted onto the queue. + * xNumberToPost++; + * + * // Delay for 100 ticks. + * crDELAY( xHandle, 100 ); + * } + * + * // Co-routines must end with a call to crEND(). + * crEND(); + * } + * @endcode + * \defgroup crQUEUE_SEND crQUEUE_SEND + * \ingroup Tasks + */ +#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult ) \ + { \ + *( pxResult ) = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), ( xTicksToWait ) ); \ + if( *( pxResult ) == errQUEUE_BLOCKED ) \ + { \ + crSET_STATE0( ( xHandle ) ); \ + *pxResult = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), 0 ); \ + } \ + if( *pxResult == errQUEUE_YIELD ) \ + { \ + crSET_STATE1( ( xHandle ) ); \ + *pxResult = pdPASS; \ + } \ + } + +/** + * croutine. h + * @code{c} + * crQUEUE_RECEIVE( + * CoRoutineHandle_t xHandle, + * QueueHandle_t pxQueue, + * void *pvBuffer, + * TickType_t xTicksToWait, + * BaseType_t *pxResult + * ) + * @endcode + * + * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine + * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. + * + * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas + * xQueueSend() and xQueueReceive() can only be used from tasks. + * + * crQUEUE_RECEIVE can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xHandle The handle of the calling co-routine. This is the xHandle + * parameter of the co-routine function. + * + * @param pxQueue The handle of the queue from which the data will be received. + * The handle is obtained as the return value when the queue is created using + * the xQueueCreate() API function. + * + * @param pvBuffer The buffer into which the received item is to be copied. + * The number of bytes of each queued item is specified when the queue is + * created. This number of bytes is copied into pvBuffer. + * + * @param xTickToDelay The number of ticks that the co-routine should block + * to wait for data to become available from the queue, should data not be + * available immediately. The actual amount of time this equates to is defined + * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant + * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see the + * crQUEUE_SEND example). + * + * @param pxResult The variable pointed to by pxResult will be set to pdPASS if + * data was successfully retrieved from the queue, otherwise it will be set to + * an error code as defined within ProjDefs.h. + * + * Example usage: + * @code{c} + * // A co-routine receives the number of an LED to flash from a queue. It + * // blocks on the queue until the number is received. + * static void prvCoRoutineFlashWorkTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex ) + * { + * // Variables in co-routines must be declared static if they must maintain value across a blocking call. + * static BaseType_t xResult; + * static UBaseType_t uxLEDToFlash; + * + * // All co-routines must start with a call to crSTART(). + * crSTART( xHandle ); + * + * for( ;; ) + * { + * // Wait for data to become available on the queue. + * crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult ); + * + * if( xResult == pdPASS ) + * { + * // We received the LED to flash - flash it! + * vParTestToggleLED( uxLEDToFlash ); + * } + * } + * + * crEND(); + * } + * @endcode + * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE + * \ingroup Tasks + */ +#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult ) \ + { \ + *( pxResult ) = xQueueCRReceive( ( pxQueue ), ( pvBuffer ), ( xTicksToWait ) ); \ + if( *( pxResult ) == errQUEUE_BLOCKED ) \ + { \ + crSET_STATE0( ( xHandle ) ); \ + *( pxResult ) = xQueueCRReceive( ( pxQueue ), ( pvBuffer ), 0 ); \ + } \ + if( *( pxResult ) == errQUEUE_YIELD ) \ + { \ + crSET_STATE1( ( xHandle ) ); \ + *( pxResult ) = pdPASS; \ + } \ + } + +/** + * croutine. h + * @code{c} + * crQUEUE_SEND_FROM_ISR( + * QueueHandle_t pxQueue, + * void *pvItemToQueue, + * BaseType_t xCoRoutinePreviouslyWoken + * ) + * @endcode + * + * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the + * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() + * functions used by tasks. + * + * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to + * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and + * xQueueReceiveFromISR() can only be used to pass data between a task and and + * ISR. + * + * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue + * that is being used from within a co-routine. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto + * the same queue multiple times from a single interrupt. The first call + * should always pass in pdFALSE. Subsequent calls should pass in + * the value returned from the previous call. + * + * @return pdTRUE if a co-routine was woken by posting onto the queue. This is + * used by the ISR to determine if a context switch may be required following + * the ISR. + * + * Example usage: + * @code{c} + * // A co-routine that blocks on a queue waiting for characters to be received. + * static void vReceivingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex ) + * { + * char cRxedChar; + * BaseType_t xResult; + * + * // All co-routines must start with a call to crSTART(). + * crSTART( xHandle ); + * + * for( ;; ) + * { + * // Wait for data to become available on the queue. This assumes the + * // queue xCommsRxQueue has already been created! + * crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult ); + * + * // Was a character received? + * if( xResult == pdPASS ) + * { + * // Process the character here. + * } + * } + * + * // All co-routines must end with a call to crEND(). + * crEND(); + * } + * + * // An ISR that uses a queue to send characters received on a serial port to + * // a co-routine. + * void vUART_ISR( void ) + * { + * char cRxedChar; + * BaseType_t xCRWokenByPost = pdFALSE; + * + * // We loop around reading characters until there are none left in the UART. + * while( UART_RX_REG_NOT_EMPTY() ) + * { + * // Obtain the character from the UART. + * cRxedChar = UART_RX_REG; + * + * // Post the character onto a queue. xCRWokenByPost will be pdFALSE + * // the first time around the loop. If the post causes a co-routine + * // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE. + * // In this manner we can ensure that if more than one co-routine is + * // blocked on the queue only one is woken by this ISR no matter how + * // many characters are posted to the queue. + * xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost ); + * } + * } + * @endcode + * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR + * \ingroup Tasks + */ +#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) \ + xQueueCRSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( xCoRoutinePreviouslyWoken ) ) + + +/** + * croutine. h + * @code{c} + * crQUEUE_SEND_FROM_ISR( + * QueueHandle_t pxQueue, + * void *pvBuffer, + * BaseType_t * pxCoRoutineWoken + * ) + * @endcode + * + * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the + * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() + * functions used by tasks. + * + * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to + * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and + * xQueueReceiveFromISR() can only be used to pass data between a task and and + * ISR. + * + * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data + * from a queue that is being used from within a co-routine (a co-routine + * posted to the queue). + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvBuffer A pointer to a buffer into which the received item will be + * placed. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from the queue into + * pvBuffer. + * + * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become + * available on the queue. If crQUEUE_RECEIVE_FROM_ISR causes such a + * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise + * *pxCoRoutineWoken will remain unchanged. + * + * @return pdTRUE an item was successfully received from the queue, otherwise + * pdFALSE. + * + * Example usage: + * @code{c} + * // A co-routine that posts a character to a queue then blocks for a fixed + * // period. The character is incremented each time. + * static void vSendingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex ) + * { + * // cChar holds its value while this co-routine is blocked and must therefore + * // be declared static. + * static char cCharToTx = 'a'; + * BaseType_t xResult; + * + * // All co-routines must start with a call to crSTART(). + * crSTART( xHandle ); + * + * for( ;; ) + * { + * // Send the next character to the queue. + * crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult ); + * + * if( xResult == pdPASS ) + * { + * // The character was successfully posted to the queue. + * } + * else + * { + * // Could not post the character to the queue. + * } + * + * // Enable the UART Tx interrupt to cause an interrupt in this + * // hypothetical UART. The interrupt will obtain the character + * // from the queue and send it. + * ENABLE_RX_INTERRUPT(); + * + * // Increment to the next character then block for a fixed period. + * // cCharToTx will maintain its value across the delay as it is + * // declared static. + * cCharToTx++; + * if( cCharToTx > 'x' ) + * { + * cCharToTx = 'a'; + * } + * crDELAY( 100 ); + * } + * + * // All co-routines must end with a call to crEND(). + * crEND(); + * } + * + * // An ISR that uses a queue to receive characters to send on a UART. + * void vUART_ISR( void ) + * { + * char cCharToTx; + * BaseType_t xCRWokenByPost = pdFALSE; + * + * while( UART_TX_REG_EMPTY() ) + * { + * // Are there any characters in the queue waiting to be sent? + * // xCRWokenByPost will automatically be set to pdTRUE if a co-routine + * // is woken by the post - ensuring that only a single co-routine is + * // woken no matter how many times we go around this loop. + * if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) ) + * { + * SEND_CHARACTER( cCharToTx ); + * } + * } + * } + * @endcode + * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR + * \ingroup Tasks + */ +#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) \ + xQueueCRReceiveFromISR( ( pxQueue ), ( pvBuffer ), ( pxCoRoutineWoken ) ) + +/* + * This function is intended for internal use by the co-routine macros only. + * The macro nature of the co-routine implementation requires that the + * prototype appears here. The function should not be used by application + * writers. + * + * Removes the current co-routine from its ready list and places it in the + * appropriate delayed list. + */ +void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, + List_t * pxEventList ); + +/* + * This function is intended for internal use by the queue implementation only. + * The function should not be used by application writers. + * + * Removes the highest priority co-routine from the event list and places it in + * the pending ready list. + */ +BaseType_t xCoRoutineRemoveFromEventList( const List_t * pxEventList ); + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* CO_ROUTINE_H */ diff --git a/hw-libs/freertos/include/deprecated_definitions.h b/hw-libs/freertos/include/deprecated_definitions.h new file mode 100644 index 000000000..a83314124 --- /dev/null +++ b/hw-libs/freertos/include/deprecated_definitions.h @@ -0,0 +1,281 @@ +/* + * FreeRTOS Kernel V10.4.6 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef DEPRECATED_DEFINITIONS_H +#define DEPRECATED_DEFINITIONS_H + + +/* Each FreeRTOS port has a unique portmacro.h header file. Originally a + * pre-processor definition was used to ensure the pre-processor found the correct + * portmacro.h file for the port being used. That scheme was deprecated in favour + * of setting the compiler's include path such that it found the correct + * portmacro.h file - removing the need for the constant and allowing the + * portmacro.h file to be located anywhere in relation to the port being used. The + * definitions below remain in the code for backward compatibility only. New + * projects should not use them. */ + +#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT + #include "..\..\Source\portable\owatcom\16bitdos\pc\portmacro.h" + typedef void ( __interrupt __far * pxISR )(); +#endif + +#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT + #include "..\..\Source\portable\owatcom\16bitdos\flsh186\portmacro.h" + typedef void ( __interrupt __far * pxISR )(); +#endif + +#ifdef GCC_MEGA_AVR + #include "../portable/GCC/ATMega323/portmacro.h" +#endif + +#ifdef IAR_MEGA_AVR + #include "../portable/IAR/ATMega323/portmacro.h" +#endif + +#ifdef MPLAB_PIC24_PORT + #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h" +#endif + +#ifdef MPLAB_DSPIC_PORT + #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h" +#endif + +#ifdef MPLAB_PIC18F_PORT + #include "../../Source/portable/MPLAB/PIC18F/portmacro.h" +#endif + +#ifdef MPLAB_PIC32MX_PORT + #include "../../Source/portable/MPLAB/PIC32MX/portmacro.h" +#endif + +#ifdef _FEDPICC + #include "libFreeRTOS/Include/portmacro.h" +#endif + +#ifdef SDCC_CYGNAL + #include "../../Source/portable/SDCC/Cygnal/portmacro.h" +#endif + +#ifdef GCC_ARM7 + #include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h" +#endif + +#ifdef GCC_ARM7_ECLIPSE + #include "portmacro.h" +#endif + +#ifdef ROWLEY_LPC23xx + #include "../../Source/portable/GCC/ARM7_LPC23xx/portmacro.h" +#endif + +#ifdef IAR_MSP430 + #include "..\..\Source\portable\IAR\MSP430\portmacro.h" +#endif + +#ifdef GCC_MSP430 + #include "../../Source/portable/GCC/MSP430F449/portmacro.h" +#endif + +#ifdef ROWLEY_MSP430 + #include "../../Source/portable/Rowley/MSP430F449/portmacro.h" +#endif + +#ifdef ARM7_LPC21xx_KEIL_RVDS + #include "..\..\Source\portable\RVDS\ARM7_LPC21xx\portmacro.h" +#endif + +#ifdef SAM7_GCC + #include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h" +#endif + +#ifdef SAM7_IAR + #include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h" +#endif + +#ifdef SAM9XE_IAR + #include "..\..\Source\portable\IAR\AtmelSAM9XE\portmacro.h" +#endif + +#ifdef LPC2000_IAR + #include "..\..\Source\portable\IAR\LPC2000\portmacro.h" +#endif + +#ifdef STR71X_IAR + #include "..\..\Source\portable\IAR\STR71x\portmacro.h" +#endif + +#ifdef STR75X_IAR + #include "..\..\Source\portable\IAR\STR75x\portmacro.h" +#endif + +#ifdef STR75X_GCC + #include "..\..\Source\portable\GCC\STR75x\portmacro.h" +#endif + +#ifdef STR91X_IAR + #include "..\..\Source\portable\IAR\STR91x\portmacro.h" +#endif + +#ifdef GCC_H8S + #include "../../Source/portable/GCC/H8S2329/portmacro.h" +#endif + +#ifdef GCC_AT91FR40008 + #include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h" +#endif + +#ifdef RVDS_ARMCM3_LM3S102 + #include "../../Source/portable/RVDS/ARM_CM3/portmacro.h" +#endif + +#ifdef GCC_ARMCM3_LM3S102 + #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" +#endif + +#ifdef GCC_ARMCM3 + #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" +#endif + +#ifdef IAR_ARM_CM3 + #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" +#endif + +#ifdef IAR_ARMCM3_LM + #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" +#endif + +#ifdef HCS12_CODE_WARRIOR + #include "../../Source/portable/CodeWarrior/HCS12/portmacro.h" +#endif + +#ifdef MICROBLAZE_GCC + #include "../../Source/portable/GCC/MicroBlaze/portmacro.h" +#endif + +#ifdef TERN_EE + #include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h" +#endif + +#ifdef GCC_HCS12 + #include "../../Source/portable/GCC/HCS12/portmacro.h" +#endif + +#ifdef GCC_MCF5235 + #include "../../Source/portable/GCC/MCF5235/portmacro.h" +#endif + +#ifdef COLDFIRE_V2_GCC + #include "../../../Source/portable/GCC/ColdFire_V2/portmacro.h" +#endif + +#ifdef COLDFIRE_V2_CODEWARRIOR + #include "../../Source/portable/CodeWarrior/ColdFire_V2/portmacro.h" +#endif + +#ifdef GCC_PPC405 + #include "../../Source/portable/GCC/PPC405_Xilinx/portmacro.h" +#endif + +#ifdef GCC_PPC440 + #include "../../Source/portable/GCC/PPC440_Xilinx/portmacro.h" +#endif + +#ifdef _16FX_SOFTUNE + #include "..\..\Source\portable\Softune\MB96340\portmacro.h" +#endif + +#ifdef BCC_INDUSTRIAL_PC_PORT + +/* A short file name has to be used in place of the normal + * FreeRTOSConfig.h when using the Borland compiler. */ + #include "frconfig.h" + #include "..\portable\BCC\16BitDOS\PC\prtmacro.h" + typedef void ( __interrupt __far * pxISR )(); +#endif + +#ifdef BCC_FLASH_LITE_186_PORT + +/* A short file name has to be used in place of the normal + * FreeRTOSConfig.h when using the Borland compiler. */ + #include "frconfig.h" + #include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h" + typedef void ( __interrupt __far * pxISR )(); +#endif + +#ifdef __GNUC__ + #ifdef __AVR32_AVR32A__ + #include "portmacro.h" + #endif +#endif + +#ifdef __ICCAVR32__ + #ifdef __CORE__ + #if __CORE__ == __AVR32A__ + #include "portmacro.h" + #endif + #endif +#endif + +#ifdef __91467D + #include "portmacro.h" +#endif + +#ifdef __96340 + #include "portmacro.h" +#endif + + +#ifdef __IAR_V850ES_Fx3__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx3__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx3_L__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx2__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Hx2__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_78K0R_Kx3__ + #include "../../Source/portable/IAR/78K0R/portmacro.h" +#endif + +#ifdef __IAR_78K0R_Kx3L__ + #include "../../Source/portable/IAR/78K0R/portmacro.h" +#endif + +#endif /* DEPRECATED_DEFINITIONS_H */ diff --git a/hw-libs/freertos/include/event_groups.h b/hw-libs/freertos/include/event_groups.h new file mode 100644 index 000000000..601a29ba9 --- /dev/null +++ b/hw-libs/freertos/include/event_groups.h @@ -0,0 +1,777 @@ +/* + * FreeRTOS Kernel V10.4.6 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef EVENT_GROUPS_H +#define EVENT_GROUPS_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h" must appear in source files before "include event_groups.h" +#endif + +/* FreeRTOS includes. */ +#include "timers.h" + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/** + * An event group is a collection of bits to which an application can assign a + * meaning. For example, an application may create an event group to convey + * the status of various CAN bus related events in which bit 0 might mean "A CAN + * message has been received and is ready for processing", bit 1 might mean "The + * application has queued a message that is ready for sending onto the CAN + * network", and bit 2 might mean "It is time to send a SYNC message onto the + * CAN network" etc. A task can then test the bit values to see which events + * are active, and optionally enter the Blocked state to wait for a specified + * bit or a group of specified bits to be active. To continue the CAN bus + * example, a CAN controlling task can enter the Blocked state (and therefore + * not consume any processing time) until either bit 0, bit 1 or bit 2 are + * active, at which time the bit that was actually active would inform the task + * which action it had to take (process a received message, send a message, or + * send a SYNC). + * + * The event groups implementation contains intelligence to avoid race + * conditions that would otherwise occur were an application to use a simple + * variable for the same purpose. This is particularly important with respect + * to when a bit within an event group is to be cleared, and when bits have to + * be set and then tested atomically - as is the case where event groups are + * used to create a synchronisation point between multiple tasks (a + * 'rendezvous'). + * + * \defgroup EventGroup + */ + + + +/** + * event_groups.h + * + * Type by which event groups are referenced. For example, a call to + * xEventGroupCreate() returns an EventGroupHandle_t variable that can then + * be used as a parameter to other event group functions. + * + * \defgroup EventGroupHandle_t EventGroupHandle_t + * \ingroup EventGroup + */ +struct EventGroupDef_t; +typedef struct EventGroupDef_t * EventGroupHandle_t; + +/* + * The type that holds event bits always matches TickType_t - therefore the + * number of bits it holds is set by configUSE_16_BIT_TICKS (16 bits if set to 1, + * 32 bits if set to 0. + * + * \defgroup EventBits_t EventBits_t + * \ingroup EventGroup + */ +typedef TickType_t EventBits_t; + +/** + * event_groups.h + * @code{c} + * EventGroupHandle_t xEventGroupCreate( void ); + * @endcode + * + * Create a new event group. + * + * Internally, within the FreeRTOS implementation, event groups use a [small] + * block of memory, in which the event group's structure is stored. If an event + * groups is created using xEventGroupCreate() then the required memory is + * automatically dynamically allocated inside the xEventGroupCreate() function. + * (see https://www.FreeRTOS.org/a00111.html). If an event group is created + * using xEventGroupCreateStatic() then the application writer must instead + * provide the memory that will get used by the event group. + * xEventGroupCreateStatic() therefore allows an event group to be created + * without using any dynamic memory allocation. + * + * Although event groups are not related to ticks, for internal implementation + * reasons the number of bits available for use in an event group is dependent + * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h. If + * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit + * 0 to bit 7). If configUSE_16_BIT_TICKS is set to 0 then each event group has + * 24 usable bits (bit 0 to bit 23). The EventBits_t type is used to store + * event bits within an event group. + * + * @return If the event group was created then a handle to the event group is + * returned. If there was insufficient FreeRTOS heap available to create the + * event group then NULL is returned. See https://www.FreeRTOS.org/a00111.html + * + * Example usage: + * @code{c} + * // Declare a variable to hold the created event group. + * EventGroupHandle_t xCreatedEventGroup; + * + * // Attempt to create the event group. + * xCreatedEventGroup = xEventGroupCreate(); + * + * // Was the event group created successfully? + * if( xCreatedEventGroup == NULL ) + * { + * // The event group was not created because there was insufficient + * // FreeRTOS heap available. + * } + * else + * { + * // The event group was created. + * } + * @endcode + * \defgroup xEventGroupCreate xEventGroupCreate + * \ingroup EventGroup + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + EventGroupHandle_t xEventGroupCreate( void ) PRIVILEGED_FUNCTION; +#endif + +/** + * event_groups.h + * @code{c} + * EventGroupHandle_t xEventGroupCreateStatic( EventGroupHandle_t * pxEventGroupBuffer ); + * @endcode + * + * Create a new event group. + * + * Internally, within the FreeRTOS implementation, event groups use a [small] + * block of memory, in which the event group's structure is stored. If an event + * groups is created using xEventGroupCreate() then the required memory is + * automatically dynamically allocated inside the xEventGroupCreate() function. + * (see https://www.FreeRTOS.org/a00111.html). If an event group is created + * using xEventGroupCreateStatic() then the application writer must instead + * provide the memory that will get used by the event group. + * xEventGroupCreateStatic() therefore allows an event group to be created + * without using any dynamic memory allocation. + * + * Although event groups are not related to ticks, for internal implementation + * reasons the number of bits available for use in an event group is dependent + * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h. If + * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit + * 0 to bit 7). If configUSE_16_BIT_TICKS is set to 0 then each event group has + * 24 usable bits (bit 0 to bit 23). The EventBits_t type is used to store + * event bits within an event group. + * + * @param pxEventGroupBuffer pxEventGroupBuffer must point to a variable of type + * StaticEventGroup_t, which will be then be used to hold the event group's data + * structures, removing the need for the memory to be allocated dynamically. + * + * @return If the event group was created then a handle to the event group is + * returned. If pxEventGroupBuffer was NULL then NULL is returned. + * + * Example usage: + * @code{c} + * // StaticEventGroup_t is a publicly accessible structure that has the same + * // size and alignment requirements as the real event group structure. It is + * // provided as a mechanism for applications to know the size of the event + * // group (which is dependent on the architecture and configuration file + * // settings) without breaking the strict data hiding policy by exposing the + * // real event group internals. This StaticEventGroup_t variable is passed + * // into the xSemaphoreCreateEventGroupStatic() function and is used to store + * // the event group's data structures + * StaticEventGroup_t xEventGroupBuffer; + * + * // Create the event group without dynamically allocating any memory. + * xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer ); + * @endcode + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) PRIVILEGED_FUNCTION; +#endif + +/** + * event_groups.h + * @code{c} + * EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, + * const EventBits_t uxBitsToWaitFor, + * const BaseType_t xClearOnExit, + * const BaseType_t xWaitForAllBits, + * const TickType_t xTicksToWait ); + * @endcode + * + * [Potentially] block to wait for one or more bits to be set within a + * previously created event group. + * + * This function cannot be called from an interrupt. + * + * @param xEventGroup The event group in which the bits are being tested. The + * event group must have previously been created using a call to + * xEventGroupCreate(). + * + * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test + * inside the event group. For example, to wait for bit 0 and/or bit 2 set + * uxBitsToWaitFor to 0x05. To wait for bits 0 and/or bit 1 and/or bit 2 set + * uxBitsToWaitFor to 0x07. Etc. + * + * @param xClearOnExit If xClearOnExit is set to pdTRUE then any bits within + * uxBitsToWaitFor that are set within the event group will be cleared before + * xEventGroupWaitBits() returns if the wait condition was met (if the function + * returns for a reason other than a timeout). If xClearOnExit is set to + * pdFALSE then the bits set in the event group are not altered when the call to + * xEventGroupWaitBits() returns. + * + * @param xWaitForAllBits If xWaitForAllBits is set to pdTRUE then + * xEventGroupWaitBits() will return when either all the bits in uxBitsToWaitFor + * are set or the specified block time expires. If xWaitForAllBits is set to + * pdFALSE then xEventGroupWaitBits() will return when any one of the bits set + * in uxBitsToWaitFor is set or the specified block time expires. The block + * time is specified by the xTicksToWait parameter. + * + * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait + * for one/all (depending on the xWaitForAllBits value) of the bits specified by + * uxBitsToWaitFor to become set. + * + * @return The value of the event group at the time either the bits being waited + * for became set, or the block time expired. Test the return value to know + * which bits were set. If xEventGroupWaitBits() returned because its timeout + * expired then not all the bits being waited for will be set. If + * xEventGroupWaitBits() returned because the bits it was waiting for were set + * then the returned value is the event group value before any bits were + * automatically cleared in the case that xClearOnExit parameter was set to + * pdTRUE. + * + * Example usage: + * @code{c} + * #define BIT_0 ( 1 << 0 ) + * #define BIT_4 ( 1 << 4 ) + * + * void aFunction( EventGroupHandle_t xEventGroup ) + * { + * EventBits_t uxBits; + * const TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS; + * + * // Wait a maximum of 100ms for either bit 0 or bit 4 to be set within + * // the event group. Clear the bits before exiting. + * uxBits = xEventGroupWaitBits( + * xEventGroup, // The event group being tested. + * BIT_0 | BIT_4, // The bits within the event group to wait for. + * pdTRUE, // BIT_0 and BIT_4 should be cleared before returning. + * pdFALSE, // Don't wait for both bits, either bit will do. + * xTicksToWait ); // Wait a maximum of 100ms for either bit to be set. + * + * if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) ) + * { + * // xEventGroupWaitBits() returned because both bits were set. + * } + * else if( ( uxBits & BIT_0 ) != 0 ) + * { + * // xEventGroupWaitBits() returned because just BIT_0 was set. + * } + * else if( ( uxBits & BIT_4 ) != 0 ) + * { + * // xEventGroupWaitBits() returned because just BIT_4 was set. + * } + * else + * { + * // xEventGroupWaitBits() returned because xTicksToWait ticks passed + * // without either BIT_0 or BIT_4 becoming set. + * } + * } + * @endcode + * \defgroup xEventGroupWaitBits xEventGroupWaitBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToWaitFor, + const BaseType_t xClearOnExit, + const BaseType_t xWaitForAllBits, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + * @code{c} + * EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ); + * @endcode + * + * Clear bits within an event group. This function cannot be called from an + * interrupt. + * + * @param xEventGroup The event group in which the bits are to be cleared. + * + * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear + * in the event group. For example, to clear bit 3 only, set uxBitsToClear to + * 0x08. To clear bit 3 and bit 0 set uxBitsToClear to 0x09. + * + * @return The value of the event group before the specified bits were cleared. + * + * Example usage: + * @code{c} + * #define BIT_0 ( 1 << 0 ) + * #define BIT_4 ( 1 << 4 ) + * + * void aFunction( EventGroupHandle_t xEventGroup ) + * { + * EventBits_t uxBits; + * + * // Clear bit 0 and bit 4 in xEventGroup. + * uxBits = xEventGroupClearBits( + * xEventGroup, // The event group being updated. + * BIT_0 | BIT_4 );// The bits being cleared. + * + * if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) ) + * { + * // Both bit 0 and bit 4 were set before xEventGroupClearBits() was + * // called. Both will now be clear (not set). + * } + * else if( ( uxBits & BIT_0 ) != 0 ) + * { + * // Bit 0 was set before xEventGroupClearBits() was called. It will + * // now be clear. + * } + * else if( ( uxBits & BIT_4 ) != 0 ) + * { + * // Bit 4 was set before xEventGroupClearBits() was called. It will + * // now be clear. + * } + * else + * { + * // Neither bit 0 nor bit 4 were set in the first place. + * } + * } + * @endcode + * \defgroup xEventGroupClearBits xEventGroupClearBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + * @code{c} + * BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ); + * @endcode + * + * A version of xEventGroupClearBits() that can be called from an interrupt. + * + * Setting bits in an event group is not a deterministic operation because there + * are an unknown number of tasks that may be waiting for the bit or bits being + * set. FreeRTOS does not allow nondeterministic operations to be performed + * while interrupts are disabled, so protects event groups that are accessed + * from tasks by suspending the scheduler rather than disabling interrupts. As + * a result event groups cannot be accessed directly from an interrupt service + * routine. Therefore xEventGroupClearBitsFromISR() sends a message to the + * timer task to have the clear operation performed in the context of the timer + * task. + * + * @param xEventGroup The event group in which the bits are to be cleared. + * + * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear. + * For example, to clear bit 3 only, set uxBitsToClear to 0x08. To clear bit 3 + * and bit 0 set uxBitsToClear to 0x09. + * + * @return If the request to execute the function was posted successfully then + * pdPASS is returned, otherwise pdFALSE is returned. pdFALSE will be returned + * if the timer service queue was full. + * + * Example usage: + * @code{c} + * #define BIT_0 ( 1 << 0 ) + * #define BIT_4 ( 1 << 4 ) + * + * // An event group which it is assumed has already been created by a call to + * // xEventGroupCreate(). + * EventGroupHandle_t xEventGroup; + * + * void anInterruptHandler( void ) + * { + * // Clear bit 0 and bit 4 in xEventGroup. + * xResult = xEventGroupClearBitsFromISR( + * xEventGroup, // The event group being updated. + * BIT_0 | BIT_4 ); // The bits being set. + * + * if( xResult == pdPASS ) + * { + * // The message was posted successfully. + * } + * } + * @endcode + * \defgroup xEventGroupClearBitsFromISR xEventGroupClearBitsFromISR + * \ingroup EventGroup + */ +#if ( configUSE_TRACE_FACILITY == 1 ) + BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION; +#else + #define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) \ + xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ) +#endif + +/** + * event_groups.h + * @code{c} + * EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ); + * @endcode + * + * Set bits within an event group. + * This function cannot be called from an interrupt. xEventGroupSetBitsFromISR() + * is a version that can be called from an interrupt. + * + * Setting bits in an event group will automatically unblock tasks that are + * blocked waiting for the bits. + * + * @param xEventGroup The event group in which the bits are to be set. + * + * @param uxBitsToSet A bitwise value that indicates the bit or bits to set. + * For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3 + * and bit 0 set uxBitsToSet to 0x09. + * + * @return The value of the event group at the time the call to + * xEventGroupSetBits() returns. There are two reasons why the returned value + * might have the bits specified by the uxBitsToSet parameter cleared. First, + * if setting a bit results in a task that was waiting for the bit leaving the + * blocked state then it is possible the bit will be cleared automatically + * (see the xClearBitOnExit parameter of xEventGroupWaitBits()). Second, any + * unblocked (or otherwise Ready state) task that has a priority above that of + * the task that called xEventGroupSetBits() will execute and may change the + * event group value before the call to xEventGroupSetBits() returns. + * + * Example usage: + * @code{c} + * #define BIT_0 ( 1 << 0 ) + * #define BIT_4 ( 1 << 4 ) + * + * void aFunction( EventGroupHandle_t xEventGroup ) + * { + * EventBits_t uxBits; + * + * // Set bit 0 and bit 4 in xEventGroup. + * uxBits = xEventGroupSetBits( + * xEventGroup, // The event group being updated. + * BIT_0 | BIT_4 );// The bits being set. + * + * if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) ) + * { + * // Both bit 0 and bit 4 remained set when the function returned. + * } + * else if( ( uxBits & BIT_0 ) != 0 ) + * { + * // Bit 0 remained set when the function returned, but bit 4 was + * // cleared. It might be that bit 4 was cleared automatically as a + * // task that was waiting for bit 4 was removed from the Blocked + * // state. + * } + * else if( ( uxBits & BIT_4 ) != 0 ) + * { + * // Bit 4 remained set when the function returned, but bit 0 was + * // cleared. It might be that bit 0 was cleared automatically as a + * // task that was waiting for bit 0 was removed from the Blocked + * // state. + * } + * else + * { + * // Neither bit 0 nor bit 4 remained set. It might be that a task + * // was waiting for both of the bits to be set, and the bits were + * // cleared as the task left the Blocked state. + * } + * } + * @endcode + * \defgroup xEventGroupSetBits xEventGroupSetBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + * @code{c} + * BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken ); + * @endcode + * + * A version of xEventGroupSetBits() that can be called from an interrupt. + * + * Setting bits in an event group is not a deterministic operation because there + * are an unknown number of tasks that may be waiting for the bit or bits being + * set. FreeRTOS does not allow nondeterministic operations to be performed in + * interrupts or from critical sections. Therefore xEventGroupSetBitsFromISR() + * sends a message to the timer task to have the set operation performed in the + * context of the timer task - where a scheduler lock is used in place of a + * critical section. + * + * @param xEventGroup The event group in which the bits are to be set. + * + * @param uxBitsToSet A bitwise value that indicates the bit or bits to set. + * For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3 + * and bit 0 set uxBitsToSet to 0x09. + * + * @param pxHigherPriorityTaskWoken As mentioned above, calling this function + * will result in a message being sent to the timer daemon task. If the + * priority of the timer daemon task is higher than the priority of the + * currently running task (the task the interrupt interrupted) then + * *pxHigherPriorityTaskWoken will be set to pdTRUE by + * xEventGroupSetBitsFromISR(), indicating that a context switch should be + * requested before the interrupt exits. For that reason + * *pxHigherPriorityTaskWoken must be initialised to pdFALSE. See the + * example code below. + * + * @return If the request to execute the function was posted successfully then + * pdPASS is returned, otherwise pdFALSE is returned. pdFALSE will be returned + * if the timer service queue was full. + * + * Example usage: + * @code{c} + * #define BIT_0 ( 1 << 0 ) + * #define BIT_4 ( 1 << 4 ) + * + * // An event group which it is assumed has already been created by a call to + * // xEventGroupCreate(). + * EventGroupHandle_t xEventGroup; + * + * void anInterruptHandler( void ) + * { + * BaseType_t xHigherPriorityTaskWoken, xResult; + * + * // xHigherPriorityTaskWoken must be initialised to pdFALSE. + * xHigherPriorityTaskWoken = pdFALSE; + * + * // Set bit 0 and bit 4 in xEventGroup. + * xResult = xEventGroupSetBitsFromISR( + * xEventGroup, // The event group being updated. + * BIT_0 | BIT_4 // The bits being set. + * &xHigherPriorityTaskWoken ); + * + * // Was the message posted successfully? + * if( xResult == pdPASS ) + * { + * // If xHigherPriorityTaskWoken is now set to pdTRUE then a context + * // switch should be requested. The macro used is port specific and + * // will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - + * // refer to the documentation page for the port being used. + * portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + * } + * } + * @endcode + * \defgroup xEventGroupSetBitsFromISR xEventGroupSetBitsFromISR + * \ingroup EventGroup + */ +#if ( configUSE_TRACE_FACILITY == 1 ) + BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; +#else + #define xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) \ + xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ) +#endif + +/** + * event_groups.h + * @code{c} + * EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, + * const EventBits_t uxBitsToSet, + * const EventBits_t uxBitsToWaitFor, + * TickType_t xTicksToWait ); + * @endcode + * + * Atomically set bits within an event group, then wait for a combination of + * bits to be set within the same event group. This functionality is typically + * used to synchronise multiple tasks, where each task has to wait for the other + * tasks to reach a synchronisation point before proceeding. + * + * This function cannot be used from an interrupt. + * + * The function will return before its block time expires if the bits specified + * by the uxBitsToWait parameter are set, or become set within that time. In + * this case all the bits specified by uxBitsToWait will be automatically + * cleared before the function returns. + * + * @param xEventGroup The event group in which the bits are being tested. The + * event group must have previously been created using a call to + * xEventGroupCreate(). + * + * @param uxBitsToSet The bits to set in the event group before determining + * if, and possibly waiting for, all the bits specified by the uxBitsToWait + * parameter are set. + * + * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test + * inside the event group. For example, to wait for bit 0 and bit 2 set + * uxBitsToWaitFor to 0x05. To wait for bits 0 and bit 1 and bit 2 set + * uxBitsToWaitFor to 0x07. Etc. + * + * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait + * for all of the bits specified by uxBitsToWaitFor to become set. + * + * @return The value of the event group at the time either the bits being waited + * for became set, or the block time expired. Test the return value to know + * which bits were set. If xEventGroupSync() returned because its timeout + * expired then not all the bits being waited for will be set. If + * xEventGroupSync() returned because all the bits it was waiting for were + * set then the returned value is the event group value before any bits were + * automatically cleared. + * + * Example usage: + * @code{c} + * // Bits used by the three tasks. + * #define TASK_0_BIT ( 1 << 0 ) + * #define TASK_1_BIT ( 1 << 1 ) + * #define TASK_2_BIT ( 1 << 2 ) + * + * #define ALL_SYNC_BITS ( TASK_0_BIT | TASK_1_BIT | TASK_2_BIT ) + * + * // Use an event group to synchronise three tasks. It is assumed this event + * // group has already been created elsewhere. + * EventGroupHandle_t xEventBits; + * + * void vTask0( void *pvParameters ) + * { + * EventBits_t uxReturn; + * TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS; + * + * for( ;; ) + * { + * // Perform task functionality here. + * + * // Set bit 0 in the event flag to note this task has reached the + * // sync point. The other two tasks will set the other two bits defined + * // by ALL_SYNC_BITS. All three tasks have reached the synchronisation + * // point when all the ALL_SYNC_BITS are set. Wait a maximum of 100ms + * // for this to happen. + * uxReturn = xEventGroupSync( xEventBits, TASK_0_BIT, ALL_SYNC_BITS, xTicksToWait ); + * + * if( ( uxReturn & ALL_SYNC_BITS ) == ALL_SYNC_BITS ) + * { + * // All three tasks reached the synchronisation point before the call + * // to xEventGroupSync() timed out. + * } + * } + * } + * + * void vTask1( void *pvParameters ) + * { + * for( ;; ) + * { + * // Perform task functionality here. + * + * // Set bit 1 in the event flag to note this task has reached the + * // synchronisation point. The other two tasks will set the other two + * // bits defined by ALL_SYNC_BITS. All three tasks have reached the + * // synchronisation point when all the ALL_SYNC_BITS are set. Wait + * // indefinitely for this to happen. + * xEventGroupSync( xEventBits, TASK_1_BIT, ALL_SYNC_BITS, portMAX_DELAY ); + * + * // xEventGroupSync() was called with an indefinite block time, so + * // this task will only reach here if the synchronisation was made by all + * // three tasks, so there is no need to test the return value. + * } + * } + * + * void vTask2( void *pvParameters ) + * { + * for( ;; ) + * { + * // Perform task functionality here. + * + * // Set bit 2 in the event flag to note this task has reached the + * // synchronisation point. The other two tasks will set the other two + * // bits defined by ALL_SYNC_BITS. All three tasks have reached the + * // synchronisation point when all the ALL_SYNC_BITS are set. Wait + * // indefinitely for this to happen. + * xEventGroupSync( xEventBits, TASK_2_BIT, ALL_SYNC_BITS, portMAX_DELAY ); + * + * // xEventGroupSync() was called with an indefinite block time, so + * // this task will only reach here if the synchronisation was made by all + * // three tasks, so there is no need to test the return value. + * } + * } + * + * @endcode + * \defgroup xEventGroupSync xEventGroupSync + * \ingroup EventGroup + */ +EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + + +/** + * event_groups.h + * @code{c} + * EventBits_t xEventGroupGetBits( EventGroupHandle_t xEventGroup ); + * @endcode + * + * Returns the current value of the bits in an event group. This function + * cannot be used from an interrupt. + * + * @param xEventGroup The event group being queried. + * + * @return The event group bits at the time xEventGroupGetBits() was called. + * + * \defgroup xEventGroupGetBits xEventGroupGetBits + * \ingroup EventGroup + */ +#define xEventGroupGetBits( xEventGroup ) xEventGroupClearBits( xEventGroup, 0 ) + +/** + * event_groups.h + * @code{c} + * EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ); + * @endcode + * + * A version of xEventGroupGetBits() that can be called from an ISR. + * + * @param xEventGroup The event group being queried. + * + * @return The event group bits at the time xEventGroupGetBitsFromISR() was called. + * + * \defgroup xEventGroupGetBitsFromISR xEventGroupGetBitsFromISR + * \ingroup EventGroup + */ +EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + * @code{c} + * void xEventGroupDelete( EventGroupHandle_t xEventGroup ); + * @endcode + * + * Delete an event group that was previously created by a call to + * xEventGroupCreate(). Tasks that are blocked on the event group will be + * unblocked and obtain 0 as the event group's value. + * + * @param xEventGroup The event group being deleted. + */ +void vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION; + +/* For internal use only. */ +void vEventGroupSetBitsCallback( void * pvEventGroup, + const uint32_t ulBitsToSet ) PRIVILEGED_FUNCTION; +void vEventGroupClearBitsCallback( void * pvEventGroup, + const uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION; + + +#if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxEventGroupGetNumber( void * xEventGroup ) PRIVILEGED_FUNCTION; + void vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) PRIVILEGED_FUNCTION; +#endif + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* EVENT_GROUPS_H */ diff --git a/hw-libs/freertos/include/list.h b/hw-libs/freertos/include/list.h new file mode 100644 index 000000000..f866f9fd5 --- /dev/null +++ b/hw-libs/freertos/include/list.h @@ -0,0 +1,499 @@ +/* + * FreeRTOS Kernel V10.4.6 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * This is the list implementation used by the scheduler. While it is tailored + * heavily for the schedulers needs, it is also available for use by + * application code. + * + * list_ts can only store pointers to list_item_ts. Each ListItem_t contains a + * numeric value (xItemValue). Most of the time the lists are sorted in + * ascending item value order. + * + * Lists are created already containing one list item. The value of this + * item is the maximum possible that can be stored, it is therefore always at + * the end of the list and acts as a marker. The list member pxHead always + * points to this marker - even though it is at the tail of the list. This + * is because the tail contains a wrap back pointer to the true head of + * the list. + * + * In addition to it's value, each list item contains a pointer to the next + * item in the list (pxNext), a pointer to the list it is in (pxContainer) + * and a pointer to back to the object that contains it. These later two + * pointers are included for efficiency of list manipulation. There is + * effectively a two way link between the object containing the list item and + * the list item itself. + * + * + * \page ListIntroduction List Implementation + * \ingroup FreeRTOSIntro + */ + + +#ifndef LIST_H +#define LIST_H + +#ifndef INC_FREERTOS_H + #error "FreeRTOS.h must be included before list.h" +#endif + +/* + * The list structure members are modified from within interrupts, and therefore + * by rights should be declared volatile. However, they are only modified in a + * functionally atomic way (within critical sections of with the scheduler + * suspended) and are either passed by reference into a function or indexed via + * a volatile variable. Therefore, in all use cases tested so far, the volatile + * qualifier can be omitted in order to provide a moderate performance + * improvement without adversely affecting functional behaviour. The assembly + * instructions generated by the IAR, ARM and GCC compilers when the respective + * compiler's options were set for maximum optimisation has been inspected and + * deemed to be as intended. That said, as compiler technology advances, and + * especially if aggressive cross module optimisation is used (a use case that + * has not been exercised to any great extend) then it is feasible that the + * volatile qualifier will be needed for correct optimisation. It is expected + * that a compiler removing essential code because, without the volatile + * qualifier on the list structure members and with aggressive cross module + * optimisation, the compiler deemed the code unnecessary will result in + * complete and obvious failure of the scheduler. If this is ever experienced + * then the volatile qualifier can be inserted in the relevant places within the + * list structures by simply defining configLIST_VOLATILE to volatile in + * FreeRTOSConfig.h (as per the example at the bottom of this comment block). + * If configLIST_VOLATILE is not defined then the preprocessor directives below + * will simply #define configLIST_VOLATILE away completely. + * + * To use volatile list structure members then add the following line to + * FreeRTOSConfig.h (without the quotes): + * "#define configLIST_VOLATILE volatile" + */ +#ifndef configLIST_VOLATILE + #define configLIST_VOLATILE +#endif /* configSUPPORT_CROSS_MODULE_OPTIMISATION */ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* Macros that can be used to place known values within the list structures, + * then check that the known values do not get corrupted during the execution of + * the application. These may catch the list data structures being overwritten in + * memory. They will not catch data errors caused by incorrect configuration or + * use of FreeRTOS.*/ +#if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 ) + /* Define the macros to do nothing. */ + #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE + #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE + #define listFIRST_LIST_INTEGRITY_CHECK_VALUE + #define listSECOND_LIST_INTEGRITY_CHECK_VALUE + #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) + #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) + #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ) + #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ) + #define listTEST_LIST_ITEM_INTEGRITY( pxItem ) + #define listTEST_LIST_INTEGRITY( pxList ) +#else /* if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 ) */ + /* Define macros that add new members into the list structures. */ + #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE TickType_t xListItemIntegrityValue1; + #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE TickType_t xListItemIntegrityValue2; + #define listFIRST_LIST_INTEGRITY_CHECK_VALUE TickType_t xListIntegrityValue1; + #define listSECOND_LIST_INTEGRITY_CHECK_VALUE TickType_t xListIntegrityValue2; + +/* Define macros that set the new structure members to known values. */ + #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrityValue1 = pdINTEGRITY_CHECK_VALUE + #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrityValue2 = pdINTEGRITY_CHECK_VALUE + #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ) ( pxList )->xListIntegrityValue1 = pdINTEGRITY_CHECK_VALUE + #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ) ( pxList )->xListIntegrityValue2 = pdINTEGRITY_CHECK_VALUE + +/* Define macros that will assert if one of the structure members does not + * contain its expected value. */ + #define listTEST_LIST_ITEM_INTEGRITY( pxItem ) configASSERT( ( ( pxItem )->xListItemIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxItem )->xListItemIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) ) + #define listTEST_LIST_INTEGRITY( pxList ) configASSERT( ( ( pxList )->xListIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxList )->xListIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) ) +#endif /* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES */ + + +/* + * Definition of the only type of object that a list can contain. + */ +struct xLIST; +struct xLIST_ITEM +{ + listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + configLIST_VOLATILE TickType_t xItemValue; /*< The value being listed. In most cases this is used to sort the list in ascending order. */ + struct xLIST_ITEM * configLIST_VOLATILE pxNext; /*< Pointer to the next ListItem_t in the list. */ + struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; /*< Pointer to the previous ListItem_t in the list. */ + void * pvOwner; /*< Pointer to the object (normally a TCB) that contains the list item. There is therefore a two way link between the object containing the list item and the list item itself. */ + struct xLIST * configLIST_VOLATILE pxContainer; /*< Pointer to the list in which this list item is placed (if any). */ + listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ +}; +typedef struct xLIST_ITEM ListItem_t; /* For some reason lint wants this as two separate definitions. */ + +struct xMINI_LIST_ITEM +{ + listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + configLIST_VOLATILE TickType_t xItemValue; + struct xLIST_ITEM * configLIST_VOLATILE pxNext; + struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; +}; +typedef struct xMINI_LIST_ITEM MiniListItem_t; + +/* + * Definition of the type of queue used by the scheduler. + */ +typedef struct xLIST +{ + listFIRST_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + volatile UBaseType_t uxNumberOfItems; + ListItem_t * configLIST_VOLATILE pxIndex; /*< Used to walk through the list. Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */ + MiniListItem_t xListEnd; /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */ + listSECOND_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ +} List_t; + +/* + * Access macro to set the owner of a list item. The owner of a list item + * is the object (usually a TCB) that contains the list item. + * + * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER + * \ingroup LinkedList + */ +#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner ) ( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) ) + +/* + * Access macro to get the owner of a list item. The owner of a list item + * is the object (usually a TCB) that contains the list item. + * + * \page listGET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER + * \ingroup LinkedList + */ +#define listGET_LIST_ITEM_OWNER( pxListItem ) ( ( pxListItem )->pvOwner ) + +/* + * Access macro to set the value of the list item. In most cases the value is + * used to sort the list in ascending order. + * + * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listSET_LIST_ITEM_VALUE( pxListItem, xValue ) ( ( pxListItem )->xItemValue = ( xValue ) ) + +/* + * Access macro to retrieve the value of the list item. The value can + * represent anything - for example the priority of a task, or the time at + * which a task should be unblocked. + * + * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listGET_LIST_ITEM_VALUE( pxListItem ) ( ( pxListItem )->xItemValue ) + +/* + * Access macro to retrieve the value of the list item at the head of a given + * list. + * + * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext->xItemValue ) + +/* + * Return the list item at the head of the list. + * + * \page listGET_HEAD_ENTRY listGET_HEAD_ENTRY + * \ingroup LinkedList + */ +#define listGET_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext ) + +/* + * Return the next list item. + * + * \page listGET_NEXT listGET_NEXT + * \ingroup LinkedList + */ +#define listGET_NEXT( pxListItem ) ( ( pxListItem )->pxNext ) + +/* + * Return the list item that marks the end of the list + * + * \page listGET_END_MARKER listGET_END_MARKER + * \ingroup LinkedList + */ +#define listGET_END_MARKER( pxList ) ( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) ) + +/* + * Access macro to determine if a list contains any items. The macro will + * only have the value true if the list is empty. + * + * \page listLIST_IS_EMPTY listLIST_IS_EMPTY + * \ingroup LinkedList + */ +#define listLIST_IS_EMPTY( pxList ) ( ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ? pdTRUE : pdFALSE ) + +/* + * Access macro to return the number of items in the list. + */ +#define listCURRENT_LIST_LENGTH( pxList ) ( ( pxList )->uxNumberOfItems ) + +/* + * Access function to obtain the owner of the next entry in a list. + * + * The list member pxIndex is used to walk through a list. Calling + * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list + * and returns that entry's pxOwner parameter. Using multiple calls to this + * function it is therefore possible to move through every item contained in + * a list. + * + * The pxOwner parameter of a list item is a pointer to the object that owns + * the list item. In the scheduler this is normally a task control block. + * The pxOwner parameter effectively creates a two way link between the list + * item and its owner. + * + * @param pxTCB pxTCB is set to the address of the owner of the next list item. + * @param pxList The list from which the next item owner is to be returned. + * + * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY + * \ingroup LinkedList + */ +#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList ) \ + { \ + List_t * const pxConstList = ( pxList ); \ + /* Increment the index to the next item and return the item, ensuring */ \ + /* we don't return the marker used at the end of the list. */ \ + ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ + if( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) ) \ + { \ + ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ + } \ + ( pxTCB ) = ( pxConstList )->pxIndex->pvOwner; \ + } + +/* + * Version of uxListRemove() that does not return a value. Provided as a slight + * optimisation for xTaskIncrementTick() by being inline. + * + * Remove an item from a list. The list item has a pointer to the list that + * it is in, so only the list item need be passed into the function. + * + * @param uxListRemove The item to be removed. The item will remove itself from + * the list pointed to by it's pxContainer parameter. + * + * @return The number of items that remain in the list after the list item has + * been removed. + * + * \page listREMOVE_ITEM listREMOVE_ITEM + * \ingroup LinkedList + */ +#define listREMOVE_ITEM( pxItemToRemove ) \ + { \ + /* The list item knows which list it is in. Obtain the list from the list \ + * item. */ \ + List_t * const pxList = ( pxItemToRemove )->pxContainer; \ + \ + ( pxItemToRemove )->pxNext->pxPrevious = ( pxItemToRemove )->pxPrevious; \ + ( pxItemToRemove )->pxPrevious->pxNext = ( pxItemToRemove )->pxNext; \ + /* Make sure the index is left pointing to a valid item. */ \ + if( pxList->pxIndex == ( pxItemToRemove ) ) \ + { \ + pxList->pxIndex = ( pxItemToRemove )->pxPrevious; \ + } \ + \ + ( pxItemToRemove )->pxContainer = NULL; \ + ( pxList->uxNumberOfItems )--; \ + } + +/* + * Inline version of vListInsertEnd() to provide slight optimisation for + * xTaskIncrementTick(). + * + * Insert a list item into a list. The item will be inserted in a position + * such that it will be the last item within the list returned by multiple + * calls to listGET_OWNER_OF_NEXT_ENTRY. + * + * The list member pxIndex is used to walk through a list. Calling + * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list. + * Placing an item in a list using vListInsertEnd effectively places the item + * in the list position pointed to by pxIndex. This means that every other + * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before + * the pxIndex parameter again points to the item being inserted. + * + * @param pxList The list into which the item is to be inserted. + * + * @param pxNewListItem The list item to be inserted into the list. + * + * \page listINSERT_END listINSERT_END + * \ingroup LinkedList + */ +#define listINSERT_END( pxList, pxNewListItem ) \ + { \ + ListItem_t * const pxIndex = ( pxList )->pxIndex; \ + \ + /* Only effective when configASSERT() is also defined, these tests may catch \ + * the list data structures being overwritten in memory. They will not catch \ + * data errors caused by incorrect configuration or use of FreeRTOS. */ \ + listTEST_LIST_INTEGRITY( ( pxList ) ); \ + listTEST_LIST_ITEM_INTEGRITY( ( pxNewListItem ) ); \ + \ + /* Insert a new list item into ( pxList ), but rather than sort the list, \ + * makes the new list item the last item to be removed by a call to \ + * listGET_OWNER_OF_NEXT_ENTRY(). */ \ + ( pxNewListItem )->pxNext = pxIndex; \ + ( pxNewListItem )->pxPrevious = pxIndex->pxPrevious; \ + \ + pxIndex->pxPrevious->pxNext = ( pxNewListItem ); \ + pxIndex->pxPrevious = ( pxNewListItem ); \ + \ + /* Remember which list the item is in. */ \ + ( pxNewListItem )->pxContainer = ( pxList ); \ + \ + ( ( pxList )->uxNumberOfItems )++; \ + } + +/* + * Access function to obtain the owner of the first entry in a list. Lists + * are normally sorted in ascending item value order. + * + * This function returns the pxOwner member of the first item in the list. + * The pxOwner parameter of a list item is a pointer to the object that owns + * the list item. In the scheduler this is normally a task control block. + * The pxOwner parameter effectively creates a two way link between the list + * item and its owner. + * + * @param pxList The list from which the owner of the head item is to be + * returned. + * + * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY + * \ingroup LinkedList + */ +#define listGET_OWNER_OF_HEAD_ENTRY( pxList ) ( ( &( ( pxList )->xListEnd ) )->pxNext->pvOwner ) + +/* + * Check to see if a list item is within a list. The list item maintains a + * "container" pointer that points to the list it is in. All this macro does + * is check to see if the container and the list match. + * + * @param pxList The list we want to know if the list item is within. + * @param pxListItem The list item we want to know if is in the list. + * @return pdTRUE if the list item is in the list, otherwise pdFALSE. + */ +#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( ( pxListItem )->pxContainer == ( pxList ) ) ? ( pdTRUE ) : ( pdFALSE ) ) + +/* + * Return the list a list item is contained within (referenced from). + * + * @param pxListItem The list item being queried. + * @return A pointer to the List_t object that references the pxListItem + */ +#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pxContainer ) + +/* + * This provides a crude means of knowing if a list has been initialised, as + * pxList->xListEnd.xItemValue is set to portMAX_DELAY by the vListInitialise() + * function. + */ +#define listLIST_IS_INITIALISED( pxList ) ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY ) + +/* + * Must be called before a list is used! This initialises all the members + * of the list structure and inserts the xListEnd item into the list as a + * marker to the back of the list. + * + * @param pxList Pointer to the list being initialised. + * + * \page vListInitialise vListInitialise + * \ingroup LinkedList + */ +void vListInitialise( List_t * const pxList ) PRIVILEGED_FUNCTION; + +/* + * Must be called before a list item is used. This sets the list container to + * null so the item does not think that it is already contained in a list. + * + * @param pxItem Pointer to the list item being initialised. + * + * \page vListInitialiseItem vListInitialiseItem + * \ingroup LinkedList + */ +void vListInitialiseItem( ListItem_t * const pxItem ) PRIVILEGED_FUNCTION; + +/* + * Insert a list item into a list. The item will be inserted into the list in + * a position determined by its item value (ascending item value order). + * + * @param pxList The list into which the item is to be inserted. + * + * @param pxNewListItem The item that is to be placed in the list. + * + * \page vListInsert vListInsert + * \ingroup LinkedList + */ +void vListInsert( List_t * const pxList, + ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION; + +/* + * Insert a list item into a list. The item will be inserted in a position + * such that it will be the last item within the list returned by multiple + * calls to listGET_OWNER_OF_NEXT_ENTRY. + * + * The list member pxIndex is used to walk through a list. Calling + * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list. + * Placing an item in a list using vListInsertEnd effectively places the item + * in the list position pointed to by pxIndex. This means that every other + * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before + * the pxIndex parameter again points to the item being inserted. + * + * @param pxList The list into which the item is to be inserted. + * + * @param pxNewListItem The list item to be inserted into the list. + * + * \page vListInsertEnd vListInsertEnd + * \ingroup LinkedList + */ +void vListInsertEnd( List_t * const pxList, + ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION; + +/* + * Remove an item from a list. The list item has a pointer to the list that + * it is in, so only the list item need be passed into the function. + * + * @param uxListRemove The item to be removed. The item will remove itself from + * the list pointed to by it's pxContainer parameter. + * + * @return The number of items that remain in the list after the list item has + * been removed. + * + * \page uxListRemove uxListRemove + * \ingroup LinkedList + */ +UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) PRIVILEGED_FUNCTION; + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* ifndef LIST_H */ diff --git a/hw-libs/freertos/include/message_buffer.h b/hw-libs/freertos/include/message_buffer.h new file mode 100644 index 000000000..140626737 --- /dev/null +++ b/hw-libs/freertos/include/message_buffer.h @@ -0,0 +1,823 @@ +/* + * FreeRTOS Kernel V10.4.6 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/* + * Message buffers build functionality on top of FreeRTOS stream buffers. + * Whereas stream buffers are used to send a continuous stream of data from one + * task or interrupt to another, message buffers are used to send variable + * length discrete messages from one task or interrupt to another. Their + * implementation is light weight, making them particularly suited for interrupt + * to task and core to core communication scenarios. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xMessageBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xMessageBufferRead()) inside a critical section and set the receive + * timeout to 0. + * + * Message buffers hold variable length messages. To enable that, when a + * message is written to the message buffer an additional sizeof( size_t ) bytes + * are also written to store the message's length (that happens internally, with + * the API function). sizeof( size_t ) is typically 4 bytes on a 32-bit + * architecture, so writing a 10 byte message to a message buffer on a 32-bit + * architecture will actually reduce the available space in the message buffer + * by 14 bytes (10 byte are used by the message, and 4 bytes to hold the length + * of the message). + */ + +#ifndef FREERTOS_MESSAGE_BUFFER_H +#define FREERTOS_MESSAGE_BUFFER_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include message_buffer.h" +#endif + +/* Message buffers are built onto of stream buffers. */ +#include "stream_buffer.h" + +/* *INDENT-OFF* */ +#if defined( __cplusplus ) + extern "C" { +#endif +/* *INDENT-ON* */ + +/** + * Type by which message buffers are referenced. For example, a call to + * xMessageBufferCreate() returns an MessageBufferHandle_t variable that can + * then be used as a parameter to xMessageBufferSend(), xMessageBufferReceive(), + * etc. + */ +typedef void * MessageBufferHandle_t; + +/*-----------------------------------------------------------*/ + +/** + * message_buffer.h + * + * @code{c} + * MessageBufferHandle_t xMessageBufferCreate( size_t xBufferSizeBytes ); + * @endcode + * + * Creates a new message buffer using dynamically allocated memory. See + * xMessageBufferCreateStatic() for a version that uses statically allocated + * memory (memory that is allocated at compile time). + * + * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in + * FreeRTOSConfig.h for xMessageBufferCreate() to be available. + * + * @param xBufferSizeBytes The total number of bytes (not messages) the message + * buffer will be able to hold at any one time. When a message is written to + * the message buffer an additional sizeof( size_t ) bytes are also written to + * store the message's length. sizeof( size_t ) is typically 4 bytes on a + * 32-bit architecture, so on most 32-bit architectures a 10 byte message will + * take up 14 bytes of message buffer space. + * + * @return If NULL is returned, then the message buffer cannot be created + * because there is insufficient heap memory available for FreeRTOS to allocate + * the message buffer data structures and storage area. A non-NULL value being + * returned indicates that the message buffer has been created successfully - + * the returned value should be stored as the handle to the created message + * buffer. + * + * Example use: + * @code{c} + * + * void vAFunction( void ) + * { + * MessageBufferHandle_t xMessageBuffer; + * const size_t xMessageBufferSizeBytes = 100; + * + * // Create a message buffer that can hold 100 bytes. The memory used to hold + * // both the message buffer structure and the messages themselves is allocated + * // dynamically. Each message added to the buffer consumes an additional 4 + * // bytes which are used to hold the lengh of the message. + * xMessageBuffer = xMessageBufferCreate( xMessageBufferSizeBytes ); + * + * if( xMessageBuffer == NULL ) + * { + * // There was not enough heap memory space available to create the + * // message buffer. + * } + * else + * { + * // The message buffer was created successfully and can now be used. + * } + * + * @endcode + * \defgroup xMessageBufferCreate xMessageBufferCreate + * \ingroup MessageBufferManagement + */ +#define xMessageBufferCreate( xBufferSizeBytes ) \ + ( MessageBufferHandle_t ) xStreamBufferGenericCreate( xBufferSizeBytes, ( size_t ) 0, pdTRUE ) + +/** + * message_buffer.h + * + * @code{c} + * MessageBufferHandle_t xMessageBufferCreateStatic( size_t xBufferSizeBytes, + * uint8_t *pucMessageBufferStorageArea, + * StaticMessageBuffer_t *pxStaticMessageBuffer ); + * @endcode + * Creates a new message buffer using statically allocated memory. See + * xMessageBufferCreate() for a version that uses dynamically allocated memory. + * + * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the + * pucMessageBufferStorageArea parameter. When a message is written to the + * message buffer an additional sizeof( size_t ) bytes are also written to store + * the message's length. sizeof( size_t ) is typically 4 bytes on a 32-bit + * architecture, so on most 32-bit architecture a 10 byte message will take up + * 14 bytes of message buffer space. The maximum number of bytes that can be + * stored in the message buffer is actually (xBufferSizeBytes - 1). + * + * @param pucMessageBufferStorageArea Must point to a uint8_t array that is at + * least xBufferSizeBytes big. This is the array to which messages are + * copied when they are written to the message buffer. + * + * @param pxStaticMessageBuffer Must point to a variable of type + * StaticMessageBuffer_t, which will be used to hold the message buffer's data + * structure. + * + * @return If the message buffer is created successfully then a handle to the + * created message buffer is returned. If either pucMessageBufferStorageArea or + * pxStaticmessageBuffer are NULL then NULL is returned. + * + * Example use: + * @code{c} + * + * // Used to dimension the array used to hold the messages. The available space + * // will actually be one less than this, so 999. + #define STORAGE_SIZE_BYTES 1000 + * + * // Defines the memory that will actually hold the messages within the message + * // buffer. + * static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ]; + * + * // The variable used to hold the message buffer structure. + * StaticMessageBuffer_t xMessageBufferStruct; + * + * void MyFunction( void ) + * { + * MessageBufferHandle_t xMessageBuffer; + * + * xMessageBuffer = xMessageBufferCreateStatic( sizeof( ucStorageBuffer ), + * ucStorageBuffer, + * &xMessageBufferStruct ); + * + * // As neither the pucMessageBufferStorageArea or pxStaticMessageBuffer + * // parameters were NULL, xMessageBuffer will not be NULL, and can be used to + * // reference the created message buffer in other message buffer API calls. + * + * // Other code that uses the message buffer can go here. + * } + * + * @endcode + * \defgroup xMessageBufferCreateStatic xMessageBufferCreateStatic + * \ingroup MessageBufferManagement + */ +#define xMessageBufferCreateStatic( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer ) \ + ( MessageBufferHandle_t ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, 0, pdTRUE, pucMessageBufferStorageArea, pxStaticMessageBuffer ) + +/** + * message_buffer.h + * + * @code{c} + * size_t xMessageBufferSend( MessageBufferHandle_t xMessageBuffer, + * const void *pvTxData, + * size_t xDataLengthBytes, + * TickType_t xTicksToWait ); + * @endcode + * + * Sends a discrete message to the message buffer. The message can be any + * length that fits within the buffer's free space, and is copied into the + * buffer. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xMessageBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xMessageBufferRead()) inside a critical section and set the receive + * block time to 0. + * + * Use xMessageBufferSend() to write to a message buffer from a task. Use + * xMessageBufferSendFromISR() to write to a message buffer from an interrupt + * service routine (ISR). + * + * @param xMessageBuffer The handle of the message buffer to which a message is + * being sent. + * + * @param pvTxData A pointer to the message that is to be copied into the + * message buffer. + * + * @param xDataLengthBytes The length of the message. That is, the number of + * bytes to copy from pvTxData into the message buffer. When a message is + * written to the message buffer an additional sizeof( size_t ) bytes are also + * written to store the message's length. sizeof( size_t ) is typically 4 bytes + * on a 32-bit architecture, so on most 32-bit architecture setting + * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24 + * bytes (20 bytes of message data and 4 bytes to hold the message length). + * + * @param xTicksToWait The maximum amount of time the calling task should remain + * in the Blocked state to wait for enough space to become available in the + * message buffer, should the message buffer have insufficient space when + * xMessageBufferSend() is called. The calling task will never block if + * xTicksToWait is zero. The block time is specified in tick periods, so the + * absolute time it represents is dependent on the tick frequency. The macro + * pdMS_TO_TICKS() can be used to convert a time specified in milliseconds into + * a time specified in ticks. Setting xTicksToWait to portMAX_DELAY will cause + * the task to wait indefinitely (without timing out), provided + * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h. Tasks do not use any + * CPU time when they are in the Blocked state. + * + * @return The number of bytes written to the message buffer. If the call to + * xMessageBufferSend() times out before there was enough space to write the + * message into the message buffer then zero is returned. If the call did not + * time out then xDataLengthBytes is returned. + * + * Example use: + * @code{c} + * void vAFunction( MessageBufferHandle_t xMessageBuffer ) + * { + * size_t xBytesSent; + * uint8_t ucArrayToSend[] = { 0, 1, 2, 3 }; + * char *pcStringToSend = "String to send"; + * const TickType_t x100ms = pdMS_TO_TICKS( 100 ); + * + * // Send an array to the message buffer, blocking for a maximum of 100ms to + * // wait for enough space to be available in the message buffer. + * xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms ); + * + * if( xBytesSent != sizeof( ucArrayToSend ) ) + * { + * // The call to xMessageBufferSend() times out before there was enough + * // space in the buffer for the data to be written. + * } + * + * // Send the string to the message buffer. Return immediately if there is + * // not enough space in the buffer. + * xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 ); + * + * if( xBytesSent != strlen( pcStringToSend ) ) + * { + * // The string could not be added to the message buffer because there was + * // not enough free space in the buffer. + * } + * } + * @endcode + * \defgroup xMessageBufferSend xMessageBufferSend + * \ingroup MessageBufferManagement + */ +#define xMessageBufferSend( xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait ) \ + xStreamBufferSend( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait ) + +/** + * message_buffer.h + * + * @code{c} + * size_t xMessageBufferSendFromISR( MessageBufferHandle_t xMessageBuffer, + * const void *pvTxData, + * size_t xDataLengthBytes, + * BaseType_t *pxHigherPriorityTaskWoken ); + * @endcode + * + * Interrupt safe version of the API function that sends a discrete message to + * the message buffer. The message can be any length that fits within the + * buffer's free space, and is copied into the buffer. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xMessageBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xMessageBufferRead()) inside a critical section and set the receive + * block time to 0. + * + * Use xMessageBufferSend() to write to a message buffer from a task. Use + * xMessageBufferSendFromISR() to write to a message buffer from an interrupt + * service routine (ISR). + * + * @param xMessageBuffer The handle of the message buffer to which a message is + * being sent. + * + * @param pvTxData A pointer to the message that is to be copied into the + * message buffer. + * + * @param xDataLengthBytes The length of the message. That is, the number of + * bytes to copy from pvTxData into the message buffer. When a message is + * written to the message buffer an additional sizeof( size_t ) bytes are also + * written to store the message's length. sizeof( size_t ) is typically 4 bytes + * on a 32-bit architecture, so on most 32-bit architecture setting + * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24 + * bytes (20 bytes of message data and 4 bytes to hold the message length). + * + * @param pxHigherPriorityTaskWoken It is possible that a message buffer will + * have a task blocked on it waiting for data. Calling + * xMessageBufferSendFromISR() can make data available, and so cause a task that + * was waiting for data to leave the Blocked state. If calling + * xMessageBufferSendFromISR() causes a task to leave the Blocked state, and the + * unblocked task has a priority higher than the currently executing task (the + * task that was interrupted), then, internally, xMessageBufferSendFromISR() + * will set *pxHigherPriorityTaskWoken to pdTRUE. If + * xMessageBufferSendFromISR() sets this value to pdTRUE, then normally a + * context switch should be performed before the interrupt is exited. This will + * ensure that the interrupt returns directly to the highest priority Ready + * state task. *pxHigherPriorityTaskWoken should be set to pdFALSE before it + * is passed into the function. See the code example below for an example. + * + * @return The number of bytes actually written to the message buffer. If the + * message buffer didn't have enough free space for the message to be stored + * then 0 is returned, otherwise xDataLengthBytes is returned. + * + * Example use: + * @code{c} + * // A message buffer that has already been created. + * MessageBufferHandle_t xMessageBuffer; + * + * void vAnInterruptServiceRoutine( void ) + * { + * size_t xBytesSent; + * char *pcStringToSend = "String to send"; + * BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE. + * + * // Attempt to send the string to the message buffer. + * xBytesSent = xMessageBufferSendFromISR( xMessageBuffer, + * ( void * ) pcStringToSend, + * strlen( pcStringToSend ), + * &xHigherPriorityTaskWoken ); + * + * if( xBytesSent != strlen( pcStringToSend ) ) + * { + * // The string could not be added to the message buffer because there was + * // not enough free space in the buffer. + * } + * + * // If xHigherPriorityTaskWoken was set to pdTRUE inside + * // xMessageBufferSendFromISR() then a task that has a priority above the + * // priority of the currently executing task was unblocked and a context + * // switch should be performed to ensure the ISR returns to the unblocked + * // task. In most FreeRTOS ports this is done by simply passing + * // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the + * // variables value, and perform the context switch if necessary. Check the + * // documentation for the port in use for port specific instructions. + * portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + * } + * @endcode + * \defgroup xMessageBufferSendFromISR xMessageBufferSendFromISR + * \ingroup MessageBufferManagement + */ +#define xMessageBufferSendFromISR( xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ) \ + xStreamBufferSendFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ) + +/** + * message_buffer.h + * + * @code{c} + * size_t xMessageBufferReceive( MessageBufferHandle_t xMessageBuffer, + * void *pvRxData, + * size_t xBufferLengthBytes, + * TickType_t xTicksToWait ); + * @endcode + * + * Receives a discrete message from a message buffer. Messages can be of + * variable length and are copied out of the buffer. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xMessageBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xMessageBufferRead()) inside a critical section and set the receive + * block time to 0. + * + * Use xMessageBufferReceive() to read from a message buffer from a task. Use + * xMessageBufferReceiveFromISR() to read from a message buffer from an + * interrupt service routine (ISR). + * + * @param xMessageBuffer The handle of the message buffer from which a message + * is being received. + * + * @param pvRxData A pointer to the buffer into which the received message is + * to be copied. + * + * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData + * parameter. This sets the maximum length of the message that can be received. + * If xBufferLengthBytes is too small to hold the next message then the message + * will be left in the message buffer and 0 will be returned. + * + * @param xTicksToWait The maximum amount of time the task should remain in the + * Blocked state to wait for a message, should the message buffer be empty. + * xMessageBufferReceive() will return immediately if xTicksToWait is zero and + * the message buffer is empty. The block time is specified in tick periods, so + * the absolute time it represents is dependent on the tick frequency. The + * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds + * into a time specified in ticks. Setting xTicksToWait to portMAX_DELAY will + * cause the task to wait indefinitely (without timing out), provided + * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h. Tasks do not use any + * CPU time when they are in the Blocked state. + * + * @return The length, in bytes, of the message read from the message buffer, if + * any. If xMessageBufferReceive() times out before a message became available + * then zero is returned. If the length of the message is greater than + * xBufferLengthBytes then the message will be left in the message buffer and + * zero is returned. + * + * Example use: + * @code{c} + * void vAFunction( MessageBuffer_t xMessageBuffer ) + * { + * uint8_t ucRxData[ 20 ]; + * size_t xReceivedBytes; + * const TickType_t xBlockTime = pdMS_TO_TICKS( 20 ); + * + * // Receive the next message from the message buffer. Wait in the Blocked + * // state (so not using any CPU processing time) for a maximum of 100ms for + * // a message to become available. + * xReceivedBytes = xMessageBufferReceive( xMessageBuffer, + * ( void * ) ucRxData, + * sizeof( ucRxData ), + * xBlockTime ); + * + * if( xReceivedBytes > 0 ) + * { + * // A ucRxData contains a message that is xReceivedBytes long. Process + * // the message here.... + * } + * } + * @endcode + * \defgroup xMessageBufferReceive xMessageBufferReceive + * \ingroup MessageBufferManagement + */ +#define xMessageBufferReceive( xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ) \ + xStreamBufferReceive( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ) + + +/** + * message_buffer.h + * + * @code{c} + * size_t xMessageBufferReceiveFromISR( MessageBufferHandle_t xMessageBuffer, + * void *pvRxData, + * size_t xBufferLengthBytes, + * BaseType_t *pxHigherPriorityTaskWoken ); + * @endcode + * + * An interrupt safe version of the API function that receives a discrete + * message from a message buffer. Messages can be of variable length and are + * copied out of the buffer. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xMessageBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xMessageBufferRead()) inside a critical section and set the receive + * block time to 0. + * + * Use xMessageBufferReceive() to read from a message buffer from a task. Use + * xMessageBufferReceiveFromISR() to read from a message buffer from an + * interrupt service routine (ISR). + * + * @param xMessageBuffer The handle of the message buffer from which a message + * is being received. + * + * @param pvRxData A pointer to the buffer into which the received message is + * to be copied. + * + * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData + * parameter. This sets the maximum length of the message that can be received. + * If xBufferLengthBytes is too small to hold the next message then the message + * will be left in the message buffer and 0 will be returned. + * + * @param pxHigherPriorityTaskWoken It is possible that a message buffer will + * have a task blocked on it waiting for space to become available. Calling + * xMessageBufferReceiveFromISR() can make space available, and so cause a task + * that is waiting for space to leave the Blocked state. If calling + * xMessageBufferReceiveFromISR() causes a task to leave the Blocked state, and + * the unblocked task has a priority higher than the currently executing task + * (the task that was interrupted), then, internally, + * xMessageBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE. + * If xMessageBufferReceiveFromISR() sets this value to pdTRUE, then normally a + * context switch should be performed before the interrupt is exited. That will + * ensure the interrupt returns directly to the highest priority Ready state + * task. *pxHigherPriorityTaskWoken should be set to pdFALSE before it is + * passed into the function. See the code example below for an example. + * + * @return The length, in bytes, of the message read from the message buffer, if + * any. + * + * Example use: + * @code{c} + * // A message buffer that has already been created. + * MessageBuffer_t xMessageBuffer; + * + * void vAnInterruptServiceRoutine( void ) + * { + * uint8_t ucRxData[ 20 ]; + * size_t xReceivedBytes; + * BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE. + * + * // Receive the next message from the message buffer. + * xReceivedBytes = xMessageBufferReceiveFromISR( xMessageBuffer, + * ( void * ) ucRxData, + * sizeof( ucRxData ), + * &xHigherPriorityTaskWoken ); + * + * if( xReceivedBytes > 0 ) + * { + * // A ucRxData contains a message that is xReceivedBytes long. Process + * // the message here.... + * } + * + * // If xHigherPriorityTaskWoken was set to pdTRUE inside + * // xMessageBufferReceiveFromISR() then a task that has a priority above the + * // priority of the currently executing task was unblocked and a context + * // switch should be performed to ensure the ISR returns to the unblocked + * // task. In most FreeRTOS ports this is done by simply passing + * // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the + * // variables value, and perform the context switch if necessary. Check the + * // documentation for the port in use for port specific instructions. + * portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + * } + * @endcode + * \defgroup xMessageBufferReceiveFromISR xMessageBufferReceiveFromISR + * \ingroup MessageBufferManagement + */ +#define xMessageBufferReceiveFromISR( xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ) \ + xStreamBufferReceiveFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ) + +/** + * message_buffer.h + * + * @code{c} + * void vMessageBufferDelete( MessageBufferHandle_t xMessageBuffer ); + * @endcode + * + * Deletes a message buffer that was previously created using a call to + * xMessageBufferCreate() or xMessageBufferCreateStatic(). If the message + * buffer was created using dynamic memory (that is, by xMessageBufferCreate()), + * then the allocated memory is freed. + * + * A message buffer handle must not be used after the message buffer has been + * deleted. + * + * @param xMessageBuffer The handle of the message buffer to be deleted. + * + */ +#define vMessageBufferDelete( xMessageBuffer ) \ + vStreamBufferDelete( ( StreamBufferHandle_t ) xMessageBuffer ) + +/** + * message_buffer.h + * @code{c} + * BaseType_t xMessageBufferIsFull( MessageBufferHandle_t xMessageBuffer ); + * @endcode + * + * Tests to see if a message buffer is full. A message buffer is full if it + * cannot accept any more messages, of any size, until space is made available + * by a message being removed from the message buffer. + * + * @param xMessageBuffer The handle of the message buffer being queried. + * + * @return If the message buffer referenced by xMessageBuffer is full then + * pdTRUE is returned. Otherwise pdFALSE is returned. + */ +#define xMessageBufferIsFull( xMessageBuffer ) \ + xStreamBufferIsFull( ( StreamBufferHandle_t ) xMessageBuffer ) + +/** + * message_buffer.h + * @code{c} + * BaseType_t xMessageBufferIsEmpty( MessageBufferHandle_t xMessageBuffer ); + * @endcode + * + * Tests to see if a message buffer is empty (does not contain any messages). + * + * @param xMessageBuffer The handle of the message buffer being queried. + * + * @return If the message buffer referenced by xMessageBuffer is empty then + * pdTRUE is returned. Otherwise pdFALSE is returned. + * + */ +#define xMessageBufferIsEmpty( xMessageBuffer ) \ + xStreamBufferIsEmpty( ( StreamBufferHandle_t ) xMessageBuffer ) + +/** + * message_buffer.h + * @code{c} + * BaseType_t xMessageBufferReset( MessageBufferHandle_t xMessageBuffer ); + * @endcode + * + * Resets a message buffer to its initial empty state, discarding any message it + * contained. + * + * A message buffer can only be reset if there are no tasks blocked on it. + * + * @param xMessageBuffer The handle of the message buffer being reset. + * + * @return If the message buffer was reset then pdPASS is returned. If the + * message buffer could not be reset because either there was a task blocked on + * the message queue to wait for space to become available, or to wait for a + * a message to be available, then pdFAIL is returned. + * + * \defgroup xMessageBufferReset xMessageBufferReset + * \ingroup MessageBufferManagement + */ +#define xMessageBufferReset( xMessageBuffer ) \ + xStreamBufferReset( ( StreamBufferHandle_t ) xMessageBuffer ) + + +/** + * message_buffer.h + * @code{c} + * size_t xMessageBufferSpaceAvailable( MessageBufferHandle_t xMessageBuffer ); + * @endcode + * Returns the number of bytes of free space in the message buffer. + * + * @param xMessageBuffer The handle of the message buffer being queried. + * + * @return The number of bytes that can be written to the message buffer before + * the message buffer would be full. When a message is written to the message + * buffer an additional sizeof( size_t ) bytes are also written to store the + * message's length. sizeof( size_t ) is typically 4 bytes on a 32-bit + * architecture, so if xMessageBufferSpacesAvailable() returns 10, then the size + * of the largest message that can be written to the message buffer is 6 bytes. + * + * \defgroup xMessageBufferSpaceAvailable xMessageBufferSpaceAvailable + * \ingroup MessageBufferManagement + */ +#define xMessageBufferSpaceAvailable( xMessageBuffer ) \ + xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer ) +#define xMessageBufferSpacesAvailable( xMessageBuffer ) \ + xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer ) /* Corrects typo in original macro name. */ + +/** + * message_buffer.h + * @code{c} + * size_t xMessageBufferNextLengthBytes( MessageBufferHandle_t xMessageBuffer ); + * @endcode + * Returns the length (in bytes) of the next message in a message buffer. + * Useful if xMessageBufferReceive() returned 0 because the size of the buffer + * passed into xMessageBufferReceive() was too small to hold the next message. + * + * @param xMessageBuffer The handle of the message buffer being queried. + * + * @return The length (in bytes) of the next message in the message buffer, or 0 + * if the message buffer is empty. + * + * \defgroup xMessageBufferNextLengthBytes xMessageBufferNextLengthBytes + * \ingroup MessageBufferManagement + */ +#define xMessageBufferNextLengthBytes( xMessageBuffer ) \ + xStreamBufferNextMessageLengthBytes( ( StreamBufferHandle_t ) xMessageBuffer ) PRIVILEGED_FUNCTION; + +/** + * message_buffer.h + * + * @code{c} + * BaseType_t xMessageBufferSendCompletedFromISR( MessageBufferHandle_t xMessageBuffer, BaseType_t *pxHigherPriorityTaskWoken ); + * @endcode + * + * For advanced users only. + * + * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when + * data is sent to a message buffer or stream buffer. If there was a task that + * was blocked on the message or stream buffer waiting for data to arrive then + * the sbSEND_COMPLETED() macro sends a notification to the task to remove it + * from the Blocked state. xMessageBufferSendCompletedFromISR() does the same + * thing. It is provided to enable application writers to implement their own + * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME. + * + * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for + * additional information. + * + * @param xMessageBuffer The handle of the stream buffer to which data was + * written. + * + * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be + * initialised to pdFALSE before it is passed into + * xMessageBufferSendCompletedFromISR(). If calling + * xMessageBufferSendCompletedFromISR() removes a task from the Blocked state, + * and the task has a priority above the priority of the currently running task, + * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a + * context switch should be performed before exiting the ISR. + * + * @return If a task was removed from the Blocked state then pdTRUE is returned. + * Otherwise pdFALSE is returned. + * + * \defgroup xMessageBufferSendCompletedFromISR xMessageBufferSendCompletedFromISR + * \ingroup StreamBufferManagement + */ +#define xMessageBufferSendCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) \ + xStreamBufferSendCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken ) + +/** + * message_buffer.h + * + * @code{c} + * BaseType_t xMessageBufferReceiveCompletedFromISR( MessageBufferHandle_t xMessageBuffer, BaseType_t *pxHigherPriorityTaskWoken ); + * @endcode + * + * For advanced users only. + * + * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when + * data is read out of a message buffer or stream buffer. If there was a task + * that was blocked on the message or stream buffer waiting for data to arrive + * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to + * remove it from the Blocked state. xMessageBufferReceiveCompletedFromISR() + * does the same thing. It is provided to enable application writers to + * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT + * ANY OTHER TIME. + * + * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for + * additional information. + * + * @param xMessageBuffer The handle of the stream buffer from which data was + * read. + * + * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be + * initialised to pdFALSE before it is passed into + * xMessageBufferReceiveCompletedFromISR(). If calling + * xMessageBufferReceiveCompletedFromISR() removes a task from the Blocked state, + * and the task has a priority above the priority of the currently running task, + * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a + * context switch should be performed before exiting the ISR. + * + * @return If a task was removed from the Blocked state then pdTRUE is returned. + * Otherwise pdFALSE is returned. + * + * \defgroup xMessageBufferReceiveCompletedFromISR xMessageBufferReceiveCompletedFromISR + * \ingroup StreamBufferManagement + */ +#define xMessageBufferReceiveCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) \ + xStreamBufferReceiveCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken ) + +/* *INDENT-OFF* */ +#if defined( __cplusplus ) + } /* extern "C" */ +#endif +/* *INDENT-ON* */ + +#endif /* !defined( FREERTOS_MESSAGE_BUFFER_H ) */ diff --git a/hw-libs/freertos/include/mpu_prototypes.h b/hw-libs/freertos/include/mpu_prototypes.h new file mode 100644 index 000000000..cb743be55 --- /dev/null +++ b/hw-libs/freertos/include/mpu_prototypes.h @@ -0,0 +1,260 @@ +/* + * FreeRTOS Kernel V10.4.6 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * When the MPU is used the standard (non MPU) API functions are mapped to + * equivalents that start "MPU_", the prototypes for which are defined in this + * header files. This will cause the application code to call the MPU_ version + * which wraps the non-MPU version with privilege promoting then demoting code, + * so the kernel code always runs will full privileges. + */ + + +#ifndef MPU_PROTOTYPES_H +#define MPU_PROTOTYPES_H + +/* MPU versions of tasks.h API functions. */ +BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode, + const char * const pcName, + const uint16_t usStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, + const char * const pcName, + const uint32_t ulStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + StackType_t * const puxStackBuffer, + StaticTask_t * const pxTaskBuffer ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskPrioritySet( TaskHandle_t xTask, + UBaseType_t uxNewPriority ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskStartScheduler( void ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSuspendAll( void ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskResumeAll( void ) FREERTOS_SYSTEM_CALL; +TickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL; +char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xTaskGetHandle( const char * pcNameToQuery ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) FREERTOS_SYSTEM_CALL; +TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) FREERTOS_SYSTEM_CALL; +void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, + void * pvParameter ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) FREERTOS_SYSTEM_CALL; +configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) FREERTOS_SYSTEM_CALL; +configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskList( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskGetRunTimeStats( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + uint32_t ulValue, + eNotifyAction eAction, + uint32_t * pulPreviousNotificationValue ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn, + uint32_t ulBitsToClearOnEntry, + uint32_t ulBitsToClearOnExit, + uint32_t * pulNotificationValue, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) FREERTOS_SYSTEM_CALL; +uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskIncrementTick( void ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskMissedYield( void ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) FREERTOS_SYSTEM_CALL; + +/* MPU versions of queue.h API functions. */ +BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +void MPU_vQueueDelete( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, + StaticQueue_t * pxStaticQueue ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, + const UBaseType_t uxInitialCount ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, + const UBaseType_t uxInitialCount, + StaticQueue_t * pxStaticQueue ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) FREERTOS_SYSTEM_CALL; +void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) FREERTOS_SYSTEM_CALL; +void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + uint8_t * pucQueueStorage, + StaticQueue_t * pxStaticQueue, + const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL; +QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL; +QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue, + BaseType_t xNewQueue ) FREERTOS_SYSTEM_CALL; +void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue, + UBaseType_t uxQueueNumber ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; + +/* MPU versions of timers.h API functions. */ +TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, + const TickType_t xTimerPeriodInTicks, + const UBaseType_t uxAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction ) FREERTOS_SYSTEM_CALL; +TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, + const TickType_t xTimerPeriodInTicks, + const UBaseType_t uxAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction, + StaticTimer_t * pxTimerBuffer ) FREERTOS_SYSTEM_CALL; +void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, + void * pvParameter1, + uint32_t ulParameter2, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const UBaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTimerCreateTimerTask( void ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, + const BaseType_t xCommandID, + const TickType_t xOptionalValue, + BaseType_t * const pxHigherPriorityTaskWoken, + const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; + +/* MPU versions of event_group.h API functions. */ +EventGroupHandle_t MPU_xEventGroupCreate( void ) FREERTOS_SYSTEM_CALL; +EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) FREERTOS_SYSTEM_CALL; +EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToWaitFor, + const BaseType_t xClearOnExit, + const BaseType_t xWaitForAllBits, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL; +EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL; +EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) FREERTOS_SYSTEM_CALL; + +/* MPU versions of message/stream_buffer.h API functions. */ +size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL; +StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xIsMessageBuffer ) FREERTOS_SYSTEM_CALL; +StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xIsMessageBuffer, + uint8_t * const pucStreamBufferStorageArea, + StaticStreamBuffer_t * const pxStaticStreamBuffer ) FREERTOS_SYSTEM_CALL; + + + +#endif /* MPU_PROTOTYPES_H */ diff --git a/hw-libs/freertos/include/mpu_wrappers.h b/hw-libs/freertos/include/mpu_wrappers.h new file mode 100644 index 000000000..9b6cd7c92 --- /dev/null +++ b/hw-libs/freertos/include/mpu_wrappers.h @@ -0,0 +1,217 @@ +/* + * FreeRTOS Kernel V10.4.6 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef MPU_WRAPPERS_H +#define MPU_WRAPPERS_H + +/* This file redefines API functions to be called through a wrapper macro, but + * only for ports that are using the MPU. */ +#if ( portUSING_MPU_WRAPPERS == 1 ) + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is + * included from queue.c or task.c to prevent it from having an effect within + * those files. */ + #ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* + * Map standard (non MPU) API functions to equivalents that start + * "MPU_". This will cause the application code to call the MPU_ + * version, which wraps the non-MPU version with privilege promoting + * then demoting code, so the kernel code always runs will full + * privileges. + */ + +/* Map standard tasks.h API functions to the MPU equivalents. */ + #define xTaskCreate MPU_xTaskCreate + #define xTaskCreateStatic MPU_xTaskCreateStatic + #define vTaskDelete MPU_vTaskDelete + #define vTaskDelay MPU_vTaskDelay + #define xTaskDelayUntil MPU_xTaskDelayUntil + #define xTaskAbortDelay MPU_xTaskAbortDelay + #define uxTaskPriorityGet MPU_uxTaskPriorityGet + #define eTaskGetState MPU_eTaskGetState + #define vTaskGetInfo MPU_vTaskGetInfo + #define vTaskPrioritySet MPU_vTaskPrioritySet + #define vTaskSuspend MPU_vTaskSuspend + #define vTaskResume MPU_vTaskResume + #define vTaskSuspendAll MPU_vTaskSuspendAll + #define xTaskResumeAll MPU_xTaskResumeAll + #define xTaskGetTickCount MPU_xTaskGetTickCount + #define uxTaskGetNumberOfTasks MPU_uxTaskGetNumberOfTasks + #define pcTaskGetName MPU_pcTaskGetName + #define xTaskGetHandle MPU_xTaskGetHandle + #define uxTaskGetStackHighWaterMark MPU_uxTaskGetStackHighWaterMark + #define uxTaskGetStackHighWaterMark2 MPU_uxTaskGetStackHighWaterMark2 + #define vTaskSetApplicationTaskTag MPU_vTaskSetApplicationTaskTag + #define xTaskGetApplicationTaskTag MPU_xTaskGetApplicationTaskTag + #define vTaskSetThreadLocalStoragePointer MPU_vTaskSetThreadLocalStoragePointer + #define pvTaskGetThreadLocalStoragePointer MPU_pvTaskGetThreadLocalStoragePointer + #define xTaskCallApplicationTaskHook MPU_xTaskCallApplicationTaskHook + #define xTaskGetIdleTaskHandle MPU_xTaskGetIdleTaskHandle + #define uxTaskGetSystemState MPU_uxTaskGetSystemState + #define vTaskList MPU_vTaskList + #define vTaskGetRunTimeStats MPU_vTaskGetRunTimeStats + #define ulTaskGetIdleRunTimeCounter MPU_ulTaskGetIdleRunTimeCounter + #define ulTaskGetIdleRunTimePercent MPU_ulTaskGetIdleRunTimePercent + #define xTaskGenericNotify MPU_xTaskGenericNotify + #define xTaskGenericNotifyWait MPU_xTaskGenericNotifyWait + #define ulTaskGenericNotifyTake MPU_ulTaskGenericNotifyTake + #define xTaskGenericNotifyStateClear MPU_xTaskGenericNotifyStateClear + #define ulTaskGenericNotifyValueClear MPU_ulTaskGenericNotifyValueClear + #define xTaskCatchUpTicks MPU_xTaskCatchUpTicks + + #define xTaskGetCurrentTaskHandle MPU_xTaskGetCurrentTaskHandle + #define vTaskSetTimeOutState MPU_vTaskSetTimeOutState + #define xTaskCheckForTimeOut MPU_xTaskCheckForTimeOut + #define xTaskGetSchedulerState MPU_xTaskGetSchedulerState + +/* Map standard queue.h API functions to the MPU equivalents. */ + #define xQueueGenericSend MPU_xQueueGenericSend + #define xQueueReceive MPU_xQueueReceive + #define xQueuePeek MPU_xQueuePeek + #define xQueueSemaphoreTake MPU_xQueueSemaphoreTake + #define uxQueueMessagesWaiting MPU_uxQueueMessagesWaiting + #define uxQueueSpacesAvailable MPU_uxQueueSpacesAvailable + #define vQueueDelete MPU_vQueueDelete + #define xQueueCreateMutex MPU_xQueueCreateMutex + #define xQueueCreateMutexStatic MPU_xQueueCreateMutexStatic + #define xQueueCreateCountingSemaphore MPU_xQueueCreateCountingSemaphore + #define xQueueCreateCountingSemaphoreStatic MPU_xQueueCreateCountingSemaphoreStatic + #define xQueueGetMutexHolder MPU_xQueueGetMutexHolder + #define xQueueTakeMutexRecursive MPU_xQueueTakeMutexRecursive + #define xQueueGiveMutexRecursive MPU_xQueueGiveMutexRecursive + #define xQueueGenericCreate MPU_xQueueGenericCreate + #define xQueueGenericCreateStatic MPU_xQueueGenericCreateStatic + #define xQueueCreateSet MPU_xQueueCreateSet + #define xQueueAddToSet MPU_xQueueAddToSet + #define xQueueRemoveFromSet MPU_xQueueRemoveFromSet + #define xQueueSelectFromSet MPU_xQueueSelectFromSet + #define xQueueGenericReset MPU_xQueueGenericReset + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + #define vQueueAddToRegistry MPU_vQueueAddToRegistry + #define vQueueUnregisterQueue MPU_vQueueUnregisterQueue + #define pcQueueGetName MPU_pcQueueGetName + #endif + +/* Map standard timer.h API functions to the MPU equivalents. */ + #define xTimerCreate MPU_xTimerCreate + #define xTimerCreateStatic MPU_xTimerCreateStatic + #define pvTimerGetTimerID MPU_pvTimerGetTimerID + #define vTimerSetTimerID MPU_vTimerSetTimerID + #define xTimerIsTimerActive MPU_xTimerIsTimerActive + #define xTimerGetTimerDaemonTaskHandle MPU_xTimerGetTimerDaemonTaskHandle + #define xTimerPendFunctionCall MPU_xTimerPendFunctionCall + #define pcTimerGetName MPU_pcTimerGetName + #define vTimerSetReloadMode MPU_vTimerSetReloadMode + #define uxTimerGetReloadMode MPU_uxTimerGetReloadMode + #define xTimerGetPeriod MPU_xTimerGetPeriod + #define xTimerGetExpiryTime MPU_xTimerGetExpiryTime + #define xTimerGenericCommand MPU_xTimerGenericCommand + +/* Map standard event_group.h API functions to the MPU equivalents. */ + #define xEventGroupCreate MPU_xEventGroupCreate + #define xEventGroupCreateStatic MPU_xEventGroupCreateStatic + #define xEventGroupWaitBits MPU_xEventGroupWaitBits + #define xEventGroupClearBits MPU_xEventGroupClearBits + #define xEventGroupSetBits MPU_xEventGroupSetBits + #define xEventGroupSync MPU_xEventGroupSync + #define vEventGroupDelete MPU_vEventGroupDelete + +/* Map standard message/stream_buffer.h API functions to the MPU + * equivalents. */ + #define xStreamBufferSend MPU_xStreamBufferSend + #define xStreamBufferReceive MPU_xStreamBufferReceive + #define xStreamBufferNextMessageLengthBytes MPU_xStreamBufferNextMessageLengthBytes + #define vStreamBufferDelete MPU_vStreamBufferDelete + #define xStreamBufferIsFull MPU_xStreamBufferIsFull + #define xStreamBufferIsEmpty MPU_xStreamBufferIsEmpty + #define xStreamBufferReset MPU_xStreamBufferReset + #define xStreamBufferSpacesAvailable MPU_xStreamBufferSpacesAvailable + #define xStreamBufferBytesAvailable MPU_xStreamBufferBytesAvailable + #define xStreamBufferSetTriggerLevel MPU_xStreamBufferSetTriggerLevel + #define xStreamBufferGenericCreate MPU_xStreamBufferGenericCreate + #define xStreamBufferGenericCreateStatic MPU_xStreamBufferGenericCreateStatic + + +/* Remove the privileged function macro, but keep the PRIVILEGED_DATA + * macro so applications can place data in privileged access sections + * (useful when using statically allocated objects). */ + #define PRIVILEGED_FUNCTION + #define PRIVILEGED_DATA __attribute__( ( section( "privileged_data" ) ) ) + #define FREERTOS_SYSTEM_CALL + + #else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */ + + /* Ensure API functions go in the privileged execution section. */ + #define PRIVILEGED_FUNCTION __attribute__( ( section( "privileged_functions" ) ) ) + #define PRIVILEGED_DATA __attribute__( ( section( "privileged_data" ) ) ) + #define FREERTOS_SYSTEM_CALL __attribute__( ( section( "freertos_system_calls" ) ) ) + + /** + * @brief Calls the port specific code to raise the privilege. + * + * Sets xRunningPrivileged to pdFALSE if privilege was raised, else sets + * it to pdTRUE. + */ + #define xPortRaisePrivilege( xRunningPrivileged ) \ + { \ + /* Check whether the processor is already privileged. */ \ + xRunningPrivileged = portIS_PRIVILEGED(); \ + \ + /* If the processor is not already privileged, raise privilege. */ \ + if( xRunningPrivileged == pdFALSE ) \ + { \ + portRAISE_PRIVILEGE(); \ + } \ + } + + /** + * @brief If xRunningPrivileged is not pdTRUE, calls the port specific + * code to reset the privilege, otherwise does nothing. + */ + #define vPortResetPrivilege( xRunningPrivileged ) \ + { \ + if( xRunningPrivileged == pdFALSE ) \ + { \ + portRESET_PRIVILEGE(); \ + } \ + } + + #endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */ + +#else /* portUSING_MPU_WRAPPERS */ + + #define PRIVILEGED_FUNCTION + #define PRIVILEGED_DATA + #define FREERTOS_SYSTEM_CALL + +#endif /* portUSING_MPU_WRAPPERS */ + + +#endif /* MPU_WRAPPERS_H */ diff --git a/hw-libs/freertos/include/portable.h b/hw-libs/freertos/include/portable.h new file mode 100644 index 000000000..0ec6416ae --- /dev/null +++ b/hw-libs/freertos/include/portable.h @@ -0,0 +1,223 @@ +/* + * FreeRTOS Kernel V10.4.6 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Portable layer API. Each function must be defined for each port. +*----------------------------------------------------------*/ + +#ifndef PORTABLE_H +#define PORTABLE_H + +/* Each FreeRTOS port has a unique portmacro.h header file. Originally a + * pre-processor definition was used to ensure the pre-processor found the correct + * portmacro.h file for the port being used. That scheme was deprecated in favour + * of setting the compiler's include path such that it found the correct + * portmacro.h file - removing the need for the constant and allowing the + * portmacro.h file to be located anywhere in relation to the port being used. + * Purely for reasons of backward compatibility the old method is still valid, but + * to make it clear that new projects should not use it, support for the port + * specific constants has been moved into the deprecated_definitions.h header + * file. */ +#include "deprecated_definitions.h" + +/* If portENTER_CRITICAL is not defined then including deprecated_definitions.h + * did not result in a portmacro.h header file being included - and it should be + * included here. In this case the path to the correct portmacro.h header file + * must be set in the compiler's include path. */ +#ifndef portENTER_CRITICAL + #include "portmacro.h" +#endif + +#if portBYTE_ALIGNMENT == 32 + #define portBYTE_ALIGNMENT_MASK ( 0x001f ) +#elif portBYTE_ALIGNMENT == 16 + #define portBYTE_ALIGNMENT_MASK ( 0x000f ) +#elif portBYTE_ALIGNMENT == 8 + #define portBYTE_ALIGNMENT_MASK ( 0x0007 ) +#elif portBYTE_ALIGNMENT == 4 + #define portBYTE_ALIGNMENT_MASK ( 0x0003 ) +#elif portBYTE_ALIGNMENT == 2 + #define portBYTE_ALIGNMENT_MASK ( 0x0001 ) +#elif portBYTE_ALIGNMENT == 1 + #define portBYTE_ALIGNMENT_MASK ( 0x0000 ) +#else /* if portBYTE_ALIGNMENT == 32 */ + #error "Invalid portBYTE_ALIGNMENT definition" +#endif /* if portBYTE_ALIGNMENT == 32 */ + +#ifndef portUSING_MPU_WRAPPERS + #define portUSING_MPU_WRAPPERS 0 +#endif + +#ifndef portNUM_CONFIGURABLE_REGIONS + #define portNUM_CONFIGURABLE_REGIONS 1 +#endif + +#ifndef portHAS_STACK_OVERFLOW_CHECKING + #define portHAS_STACK_OVERFLOW_CHECKING 0 +#endif + +#ifndef portARCH_NAME + #define portARCH_NAME NULL +#endif + +#ifndef configSTACK_ALLOCATION_FROM_SEPARATE_HEAP + /* Defaults to 0 for backward compatibility. */ + #define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 +#endif + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +#include "mpu_wrappers.h" + +/* + * Setup the stack of a new task so it is ready to be placed under the + * scheduler control. The registers have to be placed on the stack in + * the order that the port expects to find them. + * + */ +#if ( portUSING_MPU_WRAPPERS == 1 ) + #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 ) + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION; + #else + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION; + #endif +#else /* if ( portUSING_MPU_WRAPPERS == 1 ) */ + #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 ) + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) PRIVILEGED_FUNCTION; + #else + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) PRIVILEGED_FUNCTION; + #endif +#endif /* if ( portUSING_MPU_WRAPPERS == 1 ) */ + +/* Used by heap_5.c to define the start address and size of each memory region + * that together comprise the total FreeRTOS heap space. */ +typedef struct HeapRegion +{ + uint8_t * pucStartAddress; + size_t xSizeInBytes; +} HeapRegion_t; + +/* Used to pass information about the heap out of vPortGetHeapStats(). */ +typedef struct xHeapStats +{ + size_t xAvailableHeapSpaceInBytes; /* The total heap size currently available - this is the sum of all the free blocks, not the largest block that can be allocated. */ + size_t xSizeOfLargestFreeBlockInBytes; /* The maximum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */ + size_t xSizeOfSmallestFreeBlockInBytes; /* The minimum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */ + size_t xNumberOfFreeBlocks; /* The number of free memory blocks within the heap at the time vPortGetHeapStats() is called. */ + size_t xMinimumEverFreeBytesRemaining; /* The minimum amount of total free memory (sum of all free blocks) there has been in the heap since the system booted. */ + size_t xNumberOfSuccessfulAllocations; /* The number of calls to pvPortMalloc() that have returned a valid memory block. */ + size_t xNumberOfSuccessfulFrees; /* The number of calls to vPortFree() that has successfully freed a block of memory. */ +} HeapStats_t; + +/* + * Used to define multiple heap regions for use by heap_5.c. This function + * must be called before any calls to pvPortMalloc() - not creating a task, + * queue, semaphore, mutex, software timer, event group, etc. will result in + * pvPortMalloc being called. + * + * pxHeapRegions passes in an array of HeapRegion_t structures - each of which + * defines a region of memory that can be used as the heap. The array is + * terminated by a HeapRegions_t structure that has a size of 0. The region + * with the lowest start address must appear first in the array. + */ +void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION; + +/* + * Returns a HeapStats_t structure filled with information about the current + * heap state. + */ +void vPortGetHeapStats( HeapStats_t * pxHeapStats ); + +/* + * Map to the memory management routines required for the port. + */ +void * pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION; +void vPortFree( void * pv ) PRIVILEGED_FUNCTION; +void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION; +size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION; +size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION; + +#if ( configSTACK_ALLOCATION_FROM_SEPARATE_HEAP == 1 ) + void * pvPortMallocStack( size_t xSize ) PRIVILEGED_FUNCTION; + void vPortFreeStack( void * pv ) PRIVILEGED_FUNCTION; +#else + #define pvPortMallocStack pvPortMalloc + #define vPortFreeStack vPortFree +#endif + +/* + * Setup the hardware ready for the scheduler to take control. This generally + * sets up a tick interrupt and sets timers for the correct tick frequency. + */ +BaseType_t xPortStartScheduler( void ) PRIVILEGED_FUNCTION; + +/* + * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so + * the hardware is left in its original condition after the scheduler stops + * executing. + */ +void vPortEndScheduler( void ) PRIVILEGED_FUNCTION; + +/* + * The structures and methods of manipulating the MPU are contained within the + * port layer. + * + * Fills the xMPUSettings structure with the memory region information + * contained in xRegions. + */ +#if ( portUSING_MPU_WRAPPERS == 1 ) + struct xMEMORY_REGION; + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + uint32_t ulStackDepth ) PRIVILEGED_FUNCTION; +#endif + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTABLE_H */ diff --git a/hw-libs/freertos/include/projdefs.h b/hw-libs/freertos/include/projdefs.h new file mode 100644 index 000000000..e623bf7d9 --- /dev/null +++ b/hw-libs/freertos/include/projdefs.h @@ -0,0 +1,122 @@ +/* + * FreeRTOS Kernel V10.4.6 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PROJDEFS_H +#define PROJDEFS_H + +/* + * Defines the prototype to which task functions must conform. Defined in this + * file to ensure the type is known before portable.h is included. + */ +typedef void (* TaskFunction_t)( void * ); + +/* Converts a time in milliseconds to a time in ticks. This macro can be + * overridden by a macro of the same name defined in FreeRTOSConfig.h in case the + * definition here is not suitable for your application. */ +#ifndef pdMS_TO_TICKS + #define pdMS_TO_TICKS( xTimeInMs ) ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000U ) ) +#endif + +#define pdFALSE ( ( BaseType_t ) 0 ) +#define pdTRUE ( ( BaseType_t ) 1 ) + +#define pdPASS ( pdTRUE ) +#define pdFAIL ( pdFALSE ) +#define errQUEUE_EMPTY ( ( BaseType_t ) 0 ) +#define errQUEUE_FULL ( ( BaseType_t ) 0 ) + +/* FreeRTOS error definitions. */ +#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ( -1 ) +#define errQUEUE_BLOCKED ( -4 ) +#define errQUEUE_YIELD ( -5 ) + +/* Macros used for basic data corruption checks. */ +#ifndef configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES + #define configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES 0 +#endif + +#if ( configUSE_16_BIT_TICKS == 1 ) + #define pdINTEGRITY_CHECK_VALUE 0x5a5a +#else + #define pdINTEGRITY_CHECK_VALUE 0x5a5a5a5aUL +#endif + +/* The following errno values are used by FreeRTOS+ components, not FreeRTOS + * itself. */ +#define pdFREERTOS_ERRNO_NONE 0 /* No errors */ +#define pdFREERTOS_ERRNO_ENOENT 2 /* No such file or directory */ +#define pdFREERTOS_ERRNO_EINTR 4 /* Interrupted system call */ +#define pdFREERTOS_ERRNO_EIO 5 /* I/O error */ +#define pdFREERTOS_ERRNO_ENXIO 6 /* No such device or address */ +#define pdFREERTOS_ERRNO_EBADF 9 /* Bad file number */ +#define pdFREERTOS_ERRNO_EAGAIN 11 /* No more processes */ +#define pdFREERTOS_ERRNO_EWOULDBLOCK 11 /* Operation would block */ +#define pdFREERTOS_ERRNO_ENOMEM 12 /* Not enough memory */ +#define pdFREERTOS_ERRNO_EACCES 13 /* Permission denied */ +#define pdFREERTOS_ERRNO_EFAULT 14 /* Bad address */ +#define pdFREERTOS_ERRNO_EBUSY 16 /* Mount device busy */ +#define pdFREERTOS_ERRNO_EEXIST 17 /* File exists */ +#define pdFREERTOS_ERRNO_EXDEV 18 /* Cross-device link */ +#define pdFREERTOS_ERRNO_ENODEV 19 /* No such device */ +#define pdFREERTOS_ERRNO_ENOTDIR 20 /* Not a directory */ +#define pdFREERTOS_ERRNO_EISDIR 21 /* Is a directory */ +#define pdFREERTOS_ERRNO_EINVAL 22 /* Invalid argument */ +#define pdFREERTOS_ERRNO_ENOSPC 28 /* No space left on device */ +#define pdFREERTOS_ERRNO_ESPIPE 29 /* Illegal seek */ +#define pdFREERTOS_ERRNO_EROFS 30 /* Read only file system */ +#define pdFREERTOS_ERRNO_EUNATCH 42 /* Protocol driver not attached */ +#define pdFREERTOS_ERRNO_EBADE 50 /* Invalid exchange */ +#define pdFREERTOS_ERRNO_EFTYPE 79 /* Inappropriate file type or format */ +#define pdFREERTOS_ERRNO_ENMFILE 89 /* No more files */ +#define pdFREERTOS_ERRNO_ENOTEMPTY 90 /* Directory not empty */ +#define pdFREERTOS_ERRNO_ENAMETOOLONG 91 /* File or path name too long */ +#define pdFREERTOS_ERRNO_EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ +#define pdFREERTOS_ERRNO_ENOBUFS 105 /* No buffer space available */ +#define pdFREERTOS_ERRNO_ENOPROTOOPT 109 /* Protocol not available */ +#define pdFREERTOS_ERRNO_EADDRINUSE 112 /* Address already in use */ +#define pdFREERTOS_ERRNO_ETIMEDOUT 116 /* Connection timed out */ +#define pdFREERTOS_ERRNO_EINPROGRESS 119 /* Connection already in progress */ +#define pdFREERTOS_ERRNO_EALREADY 120 /* Socket already connected */ +#define pdFREERTOS_ERRNO_EADDRNOTAVAIL 125 /* Address not available */ +#define pdFREERTOS_ERRNO_EISCONN 127 /* Socket is already connected */ +#define pdFREERTOS_ERRNO_ENOTCONN 128 /* Socket is not connected */ +#define pdFREERTOS_ERRNO_ENOMEDIUM 135 /* No medium inserted */ +#define pdFREERTOS_ERRNO_EILSEQ 138 /* An invalid UTF-16 sequence was encountered. */ +#define pdFREERTOS_ERRNO_ECANCELED 140 /* Operation canceled. */ + +/* The following endian values are used by FreeRTOS+ components, not FreeRTOS + * itself. */ +#define pdFREERTOS_LITTLE_ENDIAN 0 +#define pdFREERTOS_BIG_ENDIAN 1 + +/* Re-defining endian values for generic naming. */ +#define pdLITTLE_ENDIAN pdFREERTOS_LITTLE_ENDIAN +#define pdBIG_ENDIAN pdFREERTOS_BIG_ENDIAN + + +#endif /* PROJDEFS_H */ diff --git a/hw-libs/freertos/include/queue.h b/hw-libs/freertos/include/queue.h new file mode 100644 index 000000000..6a92b6bcb --- /dev/null +++ b/hw-libs/freertos/include/queue.h @@ -0,0 +1,1722 @@ +/* + * FreeRTOS Kernel V10.4.6 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef QUEUE_H +#define QUEUE_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h" must appear in source files before "include queue.h" +#endif + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +#include "task.h" + +/** + * Type by which queues are referenced. For example, a call to xQueueCreate() + * returns an QueueHandle_t variable that can then be used as a parameter to + * xQueueSend(), xQueueReceive(), etc. + */ +struct QueueDefinition; /* Using old naming convention so as not to break kernel aware debuggers. */ +typedef struct QueueDefinition * QueueHandle_t; + +/** + * Type by which queue sets are referenced. For example, a call to + * xQueueCreateSet() returns an xQueueSet variable that can then be used as a + * parameter to xQueueSelectFromSet(), xQueueAddToSet(), etc. + */ +typedef struct QueueDefinition * QueueSetHandle_t; + +/** + * Queue sets can contain both queues and semaphores, so the + * QueueSetMemberHandle_t is defined as a type to be used where a parameter or + * return value can be either an QueueHandle_t or an SemaphoreHandle_t. + */ +typedef struct QueueDefinition * QueueSetMemberHandle_t; + +/* For internal use only. */ +#define queueSEND_TO_BACK ( ( BaseType_t ) 0 ) +#define queueSEND_TO_FRONT ( ( BaseType_t ) 1 ) +#define queueOVERWRITE ( ( BaseType_t ) 2 ) + +/* For internal use only. These definitions *must* match those in queue.c. */ +#define queueQUEUE_TYPE_BASE ( ( uint8_t ) 0U ) +#define queueQUEUE_TYPE_SET ( ( uint8_t ) 0U ) +#define queueQUEUE_TYPE_MUTEX ( ( uint8_t ) 1U ) +#define queueQUEUE_TYPE_COUNTING_SEMAPHORE ( ( uint8_t ) 2U ) +#define queueQUEUE_TYPE_BINARY_SEMAPHORE ( ( uint8_t ) 3U ) +#define queueQUEUE_TYPE_RECURSIVE_MUTEX ( ( uint8_t ) 4U ) + +/** + * queue. h + * @code{c} + * QueueHandle_t xQueueCreate( + * UBaseType_t uxQueueLength, + * UBaseType_t uxItemSize + * ); + * @endcode + * + * Creates a new queue instance, and returns a handle by which the new queue + * can be referenced. + * + * Internally, within the FreeRTOS implementation, queues use two blocks of + * memory. The first block is used to hold the queue's data structures. The + * second block is used to hold items placed into the queue. If a queue is + * created using xQueueCreate() then both blocks of memory are automatically + * dynamically allocated inside the xQueueCreate() function. (see + * https://www.FreeRTOS.org/a00111.html). If a queue is created using + * xQueueCreateStatic() then the application writer must provide the memory that + * will get used by the queue. xQueueCreateStatic() therefore allows a queue to + * be created without using any dynamic memory allocation. + * + * https://www.FreeRTOS.org/Embedded-RTOS-Queues.html + * + * @param uxQueueLength The maximum number of items that the queue can contain. + * + * @param uxItemSize The number of bytes each item in the queue will require. + * Items are queued by copy, not by reference, so this is the number of bytes + * that will be copied for each posted item. Each item on the queue must be + * the same size. + * + * @return If the queue is successfully create then a handle to the newly + * created queue is returned. If the queue cannot be created then 0 is + * returned. + * + * Example usage: + * @code{c} + * struct AMessage + * { + * char ucMessageID; + * char ucData[ 20 ]; + * }; + * + * void vATask( void *pvParameters ) + * { + * QueueHandle_t xQueue1, xQueue2; + * + * // Create a queue capable of containing 10 uint32_t values. + * xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) ); + * if( xQueue1 == 0 ) + * { + * // Queue was not created and must not be used. + * } + * + * // Create a queue capable of containing 10 pointers to AMessage structures. + * // These should be passed by pointer as they contain a lot of data. + * xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) ); + * if( xQueue2 == 0 ) + * { + * // Queue was not created and must not be used. + * } + * + * // ... Rest of task code. + * } + * @endcode + * \defgroup xQueueCreate xQueueCreate + * \ingroup QueueManagement + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + #define xQueueCreate( uxQueueLength, uxItemSize ) xQueueGenericCreate( ( uxQueueLength ), ( uxItemSize ), ( queueQUEUE_TYPE_BASE ) ) +#endif + +/** + * queue. h + * @code{c} + * QueueHandle_t xQueueCreateStatic( + * UBaseType_t uxQueueLength, + * UBaseType_t uxItemSize, + * uint8_t *pucQueueStorage, + * StaticQueue_t *pxQueueBuffer + * ); + * @endcode + * + * Creates a new queue instance, and returns a handle by which the new queue + * can be referenced. + * + * Internally, within the FreeRTOS implementation, queues use two blocks of + * memory. The first block is used to hold the queue's data structures. The + * second block is used to hold items placed into the queue. If a queue is + * created using xQueueCreate() then both blocks of memory are automatically + * dynamically allocated inside the xQueueCreate() function. (see + * https://www.FreeRTOS.org/a00111.html). If a queue is created using + * xQueueCreateStatic() then the application writer must provide the memory that + * will get used by the queue. xQueueCreateStatic() therefore allows a queue to + * be created without using any dynamic memory allocation. + * + * https://www.FreeRTOS.org/Embedded-RTOS-Queues.html + * + * @param uxQueueLength The maximum number of items that the queue can contain. + * + * @param uxItemSize The number of bytes each item in the queue will require. + * Items are queued by copy, not by reference, so this is the number of bytes + * that will be copied for each posted item. Each item on the queue must be + * the same size. + * + * @param pucQueueStorage If uxItemSize is not zero then + * pucQueueStorage must point to a uint8_t array that is at least large + * enough to hold the maximum number of items that can be in the queue at any + * one time - which is ( uxQueueLength * uxItemsSize ) bytes. If uxItemSize is + * zero then pucQueueStorage can be NULL. + * + * @param pxQueueBuffer Must point to a variable of type StaticQueue_t, which + * will be used to hold the queue's data structure. + * + * @return If the queue is created then a handle to the created queue is + * returned. If pxQueueBuffer is NULL then NULL is returned. + * + * Example usage: + * @code{c} + * struct AMessage + * { + * char ucMessageID; + * char ucData[ 20 ]; + * }; + * + #define QUEUE_LENGTH 10 + #define ITEM_SIZE sizeof( uint32_t ) + * + * // xQueueBuffer will hold the queue structure. + * StaticQueue_t xQueueBuffer; + * + * // ucQueueStorage will hold the items posted to the queue. Must be at least + * // [(queue length) * ( queue item size)] bytes long. + * uint8_t ucQueueStorage[ QUEUE_LENGTH * ITEM_SIZE ]; + * + * void vATask( void *pvParameters ) + * { + * QueueHandle_t xQueue1; + * + * // Create a queue capable of containing 10 uint32_t values. + * xQueue1 = xQueueCreate( QUEUE_LENGTH, // The number of items the queue can hold. + * ITEM_SIZE // The size of each item in the queue + * &( ucQueueStorage[ 0 ] ), // The buffer that will hold the items in the queue. + * &xQueueBuffer ); // The buffer that will hold the queue structure. + * + * // The queue is guaranteed to be created successfully as no dynamic memory + * // allocation is used. Therefore xQueue1 is now a handle to a valid queue. + * + * // ... Rest of task code. + * } + * @endcode + * \defgroup xQueueCreateStatic xQueueCreateStatic + * \ingroup QueueManagement + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + #define xQueueCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxQueueBuffer ) xQueueGenericCreateStatic( ( uxQueueLength ), ( uxItemSize ), ( pucQueueStorage ), ( pxQueueBuffer ), ( queueQUEUE_TYPE_BASE ) ) +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/** + * queue. h + * @code{c} + * BaseType_t xQueueSendToToFront( + * QueueHandle_t xQueue, + * const void *pvItemToQueue, + * TickType_t xTicksToWait + * ); + * @endcode + * + * Post an item to the front of a queue. The item is queued by copy, not by + * reference. This function must not be called from an interrupt service + * routine. See xQueueSendFromISR () for an alternative which may be used + * in an ISR. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for space to become available on the queue, should it already + * be full. The call will return immediately if this is set to 0 and the + * queue is full. The time is defined in tick periods so the constant + * portTICK_PERIOD_MS should be used to convert to real time if this is required. + * + * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. + * + * Example usage: + * @code{c} + * struct AMessage + * { + * char ucMessageID; + * char ucData[ 20 ]; + * } xMessage; + * + * uint32_t ulVar = 10UL; + * + * void vATask( void *pvParameters ) + * { + * QueueHandle_t xQueue1, xQueue2; + * struct AMessage *pxMessage; + * + * // Create a queue capable of containing 10 uint32_t values. + * xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) ); + * + * // Create a queue capable of containing 10 pointers to AMessage structures. + * // These should be passed by pointer as they contain a lot of data. + * xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) ); + * + * // ... + * + * if( xQueue1 != 0 ) + * { + * // Send an uint32_t. Wait for 10 ticks for space to become + * // available if necessary. + * if( xQueueSendToFront( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS ) + * { + * // Failed to post the message, even after 10 ticks. + * } + * } + * + * if( xQueue2 != 0 ) + * { + * // Send a pointer to a struct AMessage object. Don't block if the + * // queue is already full. + * pxMessage = & xMessage; + * xQueueSendToFront( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 ); + * } + * + * // ... Rest of task code. + * } + * @endcode + * \defgroup xQueueSend xQueueSend + * \ingroup QueueManagement + */ +#define xQueueSendToFront( xQueue, pvItemToQueue, xTicksToWait ) \ + xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT ) + +/** + * queue. h + * @code{c} + * BaseType_t xQueueSendToBack( + * QueueHandle_t xQueue, + * const void *pvItemToQueue, + * TickType_t xTicksToWait + * ); + * @endcode + * + * This is a macro that calls xQueueGenericSend(). + * + * Post an item to the back of a queue. The item is queued by copy, not by + * reference. This function must not be called from an interrupt service + * routine. See xQueueSendFromISR () for an alternative which may be used + * in an ISR. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for space to become available on the queue, should it already + * be full. The call will return immediately if this is set to 0 and the queue + * is full. The time is defined in tick periods so the constant + * portTICK_PERIOD_MS should be used to convert to real time if this is required. + * + * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. + * + * Example usage: + * @code{c} + * struct AMessage + * { + * char ucMessageID; + * char ucData[ 20 ]; + * } xMessage; + * + * uint32_t ulVar = 10UL; + * + * void vATask( void *pvParameters ) + * { + * QueueHandle_t xQueue1, xQueue2; + * struct AMessage *pxMessage; + * + * // Create a queue capable of containing 10 uint32_t values. + * xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) ); + * + * // Create a queue capable of containing 10 pointers to AMessage structures. + * // These should be passed by pointer as they contain a lot of data. + * xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) ); + * + * // ... + * + * if( xQueue1 != 0 ) + * { + * // Send an uint32_t. Wait for 10 ticks for space to become + * // available if necessary. + * if( xQueueSendToBack( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS ) + * { + * // Failed to post the message, even after 10 ticks. + * } + * } + * + * if( xQueue2 != 0 ) + * { + * // Send a pointer to a struct AMessage object. Don't block if the + * // queue is already full. + * pxMessage = & xMessage; + * xQueueSendToBack( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 ); + * } + * + * // ... Rest of task code. + * } + * @endcode + * \defgroup xQueueSend xQueueSend + * \ingroup QueueManagement + */ +#define xQueueSendToBack( xQueue, pvItemToQueue, xTicksToWait ) \ + xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK ) + +/** + * queue. h + * @code{c} + * BaseType_t xQueueSend( + * QueueHandle_t xQueue, + * const void * pvItemToQueue, + * TickType_t xTicksToWait + * ); + * @endcode + * + * This is a macro that calls xQueueGenericSend(). It is included for + * backward compatibility with versions of FreeRTOS.org that did not + * include the xQueueSendToFront() and xQueueSendToBack() macros. It is + * equivalent to xQueueSendToBack(). + * + * Post an item on a queue. The item is queued by copy, not by reference. + * This function must not be called from an interrupt service routine. + * See xQueueSendFromISR () for an alternative which may be used in an ISR. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for space to become available on the queue, should it already + * be full. The call will return immediately if this is set to 0 and the + * queue is full. The time is defined in tick periods so the constant + * portTICK_PERIOD_MS should be used to convert to real time if this is required. + * + * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. + * + * Example usage: + * @code{c} + * struct AMessage + * { + * char ucMessageID; + * char ucData[ 20 ]; + * } xMessage; + * + * uint32_t ulVar = 10UL; + * + * void vATask( void *pvParameters ) + * { + * QueueHandle_t xQueue1, xQueue2; + * struct AMessage *pxMessage; + * + * // Create a queue capable of containing 10 uint32_t values. + * xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) ); + * + * // Create a queue capable of containing 10 pointers to AMessage structures. + * // These should be passed by pointer as they contain a lot of data. + * xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) ); + * + * // ... + * + * if( xQueue1 != 0 ) + * { + * // Send an uint32_t. Wait for 10 ticks for space to become + * // available if necessary. + * if( xQueueSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS ) + * { + * // Failed to post the message, even after 10 ticks. + * } + * } + * + * if( xQueue2 != 0 ) + * { + * // Send a pointer to a struct AMessage object. Don't block if the + * // queue is already full. + * pxMessage = & xMessage; + * xQueueSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 ); + * } + * + * // ... Rest of task code. + * } + * @endcode + * \defgroup xQueueSend xQueueSend + * \ingroup QueueManagement + */ +#define xQueueSend( xQueue, pvItemToQueue, xTicksToWait ) \ + xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK ) + +/** + * queue. h + * @code{c} + * BaseType_t xQueueOverwrite( + * QueueHandle_t xQueue, + * const void * pvItemToQueue + * ); + * @endcode + * + * Only for use with queues that have a length of one - so the queue is either + * empty or full. + * + * Post an item on a queue. If the queue is already full then overwrite the + * value held in the queue. The item is queued by copy, not by reference. + * + * This function must not be called from an interrupt service routine. + * See xQueueOverwriteFromISR () for an alternative which may be used in an ISR. + * + * @param xQueue The handle of the queue to which the data is being sent. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @return xQueueOverwrite() is a macro that calls xQueueGenericSend(), and + * therefore has the same return values as xQueueSendToFront(). However, pdPASS + * is the only value that can be returned because xQueueOverwrite() will write + * to the queue even when the queue is already full. + * + * Example usage: + * @code{c} + * + * void vFunction( void *pvParameters ) + * { + * QueueHandle_t xQueue; + * uint32_t ulVarToSend, ulValReceived; + * + * // Create a queue to hold one uint32_t value. It is strongly + * // recommended *not* to use xQueueOverwrite() on queues that can + * // contain more than one value, and doing so will trigger an assertion + * // if configASSERT() is defined. + * xQueue = xQueueCreate( 1, sizeof( uint32_t ) ); + * + * // Write the value 10 to the queue using xQueueOverwrite(). + * ulVarToSend = 10; + * xQueueOverwrite( xQueue, &ulVarToSend ); + * + * // Peeking the queue should now return 10, but leave the value 10 in + * // the queue. A block time of zero is used as it is known that the + * // queue holds a value. + * ulValReceived = 0; + * xQueuePeek( xQueue, &ulValReceived, 0 ); + * + * if( ulValReceived != 10 ) + * { + * // Error unless the item was removed by a different task. + * } + * + * // The queue is still full. Use xQueueOverwrite() to overwrite the + * // value held in the queue with 100. + * ulVarToSend = 100; + * xQueueOverwrite( xQueue, &ulVarToSend ); + * + * // This time read from the queue, leaving the queue empty once more. + * // A block time of 0 is used again. + * xQueueReceive( xQueue, &ulValReceived, 0 ); + * + * // The value read should be the last value written, even though the + * // queue was already full when the value was written. + * if( ulValReceived != 100 ) + * { + * // Error! + * } + * + * // ... + * } + * @endcode + * \defgroup xQueueOverwrite xQueueOverwrite + * \ingroup QueueManagement + */ +#define xQueueOverwrite( xQueue, pvItemToQueue ) \ + xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), 0, queueOVERWRITE ) + + +/** + * queue. h + * @code{c} + * BaseType_t xQueueGenericSend( + * QueueHandle_t xQueue, + * const void * pvItemToQueue, + * TickType_t xTicksToWait + * BaseType_t xCopyPosition + * ); + * @endcode + * + * It is preferred that the macros xQueueSend(), xQueueSendToFront() and + * xQueueSendToBack() are used in place of calling this function directly. + * + * Post an item on a queue. The item is queued by copy, not by reference. + * This function must not be called from an interrupt service routine. + * See xQueueSendFromISR () for an alternative which may be used in an ISR. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for space to become available on the queue, should it already + * be full. The call will return immediately if this is set to 0 and the + * queue is full. The time is defined in tick periods so the constant + * portTICK_PERIOD_MS should be used to convert to real time if this is required. + * + * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the + * item at the back of the queue, or queueSEND_TO_FRONT to place the item + * at the front of the queue (for high priority messages). + * + * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. + * + * Example usage: + * @code{c} + * struct AMessage + * { + * char ucMessageID; + * char ucData[ 20 ]; + * } xMessage; + * + * uint32_t ulVar = 10UL; + * + * void vATask( void *pvParameters ) + * { + * QueueHandle_t xQueue1, xQueue2; + * struct AMessage *pxMessage; + * + * // Create a queue capable of containing 10 uint32_t values. + * xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) ); + * + * // Create a queue capable of containing 10 pointers to AMessage structures. + * // These should be passed by pointer as they contain a lot of data. + * xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) ); + * + * // ... + * + * if( xQueue1 != 0 ) + * { + * // Send an uint32_t. Wait for 10 ticks for space to become + * // available if necessary. + * if( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10, queueSEND_TO_BACK ) != pdPASS ) + * { + * // Failed to post the message, even after 10 ticks. + * } + * } + * + * if( xQueue2 != 0 ) + * { + * // Send a pointer to a struct AMessage object. Don't block if the + * // queue is already full. + * pxMessage = & xMessage; + * xQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0, queueSEND_TO_BACK ); + * } + * + * // ... Rest of task code. + * } + * @endcode + * \defgroup xQueueSend xQueueSend + * \ingroup QueueManagement + */ +BaseType_t xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * @code{c} + * BaseType_t xQueuePeek( + * QueueHandle_t xQueue, + * void * const pvBuffer, + * TickType_t xTicksToWait + * ); + * @endcode + * + * Receive an item from a queue without removing the item from the queue. + * The item is received by copy so a buffer of adequate size must be + * provided. The number of bytes copied into the buffer was defined when + * the queue was created. + * + * Successfully received items remain on the queue so will be returned again + * by the next call, or a call to xQueueReceive(). + * + * This macro must not be used in an interrupt service routine. See + * xQueuePeekFromISR() for an alternative that can be called from an interrupt + * service routine. + * + * @param xQueue The handle to the queue from which the item is to be + * received. + * + * @param pvBuffer Pointer to the buffer into which the received item will + * be copied. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for an item to receive should the queue be empty at the time + * of the call. The time is defined in tick periods so the constant + * portTICK_PERIOD_MS should be used to convert to real time if this is required. + * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue + * is empty. + * + * @return pdTRUE if an item was successfully received from the queue, + * otherwise pdFALSE. + * + * Example usage: + * @code{c} + * struct AMessage + * { + * char ucMessageID; + * char ucData[ 20 ]; + * } xMessage; + * + * QueueHandle_t xQueue; + * + * // Task to create a queue and post a value. + * void vATask( void *pvParameters ) + * { + * struct AMessage *pxMessage; + * + * // Create a queue capable of containing 10 pointers to AMessage structures. + * // These should be passed by pointer as they contain a lot of data. + * xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) ); + * if( xQueue == 0 ) + * { + * // Failed to create the queue. + * } + * + * // ... + * + * // Send a pointer to a struct AMessage object. Don't block if the + * // queue is already full. + * pxMessage = & xMessage; + * xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 ); + * + * // ... Rest of task code. + * } + * + * // Task to peek the data from the queue. + * void vADifferentTask( void *pvParameters ) + * { + * struct AMessage *pxRxedMessage; + * + * if( xQueue != 0 ) + * { + * // Peek a message on the created queue. Block for 10 ticks if a + * // message is not immediately available. + * if( xQueuePeek( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) ) + * { + * // pcRxedMessage now points to the struct AMessage variable posted + * // by vATask, but the item still remains on the queue. + * } + * } + * + * // ... Rest of task code. + * } + * @endcode + * \defgroup xQueuePeek xQueuePeek + * \ingroup QueueManagement + */ +BaseType_t xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * @code{c} + * BaseType_t xQueuePeekFromISR( + * QueueHandle_t xQueue, + * void *pvBuffer, + * ); + * @endcode + * + * A version of xQueuePeek() that can be called from an interrupt service + * routine (ISR). + * + * Receive an item from a queue without removing the item from the queue. + * The item is received by copy so a buffer of adequate size must be + * provided. The number of bytes copied into the buffer was defined when + * the queue was created. + * + * Successfully received items remain on the queue so will be returned again + * by the next call, or a call to xQueueReceive(). + * + * @param xQueue The handle to the queue from which the item is to be + * received. + * + * @param pvBuffer Pointer to the buffer into which the received item will + * be copied. + * + * @return pdTRUE if an item was successfully received from the queue, + * otherwise pdFALSE. + * + * \defgroup xQueuePeekFromISR xQueuePeekFromISR + * \ingroup QueueManagement + */ +BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, + void * const pvBuffer ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * @code{c} + * BaseType_t xQueueReceive( + * QueueHandle_t xQueue, + * void *pvBuffer, + * TickType_t xTicksToWait + * ); + * @endcode + * + * Receive an item from a queue. The item is received by copy so a buffer of + * adequate size must be provided. The number of bytes copied into the buffer + * was defined when the queue was created. + * + * Successfully received items are removed from the queue. + * + * This function must not be used in an interrupt service routine. See + * xQueueReceiveFromISR for an alternative that can. + * + * @param xQueue The handle to the queue from which the item is to be + * received. + * + * @param pvBuffer Pointer to the buffer into which the received item will + * be copied. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for an item to receive should the queue be empty at the time + * of the call. xQueueReceive() will return immediately if xTicksToWait + * is zero and the queue is empty. The time is defined in tick periods so the + * constant portTICK_PERIOD_MS should be used to convert to real time if this is + * required. + * + * @return pdTRUE if an item was successfully received from the queue, + * otherwise pdFALSE. + * + * Example usage: + * @code{c} + * struct AMessage + * { + * char ucMessageID; + * char ucData[ 20 ]; + * } xMessage; + * + * QueueHandle_t xQueue; + * + * // Task to create a queue and post a value. + * void vATask( void *pvParameters ) + * { + * struct AMessage *pxMessage; + * + * // Create a queue capable of containing 10 pointers to AMessage structures. + * // These should be passed by pointer as they contain a lot of data. + * xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) ); + * if( xQueue == 0 ) + * { + * // Failed to create the queue. + * } + * + * // ... + * + * // Send a pointer to a struct AMessage object. Don't block if the + * // queue is already full. + * pxMessage = & xMessage; + * xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 ); + * + * // ... Rest of task code. + * } + * + * // Task to receive from the queue. + * void vADifferentTask( void *pvParameters ) + * { + * struct AMessage *pxRxedMessage; + * + * if( xQueue != 0 ) + * { + * // Receive a message on the created queue. Block for 10 ticks if a + * // message is not immediately available. + * if( xQueueReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) ) + * { + * // pcRxedMessage now points to the struct AMessage variable posted + * // by vATask. + * } + * } + * + * // ... Rest of task code. + * } + * @endcode + * \defgroup xQueueReceive xQueueReceive + * \ingroup QueueManagement + */ +BaseType_t xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * @code{c} + * UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ); + * @endcode + * + * Return the number of messages stored in a queue. + * + * @param xQueue A handle to the queue being queried. + * + * @return The number of messages available in the queue. + * + * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting + * \ingroup QueueManagement + */ +UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * @code{c} + * UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ); + * @endcode + * + * Return the number of free spaces available in a queue. This is equal to the + * number of items that can be sent to the queue before the queue becomes full + * if no items are removed. + * + * @param xQueue A handle to the queue being queried. + * + * @return The number of spaces available in the queue. + * + * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting + * \ingroup QueueManagement + */ +UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * @code{c} + * void vQueueDelete( QueueHandle_t xQueue ); + * @endcode + * + * Delete a queue - freeing all the memory allocated for storing of items + * placed on the queue. + * + * @param xQueue A handle to the queue to be deleted. + * + * \defgroup vQueueDelete vQueueDelete + * \ingroup QueueManagement + */ +void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * @code{c} + * BaseType_t xQueueSendToFrontFromISR( + * QueueHandle_t xQueue, + * const void *pvItemToQueue, + * BaseType_t *pxHigherPriorityTaskWoken + * ); + * @endcode + * + * This is a macro that calls xQueueGenericSendFromISR(). + * + * Post an item to the front of a queue. It is safe to use this macro from + * within an interrupt service routine. + * + * Items are queued by copy not reference so it is preferable to only + * queue small items, especially when called from an ISR. In most cases + * it would be preferable to store a pointer to the item being queued. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xQueueSendToFromFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return pdTRUE if the data was successfully sent to the queue, otherwise + * errQUEUE_FULL. + * + * Example usage for buffered IO (where the ISR can obtain more than one value + * per call): + * @code{c} + * void vBufferISR( void ) + * { + * char cIn; + * BaseType_t xHigherPrioritTaskWoken; + * + * // We have not woken a task at the start of the ISR. + * xHigherPriorityTaskWoken = pdFALSE; + * + * // Loop until the buffer is empty. + * do + * { + * // Obtain a byte from the buffer. + * cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS ); + * + * // Post the byte. + * xQueueSendToFrontFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken ); + * + * } while( portINPUT_BYTE( BUFFER_COUNT ) ); + * + * // Now the buffer is empty we can switch context if necessary. + * if( xHigherPriorityTaskWoken ) + * { + * taskYIELD (); + * } + * } + * @endcode + * + * \defgroup xQueueSendFromISR xQueueSendFromISR + * \ingroup QueueManagement + */ +#define xQueueSendToFrontFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \ + xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_FRONT ) + + +/** + * queue. h + * @code{c} + * BaseType_t xQueueSendToBackFromISR( + * QueueHandle_t xQueue, + * const void *pvItemToQueue, + * BaseType_t *pxHigherPriorityTaskWoken + * ); + * @endcode + * + * This is a macro that calls xQueueGenericSendFromISR(). + * + * Post an item to the back of a queue. It is safe to use this macro from + * within an interrupt service routine. + * + * Items are queued by copy not reference so it is preferable to only + * queue small items, especially when called from an ISR. In most cases + * it would be preferable to store a pointer to the item being queued. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param pxHigherPriorityTaskWoken xQueueSendToBackFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xQueueSendToBackFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return pdTRUE if the data was successfully sent to the queue, otherwise + * errQUEUE_FULL. + * + * Example usage for buffered IO (where the ISR can obtain more than one value + * per call): + * @code{c} + * void vBufferISR( void ) + * { + * char cIn; + * BaseType_t xHigherPriorityTaskWoken; + * + * // We have not woken a task at the start of the ISR. + * xHigherPriorityTaskWoken = pdFALSE; + * + * // Loop until the buffer is empty. + * do + * { + * // Obtain a byte from the buffer. + * cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS ); + * + * // Post the byte. + * xQueueSendToBackFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken ); + * + * } while( portINPUT_BYTE( BUFFER_COUNT ) ); + * + * // Now the buffer is empty we can switch context if necessary. + * if( xHigherPriorityTaskWoken ) + * { + * taskYIELD (); + * } + * } + * @endcode + * + * \defgroup xQueueSendFromISR xQueueSendFromISR + * \ingroup QueueManagement + */ +#define xQueueSendToBackFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \ + xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK ) + +/** + * queue. h + * @code{c} + * BaseType_t xQueueOverwriteFromISR( + * QueueHandle_t xQueue, + * const void * pvItemToQueue, + * BaseType_t *pxHigherPriorityTaskWoken + * ); + * @endcode + * + * A version of xQueueOverwrite() that can be used in an interrupt service + * routine (ISR). + * + * Only for use with queues that can hold a single item - so the queue is either + * empty or full. + * + * Post an item on a queue. If the queue is already full then overwrite the + * value held in the queue. The item is queued by copy, not by reference. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param pxHigherPriorityTaskWoken xQueueOverwriteFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xQueueOverwriteFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return xQueueOverwriteFromISR() is a macro that calls + * xQueueGenericSendFromISR(), and therefore has the same return values as + * xQueueSendToFrontFromISR(). However, pdPASS is the only value that can be + * returned because xQueueOverwriteFromISR() will write to the queue even when + * the queue is already full. + * + * Example usage: + * @code{c} + * + * QueueHandle_t xQueue; + * + * void vFunction( void *pvParameters ) + * { + * // Create a queue to hold one uint32_t value. It is strongly + * // recommended *not* to use xQueueOverwriteFromISR() on queues that can + * // contain more than one value, and doing so will trigger an assertion + * // if configASSERT() is defined. + * xQueue = xQueueCreate( 1, sizeof( uint32_t ) ); + * } + * + * void vAnInterruptHandler( void ) + * { + * // xHigherPriorityTaskWoken must be set to pdFALSE before it is used. + * BaseType_t xHigherPriorityTaskWoken = pdFALSE; + * uint32_t ulVarToSend, ulValReceived; + * + * // Write the value 10 to the queue using xQueueOverwriteFromISR(). + * ulVarToSend = 10; + * xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken ); + * + * // The queue is full, but calling xQueueOverwriteFromISR() again will still + * // pass because the value held in the queue will be overwritten with the + * // new value. + * ulVarToSend = 100; + * xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken ); + * + * // Reading from the queue will now return 100. + * + * // ... + * + * if( xHigherPrioritytaskWoken == pdTRUE ) + * { + * // Writing to the queue caused a task to unblock and the unblocked task + * // has a priority higher than or equal to the priority of the currently + * // executing task (the task this interrupt interrupted). Perform a context + * // switch so this interrupt returns directly to the unblocked task. + * portYIELD_FROM_ISR(); // or portEND_SWITCHING_ISR() depending on the port. + * } + * } + * @endcode + * \defgroup xQueueOverwriteFromISR xQueueOverwriteFromISR + * \ingroup QueueManagement + */ +#define xQueueOverwriteFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \ + xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueOVERWRITE ) + +/** + * queue. h + * @code{c} + * BaseType_t xQueueSendFromISR( + * QueueHandle_t xQueue, + * const void *pvItemToQueue, + * BaseType_t *pxHigherPriorityTaskWoken + * ); + * @endcode + * + * This is a macro that calls xQueueGenericSendFromISR(). It is included + * for backward compatibility with versions of FreeRTOS.org that did not + * include the xQueueSendToBackFromISR() and xQueueSendToFrontFromISR() + * macros. + * + * Post an item to the back of a queue. It is safe to use this function from + * within an interrupt service routine. + * + * Items are queued by copy not reference so it is preferable to only + * queue small items, especially when called from an ISR. In most cases + * it would be preferable to store a pointer to the item being queued. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param pxHigherPriorityTaskWoken xQueueSendFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xQueueSendFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return pdTRUE if the data was successfully sent to the queue, otherwise + * errQUEUE_FULL. + * + * Example usage for buffered IO (where the ISR can obtain more than one value + * per call): + * @code{c} + * void vBufferISR( void ) + * { + * char cIn; + * BaseType_t xHigherPriorityTaskWoken; + * + * // We have not woken a task at the start of the ISR. + * xHigherPriorityTaskWoken = pdFALSE; + * + * // Loop until the buffer is empty. + * do + * { + * // Obtain a byte from the buffer. + * cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS ); + * + * // Post the byte. + * xQueueSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken ); + * + * } while( portINPUT_BYTE( BUFFER_COUNT ) ); + * + * // Now the buffer is empty we can switch context if necessary. + * if( xHigherPriorityTaskWoken ) + * { + * // Actual macro used here is port specific. + * portYIELD_FROM_ISR (); + * } + * } + * @endcode + * + * \defgroup xQueueSendFromISR xQueueSendFromISR + * \ingroup QueueManagement + */ +#define xQueueSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \ + xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK ) + +/** + * queue. h + * @code{c} + * BaseType_t xQueueGenericSendFromISR( + * QueueHandle_t xQueue, + * const void *pvItemToQueue, + * BaseType_t *pxHigherPriorityTaskWoken, + * BaseType_t xCopyPosition + * ); + * @endcode + * + * It is preferred that the macros xQueueSendFromISR(), + * xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place + * of calling this function directly. xQueueGiveFromISR() is an + * equivalent for use by semaphores that don't actually copy any data. + * + * Post an item on a queue. It is safe to use this function from within an + * interrupt service routine. + * + * Items are queued by copy not reference so it is preferable to only + * queue small items, especially when called from an ISR. In most cases + * it would be preferable to store a pointer to the item being queued. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param pxHigherPriorityTaskWoken xQueueGenericSendFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xQueueGenericSendFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the + * item at the back of the queue, or queueSEND_TO_FRONT to place the item + * at the front of the queue (for high priority messages). + * + * @return pdTRUE if the data was successfully sent to the queue, otherwise + * errQUEUE_FULL. + * + * Example usage for buffered IO (where the ISR can obtain more than one value + * per call): + * @code{c} + * void vBufferISR( void ) + * { + * char cIn; + * BaseType_t xHigherPriorityTaskWokenByPost; + * + * // We have not woken a task at the start of the ISR. + * xHigherPriorityTaskWokenByPost = pdFALSE; + * + * // Loop until the buffer is empty. + * do + * { + * // Obtain a byte from the buffer. + * cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS ); + * + * // Post each byte. + * xQueueGenericSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWokenByPost, queueSEND_TO_BACK ); + * + * } while( portINPUT_BYTE( BUFFER_COUNT ) ); + * + * // Now the buffer is empty we can switch context if necessary. Note that the + * // name of the yield function required is port specific. + * if( xHigherPriorityTaskWokenByPost ) + * { + * portYIELD_FROM_ISR(); + * } + * } + * @endcode + * + * \defgroup xQueueSendFromISR xQueueSendFromISR + * \ingroup QueueManagement + */ +BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, + const void * const pvItemToQueue, + BaseType_t * const pxHigherPriorityTaskWoken, + const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION; +BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, + BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * @code{c} + * BaseType_t xQueueReceiveFromISR( + * QueueHandle_t xQueue, + * void *pvBuffer, + * BaseType_t *pxTaskWoken + * ); + * @endcode + * + * Receive an item from a queue. It is safe to use this function from within an + * interrupt service routine. + * + * @param xQueue The handle to the queue from which the item is to be + * received. + * + * @param pvBuffer Pointer to the buffer into which the received item will + * be copied. + * + * @param pxTaskWoken A task may be blocked waiting for space to become + * available on the queue. If xQueueReceiveFromISR causes such a task to + * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will + * remain unchanged. + * + * @return pdTRUE if an item was successfully received from the queue, + * otherwise pdFALSE. + * + * Example usage: + * @code{c} + * + * QueueHandle_t xQueue; + * + * // Function to create a queue and post some values. + * void vAFunction( void *pvParameters ) + * { + * char cValueToPost; + * const TickType_t xTicksToWait = ( TickType_t )0xff; + * + * // Create a queue capable of containing 10 characters. + * xQueue = xQueueCreate( 10, sizeof( char ) ); + * if( xQueue == 0 ) + * { + * // Failed to create the queue. + * } + * + * // ... + * + * // Post some characters that will be used within an ISR. If the queue + * // is full then this task will block for xTicksToWait ticks. + * cValueToPost = 'a'; + * xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait ); + * cValueToPost = 'b'; + * xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait ); + * + * // ... keep posting characters ... this task may block when the queue + * // becomes full. + * + * cValueToPost = 'c'; + * xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait ); + * } + * + * // ISR that outputs all the characters received on the queue. + * void vISR_Routine( void ) + * { + * BaseType_t xTaskWokenByReceive = pdFALSE; + * char cRxedChar; + * + * while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) ) + * { + * // A character was received. Output the character now. + * vOutputCharacter( cRxedChar ); + * + * // If removing the character from the queue woke the task that was + * // posting onto the queue cTaskWokenByReceive will have been set to + * // pdTRUE. No matter how many times this loop iterates only one + * // task will be woken. + * } + * + * if( cTaskWokenByPost != ( char ) pdFALSE; + * { + * taskYIELD (); + * } + * } + * @endcode + * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR + * \ingroup QueueManagement + */ +BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, + void * const pvBuffer, + BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/* + * Utilities to query queues that are safe to use from an ISR. These utilities + * should be used only from witin an ISR, or within a critical section. + */ +BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + +/* + * The functions defined above are for passing data to and from tasks. The + * functions below are the equivalents for passing data to and from + * co-routines. + * + * These functions are called from the co-routine macro implementation and + * should not be called directly from application code. Instead use the macro + * wrappers defined within croutine.h. + */ +BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, + const void * pvItemToQueue, + BaseType_t xCoRoutinePreviouslyWoken ); +BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, + void * pvBuffer, + BaseType_t * pxTaskWoken ); +BaseType_t xQueueCRSend( QueueHandle_t xQueue, + const void * pvItemToQueue, + TickType_t xTicksToWait ); +BaseType_t xQueueCRReceive( QueueHandle_t xQueue, + void * pvBuffer, + TickType_t xTicksToWait ); + +/* + * For internal use only. Use xSemaphoreCreateMutex(), + * xSemaphoreCreateCounting() or xSemaphoreGetMutexHolder() instead of calling + * these functions directly. + */ +QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION; +QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, + StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION; +QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, + const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION; +QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, + const UBaseType_t uxInitialCount, + StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION; +BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION; +TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION; + +/* + * For internal use only. Use xSemaphoreTakeMutexRecursive() or + * xSemaphoreGiveMutexRecursive() instead of calling these functions directly. + */ +BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION; + +/* + * Reset a queue back to its original empty state. The return value is now + * obsolete and is always set to pdPASS. + */ +#define xQueueReset( xQueue ) xQueueGenericReset( xQueue, pdFALSE ) + +/* + * The registry is provided as a means for kernel aware debuggers to + * locate queues, semaphores and mutexes. Call vQueueAddToRegistry() add + * a queue, semaphore or mutex handle to the registry if you want the handle + * to be available to a kernel aware debugger. If you are not using a kernel + * aware debugger then this function can be ignored. + * + * configQUEUE_REGISTRY_SIZE defines the maximum number of handles the + * registry can hold. configQUEUE_REGISTRY_SIZE must be greater than 0 + * within FreeRTOSConfig.h for the registry to be available. Its value + * does not effect the number of queues, semaphores and mutexes that can be + * created - just the number that the registry can hold. + * + * If vQueueAddToRegistry is called more than once with the same xQueue + * parameter, the registry will store the pcQueueName parameter from the + * most recent call to vQueueAddToRegistry. + * + * @param xQueue The handle of the queue being added to the registry. This + * is the handle returned by a call to xQueueCreate(). Semaphore and mutex + * handles can also be passed in here. + * + * @param pcQueueName The name to be associated with the handle. This is the + * name that the kernel aware debugger will display. The queue registry only + * stores a pointer to the string - so the string must be persistent (global or + * preferably in ROM/Flash), not on the stack. + */ +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + void vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcQueueName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ +#endif + +/* + * The registry is provided as a means for kernel aware debuggers to + * locate queues, semaphores and mutexes. Call vQueueAddToRegistry() add + * a queue, semaphore or mutex handle to the registry if you want the handle + * to be available to a kernel aware debugger, and vQueueUnregisterQueue() to + * remove the queue, semaphore or mutex from the register. If you are not using + * a kernel aware debugger then this function can be ignored. + * + * @param xQueue The handle of the queue being removed from the registry. + */ +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + void vQueueUnregisterQueue( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +#endif + +/* + * The queue registry is provided as a means for kernel aware debuggers to + * locate queues, semaphores and mutexes. Call pcQueueGetName() to look + * up and return the name of a queue in the queue registry from the queue's + * handle. + * + * @param xQueue The handle of the queue the name of which will be returned. + * @return If the queue is in the registry then a pointer to the name of the + * queue is returned. If the queue is not in the registry then NULL is + * returned. + */ +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + const char * pcQueueGetName( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ +#endif + +/* + * Generic version of the function used to create a queue using dynamic memory + * allocation. This is called by other functions and macros that create other + * RTOS objects that use the queue structure as their base. + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + const uint8_t ucQueueType ) PRIVILEGED_FUNCTION; +#endif + +/* + * Generic version of the function used to create a queue using dynamic memory + * allocation. This is called by other functions and macros that create other + * RTOS objects that use the queue structure as their base. + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + uint8_t * pucQueueStorage, + StaticQueue_t * pxStaticQueue, + const uint8_t ucQueueType ) PRIVILEGED_FUNCTION; +#endif + +/* + * Queue sets provide a mechanism to allow a task to block (pend) on a read + * operation from multiple queues or semaphores simultaneously. + * + * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this + * function. + * + * A queue set must be explicitly created using a call to xQueueCreateSet() + * before it can be used. Once created, standard FreeRTOS queues and semaphores + * can be added to the set using calls to xQueueAddToSet(). + * xQueueSelectFromSet() is then used to determine which, if any, of the queues + * or semaphores contained in the set is in a state where a queue read or + * semaphore take operation would be successful. + * + * Note 1: See the documentation on https://www.FreeRTOS.org/RTOS-queue-sets.html + * for reasons why queue sets are very rarely needed in practice as there are + * simpler methods of blocking on multiple objects. + * + * Note 2: Blocking on a queue set that contains a mutex will not cause the + * mutex holder to inherit the priority of the blocked task. + * + * Note 3: An additional 4 bytes of RAM is required for each space in a every + * queue added to a queue set. Therefore counting semaphores that have a high + * maximum count value should not be added to a queue set. + * + * Note 4: A receive (in the case of a queue) or take (in the case of a + * semaphore) operation must not be performed on a member of a queue set unless + * a call to xQueueSelectFromSet() has first returned a handle to that set member. + * + * @param uxEventQueueLength Queue sets store events that occur on + * the queues and semaphores contained in the set. uxEventQueueLength specifies + * the maximum number of events that can be queued at once. To be absolutely + * certain that events are not lost uxEventQueueLength should be set to the + * total sum of the length of the queues added to the set, where binary + * semaphores and mutexes have a length of 1, and counting semaphores have a + * length set by their maximum count value. Examples: + * + If a queue set is to hold a queue of length 5, another queue of length 12, + * and a binary semaphore, then uxEventQueueLength should be set to + * (5 + 12 + 1), or 18. + * + If a queue set is to hold three binary semaphores then uxEventQueueLength + * should be set to (1 + 1 + 1 ), or 3. + * + If a queue set is to hold a counting semaphore that has a maximum count of + * 5, and a counting semaphore that has a maximum count of 3, then + * uxEventQueueLength should be set to (5 + 3), or 8. + * + * @return If the queue set is created successfully then a handle to the created + * queue set is returned. Otherwise NULL is returned. + */ +QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION; + +/* + * Adds a queue or semaphore to a queue set that was previously created by a + * call to xQueueCreateSet(). + * + * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this + * function. + * + * Note 1: A receive (in the case of a queue) or take (in the case of a + * semaphore) operation must not be performed on a member of a queue set unless + * a call to xQueueSelectFromSet() has first returned a handle to that set member. + * + * @param xQueueOrSemaphore The handle of the queue or semaphore being added to + * the queue set (cast to an QueueSetMemberHandle_t type). + * + * @param xQueueSet The handle of the queue set to which the queue or semaphore + * is being added. + * + * @return If the queue or semaphore was successfully added to the queue set + * then pdPASS is returned. If the queue could not be successfully added to the + * queue set because it is already a member of a different queue set then pdFAIL + * is returned. + */ +BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION; + +/* + * Removes a queue or semaphore from a queue set. A queue or semaphore can only + * be removed from a set if the queue or semaphore is empty. + * + * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this + * function. + * + * @param xQueueOrSemaphore The handle of the queue or semaphore being removed + * from the queue set (cast to an QueueSetMemberHandle_t type). + * + * @param xQueueSet The handle of the queue set in which the queue or semaphore + * is included. + * + * @return If the queue or semaphore was successfully removed from the queue set + * then pdPASS is returned. If the queue was not in the queue set, or the + * queue (or semaphore) was not empty, then pdFAIL is returned. + */ +BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION; + +/* + * xQueueSelectFromSet() selects from the members of a queue set a queue or + * semaphore that either contains data (in the case of a queue) or is available + * to take (in the case of a semaphore). xQueueSelectFromSet() effectively + * allows a task to block (pend) on a read operation on all the queues and + * semaphores in a queue set simultaneously. + * + * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this + * function. + * + * Note 1: See the documentation on https://www.FreeRTOS.org/RTOS-queue-sets.html + * for reasons why queue sets are very rarely needed in practice as there are + * simpler methods of blocking on multiple objects. + * + * Note 2: Blocking on a queue set that contains a mutex will not cause the + * mutex holder to inherit the priority of the blocked task. + * + * Note 3: A receive (in the case of a queue) or take (in the case of a + * semaphore) operation must not be performed on a member of a queue set unless + * a call to xQueueSelectFromSet() has first returned a handle to that set member. + * + * @param xQueueSet The queue set on which the task will (potentially) block. + * + * @param xTicksToWait The maximum time, in ticks, that the calling task will + * remain in the Blocked state (with other tasks executing) to wait for a member + * of the queue set to be ready for a successful queue read or semaphore take + * operation. + * + * @return xQueueSelectFromSet() will return the handle of a queue (cast to + * a QueueSetMemberHandle_t type) contained in the queue set that contains data, + * or the handle of a semaphore (cast to a QueueSetMemberHandle_t type) contained + * in the queue set that is available, or NULL if no such queue or semaphore + * exists before before the specified block time expires. + */ +QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/* + * A version of xQueueSelectFromSet() that can be used from an ISR. + */ +QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION; + +/* Not public API functions. */ +void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, + TickType_t xTicksToWait, + const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION; +BaseType_t xQueueGenericReset( QueueHandle_t xQueue, + BaseType_t xNewQueue ) PRIVILEGED_FUNCTION; +void vQueueSetQueueNumber( QueueHandle_t xQueue, + UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION; +UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* QUEUE_H */ diff --git a/hw-libs/freertos/include/semphr.h b/hw-libs/freertos/include/semphr.h new file mode 100644 index 000000000..d28d4a045 --- /dev/null +++ b/hw-libs/freertos/include/semphr.h @@ -0,0 +1,1189 @@ +/* + * FreeRTOS Kernel V10.4.6 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef SEMAPHORE_H +#define SEMAPHORE_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h" must appear in source files before "include semphr.h" +#endif + +#include "queue.h" + +typedef QueueHandle_t SemaphoreHandle_t; + +#define semBINARY_SEMAPHORE_QUEUE_LENGTH ( ( uint8_t ) 1U ) +#define semSEMAPHORE_QUEUE_ITEM_LENGTH ( ( uint8_t ) 0U ) +#define semGIVE_BLOCK_TIME ( ( TickType_t ) 0U ) + + +/** + * semphr. h + * @code{c} + * vSemaphoreCreateBinary( SemaphoreHandle_t xSemaphore ); + * @endcode + * + * In many usage scenarios it is faster and more memory efficient to use a + * direct to task notification in place of a binary semaphore! + * https://www.FreeRTOS.org/RTOS-task-notifications.html + * + * This old vSemaphoreCreateBinary() macro is now deprecated in favour of the + * xSemaphoreCreateBinary() function. Note that binary semaphores created using + * the vSemaphoreCreateBinary() macro are created in a state such that the + * first call to 'take' the semaphore would pass, whereas binary semaphores + * created using xSemaphoreCreateBinary() are created in a state such that the + * the semaphore must first be 'given' before it can be 'taken'. + * + * Macro that implements a semaphore by using the existing queue mechanism. + * The queue length is 1 as this is a binary semaphore. The data size is 0 + * as we don't want to actually store any data - we just want to know if the + * queue is empty or full. + * + * This type of semaphore can be used for pure synchronisation between tasks or + * between an interrupt and a task. The semaphore need not be given back once + * obtained, so one task/interrupt can continuously 'give' the semaphore while + * another continuously 'takes' the semaphore. For this reason this type of + * semaphore does not use a priority inheritance mechanism. For an alternative + * that does use priority inheritance see xSemaphoreCreateMutex(). + * + * @param xSemaphore Handle to the created semaphore. Should be of type SemaphoreHandle_t. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xSemaphore = NULL; + * + * void vATask( void * pvParameters ) + * { + * // Semaphore cannot be used before a call to vSemaphoreCreateBinary (). + * // This is a macro so pass the variable in directly. + * vSemaphoreCreateBinary( xSemaphore ); + * + * if( xSemaphore != NULL ) + * { + * // The semaphore was created successfully. + * // The semaphore can now be used. + * } + * } + * @endcode + * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary + * \ingroup Semaphores + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + #define vSemaphoreCreateBinary( xSemaphore ) \ + { \ + ( xSemaphore ) = xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE ); \ + if( ( xSemaphore ) != NULL ) \ + { \ + ( void ) xSemaphoreGive( ( xSemaphore ) ); \ + } \ + } +#endif + +/** + * semphr. h + * @code{c} + * SemaphoreHandle_t xSemaphoreCreateBinary( void ); + * @endcode + * + * Creates a new binary semaphore instance, and returns a handle by which the + * new semaphore can be referenced. + * + * In many usage scenarios it is faster and more memory efficient to use a + * direct to task notification in place of a binary semaphore! + * https://www.FreeRTOS.org/RTOS-task-notifications.html + * + * Internally, within the FreeRTOS implementation, binary semaphores use a block + * of memory, in which the semaphore structure is stored. If a binary semaphore + * is created using xSemaphoreCreateBinary() then the required memory is + * automatically dynamically allocated inside the xSemaphoreCreateBinary() + * function. (see https://www.FreeRTOS.org/a00111.html). If a binary semaphore + * is created using xSemaphoreCreateBinaryStatic() then the application writer + * must provide the memory. xSemaphoreCreateBinaryStatic() therefore allows a + * binary semaphore to be created without using any dynamic memory allocation. + * + * The old vSemaphoreCreateBinary() macro is now deprecated in favour of this + * xSemaphoreCreateBinary() function. Note that binary semaphores created using + * the vSemaphoreCreateBinary() macro are created in a state such that the + * first call to 'take' the semaphore would pass, whereas binary semaphores + * created using xSemaphoreCreateBinary() are created in a state such that the + * the semaphore must first be 'given' before it can be 'taken'. + * + * This type of semaphore can be used for pure synchronisation between tasks or + * between an interrupt and a task. The semaphore need not be given back once + * obtained, so one task/interrupt can continuously 'give' the semaphore while + * another continuously 'takes' the semaphore. For this reason this type of + * semaphore does not use a priority inheritance mechanism. For an alternative + * that does use priority inheritance see xSemaphoreCreateMutex(). + * + * @return Handle to the created semaphore, or NULL if the memory required to + * hold the semaphore's data structures could not be allocated. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xSemaphore = NULL; + * + * void vATask( void * pvParameters ) + * { + * // Semaphore cannot be used before a call to xSemaphoreCreateBinary(). + * // This is a macro so pass the variable in directly. + * xSemaphore = xSemaphoreCreateBinary(); + * + * if( xSemaphore != NULL ) + * { + * // The semaphore was created successfully. + * // The semaphore can now be used. + * } + * } + * @endcode + * \defgroup xSemaphoreCreateBinary xSemaphoreCreateBinary + * \ingroup Semaphores + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + #define xSemaphoreCreateBinary() xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE ) +#endif + +/** + * semphr. h + * @code{c} + * SemaphoreHandle_t xSemaphoreCreateBinaryStatic( StaticSemaphore_t *pxSemaphoreBuffer ); + * @endcode + * + * Creates a new binary semaphore instance, and returns a handle by which the + * new semaphore can be referenced. + * + * NOTE: In many usage scenarios it is faster and more memory efficient to use a + * direct to task notification in place of a binary semaphore! + * https://www.FreeRTOS.org/RTOS-task-notifications.html + * + * Internally, within the FreeRTOS implementation, binary semaphores use a block + * of memory, in which the semaphore structure is stored. If a binary semaphore + * is created using xSemaphoreCreateBinary() then the required memory is + * automatically dynamically allocated inside the xSemaphoreCreateBinary() + * function. (see https://www.FreeRTOS.org/a00111.html). If a binary semaphore + * is created using xSemaphoreCreateBinaryStatic() then the application writer + * must provide the memory. xSemaphoreCreateBinaryStatic() therefore allows a + * binary semaphore to be created without using any dynamic memory allocation. + * + * This type of semaphore can be used for pure synchronisation between tasks or + * between an interrupt and a task. The semaphore need not be given back once + * obtained, so one task/interrupt can continuously 'give' the semaphore while + * another continuously 'takes' the semaphore. For this reason this type of + * semaphore does not use a priority inheritance mechanism. For an alternative + * that does use priority inheritance see xSemaphoreCreateMutex(). + * + * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t, + * which will then be used to hold the semaphore's data structure, removing the + * need for the memory to be allocated dynamically. + * + * @return If the semaphore is created then a handle to the created semaphore is + * returned. If pxSemaphoreBuffer is NULL then NULL is returned. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xSemaphore = NULL; + * StaticSemaphore_t xSemaphoreBuffer; + * + * void vATask( void * pvParameters ) + * { + * // Semaphore cannot be used before a call to xSemaphoreCreateBinary(). + * // The semaphore's data structures will be placed in the xSemaphoreBuffer + * // variable, the address of which is passed into the function. The + * // function's parameter is not NULL, so the function will not attempt any + * // dynamic memory allocation, and therefore the function will not return + * // return NULL. + * xSemaphore = xSemaphoreCreateBinary( &xSemaphoreBuffer ); + * + * // Rest of task code goes here. + * } + * @endcode + * \defgroup xSemaphoreCreateBinaryStatic xSemaphoreCreateBinaryStatic + * \ingroup Semaphores + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + #define xSemaphoreCreateBinaryStatic( pxStaticSemaphore ) xQueueGenericCreateStatic( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticSemaphore, queueQUEUE_TYPE_BINARY_SEMAPHORE ) +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/** + * semphr. h + * @code{c} + * xSemaphoreTake( + * SemaphoreHandle_t xSemaphore, + * TickType_t xBlockTime + * ); + * @endcode + * + * Macro to obtain a semaphore. The semaphore must have previously been + * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or + * xSemaphoreCreateCounting(). + * + * @param xSemaphore A handle to the semaphore being taken - obtained when + * the semaphore was created. + * + * @param xBlockTime The time in ticks to wait for the semaphore to become + * available. The macro portTICK_PERIOD_MS can be used to convert this to a + * real time. A block time of zero can be used to poll the semaphore. A block + * time of portMAX_DELAY can be used to block indefinitely (provided + * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h). + * + * @return pdTRUE if the semaphore was obtained. pdFALSE + * if xBlockTime expired without the semaphore becoming available. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xSemaphore = NULL; + * + * // A task that creates a semaphore. + * void vATask( void * pvParameters ) + * { + * // Create the semaphore to guard a shared resource. + * xSemaphore = xSemaphoreCreateBinary(); + * } + * + * // A task that uses the semaphore. + * void vAnotherTask( void * pvParameters ) + * { + * // ... Do other things. + * + * if( xSemaphore != NULL ) + * { + * // See if we can obtain the semaphore. If the semaphore is not available + * // wait 10 ticks to see if it becomes free. + * if( xSemaphoreTake( xSemaphore, ( TickType_t ) 10 ) == pdTRUE ) + * { + * // We were able to obtain the semaphore and can now access the + * // shared resource. + * + * // ... + * + * // We have finished accessing the shared resource. Release the + * // semaphore. + * xSemaphoreGive( xSemaphore ); + * } + * else + * { + * // We could not obtain the semaphore and can therefore not access + * // the shared resource safely. + * } + * } + * } + * @endcode + * \defgroup xSemaphoreTake xSemaphoreTake + * \ingroup Semaphores + */ +#define xSemaphoreTake( xSemaphore, xBlockTime ) xQueueSemaphoreTake( ( xSemaphore ), ( xBlockTime ) ) + +/** + * semphr. h + * @code{c} + * xSemaphoreTakeRecursive( + * SemaphoreHandle_t xMutex, + * TickType_t xBlockTime + * ); + * @endcode + * + * Macro to recursively obtain, or 'take', a mutex type semaphore. + * The mutex must have previously been created using a call to + * xSemaphoreCreateRecursiveMutex(); + * + * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this + * macro to be available. + * + * This macro must not be used on mutexes created using xSemaphoreCreateMutex(). + * + * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex + * doesn't become available again until the owner has called + * xSemaphoreGiveRecursive() for each successful 'take' request. For example, + * if a task successfully 'takes' the same mutex 5 times then the mutex will + * not be available to any other task until it has also 'given' the mutex back + * exactly five times. + * + * @param xMutex A handle to the mutex being obtained. This is the + * handle returned by xSemaphoreCreateRecursiveMutex(); + * + * @param xBlockTime The time in ticks to wait for the semaphore to become + * available. The macro portTICK_PERIOD_MS can be used to convert this to a + * real time. A block time of zero can be used to poll the semaphore. If + * the task already owns the semaphore then xSemaphoreTakeRecursive() will + * return immediately no matter what the value of xBlockTime. + * + * @return pdTRUE if the semaphore was obtained. pdFALSE if xBlockTime + * expired without the semaphore becoming available. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xMutex = NULL; + * + * // A task that creates a mutex. + * void vATask( void * pvParameters ) + * { + * // Create the mutex to guard a shared resource. + * xMutex = xSemaphoreCreateRecursiveMutex(); + * } + * + * // A task that uses the mutex. + * void vAnotherTask( void * pvParameters ) + * { + * // ... Do other things. + * + * if( xMutex != NULL ) + * { + * // See if we can obtain the mutex. If the mutex is not available + * // wait 10 ticks to see if it becomes free. + * if( xSemaphoreTakeRecursive( xSemaphore, ( TickType_t ) 10 ) == pdTRUE ) + * { + * // We were able to obtain the mutex and can now access the + * // shared resource. + * + * // ... + * // For some reason due to the nature of the code further calls to + * // xSemaphoreTakeRecursive() are made on the same mutex. In real + * // code these would not be just sequential calls as this would make + * // no sense. Instead the calls are likely to be buried inside + * // a more complex call structure. + * xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ); + * xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ); + * + * // The mutex has now been 'taken' three times, so will not be + * // available to another task until it has also been given back + * // three times. Again it is unlikely that real code would have + * // these calls sequentially, but instead buried in a more complex + * // call structure. This is just for illustrative purposes. + * xSemaphoreGiveRecursive( xMutex ); + * xSemaphoreGiveRecursive( xMutex ); + * xSemaphoreGiveRecursive( xMutex ); + * + * // Now the mutex can be taken by other tasks. + * } + * else + * { + * // We could not obtain the mutex and can therefore not access + * // the shared resource safely. + * } + * } + * } + * @endcode + * \defgroup xSemaphoreTakeRecursive xSemaphoreTakeRecursive + * \ingroup Semaphores + */ +#if ( configUSE_RECURSIVE_MUTEXES == 1 ) + #define xSemaphoreTakeRecursive( xMutex, xBlockTime ) xQueueTakeMutexRecursive( ( xMutex ), ( xBlockTime ) ) +#endif + +/** + * semphr. h + * @code{c} + * xSemaphoreGive( SemaphoreHandle_t xSemaphore ); + * @endcode + * + * Macro to release a semaphore. The semaphore must have previously been + * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or + * xSemaphoreCreateCounting(). and obtained using sSemaphoreTake(). + * + * This macro must not be used from an ISR. See xSemaphoreGiveFromISR () for + * an alternative which can be used from an ISR. + * + * This macro must also not be used on semaphores created using + * xSemaphoreCreateRecursiveMutex(). + * + * @param xSemaphore A handle to the semaphore being released. This is the + * handle returned when the semaphore was created. + * + * @return pdTRUE if the semaphore was released. pdFALSE if an error occurred. + * Semaphores are implemented using queues. An error can occur if there is + * no space on the queue to post a message - indicating that the + * semaphore was not first obtained correctly. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xSemaphore = NULL; + * + * void vATask( void * pvParameters ) + * { + * // Create the semaphore to guard a shared resource. + * xSemaphore = vSemaphoreCreateBinary(); + * + * if( xSemaphore != NULL ) + * { + * if( xSemaphoreGive( xSemaphore ) != pdTRUE ) + * { + * // We would expect this call to fail because we cannot give + * // a semaphore without first "taking" it! + * } + * + * // Obtain the semaphore - don't block if the semaphore is not + * // immediately available. + * if( xSemaphoreTake( xSemaphore, ( TickType_t ) 0 ) ) + * { + * // We now have the semaphore and can access the shared resource. + * + * // ... + * + * // We have finished accessing the shared resource so can free the + * // semaphore. + * if( xSemaphoreGive( xSemaphore ) != pdTRUE ) + * { + * // We would not expect this call to fail because we must have + * // obtained the semaphore to get here. + * } + * } + * } + * } + * @endcode + * \defgroup xSemaphoreGive xSemaphoreGive + * \ingroup Semaphores + */ +#define xSemaphoreGive( xSemaphore ) xQueueGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK ) + +/** + * semphr. h + * @code{c} + * xSemaphoreGiveRecursive( SemaphoreHandle_t xMutex ); + * @endcode + * + * Macro to recursively release, or 'give', a mutex type semaphore. + * The mutex must have previously been created using a call to + * xSemaphoreCreateRecursiveMutex(); + * + * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this + * macro to be available. + * + * This macro must not be used on mutexes created using xSemaphoreCreateMutex(). + * + * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex + * doesn't become available again until the owner has called + * xSemaphoreGiveRecursive() for each successful 'take' request. For example, + * if a task successfully 'takes' the same mutex 5 times then the mutex will + * not be available to any other task until it has also 'given' the mutex back + * exactly five times. + * + * @param xMutex A handle to the mutex being released, or 'given'. This is the + * handle returned by xSemaphoreCreateMutex(); + * + * @return pdTRUE if the semaphore was given. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xMutex = NULL; + * + * // A task that creates a mutex. + * void vATask( void * pvParameters ) + * { + * // Create the mutex to guard a shared resource. + * xMutex = xSemaphoreCreateRecursiveMutex(); + * } + * + * // A task that uses the mutex. + * void vAnotherTask( void * pvParameters ) + * { + * // ... Do other things. + * + * if( xMutex != NULL ) + * { + * // See if we can obtain the mutex. If the mutex is not available + * // wait 10 ticks to see if it becomes free. + * if( xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ) == pdTRUE ) + * { + * // We were able to obtain the mutex and can now access the + * // shared resource. + * + * // ... + * // For some reason due to the nature of the code further calls to + * // xSemaphoreTakeRecursive() are made on the same mutex. In real + * // code these would not be just sequential calls as this would make + * // no sense. Instead the calls are likely to be buried inside + * // a more complex call structure. + * xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ); + * xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ); + * + * // The mutex has now been 'taken' three times, so will not be + * // available to another task until it has also been given back + * // three times. Again it is unlikely that real code would have + * // these calls sequentially, it would be more likely that the calls + * // to xSemaphoreGiveRecursive() would be called as a call stack + * // unwound. This is just for demonstrative purposes. + * xSemaphoreGiveRecursive( xMutex ); + * xSemaphoreGiveRecursive( xMutex ); + * xSemaphoreGiveRecursive( xMutex ); + * + * // Now the mutex can be taken by other tasks. + * } + * else + * { + * // We could not obtain the mutex and can therefore not access + * // the shared resource safely. + * } + * } + * } + * @endcode + * \defgroup xSemaphoreGiveRecursive xSemaphoreGiveRecursive + * \ingroup Semaphores + */ +#if ( configUSE_RECURSIVE_MUTEXES == 1 ) + #define xSemaphoreGiveRecursive( xMutex ) xQueueGiveMutexRecursive( ( xMutex ) ) +#endif + +/** + * semphr. h + * @code{c} + * xSemaphoreGiveFromISR( + * SemaphoreHandle_t xSemaphore, + * BaseType_t *pxHigherPriorityTaskWoken + * ); + * @endcode + * + * Macro to release a semaphore. The semaphore must have previously been + * created with a call to xSemaphoreCreateBinary() or xSemaphoreCreateCounting(). + * + * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex()) + * must not be used with this macro. + * + * This macro can be used from an ISR. + * + * @param xSemaphore A handle to the semaphore being released. This is the + * handle returned when the semaphore was created. + * + * @param pxHigherPriorityTaskWoken xSemaphoreGiveFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if giving the semaphore caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xSemaphoreGiveFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return pdTRUE if the semaphore was successfully given, otherwise errQUEUE_FULL. + * + * Example usage: + * @code{c} + \#define LONG_TIME 0xffff + \#define TICKS_TO_WAIT 10 + * SemaphoreHandle_t xSemaphore = NULL; + * + * // Repetitive task. + * void vATask( void * pvParameters ) + * { + * for( ;; ) + * { + * // We want this task to run every 10 ticks of a timer. The semaphore + * // was created before this task was started. + * + * // Block waiting for the semaphore to become available. + * if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE ) + * { + * // It is time to execute. + * + * // ... + * + * // We have finished our task. Return to the top of the loop where + * // we will block on the semaphore until it is time to execute + * // again. Note when using the semaphore for synchronisation with an + * // ISR in this manner there is no need to 'give' the semaphore back. + * } + * } + * } + * + * // Timer ISR + * void vTimerISR( void * pvParameters ) + * { + * static uint8_t ucLocalTickCount = 0; + * static BaseType_t xHigherPriorityTaskWoken; + * + * // A timer tick has occurred. + * + * // ... Do other time functions. + * + * // Is it time for vATask () to run? + * xHigherPriorityTaskWoken = pdFALSE; + * ucLocalTickCount++; + * if( ucLocalTickCount >= TICKS_TO_WAIT ) + * { + * // Unblock the task by releasing the semaphore. + * xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken ); + * + * // Reset the count so we release the semaphore again in 10 ticks time. + * ucLocalTickCount = 0; + * } + * + * if( xHigherPriorityTaskWoken != pdFALSE ) + * { + * // We can force a context switch here. Context switching from an + * // ISR uses port specific syntax. Check the demo task for your port + * // to find the syntax required. + * } + * } + * @endcode + * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR + * \ingroup Semaphores + */ +#define xSemaphoreGiveFromISR( xSemaphore, pxHigherPriorityTaskWoken ) xQueueGiveFromISR( ( QueueHandle_t ) ( xSemaphore ), ( pxHigherPriorityTaskWoken ) ) + +/** + * semphr. h + * @code{c} + * xSemaphoreTakeFromISR( + * SemaphoreHandle_t xSemaphore, + * BaseType_t *pxHigherPriorityTaskWoken + * ); + * @endcode + * + * Macro to take a semaphore from an ISR. The semaphore must have + * previously been created with a call to xSemaphoreCreateBinary() or + * xSemaphoreCreateCounting(). + * + * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex()) + * must not be used with this macro. + * + * This macro can be used from an ISR, however taking a semaphore from an ISR + * is not a common operation. It is likely to only be useful when taking a + * counting semaphore when an interrupt is obtaining an object from a resource + * pool (when the semaphore count indicates the number of resources available). + * + * @param xSemaphore A handle to the semaphore being taken. This is the + * handle returned when the semaphore was created. + * + * @param pxHigherPriorityTaskWoken xSemaphoreTakeFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if taking the semaphore caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xSemaphoreTakeFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return pdTRUE if the semaphore was successfully taken, otherwise + * pdFALSE + */ +#define xSemaphoreTakeFromISR( xSemaphore, pxHigherPriorityTaskWoken ) xQueueReceiveFromISR( ( QueueHandle_t ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ) ) + +/** + * semphr. h + * @code{c} + * SemaphoreHandle_t xSemaphoreCreateMutex( void ); + * @endcode + * + * Creates a new mutex type semaphore instance, and returns a handle by which + * the new mutex can be referenced. + * + * Internally, within the FreeRTOS implementation, mutex semaphores use a block + * of memory, in which the mutex structure is stored. If a mutex is created + * using xSemaphoreCreateMutex() then the required memory is automatically + * dynamically allocated inside the xSemaphoreCreateMutex() function. (see + * https://www.FreeRTOS.org/a00111.html). If a mutex is created using + * xSemaphoreCreateMutexStatic() then the application writer must provided the + * memory. xSemaphoreCreateMutexStatic() therefore allows a mutex to be created + * without using any dynamic memory allocation. + * + * Mutexes created using this function can be accessed using the xSemaphoreTake() + * and xSemaphoreGive() macros. The xSemaphoreTakeRecursive() and + * xSemaphoreGiveRecursive() macros must not be used. + * + * This type of semaphore uses a priority inheritance mechanism so a task + * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the + * semaphore it is no longer required. + * + * Mutex type semaphores cannot be used from within interrupt service routines. + * + * See xSemaphoreCreateBinary() for an alternative implementation that can be + * used for pure synchronisation (where one task or interrupt always 'gives' the + * semaphore and another always 'takes' the semaphore) and from within interrupt + * service routines. + * + * @return If the mutex was successfully created then a handle to the created + * semaphore is returned. If there was not enough heap to allocate the mutex + * data structures then NULL is returned. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xSemaphore; + * + * void vATask( void * pvParameters ) + * { + * // Semaphore cannot be used before a call to xSemaphoreCreateMutex(). + * // This is a macro so pass the variable in directly. + * xSemaphore = xSemaphoreCreateMutex(); + * + * if( xSemaphore != NULL ) + * { + * // The semaphore was created successfully. + * // The semaphore can now be used. + * } + * } + * @endcode + * \defgroup xSemaphoreCreateMutex xSemaphoreCreateMutex + * \ingroup Semaphores + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + #define xSemaphoreCreateMutex() xQueueCreateMutex( queueQUEUE_TYPE_MUTEX ) +#endif + +/** + * semphr. h + * @code{c} + * SemaphoreHandle_t xSemaphoreCreateMutexStatic( StaticSemaphore_t *pxMutexBuffer ); + * @endcode + * + * Creates a new mutex type semaphore instance, and returns a handle by which + * the new mutex can be referenced. + * + * Internally, within the FreeRTOS implementation, mutex semaphores use a block + * of memory, in which the mutex structure is stored. If a mutex is created + * using xSemaphoreCreateMutex() then the required memory is automatically + * dynamically allocated inside the xSemaphoreCreateMutex() function. (see + * https://www.FreeRTOS.org/a00111.html). If a mutex is created using + * xSemaphoreCreateMutexStatic() then the application writer must provided the + * memory. xSemaphoreCreateMutexStatic() therefore allows a mutex to be created + * without using any dynamic memory allocation. + * + * Mutexes created using this function can be accessed using the xSemaphoreTake() + * and xSemaphoreGive() macros. The xSemaphoreTakeRecursive() and + * xSemaphoreGiveRecursive() macros must not be used. + * + * This type of semaphore uses a priority inheritance mechanism so a task + * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the + * semaphore it is no longer required. + * + * Mutex type semaphores cannot be used from within interrupt service routines. + * + * See xSemaphoreCreateBinary() for an alternative implementation that can be + * used for pure synchronisation (where one task or interrupt always 'gives' the + * semaphore and another always 'takes' the semaphore) and from within interrupt + * service routines. + * + * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t, + * which will be used to hold the mutex's data structure, removing the need for + * the memory to be allocated dynamically. + * + * @return If the mutex was successfully created then a handle to the created + * mutex is returned. If pxMutexBuffer was NULL then NULL is returned. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xSemaphore; + * StaticSemaphore_t xMutexBuffer; + * + * void vATask( void * pvParameters ) + * { + * // A mutex cannot be used before it has been created. xMutexBuffer is + * // into xSemaphoreCreateMutexStatic() so no dynamic memory allocation is + * // attempted. + * xSemaphore = xSemaphoreCreateMutexStatic( &xMutexBuffer ); + * + * // As no dynamic memory allocation was performed, xSemaphore cannot be NULL, + * // so there is no need to check it. + * } + * @endcode + * \defgroup xSemaphoreCreateMutexStatic xSemaphoreCreateMutexStatic + * \ingroup Semaphores + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + #define xSemaphoreCreateMutexStatic( pxMutexBuffer ) xQueueCreateMutexStatic( queueQUEUE_TYPE_MUTEX, ( pxMutexBuffer ) ) +#endif /* configSUPPORT_STATIC_ALLOCATION */ + + +/** + * semphr. h + * @code{c} + * SemaphoreHandle_t xSemaphoreCreateRecursiveMutex( void ); + * @endcode + * + * Creates a new recursive mutex type semaphore instance, and returns a handle + * by which the new recursive mutex can be referenced. + * + * Internally, within the FreeRTOS implementation, recursive mutexs use a block + * of memory, in which the mutex structure is stored. If a recursive mutex is + * created using xSemaphoreCreateRecursiveMutex() then the required memory is + * automatically dynamically allocated inside the + * xSemaphoreCreateRecursiveMutex() function. (see + * https://www.FreeRTOS.org/a00111.html). If a recursive mutex is created using + * xSemaphoreCreateRecursiveMutexStatic() then the application writer must + * provide the memory that will get used by the mutex. + * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to + * be created without using any dynamic memory allocation. + * + * Mutexes created using this macro can be accessed using the + * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros. The + * xSemaphoreTake() and xSemaphoreGive() macros must not be used. + * + * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex + * doesn't become available again until the owner has called + * xSemaphoreGiveRecursive() for each successful 'take' request. For example, + * if a task successfully 'takes' the same mutex 5 times then the mutex will + * not be available to any other task until it has also 'given' the mutex back + * exactly five times. + * + * This type of semaphore uses a priority inheritance mechanism so a task + * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the + * semaphore it is no longer required. + * + * Mutex type semaphores cannot be used from within interrupt service routines. + * + * See xSemaphoreCreateBinary() for an alternative implementation that can be + * used for pure synchronisation (where one task or interrupt always 'gives' the + * semaphore and another always 'takes' the semaphore) and from within interrupt + * service routines. + * + * @return xSemaphore Handle to the created mutex semaphore. Should be of type + * SemaphoreHandle_t. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xSemaphore; + * + * void vATask( void * pvParameters ) + * { + * // Semaphore cannot be used before a call to xSemaphoreCreateMutex(). + * // This is a macro so pass the variable in directly. + * xSemaphore = xSemaphoreCreateRecursiveMutex(); + * + * if( xSemaphore != NULL ) + * { + * // The semaphore was created successfully. + * // The semaphore can now be used. + * } + * } + * @endcode + * \defgroup xSemaphoreCreateRecursiveMutex xSemaphoreCreateRecursiveMutex + * \ingroup Semaphores + */ +#if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) ) + #define xSemaphoreCreateRecursiveMutex() xQueueCreateMutex( queueQUEUE_TYPE_RECURSIVE_MUTEX ) +#endif + +/** + * semphr. h + * @code{c} + * SemaphoreHandle_t xSemaphoreCreateRecursiveMutexStatic( StaticSemaphore_t *pxMutexBuffer ); + * @endcode + * + * Creates a new recursive mutex type semaphore instance, and returns a handle + * by which the new recursive mutex can be referenced. + * + * Internally, within the FreeRTOS implementation, recursive mutexs use a block + * of memory, in which the mutex structure is stored. If a recursive mutex is + * created using xSemaphoreCreateRecursiveMutex() then the required memory is + * automatically dynamically allocated inside the + * xSemaphoreCreateRecursiveMutex() function. (see + * https://www.FreeRTOS.org/a00111.html). If a recursive mutex is created using + * xSemaphoreCreateRecursiveMutexStatic() then the application writer must + * provide the memory that will get used by the mutex. + * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to + * be created without using any dynamic memory allocation. + * + * Mutexes created using this macro can be accessed using the + * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros. The + * xSemaphoreTake() and xSemaphoreGive() macros must not be used. + * + * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex + * doesn't become available again until the owner has called + * xSemaphoreGiveRecursive() for each successful 'take' request. For example, + * if a task successfully 'takes' the same mutex 5 times then the mutex will + * not be available to any other task until it has also 'given' the mutex back + * exactly five times. + * + * This type of semaphore uses a priority inheritance mechanism so a task + * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the + * semaphore it is no longer required. + * + * Mutex type semaphores cannot be used from within interrupt service routines. + * + * See xSemaphoreCreateBinary() for an alternative implementation that can be + * used for pure synchronisation (where one task or interrupt always 'gives' the + * semaphore and another always 'takes' the semaphore) and from within interrupt + * service routines. + * + * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t, + * which will then be used to hold the recursive mutex's data structure, + * removing the need for the memory to be allocated dynamically. + * + * @return If the recursive mutex was successfully created then a handle to the + * created recursive mutex is returned. If pxMutexBuffer was NULL then NULL is + * returned. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xSemaphore; + * StaticSemaphore_t xMutexBuffer; + * + * void vATask( void * pvParameters ) + * { + * // A recursive semaphore cannot be used before it is created. Here a + * // recursive mutex is created using xSemaphoreCreateRecursiveMutexStatic(). + * // The address of xMutexBuffer is passed into the function, and will hold + * // the mutexes data structures - so no dynamic memory allocation will be + * // attempted. + * xSemaphore = xSemaphoreCreateRecursiveMutexStatic( &xMutexBuffer ); + * + * // As no dynamic memory allocation was performed, xSemaphore cannot be NULL, + * // so there is no need to check it. + * } + * @endcode + * \defgroup xSemaphoreCreateRecursiveMutexStatic xSemaphoreCreateRecursiveMutexStatic + * \ingroup Semaphores + */ +#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) ) + #define xSemaphoreCreateRecursiveMutexStatic( pxStaticSemaphore ) xQueueCreateMutexStatic( queueQUEUE_TYPE_RECURSIVE_MUTEX, pxStaticSemaphore ) +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/** + * semphr. h + * @code{c} + * SemaphoreHandle_t xSemaphoreCreateCounting( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount ); + * @endcode + * + * Creates a new counting semaphore instance, and returns a handle by which the + * new counting semaphore can be referenced. + * + * In many usage scenarios it is faster and more memory efficient to use a + * direct to task notification in place of a counting semaphore! + * https://www.FreeRTOS.org/RTOS-task-notifications.html + * + * Internally, within the FreeRTOS implementation, counting semaphores use a + * block of memory, in which the counting semaphore structure is stored. If a + * counting semaphore is created using xSemaphoreCreateCounting() then the + * required memory is automatically dynamically allocated inside the + * xSemaphoreCreateCounting() function. (see + * https://www.FreeRTOS.org/a00111.html). If a counting semaphore is created + * using xSemaphoreCreateCountingStatic() then the application writer can + * instead optionally provide the memory that will get used by the counting + * semaphore. xSemaphoreCreateCountingStatic() therefore allows a counting + * semaphore to be created without using any dynamic memory allocation. + * + * Counting semaphores are typically used for two things: + * + * 1) Counting events. + * + * In this usage scenario an event handler will 'give' a semaphore each time + * an event occurs (incrementing the semaphore count value), and a handler + * task will 'take' a semaphore each time it processes an event + * (decrementing the semaphore count value). The count value is therefore + * the difference between the number of events that have occurred and the + * number that have been processed. In this case it is desirable for the + * initial count value to be zero. + * + * 2) Resource management. + * + * In this usage scenario the count value indicates the number of resources + * available. To obtain control of a resource a task must first obtain a + * semaphore - decrementing the semaphore count value. When the count value + * reaches zero there are no free resources. When a task finishes with the + * resource it 'gives' the semaphore back - incrementing the semaphore count + * value. In this case it is desirable for the initial count value to be + * equal to the maximum count value, indicating that all resources are free. + * + * @param uxMaxCount The maximum count value that can be reached. When the + * semaphore reaches this value it can no longer be 'given'. + * + * @param uxInitialCount The count value assigned to the semaphore when it is + * created. + * + * @return Handle to the created semaphore. Null if the semaphore could not be + * created. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xSemaphore; + * + * void vATask( void * pvParameters ) + * { + * SemaphoreHandle_t xSemaphore = NULL; + * + * // Semaphore cannot be used before a call to xSemaphoreCreateCounting(). + * // The max value to which the semaphore can count should be 10, and the + * // initial value assigned to the count should be 0. + * xSemaphore = xSemaphoreCreateCounting( 10, 0 ); + * + * if( xSemaphore != NULL ) + * { + * // The semaphore was created successfully. + * // The semaphore can now be used. + * } + * } + * @endcode + * \defgroup xSemaphoreCreateCounting xSemaphoreCreateCounting + * \ingroup Semaphores + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + #define xSemaphoreCreateCounting( uxMaxCount, uxInitialCount ) xQueueCreateCountingSemaphore( ( uxMaxCount ), ( uxInitialCount ) ) +#endif + +/** + * semphr. h + * @code{c} + * SemaphoreHandle_t xSemaphoreCreateCountingStatic( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount, StaticSemaphore_t *pxSemaphoreBuffer ); + * @endcode + * + * Creates a new counting semaphore instance, and returns a handle by which the + * new counting semaphore can be referenced. + * + * In many usage scenarios it is faster and more memory efficient to use a + * direct to task notification in place of a counting semaphore! + * https://www.FreeRTOS.org/RTOS-task-notifications.html + * + * Internally, within the FreeRTOS implementation, counting semaphores use a + * block of memory, in which the counting semaphore structure is stored. If a + * counting semaphore is created using xSemaphoreCreateCounting() then the + * required memory is automatically dynamically allocated inside the + * xSemaphoreCreateCounting() function. (see + * https://www.FreeRTOS.org/a00111.html). If a counting semaphore is created + * using xSemaphoreCreateCountingStatic() then the application writer must + * provide the memory. xSemaphoreCreateCountingStatic() therefore allows a + * counting semaphore to be created without using any dynamic memory allocation. + * + * Counting semaphores are typically used for two things: + * + * 1) Counting events. + * + * In this usage scenario an event handler will 'give' a semaphore each time + * an event occurs (incrementing the semaphore count value), and a handler + * task will 'take' a semaphore each time it processes an event + * (decrementing the semaphore count value). The count value is therefore + * the difference between the number of events that have occurred and the + * number that have been processed. In this case it is desirable for the + * initial count value to be zero. + * + * 2) Resource management. + * + * In this usage scenario the count value indicates the number of resources + * available. To obtain control of a resource a task must first obtain a + * semaphore - decrementing the semaphore count value. When the count value + * reaches zero there are no free resources. When a task finishes with the + * resource it 'gives' the semaphore back - incrementing the semaphore count + * value. In this case it is desirable for the initial count value to be + * equal to the maximum count value, indicating that all resources are free. + * + * @param uxMaxCount The maximum count value that can be reached. When the + * semaphore reaches this value it can no longer be 'given'. + * + * @param uxInitialCount The count value assigned to the semaphore when it is + * created. + * + * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t, + * which will then be used to hold the semaphore's data structure, removing the + * need for the memory to be allocated dynamically. + * + * @return If the counting semaphore was successfully created then a handle to + * the created counting semaphore is returned. If pxSemaphoreBuffer was NULL + * then NULL is returned. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xSemaphore; + * StaticSemaphore_t xSemaphoreBuffer; + * + * void vATask( void * pvParameters ) + * { + * SemaphoreHandle_t xSemaphore = NULL; + * + * // Counting semaphore cannot be used before they have been created. Create + * // a counting semaphore using xSemaphoreCreateCountingStatic(). The max + * // value to which the semaphore can count is 10, and the initial value + * // assigned to the count will be 0. The address of xSemaphoreBuffer is + * // passed in and will be used to hold the semaphore structure, so no dynamic + * // memory allocation will be used. + * xSemaphore = xSemaphoreCreateCounting( 10, 0, &xSemaphoreBuffer ); + * + * // No memory allocation was attempted so xSemaphore cannot be NULL, so there + * // is no need to check its value. + * } + * @endcode + * \defgroup xSemaphoreCreateCountingStatic xSemaphoreCreateCountingStatic + * \ingroup Semaphores + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + #define xSemaphoreCreateCountingStatic( uxMaxCount, uxInitialCount, pxSemaphoreBuffer ) xQueueCreateCountingSemaphoreStatic( ( uxMaxCount ), ( uxInitialCount ), ( pxSemaphoreBuffer ) ) +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/** + * semphr. h + * @code{c} + * void vSemaphoreDelete( SemaphoreHandle_t xSemaphore ); + * @endcode + * + * Delete a semaphore. This function must be used with care. For example, + * do not delete a mutex type semaphore if the mutex is held by a task. + * + * @param xSemaphore A handle to the semaphore to be deleted. + * + * \defgroup vSemaphoreDelete vSemaphoreDelete + * \ingroup Semaphores + */ +#define vSemaphoreDelete( xSemaphore ) vQueueDelete( ( QueueHandle_t ) ( xSemaphore ) ) + +/** + * semphr.h + * @code{c} + * TaskHandle_t xSemaphoreGetMutexHolder( SemaphoreHandle_t xMutex ); + * @endcode + * + * If xMutex is indeed a mutex type semaphore, return the current mutex holder. + * If xMutex is not a mutex type semaphore, or the mutex is available (not held + * by a task), return NULL. + * + * Note: This is a good way of determining if the calling task is the mutex + * holder, but not a good way of determining the identity of the mutex holder as + * the holder may change between the function exiting and the returned value + * being tested. + */ +#define xSemaphoreGetMutexHolder( xSemaphore ) xQueueGetMutexHolder( ( xSemaphore ) ) + +/** + * semphr.h + * @code{c} + * TaskHandle_t xSemaphoreGetMutexHolderFromISR( SemaphoreHandle_t xMutex ); + * @endcode + * + * If xMutex is indeed a mutex type semaphore, return the current mutex holder. + * If xMutex is not a mutex type semaphore, or the mutex is available (not held + * by a task), return NULL. + * + */ +#define xSemaphoreGetMutexHolderFromISR( xSemaphore ) xQueueGetMutexHolderFromISR( ( xSemaphore ) ) + +/** + * semphr.h + * @code{c} + * UBaseType_t uxSemaphoreGetCount( SemaphoreHandle_t xSemaphore ); + * @endcode + * + * If the semaphore is a counting semaphore then uxSemaphoreGetCount() returns + * its current count value. If the semaphore is a binary semaphore then + * uxSemaphoreGetCount() returns 1 if the semaphore is available, and 0 if the + * semaphore is not available. + * + */ +#define uxSemaphoreGetCount( xSemaphore ) uxQueueMessagesWaiting( ( QueueHandle_t ) ( xSemaphore ) ) + +/** + * semphr.h + * @code{c} + * UBaseType_t uxSemaphoreGetCountFromISR( SemaphoreHandle_t xSemaphore ); + * @endcode + * + * If the semaphore is a counting semaphore then uxSemaphoreGetCountFromISR() returns + * its current count value. If the semaphore is a binary semaphore then + * uxSemaphoreGetCountFromISR() returns 1 if the semaphore is available, and 0 if the + * semaphore is not available. + * + */ +#define uxSemaphoreGetCountFromISR( xSemaphore ) uxQueueMessagesWaitingFromISR( ( QueueHandle_t ) ( xSemaphore ) ) + +#endif /* SEMAPHORE_H */ diff --git a/hw-libs/freertos/include/stack_macros.h b/hw-libs/freertos/include/stack_macros.h new file mode 100644 index 000000000..cfe5b9532 --- /dev/null +++ b/hw-libs/freertos/include/stack_macros.h @@ -0,0 +1,137 @@ +/* + * FreeRTOS Kernel V10.4.6 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef STACK_MACROS_H +#define STACK_MACROS_H + +/* + * Call the stack overflow hook function if the stack of the task being swapped + * out is currently overflowed, or looks like it might have overflowed in the + * past. + * + * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check + * the current stack state only - comparing the current top of stack value to + * the stack limit. Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1 + * will also cause the last few stack bytes to be checked to ensure the value + * to which the bytes were set when the task was created have not been + * overwritten. Note this second test does not guarantee that an overflowed + * stack will always be recognised. + */ + +/*-----------------------------------------------------------*/ + +/* + * portSTACK_LIMIT_PADDING is a number of extra words to consider to be in + * use on the stack. + */ +#ifndef portSTACK_LIMIT_PADDING + #define portSTACK_LIMIT_PADDING 0 +#endif + +#if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) ) + +/* Only the current stack state is to be checked. */ + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + /* Is the currently saved stack pointer within the stack limit? */ \ + if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack + portSTACK_LIMIT_PADDING ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) ) + +/* Only the current stack state is to be checked. */ + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + \ + /* Is the currently saved stack pointer within the stack limit? */ \ + if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack - portSTACK_LIMIT_PADDING ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) ) + + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack; \ + const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5; \ + \ + if( ( pulStack[ 0 ] != ulCheckValue ) || \ + ( pulStack[ 1 ] != ulCheckValue ) || \ + ( pulStack[ 2 ] != ulCheckValue ) || \ + ( pulStack[ 3 ] != ulCheckValue ) ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) ) + + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + int8_t * pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack; \ + static const uint8_t ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \ + \ + \ + pcEndOfStack -= sizeof( ucExpectedStackBytes ); \ + \ + /* Has the extremity of the task stack ever been written over? */ \ + if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */ +/*-----------------------------------------------------------*/ + +/* Remove stack overflow macro if not being used. */ +#ifndef taskCHECK_FOR_STACK_OVERFLOW + #define taskCHECK_FOR_STACK_OVERFLOW() +#endif + + + +#endif /* STACK_MACROS_H */ diff --git a/hw-libs/freertos/include/stdint.readme b/hw-libs/freertos/include/stdint.readme new file mode 100644 index 000000000..654c62b1a --- /dev/null +++ b/hw-libs/freertos/include/stdint.readme @@ -0,0 +1,58 @@ +/* + * FreeRTOS Kernel V10.4.6 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FREERTOS_STDINT +#define FREERTOS_STDINT + +/******************************************************************************* + * THIS IS NOT A FULL stdint.h IMPLEMENTATION - It only contains the definitions + * necessary to build the FreeRTOS code. It is provided to allow FreeRTOS to be + * built using compilers that do not provide their own stdint.h definition. + * + * To use this file: + * + * 1) Copy this file into the directory that contains your FreeRTOSConfig.h + * header file, as that directory will already be in the compiler's include + * path. + * + * 2) Rename the copied file stdint.h. + * + */ + +typedef signed char int8_t; +typedef unsigned char uint8_t; +typedef short int16_t; +typedef unsigned short uint16_t; +typedef long int32_t; +typedef unsigned long uint32_t; + +#ifndef SIZE_MAX + #define SIZE_MAX ( ( size_t ) -1 ) +#endif + +#endif /* FREERTOS_STDINT */ diff --git a/hw-libs/freertos/include/stream_buffer.h b/hw-libs/freertos/include/stream_buffer.h new file mode 100644 index 000000000..c2812d411 --- /dev/null +++ b/hw-libs/freertos/include/stream_buffer.h @@ -0,0 +1,869 @@ +/* + * FreeRTOS Kernel V10.4.6 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Stream buffers are used to send a continuous stream of data from one task or + * interrupt to another. Their implementation is light weight, making them + * particularly suited for interrupt to task and core to core communication + * scenarios. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xStreamBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xStreamBufferReceive()) inside a critical section section and set the + * receive block time to 0. + * + */ + +#ifndef STREAM_BUFFER_H +#define STREAM_BUFFER_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include stream_buffer.h" +#endif + +/* *INDENT-OFF* */ +#if defined( __cplusplus ) + extern "C" { +#endif +/* *INDENT-ON* */ + +/** + * Type by which stream buffers are referenced. For example, a call to + * xStreamBufferCreate() returns an StreamBufferHandle_t variable that can + * then be used as a parameter to xStreamBufferSend(), xStreamBufferReceive(), + * etc. + */ +struct StreamBufferDef_t; +typedef struct StreamBufferDef_t * StreamBufferHandle_t; + + +/** + * stream_buffer.h + * + * @code{c} + * StreamBufferHandle_t xStreamBufferCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes ); + * @endcode + * + * Creates a new stream buffer using dynamically allocated memory. See + * xStreamBufferCreateStatic() for a version that uses statically allocated + * memory (memory that is allocated at compile time). + * + * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in + * FreeRTOSConfig.h for xStreamBufferCreate() to be available. + * + * @param xBufferSizeBytes The total number of bytes the stream buffer will be + * able to hold at any one time. + * + * @param xTriggerLevelBytes The number of bytes that must be in the stream + * buffer before a task that is blocked on the stream buffer to wait for data is + * moved out of the blocked state. For example, if a task is blocked on a read + * of an empty stream buffer that has a trigger level of 1 then the task will be + * unblocked when a single byte is written to the buffer or the task's block + * time expires. As another example, if a task is blocked on a read of an empty + * stream buffer that has a trigger level of 10 then the task will not be + * unblocked until the stream buffer contains at least 10 bytes or the task's + * block time expires. If a reading task's block time expires before the + * trigger level is reached then the task will still receive however many bytes + * are actually available. Setting a trigger level of 0 will result in a + * trigger level of 1 being used. It is not valid to specify a trigger level + * that is greater than the buffer size. + * + * @return If NULL is returned, then the stream buffer cannot be created + * because there is insufficient heap memory available for FreeRTOS to allocate + * the stream buffer data structures and storage area. A non-NULL value being + * returned indicates that the stream buffer has been created successfully - + * the returned value should be stored as the handle to the created stream + * buffer. + * + * Example use: + * @code{c} + * + * void vAFunction( void ) + * { + * StreamBufferHandle_t xStreamBuffer; + * const size_t xStreamBufferSizeBytes = 100, xTriggerLevel = 10; + * + * // Create a stream buffer that can hold 100 bytes. The memory used to hold + * // both the stream buffer structure and the data in the stream buffer is + * // allocated dynamically. + * xStreamBuffer = xStreamBufferCreate( xStreamBufferSizeBytes, xTriggerLevel ); + * + * if( xStreamBuffer == NULL ) + * { + * // There was not enough heap memory space available to create the + * // stream buffer. + * } + * else + * { + * // The stream buffer was created successfully and can now be used. + * } + * } + * @endcode + * \defgroup xStreamBufferCreate xStreamBufferCreate + * \ingroup StreamBufferManagement + */ +#define xStreamBufferCreate( xBufferSizeBytes, xTriggerLevelBytes ) xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE ) + +/** + * stream_buffer.h + * + * @code{c} + * StreamBufferHandle_t xStreamBufferCreateStatic( size_t xBufferSizeBytes, + * size_t xTriggerLevelBytes, + * uint8_t *pucStreamBufferStorageArea, + * StaticStreamBuffer_t *pxStaticStreamBuffer ); + * @endcode + * Creates a new stream buffer using statically allocated memory. See + * xStreamBufferCreate() for a version that uses dynamically allocated memory. + * + * configSUPPORT_STATIC_ALLOCATION must be set to 1 in FreeRTOSConfig.h for + * xStreamBufferCreateStatic() to be available. + * + * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the + * pucStreamBufferStorageArea parameter. + * + * @param xTriggerLevelBytes The number of bytes that must be in the stream + * buffer before a task that is blocked on the stream buffer to wait for data is + * moved out of the blocked state. For example, if a task is blocked on a read + * of an empty stream buffer that has a trigger level of 1 then the task will be + * unblocked when a single byte is written to the buffer or the task's block + * time expires. As another example, if a task is blocked on a read of an empty + * stream buffer that has a trigger level of 10 then the task will not be + * unblocked until the stream buffer contains at least 10 bytes or the task's + * block time expires. If a reading task's block time expires before the + * trigger level is reached then the task will still receive however many bytes + * are actually available. Setting a trigger level of 0 will result in a + * trigger level of 1 being used. It is not valid to specify a trigger level + * that is greater than the buffer size. + * + * @param pucStreamBufferStorageArea Must point to a uint8_t array that is at + * least xBufferSizeBytes big. This is the array to which streams are + * copied when they are written to the stream buffer. + * + * @param pxStaticStreamBuffer Must point to a variable of type + * StaticStreamBuffer_t, which will be used to hold the stream buffer's data + * structure. + * + * @return If the stream buffer is created successfully then a handle to the + * created stream buffer is returned. If either pucStreamBufferStorageArea or + * pxStaticstreamBuffer are NULL then NULL is returned. + * + * Example use: + * @code{c} + * + * // Used to dimension the array used to hold the streams. The available space + * // will actually be one less than this, so 999. + #define STORAGE_SIZE_BYTES 1000 + * + * // Defines the memory that will actually hold the streams within the stream + * // buffer. + * static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ]; + * + * // The variable used to hold the stream buffer structure. + * StaticStreamBuffer_t xStreamBufferStruct; + * + * void MyFunction( void ) + * { + * StreamBufferHandle_t xStreamBuffer; + * const size_t xTriggerLevel = 1; + * + * xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucStorageBuffer ), + * xTriggerLevel, + * ucStorageBuffer, + * &xStreamBufferStruct ); + * + * // As neither the pucStreamBufferStorageArea or pxStaticStreamBuffer + * // parameters were NULL, xStreamBuffer will not be NULL, and can be used to + * // reference the created stream buffer in other stream buffer API calls. + * + * // Other code that uses the stream buffer can go here. + * } + * + * @endcode + * \defgroup xStreamBufferCreateStatic xStreamBufferCreateStatic + * \ingroup StreamBufferManagement + */ +#define xStreamBufferCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer ) \ + xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE, pucStreamBufferStorageArea, pxStaticStreamBuffer ) + +/** + * stream_buffer.h + * + * @code{c} + * size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + * const void *pvTxData, + * size_t xDataLengthBytes, + * TickType_t xTicksToWait ); + * @endcode + * + * Sends bytes to a stream buffer. The bytes are copied into the stream buffer. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xStreamBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xStreamBufferReceive()) inside a critical section and set the receive + * block time to 0. + * + * Use xStreamBufferSend() to write to a stream buffer from a task. Use + * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt + * service routine (ISR). + * + * @param xStreamBuffer The handle of the stream buffer to which a stream is + * being sent. + * + * @param pvTxData A pointer to the buffer that holds the bytes to be copied + * into the stream buffer. + * + * @param xDataLengthBytes The maximum number of bytes to copy from pvTxData + * into the stream buffer. + * + * @param xTicksToWait The maximum amount of time the task should remain in the + * Blocked state to wait for enough space to become available in the stream + * buffer, should the stream buffer contain too little space to hold the + * another xDataLengthBytes bytes. The block time is specified in tick periods, + * so the absolute time it represents is dependent on the tick frequency. The + * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds + * into a time specified in ticks. Setting xTicksToWait to portMAX_DELAY will + * cause the task to wait indefinitely (without timing out), provided + * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h. If a task times out + * before it can write all xDataLengthBytes into the buffer it will still write + * as many bytes as possible. A task does not use any CPU time when it is in + * the blocked state. + * + * @return The number of bytes written to the stream buffer. If a task times + * out before it can write all xDataLengthBytes into the buffer it will still + * write as many bytes as possible. + * + * Example use: + * @code{c} + * void vAFunction( StreamBufferHandle_t xStreamBuffer ) + * { + * size_t xBytesSent; + * uint8_t ucArrayToSend[] = { 0, 1, 2, 3 }; + * char *pcStringToSend = "String to send"; + * const TickType_t x100ms = pdMS_TO_TICKS( 100 ); + * + * // Send an array to the stream buffer, blocking for a maximum of 100ms to + * // wait for enough space to be available in the stream buffer. + * xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms ); + * + * if( xBytesSent != sizeof( ucArrayToSend ) ) + * { + * // The call to xStreamBufferSend() times out before there was enough + * // space in the buffer for the data to be written, but it did + * // successfully write xBytesSent bytes. + * } + * + * // Send the string to the stream buffer. Return immediately if there is not + * // enough space in the buffer. + * xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 ); + * + * if( xBytesSent != strlen( pcStringToSend ) ) + * { + * // The entire string could not be added to the stream buffer because + * // there was not enough free space in the buffer, but xBytesSent bytes + * // were sent. Could try again to send the remaining bytes. + * } + * } + * @endcode + * \defgroup xStreamBufferSend xStreamBufferSend + * \ingroup StreamBufferManagement + */ +size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer, + * const void *pvTxData, + * size_t xDataLengthBytes, + * BaseType_t *pxHigherPriorityTaskWoken ); + * @endcode + * + * Interrupt safe version of the API function that sends a stream of bytes to + * the stream buffer. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xStreamBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xStreamBufferReceive()) inside a critical section and set the receive + * block time to 0. + * + * Use xStreamBufferSend() to write to a stream buffer from a task. Use + * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt + * service routine (ISR). + * + * @param xStreamBuffer The handle of the stream buffer to which a stream is + * being sent. + * + * @param pvTxData A pointer to the data that is to be copied into the stream + * buffer. + * + * @param xDataLengthBytes The maximum number of bytes to copy from pvTxData + * into the stream buffer. + * + * @param pxHigherPriorityTaskWoken It is possible that a stream buffer will + * have a task blocked on it waiting for data. Calling + * xStreamBufferSendFromISR() can make data available, and so cause a task that + * was waiting for data to leave the Blocked state. If calling + * xStreamBufferSendFromISR() causes a task to leave the Blocked state, and the + * unblocked task has a priority higher than the currently executing task (the + * task that was interrupted), then, internally, xStreamBufferSendFromISR() + * will set *pxHigherPriorityTaskWoken to pdTRUE. If + * xStreamBufferSendFromISR() sets this value to pdTRUE, then normally a + * context switch should be performed before the interrupt is exited. This will + * ensure that the interrupt returns directly to the highest priority Ready + * state task. *pxHigherPriorityTaskWoken should be set to pdFALSE before it + * is passed into the function. See the example code below for an example. + * + * @return The number of bytes actually written to the stream buffer, which will + * be less than xDataLengthBytes if the stream buffer didn't have enough free + * space for all the bytes to be written. + * + * Example use: + * @code{c} + * // A stream buffer that has already been created. + * StreamBufferHandle_t xStreamBuffer; + * + * void vAnInterruptServiceRoutine( void ) + * { + * size_t xBytesSent; + * char *pcStringToSend = "String to send"; + * BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE. + * + * // Attempt to send the string to the stream buffer. + * xBytesSent = xStreamBufferSendFromISR( xStreamBuffer, + * ( void * ) pcStringToSend, + * strlen( pcStringToSend ), + * &xHigherPriorityTaskWoken ); + * + * if( xBytesSent != strlen( pcStringToSend ) ) + * { + * // There was not enough free space in the stream buffer for the entire + * // string to be written, ut xBytesSent bytes were written. + * } + * + * // If xHigherPriorityTaskWoken was set to pdTRUE inside + * // xStreamBufferSendFromISR() then a task that has a priority above the + * // priority of the currently executing task was unblocked and a context + * // switch should be performed to ensure the ISR returns to the unblocked + * // task. In most FreeRTOS ports this is done by simply passing + * // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the + * // variables value, and perform the context switch if necessary. Check the + * // documentation for the port in use for port specific instructions. + * taskYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + * } + * @endcode + * \defgroup xStreamBufferSendFromISR xStreamBufferSendFromISR + * \ingroup StreamBufferManagement + */ +size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + * void *pvRxData, + * size_t xBufferLengthBytes, + * TickType_t xTicksToWait ); + * @endcode + * + * Receives bytes from a stream buffer. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xStreamBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xStreamBufferReceive()) inside a critical section and set the receive + * block time to 0. + * + * Use xStreamBufferReceive() to read from a stream buffer from a task. Use + * xStreamBufferReceiveFromISR() to read from a stream buffer from an + * interrupt service routine (ISR). + * + * @param xStreamBuffer The handle of the stream buffer from which bytes are to + * be received. + * + * @param pvRxData A pointer to the buffer into which the received bytes will be + * copied. + * + * @param xBufferLengthBytes The length of the buffer pointed to by the + * pvRxData parameter. This sets the maximum number of bytes to receive in one + * call. xStreamBufferReceive will return as many bytes as possible up to a + * maximum set by xBufferLengthBytes. + * + * @param xTicksToWait The maximum amount of time the task should remain in the + * Blocked state to wait for data to become available if the stream buffer is + * empty. xStreamBufferReceive() will return immediately if xTicksToWait is + * zero. The block time is specified in tick periods, so the absolute time it + * represents is dependent on the tick frequency. The macro pdMS_TO_TICKS() can + * be used to convert a time specified in milliseconds into a time specified in + * ticks. Setting xTicksToWait to portMAX_DELAY will cause the task to wait + * indefinitely (without timing out), provided INCLUDE_vTaskSuspend is set to 1 + * in FreeRTOSConfig.h. A task does not use any CPU time when it is in the + * Blocked state. + * + * @return The number of bytes actually read from the stream buffer, which will + * be less than xBufferLengthBytes if the call to xStreamBufferReceive() timed + * out before xBufferLengthBytes were available. + * + * Example use: + * @code{c} + * void vAFunction( StreamBuffer_t xStreamBuffer ) + * { + * uint8_t ucRxData[ 20 ]; + * size_t xReceivedBytes; + * const TickType_t xBlockTime = pdMS_TO_TICKS( 20 ); + * + * // Receive up to another sizeof( ucRxData ) bytes from the stream buffer. + * // Wait in the Blocked state (so not using any CPU processing time) for a + * // maximum of 100ms for the full sizeof( ucRxData ) number of bytes to be + * // available. + * xReceivedBytes = xStreamBufferReceive( xStreamBuffer, + * ( void * ) ucRxData, + * sizeof( ucRxData ), + * xBlockTime ); + * + * if( xReceivedBytes > 0 ) + * { + * // A ucRxData contains another xRecievedBytes bytes of data, which can + * // be processed here.... + * } + * } + * @endcode + * \defgroup xStreamBufferReceive xStreamBufferReceive + * \ingroup StreamBufferManagement + */ +size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer, + * void *pvRxData, + * size_t xBufferLengthBytes, + * BaseType_t *pxHigherPriorityTaskWoken ); + * @endcode + * + * An interrupt safe version of the API function that receives bytes from a + * stream buffer. + * + * Use xStreamBufferReceive() to read bytes from a stream buffer from a task. + * Use xStreamBufferReceiveFromISR() to read bytes from a stream buffer from an + * interrupt service routine (ISR). + * + * @param xStreamBuffer The handle of the stream buffer from which a stream + * is being received. + * + * @param pvRxData A pointer to the buffer into which the received bytes are + * copied. + * + * @param xBufferLengthBytes The length of the buffer pointed to by the + * pvRxData parameter. This sets the maximum number of bytes to receive in one + * call. xStreamBufferReceive will return as many bytes as possible up to a + * maximum set by xBufferLengthBytes. + * + * @param pxHigherPriorityTaskWoken It is possible that a stream buffer will + * have a task blocked on it waiting for space to become available. Calling + * xStreamBufferReceiveFromISR() can make space available, and so cause a task + * that is waiting for space to leave the Blocked state. If calling + * xStreamBufferReceiveFromISR() causes a task to leave the Blocked state, and + * the unblocked task has a priority higher than the currently executing task + * (the task that was interrupted), then, internally, + * xStreamBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE. + * If xStreamBufferReceiveFromISR() sets this value to pdTRUE, then normally a + * context switch should be performed before the interrupt is exited. That will + * ensure the interrupt returns directly to the highest priority Ready state + * task. *pxHigherPriorityTaskWoken should be set to pdFALSE before it is + * passed into the function. See the code example below for an example. + * + * @return The number of bytes read from the stream buffer, if any. + * + * Example use: + * @code{c} + * // A stream buffer that has already been created. + * StreamBuffer_t xStreamBuffer; + * + * void vAnInterruptServiceRoutine( void ) + * { + * uint8_t ucRxData[ 20 ]; + * size_t xReceivedBytes; + * BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE. + * + * // Receive the next stream from the stream buffer. + * xReceivedBytes = xStreamBufferReceiveFromISR( xStreamBuffer, + * ( void * ) ucRxData, + * sizeof( ucRxData ), + * &xHigherPriorityTaskWoken ); + * + * if( xReceivedBytes > 0 ) + * { + * // ucRxData contains xReceivedBytes read from the stream buffer. + * // Process the stream here.... + * } + * + * // If xHigherPriorityTaskWoken was set to pdTRUE inside + * // xStreamBufferReceiveFromISR() then a task that has a priority above the + * // priority of the currently executing task was unblocked and a context + * // switch should be performed to ensure the ISR returns to the unblocked + * // task. In most FreeRTOS ports this is done by simply passing + * // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the + * // variables value, and perform the context switch if necessary. Check the + * // documentation for the port in use for port specific instructions. + * taskYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + * } + * @endcode + * \defgroup xStreamBufferReceiveFromISR xStreamBufferReceiveFromISR + * \ingroup StreamBufferManagement + */ +size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ); + * @endcode + * + * Deletes a stream buffer that was previously created using a call to + * xStreamBufferCreate() or xStreamBufferCreateStatic(). If the stream + * buffer was created using dynamic memory (that is, by xStreamBufferCreate()), + * then the allocated memory is freed. + * + * A stream buffer handle must not be used after the stream buffer has been + * deleted. + * + * @param xStreamBuffer The handle of the stream buffer to be deleted. + * + * \defgroup vStreamBufferDelete vStreamBufferDelete + * \ingroup StreamBufferManagement + */ +void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ); + * @endcode + * + * Queries a stream buffer to see if it is full. A stream buffer is full if it + * does not have any free space, and therefore cannot accept any more data. + * + * @param xStreamBuffer The handle of the stream buffer being queried. + * + * @return If the stream buffer is full then pdTRUE is returned. Otherwise + * pdFALSE is returned. + * + * \defgroup xStreamBufferIsFull xStreamBufferIsFull + * \ingroup StreamBufferManagement + */ +BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ); + * @endcode + * + * Queries a stream buffer to see if it is empty. A stream buffer is empty if + * it does not contain any data. + * + * @param xStreamBuffer The handle of the stream buffer being queried. + * + * @return If the stream buffer is empty then pdTRUE is returned. Otherwise + * pdFALSE is returned. + * + * \defgroup xStreamBufferIsEmpty xStreamBufferIsEmpty + * \ingroup StreamBufferManagement + */ +BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ); + * @endcode + * + * Resets a stream buffer to its initial, empty, state. Any data that was in + * the stream buffer is discarded. A stream buffer can only be reset if there + * are no tasks blocked waiting to either send to or receive from the stream + * buffer. + * + * @param xStreamBuffer The handle of the stream buffer being reset. + * + * @return If the stream buffer is reset then pdPASS is returned. If there was + * a task blocked waiting to send to or read from the stream buffer then the + * stream buffer is not reset and pdFAIL is returned. + * + * \defgroup xStreamBufferReset xStreamBufferReset + * \ingroup StreamBufferManagement + */ +BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ); + * @endcode + * + * Queries a stream buffer to see how much free space it contains, which is + * equal to the amount of data that can be sent to the stream buffer before it + * is full. + * + * @param xStreamBuffer The handle of the stream buffer being queried. + * + * @return The number of bytes that can be written to the stream buffer before + * the stream buffer would be full. + * + * \defgroup xStreamBufferSpacesAvailable xStreamBufferSpacesAvailable + * \ingroup StreamBufferManagement + */ +size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ); + * @endcode + * + * Queries a stream buffer to see how much data it contains, which is equal to + * the number of bytes that can be read from the stream buffer before the stream + * buffer would be empty. + * + * @param xStreamBuffer The handle of the stream buffer being queried. + * + * @return The number of bytes that can be read from the stream buffer before + * the stream buffer would be empty. + * + * \defgroup xStreamBufferBytesAvailable xStreamBufferBytesAvailable + * \ingroup StreamBufferManagement + */ +size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ); + * @endcode + * + * A stream buffer's trigger level is the number of bytes that must be in the + * stream buffer before a task that is blocked on the stream buffer to + * wait for data is moved out of the blocked state. For example, if a task is + * blocked on a read of an empty stream buffer that has a trigger level of 1 + * then the task will be unblocked when a single byte is written to the buffer + * or the task's block time expires. As another example, if a task is blocked + * on a read of an empty stream buffer that has a trigger level of 10 then the + * task will not be unblocked until the stream buffer contains at least 10 bytes + * or the task's block time expires. If a reading task's block time expires + * before the trigger level is reached then the task will still receive however + * many bytes are actually available. Setting a trigger level of 0 will result + * in a trigger level of 1 being used. It is not valid to specify a trigger + * level that is greater than the buffer size. + * + * A trigger level is set when the stream buffer is created, and can be modified + * using xStreamBufferSetTriggerLevel(). + * + * @param xStreamBuffer The handle of the stream buffer being updated. + * + * @param xTriggerLevel The new trigger level for the stream buffer. + * + * @return If xTriggerLevel was less than or equal to the stream buffer's length + * then the trigger level will be updated and pdTRUE is returned. Otherwise + * pdFALSE is returned. + * + * \defgroup xStreamBufferSetTriggerLevel xStreamBufferSetTriggerLevel + * \ingroup StreamBufferManagement + */ +BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ); + * @endcode + * + * For advanced users only. + * + * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when + * data is sent to a message buffer or stream buffer. If there was a task that + * was blocked on the message or stream buffer waiting for data to arrive then + * the sbSEND_COMPLETED() macro sends a notification to the task to remove it + * from the Blocked state. xStreamBufferSendCompletedFromISR() does the same + * thing. It is provided to enable application writers to implement their own + * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME. + * + * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for + * additional information. + * + * @param xStreamBuffer The handle of the stream buffer to which data was + * written. + * + * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be + * initialised to pdFALSE before it is passed into + * xStreamBufferSendCompletedFromISR(). If calling + * xStreamBufferSendCompletedFromISR() removes a task from the Blocked state, + * and the task has a priority above the priority of the currently running task, + * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a + * context switch should be performed before exiting the ISR. + * + * @return If a task was removed from the Blocked state then pdTRUE is returned. + * Otherwise pdFALSE is returned. + * + * \defgroup xStreamBufferSendCompletedFromISR xStreamBufferSendCompletedFromISR + * \ingroup StreamBufferManagement + */ +BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, + BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ); + * @endcode + * + * For advanced users only. + * + * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when + * data is read out of a message buffer or stream buffer. If there was a task + * that was blocked on the message or stream buffer waiting for data to arrive + * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to + * remove it from the Blocked state. xStreamBufferReceiveCompletedFromISR() + * does the same thing. It is provided to enable application writers to + * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT + * ANY OTHER TIME. + * + * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for + * additional information. + * + * @param xStreamBuffer The handle of the stream buffer from which data was + * read. + * + * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be + * initialised to pdFALSE before it is passed into + * xStreamBufferReceiveCompletedFromISR(). If calling + * xStreamBufferReceiveCompletedFromISR() removes a task from the Blocked state, + * and the task has a priority above the priority of the currently running task, + * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a + * context switch should be performed before exiting the ISR. + * + * @return If a task was removed from the Blocked state then pdTRUE is returned. + * Otherwise pdFALSE is returned. + * + * \defgroup xStreamBufferReceiveCompletedFromISR xStreamBufferReceiveCompletedFromISR + * \ingroup StreamBufferManagement + */ +BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, + BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/* Functions below here are not part of the public API. */ +StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xIsMessageBuffer ) PRIVILEGED_FUNCTION; + +StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xIsMessageBuffer, + uint8_t * const pucStreamBufferStorageArea, + StaticStreamBuffer_t * const pxStaticStreamBuffer ) PRIVILEGED_FUNCTION; + +size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +#if ( configUSE_TRACE_FACILITY == 1 ) + void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, + UBaseType_t uxStreamBufferNumber ) PRIVILEGED_FUNCTION; + UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; +#endif + +/* *INDENT-OFF* */ +#if defined( __cplusplus ) + } +#endif +/* *INDENT-ON* */ + +#endif /* !defined( STREAM_BUFFER_H ) */ diff --git a/hw-libs/freertos/include/task.h b/hw-libs/freertos/include/task.h new file mode 100644 index 000000000..e3e6e9849 --- /dev/null +++ b/hw-libs/freertos/include/task.h @@ -0,0 +1,3127 @@ +/* + * FreeRTOS Kernel V10.4.6 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef INC_TASK_H +#define INC_TASK_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include task.h" +#endif + +#include "list.h" + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- +* MACROS AND DEFINITIONS +*----------------------------------------------------------*/ + +/* + * If tskKERNEL_VERSION_NUMBER ends with + it represents the version in development + * after the numbered release. + * + * The tskKERNEL_VERSION_MAJOR, tskKERNEL_VERSION_MINOR, tskKERNEL_VERSION_BUILD + * values will reflect the last released version number. + */ +#define tskKERNEL_VERSION_NUMBER "V10.4.6" +#define tskKERNEL_VERSION_MAJOR 10 +#define tskKERNEL_VERSION_MINOR 4 +#define tskKERNEL_VERSION_BUILD 6 + +/* MPU region parameters passed in ulParameters + * of MemoryRegion_t struct. */ +#define tskMPU_REGION_READ_ONLY ( 1UL << 0UL ) +#define tskMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define tskMPU_REGION_EXECUTE_NEVER ( 1UL << 2UL ) +#define tskMPU_REGION_NORMAL_MEMORY ( 1UL << 3UL ) +#define tskMPU_REGION_DEVICE_MEMORY ( 1UL << 4UL ) + +/* The direct to task notification feature used to have only a single notification + * per task. Now there is an array of notifications per task that is dimensioned by + * configTASK_NOTIFICATION_ARRAY_ENTRIES. For backward compatibility, any use of the + * original direct to task notification defaults to using the first index in the + * array. */ +#define tskDEFAULT_INDEX_TO_NOTIFY ( 0 ) + +/** + * task. h + * + * Type by which tasks are referenced. For example, a call to xTaskCreate + * returns (via a pointer parameter) an TaskHandle_t variable that can then + * be used as a parameter to vTaskDelete to delete the task. + * + * \defgroup TaskHandle_t TaskHandle_t + * \ingroup Tasks + */ +struct tskTaskControlBlock; /* The old naming convention is used to prevent breaking kernel aware debuggers. */ +typedef struct tskTaskControlBlock * TaskHandle_t; + +/* + * Defines the prototype to which the application task hook function must + * conform. + */ +typedef BaseType_t (* TaskHookFunction_t)( void * ); + +/* Task states returned by eTaskGetState. */ +typedef enum +{ + eRunning = 0, /* A task is querying the state of itself, so must be running. */ + eReady, /* The task being queried is in a ready or pending ready list. */ + eBlocked, /* The task being queried is in the Blocked state. */ + eSuspended, /* The task being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */ + eDeleted, /* The task being queried has been deleted, but its TCB has not yet been freed. */ + eInvalid /* Used as an 'invalid state' value. */ +} eTaskState; + +/* Actions that can be performed when vTaskNotify() is called. */ +typedef enum +{ + eNoAction = 0, /* Notify the task without updating its notify value. */ + eSetBits, /* Set bits in the task's notification value. */ + eIncrement, /* Increment the task's notification value. */ + eSetValueWithOverwrite, /* Set the task's notification value to a specific value even if the previous value has not yet been read by the task. */ + eSetValueWithoutOverwrite /* Set the task's notification value if the previous value has been read by the task. */ +} eNotifyAction; + +/* + * Used internally only. + */ +typedef struct xTIME_OUT +{ + BaseType_t xOverflowCount; + TickType_t xTimeOnEntering; +} TimeOut_t; + +/* + * Defines the memory ranges allocated to the task when an MPU is used. + */ +typedef struct xMEMORY_REGION +{ + void * pvBaseAddress; + uint32_t ulLengthInBytes; + uint32_t ulParameters; +} MemoryRegion_t; + +/* + * Parameters required to create an MPU protected task. + */ +typedef struct xTASK_PARAMETERS +{ + TaskFunction_t pvTaskCode; + const char * pcName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + configSTACK_DEPTH_TYPE usStackDepth; + void * pvParameters; + UBaseType_t uxPriority; + StackType_t * puxStackBuffer; + MemoryRegion_t xRegions[ portNUM_CONFIGURABLE_REGIONS ]; + #if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + StaticTask_t * const pxTaskBuffer; + #endif +} TaskParameters_t; + +/* Used with the uxTaskGetSystemState() function to return the state of each task + * in the system. */ +typedef struct xTASK_STATUS +{ + TaskHandle_t xHandle; /* The handle of the task to which the rest of the information in the structure relates. */ + const char * pcTaskName; /* A pointer to the task's name. This value will be invalid if the task was deleted since the structure was populated! */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + UBaseType_t xTaskNumber; /* A number unique to the task. */ + eTaskState eCurrentState; /* The state in which the task existed when the structure was populated. */ + UBaseType_t uxCurrentPriority; /* The priority at which the task was running (may be inherited) when the structure was populated. */ + UBaseType_t uxBasePriority; /* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex. Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */ + configRUN_TIME_COUNTER_TYPE ulRunTimeCounter; /* The total run time allocated to the task so far, as defined by the run time stats clock. See https://www.FreeRTOS.org/rtos-run-time-stats.html. Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */ + StackType_t * pxStackBase; /* Points to the lowest address of the task's stack area. */ + configSTACK_DEPTH_TYPE usStackHighWaterMark; /* The minimum amount of stack space that has remained for the task since the task was created. The closer this value is to zero the closer the task has come to overflowing its stack. */ +} TaskStatus_t; + +/* Possible return values for eTaskConfirmSleepModeStatus(). */ +typedef enum +{ + eAbortSleep = 0, /* A task has been made ready or a context switch pended since portSUPPRESS_TICKS_AND_SLEEP() was called - abort entering a sleep mode. */ + eStandardSleep, /* Enter a sleep mode that will not last any longer than the expected idle time. */ + eNoTasksWaitingTimeout /* No tasks are waiting for a timeout so it is safe to enter a sleep mode that can only be exited by an external interrupt. */ +} eSleepModeStatus; + +/** + * Defines the priority used by the idle task. This must not be modified. + * + * \ingroup TaskUtils + */ +#define tskIDLE_PRIORITY ( ( UBaseType_t ) 0U ) + +/** + * task. h + * + * Macro for forcing a context switch. + * + * \defgroup taskYIELD taskYIELD + * \ingroup SchedulerControl + */ +#define taskYIELD() portYIELD() + +/** + * task. h + * + * Macro to mark the start of a critical code region. Preemptive context + * switches cannot occur when in a critical region. + * + * NOTE: This may alter the stack (depending on the portable implementation) + * so must be used with care! + * + * \defgroup taskENTER_CRITICAL taskENTER_CRITICAL + * \ingroup SchedulerControl + */ +#define taskENTER_CRITICAL() portENTER_CRITICAL() +#define taskENTER_CRITICAL_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR() + +/** + * task. h + * + * Macro to mark the end of a critical code region. Preemptive context + * switches cannot occur when in a critical region. + * + * NOTE: This may alter the stack (depending on the portable implementation) + * so must be used with care! + * + * \defgroup taskEXIT_CRITICAL taskEXIT_CRITICAL + * \ingroup SchedulerControl + */ +#define taskEXIT_CRITICAL() portEXIT_CRITICAL() +#define taskEXIT_CRITICAL_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) + +/** + * task. h + * + * Macro to disable all maskable interrupts. + * + * \defgroup taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS + * \ingroup SchedulerControl + */ +#define taskDISABLE_INTERRUPTS() portDISABLE_INTERRUPTS() + +/** + * task. h + * + * Macro to enable microcontroller interrupts. + * + * \defgroup taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS + * \ingroup SchedulerControl + */ +#define taskENABLE_INTERRUPTS() portENABLE_INTERRUPTS() + +/* Definitions returned by xTaskGetSchedulerState(). taskSCHEDULER_SUSPENDED is + * 0 to generate more optimal code when configASSERT() is defined as the constant + * is used in assert() statements. */ +#define taskSCHEDULER_SUSPENDED ( ( BaseType_t ) 0 ) +#define taskSCHEDULER_NOT_STARTED ( ( BaseType_t ) 1 ) +#define taskSCHEDULER_RUNNING ( ( BaseType_t ) 2 ) + + +/*----------------------------------------------------------- +* TASK CREATION API +*----------------------------------------------------------*/ + +/** + * task. h + * @code{c} + * BaseType_t xTaskCreate( + * TaskFunction_t pxTaskCode, + * const char *pcName, + * configSTACK_DEPTH_TYPE usStackDepth, + * void *pvParameters, + * UBaseType_t uxPriority, + * TaskHandle_t *pxCreatedTask + * ); + * @endcode + * + * Create a new task and add it to the list of tasks that are ready to run. + * + * Internally, within the FreeRTOS implementation, tasks use two blocks of + * memory. The first block is used to hold the task's data structures. The + * second block is used by the task as its stack. If a task is created using + * xTaskCreate() then both blocks of memory are automatically dynamically + * allocated inside the xTaskCreate() function. (see + * https://www.FreeRTOS.org/a00111.html). If a task is created using + * xTaskCreateStatic() then the application writer must provide the required + * memory. xTaskCreateStatic() therefore allows a task to be created without + * using any dynamic memory allocation. + * + * See xTaskCreateStatic() for a version that does not use any dynamic memory + * allocation. + * + * xTaskCreate() can only be used to create a task that has unrestricted + * access to the entire microcontroller memory map. Systems that include MPU + * support can alternatively create an MPU constrained task using + * xTaskCreateRestricted(). + * + * @param pxTaskCode Pointer to the task entry function. Tasks + * must be implemented to never return (i.e. continuous loop). + * + * @param pcName A descriptive name for the task. This is mainly used to + * facilitate debugging. Max length defined by configMAX_TASK_NAME_LEN - default + * is 16. + * + * @param usStackDepth The size of the task stack specified as the number of + * variables the stack can hold - not the number of bytes. For example, if + * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes + * will be allocated for stack storage. + * + * @param pvParameters Pointer that will be used as the parameter for the task + * being created. + * + * @param uxPriority The priority at which the task should run. Systems that + * include MPU support can optionally create tasks in a privileged (system) + * mode by setting bit portPRIVILEGE_BIT of the priority parameter. For + * example, to create a privileged task at priority 2 the uxPriority parameter + * should be set to ( 2 | portPRIVILEGE_BIT ). + * + * @param pxCreatedTask Used to pass back a handle by which the created task + * can be referenced. + * + * @return pdPASS if the task was successfully created and added to a ready + * list, otherwise an error code defined in the file projdefs.h + * + * Example usage: + * @code{c} + * // Task to be created. + * void vTaskCode( void * pvParameters ) + * { + * for( ;; ) + * { + * // Task code goes here. + * } + * } + * + * // Function that creates a task. + * void vOtherFunction( void ) + * { + * static uint8_t ucParameterToPass; + * TaskHandle_t xHandle = NULL; + * + * // Create the task, storing the handle. Note that the passed parameter ucParameterToPass + * // must exist for the lifetime of the task, so in this case is declared static. If it was just an + * // an automatic stack variable it might no longer exist, or at least have been corrupted, by the time + * // the new task attempts to access it. + * xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle ); + * configASSERT( xHandle ); + * + * // Use the handle to delete the task. + * if( xHandle != NULL ) + * { + * vTaskDelete( xHandle ); + * } + * } + * @endcode + * \defgroup xTaskCreate xTaskCreate + * \ingroup Tasks + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + BaseType_t xTaskCreate( TaskFunction_t pxTaskCode, + const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const configSTACK_DEPTH_TYPE usStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION; +#endif + +/** + * task. h + * @code{c} + * TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode, + * const char *pcName, + * uint32_t ulStackDepth, + * void *pvParameters, + * UBaseType_t uxPriority, + * StackType_t *puxStackBuffer, + * StaticTask_t *pxTaskBuffer ); + * @endcode + * + * Create a new task and add it to the list of tasks that are ready to run. + * + * Internally, within the FreeRTOS implementation, tasks use two blocks of + * memory. The first block is used to hold the task's data structures. The + * second block is used by the task as its stack. If a task is created using + * xTaskCreate() then both blocks of memory are automatically dynamically + * allocated inside the xTaskCreate() function. (see + * https://www.FreeRTOS.org/a00111.html). If a task is created using + * xTaskCreateStatic() then the application writer must provide the required + * memory. xTaskCreateStatic() therefore allows a task to be created without + * using any dynamic memory allocation. + * + * @param pxTaskCode Pointer to the task entry function. Tasks + * must be implemented to never return (i.e. continuous loop). + * + * @param pcName A descriptive name for the task. This is mainly used to + * facilitate debugging. The maximum length of the string is defined by + * configMAX_TASK_NAME_LEN in FreeRTOSConfig.h. + * + * @param ulStackDepth The size of the task stack specified as the number of + * variables the stack can hold - not the number of bytes. For example, if + * the stack is 32-bits wide and ulStackDepth is defined as 100 then 400 bytes + * will be allocated for stack storage. + * + * @param pvParameters Pointer that will be used as the parameter for the task + * being created. + * + * @param uxPriority The priority at which the task will run. + * + * @param puxStackBuffer Must point to a StackType_t array that has at least + * ulStackDepth indexes - the array will then be used as the task's stack, + * removing the need for the stack to be allocated dynamically. + * + * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will + * then be used to hold the task's data structures, removing the need for the + * memory to be allocated dynamically. + * + * @return If neither puxStackBuffer nor pxTaskBuffer are NULL, then the task + * will be created and a handle to the created task is returned. If either + * puxStackBuffer or pxTaskBuffer are NULL then the task will not be created and + * NULL is returned. + * + * Example usage: + * @code{c} + * + * // Dimensions of the buffer that the task being created will use as its stack. + * // NOTE: This is the number of words the stack will hold, not the number of + * // bytes. For example, if each stack item is 32-bits, and this is set to 100, + * // then 400 bytes (100 * 32-bits) will be allocated. + #define STACK_SIZE 200 + * + * // Structure that will hold the TCB of the task being created. + * StaticTask_t xTaskBuffer; + * + * // Buffer that the task being created will use as its stack. Note this is + * // an array of StackType_t variables. The size of StackType_t is dependent on + * // the RTOS port. + * StackType_t xStack[ STACK_SIZE ]; + * + * // Function that implements the task being created. + * void vTaskCode( void * pvParameters ) + * { + * // The parameter value is expected to be 1 as 1 is passed in the + * // pvParameters value in the call to xTaskCreateStatic(). + * configASSERT( ( uint32_t ) pvParameters == 1UL ); + * + * for( ;; ) + * { + * // Task code goes here. + * } + * } + * + * // Function that creates a task. + * void vOtherFunction( void ) + * { + * TaskHandle_t xHandle = NULL; + * + * // Create the task without using any dynamic memory allocation. + * xHandle = xTaskCreateStatic( + * vTaskCode, // Function that implements the task. + * "NAME", // Text name for the task. + * STACK_SIZE, // Stack size in words, not bytes. + * ( void * ) 1, // Parameter passed into the task. + * tskIDLE_PRIORITY,// Priority at which the task is created. + * xStack, // Array to use as the task's stack. + * &xTaskBuffer ); // Variable to hold the task's data structure. + * + * // puxStackBuffer and pxTaskBuffer were not NULL, so the task will have + * // been created, and xHandle will be the task's handle. Use the handle + * // to suspend the task. + * vTaskSuspend( xHandle ); + * } + * @endcode + * \defgroup xTaskCreateStatic xTaskCreateStatic + * \ingroup Tasks + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode, + const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const uint32_t ulStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + StackType_t * const puxStackBuffer, + StaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION; +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/** + * task. h + * @code{c} + * BaseType_t xTaskCreateRestricted( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask ); + * @endcode + * + * Only available when configSUPPORT_DYNAMIC_ALLOCATION is set to 1. + * + * xTaskCreateRestricted() should only be used in systems that include an MPU + * implementation. + * + * Create a new task and add it to the list of tasks that are ready to run. + * The function parameters define the memory regions and associated access + * permissions allocated to the task. + * + * See xTaskCreateRestrictedStatic() for a version that does not use any + * dynamic memory allocation. + * + * @param pxTaskDefinition Pointer to a structure that contains a member + * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API + * documentation) plus an optional stack buffer and the memory region + * definitions. + * + * @param pxCreatedTask Used to pass back a handle by which the created task + * can be referenced. + * + * @return pdPASS if the task was successfully created and added to a ready + * list, otherwise an error code defined in the file projdefs.h + * + * Example usage: + * @code{c} + * // Create an TaskParameters_t structure that defines the task to be created. + * static const TaskParameters_t xCheckTaskParameters = + * { + * vATask, // pvTaskCode - the function that implements the task. + * "ATask", // pcName - just a text name for the task to assist debugging. + * 100, // usStackDepth - the stack size DEFINED IN WORDS. + * NULL, // pvParameters - passed into the task function as the function parameters. + * ( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state. + * cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack. + * + * // xRegions - Allocate up to three separate memory regions for access by + * // the task, with appropriate access permissions. Different processors have + * // different memory alignment requirements - refer to the FreeRTOS documentation + * // for full information. + * { + * // Base address Length Parameters + * { cReadWriteArray, 32, portMPU_REGION_READ_WRITE }, + * { cReadOnlyArray, 32, portMPU_REGION_READ_ONLY }, + * { cPrivilegedOnlyAccessArray, 128, portMPU_REGION_PRIVILEGED_READ_WRITE } + * } + * }; + * + * int main( void ) + * { + * TaskHandle_t xHandle; + * + * // Create a task from the const structure defined above. The task handle + * // is requested (the second parameter is not NULL) but in this case just for + * // demonstration purposes as its not actually used. + * xTaskCreateRestricted( &xRegTest1Parameters, &xHandle ); + * + * // Start the scheduler. + * vTaskStartScheduler(); + * + * // Will only get here if there was insufficient memory to create the idle + * // and/or timer task. + * for( ;; ); + * } + * @endcode + * \defgroup xTaskCreateRestricted xTaskCreateRestricted + * \ingroup Tasks + */ +#if ( portUSING_MPU_WRAPPERS == 1 ) + BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, + TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION; +#endif + +/** + * task. h + * @code{c} + * BaseType_t xTaskCreateRestrictedStatic( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask ); + * @endcode + * + * Only available when configSUPPORT_STATIC_ALLOCATION is set to 1. + * + * xTaskCreateRestrictedStatic() should only be used in systems that include an + * MPU implementation. + * + * Internally, within the FreeRTOS implementation, tasks use two blocks of + * memory. The first block is used to hold the task's data structures. The + * second block is used by the task as its stack. If a task is created using + * xTaskCreateRestricted() then the stack is provided by the application writer, + * and the memory used to hold the task's data structure is automatically + * dynamically allocated inside the xTaskCreateRestricted() function. If a task + * is created using xTaskCreateRestrictedStatic() then the application writer + * must provide the memory used to hold the task's data structures too. + * xTaskCreateRestrictedStatic() therefore allows a memory protected task to be + * created without using any dynamic memory allocation. + * + * @param pxTaskDefinition Pointer to a structure that contains a member + * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API + * documentation) plus an optional stack buffer and the memory region + * definitions. If configSUPPORT_STATIC_ALLOCATION is set to 1 the structure + * contains an additional member, which is used to point to a variable of type + * StaticTask_t - which is then used to hold the task's data structure. + * + * @param pxCreatedTask Used to pass back a handle by which the created task + * can be referenced. + * + * @return pdPASS if the task was successfully created and added to a ready + * list, otherwise an error code defined in the file projdefs.h + * + * Example usage: + * @code{c} + * // Create an TaskParameters_t structure that defines the task to be created. + * // The StaticTask_t variable is only included in the structure when + * // configSUPPORT_STATIC_ALLOCATION is set to 1. The PRIVILEGED_DATA macro can + * // be used to force the variable into the RTOS kernel's privileged data area. + * static PRIVILEGED_DATA StaticTask_t xTaskBuffer; + * static const TaskParameters_t xCheckTaskParameters = + * { + * vATask, // pvTaskCode - the function that implements the task. + * "ATask", // pcName - just a text name for the task to assist debugging. + * 100, // usStackDepth - the stack size DEFINED IN WORDS. + * NULL, // pvParameters - passed into the task function as the function parameters. + * ( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state. + * cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack. + * + * // xRegions - Allocate up to three separate memory regions for access by + * // the task, with appropriate access permissions. Different processors have + * // different memory alignment requirements - refer to the FreeRTOS documentation + * // for full information. + * { + * // Base address Length Parameters + * { cReadWriteArray, 32, portMPU_REGION_READ_WRITE }, + * { cReadOnlyArray, 32, portMPU_REGION_READ_ONLY }, + * { cPrivilegedOnlyAccessArray, 128, portMPU_REGION_PRIVILEGED_READ_WRITE } + * } + * + * &xTaskBuffer; // Holds the task's data structure. + * }; + * + * int main( void ) + * { + * TaskHandle_t xHandle; + * + * // Create a task from the const structure defined above. The task handle + * // is requested (the second parameter is not NULL) but in this case just for + * // demonstration purposes as its not actually used. + * xTaskCreateRestricted( &xRegTest1Parameters, &xHandle ); + * + * // Start the scheduler. + * vTaskStartScheduler(); + * + * // Will only get here if there was insufficient memory to create the idle + * // and/or timer task. + * for( ;; ); + * } + * @endcode + * \defgroup xTaskCreateRestrictedStatic xTaskCreateRestrictedStatic + * \ingroup Tasks + */ +#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, + TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION; +#endif + +/** + * task. h + * @code{c} + * void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ); + * @endcode + * + * Memory regions are assigned to a restricted task when the task is created by + * a call to xTaskCreateRestricted(). These regions can be redefined using + * vTaskAllocateMPURegions(). + * + * @param xTask The handle of the task being updated. + * + * @param xRegions A pointer to a MemoryRegion_t structure that contains the + * new memory region definitions. + * + * Example usage: + * @code{c} + * // Define an array of MemoryRegion_t structures that configures an MPU region + * // allowing read/write access for 1024 bytes starting at the beginning of the + * // ucOneKByte array. The other two of the maximum 3 definable regions are + * // unused so set to zero. + * static const MemoryRegion_t xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] = + * { + * // Base address Length Parameters + * { ucOneKByte, 1024, portMPU_REGION_READ_WRITE }, + * { 0, 0, 0 }, + * { 0, 0, 0 } + * }; + * + * void vATask( void *pvParameters ) + * { + * // This task was created such that it has access to certain regions of + * // memory as defined by the MPU configuration. At some point it is + * // desired that these MPU regions are replaced with that defined in the + * // xAltRegions const struct above. Use a call to vTaskAllocateMPURegions() + * // for this purpose. NULL is used as the task handle to indicate that this + * // function should modify the MPU regions of the calling task. + * vTaskAllocateMPURegions( NULL, xAltRegions ); + * + * // Now the task can continue its function, but from this point on can only + * // access its stack and the ucOneKByte array (unless any other statically + * // defined or shared regions have been declared elsewhere). + * } + * @endcode + * \defgroup xTaskCreateRestricted xTaskCreateRestricted + * \ingroup Tasks + */ +void vTaskAllocateMPURegions( TaskHandle_t xTask, + const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * void vTaskDelete( TaskHandle_t xTaskToDelete ); + * @endcode + * + * INCLUDE_vTaskDelete must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Remove a task from the RTOS real time kernel's management. The task being + * deleted will be removed from all ready, blocked, suspended and event lists. + * + * NOTE: The idle task is responsible for freeing the kernel allocated + * memory from tasks that have been deleted. It is therefore important that + * the idle task is not starved of microcontroller processing time if your + * application makes any calls to vTaskDelete (). Memory allocated by the + * task code is not automatically freed, and should be freed before the task + * is deleted. + * + * See the demo application file death.c for sample code that utilises + * vTaskDelete (). + * + * @param xTaskToDelete The handle of the task to be deleted. Passing NULL will + * cause the calling task to be deleted. + * + * Example usage: + * @code{c} + * void vOtherFunction( void ) + * { + * TaskHandle_t xHandle; + * + * // Create the task, storing the handle. + * xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle ); + * + * // Use the handle to delete the task. + * vTaskDelete( xHandle ); + * } + * @endcode + * \defgroup vTaskDelete vTaskDelete + * \ingroup Tasks + */ +void vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION; + +/*----------------------------------------------------------- +* TASK CONTROL API +*----------------------------------------------------------*/ + +/** + * task. h + * @code{c} + * void vTaskDelay( const TickType_t xTicksToDelay ); + * @endcode + * + * Delay a task for a given number of ticks. The actual time that the + * task remains blocked depends on the tick rate. The constant + * portTICK_PERIOD_MS can be used to calculate real time from the tick + * rate - with the resolution of one tick period. + * + * INCLUDE_vTaskDelay must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * + * vTaskDelay() specifies a time at which the task wishes to unblock relative to + * the time at which vTaskDelay() is called. For example, specifying a block + * period of 100 ticks will cause the task to unblock 100 ticks after + * vTaskDelay() is called. vTaskDelay() does not therefore provide a good method + * of controlling the frequency of a periodic task as the path taken through the + * code, as well as other task and interrupt activity, will affect the frequency + * at which vTaskDelay() gets called and therefore the time at which the task + * next executes. See xTaskDelayUntil() for an alternative API function designed + * to facilitate fixed frequency execution. It does this by specifying an + * absolute time (rather than a relative time) at which the calling task should + * unblock. + * + * @param xTicksToDelay The amount of time, in tick periods, that + * the calling task should block. + * + * Example usage: + * + * void vTaskFunction( void * pvParameters ) + * { + * // Block for 500ms. + * const TickType_t xDelay = 500 / portTICK_PERIOD_MS; + * + * for( ;; ) + * { + * // Simply toggle the LED every 500ms, blocking between each toggle. + * vToggleLED(); + * vTaskDelay( xDelay ); + * } + * } + * + * \defgroup vTaskDelay vTaskDelay + * \ingroup TaskCtrl + */ +void vTaskDelay( const TickType_t xTicksToDelay ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * BaseType_t xTaskDelayUntil( TickType_t *pxPreviousWakeTime, const TickType_t xTimeIncrement ); + * @endcode + * + * INCLUDE_xTaskDelayUntil must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Delay a task until a specified time. This function can be used by periodic + * tasks to ensure a constant execution frequency. + * + * This function differs from vTaskDelay () in one important aspect: vTaskDelay () will + * cause a task to block for the specified number of ticks from the time vTaskDelay () is + * called. It is therefore difficult to use vTaskDelay () by itself to generate a fixed + * execution frequency as the time between a task starting to execute and that task + * calling vTaskDelay () may not be fixed [the task may take a different path though the + * code between calls, or may get interrupted or preempted a different number of times + * each time it executes]. + * + * Whereas vTaskDelay () specifies a wake time relative to the time at which the function + * is called, xTaskDelayUntil () specifies the absolute (exact) time at which it wishes to + * unblock. + * + * The macro pdMS_TO_TICKS() can be used to calculate the number of ticks from a + * time specified in milliseconds with a resolution of one tick period. + * + * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the + * task was last unblocked. The variable must be initialised with the current time + * prior to its first use (see the example below). Following this the variable is + * automatically updated within xTaskDelayUntil (). + * + * @param xTimeIncrement The cycle time period. The task will be unblocked at + * time *pxPreviousWakeTime + xTimeIncrement. Calling xTaskDelayUntil with the + * same xTimeIncrement parameter value will cause the task to execute with + * a fixed interface period. + * + * @return Value which can be used to check whether the task was actually delayed. + * Will be pdTRUE if the task way delayed and pdFALSE otherwise. A task will not + * be delayed if the next expected wake time is in the past. + * + * Example usage: + * @code{c} + * // Perform an action every 10 ticks. + * void vTaskFunction( void * pvParameters ) + * { + * TickType_t xLastWakeTime; + * const TickType_t xFrequency = 10; + * BaseType_t xWasDelayed; + * + * // Initialise the xLastWakeTime variable with the current time. + * xLastWakeTime = xTaskGetTickCount (); + * for( ;; ) + * { + * // Wait for the next cycle. + * xWasDelayed = xTaskDelayUntil( &xLastWakeTime, xFrequency ); + * + * // Perform action here. xWasDelayed value can be used to determine + * // whether a deadline was missed if the code here took too long. + * } + * } + * @endcode + * \defgroup xTaskDelayUntil xTaskDelayUntil + * \ingroup TaskCtrl + */ +BaseType_t xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) PRIVILEGED_FUNCTION; + +/* + * vTaskDelayUntil() is the older version of xTaskDelayUntil() and does not + * return a value. + */ +#define vTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement ) \ + { \ + ( void ) xTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement ); \ + } + + +/** + * task. h + * @code{c} + * BaseType_t xTaskAbortDelay( TaskHandle_t xTask ); + * @endcode + * + * INCLUDE_xTaskAbortDelay must be defined as 1 in FreeRTOSConfig.h for this + * function to be available. + * + * A task will enter the Blocked state when it is waiting for an event. The + * event it is waiting for can be a temporal event (waiting for a time), such + * as when vTaskDelay() is called, or an event on an object, such as when + * xQueueReceive() or ulTaskNotifyTake() is called. If the handle of a task + * that is in the Blocked state is used in a call to xTaskAbortDelay() then the + * task will leave the Blocked state, and return from whichever function call + * placed the task into the Blocked state. + * + * There is no 'FromISR' version of this function as an interrupt would need to + * know which object a task was blocked on in order to know which actions to + * take. For example, if the task was blocked on a queue the interrupt handler + * would then need to know if the queue was locked. + * + * @param xTask The handle of the task to remove from the Blocked state. + * + * @return If the task referenced by xTask was not in the Blocked state then + * pdFAIL is returned. Otherwise pdPASS is returned. + * + * \defgroup xTaskAbortDelay xTaskAbortDelay + * \ingroup TaskCtrl + */ +BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask ); + * @endcode + * + * INCLUDE_uxTaskPriorityGet must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Obtain the priority of any task. + * + * @param xTask Handle of the task to be queried. Passing a NULL + * handle results in the priority of the calling task being returned. + * + * @return The priority of xTask. + * + * Example usage: + * @code{c} + * void vAFunction( void ) + * { + * TaskHandle_t xHandle; + * + * // Create a task, storing the handle. + * xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle ); + * + * // ... + * + * // Use the handle to obtain the priority of the created task. + * // It was created with tskIDLE_PRIORITY, but may have changed + * // it itself. + * if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY ) + * { + * // The task has changed it's priority. + * } + * + * // ... + * + * // Is our priority higher than the created task? + * if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) ) + * { + * // Our priority (obtained using NULL handle) is higher. + * } + * } + * @endcode + * \defgroup uxTaskPriorityGet uxTaskPriorityGet + * \ingroup TaskCtrl + */ +UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask ); + * @endcode + * + * A version of uxTaskPriorityGet() that can be used from an ISR. + */ +UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * eTaskState eTaskGetState( TaskHandle_t xTask ); + * @endcode + * + * INCLUDE_eTaskGetState must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Obtain the state of any task. States are encoded by the eTaskState + * enumerated type. + * + * @param xTask Handle of the task to be queried. + * + * @return The state of xTask at the time the function was called. Note the + * state of the task might change between the function being called, and the + * functions return value being tested by the calling task. + */ +eTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +// Added by Inertial Sense +/** + * vTaskResetRunTimeCounter( TaskHandle_t xTask ) + * + * configUSE_TRACE_FACILITY must be defined as 1 for this function to be + * available. See the configuration section for more information. + * + * @param xTask Handle of the task which will have its runtime counter reset to 0 + * + * This function resets the ulRunTimeCounter of the task in question to 0. + * Call this once after wrap is detected, but before using ulRunTimeCounter in + * calculations. + */ +void vTaskResetRunTimeCounter( TaskHandle_t xTask ); + +/** + * task. h + * @code{c} + * void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ); + * @endcode + * + * configUSE_TRACE_FACILITY must be defined as 1 for this function to be + * available. See the configuration section for more information. + * + * Populates a TaskStatus_t structure with information about a task. + * + * @param xTask Handle of the task being queried. If xTask is NULL then + * information will be returned about the calling task. + * + * @param pxTaskStatus A pointer to the TaskStatus_t structure that will be + * filled with information about the task referenced by the handle passed using + * the xTask parameter. + * + * @xGetFreeStackSpace The TaskStatus_t structure contains a member to report + * the stack high water mark of the task being queried. Calculating the stack + * high water mark takes a relatively long time, and can make the system + * temporarily unresponsive - so the xGetFreeStackSpace parameter is provided to + * allow the high water mark checking to be skipped. The high watermark value + * will only be written to the TaskStatus_t structure if xGetFreeStackSpace is + * not set to pdFALSE; + * + * @param eState The TaskStatus_t structure contains a member to report the + * state of the task being queried. Obtaining the task state is not as fast as + * a simple assignment - so the eState parameter is provided to allow the state + * information to be omitted from the TaskStatus_t structure. To obtain state + * information then set eState to eInvalid - otherwise the value passed in + * eState will be reported as the task state in the TaskStatus_t structure. + * + * Example usage: + * @code{c} + * void vAFunction( void ) + * { + * TaskHandle_t xHandle; + * TaskStatus_t xTaskDetails; + * + * // Obtain the handle of a task from its name. + * xHandle = xTaskGetHandle( "Task_Name" ); + * + * // Check the handle is not NULL. + * configASSERT( xHandle ); + * + * // Use the handle to obtain further information about the task. + * vTaskGetInfo( xHandle, + * &xTaskDetails, + * pdTRUE, // Include the high water mark in xTaskDetails. + * eInvalid ); // Include the task state in xTaskDetails. + * } + * @endcode + * \defgroup vTaskGetInfo vTaskGetInfo + * \ingroup TaskCtrl + */ +void vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ); + * @endcode + * + * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Set the priority of any task. + * + * A context switch will occur before the function returns if the priority + * being set is higher than the currently executing task. + * + * @param xTask Handle to the task for which the priority is being set. + * Passing a NULL handle results in the priority of the calling task being set. + * + * @param uxNewPriority The priority to which the task will be set. + * + * Example usage: + * @code{c} + * void vAFunction( void ) + * { + * TaskHandle_t xHandle; + * + * // Create a task, storing the handle. + * xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle ); + * + * // ... + * + * // Use the handle to raise the priority of the created task. + * vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 ); + * + * // ... + * + * // Use a NULL handle to raise our priority to the same value. + * vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 ); + * } + * @endcode + * \defgroup vTaskPrioritySet vTaskPrioritySet + * \ingroup TaskCtrl + */ +void vTaskPrioritySet( TaskHandle_t xTask, + UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * void vTaskSuspend( TaskHandle_t xTaskToSuspend ); + * @endcode + * + * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Suspend any task. When suspended a task will never get any microcontroller + * processing time, no matter what its priority. + * + * Calls to vTaskSuspend are not accumulative - + * i.e. calling vTaskSuspend () twice on the same task still only requires one + * call to vTaskResume () to ready the suspended task. + * + * @param xTaskToSuspend Handle to the task being suspended. Passing a NULL + * handle will cause the calling task to be suspended. + * + * Example usage: + * @code{c} + * void vAFunction( void ) + * { + * TaskHandle_t xHandle; + * + * // Create a task, storing the handle. + * xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle ); + * + * // ... + * + * // Use the handle to suspend the created task. + * vTaskSuspend( xHandle ); + * + * // ... + * + * // The created task will not run during this period, unless + * // another task calls vTaskResume( xHandle ). + * + * //... + * + * + * // Suspend ourselves. + * vTaskSuspend( NULL ); + * + * // We cannot get here unless another task calls vTaskResume + * // with our handle as the parameter. + * } + * @endcode + * \defgroup vTaskSuspend vTaskSuspend + * \ingroup TaskCtrl + */ +void vTaskSuspend( TaskHandle_t xTaskToSuspend ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * void vTaskResume( TaskHandle_t xTaskToResume ); + * @endcode + * + * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Resumes a suspended task. + * + * A task that has been suspended by one or more calls to vTaskSuspend () + * will be made available for running again by a single call to + * vTaskResume (). + * + * @param xTaskToResume Handle to the task being readied. + * + * Example usage: + * @code{c} + * void vAFunction( void ) + * { + * TaskHandle_t xHandle; + * + * // Create a task, storing the handle. + * xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle ); + * + * // ... + * + * // Use the handle to suspend the created task. + * vTaskSuspend( xHandle ); + * + * // ... + * + * // The created task will not run during this period, unless + * // another task calls vTaskResume( xHandle ). + * + * //... + * + * + * // Resume the suspended task ourselves. + * vTaskResume( xHandle ); + * + * // The created task will once again get microcontroller processing + * // time in accordance with its priority within the system. + * } + * @endcode + * \defgroup vTaskResume vTaskResume + * \ingroup TaskCtrl + */ +void vTaskResume( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * void xTaskResumeFromISR( TaskHandle_t xTaskToResume ); + * @endcode + * + * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be + * available. See the configuration section for more information. + * + * An implementation of vTaskResume() that can be called from within an ISR. + * + * A task that has been suspended by one or more calls to vTaskSuspend () + * will be made available for running again by a single call to + * xTaskResumeFromISR (). + * + * xTaskResumeFromISR() should not be used to synchronise a task with an + * interrupt if there is a chance that the interrupt could arrive prior to the + * task being suspended - as this can lead to interrupts being missed. Use of a + * semaphore as a synchronisation mechanism would avoid this eventuality. + * + * @param xTaskToResume Handle to the task being readied. + * + * @return pdTRUE if resuming the task should result in a context switch, + * otherwise pdFALSE. This is used by the ISR to determine if a context switch + * may be required following the ISR. + * + * \defgroup vTaskResumeFromISR vTaskResumeFromISR + * \ingroup TaskCtrl + */ +BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION; + +/*----------------------------------------------------------- +* SCHEDULER CONTROL +*----------------------------------------------------------*/ + +/** + * task. h + * @code{c} + * void vTaskStartScheduler( void ); + * @endcode + * + * Starts the real time kernel tick processing. After calling the kernel + * has control over which tasks are executed and when. + * + * See the demo application file main.c for an example of creating + * tasks and starting the kernel. + * + * Example usage: + * @code{c} + * void vAFunction( void ) + * { + * // Create at least one task before starting the kernel. + * xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + * + * // Start the real time kernel with preemption. + * vTaskStartScheduler (); + * + * // Will not get here unless a task calls vTaskEndScheduler () + * } + * @endcode + * + * \defgroup vTaskStartScheduler vTaskStartScheduler + * \ingroup SchedulerControl + */ +void vTaskStartScheduler( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * void vTaskEndScheduler( void ); + * @endcode + * + * NOTE: At the time of writing only the x86 real mode port, which runs on a PC + * in place of DOS, implements this function. + * + * Stops the real time kernel tick. All created tasks will be automatically + * deleted and multitasking (either preemptive or cooperative) will + * stop. Execution then resumes from the point where vTaskStartScheduler () + * was called, as if vTaskStartScheduler () had just returned. + * + * See the demo application file main. c in the demo/PC directory for an + * example that uses vTaskEndScheduler (). + * + * vTaskEndScheduler () requires an exit function to be defined within the + * portable layer (see vPortEndScheduler () in port. c for the PC port). This + * performs hardware specific operations such as stopping the kernel tick. + * + * vTaskEndScheduler () will cause all of the resources allocated by the + * kernel to be freed - but will not free resources allocated by application + * tasks. + * + * Example usage: + * @code{c} + * void vTaskCode( void * pvParameters ) + * { + * for( ;; ) + * { + * // Task code goes here. + * + * // At some point we want to end the real time kernel processing + * // so call ... + * vTaskEndScheduler (); + * } + * } + * + * void vAFunction( void ) + * { + * // Create at least one task before starting the kernel. + * xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + * + * // Start the real time kernel with preemption. + * vTaskStartScheduler (); + * + * // Will only get here when the vTaskCode () task has called + * // vTaskEndScheduler (). When we get here we are back to single task + * // execution. + * } + * @endcode + * + * \defgroup vTaskEndScheduler vTaskEndScheduler + * \ingroup SchedulerControl + */ +void vTaskEndScheduler( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * void vTaskSuspendAll( void ); + * @endcode + * + * Suspends the scheduler without disabling interrupts. Context switches will + * not occur while the scheduler is suspended. + * + * After calling vTaskSuspendAll () the calling task will continue to execute + * without risk of being swapped out until a call to xTaskResumeAll () has been + * made. + * + * API functions that have the potential to cause a context switch (for example, + * xTaskDelayUntil(), xQueueSend(), etc.) must not be called while the scheduler + * is suspended. + * + * Example usage: + * @code{c} + * void vTask1( void * pvParameters ) + * { + * for( ;; ) + * { + * // Task code goes here. + * + * // ... + * + * // At some point the task wants to perform a long operation during + * // which it does not want to get swapped out. It cannot use + * // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the + * // operation may cause interrupts to be missed - including the + * // ticks. + * + * // Prevent the real time kernel swapping out the task. + * vTaskSuspendAll (); + * + * // Perform the operation here. There is no need to use critical + * // sections as we have all the microcontroller processing time. + * // During this time interrupts will still operate and the kernel + * // tick count will be maintained. + * + * // ... + * + * // The operation is complete. Restart the kernel. + * xTaskResumeAll (); + * } + * } + * @endcode + * \defgroup vTaskSuspendAll vTaskSuspendAll + * \ingroup SchedulerControl + */ +void vTaskSuspendAll( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * BaseType_t xTaskResumeAll( void ); + * @endcode + * + * Resumes scheduler activity after it was suspended by a call to + * vTaskSuspendAll(). + * + * xTaskResumeAll() only resumes the scheduler. It does not unsuspend tasks + * that were previously suspended by a call to vTaskSuspend(). + * + * @return If resuming the scheduler caused a context switch then pdTRUE is + * returned, otherwise pdFALSE is returned. + * + * Example usage: + * @code{c} + * void vTask1( void * pvParameters ) + * { + * for( ;; ) + * { + * // Task code goes here. + * + * // ... + * + * // At some point the task wants to perform a long operation during + * // which it does not want to get swapped out. It cannot use + * // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the + * // operation may cause interrupts to be missed - including the + * // ticks. + * + * // Prevent the real time kernel swapping out the task. + * vTaskSuspendAll (); + * + * // Perform the operation here. There is no need to use critical + * // sections as we have all the microcontroller processing time. + * // During this time interrupts will still operate and the real + * // time kernel tick count will be maintained. + * + * // ... + * + * // The operation is complete. Restart the kernel. We want to force + * // a context switch - but there is no point if resuming the scheduler + * // caused a context switch already. + * if( !xTaskResumeAll () ) + * { + * taskYIELD (); + * } + * } + * } + * @endcode + * \defgroup xTaskResumeAll xTaskResumeAll + * \ingroup SchedulerControl + */ +BaseType_t xTaskResumeAll( void ) PRIVILEGED_FUNCTION; + +/*----------------------------------------------------------- +* TASK UTILITIES +*----------------------------------------------------------*/ + +/** + * task. h + * @code{c} + * TickType_t xTaskGetTickCount( void ); + * @endcode + * + * @return The count of ticks since vTaskStartScheduler was called. + * + * \defgroup xTaskGetTickCount xTaskGetTickCount + * \ingroup TaskUtils + */ +TickType_t xTaskGetTickCount( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * TickType_t xTaskGetTickCountFromISR( void ); + * @endcode + * + * @return The count of ticks since vTaskStartScheduler was called. + * + * This is a version of xTaskGetTickCount() that is safe to be called from an + * ISR - provided that TickType_t is the natural word size of the + * microcontroller being used or interrupt nesting is either not supported or + * not being used. + * + * \defgroup xTaskGetTickCountFromISR xTaskGetTickCountFromISR + * \ingroup TaskUtils + */ +TickType_t xTaskGetTickCountFromISR( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * uint16_t uxTaskGetNumberOfTasks( void ); + * @endcode + * + * @return The number of tasks that the real time kernel is currently managing. + * This includes all ready, blocked and suspended tasks. A task that + * has been deleted but not yet freed by the idle task will also be + * included in the count. + * + * \defgroup uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks + * \ingroup TaskUtils + */ +UBaseType_t uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * char *pcTaskGetName( TaskHandle_t xTaskToQuery ); + * @endcode + * + * @return The text (human readable) name of the task referenced by the handle + * xTaskToQuery. A task can query its own name by either passing in its own + * handle, or by setting xTaskToQuery to NULL. + * + * \defgroup pcTaskGetName pcTaskGetName + * \ingroup TaskUtils + */ +char * pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + +/** + * task. h + * @code{c} + * TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ); + * @endcode + * + * NOTE: This function takes a relatively long time to complete and should be + * used sparingly. + * + * @return The handle of the task that has the human readable name pcNameToQuery. + * NULL is returned if no matching name is found. INCLUDE_xTaskGetHandle + * must be set to 1 in FreeRTOSConfig.h for pcTaskGetHandle() to be available. + * + * \defgroup pcTaskGetHandle pcTaskGetHandle + * \ingroup TaskUtils + */ +TaskHandle_t xTaskGetHandle( const char * pcNameToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + +/** + * task.h + * @code{c} + * UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ); + * @endcode + * + * INCLUDE_uxTaskGetStackHighWaterMark must be set to 1 in FreeRTOSConfig.h for + * this function to be available. + * + * Returns the high water mark of the stack associated with xTask. That is, + * the minimum free stack space there has been (in words, so on a 32 bit machine + * a value of 1 means 4 bytes) since the task started. The smaller the returned + * number the closer the task has come to overflowing its stack. + * + * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the + * same except for their return type. Using configSTACK_DEPTH_TYPE allows the + * user to determine the return type. It gets around the problem of the value + * overflowing on 8-bit types without breaking backward compatibility for + * applications that expect an 8-bit return type. + * + * @param xTask Handle of the task associated with the stack to be checked. + * Set xTask to NULL to check the stack of the calling task. + * + * @return The smallest amount of free stack space there has been (in words, so + * actual spaces on the stack rather than bytes) since the task referenced by + * xTask was created. + */ +UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/** + * task.h + * @code{c} + * configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ); + * @endcode + * + * INCLUDE_uxTaskGetStackHighWaterMark2 must be set to 1 in FreeRTOSConfig.h for + * this function to be available. + * + * Returns the high water mark of the stack associated with xTask. That is, + * the minimum free stack space there has been (in words, so on a 32 bit machine + * a value of 1 means 4 bytes) since the task started. The smaller the returned + * number the closer the task has come to overflowing its stack. + * + * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the + * same except for their return type. Using configSTACK_DEPTH_TYPE allows the + * user to determine the return type. It gets around the problem of the value + * overflowing on 8-bit types without breaking backward compatibility for + * applications that expect an 8-bit return type. + * + * @param xTask Handle of the task associated with the stack to be checked. + * Set xTask to NULL to check the stack of the calling task. + * + * @return The smallest amount of free stack space there has been (in words, so + * actual spaces on the stack rather than bytes) since the task referenced by + * xTask was created. + */ +configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/* When using trace macros it is sometimes necessary to include task.h before + * FreeRTOS.h. When this is done TaskHookFunction_t will not yet have been defined, + * so the following two prototypes will cause a compilation error. This can be + * fixed by simply guarding against the inclusion of these two prototypes unless + * they are explicitly required by the configUSE_APPLICATION_TASK_TAG configuration + * constant. */ +#ifdef configUSE_APPLICATION_TASK_TAG + #if configUSE_APPLICATION_TASK_TAG == 1 + +/** + * task.h + * @code{c} + * void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ); + * @endcode + * + * Sets pxHookFunction to be the task hook function used by the task xTask. + * Passing xTask as NULL has the effect of setting the calling tasks hook + * function. + */ + void vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) PRIVILEGED_FUNCTION; + +/** + * task.h + * @code{c} + * void xTaskGetApplicationTaskTag( TaskHandle_t xTask ); + * @endcode + * + * Returns the pxHookFunction value assigned to the task xTask. Do not + * call from an interrupt service routine - call + * xTaskGetApplicationTaskTagFromISR() instead. + */ + TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/** + * task.h + * @code{c} + * void xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ); + * @endcode + * + * Returns the pxHookFunction value assigned to the task xTask. Can + * be called from an interrupt service routine. + */ + TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + #endif /* configUSE_APPLICATION_TASK_TAG ==1 */ +#endif /* ifdef configUSE_APPLICATION_TASK_TAG */ + +#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 ) + +/* Each task contains an array of pointers that is dimensioned by the + * configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h. The + * kernel does not use the pointers itself, so the application writer can use + * the pointers for any purpose they wish. The following two functions are + * used to set and query a pointer respectively. */ + void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) PRIVILEGED_FUNCTION; + void * pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) PRIVILEGED_FUNCTION; + +#endif + +#if ( configCHECK_FOR_STACK_OVERFLOW > 0 ) + +/** + * task.h + * @code{c} + * void vApplicationStackOverflowHook( TaskHandle_t xTask char *pcTaskName); + * @endcode + * + * The application stack overflow hook is called when a stack overflow is detected for a task. + * + * Details on stack overflow detection can be found here: https://www.FreeRTOS.org/Stacks-and-stack-overflow-checking.html + * + * @param xTask the task that just exceeded its stack boundaries. + * @param pcTaskName A character string containing the name of the offending task. + */ + void vApplicationStackOverflowHook( TaskHandle_t xTask, + char * pcTaskName ); + +#endif + +#if ( configUSE_TICK_HOOK > 0 ) + +/** + * task.h + * @code{c} + * void vApplicationTickHook( void ); + * @endcode + * + * This hook function is called in the system tick handler after any OS work is completed. + */ + void vApplicationTickHook( void ); /*lint !e526 Symbol not defined as it is an application callback. */ + +#endif + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + +/** + * task.h + * @code{c} + * void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, StackType_t ** ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ) + * @endcode + * + * This function is used to provide a statically allocated block of memory to FreeRTOS to hold the Idle Task TCB. This function is required when + * configSUPPORT_STATIC_ALLOCATION is set. For more information see this URI: https://www.FreeRTOS.org/a00110.html#configSUPPORT_STATIC_ALLOCATION + * + * @param ppxIdleTaskTCBBuffer A handle to a statically allocated TCB buffer + * @param ppxIdleTaskStackBuffer A handle to a statically allocated Stack buffer for the idle task + * @param pulIdleTaskStackSize A pointer to the number of elements that will fit in the allocated stack buffer + */ + void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, + StackType_t ** ppxIdleTaskStackBuffer, + uint32_t * pulIdleTaskStackSize ); /*lint !e526 Symbol not defined as it is an application callback. */ +#endif + +/** + * task.h + * @code{c} + * BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ); + * @endcode + * + * Calls the hook function associated with xTask. Passing xTask as NULL has + * the effect of calling the Running tasks (the calling task) hook function. + * + * pvParameter is passed to the hook function for the task to interpret as it + * wants. The return value is the value returned by the task hook function + * registered by the user. + */ +BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, + void * pvParameter ) PRIVILEGED_FUNCTION; + +/** + * xTaskGetIdleTaskHandle() is only available if + * INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h. + * + * Simply returns the handle of the idle task. It is not valid to call + * xTaskGetIdleTaskHandle() before the scheduler has been started. + */ +TaskHandle_t xTaskGetIdleTaskHandle( void ) PRIVILEGED_FUNCTION; + +/** + * configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for + * uxTaskGetSystemState() to be available. + * + * uxTaskGetSystemState() populates an TaskStatus_t structure for each task in + * the system. TaskStatus_t structures contain, among other things, members + * for the task handle, task name, task priority, task state, and total amount + * of run time consumed by the task. See the TaskStatus_t structure + * definition in this file for the full member list. + * + * NOTE: This function is intended for debugging use only as its use results in + * the scheduler remaining suspended for an extended period. + * + * @param pxTaskStatusArray A pointer to an array of TaskStatus_t structures. + * The array must contain at least one TaskStatus_t structure for each task + * that is under the control of the RTOS. The number of tasks under the control + * of the RTOS can be determined using the uxTaskGetNumberOfTasks() API function. + * + * @param uxArraySize The size of the array pointed to by the pxTaskStatusArray + * parameter. The size is specified as the number of indexes in the array, or + * the number of TaskStatus_t structures contained in the array, not by the + * number of bytes in the array. + * + * @param pulTotalRunTime If configGENERATE_RUN_TIME_STATS is set to 1 in + * FreeRTOSConfig.h then *pulTotalRunTime is set by uxTaskGetSystemState() to the + * total run time (as defined by the run time stats clock, see + * https://www.FreeRTOS.org/rtos-run-time-stats.html) since the target booted. + * pulTotalRunTime can be set to NULL to omit the total run time information. + * + * @return The number of TaskStatus_t structures that were populated by + * uxTaskGetSystemState(). This should equal the number returned by the + * uxTaskGetNumberOfTasks() API function, but will be zero if the value passed + * in the uxArraySize parameter was too small. + * + * Example usage: + * @code{c} + * // This example demonstrates how a human readable table of run time stats + * // information is generated from raw data provided by uxTaskGetSystemState(). + * // The human readable table is written to pcWriteBuffer + * void vTaskGetRunTimeStats( char *pcWriteBuffer ) + * { + * TaskStatus_t *pxTaskStatusArray; + * volatile UBaseType_t uxArraySize, x; + * configRUN_TIME_COUNTER_TYPE ulTotalRunTime, ulStatsAsPercentage; + * + * // Make sure the write buffer does not contain a string. + * pcWriteBuffer = 0x00; + * + * // Take a snapshot of the number of tasks in case it changes while this + * // function is executing. + * uxArraySize = uxTaskGetNumberOfTasks(); + * + * // Allocate a TaskStatus_t structure for each task. An array could be + * // allocated statically at compile time. + * pxTaskStatusArray = pvPortMalloc( uxArraySize * sizeof( TaskStatus_t ) ); + * + * if( pxTaskStatusArray != NULL ) + * { + * // Generate raw status information about each task. + * uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalRunTime ); + * + * // For percentage calculations. + * ulTotalRunTime /= 100UL; + * + * // Avoid divide by zero errors. + * if( ulTotalRunTime > 0 ) + * { + * // For each populated position in the pxTaskStatusArray array, + * // format the raw data as human readable ASCII data + * for( x = 0; x < uxArraySize; x++ ) + * { + * // What percentage of the total run time has the task used? + * // This will always be rounded down to the nearest integer. + * // ulTotalRunTimeDiv100 has already been divided by 100. + * ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalRunTime; + * + * if( ulStatsAsPercentage > 0UL ) + * { + * sprintf( pcWriteBuffer, "%s\t\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage ); + * } + * else + * { + * // If the percentage is zero here then the task has + * // consumed less than 1% of the total run time. + * sprintf( pcWriteBuffer, "%s\t\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter ); + * } + * + * pcWriteBuffer += strlen( ( char * ) pcWriteBuffer ); + * } + * } + * + * // The array is no longer needed, free the memory it consumes. + * vPortFree( pxTaskStatusArray ); + * } + * } + * @endcode + */ +UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * void vTaskList( char *pcWriteBuffer ); + * @endcode + * + * configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must + * both be defined as 1 for this function to be available. See the + * configuration section of the FreeRTOS.org website for more information. + * + * NOTE 1: This function will disable interrupts for its duration. It is + * not intended for normal application runtime use but as a debug aid. + * + * Lists all the current tasks, along with their current state and stack + * usage high water mark. + * + * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or + * suspended ('S'). + * + * PLEASE NOTE: + * + * This function is provided for convenience only, and is used by many of the + * demo applications. Do not consider it to be part of the scheduler. + * + * vTaskList() calls uxTaskGetSystemState(), then formats part of the + * uxTaskGetSystemState() output into a human readable table that displays task: + * names, states, priority, stack usage and task number. + * Stack usage specified as the number of unused StackType_t words stack can hold + * on top of stack - not the number of bytes. + * + * vTaskList() has a dependency on the sprintf() C library function that might + * bloat the code size, use a lot of stack, and provide different results on + * different platforms. An alternative, tiny, third party, and limited + * functionality implementation of sprintf() is provided in many of the + * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note + * printf-stdarg.c does not provide a full snprintf() implementation!). + * + * It is recommended that production systems call uxTaskGetSystemState() + * directly to get access to raw stats data, rather than indirectly through a + * call to vTaskList(). + * + * @param pcWriteBuffer A buffer into which the above mentioned details + * will be written, in ASCII form. This buffer is assumed to be large + * enough to contain the generated report. Approximately 40 bytes per + * task should be sufficient. + * + * \defgroup vTaskList vTaskList + * \ingroup TaskUtils + */ +void vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + +/** + * task. h + * @code{c} + * void vTaskGetRunTimeStats( char *pcWriteBuffer ); + * @endcode + * + * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS + * must both be defined as 1 for this function to be available. The application + * must also then provide definitions for + * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE() + * to configure a peripheral timer/counter and return the timers current count + * value respectively. The counter should be at least 10 times the frequency of + * the tick count. + * + * NOTE 1: This function will disable interrupts for its duration. It is + * not intended for normal application runtime use but as a debug aid. + * + * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total + * accumulated execution time being stored for each task. The resolution + * of the accumulated time value depends on the frequency of the timer + * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro. + * Calling vTaskGetRunTimeStats() writes the total execution time of each + * task into a buffer, both as an absolute count value and as a percentage + * of the total system execution time. + * + * NOTE 2: + * + * This function is provided for convenience only, and is used by many of the + * demo applications. Do not consider it to be part of the scheduler. + * + * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part of the + * uxTaskGetSystemState() output into a human readable table that displays the + * amount of time each task has spent in the Running state in both absolute and + * percentage terms. + * + * vTaskGetRunTimeStats() has a dependency on the sprintf() C library function + * that might bloat the code size, use a lot of stack, and provide different + * results on different platforms. An alternative, tiny, third party, and + * limited functionality implementation of sprintf() is provided in many of the + * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note + * printf-stdarg.c does not provide a full snprintf() implementation!). + * + * It is recommended that production systems call uxTaskGetSystemState() directly + * to get access to raw stats data, rather than indirectly through a call to + * vTaskGetRunTimeStats(). + * + * @param pcWriteBuffer A buffer into which the execution times will be + * written, in ASCII form. This buffer is assumed to be large enough to + * contain the generated report. Approximately 40 bytes per task should + * be sufficient. + * + * \defgroup vTaskGetRunTimeStats vTaskGetRunTimeStats + * \ingroup TaskUtils + */ +void vTaskGetRunTimeStats( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + +/** + * task. h + * @code{c} + * configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimeCounter( void ); + * configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimePercent( void ); + * @endcode + * + * configGENERATE_RUN_TIME_STATS, configUSE_STATS_FORMATTING_FUNCTIONS and + * INCLUDE_xTaskGetIdleTaskHandle must all be defined as 1 for these functions + * to be available. The application must also then provide definitions for + * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE() + * to configure a peripheral timer/counter and return the timers current count + * value respectively. The counter should be at least 10 times the frequency of + * the tick count. + * + * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total + * accumulated execution time being stored for each task. The resolution + * of the accumulated time value depends on the frequency of the timer + * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro. + * While uxTaskGetSystemState() and vTaskGetRunTimeStats() writes the total + * execution time of each task into a buffer, ulTaskGetIdleRunTimeCounter() + * returns the total execution time of just the idle task and + * ulTaskGetIdleRunTimePercent() returns the percentage of the CPU time used by + * just the idle task. + * + * Note the amount of idle time is only a good measure of the slack time in a + * system if there are no other tasks executing at the idle priority, tickless + * idle is not used, and configIDLE_SHOULD_YIELD is set to 0. + * + * @return The total run time of the idle task or the percentage of the total + * run time consumed by the idle task. This is the amount of time the + * idle task has actually been executing. The unit of time is dependent on the + * frequency configured using the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and + * portGET_RUN_TIME_COUNTER_VALUE() macros. + * + * \defgroup ulTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounter + * \ingroup TaskUtils + */ +configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimeCounter( void ) PRIVILEGED_FUNCTION; +configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimePercent( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * BaseType_t xTaskNotifyIndexed( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction ); + * BaseType_t xTaskNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction ); + * @endcode + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these + * functions to be available. + * + * Sends a direct to task notification to a task, with an optional value and + * action. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment one of the task's notification values. In + * that way task notifications can be used to send data to a task, or be used as + * light weight and fast binary or counting semaphores. + * + * A task can use xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() to + * [optionally] block to wait for a notification to be pending. The task does + * not consume any CPU time while it is in the Blocked state. + * + * A notification sent to a task will remain pending until it is cleared by the + * task calling xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() (or their + * un-indexed equivalents). If the task was already in the Blocked state to + * wait for a notification when the notification arrives then the task will + * automatically be removed from the Blocked state (unblocked) and the + * notification cleared. + * + * **NOTE** Each notification within the array operates independently - a task + * can only block on one notification within the array at a time and will not be + * unblocked by a notification sent to any other array index. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. xTaskNotify() is the original API function, and remains backward + * compatible by always operating on the notification value at index 0 in the + * array. Calling xTaskNotify() is equivalent to calling xTaskNotifyIndexed() + * with the uxIndexToNotify parameter set to 0. + * + * @param xTaskToNotify The handle of the task being notified. The handle to a + * task can be returned from the xTaskCreate() API function used to create the + * task, and the handle of the currently running task can be obtained by calling + * xTaskGetCurrentTaskHandle(). + * + * @param uxIndexToNotify The index within the target task's array of + * notification values to which the notification is to be sent. uxIndexToNotify + * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES. xTaskNotify() does + * not have this parameter and always sends notifications to index 0. + * + * @param ulValue Data that can be sent with the notification. How the data is + * used depends on the value of the eAction parameter. + * + * @param eAction Specifies how the notification updates the task's notification + * value, if at all. Valid values for eAction are as follows: + * + * eSetBits - + * The target notification value is bitwise ORed with ulValue. + * xTaskNotifyIndexed() always returns pdPASS in this case. + * + * eIncrement - + * The target notification value is incremented. ulValue is not used and + * xTaskNotifyIndexed() always returns pdPASS in this case. + * + * eSetValueWithOverwrite - + * The target notification value is set to the value of ulValue, even if the + * task being notified had not yet processed the previous notification at the + * same array index (the task already had a notification pending at that index). + * xTaskNotifyIndexed() always returns pdPASS in this case. + * + * eSetValueWithoutOverwrite - + * If the task being notified did not already have a notification pending at the + * same array index then the target notification value is set to ulValue and + * xTaskNotifyIndexed() will return pdPASS. If the task being notified already + * had a notification pending at the same array index then no action is + * performed and pdFAIL is returned. + * + * eNoAction - + * The task receives a notification at the specified array index without the + * notification value at that index being updated. ulValue is not used and + * xTaskNotifyIndexed() always returns pdPASS in this case. + * + * pulPreviousNotificationValue - + * Can be used to pass out the subject task's notification value before any + * bits are modified by the notify function. + * + * @return Dependent on the value of eAction. See the description of the + * eAction parameter. + * + * \defgroup xTaskNotifyIndexed xTaskNotifyIndexed + * \ingroup TaskNotifications + */ +BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + uint32_t ulValue, + eNotifyAction eAction, + uint32_t * pulPreviousNotificationValue ) PRIVILEGED_FUNCTION; +#define xTaskNotify( xTaskToNotify, ulValue, eAction ) \ + xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), NULL ) +#define xTaskNotifyIndexed( xTaskToNotify, uxIndexToNotify, ulValue, eAction ) \ + xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), NULL ) + +/** + * task. h + * @code{c} + * BaseType_t xTaskNotifyAndQueryIndexed( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotifyValue ); + * BaseType_t xTaskNotifyAndQuery( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotifyValue ); + * @endcode + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * xTaskNotifyAndQueryIndexed() performs the same operation as + * xTaskNotifyIndexed() with the addition that it also returns the subject + * task's prior notification value (the notification value at the time the + * function is called rather than when the function returns) in the additional + * pulPreviousNotifyValue parameter. + * + * xTaskNotifyAndQuery() performs the same operation as xTaskNotify() with the + * addition that it also returns the subject task's prior notification value + * (the notification value as it was at the time the function is called, rather + * than when the function returns) in the additional pulPreviousNotifyValue + * parameter. + * + * \defgroup xTaskNotifyAndQueryIndexed xTaskNotifyAndQueryIndexed + * \ingroup TaskNotifications + */ +#define xTaskNotifyAndQuery( xTaskToNotify, ulValue, eAction, pulPreviousNotifyValue ) \ + xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) ) +#define xTaskNotifyAndQueryIndexed( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotifyValue ) \ + xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) ) + +/** + * task. h + * @code{c} + * BaseType_t xTaskNotifyIndexedFromISR( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken ); + * BaseType_t xTaskNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken ); + * @endcode + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these + * functions to be available. + * + * A version of xTaskNotifyIndexed() that can be used from an interrupt service + * routine (ISR). + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment one of the task's notification values. In + * that way task notifications can be used to send data to a task, or be used as + * light weight and fast binary or counting semaphores. + * + * A task can use xTaskNotifyWaitIndexed() to [optionally] block to wait for a + * notification to be pending, or ulTaskNotifyTakeIndexed() to [optionally] block + * to wait for a notification value to have a non-zero value. The task does + * not consume any CPU time while it is in the Blocked state. + * + * A notification sent to a task will remain pending until it is cleared by the + * task calling xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() (or their + * un-indexed equivalents). If the task was already in the Blocked state to + * wait for a notification when the notification arrives then the task will + * automatically be removed from the Blocked state (unblocked) and the + * notification cleared. + * + * **NOTE** Each notification within the array operates independently - a task + * can only block on one notification within the array at a time and will not be + * unblocked by a notification sent to any other array index. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. xTaskNotifyFromISR() is the original API function, and remains + * backward compatible by always operating on the notification value at index 0 + * within the array. Calling xTaskNotifyFromISR() is equivalent to calling + * xTaskNotifyIndexedFromISR() with the uxIndexToNotify parameter set to 0. + * + * @param uxIndexToNotify The index within the target task's array of + * notification values to which the notification is to be sent. uxIndexToNotify + * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES. xTaskNotifyFromISR() + * does not have this parameter and always sends notifications to index 0. + * + * @param xTaskToNotify The handle of the task being notified. The handle to a + * task can be returned from the xTaskCreate() API function used to create the + * task, and the handle of the currently running task can be obtained by calling + * xTaskGetCurrentTaskHandle(). + * + * @param ulValue Data that can be sent with the notification. How the data is + * used depends on the value of the eAction parameter. + * + * @param eAction Specifies how the notification updates the task's notification + * value, if at all. Valid values for eAction are as follows: + * + * eSetBits - + * The task's notification value is bitwise ORed with ulValue. xTaskNotify() + * always returns pdPASS in this case. + * + * eIncrement - + * The task's notification value is incremented. ulValue is not used and + * xTaskNotify() always returns pdPASS in this case. + * + * eSetValueWithOverwrite - + * The task's notification value is set to the value of ulValue, even if the + * task being notified had not yet processed the previous notification (the + * task already had a notification pending). xTaskNotify() always returns + * pdPASS in this case. + * + * eSetValueWithoutOverwrite - + * If the task being notified did not already have a notification pending then + * the task's notification value is set to ulValue and xTaskNotify() will + * return pdPASS. If the task being notified already had a notification + * pending then no action is performed and pdFAIL is returned. + * + * eNoAction - + * The task receives a notification without its notification value being + * updated. ulValue is not used and xTaskNotify() always returns pdPASS in + * this case. + * + * @param pxHigherPriorityTaskWoken xTaskNotifyFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the + * task to which the notification was sent to leave the Blocked state, and the + * unblocked task has a priority higher than the currently running task. If + * xTaskNotifyFromISR() sets this value to pdTRUE then a context switch should + * be requested before the interrupt is exited. How a context switch is + * requested from an ISR is dependent on the port - see the documentation page + * for the port in use. + * + * @return Dependent on the value of eAction. See the description of the + * eAction parameter. + * + * \defgroup xTaskNotifyIndexedFromISR xTaskNotifyIndexedFromISR + * \ingroup TaskNotifications + */ +BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + uint32_t ulValue, + eNotifyAction eAction, + uint32_t * pulPreviousNotificationValue, + BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; +#define xTaskNotifyFromISR( xTaskToNotify, ulValue, eAction, pxHigherPriorityTaskWoken ) \ + xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) ) +#define xTaskNotifyIndexedFromISR( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pxHigherPriorityTaskWoken ) \ + xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) ) + +/** + * task. h + * @code{c} + * BaseType_t xTaskNotifyAndQueryIndexedFromISR( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken ); + * BaseType_t xTaskNotifyAndQueryFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken ); + * @endcode + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * xTaskNotifyAndQueryIndexedFromISR() performs the same operation as + * xTaskNotifyIndexedFromISR() with the addition that it also returns the + * subject task's prior notification value (the notification value at the time + * the function is called rather than at the time the function returns) in the + * additional pulPreviousNotifyValue parameter. + * + * xTaskNotifyAndQueryFromISR() performs the same operation as + * xTaskNotifyFromISR() with the addition that it also returns the subject + * task's prior notification value (the notification value at the time the + * function is called rather than at the time the function returns) in the + * additional pulPreviousNotifyValue parameter. + * + * \defgroup xTaskNotifyAndQueryIndexedFromISR xTaskNotifyAndQueryIndexedFromISR + * \ingroup TaskNotifications + */ +#define xTaskNotifyAndQueryIndexedFromISR( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) \ + xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) ) +#define xTaskNotifyAndQueryFromISR( xTaskToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) \ + xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) ) + +/** + * task. h + * @code{c} + * BaseType_t xTaskNotifyWaitIndexed( UBaseType_t uxIndexToWaitOn, uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ); + * + * BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ); + * @endcode + * + * Waits for a direct to task notification to be pending at a given index within + * an array of direct to task notifications. + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this + * function to be available. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment one of the task's notification values. In + * that way task notifications can be used to send data to a task, or be used as + * light weight and fast binary or counting semaphores. + * + * A notification sent to a task will remain pending until it is cleared by the + * task calling xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() (or their + * un-indexed equivalents). If the task was already in the Blocked state to + * wait for a notification when the notification arrives then the task will + * automatically be removed from the Blocked state (unblocked) and the + * notification cleared. + * + * A task can use xTaskNotifyWaitIndexed() to [optionally] block to wait for a + * notification to be pending, or ulTaskNotifyTakeIndexed() to [optionally] block + * to wait for a notification value to have a non-zero value. The task does + * not consume any CPU time while it is in the Blocked state. + * + * **NOTE** Each notification within the array operates independently - a task + * can only block on one notification within the array at a time and will not be + * unblocked by a notification sent to any other array index. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. xTaskNotifyWait() is the original API function, and remains backward + * compatible by always operating on the notification value at index 0 in the + * array. Calling xTaskNotifyWait() is equivalent to calling + * xTaskNotifyWaitIndexed() with the uxIndexToWaitOn parameter set to 0. + * + * @param uxIndexToWaitOn The index within the calling task's array of + * notification values on which the calling task will wait for a notification to + * be received. uxIndexToWaitOn must be less than + * configTASK_NOTIFICATION_ARRAY_ENTRIES. xTaskNotifyWait() does + * not have this parameter and always waits for notifications on index 0. + * + * @param ulBitsToClearOnEntry Bits that are set in ulBitsToClearOnEntry value + * will be cleared in the calling task's notification value before the task + * checks to see if any notifications are pending, and optionally blocks if no + * notifications are pending. Setting ulBitsToClearOnEntry to ULONG_MAX (if + * limits.h is included) or 0xffffffffUL (if limits.h is not included) will have + * the effect of resetting the task's notification value to 0. Setting + * ulBitsToClearOnEntry to 0 will leave the task's notification value unchanged. + * + * @param ulBitsToClearOnExit If a notification is pending or received before + * the calling task exits the xTaskNotifyWait() function then the task's + * notification value (see the xTaskNotify() API function) is passed out using + * the pulNotificationValue parameter. Then any bits that are set in + * ulBitsToClearOnExit will be cleared in the task's notification value (note + * *pulNotificationValue is set before any bits are cleared). Setting + * ulBitsToClearOnExit to ULONG_MAX (if limits.h is included) or 0xffffffffUL + * (if limits.h is not included) will have the effect of resetting the task's + * notification value to 0 before the function exits. Setting + * ulBitsToClearOnExit to 0 will leave the task's notification value unchanged + * when the function exits (in which case the value passed out in + * pulNotificationValue will match the task's notification value). + * + * @param pulNotificationValue Used to pass the task's notification value out + * of the function. Note the value passed out will not be effected by the + * clearing of any bits caused by ulBitsToClearOnExit being non-zero. + * + * @param xTicksToWait The maximum amount of time that the task should wait in + * the Blocked state for a notification to be received, should a notification + * not already be pending when xTaskNotifyWait() was called. The task + * will not consume any processing time while it is in the Blocked state. This + * is specified in kernel ticks, the macro pdMS_TO_TICKS( value_in_ms ) can be + * used to convert a time specified in milliseconds to a time specified in + * ticks. + * + * @return If a notification was received (including notifications that were + * already pending when xTaskNotifyWait was called) then pdPASS is + * returned. Otherwise pdFAIL is returned. + * + * \defgroup xTaskNotifyWaitIndexed xTaskNotifyWaitIndexed + * \ingroup TaskNotifications + */ +BaseType_t xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn, + uint32_t ulBitsToClearOnEntry, + uint32_t ulBitsToClearOnExit, + uint32_t * pulNotificationValue, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +#define xTaskNotifyWait( ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait ) \ + xTaskGenericNotifyWait( tskDEFAULT_INDEX_TO_NOTIFY, ( ulBitsToClearOnEntry ), ( ulBitsToClearOnExit ), ( pulNotificationValue ), ( xTicksToWait ) ) +#define xTaskNotifyWaitIndexed( uxIndexToWaitOn, ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait ) \ + xTaskGenericNotifyWait( ( uxIndexToWaitOn ), ( ulBitsToClearOnEntry ), ( ulBitsToClearOnExit ), ( pulNotificationValue ), ( xTicksToWait ) ) + +/** + * task. h + * @code{c} + * BaseType_t xTaskNotifyGiveIndexed( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify ); + * BaseType_t xTaskNotifyGive( TaskHandle_t xTaskToNotify ); + * @endcode + * + * Sends a direct to task notification to a particular index in the target + * task's notification array in a manner similar to giving a counting semaphore. + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for more details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these + * macros to be available. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment one of the task's notification values. In + * that way task notifications can be used to send data to a task, or be used as + * light weight and fast binary or counting semaphores. + * + * xTaskNotifyGiveIndexed() is a helper macro intended for use when task + * notifications are used as light weight and faster binary or counting + * semaphore equivalents. Actual FreeRTOS semaphores are given using the + * xSemaphoreGive() API function, the equivalent action that instead uses a task + * notification is xTaskNotifyGiveIndexed(). + * + * When task notifications are being used as a binary or counting semaphore + * equivalent then the task being notified should wait for the notification + * using the ulTaskNotificationTakeIndexed() API function rather than the + * xTaskNotifyWaitIndexed() API function. + * + * **NOTE** Each notification within the array operates independently - a task + * can only block on one notification within the array at a time and will not be + * unblocked by a notification sent to any other array index. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. xTaskNotifyGive() is the original API function, and remains backward + * compatible by always operating on the notification value at index 0 in the + * array. Calling xTaskNotifyGive() is equivalent to calling + * xTaskNotifyGiveIndexed() with the uxIndexToNotify parameter set to 0. + * + * @param xTaskToNotify The handle of the task being notified. The handle to a + * task can be returned from the xTaskCreate() API function used to create the + * task, and the handle of the currently running task can be obtained by calling + * xTaskGetCurrentTaskHandle(). + * + * @param uxIndexToNotify The index within the target task's array of + * notification values to which the notification is to be sent. uxIndexToNotify + * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES. xTaskNotifyGive() + * does not have this parameter and always sends notifications to index 0. + * + * @return xTaskNotifyGive() is a macro that calls xTaskNotify() with the + * eAction parameter set to eIncrement - so pdPASS is always returned. + * + * \defgroup xTaskNotifyGiveIndexed xTaskNotifyGiveIndexed + * \ingroup TaskNotifications + */ +#define xTaskNotifyGive( xTaskToNotify ) \ + xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( 0 ), eIncrement, NULL ) +#define xTaskNotifyGiveIndexed( xTaskToNotify, uxIndexToNotify ) \ + xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( 0 ), eIncrement, NULL ) + +/** + * task. h + * @code{c} + * void vTaskNotifyGiveIndexedFromISR( TaskHandle_t xTaskHandle, UBaseType_t uxIndexToNotify, BaseType_t *pxHigherPriorityTaskWoken ); + * void vTaskNotifyGiveFromISR( TaskHandle_t xTaskHandle, BaseType_t *pxHigherPriorityTaskWoken ); + * @endcode + * + * A version of xTaskNotifyGiveIndexed() that can be called from an interrupt + * service routine (ISR). + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for more details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro + * to be available. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment one of the task's notification values. In + * that way task notifications can be used to send data to a task, or be used as + * light weight and fast binary or counting semaphores. + * + * vTaskNotifyGiveIndexedFromISR() is intended for use when task notifications + * are used as light weight and faster binary or counting semaphore equivalents. + * Actual FreeRTOS semaphores are given from an ISR using the + * xSemaphoreGiveFromISR() API function, the equivalent action that instead uses + * a task notification is vTaskNotifyGiveIndexedFromISR(). + * + * When task notifications are being used as a binary or counting semaphore + * equivalent then the task being notified should wait for the notification + * using the ulTaskNotificationTakeIndexed() API function rather than the + * xTaskNotifyWaitIndexed() API function. + * + * **NOTE** Each notification within the array operates independently - a task + * can only block on one notification within the array at a time and will not be + * unblocked by a notification sent to any other array index. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. xTaskNotifyFromISR() is the original API function, and remains + * backward compatible by always operating on the notification value at index 0 + * within the array. Calling xTaskNotifyGiveFromISR() is equivalent to calling + * xTaskNotifyGiveIndexedFromISR() with the uxIndexToNotify parameter set to 0. + * + * @param xTaskToNotify The handle of the task being notified. The handle to a + * task can be returned from the xTaskCreate() API function used to create the + * task, and the handle of the currently running task can be obtained by calling + * xTaskGetCurrentTaskHandle(). + * + * @param uxIndexToNotify The index within the target task's array of + * notification values to which the notification is to be sent. uxIndexToNotify + * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES. + * xTaskNotifyGiveFromISR() does not have this parameter and always sends + * notifications to index 0. + * + * @param pxHigherPriorityTaskWoken vTaskNotifyGiveFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the + * task to which the notification was sent to leave the Blocked state, and the + * unblocked task has a priority higher than the currently running task. If + * vTaskNotifyGiveFromISR() sets this value to pdTRUE then a context switch + * should be requested before the interrupt is exited. How a context switch is + * requested from an ISR is dependent on the port - see the documentation page + * for the port in use. + * + * \defgroup vTaskNotifyGiveIndexedFromISR vTaskNotifyGiveIndexedFromISR + * \ingroup TaskNotifications + */ +void vTaskGenericNotifyGiveFromISR( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; +#define vTaskNotifyGiveFromISR( xTaskToNotify, pxHigherPriorityTaskWoken ) \ + vTaskGenericNotifyGiveFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( pxHigherPriorityTaskWoken ) ); +#define vTaskNotifyGiveIndexedFromISR( xTaskToNotify, uxIndexToNotify, pxHigherPriorityTaskWoken ) \ + vTaskGenericNotifyGiveFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( pxHigherPriorityTaskWoken ) ); + +/** + * task. h + * @code{c} + * uint32_t ulTaskNotifyTakeIndexed( UBaseType_t uxIndexToWaitOn, BaseType_t xClearCountOnExit, TickType_t xTicksToWait ); + * + * uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ); + * @endcode + * + * Waits for a direct to task notification on a particular index in the calling + * task's notification array in a manner similar to taking a counting semaphore. + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this + * function to be available. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment one of the task's notification values. In + * that way task notifications can be used to send data to a task, or be used as + * light weight and fast binary or counting semaphores. + * + * ulTaskNotifyTakeIndexed() is intended for use when a task notification is + * used as a faster and lighter weight binary or counting semaphore alternative. + * Actual FreeRTOS semaphores are taken using the xSemaphoreTake() API function, + * the equivalent action that instead uses a task notification is + * ulTaskNotifyTakeIndexed(). + * + * When a task is using its notification value as a binary or counting semaphore + * other tasks should send notifications to it using the xTaskNotifyGiveIndexed() + * macro, or xTaskNotifyIndex() function with the eAction parameter set to + * eIncrement. + * + * ulTaskNotifyTakeIndexed() can either clear the task's notification value at + * the array index specified by the uxIndexToWaitOn parameter to zero on exit, + * in which case the notification value acts like a binary semaphore, or + * decrement the notification value on exit, in which case the notification + * value acts like a counting semaphore. + * + * A task can use ulTaskNotifyTakeIndexed() to [optionally] block to wait for + * a notification. The task does not consume any CPU time while it is in the + * Blocked state. + * + * Where as xTaskNotifyWaitIndexed() will return when a notification is pending, + * ulTaskNotifyTakeIndexed() will return when the task's notification value is + * not zero. + * + * **NOTE** Each notification within the array operates independently - a task + * can only block on one notification within the array at a time and will not be + * unblocked by a notification sent to any other array index. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. ulTaskNotifyTake() is the original API function, and remains backward + * compatible by always operating on the notification value at index 0 in the + * array. Calling ulTaskNotifyTake() is equivalent to calling + * ulTaskNotifyTakeIndexed() with the uxIndexToWaitOn parameter set to 0. + * + * @param uxIndexToWaitOn The index within the calling task's array of + * notification values on which the calling task will wait for a notification to + * be non-zero. uxIndexToWaitOn must be less than + * configTASK_NOTIFICATION_ARRAY_ENTRIES. xTaskNotifyTake() does + * not have this parameter and always waits for notifications on index 0. + * + * @param xClearCountOnExit if xClearCountOnExit is pdFALSE then the task's + * notification value is decremented when the function exits. In this way the + * notification value acts like a counting semaphore. If xClearCountOnExit is + * not pdFALSE then the task's notification value is cleared to zero when the + * function exits. In this way the notification value acts like a binary + * semaphore. + * + * @param xTicksToWait The maximum amount of time that the task should wait in + * the Blocked state for the task's notification value to be greater than zero, + * should the count not already be greater than zero when + * ulTaskNotifyTake() was called. The task will not consume any processing + * time while it is in the Blocked state. This is specified in kernel ticks, + * the macro pdMS_TO_TICKS( value_in_ms ) can be used to convert a time + * specified in milliseconds to a time specified in ticks. + * + * @return The task's notification count before it is either cleared to zero or + * decremented (see the xClearCountOnExit parameter). + * + * \defgroup ulTaskNotifyTakeIndexed ulTaskNotifyTakeIndexed + * \ingroup TaskNotifications + */ +uint32_t ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +#define ulTaskNotifyTake( xClearCountOnExit, xTicksToWait ) \ + ulTaskGenericNotifyTake( ( tskDEFAULT_INDEX_TO_NOTIFY ), ( xClearCountOnExit ), ( xTicksToWait ) ) +#define ulTaskNotifyTakeIndexed( uxIndexToWaitOn, xClearCountOnExit, xTicksToWait ) \ + ulTaskGenericNotifyTake( ( uxIndexToWaitOn ), ( xClearCountOnExit ), ( xTicksToWait ) ) + +/** + * task. h + * @code{c} + * BaseType_t xTaskNotifyStateClearIndexed( TaskHandle_t xTask, UBaseType_t uxIndexToCLear ); + * + * BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask ); + * @endcode + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these + * functions to be available. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * If a notification is sent to an index within the array of notifications then + * the notification at that index is said to be 'pending' until it is read or + * explicitly cleared by the receiving task. xTaskNotifyStateClearIndexed() + * is the function that clears a pending notification without reading the + * notification value. The notification value at the same array index is not + * altered. Set xTask to NULL to clear the notification state of the calling + * task. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. xTaskNotifyStateClear() is the original API function, and remains + * backward compatible by always operating on the notification value at index 0 + * within the array. Calling xTaskNotifyStateClear() is equivalent to calling + * xTaskNotifyStateClearIndexed() with the uxIndexToNotify parameter set to 0. + * + * @param xTask The handle of the RTOS task that will have a notification state + * cleared. Set xTask to NULL to clear a notification state in the calling + * task. To obtain a task's handle create the task using xTaskCreate() and + * make use of the pxCreatedTask parameter, or create the task using + * xTaskCreateStatic() and store the returned value, or use the task's name in + * a call to xTaskGetHandle(). + * + * @param uxIndexToClear The index within the target task's array of + * notification values to act upon. For example, setting uxIndexToClear to 1 + * will clear the state of the notification at index 1 within the array. + * uxIndexToClear must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES. + * ulTaskNotifyStateClear() does not have this parameter and always acts on the + * notification at index 0. + * + * @return pdTRUE if the task's notification state was set to + * eNotWaitingNotification, otherwise pdFALSE. + * + * \defgroup xTaskNotifyStateClearIndexed xTaskNotifyStateClearIndexed + * \ingroup TaskNotifications + */ +BaseType_t xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) PRIVILEGED_FUNCTION; +#define xTaskNotifyStateClear( xTask ) \ + xTaskGenericNotifyStateClear( ( xTask ), ( tskDEFAULT_INDEX_TO_NOTIFY ) ) +#define xTaskNotifyStateClearIndexed( xTask, uxIndexToClear ) \ + xTaskGenericNotifyStateClear( ( xTask ), ( uxIndexToClear ) ) + +/** + * task. h + * @code{c} + * uint32_t ulTaskNotifyValueClearIndexed( TaskHandle_t xTask, UBaseType_t uxIndexToClear, uint32_t ulBitsToClear ); + * + * uint32_t ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear ); + * @endcode + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these + * functions to be available. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * ulTaskNotifyValueClearIndexed() clears the bits specified by the + * ulBitsToClear bit mask in the notification value at array index uxIndexToClear + * of the task referenced by xTask. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. ulTaskNotifyValueClear() is the original API function, and remains + * backward compatible by always operating on the notification value at index 0 + * within the array. Calling ulTaskNotifyValueClear() is equivalent to calling + * ulTaskNotifyValueClearIndexed() with the uxIndexToClear parameter set to 0. + * + * @param xTask The handle of the RTOS task that will have bits in one of its + * notification values cleared. Set xTask to NULL to clear bits in a + * notification value of the calling task. To obtain a task's handle create the + * task using xTaskCreate() and make use of the pxCreatedTask parameter, or + * create the task using xTaskCreateStatic() and store the returned value, or + * use the task's name in a call to xTaskGetHandle(). + * + * @param uxIndexToClear The index within the target task's array of + * notification values in which to clear the bits. uxIndexToClear + * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES. + * ulTaskNotifyValueClear() does not have this parameter and always clears bits + * in the notification value at index 0. + * + * @param ulBitsToClear Bit mask of the bits to clear in the notification value of + * xTask. Set a bit to 1 to clear the corresponding bits in the task's notification + * value. Set ulBitsToClear to 0xffffffff (UINT_MAX on 32-bit architectures) to clear + * the notification value to 0. Set ulBitsToClear to 0 to query the task's + * notification value without clearing any bits. + * + * + * @return The value of the target task's notification value before the bits + * specified by ulBitsToClear were cleared. + * \defgroup ulTaskNotifyValueClear ulTaskNotifyValueClear + * \ingroup TaskNotifications + */ +uint32_t ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION; +#define ulTaskNotifyValueClear( xTask, ulBitsToClear ) \ + ulTaskGenericNotifyValueClear( ( xTask ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulBitsToClear ) ) +#define ulTaskNotifyValueClearIndexed( xTask, uxIndexToClear, ulBitsToClear ) \ + ulTaskGenericNotifyValueClear( ( xTask ), ( uxIndexToClear ), ( ulBitsToClear ) ) + +/** + * task.h + * @code{c} + * void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ); + * @endcode + * + * Capture the current time for future use with xTaskCheckForTimeOut(). + * + * @param pxTimeOut Pointer to a timeout object into which the current time + * is to be captured. The captured time includes the tick count and the number + * of times the tick count has overflowed since the system first booted. + * \defgroup vTaskSetTimeOutState vTaskSetTimeOutState + * \ingroup TaskCtrl + */ +void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION; + +/** + * task.h + * @code{c} + * BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ); + * @endcode + * + * Determines if pxTicksToWait ticks has passed since a time was captured + * using a call to vTaskSetTimeOutState(). The captured time includes the tick + * count and the number of times the tick count has overflowed. + * + * @param pxTimeOut The time status as captured previously using + * vTaskSetTimeOutState. If the timeout has not yet occurred, it is updated + * to reflect the current time status. + * @param pxTicksToWait The number of ticks to check for timeout i.e. if + * pxTicksToWait ticks have passed since pxTimeOut was last updated (either by + * vTaskSetTimeOutState() or xTaskCheckForTimeOut()), the timeout has occurred. + * If the timeout has not occurred, pxTicksToWait is updated to reflect the + * number of remaining ticks. + * + * @return If timeout has occurred, pdTRUE is returned. Otherwise pdFALSE is + * returned and pxTicksToWait is updated to reflect the number of remaining + * ticks. + * + * @see https://www.FreeRTOS.org/xTaskCheckForTimeOut.html + * + * Example Usage: + * @code{c} + * // Driver library function used to receive uxWantedBytes from an Rx buffer + * // that is filled by a UART interrupt. If there are not enough bytes in the + * // Rx buffer then the task enters the Blocked state until it is notified that + * // more data has been placed into the buffer. If there is still not enough + * // data then the task re-enters the Blocked state, and xTaskCheckForTimeOut() + * // is used to re-calculate the Block time to ensure the total amount of time + * // spent in the Blocked state does not exceed MAX_TIME_TO_WAIT. This + * // continues until either the buffer contains at least uxWantedBytes bytes, + * // or the total amount of time spent in the Blocked state reaches + * // MAX_TIME_TO_WAIT - at which point the task reads however many bytes are + * // available up to a maximum of uxWantedBytes. + * + * size_t xUART_Receive( uint8_t *pucBuffer, size_t uxWantedBytes ) + * { + * size_t uxReceived = 0; + * TickType_t xTicksToWait = MAX_TIME_TO_WAIT; + * TimeOut_t xTimeOut; + * + * // Initialize xTimeOut. This records the time at which this function + * // was entered. + * vTaskSetTimeOutState( &xTimeOut ); + * + * // Loop until the buffer contains the wanted number of bytes, or a + * // timeout occurs. + * while( UART_bytes_in_rx_buffer( pxUARTInstance ) < uxWantedBytes ) + * { + * // The buffer didn't contain enough data so this task is going to + * // enter the Blocked state. Adjusting xTicksToWait to account for + * // any time that has been spent in the Blocked state within this + * // function so far to ensure the total amount of time spent in the + * // Blocked state does not exceed MAX_TIME_TO_WAIT. + * if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) != pdFALSE ) + * { + * //Timed out before the wanted number of bytes were available, + * // exit the loop. + * break; + * } + * + * // Wait for a maximum of xTicksToWait ticks to be notified that the + * // receive interrupt has placed more data into the buffer. + * ulTaskNotifyTake( pdTRUE, xTicksToWait ); + * } + * + * // Attempt to read uxWantedBytes from the receive buffer into pucBuffer. + * // The actual number of bytes read (which might be less than + * // uxWantedBytes) is returned. + * uxReceived = UART_read_from_receive_buffer( pxUARTInstance, + * pucBuffer, + * uxWantedBytes ); + * + * return uxReceived; + * } + * @endcode + * \defgroup xTaskCheckForTimeOut xTaskCheckForTimeOut + * \ingroup TaskCtrl + */ +BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * task.h + * @code{c} + * BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ); + * @endcode + * + * This function corrects the tick count value after the application code has held + * interrupts disabled for an extended period resulting in tick interrupts having + * been missed. + * + * This function is similar to vTaskStepTick(), however, unlike + * vTaskStepTick(), xTaskCatchUpTicks() may move the tick count forward past a + * time at which a task should be removed from the blocked state. That means + * tasks may have to be removed from the blocked state as the tick count is + * moved. + * + * @param xTicksToCatchUp The number of tick interrupts that have been missed due to + * interrupts being disabled. Its value is not computed automatically, so must be + * computed by the application writer. + * + * @return pdTRUE if moving the tick count forward resulted in a task leaving the + * blocked state and a context switch being performed. Otherwise pdFALSE. + * + * \defgroup xTaskCatchUpTicks xTaskCatchUpTicks + * \ingroup TaskCtrl + */ +BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) PRIVILEGED_FUNCTION; + + +/*----------------------------------------------------------- +* SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES +*----------------------------------------------------------*/ + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY + * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS + * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * Called from the real time kernel tick (either preemptive or cooperative), + * this increments the tick count and checks if any tasks that are blocked + * for a finite period required removing from a blocked list and placing on + * a ready list. If a non-zero value is returned then a context switch is + * required because either: + * + A task was removed from a blocked list because its timeout had expired, + * or + * + Time slicing is in use and there is a task of equal priority to the + * currently running task. + */ +BaseType_t xTaskIncrementTick( void ) PRIVILEGED_FUNCTION; + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN + * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. + * + * Removes the calling task from the ready list and places it both + * on the list of tasks waiting for a particular event, and the + * list of delayed tasks. The task will be removed from both lists + * and replaced on the ready list should either the event occur (and + * there be no higher priority tasks waiting on the same event) or + * the delay period expires. + * + * The 'unordered' version replaces the event list item value with the + * xItemValue value, and inserts the list item at the end of the list. + * + * The 'ordered' version uses the existing event list item value (which is the + * owning task's priority) to insert the list item into the event list in task + * priority order. + * + * @param pxEventList The list containing tasks that are blocked waiting + * for the event to occur. + * + * @param xItemValue The item value to use for the event list item when the + * event list is not ordered by task priority. + * + * @param xTicksToWait The maximum amount of time that the task should wait + * for the event to occur. This is specified in kernel ticks, the constant + * portTICK_PERIOD_MS can be used to convert kernel ticks into a real time + * period. + */ +void vTaskPlaceOnEventList( List_t * const pxEventList, + const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, + const TickType_t xItemValue, + const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN + * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. + * + * This function performs nearly the same function as vTaskPlaceOnEventList(). + * The difference being that this function does not permit tasks to block + * indefinitely, whereas vTaskPlaceOnEventList() does. + * + */ +void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, + TickType_t xTicksToWait, + const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION; + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN + * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. + * + * Removes a task from both the specified event list and the list of blocked + * tasks, and places it on a ready queue. + * + * xTaskRemoveFromEventList()/vTaskRemoveFromUnorderedEventList() will be called + * if either an event occurs to unblock a task, or the block timeout period + * expires. + * + * xTaskRemoveFromEventList() is used when the event list is in task priority + * order. It removes the list item from the head of the event list as that will + * have the highest priority owning task of all the tasks on the event list. + * vTaskRemoveFromUnorderedEventList() is used when the event list is not + * ordered and the event list items hold something other than the owning tasks + * priority. In this case the event list item value is updated to the value + * passed in the xItemValue parameter. + * + * @return pdTRUE if the task being removed has a higher priority than the task + * making the call, otherwise pdFALSE. + */ +BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) PRIVILEGED_FUNCTION; +void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, + const TickType_t xItemValue ) PRIVILEGED_FUNCTION; + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY + * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS + * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * Sets the pointer to the current TCB to the TCB of the highest priority task + * that is ready to run. + */ +portDONT_DISCARD void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION; + +/* + * THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE. THEY ARE USED BY + * THE EVENT BITS MODULE. + */ +TickType_t uxTaskResetEventItemValue( void ) PRIVILEGED_FUNCTION; + +/* + * Return the handle of the calling task. + */ +TaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION; + +/* + * Shortcut used by the queue implementation to prevent unnecessary call to + * taskYIELD(); + */ +void vTaskMissedYield( void ) PRIVILEGED_FUNCTION; + +/* + * Returns the scheduler state as taskSCHEDULER_RUNNING, + * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED. + */ +BaseType_t xTaskGetSchedulerState( void ) PRIVILEGED_FUNCTION; + +/* + * Raises the priority of the mutex holder to that of the calling task should + * the mutex holder have a priority less than the calling task. + */ +BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION; + +/* + * Set the priority of a task back to its proper priority in the case that it + * inherited a higher priority while it was holding a semaphore. + */ +BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION; + +/* + * If a higher priority task attempting to obtain a mutex caused a lower + * priority task to inherit the higher priority task's priority - but the higher + * priority task then timed out without obtaining the mutex, then the lower + * priority task will disinherit the priority again - but only down as far as + * the highest priority task that is still waiting for the mutex (if there were + * more than one task waiting for the mutex). + */ +void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, + UBaseType_t uxHighestPriorityWaitingTask ) PRIVILEGED_FUNCTION; + +/* + * Get the uxTCBNumber assigned to the task referenced by the xTask parameter. + */ +UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/* + * Set the uxTaskNumber of the task referenced by the xTask parameter to + * uxHandle. + */ +void vTaskSetTaskNumber( TaskHandle_t xTask, + const UBaseType_t uxHandle ) PRIVILEGED_FUNCTION; + +/* + * Only available when configUSE_TICKLESS_IDLE is set to 1. + * If tickless mode is being used, or a low power mode is implemented, then + * the tick interrupt will not execute during idle periods. When this is the + * case, the tick count value maintained by the scheduler needs to be kept up + * to date with the actual execution time by being skipped forward by a time + * equal to the idle period. + */ +void vTaskStepTick( const TickType_t xTicksToJump ) PRIVILEGED_FUNCTION; + +/* + * Only available when configUSE_TICKLESS_IDLE is set to 1. + * Provided for use within portSUPPRESS_TICKS_AND_SLEEP() to allow the port + * specific sleep function to determine if it is ok to proceed with the sleep, + * and if it is ok to proceed, if it is ok to sleep indefinitely. + * + * This function is necessary because portSUPPRESS_TICKS_AND_SLEEP() is only + * called with the scheduler suspended, not from within a critical section. It + * is therefore possible for an interrupt to request a context switch between + * portSUPPRESS_TICKS_AND_SLEEP() and the low power mode actually being + * entered. eTaskConfirmSleepModeStatus() should be called from a short + * critical section between the timer being stopped and the sleep mode being + * entered to ensure it is ok to proceed into the sleep mode. + */ +eSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION; + +/* + * For internal use only. Increment the mutex held count when a mutex is + * taken and return the handle of the task that has taken the mutex. + */ +TaskHandle_t pvTaskIncrementMutexHeldCount( void ) PRIVILEGED_FUNCTION; + +/* + * For internal use only. Same as vTaskSetTimeOutState(), but without a critical + * section. + */ +void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION; + + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ +#endif /* INC_TASK_H */ diff --git a/hw-libs/freertos/include/timers.h b/hw-libs/freertos/include/timers.h new file mode 100644 index 000000000..2be826c21 --- /dev/null +++ b/hw-libs/freertos/include/timers.h @@ -0,0 +1,1355 @@ +/* + * FreeRTOS Kernel V10.4.6 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef TIMERS_H +#define TIMERS_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include timers.h" +#endif + +/*lint -save -e537 This headers are only multiply included if the application code + * happens to also be including task.h. */ +#include "task.h" +/*lint -restore */ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- +* MACROS AND DEFINITIONS +*----------------------------------------------------------*/ + +/* IDs for commands that can be sent/received on the timer queue. These are to + * be used solely through the macros that make up the public software timer API, + * as defined below. The commands that are sent from interrupts must use the + * highest numbers as tmrFIRST_FROM_ISR_COMMAND is used to determine if the task + * or interrupt version of the queue send function should be used. */ +#define tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR ( ( BaseType_t ) -2 ) +#define tmrCOMMAND_EXECUTE_CALLBACK ( ( BaseType_t ) -1 ) +#define tmrCOMMAND_START_DONT_TRACE ( ( BaseType_t ) 0 ) +#define tmrCOMMAND_START ( ( BaseType_t ) 1 ) +#define tmrCOMMAND_RESET ( ( BaseType_t ) 2 ) +#define tmrCOMMAND_STOP ( ( BaseType_t ) 3 ) +#define tmrCOMMAND_CHANGE_PERIOD ( ( BaseType_t ) 4 ) +#define tmrCOMMAND_DELETE ( ( BaseType_t ) 5 ) + +#define tmrFIRST_FROM_ISR_COMMAND ( ( BaseType_t ) 6 ) +#define tmrCOMMAND_START_FROM_ISR ( ( BaseType_t ) 6 ) +#define tmrCOMMAND_RESET_FROM_ISR ( ( BaseType_t ) 7 ) +#define tmrCOMMAND_STOP_FROM_ISR ( ( BaseType_t ) 8 ) +#define tmrCOMMAND_CHANGE_PERIOD_FROM_ISR ( ( BaseType_t ) 9 ) + + +/** + * Type by which software timers are referenced. For example, a call to + * xTimerCreate() returns an TimerHandle_t variable that can then be used to + * reference the subject timer in calls to other software timer API functions + * (for example, xTimerStart(), xTimerReset(), etc.). + */ +struct tmrTimerControl; /* The old naming convention is used to prevent breaking kernel aware debuggers. */ +typedef struct tmrTimerControl * TimerHandle_t; + +/* + * Defines the prototype to which timer callback functions must conform. + */ +typedef void (* TimerCallbackFunction_t)( TimerHandle_t xTimer ); + +/* + * Defines the prototype to which functions used with the + * xTimerPendFunctionCallFromISR() function must conform. + */ +typedef void (* PendedFunction_t)( void *, + uint32_t ); + +/** + * TimerHandle_t xTimerCreate( const char * const pcTimerName, + * TickType_t xTimerPeriodInTicks, + * UBaseType_t uxAutoReload, + * void * pvTimerID, + * TimerCallbackFunction_t pxCallbackFunction ); + * + * Creates a new software timer instance, and returns a handle by which the + * created software timer can be referenced. + * + * Internally, within the FreeRTOS implementation, software timers use a block + * of memory, in which the timer data structure is stored. If a software timer + * is created using xTimerCreate() then the required memory is automatically + * dynamically allocated inside the xTimerCreate() function. (see + * https://www.FreeRTOS.org/a00111.html). If a software timer is created using + * xTimerCreateStatic() then the application writer must provide the memory that + * will get used by the software timer. xTimerCreateStatic() therefore allows a + * software timer to be created without using any dynamic memory allocation. + * + * Timers are created in the dormant state. The xTimerStart(), xTimerReset(), + * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and + * xTimerChangePeriodFromISR() API functions can all be used to transition a + * timer into the active state. + * + * @param pcTimerName A text name that is assigned to the timer. This is done + * purely to assist debugging. The kernel itself only ever references a timer + * by its handle, and never by its name. + * + * @param xTimerPeriodInTicks The timer period. The time is defined in tick + * periods so the constant portTICK_PERIOD_MS can be used to convert a time that + * has been specified in milliseconds. For example, if the timer must expire + * after 100 ticks, then xTimerPeriodInTicks should be set to 100. + * Alternatively, if the timer must expire after 500ms, then xPeriod can be set + * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or + * equal to 1000. Time timer period must be greater than 0. + * + * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will + * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter. + * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and + * enter the dormant state after it expires. + * + * @param pvTimerID An identifier that is assigned to the timer being created. + * Typically this would be used in the timer callback function to identify which + * timer expired when the same callback function is assigned to more than one + * timer. + * + * @param pxCallbackFunction The function to call when the timer expires. + * Callback functions must have the prototype defined by TimerCallbackFunction_t, + * which is "void vCallbackFunction( TimerHandle_t xTimer );". + * + * @return If the timer is successfully created then a handle to the newly + * created timer is returned. If the timer cannot be created because there is + * insufficient FreeRTOS heap remaining to allocate the timer + * structures then NULL is returned. + * + * Example usage: + * @verbatim + * #define NUM_TIMERS 5 + * + * // An array to hold handles to the created timers. + * TimerHandle_t xTimers[ NUM_TIMERS ]; + * + * // An array to hold a count of the number of times each timer expires. + * int32_t lExpireCounters[ NUM_TIMERS ] = { 0 }; + * + * // Define a callback function that will be used by multiple timer instances. + * // The callback function does nothing but count the number of times the + * // associated timer expires, and stop the timer once the timer has expired + * // 10 times. + * void vTimerCallback( TimerHandle_t pxTimer ) + * { + * int32_t lArrayIndex; + * const int32_t xMaxExpiryCountBeforeStopping = 10; + * + * // Optionally do something if the pxTimer parameter is NULL. + * configASSERT( pxTimer ); + * + * // Which timer expired? + * lArrayIndex = ( int32_t ) pvTimerGetTimerID( pxTimer ); + * + * // Increment the number of times that pxTimer has expired. + * lExpireCounters[ lArrayIndex ] += 1; + * + * // If the timer has expired 10 times then stop it from running. + * if( lExpireCounters[ lArrayIndex ] == xMaxExpiryCountBeforeStopping ) + * { + * // Do not use a block time if calling a timer API function from a + * // timer callback function, as doing so could cause a deadlock! + * xTimerStop( pxTimer, 0 ); + * } + * } + * + * void main( void ) + * { + * int32_t x; + * + * // Create then start some timers. Starting the timers before the scheduler + * // has been started means the timers will start running immediately that + * // the scheduler starts. + * for( x = 0; x < NUM_TIMERS; x++ ) + * { + * xTimers[ x ] = xTimerCreate( "Timer", // Just a text name, not used by the kernel. + * ( 100 * x ), // The timer period in ticks. + * pdTRUE, // The timers will auto-reload themselves when they expire. + * ( void * ) x, // Assign each timer a unique id equal to its array index. + * vTimerCallback // Each timer calls the same callback when it expires. + * ); + * + * if( xTimers[ x ] == NULL ) + * { + * // The timer was not created. + * } + * else + * { + * // Start the timer. No block time is specified, and even if one was + * // it would be ignored because the scheduler has not yet been + * // started. + * if( xTimerStart( xTimers[ x ], 0 ) != pdPASS ) + * { + * // The timer could not be set into the Active state. + * } + * } + * } + * + * // ... + * // Create tasks here. + * // ... + * + * // Starting the scheduler will start the timers running as they have already + * // been set into the active state. + * vTaskStartScheduler(); + * + * // Should not reach here. + * for( ;; ); + * } + * @endverbatim + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + TimerHandle_t xTimerCreate( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const TickType_t xTimerPeriodInTicks, + const UBaseType_t uxAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION; +#endif + +/** + * TimerHandle_t xTimerCreateStatic(const char * const pcTimerName, + * TickType_t xTimerPeriodInTicks, + * UBaseType_t uxAutoReload, + * void * pvTimerID, + * TimerCallbackFunction_t pxCallbackFunction, + * StaticTimer_t *pxTimerBuffer ); + * + * Creates a new software timer instance, and returns a handle by which the + * created software timer can be referenced. + * + * Internally, within the FreeRTOS implementation, software timers use a block + * of memory, in which the timer data structure is stored. If a software timer + * is created using xTimerCreate() then the required memory is automatically + * dynamically allocated inside the xTimerCreate() function. (see + * https://www.FreeRTOS.org/a00111.html). If a software timer is created using + * xTimerCreateStatic() then the application writer must provide the memory that + * will get used by the software timer. xTimerCreateStatic() therefore allows a + * software timer to be created without using any dynamic memory allocation. + * + * Timers are created in the dormant state. The xTimerStart(), xTimerReset(), + * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and + * xTimerChangePeriodFromISR() API functions can all be used to transition a + * timer into the active state. + * + * @param pcTimerName A text name that is assigned to the timer. This is done + * purely to assist debugging. The kernel itself only ever references a timer + * by its handle, and never by its name. + * + * @param xTimerPeriodInTicks The timer period. The time is defined in tick + * periods so the constant portTICK_PERIOD_MS can be used to convert a time that + * has been specified in milliseconds. For example, if the timer must expire + * after 100 ticks, then xTimerPeriodInTicks should be set to 100. + * Alternatively, if the timer must expire after 500ms, then xPeriod can be set + * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or + * equal to 1000. The timer period must be greater than 0. + * + * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will + * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter. + * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and + * enter the dormant state after it expires. + * + * @param pvTimerID An identifier that is assigned to the timer being created. + * Typically this would be used in the timer callback function to identify which + * timer expired when the same callback function is assigned to more than one + * timer. + * + * @param pxCallbackFunction The function to call when the timer expires. + * Callback functions must have the prototype defined by TimerCallbackFunction_t, + * which is "void vCallbackFunction( TimerHandle_t xTimer );". + * + * @param pxTimerBuffer Must point to a variable of type StaticTimer_t, which + * will be then be used to hold the software timer's data structures, removing + * the need for the memory to be allocated dynamically. + * + * @return If the timer is created then a handle to the created timer is + * returned. If pxTimerBuffer was NULL then NULL is returned. + * + * Example usage: + * @verbatim + * + * // The buffer used to hold the software timer's data structure. + * static StaticTimer_t xTimerBuffer; + * + * // A variable that will be incremented by the software timer's callback + * // function. + * UBaseType_t uxVariableToIncrement = 0; + * + * // A software timer callback function that increments a variable passed to + * // it when the software timer was created. After the 5th increment the + * // callback function stops the software timer. + * static void prvTimerCallback( TimerHandle_t xExpiredTimer ) + * { + * UBaseType_t *puxVariableToIncrement; + * BaseType_t xReturned; + * + * // Obtain the address of the variable to increment from the timer ID. + * puxVariableToIncrement = ( UBaseType_t * ) pvTimerGetTimerID( xExpiredTimer ); + * + * // Increment the variable to show the timer callback has executed. + * ( *puxVariableToIncrement )++; + * + * // If this callback has executed the required number of times, stop the + * // timer. + * if( *puxVariableToIncrement == 5 ) + * { + * // This is called from a timer callback so must not block. + * xTimerStop( xExpiredTimer, staticDONT_BLOCK ); + * } + * } + * + * + * void main( void ) + * { + * // Create the software time. xTimerCreateStatic() has an extra parameter + * // than the normal xTimerCreate() API function. The parameter is a pointer + * // to the StaticTimer_t structure that will hold the software timer + * // structure. If the parameter is passed as NULL then the structure will be + * // allocated dynamically, just as if xTimerCreate() had been called. + * xTimer = xTimerCreateStatic( "T1", // Text name for the task. Helps debugging only. Not used by FreeRTOS. + * xTimerPeriod, // The period of the timer in ticks. + * pdTRUE, // This is an auto-reload timer. + * ( void * ) &uxVariableToIncrement, // A variable incremented by the software timer's callback function + * prvTimerCallback, // The function to execute when the timer expires. + * &xTimerBuffer ); // The buffer that will hold the software timer structure. + * + * // The scheduler has not started yet so a block time is not used. + * xReturned = xTimerStart( xTimer, 0 ); + * + * // ... + * // Create tasks here. + * // ... + * + * // Starting the scheduler will start the timers running as they have already + * // been set into the active state. + * vTaskStartScheduler(); + * + * // Should not reach here. + * for( ;; ); + * } + * @endverbatim + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + TimerHandle_t xTimerCreateStatic( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const TickType_t xTimerPeriodInTicks, + const UBaseType_t uxAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction, + StaticTimer_t * pxTimerBuffer ) PRIVILEGED_FUNCTION; +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/** + * void *pvTimerGetTimerID( TimerHandle_t xTimer ); + * + * Returns the ID assigned to the timer. + * + * IDs are assigned to timers using the pvTimerID parameter of the call to + * xTimerCreated() that was used to create the timer, and by calling the + * vTimerSetTimerID() API function. + * + * If the same callback function is assigned to multiple timers then the timer + * ID can be used as time specific (timer local) storage. + * + * @param xTimer The timer being queried. + * + * @return The ID assigned to the timer being queried. + * + * Example usage: + * + * See the xTimerCreate() API function example usage scenario. + */ +void * pvTimerGetTimerID( const TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; + +/** + * void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ); + * + * Sets the ID assigned to the timer. + * + * IDs are assigned to timers using the pvTimerID parameter of the call to + * xTimerCreated() that was used to create the timer. + * + * If the same callback function is assigned to multiple timers then the timer + * ID can be used as time specific (timer local) storage. + * + * @param xTimer The timer being updated. + * + * @param pvNewID The ID to assign to the timer. + * + * Example usage: + * + * See the xTimerCreate() API function example usage scenario. + */ +void vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) PRIVILEGED_FUNCTION; + +/** + * BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ); + * + * Queries a timer to see if it is active or dormant. + * + * A timer will be dormant if: + * 1) It has been created but not started, or + * 2) It is an expired one-shot timer that has not been restarted. + * + * Timers are created in the dormant state. The xTimerStart(), xTimerReset(), + * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and + * xTimerChangePeriodFromISR() API functions can all be used to transition a timer into the + * active state. + * + * @param xTimer The timer being queried. + * + * @return pdFALSE will be returned if the timer is dormant. A value other than + * pdFALSE will be returned if the timer is active. + * + * Example usage: + * @verbatim + * // This function assumes xTimer has already been created. + * void vAFunction( TimerHandle_t xTimer ) + * { + * if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )" + * { + * // xTimer is active, do something. + * } + * else + * { + * // xTimer is not active, do something else. + * } + * } + * @endverbatim + */ +BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; + +/** + * TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ); + * + * Simply returns the handle of the timer service/daemon task. It it not valid + * to call xTimerGetTimerDaemonTaskHandle() before the scheduler has been started. + */ +TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) PRIVILEGED_FUNCTION; + +/** + * BaseType_t xTimerStart( TimerHandle_t xTimer, TickType_t xTicksToWait ); + * + * Timer functionality is provided by a timer service/daemon task. Many of the + * public FreeRTOS timer API functions send commands to the timer service task + * through a queue called the timer command queue. The timer command queue is + * private to the kernel itself and is not directly accessible to application + * code. The length of the timer command queue is set by the + * configTIMER_QUEUE_LENGTH configuration constant. + * + * xTimerStart() starts a timer that was previously created using the + * xTimerCreate() API function. If the timer had already been started and was + * already in the active state, then xTimerStart() has equivalent functionality + * to the xTimerReset() API function. + * + * Starting a timer ensures the timer is in the active state. If the timer + * is not stopped, deleted, or reset in the mean time, the callback function + * associated with the timer will get called 'n' ticks after xTimerStart() was + * called, where 'n' is the timers defined period. + * + * It is valid to call xTimerStart() before the scheduler has been started, but + * when this is done the timer will not actually start until the scheduler is + * started, and the timers expiry time will be relative to when the scheduler is + * started, not relative to when xTimerStart() was called. + * + * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStart() + * to be available. + * + * @param xTimer The handle of the timer being started/restarted. + * + * @param xTicksToWait Specifies the time, in ticks, that the calling task should + * be held in the Blocked state to wait for the start command to be successfully + * sent to the timer command queue, should the queue already be full when + * xTimerStart() was called. xTicksToWait is ignored if xTimerStart() is called + * before the scheduler is started. + * + * @return pdFAIL will be returned if the start command could not be sent to + * the timer command queue even after xTicksToWait ticks had passed. pdPASS will + * be returned if the command was successfully sent to the timer command queue. + * When the command is actually processed will depend on the priority of the + * timer service/daemon task relative to other tasks in the system, although the + * timers expiry time is relative to when xTimerStart() is actually called. The + * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY + * configuration constant. + * + * Example usage: + * + * See the xTimerCreate() API function example usage scenario. + * + */ +#define xTimerStart( xTimer, xTicksToWait ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) ) + +/** + * BaseType_t xTimerStop( TimerHandle_t xTimer, TickType_t xTicksToWait ); + * + * Timer functionality is provided by a timer service/daemon task. Many of the + * public FreeRTOS timer API functions send commands to the timer service task + * through a queue called the timer command queue. The timer command queue is + * private to the kernel itself and is not directly accessible to application + * code. The length of the timer command queue is set by the + * configTIMER_QUEUE_LENGTH configuration constant. + * + * xTimerStop() stops a timer that was previously started using either of the + * The xTimerStart(), xTimerReset(), xTimerStartFromISR(), xTimerResetFromISR(), + * xTimerChangePeriod() or xTimerChangePeriodFromISR() API functions. + * + * Stopping a timer ensures the timer is not in the active state. + * + * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStop() + * to be available. + * + * @param xTimer The handle of the timer being stopped. + * + * @param xTicksToWait Specifies the time, in ticks, that the calling task should + * be held in the Blocked state to wait for the stop command to be successfully + * sent to the timer command queue, should the queue already be full when + * xTimerStop() was called. xTicksToWait is ignored if xTimerStop() is called + * before the scheduler is started. + * + * @return pdFAIL will be returned if the stop command could not be sent to + * the timer command queue even after xTicksToWait ticks had passed. pdPASS will + * be returned if the command was successfully sent to the timer command queue. + * When the command is actually processed will depend on the priority of the + * timer service/daemon task relative to other tasks in the system. The timer + * service/daemon task priority is set by the configTIMER_TASK_PRIORITY + * configuration constant. + * + * Example usage: + * + * See the xTimerCreate() API function example usage scenario. + * + */ +#define xTimerStop( xTimer, xTicksToWait ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0U, NULL, ( xTicksToWait ) ) + +/** + * BaseType_t xTimerChangePeriod( TimerHandle_t xTimer, + * TickType_t xNewPeriod, + * TickType_t xTicksToWait ); + * + * Timer functionality is provided by a timer service/daemon task. Many of the + * public FreeRTOS timer API functions send commands to the timer service task + * through a queue called the timer command queue. The timer command queue is + * private to the kernel itself and is not directly accessible to application + * code. The length of the timer command queue is set by the + * configTIMER_QUEUE_LENGTH configuration constant. + * + * xTimerChangePeriod() changes the period of a timer that was previously + * created using the xTimerCreate() API function. + * + * xTimerChangePeriod() can be called to change the period of an active or + * dormant state timer. + * + * The configUSE_TIMERS configuration constant must be set to 1 for + * xTimerChangePeriod() to be available. + * + * @param xTimer The handle of the timer that is having its period changed. + * + * @param xNewPeriod The new period for xTimer. Timer periods are specified in + * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time + * that has been specified in milliseconds. For example, if the timer must + * expire after 100 ticks, then xNewPeriod should be set to 100. Alternatively, + * if the timer must expire after 500ms, then xNewPeriod can be set to + * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than + * or equal to 1000. + * + * @param xTicksToWait Specifies the time, in ticks, that the calling task should + * be held in the Blocked state to wait for the change period command to be + * successfully sent to the timer command queue, should the queue already be + * full when xTimerChangePeriod() was called. xTicksToWait is ignored if + * xTimerChangePeriod() is called before the scheduler is started. + * + * @return pdFAIL will be returned if the change period command could not be + * sent to the timer command queue even after xTicksToWait ticks had passed. + * pdPASS will be returned if the command was successfully sent to the timer + * command queue. When the command is actually processed will depend on the + * priority of the timer service/daemon task relative to other tasks in the + * system. The timer service/daemon task priority is set by the + * configTIMER_TASK_PRIORITY configuration constant. + * + * Example usage: + * @verbatim + * // This function assumes xTimer has already been created. If the timer + * // referenced by xTimer is already active when it is called, then the timer + * // is deleted. If the timer referenced by xTimer is not active when it is + * // called, then the period of the timer is set to 500ms and the timer is + * // started. + * void vAFunction( TimerHandle_t xTimer ) + * { + * if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )" + * { + * // xTimer is already active - delete it. + * xTimerDelete( xTimer ); + * } + * else + * { + * // xTimer is not active, change its period to 500ms. This will also + * // cause the timer to start. Block for a maximum of 100 ticks if the + * // change period command cannot immediately be sent to the timer + * // command queue. + * if( xTimerChangePeriod( xTimer, 500 / portTICK_PERIOD_MS, 100 ) == pdPASS ) + * { + * // The command was successfully sent. + * } + * else + * { + * // The command could not be sent, even after waiting for 100 ticks + * // to pass. Take appropriate action here. + * } + * } + * } + * @endverbatim + */ +#define xTimerChangePeriod( xTimer, xNewPeriod, xTicksToWait ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), NULL, ( xTicksToWait ) ) + +/** + * BaseType_t xTimerDelete( TimerHandle_t xTimer, TickType_t xTicksToWait ); + * + * Timer functionality is provided by a timer service/daemon task. Many of the + * public FreeRTOS timer API functions send commands to the timer service task + * through a queue called the timer command queue. The timer command queue is + * private to the kernel itself and is not directly accessible to application + * code. The length of the timer command queue is set by the + * configTIMER_QUEUE_LENGTH configuration constant. + * + * xTimerDelete() deletes a timer that was previously created using the + * xTimerCreate() API function. + * + * The configUSE_TIMERS configuration constant must be set to 1 for + * xTimerDelete() to be available. + * + * @param xTimer The handle of the timer being deleted. + * + * @param xTicksToWait Specifies the time, in ticks, that the calling task should + * be held in the Blocked state to wait for the delete command to be + * successfully sent to the timer command queue, should the queue already be + * full when xTimerDelete() was called. xTicksToWait is ignored if xTimerDelete() + * is called before the scheduler is started. + * + * @return pdFAIL will be returned if the delete command could not be sent to + * the timer command queue even after xTicksToWait ticks had passed. pdPASS will + * be returned if the command was successfully sent to the timer command queue. + * When the command is actually processed will depend on the priority of the + * timer service/daemon task relative to other tasks in the system. The timer + * service/daemon task priority is set by the configTIMER_TASK_PRIORITY + * configuration constant. + * + * Example usage: + * + * See the xTimerChangePeriod() API function example usage scenario. + */ +#define xTimerDelete( xTimer, xTicksToWait ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_DELETE, 0U, NULL, ( xTicksToWait ) ) + +/** + * BaseType_t xTimerReset( TimerHandle_t xTimer, TickType_t xTicksToWait ); + * + * Timer functionality is provided by a timer service/daemon task. Many of the + * public FreeRTOS timer API functions send commands to the timer service task + * through a queue called the timer command queue. The timer command queue is + * private to the kernel itself and is not directly accessible to application + * code. The length of the timer command queue is set by the + * configTIMER_QUEUE_LENGTH configuration constant. + * + * xTimerReset() re-starts a timer that was previously created using the + * xTimerCreate() API function. If the timer had already been started and was + * already in the active state, then xTimerReset() will cause the timer to + * re-evaluate its expiry time so that it is relative to when xTimerReset() was + * called. If the timer was in the dormant state then xTimerReset() has + * equivalent functionality to the xTimerStart() API function. + * + * Resetting a timer ensures the timer is in the active state. If the timer + * is not stopped, deleted, or reset in the mean time, the callback function + * associated with the timer will get called 'n' ticks after xTimerReset() was + * called, where 'n' is the timers defined period. + * + * It is valid to call xTimerReset() before the scheduler has been started, but + * when this is done the timer will not actually start until the scheduler is + * started, and the timers expiry time will be relative to when the scheduler is + * started, not relative to when xTimerReset() was called. + * + * The configUSE_TIMERS configuration constant must be set to 1 for xTimerReset() + * to be available. + * + * @param xTimer The handle of the timer being reset/started/restarted. + * + * @param xTicksToWait Specifies the time, in ticks, that the calling task should + * be held in the Blocked state to wait for the reset command to be successfully + * sent to the timer command queue, should the queue already be full when + * xTimerReset() was called. xTicksToWait is ignored if xTimerReset() is called + * before the scheduler is started. + * + * @return pdFAIL will be returned if the reset command could not be sent to + * the timer command queue even after xTicksToWait ticks had passed. pdPASS will + * be returned if the command was successfully sent to the timer command queue. + * When the command is actually processed will depend on the priority of the + * timer service/daemon task relative to other tasks in the system, although the + * timers expiry time is relative to when xTimerStart() is actually called. The + * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY + * configuration constant. + * + * Example usage: + * @verbatim + * // When a key is pressed, an LCD back-light is switched on. If 5 seconds pass + * // without a key being pressed, then the LCD back-light is switched off. In + * // this case, the timer is a one-shot timer. + * + * TimerHandle_t xBacklightTimer = NULL; + * + * // The callback function assigned to the one-shot timer. In this case the + * // parameter is not used. + * void vBacklightTimerCallback( TimerHandle_t pxTimer ) + * { + * // The timer expired, therefore 5 seconds must have passed since a key + * // was pressed. Switch off the LCD back-light. + * vSetBacklightState( BACKLIGHT_OFF ); + * } + * + * // The key press event handler. + * void vKeyPressEventHandler( char cKey ) + * { + * // Ensure the LCD back-light is on, then reset the timer that is + * // responsible for turning the back-light off after 5 seconds of + * // key inactivity. Wait 10 ticks for the command to be successfully sent + * // if it cannot be sent immediately. + * vSetBacklightState( BACKLIGHT_ON ); + * if( xTimerReset( xBacklightTimer, 100 ) != pdPASS ) + * { + * // The reset command was not executed successfully. Take appropriate + * // action here. + * } + * + * // Perform the rest of the key processing here. + * } + * + * void main( void ) + * { + * int32_t x; + * + * // Create then start the one-shot timer that is responsible for turning + * // the back-light off if no keys are pressed within a 5 second period. + * xBacklightTimer = xTimerCreate( "BacklightTimer", // Just a text name, not used by the kernel. + * ( 5000 / portTICK_PERIOD_MS), // The timer period in ticks. + * pdFALSE, // The timer is a one-shot timer. + * 0, // The id is not used by the callback so can take any value. + * vBacklightTimerCallback // The callback function that switches the LCD back-light off. + * ); + * + * if( xBacklightTimer == NULL ) + * { + * // The timer was not created. + * } + * else + * { + * // Start the timer. No block time is specified, and even if one was + * // it would be ignored because the scheduler has not yet been + * // started. + * if( xTimerStart( xBacklightTimer, 0 ) != pdPASS ) + * { + * // The timer could not be set into the Active state. + * } + * } + * + * // ... + * // Create tasks here. + * // ... + * + * // Starting the scheduler will start the timer running as it has already + * // been set into the active state. + * vTaskStartScheduler(); + * + * // Should not reach here. + * for( ;; ); + * } + * @endverbatim + */ +#define xTimerReset( xTimer, xTicksToWait ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) ) + +/** + * BaseType_t xTimerStartFromISR( TimerHandle_t xTimer, + * BaseType_t *pxHigherPriorityTaskWoken ); + * + * A version of xTimerStart() that can be called from an interrupt service + * routine. + * + * @param xTimer The handle of the timer being started/restarted. + * + * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most + * of its time in the Blocked state, waiting for messages to arrive on the timer + * command queue. Calling xTimerStartFromISR() writes a message to the timer + * command queue, so has the potential to transition the timer service/daemon + * task out of the Blocked state. If calling xTimerStartFromISR() causes the + * timer service/daemon task to leave the Blocked state, and the timer service/ + * daemon task has a priority equal to or greater than the currently executing + * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will + * get set to pdTRUE internally within the xTimerStartFromISR() function. If + * xTimerStartFromISR() sets this value to pdTRUE then a context switch should + * be performed before the interrupt exits. + * + * @return pdFAIL will be returned if the start command could not be sent to + * the timer command queue. pdPASS will be returned if the command was + * successfully sent to the timer command queue. When the command is actually + * processed will depend on the priority of the timer service/daemon task + * relative to other tasks in the system, although the timers expiry time is + * relative to when xTimerStartFromISR() is actually called. The timer + * service/daemon task priority is set by the configTIMER_TASK_PRIORITY + * configuration constant. + * + * Example usage: + * @verbatim + * // This scenario assumes xBacklightTimer has already been created. When a + * // key is pressed, an LCD back-light is switched on. If 5 seconds pass + * // without a key being pressed, then the LCD back-light is switched off. In + * // this case, the timer is a one-shot timer, and unlike the example given for + * // the xTimerReset() function, the key press event handler is an interrupt + * // service routine. + * + * // The callback function assigned to the one-shot timer. In this case the + * // parameter is not used. + * void vBacklightTimerCallback( TimerHandle_t pxTimer ) + * { + * // The timer expired, therefore 5 seconds must have passed since a key + * // was pressed. Switch off the LCD back-light. + * vSetBacklightState( BACKLIGHT_OFF ); + * } + * + * // The key press interrupt service routine. + * void vKeyPressEventInterruptHandler( void ) + * { + * BaseType_t xHigherPriorityTaskWoken = pdFALSE; + * + * // Ensure the LCD back-light is on, then restart the timer that is + * // responsible for turning the back-light off after 5 seconds of + * // key inactivity. This is an interrupt service routine so can only + * // call FreeRTOS API functions that end in "FromISR". + * vSetBacklightState( BACKLIGHT_ON ); + * + * // xTimerStartFromISR() or xTimerResetFromISR() could be called here + * // as both cause the timer to re-calculate its expiry time. + * // xHigherPriorityTaskWoken was initialised to pdFALSE when it was + * // declared (in this function). + * if( xTimerStartFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS ) + * { + * // The start command was not executed successfully. Take appropriate + * // action here. + * } + * + * // Perform the rest of the key processing here. + * + * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch + * // should be performed. The syntax required to perform a context switch + * // from inside an ISR varies from port to port, and from compiler to + * // compiler. Inspect the demos for the port you are using to find the + * // actual syntax required. + * if( xHigherPriorityTaskWoken != pdFALSE ) + * { + * // Call the interrupt safe yield function here (actual function + * // depends on the FreeRTOS port being used). + * } + * } + * @endverbatim + */ +#define xTimerStartFromISR( xTimer, pxHigherPriorityTaskWoken ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U ) + +/** + * BaseType_t xTimerStopFromISR( TimerHandle_t xTimer, + * BaseType_t *pxHigherPriorityTaskWoken ); + * + * A version of xTimerStop() that can be called from an interrupt service + * routine. + * + * @param xTimer The handle of the timer being stopped. + * + * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most + * of its time in the Blocked state, waiting for messages to arrive on the timer + * command queue. Calling xTimerStopFromISR() writes a message to the timer + * command queue, so has the potential to transition the timer service/daemon + * task out of the Blocked state. If calling xTimerStopFromISR() causes the + * timer service/daemon task to leave the Blocked state, and the timer service/ + * daemon task has a priority equal to or greater than the currently executing + * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will + * get set to pdTRUE internally within the xTimerStopFromISR() function. If + * xTimerStopFromISR() sets this value to pdTRUE then a context switch should + * be performed before the interrupt exits. + * + * @return pdFAIL will be returned if the stop command could not be sent to + * the timer command queue. pdPASS will be returned if the command was + * successfully sent to the timer command queue. When the command is actually + * processed will depend on the priority of the timer service/daemon task + * relative to other tasks in the system. The timer service/daemon task + * priority is set by the configTIMER_TASK_PRIORITY configuration constant. + * + * Example usage: + * @verbatim + * // This scenario assumes xTimer has already been created and started. When + * // an interrupt occurs, the timer should be simply stopped. + * + * // The interrupt service routine that stops the timer. + * void vAnExampleInterruptServiceRoutine( void ) + * { + * BaseType_t xHigherPriorityTaskWoken = pdFALSE; + * + * // The interrupt has occurred - simply stop the timer. + * // xHigherPriorityTaskWoken was set to pdFALSE where it was defined + * // (within this function). As this is an interrupt service routine, only + * // FreeRTOS API functions that end in "FromISR" can be used. + * if( xTimerStopFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS ) + * { + * // The stop command was not executed successfully. Take appropriate + * // action here. + * } + * + * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch + * // should be performed. The syntax required to perform a context switch + * // from inside an ISR varies from port to port, and from compiler to + * // compiler. Inspect the demos for the port you are using to find the + * // actual syntax required. + * if( xHigherPriorityTaskWoken != pdFALSE ) + * { + * // Call the interrupt safe yield function here (actual function + * // depends on the FreeRTOS port being used). + * } + * } + * @endverbatim + */ +#define xTimerStopFromISR( xTimer, pxHigherPriorityTaskWoken ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP_FROM_ISR, 0, ( pxHigherPriorityTaskWoken ), 0U ) + +/** + * BaseType_t xTimerChangePeriodFromISR( TimerHandle_t xTimer, + * TickType_t xNewPeriod, + * BaseType_t *pxHigherPriorityTaskWoken ); + * + * A version of xTimerChangePeriod() that can be called from an interrupt + * service routine. + * + * @param xTimer The handle of the timer that is having its period changed. + * + * @param xNewPeriod The new period for xTimer. Timer periods are specified in + * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time + * that has been specified in milliseconds. For example, if the timer must + * expire after 100 ticks, then xNewPeriod should be set to 100. Alternatively, + * if the timer must expire after 500ms, then xNewPeriod can be set to + * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than + * or equal to 1000. + * + * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most + * of its time in the Blocked state, waiting for messages to arrive on the timer + * command queue. Calling xTimerChangePeriodFromISR() writes a message to the + * timer command queue, so has the potential to transition the timer service/ + * daemon task out of the Blocked state. If calling xTimerChangePeriodFromISR() + * causes the timer service/daemon task to leave the Blocked state, and the + * timer service/daemon task has a priority equal to or greater than the + * currently executing task (the task that was interrupted), then + * *pxHigherPriorityTaskWoken will get set to pdTRUE internally within the + * xTimerChangePeriodFromISR() function. If xTimerChangePeriodFromISR() sets + * this value to pdTRUE then a context switch should be performed before the + * interrupt exits. + * + * @return pdFAIL will be returned if the command to change the timers period + * could not be sent to the timer command queue. pdPASS will be returned if the + * command was successfully sent to the timer command queue. When the command + * is actually processed will depend on the priority of the timer service/daemon + * task relative to other tasks in the system. The timer service/daemon task + * priority is set by the configTIMER_TASK_PRIORITY configuration constant. + * + * Example usage: + * @verbatim + * // This scenario assumes xTimer has already been created and started. When + * // an interrupt occurs, the period of xTimer should be changed to 500ms. + * + * // The interrupt service routine that changes the period of xTimer. + * void vAnExampleInterruptServiceRoutine( void ) + * { + * BaseType_t xHigherPriorityTaskWoken = pdFALSE; + * + * // The interrupt has occurred - change the period of xTimer to 500ms. + * // xHigherPriorityTaskWoken was set to pdFALSE where it was defined + * // (within this function). As this is an interrupt service routine, only + * // FreeRTOS API functions that end in "FromISR" can be used. + * if( xTimerChangePeriodFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS ) + * { + * // The command to change the timers period was not executed + * // successfully. Take appropriate action here. + * } + * + * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch + * // should be performed. The syntax required to perform a context switch + * // from inside an ISR varies from port to port, and from compiler to + * // compiler. Inspect the demos for the port you are using to find the + * // actual syntax required. + * if( xHigherPriorityTaskWoken != pdFALSE ) + * { + * // Call the interrupt safe yield function here (actual function + * // depends on the FreeRTOS port being used). + * } + * } + * @endverbatim + */ +#define xTimerChangePeriodFromISR( xTimer, xNewPeriod, pxHigherPriorityTaskWoken ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD_FROM_ISR, ( xNewPeriod ), ( pxHigherPriorityTaskWoken ), 0U ) + +/** + * BaseType_t xTimerResetFromISR( TimerHandle_t xTimer, + * BaseType_t *pxHigherPriorityTaskWoken ); + * + * A version of xTimerReset() that can be called from an interrupt service + * routine. + * + * @param xTimer The handle of the timer that is to be started, reset, or + * restarted. + * + * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most + * of its time in the Blocked state, waiting for messages to arrive on the timer + * command queue. Calling xTimerResetFromISR() writes a message to the timer + * command queue, so has the potential to transition the timer service/daemon + * task out of the Blocked state. If calling xTimerResetFromISR() causes the + * timer service/daemon task to leave the Blocked state, and the timer service/ + * daemon task has a priority equal to or greater than the currently executing + * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will + * get set to pdTRUE internally within the xTimerResetFromISR() function. If + * xTimerResetFromISR() sets this value to pdTRUE then a context switch should + * be performed before the interrupt exits. + * + * @return pdFAIL will be returned if the reset command could not be sent to + * the timer command queue. pdPASS will be returned if the command was + * successfully sent to the timer command queue. When the command is actually + * processed will depend on the priority of the timer service/daemon task + * relative to other tasks in the system, although the timers expiry time is + * relative to when xTimerResetFromISR() is actually called. The timer service/daemon + * task priority is set by the configTIMER_TASK_PRIORITY configuration constant. + * + * Example usage: + * @verbatim + * // This scenario assumes xBacklightTimer has already been created. When a + * // key is pressed, an LCD back-light is switched on. If 5 seconds pass + * // without a key being pressed, then the LCD back-light is switched off. In + * // this case, the timer is a one-shot timer, and unlike the example given for + * // the xTimerReset() function, the key press event handler is an interrupt + * // service routine. + * + * // The callback function assigned to the one-shot timer. In this case the + * // parameter is not used. + * void vBacklightTimerCallback( TimerHandle_t pxTimer ) + * { + * // The timer expired, therefore 5 seconds must have passed since a key + * // was pressed. Switch off the LCD back-light. + * vSetBacklightState( BACKLIGHT_OFF ); + * } + * + * // The key press interrupt service routine. + * void vKeyPressEventInterruptHandler( void ) + * { + * BaseType_t xHigherPriorityTaskWoken = pdFALSE; + * + * // Ensure the LCD back-light is on, then reset the timer that is + * // responsible for turning the back-light off after 5 seconds of + * // key inactivity. This is an interrupt service routine so can only + * // call FreeRTOS API functions that end in "FromISR". + * vSetBacklightState( BACKLIGHT_ON ); + * + * // xTimerStartFromISR() or xTimerResetFromISR() could be called here + * // as both cause the timer to re-calculate its expiry time. + * // xHigherPriorityTaskWoken was initialised to pdFALSE when it was + * // declared (in this function). + * if( xTimerResetFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS ) + * { + * // The reset command was not executed successfully. Take appropriate + * // action here. + * } + * + * // Perform the rest of the key processing here. + * + * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch + * // should be performed. The syntax required to perform a context switch + * // from inside an ISR varies from port to port, and from compiler to + * // compiler. Inspect the demos for the port you are using to find the + * // actual syntax required. + * if( xHigherPriorityTaskWoken != pdFALSE ) + * { + * // Call the interrupt safe yield function here (actual function + * // depends on the FreeRTOS port being used). + * } + * } + * @endverbatim + */ +#define xTimerResetFromISR( xTimer, pxHigherPriorityTaskWoken ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U ) + + +/** + * BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, + * void *pvParameter1, + * uint32_t ulParameter2, + * BaseType_t *pxHigherPriorityTaskWoken ); + * + * + * Used from application interrupt service routines to defer the execution of a + * function to the RTOS daemon task (the timer service task, hence this function + * is implemented in timers.c and is prefixed with 'Timer'). + * + * Ideally an interrupt service routine (ISR) is kept as short as possible, but + * sometimes an ISR either has a lot of processing to do, or needs to perform + * processing that is not deterministic. In these cases + * xTimerPendFunctionCallFromISR() can be used to defer processing of a function + * to the RTOS daemon task. + * + * A mechanism is provided that allows the interrupt to return directly to the + * task that will subsequently execute the pended callback function. This + * allows the callback function to execute contiguously in time with the + * interrupt - just as if the callback had executed in the interrupt itself. + * + * @param xFunctionToPend The function to execute from the timer service/ + * daemon task. The function must conform to the PendedFunction_t + * prototype. + * + * @param pvParameter1 The value of the callback function's first parameter. + * The parameter has a void * type to allow it to be used to pass any type. + * For example, unsigned longs can be cast to a void *, or the void * can be + * used to point to a structure. + * + * @param ulParameter2 The value of the callback function's second parameter. + * + * @param pxHigherPriorityTaskWoken As mentioned above, calling this function + * will result in a message being sent to the timer daemon task. If the + * priority of the timer daemon task (which is set using + * configTIMER_TASK_PRIORITY in FreeRTOSConfig.h) is higher than the priority of + * the currently running task (the task the interrupt interrupted) then + * *pxHigherPriorityTaskWoken will be set to pdTRUE within + * xTimerPendFunctionCallFromISR(), indicating that a context switch should be + * requested before the interrupt exits. For that reason + * *pxHigherPriorityTaskWoken must be initialised to pdFALSE. See the + * example code below. + * + * @return pdPASS is returned if the message was successfully sent to the + * timer daemon task, otherwise pdFALSE is returned. + * + * Example usage: + * @verbatim + * + * // The callback function that will execute in the context of the daemon task. + * // Note callback functions must all use this same prototype. + * void vProcessInterface( void *pvParameter1, uint32_t ulParameter2 ) + * { + * BaseType_t xInterfaceToService; + * + * // The interface that requires servicing is passed in the second + * // parameter. The first parameter is not used in this case. + * xInterfaceToService = ( BaseType_t ) ulParameter2; + * + * // ...Perform the processing here... + * } + * + * // An ISR that receives data packets from multiple interfaces + * void vAnISR( void ) + * { + * BaseType_t xInterfaceToService, xHigherPriorityTaskWoken; + * + * // Query the hardware to determine which interface needs processing. + * xInterfaceToService = prvCheckInterfaces(); + * + * // The actual processing is to be deferred to a task. Request the + * // vProcessInterface() callback function is executed, passing in the + * // number of the interface that needs processing. The interface to + * // service is passed in the second parameter. The first parameter is + * // not used in this case. + * xHigherPriorityTaskWoken = pdFALSE; + * xTimerPendFunctionCallFromISR( vProcessInterface, NULL, ( uint32_t ) xInterfaceToService, &xHigherPriorityTaskWoken ); + * + * // If xHigherPriorityTaskWoken is now set to pdTRUE then a context + * // switch should be requested. The macro used is port specific and will + * // be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to + * // the documentation page for the port being used. + * portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + * + * } + * @endverbatim + */ +BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, + void * pvParameter1, + uint32_t ulParameter2, + BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/** + * BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, + * void *pvParameter1, + * uint32_t ulParameter2, + * TickType_t xTicksToWait ); + * + * + * Used to defer the execution of a function to the RTOS daemon task (the timer + * service task, hence this function is implemented in timers.c and is prefixed + * with 'Timer'). + * + * @param xFunctionToPend The function to execute from the timer service/ + * daemon task. The function must conform to the PendedFunction_t + * prototype. + * + * @param pvParameter1 The value of the callback function's first parameter. + * The parameter has a void * type to allow it to be used to pass any type. + * For example, unsigned longs can be cast to a void *, or the void * can be + * used to point to a structure. + * + * @param ulParameter2 The value of the callback function's second parameter. + * + * @param xTicksToWait Calling this function will result in a message being + * sent to the timer daemon task on a queue. xTicksToWait is the amount of + * time the calling task should remain in the Blocked state (so not using any + * processing time) for space to become available on the timer queue if the + * queue is found to be full. + * + * @return pdPASS is returned if the message was successfully sent to the + * timer daemon task, otherwise pdFALSE is returned. + * + */ +BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, + void * pvParameter1, + uint32_t ulParameter2, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * const char * const pcTimerGetName( TimerHandle_t xTimer ); + * + * Returns the name that was assigned to a timer when the timer was created. + * + * @param xTimer The handle of the timer being queried. + * + * @return The name assigned to the timer specified by the xTimer parameter. + */ +const char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + +/** + * void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ); + * + * Updates a timer to be either an auto-reload timer, in which case the timer + * automatically resets itself each time it expires, or a one-shot timer, in + * which case the timer will only expire once unless it is manually restarted. + * + * @param xTimer The handle of the timer being updated. + * + * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will + * expire repeatedly with a frequency set by the timer's period (see the + * xTimerPeriodInTicks parameter of the xTimerCreate() API function). If + * uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and + * enter the dormant state after it expires. + */ +void vTimerSetReloadMode( TimerHandle_t xTimer, + const UBaseType_t uxAutoReload ) PRIVILEGED_FUNCTION; + +/** + * UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer ); + * + * Queries a timer to determine if it is an auto-reload timer, in which case the timer + * automatically resets itself each time it expires, or a one-shot timer, in + * which case the timer will only expire once unless it is manually restarted. + * + * @param xTimer The handle of the timer being queried. + * + * @return If the timer is an auto-reload timer then pdTRUE is returned, otherwise + * pdFALSE is returned. + */ +UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; + +/** + * TickType_t xTimerGetPeriod( TimerHandle_t xTimer ); + * + * Returns the period of a timer. + * + * @param xTimer The handle of the timer being queried. + * + * @return The period of the timer in ticks. + */ +TickType_t xTimerGetPeriod( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; + +/** + * TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ); + * + * Returns the time in ticks at which the timer will expire. If this is less + * than the current tick count then the expiry time has overflowed from the + * current time. + * + * @param xTimer The handle of the timer being queried. + * + * @return If the timer is running then the time in ticks at which the timer + * will next expire is returned. If the timer is not running then the return + * value is undefined. + */ +TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; + +/* + * Functions beyond this part are not part of the public API and are intended + * for use by the kernel only. + */ +BaseType_t xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION; +BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, + const BaseType_t xCommandID, + const TickType_t xOptionalValue, + BaseType_t * const pxHigherPriorityTaskWoken, + const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +#if ( configUSE_TRACE_FACILITY == 1 ) + void vTimerSetTimerNumber( TimerHandle_t xTimer, + UBaseType_t uxTimerNumber ) PRIVILEGED_FUNCTION; + UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; +#endif + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + +/** + * task.h + * @code{c} + * void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, StackType_t ** ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize ) + * @endcode + * + * This function is used to provide a statically allocated block of memory to FreeRTOS to hold the Timer Task TCB. This function is required when + * configSUPPORT_STATIC_ALLOCATION is set. For more information see this URI: https://www.FreeRTOS.org/a00110.html#configSUPPORT_STATIC_ALLOCATION + * + * @param ppxTimerTaskTCBBuffer A handle to a statically allocated TCB buffer + * @param ppxTimerTaskStackBuffer A handle to a statically allocated Stack buffer for thie idle task + * @param pulTimerTaskStackSize A pointer to the number of elements that will fit in the allocated stack buffer + */ + void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, + StackType_t ** ppxTimerTaskStackBuffer, + uint32_t * pulTimerTaskStackSize ); + +#endif + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ +#endif /* TIMERS_H */ diff --git a/hw-libs/freertos/list.c b/hw-libs/freertos/list.c new file mode 100644 index 000000000..42a2e0989 --- /dev/null +++ b/hw-libs/freertos/list.c @@ -0,0 +1,215 @@ +/* + * FreeRTOS Kernel V10.4.6 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#include "FreeRTOS.h" +#include "list.h" + +/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified + * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be + * defined for the header files above, but not in this file, in order to + * generate the correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */ + +/*----------------------------------------------------------- +* PUBLIC LIST API documented in list.h +*----------------------------------------------------------*/ + +void vListInitialise( List_t * const pxList ) +{ + /* The list structure contains a list item which is used to mark the + * end of the list. To initialise the list the list end is inserted + * as the only list entry. */ + pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + + /* The list end value is the highest possible value in the list to + * ensure it remains at the end of the list. */ + pxList->xListEnd.xItemValue = portMAX_DELAY; + + /* The list end next and previous pointers point to itself so we know + * when the list is empty. */ + pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + + pxList->uxNumberOfItems = ( UBaseType_t ) 0U; + + /* Write known values into the list if + * configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ); + listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ); +} +/*-----------------------------------------------------------*/ + +void vListInitialiseItem( ListItem_t * const pxItem ) +{ + /* Make sure the list item is not recorded as being on a list. */ + pxItem->pxContainer = NULL; + + /* Write known values into the list item if + * configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); + listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); +} +/*-----------------------------------------------------------*/ + +void vListInsertEnd( List_t * const pxList, + ListItem_t * const pxNewListItem ) +{ + ListItem_t * const pxIndex = pxList->pxIndex; + + /* Only effective when configASSERT() is also defined, these tests may catch + * the list data structures being overwritten in memory. They will not catch + * data errors caused by incorrect configuration or use of FreeRTOS. */ + listTEST_LIST_INTEGRITY( pxList ); + listTEST_LIST_ITEM_INTEGRITY( pxNewListItem ); + + /* Insert a new list item into pxList, but rather than sort the list, + * makes the new list item the last item to be removed by a call to + * listGET_OWNER_OF_NEXT_ENTRY(). */ + pxNewListItem->pxNext = pxIndex; + pxNewListItem->pxPrevious = pxIndex->pxPrevious; + + /* Only used during decision coverage testing. */ + mtCOVERAGE_TEST_DELAY(); + + pxIndex->pxPrevious->pxNext = pxNewListItem; + pxIndex->pxPrevious = pxNewListItem; + + /* Remember which list the item is in. */ + pxNewListItem->pxContainer = pxList; + + ( pxList->uxNumberOfItems )++; +} +/*-----------------------------------------------------------*/ + +void vListInsert( List_t * const pxList, + ListItem_t * const pxNewListItem ) +{ + ListItem_t * pxIterator; + const TickType_t xValueOfInsertion = pxNewListItem->xItemValue; + + /* Only effective when configASSERT() is also defined, these tests may catch + * the list data structures being overwritten in memory. They will not catch + * data errors caused by incorrect configuration or use of FreeRTOS. */ + listTEST_LIST_INTEGRITY( pxList ); + listTEST_LIST_ITEM_INTEGRITY( pxNewListItem ); + + /* Insert the new list item into the list, sorted in xItemValue order. + * + * If the list already contains a list item with the same item value then the + * new list item should be placed after it. This ensures that TCBs which are + * stored in ready lists (all of which have the same xItemValue value) get a + * share of the CPU. However, if the xItemValue is the same as the back marker + * the iteration loop below will not end. Therefore the value is checked + * first, and the algorithm slightly modified if necessary. */ + if( xValueOfInsertion == portMAX_DELAY ) + { + pxIterator = pxList->xListEnd.pxPrevious; + } + else + { + /* *** NOTE *********************************************************** + * If you find your application is crashing here then likely causes are + * listed below. In addition see https://www.FreeRTOS.org/FAQHelp.html for + * more tips, and ensure configASSERT() is defined! + * https://www.FreeRTOS.org/a00110.html#configASSERT + * + * 1) Stack overflow - + * see https://www.FreeRTOS.org/Stacks-and-stack-overflow-checking.html + * 2) Incorrect interrupt priority assignment, especially on Cortex-M + * parts where numerically high priority values denote low actual + * interrupt priorities, which can seem counter intuitive. See + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html and the definition + * of configMAX_SYSCALL_INTERRUPT_PRIORITY on + * https://www.FreeRTOS.org/a00110.html + * 3) Calling an API function from within a critical section or when + * the scheduler is suspended, or calling an API function that does + * not end in "FromISR" from an interrupt. + * 4) Using a queue or semaphore before it has been initialised or + * before the scheduler has been started (are interrupts firing + * before vTaskStartScheduler() has been called?). + * 5) If the FreeRTOS port supports interrupt nesting then ensure that + * the priority of the tick interrupt is at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + **********************************************************************/ + + for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */ + { + /* There is nothing to do here, just iterating to the wanted + * insertion position. */ + } + } + + pxNewListItem->pxNext = pxIterator->pxNext; + pxNewListItem->pxNext->pxPrevious = pxNewListItem; + pxNewListItem->pxPrevious = pxIterator; + pxIterator->pxNext = pxNewListItem; + + /* Remember which list the item is in. This allows fast removal of the + * item later. */ + pxNewListItem->pxContainer = pxList; + + ( pxList->uxNumberOfItems )++; +} +/*-----------------------------------------------------------*/ + +UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) +{ +/* The list item knows which list it is in. Obtain the list from the list + * item. */ + List_t * const pxList = pxItemToRemove->pxContainer; + + pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; + pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; + + /* Only used during decision coverage testing. */ + mtCOVERAGE_TEST_DELAY(); + + /* Make sure the index is left pointing to a valid item. */ + if( pxList->pxIndex == pxItemToRemove ) + { + pxList->pxIndex = pxItemToRemove->pxPrevious; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + pxItemToRemove->pxContainer = NULL; + ( pxList->uxNumberOfItems )--; + + return pxList->uxNumberOfItems; +} +/*-----------------------------------------------------------*/ diff --git a/hw-libs/freertos/portable/GCC/ARM_CM4F/port.c b/hw-libs/freertos/portable/GCC/ARM_CM4F/port.c new file mode 100644 index 000000000..0f7929c3a --- /dev/null +++ b/hw-libs/freertos/portable/GCC/ARM_CM4F/port.c @@ -0,0 +1,785 @@ +/* + * FreeRTOS Kernel V10.4.6 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM4F port. +*----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef __VFP_FP__ + #error This port can only be used when the project options are configured to enable hardware floating point support. +#endif + +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#else + +/* The way the SysTick is clocked is not modified in case it is not the same + * as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 0 ) +#endif + +/* Constants required to manipulate the core. Registers first... */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +/* ...then bits in the registers. */ +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) + +/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7 + * r0p1 port. */ +#define portCPUID ( *( ( volatile uint32_t * ) 0xE000ed00 ) ) +#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL ) +#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL ) + +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ +#define portVECTACTIVE_MASK ( 0xFFUL ) + +/* Constants required to manipulate the VFP. */ +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */ +#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) +#define portINITIAL_EXC_RETURN ( 0xfffffffd ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* For strict compliance with the Cortex-M spec the task start address should + * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have + * occurred while the SysTick counter is stopped during tickless idle + * calculations. */ +#define portMISSED_COUNTS_FACTOR ( 45UL ) + +/* Let the user override the pre-loading of the initial LR with the address of + * prvTaskExitError() in case it messes up unwinding of the stack in the + * debugger. */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortPendSVHandler( void ) __attribute__( ( naked ) ); +void xPortSysTickHandler( void ); +void vPortSVCHandler( void ) __attribute__( ( naked ) ); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +static void prvPortStartFirstTask( void ) __attribute__( ( naked ) ); + +/* + * Function to enable the VFP. + */ +static void vPortEnableVFP( void ) __attribute__( ( naked ) ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* Each task maintains its own interrupt status in the critical nesting + * variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* + * The number of SysTick increments that make up one tick period. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Compensate for the CPU cycles that pass while the SysTick is stopped (low + * power functionality only. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16; +#endif /* configASSERT_DEFINED */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + + /* Offset added to account for the way the MCU uses the stack on entry/exit + * of interrupts, and to ensure alignment. */ + pxTopOfStack--; + + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + + /* Save code space by skipping register initialisation. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + + /* A save method is being used that requires each task to maintain its + * own exec return value. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; + + pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being defined + * but never called. ulDummy is used purely to quieten other warnings + * about code appearing after this function is called - making ulDummy + * volatile makes the compiler think the function could return and + * therefore not output an 'unreachable code' warning for code that appears + * after it. */ + } +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler( void ) +{ + __asm volatile ( + " ldr r3, pxCurrentTCBConst2 \n"/* Restore the context. */ + " ldr r1, [r3] \n"/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */ + " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */ + " ldmia r0!, {r4-r11, r14} \n"/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */ + " msr psp, r0 \n"/* Restore the task stack pointer. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" + " bx r14 \n" + " \n" + " .align 4 \n" + "pxCurrentTCBConst2: .word pxCurrentTCB \n" + ); +} +/*-----------------------------------------------------------*/ + +static void prvPortStartFirstTask( void ) +{ + /* Start the first task. This also clears the bit that indicates the FPU is + * in use in case the FPU was used before the scheduler was started - which + * would otherwise result in the unnecessary leaving of space in the SVC stack + * for lazy saving of FPU registers. */ + __asm volatile ( + " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n" + " ldr r0, [r0] \n" + " msr msp, r0 \n"/* Set the msp back to the start of the stack. */ + " mov r0, #0 \n"/* Clear the bit that indicates the FPU is in use, see comment above. */ + " msr control, r0 \n" + " cpsie i \n"/* Globally enable interrupts. */ + " cpsie f \n" + " dsb \n" + " isb \n" + " svc 0 \n"/* System call to start first task. */ + " nop \n" + " .ltorg \n" + ); +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + + /* This port can be used on all revisions of the Cortex-M7 core other than + * the r0p1 parts. r0p1 parts should use the port from the + * /source/portable/GCC/ARM_CM7/r0p1 directory. */ + configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); + configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); + + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint32_t ulOriginalPriority; + volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * Save the interrupt priority value that is about to be clobbered. */ + ulOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + * possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; + + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulMaxPRIGROUPValue--; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + #ifdef __NVIC_PRIO_BITS + { + /* Check the CMSIS configuration that defines the number of + * priority bits matches the number of priority bits actually queried + * from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS ); + } + #endif + + #ifdef configPRIO_BITS + { + /* Check the FreeRTOS configuration that defines the number of + * priority bits matches the number of priority bits actually queried + * from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); + } + #endif + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ulOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Ensure the VFP is enabled - it should be anyway. */ + vPortEnableVFP(); + + /* Lazy save always. */ + *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; + + /* Start the first task. */ + prvPortStartFirstTask(); + + /* Should never get here as the tasks will now be executing! Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimisation does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void xPortPendSVHandler( void ) +{ + /* This is a naked function. */ + + __asm volatile + ( + " mrs r0, psp \n" + " isb \n" + " \n" + " ldr r3, pxCurrentTCBConst \n"/* Get the location of the current TCB. */ + " ldr r2, [r3] \n" + " \n" + " tst r14, #0x10 \n"/* Is the task using the FPU context? If so, push high vfp registers. */ + " it eq \n" + " vstmdbeq r0!, {s16-s31} \n" + " \n" + " stmdb r0!, {r4-r11, r14} \n"/* Save the core registers. */ + " str r0, [r2] \n"/* Save the new top of stack into the first member of the TCB. */ + " \n" + " stmdb sp!, {r0, r3} \n" + " mov r0, %0 \n" + " msr basepri, r0 \n" + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" + " ldmia sp!, {r0, r3} \n" + " \n" + " ldr r1, [r3] \n"/* The first item in pxCurrentTCB is the task top of stack. */ + " ldr r0, [r1] \n" + " \n" + " ldmia r0!, {r4-r11, r14} \n"/* Pop the core registers. */ + " \n" + " tst r14, #0x10 \n"/* Is the task using the FPU context? If so, pop the high vfp registers too. */ + " it eq \n" + " vldmiaeq r0!, {s16-s31} \n" + " \n" + " msr psp, r0 \n" + " isb \n" + " \n" + #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */ + #if WORKAROUND_PMU_CM001 == 1 + " push { r14 } \n" + " pop { pc } \n" + #endif + #endif + " \n" + " bx r14 \n" + " \n" + " .align 4 \n" + "pxCurrentTCBConst: .word pxCurrentTCB \n" + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + /* The SysTick runs at the lowest interrupt priority, so when this interrupt + * executes all interrupts must be unmasked. There is therefore no need to + * save and then restore the interrupt mask value as its value is already + * known. */ + portDISABLE_INTERRUPTS(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* A context switch is required. Context switching is performed in + * the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portENABLE_INTERRUPTS(); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code will execute part way + * through one of the tick periods. */ + ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Restart from whatever is left in the count register to complete + * this tick period. */ + portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Reset the reload register to the value required for normal tick + * periods. */ + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Re-enable interrupts - see comments above the cpsid instruction() + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. see comments above + * __disable_interrupt() call above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT ); + + /* Determine if the SysTick clock has already counted to zero and + * been set back to the current reload value (the reload back being + * correct for the entire expected idle time) or if the SysTick is yet + * to count to zero (in which case an interrupt other than the SysTick + * must have brought the system out of sleep mode). */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt is already pending, and the SysTick count + * reloaded with ulReloadValue. Reset the + * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick + * period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long. */ + if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + * Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG + * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard + * value. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + vTaskStepTick( ulCompleteTickPeriods ); + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* #if configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); +} +/*-----------------------------------------------------------*/ + +/* This is a naked function. */ +static void vPortEnableVFP( void ) +{ + __asm volatile + ( + " ldr.w r0, =0xE000ED88 \n"/* The FPU enable bits are in the CPACR. */ + " ldr r1, [r0] \n" + " \n" + " orr r1, r1, #( 0xf << 20 ) \n"/* Enable CP10 and CP11 coprocessors, then save back. */ + " str r1, [r0] \n" + " bx r14 \n" + " .ltorg \n" + ); +} +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.FreeRTOS.org/FAQHelp.html */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* configASSERT_DEFINED */ diff --git a/hw-libs/freertos/portable/GCC/ARM_CM4F/portmacro.h b/hw-libs/freertos/portable/GCC/ARM_CM4F/portmacro.h new file mode 100644 index 000000000..615bb2a0d --- /dev/null +++ b/hw-libs/freertos/portable/GCC/ARM_CM4F/portmacro.h @@ -0,0 +1,245 @@ +/* + * FreeRTOS Kernel V10.4.6 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H + #define PORTMACRO_H + + #ifdef __cplusplus + extern "C" { + #endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + #define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/* Scheduler utilities. */ + #define portYIELD() \ + { \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + \ + /* Barriers are normally not required but do ensure the code is completely \ + * within the specified behaviour for the architecture. */ \ + __asm volatile ( "dsb" ::: "memory" ); \ + __asm volatile ( "isb" ); \ + } + + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) + #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) + #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 ) + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ + extern void vPortEnterCritical( void ); + extern void vPortExitCritical( void ); + #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) + #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() + #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo files + * (which build with all the ports) will build. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ + #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #endif + + #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Generic helper function. */ + __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint8_t ucReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ucReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + + #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/*-----------------------------------------------------------*/ + + #ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif + +/* portNOP() is not required by this port. */ + #define portNOP() + + #define portINLINE __inline + + #ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) + #endif + + portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) + { + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; + } + +/*-----------------------------------------------------------*/ + + portFORCE_INLINE static void vPortRaiseBASEPRI( void ) + { + uint32_t ulNewBASEPRI; + + __asm volatile + ( + " mov %0, %1 \n"\ + " msr basepri, %0 \n"\ + " isb \n"\ + " dsb \n"\ + : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); + } + +/*-----------------------------------------------------------*/ + + portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) + { + uint32_t ulOriginalBASEPRI, ulNewBASEPRI; + + __asm volatile + ( + " mrs %0, basepri \n"\ + " mov %1, %2 \n"\ + " msr basepri, %1 \n"\ + " isb \n"\ + " dsb \n"\ + : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); + + /* This return will not be reached but is necessary to prevent compiler + * warnings. */ + return ulOriginalBASEPRI; + } +/*-----------------------------------------------------------*/ + + portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) + { + __asm volatile + ( + " msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) + + #ifdef __cplusplus + } + #endif + +#endif /* PORTMACRO_H */ diff --git a/hw-libs/freertos/portable/GCC/ARM_CM7/ReadMe.txt b/hw-libs/freertos/portable/GCC/ARM_CM7/ReadMe.txt new file mode 100644 index 000000000..4cf25c5a4 --- /dev/null +++ b/hw-libs/freertos/portable/GCC/ARM_CM7/ReadMe.txt @@ -0,0 +1,18 @@ +There are two options for running FreeRTOS on ARM Cortex-M7 microcontrollers. +The best option depends on the revision of the ARM Cortex-M7 core in use. The +revision is specified by an 'r' number, and a 'p' number, so will look something +like 'r0p1'. Check the documentation for the microcontroller in use to find the +revision of the Cortex-M7 core used in that microcontroller. If in doubt, use +the FreeRTOS port provided specifically for r0p1 revisions, as that can be used +with all core revisions. + +The first option is to use the ARM Cortex-M4F port, and the second option is to +use the Cortex-M7 r0p1 port - the latter containing a minor errata workaround. + +If the revision of the ARM Cortex-M7 core is not r0p1 then either option can be +used, but it is recommended to use the FreeRTOS ARM Cortex-M4F port located in +the /FreeRTOS/Source/portable/GCC/ARM_CM4F directory. + +If the revision of the ARM Cortex-M7 core is r0p1 then use the FreeRTOS ARM +Cortex-M7 r0p1 port located in the /FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 +directory. \ No newline at end of file diff --git a/hw-libs/freertos/portable/GCC/ARM_CM7/r0p1/port.c b/hw-libs/freertos/portable/GCC/ARM_CM7/r0p1/port.c new file mode 100644 index 000000000..f7f733588 --- /dev/null +++ b/hw-libs/freertos/portable/GCC/ARM_CM7/r0p1/port.c @@ -0,0 +1,775 @@ +/* + * FreeRTOS Kernel V10.4.6 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM7 port. +*----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef __VFP_FP__ + #error This port can only be used when the project options are configured to enable hardware floating point support. +#endif + +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#else + +/* The way the SysTick is clocked is not modified in case it is not the same + * as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 0 ) +#endif + +/* Constants required to manipulate the core. Registers first... */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +/* ...then bits in the registers. */ +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) + +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ +#define portVECTACTIVE_MASK ( 0xFFUL ) + +/* Constants required to manipulate the VFP. */ +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */ +#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) +#define portINITIAL_EXC_RETURN ( 0xfffffffd ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* For strict compliance with the Cortex-M spec the task start address should + * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have + * occurred while the SysTick counter is stopped during tickless idle + * calculations. */ +#define portMISSED_COUNTS_FACTOR ( 45UL ) + +/* Let the user override the pre-loading of the initial LR with the address of + * prvTaskExitError() in case it messes up unwinding of the stack in the + * debugger. */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortPendSVHandler( void ) __attribute__( ( naked ) ); +void xPortSysTickHandler( void ); +void vPortSVCHandler( void ) __attribute__( ( naked ) ); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +static void prvPortStartFirstTask( void ) __attribute__( ( naked ) ); + +/* + * Function to enable the VFP. + */ +static void vPortEnableVFP( void ) __attribute__( ( naked ) ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* Each task maintains its own interrupt status in the critical nesting + * variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* + * The number of SysTick increments that make up one tick period. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Compensate for the CPU cycles that pass while the SysTick is stopped (low + * power functionality only. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16; +#endif /* configASSERT_DEFINED */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + + /* Offset added to account for the way the MCU uses the stack on entry/exit + * of interrupts, and to ensure alignment. */ + pxTopOfStack--; + + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + + /* Save code space by skipping register initialisation. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + + /* A save method is being used that requires each task to maintain its + * own exec return value. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; + + pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being defined + * but never called. ulDummy is used purely to quieten other warnings + * about code appearing after this function is called - making ulDummy + * volatile makes the compiler think the function could return and + * therefore not output an 'unreachable code' warning for code that appears + * after it. */ + } +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler( void ) +{ + __asm volatile ( + " ldr r3, pxCurrentTCBConst2 \n"/* Restore the context. */ + " ldr r1, [r3] \n"/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */ + " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */ + " ldmia r0!, {r4-r11, r14} \n"/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */ + " msr psp, r0 \n"/* Restore the task stack pointer. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" + " bx r14 \n" + " \n" + " .align 4 \n" + "pxCurrentTCBConst2: .word pxCurrentTCB \n" + ); +} +/*-----------------------------------------------------------*/ + +static void prvPortStartFirstTask( void ) +{ + /* Start the first task. This also clears the bit that indicates the FPU is + * in use in case the FPU was used before the scheduler was started - which + * would otherwise result in the unnecessary leaving of space in the SVC stack + * for lazy saving of FPU registers. */ + __asm volatile ( + " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n" + " ldr r0, [r0] \n" + " msr msp, r0 \n"/* Set the msp back to the start of the stack. */ + " mov r0, #0 \n"/* Clear the bit that indicates the FPU is in use, see comment above. */ + " msr control, r0 \n" + " cpsie i \n"/* Globally enable interrupts. */ + " cpsie f \n" + " dsb \n" + " isb \n" + " svc 0 \n"/* System call to start first task. */ + " nop \n" + " .ltorg \n" + ); +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint32_t ulOriginalPriority; + volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * Save the interrupt priority value that is about to be clobbered. */ + ulOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + * possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; + + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulMaxPRIGROUPValue--; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + #ifdef __NVIC_PRIO_BITS + { + /* Check the CMSIS configuration that defines the number of + * priority bits matches the number of priority bits actually queried + * from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS ); + } + #endif + + #ifdef configPRIO_BITS + { + /* Check the FreeRTOS configuration that defines the number of + * priority bits matches the number of priority bits actually queried + * from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); + } + #endif + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ulOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Ensure the VFP is enabled - it should be anyway. */ + vPortEnableVFP(); + + /* Lazy save always. */ + *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; + + /* Start the first task. */ + prvPortStartFirstTask(); + + /* Should never get here as the tasks will now be executing! Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimisation does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void xPortPendSVHandler( void ) +{ + /* This is a naked function. */ + + __asm volatile + ( + " mrs r0, psp \n" + " isb \n" + " \n" + " ldr r3, pxCurrentTCBConst \n"/* Get the location of the current TCB. */ + " ldr r2, [r3] \n" + " \n" + " tst r14, #0x10 \n"/* Is the task using the FPU context? If so, push high vfp registers. */ + " it eq \n" + " vstmdbeq r0!, {s16-s31} \n" + " \n" + " stmdb r0!, {r4-r11, r14} \n"/* Save the core registers. */ + " str r0, [r2] \n"/* Save the new top of stack into the first member of the TCB. */ + " \n" + " stmdb sp!, {r0, r3} \n" + " mov r0, %0 \n" + " cpsid i \n"/* Errata workaround. */ + " msr basepri, r0 \n" + " dsb \n" + " isb \n" + " cpsie i \n"/* Errata workaround. */ + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" + " ldmia sp!, {r0, r3} \n" + " \n" + " ldr r1, [r3] \n"/* The first item in pxCurrentTCB is the task top of stack. */ + " ldr r0, [r1] \n" + " \n" + " ldmia r0!, {r4-r11, r14} \n"/* Pop the core registers. */ + " \n" + " tst r14, #0x10 \n"/* Is the task using the FPU context? If so, pop the high vfp registers too. */ + " it eq \n" + " vldmiaeq r0!, {s16-s31} \n" + " \n" + " msr psp, r0 \n" + " isb \n" + " \n" + #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */ + #if WORKAROUND_PMU_CM001 == 1 + " push { r14 } \n" + " pop { pc } \n" + #endif + #endif + " \n" + " bx r14 \n" + " \n" + " .align 4 \n" + "pxCurrentTCBConst: .word pxCurrentTCB \n" + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + /* The SysTick runs at the lowest interrupt priority, so when this interrupt + * executes all interrupts must be unmasked. There is therefore no need to + * save and then restore the interrupt mask value as its value is already + * known. */ + portDISABLE_INTERRUPTS(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* A context switch is required. Context switching is performed in + * the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portENABLE_INTERRUPTS(); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code will execute part way + * through one of the tick periods. */ + ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Restart from whatever is left in the count register to complete + * this tick period. */ + portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Reset the reload register to the value required for normal tick + * periods. */ + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Re-enable interrupts - see comments above the cpsid instruction() + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. see comments above + * __disable_interrupt() call above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT ); + + /* Determine if the SysTick clock has already counted to zero and + * been set back to the current reload value (the reload back being + * correct for the entire expected idle time) or if the SysTick is yet + * to count to zero (in which case an interrupt other than the SysTick + * must have brought the system out of sleep mode). */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt is already pending, and the SysTick count + * reloaded with ulReloadValue. Reset the + * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick + * period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long. */ + if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + * Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG + * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard + * value. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + vTaskStepTick( ulCompleteTickPeriods ); + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* #if configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); +} +/*-----------------------------------------------------------*/ + +/* This is a naked function. */ +static void vPortEnableVFP( void ) +{ + __asm volatile + ( + " ldr.w r0, =0xE000ED88 \n"/* The FPU enable bits are in the CPACR. */ + " ldr r1, [r0] \n" + " \n" + " orr r1, r1, #( 0xf << 20 ) \n"/* Enable CP10 and CP11 coprocessors, then save back. */ + " str r1, [r0] \n" + " bx r14 \n" + " .ltorg \n" + ); +} +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.FreeRTOS.org/FAQHelp.html */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* configASSERT_DEFINED */ diff --git a/hw-libs/freertos/portable/GCC/ARM_CM7/r0p1/portmacro.h b/hw-libs/freertos/portable/GCC/ARM_CM7/r0p1/portmacro.h new file mode 100644 index 000000000..e304b100a --- /dev/null +++ b/hw-libs/freertos/portable/GCC/ARM_CM7/r0p1/portmacro.h @@ -0,0 +1,249 @@ +/* + * FreeRTOS Kernel V10.4.6 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H + #define PORTMACRO_H + + #ifdef __cplusplus + extern "C" { + #endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + #define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/* Scheduler utilities. */ + #define portYIELD() \ + { \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + \ + /* Barriers are normally not required but do ensure the code is completely \ + * within the specified behaviour for the architecture. */ \ + __asm volatile ( "dsb" ::: "memory" ); \ + __asm volatile ( "isb" ); \ + } + + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) + #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) + #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 ) + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ + extern void vPortEnterCritical( void ); + extern void vPortExitCritical( void ); + #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) + #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() + #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo files + * (which build with all the ports) will build. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ + #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #endif + + #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Generic helper function. */ + __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint8_t ucReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ucReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + + #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/*-----------------------------------------------------------*/ + + #ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif + +/* portNOP() is not required by this port. */ + #define portNOP() + + #define portINLINE __inline + + #ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) + #endif + + portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) + { + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; + } + +/*-----------------------------------------------------------*/ + + portFORCE_INLINE static void vPortRaiseBASEPRI( void ) + { + uint32_t ulNewBASEPRI; + + __asm volatile + ( + " mov %0, %1 \n"\ + " cpsid i \n"\ + " msr basepri, %0 \n"\ + " isb \n"\ + " dsb \n"\ + " cpsie i \n"\ + : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); + } + +/*-----------------------------------------------------------*/ + + portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) + { + uint32_t ulOriginalBASEPRI, ulNewBASEPRI; + + __asm volatile + ( + " mrs %0, basepri \n"\ + " mov %1, %2 \n"\ + " cpsid i \n"\ + " msr basepri, %1 \n"\ + " isb \n"\ + " dsb \n"\ + " cpsie i \n"\ + : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); + + /* This return will not be reached but is necessary to prevent compiler + * warnings. */ + return ulOriginalBASEPRI; + } +/*-----------------------------------------------------------*/ + + portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) + { + __asm volatile + ( + " msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) + + #ifdef __cplusplus + } + #endif + +#endif /* PORTMACRO_H */ diff --git a/hw-libs/freertos/portable/MemMang/heap_1.c b/hw-libs/freertos/portable/MemMang/heap_1.c new file mode 100644 index 000000000..f442caf25 --- /dev/null +++ b/hw-libs/freertos/portable/MemMang/heap_1.c @@ -0,0 +1,153 @@ +/* + * FreeRTOS Kernel V10.4.6 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/* + * The simplest possible implementation of pvPortMalloc(). Note that this + * implementation does NOT allow allocated memory to be freed again. + * + * See heap_2.c, heap_3.c and heap_4.c for alternative implementations, and the + * memory management pages of https://www.FreeRTOS.org for more information. + */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#include "FreeRTOS.h" +#include "task.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) + #error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0 +#endif + +/* A few bytes might be lost to byte aligning the heap start address. */ +#define configADJUSTED_HEAP_SIZE ( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT ) + +/* Allocate the memory for the heap. */ +#if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) + +/* The application writer has already defined the array used for the RTOS +* heap - probably so it can be placed in a special segment or address. */ + extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; +#else + static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; +#endif /* configAPPLICATION_ALLOCATED_HEAP */ + +/* Index into the ucHeap array. */ +static size_t xNextFreeByte = ( size_t ) 0; + +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + void * pvReturn = NULL; + static uint8_t * pucAlignedHeap = NULL; + + /* Ensure that blocks are always aligned. */ + #if ( portBYTE_ALIGNMENT != 1 ) + { + if( xWantedSize & portBYTE_ALIGNMENT_MASK ) + { + /* Byte alignment required. Check for overflow. */ + if ( (xWantedSize + ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) )) > xWantedSize ) + { + xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ); + } + else + { + xWantedSize = 0; + } + } + } + #endif + + vTaskSuspendAll(); + { + if( pucAlignedHeap == NULL ) + { + /* Ensure the heap starts on a correctly aligned boundary. */ + pucAlignedHeap = ( uint8_t * ) ( ( ( portPOINTER_SIZE_TYPE ) & ucHeap[ portBYTE_ALIGNMENT - 1 ] ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); + } + + /* Check there is enough room left for the allocation and. */ + if( ( xWantedSize > 0 ) && /* valid size */ + ( ( xNextFreeByte + xWantedSize ) < configADJUSTED_HEAP_SIZE ) && + ( ( xNextFreeByte + xWantedSize ) > xNextFreeByte ) ) /* Check for overflow. */ + { + /* Return the next free byte then increment the index past this + * block. */ + pvReturn = pucAlignedHeap + xNextFreeByte; + xNextFreeByte += xWantedSize; + } + + traceMALLOC( pvReturn, xWantedSize ); + } + ( void ) xTaskResumeAll(); + + #if ( configUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); + } + } + #endif + + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + /* Memory cannot be freed using this scheme. See heap_2.c, heap_3.c and + * heap_4.c for alternative implementations, and the memory management pages of + * https://www.FreeRTOS.org for more information. */ + ( void ) pv; + + /* Force an assert as it is invalid to call this function. */ + configASSERT( pv == NULL ); +} +/*-----------------------------------------------------------*/ + +void vPortInitialiseBlocks( void ) +{ + /* Only required when static memory is not cleared. */ + xNextFreeByte = ( size_t ) 0; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return( configADJUSTED_HEAP_SIZE - xNextFreeByte ); +} diff --git a/hw-libs/freertos/portable/MemMang/heap_2.c b/hw-libs/freertos/portable/MemMang/heap_2.c new file mode 100644 index 000000000..f690fd2a0 --- /dev/null +++ b/hw-libs/freertos/portable/MemMang/heap_2.c @@ -0,0 +1,286 @@ +/* + * FreeRTOS Kernel V10.4.6 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * A sample implementation of pvPortMalloc() and vPortFree() that permits + * allocated blocks to be freed, but does not combine adjacent free blocks + * into a single larger block (and so will fragment memory). See heap_4.c for + * an equivalent that does combine adjacent blocks into single larger blocks. + * + * See heap_1.c, heap_3.c and heap_4.c for alternative implementations, and the + * memory management pages of https://www.FreeRTOS.org for more information. + */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#include "FreeRTOS.h" +#include "task.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) + #error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0 +#endif + +/* A few bytes might be lost to byte aligning the heap start address. */ +#define configADJUSTED_HEAP_SIZE ( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT ) + +/* + * Initialises the heap structures before their first use. + */ +static void prvHeapInit( void ); + +/* Allocate the memory for the heap. */ +#if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) + +/* The application writer has already defined the array used for the RTOS +* heap - probably so it can be placed in a special segment or address. */ + extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; +#else + static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; +#endif /* configAPPLICATION_ALLOCATED_HEAP */ + + +/* Define the linked list structure. This is used to link free blocks in order + * of their size. */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK * pxNextFreeBlock; /*<< The next free block in the list. */ + size_t xBlockSize; /*<< The size of the free block. */ +} BlockLink_t; + + +static const uint16_t heapSTRUCT_SIZE = ( ( sizeof( BlockLink_t ) + ( portBYTE_ALIGNMENT - 1 ) ) & ~portBYTE_ALIGNMENT_MASK ); +#define heapMINIMUM_BLOCK_SIZE ( ( size_t ) ( heapSTRUCT_SIZE * 2 ) ) + +/* Create a couple of list links to mark the start and end of the list. */ +static BlockLink_t xStart, xEnd; + +/* Keeps track of the number of free bytes remaining, but says nothing about + * fragmentation. */ +static size_t xFreeBytesRemaining = configADJUSTED_HEAP_SIZE; + +/* STATIC FUNCTIONS ARE DEFINED AS MACROS TO MINIMIZE THE FUNCTION CALL DEPTH. */ + +/* + * Insert a block into the list of free blocks - which is ordered by size of + * the block. Small blocks at the start of the list and large blocks at the end + * of the list. + */ +#define prvInsertBlockIntoFreeList( pxBlockToInsert ) \ + { \ + BlockLink_t * pxIterator; \ + size_t xBlockSize; \ + \ + xBlockSize = pxBlockToInsert->xBlockSize; \ + \ + /* Iterate through the list until a block is found that has a larger size */ \ + /* than the block we are inserting. */ \ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock->xBlockSize < xBlockSize; pxIterator = pxIterator->pxNextFreeBlock ) \ + { \ + /* There is nothing to do here - just iterate to the correct position. */ \ + } \ + \ + /* Update the list to include the block being inserted in the correct */ \ + /* position. */ \ + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; \ + pxIterator->pxNextFreeBlock = pxBlockToInsert; \ + } +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + BlockLink_t * pxBlock, * pxPreviousBlock, * pxNewBlockLink; + static BaseType_t xHeapHasBeenInitialised = pdFALSE; + void * pvReturn = NULL; + + vTaskSuspendAll(); + { + /* If this is the first call to malloc then the heap will require + * initialisation to setup the list of free blocks. */ + if( xHeapHasBeenInitialised == pdFALSE ) + { + prvHeapInit(); + xHeapHasBeenInitialised = pdTRUE; + } + + /* The wanted size must be increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. */ + if( ( xWantedSize > 0 ) && + ( ( xWantedSize + heapSTRUCT_SIZE ) > xWantedSize ) ) /* Overflow check */ + { + xWantedSize += heapSTRUCT_SIZE; + + /* Byte alignment required. Check for overflow. */ + if( ( xWantedSize + ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ) ) + > xWantedSize ) + { + xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ); + configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 ); + } + else + { + xWantedSize = 0; + } + } + else + { + xWantedSize = 0; + } + + + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + { + /* Blocks are stored in byte order - traverse the list from the start + * (smallest) block until one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = xStart.pxNextFreeBlock; + + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = pxBlock->pxNextFreeBlock; + } + + /* If we found the end marker then a block of adequate size was not found. */ + if( pxBlock != &xEnd ) + { + /* Return the memory space - jumping over the BlockLink_t structure + * at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + heapSTRUCT_SIZE ); + + /* This block is being returned for use so must be taken out of the + * list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new block + * following the number of bytes requested. The void cast is + * used to prevent byte alignment warnings from the compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + + /* Calculate the sizes of two blocks split from the single + * block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + prvInsertBlockIntoFreeList( ( pxNewBlockLink ) ); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + } + } + + traceMALLOC( pvReturn, xWantedSize ); + } + ( void ) xTaskResumeAll(); + + #if ( configUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); + } + } + #endif + + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + uint8_t * puc = ( uint8_t * ) pv; + BlockLink_t * pxLink; + + if( pv != NULL ) + { + /* The memory being freed will have an BlockLink_t structure immediately + * before it. */ + puc -= heapSTRUCT_SIZE; + + /* This unexpected casting is to keep some compilers from issuing + * byte alignment warnings. */ + pxLink = ( void * ) puc; + + vTaskSuspendAll(); + { + /* Add this block to the list of free blocks. */ + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + xFreeBytesRemaining += pxLink->xBlockSize; + traceFREE( pv, pxLink->xBlockSize ); + } + ( void ) xTaskResumeAll(); + } +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +void vPortInitialiseBlocks( void ) +{ + /* This just exists to keep the linker quiet. */ +} +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) +{ + BlockLink_t * pxFirstFreeBlock; + uint8_t * pucAlignedHeap; + + /* Ensure the heap starts on a correctly aligned boundary. */ + pucAlignedHeap = ( uint8_t * ) ( ( ( portPOINTER_SIZE_TYPE ) & ucHeap[ portBYTE_ALIGNMENT - 1 ] ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); + + /* xStart is used to hold a pointer to the first item in the list of free + * blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + xStart.xBlockSize = ( size_t ) 0; + + /* xEnd is used to mark the end of the list of free blocks. */ + xEnd.xBlockSize = configADJUSTED_HEAP_SIZE; + xEnd.pxNextFreeBlock = NULL; + + /* To start with there is a single free block that is sized to take up the + * entire heap space. */ + pxFirstFreeBlock = ( void * ) pucAlignedHeap; + pxFirstFreeBlock->xBlockSize = configADJUSTED_HEAP_SIZE; + pxFirstFreeBlock->pxNextFreeBlock = &xEnd; +} +/*-----------------------------------------------------------*/ diff --git a/hw-libs/freertos/portable/MemMang/heap_3.c b/hw-libs/freertos/portable/MemMang/heap_3.c new file mode 100644 index 000000000..b73476919 --- /dev/null +++ b/hw-libs/freertos/portable/MemMang/heap_3.c @@ -0,0 +1,95 @@ +/* + * FreeRTOS Kernel V10.4.6 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/* + * Implementation of pvPortMalloc() and vPortFree() that relies on the + * compilers own malloc() and free() implementations. + * + * This file can only be used if the linker is configured to to generate + * a heap memory area. + * + * See heap_1.c, heap_2.c and heap_4.c for alternative implementations, and the + * memory management pages of https://www.FreeRTOS.org for more information. + */ + +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#include "FreeRTOS.h" +#include "task.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) + #error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0 +#endif + +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + void * pvReturn; + + vTaskSuspendAll(); + { + pvReturn = malloc( xWantedSize ); + traceMALLOC( pvReturn, xWantedSize ); + } + ( void ) xTaskResumeAll(); + + #if ( configUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); + } + } + #endif + + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + if( pv ) + { + vTaskSuspendAll(); + { + free( pv ); + traceFREE( pv, 0 ); + } + ( void ) xTaskResumeAll(); + } +} diff --git a/hw-libs/freertos/portable/MemMang/heap_4.c b/hw-libs/freertos/portable/MemMang/heap_4.c new file mode 100644 index 000000000..2676835b7 --- /dev/null +++ b/hw-libs/freertos/portable/MemMang/heap_4.c @@ -0,0 +1,504 @@ +/* + * FreeRTOS Kernel V10.4.6 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * A sample implementation of pvPortMalloc() and vPortFree() that combines + * (coalescences) adjacent memory blocks as they are freed, and in so doing + * limits memory fragmentation. + * + * See heap_1.c, heap_2.c and heap_3.c for alternative implementations, and the + * memory management pages of https://www.FreeRTOS.org for more information. + */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#include "FreeRTOS.h" +#include "task.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) + #error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0 +#endif + +/* Block sizes must not get too small. */ +#define heapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) ) + +/* Assumes 8bit bytes! */ +#define heapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Allocate the memory for the heap. */ +#if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) + +/* The application writer has already defined the array used for the RTOS +* heap - probably so it can be placed in a special segment or address. */ + extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; +#else + PRIVILEGED_DATA static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; +#endif /* configAPPLICATION_ALLOCATED_HEAP */ + +/* Define the linked list structure. This is used to link free blocks in order + * of their memory address. */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK * pxNextFreeBlock; /*<< The next free block in the list. */ + size_t xBlockSize; /*<< The size of the free block. */ +} BlockLink_t; + +/*-----------------------------------------------------------*/ + +/* + * Inserts a block of memory that is being freed into the correct position in + * the list of free memory blocks. The block being freed will be merged with + * the block in front it and/or the block behind it if the memory blocks are + * adjacent to each other. + */ +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) PRIVILEGED_FUNCTION; + +/* + * Called automatically to setup the required heap structures the first time + * pvPortMalloc() is called. + */ +static void prvHeapInit( void ) PRIVILEGED_FUNCTION; + +/*-----------------------------------------------------------*/ + +/* The size of the structure placed at the beginning of each allocated memory + * block must by correctly byte aligned. */ +static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); + +/* Create a couple of list links to mark the start and end of the list. */ +PRIVILEGED_DATA static BlockLink_t xStart, * pxEnd = NULL; + +/* Keeps track of the number of calls to allocate and free memory as well as the + * number of free bytes remaining, but says nothing about fragmentation. */ +PRIVILEGED_DATA static size_t xFreeBytesRemaining = 0U; +PRIVILEGED_DATA static size_t xMinimumEverFreeBytesRemaining = 0U; +PRIVILEGED_DATA static size_t xNumberOfSuccessfulAllocations = 0; +PRIVILEGED_DATA static size_t xNumberOfSuccessfulFrees = 0; + +/* Gets set to the top bit of an size_t type. When this bit in the xBlockSize + * member of an BlockLink_t structure is set then the block belongs to the + * application. When the bit is free the block is still part of the free heap + * space. */ +PRIVILEGED_DATA static size_t xBlockAllocatedBit = 0; + +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + BlockLink_t * pxBlock, * pxPreviousBlock, * pxNewBlockLink; + void * pvReturn = NULL; + + vTaskSuspendAll(); + { + /* If this is the first call to malloc then the heap will require + * initialisation to setup the list of free blocks. */ + if( pxEnd == NULL ) + { + prvHeapInit(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Check the requested block size is not so large that the top bit is + * set. The top bit of the block size member of the BlockLink_t structure + * is used to determine who owns the block - the application or the + * kernel, so it must be free. */ + if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) + { + /* The wanted size must be increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. */ + if( ( xWantedSize > 0 ) && + ( ( xWantedSize + xHeapStructSize ) > xWantedSize ) ) /* Overflow check */ + { + xWantedSize += xHeapStructSize; + + /* Ensure that blocks are always aligned. */ + if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 ) + { + /* Byte alignment required. Check for overflow. */ + if( ( xWantedSize + ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ) ) + > xWantedSize ) + { + xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ); + configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 ); + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + xWantedSize = 0; + } + + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + { + /* Traverse the list from the start (lowest address) block until + * one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = xStart.pxNextFreeBlock; + + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = pxBlock->pxNextFreeBlock; + } + + /* If the end marker was reached then a block of adequate size + * was not found. */ + if( pxBlock != pxEnd ) + { + /* Return the memory space pointed to - jumping over the + * BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + + /* This block is being returned for use so must be taken out + * of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into + * two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new + * block following the number of bytes requested. The void + * cast is used to prevent byte alignment warnings from the + * compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 ); + + /* Calculate the sizes of two blocks split from the + * single block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + prvInsertBlockIntoFreeList( pxNewBlockLink ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The block is being returned - it is allocated and owned + * by the application and has no "next" block. */ + pxBlock->xBlockSize |= xBlockAllocatedBit; + pxBlock->pxNextFreeBlock = NULL; + xNumberOfSuccessfulAllocations++; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xWantedSize ); + } + ( void ) xTaskResumeAll(); + + #if ( configUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* if ( configUSE_MALLOC_FAILED_HOOK == 1 ) */ + + configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 ); + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + uint8_t * puc = ( uint8_t * ) pv; + BlockLink_t * pxLink; + + if( pv != NULL ) + { + /* The memory being freed will have an BlockLink_t structure immediately + * before it. */ + puc -= xHeapStructSize; + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + + /* Check the block is actually allocated. */ + configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); + configASSERT( pxLink->pxNextFreeBlock == NULL ); + + if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) + { + if( pxLink->pxNextFreeBlock == NULL ) + { + /* The block is being returned to the heap - it is no longer + * allocated. */ + pxLink->xBlockSize &= ~xBlockAllocatedBit; + + vTaskSuspendAll(); + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + xNumberOfSuccessfulFrees++; + } + ( void ) xTaskResumeAll(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetMinimumEverFreeHeapSize( void ) +{ + return xMinimumEverFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +void vPortInitialiseBlocks( void ) +{ + /* This just exists to keep the linker quiet. */ +} +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) /* PRIVILEGED_FUNCTION */ +{ + BlockLink_t * pxFirstFreeBlock; + uint8_t * pucAlignedHeap; + size_t uxAddress; + size_t xTotalHeapSize = configTOTAL_HEAP_SIZE; + + /* Ensure the heap starts on a correctly aligned boundary. */ + uxAddress = ( size_t ) ucHeap; + + if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 ) + { + uxAddress += ( portBYTE_ALIGNMENT - 1 ); + uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); + xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; + } + + pucAlignedHeap = ( uint8_t * ) uxAddress; + + /* xStart is used to hold a pointer to the first item in the list of free + * blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + xStart.xBlockSize = ( size_t ) 0; + + /* pxEnd is used to mark the end of the list of free blocks and is inserted + * at the end of the heap space. */ + uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; + uxAddress -= xHeapStructSize; + uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); + pxEnd = ( void * ) uxAddress; + pxEnd->xBlockSize = 0; + pxEnd->pxNextFreeBlock = NULL; + + /* To start with there is a single free block that is sized to take up the + * entire heap space, minus the space taken by pxEnd. */ + pxFirstFreeBlock = ( void * ) pucAlignedHeap; + pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; + pxFirstFreeBlock->pxNextFreeBlock = pxEnd; + + /* Only one block exists - and it covers the entire usable heap space. */ + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + + /* Work out the position of the top bit in a size_t variable. */ + xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ); +} +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) /* PRIVILEGED_FUNCTION */ +{ + BlockLink_t * pxIterator; + uint8_t * puc; + + /* Iterate through the list until a block is found that has a higher address + * than the block being inserted. */ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + { + /* Nothing to do here, just iterate to the right position. */ + } + + /* Do the block being inserted, and the block it is being inserted after + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + pxBlockToInsert = pxIterator; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + { + if( pxIterator->pxNextFreeBlock != pxEnd ) + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxEnd; + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + } + + /* If the block being inserted plugged a gab, so was merged with the block + * before and the block after, then it's pxNextFreeBlock pointer will have + * already been set, and should not be set here as that would make it point + * to itself. */ + if( pxIterator != pxBlockToInsert ) + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +void vPortGetHeapStats( HeapStats_t * pxHeapStats ) +{ + BlockLink_t * pxBlock; + size_t xBlocks = 0, xMaxSize = 0, xMinSize = portMAX_DELAY; /* portMAX_DELAY used as a portable way of getting the maximum value. */ + + vTaskSuspendAll(); + { + pxBlock = xStart.pxNextFreeBlock; + + /* pxBlock will be NULL if the heap has not been initialised. The heap + * is initialised automatically when the first allocation is made. */ + if( pxBlock != NULL ) + { + do + { + /* Increment the number of blocks and record the largest block seen + * so far. */ + xBlocks++; + + if( pxBlock->xBlockSize > xMaxSize ) + { + xMaxSize = pxBlock->xBlockSize; + } + + if( pxBlock->xBlockSize < xMinSize ) + { + xMinSize = pxBlock->xBlockSize; + } + + /* Move to the next block in the chain until the last block is + * reached. */ + pxBlock = pxBlock->pxNextFreeBlock; + } while( pxBlock != pxEnd ); + } + } + ( void ) xTaskResumeAll(); + + pxHeapStats->xSizeOfLargestFreeBlockInBytes = xMaxSize; + pxHeapStats->xSizeOfSmallestFreeBlockInBytes = xMinSize; + pxHeapStats->xNumberOfFreeBlocks = xBlocks; + + taskENTER_CRITICAL(); + { + pxHeapStats->xAvailableHeapSpaceInBytes = xFreeBytesRemaining; + pxHeapStats->xNumberOfSuccessfulAllocations = xNumberOfSuccessfulAllocations; + pxHeapStats->xNumberOfSuccessfulFrees = xNumberOfSuccessfulFrees; + pxHeapStats->xMinimumEverFreeBytesRemaining = xMinimumEverFreeBytesRemaining; + } + taskEXIT_CRITICAL(); +} diff --git a/hw-libs/freertos/portable/MemMang/heap_5.c b/hw-libs/freertos/portable/MemMang/heap_5.c new file mode 100644 index 000000000..53a818bbb --- /dev/null +++ b/hw-libs/freertos/portable/MemMang/heap_5.c @@ -0,0 +1,559 @@ +/* + * FreeRTOS Kernel V10.4.6 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * A sample implementation of pvPortMalloc() that allows the heap to be defined + * across multiple non-contigous blocks and combines (coalescences) adjacent + * memory blocks as they are freed. + * + * See heap_1.c, heap_2.c, heap_3.c and heap_4.c for alternative + * implementations, and the memory management pages of https://www.FreeRTOS.org + * for more information. + * + * Usage notes: + * + * vPortDefineHeapRegions() ***must*** be called before pvPortMalloc(). + * pvPortMalloc() will be called if any task objects (tasks, queues, event + * groups, etc.) are created, therefore vPortDefineHeapRegions() ***must*** be + * called before any other objects are defined. + * + * vPortDefineHeapRegions() takes a single parameter. The parameter is an array + * of HeapRegion_t structures. HeapRegion_t is defined in portable.h as + * + * typedef struct HeapRegion + * { + * uint8_t *pucStartAddress; << Start address of a block of memory that will be part of the heap. + * size_t xSizeInBytes; << Size of the block of memory. + * } HeapRegion_t; + * + * The array is terminated using a NULL zero sized region definition, and the + * memory regions defined in the array ***must*** appear in address order from + * low address to high address. So the following is a valid example of how + * to use the function. + * + * HeapRegion_t xHeapRegions[] = + * { + * { ( uint8_t * ) 0x80000000UL, 0x10000 }, << Defines a block of 0x10000 bytes starting at address 0x80000000 + * { ( uint8_t * ) 0x90000000UL, 0xa0000 }, << Defines a block of 0xa0000 bytes starting at address of 0x90000000 + * { NULL, 0 } << Terminates the array. + * }; + * + * vPortDefineHeapRegions( xHeapRegions ); << Pass the array into vPortDefineHeapRegions(). + * + * Note 0x80000000 is the lower address so appears in the array first. + * + */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#include "FreeRTOS.h" +#include "task.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) + #error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0 +#endif + +/* Block sizes must not get too small. */ +#define heapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) ) + +/* Assumes 8bit bytes! */ +#define heapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Define the linked list structure. This is used to link free blocks in order + * of their memory address. */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK * pxNextFreeBlock; /*<< The next free block in the list. */ + size_t xBlockSize; /*<< The size of the free block. */ +} BlockLink_t; + +/*-----------------------------------------------------------*/ + +/* + * Inserts a block of memory that is being freed into the correct position in + * the list of free memory blocks. The block being freed will be merged with + * the block in front it and/or the block behind it if the memory blocks are + * adjacent to each other. + */ +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ); + +/*-----------------------------------------------------------*/ + +/* The size of the structure placed at the beginning of each allocated memory + * block must by correctly byte aligned. */ +static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); + +/* Create a couple of list links to mark the start and end of the list. */ +static BlockLink_t xStart, * pxEnd = NULL; + +/* Keeps track of the number of calls to allocate and free memory as well as the + * number of free bytes remaining, but says nothing about fragmentation. */ +static size_t xFreeBytesRemaining = 0U; +static size_t xMinimumEverFreeBytesRemaining = 0U; +static size_t xNumberOfSuccessfulAllocations = 0; +static size_t xNumberOfSuccessfulFrees = 0; + +/* Gets set to the top bit of an size_t type. When this bit in the xBlockSize + * member of an BlockLink_t structure is set then the block belongs to the + * application. When the bit is free the block is still part of the free heap + * space. */ +static size_t xBlockAllocatedBit = 0; + +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + BlockLink_t * pxBlock, * pxPreviousBlock, * pxNewBlockLink; + void * pvReturn = NULL; + + /* The heap must be initialised before the first call to + * prvPortMalloc(). */ + configASSERT( pxEnd ); + + vTaskSuspendAll(); + { + /* Check the requested block size is not so large that the top bit is + * set. The top bit of the block size member of the BlockLink_t structure + * is used to determine who owns the block - the application or the + * kernel, so it must be free. */ + if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) + { + /* The wanted size is increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. */ + if( ( xWantedSize > 0 ) && + ( ( xWantedSize + xHeapStructSize ) > xWantedSize ) ) /* Overflow check */ + { + xWantedSize += xHeapStructSize; + + /* Ensure that blocks are always aligned */ + if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 ) + { + /* Byte alignment required. Check for overflow */ + if( ( xWantedSize + ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ) ) > + xWantedSize ) + { + xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ); + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + xWantedSize = 0; + } + + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + { + /* Traverse the list from the start (lowest address) block until + * one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = xStart.pxNextFreeBlock; + + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = pxBlock->pxNextFreeBlock; + } + + /* If the end marker was reached then a block of adequate size + * was not found. */ + if( pxBlock != pxEnd ) + { + /* Return the memory space pointed to - jumping over the + * BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + + /* This block is being returned for use so must be taken out + * of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into + * two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new + * block following the number of bytes requested. The void + * cast is used to prevent byte alignment warnings from the + * compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + + /* Calculate the sizes of two blocks split from the + * single block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + prvInsertBlockIntoFreeList( ( pxNewBlockLink ) ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The block is being returned - it is allocated and owned + * by the application and has no "next" block. */ + pxBlock->xBlockSize |= xBlockAllocatedBit; + pxBlock->pxNextFreeBlock = NULL; + xNumberOfSuccessfulAllocations++; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xWantedSize ); + } + ( void ) xTaskResumeAll(); + + #if ( configUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* if ( configUSE_MALLOC_FAILED_HOOK == 1 ) */ + + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + uint8_t * puc = ( uint8_t * ) pv; + BlockLink_t * pxLink; + + if( pv != NULL ) + { + /* The memory being freed will have an BlockLink_t structure immediately + * before it. */ + puc -= xHeapStructSize; + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + + /* Check the block is actually allocated. */ + configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); + configASSERT( pxLink->pxNextFreeBlock == NULL ); + + if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) + { + if( pxLink->pxNextFreeBlock == NULL ) + { + /* The block is being returned to the heap - it is no longer + * allocated. */ + pxLink->xBlockSize &= ~xBlockAllocatedBit; + + vTaskSuspendAll(); + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + xNumberOfSuccessfulFrees++; + } + ( void ) xTaskResumeAll(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetMinimumEverFreeHeapSize( void ) +{ + return xMinimumEverFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) +{ + BlockLink_t * pxIterator; + uint8_t * puc; + + /* Iterate through the list until a block is found that has a higher address + * than the block being inserted. */ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + { + /* Nothing to do here, just iterate to the right position. */ + } + + /* Do the block being inserted, and the block it is being inserted after + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + pxBlockToInsert = pxIterator; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + { + if( pxIterator->pxNextFreeBlock != pxEnd ) + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxEnd; + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + } + + /* If the block being inserted plugged a gab, so was merged with the block + * before and the block after, then it's pxNextFreeBlock pointer will have + * already been set, and should not be set here as that would make it point + * to itself. */ + if( pxIterator != pxBlockToInsert ) + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) +{ + BlockLink_t * pxFirstFreeBlockInRegion = NULL, * pxPreviousFreeBlock; + size_t xAlignedHeap; + size_t xTotalRegionSize, xTotalHeapSize = 0; + BaseType_t xDefinedRegions = 0; + size_t xAddress; + const HeapRegion_t * pxHeapRegion; + + /* Can only call once! */ + configASSERT( pxEnd == NULL ); + + pxHeapRegion = &( pxHeapRegions[ xDefinedRegions ] ); + + while( pxHeapRegion->xSizeInBytes > 0 ) + { + xTotalRegionSize = pxHeapRegion->xSizeInBytes; + + /* Ensure the heap region starts on a correctly aligned boundary. */ + xAddress = ( size_t ) pxHeapRegion->pucStartAddress; + + if( ( xAddress & portBYTE_ALIGNMENT_MASK ) != 0 ) + { + xAddress += ( portBYTE_ALIGNMENT - 1 ); + xAddress &= ~portBYTE_ALIGNMENT_MASK; + + /* Adjust the size for the bytes lost to alignment. */ + xTotalRegionSize -= xAddress - ( size_t ) pxHeapRegion->pucStartAddress; + } + + xAlignedHeap = xAddress; + + /* Set xStart if it has not already been set. */ + if( xDefinedRegions == 0 ) + { + /* xStart is used to hold a pointer to the first item in the list of + * free blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( BlockLink_t * ) xAlignedHeap; + xStart.xBlockSize = ( size_t ) 0; + } + else + { + /* Should only get here if one region has already been added to the + * heap. */ + configASSERT( pxEnd != NULL ); + + /* Check blocks are passed in with increasing start addresses. */ + configASSERT( xAddress > ( size_t ) pxEnd ); + } + + /* Remember the location of the end marker in the previous region, if + * any. */ + pxPreviousFreeBlock = pxEnd; + + /* pxEnd is used to mark the end of the list of free blocks and is + * inserted at the end of the region space. */ + xAddress = xAlignedHeap + xTotalRegionSize; + xAddress -= xHeapStructSize; + xAddress &= ~portBYTE_ALIGNMENT_MASK; + pxEnd = ( BlockLink_t * ) xAddress; + pxEnd->xBlockSize = 0; + pxEnd->pxNextFreeBlock = NULL; + + /* To start with there is a single free block in this region that is + * sized to take up the entire heap region minus the space taken by the + * free block structure. */ + pxFirstFreeBlockInRegion = ( BlockLink_t * ) xAlignedHeap; + pxFirstFreeBlockInRegion->xBlockSize = xAddress - ( size_t ) pxFirstFreeBlockInRegion; + pxFirstFreeBlockInRegion->pxNextFreeBlock = pxEnd; + + /* If this is not the first region that makes up the entire heap space + * then link the previous region to this region. */ + if( pxPreviousFreeBlock != NULL ) + { + pxPreviousFreeBlock->pxNextFreeBlock = pxFirstFreeBlockInRegion; + } + + xTotalHeapSize += pxFirstFreeBlockInRegion->xBlockSize; + + /* Move onto the next HeapRegion_t structure. */ + xDefinedRegions++; + pxHeapRegion = &( pxHeapRegions[ xDefinedRegions ] ); + } + + xMinimumEverFreeBytesRemaining = xTotalHeapSize; + xFreeBytesRemaining = xTotalHeapSize; + + /* Check something was actually defined before it is accessed. */ + configASSERT( xTotalHeapSize ); + + /* Work out the position of the top bit in a size_t variable. */ + xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ); +} +/*-----------------------------------------------------------*/ + +void vPortGetHeapStats( HeapStats_t * pxHeapStats ) +{ + BlockLink_t * pxBlock; + size_t xBlocks = 0, xMaxSize = 0, xMinSize = portMAX_DELAY; /* portMAX_DELAY used as a portable way of getting the maximum value. */ + + vTaskSuspendAll(); + { + pxBlock = xStart.pxNextFreeBlock; + + /* pxBlock will be NULL if the heap has not been initialised. The heap + * is initialised automatically when the first allocation is made. */ + if( pxBlock != NULL ) + { + do + { + /* Increment the number of blocks and record the largest block seen + * so far. */ + xBlocks++; + + if( pxBlock->xBlockSize > xMaxSize ) + { + xMaxSize = pxBlock->xBlockSize; + } + + /* Heap five will have a zero sized block at the end of each + * each region - the block is only used to link to the next + * heap region so it not a real block. */ + if( pxBlock->xBlockSize != 0 ) + { + if( pxBlock->xBlockSize < xMinSize ) + { + xMinSize = pxBlock->xBlockSize; + } + } + + /* Move to the next block in the chain until the last block is + * reached. */ + pxBlock = pxBlock->pxNextFreeBlock; + } while( pxBlock != pxEnd ); + } + } + ( void ) xTaskResumeAll(); + + pxHeapStats->xSizeOfLargestFreeBlockInBytes = xMaxSize; + pxHeapStats->xSizeOfSmallestFreeBlockInBytes = xMinSize; + pxHeapStats->xNumberOfFreeBlocks = xBlocks; + + taskENTER_CRITICAL(); + { + pxHeapStats->xAvailableHeapSpaceInBytes = xFreeBytesRemaining; + pxHeapStats->xNumberOfSuccessfulAllocations = xNumberOfSuccessfulAllocations; + pxHeapStats->xNumberOfSuccessfulFrees = xNumberOfSuccessfulFrees; + pxHeapStats->xMinimumEverFreeBytesRemaining = xMinimumEverFreeBytesRemaining; + } + taskEXIT_CRITICAL(); +} diff --git a/hw-libs/freertos/queue.c b/hw-libs/freertos/queue.c new file mode 100644 index 000000000..46ed9a4ff --- /dev/null +++ b/hw-libs/freertos/queue.c @@ -0,0 +1,3075 @@ +/* + * FreeRTOS Kernel V10.4.6 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +#if ( configUSE_CO_ROUTINES == 1 ) + #include "croutine.h" +#endif + +/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified + * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined + * for the header files above, but not in this file, in order to generate the + * correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */ + + +/* Constants used with the cRxLock and cTxLock structure members. */ +#define queueUNLOCKED ( ( int8_t ) -1 ) +#define queueLOCKED_UNMODIFIED ( ( int8_t ) 0 ) +#define queueINT8_MAX ( ( int8_t ) 127 ) + +/* When the Queue_t structure is used to represent a base queue its pcHead and + * pcTail members are used as pointers into the queue storage area. When the + * Queue_t structure is used to represent a mutex pcHead and pcTail pointers are + * not necessary, and the pcHead pointer is set to NULL to indicate that the + * structure instead holds a pointer to the mutex holder (if any). Map alternative + * names to the pcHead and structure member to ensure the readability of the code + * is maintained. The QueuePointers_t and SemaphoreData_t types are used to form + * a union as their usage is mutually exclusive dependent on what the queue is + * being used for. */ +#define uxQueueType pcHead +#define queueQUEUE_IS_MUTEX NULL + +typedef struct QueuePointers +{ + int8_t * pcTail; /*< Points to the byte at the end of the queue storage area. Once more byte is allocated than necessary to store the queue items, this is used as a marker. */ + int8_t * pcReadFrom; /*< Points to the last place that a queued item was read from when the structure is used as a queue. */ +} QueuePointers_t; + +typedef struct SemaphoreData +{ + TaskHandle_t xMutexHolder; /*< The handle of the task that holds the mutex. */ + UBaseType_t uxRecursiveCallCount; /*< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */ +} SemaphoreData_t; + +/* Semaphores do not actually store or copy data, so have an item size of + * zero. */ +#define queueSEMAPHORE_QUEUE_ITEM_LENGTH ( ( UBaseType_t ) 0 ) +#define queueMUTEX_GIVE_BLOCK_TIME ( ( TickType_t ) 0U ) + +#if ( configUSE_PREEMPTION == 0 ) + +/* If the cooperative scheduler is being used then a yield should not be + * performed just because a higher priority task has been woken. */ + #define queueYIELD_IF_USING_PREEMPTION() +#else + #define queueYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API() +#endif + +/* + * Definition of the queue used by the scheduler. + * Items are queued by copy, not reference. See the following link for the + * rationale: https://www.FreeRTOS.org/Embedded-RTOS-Queues.html + */ +typedef struct QueueDefinition /* The old naming convention is used to prevent breaking kernel aware debuggers. */ +{ + int8_t * pcHead; /*< Points to the beginning of the queue storage area. */ + int8_t * pcWriteTo; /*< Points to the free next place in the storage area. */ + + union + { + QueuePointers_t xQueue; /*< Data required exclusively when this structure is used as a queue. */ + SemaphoreData_t xSemaphore; /*< Data required exclusively when this structure is used as a semaphore. */ + } u; + + List_t xTasksWaitingToSend; /*< List of tasks that are blocked waiting to post onto this queue. Stored in priority order. */ + List_t xTasksWaitingToReceive; /*< List of tasks that are blocked waiting to read from this queue. Stored in priority order. */ + + volatile UBaseType_t uxMessagesWaiting; /*< The number of items currently in the queue. */ + UBaseType_t uxLength; /*< The length of the queue defined as the number of items it will hold, not the number of bytes. */ + UBaseType_t uxItemSize; /*< The size of each items that the queue will hold. */ + + volatile int8_t cRxLock; /*< Stores the number of items received from the queue (removed from the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */ + volatile int8_t cTxLock; /*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */ + + #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the memory used by the queue was statically allocated to ensure no attempt is made to free the memory. */ + #endif + + #if ( configUSE_QUEUE_SETS == 1 ) + struct QueueDefinition * pxQueueSetContainer; + #endif + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxQueueNumber; + uint8_t ucQueueType; + #endif +} xQUEUE; + +/* The old xQUEUE name is maintained above then typedefed to the new Queue_t + * name below to enable the use of older kernel aware debuggers. */ +typedef xQUEUE Queue_t; + +/*-----------------------------------------------------------*/ + +/* + * The queue registry is just a means for kernel aware debuggers to locate + * queue structures. It has no other purpose so is an optional component. + */ +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + +/* The type stored within the queue registry array. This allows a name + * to be assigned to each queue making kernel aware debugging a little + * more user friendly. */ + typedef struct QUEUE_REGISTRY_ITEM + { + const char * pcQueueName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + QueueHandle_t xHandle; + } xQueueRegistryItem; + +/* The old xQueueRegistryItem name is maintained above then typedefed to the + * new xQueueRegistryItem name below to enable the use of older kernel aware + * debuggers. */ + typedef xQueueRegistryItem QueueRegistryItem_t; + +/* The queue registry is simply an array of QueueRegistryItem_t structures. + * The pcQueueName member of a structure being NULL is indicative of the + * array position being vacant. */ + PRIVILEGED_DATA QueueRegistryItem_t xQueueRegistry[ configQUEUE_REGISTRY_SIZE ]; + +#endif /* configQUEUE_REGISTRY_SIZE */ + +/* + * Unlocks a queue locked by a call to prvLockQueue. Locking a queue does not + * prevent an ISR from adding or removing items to the queue, but does prevent + * an ISR from removing tasks from the queue event lists. If an ISR finds a + * queue is locked it will instead increment the appropriate queue lock count + * to indicate that a task may require unblocking. When the queue in unlocked + * these lock counts are inspected, and the appropriate action taken. + */ +static void prvUnlockQueue( Queue_t * const pxQueue ) PRIVILEGED_FUNCTION; + +/* + * Uses a critical section to determine if there is any data in a queue. + * + * @return pdTRUE if the queue contains no items, otherwise pdFALSE. + */ +static BaseType_t prvIsQueueEmpty( const Queue_t * pxQueue ) PRIVILEGED_FUNCTION; + +/* + * Uses a critical section to determine if there is any space in a queue. + * + * @return pdTRUE if there is no space, otherwise pdFALSE; + */ +static BaseType_t prvIsQueueFull( const Queue_t * pxQueue ) PRIVILEGED_FUNCTION; + +/* + * Copies an item into the queue, either at the front of the queue or the + * back of the queue. + */ +static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, + const void * pvItemToQueue, + const BaseType_t xPosition ) PRIVILEGED_FUNCTION; + +/* + * Copies an item out of a queue. + */ +static void prvCopyDataFromQueue( Queue_t * const pxQueue, + void * const pvBuffer ) PRIVILEGED_FUNCTION; + +#if ( configUSE_QUEUE_SETS == 1 ) + +/* + * Checks to see if a queue is a member of a queue set, and if so, notifies + * the queue set that the queue contains data. + */ + static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION; +#endif + +/* + * Called after a Queue_t structure has been allocated either statically or + * dynamically to fill in the structure's members. + */ +static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + uint8_t * pucQueueStorage, + const uint8_t ucQueueType, + Queue_t * pxNewQueue ) PRIVILEGED_FUNCTION; + +/* + * Mutexes are a special type of queue. When a mutex is created, first the + * queue is created, then prvInitialiseMutex() is called to configure the queue + * as a mutex. + */ +#if ( configUSE_MUTEXES == 1 ) + static void prvInitialiseMutex( Queue_t * pxNewQueue ) PRIVILEGED_FUNCTION; +#endif + +#if ( configUSE_MUTEXES == 1 ) + +/* + * If a task waiting for a mutex causes the mutex holder to inherit a + * priority, but the waiting task times out, then the holder should + * disinherit the priority - but only down to the highest priority of any + * other tasks that are waiting for the same mutex. This function returns + * that priority. + */ + static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION; +#endif +/*-----------------------------------------------------------*/ + +/* + * Macro to mark a queue as locked. Locking a queue prevents an ISR from + * accessing the queue event lists. + */ +#define prvLockQueue( pxQueue ) \ + taskENTER_CRITICAL(); \ + { \ + if( ( pxQueue )->cRxLock == queueUNLOCKED ) \ + { \ + ( pxQueue )->cRxLock = queueLOCKED_UNMODIFIED; \ + } \ + if( ( pxQueue )->cTxLock == queueUNLOCKED ) \ + { \ + ( pxQueue )->cTxLock = queueLOCKED_UNMODIFIED; \ + } \ + } \ + taskEXIT_CRITICAL() +/*-----------------------------------------------------------*/ + +BaseType_t xQueueGenericReset( QueueHandle_t xQueue, + BaseType_t xNewQueue ) +{ + BaseType_t xReturn = pdPASS; + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + + if( ( pxQueue != NULL ) && + ( pxQueue->uxLength >= 1U ) && + /* Check for multiplication overflow. */ + ( ( SIZE_MAX / pxQueue->uxLength ) >= pxQueue->uxItemSize ) ) + { + taskENTER_CRITICAL(); + { + pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ + pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U; + pxQueue->pcWriteTo = pxQueue->pcHead; + pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ + pxQueue->cRxLock = queueUNLOCKED; + pxQueue->cTxLock = queueUNLOCKED; + + if( xNewQueue == pdFALSE ) + { + /* If there are tasks blocked waiting to read from the queue, then + * the tasks will remain blocked as after this function exits the queue + * will still be empty. If there are tasks blocked waiting to write to + * the queue, then one should be unblocked as after this function exits + * it will be possible to write to it. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* Ensure the event queues start in the correct state. */ + vListInitialise( &( pxQueue->xTasksWaitingToSend ) ); + vListInitialise( &( pxQueue->xTasksWaitingToReceive ) ); + } + } + taskEXIT_CRITICAL(); + } + else + { + xReturn = pdFAIL; + } + + configASSERT( xReturn != pdFAIL ); + + /* A value is returned for calling semantic consistency with previous + * versions. */ + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + + QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + uint8_t * pucQueueStorage, + StaticQueue_t * pxStaticQueue, + const uint8_t ucQueueType ) + { + Queue_t * pxNewQueue = NULL; + + /* The StaticQueue_t structure and the queue storage area must be + * supplied. */ + configASSERT( pxStaticQueue ); + + if( ( uxQueueLength > ( UBaseType_t ) 0 ) && + ( pxStaticQueue != NULL ) && + + /* A queue storage area should be provided if the item size is not 0, and + * should not be provided if the item size is 0. */ + ( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) ) && + ( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) ) ) + { + #if ( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + * variable of type StaticQueue_t or StaticSemaphore_t equals the size of + * the real queue and semaphore structures. */ + volatile size_t xSize = sizeof( StaticQueue_t ); + + /* This assertion cannot be branch covered in unit tests */ + configASSERT( xSize == sizeof( Queue_t ) ); /* LCOV_EXCL_BR_LINE */ + ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ + } + #endif /* configASSERT_DEFINED */ + + /* The address of a statically allocated queue was passed in, use it. + * The address of a statically allocated storage area was also passed in + * but is already set. */ + pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ + + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + /* Queues can be allocated wither statically or dynamically, so + * note this queue was allocated statically in case the queue is + * later deleted. */ + pxNewQueue->ucStaticallyAllocated = pdTRUE; + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + + prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); + } + else + { + configASSERT( pxNewQueue ); + mtCOVERAGE_TEST_MARKER(); + } + + return pxNewQueue; + } + +#endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + const uint8_t ucQueueType ) + { + Queue_t * pxNewQueue = NULL; + size_t xQueueSizeInBytes; + uint8_t * pucQueueStorage; + + if( ( uxQueueLength > ( UBaseType_t ) 0 ) && + /* Check for multiplication overflow. */ + ( ( SIZE_MAX / uxQueueLength ) >= uxItemSize ) && + /* Check for addition overflow. */ + ( ( SIZE_MAX - sizeof( Queue_t ) ) >= ( uxQueueLength * uxItemSize ) ) ) + { + /* Allocate enough space to hold the maximum number of items that + * can be in the queue at any time. It is valid for uxItemSize to be + * zero in the case the queue is used as a semaphore. */ + xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + + /* Allocate the queue and storage area. Justification for MISRA + * deviation as follows: pvPortMalloc() always ensures returned memory + * blocks are aligned per the requirements of the MCU stack. In this case + * pvPortMalloc() must return a pointer that is guaranteed to meet the + * alignment requirements of the Queue_t structure - which in this case + * is an int8_t *. Therefore, whenever the stack alignment requirements + * are greater than or equal to the pointer to char requirements the cast + * is safe. In other cases alignment requirements are not strict (one or + * two bytes). */ + pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */ + + if( pxNewQueue != NULL ) + { + /* Jump past the queue structure to find the location of the queue + * storage area. */ + pucQueueStorage = ( uint8_t * ) pxNewQueue; + pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + /* Queues can be created either statically or dynamically, so + * note this task was created dynamically in case it is later + * deleted. */ + pxNewQueue->ucStaticallyAllocated = pdFALSE; + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ + + prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); + } + else + { + traceQUEUE_CREATE_FAILED( ucQueueType ); + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + configASSERT( pxNewQueue ); + mtCOVERAGE_TEST_MARKER(); + } + + return pxNewQueue; + } + +#endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + uint8_t * pucQueueStorage, + const uint8_t ucQueueType, + Queue_t * pxNewQueue ) +{ + /* Remove compiler warnings about unused parameters should + * configUSE_TRACE_FACILITY not be set to 1. */ + ( void ) ucQueueType; + + if( uxItemSize == ( UBaseType_t ) 0 ) + { + /* No RAM was allocated for the queue storage area, but PC head cannot + * be set to NULL because NULL is used as a key to say the queue is used as + * a mutex. Therefore just set pcHead to point to the queue as a benign + * value that is known to be within the memory map. */ + pxNewQueue->pcHead = ( int8_t * ) pxNewQueue; + } + else + { + /* Set the head to the start of the queue storage area. */ + pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage; + } + + /* Initialise the queue members as described where the queue type is + * defined. */ + pxNewQueue->uxLength = uxQueueLength; + pxNewQueue->uxItemSize = uxItemSize; + ( void ) xQueueGenericReset( pxNewQueue, pdTRUE ); + + #if ( configUSE_TRACE_FACILITY == 1 ) + { + pxNewQueue->ucQueueType = ucQueueType; + } + #endif /* configUSE_TRACE_FACILITY */ + + #if ( configUSE_QUEUE_SETS == 1 ) + { + pxNewQueue->pxQueueSetContainer = NULL; + } + #endif /* configUSE_QUEUE_SETS */ + + traceQUEUE_CREATE( pxNewQueue ); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_MUTEXES == 1 ) + + static void prvInitialiseMutex( Queue_t * pxNewQueue ) + { + if( pxNewQueue != NULL ) + { + /* The queue create function will set all the queue structure members + * correctly for a generic queue, but this function is creating a + * mutex. Overwrite those members that need to be set differently - + * in particular the information required for priority inheritance. */ + pxNewQueue->u.xSemaphore.xMutexHolder = NULL; + pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX; + + /* In case this is a recursive mutex. */ + pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0; + + traceCREATE_MUTEX( pxNewQueue ); + + /* Start with the semaphore in the expected state. */ + ( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK ); + } + else + { + traceCREATE_MUTEX_FAILED(); + } + } + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + + QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) + { + QueueHandle_t xNewQueue; + const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; + + xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType ); + prvInitialiseMutex( ( Queue_t * ) xNewQueue ); + + return xNewQueue; + } + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + + QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, + StaticQueue_t * pxStaticQueue ) + { + QueueHandle_t xNewQueue; + const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; + + /* Prevent compiler warnings about unused parameters if + * configUSE_TRACE_FACILITY does not equal 1. */ + ( void ) ucQueueType; + + xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType ); + prvInitialiseMutex( ( Queue_t * ) xNewQueue ); + + return xNewQueue; + } + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + + TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) + { + TaskHandle_t pxReturn; + Queue_t * const pxSemaphore = ( Queue_t * ) xSemaphore; + + configASSERT( xSemaphore ); + + /* This function is called by xSemaphoreGetMutexHolder(), and should not + * be called directly. Note: This is a good way of determining if the + * calling task is the mutex holder, but not a good way of determining the + * identity of the mutex holder, as the holder may change between the + * following critical section exiting and the function returning. */ + taskENTER_CRITICAL(); + { + if( pxSemaphore->uxQueueType == queueQUEUE_IS_MUTEX ) + { + pxReturn = pxSemaphore->u.xSemaphore.xMutexHolder; + } + else + { + pxReturn = NULL; + } + } + taskEXIT_CRITICAL(); + + return pxReturn; + } /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */ + +#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + + TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) + { + TaskHandle_t pxReturn; + + configASSERT( xSemaphore ); + + /* Mutexes cannot be used in interrupt service routines, so the mutex + * holder should not change in an ISR, and therefore a critical section is + * not required here. */ + if( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX ) + { + pxReturn = ( ( Queue_t * ) xSemaphore )->u.xSemaphore.xMutexHolder; + } + else + { + pxReturn = NULL; + } + + return pxReturn; + } /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */ + +#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) + { + BaseType_t xReturn; + Queue_t * const pxMutex = ( Queue_t * ) xMutex; + + configASSERT( pxMutex ); + + /* If this is the task that holds the mutex then xMutexHolder will not + * change outside of this task. If this task does not hold the mutex then + * pxMutexHolder can never coincidentally equal the tasks handle, and as + * this is the only condition we are interested in it does not matter if + * pxMutexHolder is accessed simultaneously by another task. Therefore no + * mutual exclusion is required to test the pxMutexHolder variable. */ + if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() ) + { + traceGIVE_MUTEX_RECURSIVE( pxMutex ); + + /* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to + * the task handle, therefore no underflow check is required. Also, + * uxRecursiveCallCount is only modified by the mutex holder, and as + * there can only be one, no mutual exclusion is required to modify the + * uxRecursiveCallCount member. */ + ( pxMutex->u.xSemaphore.uxRecursiveCallCount )--; + + /* Has the recursive call count unwound to 0? */ + if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 ) + { + /* Return the mutex. This will automatically unblock any other + * task that might be waiting to access the mutex. */ + ( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xReturn = pdPASS; + } + else + { + /* The mutex cannot be given because the calling task is not the + * holder. */ + xReturn = pdFAIL; + + traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex ); + } + + return xReturn; + } + +#endif /* configUSE_RECURSIVE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) + { + BaseType_t xReturn; + Queue_t * const pxMutex = ( Queue_t * ) xMutex; + + configASSERT( pxMutex ); + + /* Comments regarding mutual exclusion as per those within + * xQueueGiveMutexRecursive(). */ + + traceTAKE_MUTEX_RECURSIVE( pxMutex ); + + if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() ) + { + ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++; + xReturn = pdPASS; + } + else + { + xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait ); + + /* pdPASS will only be returned if the mutex was successfully + * obtained. The calling task may have entered the Blocked state + * before reaching here. */ + if( xReturn != pdFAIL ) + { + ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++; + } + else + { + traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex ); + } + } + + return xReturn; + } + +#endif /* configUSE_RECURSIVE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + + QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, + const UBaseType_t uxInitialCount, + StaticQueue_t * pxStaticQueue ) + { + QueueHandle_t xHandle = NULL; + + if( ( uxMaxCount != 0 ) && + ( uxInitialCount <= uxMaxCount ) ) + { + xHandle = xQueueGenericCreateStatic( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticQueue, queueQUEUE_TYPE_COUNTING_SEMAPHORE ); + + if( xHandle != NULL ) + { + ( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount; + + traceCREATE_COUNTING_SEMAPHORE(); + } + else + { + traceCREATE_COUNTING_SEMAPHORE_FAILED(); + } + } + else + { + configASSERT( xHandle ); + mtCOVERAGE_TEST_MARKER(); + } + + return xHandle; + } + +#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + + QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, + const UBaseType_t uxInitialCount ) + { + QueueHandle_t xHandle = NULL; + + if( ( uxMaxCount != 0 ) && + ( uxInitialCount <= uxMaxCount ) ) + { + xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE ); + + if( xHandle != NULL ) + { + ( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount; + + traceCREATE_COUNTING_SEMAPHORE(); + } + else + { + traceCREATE_COUNTING_SEMAPHORE_FAILED(); + } + } + else + { + configASSERT( xHandle ); + mtCOVERAGE_TEST_MARKER(); + } + + return xHandle; + } + +#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) +{ + BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired; + TimeOut_t xTimeOut; + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); + configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + /*lint -save -e904 This function relaxes the coding standard somewhat to + * allow return statements within the function itself. This is done in the + * interest of execution time efficiency. */ + for( ; ; ) + { + taskENTER_CRITICAL(); + { + /* Is there room on the queue now? The running task must be the + * highest priority task wanting to access the queue. If the head item + * in the queue is to be overwritten then it does not matter if the + * queue is full. */ + if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) + { + traceQUEUE_SEND( pxQueue ); + + #if ( configUSE_QUEUE_SETS == 1 ) + { + const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting; + + xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); + + if( pxQueue->pxQueueSetContainer != NULL ) + { + if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) ) + { + /* Do not notify the queue set as an existing item + * was overwritten in the queue so the number of items + * in the queue has not changed. */ + mtCOVERAGE_TEST_MARKER(); + } + else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE ) + { + /* The queue is a member of a queue set, and posting + * to the queue set caused a higher priority task to + * unblock. A context switch is required. */ + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* If there was a task waiting for data to arrive on the + * queue then unblock it now. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The unblocked task has a priority higher than + * our own so yield immediately. Yes it is ok to + * do this from within the critical section - the + * kernel takes care of that. */ + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else if( xYieldRequired != pdFALSE ) + { + /* This path is a special case that will only get + * executed if the task was holding multiple mutexes + * and the mutexes were given back in an order that is + * different to that in which they were taken. */ + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + #else /* configUSE_QUEUE_SETS */ + { + xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); + + /* If there was a task waiting for data to arrive on the + * queue then unblock it now. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The unblocked task has a priority higher than + * our own so yield immediately. Yes it is ok to do + * this from within the critical section - the kernel + * takes care of that. */ + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else if( xYieldRequired != pdFALSE ) + { + /* This path is a special case that will only get + * executed if the task was holding multiple mutexes and + * the mutexes were given back in an order that is + * different to that in which they were taken. */ + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_QUEUE_SETS */ + + taskEXIT_CRITICAL(); + return pdPASS; + } + else + { + if( xTicksToWait == ( TickType_t ) 0 ) + { + /* The queue was full and no block time is specified (or + * the block time has expired) so leave now. */ + taskEXIT_CRITICAL(); + + /* Return to the original privilege level before exiting + * the function. */ + traceQUEUE_SEND_FAILED( pxQueue ); + return errQUEUE_FULL; + } + else if( xEntryTimeSet == pdFALSE ) + { + /* The queue was full and a block time was specified so + * configure the timeout structure. */ + vTaskInternalSetTimeOutState( &xTimeOut ); + xEntryTimeSet = pdTRUE; + } + else + { + /* Entry time was already set. */ + mtCOVERAGE_TEST_MARKER(); + } + } + } + taskEXIT_CRITICAL(); + + /* Interrupts and other tasks can send to and receive from the queue + * now the critical section has been exited. */ + + vTaskSuspendAll(); + prvLockQueue( pxQueue ); + + /* Update the timeout state to see if it has expired yet. */ + if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) + { + if( prvIsQueueFull( pxQueue ) != pdFALSE ) + { + traceBLOCKING_ON_QUEUE_SEND( pxQueue ); + vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); + + /* Unlocking the queue means queue events can effect the + * event list. It is possible that interrupts occurring now + * remove this task from the event list again - but as the + * scheduler is suspended the task will go onto the pending + * ready list instead of the actual ready list. */ + prvUnlockQueue( pxQueue ); + + /* Resuming the scheduler will move tasks from the pending + * ready list into the ready list - so it is feasible that this + * task is already in the ready list before it yields - in which + * case the yield will not cause a context switch unless there + * is also a higher priority task in the pending ready list. */ + if( xTaskResumeAll() == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + } + else + { + /* Try again. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + } + } + else + { + /* The timeout has expired. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + + traceQUEUE_SEND_FAILED( pxQueue ); + return errQUEUE_FULL; + } + } /*lint -restore */ +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, + const void * const pvItemToQueue, + BaseType_t * const pxHigherPriorityTaskWoken, + const BaseType_t xCopyPosition ) +{ + BaseType_t xReturn; + UBaseType_t uxSavedInterruptStatus; + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); + configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); + + /* RTOS ports that support interrupt nesting have the concept of a maximum + * system call (or maximum API call) interrupt priority. Interrupts that are + * above the maximum system call priority are kept permanently enabled, even + * when the RTOS kernel is in a critical section, but cannot make any calls to + * FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h + * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has been + * assigned a priority above the configured maximum system call priority. + * Only FreeRTOS functions that end in FromISR can be called from interrupts + * that have been assigned a priority at or (logically) below the maximum + * system call interrupt priority. FreeRTOS maintains a separate interrupt + * safe API to ensure interrupt entry is as fast and as simple as possible. + * More information (albeit Cortex-M specific) is provided on the following + * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + /* Similar to xQueueGenericSend, except without blocking if there is no room + * in the queue. Also don't directly wake a task that was blocked on a queue + * read, instead return a flag to say whether a context switch is required or + * not (i.e. has a task with a higher priority than us been woken by this + * post). */ + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) + { + const int8_t cTxLock = pxQueue->cTxLock; + const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting; + + traceQUEUE_SEND_FROM_ISR( pxQueue ); + + /* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a + * semaphore or mutex. That means prvCopyDataToQueue() cannot result + * in a task disinheriting a priority and prvCopyDataToQueue() can be + * called here even though the disinherit function does not check if + * the scheduler is suspended before accessing the ready lists. */ + ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); + + /* The event list is not altered if the queue is locked. This will + * be done when the queue is unlocked later. */ + if( cTxLock == queueUNLOCKED ) + { + #if ( configUSE_QUEUE_SETS == 1 ) + { + if( pxQueue->pxQueueSetContainer != NULL ) + { + if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) ) + { + /* Do not notify the queue set as an existing item + * was overwritten in the queue so the number of items + * in the queue has not changed. */ + mtCOVERAGE_TEST_MARKER(); + } + else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE ) + { + /* The queue is a member of a queue set, and posting + * to the queue set caused a higher priority task to + * unblock. A context switch is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority so + * record that a context switch is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + #else /* configUSE_QUEUE_SETS */ + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority so record that a + * context switch is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Not used in this path. */ + ( void ) uxPreviousMessagesWaiting; + } + #endif /* configUSE_QUEUE_SETS */ + } + else + { + /* Increment the lock count so the task that unlocks the queue + * knows that data was posted while it was locked. */ + configASSERT( cTxLock != queueINT8_MAX ); + + pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 ); + } + + xReturn = pdPASS; + } + else + { + traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ); + xReturn = errQUEUE_FULL; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, + BaseType_t * const pxHigherPriorityTaskWoken ) +{ + BaseType_t xReturn; + UBaseType_t uxSavedInterruptStatus; + Queue_t * const pxQueue = xQueue; + + /* Similar to xQueueGenericSendFromISR() but used with semaphores where the + * item size is 0. Don't directly wake a task that was blocked on a queue + * read, instead return a flag to say whether a context switch is required or + * not (i.e. has a task with a higher priority than us been woken by this + * post). */ + + configASSERT( pxQueue ); + + /* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR() + * if the item size is not 0. */ + configASSERT( pxQueue->uxItemSize == 0 ); + + /* Normally a mutex would not be given from an interrupt, especially if + * there is a mutex holder, as priority inheritance makes no sense for an + * interrupts, only tasks. */ + configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) ); + + /* RTOS ports that support interrupt nesting have the concept of a maximum + * system call (or maximum API call) interrupt priority. Interrupts that are + * above the maximum system call priority are kept permanently enabled, even + * when the RTOS kernel is in a critical section, but cannot make any calls to + * FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h + * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has been + * assigned a priority above the configured maximum system call priority. + * Only FreeRTOS functions that end in FromISR can be called from interrupts + * that have been assigned a priority at or (logically) below the maximum + * system call interrupt priority. FreeRTOS maintains a separate interrupt + * safe API to ensure interrupt entry is as fast and as simple as possible. + * More information (albeit Cortex-M specific) is provided on the following + * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; + + /* When the queue is used to implement a semaphore no data is ever + * moved through the queue but it is still valid to see if the queue 'has + * space'. */ + if( uxMessagesWaiting < pxQueue->uxLength ) + { + const int8_t cTxLock = pxQueue->cTxLock; + + traceQUEUE_SEND_FROM_ISR( pxQueue ); + + /* A task can only have an inherited priority if it is a mutex + * holder - and if there is a mutex holder then the mutex cannot be + * given from an ISR. As this is the ISR version of the function it + * can be assumed there is no mutex holder and no need to determine if + * priority disinheritance is needed. Simply increase the count of + * messages (semaphores) available. */ + pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; + + /* The event list is not altered if the queue is locked. This will + * be done when the queue is unlocked later. */ + if( cTxLock == queueUNLOCKED ) + { + #if ( configUSE_QUEUE_SETS == 1 ) + { + if( pxQueue->pxQueueSetContainer != NULL ) + { + if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE ) + { + /* The semaphore is a member of a queue set, and + * posting to the queue set caused a higher priority + * task to unblock. A context switch is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority so + * record that a context switch is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + #else /* configUSE_QUEUE_SETS */ + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority so record that a + * context switch is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_QUEUE_SETS */ + } + else + { + /* Increment the lock count so the task that unlocks the queue + * knows that data was posted while it was locked. */ + configASSERT( cTxLock != queueINT8_MAX ); + + pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 ); + } + + xReturn = pdPASS; + } + else + { + traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ); + xReturn = errQUEUE_FULL; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) +{ + BaseType_t xEntryTimeSet = pdFALSE; + TimeOut_t xTimeOut; + Queue_t * const pxQueue = xQueue; + + /* Check the pointer is not NULL. */ + configASSERT( ( pxQueue ) ); + + /* The buffer into which data is received can only be NULL if the data size + * is zero (so no data is copied into the buffer). */ + configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) ); + + /* Cannot block if the scheduler is suspended. */ + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + /*lint -save -e904 This function relaxes the coding standard somewhat to + * allow return statements within the function itself. This is done in the + * interest of execution time efficiency. */ + for( ; ; ) + { + taskENTER_CRITICAL(); + { + const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; + + /* Is there data in the queue now? To be running the calling task + * must be the highest priority task wanting to access the queue. */ + if( uxMessagesWaiting > ( UBaseType_t ) 0 ) + { + /* Data available, remove one item. */ + prvCopyDataFromQueue( pxQueue, pvBuffer ); + traceQUEUE_RECEIVE( pxQueue ); + pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; + + /* There is now space in the queue, were any tasks waiting to + * post to the queue? If so, unblock the highest priority waiting + * task. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + taskEXIT_CRITICAL(); + return pdPASS; + } + else + { + if( xTicksToWait == ( TickType_t ) 0 ) + { + /* The queue was empty and no block time is specified (or + * the block time has expired) so leave now. */ + taskEXIT_CRITICAL(); + traceQUEUE_RECEIVE_FAILED( pxQueue ); + return errQUEUE_EMPTY; + } + else if( xEntryTimeSet == pdFALSE ) + { + /* The queue was empty and a block time was specified so + * configure the timeout structure. */ + vTaskInternalSetTimeOutState( &xTimeOut ); + xEntryTimeSet = pdTRUE; + } + else + { + /* Entry time was already set. */ + mtCOVERAGE_TEST_MARKER(); + } + } + } + taskEXIT_CRITICAL(); + + /* Interrupts and other tasks can send to and receive from the queue + * now the critical section has been exited. */ + + vTaskSuspendAll(); + prvLockQueue( pxQueue ); + + /* Update the timeout state to see if it has expired yet. */ + if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) + { + /* The timeout has not expired. If the queue is still empty place + * the task on the list of tasks waiting to receive from the queue. */ + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + { + traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); + vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); + prvUnlockQueue( pxQueue ); + + if( xTaskResumeAll() == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* The queue contains data again. Loop back to try and read the + * data. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + } + } + else + { + /* Timed out. If there is no data in the queue exit, otherwise loop + * back and attempt to read the data. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + { + traceQUEUE_RECEIVE_FAILED( pxQueue ); + return errQUEUE_EMPTY; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } /*lint -restore */ +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) +{ + BaseType_t xEntryTimeSet = pdFALSE; + TimeOut_t xTimeOut; + Queue_t * const pxQueue = xQueue; + + #if ( configUSE_MUTEXES == 1 ) + BaseType_t xInheritanceOccurred = pdFALSE; + #endif + + /* Check the queue pointer is not NULL. */ + configASSERT( ( pxQueue ) ); + + /* Check this really is a semaphore, in which case the item size will be + * 0. */ + configASSERT( pxQueue->uxItemSize == 0 ); + + /* Cannot block if the scheduler is suspended. */ + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + /*lint -save -e904 This function relaxes the coding standard somewhat to allow return + * statements within the function itself. This is done in the interest + * of execution time efficiency. */ + for( ; ; ) + { + taskENTER_CRITICAL(); + { + /* Semaphores are queues with an item size of 0, and where the + * number of messages in the queue is the semaphore's count value. */ + const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting; + + /* Is there data in the queue now? To be running the calling task + * must be the highest priority task wanting to access the queue. */ + if( uxSemaphoreCount > ( UBaseType_t ) 0 ) + { + traceQUEUE_RECEIVE( pxQueue ); + + /* Semaphores are queues with a data size of zero and where the + * messages waiting is the semaphore's count. Reduce the count. */ + pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1; + + #if ( configUSE_MUTEXES == 1 ) + { + if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) + { + /* Record the information required to implement + * priority inheritance should it become necessary. */ + pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_MUTEXES */ + + /* Check to see if other tasks are blocked waiting to give the + * semaphore, and if so, unblock the highest priority such task. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + taskEXIT_CRITICAL(); + return pdPASS; + } + else + { + if( xTicksToWait == ( TickType_t ) 0 ) + { + /* For inheritance to have occurred there must have been an + * initial timeout, and an adjusted timeout cannot become 0, as + * if it were 0 the function would have exited. */ + #if ( configUSE_MUTEXES == 1 ) + { + configASSERT( xInheritanceOccurred == pdFALSE ); + } + #endif /* configUSE_MUTEXES */ + + /* The semaphore count was 0 and no block time is specified + * (or the block time has expired) so exit now. */ + taskEXIT_CRITICAL(); + traceQUEUE_RECEIVE_FAILED( pxQueue ); + return errQUEUE_EMPTY; + } + else if( xEntryTimeSet == pdFALSE ) + { + /* The semaphore count was 0 and a block time was specified + * so configure the timeout structure ready to block. */ + vTaskInternalSetTimeOutState( &xTimeOut ); + xEntryTimeSet = pdTRUE; + } + else + { + /* Entry time was already set. */ + mtCOVERAGE_TEST_MARKER(); + } + } + } + taskEXIT_CRITICAL(); + + /* Interrupts and other tasks can give to and take from the semaphore + * now the critical section has been exited. */ + + vTaskSuspendAll(); + prvLockQueue( pxQueue ); + + /* Update the timeout state to see if it has expired yet. */ + if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) + { + /* A block time is specified and not expired. If the semaphore + * count is 0 then enter the Blocked state to wait for a semaphore to + * become available. As semaphores are implemented with queues the + * queue being empty is equivalent to the semaphore count being 0. */ + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + { + traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); + + #if ( configUSE_MUTEXES == 1 ) + { + if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) + { + taskENTER_CRITICAL(); + { + xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder ); + } + taskEXIT_CRITICAL(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* if ( configUSE_MUTEXES == 1 ) */ + + vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); + prvUnlockQueue( pxQueue ); + + if( xTaskResumeAll() == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* There was no timeout and the semaphore count was not 0, so + * attempt to take the semaphore again. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + } + } + else + { + /* Timed out. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + + /* If the semaphore count is 0 exit now as the timeout has + * expired. Otherwise return to attempt to take the semaphore that is + * known to be available. As semaphores are implemented by queues the + * queue being empty is equivalent to the semaphore count being 0. */ + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + { + #if ( configUSE_MUTEXES == 1 ) + { + /* xInheritanceOccurred could only have be set if + * pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to + * test the mutex type again to check it is actually a mutex. */ + if( xInheritanceOccurred != pdFALSE ) + { + taskENTER_CRITICAL(); + { + UBaseType_t uxHighestWaitingPriority; + + /* This task blocking on the mutex caused another + * task to inherit this task's priority. Now this task + * has timed out the priority should be disinherited + * again, but only as low as the next highest priority + * task that is waiting for the same mutex. */ + uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue ); + vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority ); + } + taskEXIT_CRITICAL(); + } + } + #endif /* configUSE_MUTEXES */ + + traceQUEUE_RECEIVE_FAILED( pxQueue ); + return errQUEUE_EMPTY; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } /*lint -restore */ +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) +{ + BaseType_t xEntryTimeSet = pdFALSE; + TimeOut_t xTimeOut; + int8_t * pcOriginalReadPosition; + Queue_t * const pxQueue = xQueue; + + /* Check the pointer is not NULL. */ + configASSERT( ( pxQueue ) ); + + /* The buffer into which data is received can only be NULL if the data size + * is zero (so no data is copied into the buffer. */ + configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) ); + + /* Cannot block if the scheduler is suspended. */ + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + /*lint -save -e904 This function relaxes the coding standard somewhat to + * allow return statements within the function itself. This is done in the + * interest of execution time efficiency. */ + for( ; ; ) + { + taskENTER_CRITICAL(); + { + const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; + + /* Is there data in the queue now? To be running the calling task + * must be the highest priority task wanting to access the queue. */ + if( uxMessagesWaiting > ( UBaseType_t ) 0 ) + { + /* Remember the read position so it can be reset after the data + * is read from the queue as this function is only peeking the + * data, not removing it. */ + pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom; + + prvCopyDataFromQueue( pxQueue, pvBuffer ); + traceQUEUE_PEEK( pxQueue ); + + /* The data is not being removed, so reset the read pointer. */ + pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition; + + /* The data is being left in the queue, so see if there are + * any other tasks waiting for the data. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority than this task. */ + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + taskEXIT_CRITICAL(); + return pdPASS; + } + else + { + if( xTicksToWait == ( TickType_t ) 0 ) + { + /* The queue was empty and no block time is specified (or + * the block time has expired) so leave now. */ + taskEXIT_CRITICAL(); + traceQUEUE_PEEK_FAILED( pxQueue ); + return errQUEUE_EMPTY; + } + else if( xEntryTimeSet == pdFALSE ) + { + /* The queue was empty and a block time was specified so + * configure the timeout structure ready to enter the blocked + * state. */ + vTaskInternalSetTimeOutState( &xTimeOut ); + xEntryTimeSet = pdTRUE; + } + else + { + /* Entry time was already set. */ + mtCOVERAGE_TEST_MARKER(); + } + } + } + taskEXIT_CRITICAL(); + + /* Interrupts and other tasks can send to and receive from the queue + * now that the critical section has been exited. */ + + vTaskSuspendAll(); + prvLockQueue( pxQueue ); + + /* Update the timeout state to see if it has expired yet. */ + if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) + { + /* Timeout has not expired yet, check to see if there is data in the + * queue now, and if not enter the Blocked state to wait for data. */ + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + { + traceBLOCKING_ON_QUEUE_PEEK( pxQueue ); + vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); + prvUnlockQueue( pxQueue ); + + if( xTaskResumeAll() == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* There is data in the queue now, so don't enter the blocked + * state, instead return to try and obtain the data. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + } + } + else + { + /* The timeout has expired. If there is still no data in the queue + * exit, otherwise go back and try to read the data again. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + { + traceQUEUE_PEEK_FAILED( pxQueue ); + return errQUEUE_EMPTY; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } /*lint -restore */ +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, + void * const pvBuffer, + BaseType_t * const pxHigherPriorityTaskWoken ) +{ + BaseType_t xReturn; + UBaseType_t uxSavedInterruptStatus; + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); + + /* RTOS ports that support interrupt nesting have the concept of a maximum + * system call (or maximum API call) interrupt priority. Interrupts that are + * above the maximum system call priority are kept permanently enabled, even + * when the RTOS kernel is in a critical section, but cannot make any calls to + * FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h + * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has been + * assigned a priority above the configured maximum system call priority. + * Only FreeRTOS functions that end in FromISR can be called from interrupts + * that have been assigned a priority at or (logically) below the maximum + * system call interrupt priority. FreeRTOS maintains a separate interrupt + * safe API to ensure interrupt entry is as fast and as simple as possible. + * More information (albeit Cortex-M specific) is provided on the following + * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; + + /* Cannot block in an ISR, so check there is data available. */ + if( uxMessagesWaiting > ( UBaseType_t ) 0 ) + { + const int8_t cRxLock = pxQueue->cRxLock; + + traceQUEUE_RECEIVE_FROM_ISR( pxQueue ); + + prvCopyDataFromQueue( pxQueue, pvBuffer ); + pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; + + /* If the queue is locked the event list will not be modified. + * Instead update the lock count so the task that unlocks the queue + * will know that an ISR has removed data while the queue was + * locked. */ + if( cRxLock == queueUNLOCKED ) + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + /* The task waiting has a higher priority than us so + * force a context switch. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* Increment the lock count so the task that unlocks the queue + * knows that data was removed while it was locked. */ + configASSERT( cRxLock != queueINT8_MAX ); + + pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 ); + } + + xReturn = pdPASS; + } + else + { + xReturn = pdFAIL; + traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, + void * const pvBuffer ) +{ + BaseType_t xReturn; + UBaseType_t uxSavedInterruptStatus; + int8_t * pcOriginalReadPosition; + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); + configASSERT( pxQueue->uxItemSize != 0 ); /* Can't peek a semaphore. */ + + /* RTOS ports that support interrupt nesting have the concept of a maximum + * system call (or maximum API call) interrupt priority. Interrupts that are + * above the maximum system call priority are kept permanently enabled, even + * when the RTOS kernel is in a critical section, but cannot make any calls to + * FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h + * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has been + * assigned a priority above the configured maximum system call priority. + * Only FreeRTOS functions that end in FromISR can be called from interrupts + * that have been assigned a priority at or (logically) below the maximum + * system call interrupt priority. FreeRTOS maintains a separate interrupt + * safe API to ensure interrupt entry is as fast and as simple as possible. + * More information (albeit Cortex-M specific) is provided on the following + * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Cannot block in an ISR, so check there is data available. */ + if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 ) + { + traceQUEUE_PEEK_FROM_ISR( pxQueue ); + + /* Remember the read position so it can be reset as nothing is + * actually being removed from the queue. */ + pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom; + prvCopyDataFromQueue( pxQueue, pvBuffer ); + pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition; + + xReturn = pdPASS; + } + else + { + xReturn = pdFAIL; + traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue ); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) +{ + UBaseType_t uxReturn; + + configASSERT( xQueue ); + + taskENTER_CRITICAL(); + { + uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting; + } + taskEXIT_CRITICAL(); + + return uxReturn; +} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */ +/*-----------------------------------------------------------*/ + +UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) +{ + UBaseType_t uxReturn; + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + + taskENTER_CRITICAL(); + { + uxReturn = pxQueue->uxLength - pxQueue->uxMessagesWaiting; + } + taskEXIT_CRITICAL(); + + return uxReturn; +} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */ +/*-----------------------------------------------------------*/ + +UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) +{ + UBaseType_t uxReturn; + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + uxReturn = pxQueue->uxMessagesWaiting; + + return uxReturn; +} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */ +/*-----------------------------------------------------------*/ + +void vQueueDelete( QueueHandle_t xQueue ) +{ + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + traceQUEUE_DELETE( pxQueue ); + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + { + vQueueUnregisterQueue( pxQueue ); + } + #endif + + #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) ) + { + /* The queue can only have been allocated dynamically - free it + * again. */ + vPortFree( pxQueue ); + } + #elif ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + { + /* The queue could have been allocated statically or dynamically, so + * check before attempting to free the memory. */ + if( pxQueue->ucStaticallyAllocated == ( uint8_t ) pdFALSE ) + { + vPortFree( pxQueue ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #else /* if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) ) */ + { + /* The queue must have been statically allocated, so is not going to be + * deleted. Avoid compiler warnings about the unused parameter. */ + ( void ) pxQueue; + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) + { + return ( ( Queue_t * ) xQueue )->uxQueueNumber; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + void vQueueSetQueueNumber( QueueHandle_t xQueue, + UBaseType_t uxQueueNumber ) + { + ( ( Queue_t * ) xQueue )->uxQueueNumber = uxQueueNumber; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) + { + return ( ( Queue_t * ) xQueue )->ucQueueType; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_MUTEXES == 1 ) + + static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) + { + UBaseType_t uxHighestPriorityOfWaitingTasks; + + /* If a task waiting for a mutex causes the mutex holder to inherit a + * priority, but the waiting task times out, then the holder should + * disinherit the priority - but only down to the highest priority of any + * other tasks that are waiting for the same mutex. For this purpose, + * return the priority of the highest priority task that is waiting for the + * mutex. */ + if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U ) + { + uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) ); + } + else + { + uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY; + } + + return uxHighestPriorityOfWaitingTasks; + } + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, + const void * pvItemToQueue, + const BaseType_t xPosition ) +{ + BaseType_t xReturn = pdFALSE; + UBaseType_t uxMessagesWaiting; + + /* This function is called from a critical section. */ + + uxMessagesWaiting = pxQueue->uxMessagesWaiting; + + if( pxQueue->uxItemSize == ( UBaseType_t ) 0 ) + { + #if ( configUSE_MUTEXES == 1 ) + { + if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) + { + /* The mutex is no longer being held. */ + xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder ); + pxQueue->u.xSemaphore.xMutexHolder = NULL; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_MUTEXES */ + } + else if( xPosition == queueSEND_TO_BACK ) + { + ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ + pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ + + if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ + { + pxQueue->pcWriteTo = pxQueue->pcHead; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */ + pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize; + + if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ + { + pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xPosition == queueOVERWRITE ) + { + if( uxMessagesWaiting > ( UBaseType_t ) 0 ) + { + /* An item is not being added but overwritten, so subtract + * one from the recorded number of items in the queue so when + * one is added again below the number of recorded items remains + * correct. */ + --uxMessagesWaiting; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static void prvCopyDataFromQueue( Queue_t * const pxQueue, + void * const pvBuffer ) +{ + if( pxQueue->uxItemSize != ( UBaseType_t ) 0 ) + { + pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ + + if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */ + { + pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ + } +} +/*-----------------------------------------------------------*/ + +static void prvUnlockQueue( Queue_t * const pxQueue ) +{ + /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */ + + /* The lock counts contains the number of extra data items placed or + * removed from the queue while the queue was locked. When a queue is + * locked items can be added or removed, but the event lists cannot be + * updated. */ + taskENTER_CRITICAL(); + { + int8_t cTxLock = pxQueue->cTxLock; + + /* See if data was added to the queue while it was locked. */ + while( cTxLock > queueLOCKED_UNMODIFIED ) + { + /* Data was posted while the queue was locked. Are any tasks + * blocked waiting for data to become available? */ + #if ( configUSE_QUEUE_SETS == 1 ) + { + if( pxQueue->pxQueueSetContainer != NULL ) + { + if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE ) + { + /* The queue is a member of a queue set, and posting to + * the queue set caused a higher priority task to unblock. + * A context switch is required. */ + vTaskMissedYield(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* Tasks that are removed from the event list will get + * added to the pending ready list as the scheduler is still + * suspended. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority so record that a + * context switch is required. */ + vTaskMissedYield(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + break; + } + } + } + #else /* configUSE_QUEUE_SETS */ + { + /* Tasks that are removed from the event list will get added to + * the pending ready list as the scheduler is still suspended. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority so record that + * a context switch is required. */ + vTaskMissedYield(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + break; + } + } + #endif /* configUSE_QUEUE_SETS */ + + --cTxLock; + } + + pxQueue->cTxLock = queueUNLOCKED; + } + taskEXIT_CRITICAL(); + + /* Do the same for the Rx lock. */ + taskENTER_CRITICAL(); + { + int8_t cRxLock = pxQueue->cRxLock; + + while( cRxLock > queueLOCKED_UNMODIFIED ) + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + vTaskMissedYield(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + --cRxLock; + } + else + { + break; + } + } + + pxQueue->cRxLock = queueUNLOCKED; + } + taskEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvIsQueueEmpty( const Queue_t * pxQueue ) +{ + BaseType_t xReturn; + + taskENTER_CRITICAL(); + { + if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + } + taskEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) +{ + BaseType_t xReturn; + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + + if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; +} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ +/*-----------------------------------------------------------*/ + +static BaseType_t prvIsQueueFull( const Queue_t * pxQueue ) +{ + BaseType_t xReturn; + + taskENTER_CRITICAL(); + { + if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + } + taskEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) +{ + BaseType_t xReturn; + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + + if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; +} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_CO_ROUTINES == 1 ) + + BaseType_t xQueueCRSend( QueueHandle_t xQueue, + const void * pvItemToQueue, + TickType_t xTicksToWait ) + { + BaseType_t xReturn; + Queue_t * const pxQueue = xQueue; + + /* If the queue is already full we may have to block. A critical section + * is required to prevent an interrupt removing something from the queue + * between the check to see if the queue is full and blocking on the queue. */ + portDISABLE_INTERRUPTS(); + { + if( prvIsQueueFull( pxQueue ) != pdFALSE ) + { + /* The queue is full - do we want to block or just leave without + * posting? */ + if( xTicksToWait > ( TickType_t ) 0 ) + { + /* As this is called from a coroutine we cannot block directly, but + * return indicating that we need to block. */ + vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) ); + portENABLE_INTERRUPTS(); + return errQUEUE_BLOCKED; + } + else + { + portENABLE_INTERRUPTS(); + return errQUEUE_FULL; + } + } + } + portENABLE_INTERRUPTS(); + + portDISABLE_INTERRUPTS(); + { + if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) + { + /* There is room in the queue, copy the data into the queue. */ + prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK ); + xReturn = pdPASS; + + /* Were any co-routines waiting for data to become available? */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + /* In this instance the co-routine could be placed directly + * into the ready list as we are within a critical section. + * Instead the same pending ready list mechanism is used as if + * the event were caused from within an interrupt. */ + if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The co-routine waiting has a higher priority so record + * that a yield might be appropriate. */ + xReturn = errQUEUE_YIELD; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + xReturn = errQUEUE_FULL; + } + } + portENABLE_INTERRUPTS(); + + return xReturn; + } + +#endif /* configUSE_CO_ROUTINES */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_CO_ROUTINES == 1 ) + + BaseType_t xQueueCRReceive( QueueHandle_t xQueue, + void * pvBuffer, + TickType_t xTicksToWait ) + { + BaseType_t xReturn; + Queue_t * const pxQueue = xQueue; + + /* If the queue is already empty we may have to block. A critical section + * is required to prevent an interrupt adding something to the queue + * between the check to see if the queue is empty and blocking on the queue. */ + portDISABLE_INTERRUPTS(); + { + if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) + { + /* There are no messages in the queue, do we want to block or just + * leave with nothing? */ + if( xTicksToWait > ( TickType_t ) 0 ) + { + /* As this is a co-routine we cannot block directly, but return + * indicating that we need to block. */ + vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) ); + portENABLE_INTERRUPTS(); + return errQUEUE_BLOCKED; + } + else + { + portENABLE_INTERRUPTS(); + return errQUEUE_FULL; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + portENABLE_INTERRUPTS(); + + portDISABLE_INTERRUPTS(); + { + if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 ) + { + /* Data is available from the queue. */ + pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; + + if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) + { + pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + --( pxQueue->uxMessagesWaiting ); + ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); + + xReturn = pdPASS; + + /* Were any co-routines waiting for space to become available? */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + { + /* In this instance the co-routine could be placed directly + * into the ready list as we are within a critical section. + * Instead the same pending ready list mechanism is used as if + * the event were caused from within an interrupt. */ + if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + xReturn = errQUEUE_YIELD; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + xReturn = pdFAIL; + } + } + portENABLE_INTERRUPTS(); + + return xReturn; + } + +#endif /* configUSE_CO_ROUTINES */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_CO_ROUTINES == 1 ) + + BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, + const void * pvItemToQueue, + BaseType_t xCoRoutinePreviouslyWoken ) + { + Queue_t * const pxQueue = xQueue; + + /* Cannot block within an ISR so if there is no space on the queue then + * exit without doing anything. */ + if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) + { + prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK ); + + /* We only want to wake one co-routine per ISR, so check that a + * co-routine has not already been woken. */ + if( xCoRoutinePreviouslyWoken == pdFALSE ) + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + return pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xCoRoutinePreviouslyWoken; + } + +#endif /* configUSE_CO_ROUTINES */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_CO_ROUTINES == 1 ) + + BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, + void * pvBuffer, + BaseType_t * pxCoRoutineWoken ) + { + BaseType_t xReturn; + Queue_t * const pxQueue = xQueue; + + /* We cannot block from an ISR, so check there is data available. If + * not then just leave without doing anything. */ + if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 ) + { + /* Copy the data from the queue. */ + pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; + + if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) + { + pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + --( pxQueue->uxMessagesWaiting ); + ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); + + if( ( *pxCoRoutineWoken ) == pdFALSE ) + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + { + if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + *pxCoRoutineWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xReturn = pdPASS; + } + else + { + xReturn = pdFAIL; + } + + return xReturn; + } + +#endif /* configUSE_CO_ROUTINES */ +/*-----------------------------------------------------------*/ + +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + { + UBaseType_t ux; + + configASSERT( xQueue ); + + QueueRegistryItem_t * pxEntryToWrite = NULL; + + if( pcQueueName != NULL ) + { + /* See if there is an empty space in the registry. A NULL name denotes + * a free slot. */ + for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) + { + /* Replace an existing entry if the queue is already in the registry. */ + if( xQueue == xQueueRegistry[ ux ].xHandle ) + { + pxEntryToWrite = &( xQueueRegistry[ ux ] ); + break; + } + /* Otherwise, store in the next empty location */ + else if( ( pxEntryToWrite == NULL ) && ( xQueueRegistry[ ux ].pcQueueName == NULL ) ) + { + pxEntryToWrite = &( xQueueRegistry[ ux ] ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + + if( pxEntryToWrite != NULL ) + { + /* Store the information on this queue. */ + pxEntryToWrite->pcQueueName = pcQueueName; + pxEntryToWrite->xHandle = xQueue; + + traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName ); + } + } + +#endif /* configQUEUE_REGISTRY_SIZE */ +/*-----------------------------------------------------------*/ + +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + + const char * pcQueueGetName( QueueHandle_t xQueue ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + { + UBaseType_t ux; + const char * pcReturn = NULL; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + + configASSERT( xQueue ); + + /* Note there is nothing here to protect against another task adding or + * removing entries from the registry while it is being searched. */ + + for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) + { + if( xQueueRegistry[ ux ].xHandle == xQueue ) + { + pcReturn = xQueueRegistry[ ux ].pcQueueName; + break; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + return pcReturn; + } /*lint !e818 xQueue cannot be a pointer to const because it is a typedef. */ + +#endif /* configQUEUE_REGISTRY_SIZE */ +/*-----------------------------------------------------------*/ + +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void vQueueUnregisterQueue( QueueHandle_t xQueue ) + { + UBaseType_t ux; + + configASSERT( xQueue ); + + /* See if the handle of the queue being unregistered in actually in the + * registry. */ + for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) + { + if( xQueueRegistry[ ux ].xHandle == xQueue ) + { + /* Set the name to NULL to show that this slot if free again. */ + xQueueRegistry[ ux ].pcQueueName = NULL; + + /* Set the handle to NULL to ensure the same queue handle cannot + * appear in the registry twice if it is added, removed, then + * added again. */ + xQueueRegistry[ ux ].xHandle = ( QueueHandle_t ) 0; + break; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ + +#endif /* configQUEUE_REGISTRY_SIZE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TIMERS == 1 ) + + void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, + TickType_t xTicksToWait, + const BaseType_t xWaitIndefinitely ) + { + Queue_t * const pxQueue = xQueue; + + /* This function should not be called by application code hence the + * 'Restricted' in its name. It is not part of the public API. It is + * designed for use by kernel code, and has special calling requirements. + * It can result in vListInsert() being called on a list that can only + * possibly ever have one item in it, so the list will be fast, but even + * so it should be called with the scheduler locked and not from a critical + * section. */ + + /* Only do anything if there are no messages in the queue. This function + * will not actually cause the task to block, just place it on a blocked + * list. It will not block until the scheduler is unlocked - at which + * time a yield will be performed. If an item is added to the queue while + * the queue is locked, and the calling task blocks on the queue, then the + * calling task will be immediately unblocked when the queue is unlocked. */ + prvLockQueue( pxQueue ); + + if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U ) + { + /* There is nothing in the queue, block for the specified period. */ + vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + prvUnlockQueue( pxQueue ); + } + +#endif /* configUSE_TIMERS */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + + QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) + { + QueueSetHandle_t pxQueue; + + pxQueue = xQueueGenericCreate( uxEventQueueLength, ( UBaseType_t ) sizeof( Queue_t * ), queueQUEUE_TYPE_SET ); + + return pxQueue; + } + +#endif /* configUSE_QUEUE_SETS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_QUEUE_SETS == 1 ) + + BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) + { + BaseType_t xReturn; + + taskENTER_CRITICAL(); + { + if( ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer != NULL ) + { + /* Cannot add a queue/semaphore to more than one queue set. */ + xReturn = pdFAIL; + } + else if( ( ( Queue_t * ) xQueueOrSemaphore )->uxMessagesWaiting != ( UBaseType_t ) 0 ) + { + /* Cannot add a queue/semaphore to a queue set if there are already + * items in the queue/semaphore. */ + xReturn = pdFAIL; + } + else + { + ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer = xQueueSet; + xReturn = pdPASS; + } + } + taskEXIT_CRITICAL(); + + return xReturn; + } + +#endif /* configUSE_QUEUE_SETS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_QUEUE_SETS == 1 ) + + BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) + { + BaseType_t xReturn; + Queue_t * const pxQueueOrSemaphore = ( Queue_t * ) xQueueOrSemaphore; + + if( pxQueueOrSemaphore->pxQueueSetContainer != xQueueSet ) + { + /* The queue was not a member of the set. */ + xReturn = pdFAIL; + } + else if( pxQueueOrSemaphore->uxMessagesWaiting != ( UBaseType_t ) 0 ) + { + /* It is dangerous to remove a queue from a set when the queue is + * not empty because the queue set will still hold pending events for + * the queue. */ + xReturn = pdFAIL; + } + else + { + taskENTER_CRITICAL(); + { + /* The queue is no longer contained in the set. */ + pxQueueOrSemaphore->pxQueueSetContainer = NULL; + } + taskEXIT_CRITICAL(); + xReturn = pdPASS; + } + + return xReturn; + } /*lint !e818 xQueueSet could not be declared as pointing to const as it is a typedef. */ + +#endif /* configUSE_QUEUE_SETS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_QUEUE_SETS == 1 ) + + QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + TickType_t const xTicksToWait ) + { + QueueSetMemberHandle_t xReturn = NULL; + + ( void ) xQueueReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait ); /*lint !e961 Casting from one typedef to another is not redundant. */ + return xReturn; + } + +#endif /* configUSE_QUEUE_SETS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_QUEUE_SETS == 1 ) + + QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) + { + QueueSetMemberHandle_t xReturn = NULL; + + ( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL ); /*lint !e961 Casting from one typedef to another is not redundant. */ + return xReturn; + } + +#endif /* configUSE_QUEUE_SETS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_QUEUE_SETS == 1 ) + + static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue ) + { + Queue_t * pxQueueSetContainer = pxQueue->pxQueueSetContainer; + BaseType_t xReturn = pdFALSE; + + /* This function must be called form a critical section. */ + + /* The following line is not reachable in unit tests because every call + * to prvNotifyQueueSetContainer is preceded by a check that + * pxQueueSetContainer != NULL */ + configASSERT( pxQueueSetContainer ); /* LCOV_EXCL_BR_LINE */ + configASSERT( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength ); + + if( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength ) + { + const int8_t cTxLock = pxQueueSetContainer->cTxLock; + + traceQUEUE_SET_SEND( pxQueueSetContainer ); + + /* The data copied is the handle of the queue that contains data. */ + xReturn = prvCopyDataToQueue( pxQueueSetContainer, &pxQueue, queueSEND_TO_BACK ); + + if( cTxLock == queueUNLOCKED ) + { + if( listLIST_IS_EMPTY( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority. */ + xReturn = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + configASSERT( cTxLock != queueINT8_MAX ); + + pxQueueSetContainer->cTxLock = ( int8_t ) ( cTxLock + 1 ); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xReturn; + } + +#endif /* configUSE_QUEUE_SETS */ diff --git a/hw-libs/freertos/stream_buffer.c b/hw-libs/freertos/stream_buffer.c new file mode 100644 index 000000000..adca5f7bf --- /dev/null +++ b/hw-libs/freertos/stream_buffer.c @@ -0,0 +1,1310 @@ +/* + * FreeRTOS Kernel V10.4.6 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "stream_buffer.h" + +#if ( configUSE_TASK_NOTIFICATIONS != 1 ) + #error configUSE_TASK_NOTIFICATIONS must be set to 1 to build stream_buffer.c +#endif + +/* Lint e961, e9021 and e750 are suppressed as a MISRA exception justified + * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined + * for the header files above, but not in this file, in order to generate the + * correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */ + +/* If the user has not provided application specific Rx notification macros, + * or #defined the notification macros away, then provide default implementations + * that uses task notifications. */ +/*lint -save -e9026 Function like macros allowed and needed here so they can be overridden. */ +#ifndef sbRECEIVE_COMPLETED + #define sbRECEIVE_COMPLETED( pxStreamBuffer ) \ + vTaskSuspendAll(); \ + { \ + if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL ) \ + { \ + ( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToSend, \ + ( uint32_t ) 0, \ + eNoAction ); \ + ( pxStreamBuffer )->xTaskWaitingToSend = NULL; \ + } \ + } \ + ( void ) xTaskResumeAll(); +#endif /* sbRECEIVE_COMPLETED */ + +#ifndef sbRECEIVE_COMPLETED_FROM_ISR + #define sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, \ + pxHigherPriorityTaskWoken ) \ + { \ + UBaseType_t uxSavedInterruptStatus; \ + \ + uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR(); \ + { \ + if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL ) \ + { \ + ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend, \ + ( uint32_t ) 0, \ + eNoAction, \ + pxHigherPriorityTaskWoken ); \ + ( pxStreamBuffer )->xTaskWaitingToSend = NULL; \ + } \ + } \ + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); \ + } +#endif /* sbRECEIVE_COMPLETED_FROM_ISR */ + +/* If the user has not provided an application specific Tx notification macro, + * or #defined the notification macro away, them provide a default implementation + * that uses task notifications. */ +#ifndef sbSEND_COMPLETED + #define sbSEND_COMPLETED( pxStreamBuffer ) \ + vTaskSuspendAll(); \ + { \ + if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL ) \ + { \ + ( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToReceive, \ + ( uint32_t ) 0, \ + eNoAction ); \ + ( pxStreamBuffer )->xTaskWaitingToReceive = NULL; \ + } \ + } \ + ( void ) xTaskResumeAll(); +#endif /* sbSEND_COMPLETED */ + +#ifndef sbSEND_COMPLETE_FROM_ISR + #define sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ) \ + { \ + UBaseType_t uxSavedInterruptStatus; \ + \ + uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR(); \ + { \ + if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL ) \ + { \ + ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive, \ + ( uint32_t ) 0, \ + eNoAction, \ + pxHigherPriorityTaskWoken ); \ + ( pxStreamBuffer )->xTaskWaitingToReceive = NULL; \ + } \ + } \ + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); \ + } +#endif /* sbSEND_COMPLETE_FROM_ISR */ +/*lint -restore (9026) */ + +/* The number of bytes used to hold the length of a message in the buffer. */ +#define sbBYTES_TO_STORE_MESSAGE_LENGTH ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) ) + +/* Bits stored in the ucFlags field of the stream buffer. */ +#define sbFLAGS_IS_MESSAGE_BUFFER ( ( uint8_t ) 1 ) /* Set if the stream buffer was created as a message buffer, in which case it holds discrete messages rather than a stream. */ +#define sbFLAGS_IS_STATICALLY_ALLOCATED ( ( uint8_t ) 2 ) /* Set if the stream buffer was created using statically allocated memory. */ + +/*-----------------------------------------------------------*/ + +/* Structure that hold state information on the buffer. */ +typedef struct StreamBufferDef_t /*lint !e9058 Style convention uses tag. */ +{ + volatile size_t xTail; /* Index to the next item to read within the buffer. */ + volatile size_t xHead; /* Index to the next item to write within the buffer. */ + size_t xLength; /* The length of the buffer pointed to by pucBuffer. */ + size_t xTriggerLevelBytes; /* The number of bytes that must be in the stream buffer before a task that is waiting for data is unblocked. */ + volatile TaskHandle_t xTaskWaitingToReceive; /* Holds the handle of a task waiting for data, or NULL if no tasks are waiting. */ + volatile TaskHandle_t xTaskWaitingToSend; /* Holds the handle of a task waiting to send data to a message buffer that is full. */ + uint8_t * pucBuffer; /* Points to the buffer itself - that is - the RAM that stores the data passed through the buffer. */ + uint8_t ucFlags; + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxStreamBufferNumber; /* Used for tracing purposes. */ + #endif +} StreamBuffer_t; + +/* + * The number of bytes available to be read from the buffer. + */ +static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) PRIVILEGED_FUNCTION; + +/* + * Add xCount bytes from pucData into the pxStreamBuffer's data storage area. + * This function does not update the buffer's xHead pointer, so multiple writes + * may be chained together "atomically". This is useful for Message Buffers where + * the length and data bytes are written in two separate chunks, and we don't want + * the reader to see the buffer as having grown until after all data is copied over. + * This function takes a custom xHead value to indicate where to write to (necessary + * for chaining) and returns the the resulting xHead position. + * To mark the write as complete, manually set the buffer's xHead field with the + * returned xHead from this function. + */ +static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, + const uint8_t * pucData, + size_t xCount, + size_t xHead ) PRIVILEGED_FUNCTION; + +/* + * If the stream buffer is being used as a message buffer, then reads an entire + * message out of the buffer. If the stream buffer is being used as a stream + * buffer then read as many bytes as possible from the buffer. + * prvReadBytesFromBuffer() is called to actually extract the bytes from the + * buffer's data storage area. + */ +static size_t prvReadMessageFromBuffer( StreamBuffer_t * pxStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + size_t xBytesAvailable ) PRIVILEGED_FUNCTION; + +/* + * If the stream buffer is being used as a message buffer, then writes an entire + * message to the buffer. If the stream buffer is being used as a stream + * buffer then write as many bytes as possible to the buffer. + * prvWriteBytestoBuffer() is called to actually send the bytes to the buffer's + * data storage area. + */ +static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + size_t xSpace, + size_t xRequiredSpace ) PRIVILEGED_FUNCTION; + +/* + * Copies xCount bytes from the pxStreamBuffer's data storage area to pucData. + * This function does not update the buffer's xTail pointer, so multiple reads + * may be chained together "atomically". This is useful for Message Buffers where + * the length and data bytes are read in two separate chunks, and we don't want + * the writer to see the buffer as having more free space until after all data is + * copied over, especially if we have to abort the read due to insufficient receiving space. + * This function takes a custom xTail value to indicate where to read from (necessary + * for chaining) and returns the the resulting xTail position. + * To mark the read as complete, manually set the buffer's xTail field with the + * returned xTail from this function. + */ +static size_t prvReadBytesFromBuffer( StreamBuffer_t * pxStreamBuffer, + uint8_t * pucData, + size_t xCount, + size_t xTail ) PRIVILEGED_FUNCTION; + +/* + * Called by both pxStreamBufferCreate() and pxStreamBufferCreateStatic() to + * initialise the members of the newly created stream buffer structure. + */ +static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, + uint8_t * const pucBuffer, + size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + uint8_t ucFlags ) PRIVILEGED_FUNCTION; + +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) +#if 0 /* Inertial Sense - use static allocation for stream buffers, this + throws a compiler warning because of an unaligned cast */ + + StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xIsMessageBuffer ) + { + uint8_t * pucAllocatedMemory; + uint8_t ucFlags; + + /* In case the stream buffer is going to be used as a message buffer + * (that is, it will hold discrete messages with a little meta data that + * says how big the next message is) check the buffer will be large enough + * to hold at least one message. */ + if( xIsMessageBuffer == pdTRUE ) + { + /* Is a message buffer but not statically allocated. */ + ucFlags = sbFLAGS_IS_MESSAGE_BUFFER; + configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH ); + } + else + { + /* Not a message buffer and not statically allocated. */ + ucFlags = 0; + configASSERT( xBufferSizeBytes > 0 ); + } + + configASSERT( xTriggerLevelBytes <= xBufferSizeBytes ); + + /* A trigger level of 0 would cause a waiting task to unblock even when + * the buffer was empty. */ + if( xTriggerLevelBytes == ( size_t ) 0 ) + { + xTriggerLevelBytes = ( size_t ) 1; + } + + /* A stream buffer requires a StreamBuffer_t structure and a buffer. + * Both are allocated in a single call to pvPortMalloc(). The + * StreamBuffer_t structure is placed at the start of the allocated memory + * and the buffer follows immediately after. The requested size is + * incremented so the free space is returned as the user would expect - + * this is a quirk of the implementation that means otherwise the free + * space would be reported as one byte smaller than would be logically + * expected. */ + if( xBufferSizeBytes < ( xBufferSizeBytes + 1 + sizeof( StreamBuffer_t ) ) ) + { + xBufferSizeBytes++; + pucAllocatedMemory = ( uint8_t * ) pvPortMalloc( xBufferSizeBytes + sizeof( StreamBuffer_t ) ); /*lint !e9079 malloc() only returns void*. */ + } + else + { + pucAllocatedMemory = NULL; + } + + if( pucAllocatedMemory != NULL ) + { + prvInitialiseNewStreamBuffer( ( StreamBuffer_t * ) pucAllocatedMemory, /* Structure at the start of the allocated memory. */ /*lint !e9087 Safe cast as allocated memory is aligned. */ /*lint !e826 Area is not too small and alignment is guaranteed provided malloc() behaves as expected and returns aligned buffer. */ + pucAllocatedMemory + sizeof( StreamBuffer_t ), /* Storage area follows. */ /*lint !e9016 Indexing past structure valid for uint8_t pointer, also storage area has no alignment requirement. */ + xBufferSizeBytes, + xTriggerLevelBytes, + ucFlags ); + + traceSTREAM_BUFFER_CREATE( ( ( StreamBuffer_t * ) pucAllocatedMemory ), xIsMessageBuffer ); + } + else + { + traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer ); + } + + return ( StreamBufferHandle_t ) pucAllocatedMemory; /*lint !e9087 !e826 Safe cast as allocated memory is aligned. */ + } + +#endif /* Inertial Sense */ +#endif /* configSUPPORT_DYNAMIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + + StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xIsMessageBuffer, + uint8_t * const pucStreamBufferStorageArea, + StaticStreamBuffer_t * const pxStaticStreamBuffer ) + { + StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) pxStaticStreamBuffer; /*lint !e740 !e9087 Safe cast as StaticStreamBuffer_t is opaque Streambuffer_t. */ + StreamBufferHandle_t xReturn; + uint8_t ucFlags; + + configASSERT( pucStreamBufferStorageArea ); + configASSERT( pxStaticStreamBuffer ); + configASSERT( xTriggerLevelBytes <= xBufferSizeBytes ); + + /* A trigger level of 0 would cause a waiting task to unblock even when + * the buffer was empty. */ + if( xTriggerLevelBytes == ( size_t ) 0 ) + { + xTriggerLevelBytes = ( size_t ) 1; + } + + if( xIsMessageBuffer != pdFALSE ) + { + /* Statically allocated message buffer. */ + ucFlags = sbFLAGS_IS_MESSAGE_BUFFER | sbFLAGS_IS_STATICALLY_ALLOCATED; + } + else + { + /* Statically allocated stream buffer. */ + ucFlags = sbFLAGS_IS_STATICALLY_ALLOCATED; + } + + /* In case the stream buffer is going to be used as a message buffer + * (that is, it will hold discrete messages with a little meta data that + * says how big the next message is) check the buffer will be large enough + * to hold at least one message. */ + configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH ); + + #if ( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + * variable of type StaticStreamBuffer_t equals the size of the real + * message buffer structure. */ + volatile size_t xSize = sizeof( StaticStreamBuffer_t ); + configASSERT( xSize == sizeof( StreamBuffer_t ) ); + } /*lint !e529 xSize is referenced is configASSERT() is defined. */ + #endif /* configASSERT_DEFINED */ + + if( ( pucStreamBufferStorageArea != NULL ) && ( pxStaticStreamBuffer != NULL ) ) + { + prvInitialiseNewStreamBuffer( pxStreamBuffer, + pucStreamBufferStorageArea, + xBufferSizeBytes, + xTriggerLevelBytes, + ucFlags ); + + /* Remember this was statically allocated in case it is ever deleted + * again. */ + pxStreamBuffer->ucFlags |= sbFLAGS_IS_STATICALLY_ALLOCATED; + + traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer ); + + xReturn = ( StreamBufferHandle_t ) pxStaticStreamBuffer; /*lint !e9087 Data hiding requires cast to opaque type. */ + } + else + { + xReturn = NULL; + traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer ); + } + + return xReturn; + } + +#endif /* ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ +/*-----------------------------------------------------------*/ + +void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) +{ + StreamBuffer_t * pxStreamBuffer = xStreamBuffer; + + configASSERT( pxStreamBuffer ); + + traceSTREAM_BUFFER_DELETE( xStreamBuffer ); + + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) pdFALSE ) + { + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + /* Both the structure and the buffer were allocated using a single call + * to pvPortMalloc(), hence only one call to vPortFree() is required. */ + vPortFree( ( void * ) pxStreamBuffer ); /*lint !e9087 Standard free() semantics require void *, plus pxStreamBuffer was allocated by pvPortMalloc(). */ + } + #else + { + /* Should not be possible to get here, ucFlags must be corrupt. + * Force an assert. */ + configASSERT( xStreamBuffer == ( StreamBufferHandle_t ) ~0 ); + } + #endif + } + else + { + /* The structure and buffer were not allocated dynamically and cannot be + * freed - just scrub the structure so future use will assert. */ + ( void ) memset( pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); + } +} +/*-----------------------------------------------------------*/ + +BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + BaseType_t xReturn = pdFAIL; + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxStreamBufferNumber; + #endif + + configASSERT( pxStreamBuffer ); + + #if ( configUSE_TRACE_FACILITY == 1 ) + { + /* Store the stream buffer number so it can be restored after the + * reset. */ + uxStreamBufferNumber = pxStreamBuffer->uxStreamBufferNumber; + } + #endif + + /* Can only reset a message buffer if there are no tasks blocked on it. */ + taskENTER_CRITICAL(); + { + if( pxStreamBuffer->xTaskWaitingToReceive == NULL ) + { + if( pxStreamBuffer->xTaskWaitingToSend == NULL ) + { + prvInitialiseNewStreamBuffer( pxStreamBuffer, + pxStreamBuffer->pucBuffer, + pxStreamBuffer->xLength, + pxStreamBuffer->xTriggerLevelBytes, + pxStreamBuffer->ucFlags ); + xReturn = pdPASS; + + #if ( configUSE_TRACE_FACILITY == 1 ) + { + pxStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber; + } + #endif + + traceSTREAM_BUFFER_RESET( xStreamBuffer ); + } + } + } + taskEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + BaseType_t xReturn; + + configASSERT( pxStreamBuffer ); + + /* It is not valid for the trigger level to be 0. */ + if( xTriggerLevel == ( size_t ) 0 ) + { + xTriggerLevel = ( size_t ) 1; + } + + /* The trigger level is the number of bytes that must be in the stream + * buffer before a task that is waiting for data is unblocked. */ + if( xTriggerLevel < pxStreamBuffer->xLength ) + { + pxStreamBuffer->xTriggerLevelBytes = xTriggerLevel; + xReturn = pdPASS; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) +{ + const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + size_t xSpace; + size_t xOriginalTail; + + configASSERT( pxStreamBuffer ); + + /* The code below reads xTail and then xHead. This is safe if the stream + * buffer is updated once between the two reads - but not if the stream buffer + * is updated more than once between the two reads - hence the loop. */ + do + { + xOriginalTail = pxStreamBuffer->xTail; + xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail; + xSpace -= pxStreamBuffer->xHead; + } while( xOriginalTail != pxStreamBuffer->xTail ); + + xSpace -= ( size_t ) 1; + + if( xSpace >= pxStreamBuffer->xLength ) + { + xSpace -= pxStreamBuffer->xLength; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xSpace; +} +/*-----------------------------------------------------------*/ + +size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) +{ + const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + size_t xReturn; + + configASSERT( pxStreamBuffer ); + + xReturn = prvBytesInBuffer( pxStreamBuffer ); + return xReturn; +} +/*-----------------------------------------------------------*/ + +size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + size_t xReturn, xSpace = 0; + size_t xRequiredSpace = xDataLengthBytes; + TimeOut_t xTimeOut; + size_t xMaxReportedSpace = 0; + + configASSERT( pvTxData ); + configASSERT( pxStreamBuffer ); + + /* The maximum amount of space a stream buffer will ever report is its length + * minus 1. */ + xMaxReportedSpace = pxStreamBuffer->xLength - ( size_t ) 1; + + /* This send function is used to write to both message buffers and stream + * buffers. If this is a message buffer then the space needed must be + * increased by the amount of bytes needed to store the length of the + * message. */ + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) + { + xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH; + + /* Overflow? */ + configASSERT( xRequiredSpace > xDataLengthBytes ); + + /* If this is a message buffer then it must be possible to write the + * whole message. */ + if( xRequiredSpace > xMaxReportedSpace ) + { + /* The message would not fit even if the entire buffer was empty, + * so don't wait for space. */ + xTicksToWait = ( TickType_t ) 0; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* If this is a stream buffer then it is acceptable to write only part + * of the message to the buffer. Cap the length to the total length of + * the buffer. */ + if( xRequiredSpace > xMaxReportedSpace ) + { + xRequiredSpace = xMaxReportedSpace; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + if( xTicksToWait != ( TickType_t ) 0 ) + { + vTaskSetTimeOutState( &xTimeOut ); + + do + { + /* Wait until the required number of bytes are free in the message + * buffer. */ + taskENTER_CRITICAL(); + { + xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer ); + + if( xSpace < xRequiredSpace ) + { + /* Clear notification state as going to wait for space. */ + ( void ) xTaskNotifyStateClear( NULL ); + + /* Should only be one writer. */ + configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL ); + pxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle(); + } + else + { + taskEXIT_CRITICAL(); + break; + } + } + taskEXIT_CRITICAL(); + + traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer ); + ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait ); + pxStreamBuffer->xTaskWaitingToSend = NULL; + } while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xSpace == ( size_t ) 0 ) + { + xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace ); + + if( xReturn > ( size_t ) 0 ) + { + traceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn ); + + /* Was a task waiting for the data? */ + if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes ) + { + sbSEND_COMPLETED( pxStreamBuffer ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer ); + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + BaseType_t * const pxHigherPriorityTaskWoken ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + size_t xReturn, xSpace; + size_t xRequiredSpace = xDataLengthBytes; + + configASSERT( pvTxData ); + configASSERT( pxStreamBuffer ); + + /* This send function is used to write to both message buffers and stream + * buffers. If this is a message buffer then the space needed must be + * increased by the amount of bytes needed to store the length of the + * message. */ + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) + { + xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer ); + xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace ); + + if( xReturn > ( size_t ) 0 ) + { + /* Was a task waiting for the data? */ + if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes ) + { + sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xReturn ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + size_t xSpace, + size_t xRequiredSpace ) +{ + size_t xNextHead = pxStreamBuffer->xHead; + + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) + { + /* This is a message buffer, as opposed to a stream buffer. */ + + if( xSpace >= xRequiredSpace ) + { + /* There is enough space to write both the message length and the message + * itself into the buffer. Start by writing the length of the data, the data + * itself will be written later in this function. */ + xNextHead = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xDataLengthBytes ), sbBYTES_TO_STORE_MESSAGE_LENGTH, xNextHead ); + } + else + { + /* Not enough space, so do not write data to the buffer. */ + xDataLengthBytes = 0; + } + } + else + { + /* This is a stream buffer, as opposed to a message buffer, so writing a + * stream of bytes rather than discrete messages. Plan to write as many + * bytes as possible. */ + xDataLengthBytes = configMIN( xDataLengthBytes, xSpace ); + } + + if( xDataLengthBytes != ( size_t ) 0 ) + { + /* Write the data to the buffer. */ + pxStreamBuffer->xHead = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes, xNextHead ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alignment and access. */ + } + + return xDataLengthBytes; +} +/*-----------------------------------------------------------*/ + +size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength; + + configASSERT( pvRxData ); + configASSERT( pxStreamBuffer ); + + /* This receive function is used by both message buffers, which store + * discrete messages, and stream buffers, which store a continuous stream of + * bytes. Discrete messages include an additional + * sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the + * message. */ + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) + { + xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH; + } + else + { + xBytesToStoreMessageLength = 0; + } + + if( xTicksToWait != ( TickType_t ) 0 ) + { + /* Checking if there is data and clearing the notification state must be + * performed atomically. */ + taskENTER_CRITICAL(); + { + xBytesAvailable = prvBytesInBuffer( pxStreamBuffer ); + + /* If this function was invoked by a message buffer read then + * xBytesToStoreMessageLength holds the number of bytes used to hold + * the length of the next discrete message. If this function was + * invoked by a stream buffer read then xBytesToStoreMessageLength will + * be 0. */ + if( xBytesAvailable <= xBytesToStoreMessageLength ) + { + /* Clear notification state as going to wait for data. */ + ( void ) xTaskNotifyStateClear( NULL ); + + /* Should only be one reader. */ + configASSERT( pxStreamBuffer->xTaskWaitingToReceive == NULL ); + pxStreamBuffer->xTaskWaitingToReceive = xTaskGetCurrentTaskHandle(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + if( xBytesAvailable <= xBytesToStoreMessageLength ) + { + /* Wait for data to be available. */ + traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer ); + ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait ); + pxStreamBuffer->xTaskWaitingToReceive = NULL; + + /* Recheck the data available after blocking. */ + xBytesAvailable = prvBytesInBuffer( pxStreamBuffer ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + xBytesAvailable = prvBytesInBuffer( pxStreamBuffer ); + } + + /* Whether receiving a discrete message (where xBytesToStoreMessageLength + * holds the number of bytes used to store the message length) or a stream of + * bytes (where xBytesToStoreMessageLength is zero), the number of bytes + * available must be greater than xBytesToStoreMessageLength to be able to + * read bytes from the buffer. */ + if( xBytesAvailable > xBytesToStoreMessageLength ) + { + xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable ); + + /* Was a task waiting for space in the buffer? */ + if( xReceivedLength != ( size_t ) 0 ) + { + traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength ); + sbRECEIVE_COMPLETED( pxStreamBuffer ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer ); + mtCOVERAGE_TEST_MARKER(); + } + + return xReceivedLength; +} +/*-----------------------------------------------------------*/ + +size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + size_t xReturn, xBytesAvailable; + configMESSAGE_BUFFER_LENGTH_TYPE xTempReturn; + + configASSERT( pxStreamBuffer ); + + /* Ensure the stream buffer is being used as a message buffer. */ + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) + { + xBytesAvailable = prvBytesInBuffer( pxStreamBuffer ); + + if( xBytesAvailable > sbBYTES_TO_STORE_MESSAGE_LENGTH ) + { + /* The number of bytes available is greater than the number of bytes + * required to hold the length of the next message, so another message + * is available. */ + ( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempReturn, sbBYTES_TO_STORE_MESSAGE_LENGTH, pxStreamBuffer->xTail ); + xReturn = ( size_t ) xTempReturn; + } + else + { + /* The minimum amount of bytes in a message buffer is + * ( sbBYTES_TO_STORE_MESSAGE_LENGTH + 1 ), so if xBytesAvailable is + * less than sbBYTES_TO_STORE_MESSAGE_LENGTH the only other valid + * value is 0. */ + configASSERT( xBytesAvailable == 0 ); + xReturn = 0; + } + } + else + { + xReturn = 0; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + BaseType_t * const pxHigherPriorityTaskWoken ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength; + + configASSERT( pvRxData ); + configASSERT( pxStreamBuffer ); + + /* This receive function is used by both message buffers, which store + * discrete messages, and stream buffers, which store a continuous stream of + * bytes. Discrete messages include an additional + * sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the + * message. */ + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) + { + xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH; + } + else + { + xBytesToStoreMessageLength = 0; + } + + xBytesAvailable = prvBytesInBuffer( pxStreamBuffer ); + + /* Whether receiving a discrete message (where xBytesToStoreMessageLength + * holds the number of bytes used to store the message length) or a stream of + * bytes (where xBytesToStoreMessageLength is zero), the number of bytes + * available must be greater than xBytesToStoreMessageLength to be able to + * read bytes from the buffer. */ + if( xBytesAvailable > xBytesToStoreMessageLength ) + { + xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable ); + + /* Was a task waiting for space in the buffer? */ + if( xReceivedLength != ( size_t ) 0 ) + { + sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength ); + + return xReceivedLength; +} +/*-----------------------------------------------------------*/ + +static size_t prvReadMessageFromBuffer( StreamBuffer_t * pxStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + size_t xBytesAvailable ) +{ + size_t xCount, xNextMessageLength; + configMESSAGE_BUFFER_LENGTH_TYPE xTempNextMessageLength; + size_t xNextTail = pxStreamBuffer->xTail; + + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) + { + /* A discrete message is being received. First receive the length + * of the message. */ + xNextTail = prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempNextMessageLength, sbBYTES_TO_STORE_MESSAGE_LENGTH, xNextTail ); + xNextMessageLength = ( size_t ) xTempNextMessageLength; + + /* Reduce the number of bytes available by the number of bytes just + * read out. */ + xBytesAvailable -= sbBYTES_TO_STORE_MESSAGE_LENGTH; + + /* Check there is enough space in the buffer provided by the + * user. */ + if( xNextMessageLength > xBufferLengthBytes ) + { + /* The user has provided insufficient space to read the message. */ + xNextMessageLength = 0; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* A stream of bytes is being received (as opposed to a discrete + * message), so read as many bytes as possible. */ + xNextMessageLength = xBufferLengthBytes; + } + + /* Use the minimum of the wanted bytes and the available bytes. */ + xCount = configMIN( xNextMessageLength, xBytesAvailable ); + + if( xCount != ( size_t ) 0 ) + { + /* Read the actual data and update the tail to mark the data as officially consumed. */ + pxStreamBuffer->xTail = prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) pvRxData, xCount, xNextTail ); /*lint !e9079 Data storage area is implemented as uint8_t array for ease of sizing, indexing and alignment. */ + } + + return xCount; +} +/*-----------------------------------------------------------*/ + +BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) +{ + const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + BaseType_t xReturn; + size_t xTail; + + configASSERT( pxStreamBuffer ); + + /* True if no bytes are available. */ + xTail = pxStreamBuffer->xTail; + + if( pxStreamBuffer->xHead == xTail ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) +{ + BaseType_t xReturn; + size_t xBytesToStoreMessageLength; + const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + + configASSERT( pxStreamBuffer ); + + /* This generic version of the receive function is used by both message + * buffers, which store discrete messages, and stream buffers, which store a + * continuous stream of bytes. Discrete messages include an additional + * sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the message. */ + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) + { + xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH; + } + else + { + xBytesToStoreMessageLength = 0; + } + + /* True if the available space equals zero. */ + if( xStreamBufferSpacesAvailable( xStreamBuffer ) <= xBytesToStoreMessageLength ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, + BaseType_t * pxHigherPriorityTaskWoken ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + BaseType_t xReturn; + UBaseType_t uxSavedInterruptStatus; + + configASSERT( pxStreamBuffer ); + + uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR(); + { + if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL ) + { + ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive, + ( uint32_t ) 0, + eNoAction, + pxHigherPriorityTaskWoken ); + ( pxStreamBuffer )->xTaskWaitingToReceive = NULL; + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, + BaseType_t * pxHigherPriorityTaskWoken ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + BaseType_t xReturn; + UBaseType_t uxSavedInterruptStatus; + + configASSERT( pxStreamBuffer ); + + uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR(); + { + if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL ) + { + ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend, + ( uint32_t ) 0, + eNoAction, + pxHigherPriorityTaskWoken ); + ( pxStreamBuffer )->xTaskWaitingToSend = NULL; + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, + const uint8_t * pucData, + size_t xCount, + size_t xHead ) +{ + size_t xFirstLength; + + configASSERT( xCount > ( size_t ) 0 ); + + /* Calculate the number of bytes that can be added in the first write - + * which may be less than the total number of bytes that need to be added if + * the buffer will wrap back to the beginning. */ + xFirstLength = configMIN( pxStreamBuffer->xLength - xHead, xCount ); + + /* Write as many bytes as can be written in the first write. */ + configASSERT( ( xHead + xFirstLength ) <= pxStreamBuffer->xLength ); + ( void ) memcpy( ( void * ) ( &( pxStreamBuffer->pucBuffer[ xHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */ + + /* If the number of bytes written was less than the number that could be + * written in the first write... */ + if( xCount > xFirstLength ) + { + /* ...then write the remaining bytes to the start of the buffer. */ + configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength ); + ( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xHead += xCount; + + if( xHead >= pxStreamBuffer->xLength ) + { + xHead -= pxStreamBuffer->xLength; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xHead; +} +/*-----------------------------------------------------------*/ + +static size_t prvReadBytesFromBuffer( StreamBuffer_t * pxStreamBuffer, + uint8_t * pucData, + size_t xCount, + size_t xTail ) +{ + size_t xFirstLength; + + configASSERT( xCount != ( size_t ) 0 ); + + /* Calculate the number of bytes that can be read - which may be + * less than the number wanted if the data wraps around to the start of + * the buffer. */ + xFirstLength = configMIN( pxStreamBuffer->xLength - xTail, xCount ); + + /* Obtain the number of bytes it is possible to obtain in the first + * read. Asserts check bounds of read and write. */ + configASSERT( xFirstLength <= xCount ); + configASSERT( ( xTail + xFirstLength ) <= pxStreamBuffer->xLength ); + ( void ) memcpy( ( void * ) pucData, ( const void * ) &( pxStreamBuffer->pucBuffer[ xTail ] ), xFirstLength ); /*lint !e9087 memcpy() requires void *. */ + + /* If the total number of wanted bytes is greater than the number + * that could be read in the first read... */ + if( xCount > xFirstLength ) + { + /* ...then read the remaining bytes from the start of the buffer. */ + ( void ) memcpy( ( void * ) &( pucData[ xFirstLength ] ), ( void * ) ( pxStreamBuffer->pucBuffer ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Move the tail pointer to effectively remove the data read from the buffer. */ + xTail += xCount; + + if( xTail >= pxStreamBuffer->xLength ) + { + xTail -= pxStreamBuffer->xLength; + } + + return xTail; +} +/*-----------------------------------------------------------*/ + +static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) +{ +/* Returns the distance between xTail and xHead. */ + size_t xCount; + + xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead; + xCount -= pxStreamBuffer->xTail; + + if( xCount >= pxStreamBuffer->xLength ) + { + xCount -= pxStreamBuffer->xLength; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xCount; +} +/*-----------------------------------------------------------*/ + +static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, + uint8_t * const pucBuffer, + size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + uint8_t ucFlags ) +{ + /* Assert here is deliberately writing to the entire buffer to ensure it can + * be written to without generating exceptions, and is setting the buffer to a + * known value to assist in development/debugging. */ + #if ( configASSERT_DEFINED == 1 ) + { + /* The value written just has to be identifiable when looking at the + * memory. Don't use 0xA5 as that is the stack fill value and could + * result in confusion as to what is actually being observed. */ + const BaseType_t xWriteValue = 0x55; + configASSERT( memset( pucBuffer, ( int ) xWriteValue, xBufferSizeBytes ) == pucBuffer ); + } /*lint !e529 !e438 xWriteValue is only used if configASSERT() is defined. */ + #endif + + ( void ) memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); /*lint !e9087 memset() requires void *. */ + pxStreamBuffer->pucBuffer = pucBuffer; + pxStreamBuffer->xLength = xBufferSizeBytes; + pxStreamBuffer->xTriggerLevelBytes = xTriggerLevelBytes; + pxStreamBuffer->ucFlags = ucFlags; +} + +#if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) + { + return xStreamBuffer->uxStreamBufferNumber; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, + UBaseType_t uxStreamBufferNumber ) + { + xStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer ) + { + return( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ); + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ diff --git a/hw-libs/freertos/tasks.c b/hw-libs/freertos/tasks.c new file mode 100644 index 000000000..b2e892ca1 --- /dev/null +++ b/hw-libs/freertos/tasks.c @@ -0,0 +1,5458 @@ +/* + * FreeRTOS Kernel V10.4.6 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "stack_macros.h" + +/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified + * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined + * for the header files above, but not in this file, in order to generate the + * correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */ + +/* Set configUSE_STATS_FORMATTING_FUNCTIONS to 2 to include the stats formatting + * functions but without including stdio.h here. */ +#if ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) + +/* At the bottom of this file are two optional functions that can be used + * to generate human readable text from the raw data generated by the + * uxTaskGetSystemState() function. Note the formatting functions are provided + * for convenience only, and are NOT considered part of the kernel. */ + #include +#endif /* configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) */ + +#if ( configUSE_PREEMPTION == 0 ) + +/* If the cooperative scheduler is being used then a yield should not be + * performed just because a higher priority task has been woken. */ + #define taskYIELD_IF_USING_PREEMPTION() +#else + #define taskYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API() +#endif + +/* Values that can be assigned to the ucNotifyState member of the TCB. */ +#define taskNOT_WAITING_NOTIFICATION ( ( uint8_t ) 0 ) /* Must be zero as it is the initialised value. */ +#define taskWAITING_NOTIFICATION ( ( uint8_t ) 1 ) +#define taskNOTIFICATION_RECEIVED ( ( uint8_t ) 2 ) + +/* + * The value used to fill the stack of a task when the task is created. This + * is used purely for checking the high water mark for tasks. + */ +#define tskSTACK_FILL_BYTE ( 0xa5U ) + +/* Bits used to record how a task's stack and TCB were allocated. */ +#define tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB ( ( uint8_t ) 0 ) +#define tskSTATICALLY_ALLOCATED_STACK_ONLY ( ( uint8_t ) 1 ) +#define tskSTATICALLY_ALLOCATED_STACK_AND_TCB ( ( uint8_t ) 2 ) + +/* If any of the following are set then task stacks are filled with a known + * value so the high water mark can be determined. If none of the following are + * set then don't fill the stack so there is no unnecessary dependency on memset. */ +#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) + #define tskSET_NEW_STACKS_TO_KNOWN_VALUE 1 +#else + #define tskSET_NEW_STACKS_TO_KNOWN_VALUE 0 +#endif + +/* + * Macros used by vListTask to indicate which state a task is in. + */ +#define tskRUNNING_CHAR ( 'X' ) +#define tskBLOCKED_CHAR ( 'B' ) +#define tskREADY_CHAR ( 'R' ) +#define tskDELETED_CHAR ( 'D' ) +#define tskSUSPENDED_CHAR ( 'S' ) + +/* + * Some kernel aware debuggers require the data the debugger needs access to to + * be global, rather than file scope. + */ +#ifdef portREMOVE_STATIC_QUALIFIER + #define static +#endif + +/* The name allocated to the Idle task. This can be overridden by defining + * configIDLE_TASK_NAME in FreeRTOSConfig.h. */ +#ifndef configIDLE_TASK_NAME + #define configIDLE_TASK_NAME "IDLE" +#endif + +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 ) + +/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 0 then task selection is + * performed in a generic way that is not optimised to any particular + * microcontroller architecture. */ + +/* uxTopReadyPriority holds the priority of the highest priority ready + * state task. */ + #define taskRECORD_READY_PRIORITY( uxPriority ) \ + { \ + if( ( uxPriority ) > uxTopReadyPriority ) \ + { \ + uxTopReadyPriority = ( uxPriority ); \ + } \ + } /* taskRECORD_READY_PRIORITY */ + +/*-----------------------------------------------------------*/ + + #define taskSELECT_HIGHEST_PRIORITY_TASK() \ + { \ + UBaseType_t uxTopPriority = uxTopReadyPriority; \ + \ + /* Find the highest priority queue that contains ready tasks. */ \ + while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopPriority ] ) ) ) \ + { \ + configASSERT( uxTopPriority ); \ + --uxTopPriority; \ + } \ + \ + /* listGET_OWNER_OF_NEXT_ENTRY indexes through the list, so the tasks of \ + * the same priority get an equal share of the processor time. */ \ + listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) ); \ + uxTopReadyPriority = uxTopPriority; \ + } /* taskSELECT_HIGHEST_PRIORITY_TASK */ + +/*-----------------------------------------------------------*/ + +/* Define away taskRESET_READY_PRIORITY() and portRESET_READY_PRIORITY() as + * they are only required when a port optimised method of task selection is + * being used. */ + #define taskRESET_READY_PRIORITY( uxPriority ) + #define portRESET_READY_PRIORITY( uxPriority, uxTopReadyPriority ) + +#else /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 1 then task selection is + * performed in a way that is tailored to the particular microcontroller + * architecture being used. */ + +/* A port optimised version is provided. Call the port defined macros. */ + #define taskRECORD_READY_PRIORITY( uxPriority ) portRECORD_READY_PRIORITY( uxPriority, uxTopReadyPriority ) + +/*-----------------------------------------------------------*/ + + #define taskSELECT_HIGHEST_PRIORITY_TASK() \ + { \ + UBaseType_t uxTopPriority; \ + \ + /* Find the highest priority list that contains ready tasks. */ \ + portGET_HIGHEST_PRIORITY( uxTopPriority, uxTopReadyPriority ); \ + configASSERT( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ uxTopPriority ] ) ) > 0 ); \ + listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) ); \ + } /* taskSELECT_HIGHEST_PRIORITY_TASK() */ + +/*-----------------------------------------------------------*/ + +/* A port optimised version is provided, call it only if the TCB being reset + * is being referenced from a ready list. If it is referenced from a delayed + * or suspended list then it won't be in a ready list. */ + #define taskRESET_READY_PRIORITY( uxPriority ) \ + { \ + if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ ( uxPriority ) ] ) ) == ( UBaseType_t ) 0 ) \ + { \ + portRESET_READY_PRIORITY( ( uxPriority ), ( uxTopReadyPriority ) ); \ + } \ + } + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/*-----------------------------------------------------------*/ + +/* pxDelayedTaskList and pxOverflowDelayedTaskList are switched when the tick + * count overflows. */ +#define taskSWITCH_DELAYED_LISTS() \ + { \ + List_t * pxTemp; \ + \ + /* The delayed tasks list should be empty when the lists are switched. */ \ + configASSERT( ( listLIST_IS_EMPTY( pxDelayedTaskList ) ) ); \ + \ + pxTemp = pxDelayedTaskList; \ + pxDelayedTaskList = pxOverflowDelayedTaskList; \ + pxOverflowDelayedTaskList = pxTemp; \ + xNumOfOverflows++; \ + prvResetNextTaskUnblockTime(); \ + } + +/*-----------------------------------------------------------*/ + +/* + * Place the task represented by pxTCB into the appropriate ready list for + * the task. It is inserted at the end of the list. + */ +#define prvAddTaskToReadyList( pxTCB ) \ + traceMOVED_TASK_TO_READY_STATE( pxTCB ); \ + taskRECORD_READY_PRIORITY( ( pxTCB )->uxPriority ); \ + listINSERT_END( &( pxReadyTasksLists[ ( pxTCB )->uxPriority ] ), &( ( pxTCB )->xStateListItem ) ); \ + tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB ) +/*-----------------------------------------------------------*/ + +/* + * Several functions take a TaskHandle_t parameter that can optionally be NULL, + * where NULL is used to indicate that the handle of the currently executing + * task should be used in place of the parameter. This macro simply checks to + * see if the parameter is NULL and returns a pointer to the appropriate TCB. + */ +#define prvGetTCBFromHandle( pxHandle ) ( ( ( pxHandle ) == NULL ) ? pxCurrentTCB : ( pxHandle ) ) + +/* The item value of the event list item is normally used to hold the priority + * of the task to which it belongs (coded to allow it to be held in reverse + * priority order). However, it is occasionally borrowed for other purposes. It + * is important its value is not updated due to a task priority change while it is + * being used for another purpose. The following bit definition is used to inform + * the scheduler that the value should not be changed - in which case it is the + * responsibility of whichever module is using the value to ensure it gets set back + * to its original value when it is released. */ +#if ( configUSE_16_BIT_TICKS == 1 ) + #define taskEVENT_LIST_ITEM_VALUE_IN_USE 0x8000U +#else + #define taskEVENT_LIST_ITEM_VALUE_IN_USE 0x80000000UL +#endif + +/* + * Task control block. A task control block (TCB) is allocated for each task, + * and stores task state information, including a pointer to the task's context + * (the task's run time environment, including register values) + */ +typedef struct tskTaskControlBlock /* The old naming convention is used to prevent breaking kernel aware debuggers. */ +{ + volatile StackType_t * pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack. THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */ + + #if ( portUSING_MPU_WRAPPERS == 1 ) + xMPU_SETTINGS xMPUSettings; /*< The MPU settings are defined as part of the port layer. THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */ + #endif + + ListItem_t xStateListItem; /*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */ + ListItem_t xEventListItem; /*< Used to reference a task from an event list. */ + UBaseType_t uxPriority; /*< The priority of the task. 0 is the lowest priority. */ + StackType_t * pxStack; /*< Points to the start of the stack. */ + char pcTaskName[ configMAX_TASK_NAME_LEN ]; /*< Descriptive name given to the task when created. Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + + #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) + StackType_t * pxEndOfStack; /*< Points to the highest valid address for the stack. */ + #endif + + #if ( portCRITICAL_NESTING_IN_TCB == 1 ) + UBaseType_t uxCriticalNesting; /*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */ + #endif + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxTCBNumber; /*< Stores a number that increments each time a TCB is created. It allows debuggers to determine when a task has been deleted and then recreated. */ + UBaseType_t uxTaskNumber; /*< Stores a number specifically for use by third party trace code. */ + #endif + + #if ( configUSE_MUTEXES == 1 ) + UBaseType_t uxBasePriority; /*< The priority last assigned to the task - used by the priority inheritance mechanism. */ + UBaseType_t uxMutexesHeld; + #endif + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + TaskHookFunction_t pxTaskTag; + #endif + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 ) + void * pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ]; + #endif + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + configRUN_TIME_COUNTER_TYPE ulRunTimeCounter; /*< Stores the amount of time the task has spent in the Running state. */ + #endif + + #if ( configUSE_NEWLIB_REENTRANT == 1 ) + + /* Allocate a Newlib reent structure that is specific to this task. + * Note Newlib support has been included by popular demand, but is not + * used by the FreeRTOS maintainers themselves. FreeRTOS is not + * responsible for resulting newlib operation. User must be familiar with + * newlib and must provide system-wide implementations of the necessary + * stubs. Be warned that (at the time of writing) the current newlib design + * implements a system-wide malloc() that must be provided with locks. + * + * See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html + * for additional information. */ + struct _reent xNewLib_reent; + #endif + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + volatile uint32_t ulNotifiedValue[ configTASK_NOTIFICATION_ARRAY_ENTRIES ]; + volatile uint8_t ucNotifyState[ configTASK_NOTIFICATION_ARRAY_ENTRIES ]; + #endif + + /* See the comments in FreeRTOS.h with the definition of + * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */ + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ + uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */ + #endif + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + uint8_t ucDelayAborted; + #endif + + #if ( configUSE_POSIX_ERRNO == 1 ) + int iTaskErrno; + #endif +} tskTCB; + +/* The old tskTCB name is maintained above then typedefed to the new TCB_t name + * below to enable the use of older kernel aware debuggers. */ +typedef tskTCB TCB_t; + +/*lint -save -e956 A manual analysis and inspection has been used to determine + * which static variables must be declared volatile. */ +PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL; + +/* Lists for ready and blocked tasks. -------------------- + * xDelayedTaskList1 and xDelayedTaskList2 could be moved to function scope but + * doing so breaks some kernel aware debuggers and debuggers that rely on removing + * the static qualifier. */ +PRIVILEGED_DATA static List_t pxReadyTasksLists[ configMAX_PRIORITIES ]; /*< Prioritised ready tasks. */ +PRIVILEGED_DATA static List_t xDelayedTaskList1; /*< Delayed tasks. */ +PRIVILEGED_DATA static List_t xDelayedTaskList2; /*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */ +PRIVILEGED_DATA static List_t * volatile pxDelayedTaskList; /*< Points to the delayed task list currently being used. */ +PRIVILEGED_DATA static List_t * volatile pxOverflowDelayedTaskList; /*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */ +PRIVILEGED_DATA static List_t xPendingReadyList; /*< Tasks that have been readied while the scheduler was suspended. They will be moved to the ready list when the scheduler is resumed. */ + +#if ( INCLUDE_vTaskDelete == 1 ) + + PRIVILEGED_DATA static List_t xTasksWaitingTermination; /*< Tasks that have been deleted - but their memory not yet freed. */ + PRIVILEGED_DATA static volatile UBaseType_t uxDeletedTasksWaitingCleanUp = ( UBaseType_t ) 0U; + +#endif + +#if ( INCLUDE_vTaskSuspend == 1 ) + + PRIVILEGED_DATA static List_t xSuspendedTaskList; /*< Tasks that are currently suspended. */ + +#endif + +/* Global POSIX errno. Its value is changed upon context switching to match + * the errno of the currently running task. */ +#if ( configUSE_POSIX_ERRNO == 1 ) + int FreeRTOS_errno = 0; +#endif + +/* Other file private variables. --------------------------------*/ +PRIVILEGED_DATA static volatile UBaseType_t uxCurrentNumberOfTasks = ( UBaseType_t ) 0U; +PRIVILEGED_DATA static volatile TickType_t xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT; +PRIVILEGED_DATA static volatile UBaseType_t uxTopReadyPriority = tskIDLE_PRIORITY; +PRIVILEGED_DATA static volatile BaseType_t xSchedulerRunning = pdFALSE; +PRIVILEGED_DATA static volatile TickType_t xPendedTicks = ( TickType_t ) 0U; +PRIVILEGED_DATA static volatile BaseType_t xYieldPending = pdFALSE; +PRIVILEGED_DATA static volatile BaseType_t xNumOfOverflows = ( BaseType_t ) 0; +PRIVILEGED_DATA static UBaseType_t uxTaskNumber = ( UBaseType_t ) 0U; +PRIVILEGED_DATA static volatile TickType_t xNextTaskUnblockTime = ( TickType_t ) 0U; /* Initialised to portMAX_DELAY before the scheduler starts. */ +PRIVILEGED_DATA static TaskHandle_t xIdleTaskHandle = NULL; /*< Holds the handle of the idle task. The idle task is created automatically when the scheduler is started. */ + +/* Improve support for OpenOCD. The kernel tracks Ready tasks via priority lists. + * For tracking the state of remote threads, OpenOCD uses uxTopUsedPriority + * to determine the number of priority lists to read back from the remote target. */ +const volatile UBaseType_t uxTopUsedPriority = configMAX_PRIORITIES - 1U; + +/* Context switches are held pending while the scheduler is suspended. Also, + * interrupts must not manipulate the xStateListItem of a TCB, or any of the + * lists the xStateListItem can be referenced from, if the scheduler is suspended. + * If an interrupt needs to unblock a task while the scheduler is suspended then it + * moves the task's event list item into the xPendingReadyList, ready for the + * kernel to move the task from the pending ready list into the real ready list + * when the scheduler is unsuspended. The pending ready list itself can only be + * accessed from a critical section. */ +PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended = ( UBaseType_t ) pdFALSE; + +#if ( configGENERATE_RUN_TIME_STATS == 1 ) + +/* Do not move these variables to function scope as doing so prevents the + * code working with debuggers that need to remove the static qualifier. */ + PRIVILEGED_DATA static configRUN_TIME_COUNTER_TYPE ulTaskSwitchedInTime = 0UL; /*< Holds the value of a timer/counter the last time a task was switched in. */ + PRIVILEGED_DATA static volatile configRUN_TIME_COUNTER_TYPE ulTotalRunTime = 0UL; /*< Holds the total amount of execution time as defined by the run time counter clock. */ + +#endif + +/*lint -restore */ + +/*-----------------------------------------------------------*/ + +/* File private functions. --------------------------------*/ + +/** + * Utility task that simply returns pdTRUE if the task referenced by xTask is + * currently in the Suspended state, or pdFALSE if the task referenced by xTask + * is in any other state. + */ +#if ( INCLUDE_vTaskSuspend == 1 ) + + static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +#endif /* INCLUDE_vTaskSuspend */ + +/* + * Utility to ready all the lists used by the scheduler. This is called + * automatically upon the creation of the first task. + */ +static void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION; + +/* + * The idle task, which as all tasks is implemented as a never ending loop. + * The idle task is automatically created and added to the ready lists upon + * creation of the first user task. + * + * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific + * language extensions. The equivalent prototype for this function is: + * + * void prvIdleTask( void *pvParameters ); + * + */ +static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters ) PRIVILEGED_FUNCTION; + +/* + * Utility to free all memory allocated by the scheduler to hold a TCB, + * including the stack pointed to by the TCB. + * + * This does not free memory allocated by the task itself (i.e. memory + * allocated by calls to pvPortMalloc from within the tasks application code). + */ +#if ( INCLUDE_vTaskDelete == 1 ) + + static void prvDeleteTCB( TCB_t * pxTCB ) PRIVILEGED_FUNCTION; + +#endif + +/* + * Used only by the idle task. This checks to see if anything has been placed + * in the list of tasks waiting to be deleted. If so the task is cleaned up + * and its TCB deleted. + */ +static void prvCheckTasksWaitingTermination( void ) PRIVILEGED_FUNCTION; + +/* + * The currently executing task is entering the Blocked state. Add the task to + * either the current or the overflow delayed task list. + */ +static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, + const BaseType_t xCanBlockIndefinitely ) PRIVILEGED_FUNCTION; + +/* + * Fills an TaskStatus_t structure with information on each task that is + * referenced from the pxList list (which may be a ready list, a delayed list, + * a suspended list, etc.). + * + * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM + * NORMAL APPLICATION CODE. + */ +#if ( configUSE_TRACE_FACILITY == 1 ) + + static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t * pxTaskStatusArray, + List_t * pxList, + eTaskState eState ) PRIVILEGED_FUNCTION; + +#endif + +/* + * Searches pxList for a task with name pcNameToQuery - returning a handle to + * the task if it is found, or NULL if the task is not found. + */ +#if ( INCLUDE_xTaskGetHandle == 1 ) + + static TCB_t * prvSearchForNameWithinSingleList( List_t * pxList, + const char pcNameToQuery[] ) PRIVILEGED_FUNCTION; + +#endif + +/* + * When a task is created, the stack of the task is filled with a known value. + * This function determines the 'high water mark' of the task stack by + * determining how much of the stack remains at the original preset value. + */ +#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) + + static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION; + +#endif + +/* + * Return the amount of time, in ticks, that will pass before the kernel will + * next move a task from the Blocked state to the Running state. + * + * This conditional compilation should use inequality to 0, not equality to 1. + * This is to ensure portSUPPRESS_TICKS_AND_SLEEP() can be called when user + * defined low power mode implementations require configUSE_TICKLESS_IDLE to be + * set to a value other than 1. + */ +#if ( configUSE_TICKLESS_IDLE != 0 ) + + static TickType_t prvGetExpectedIdleTime( void ) PRIVILEGED_FUNCTION; + +#endif + +/* + * Set xNextTaskUnblockTime to the time at which the next Blocked state task + * will exit the Blocked state. + */ +static void prvResetNextTaskUnblockTime( void ) PRIVILEGED_FUNCTION; + +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) + +/* + * Helper function used to pad task names with spaces when printing out + * human readable tables of task information. + */ + static char * prvWriteNameToBuffer( char * pcBuffer, + const char * pcTaskName ) PRIVILEGED_FUNCTION; + +#endif + +/* + * Called after a Task_t structure has been allocated either statically or + * dynamically to fill in the structure's members. + */ +static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, + const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const uint32_t ulStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask, + TCB_t * pxNewTCB, + const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION; + +/* + * Called after a new task has been created and initialised to place the task + * under the control of the scheduler. + */ +static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION; + +/* + * freertos_tasks_c_additions_init() should only be called if the user definable + * macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is the only macro + * called by the function. + */ +#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT + + static void freertos_tasks_c_additions_init( void ) PRIVILEGED_FUNCTION; + +#endif + +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + + TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode, + const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const uint32_t ulStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + StackType_t * const puxStackBuffer, + StaticTask_t * const pxTaskBuffer ) + { + TCB_t * pxNewTCB; + TaskHandle_t xReturn; + + configASSERT( puxStackBuffer != NULL ); + configASSERT( pxTaskBuffer != NULL ); + + #if ( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + * variable of type StaticTask_t equals the size of the real task + * structure. */ + volatile size_t xSize = sizeof( StaticTask_t ); + configASSERT( xSize == sizeof( TCB_t ) ); + ( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */ + } + #endif /* configASSERT_DEFINED */ + + if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) ) + { + /* The memory used for the task's TCB and stack are passed into this + * function - use them. */ + pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ + pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer; + + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ + { + /* Tasks can be created statically or dynamically, so note this + * task was created statically in case the task is later deleted. */ + pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; + } + #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ + + prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL ); + prvAddNewTaskToReadyList( pxNewTCB ); + } + else + { + xReturn = NULL; + } + + return xReturn; + } + +#endif /* SUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + + BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, + TaskHandle_t * pxCreatedTask ) + { + TCB_t * pxNewTCB; + BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + + configASSERT( pxTaskDefinition->puxStackBuffer != NULL ); + configASSERT( pxTaskDefinition->pxTaskBuffer != NULL ); + + if( ( pxTaskDefinition->puxStackBuffer != NULL ) && ( pxTaskDefinition->pxTaskBuffer != NULL ) ) + { + /* Allocate space for the TCB. Where the memory comes from depends + * on the implementation of the port malloc function and whether or + * not static allocation is being used. */ + pxNewTCB = ( TCB_t * ) pxTaskDefinition->pxTaskBuffer; + + /* Store the stack location in the TCB. */ + pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer; + + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) + { + /* Tasks can be created statically or dynamically, so note this + * task was created statically in case the task is later deleted. */ + pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; + } + #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ + + prvInitialiseNewTask( pxTaskDefinition->pvTaskCode, + pxTaskDefinition->pcName, + ( uint32_t ) pxTaskDefinition->usStackDepth, + pxTaskDefinition->pvParameters, + pxTaskDefinition->uxPriority, + pxCreatedTask, pxNewTCB, + pxTaskDefinition->xRegions ); + + prvAddNewTaskToReadyList( pxNewTCB ); + xReturn = pdPASS; + } + + return xReturn; + } + +#endif /* ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + + BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, + TaskHandle_t * pxCreatedTask ) + { + TCB_t * pxNewTCB; + BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + + configASSERT( pxTaskDefinition->puxStackBuffer ); + + if( pxTaskDefinition->puxStackBuffer != NULL ) + { + /* Allocate space for the TCB. Where the memory comes from depends + * on the implementation of the port malloc function and whether or + * not static allocation is being used. */ + pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); + + if( pxNewTCB != NULL ) + { + /* Store the stack location in the TCB. */ + pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer; + + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) + { + /* Tasks can be created statically or dynamically, so note + * this task had a statically allocated stack in case it is + * later deleted. The TCB was allocated dynamically. */ + pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_ONLY; + } + #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ + + prvInitialiseNewTask( pxTaskDefinition->pvTaskCode, + pxTaskDefinition->pcName, + ( uint32_t ) pxTaskDefinition->usStackDepth, + pxTaskDefinition->pvParameters, + pxTaskDefinition->uxPriority, + pxCreatedTask, pxNewTCB, + pxTaskDefinition->xRegions ); + + prvAddNewTaskToReadyList( pxNewTCB ); + xReturn = pdPASS; + } + } + + return xReturn; + } + +#endif /* portUSING_MPU_WRAPPERS */ +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + BaseType_t xTaskCreate( TaskFunction_t pxTaskCode, + const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const configSTACK_DEPTH_TYPE usStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask ) + { + TCB_t * pxNewTCB; + BaseType_t xReturn; + + /* If the stack grows down then allocate the stack then the TCB so the stack + * does not grow into the TCB. Likewise if the stack grows up then allocate + * the TCB then the stack. */ + #if ( portSTACK_GROWTH > 0 ) + { + /* Allocate space for the TCB. Where the memory comes from depends on + * the implementation of the port malloc function and whether or not static + * allocation is being used. */ + pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); + + if( pxNewTCB != NULL ) + { + /* Allocate space for the stack used by the task being created. + * The base of the stack memory stored in the TCB so the task can + * be deleted later if required. */ + pxNewTCB->pxStack = ( StackType_t * ) pvPortMallocStack( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + + if( pxNewTCB->pxStack == NULL ) + { + /* Could not allocate the stack. Delete the allocated TCB. */ + vPortFree( pxNewTCB ); + pxNewTCB = NULL; + } + } + } + #else /* portSTACK_GROWTH */ + { + StackType_t * pxStack; + + /* Allocate space for the stack used by the task being created. */ + pxStack = pvPortMallocStack( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */ + + if( pxStack != NULL ) + { + /* Allocate space for the TCB. */ + pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */ + + if( pxNewTCB != NULL ) + { + /* Store the stack location in the TCB. */ + pxNewTCB->pxStack = pxStack; + } + else + { + /* The stack cannot be used as the TCB was not created. Free + * it again. */ + vPortFreeStack( pxStack ); + } + } + else + { + pxNewTCB = NULL; + } + } + #endif /* portSTACK_GROWTH */ + + if( pxNewTCB != NULL ) + { + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */ + { + /* Tasks can be created statically or dynamically, so note this + * task was created dynamically in case it is later deleted. */ + pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB; + } + #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ + + prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL ); + prvAddNewTaskToReadyList( pxNewTCB ); + xReturn = pdPASS; + } + else + { + xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + } + + return xReturn; + } + +#endif /* configSUPPORT_DYNAMIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, + const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const uint32_t ulStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask, + TCB_t * pxNewTCB, + const MemoryRegion_t * const xRegions ) +{ + StackType_t * pxTopOfStack; + UBaseType_t x; + + #if ( portUSING_MPU_WRAPPERS == 1 ) + /* Should the task be created in privileged mode? */ + BaseType_t xRunPrivileged; + + if( ( uxPriority & portPRIVILEGE_BIT ) != 0U ) + { + xRunPrivileged = pdTRUE; + } + else + { + xRunPrivileged = pdFALSE; + } + uxPriority &= ~portPRIVILEGE_BIT; + #endif /* portUSING_MPU_WRAPPERS == 1 */ + + /* Avoid dependency on memset() if it is not required. */ + #if ( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 ) + { + /* Fill the stack with a known value to assist debugging. */ + ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) ); + } + #endif /* tskSET_NEW_STACKS_TO_KNOWN_VALUE */ + + /* Calculate the top of stack address. This depends on whether the stack + * grows from high memory to low (as per the 80x86) or vice versa. + * portSTACK_GROWTH is used to make the result positive or negative as required + * by the port. */ + #if ( portSTACK_GROWTH < 0 ) + { + pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] ); + pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */ + + /* Check the alignment of the calculated top of stack is correct. */ + configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) ); + + #if ( configRECORD_STACK_HIGH_ADDRESS == 1 ) + { + /* Also record the stack's high address, which may assist + * debugging. */ + pxNewTCB->pxEndOfStack = pxTopOfStack; + } + #endif /* configRECORD_STACK_HIGH_ADDRESS */ + } + #else /* portSTACK_GROWTH */ + { + pxTopOfStack = pxNewTCB->pxStack; + + /* Check the alignment of the stack buffer is correct. */ + configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxNewTCB->pxStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) ); + + /* The other extreme of the stack space is required if stack checking is + * performed. */ + pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 ); + } + #endif /* portSTACK_GROWTH */ + + /* Store the task name in the TCB. */ + if( pcName != NULL ) + { + for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) + { + pxNewTCB->pcTaskName[ x ] = pcName[ x ]; + + /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than + * configMAX_TASK_NAME_LEN characters just in case the memory after the + * string is not accessible (extremely unlikely). */ + if( pcName[ x ] == ( char ) 0x00 ) + { + break; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + /* Ensure the name string is terminated in the case that the string length + * was greater or equal to configMAX_TASK_NAME_LEN. */ + pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0'; + } + else + { + /* The task has not been given a name, so just ensure there is a NULL + * terminator when it is read out. */ + pxNewTCB->pcTaskName[ 0 ] = 0x00; + } + + /* This is used as an array index so must ensure it's not too large. */ + configASSERT( uxPriority < configMAX_PRIORITIES ); + + if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES ) + { + uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + pxNewTCB->uxPriority = uxPriority; + #if ( configUSE_MUTEXES == 1 ) + { + pxNewTCB->uxBasePriority = uxPriority; + pxNewTCB->uxMutexesHeld = 0; + } + #endif /* configUSE_MUTEXES */ + + vListInitialiseItem( &( pxNewTCB->xStateListItem ) ); + vListInitialiseItem( &( pxNewTCB->xEventListItem ) ); + + /* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get + * back to the containing TCB from a generic item in a list. */ + listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB ); + + /* Event lists are always in priority order. */ + listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB ); + + #if ( portCRITICAL_NESTING_IN_TCB == 1 ) + { + pxNewTCB->uxCriticalNesting = ( UBaseType_t ) 0U; + } + #endif /* portCRITICAL_NESTING_IN_TCB */ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + { + pxNewTCB->pxTaskTag = NULL; + } + #endif /* configUSE_APPLICATION_TASK_TAG */ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + { + pxNewTCB->ulRunTimeCounter = ( configRUN_TIME_COUNTER_TYPE ) 0; + } + #endif /* configGENERATE_RUN_TIME_STATS */ + + #if ( portUSING_MPU_WRAPPERS == 1 ) + { + vPortStoreTaskMPUSettings( &( pxNewTCB->xMPUSettings ), xRegions, pxNewTCB->pxStack, ulStackDepth ); + } + #else + { + /* Avoid compiler warning about unreferenced parameter. */ + ( void ) xRegions; + } + #endif + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + { + memset( ( void * ) &( pxNewTCB->pvThreadLocalStoragePointers[ 0 ] ), 0x00, sizeof( pxNewTCB->pvThreadLocalStoragePointers ) ); + } + #endif + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + { + memset( ( void * ) &( pxNewTCB->ulNotifiedValue[ 0 ] ), 0x00, sizeof( pxNewTCB->ulNotifiedValue ) ); + memset( ( void * ) &( pxNewTCB->ucNotifyState[ 0 ] ), 0x00, sizeof( pxNewTCB->ucNotifyState ) ); + } + #endif + + #if ( configUSE_NEWLIB_REENTRANT == 1 ) + { + /* Initialise this task's Newlib reent structure. + * See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html + * for additional information. */ + _REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) ); + } + #endif + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + { + pxNewTCB->ucDelayAborted = pdFALSE; + } + #endif + + /* Initialize the TCB stack to look as if the task was already running, + * but had been interrupted by the scheduler. The return address is set + * to the start of the task function. Once the stack has been initialised + * the top of stack variable is updated. */ + #if ( portUSING_MPU_WRAPPERS == 1 ) + { + /* If the port has capability to detect stack overflow, + * pass the stack end address to the stack initialization + * function as well. */ + #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 ) + { + #if ( portSTACK_GROWTH < 0 ) + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters, xRunPrivileged ); + } + #else /* portSTACK_GROWTH */ + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters, xRunPrivileged ); + } + #endif /* portSTACK_GROWTH */ + } + #else /* portHAS_STACK_OVERFLOW_CHECKING */ + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged ); + } + #endif /* portHAS_STACK_OVERFLOW_CHECKING */ + } + #else /* portUSING_MPU_WRAPPERS */ + { + /* If the port has capability to detect stack overflow, + * pass the stack end address to the stack initialization + * function as well. */ + #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 ) + { + #if ( portSTACK_GROWTH < 0 ) + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters ); + } + #else /* portSTACK_GROWTH */ + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters ); + } + #endif /* portSTACK_GROWTH */ + } + #else /* portHAS_STACK_OVERFLOW_CHECKING */ + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters ); + } + #endif /* portHAS_STACK_OVERFLOW_CHECKING */ + } + #endif /* portUSING_MPU_WRAPPERS */ + + if( pxCreatedTask != NULL ) + { + /* Pass the handle out in an anonymous way. The handle can be used to + * change the created task's priority, delete the created task, etc.*/ + *pxCreatedTask = ( TaskHandle_t ) pxNewTCB; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) +{ + /* Ensure interrupts don't access the task lists while the lists are being + * updated. */ + taskENTER_CRITICAL(); + { + uxCurrentNumberOfTasks++; + + if( pxCurrentTCB == NULL ) + { + /* There are no other tasks, or all the other tasks are in + * the suspended state - make this the current task. */ + pxCurrentTCB = pxNewTCB; + + if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 ) + { + /* This is the first task to be created so do the preliminary + * initialisation required. We will not recover if this call + * fails, but we will report the failure. */ + prvInitialiseTaskLists(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* If the scheduler is not already running, make this task the + * current task if it is the highest priority task to be created + * so far. */ + if( xSchedulerRunning == pdFALSE ) + { + if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority ) + { + pxCurrentTCB = pxNewTCB; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + uxTaskNumber++; + + #if ( configUSE_TRACE_FACILITY == 1 ) + { + /* Add a counter into the TCB for tracing only. */ + pxNewTCB->uxTCBNumber = uxTaskNumber; + } + #endif /* configUSE_TRACE_FACILITY */ + traceTASK_CREATE( pxNewTCB ); + + prvAddTaskToReadyList( pxNewTCB ); + + portSETUP_TCB( pxNewTCB ); + } + taskEXIT_CRITICAL(); + + if( xSchedulerRunning != pdFALSE ) + { + /* If the created task is of a higher priority than the current task + * then it should run now. */ + if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority ) + { + taskYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskDelete == 1 ) + + void vTaskDelete( TaskHandle_t xTaskToDelete ) + { + TCB_t * pxTCB; + + taskENTER_CRITICAL(); + { + /* If null is passed in here then it is the calling task that is + * being deleted. */ + pxTCB = prvGetTCBFromHandle( xTaskToDelete ); + + /* Remove task from the ready/delayed list. */ + if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + { + taskRESET_READY_PRIORITY( pxTCB->uxPriority ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Is the task waiting on an event also? */ + if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) + { + ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Increment the uxTaskNumber also so kernel aware debuggers can + * detect that the task lists need re-generating. This is done before + * portPRE_TASK_DELETE_HOOK() as in the Windows port that macro will + * not return. */ + uxTaskNumber++; + + if( pxTCB == pxCurrentTCB ) + { + /* A task is deleting itself. This cannot complete within the + * task itself, as a context switch to another task is required. + * Place the task in the termination list. The idle task will + * check the termination list and free up any memory allocated by + * the scheduler for the TCB and stack of the deleted task. */ + vListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xStateListItem ) ); + + /* Increment the ucTasksDeleted variable so the idle task knows + * there is a task that has been deleted and that it should therefore + * check the xTasksWaitingTermination list. */ + ++uxDeletedTasksWaitingCleanUp; + + /* Call the delete hook before portPRE_TASK_DELETE_HOOK() as + * portPRE_TASK_DELETE_HOOK() does not return in the Win32 port. */ + traceTASK_DELETE( pxTCB ); + + /* The pre-delete hook is primarily for the Windows simulator, + * in which Windows specific clean up operations are performed, + * after which it is not possible to yield away from this task - + * hence xYieldPending is used to latch that a context switch is + * required. */ + portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPending ); + } + else + { + --uxCurrentNumberOfTasks; + traceTASK_DELETE( pxTCB ); + + /* Reset the next expected unblock time in case it referred to + * the task that has just been deleted. */ + prvResetNextTaskUnblockTime(); + } + } + taskEXIT_CRITICAL(); + + /* If the task is not deleting itself, call prvDeleteTCB from outside of + * critical section. If a task deletes itself, prvDeleteTCB is called + * from prvCheckTasksWaitingTermination which is called from Idle task. */ + if( pxTCB != pxCurrentTCB ) + { + prvDeleteTCB( pxTCB ); + } + + /* Force a reschedule if it is the currently running task that has just + * been deleted. */ + if( xSchedulerRunning != pdFALSE ) + { + if( pxTCB == pxCurrentTCB ) + { + configASSERT( uxSchedulerSuspended == 0 ); + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + +#endif /* INCLUDE_vTaskDelete */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_xTaskDelayUntil == 1 ) + + BaseType_t xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) + { + TickType_t xTimeToWake; + BaseType_t xAlreadyYielded, xShouldDelay = pdFALSE; + + configASSERT( pxPreviousWakeTime ); + configASSERT( ( xTimeIncrement > 0U ) ); + configASSERT( uxSchedulerSuspended == 0 ); + + vTaskSuspendAll(); + { + /* Minor optimisation. The tick count cannot change in this + * block. */ + const TickType_t xConstTickCount = xTickCount; + + /* Generate the tick time at which the task wants to wake. */ + xTimeToWake = *pxPreviousWakeTime + xTimeIncrement; + + if( xConstTickCount < *pxPreviousWakeTime ) + { + /* The tick count has overflowed since this function was + * lasted called. In this case the only time we should ever + * actually delay is if the wake time has also overflowed, + * and the wake time is greater than the tick time. When this + * is the case it is as if neither time had overflowed. */ + if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xConstTickCount ) ) + { + xShouldDelay = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* The tick time has not overflowed. In this case we will + * delay if either the wake time has overflowed, and/or the + * tick time is less than the wake time. */ + if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xConstTickCount ) ) + { + xShouldDelay = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + /* Update the wake time ready for the next call. */ + *pxPreviousWakeTime = xTimeToWake; + + if( xShouldDelay != pdFALSE ) + { + traceTASK_DELAY_UNTIL( xTimeToWake ); + + /* prvAddCurrentTaskToDelayedList() needs the block time, not + * the time to wake, so subtract the current tick count. */ + prvAddCurrentTaskToDelayedList( xTimeToWake - xConstTickCount, pdFALSE ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + xAlreadyYielded = xTaskResumeAll(); + + /* Force a reschedule if xTaskResumeAll has not already done so, we may + * have put ourselves to sleep. */ + if( xAlreadyYielded == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xShouldDelay; + } + +#endif /* INCLUDE_xTaskDelayUntil */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskDelay == 1 ) + + void vTaskDelay( const TickType_t xTicksToDelay ) + { + BaseType_t xAlreadyYielded = pdFALSE; + + /* A delay time of zero just forces a reschedule. */ + if( xTicksToDelay > ( TickType_t ) 0U ) + { + configASSERT( uxSchedulerSuspended == 0 ); + vTaskSuspendAll(); + { + traceTASK_DELAY(); + + /* A task that is removed from the event list while the + * scheduler is suspended will not get placed in the ready + * list or removed from the blocked list until the scheduler + * is resumed. + * + * This task cannot be in an event list as it is the currently + * executing task. */ + prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE ); + } + xAlreadyYielded = xTaskResumeAll(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Force a reschedule if xTaskResumeAll has not already done so, we may + * have put ourselves to sleep. */ + if( xAlreadyYielded == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + +#endif /* INCLUDE_vTaskDelay */ +/*-----------------------------------------------------------*/ + +#if ( ( INCLUDE_eTaskGetState == 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_xTaskAbortDelay == 1 ) ) + + eTaskState eTaskGetState( TaskHandle_t xTask ) + { + eTaskState eReturn; + List_t const * pxStateList, * pxDelayedList, * pxOverflowedDelayedList; + const TCB_t * const pxTCB = xTask; + + configASSERT( pxTCB ); + + if( pxTCB == pxCurrentTCB ) + { + /* The task calling this function is querying its own state. */ + eReturn = eRunning; + } + else + { + taskENTER_CRITICAL(); + { + pxStateList = listLIST_ITEM_CONTAINER( &( pxTCB->xStateListItem ) ); + pxDelayedList = pxDelayedTaskList; + pxOverflowedDelayedList = pxOverflowDelayedTaskList; + } + taskEXIT_CRITICAL(); + + if( ( pxStateList == pxDelayedList ) || ( pxStateList == pxOverflowedDelayedList ) ) + { + /* The task being queried is referenced from one of the Blocked + * lists. */ + eReturn = eBlocked; + } + + #if ( INCLUDE_vTaskSuspend == 1 ) + else if( pxStateList == &xSuspendedTaskList ) + { + /* The task being queried is referenced from the suspended + * list. Is it genuinely suspended or is it blocked + * indefinitely? */ + if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ) + { + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + { + BaseType_t x; + + /* The task does not appear on the event list item of + * and of the RTOS objects, but could still be in the + * blocked state if it is waiting on its notification + * rather than waiting on an object. If not, is + * suspended. */ + eReturn = eSuspended; + + for( x = 0; x < configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ ) + { + if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION ) + { + eReturn = eBlocked; + break; + } + } + } + #else /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ + { + eReturn = eSuspended; + } + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ + } + else + { + eReturn = eBlocked; + } + } + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ + + #if ( INCLUDE_vTaskDelete == 1 ) + else if( ( pxStateList == &xTasksWaitingTermination ) || ( pxStateList == NULL ) ) + { + /* The task being queried is referenced from the deleted + * tasks list, or it is not referenced from any lists at + * all. */ + eReturn = eDeleted; + } + #endif + + else /*lint !e525 Negative indentation is intended to make use of pre-processor clearer. */ + { + /* If the task is not in any other state, it must be in the + * Ready (including pending ready) state. */ + eReturn = eReady; + } + } + + return eReturn; + } /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */ + +#endif /* INCLUDE_eTaskGetState */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_uxTaskPriorityGet == 1 ) + + UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask ) + { + TCB_t const * pxTCB; + UBaseType_t uxReturn; + + taskENTER_CRITICAL(); + { + /* If null is passed in here then it is the priority of the task + * that called uxTaskPriorityGet() that is being queried. */ + pxTCB = prvGetTCBFromHandle( xTask ); + uxReturn = pxTCB->uxPriority; + } + taskEXIT_CRITICAL(); + + return uxReturn; + } + +#endif /* INCLUDE_uxTaskPriorityGet */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_uxTaskPriorityGet == 1 ) + + UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) + { + TCB_t const * pxTCB; + UBaseType_t uxReturn, uxSavedInterruptState; + + /* RTOS ports that support interrupt nesting have the concept of a + * maximum system call (or maximum API call) interrupt priority. + * Interrupts that are above the maximum system call priority are keep + * permanently enabled, even when the RTOS kernel is in a critical section, + * but cannot make any calls to FreeRTOS API functions. If configASSERT() + * is defined in FreeRTOSConfig.h then + * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has + * been assigned a priority above the configured maximum system call + * priority. Only FreeRTOS functions that end in FromISR can be called + * from interrupts that have been assigned a priority at or (logically) + * below the maximum system call interrupt priority. FreeRTOS maintains a + * separate interrupt safe API to ensure interrupt entry is as fast and as + * simple as possible. More information (albeit Cortex-M specific) is + * provided on the following link: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + uxSavedInterruptState = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* If null is passed in here then it is the priority of the calling + * task that is being queried. */ + pxTCB = prvGetTCBFromHandle( xTask ); + uxReturn = pxTCB->uxPriority; + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptState ); + + return uxReturn; + } + +#endif /* INCLUDE_uxTaskPriorityGet */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskPrioritySet == 1 ) + + void vTaskPrioritySet( TaskHandle_t xTask, + UBaseType_t uxNewPriority ) + { + TCB_t * pxTCB; + UBaseType_t uxCurrentBasePriority, uxPriorityUsedOnEntry; + BaseType_t xYieldRequired = pdFALSE; + + configASSERT( uxNewPriority < configMAX_PRIORITIES ); + + /* Ensure the new priority is valid. */ + if( uxNewPriority >= ( UBaseType_t ) configMAX_PRIORITIES ) + { + uxNewPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + taskENTER_CRITICAL(); + { + /* If null is passed in here then it is the priority of the calling + * task that is being changed. */ + pxTCB = prvGetTCBFromHandle( xTask ); + + traceTASK_PRIORITY_SET( pxTCB, uxNewPriority ); + + #if ( configUSE_MUTEXES == 1 ) + { + uxCurrentBasePriority = pxTCB->uxBasePriority; + } + #else + { + uxCurrentBasePriority = pxTCB->uxPriority; + } + #endif + + if( uxCurrentBasePriority != uxNewPriority ) + { + /* The priority change may have readied a task of higher + * priority than the calling task. */ + if( uxNewPriority > uxCurrentBasePriority ) + { + if( pxTCB != pxCurrentTCB ) + { + /* The priority of a task other than the currently + * running task is being raised. Is the priority being + * raised above that of the running task? */ + if( uxNewPriority >= pxCurrentTCB->uxPriority ) + { + xYieldRequired = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* The priority of the running task is being raised, + * but the running task must already be the highest + * priority task able to run so no yield is required. */ + } + } + else if( pxTCB == pxCurrentTCB ) + { + /* Setting the priority of the running task down means + * there may now be another task of higher priority that + * is ready to execute. */ + xYieldRequired = pdTRUE; + } + else + { + /* Setting the priority of any other task down does not + * require a yield as the running task must be above the + * new priority of the task being modified. */ + } + + /* Remember the ready list the task might be referenced from + * before its uxPriority member is changed so the + * taskRESET_READY_PRIORITY() macro can function correctly. */ + uxPriorityUsedOnEntry = pxTCB->uxPriority; + + #if ( configUSE_MUTEXES == 1 ) + { + /* Only change the priority being used if the task is not + * currently using an inherited priority. */ + if( pxTCB->uxBasePriority == pxTCB->uxPriority ) + { + pxTCB->uxPriority = uxNewPriority; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The base priority gets set whatever. */ + pxTCB->uxBasePriority = uxNewPriority; + } + #else /* if ( configUSE_MUTEXES == 1 ) */ + { + pxTCB->uxPriority = uxNewPriority; + } + #endif /* if ( configUSE_MUTEXES == 1 ) */ + + /* Only reset the event list item value if the value is not + * being used for anything else. */ + if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) + { + listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* If the task is in the blocked or suspended list we need do + * nothing more than change its priority variable. However, if + * the task is in a ready list it needs to be removed and placed + * in the list appropriate to its new priority. */ + if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE ) + { + /* The task is currently in its ready list - remove before + * adding it to its new ready list. As we are in a critical + * section we can do this even if the scheduler is suspended. */ + if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + { + /* It is known that the task is in its ready list so + * there is no need to check again and the port level + * reset macro can be called directly. */ + portRESET_READY_PRIORITY( uxPriorityUsedOnEntry, uxTopReadyPriority ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + prvAddTaskToReadyList( pxTCB ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xYieldRequired != pdFALSE ) + { + taskYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Remove compiler warning about unused variables when the port + * optimised task selection is not being used. */ + ( void ) uxPriorityUsedOnEntry; + } + } + taskEXIT_CRITICAL(); + } + +#endif /* INCLUDE_vTaskPrioritySet */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskSuspend == 1 ) + + void vTaskSuspend( TaskHandle_t xTaskToSuspend ) + { + TCB_t * pxTCB; + + taskENTER_CRITICAL(); + { + /* If null is passed in here then it is the running task that is + * being suspended. */ + pxTCB = prvGetTCBFromHandle( xTaskToSuspend ); + + traceTASK_SUSPEND( pxTCB ); + + /* Remove task from the ready/delayed list and place in the + * suspended list. */ + if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + { + taskRESET_READY_PRIORITY( pxTCB->uxPriority ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Is the task waiting on an event also? */ + if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) + { + ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + vListInsertEnd( &xSuspendedTaskList, &( pxTCB->xStateListItem ) ); + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + { + BaseType_t x; + + for( x = 0; x < configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ ) + { + if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION ) + { + /* The task was blocked to wait for a notification, but is + * now suspended, so no notification was received. */ + pxTCB->ucNotifyState[ x ] = taskNOT_WAITING_NOTIFICATION; + } + } + } + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ + } + taskEXIT_CRITICAL(); + + if( xSchedulerRunning != pdFALSE ) + { + /* Reset the next expected unblock time in case it referred to the + * task that is now in the Suspended state. */ + taskENTER_CRITICAL(); + { + prvResetNextTaskUnblockTime(); + } + taskEXIT_CRITICAL(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( pxTCB == pxCurrentTCB ) + { + if( xSchedulerRunning != pdFALSE ) + { + /* The current task has just been suspended. */ + configASSERT( uxSchedulerSuspended == 0 ); + portYIELD_WITHIN_API(); + } + else + { + /* The scheduler is not running, but the task that was pointed + * to by pxCurrentTCB has just been suspended and pxCurrentTCB + * must be adjusted to point to a different task. */ + if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks ) /*lint !e931 Right has no side effect, just volatile. */ + { + /* No other tasks are ready, so set pxCurrentTCB back to + * NULL so when the next task is created pxCurrentTCB will + * be set to point to it no matter what its relative priority + * is. */ + pxCurrentTCB = NULL; + } + else + { + vTaskSwitchContext(); + } + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + +#endif /* INCLUDE_vTaskSuspend */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskSuspend == 1 ) + + static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ) + { + BaseType_t xReturn = pdFALSE; + const TCB_t * const pxTCB = xTask; + + /* Accesses xPendingReadyList so must be called from a critical + * section. */ + + /* It does not make sense to check if the calling task is suspended. */ + configASSERT( xTask ); + + /* Is the task being resumed actually in the suspended list? */ + if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xStateListItem ) ) != pdFALSE ) + { + /* Has the task already been resumed from within an ISR? */ + if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) == pdFALSE ) + { + /* Is it in the suspended list because it is in the Suspended + * state, or because is is blocked with no timeout? */ + if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE ) /*lint !e961. The cast is only redundant when NULL is used. */ + { + xReturn = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xReturn; + } /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */ + +#endif /* INCLUDE_vTaskSuspend */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskSuspend == 1 ) + + void vTaskResume( TaskHandle_t xTaskToResume ) + { + TCB_t * const pxTCB = xTaskToResume; + + /* It does not make sense to resume the calling task. */ + configASSERT( xTaskToResume ); + + /* The parameter cannot be NULL as it is impossible to resume the + * currently executing task. */ + if( ( pxTCB != pxCurrentTCB ) && ( pxTCB != NULL ) ) + { + taskENTER_CRITICAL(); + { + if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE ) + { + traceTASK_RESUME( pxTCB ); + + /* The ready list can be accessed even if the scheduler is + * suspended because this is inside a critical section. */ + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + prvAddTaskToReadyList( pxTCB ); + + /* A higher priority task may have just been resumed. */ + if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) + { + /* This yield may not cause the task just resumed to run, + * but will leave the lists in the correct state for the + * next yield. */ + taskYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + +#endif /* INCLUDE_vTaskSuspend */ + +/*-----------------------------------------------------------*/ + +#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) + + BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) + { + BaseType_t xYieldRequired = pdFALSE; + TCB_t * const pxTCB = xTaskToResume; + UBaseType_t uxSavedInterruptStatus; + + configASSERT( xTaskToResume ); + + /* RTOS ports that support interrupt nesting have the concept of a + * maximum system call (or maximum API call) interrupt priority. + * Interrupts that are above the maximum system call priority are keep + * permanently enabled, even when the RTOS kernel is in a critical section, + * but cannot make any calls to FreeRTOS API functions. If configASSERT() + * is defined in FreeRTOSConfig.h then + * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has + * been assigned a priority above the configured maximum system call + * priority. Only FreeRTOS functions that end in FromISR can be called + * from interrupts that have been assigned a priority at or (logically) + * below the maximum system call interrupt priority. FreeRTOS maintains a + * separate interrupt safe API to ensure interrupt entry is as fast and as + * simple as possible. More information (albeit Cortex-M specific) is + * provided on the following link: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE ) + { + traceTASK_RESUME_FROM_ISR( pxTCB ); + + /* Check the ready lists can be accessed. */ + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + { + /* Ready lists can be accessed so move the task from the + * suspended list to the ready list directly. */ + if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) + { + xYieldRequired = pdTRUE; + + /* Mark that a yield is pending in case the user is not + * using the return value to initiate a context switch + * from the ISR using portYIELD_FROM_ISR. */ + xYieldPending = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + prvAddTaskToReadyList( pxTCB ); + } + else + { + /* The delayed or ready lists cannot be accessed so the task + * is held in the pending ready list until the scheduler is + * unsuspended. */ + vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xYieldRequired; + } + +#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */ +/*-----------------------------------------------------------*/ + +void vTaskStartScheduler( void ) +{ + BaseType_t xReturn; + + /* Add the idle task at the lowest priority. */ + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + StaticTask_t * pxIdleTaskTCBBuffer = NULL; + StackType_t * pxIdleTaskStackBuffer = NULL; + uint32_t ulIdleTaskStackSize; + + /* The Idle task is created using user provided RAM - obtain the + * address of the RAM then create the idle task. */ + vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize ); + xIdleTaskHandle = xTaskCreateStatic( prvIdleTask, + configIDLE_TASK_NAME, + ulIdleTaskStackSize, + ( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */ + portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */ + pxIdleTaskStackBuffer, + pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */ + + if( xIdleTaskHandle != NULL ) + { + xReturn = pdPASS; + } + else + { + xReturn = pdFAIL; + } + } + #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ + { + /* The Idle task is being created using dynamically allocated RAM. */ + xReturn = xTaskCreate( prvIdleTask, + configIDLE_TASK_NAME, + configMINIMAL_STACK_SIZE, + ( void * ) NULL, + portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */ + &xIdleTaskHandle ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */ + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ + + #if ( configUSE_TIMERS == 1 ) + { + if( xReturn == pdPASS ) + { + xReturn = xTimerCreateTimerTask(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_TIMERS */ + + if( xReturn == pdPASS ) + { + /* freertos_tasks_c_additions_init() should only be called if the user + * definable macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is + * the only macro called by the function. */ + #ifdef FREERTOS_TASKS_C_ADDITIONS_INIT + { + freertos_tasks_c_additions_init(); + } + #endif + + /* Interrupts are turned off here, to ensure a tick does not occur + * before or during the call to xPortStartScheduler(). The stacks of + * the created tasks contain a status word with interrupts switched on + * so interrupts will automatically get re-enabled when the first task + * starts to run. */ + portDISABLE_INTERRUPTS(); + + #if ( configUSE_NEWLIB_REENTRANT == 1 ) + { + /* Switch Newlib's _impure_ptr variable to point to the _reent + * structure specific to the task that will run first. + * See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html + * for additional information. */ + _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); + } + #endif /* configUSE_NEWLIB_REENTRANT */ + + xNextTaskUnblockTime = portMAX_DELAY; + xSchedulerRunning = pdTRUE; + xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT; + + /* If configGENERATE_RUN_TIME_STATS is defined then the following + * macro must be defined to configure the timer/counter used to generate + * the run time counter time base. NOTE: If configGENERATE_RUN_TIME_STATS + * is set to 0 and the following line fails to build then ensure you do not + * have portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() defined in your + * FreeRTOSConfig.h file. */ + portCONFIGURE_TIMER_FOR_RUN_TIME_STATS(); + + traceTASK_SWITCHED_IN(); + + /* Setting up the timer tick is hardware specific and thus in the + * portable interface. */ + if( xPortStartScheduler() != pdFALSE ) + { + /* Should not reach here as if the scheduler is running the + * function will not return. */ + } + else + { + /* Should only reach here if a task calls xTaskEndScheduler(). */ + } + } + else + { + /* This line will only be reached if the kernel could not be started, + * because there was not enough FreeRTOS heap to create the idle task + * or the timer task. */ + configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ); + } + + /* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0, + * meaning xIdleTaskHandle is not used anywhere else. */ + ( void ) xIdleTaskHandle; + + /* OpenOCD makes use of uxTopUsedPriority for thread debugging. Prevent uxTopUsedPriority + * from getting optimized out as it is no longer used by the kernel. */ + ( void ) uxTopUsedPriority; +} +/*-----------------------------------------------------------*/ + +void vTaskEndScheduler( void ) +{ + /* Stop the scheduler interrupts and call the portable scheduler end + * routine so the original ISRs can be restored if necessary. The port + * layer must ensure interrupts enable bit is left in the correct state. */ + portDISABLE_INTERRUPTS(); + xSchedulerRunning = pdFALSE; + vPortEndScheduler(); +} +/*----------------------------------------------------------*/ + +void vTaskSuspendAll( void ) +{ + /* A critical section is not required as the variable is of type + * BaseType_t. Please read Richard Barry's reply in the following link to a + * post in the FreeRTOS support forum before reporting this as a bug! - + * https://goo.gl/wu4acr */ + + /* portSOFTWARE_BARRIER() is only implemented for emulated/simulated ports that + * do not otherwise exhibit real time behaviour. */ + portSOFTWARE_BARRIER(); + + /* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment + * is used to allow calls to vTaskSuspendAll() to nest. */ + ++uxSchedulerSuspended; + + /* Enforces ordering for ports and optimised compilers that may otherwise place + * the above increment elsewhere. */ + portMEMORY_BARRIER(); +} +/*----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE != 0 ) + + static TickType_t prvGetExpectedIdleTime( void ) + { + TickType_t xReturn; + UBaseType_t uxHigherPriorityReadyTasks = pdFALSE; + + /* uxHigherPriorityReadyTasks takes care of the case where + * configUSE_PREEMPTION is 0, so there may be tasks above the idle priority + * task that are in the Ready state, even though the idle task is + * running. */ + #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 ) + { + if( uxTopReadyPriority > tskIDLE_PRIORITY ) + { + uxHigherPriorityReadyTasks = pdTRUE; + } + } + #else + { + const UBaseType_t uxLeastSignificantBit = ( UBaseType_t ) 0x01; + + /* When port optimised task selection is used the uxTopReadyPriority + * variable is used as a bit map. If bits other than the least + * significant bit are set then there are tasks that have a priority + * above the idle priority that are in the Ready state. This takes + * care of the case where the co-operative scheduler is in use. */ + if( uxTopReadyPriority > uxLeastSignificantBit ) + { + uxHigherPriorityReadyTasks = pdTRUE; + } + } + #endif /* if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 ) */ + + if( pxCurrentTCB->uxPriority > tskIDLE_PRIORITY ) + { + xReturn = 0; + } + else if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1 ) + { + /* There are other idle priority tasks in the ready state. If + * time slicing is used then the very next tick interrupt must be + * processed. */ + xReturn = 0; + } + else if( uxHigherPriorityReadyTasks != pdFALSE ) + { + /* There are tasks in the Ready state that have a priority above the + * idle priority. This path can only be reached if + * configUSE_PREEMPTION is 0. */ + xReturn = 0; + } + else + { + xReturn = xNextTaskUnblockTime - xTickCount; + } + + return xReturn; + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*----------------------------------------------------------*/ + +BaseType_t xTaskResumeAll( void ) +{ + TCB_t * pxTCB = NULL; + BaseType_t xAlreadyYielded = pdFALSE; + + /* If uxSchedulerSuspended is zero then this function does not match a + * previous call to vTaskSuspendAll(). */ + configASSERT( uxSchedulerSuspended ); + + /* It is possible that an ISR caused a task to be removed from an event + * list while the scheduler was suspended. If this was the case then the + * removed task will have been added to the xPendingReadyList. Once the + * scheduler has been resumed it is safe to move all the pending ready + * tasks from this list into their appropriate ready list. */ + taskENTER_CRITICAL(); + { + --uxSchedulerSuspended; + + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + { + if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U ) + { + /* Move any readied tasks from the pending list into the + * appropriate ready list. */ + while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) + { + pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + listREMOVE_ITEM( &( pxTCB->xEventListItem ) ); + portMEMORY_BARRIER(); + listREMOVE_ITEM( &( pxTCB->xStateListItem ) ); + prvAddTaskToReadyList( pxTCB ); + + /* If the moved task has a priority higher than or equal to + * the current task then a yield must be performed. */ + if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) + { + xYieldPending = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + if( pxTCB != NULL ) + { + /* A task was unblocked while the scheduler was suspended, + * which may have prevented the next unblock time from being + * re-calculated, in which case re-calculate it now. Mainly + * important for low power tickless implementations, where + * this can prevent an unnecessary exit from low power + * state. */ + prvResetNextTaskUnblockTime(); + } + + /* If any ticks occurred while the scheduler was suspended then + * they should be processed now. This ensures the tick count does + * not slip, and that any delayed tasks are resumed at the correct + * time. */ + { + TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */ + + if( xPendedCounts > ( TickType_t ) 0U ) + { + do + { + if( xTaskIncrementTick() != pdFALSE ) + { + xYieldPending = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + --xPendedCounts; + } while( xPendedCounts > ( TickType_t ) 0U ); + + xPendedTicks = 0; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + if( xYieldPending != pdFALSE ) + { + #if ( configUSE_PREEMPTION != 0 ) + { + xAlreadyYielded = pdTRUE; + } + #endif + taskYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + return xAlreadyYielded; +} +/*-----------------------------------------------------------*/ + +TickType_t xTaskGetTickCount( void ) +{ + TickType_t xTicks; + + /* Critical section required if running on a 16 bit processor. */ + portTICK_TYPE_ENTER_CRITICAL(); + { + xTicks = xTickCount; + } + portTICK_TYPE_EXIT_CRITICAL(); + + return xTicks; +} +/*-----------------------------------------------------------*/ + +TickType_t xTaskGetTickCountFromISR( void ) +{ + TickType_t xReturn; + UBaseType_t uxSavedInterruptStatus; + + /* RTOS ports that support interrupt nesting have the concept of a maximum + * system call (or maximum API call) interrupt priority. Interrupts that are + * above the maximum system call priority are kept permanently enabled, even + * when the RTOS kernel is in a critical section, but cannot make any calls to + * FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h + * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has been + * assigned a priority above the configured maximum system call priority. + * Only FreeRTOS functions that end in FromISR can be called from interrupts + * that have been assigned a priority at or (logically) below the maximum + * system call interrupt priority. FreeRTOS maintains a separate interrupt + * safe API to ensure interrupt entry is as fast and as simple as possible. + * More information (albeit Cortex-M specific) is provided on the following + * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR(); + { + xReturn = xTickCount; + } + portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +UBaseType_t uxTaskGetNumberOfTasks( void ) +{ + /* A critical section is not required because the variables are of type + * BaseType_t. */ + return uxCurrentNumberOfTasks; +} +/*-----------------------------------------------------------*/ + +char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ +{ + TCB_t * pxTCB; + + /* If null is passed in here then the name of the calling task is being + * queried. */ + pxTCB = prvGetTCBFromHandle( xTaskToQuery ); + configASSERT( pxTCB ); + return &( pxTCB->pcTaskName[ 0 ] ); +} +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_xTaskGetHandle == 1 ) + + static TCB_t * prvSearchForNameWithinSingleList( List_t * pxList, + const char pcNameToQuery[] ) + { + TCB_t * pxNextTCB, * pxFirstTCB, * pxReturn = NULL; + UBaseType_t x; + char cNextChar; + BaseType_t xBreakLoop; + + /* This function is called with the scheduler suspended. */ + + if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 ) + { + listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + + do + { + listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + + /* Check each character in the name looking for a match or + * mismatch. */ + xBreakLoop = pdFALSE; + + for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) + { + cNextChar = pxNextTCB->pcTaskName[ x ]; + + if( cNextChar != pcNameToQuery[ x ] ) + { + /* Characters didn't match. */ + xBreakLoop = pdTRUE; + } + else if( cNextChar == ( char ) 0x00 ) + { + /* Both strings terminated, a match must have been + * found. */ + pxReturn = pxNextTCB; + xBreakLoop = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xBreakLoop != pdFALSE ) + { + break; + } + } + + if( pxReturn != NULL ) + { + /* The handle has been found. */ + break; + } + } while( pxNextTCB != pxFirstTCB ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return pxReturn; + } + +#endif /* INCLUDE_xTaskGetHandle */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_xTaskGetHandle == 1 ) + + TaskHandle_t xTaskGetHandle( const char * pcNameToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + { + UBaseType_t uxQueue = configMAX_PRIORITIES; + TCB_t * pxTCB; + + /* Task names will be truncated to configMAX_TASK_NAME_LEN - 1 bytes. */ + configASSERT( strlen( pcNameToQuery ) < configMAX_TASK_NAME_LEN ); + + vTaskSuspendAll(); + { + /* Search the ready lists. */ + do + { + uxQueue--; + pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) &( pxReadyTasksLists[ uxQueue ] ), pcNameToQuery ); + + if( pxTCB != NULL ) + { + /* Found the handle. */ + break; + } + } while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + + /* Search the delayed lists. */ + if( pxTCB == NULL ) + { + pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxDelayedTaskList, pcNameToQuery ); + } + + if( pxTCB == NULL ) + { + pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxOverflowDelayedTaskList, pcNameToQuery ); + } + + #if ( INCLUDE_vTaskSuspend == 1 ) + { + if( pxTCB == NULL ) + { + /* Search the suspended list. */ + pxTCB = prvSearchForNameWithinSingleList( &xSuspendedTaskList, pcNameToQuery ); + } + } + #endif + + #if ( INCLUDE_vTaskDelete == 1 ) + { + if( pxTCB == NULL ) + { + /* Search the deleted list. */ + pxTCB = prvSearchForNameWithinSingleList( &xTasksWaitingTermination, pcNameToQuery ); + } + } + #endif + } + ( void ) xTaskResumeAll(); + + return pxTCB; + } + +#endif /* INCLUDE_xTaskGetHandle */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) + { + UBaseType_t uxTask = 0, uxQueue = configMAX_PRIORITIES; + + vTaskSuspendAll(); + { + /* Is there a space in the array for each task in the system? */ + if( uxArraySize >= uxCurrentNumberOfTasks ) + { + /* Fill in an TaskStatus_t structure with information on each + * task in the Ready state. */ + do + { + uxQueue--; + uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &( pxReadyTasksLists[ uxQueue ] ), eReady ); + } while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + + /* Fill in an TaskStatus_t structure with information on each + * task in the Blocked state. */ + uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxDelayedTaskList, eBlocked ); + uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxOverflowDelayedTaskList, eBlocked ); + + #if ( INCLUDE_vTaskDelete == 1 ) + { + /* Fill in an TaskStatus_t structure with information on + * each task that has been deleted but not yet cleaned up. */ + uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted ); + } + #endif + + #if ( INCLUDE_vTaskSuspend == 1 ) + { + /* Fill in an TaskStatus_t structure with information on + * each task in the Suspended state. */ + uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended ); + } + #endif + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + { + if( pulTotalRunTime != NULL ) + { + #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE + portALT_GET_RUN_TIME_COUNTER_VALUE( ( *pulTotalRunTime ) ); + #else + *pulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE(); + #endif + } + } + #else /* if ( configGENERATE_RUN_TIME_STATS == 1 ) */ + { + if( pulTotalRunTime != NULL ) + { + *pulTotalRunTime = 0; + } + } + #endif /* if ( configGENERATE_RUN_TIME_STATS == 1 ) */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + ( void ) xTaskResumeAll(); + + return uxTask; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*----------------------------------------------------------*/ + +#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) + + TaskHandle_t xTaskGetIdleTaskHandle( void ) + { + /* If xTaskGetIdleTaskHandle() is called before the scheduler has been + * started, then xIdleTaskHandle will be NULL. */ + configASSERT( ( xIdleTaskHandle != NULL ) ); + return xIdleTaskHandle; + } + +#endif /* INCLUDE_xTaskGetIdleTaskHandle */ +/*----------------------------------------------------------*/ + +/* This conditional compilation should use inequality to 0, not equality to 1. + * This is to ensure vTaskStepTick() is available when user defined low power mode + * implementations require configUSE_TICKLESS_IDLE to be set to a value other than + * 1. */ +#if ( configUSE_TICKLESS_IDLE != 0 ) + + void vTaskStepTick( const TickType_t xTicksToJump ) + { + /* Correct the tick count value after a period during which the tick + * was suppressed. Note this does *not* call the tick hook function for + * each stepped tick. */ + configASSERT( ( xTickCount + xTicksToJump ) <= xNextTaskUnblockTime ); + xTickCount += xTicksToJump; + traceINCREASE_TICK_COUNT( xTicksToJump ); + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*----------------------------------------------------------*/ + +BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) +{ + BaseType_t xYieldOccurred; + + /* Must not be called with the scheduler suspended as the implementation + * relies on xPendedTicks being wound down to 0 in xTaskResumeAll(). */ + configASSERT( uxSchedulerSuspended == 0 ); + + /* Use xPendedTicks to mimic xTicksToCatchUp number of ticks occurring when + * the scheduler is suspended so the ticks are executed in xTaskResumeAll(). */ + vTaskSuspendAll(); + xPendedTicks += xTicksToCatchUp; + xYieldOccurred = xTaskResumeAll(); + + return xYieldOccurred; +} +/*----------------------------------------------------------*/ + +#if ( INCLUDE_xTaskAbortDelay == 1 ) + + BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) + { + TCB_t * pxTCB = xTask; + BaseType_t xReturn; + + configASSERT( pxTCB ); + + vTaskSuspendAll(); + { + /* A task can only be prematurely removed from the Blocked state if + * it is actually in the Blocked state. */ + if( eTaskGetState( xTask ) == eBlocked ) + { + xReturn = pdPASS; + + /* Remove the reference to the task from the blocked list. An + * interrupt won't touch the xStateListItem because the + * scheduler is suspended. */ + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + + /* Is the task waiting on an event also? If so remove it from + * the event list too. Interrupts can touch the event list item, + * even though the scheduler is suspended, so a critical section + * is used. */ + taskENTER_CRITICAL(); + { + if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) + { + ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); + + /* This lets the task know it was forcibly removed from the + * blocked state so it should not re-evaluate its block time and + * then block again. */ + pxTCB->ucDelayAborted = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + /* Place the unblocked task into the appropriate ready list. */ + prvAddTaskToReadyList( pxTCB ); + + /* A task being unblocked cannot cause an immediate context + * switch if preemption is turned off. */ + #if ( configUSE_PREEMPTION == 1 ) + { + /* Preemption is on, but a context switch should only be + * performed if the unblocked task has a priority that is + * higher than the currently executing task. */ + if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) + { + /* Pend the yield to be performed when the scheduler + * is unsuspended. */ + xYieldPending = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_PREEMPTION */ + } + else + { + xReturn = pdFAIL; + } + } + ( void ) xTaskResumeAll(); + + return xReturn; + } + +#endif /* INCLUDE_xTaskAbortDelay */ +/*----------------------------------------------------------*/ + +BaseType_t xTaskIncrementTick( void ) +{ + TCB_t * pxTCB; + TickType_t xItemValue; + BaseType_t xSwitchRequired = pdFALSE; + + /* Called by the portable layer each time a tick interrupt occurs. + * Increments the tick then checks to see if the new tick value will cause any + * tasks to be unblocked. */ + traceTASK_INCREMENT_TICK( xTickCount ); + + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + { + /* Minor optimisation. The tick count cannot change in this + * block. */ + const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1; + + /* Increment the RTOS tick, switching the delayed and overflowed + * delayed lists if it wraps to 0. */ + xTickCount = xConstTickCount; + + if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */ + { + taskSWITCH_DELAYED_LISTS(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* See if this tick has made a timeout expire. Tasks are stored in + * the queue in the order of their wake time - meaning once one task + * has been found whose block time has not expired there is no need to + * look any further down the list. */ + if( xConstTickCount >= xNextTaskUnblockTime ) + { + for( ; ; ) + { + if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) + { + /* The delayed list is empty. Set xNextTaskUnblockTime + * to the maximum possible value so it is extremely + * unlikely that the + * if( xTickCount >= xNextTaskUnblockTime ) test will pass + * next time through. */ + xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + break; + } + else + { + /* The delayed list is not empty, get the value of the + * item at the head of the delayed list. This is the time + * at which the task at the head of the delayed list must + * be removed from the Blocked state. */ + pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) ); + + if( xConstTickCount < xItemValue ) + { + /* It is not time to unblock this item yet, but the + * item value is the time at which the task at the head + * of the blocked list must be removed from the Blocked + * state - so record the item value in + * xNextTaskUnblockTime. */ + xNextTaskUnblockTime = xItemValue; + break; /*lint !e9011 Code structure here is deemed easier to understand with multiple breaks. */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* It is time to remove the item from the Blocked state. */ + listREMOVE_ITEM( &( pxTCB->xStateListItem ) ); + + /* Is the task waiting on an event also? If so remove + * it from the event list. */ + if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) + { + listREMOVE_ITEM( &( pxTCB->xEventListItem ) ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Place the unblocked task into the appropriate ready + * list. */ + prvAddTaskToReadyList( pxTCB ); + + /* A task being unblocked cannot cause an immediate + * context switch if preemption is turned off. */ + #if ( configUSE_PREEMPTION == 1 ) + { + /* Preemption is on, but a context switch should + * only be performed if the unblocked task has a + * priority that is equal to or higher than the + * currently executing task. */ + if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) + { + xSwitchRequired = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_PREEMPTION */ + } + } + } + + /* Tasks of equal priority to the currently running task will share + * processing time (time slice) if preemption is on, and the application + * writer has not explicitly turned time slicing off. */ + #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) + { + if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 ) + { + xSwitchRequired = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */ + + #if ( configUSE_TICK_HOOK == 1 ) + { + /* Guard against the tick hook being called when the pended tick + * count is being unwound (when the scheduler is being unlocked). */ + if( xPendedTicks == ( TickType_t ) 0 ) + { + vApplicationTickHook(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_TICK_HOOK */ + + #if ( configUSE_PREEMPTION == 1 ) + { + if( xYieldPending != pdFALSE ) + { + xSwitchRequired = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_PREEMPTION */ + } + else + { + ++xPendedTicks; + + /* The tick hook gets called at regular intervals, even if the + * scheduler is locked. */ + #if ( configUSE_TICK_HOOK == 1 ) + { + vApplicationTickHook(); + } + #endif + } + + return xSwitchRequired; +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + void vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) + { + TCB_t * xTCB; + + /* If xTask is NULL then it is the task hook of the calling task that is + * getting set. */ + if( xTask == NULL ) + { + xTCB = ( TCB_t * ) pxCurrentTCB; + } + else + { + xTCB = xTask; + } + + /* Save the hook function in the TCB. A critical section is required as + * the value can be accessed from an interrupt. */ + taskENTER_CRITICAL(); + { + xTCB->pxTaskTag = pxHookFunction; + } + taskEXIT_CRITICAL(); + } + +#endif /* configUSE_APPLICATION_TASK_TAG */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) + { + TCB_t * pxTCB; + TaskHookFunction_t xReturn; + + /* If xTask is NULL then set the calling task's hook. */ + pxTCB = prvGetTCBFromHandle( xTask ); + + /* Save the hook function in the TCB. A critical section is required as + * the value can be accessed from an interrupt. */ + taskENTER_CRITICAL(); + { + xReturn = pxTCB->pxTaskTag; + } + taskEXIT_CRITICAL(); + + return xReturn; + } + +#endif /* configUSE_APPLICATION_TASK_TAG */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) + { + TCB_t * pxTCB; + TaskHookFunction_t xReturn; + UBaseType_t uxSavedInterruptStatus; + + /* If xTask is NULL then set the calling task's hook. */ + pxTCB = prvGetTCBFromHandle( xTask ); + + /* Save the hook function in the TCB. A critical section is required as + * the value can be accessed from an interrupt. */ + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + xReturn = pxTCB->pxTaskTag; + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; + } + +#endif /* configUSE_APPLICATION_TASK_TAG */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, + void * pvParameter ) + { + TCB_t * xTCB; + BaseType_t xReturn; + + /* If xTask is NULL then we are calling our own task hook. */ + if( xTask == NULL ) + { + xTCB = pxCurrentTCB; + } + else + { + xTCB = xTask; + } + + if( xTCB->pxTaskTag != NULL ) + { + xReturn = xTCB->pxTaskTag( pvParameter ); + } + else + { + xReturn = pdFAIL; + } + + return xReturn; + } + +#endif /* configUSE_APPLICATION_TASK_TAG */ +/*-----------------------------------------------------------*/ + +void vTaskSwitchContext( void ) +{ + if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE ) + { + /* The scheduler is currently suspended - do not allow a context + * switch. */ + xYieldPending = pdTRUE; + } + else + { + xYieldPending = pdFALSE; + traceTASK_SWITCHED_OUT(); + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + { + #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE + portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime ); + #else + ulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE(); + #endif + + /* Add the amount of time the task has been running to the + * accumulated time so far. The time the task started running was + * stored in ulTaskSwitchedInTime. Note that there is no overflow + * protection here so count values are only valid until the timer + * overflows. The guard against negative values is to protect + * against suspect run time stat counter implementations - which + * are provided by the application, not the kernel. */ + if( ulTotalRunTime > ulTaskSwitchedInTime ) + { + pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + ulTaskSwitchedInTime = ulTotalRunTime; + } + #endif /* configGENERATE_RUN_TIME_STATS */ + + /* Check for stack overflow, if configured. */ + taskCHECK_FOR_STACK_OVERFLOW(); + + /* Before the currently running task is switched out, save its errno. */ + #if ( configUSE_POSIX_ERRNO == 1 ) + { + pxCurrentTCB->iTaskErrno = FreeRTOS_errno; + } + #endif + + /* Select a new task to run using either the generic C or port + * optimised asm code. */ + taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + traceTASK_SWITCHED_IN(); + + /* After the new task is switched in, update the global errno. */ + #if ( configUSE_POSIX_ERRNO == 1 ) + { + FreeRTOS_errno = pxCurrentTCB->iTaskErrno; + } + #endif + + #if ( configUSE_NEWLIB_REENTRANT == 1 ) + { + /* Switch Newlib's _impure_ptr variable to point to the _reent + * structure specific to this task. + * See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html + * for additional information. */ + _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); + } + #endif /* configUSE_NEWLIB_REENTRANT */ + } +} +/*-----------------------------------------------------------*/ + +void vTaskPlaceOnEventList( List_t * const pxEventList, + const TickType_t xTicksToWait ) +{ + configASSERT( pxEventList ); + + /* THIS FUNCTION MUST BE CALLED WITH EITHER INTERRUPTS DISABLED OR THE + * SCHEDULER SUSPENDED AND THE QUEUE BEING ACCESSED LOCKED. */ + + /* Place the event list item of the TCB in the appropriate event list. + * This is placed in the list in priority order so the highest priority task + * is the first to be woken by the event. + * + * Note: Lists are sorted in ascending order by ListItem_t.xItemValue. + * Normally, the xItemValue of a TCB's ListItem_t members is: + * xItemValue = ( configMAX_PRIORITIES - uxPriority ) + * Therefore, the event list is sorted in descending priority order. + * + * The queue that contains the event list is locked, preventing + * simultaneous access from interrupts. */ + vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) ); + + prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); +} +/*-----------------------------------------------------------*/ + +void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, + const TickType_t xItemValue, + const TickType_t xTicksToWait ) +{ + configASSERT( pxEventList ); + + /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. It is used by + * the event groups implementation. */ + configASSERT( uxSchedulerSuspended != 0 ); + + /* Store the item value in the event list item. It is safe to access the + * event list item here as interrupts won't access the event list item of a + * task that is not in the Blocked state. */ + listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE ); + + /* Place the event list item of the TCB at the end of the appropriate event + * list. It is safe to access the event list here because it is part of an + * event group implementation - and interrupts don't access event groups + * directly (instead they access them indirectly by pending function calls to + * the task level). */ + listINSERT_END( pxEventList, &( pxCurrentTCB->xEventListItem ) ); + + prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TIMERS == 1 ) + + void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, + TickType_t xTicksToWait, + const BaseType_t xWaitIndefinitely ) + { + configASSERT( pxEventList ); + + /* This function should not be called by application code hence the + * 'Restricted' in its name. It is not part of the public API. It is + * designed for use by kernel code, and has special calling requirements - + * it should be called with the scheduler suspended. */ + + + /* Place the event list item of the TCB in the appropriate event list. + * In this case it is assume that this is the only task that is going to + * be waiting on this event list, so the faster vListInsertEnd() function + * can be used in place of vListInsert. */ + listINSERT_END( pxEventList, &( pxCurrentTCB->xEventListItem ) ); + + /* If the task should block indefinitely then set the block time to a + * value that will be recognised as an indefinite delay inside the + * prvAddCurrentTaskToDelayedList() function. */ + if( xWaitIndefinitely != pdFALSE ) + { + xTicksToWait = portMAX_DELAY; + } + + traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) ); + prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely ); + } + +#endif /* configUSE_TIMERS */ +/*-----------------------------------------------------------*/ + +BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) +{ + TCB_t * pxUnblockedTCB; + BaseType_t xReturn; + + /* THIS FUNCTION MUST BE CALLED FROM A CRITICAL SECTION. It can also be + * called from a critical section within an ISR. */ + + /* The event list is sorted in priority order, so the first in the list can + * be removed as it is known to be the highest priority. Remove the TCB from + * the delayed list, and add it to the ready list. + * + * If an event is for a queue that is locked then this function will never + * get called - the lock count on the queue will get modified instead. This + * means exclusive access to the event list is guaranteed here. + * + * This function assumes that a check has already been made to ensure that + * pxEventList is not empty. */ + pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + configASSERT( pxUnblockedTCB ); + listREMOVE_ITEM( &( pxUnblockedTCB->xEventListItem ) ); + + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + { + listREMOVE_ITEM( &( pxUnblockedTCB->xStateListItem ) ); + prvAddTaskToReadyList( pxUnblockedTCB ); + + #if ( configUSE_TICKLESS_IDLE != 0 ) + { + /* If a task is blocked on a kernel object then xNextTaskUnblockTime + * might be set to the blocked task's time out time. If the task is + * unblocked for a reason other than a timeout xNextTaskUnblockTime is + * normally left unchanged, because it is automatically reset to a new + * value when the tick count equals xNextTaskUnblockTime. However if + * tickless idling is used it might be more important to enter sleep mode + * at the earliest possible time - so reset xNextTaskUnblockTime here to + * ensure it is updated at the earliest possible time. */ + prvResetNextTaskUnblockTime(); + } + #endif + } + else + { + /* The delayed and ready lists cannot be accessed, so hold this task + * pending until the scheduler is resumed. */ + listINSERT_END( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) ); + } + + if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority ) + { + /* Return true if the task removed from the event list has a higher + * priority than the calling task. This allows the calling task to know if + * it should force a context switch now. */ + xReturn = pdTRUE; + + /* Mark that a yield is pending in case the user is not using the + * "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ + xYieldPending = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, + const TickType_t xItemValue ) +{ + TCB_t * pxUnblockedTCB; + + /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. It is used by + * the event flags implementation. */ + configASSERT( uxSchedulerSuspended != pdFALSE ); + + /* Store the new item value in the event list. */ + listSET_LIST_ITEM_VALUE( pxEventListItem, xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE ); + + /* Remove the event list form the event flag. Interrupts do not access + * event flags. */ + pxUnblockedTCB = listGET_LIST_ITEM_OWNER( pxEventListItem ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + configASSERT( pxUnblockedTCB ); + listREMOVE_ITEM( pxEventListItem ); + + #if ( configUSE_TICKLESS_IDLE != 0 ) + { + /* If a task is blocked on a kernel object then xNextTaskUnblockTime + * might be set to the blocked task's time out time. If the task is + * unblocked for a reason other than a timeout xNextTaskUnblockTime is + * normally left unchanged, because it is automatically reset to a new + * value when the tick count equals xNextTaskUnblockTime. However if + * tickless idling is used it might be more important to enter sleep mode + * at the earliest possible time - so reset xNextTaskUnblockTime here to + * ensure it is updated at the earliest possible time. */ + prvResetNextTaskUnblockTime(); + } + #endif + + /* Remove the task from the delayed list and add it to the ready list. The + * scheduler is suspended so interrupts will not be accessing the ready + * lists. */ + listREMOVE_ITEM( &( pxUnblockedTCB->xStateListItem ) ); + prvAddTaskToReadyList( pxUnblockedTCB ); + + if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority ) + { + /* The unblocked task has a priority above that of the calling task, so + * a context switch is required. This function is called with the + * scheduler suspended so xYieldPending is set so the context switch + * occurs immediately that the scheduler is resumed (unsuspended). */ + xYieldPending = pdTRUE; + } +} +/*-----------------------------------------------------------*/ + +void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) +{ + configASSERT( pxTimeOut ); + taskENTER_CRITICAL(); + { + pxTimeOut->xOverflowCount = xNumOfOverflows; + pxTimeOut->xTimeOnEntering = xTickCount; + } + taskEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) +{ + /* For internal use only as it does not use a critical section. */ + pxTimeOut->xOverflowCount = xNumOfOverflows; + pxTimeOut->xTimeOnEntering = xTickCount; +} +/*-----------------------------------------------------------*/ + +BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) +{ + BaseType_t xReturn; + + configASSERT( pxTimeOut ); + configASSERT( pxTicksToWait ); + + taskENTER_CRITICAL(); + { + /* Minor optimisation. The tick count cannot change in this block. */ + const TickType_t xConstTickCount = xTickCount; + const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering; + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + if( pxCurrentTCB->ucDelayAborted != ( uint8_t ) pdFALSE ) + { + /* The delay was aborted, which is not the same as a time out, + * but has the same result. */ + pxCurrentTCB->ucDelayAborted = pdFALSE; + xReturn = pdTRUE; + } + else + #endif + + #if ( INCLUDE_vTaskSuspend == 1 ) + if( *pxTicksToWait == portMAX_DELAY ) + { + /* If INCLUDE_vTaskSuspend is set to 1 and the block time + * specified is the maximum block time then the task should block + * indefinitely, and therefore never time out. */ + xReturn = pdFALSE; + } + else + #endif + + if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */ + { + /* The tick count is greater than the time at which + * vTaskSetTimeout() was called, but has also overflowed since + * vTaskSetTimeOut() was called. It must have wrapped all the way + * around and gone past again. This passed since vTaskSetTimeout() + * was called. */ + xReturn = pdTRUE; + *pxTicksToWait = ( TickType_t ) 0; + } + else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */ + { + /* Not a genuine timeout. Adjust parameters for time remaining. */ + *pxTicksToWait -= xElapsedTime; + vTaskInternalSetTimeOutState( pxTimeOut ); + xReturn = pdFALSE; + } + else + { + *pxTicksToWait = ( TickType_t ) 0; + xReturn = pdTRUE; + } + } + taskEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vTaskMissedYield( void ) +{ + xYieldPending = pdTRUE; +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) + { + UBaseType_t uxReturn; + TCB_t const * pxTCB; + + if( xTask != NULL ) + { + pxTCB = xTask; + uxReturn = pxTCB->uxTaskNumber; + } + else + { + uxReturn = 0U; + } + + return uxReturn; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + void vTaskSetTaskNumber( TaskHandle_t xTask, + const UBaseType_t uxHandle ) + { + TCB_t * pxTCB; + + if( xTask != NULL ) + { + pxTCB = xTask; + pxTCB->uxTaskNumber = uxHandle; + } + } + +#endif /* configUSE_TRACE_FACILITY */ + +/* + * ----------------------------------------------------------- + * The Idle task. + * ---------------------------------------------------------- + * + * The portTASK_FUNCTION() macro is used to allow port/compiler specific + * language extensions. The equivalent prototype for this function is: + * + * void prvIdleTask( void *pvParameters ); + * + */ +static portTASK_FUNCTION( prvIdleTask, pvParameters ) +{ + /* Stop warnings. */ + ( void ) pvParameters; + + /** THIS IS THE RTOS IDLE TASK - WHICH IS CREATED AUTOMATICALLY WHEN THE + * SCHEDULER IS STARTED. **/ + + /* In case a task that has a secure context deletes itself, in which case + * the idle task is responsible for deleting the task's secure context, if + * any. */ + portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE ); + + for( ; ; ) + { + /* See if any tasks have deleted themselves - if so then the idle task + * is responsible for freeing the deleted task's TCB and stack. */ + prvCheckTasksWaitingTermination(); + + #if ( configUSE_PREEMPTION == 0 ) + { + /* If we are not using preemption we keep forcing a task switch to + * see if any other task has become available. If we are using + * preemption we don't need to do this as any task becoming available + * will automatically get the processor anyway. */ + taskYIELD(); + } + #endif /* configUSE_PREEMPTION */ + + #if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) + { + /* When using preemption tasks of equal priority will be + * timesliced. If a task that is sharing the idle priority is ready + * to run then the idle task should yield before the end of the + * timeslice. + * + * A critical region is not required here as we are just reading from + * the list, and an occasional incorrect value will not matter. If + * the ready list at the idle priority contains more than one task + * then a task other than the idle task is ready to execute. */ + if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 ) + { + taskYIELD(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */ + + #if ( configUSE_IDLE_HOOK == 1 ) + { + extern void vApplicationIdleHook( void ); + + /* Call the user defined function from within the idle task. This + * allows the application designer to add background functionality + * without the overhead of a separate task. + * NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES, + * CALL A FUNCTION THAT MIGHT BLOCK. */ + vApplicationIdleHook(); + } + #endif /* configUSE_IDLE_HOOK */ + + /* This conditional compilation should use inequality to 0, not equality + * to 1. This is to ensure portSUPPRESS_TICKS_AND_SLEEP() is called when + * user defined low power mode implementations require + * configUSE_TICKLESS_IDLE to be set to a value other than 1. */ + #if ( configUSE_TICKLESS_IDLE != 0 ) + { + TickType_t xExpectedIdleTime; + + /* It is not desirable to suspend then resume the scheduler on + * each iteration of the idle task. Therefore, a preliminary + * test of the expected idle time is performed without the + * scheduler suspended. The result here is not necessarily + * valid. */ + xExpectedIdleTime = prvGetExpectedIdleTime(); + + if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP ) + { + vTaskSuspendAll(); + { + /* Now the scheduler is suspended, the expected idle + * time can be sampled again, and this time its value can + * be used. */ + configASSERT( xNextTaskUnblockTime >= xTickCount ); + xExpectedIdleTime = prvGetExpectedIdleTime(); + + /* Define the following macro to set xExpectedIdleTime to 0 + * if the application does not want + * portSUPPRESS_TICKS_AND_SLEEP() to be called. */ + configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( xExpectedIdleTime ); + + if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP ) + { + traceLOW_POWER_IDLE_BEGIN(); + portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ); + traceLOW_POWER_IDLE_END(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + ( void ) xTaskResumeAll(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_TICKLESS_IDLE */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE != 0 ) + + eSleepModeStatus eTaskConfirmSleepModeStatus( void ) + { + /* The idle task exists in addition to the application tasks. */ + const UBaseType_t uxNonApplicationTasks = 1; + eSleepModeStatus eReturn = eStandardSleep; + + /* This function must be called from a critical section. */ + + if( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0 ) + { + /* A task was made ready while the scheduler was suspended. */ + eReturn = eAbortSleep; + } + else if( xYieldPending != pdFALSE ) + { + /* A yield was pended while the scheduler was suspended. */ + eReturn = eAbortSleep; + } + else if( xPendedTicks != 0 ) + { + /* A tick interrupt has already occurred but was held pending + * because the scheduler is suspended. */ + eReturn = eAbortSleep; + } + else + { + /* If all the tasks are in the suspended list (which might mean they + * have an infinite block time rather than actually being suspended) + * then it is safe to turn all clocks off and just wait for external + * interrupts. */ + if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == ( uxCurrentNumberOfTasks - uxNonApplicationTasks ) ) + { + eReturn = eNoTasksWaitingTimeout; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + return eReturn; + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) + { + TCB_t * pxTCB; + + if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS ) + { + pxTCB = prvGetTCBFromHandle( xTaskToSet ); + configASSERT( pxTCB != NULL ); + pxTCB->pvThreadLocalStoragePointers[ xIndex ] = pvValue; + } + } + +#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */ +/*-----------------------------------------------------------*/ + +#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void * pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) + { + void * pvReturn = NULL; + TCB_t * pxTCB; + + if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS ) + { + pxTCB = prvGetTCBFromHandle( xTaskToQuery ); + pvReturn = pxTCB->pvThreadLocalStoragePointers[ xIndex ]; + } + else + { + pvReturn = NULL; + } + + return pvReturn; + } + +#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */ +/*-----------------------------------------------------------*/ + +#if ( portUSING_MPU_WRAPPERS == 1 ) + + void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify, + const MemoryRegion_t * const xRegions ) + { + TCB_t * pxTCB; + + /* If null is passed in here then we are modifying the MPU settings of + * the calling task. */ + pxTCB = prvGetTCBFromHandle( xTaskToModify ); + + vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, NULL, 0 ); + } + +#endif /* portUSING_MPU_WRAPPERS */ +/*-----------------------------------------------------------*/ + +static void prvInitialiseTaskLists( void ) +{ + UBaseType_t uxPriority; + + for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) + { + vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) ); + } + + vListInitialise( &xDelayedTaskList1 ); + vListInitialise( &xDelayedTaskList2 ); + vListInitialise( &xPendingReadyList ); + + #if ( INCLUDE_vTaskDelete == 1 ) + { + vListInitialise( &xTasksWaitingTermination ); + } + #endif /* INCLUDE_vTaskDelete */ + + #if ( INCLUDE_vTaskSuspend == 1 ) + { + vListInitialise( &xSuspendedTaskList ); + } + #endif /* INCLUDE_vTaskSuspend */ + + /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList + * using list2. */ + pxDelayedTaskList = &xDelayedTaskList1; + pxOverflowDelayedTaskList = &xDelayedTaskList2; +} +/*-----------------------------------------------------------*/ + +static void prvCheckTasksWaitingTermination( void ) +{ + /** THIS FUNCTION IS CALLED FROM THE RTOS IDLE TASK **/ + + #if ( INCLUDE_vTaskDelete == 1 ) + { + TCB_t * pxTCB; + + /* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL() + * being called too often in the idle task. */ + while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) + { + taskENTER_CRITICAL(); + { + pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + --uxCurrentNumberOfTasks; + --uxDeletedTasksWaitingCleanUp; + } + taskEXIT_CRITICAL(); + + prvDeleteTCB( pxTCB ); + } + } + #endif /* INCLUDE_vTaskDelete */ +} +/*-----------------------------------------------------------*/ + +// Added by Inertial Sense + +#if( configUSE_TRACE_FACILITY == 1 ) + void vTaskResetRunTimeCounter( TaskHandle_t xTask ) + { + TCB_t *pxTCB; + + /* xTask is NULL then get the state of the calling task. */ + pxTCB = prvGetTCBFromHandle( xTask ); + + pxTCB->ulRunTimeCounter = 0; + } +#endif /* configUSE_TRACE_FACILITY */ + +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + void vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) + { + TCB_t * pxTCB; + + /* xTask is NULL then get the state of the calling task. */ + pxTCB = prvGetTCBFromHandle( xTask ); + + pxTaskStatus->xHandle = ( TaskHandle_t ) pxTCB; + pxTaskStatus->pcTaskName = ( const char * ) &( pxTCB->pcTaskName[ 0 ] ); + pxTaskStatus->uxCurrentPriority = pxTCB->uxPriority; + pxTaskStatus->pxStackBase = pxTCB->pxStack; + pxTaskStatus->xTaskNumber = pxTCB->uxTCBNumber; + + #if ( configUSE_MUTEXES == 1 ) + { + pxTaskStatus->uxBasePriority = pxTCB->uxBasePriority; + } + #else + { + pxTaskStatus->uxBasePriority = 0; + } + #endif + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + { + pxTaskStatus->ulRunTimeCounter = pxTCB->ulRunTimeCounter; + } + #else + { + pxTaskStatus->ulRunTimeCounter = ( configRUN_TIME_COUNTER_TYPE ) 0; + } + #endif + + /* Obtaining the task state is a little fiddly, so is only done if the + * value of eState passed into this function is eInvalid - otherwise the + * state is just set to whatever is passed in. */ + if( eState != eInvalid ) + { + if( pxTCB == pxCurrentTCB ) + { + pxTaskStatus->eCurrentState = eRunning; + } + else + { + pxTaskStatus->eCurrentState = eState; + + #if ( INCLUDE_vTaskSuspend == 1 ) + { + /* If the task is in the suspended list then there is a + * chance it is actually just blocked indefinitely - so really + * it should be reported as being in the Blocked state. */ + if( eState == eSuspended ) + { + vTaskSuspendAll(); + { + if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) + { + pxTaskStatus->eCurrentState = eBlocked; + } + } + ( void ) xTaskResumeAll(); + } + } + #endif /* INCLUDE_vTaskSuspend */ + } + } + else + { + pxTaskStatus->eCurrentState = eTaskGetState( pxTCB ); + } + + /* Obtaining the stack space takes some time, so the xGetFreeStackSpace + * parameter is provided to allow it to be skipped. */ + if( xGetFreeStackSpace != pdFALSE ) + { + #if ( portSTACK_GROWTH > 0 ) + { + pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxEndOfStack ); + } + #else + { + pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxStack ); + } + #endif + } + else + { + pxTaskStatus->usStackHighWaterMark = 0; + } + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t * pxTaskStatusArray, + List_t * pxList, + eTaskState eState ) + { + configLIST_VOLATILE TCB_t * pxNextTCB, * pxFirstTCB; + UBaseType_t uxTask = 0; + + if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 ) + { + listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + + /* Populate an TaskStatus_t structure within the + * pxTaskStatusArray array for each task that is referenced from + * pxList. See the definition of TaskStatus_t in task.h for the + * meaning of each TaskStatus_t structure member. */ + do + { + listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + vTaskGetInfo( ( TaskHandle_t ) pxNextTCB, &( pxTaskStatusArray[ uxTask ] ), pdTRUE, eState ); + uxTask++; + } while( pxNextTCB != pxFirstTCB ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return uxTask; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) + + static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) + { + uint32_t ulCount = 0U; + + while( *pucStackByte == ( uint8_t ) tskSTACK_FILL_BYTE ) + { + pucStackByte -= portSTACK_GROWTH; + ulCount++; + } + + ulCount /= ( uint32_t ) sizeof( StackType_t ); /*lint !e961 Casting is not redundant on smaller architectures. */ + + return ( configSTACK_DEPTH_TYPE ) ulCount; + } + +#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) + +/* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the + * same except for their return type. Using configSTACK_DEPTH_TYPE allows the + * user to determine the return type. It gets around the problem of the value + * overflowing on 8-bit types without breaking backward compatibility for + * applications that expect an 8-bit return type. */ + configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) + { + TCB_t * pxTCB; + uint8_t * pucEndOfStack; + configSTACK_DEPTH_TYPE uxReturn; + + /* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are + * the same except for their return type. Using configSTACK_DEPTH_TYPE + * allows the user to determine the return type. It gets around the + * problem of the value overflowing on 8-bit types without breaking + * backward compatibility for applications that expect an 8-bit return + * type. */ + + pxTCB = prvGetTCBFromHandle( xTask ); + + #if portSTACK_GROWTH < 0 + { + pucEndOfStack = ( uint8_t * ) pxTCB->pxStack; + } + #else + { + pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack; + } + #endif + + uxReturn = prvTaskCheckFreeStackSpace( pucEndOfStack ); + + return uxReturn; + } + +#endif /* INCLUDE_uxTaskGetStackHighWaterMark2 */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) + + UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) + { + TCB_t * pxTCB; + uint8_t * pucEndOfStack; + UBaseType_t uxReturn; + + pxTCB = prvGetTCBFromHandle( xTask ); + + #if portSTACK_GROWTH < 0 + { + pucEndOfStack = ( uint8_t * ) pxTCB->pxStack; + } + #else + { + pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack; + } + #endif + + uxReturn = ( UBaseType_t ) prvTaskCheckFreeStackSpace( pucEndOfStack ); + + return uxReturn; + } + +#endif /* INCLUDE_uxTaskGetStackHighWaterMark */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskDelete == 1 ) + + static void prvDeleteTCB( TCB_t * pxTCB ) + { + /* This call is required specifically for the TriCore port. It must be + * above the vPortFree() calls. The call is also used by ports/demos that + * want to allocate and clean RAM statically. */ + portCLEAN_UP_TCB( pxTCB ); + + /* Free up the memory allocated by the scheduler for the task. It is up + * to the task to free any memory allocated at the application level. + * See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html + * for additional information. */ + #if ( configUSE_NEWLIB_REENTRANT == 1 ) + { + _reclaim_reent( &( pxTCB->xNewLib_reent ) ); + } + #endif /* configUSE_NEWLIB_REENTRANT */ + + #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( portUSING_MPU_WRAPPERS == 0 ) ) + { + /* The task can only have been allocated dynamically - free both + * the stack and TCB. */ + vPortFreeStack( pxTCB->pxStack ); + vPortFree( pxTCB ); + } + #elif ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ + { + /* The task could have been allocated statically or dynamically, so + * check what was statically allocated before trying to free the + * memory. */ + if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB ) + { + /* Both the stack and TCB were allocated dynamically, so both + * must be freed. */ + vPortFreeStack( pxTCB->pxStack ); + vPortFree( pxTCB ); + } + else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY ) + { + /* Only the stack was statically allocated, so the TCB is the + * only memory that must be freed. */ + vPortFree( pxTCB ); + } + else + { + /* Neither the stack nor the TCB were allocated dynamically, so + * nothing needs to be freed. */ + configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + } + +#endif /* INCLUDE_vTaskDelete */ +/*-----------------------------------------------------------*/ + +static void prvResetNextTaskUnblockTime( void ) +{ + if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) + { + /* The new current delayed list is empty. Set xNextTaskUnblockTime to + * the maximum possible value so it is extremely unlikely that the + * if( xTickCount >= xNextTaskUnblockTime ) test will pass until + * there is an item in the delayed list. */ + xNextTaskUnblockTime = portMAX_DELAY; + } + else + { + /* The new current delayed list is not empty, get the value of + * the item at the head of the delayed list. This is the time at + * which the task at the head of the delayed list should be removed + * from the Blocked state. */ + xNextTaskUnblockTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxDelayedTaskList ); + } +} +/*-----------------------------------------------------------*/ + +#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) + + TaskHandle_t xTaskGetCurrentTaskHandle( void ) + { + TaskHandle_t xReturn; + + /* A critical section is not required as this is not called from + * an interrupt and the current TCB will always be the same for any + * individual execution thread. */ + xReturn = pxCurrentTCB; + + return xReturn; + } + +#endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + + BaseType_t xTaskGetSchedulerState( void ) + { + BaseType_t xReturn; + + if( xSchedulerRunning == pdFALSE ) + { + xReturn = taskSCHEDULER_NOT_STARTED; + } + else + { + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + { + xReturn = taskSCHEDULER_RUNNING; + } + else + { + xReturn = taskSCHEDULER_SUSPENDED; + } + } + + return xReturn; + } + +#endif /* ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_MUTEXES == 1 ) + + BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) + { + TCB_t * const pxMutexHolderTCB = pxMutexHolder; + BaseType_t xReturn = pdFALSE; + + /* If the mutex was given back by an interrupt while the queue was + * locked then the mutex holder might now be NULL. _RB_ Is this still + * needed as interrupts can no longer use mutexes? */ + if( pxMutexHolder != NULL ) + { + /* If the holder of the mutex has a priority below the priority of + * the task attempting to obtain the mutex then it will temporarily + * inherit the priority of the task attempting to obtain the mutex. */ + if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority ) + { + /* Adjust the mutex holder state to account for its new + * priority. Only reset the event list item value if the value is + * not being used for anything else. */ + if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) + { + listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* If the task being modified is in the ready state it will need + * to be moved into a new list. */ + if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE ) + { + if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + { + /* It is known that the task is in its ready list so + * there is no need to check again and the port level + * reset macro can be called directly. */ + portRESET_READY_PRIORITY( pxMutexHolderTCB->uxPriority, uxTopReadyPriority ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Inherit the priority before being moved into the new list. */ + pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; + prvAddTaskToReadyList( pxMutexHolderTCB ); + } + else + { + /* Just inherit the priority. */ + pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; + } + + traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority ); + + /* Inheritance occurred. */ + xReturn = pdTRUE; + } + else + { + if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority ) + { + /* The base priority of the mutex holder is lower than the + * priority of the task attempting to take the mutex, but the + * current priority of the mutex holder is not lower than the + * priority of the task attempting to take the mutex. + * Therefore the mutex holder must have already inherited a + * priority, but inheritance would have occurred if that had + * not been the case. */ + xReturn = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xReturn; + } + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_MUTEXES == 1 ) + + BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) + { + TCB_t * const pxTCB = pxMutexHolder; + BaseType_t xReturn = pdFALSE; + + if( pxMutexHolder != NULL ) + { + /* A task can only have an inherited priority if it holds the mutex. + * If the mutex is held by a task then it cannot be given from an + * interrupt, and if a mutex is given by the holding task then it must + * be the running state task. */ + configASSERT( pxTCB == pxCurrentTCB ); + configASSERT( pxTCB->uxMutexesHeld ); + ( pxTCB->uxMutexesHeld )--; + + /* Has the holder of the mutex inherited the priority of another + * task? */ + if( pxTCB->uxPriority != pxTCB->uxBasePriority ) + { + /* Only disinherit if no other mutexes are held. */ + if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 ) + { + /* A task can only have an inherited priority if it holds + * the mutex. If the mutex is held by a task then it cannot be + * given from an interrupt, and if a mutex is given by the + * holding task then it must be the running state task. Remove + * the holding task from the ready list. */ + if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + { + portRESET_READY_PRIORITY( pxTCB->uxPriority, uxTopReadyPriority ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Disinherit the priority before adding the task into the + * new ready list. */ + traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority ); + pxTCB->uxPriority = pxTCB->uxBasePriority; + + /* Reset the event list item value. It cannot be in use for + * any other purpose if this task is running, and it must be + * running to give back the mutex. */ + listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + prvAddTaskToReadyList( pxTCB ); + + /* Return true to indicate that a context switch is required. + * This is only actually required in the corner case whereby + * multiple mutexes were held and the mutexes were given back + * in an order different to that in which they were taken. + * If a context switch did not occur when the first mutex was + * returned, even if a task was waiting on it, then a context + * switch should occur when the last mutex is returned whether + * a task is waiting on it or not. */ + xReturn = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xReturn; + } + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_MUTEXES == 1 ) + + void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, + UBaseType_t uxHighestPriorityWaitingTask ) + { + TCB_t * const pxTCB = pxMutexHolder; + UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse; + const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1; + + if( pxMutexHolder != NULL ) + { + /* If pxMutexHolder is not NULL then the holder must hold at least + * one mutex. */ + configASSERT( pxTCB->uxMutexesHeld ); + + /* Determine the priority to which the priority of the task that + * holds the mutex should be set. This will be the greater of the + * holding task's base priority and the priority of the highest + * priority task that is waiting to obtain the mutex. */ + if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask ) + { + uxPriorityToUse = uxHighestPriorityWaitingTask; + } + else + { + uxPriorityToUse = pxTCB->uxBasePriority; + } + + /* Does the priority need to change? */ + if( pxTCB->uxPriority != uxPriorityToUse ) + { + /* Only disinherit if no other mutexes are held. This is a + * simplification in the priority inheritance implementation. If + * the task that holds the mutex is also holding other mutexes then + * the other mutexes may have caused the priority inheritance. */ + if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld ) + { + /* If a task has timed out because it already holds the + * mutex it was trying to obtain then it cannot of inherited + * its own priority. */ + configASSERT( pxTCB != pxCurrentTCB ); + + /* Disinherit the priority, remembering the previous + * priority to facilitate determining the subject task's + * state. */ + traceTASK_PRIORITY_DISINHERIT( pxTCB, uxPriorityToUse ); + uxPriorityUsedOnEntry = pxTCB->uxPriority; + pxTCB->uxPriority = uxPriorityToUse; + + /* Only reset the event list item value if the value is not + * being used for anything else. */ + if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) + { + listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* If the running task is not the task that holds the mutex + * then the task that holds the mutex could be in either the + * Ready, Blocked or Suspended states. Only remove the task + * from its current state list if it is in the Ready state as + * the task's priority is going to change and there is one + * Ready list per priority. */ + if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE ) + { + if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + { + /* It is known that the task is in its ready list so + * there is no need to check again and the port level + * reset macro can be called directly. */ + portRESET_READY_PRIORITY( pxTCB->uxPriority, uxTopReadyPriority ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + prvAddTaskToReadyList( pxTCB ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( portCRITICAL_NESTING_IN_TCB == 1 ) + + void vTaskEnterCritical( void ) + { + portDISABLE_INTERRUPTS(); + + if( xSchedulerRunning != pdFALSE ) + { + ( pxCurrentTCB->uxCriticalNesting )++; + + /* This is not the interrupt safe version of the enter critical + * function so assert() if it is being called from an interrupt + * context. Only API functions that end in "FromISR" can be used in an + * interrupt. Only assert if the critical nesting count is 1 to + * protect against recursive calls if the assert function also uses a + * critical section. */ + if( pxCurrentTCB->uxCriticalNesting == 1 ) + { + portASSERT_IF_IN_ISR(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + +#endif /* portCRITICAL_NESTING_IN_TCB */ +/*-----------------------------------------------------------*/ + +#if ( portCRITICAL_NESTING_IN_TCB == 1 ) + + void vTaskExitCritical( void ) + { + if( xSchedulerRunning != pdFALSE ) + { + if( pxCurrentTCB->uxCriticalNesting > 0U ) + { + ( pxCurrentTCB->uxCriticalNesting )--; + + if( pxCurrentTCB->uxCriticalNesting == 0U ) + { + portENABLE_INTERRUPTS(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + +#endif /* portCRITICAL_NESTING_IN_TCB */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) + + static char * prvWriteNameToBuffer( char * pcBuffer, + const char * pcTaskName ) + { + size_t x; + + /* Start by copying the entire string. */ + strcpy( pcBuffer, pcTaskName ); + + /* Pad the end of the string with spaces to ensure columns line up when + * printed out. */ + for( x = strlen( pcBuffer ); x < ( size_t ) ( configMAX_TASK_NAME_LEN - 1 ); x++ ) + { + pcBuffer[ x ] = ' '; + } + + /* Terminate. */ + pcBuffer[ x ] = ( char ) 0x00; + + /* Return the new end of string. */ + return &( pcBuffer[ x ] ); + } + +#endif /* ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + + void vTaskList( char * pcWriteBuffer ) + { + TaskStatus_t * pxTaskStatusArray; + UBaseType_t uxArraySize, x; + char cStatus; + + /* + * PLEASE NOTE: + * + * This function is provided for convenience only, and is used by many + * of the demo applications. Do not consider it to be part of the + * scheduler. + * + * vTaskList() calls uxTaskGetSystemState(), then formats part of the + * uxTaskGetSystemState() output into a human readable table that + * displays task: names, states, priority, stack usage and task number. + * Stack usage specified as the number of unused StackType_t words stack can hold + * on top of stack - not the number of bytes. + * + * vTaskList() has a dependency on the sprintf() C library function that + * might bloat the code size, use a lot of stack, and provide different + * results on different platforms. An alternative, tiny, third party, + * and limited functionality implementation of sprintf() is provided in + * many of the FreeRTOS/Demo sub-directories in a file called + * printf-stdarg.c (note printf-stdarg.c does not provide a full + * snprintf() implementation!). + * + * It is recommended that production systems call uxTaskGetSystemState() + * directly to get access to raw stats data, rather than indirectly + * through a call to vTaskList(). + */ + + + /* Make sure the write buffer does not contain a string. */ + *pcWriteBuffer = ( char ) 0x00; + + /* Take a snapshot of the number of tasks in case it changes while this + * function is executing. */ + uxArraySize = uxCurrentNumberOfTasks; + + /* Allocate an array index for each task. NOTE! if + * configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will + * equate to NULL. */ + pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */ + + if( pxTaskStatusArray != NULL ) + { + /* Generate the (binary) data. */ + uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, NULL ); + + /* Create a human readable table from the binary data. */ + for( x = 0; x < uxArraySize; x++ ) + { + switch( pxTaskStatusArray[ x ].eCurrentState ) + { + case eRunning: + cStatus = tskRUNNING_CHAR; + break; + + case eReady: + cStatus = tskREADY_CHAR; + break; + + case eBlocked: + cStatus = tskBLOCKED_CHAR; + break; + + case eSuspended: + cStatus = tskSUSPENDED_CHAR; + break; + + case eDeleted: + cStatus = tskDELETED_CHAR; + break; + + case eInvalid: /* Fall through. */ + default: /* Should not get here, but it is included + * to prevent static checking errors. */ + cStatus = ( char ) 0x00; + break; + } + + /* Write the task name to the string, padding with spaces so it + * can be printed in tabular form more easily. */ + pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName ); + + /* Write the rest of the string. */ + sprintf( pcWriteBuffer, "\t%c\t%u\t%u\t%u\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */ + pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */ + } + + /* Free the array again. NOTE! If configSUPPORT_DYNAMIC_ALLOCATION + * is 0 then vPortFree() will be #defined to nothing. */ + vPortFree( pxTaskStatusArray ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + +#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ +/*----------------------------------------------------------*/ + +#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + + void vTaskGetRunTimeStats( char * pcWriteBuffer ) + { + TaskStatus_t * pxTaskStatusArray; + UBaseType_t uxArraySize, x; + configRUN_TIME_COUNTER_TYPE ulTotalTime, ulStatsAsPercentage; + + #if ( configUSE_TRACE_FACILITY != 1 ) + { + #error configUSE_TRACE_FACILITY must also be set to 1 in FreeRTOSConfig.h to use vTaskGetRunTimeStats(). + } + #endif + + /* + * PLEASE NOTE: + * + * This function is provided for convenience only, and is used by many + * of the demo applications. Do not consider it to be part of the + * scheduler. + * + * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part + * of the uxTaskGetSystemState() output into a human readable table that + * displays the amount of time each task has spent in the Running state + * in both absolute and percentage terms. + * + * vTaskGetRunTimeStats() has a dependency on the sprintf() C library + * function that might bloat the code size, use a lot of stack, and + * provide different results on different platforms. An alternative, + * tiny, third party, and limited functionality implementation of + * sprintf() is provided in many of the FreeRTOS/Demo sub-directories in + * a file called printf-stdarg.c (note printf-stdarg.c does not provide + * a full snprintf() implementation!). + * + * It is recommended that production systems call uxTaskGetSystemState() + * directly to get access to raw stats data, rather than indirectly + * through a call to vTaskGetRunTimeStats(). + */ + + /* Make sure the write buffer does not contain a string. */ + *pcWriteBuffer = ( char ) 0x00; + + /* Take a snapshot of the number of tasks in case it changes while this + * function is executing. */ + uxArraySize = uxCurrentNumberOfTasks; + + /* Allocate an array index for each task. NOTE! If + * configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will + * equate to NULL. */ + pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */ + + if( pxTaskStatusArray != NULL ) + { + /* Generate the (binary) data. */ + uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalTime ); + + /* For percentage calculations. */ + ulTotalTime /= 100UL; + + /* Avoid divide by zero errors. */ + if( ulTotalTime > 0UL ) + { + /* Create a human readable table from the binary data. */ + for( x = 0; x < uxArraySize; x++ ) + { + /* What percentage of the total run time has the task used? + * This will always be rounded down to the nearest integer. + * ulTotalRunTime has already been divided by 100. */ + ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalTime; + + /* Write the task name to the string, padding with + * spaces so it can be printed in tabular form more + * easily. */ + pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName ); + + if( ulStatsAsPercentage > 0UL ) + { + #ifdef portLU_PRINTF_SPECIFIER_REQUIRED + { + sprintf( pcWriteBuffer, "\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage ); + } + #else + { + /* sizeof( int ) == sizeof( long ) so a smaller + * printf() library can be used. */ + sprintf( pcWriteBuffer, "\t%u\t\t%u%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */ + } + #endif + } + else + { + /* If the percentage is zero here then the task has + * consumed less than 1% of the total run time. */ + #ifdef portLU_PRINTF_SPECIFIER_REQUIRED + { + sprintf( pcWriteBuffer, "\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter ); + } + #else + { + /* sizeof( int ) == sizeof( long ) so a smaller + * printf() library can be used. */ + sprintf( pcWriteBuffer, "\t%u\t\t<1%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */ + } + #endif + } + + pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */ + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Free the array again. NOTE! If configSUPPORT_DYNAMIC_ALLOCATION + * is 0 then vPortFree() will be #defined to nothing. */ + vPortFree( pxTaskStatusArray ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + +#endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +TickType_t uxTaskResetEventItemValue( void ) +{ + TickType_t uxReturn; + + uxReturn = listGET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ) ); + + /* Reset the event list item to its normal value - so it can be used with + * queues and semaphores. */ + listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_MUTEXES == 1 ) + + TaskHandle_t pvTaskIncrementMutexHeldCount( void ) + { + /* If xSemaphoreCreateMutex() is called before any tasks have been created + * then pxCurrentTCB will be NULL. */ + if( pxCurrentTCB != NULL ) + { + ( pxCurrentTCB->uxMutexesHeld )++; + } + + return pxCurrentTCB; + } + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t ulTaskGenericNotifyTake( UBaseType_t uxIndexToWait, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) + { + uint32_t ulReturn; + + configASSERT( uxIndexToWait < configTASK_NOTIFICATION_ARRAY_ENTRIES ); + + taskENTER_CRITICAL(); + { + /* Only block if the notification count is not already non-zero. */ + if( pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] == 0UL ) + { + /* Mark this task as waiting for a notification. */ + pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskWAITING_NOTIFICATION; + + if( xTicksToWait > ( TickType_t ) 0 ) + { + prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); + traceTASK_NOTIFY_TAKE_BLOCK( uxIndexToWait ); + + /* All ports are written to allow a yield in a critical + * section (some will yield immediately, others wait until the + * critical section exits) - but it is not something that + * application code should ever do. */ + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + taskENTER_CRITICAL(); + { + traceTASK_NOTIFY_TAKE( uxIndexToWait ); + ulReturn = pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ]; + + if( ulReturn != 0UL ) + { + if( xClearCountOnExit != pdFALSE ) + { + pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] = 0UL; + } + else + { + pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] = ulReturn - ( uint32_t ) 1; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskNOT_WAITING_NOTIFICATION; + } + taskEXIT_CRITICAL(); + + return ulReturn; + } + +#endif /* configUSE_TASK_NOTIFICATIONS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t xTaskGenericNotifyWait( UBaseType_t uxIndexToWait, + uint32_t ulBitsToClearOnEntry, + uint32_t ulBitsToClearOnExit, + uint32_t * pulNotificationValue, + TickType_t xTicksToWait ) + { + BaseType_t xReturn; + + configASSERT( uxIndexToWait < configTASK_NOTIFICATION_ARRAY_ENTRIES ); + + taskENTER_CRITICAL(); + { + /* Only block if a notification is not already pending. */ + if( pxCurrentTCB->ucNotifyState[ uxIndexToWait ] != taskNOTIFICATION_RECEIVED ) + { + /* Clear bits in the task's notification value as bits may get + * set by the notifying task or interrupt. This can be used to + * clear the value to zero. */ + pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] &= ~ulBitsToClearOnEntry; + + /* Mark this task as waiting for a notification. */ + pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskWAITING_NOTIFICATION; + + if( xTicksToWait > ( TickType_t ) 0 ) + { + prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); + traceTASK_NOTIFY_WAIT_BLOCK( uxIndexToWait ); + + /* All ports are written to allow a yield in a critical + * section (some will yield immediately, others wait until the + * critical section exits) - but it is not something that + * application code should ever do. */ + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + taskENTER_CRITICAL(); + { + traceTASK_NOTIFY_WAIT( uxIndexToWait ); + + if( pulNotificationValue != NULL ) + { + /* Output the current notification value, which may or may not + * have changed. */ + *pulNotificationValue = pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ]; + } + + /* If ucNotifyValue is set then either the task never entered the + * blocked state (because a notification was already pending) or the + * task unblocked because of a notification. Otherwise the task + * unblocked because of a timeout. */ + if( pxCurrentTCB->ucNotifyState[ uxIndexToWait ] != taskNOTIFICATION_RECEIVED ) + { + /* A notification was not received. */ + xReturn = pdFALSE; + } + else + { + /* A notification was already pending or a notification was + * received while the task was waiting. */ + pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] &= ~ulBitsToClearOnExit; + xReturn = pdTRUE; + } + + pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskNOT_WAITING_NOTIFICATION; + } + taskEXIT_CRITICAL(); + + return xReturn; + } + +#endif /* configUSE_TASK_NOTIFICATIONS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + uint32_t ulValue, + eNotifyAction eAction, + uint32_t * pulPreviousNotificationValue ) + { + TCB_t * pxTCB; + BaseType_t xReturn = pdPASS; + uint8_t ucOriginalNotifyState; + + configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES ); + configASSERT( xTaskToNotify ); + pxTCB = xTaskToNotify; + + taskENTER_CRITICAL(); + { + if( pulPreviousNotificationValue != NULL ) + { + *pulPreviousNotificationValue = pxTCB->ulNotifiedValue[ uxIndexToNotify ]; + } + + ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ]; + + pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED; + + switch( eAction ) + { + case eSetBits: + pxTCB->ulNotifiedValue[ uxIndexToNotify ] |= ulValue; + break; + + case eIncrement: + ( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++; + break; + + case eSetValueWithOverwrite: + pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue; + break; + + case eSetValueWithoutOverwrite: + + if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED ) + { + pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue; + } + else + { + /* The value could not be written to the task. */ + xReturn = pdFAIL; + } + + break; + + case eNoAction: + + /* The task is being notified without its notify value being + * updated. */ + break; + + default: + + /* Should not get here if all enums are handled. + * Artificially force an assert by testing a value the + * compiler can't assume is const. */ + configASSERT( xTickCount == ( TickType_t ) 0 ); + + break; + } + + traceTASK_NOTIFY( uxIndexToNotify ); + + /* If the task is in the blocked state specifically to wait for a + * notification then unblock it now. */ + if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) + { + listREMOVE_ITEM( &( pxTCB->xStateListItem ) ); + prvAddTaskToReadyList( pxTCB ); + + /* The task should not have been on an event list. */ + configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); + + #if ( configUSE_TICKLESS_IDLE != 0 ) + { + /* If a task is blocked waiting for a notification then + * xNextTaskUnblockTime might be set to the blocked task's time + * out time. If the task is unblocked for a reason other than + * a timeout xNextTaskUnblockTime is normally left unchanged, + * because it will automatically get reset to a new value when + * the tick count equals xNextTaskUnblockTime. However if + * tickless idling is used it might be more important to enter + * sleep mode at the earliest possible time - so reset + * xNextTaskUnblockTime here to ensure it is updated at the + * earliest possible time. */ + prvResetNextTaskUnblockTime(); + } + #endif + + if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) + { + /* The notified task has a priority above the currently + * executing task so a yield is required. */ + taskYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + return xReturn; + } + +#endif /* configUSE_TASK_NOTIFICATIONS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + uint32_t ulValue, + eNotifyAction eAction, + uint32_t * pulPreviousNotificationValue, + BaseType_t * pxHigherPriorityTaskWoken ) + { + TCB_t * pxTCB; + uint8_t ucOriginalNotifyState; + BaseType_t xReturn = pdPASS; + UBaseType_t uxSavedInterruptStatus; + + configASSERT( xTaskToNotify ); + configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES ); + + /* RTOS ports that support interrupt nesting have the concept of a + * maximum system call (or maximum API call) interrupt priority. + * Interrupts that are above the maximum system call priority are keep + * permanently enabled, even when the RTOS kernel is in a critical section, + * but cannot make any calls to FreeRTOS API functions. If configASSERT() + * is defined in FreeRTOSConfig.h then + * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has + * been assigned a priority above the configured maximum system call + * priority. Only FreeRTOS functions that end in FromISR can be called + * from interrupts that have been assigned a priority at or (logically) + * below the maximum system call interrupt priority. FreeRTOS maintains a + * separate interrupt safe API to ensure interrupt entry is as fast and as + * simple as possible. More information (albeit Cortex-M specific) is + * provided on the following link: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + pxTCB = xTaskToNotify; + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + if( pulPreviousNotificationValue != NULL ) + { + *pulPreviousNotificationValue = pxTCB->ulNotifiedValue[ uxIndexToNotify ]; + } + + ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ]; + pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED; + + switch( eAction ) + { + case eSetBits: + pxTCB->ulNotifiedValue[ uxIndexToNotify ] |= ulValue; + break; + + case eIncrement: + ( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++; + break; + + case eSetValueWithOverwrite: + pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue; + break; + + case eSetValueWithoutOverwrite: + + if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED ) + { + pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue; + } + else + { + /* The value could not be written to the task. */ + xReturn = pdFAIL; + } + + break; + + case eNoAction: + + /* The task is being notified without its notify value being + * updated. */ + break; + + default: + + /* Should not get here if all enums are handled. + * Artificially force an assert by testing a value the + * compiler can't assume is const. */ + configASSERT( xTickCount == ( TickType_t ) 0 ); + break; + } + + traceTASK_NOTIFY_FROM_ISR( uxIndexToNotify ); + + /* If the task is in the blocked state specifically to wait for a + * notification then unblock it now. */ + if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) + { + /* The task should not have been on an event list. */ + configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); + + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + { + listREMOVE_ITEM( &( pxTCB->xStateListItem ) ); + prvAddTaskToReadyList( pxTCB ); + } + else + { + /* The delayed and ready lists cannot be accessed, so hold + * this task pending until the scheduler is resumed. */ + listINSERT_END( &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); + } + + if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) + { + /* The notified task has a priority above the currently + * executing task so a yield is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + + /* Mark that a yield is pending in case the user is not + * using the "xHigherPriorityTaskWoken" parameter to an ISR + * safe FreeRTOS function. */ + xYieldPending = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; + } + +#endif /* configUSE_TASK_NOTIFICATIONS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + void vTaskGenericNotifyGiveFromISR( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + BaseType_t * pxHigherPriorityTaskWoken ) + { + TCB_t * pxTCB; + uint8_t ucOriginalNotifyState; + UBaseType_t uxSavedInterruptStatus; + + configASSERT( xTaskToNotify ); + configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES ); + + /* RTOS ports that support interrupt nesting have the concept of a + * maximum system call (or maximum API call) interrupt priority. + * Interrupts that are above the maximum system call priority are keep + * permanently enabled, even when the RTOS kernel is in a critical section, + * but cannot make any calls to FreeRTOS API functions. If configASSERT() + * is defined in FreeRTOSConfig.h then + * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has + * been assigned a priority above the configured maximum system call + * priority. Only FreeRTOS functions that end in FromISR can be called + * from interrupts that have been assigned a priority at or (logically) + * below the maximum system call interrupt priority. FreeRTOS maintains a + * separate interrupt safe API to ensure interrupt entry is as fast and as + * simple as possible. More information (albeit Cortex-M specific) is + * provided on the following link: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + pxTCB = xTaskToNotify; + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ]; + pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED; + + /* 'Giving' is equivalent to incrementing a count in a counting + * semaphore. */ + ( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++; + + traceTASK_NOTIFY_GIVE_FROM_ISR( uxIndexToNotify ); + + /* If the task is in the blocked state specifically to wait for a + * notification then unblock it now. */ + if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) + { + /* The task should not have been on an event list. */ + configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); + + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + { + listREMOVE_ITEM( &( pxTCB->xStateListItem ) ); + prvAddTaskToReadyList( pxTCB ); + } + else + { + /* The delayed and ready lists cannot be accessed, so hold + * this task pending until the scheduler is resumed. */ + listINSERT_END( &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); + } + + if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) + { + /* The notified task has a priority above the currently + * executing task so a yield is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + + /* Mark that a yield is pending in case the user is not + * using the "xHigherPriorityTaskWoken" parameter in an ISR + * safe FreeRTOS function. */ + xYieldPending = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + } + +#endif /* configUSE_TASK_NOTIFICATIONS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) + { + TCB_t * pxTCB; + BaseType_t xReturn; + + configASSERT( uxIndexToClear < configTASK_NOTIFICATION_ARRAY_ENTRIES ); + + /* If null is passed in here then it is the calling task that is having + * its notification state cleared. */ + pxTCB = prvGetTCBFromHandle( xTask ); + + taskENTER_CRITICAL(); + { + if( pxTCB->ucNotifyState[ uxIndexToClear ] == taskNOTIFICATION_RECEIVED ) + { + pxTCB->ucNotifyState[ uxIndexToClear ] = taskNOT_WAITING_NOTIFICATION; + xReturn = pdPASS; + } + else + { + xReturn = pdFAIL; + } + } + taskEXIT_CRITICAL(); + + return xReturn; + } + +#endif /* configUSE_TASK_NOTIFICATIONS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) + { + TCB_t * pxTCB; + uint32_t ulReturn; + + /* If null is passed in here then it is the calling task that is having + * its notification state cleared. */ + pxTCB = prvGetTCBFromHandle( xTask ); + + taskENTER_CRITICAL(); + { + /* Return the notification as it was before the bits were cleared, + * then clear the bit mask. */ + ulReturn = pxTCB->ulNotifiedValue[ uxIndexToClear ]; + pxTCB->ulNotifiedValue[ uxIndexToClear ] &= ~ulBitsToClear; + } + taskEXIT_CRITICAL(); + + return ulReturn; + } + +#endif /* configUSE_TASK_NOTIFICATIONS */ +/*-----------------------------------------------------------*/ + +#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimeCounter( void ) + { + return xIdleTaskHandle->ulRunTimeCounter; + } + +#endif +/*-----------------------------------------------------------*/ + +#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimePercent( void ) + { + configRUN_TIME_COUNTER_TYPE ulTotalTime, ulReturn; + + ulTotalTime = portGET_RUN_TIME_COUNTER_VALUE(); + + /* For percentage calculations. */ + ulTotalTime /= ( configRUN_TIME_COUNTER_TYPE ) 100; + + /* Avoid divide by zero errors. */ + if( ulTotalTime > ( configRUN_TIME_COUNTER_TYPE ) 0 ) + { + ulReturn = xIdleTaskHandle->ulRunTimeCounter / ulTotalTime; + } + else + { + ulReturn = 0; + } + + return ulReturn; + } + +#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + +static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, + const BaseType_t xCanBlockIndefinitely ) +{ + TickType_t xTimeToWake; + const TickType_t xConstTickCount = xTickCount; + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + { + /* About to enter a delayed list, so ensure the ucDelayAborted flag is + * reset to pdFALSE so it can be detected as having been set to pdTRUE + * when the task leaves the Blocked state. */ + pxCurrentTCB->ucDelayAborted = pdFALSE; + } + #endif + + /* Remove the task from the ready list before adding it to the blocked list + * as the same list item is used for both lists. */ + if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + { + /* The current task must be in a ready list, so there is no need to + * check, and the port reset macro can be called directly. */ + portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task. pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + #if ( INCLUDE_vTaskSuspend == 1 ) + { + if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) ) + { + /* Add the task to the suspended task list instead of a delayed task + * list to ensure it is not woken by a timing event. It will block + * indefinitely. */ + listINSERT_END( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) ); + } + else + { + /* Calculate the time at which the task should be woken if the event + * does not occur. This may overflow but this doesn't matter, the + * kernel will manage it correctly. */ + xTimeToWake = xConstTickCount + xTicksToWait; + + /* The list item will be inserted in wake time order. */ + listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake ); + + if( xTimeToWake < xConstTickCount ) + { + /* Wake time has overflowed. Place this item in the overflow + * list. */ + vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); + } + else + { + /* The wake time has not overflowed, so the current block list + * is used. */ + vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); + + /* If the task entering the blocked state was placed at the + * head of the list of blocked tasks then xNextTaskUnblockTime + * needs to be updated too. */ + if( xTimeToWake < xNextTaskUnblockTime ) + { + xNextTaskUnblockTime = xTimeToWake; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + } + #else /* INCLUDE_vTaskSuspend */ + { + /* Calculate the time at which the task should be woken if the event + * does not occur. This may overflow but this doesn't matter, the kernel + * will manage it correctly. */ + xTimeToWake = xConstTickCount + xTicksToWait; + + /* The list item will be inserted in wake time order. */ + listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake ); + + if( xTimeToWake < xConstTickCount ) + { + /* Wake time has overflowed. Place this item in the overflow list. */ + vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); + } + else + { + /* The wake time has not overflowed, so the current block list is used. */ + vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); + + /* If the task entering the blocked state was placed at the head of the + * list of blocked tasks then xNextTaskUnblockTime needs to be updated + * too. */ + if( xTimeToWake < xNextTaskUnblockTime ) + { + xNextTaskUnblockTime = xTimeToWake; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */ + ( void ) xCanBlockIndefinitely; + } + #endif /* INCLUDE_vTaskSuspend */ +} + +/* Code below here allows additional code to be inserted into this source file, + * especially where access to file scope functions and data is needed (for example + * when performing module tests). */ + +#ifdef FREERTOS_MODULE_TEST + #include "tasks_test_access_functions.h" +#endif + + +#if ( configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1 ) + + #include "freertos_tasks_c_additions.h" + + #ifdef FREERTOS_TASKS_C_ADDITIONS_INIT + static void freertos_tasks_c_additions_init( void ) + { + FREERTOS_TASKS_C_ADDITIONS_INIT(); + } + #endif + +#endif /* if ( configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1 ) */ diff --git a/hw-libs/freertos/timers.c b/hw-libs/freertos/timers.c new file mode 100644 index 000000000..88d834b9e --- /dev/null +++ b/hw-libs/freertos/timers.c @@ -0,0 +1,1119 @@ +/* + * FreeRTOS Kernel V10.4.6 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" + +#if ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 0 ) + #error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available. +#endif + +/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified + * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined + * for the header files above, but not in this file, in order to generate the + * correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e9021 !e961 !e750. */ + + +/* This entire source file will be skipped if the application is not configured + * to include software timer functionality. This #if is closed at the very bottom + * of this file. If you want to include software timer functionality then ensure + * configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */ +#if ( configUSE_TIMERS == 1 ) + +/* Misc definitions. */ + #define tmrNO_DELAY ( ( TickType_t ) 0U ) + #define tmrMAX_TIME_BEFORE_OVERFLOW ( ( TickType_t ) -1 ) + +/* The name assigned to the timer service task. This can be overridden by + * defining trmTIMER_SERVICE_TASK_NAME in FreeRTOSConfig.h. */ + #ifndef configTIMER_SERVICE_TASK_NAME + #define configTIMER_SERVICE_TASK_NAME "Tmr Svc" + #endif + +/* Bit definitions used in the ucStatus member of a timer structure. */ + #define tmrSTATUS_IS_ACTIVE ( ( uint8_t ) 0x01 ) + #define tmrSTATUS_IS_STATICALLY_ALLOCATED ( ( uint8_t ) 0x02 ) + #define tmrSTATUS_IS_AUTORELOAD ( ( uint8_t ) 0x04 ) + +/* The definition of the timers themselves. */ + typedef struct tmrTimerControl /* The old naming convention is used to prevent breaking kernel aware debuggers. */ + { + const char * pcTimerName; /*<< Text name. This is not used by the kernel, it is included simply to make debugging easier. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + ListItem_t xTimerListItem; /*<< Standard linked list item as used by all kernel features for event management. */ + TickType_t xTimerPeriodInTicks; /*<< How quickly and often the timer expires. */ + void * pvTimerID; /*<< An ID to identify the timer. This allows the timer to be identified when the same callback is used for multiple timers. */ + TimerCallbackFunction_t pxCallbackFunction; /*<< The function that will be called when the timer expires. */ + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxTimerNumber; /*<< An ID assigned by trace tools such as FreeRTOS+Trace */ + #endif + uint8_t ucStatus; /*<< Holds bits to say if the timer was statically allocated or not, and if it is active or not. */ + } xTIMER; + +/* The old xTIMER name is maintained above then typedefed to the new Timer_t + * name below to enable the use of older kernel aware debuggers. */ + typedef xTIMER Timer_t; + +/* The definition of messages that can be sent and received on the timer queue. + * Two types of message can be queued - messages that manipulate a software timer, + * and messages that request the execution of a non-timer related callback. The + * two message types are defined in two separate structures, xTimerParametersType + * and xCallbackParametersType respectively. */ + typedef struct tmrTimerParameters + { + TickType_t xMessageValue; /*<< An optional value used by a subset of commands, for example, when changing the period of a timer. */ + Timer_t * pxTimer; /*<< The timer to which the command will be applied. */ + } TimerParameter_t; + + + typedef struct tmrCallbackParameters + { + PendedFunction_t pxCallbackFunction; /* << The callback function to execute. */ + void * pvParameter1; /* << The value that will be used as the callback functions first parameter. */ + uint32_t ulParameter2; /* << The value that will be used as the callback functions second parameter. */ + } CallbackParameters_t; + +/* The structure that contains the two message types, along with an identifier + * that is used to determine which message type is valid. */ + typedef struct tmrTimerQueueMessage + { + BaseType_t xMessageID; /*<< The command being sent to the timer service task. */ + union + { + TimerParameter_t xTimerParameters; + + /* Don't include xCallbackParameters if it is not going to be used as + * it makes the structure (and therefore the timer queue) larger. */ + #if ( INCLUDE_xTimerPendFunctionCall == 1 ) + CallbackParameters_t xCallbackParameters; + #endif /* INCLUDE_xTimerPendFunctionCall */ + } u; + } DaemonTaskMessage_t; + +/*lint -save -e956 A manual analysis and inspection has been used to determine + * which static variables must be declared volatile. */ + +/* The list in which active timers are stored. Timers are referenced in expire + * time order, with the nearest expiry time at the front of the list. Only the + * timer service task is allowed to access these lists. + * xActiveTimerList1 and xActiveTimerList2 could be at function scope but that + * breaks some kernel aware debuggers, and debuggers that reply on removing the + * static qualifier. */ + PRIVILEGED_DATA static List_t xActiveTimerList1; + PRIVILEGED_DATA static List_t xActiveTimerList2; + PRIVILEGED_DATA static List_t * pxCurrentTimerList; + PRIVILEGED_DATA static List_t * pxOverflowTimerList; + +/* A queue that is used to send commands to the timer service task. */ + PRIVILEGED_DATA static QueueHandle_t xTimerQueue = NULL; + PRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL; + +/*lint -restore */ + +/*-----------------------------------------------------------*/ + +/* + * Initialise the infrastructure used by the timer service task if it has not + * been initialised already. + */ + static void prvCheckForValidListAndQueue( void ) PRIVILEGED_FUNCTION; + +/* + * The timer service task (daemon). Timer functionality is controlled by this + * task. Other tasks communicate with the timer service task using the + * xTimerQueue queue. + */ + static portTASK_FUNCTION_PROTO( prvTimerTask, pvParameters ) PRIVILEGED_FUNCTION; + +/* + * Called by the timer service task to interpret and process a command it + * received on the timer queue. + */ + static void prvProcessReceivedCommands( void ) PRIVILEGED_FUNCTION; + +/* + * Insert the timer into either xActiveTimerList1, or xActiveTimerList2, + * depending on if the expire time causes a timer counter overflow. + */ + static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, + const TickType_t xNextExpiryTime, + const TickType_t xTimeNow, + const TickType_t xCommandTime ) PRIVILEGED_FUNCTION; + +/* + * Reload the specified auto-reload timer. If the reloading is backlogged, + * clear the backlog, calling the callback for each additional reload. When + * this function returns, the next expiry time is after xTimeNow. + */ + static void prvReloadTimer( Timer_t * const pxTimer, + TickType_t xExpiredTime, + const TickType_t xTimeNow ) PRIVILEGED_FUNCTION; + +/* + * An active timer has reached its expire time. Reload the timer if it is an + * auto-reload timer, then call its callback. + */ + static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, + const TickType_t xTimeNow ) PRIVILEGED_FUNCTION; + +/* + * The tick count has overflowed. Switch the timer lists after ensuring the + * current timer list does not still reference some timers. + */ + static void prvSwitchTimerLists( void ) PRIVILEGED_FUNCTION; + +/* + * Obtain the current tick count, setting *pxTimerListsWereSwitched to pdTRUE + * if a tick count overflow occurred since prvSampleTimeNow() was last called. + */ + static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) PRIVILEGED_FUNCTION; + +/* + * If the timer list contains any active timers then return the expire time of + * the timer that will expire first and set *pxListWasEmpty to false. If the + * timer list does not contain any timers then return 0 and set *pxListWasEmpty + * to pdTRUE. + */ + static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) PRIVILEGED_FUNCTION; + +/* + * If a timer has expired, process it. Otherwise, block the timer service task + * until either a timer does expire or a command is received. + */ + static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, + BaseType_t xListWasEmpty ) PRIVILEGED_FUNCTION; + +/* + * Called after a Timer_t structure has been allocated either statically or + * dynamically to fill in the structure's members. + */ + static void prvInitialiseNewTimer( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const TickType_t xTimerPeriodInTicks, + const UBaseType_t uxAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction, + Timer_t * pxNewTimer ) PRIVILEGED_FUNCTION; +/*-----------------------------------------------------------*/ + + BaseType_t xTimerCreateTimerTask( void ) + { + BaseType_t xReturn = pdFAIL; + + /* This function is called when the scheduler is started if + * configUSE_TIMERS is set to 1. Check that the infrastructure used by the + * timer service task has been created/initialised. If timers have already + * been created then the initialisation will already have been performed. */ + prvCheckForValidListAndQueue(); + + if( xTimerQueue != NULL ) + { + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + StaticTask_t * pxTimerTaskTCBBuffer = NULL; + StackType_t * pxTimerTaskStackBuffer = NULL; + uint32_t ulTimerTaskStackSize; + + vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize ); + xTimerTaskHandle = xTaskCreateStatic( prvTimerTask, + configTIMER_SERVICE_TASK_NAME, + ulTimerTaskStackSize, + NULL, + ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, + pxTimerTaskStackBuffer, + pxTimerTaskTCBBuffer ); + + if( xTimerTaskHandle != NULL ) + { + xReturn = pdPASS; + } + } + #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ + { + xReturn = xTaskCreate( prvTimerTask, + configTIMER_SERVICE_TASK_NAME, + configTIMER_TASK_STACK_DEPTH, + NULL, + ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, + &xTimerTaskHandle ); + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + configASSERT( xReturn ); + return xReturn; + } +/*-----------------------------------------------------------*/ + + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + TimerHandle_t xTimerCreate( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const TickType_t xTimerPeriodInTicks, + const UBaseType_t uxAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction ) + { + Timer_t * pxNewTimer; + + pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */ + + if( pxNewTimer != NULL ) + { + /* Status is thus far zero as the timer is not created statically + * and has not been started. The auto-reload bit may get set in + * prvInitialiseNewTimer. */ + pxNewTimer->ucStatus = 0x00; + prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer ); + } + + return pxNewTimer; + } + + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + + TimerHandle_t xTimerCreateStatic( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const TickType_t xTimerPeriodInTicks, + const UBaseType_t uxAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction, + StaticTimer_t * pxTimerBuffer ) + { + Timer_t * pxNewTimer; + + #if ( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + * variable of type StaticTimer_t equals the size of the real timer + * structure. */ + volatile size_t xSize = sizeof( StaticTimer_t ); + configASSERT( xSize == sizeof( Timer_t ) ); + ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ + } + #endif /* configASSERT_DEFINED */ + + /* A pointer to a StaticTimer_t structure MUST be provided, use it. */ + configASSERT( pxTimerBuffer ); + pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 !e9087 StaticTimer_t is a pointer to a Timer_t, so guaranteed to be aligned and sized correctly (checked by an assert()), so this is safe. */ + + if( pxNewTimer != NULL ) + { + /* Timers can be created statically or dynamically so note this + * timer was created statically in case it is later deleted. The + * auto-reload bit may get set in prvInitialiseNewTimer(). */ + pxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED; + + prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer ); + } + + return pxNewTimer; + } + + #endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + + static void prvInitialiseNewTimer( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const TickType_t xTimerPeriodInTicks, + const UBaseType_t uxAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction, + Timer_t * pxNewTimer ) + { + /* 0 is not a valid value for xTimerPeriodInTicks. */ + configASSERT( ( xTimerPeriodInTicks > 0 ) ); + + /* Ensure the infrastructure used by the timer service task has been + * created/initialised. */ + prvCheckForValidListAndQueue(); + + /* Initialise the timer structure members using the function + * parameters. */ + pxNewTimer->pcTimerName = pcTimerName; + pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks; + pxNewTimer->pvTimerID = pvTimerID; + pxNewTimer->pxCallbackFunction = pxCallbackFunction; + vListInitialiseItem( &( pxNewTimer->xTimerListItem ) ); + + if( uxAutoReload != pdFALSE ) + { + pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD; + } + + traceTIMER_CREATE( pxNewTimer ); + } +/*-----------------------------------------------------------*/ + + BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, + const BaseType_t xCommandID, + const TickType_t xOptionalValue, + BaseType_t * const pxHigherPriorityTaskWoken, + const TickType_t xTicksToWait ) + { + BaseType_t xReturn = pdFAIL; + DaemonTaskMessage_t xMessage; + + configASSERT( xTimer ); + + /* Send a message to the timer service task to perform a particular action + * on a particular timer definition. */ + if( xTimerQueue != NULL ) + { + /* Send a command to the timer service task to start the xTimer timer. */ + xMessage.xMessageID = xCommandID; + xMessage.u.xTimerParameters.xMessageValue = xOptionalValue; + xMessage.u.xTimerParameters.pxTimer = xTimer; + + if( xCommandID < tmrFIRST_FROM_ISR_COMMAND ) + { + if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING ) + { + xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait ); + } + else + { + xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY ); + } + } + else + { + xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken ); + } + + traceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) + { + /* If xTimerGetTimerDaemonTaskHandle() is called before the scheduler has been + * started, then xTimerTaskHandle will be NULL. */ + configASSERT( ( xTimerTaskHandle != NULL ) ); + return xTimerTaskHandle; + } +/*-----------------------------------------------------------*/ + + TickType_t xTimerGetPeriod( TimerHandle_t xTimer ) + { + Timer_t * pxTimer = xTimer; + + configASSERT( xTimer ); + return pxTimer->xTimerPeriodInTicks; + } +/*-----------------------------------------------------------*/ + + void vTimerSetReloadMode( TimerHandle_t xTimer, + const UBaseType_t uxAutoReload ) + { + Timer_t * pxTimer = xTimer; + + configASSERT( xTimer ); + taskENTER_CRITICAL(); + { + if( uxAutoReload != pdFALSE ) + { + pxTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD; + } + else + { + pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_AUTORELOAD ); + } + } + taskEXIT_CRITICAL(); + } +/*-----------------------------------------------------------*/ + + UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer ) + { + Timer_t * pxTimer = xTimer; + UBaseType_t uxReturn; + + configASSERT( xTimer ); + taskENTER_CRITICAL(); + { + if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) == 0 ) + { + /* Not an auto-reload timer. */ + uxReturn = ( UBaseType_t ) pdFALSE; + } + else + { + /* Is an auto-reload timer. */ + uxReturn = ( UBaseType_t ) pdTRUE; + } + } + taskEXIT_CRITICAL(); + + return uxReturn; + } +/*-----------------------------------------------------------*/ + + TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ) + { + Timer_t * pxTimer = xTimer; + TickType_t xReturn; + + configASSERT( xTimer ); + xReturn = listGET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ) ); + return xReturn; + } +/*-----------------------------------------------------------*/ + + const char * pcTimerGetName( TimerHandle_t xTimer ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + { + Timer_t * pxTimer = xTimer; + + configASSERT( xTimer ); + return pxTimer->pcTimerName; + } +/*-----------------------------------------------------------*/ + + static void prvReloadTimer( Timer_t * const pxTimer, + TickType_t xExpiredTime, + const TickType_t xTimeNow ) + { + /* Insert the timer into the appropriate list for the next expiry time. + * If the next expiry time has already passed, advance the expiry time, + * call the callback function, and try again. */ + while( prvInsertTimerInActiveList( pxTimer, ( xExpiredTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xExpiredTime ) != pdFALSE ) + { + /* Advance the expiry time. */ + xExpiredTime += pxTimer->xTimerPeriodInTicks; + + /* Call the timer callback. */ + traceTIMER_EXPIRED( pxTimer ); + pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); + } + } +/*-----------------------------------------------------------*/ + + static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, + const TickType_t xTimeNow ) + { + Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + + /* Remove the timer from the list of active timers. A check has already + * been performed to ensure the list is not empty. */ + + ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); + + /* If the timer is an auto-reload timer then calculate the next + * expiry time and re-insert the timer in the list of active timers. */ + if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) + { + prvReloadTimer( pxTimer, xNextExpireTime, xTimeNow ); + } + else + { + pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE ); + } + + /* Call the timer callback. */ + traceTIMER_EXPIRED( pxTimer ); + pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); + } +/*-----------------------------------------------------------*/ + + static portTASK_FUNCTION( prvTimerTask, pvParameters ) + { + TickType_t xNextExpireTime; + BaseType_t xListWasEmpty; + + /* Just to avoid compiler warnings. */ + ( void ) pvParameters; + + #if ( configUSE_DAEMON_TASK_STARTUP_HOOK == 1 ) + { + extern void vApplicationDaemonTaskStartupHook( void ); + + /* Allow the application writer to execute some code in the context of + * this task at the point the task starts executing. This is useful if the + * application includes initialisation code that would benefit from + * executing after the scheduler has been started. */ + vApplicationDaemonTaskStartupHook(); + } + #endif /* configUSE_DAEMON_TASK_STARTUP_HOOK */ + + for( ; ; ) + { + /* Query the timers list to see if it contains any timers, and if so, + * obtain the time at which the next timer will expire. */ + xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); + + /* If a timer has expired, process it. Otherwise, block this task + * until either a timer does expire, or a command is received. */ + prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty ); + + /* Empty the command queue. */ + prvProcessReceivedCommands(); + } + } +/*-----------------------------------------------------------*/ + + static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, + BaseType_t xListWasEmpty ) + { + TickType_t xTimeNow; + BaseType_t xTimerListsWereSwitched; + + vTaskSuspendAll(); + { + /* Obtain the time now to make an assessment as to whether the timer + * has expired or not. If obtaining the time causes the lists to switch + * then don't process this timer as any timers that remained in the list + * when the lists were switched will have been processed within the + * prvSampleTimeNow() function. */ + xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); + + if( xTimerListsWereSwitched == pdFALSE ) + { + /* The tick count has not overflowed, has the timer expired? */ + if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) ) + { + ( void ) xTaskResumeAll(); + prvProcessExpiredTimer( xNextExpireTime, xTimeNow ); + } + else + { + /* The tick count has not overflowed, and the next expire + * time has not been reached yet. This task should therefore + * block to wait for the next expire time or a command to be + * received - whichever comes first. The following line cannot + * be reached unless xNextExpireTime > xTimeNow, except in the + * case when the current timer list is empty. */ + if( xListWasEmpty != pdFALSE ) + { + /* The current timer list is empty - is the overflow list + * also empty? */ + xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList ); + } + + vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty ); + + if( xTaskResumeAll() == pdFALSE ) + { + /* Yield to wait for either a command to arrive, or the + * block time to expire. If a command arrived between the + * critical section being exited and this yield then the yield + * will not cause the task to block. */ + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + else + { + ( void ) xTaskResumeAll(); + } + } + } +/*-----------------------------------------------------------*/ + + static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) + { + TickType_t xNextExpireTime; + + /* Timers are listed in expiry time order, with the head of the list + * referencing the task that will expire first. Obtain the time at which + * the timer with the nearest expiry time will expire. If there are no + * active timers then just set the next expire time to 0. That will cause + * this task to unblock when the tick count overflows, at which point the + * timer lists will be switched and the next expiry time can be + * re-assessed. */ + *pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList ); + + if( *pxListWasEmpty == pdFALSE ) + { + xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); + } + else + { + /* Ensure the task unblocks when the tick count rolls over. */ + xNextExpireTime = ( TickType_t ) 0U; + } + + return xNextExpireTime; + } +/*-----------------------------------------------------------*/ + + static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) + { + TickType_t xTimeNow; + PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */ + + xTimeNow = xTaskGetTickCount(); + + if( xTimeNow < xLastTime ) + { + prvSwitchTimerLists(); + *pxTimerListsWereSwitched = pdTRUE; + } + else + { + *pxTimerListsWereSwitched = pdFALSE; + } + + xLastTime = xTimeNow; + + return xTimeNow; + } +/*-----------------------------------------------------------*/ + + static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, + const TickType_t xNextExpiryTime, + const TickType_t xTimeNow, + const TickType_t xCommandTime ) + { + BaseType_t xProcessTimerNow = pdFALSE; + + listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime ); + listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); + + if( xNextExpiryTime <= xTimeNow ) + { + /* Has the expiry time elapsed between the command to start/reset a + * timer was issued, and the time the command was processed? */ + if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + { + /* The time between a command being issued and the command being + * processed actually exceeds the timers period. */ + xProcessTimerNow = pdTRUE; + } + else + { + vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) ); + } + } + else + { + if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) ) + { + /* If, since the command was issued, the tick count has overflowed + * but the expiry time has not, then the timer must have already passed + * its expiry time and should be processed immediately. */ + xProcessTimerNow = pdTRUE; + } + else + { + vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); + } + } + + return xProcessTimerNow; + } +/*-----------------------------------------------------------*/ + + static void prvProcessReceivedCommands( void ) + { + DaemonTaskMessage_t xMessage; + Timer_t * pxTimer; + BaseType_t xTimerListsWereSwitched; + TickType_t xTimeNow; + + while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ + { + #if ( INCLUDE_xTimerPendFunctionCall == 1 ) + { + /* Negative commands are pended function calls rather than timer + * commands. */ + if( xMessage.xMessageID < ( BaseType_t ) 0 ) + { + const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters ); + + /* The timer uses the xCallbackParameters member to request a + * callback be executed. Check the callback is not NULL. */ + configASSERT( pxCallback ); + + /* Call the function. */ + pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* INCLUDE_xTimerPendFunctionCall */ + + /* Commands that are positive are timer commands rather than pended + * function calls. */ + if( xMessage.xMessageID >= ( BaseType_t ) 0 ) + { + /* The messages uses the xTimerParameters member to work on a + * software timer. */ + pxTimer = xMessage.u.xTimerParameters.pxTimer; + + if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */ + { + /* The timer is in a list, remove it. */ + ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.u.xTimerParameters.xMessageValue ); + + /* In this case the xTimerListsWereSwitched parameter is not used, but + * it must be present in the function call. prvSampleTimeNow() must be + * called after the message is received from xTimerQueue so there is no + * possibility of a higher priority task adding a message to the message + * queue with a time that is ahead of the timer daemon task (because it + * pre-empted the timer daemon task after the xTimeNow value was set). */ + xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); + + switch( xMessage.xMessageID ) + { + case tmrCOMMAND_START: + case tmrCOMMAND_START_FROM_ISR: + case tmrCOMMAND_RESET: + case tmrCOMMAND_RESET_FROM_ISR: + /* Start or restart a timer. */ + pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; + + if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE ) + { + /* The timer expired before it was added to the active + * timer list. Process it now. */ + if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) + { + prvReloadTimer( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow ); + } + else + { + pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE ); + } + + /* Call the timer callback. */ + traceTIMER_EXPIRED( pxTimer ); + pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + break; + + case tmrCOMMAND_STOP: + case tmrCOMMAND_STOP_FROM_ISR: + /* The timer has already been removed from the active list. */ + pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE ); + break; + + case tmrCOMMAND_CHANGE_PERIOD: + case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR: + pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; + pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue; + configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) ); + + /* The new period does not really have a reference, and can + * be longer or shorter than the old one. The command time is + * therefore set to the current time, and as the period cannot + * be zero the next expiry time can only be in the future, + * meaning (unlike for the xTimerStart() case above) there is + * no fail case that needs to be handled here. */ + ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow ); + break; + + case tmrCOMMAND_DELETE: + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + /* The timer has already been removed from the active list, + * just free up the memory if the memory was dynamically + * allocated. */ + if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 ) + { + vPortFree( pxTimer ); + } + else + { + pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE ); + } + } + #else /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */ + { + /* If dynamic allocation is not enabled, the memory + * could not have been dynamically allocated. So there is + * no need to free the memory - just mark the timer as + * "not active". */ + pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE ); + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + break; + + default: + /* Don't expect to get here. */ + break; + } + } + } + } +/*-----------------------------------------------------------*/ + + static void prvSwitchTimerLists( void ) + { + TickType_t xNextExpireTime; + List_t * pxTemp; + + /* The tick count has overflowed. The timer lists must be switched. + * If there are any timers still referenced from the current timer list + * then they must have expired and should be processed before the lists + * are switched. */ + while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) + { + xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); + + /* Process the expired timer. For auto-reload timers, be careful to + * process only expirations that occur on the current list. Further + * expirations must wait until after the lists are switched. */ + prvProcessExpiredTimer( xNextExpireTime, tmrMAX_TIME_BEFORE_OVERFLOW ); + } + + pxTemp = pxCurrentTimerList; + pxCurrentTimerList = pxOverflowTimerList; + pxOverflowTimerList = pxTemp; + } +/*-----------------------------------------------------------*/ + + static void prvCheckForValidListAndQueue( void ) + { + /* Check that the list from which active timers are referenced, and the + * queue used to communicate with the timer service, have been + * initialised. */ + taskENTER_CRITICAL(); + { + if( xTimerQueue == NULL ) + { + vListInitialise( &xActiveTimerList1 ); + vListInitialise( &xActiveTimerList2 ); + pxCurrentTimerList = &xActiveTimerList1; + pxOverflowTimerList = &xActiveTimerList2; + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + /* The timer queue is allocated statically in case + * configSUPPORT_DYNAMIC_ALLOCATION is 0. */ + PRIVILEGED_DATA static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ + PRIVILEGED_DATA static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ + + xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue ); + } + #else + { + xTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, sizeof( DaemonTaskMessage_t ) ); + } + #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + { + if( xTimerQueue != NULL ) + { + vQueueAddToRegistry( xTimerQueue, "TmrQ" ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configQUEUE_REGISTRY_SIZE */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + } +/*-----------------------------------------------------------*/ + + BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) + { + BaseType_t xReturn; + Timer_t * pxTimer = xTimer; + + configASSERT( xTimer ); + + /* Is the timer in the list of active timers? */ + taskENTER_CRITICAL(); + { + if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + } + taskEXIT_CRITICAL(); + + return xReturn; + } /*lint !e818 Can't be pointer to const due to the typedef. */ +/*-----------------------------------------------------------*/ + + void * pvTimerGetTimerID( const TimerHandle_t xTimer ) + { + Timer_t * const pxTimer = xTimer; + void * pvReturn; + + configASSERT( xTimer ); + + taskENTER_CRITICAL(); + { + pvReturn = pxTimer->pvTimerID; + } + taskEXIT_CRITICAL(); + + return pvReturn; + } +/*-----------------------------------------------------------*/ + + void vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) + { + Timer_t * const pxTimer = xTimer; + + configASSERT( xTimer ); + + taskENTER_CRITICAL(); + { + pxTimer->pvTimerID = pvNewID; + } + taskEXIT_CRITICAL(); + } +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTimerPendFunctionCall == 1 ) + + BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, + void * pvParameter1, + uint32_t ulParameter2, + BaseType_t * pxHigherPriorityTaskWoken ) + { + DaemonTaskMessage_t xMessage; + BaseType_t xReturn; + + /* Complete the message with the function parameters and post it to the + * daemon task. */ + xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR; + xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend; + xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1; + xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2; + + xReturn = xQueueSendFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken ); + + tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, xReturn ); + + return xReturn; + } + + #endif /* INCLUDE_xTimerPendFunctionCall */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTimerPendFunctionCall == 1 ) + + BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, + void * pvParameter1, + uint32_t ulParameter2, + TickType_t xTicksToWait ) + { + DaemonTaskMessage_t xMessage; + BaseType_t xReturn; + + /* This function can only be called after a timer has been created or + * after the scheduler has been started because, until then, the timer + * queue does not exist. */ + configASSERT( xTimerQueue ); + + /* Complete the message with the function parameters and post it to the + * daemon task. */ + xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK; + xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend; + xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1; + xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2; + + xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait ); + + tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, xReturn ); + + return xReturn; + } + + #endif /* INCLUDE_xTimerPendFunctionCall */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer ) + { + return ( ( Timer_t * ) xTimer )->uxTimerNumber; + } + + #endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + void vTimerSetTimerNumber( TimerHandle_t xTimer, + UBaseType_t uxTimerNumber ) + { + ( ( Timer_t * ) xTimer )->uxTimerNumber = uxTimerNumber; + } + + #endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +/* This entire source file will be skipped if the application is not configured + * to include software timer functionality. If you want to include software timer + * functionality then ensure configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */ +#endif /* configUSE_TIMERS == 1 */ diff --git a/hw-libs/misc/new.cpp b/hw-libs/misc/new.cpp new file mode 100644 index 000000000..7411f0322 --- /dev/null +++ b/hw-libs/misc/new.cpp @@ -0,0 +1,53 @@ +#include +#include +#include + +extern "C" void * pvPortMalloc(size_t xWantedSize); +extern "C" void vPortFree(void * pv); + +void * operator new(size_t size) +{ + void* ptr = pvPortMalloc(size); + while (ptr == 0) {} + return ptr; +} + +void operator delete(void *p) +{ + vPortFree(p); +} + +void * operator new[](size_t size) +{ + void* ptr = pvPortMalloc(size); + while (ptr == 0) {} + return ptr; +} + +void operator delete[](void *p) +{ + vPortFree(p); +} + + +// These override the standard libc-nano malloc & free + +void *malloc( size_t size ) +{ + return pvPortMalloc( size ); +} + +void free( void *ptr ) +{ + vPortFree( ptr ); +} + +void *realloc(void *ptr, size_t size) +{ // Not available + return nullptr; +} + +void *calloc(size_t nitems, size_t size) +{ // Not available + return nullptr; +} diff --git a/hw-libs/misc/rtos.c b/hw-libs/misc/rtos.c index cca09da06..02a8f5772 100644 --- a/hw-libs/misc/rtos.c +++ b/hw-libs/misc/rtos.c @@ -162,10 +162,10 @@ void vApplicationTickHook(void) static void setGpbrWithTaskInfo(void) { uint32_t task; - if((uint32_t)xTaskGetCurrentTaskHandle() == (uint32_t)g_rtos.task[TASK_SAMPLE].handle){ task = TASK_SAMPLE; } - if((uint32_t)xTaskGetCurrentTaskHandle() == (uint32_t)g_rtos.task[TASK_NAV].handle){ task = TASK_NAV; } - if((uint32_t)xTaskGetCurrentTaskHandle() == (uint32_t)g_rtos.task[TASK_COMMUNICATIONS].handle){ task = TASK_COMMUNICATIONS; } - if((uint32_t)xTaskGetCurrentTaskHandle() == (uint32_t)g_rtos.task[TASK_MAINTENANCE].handle){ task = TASK_MAINTENANCE; } + if((uint32_t)xTaskGetCurrentTaskHandle() == (uint32_t)g_rtos.task[IMX_TASK_SAMPLE].handle){ task = IMX_TASK_SAMPLE; } + if((uint32_t)xTaskGetCurrentTaskHandle() == (uint32_t)g_rtos.task[IMX_TASK_NAV].handle){ task = IMX_TASK_NAV; } + if((uint32_t)xTaskGetCurrentTaskHandle() == (uint32_t)g_rtos.task[IMX_TASK_COMMUNICATIONS].handle){ task = IMX_TASK_COMMUNICATIONS; } + if((uint32_t)xTaskGetCurrentTaskHandle() == (uint32_t)g_rtos.task[IMX_TASK_MAINTENANCE].handle){ task = IMX_TASK_MAINTENANCE; } #ifndef IMX_5 GPBR->SYS_GPBR[GPBR_IDX_G1_TASK] = task; diff --git a/hw-libs/misc/rtos.h b/hw-libs/misc/rtos.h new file mode 100644 index 000000000..67cfd7ab7 --- /dev/null +++ b/hw-libs/misc/rtos.h @@ -0,0 +1,74 @@ +/* +MIT LICENSE + +Copyright 2014-2019 Inertial Sense, Inc. - http://inertialsense.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions : + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +#ifndef RTOS_H_ +#define RTOS_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#include "../../src/ISConstants.h" +#include "FreeRTOS.h" +#include "task.h" +#include "d_time.h" + +#if defined(PLATFORM_IS_EVB_2) && PLATFORM_IS_EVB_2 +#define RTOS_NUM_TASKS (EVB_RTOS_NUM_TASKS) +#else +#define RTOS_NUM_TASKS (IMX_RTOS_NUM_TASKS) +#endif + +#if defined(DBGPIO_START) && defined(DBGPIO_END) +#define BEGIN_CRITICAL_SECTION {vTaskSuspendAll(); taskENTER_CRITICAL(); DBGPIO_START(DBG_CRITICAL_SECTION_PIN);} +#define END_CRITICAL_SECTION {DBGPIO_END(DBG_CRITICAL_SECTION_PIN); taskEXIT_CRITICAL(); xTaskResumeAll();} +#else +#define BEGIN_CRITICAL_SECTION {vTaskSuspendAll(); taskENTER_CRITICAL();} +#define END_CRITICAL_SECTION {taskEXIT_CRITICAL(); xTaskResumeAll();} +#endif + +#define GPBR_IDX_STATUS 0 +#define GPBR_IDX_G1_TASK 1 +#define GPBR_IDX_G2_FILE_NUM 2 +#define GPBR_IDX_G3_LINE_NUM 3 +#define GPBR_IDX_G4_FLASH_MIG 4 +#define GPBR_IDX_G5_LR 5 +#define GPBR_IDX_PC 6 +#define GPBR_IDX_PSR 7 + +int createTask( + int index, + pdTASK_CODE pxTaskCode, + const char * const pcName, + unsigned short usStackDepth, + void *pvParameters, + unsigned portBASE_TYPE uxPriority, + portTickType xTimeIncrement, + uint32_t overrunMs); + +// Monitor state of RTOS (i.e. stack high water mark, unused words). +void rtos_monitor(int numRtosTasks); +void rtosResetStats(void); +void rtosResetTaskCounters(void); + +void vApplicationIdleHook(void); +void vApplicationTickHook(void); + +void vApplicationMallocFailedHook(uint32_t size, uint32_t remaining, uint32_t prevLR); +void vApplicationDaemonTaskStartupHook(void); + +extern uint32_t g_faultLineNumber; +extern uint32_t g_faultFileNumber; + +#ifdef __cplusplus +} +#endif +#endif // RTOS_H_ diff --git a/hw-libs/printf/LICENSE b/hw-libs/printf/LICENSE new file mode 100644 index 000000000..8f7ebd0b9 --- /dev/null +++ b/hw-libs/printf/LICENSE @@ -0,0 +1,22 @@ +The MIT License (MIT) + +Copyright (c) 2014 Marco Paland + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. + diff --git a/hw-libs/printf/README.md b/hw-libs/printf/README.md new file mode 100644 index 000000000..017d640cc --- /dev/null +++ b/hw-libs/printf/README.md @@ -0,0 +1,206 @@ +# A printf / sprintf Implementation for Embedded Systems + +[![Build Status](https://travis-ci.org/mpaland/printf.svg?branch=master)](https://travis-ci.org/mpaland/printf) +[![codecov](https://codecov.io/gh/mpaland/printf/branch/master/graph/badge.svg)](https://codecov.io/gh/mpaland/printf) +[![Coverity Status](https://img.shields.io/coverity/scan/14180.svg)](https://scan.coverity.com/projects/mpaland-printf) +[![Github Issues](https://img.shields.io/github/issues/mpaland/printf.svg)](http://github.com/mpaland/printf/issues) +[![Github Releases](https://img.shields.io/github/release/mpaland/printf.svg)](https://github.com/mpaland/printf/releases) +[![GitHub license](https://img.shields.io/badge/license-MIT-blue.svg)](https://raw.githubusercontent.com/mpaland/avl_array/master/LICENSE) + +This is a tiny but **fully loaded** printf, sprintf and (v)snprintf implementation. +Primarily designed for usage in embedded systems, where printf is not available due to memory issues or in avoidance of linking against libc. +Using the standard libc printf may pull **a lot** of unwanted library stuff and can bloat code size about 20k or is not 100% thread safe. In this cases the following implementation can be used. +Absolutely **NO dependencies** are required, *printf.c* brings all necessary routines, even its own fast `ftoa` (floating point), `ntoa` (decimal) conversion. + +If memory footprint is really a critical issue, floating point, exponential and 'long long' support and can be turned off via the `PRINTF_DISABLE_SUPPORT_FLOAT`, `PRINTF_DISABLE_SUPPORT_EXPONENTIAL` and `PRINTF_DISABLE_SUPPORT_LONG_LONG` compiler switches. +When using printf (instead of sprintf/snprintf) you have to provide your own `_putchar()` low level function as console/serial output. + + +## Highlights and Design Goals + +There is a boatload of so called 'tiny' printf implementations around. So why this one? +I've tested many implementations, but most of them have very limited flag/specifier support, a lot of other dependencies or are just not standard compliant and failing most of the test suite. +Therefore I decided to write an own, final implementation which meets the following items: + + - Very small implementation (around 600 code lines) + - NO dependencies, no libs, just one module file + - Support of all important flags, width and precision sub-specifiers (see below) + - Support of decimal/floating number representation (with an own fast itoa/ftoa) + - Reentrant and thread-safe, malloc free, no static vars/buffers + - LINT and compiler L4 warning free, mature, coverity clean, automotive ready + - Extensive test suite (> 400 test cases) passing + - Simply the best *printf* around the net + - MIT license + + +## Usage + +Add/link *printf.c* to your project and include *printf.h*. That's it. +Implement your low level output function needed for `printf()`: +```C +void _putchar(char character) +{ + // send char to console etc. +} +``` + +Usage is 1:1 like the according stdio.h library version: +```C +int printf(const char* format, ...); +int sprintf(char* buffer, const char* format, ...); +int snprintf(char* buffer, size_t count, const char* format, ...); +int vsnprintf(char* buffer, size_t count, const char* format, va_list va); + +// use output function (instead of buffer) for streamlike interface +int fctprintf(void (*out)(char character, void* arg), void* arg, const char* format, ...); +``` + +**Due to general security reasons it is highly recommended to prefer and use `snprintf` (with the max buffer size as `count` parameter) instead of `sprintf`.** +`sprintf` has no buffer limitation, so when needed - use it really with care! + +### Streamlike Usage +Besides the regular standard `printf()` functions, this module also provides `fctprintf()`, which takes an output function as first parameter to build a streamlike output like `fprintf()`: +```C +// define the output function +void my_stream_output(char character, void* arg) +{ + // opt. evaluate the argument and send the char somewhere +} + +{ + // in your code + void* arg = (void*)100; // this argument is passed to the output function + fctprintf(&my_stream_output, arg, "This is a test: %X", 0xAA); + fctprintf(&my_stream_output, nullptr, "Send to null dev"); +} +``` + +## Format Specifiers + +A format specifier follows this prototype: `%[flags][width][.precision][length]type` +The following format specifiers are supported: + + +### Supported Types + +| Type | Output | +|--------|--------| +| d or i | Signed decimal integer | +| u | Unsigned decimal integer | +| b | Unsigned binary | +| o | Unsigned octal | +| x | Unsigned hexadecimal integer (lowercase) | +| X | Unsigned hexadecimal integer (uppercase) | +| f or F | Decimal floating point | +| e or E | Scientific-notation (exponential) floating point | +| g or G | Scientific or decimal floating point | +| c | Single character | +| s | String of characters | +| p | Pointer address | +| % | A % followed by another % character will write a single % | + + +### Supported Flags + +| Flags | Description | +|-------|-------------| +| - | Left-justify within the given field width; Right justification is the default. | +| + | Forces to precede the result with a plus or minus sign (+ or -) even for positive numbers.
By default, only negative numbers are preceded with a - sign. | +| (space) | If no sign is going to be written, a blank space is inserted before the value. | +| # | Used with o, b, x or X specifiers the value is preceded with 0, 0b, 0x or 0X respectively for values different than zero.
Used with f, F it forces the written output to contain a decimal point even if no more digits follow. By default, if no digits follow, no decimal point is written. | +| 0 | Left-pads the number with zeros (0) instead of spaces when padding is specified (see width sub-specifier). | + + +### Supported Width + +| Width | Description | +|----------|-------------| +| (number) | Minimum number of characters to be printed. If the value to be printed is shorter than this number, the result is padded with blank spaces. The value is not truncated even if the result is larger. | +| * | The width is not specified in the format string, but as an additional integer value argument preceding the argument that has to be formatted. | + + +### Supported Precision + +| Precision | Description | +|-----------|-------------| +| .number | For integer specifiers (d, i, o, u, x, X): precision specifies the minimum number of digits to be written. If the value to be written is shorter than this number, the result is padded with leading zeros. The value is not truncated even if the result is longer. A precision of 0 means that no character is written for the value 0.
For f and F specifiers: this is the number of digits to be printed after the decimal point. **By default, this is 6, maximum is 9**.
For s: this is the maximum number of characters to be printed. By default all characters are printed until the ending null character is encountered.
If the period is specified without an explicit value for precision, 0 is assumed. | +| .* | The precision is not specified in the format string, but as an additional integer value argument preceding the argument that has to be formatted. | + + +### Supported Length + +The length sub-specifier modifies the length of the data type. + +| Length | d i | u o x X | +|--------|------|---------| +| (none) | int | unsigned int | +| hh | char | unsigned char | +| h | short int | unsigned short int | +| l | long int | unsigned long int | +| ll | long long int | unsigned long long int (if PRINTF_SUPPORT_LONG_LONG is defined) | +| j | intmax_t | uintmax_t | +| z | size_t | size_t | +| t | ptrdiff_t | ptrdiff_t (if PRINTF_SUPPORT_PTRDIFF_T is defined) | + + +### Return Value + +Upon successful return, all functions return the number of characters written, _excluding_ the terminating null character used to end the string. +Functions `snprintf()` and `vsnprintf()` don't write more than `count` bytes, _including_ the terminating null byte ('\0'). +Anyway, if the output was truncated due to this limit, the return value is the number of characters that _could_ have been written. +Notice that a value equal or larger than `count` indicates a truncation. Only when the returned value is non-negative and less than `count`, +the string has been completely written. +If any error is encountered, `-1` is returned. + +If `buffer` is set to `NULL` (`nullptr`) nothing is written and just the formatted length is returned. +```C +int length = sprintf(NULL, "Hello, world"); // length is set to 12 +``` + + +## Compiler Switches/Defines + +| Name | Default value | Description | +|------|---------------|-------------| +| PRINTF_INCLUDE_CONFIG_H | undefined | Define this as compiler switch (e.g. `gcc -DPRINTF_INCLUDE_CONFIG_H`) to include a "printf_config.h" definition file | +| PRINTF_NTOA_BUFFER_SIZE | 32 | ntoa (integer) conversion buffer size. This must be big enough to hold one converted numeric number _including_ leading zeros, normally 32 is a sufficient value. Created on the stack | +| PRINTF_FTOA_BUFFER_SIZE | 32 | ftoa (float) conversion buffer size. This must be big enough to hold one converted float number _including_ leading zeros, normally 32 is a sufficient value. Created on the stack | +| PRINTF_DEFAULT_FLOAT_PRECISION | 6 | Define the default floating point precision | +| PRINTF_MAX_FLOAT | 1e9 | Define the largest suitable value to be printed with %f, before using exponential representation | +| PRINTF_DISABLE_SUPPORT_FLOAT | undefined | Define this to disable floating point (%f) support | +| PRINTF_DISABLE_SUPPORT_EXPONENTIAL | undefined | Define this to disable exponential floating point (%e) support | +| PRINTF_DISABLE_SUPPORT_LONG_LONG | undefined | Define this to disable long long (%ll) support | +| PRINTF_DISABLE_SUPPORT_PTRDIFF_T | undefined | Define this to disable ptrdiff_t (%t) support | + + +## Caveats +None anymore (finally). + + +## Test Suite +For testing just compile, build and run the test suite located in `test/test_suite.cpp`. This uses the [catch](https://github.com/catchorg/Catch2) framework for unit-tests, which is auto-adding main(). +Running with the `--wait-for-keypress exit` option waits for the enter key after test end. + + +## Projects Using printf +- [turnkeyboard](https://github.com/mpaland/turnkeyboard) uses printf as log and generic tty (formatting) output. +- printf is part of [embeddedartistry/libc](https://github.com/embeddedartistry/libc), a libc targeted for embedded systems usage. +- The [Hatchling Platform]( https://github.com/adrian3git/HatchlingPlatform) uses printf. + +(Just send me a mail/issue/PR to get *your* project listed here) + + +## Contributing + +0. Give this project a :star: +1. Create an issue and describe your idea +2. [Fork it](https://github.com/mpaland/printf/fork) +3. Create your feature branch (`git checkout -b my-new-feature`) +4. Commit your changes (`git commit -am 'Add some feature'`) +5. Publish the branch (`git push origin my-new-feature`) +6. Create a new pull request +7. Profit! :heavy_check_mark: + + +## License +printf is written under the [MIT license](http://www.opensource.org/licenses/MIT). diff --git a/hw-libs/printf/codecov.yml b/hw-libs/printf/codecov.yml new file mode 100644 index 000000000..cece49d24 --- /dev/null +++ b/hw-libs/printf/codecov.yml @@ -0,0 +1,2 @@ +ignore: + - "test" # ignore the test folder diff --git a/hw-libs/printf/printf.h b/hw-libs/printf/printf.h new file mode 100644 index 000000000..2a462f7c7 --- /dev/null +++ b/hw-libs/printf/printf.h @@ -0,0 +1,120 @@ +/////////////////////////////////////////////////////////////////////////////// +// \author (c) Marco Paland (info@paland.com) +// 2014-2019, PALANDesign Hannover, Germany +// +// \license The MIT License (MIT) +// +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +// THE SOFTWARE. +// +// \brief Tiny printf, sprintf and SNPRINTF implementation, optimized for speed on +// embedded systems with a very limited resources. +// Use this instead of bloated standard/newlib printf. +// These routines are thread safe and reentrant. +// +/////////////////////////////////////////////////////////////////////////////// + +#ifndef _PRINTF_H_ +#define _PRINTF_H_ + +#include +#include + + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * Output a character to a custom device like UART, used by the printf() function + * This function is declared here only. You have to write your custom implementation somewhere + * \param character Character to output + */ +void _putchar(char character); + + +/** + * Tiny printf implementation + * You have to implement _putchar if you use printf() + * To avoid conflicts with the regular printf() API it is overridden by macro defines + * and internal underscore-appended functions like printf_() are used + * \param format A string that specifies the format of the output + * \return The number of characters that are written into the array, not counting the terminating null character + */ +#ifdef printf +#undef printf +#endif +#define printf printf_ +int printf_(const char* format, ...); + + +/** + * Tiny sprintf implementation + * Due to security reasons (buffer overflow) YOU SHOULD CONSIDER USING (V)SNPRINTF INSTEAD! + * \param buffer A pointer to the buffer where to store the formatted string. MUST be big enough to store the output! + * \param format A string that specifies the format of the output + * \return The number of characters that are WRITTEN into the buffer, not counting the terminating null character + */ +#define sprintf sprintf_ +int sprintf_(char* buffer, const char* format, ...); + + +/** + * Tiny SNPRINTF/vsnprintf implementation + * \param buffer A pointer to the buffer where to store the formatted string + * \param count The maximum number of characters to store in the buffer, including a terminating null character + * \param format A string that specifies the format of the output + * \param va A value identifying a variable arguments list + * \return The number of characters that COULD have been written into the buffer, not counting the terminating + * null character. A value equal or larger than count indicates truncation. Only when the returned value + * is non-negative and less than count, the string has been completely written. + */ +#define snprintf snprintf_ +#define vsnprintf vsnprintf_ +int snprintf_(char* buffer, size_t count, const char* format, ...); +int vsnprintf_(char* buffer, size_t count, const char* format, va_list va); + + +/** + * Tiny vprintf implementation + * \param format A string that specifies the format of the output + * \param va A value identifying a variable arguments list + * \return The number of characters that are WRITTEN into the buffer, not counting the terminating null character + */ +#define vprintf vprintf_ +int vprintf_(const char* format, va_list va); + + +/** + * printf with output function + * You may use this as dynamic alternative to printf() with its fixed _putchar() output + * \param out An output function which takes one character and an argument pointer + * \param arg An argument pointer for user data passed to output function + * \param format A string that specifies the format of the output + * \return The number of characters that are sent to the output function, not counting the terminating null character + */ +int fctprintf(void (*out)(char character, void* arg), void* arg, const char* format, ...); + + +#ifdef __cplusplus +} +#endif + + +#endif // _PRINTF_H_ diff --git a/hw-libs/printf/test/catch.hpp b/hw-libs/printf/test/catch.hpp new file mode 100644 index 000000000..1850fff12 --- /dev/null +++ b/hw-libs/printf/test/catch.hpp @@ -0,0 +1,14934 @@ +/* + * Catch v2.7.0 + * Generated: 2019-03-07 21:34:30.252164 + * ---------------------------------------------------------- + * This file has been merged from multiple headers. Please don't edit it directly + * Copyright (c) 2019 Two Blue Cubes Ltd. All rights reserved. + * + * Distributed under the Boost Software License, Version 1.0. (See accompanying + * file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt) + */ +#ifndef TWOBLUECUBES_SINGLE_INCLUDE_CATCH_HPP_INCLUDED +#define TWOBLUECUBES_SINGLE_INCLUDE_CATCH_HPP_INCLUDED +// start catch.hpp + + +#define CATCH_VERSION_MAJOR 2 +#define CATCH_VERSION_MINOR 7 +#define CATCH_VERSION_PATCH 0 + +#ifdef __clang__ +# pragma clang system_header +#elif defined __GNUC__ +# pragma GCC system_header +#endif + +// start catch_suppress_warnings.h + +#ifdef __clang__ +# ifdef __ICC // icpc defines the __clang__ macro +# pragma warning(push) +# pragma warning(disable: 161 1682) +# else // __ICC +# pragma clang diagnostic push +# pragma clang diagnostic ignored "-Wpadded" +# pragma clang diagnostic ignored "-Wswitch-enum" +# pragma clang diagnostic ignored "-Wcovered-switch-default" +# endif +#elif defined __GNUC__ + // Because REQUIREs trigger GCC's -Wparentheses, and because still + // supported version of g++ have only buggy support for _Pragmas, + // Wparentheses have to be suppressed globally. +# pragma GCC diagnostic ignored "-Wparentheses" // See #674 for details + +# pragma GCC diagnostic push +# pragma GCC diagnostic ignored "-Wunused-variable" +# pragma GCC diagnostic ignored "-Wpadded" +#endif +// end catch_suppress_warnings.h +#if defined(CATCH_CONFIG_MAIN) || defined(CATCH_CONFIG_RUNNER) +# define CATCH_IMPL +# define CATCH_CONFIG_ALL_PARTS +#endif + +// In the impl file, we want to have access to all parts of the headers +// Can also be used to sanely support PCHs +#if defined(CATCH_CONFIG_ALL_PARTS) +# define CATCH_CONFIG_EXTERNAL_INTERFACES +# if defined(CATCH_CONFIG_DISABLE_MATCHERS) +# undef CATCH_CONFIG_DISABLE_MATCHERS +# endif +# if !defined(CATCH_CONFIG_ENABLE_CHRONO_STRINGMAKER) +# define CATCH_CONFIG_ENABLE_CHRONO_STRINGMAKER +# endif +#endif + +#if !defined(CATCH_CONFIG_IMPL_ONLY) +// start catch_platform.h + +#ifdef __APPLE__ +# include +# if TARGET_OS_OSX == 1 +# define CATCH_PLATFORM_MAC +# elif TARGET_OS_IPHONE == 1 +# define CATCH_PLATFORM_IPHONE +# endif + +#elif defined(linux) || defined(__linux) || defined(__linux__) +# define CATCH_PLATFORM_LINUX + +#elif defined(WIN32) || defined(__WIN32__) || defined(_WIN32) || defined(_MSC_VER) || defined(__MINGW32__) +# define CATCH_PLATFORM_WINDOWS +#endif + +// end catch_platform.h + +#ifdef CATCH_IMPL +# ifndef CLARA_CONFIG_MAIN +# define CLARA_CONFIG_MAIN_NOT_DEFINED +# define CLARA_CONFIG_MAIN +# endif +#endif + +// start catch_user_interfaces.h + +namespace Catch { + unsigned int rngSeed(); +} + +// end catch_user_interfaces.h +// start catch_tag_alias_autoregistrar.h + +// start catch_common.h + +// start catch_compiler_capabilities.h + +// Detect a number of compiler features - by compiler +// The following features are defined: +// +// CATCH_CONFIG_COUNTER : is the __COUNTER__ macro supported? +// CATCH_CONFIG_WINDOWS_SEH : is Windows SEH supported? +// CATCH_CONFIG_POSIX_SIGNALS : are POSIX signals supported? +// CATCH_CONFIG_DISABLE_EXCEPTIONS : Are exceptions enabled? +// **************** +// Note to maintainers: if new toggles are added please document them +// in configuration.md, too +// **************** + +// In general each macro has a _NO_ form +// (e.g. CATCH_CONFIG_NO_POSIX_SIGNALS) which disables the feature. +// Many features, at point of detection, define an _INTERNAL_ macro, so they +// can be combined, en-mass, with the _NO_ forms later. + +#ifdef __cplusplus + +# if (__cplusplus >= 201402L) || (defined(_MSVC_LANG) && _MSVC_LANG >= 201402L) +# define CATCH_CPP14_OR_GREATER +# endif + +# if (__cplusplus >= 201703L) || (defined(_MSVC_LANG) && _MSVC_LANG >= 201703L) +# define CATCH_CPP17_OR_GREATER +# endif + +#endif + +#if defined(CATCH_CPP17_OR_GREATER) +# define CATCH_INTERNAL_CONFIG_CPP17_UNCAUGHT_EXCEPTIONS +#endif + +#ifdef __clang__ + +# define CATCH_INTERNAL_SUPPRESS_GLOBALS_WARNINGS \ + _Pragma( "clang diagnostic push" ) \ + _Pragma( "clang diagnostic ignored \"-Wexit-time-destructors\"" ) \ + _Pragma( "clang diagnostic ignored \"-Wglobal-constructors\"") +# define CATCH_INTERNAL_UNSUPPRESS_GLOBALS_WARNINGS \ + _Pragma( "clang diagnostic pop" ) + +# define CATCH_INTERNAL_SUPPRESS_PARENTHESES_WARNINGS \ + _Pragma( "clang diagnostic push" ) \ + _Pragma( "clang diagnostic ignored \"-Wparentheses\"" ) +# define CATCH_INTERNAL_UNSUPPRESS_PARENTHESES_WARNINGS \ + _Pragma( "clang diagnostic pop" ) + +# define CATCH_INTERNAL_SUPPRESS_UNUSED_WARNINGS \ + _Pragma( "clang diagnostic push" ) \ + _Pragma( "clang diagnostic ignored \"-Wunused-variable\"" ) +# define CATCH_INTERNAL_UNSUPPRESS_UNUSED_WARNINGS \ + _Pragma( "clang diagnostic pop" ) + +#endif // __clang__ + +//////////////////////////////////////////////////////////////////////////////// +// Assume that non-Windows platforms support posix signals by default +#if !defined(CATCH_PLATFORM_WINDOWS) + #define CATCH_INTERNAL_CONFIG_POSIX_SIGNALS +#endif + +//////////////////////////////////////////////////////////////////////////////// +// We know some environments not to support full POSIX signals +#if defined(__CYGWIN__) || defined(__QNX__) || defined(__EMSCRIPTEN__) || defined(__DJGPP__) + #define CATCH_INTERNAL_CONFIG_NO_POSIX_SIGNALS +#endif + +#ifdef __OS400__ +# define CATCH_INTERNAL_CONFIG_NO_POSIX_SIGNALS +# define CATCH_CONFIG_COLOUR_NONE +#endif + +//////////////////////////////////////////////////////////////////////////////// +// Android somehow still does not support std::to_string +#if defined(__ANDROID__) +# define CATCH_INTERNAL_CONFIG_NO_CPP11_TO_STRING +#endif + +//////////////////////////////////////////////////////////////////////////////// +// Not all Windows environments support SEH properly +#if defined(__MINGW32__) +# define CATCH_INTERNAL_CONFIG_NO_WINDOWS_SEH +#endif + +//////////////////////////////////////////////////////////////////////////////// +// PS4 +#if defined(__ORBIS__) +# define CATCH_INTERNAL_CONFIG_NO_NEW_CAPTURE +#endif + +//////////////////////////////////////////////////////////////////////////////// +// Cygwin +#ifdef __CYGWIN__ + +// Required for some versions of Cygwin to declare gettimeofday +// see: http://stackoverflow.com/questions/36901803/gettimeofday-not-declared-in-this-scope-cygwin +# define _BSD_SOURCE +// some versions of cygwin (most) do not support std::to_string. Use the libstd check. +// https://gcc.gnu.org/onlinedocs/gcc-4.8.2/libstdc++/api/a01053_source.html line 2812-2813 +# if !((__cplusplus >= 201103L) && defined(_GLIBCXX_USE_C99) \ + && !defined(_GLIBCXX_HAVE_BROKEN_VSWPRINTF)) + +# define CATCH_INTERNAL_CONFIG_NO_CPP11_TO_STRING + +# endif +#endif // __CYGWIN__ + +//////////////////////////////////////////////////////////////////////////////// +// Visual C++ +#ifdef _MSC_VER + +# if _MSC_VER >= 1900 // Visual Studio 2015 or newer +# define CATCH_INTERNAL_CONFIG_CPP17_UNCAUGHT_EXCEPTIONS +# endif + +// Universal Windows platform does not support SEH +// Or console colours (or console at all...) +# if defined(WINAPI_FAMILY) && (WINAPI_FAMILY == WINAPI_FAMILY_APP) +# define CATCH_CONFIG_COLOUR_NONE +# else +# define CATCH_INTERNAL_CONFIG_WINDOWS_SEH +# endif + +// MSVC traditional preprocessor needs some workaround for __VA_ARGS__ +// _MSVC_TRADITIONAL == 0 means new conformant preprocessor +// _MSVC_TRADITIONAL == 1 means old traditional non-conformant preprocessor +# if !defined(_MSVC_TRADITIONAL) || (defined(_MSVC_TRADITIONAL) && _MSVC_TRADITIONAL) +# define CATCH_INTERNAL_CONFIG_TRADITIONAL_MSVC_PREPROCESSOR +# endif + +#endif // _MSC_VER + +//////////////////////////////////////////////////////////////////////////////// +// Check if we are compiled with -fno-exceptions or equivalent +#if defined(__EXCEPTIONS) || defined(__cpp_exceptions) || defined(_CPPUNWIND) +# define CATCH_INTERNAL_CONFIG_EXCEPTIONS_ENABLED +#endif + +//////////////////////////////////////////////////////////////////////////////// +// DJGPP +#ifdef __DJGPP__ +# define CATCH_INTERNAL_CONFIG_NO_WCHAR +#endif // __DJGPP__ + +//////////////////////////////////////////////////////////////////////////////// +// Embarcadero C++Build +#if defined(__BORLANDC__) + #define CATCH_INTERNAL_CONFIG_POLYFILL_ISNAN +#endif + +//////////////////////////////////////////////////////////////////////////////// + +// Use of __COUNTER__ is suppressed during code analysis in +// CLion/AppCode 2017.2.x and former, because __COUNTER__ is not properly +// handled by it. +// Otherwise all supported compilers support COUNTER macro, +// but user still might want to turn it off +#if ( !defined(__JETBRAINS_IDE__) || __JETBRAINS_IDE__ >= 20170300L ) + #define CATCH_INTERNAL_CONFIG_COUNTER +#endif + +//////////////////////////////////////////////////////////////////////////////// +// Check if string_view is available and usable +// The check is split apart to work around v140 (VS2015) preprocessor issue... +#if defined(__has_include) +#if __has_include() && defined(CATCH_CPP17_OR_GREATER) +# define CATCH_INTERNAL_CONFIG_CPP17_STRING_VIEW +#endif +#endif + +//////////////////////////////////////////////////////////////////////////////// +// Check if optional is available and usable +#if defined(__has_include) +# if __has_include() && defined(CATCH_CPP17_OR_GREATER) +# define CATCH_INTERNAL_CONFIG_CPP17_OPTIONAL +# endif // __has_include() && defined(CATCH_CPP17_OR_GREATER) +#endif // __has_include + +//////////////////////////////////////////////////////////////////////////////// +// Check if variant is available and usable +#if defined(__has_include) +# if __has_include() && defined(CATCH_CPP17_OR_GREATER) +# if defined(__clang__) && (__clang_major__ < 8) + // work around clang bug with libstdc++ https://bugs.llvm.org/show_bug.cgi?id=31852 + // fix should be in clang 8, workaround in libstdc++ 8.2 +# include +# if defined(__GLIBCXX__) && defined(_GLIBCXX_RELEASE) && (_GLIBCXX_RELEASE < 9) +# define CATCH_CONFIG_NO_CPP17_VARIANT +# else +# define CATCH_INTERNAL_CONFIG_CPP17_VARIANT +# endif // defined(__GLIBCXX__) && defined(_GLIBCXX_RELEASE) && (_GLIBCXX_RELEASE < 9) +# else +# define CATCH_INTERNAL_CONFIG_CPP17_VARIANT +# endif // defined(__clang__) && (__clang_major__ < 8) +# endif // __has_include() && defined(CATCH_CPP17_OR_GREATER) +#endif // __has_include + +#if defined(CATCH_INTERNAL_CONFIG_COUNTER) && !defined(CATCH_CONFIG_NO_COUNTER) && !defined(CATCH_CONFIG_COUNTER) +# define CATCH_CONFIG_COUNTER +#endif +#if defined(CATCH_INTERNAL_CONFIG_WINDOWS_SEH) && !defined(CATCH_CONFIG_NO_WINDOWS_SEH) && !defined(CATCH_CONFIG_WINDOWS_SEH) && !defined(CATCH_INTERNAL_CONFIG_NO_WINDOWS_SEH) +# define CATCH_CONFIG_WINDOWS_SEH +#endif +// This is set by default, because we assume that unix compilers are posix-signal-compatible by default. +#if defined(CATCH_INTERNAL_CONFIG_POSIX_SIGNALS) && !defined(CATCH_INTERNAL_CONFIG_NO_POSIX_SIGNALS) && !defined(CATCH_CONFIG_NO_POSIX_SIGNALS) && !defined(CATCH_CONFIG_POSIX_SIGNALS) +# define CATCH_CONFIG_POSIX_SIGNALS +#endif +// This is set by default, because we assume that compilers with no wchar_t support are just rare exceptions. +#if !defined(CATCH_INTERNAL_CONFIG_NO_WCHAR) && !defined(CATCH_CONFIG_NO_WCHAR) && !defined(CATCH_CONFIG_WCHAR) +# define CATCH_CONFIG_WCHAR +#endif + +#if !defined(CATCH_INTERNAL_CONFIG_NO_CPP11_TO_STRING) && !defined(CATCH_CONFIG_NO_CPP11_TO_STRING) && !defined(CATCH_CONFIG_CPP11_TO_STRING) +# define CATCH_CONFIG_CPP11_TO_STRING +#endif + +#if defined(CATCH_INTERNAL_CONFIG_CPP17_OPTIONAL) && !defined(CATCH_CONFIG_NO_CPP17_OPTIONAL) && !defined(CATCH_CONFIG_CPP17_OPTIONAL) +# define CATCH_CONFIG_CPP17_OPTIONAL +#endif + +#if defined(CATCH_INTERNAL_CONFIG_CPP17_UNCAUGHT_EXCEPTIONS) && !defined(CATCH_CONFIG_NO_CPP17_UNCAUGHT_EXCEPTIONS) && !defined(CATCH_CONFIG_CPP17_UNCAUGHT_EXCEPTIONS) +# define CATCH_CONFIG_CPP17_UNCAUGHT_EXCEPTIONS +#endif + +#if defined(CATCH_INTERNAL_CONFIG_CPP17_STRING_VIEW) && !defined(CATCH_CONFIG_NO_CPP17_STRING_VIEW) && !defined(CATCH_CONFIG_CPP17_STRING_VIEW) +# define CATCH_CONFIG_CPP17_STRING_VIEW +#endif + +#if defined(CATCH_INTERNAL_CONFIG_CPP17_VARIANT) && !defined(CATCH_CONFIG_NO_CPP17_VARIANT) && !defined(CATCH_CONFIG_CPP17_VARIANT) +# define CATCH_CONFIG_CPP17_VARIANT +#endif + +#if defined(CATCH_CONFIG_EXPERIMENTAL_REDIRECT) +# define CATCH_INTERNAL_CONFIG_NEW_CAPTURE +#endif + +#if defined(CATCH_INTERNAL_CONFIG_NEW_CAPTURE) && !defined(CATCH_INTERNAL_CONFIG_NO_NEW_CAPTURE) && !defined(CATCH_CONFIG_NO_NEW_CAPTURE) && !defined(CATCH_CONFIG_NEW_CAPTURE) +# define CATCH_CONFIG_NEW_CAPTURE +#endif + +#if !defined(CATCH_INTERNAL_CONFIG_EXCEPTIONS_ENABLED) && !defined(CATCH_CONFIG_DISABLE_EXCEPTIONS) +# define CATCH_CONFIG_DISABLE_EXCEPTIONS +#endif + +#if defined(CATCH_INTERNAL_CONFIG_POLYFILL_ISNAN) && !defined(CATCH_CONFIG_NO_POLYFILL_ISNAN) && !defined(CATCH_CONFIG_POLYFILL_ISNAN) +# define CATCH_CONFIG_POLYFILL_ISNAN +#endif + +#if !defined(CATCH_INTERNAL_SUPPRESS_PARENTHESES_WARNINGS) +# define CATCH_INTERNAL_SUPPRESS_PARENTHESES_WARNINGS +# define CATCH_INTERNAL_UNSUPPRESS_PARENTHESES_WARNINGS +#endif +#if !defined(CATCH_INTERNAL_SUPPRESS_GLOBALS_WARNINGS) +# define CATCH_INTERNAL_SUPPRESS_GLOBALS_WARNINGS +# define CATCH_INTERNAL_UNSUPPRESS_GLOBALS_WARNINGS +#endif +#if !defined(CATCH_INTERNAL_SUPPRESS_UNUSED_WARNINGS) +# define CATCH_INTERNAL_SUPPRESS_UNUSED_WARNINGS +# define CATCH_INTERNAL_UNSUPPRESS_UNUSED_WARNINGS +#endif + +#if defined(CATCH_CONFIG_DISABLE_EXCEPTIONS) +#define CATCH_TRY if ((true)) +#define CATCH_CATCH_ALL if ((false)) +#define CATCH_CATCH_ANON(type) if ((false)) +#else +#define CATCH_TRY try +#define CATCH_CATCH_ALL catch (...) +#define CATCH_CATCH_ANON(type) catch (type) +#endif + +#if defined(CATCH_INTERNAL_CONFIG_TRADITIONAL_MSVC_PREPROCESSOR) && !defined(CATCH_CONFIG_NO_TRADITIONAL_MSVC_PREPROCESSOR) && !defined(CATCH_CONFIG_TRADITIONAL_MSVC_PREPROCESSOR) +#define CATCH_CONFIG_TRADITIONAL_MSVC_PREPROCESSOR +#endif + +// end catch_compiler_capabilities.h +#define INTERNAL_CATCH_UNIQUE_NAME_LINE2( name, line ) name##line +#define INTERNAL_CATCH_UNIQUE_NAME_LINE( name, line ) INTERNAL_CATCH_UNIQUE_NAME_LINE2( name, line ) +#ifdef CATCH_CONFIG_COUNTER +# define INTERNAL_CATCH_UNIQUE_NAME( name ) INTERNAL_CATCH_UNIQUE_NAME_LINE( name, __COUNTER__ ) +#else +# define INTERNAL_CATCH_UNIQUE_NAME( name ) INTERNAL_CATCH_UNIQUE_NAME_LINE( name, __LINE__ ) +#endif + +#include +#include +#include + +// We need a dummy global operator<< so we can bring it into Catch namespace later +struct Catch_global_namespace_dummy {}; +std::ostream& operator<<(std::ostream&, Catch_global_namespace_dummy); + +namespace Catch { + + struct CaseSensitive { enum Choice { + Yes, + No + }; }; + + class NonCopyable { + NonCopyable( NonCopyable const& ) = delete; + NonCopyable( NonCopyable && ) = delete; + NonCopyable& operator = ( NonCopyable const& ) = delete; + NonCopyable& operator = ( NonCopyable && ) = delete; + + protected: + NonCopyable(); + virtual ~NonCopyable(); + }; + + struct SourceLineInfo { + + SourceLineInfo() = delete; + SourceLineInfo( char const* _file, std::size_t _line ) noexcept + : file( _file ), + line( _line ) + {} + + SourceLineInfo( SourceLineInfo const& other ) = default; + SourceLineInfo& operator = ( SourceLineInfo const& ) = default; + SourceLineInfo( SourceLineInfo&& ) noexcept = default; + SourceLineInfo& operator = ( SourceLineInfo&& ) noexcept = default; + + bool empty() const noexcept; + bool operator == ( SourceLineInfo const& other ) const noexcept; + bool operator < ( SourceLineInfo const& other ) const noexcept; + + char const* file; + std::size_t line; + }; + + std::ostream& operator << ( std::ostream& os, SourceLineInfo const& info ); + + // Bring in operator<< from global namespace into Catch namespace + // This is necessary because the overload of operator<< above makes + // lookup stop at namespace Catch + using ::operator<<; + + // Use this in variadic streaming macros to allow + // >> +StreamEndStop + // as well as + // >> stuff +StreamEndStop + struct StreamEndStop { + std::string operator+() const; + }; + template + T const& operator + ( T const& value, StreamEndStop ) { + return value; + } +} + +#define CATCH_INTERNAL_LINEINFO \ + ::Catch::SourceLineInfo( __FILE__, static_cast( __LINE__ ) ) + +// end catch_common.h +namespace Catch { + + struct RegistrarForTagAliases { + RegistrarForTagAliases( char const* alias, char const* tag, SourceLineInfo const& lineInfo ); + }; + +} // end namespace Catch + +#define CATCH_REGISTER_TAG_ALIAS( alias, spec ) \ + CATCH_INTERNAL_SUPPRESS_GLOBALS_WARNINGS \ + namespace{ Catch::RegistrarForTagAliases INTERNAL_CATCH_UNIQUE_NAME( AutoRegisterTagAlias )( alias, spec, CATCH_INTERNAL_LINEINFO ); } \ + CATCH_INTERNAL_UNSUPPRESS_GLOBALS_WARNINGS + +// end catch_tag_alias_autoregistrar.h +// start catch_test_registry.h + +// start catch_interfaces_testcase.h + +#include + +namespace Catch { + + class TestSpec; + + struct ITestInvoker { + virtual void invoke () const = 0; + virtual ~ITestInvoker(); + }; + + class TestCase; + struct IConfig; + + struct ITestCaseRegistry { + virtual ~ITestCaseRegistry(); + virtual std::vector const& getAllTests() const = 0; + virtual std::vector const& getAllTestsSorted( IConfig const& config ) const = 0; + }; + + bool matchTest( TestCase const& testCase, TestSpec const& testSpec, IConfig const& config ); + std::vector filterTests( std::vector const& testCases, TestSpec const& testSpec, IConfig const& config ); + std::vector const& getAllTestCasesSorted( IConfig const& config ); + +} + +// end catch_interfaces_testcase.h +// start catch_stringref.h + +#include +#include +#include + +namespace Catch { + + /// A non-owning string class (similar to the forthcoming std::string_view) + /// Note that, because a StringRef may be a substring of another string, + /// it may not be null terminated. c_str() must return a null terminated + /// string, however, and so the StringRef will internally take ownership + /// (taking a copy), if necessary. In theory this ownership is not externally + /// visible - but it does mean (substring) StringRefs should not be shared between + /// threads. + class StringRef { + public: + using size_type = std::size_t; + + private: + friend struct StringRefTestAccess; + + char const* m_start; + size_type m_size; + + char* m_data = nullptr; + + void takeOwnership(); + + static constexpr char const* const s_empty = ""; + + public: // construction/ assignment + StringRef() noexcept + : StringRef( s_empty, 0 ) + {} + + StringRef( StringRef const& other ) noexcept + : m_start( other.m_start ), + m_size( other.m_size ) + {} + + StringRef( StringRef&& other ) noexcept + : m_start( other.m_start ), + m_size( other.m_size ), + m_data( other.m_data ) + { + other.m_data = nullptr; + } + + StringRef( char const* rawChars ) noexcept; + + StringRef( char const* rawChars, size_type size ) noexcept + : m_start( rawChars ), + m_size( size ) + {} + + StringRef( std::string const& stdString ) noexcept + : m_start( stdString.c_str() ), + m_size( stdString.size() ) + {} + + ~StringRef() noexcept { + delete[] m_data; + } + + auto operator = ( StringRef const &other ) noexcept -> StringRef& { + delete[] m_data; + m_data = nullptr; + m_start = other.m_start; + m_size = other.m_size; + return *this; + } + + operator std::string() const; + + void swap( StringRef& other ) noexcept; + + public: // operators + auto operator == ( StringRef const& other ) const noexcept -> bool; + auto operator != ( StringRef const& other ) const noexcept -> bool; + + auto operator[] ( size_type index ) const noexcept -> char; + + public: // named queries + auto empty() const noexcept -> bool { + return m_size == 0; + } + auto size() const noexcept -> size_type { + return m_size; + } + + auto numberOfCharacters() const noexcept -> size_type; + auto c_str() const -> char const*; + + public: // substrings and searches + auto substr( size_type start, size_type size ) const noexcept -> StringRef; + + // Returns the current start pointer. + // Note that the pointer can change when if the StringRef is a substring + auto currentData() const noexcept -> char const*; + + private: // ownership queries - may not be consistent between calls + auto isOwned() const noexcept -> bool; + auto isSubstring() const noexcept -> bool; + }; + + auto operator + ( StringRef const& lhs, StringRef const& rhs ) -> std::string; + auto operator + ( StringRef const& lhs, char const* rhs ) -> std::string; + auto operator + ( char const* lhs, StringRef const& rhs ) -> std::string; + + auto operator += ( std::string& lhs, StringRef const& sr ) -> std::string&; + auto operator << ( std::ostream& os, StringRef const& sr ) -> std::ostream&; + + inline auto operator "" _sr( char const* rawChars, std::size_t size ) noexcept -> StringRef { + return StringRef( rawChars, size ); + } + +} // namespace Catch + +inline auto operator "" _catch_sr( char const* rawChars, std::size_t size ) noexcept -> Catch::StringRef { + return Catch::StringRef( rawChars, size ); +} + +// end catch_stringref.h +// start catch_type_traits.hpp + + +#include + +namespace Catch{ + +#ifdef CATCH_CPP17_OR_GREATER + template + inline constexpr auto is_unique = std::true_type{}; + + template + inline constexpr auto is_unique = std::bool_constant< + (!std::is_same_v && ...) && is_unique + >{}; +#else + +template +struct is_unique : std::true_type{}; + +template +struct is_unique : std::integral_constant +::value + && is_unique::value + && is_unique::value +>{}; + +#endif +} + +// end catch_type_traits.hpp +// start catch_preprocessor.hpp + + +#define CATCH_RECURSION_LEVEL0(...) __VA_ARGS__ +#define CATCH_RECURSION_LEVEL1(...) CATCH_RECURSION_LEVEL0(CATCH_RECURSION_LEVEL0(CATCH_RECURSION_LEVEL0(__VA_ARGS__))) +#define CATCH_RECURSION_LEVEL2(...) CATCH_RECURSION_LEVEL1(CATCH_RECURSION_LEVEL1(CATCH_RECURSION_LEVEL1(__VA_ARGS__))) +#define CATCH_RECURSION_LEVEL3(...) CATCH_RECURSION_LEVEL2(CATCH_RECURSION_LEVEL2(CATCH_RECURSION_LEVEL2(__VA_ARGS__))) +#define CATCH_RECURSION_LEVEL4(...) CATCH_RECURSION_LEVEL3(CATCH_RECURSION_LEVEL3(CATCH_RECURSION_LEVEL3(__VA_ARGS__))) +#define CATCH_RECURSION_LEVEL5(...) CATCH_RECURSION_LEVEL4(CATCH_RECURSION_LEVEL4(CATCH_RECURSION_LEVEL4(__VA_ARGS__))) + +#ifdef CATCH_CONFIG_TRADITIONAL_MSVC_PREPROCESSOR +#define INTERNAL_CATCH_EXPAND_VARGS(...) __VA_ARGS__ +// MSVC needs more evaluations +#define CATCH_RECURSION_LEVEL6(...) CATCH_RECURSION_LEVEL5(CATCH_RECURSION_LEVEL5(CATCH_RECURSION_LEVEL5(__VA_ARGS__))) +#define CATCH_RECURSE(...) CATCH_RECURSION_LEVEL6(CATCH_RECURSION_LEVEL6(__VA_ARGS__)) +#else +#define CATCH_RECURSE(...) CATCH_RECURSION_LEVEL5(__VA_ARGS__) +#endif + +#define CATCH_REC_END(...) +#define CATCH_REC_OUT + +#define CATCH_EMPTY() +#define CATCH_DEFER(id) id CATCH_EMPTY() + +#define CATCH_REC_GET_END2() 0, CATCH_REC_END +#define CATCH_REC_GET_END1(...) CATCH_REC_GET_END2 +#define CATCH_REC_GET_END(...) CATCH_REC_GET_END1 +#define CATCH_REC_NEXT0(test, next, ...) next CATCH_REC_OUT +#define CATCH_REC_NEXT1(test, next) CATCH_DEFER ( CATCH_REC_NEXT0 ) ( test, next, 0) +#define CATCH_REC_NEXT(test, next) CATCH_REC_NEXT1(CATCH_REC_GET_END test, next) + +#define CATCH_REC_LIST0(f, x, peek, ...) , f(x) CATCH_DEFER ( CATCH_REC_NEXT(peek, CATCH_REC_LIST1) ) ( f, peek, __VA_ARGS__ ) +#define CATCH_REC_LIST1(f, x, peek, ...) , f(x) CATCH_DEFER ( CATCH_REC_NEXT(peek, CATCH_REC_LIST0) ) ( f, peek, __VA_ARGS__ ) +#define CATCH_REC_LIST2(f, x, peek, ...) f(x) CATCH_DEFER ( CATCH_REC_NEXT(peek, CATCH_REC_LIST1) ) ( f, peek, __VA_ARGS__ ) + +#define CATCH_REC_LIST0_UD(f, userdata, x, peek, ...) , f(userdata, x) CATCH_DEFER ( CATCH_REC_NEXT(peek, CATCH_REC_LIST1_UD) ) ( f, userdata, peek, __VA_ARGS__ ) +#define CATCH_REC_LIST1_UD(f, userdata, x, peek, ...) , f(userdata, x) CATCH_DEFER ( CATCH_REC_NEXT(peek, CATCH_REC_LIST0_UD) ) ( f, userdata, peek, __VA_ARGS__ ) +#define CATCH_REC_LIST2_UD(f, userdata, x, peek, ...) f(userdata, x) CATCH_DEFER ( CATCH_REC_NEXT(peek, CATCH_REC_LIST1_UD) ) ( f, userdata, peek, __VA_ARGS__ ) + +// Applies the function macro `f` to each of the remaining parameters, inserts commas between the results, +// and passes userdata as the first parameter to each invocation, +// e.g. CATCH_REC_LIST_UD(f, x, a, b, c) evaluates to f(x, a), f(x, b), f(x, c) +#define CATCH_REC_LIST_UD(f, userdata, ...) CATCH_RECURSE(CATCH_REC_LIST2_UD(f, userdata, __VA_ARGS__, ()()(), ()()(), ()()(), 0)) + +#define CATCH_REC_LIST(f, ...) CATCH_RECURSE(CATCH_REC_LIST2(f, __VA_ARGS__, ()()(), ()()(), ()()(), 0)) + +#define INTERNAL_CATCH_EXPAND1(param) INTERNAL_CATCH_EXPAND2(param) +#define INTERNAL_CATCH_EXPAND2(...) INTERNAL_CATCH_NO## __VA_ARGS__ +#define INTERNAL_CATCH_DEF(...) INTERNAL_CATCH_DEF __VA_ARGS__ +#define INTERNAL_CATCH_NOINTERNAL_CATCH_DEF +#define INTERNAL_CATCH_STRINGIZE(...) INTERNAL_CATCH_STRINGIZE2(__VA_ARGS__) +#ifndef CATCH_CONFIG_TRADITIONAL_MSVC_PREPROCESSOR +#define INTERNAL_CATCH_STRINGIZE2(...) #__VA_ARGS__ +#define INTERNAL_CATCH_STRINGIZE_WITHOUT_PARENS(param) INTERNAL_CATCH_STRINGIZE(INTERNAL_CATCH_REMOVE_PARENS(param)) +#else +// MSVC is adding extra space and needs another indirection to expand INTERNAL_CATCH_NOINTERNAL_CATCH_DEF +#define INTERNAL_CATCH_STRINGIZE2(...) INTERNAL_CATCH_STRINGIZE3(__VA_ARGS__) +#define INTERNAL_CATCH_STRINGIZE3(...) #__VA_ARGS__ +#define INTERNAL_CATCH_STRINGIZE_WITHOUT_PARENS(param) (INTERNAL_CATCH_STRINGIZE(INTERNAL_CATCH_REMOVE_PARENS(param)) + 1) +#endif + +#define INTERNAL_CATCH_REMOVE_PARENS(...) INTERNAL_CATCH_EXPAND1(INTERNAL_CATCH_DEF __VA_ARGS__) + +#define INTERNAL_CATCH_TEMPLATE_UNIQUE_NAME2(Name, ...) INTERNAL_CATCH_TEMPLATE_UNIQUE_NAME3(Name, __VA_ARGS__) +#ifndef CATCH_CONFIG_TRADITIONAL_MSVC_PREPROCESSOR +#define INTERNAL_CATCH_TEMPLATE_UNIQUE_NAME3(Name,...) Name " - " #__VA_ARGS__ +#define INTERNAL_CATCH_TEMPLATE_UNIQUE_NAME(Name,...) INTERNAL_CATCH_TEMPLATE_UNIQUE_NAME2(Name, INTERNAL_CATCH_REMOVE_PARENS(__VA_ARGS__)) +#else +// MSVC is adding extra space and needs more calls to properly remove () +#define INTERNAL_CATCH_TEMPLATE_UNIQUE_NAME3(Name,...) Name " -" #__VA_ARGS__ +#define INTERNAL_CATCH_TEMPLATE_UNIQUE_NAME1(Name, ...) INTERNAL_CATCH_TEMPLATE_UNIQUE_NAME2(Name, __VA_ARGS__) +#define INTERNAL_CATCH_TEMPLATE_UNIQUE_NAME(Name, ...) INTERNAL_CATCH_TEMPLATE_UNIQUE_NAME1(Name, INTERNAL_CATCH_EXPAND_VARGS(INTERNAL_CATCH_REMOVE_PARENS(__VA_ARGS__))) +#endif + +#define INTERNAL_CATCH_MAKE_TYPE_LIST(types) Catch::TypeList + +#define INTERNAL_CATCH_MAKE_TYPE_LISTS_FROM_TYPES(types)\ + CATCH_REC_LIST(INTERNAL_CATCH_MAKE_TYPE_LIST,INTERNAL_CATCH_REMOVE_PARENS(types)) + +// end catch_preprocessor.hpp +// start catch_meta.hpp + + +#include + +namespace Catch { +template< typename... > +struct TypeList {}; + +template< typename... > +struct append; + +template< template class L1 + , typename...E1 + , template class L2 + , typename...E2 +> +struct append< L1, L2 > { + using type = L1; +}; + +template< template class L1 + , typename...E1 + , template class L2 + , typename...E2 + , typename...Rest +> +struct append< L1, L2, Rest...> { + using type = typename append< L1, Rest... >::type; +}; + +template< template class + , typename... +> +struct rewrap; + +template< template class Container + , template class List + , typename...elems +> +struct rewrap> { + using type = TypeList< Container< elems... > >; +}; + +template< template class Container + , template class List + , class...Elems + , typename...Elements> + struct rewrap, Elements...> { + using type = typename append>, typename rewrap::type>::type; +}; + +template< template class...Containers > +struct combine { + template< typename...Types > + struct with_types { + template< template class Final > + struct into { + using type = typename append, typename rewrap::type...>::type; + }; + }; +}; + +template +struct always_false : std::false_type {}; + +} // namespace Catch + +// end catch_meta.hpp +namespace Catch { + +template +class TestInvokerAsMethod : public ITestInvoker { + void (C::*m_testAsMethod)(); +public: + TestInvokerAsMethod( void (C::*testAsMethod)() ) noexcept : m_testAsMethod( testAsMethod ) {} + + void invoke() const override { + C obj; + (obj.*m_testAsMethod)(); + } +}; + +auto makeTestInvoker( void(*testAsFunction)() ) noexcept -> ITestInvoker*; + +template +auto makeTestInvoker( void (C::*testAsMethod)() ) noexcept -> ITestInvoker* { + return new(std::nothrow) TestInvokerAsMethod( testAsMethod ); +} + +struct NameAndTags { + NameAndTags( StringRef const& name_ = StringRef(), StringRef const& tags_ = StringRef() ) noexcept; + StringRef name; + StringRef tags; +}; + +struct AutoReg : NonCopyable { + AutoReg( ITestInvoker* invoker, SourceLineInfo const& lineInfo, StringRef const& classOrMethod, NameAndTags const& nameAndTags ) noexcept; + ~AutoReg(); +}; + +} // end namespace Catch + +#if defined(CATCH_CONFIG_DISABLE) + #define INTERNAL_CATCH_TESTCASE_NO_REGISTRATION( TestName, ... ) \ + static void TestName() + #define INTERNAL_CATCH_TESTCASE_METHOD_NO_REGISTRATION( TestName, ClassName, ... ) \ + namespace{ \ + struct TestName : INTERNAL_CATCH_REMOVE_PARENS(ClassName) { \ + void test(); \ + }; \ + } \ + void TestName::test() + #define INTERNAL_CATCH_TEMPLATE_TEST_CASE_NO_REGISTRATION( TestName, ... ) \ + template \ + static void TestName() + #define INTERNAL_CATCH_TEMPLATE_TEST_CASE_METHOD_NO_REGISTRATION( TestName, ClassName, ... ) \ + namespace{ \ + template \ + struct TestName : INTERNAL_CATCH_REMOVE_PARENS(ClassName ) { \ + void test(); \ + }; \ + } \ + template \ + void TestName::test() +#endif + + /////////////////////////////////////////////////////////////////////////////// + #define INTERNAL_CATCH_TESTCASE2( TestName, ... ) \ + static void TestName(); \ + CATCH_INTERNAL_SUPPRESS_GLOBALS_WARNINGS \ + namespace{ Catch::AutoReg INTERNAL_CATCH_UNIQUE_NAME( autoRegistrar )( Catch::makeTestInvoker( &TestName ), CATCH_INTERNAL_LINEINFO, Catch::StringRef(), Catch::NameAndTags{ __VA_ARGS__ } ); } /* NOLINT */ \ + CATCH_INTERNAL_UNSUPPRESS_GLOBALS_WARNINGS \ + static void TestName() + #define INTERNAL_CATCH_TESTCASE( ... ) \ + INTERNAL_CATCH_TESTCASE2( INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_S_T____ ), __VA_ARGS__ ) + + /////////////////////////////////////////////////////////////////////////////// + #define INTERNAL_CATCH_METHOD_AS_TEST_CASE( QualifiedMethod, ... ) \ + CATCH_INTERNAL_SUPPRESS_GLOBALS_WARNINGS \ + namespace{ Catch::AutoReg INTERNAL_CATCH_UNIQUE_NAME( autoRegistrar )( Catch::makeTestInvoker( &QualifiedMethod ), CATCH_INTERNAL_LINEINFO, "&" #QualifiedMethod, Catch::NameAndTags{ __VA_ARGS__ } ); } /* NOLINT */ \ + CATCH_INTERNAL_UNSUPPRESS_GLOBALS_WARNINGS + + /////////////////////////////////////////////////////////////////////////////// + #define INTERNAL_CATCH_TEST_CASE_METHOD2( TestName, ClassName, ... )\ + CATCH_INTERNAL_SUPPRESS_GLOBALS_WARNINGS \ + namespace{ \ + struct TestName : INTERNAL_CATCH_REMOVE_PARENS(ClassName) { \ + void test(); \ + }; \ + Catch::AutoReg INTERNAL_CATCH_UNIQUE_NAME( autoRegistrar ) ( Catch::makeTestInvoker( &TestName::test ), CATCH_INTERNAL_LINEINFO, #ClassName, Catch::NameAndTags{ __VA_ARGS__ } ); /* NOLINT */ \ + } \ + CATCH_INTERNAL_UNSUPPRESS_GLOBALS_WARNINGS \ + void TestName::test() + #define INTERNAL_CATCH_TEST_CASE_METHOD( ClassName, ... ) \ + INTERNAL_CATCH_TEST_CASE_METHOD2( INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_S_T____ ), ClassName, __VA_ARGS__ ) + + /////////////////////////////////////////////////////////////////////////////// + #define INTERNAL_CATCH_REGISTER_TESTCASE( Function, ... ) \ + CATCH_INTERNAL_SUPPRESS_GLOBALS_WARNINGS \ + Catch::AutoReg INTERNAL_CATCH_UNIQUE_NAME( autoRegistrar )( Catch::makeTestInvoker( Function ), CATCH_INTERNAL_LINEINFO, Catch::StringRef(), Catch::NameAndTags{ __VA_ARGS__ } ); /* NOLINT */ \ + CATCH_INTERNAL_UNSUPPRESS_GLOBALS_WARNINGS + + /////////////////////////////////////////////////////////////////////////////// + #define INTERNAL_CATCH_TEMPLATE_TEST_CASE_2(TestName, TestFunc, Name, Tags, ... )\ + CATCH_INTERNAL_SUPPRESS_GLOBALS_WARNINGS \ + template \ + static void TestFunc();\ + namespace {\ + template \ + struct TestName{\ + template \ + TestName(Ts...names){\ + CATCH_INTERNAL_CHECK_UNIQUE_TYPES(CATCH_REC_LIST(INTERNAL_CATCH_REMOVE_PARENS, __VA_ARGS__)) \ + using expander = int[];\ + (void)expander{(Catch::AutoReg( Catch::makeTestInvoker( &TestFunc ), CATCH_INTERNAL_LINEINFO, Catch::StringRef(), Catch::NameAndTags{ names, Tags } ), 0)... };/* NOLINT */ \ + }\ + };\ + INTERNAL_CATCH_TEMPLATE_REGISTRY_INITIATE(TestName, Name, __VA_ARGS__) \ + }\ + CATCH_INTERNAL_UNSUPPRESS_GLOBALS_WARNINGS \ + template \ + static void TestFunc() + +#if defined(CATCH_CPP17_OR_GREATER) +#define CATCH_INTERNAL_CHECK_UNIQUE_TYPES(...) static_assert(Catch::is_unique<__VA_ARGS__>,"Duplicate type detected in declaration of template test case"); +#else +#define CATCH_INTERNAL_CHECK_UNIQUE_TYPES(...) static_assert(Catch::is_unique<__VA_ARGS__>::value,"Duplicate type detected in declaration of template test case"); +#endif + +#ifndef CATCH_CONFIG_TRADITIONAL_MSVC_PREPROCESSOR + #define INTERNAL_CATCH_TEMPLATE_TEST_CASE(Name, Tags, ...) \ + INTERNAL_CATCH_TEMPLATE_TEST_CASE_2( INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____ ), INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____F_U_N_C____ ), Name, Tags, __VA_ARGS__ ) +#else + #define INTERNAL_CATCH_TEMPLATE_TEST_CASE(Name, Tags, ...) \ + INTERNAL_CATCH_EXPAND_VARGS( INTERNAL_CATCH_TEMPLATE_TEST_CASE_2( INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____ ), INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____F_U_N_C____ ), Name, Tags, __VA_ARGS__ ) ) +#endif + + #define INTERNAL_CATCH_TEMPLATE_REGISTRY_INITIATE(TestName, Name, ...)\ + static int INTERNAL_CATCH_UNIQUE_NAME( globalRegistrar ) = [](){\ + TestName(CATCH_REC_LIST_UD(INTERNAL_CATCH_TEMPLATE_UNIQUE_NAME,Name, __VA_ARGS__));\ + return 0;\ + }(); + + #define INTERNAL_CATCH_TEMPLATE_PRODUCT_TEST_CASE2(TestName, TestFuncName, Name, Tags, TmplTypes, TypesList) \ + CATCH_INTERNAL_SUPPRESS_GLOBALS_WARNINGS \ + template static void TestFuncName(); \ + namespace { \ + template \ + struct TestName { \ + TestName() { \ + CATCH_INTERNAL_CHECK_UNIQUE_TYPES(Types...) \ + int index = 0; \ + using expander = int[]; \ + constexpr char const* tmpl_types[] = {CATCH_REC_LIST(INTERNAL_CATCH_STRINGIZE_WITHOUT_PARENS, INTERNAL_CATCH_REMOVE_PARENS(TmplTypes))};\ + constexpr char const* types_list[] = {CATCH_REC_LIST(INTERNAL_CATCH_STRINGIZE_WITHOUT_PARENS, INTERNAL_CATCH_REMOVE_PARENS(TypesList))};\ + constexpr auto num_types = sizeof(types_list) / sizeof(types_list[0]);\ + (void)expander{(Catch::AutoReg( Catch::makeTestInvoker( &TestFuncName ), CATCH_INTERNAL_LINEINFO, Catch::StringRef(), Catch::NameAndTags{ Name " - " + std::string(tmpl_types[index / num_types]) + "<" + std::string(types_list[index % num_types]) + ">", Tags } ), index++, 0)... };/* NOLINT */\ + } \ + }; \ + static int INTERNAL_CATCH_UNIQUE_NAME( globalRegistrar ) = [](){ \ + using TestInit = Catch::combine \ + ::with_types::into::type; \ + TestInit(); \ + return 0; \ + }(); \ + } \ + CATCH_INTERNAL_UNSUPPRESS_GLOBALS_WARNINGS \ + template \ + static void TestFuncName() + +#ifndef CATCH_CONFIG_TRADITIONAL_MSVC_PREPROCESSOR + #define INTERNAL_CATCH_TEMPLATE_PRODUCT_TEST_CASE(Name, Tags, ...)\ + INTERNAL_CATCH_TEMPLATE_PRODUCT_TEST_CASE2(INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____ ), INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____F_U_N_C____ ),Name,Tags,__VA_ARGS__) +#else + #define INTERNAL_CATCH_TEMPLATE_PRODUCT_TEST_CASE(Name, Tags, ...)\ + INTERNAL_CATCH_EXPAND_VARGS( INTERNAL_CATCH_TEMPLATE_PRODUCT_TEST_CASE2( INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____ ), INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____F_U_N_C____ ), Name, Tags, __VA_ARGS__ ) ) +#endif + + #define INTERNAL_CATCH_TEMPLATE_TEST_CASE_METHOD_2( TestNameClass, TestName, ClassName, Name, Tags, ... ) \ + CATCH_INTERNAL_SUPPRESS_GLOBALS_WARNINGS \ + namespace{ \ + template \ + struct TestName : INTERNAL_CATCH_REMOVE_PARENS(ClassName ) { \ + void test();\ + };\ + template \ + struct TestNameClass{\ + template \ + TestNameClass(Ts...names){\ + CATCH_INTERNAL_CHECK_UNIQUE_TYPES(CATCH_REC_LIST(INTERNAL_CATCH_REMOVE_PARENS, __VA_ARGS__)) \ + using expander = int[];\ + (void)expander{(Catch::AutoReg( Catch::makeTestInvoker( &TestName::test ), CATCH_INTERNAL_LINEINFO, #ClassName, Catch::NameAndTags{ names, Tags } ), 0)... };/* NOLINT */ \ + }\ + };\ + INTERNAL_CATCH_TEMPLATE_REGISTRY_INITIATE(TestNameClass, Name, __VA_ARGS__)\ + }\ + CATCH_INTERNAL_UNSUPPRESS_GLOBALS_WARNINGS\ + template \ + void TestName::test() + +#ifndef CATCH_CONFIG_TRADITIONAL_MSVC_PREPROCESSOR + #define INTERNAL_CATCH_TEMPLATE_TEST_CASE_METHOD( ClassName, Name, Tags,... ) \ + INTERNAL_CATCH_TEMPLATE_TEST_CASE_METHOD_2( INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____C_L_A_S_S____ ), INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____ ) , ClassName, Name, Tags, __VA_ARGS__ ) +#else + #define INTERNAL_CATCH_TEMPLATE_TEST_CASE_METHOD( ClassName, Name, Tags,... ) \ + INTERNAL_CATCH_EXPAND_VARGS( INTERNAL_CATCH_TEMPLATE_TEST_CASE_METHOD_2( INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____C_L_A_S_S____ ), INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____ ) , ClassName, Name, Tags, __VA_ARGS__ ) ) +#endif + + #define INTERNAL_CATCH_TEMPLATE_PRODUCT_TEST_CASE_METHOD_2(TestNameClass, TestName, ClassName, Name, Tags, TmplTypes, TypesList)\ + CATCH_INTERNAL_SUPPRESS_GLOBALS_WARNINGS \ + template \ + struct TestName : INTERNAL_CATCH_REMOVE_PARENS(ClassName ) { \ + void test();\ + };\ + namespace {\ + template\ + struct TestNameClass{\ + TestNameClass(){\ + CATCH_INTERNAL_CHECK_UNIQUE_TYPES(Types...)\ + int index = 0;\ + using expander = int[];\ + constexpr char const* tmpl_types[] = {CATCH_REC_LIST(INTERNAL_CATCH_STRINGIZE_WITHOUT_PARENS, INTERNAL_CATCH_REMOVE_PARENS(TmplTypes))};\ + constexpr char const* types_list[] = {CATCH_REC_LIST(INTERNAL_CATCH_STRINGIZE_WITHOUT_PARENS, INTERNAL_CATCH_REMOVE_PARENS(TypesList))};\ + constexpr auto num_types = sizeof(types_list) / sizeof(types_list[0]);\ + (void)expander{(Catch::AutoReg( Catch::makeTestInvoker( &TestName::test ), CATCH_INTERNAL_LINEINFO, #ClassName, Catch::NameAndTags{ Name " - " + std::string(tmpl_types[index / num_types]) + "<" + std::string(types_list[index % num_types]) + ">", Tags } ), index++, 0)... };/* NOLINT */ \ + }\ + };\ + static int INTERNAL_CATCH_UNIQUE_NAME( globalRegistrar ) = [](){\ + using TestInit = Catch::combine\ + ::with_types::into::type;\ + TestInit();\ + return 0;\ + }(); \ + }\ + CATCH_INTERNAL_UNSUPPRESS_GLOBALS_WARNINGS \ + template \ + void TestName::test() + +#ifndef CATCH_CONFIG_TRADITIONAL_MSVC_PREPROCESSOR + #define INTERNAL_CATCH_TEMPLATE_PRODUCT_TEST_CASE_METHOD( ClassName, Name, Tags, ... )\ + INTERNAL_CATCH_TEMPLATE_PRODUCT_TEST_CASE_METHOD_2( INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____ ), INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____F_U_N_C____ ), ClassName, Name, Tags, __VA_ARGS__ ) +#else + #define INTERNAL_CATCH_TEMPLATE_PRODUCT_TEST_CASE_METHOD( ClassName, Name, Tags, ... )\ + INTERNAL_CATCH_EXPAND_VARGS( INTERNAL_CATCH_TEMPLATE_PRODUCT_TEST_CASE_METHOD_2( INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____ ), INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____F_U_N_C____ ), ClassName, Name, Tags, __VA_ARGS__ ) ) +#endif + +// end catch_test_registry.h +// start catch_capture.hpp + +// start catch_assertionhandler.h + +// start catch_assertioninfo.h + +// start catch_result_type.h + +namespace Catch { + + // ResultWas::OfType enum + struct ResultWas { enum OfType { + Unknown = -1, + Ok = 0, + Info = 1, + Warning = 2, + + FailureBit = 0x10, + + ExpressionFailed = FailureBit | 1, + ExplicitFailure = FailureBit | 2, + + Exception = 0x100 | FailureBit, + + ThrewException = Exception | 1, + DidntThrowException = Exception | 2, + + FatalErrorCondition = 0x200 | FailureBit + + }; }; + + bool isOk( ResultWas::OfType resultType ); + bool isJustInfo( int flags ); + + // ResultDisposition::Flags enum + struct ResultDisposition { enum Flags { + Normal = 0x01, + + ContinueOnFailure = 0x02, // Failures fail test, but execution continues + FalseTest = 0x04, // Prefix expression with ! + SuppressFail = 0x08 // Failures are reported but do not fail the test + }; }; + + ResultDisposition::Flags operator | ( ResultDisposition::Flags lhs, ResultDisposition::Flags rhs ); + + bool shouldContinueOnFailure( int flags ); + inline bool isFalseTest( int flags ) { return ( flags & ResultDisposition::FalseTest ) != 0; } + bool shouldSuppressFailure( int flags ); + +} // end namespace Catch + +// end catch_result_type.h +namespace Catch { + + struct AssertionInfo + { + StringRef macroName; + SourceLineInfo lineInfo; + StringRef capturedExpression; + ResultDisposition::Flags resultDisposition; + + // We want to delete this constructor but a compiler bug in 4.8 means + // the struct is then treated as non-aggregate + //AssertionInfo() = delete; + }; + +} // end namespace Catch + +// end catch_assertioninfo.h +// start catch_decomposer.h + +// start catch_tostring.h + +#include +#include +#include +#include +// start catch_stream.h + +#include +#include +#include + +namespace Catch { + + std::ostream& cout(); + std::ostream& cerr(); + std::ostream& clog(); + + class StringRef; + + struct IStream { + virtual ~IStream(); + virtual std::ostream& stream() const = 0; + }; + + auto makeStream( StringRef const &filename ) -> IStream const*; + + class ReusableStringStream { + std::size_t m_index; + std::ostream* m_oss; + public: + ReusableStringStream(); + ~ReusableStringStream(); + + auto str() const -> std::string; + + template + auto operator << ( T const& value ) -> ReusableStringStream& { + *m_oss << value; + return *this; + } + auto get() -> std::ostream& { return *m_oss; } + }; +} + +// end catch_stream.h + +#ifdef CATCH_CONFIG_CPP17_STRING_VIEW +#include +#endif + +#ifdef __OBJC__ +// start catch_objc_arc.hpp + +#import + +#ifdef __has_feature +#define CATCH_ARC_ENABLED __has_feature(objc_arc) +#else +#define CATCH_ARC_ENABLED 0 +#endif + +void arcSafeRelease( NSObject* obj ); +id performOptionalSelector( id obj, SEL sel ); + +#if !CATCH_ARC_ENABLED +inline void arcSafeRelease( NSObject* obj ) { + [obj release]; +} +inline id performOptionalSelector( id obj, SEL sel ) { + if( [obj respondsToSelector: sel] ) + return [obj performSelector: sel]; + return nil; +} +#define CATCH_UNSAFE_UNRETAINED +#define CATCH_ARC_STRONG +#else +inline void arcSafeRelease( NSObject* ){} +inline id performOptionalSelector( id obj, SEL sel ) { +#ifdef __clang__ +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Warc-performSelector-leaks" +#endif + if( [obj respondsToSelector: sel] ) + return [obj performSelector: sel]; +#ifdef __clang__ +#pragma clang diagnostic pop +#endif + return nil; +} +#define CATCH_UNSAFE_UNRETAINED __unsafe_unretained +#define CATCH_ARC_STRONG __strong +#endif + +// end catch_objc_arc.hpp +#endif + +#ifdef _MSC_VER +#pragma warning(push) +#pragma warning(disable:4180) // We attempt to stream a function (address) by const&, which MSVC complains about but is harmless +#endif + +namespace Catch { + namespace Detail { + + extern const std::string unprintableString; + + std::string rawMemoryToString( const void *object, std::size_t size ); + + template + std::string rawMemoryToString( const T& object ) { + return rawMemoryToString( &object, sizeof(object) ); + } + + template + class IsStreamInsertable { + template + static auto test(int) + -> decltype(std::declval() << std::declval(), std::true_type()); + + template + static auto test(...)->std::false_type; + + public: + static const bool value = decltype(test(0))::value; + }; + + template + std::string convertUnknownEnumToString( E e ); + + template + typename std::enable_if< + !std::is_enum::value && !std::is_base_of::value, + std::string>::type convertUnstreamable( T const& ) { + return Detail::unprintableString; + } + template + typename std::enable_if< + !std::is_enum::value && std::is_base_of::value, + std::string>::type convertUnstreamable(T const& ex) { + return ex.what(); + } + + template + typename std::enable_if< + std::is_enum::value + , std::string>::type convertUnstreamable( T const& value ) { + return convertUnknownEnumToString( value ); + } + +#if defined(_MANAGED) + //! Convert a CLR string to a utf8 std::string + template + std::string clrReferenceToString( T^ ref ) { + if (ref == nullptr) + return std::string("null"); + auto bytes = System::Text::Encoding::UTF8->GetBytes(ref->ToString()); + cli::pin_ptr p = &bytes[0]; + return std::string(reinterpret_cast(p), bytes->Length); + } +#endif + + } // namespace Detail + + // If we decide for C++14, change these to enable_if_ts + template + struct StringMaker { + template + static + typename std::enable_if<::Catch::Detail::IsStreamInsertable::value, std::string>::type + convert(const Fake& value) { + ReusableStringStream rss; + // NB: call using the function-like syntax to avoid ambiguity with + // user-defined templated operator<< under clang. + rss.operator<<(value); + return rss.str(); + } + + template + static + typename std::enable_if::value, std::string>::type + convert( const Fake& value ) { +#if !defined(CATCH_CONFIG_FALLBACK_STRINGIFIER) + return Detail::convertUnstreamable(value); +#else + return CATCH_CONFIG_FALLBACK_STRINGIFIER(value); +#endif + } + }; + + namespace Detail { + + // This function dispatches all stringification requests inside of Catch. + // Should be preferably called fully qualified, like ::Catch::Detail::stringify + template + std::string stringify(const T& e) { + return ::Catch::StringMaker::type>::type>::convert(e); + } + + template + std::string convertUnknownEnumToString( E e ) { + return ::Catch::Detail::stringify(static_cast::type>(e)); + } + +#if defined(_MANAGED) + template + std::string stringify( T^ e ) { + return ::Catch::StringMaker::convert(e); + } +#endif + + } // namespace Detail + + // Some predefined specializations + + template<> + struct StringMaker { + static std::string convert(const std::string& str); + }; + +#ifdef CATCH_CONFIG_CPP17_STRING_VIEW + template<> + struct StringMaker { + static std::string convert(std::string_view str); + }; +#endif + + template<> + struct StringMaker { + static std::string convert(char const * str); + }; + template<> + struct StringMaker { + static std::string convert(char * str); + }; + +#ifdef CATCH_CONFIG_WCHAR + template<> + struct StringMaker { + static std::string convert(const std::wstring& wstr); + }; + +# ifdef CATCH_CONFIG_CPP17_STRING_VIEW + template<> + struct StringMaker { + static std::string convert(std::wstring_view str); + }; +# endif + + template<> + struct StringMaker { + static std::string convert(wchar_t const * str); + }; + template<> + struct StringMaker { + static std::string convert(wchar_t * str); + }; +#endif + + // TBD: Should we use `strnlen` to ensure that we don't go out of the buffer, + // while keeping string semantics? + template + struct StringMaker { + static std::string convert(char const* str) { + return ::Catch::Detail::stringify(std::string{ str }); + } + }; + template + struct StringMaker { + static std::string convert(signed char const* str) { + return ::Catch::Detail::stringify(std::string{ reinterpret_cast(str) }); + } + }; + template + struct StringMaker { + static std::string convert(unsigned char const* str) { + return ::Catch::Detail::stringify(std::string{ reinterpret_cast(str) }); + } + }; + + template<> + struct StringMaker { + static std::string convert(int value); + }; + template<> + struct StringMaker { + static std::string convert(long value); + }; + template<> + struct StringMaker { + static std::string convert(long long value); + }; + template<> + struct StringMaker { + static std::string convert(unsigned int value); + }; + template<> + struct StringMaker { + static std::string convert(unsigned long value); + }; + template<> + struct StringMaker { + static std::string convert(unsigned long long value); + }; + + template<> + struct StringMaker { + static std::string convert(bool b); + }; + + template<> + struct StringMaker { + static std::string convert(char c); + }; + template<> + struct StringMaker { + static std::string convert(signed char c); + }; + template<> + struct StringMaker { + static std::string convert(unsigned char c); + }; + + template<> + struct StringMaker { + static std::string convert(std::nullptr_t); + }; + + template<> + struct StringMaker { + static std::string convert(float value); + }; + template<> + struct StringMaker { + static std::string convert(double value); + }; + + template + struct StringMaker { + template + static std::string convert(U* p) { + if (p) { + return ::Catch::Detail::rawMemoryToString(p); + } else { + return "nullptr"; + } + } + }; + + template + struct StringMaker { + static std::string convert(R C::* p) { + if (p) { + return ::Catch::Detail::rawMemoryToString(p); + } else { + return "nullptr"; + } + } + }; + +#if defined(_MANAGED) + template + struct StringMaker { + static std::string convert( T^ ref ) { + return ::Catch::Detail::clrReferenceToString(ref); + } + }; +#endif + + namespace Detail { + template + std::string rangeToString(InputIterator first, InputIterator last) { + ReusableStringStream rss; + rss << "{ "; + if (first != last) { + rss << ::Catch::Detail::stringify(*first); + for (++first; first != last; ++first) + rss << ", " << ::Catch::Detail::stringify(*first); + } + rss << " }"; + return rss.str(); + } + } + +#ifdef __OBJC__ + template<> + struct StringMaker { + static std::string convert(NSString * nsstring) { + if (!nsstring) + return "nil"; + return std::string("@") + [nsstring UTF8String]; + } + }; + template<> + struct StringMaker { + static std::string convert(NSObject* nsObject) { + return ::Catch::Detail::stringify([nsObject description]); + } + + }; + namespace Detail { + inline std::string stringify( NSString* nsstring ) { + return StringMaker::convert( nsstring ); + } + + } // namespace Detail +#endif // __OBJC__ + +} // namespace Catch + +////////////////////////////////////////////////////// +// Separate std-lib types stringification, so it can be selectively enabled +// This means that we do not bring in + +#if defined(CATCH_CONFIG_ENABLE_ALL_STRINGMAKERS) +# define CATCH_CONFIG_ENABLE_PAIR_STRINGMAKER +# define CATCH_CONFIG_ENABLE_TUPLE_STRINGMAKER +# define CATCH_CONFIG_ENABLE_VARIANT_STRINGMAKER +# define CATCH_CONFIG_ENABLE_CHRONO_STRINGMAKER +# define CATCH_CONFIG_ENABLE_OPTIONAL_STRINGMAKER +#endif + +// Separate std::pair specialization +#if defined(CATCH_CONFIG_ENABLE_PAIR_STRINGMAKER) +#include +namespace Catch { + template + struct StringMaker > { + static std::string convert(const std::pair& pair) { + ReusableStringStream rss; + rss << "{ " + << ::Catch::Detail::stringify(pair.first) + << ", " + << ::Catch::Detail::stringify(pair.second) + << " }"; + return rss.str(); + } + }; +} +#endif // CATCH_CONFIG_ENABLE_PAIR_STRINGMAKER + +#if defined(CATCH_CONFIG_ENABLE_OPTIONAL_STRINGMAKER) && defined(CATCH_CONFIG_CPP17_OPTIONAL) +#include +namespace Catch { + template + struct StringMaker > { + static std::string convert(const std::optional& optional) { + ReusableStringStream rss; + if (optional.has_value()) { + rss << ::Catch::Detail::stringify(*optional); + } else { + rss << "{ }"; + } + return rss.str(); + } + }; +} +#endif // CATCH_CONFIG_ENABLE_OPTIONAL_STRINGMAKER + +// Separate std::tuple specialization +#if defined(CATCH_CONFIG_ENABLE_TUPLE_STRINGMAKER) +#include +namespace Catch { + namespace Detail { + template< + typename Tuple, + std::size_t N = 0, + bool = (N < std::tuple_size::value) + > + struct TupleElementPrinter { + static void print(const Tuple& tuple, std::ostream& os) { + os << (N ? ", " : " ") + << ::Catch::Detail::stringify(std::get(tuple)); + TupleElementPrinter::print(tuple, os); + } + }; + + template< + typename Tuple, + std::size_t N + > + struct TupleElementPrinter { + static void print(const Tuple&, std::ostream&) {} + }; + + } + + template + struct StringMaker> { + static std::string convert(const std::tuple& tuple) { + ReusableStringStream rss; + rss << '{'; + Detail::TupleElementPrinter>::print(tuple, rss.get()); + rss << " }"; + return rss.str(); + } + }; +} +#endif // CATCH_CONFIG_ENABLE_TUPLE_STRINGMAKER + +#if defined(CATCH_CONFIG_ENABLE_VARIANT_STRINGMAKER) && defined(CATCH_CONFIG_CPP17_VARIANT) +#include +namespace Catch { + template<> + struct StringMaker { + static std::string convert(const std::monostate&) { + return "{ }"; + } + }; + + template + struct StringMaker> { + static std::string convert(const std::variant& variant) { + if (variant.valueless_by_exception()) { + return "{valueless variant}"; + } else { + return std::visit( + [](const auto& value) { + return ::Catch::Detail::stringify(value); + }, + variant + ); + } + } + }; +} +#endif // CATCH_CONFIG_ENABLE_VARIANT_STRINGMAKER + +namespace Catch { + struct not_this_one {}; // Tag type for detecting which begin/ end are being selected + + // Import begin/ end from std here so they are considered alongside the fallback (...) overloads in this namespace + using std::begin; + using std::end; + + not_this_one begin( ... ); + not_this_one end( ... ); + + template + struct is_range { + static const bool value = + !std::is_same())), not_this_one>::value && + !std::is_same())), not_this_one>::value; + }; + +#if defined(_MANAGED) // Managed types are never ranges + template + struct is_range { + static const bool value = false; + }; +#endif + + template + std::string rangeToString( Range const& range ) { + return ::Catch::Detail::rangeToString( begin( range ), end( range ) ); + } + + // Handle vector specially + template + std::string rangeToString( std::vector const& v ) { + ReusableStringStream rss; + rss << "{ "; + bool first = true; + for( bool b : v ) { + if( first ) + first = false; + else + rss << ", "; + rss << ::Catch::Detail::stringify( b ); + } + rss << " }"; + return rss.str(); + } + + template + struct StringMaker::value && !::Catch::Detail::IsStreamInsertable::value>::type> { + static std::string convert( R const& range ) { + return rangeToString( range ); + } + }; + + template + struct StringMaker { + static std::string convert(T const(&arr)[SZ]) { + return rangeToString(arr); + } + }; + +} // namespace Catch + +// Separate std::chrono::duration specialization +#if defined(CATCH_CONFIG_ENABLE_CHRONO_STRINGMAKER) +#include +#include +#include + +namespace Catch { + +template +struct ratio_string { + static std::string symbol(); +}; + +template +std::string ratio_string::symbol() { + Catch::ReusableStringStream rss; + rss << '[' << Ratio::num << '/' + << Ratio::den << ']'; + return rss.str(); +} +template <> +struct ratio_string { + static std::string symbol(); +}; +template <> +struct ratio_string { + static std::string symbol(); +}; +template <> +struct ratio_string { + static std::string symbol(); +}; +template <> +struct ratio_string { + static std::string symbol(); +}; +template <> +struct ratio_string { + static std::string symbol(); +}; +template <> +struct ratio_string { + static std::string symbol(); +}; + + //////////// + // std::chrono::duration specializations + template + struct StringMaker> { + static std::string convert(std::chrono::duration const& duration) { + ReusableStringStream rss; + rss << duration.count() << ' ' << ratio_string::symbol() << 's'; + return rss.str(); + } + }; + template + struct StringMaker>> { + static std::string convert(std::chrono::duration> const& duration) { + ReusableStringStream rss; + rss << duration.count() << " s"; + return rss.str(); + } + }; + template + struct StringMaker>> { + static std::string convert(std::chrono::duration> const& duration) { + ReusableStringStream rss; + rss << duration.count() << " m"; + return rss.str(); + } + }; + template + struct StringMaker>> { + static std::string convert(std::chrono::duration> const& duration) { + ReusableStringStream rss; + rss << duration.count() << " h"; + return rss.str(); + } + }; + + //////////// + // std::chrono::time_point specialization + // Generic time_point cannot be specialized, only std::chrono::time_point + template + struct StringMaker> { + static std::string convert(std::chrono::time_point const& time_point) { + return ::Catch::Detail::stringify(time_point.time_since_epoch()) + " since epoch"; + } + }; + // std::chrono::time_point specialization + template + struct StringMaker> { + static std::string convert(std::chrono::time_point const& time_point) { + auto converted = std::chrono::system_clock::to_time_t(time_point); + +#ifdef _MSC_VER + std::tm timeInfo = {}; + gmtime_s(&timeInfo, &converted); +#else + std::tm* timeInfo = std::gmtime(&converted); +#endif + + auto const timeStampSize = sizeof("2017-01-16T17:06:45Z"); + char timeStamp[timeStampSize]; + const char * const fmt = "%Y-%m-%dT%H:%M:%SZ"; + +#ifdef _MSC_VER + std::strftime(timeStamp, timeStampSize, fmt, &timeInfo); +#else + std::strftime(timeStamp, timeStampSize, fmt, timeInfo); +#endif + return std::string(timeStamp); + } + }; +} +#endif // CATCH_CONFIG_ENABLE_CHRONO_STRINGMAKER + +#ifdef _MSC_VER +#pragma warning(pop) +#endif + +// end catch_tostring.h +#include + +#ifdef _MSC_VER +#pragma warning(push) +#pragma warning(disable:4389) // '==' : signed/unsigned mismatch +#pragma warning(disable:4018) // more "signed/unsigned mismatch" +#pragma warning(disable:4312) // Converting int to T* using reinterpret_cast (issue on x64 platform) +#pragma warning(disable:4180) // qualifier applied to function type has no meaning +#pragma warning(disable:4800) // Forcing result to true or false +#endif + +namespace Catch { + + struct ITransientExpression { + auto isBinaryExpression() const -> bool { return m_isBinaryExpression; } + auto getResult() const -> bool { return m_result; } + virtual void streamReconstructedExpression( std::ostream &os ) const = 0; + + ITransientExpression( bool isBinaryExpression, bool result ) + : m_isBinaryExpression( isBinaryExpression ), + m_result( result ) + {} + + // We don't actually need a virtual destructor, but many static analysers + // complain if it's not here :-( + virtual ~ITransientExpression(); + + bool m_isBinaryExpression; + bool m_result; + + }; + + void formatReconstructedExpression( std::ostream &os, std::string const& lhs, StringRef op, std::string const& rhs ); + + template + class BinaryExpr : public ITransientExpression { + LhsT m_lhs; + StringRef m_op; + RhsT m_rhs; + + void streamReconstructedExpression( std::ostream &os ) const override { + formatReconstructedExpression + ( os, Catch::Detail::stringify( m_lhs ), m_op, Catch::Detail::stringify( m_rhs ) ); + } + + public: + BinaryExpr( bool comparisonResult, LhsT lhs, StringRef op, RhsT rhs ) + : ITransientExpression{ true, comparisonResult }, + m_lhs( lhs ), + m_op( op ), + m_rhs( rhs ) + {} + + template + auto operator && ( T ) const -> BinaryExpr const { + static_assert(always_false::value, + "chained comparisons are not supported inside assertions, " + "wrap the expression inside parentheses, or decompose it"); + } + + template + auto operator || ( T ) const -> BinaryExpr const { + static_assert(always_false::value, + "chained comparisons are not supported inside assertions, " + "wrap the expression inside parentheses, or decompose it"); + } + + template + auto operator == ( T ) const -> BinaryExpr const { + static_assert(always_false::value, + "chained comparisons are not supported inside assertions, " + "wrap the expression inside parentheses, or decompose it"); + } + + template + auto operator != ( T ) const -> BinaryExpr const { + static_assert(always_false::value, + "chained comparisons are not supported inside assertions, " + "wrap the expression inside parentheses, or decompose it"); + } + + template + auto operator > ( T ) const -> BinaryExpr const { + static_assert(always_false::value, + "chained comparisons are not supported inside assertions, " + "wrap the expression inside parentheses, or decompose it"); + } + + template + auto operator < ( T ) const -> BinaryExpr const { + static_assert(always_false::value, + "chained comparisons are not supported inside assertions, " + "wrap the expression inside parentheses, or decompose it"); + } + + template + auto operator >= ( T ) const -> BinaryExpr const { + static_assert(always_false::value, + "chained comparisons are not supported inside assertions, " + "wrap the expression inside parentheses, or decompose it"); + } + + template + auto operator <= ( T ) const -> BinaryExpr const { + static_assert(always_false::value, + "chained comparisons are not supported inside assertions, " + "wrap the expression inside parentheses, or decompose it"); + } + }; + + template + class UnaryExpr : public ITransientExpression { + LhsT m_lhs; + + void streamReconstructedExpression( std::ostream &os ) const override { + os << Catch::Detail::stringify( m_lhs ); + } + + public: + explicit UnaryExpr( LhsT lhs ) + : ITransientExpression{ false, static_cast(lhs) }, + m_lhs( lhs ) + {} + }; + + // Specialised comparison functions to handle equality comparisons between ints and pointers (NULL deduces as an int) + template + auto compareEqual( LhsT const& lhs, RhsT const& rhs ) -> bool { return static_cast(lhs == rhs); } + template + auto compareEqual( T* const& lhs, int rhs ) -> bool { return lhs == reinterpret_cast( rhs ); } + template + auto compareEqual( T* const& lhs, long rhs ) -> bool { return lhs == reinterpret_cast( rhs ); } + template + auto compareEqual( int lhs, T* const& rhs ) -> bool { return reinterpret_cast( lhs ) == rhs; } + template + auto compareEqual( long lhs, T* const& rhs ) -> bool { return reinterpret_cast( lhs ) == rhs; } + + template + auto compareNotEqual( LhsT const& lhs, RhsT&& rhs ) -> bool { return static_cast(lhs != rhs); } + template + auto compareNotEqual( T* const& lhs, int rhs ) -> bool { return lhs != reinterpret_cast( rhs ); } + template + auto compareNotEqual( T* const& lhs, long rhs ) -> bool { return lhs != reinterpret_cast( rhs ); } + template + auto compareNotEqual( int lhs, T* const& rhs ) -> bool { return reinterpret_cast( lhs ) != rhs; } + template + auto compareNotEqual( long lhs, T* const& rhs ) -> bool { return reinterpret_cast( lhs ) != rhs; } + + template + class ExprLhs { + LhsT m_lhs; + public: + explicit ExprLhs( LhsT lhs ) : m_lhs( lhs ) {} + + template + auto operator == ( RhsT const& rhs ) -> BinaryExpr const { + return { compareEqual( m_lhs, rhs ), m_lhs, "==", rhs }; + } + auto operator == ( bool rhs ) -> BinaryExpr const { + return { m_lhs == rhs, m_lhs, "==", rhs }; + } + + template + auto operator != ( RhsT const& rhs ) -> BinaryExpr const { + return { compareNotEqual( m_lhs, rhs ), m_lhs, "!=", rhs }; + } + auto operator != ( bool rhs ) -> BinaryExpr const { + return { m_lhs != rhs, m_lhs, "!=", rhs }; + } + + template + auto operator > ( RhsT const& rhs ) -> BinaryExpr const { + return { static_cast(m_lhs > rhs), m_lhs, ">", rhs }; + } + template + auto operator < ( RhsT const& rhs ) -> BinaryExpr const { + return { static_cast(m_lhs < rhs), m_lhs, "<", rhs }; + } + template + auto operator >= ( RhsT const& rhs ) -> BinaryExpr const { + return { static_cast(m_lhs >= rhs), m_lhs, ">=", rhs }; + } + template + auto operator <= ( RhsT const& rhs ) -> BinaryExpr const { + return { static_cast(m_lhs <= rhs), m_lhs, "<=", rhs }; + } + + template + auto operator && ( RhsT const& ) -> BinaryExpr const { + static_assert(always_false::value, + "operator&& is not supported inside assertions, " + "wrap the expression inside parentheses, or decompose it"); + } + + template + auto operator || ( RhsT const& ) -> BinaryExpr const { + static_assert(always_false::value, + "operator|| is not supported inside assertions, " + "wrap the expression inside parentheses, or decompose it"); + } + + auto makeUnaryExpr() const -> UnaryExpr { + return UnaryExpr{ m_lhs }; + } + }; + + void handleExpression( ITransientExpression const& expr ); + + template + void handleExpression( ExprLhs const& expr ) { + handleExpression( expr.makeUnaryExpr() ); + } + + struct Decomposer { + template + auto operator <= ( T const& lhs ) -> ExprLhs { + return ExprLhs{ lhs }; + } + + auto operator <=( bool value ) -> ExprLhs { + return ExprLhs{ value }; + } + }; + +} // end namespace Catch + +#ifdef _MSC_VER +#pragma warning(pop) +#endif + +// end catch_decomposer.h +// start catch_interfaces_capture.h + +#include + +namespace Catch { + + class AssertionResult; + struct AssertionInfo; + struct SectionInfo; + struct SectionEndInfo; + struct MessageInfo; + struct MessageBuilder; + struct Counts; + struct BenchmarkInfo; + struct BenchmarkStats; + struct AssertionReaction; + struct SourceLineInfo; + + struct ITransientExpression; + struct IGeneratorTracker; + + struct IResultCapture { + + virtual ~IResultCapture(); + + virtual bool sectionStarted( SectionInfo const& sectionInfo, + Counts& assertions ) = 0; + virtual void sectionEnded( SectionEndInfo const& endInfo ) = 0; + virtual void sectionEndedEarly( SectionEndInfo const& endInfo ) = 0; + + virtual auto acquireGeneratorTracker( SourceLineInfo const& lineInfo ) -> IGeneratorTracker& = 0; + + virtual void benchmarkStarting( BenchmarkInfo const& info ) = 0; + virtual void benchmarkEnded( BenchmarkStats const& stats ) = 0; + + virtual void pushScopedMessage( MessageInfo const& message ) = 0; + virtual void popScopedMessage( MessageInfo const& message ) = 0; + + virtual void emplaceUnscopedMessage( MessageBuilder const& builder ) = 0; + + virtual void handleFatalErrorCondition( StringRef message ) = 0; + + virtual void handleExpr + ( AssertionInfo const& info, + ITransientExpression const& expr, + AssertionReaction& reaction ) = 0; + virtual void handleMessage + ( AssertionInfo const& info, + ResultWas::OfType resultType, + StringRef const& message, + AssertionReaction& reaction ) = 0; + virtual void handleUnexpectedExceptionNotThrown + ( AssertionInfo const& info, + AssertionReaction& reaction ) = 0; + virtual void handleUnexpectedInflightException + ( AssertionInfo const& info, + std::string const& message, + AssertionReaction& reaction ) = 0; + virtual void handleIncomplete + ( AssertionInfo const& info ) = 0; + virtual void handleNonExpr + ( AssertionInfo const &info, + ResultWas::OfType resultType, + AssertionReaction &reaction ) = 0; + + virtual bool lastAssertionPassed() = 0; + virtual void assertionPassed() = 0; + + // Deprecated, do not use: + virtual std::string getCurrentTestName() const = 0; + virtual const AssertionResult* getLastResult() const = 0; + virtual void exceptionEarlyReported() = 0; + }; + + IResultCapture& getResultCapture(); +} + +// end catch_interfaces_capture.h +namespace Catch { + + struct TestFailureException{}; + struct AssertionResultData; + struct IResultCapture; + class RunContext; + + class LazyExpression { + friend class AssertionHandler; + friend struct AssertionStats; + friend class RunContext; + + ITransientExpression const* m_transientExpression = nullptr; + bool m_isNegated; + public: + LazyExpression( bool isNegated ); + LazyExpression( LazyExpression const& other ); + LazyExpression& operator = ( LazyExpression const& ) = delete; + + explicit operator bool() const; + + friend auto operator << ( std::ostream& os, LazyExpression const& lazyExpr ) -> std::ostream&; + }; + + struct AssertionReaction { + bool shouldDebugBreak = false; + bool shouldThrow = false; + }; + + class AssertionHandler { + AssertionInfo m_assertionInfo; + AssertionReaction m_reaction; + bool m_completed = false; + IResultCapture& m_resultCapture; + + public: + AssertionHandler + ( StringRef const& macroName, + SourceLineInfo const& lineInfo, + StringRef capturedExpression, + ResultDisposition::Flags resultDisposition ); + ~AssertionHandler() { + if ( !m_completed ) { + m_resultCapture.handleIncomplete( m_assertionInfo ); + } + } + + template + void handleExpr( ExprLhs const& expr ) { + handleExpr( expr.makeUnaryExpr() ); + } + void handleExpr( ITransientExpression const& expr ); + + void handleMessage(ResultWas::OfType resultType, StringRef const& message); + + void handleExceptionThrownAsExpected(); + void handleUnexpectedExceptionNotThrown(); + void handleExceptionNotThrownAsExpected(); + void handleThrowingCallSkipped(); + void handleUnexpectedInflightException(); + + void complete(); + void setCompleted(); + + // query + auto allowThrows() const -> bool; + }; + + void handleExceptionMatchExpr( AssertionHandler& handler, std::string const& str, StringRef const& matcherString ); + +} // namespace Catch + +// end catch_assertionhandler.h +// start catch_message.h + +#include +#include + +namespace Catch { + + struct MessageInfo { + MessageInfo( StringRef const& _macroName, + SourceLineInfo const& _lineInfo, + ResultWas::OfType _type ); + + StringRef macroName; + std::string message; + SourceLineInfo lineInfo; + ResultWas::OfType type; + unsigned int sequence; + + bool operator == ( MessageInfo const& other ) const; + bool operator < ( MessageInfo const& other ) const; + private: + static unsigned int globalCount; + }; + + struct MessageStream { + + template + MessageStream& operator << ( T const& value ) { + m_stream << value; + return *this; + } + + ReusableStringStream m_stream; + }; + + struct MessageBuilder : MessageStream { + MessageBuilder( StringRef const& macroName, + SourceLineInfo const& lineInfo, + ResultWas::OfType type ); + + template + MessageBuilder& operator << ( T const& value ) { + m_stream << value; + return *this; + } + + MessageInfo m_info; + }; + + class ScopedMessage { + public: + explicit ScopedMessage( MessageBuilder const& builder ); + ScopedMessage( ScopedMessage& duplicate ) = delete; + ScopedMessage( ScopedMessage&& old ); + ~ScopedMessage(); + + MessageInfo m_info; + bool m_moved; + }; + + class Capturer { + std::vector m_messages; + IResultCapture& m_resultCapture = getResultCapture(); + size_t m_captured = 0; + public: + Capturer( StringRef macroName, SourceLineInfo const& lineInfo, ResultWas::OfType resultType, StringRef names ); + ~Capturer(); + + void captureValue( size_t index, std::string const& value ); + + template + void captureValues( size_t index, T const& value ) { + captureValue( index, Catch::Detail::stringify( value ) ); + } + + template + void captureValues( size_t index, T const& value, Ts const&... values ) { + captureValue( index, Catch::Detail::stringify(value) ); + captureValues( index+1, values... ); + } + }; + +} // end namespace Catch + +// end catch_message.h +#if !defined(CATCH_CONFIG_DISABLE) + +#if !defined(CATCH_CONFIG_DISABLE_STRINGIFICATION) + #define CATCH_INTERNAL_STRINGIFY(...) #__VA_ARGS__ +#else + #define CATCH_INTERNAL_STRINGIFY(...) "Disabled by CATCH_CONFIG_DISABLE_STRINGIFICATION" +#endif + +#if defined(CATCH_CONFIG_FAST_COMPILE) || defined(CATCH_CONFIG_DISABLE_EXCEPTIONS) + +/////////////////////////////////////////////////////////////////////////////// +// Another way to speed-up compilation is to omit local try-catch for REQUIRE* +// macros. +#define INTERNAL_CATCH_TRY +#define INTERNAL_CATCH_CATCH( capturer ) + +#else // CATCH_CONFIG_FAST_COMPILE + +#define INTERNAL_CATCH_TRY try +#define INTERNAL_CATCH_CATCH( handler ) catch(...) { handler.handleUnexpectedInflightException(); } + +#endif + +#define INTERNAL_CATCH_REACT( handler ) handler.complete(); + +/////////////////////////////////////////////////////////////////////////////// +#define INTERNAL_CATCH_TEST( macroName, resultDisposition, ... ) \ + do { \ + Catch::AssertionHandler catchAssertionHandler( macroName##_catch_sr, CATCH_INTERNAL_LINEINFO, CATCH_INTERNAL_STRINGIFY(__VA_ARGS__), resultDisposition ); \ + INTERNAL_CATCH_TRY { \ + CATCH_INTERNAL_SUPPRESS_PARENTHESES_WARNINGS \ + catchAssertionHandler.handleExpr( Catch::Decomposer() <= __VA_ARGS__ ); \ + CATCH_INTERNAL_UNSUPPRESS_PARENTHESES_WARNINGS \ + } INTERNAL_CATCH_CATCH( catchAssertionHandler ) \ + INTERNAL_CATCH_REACT( catchAssertionHandler ) \ + } while( (void)0, (false) && static_cast( !!(__VA_ARGS__) ) ) // the expression here is never evaluated at runtime but it forces the compiler to give it a look + // The double negation silences MSVC's C4800 warning, the static_cast forces short-circuit evaluation if the type has overloaded &&. + +/////////////////////////////////////////////////////////////////////////////// +#define INTERNAL_CATCH_IF( macroName, resultDisposition, ... ) \ + INTERNAL_CATCH_TEST( macroName, resultDisposition, __VA_ARGS__ ); \ + if( Catch::getResultCapture().lastAssertionPassed() ) + +/////////////////////////////////////////////////////////////////////////////// +#define INTERNAL_CATCH_ELSE( macroName, resultDisposition, ... ) \ + INTERNAL_CATCH_TEST( macroName, resultDisposition, __VA_ARGS__ ); \ + if( !Catch::getResultCapture().lastAssertionPassed() ) + +/////////////////////////////////////////////////////////////////////////////// +#define INTERNAL_CATCH_NO_THROW( macroName, resultDisposition, ... ) \ + do { \ + Catch::AssertionHandler catchAssertionHandler( macroName##_catch_sr, CATCH_INTERNAL_LINEINFO, CATCH_INTERNAL_STRINGIFY(__VA_ARGS__), resultDisposition ); \ + try { \ + static_cast(__VA_ARGS__); \ + catchAssertionHandler.handleExceptionNotThrownAsExpected(); \ + } \ + catch( ... ) { \ + catchAssertionHandler.handleUnexpectedInflightException(); \ + } \ + INTERNAL_CATCH_REACT( catchAssertionHandler ) \ + } while( false ) + +/////////////////////////////////////////////////////////////////////////////// +#define INTERNAL_CATCH_THROWS( macroName, resultDisposition, ... ) \ + do { \ + Catch::AssertionHandler catchAssertionHandler( macroName##_catch_sr, CATCH_INTERNAL_LINEINFO, CATCH_INTERNAL_STRINGIFY(__VA_ARGS__), resultDisposition); \ + if( catchAssertionHandler.allowThrows() ) \ + try { \ + static_cast(__VA_ARGS__); \ + catchAssertionHandler.handleUnexpectedExceptionNotThrown(); \ + } \ + catch( ... ) { \ + catchAssertionHandler.handleExceptionThrownAsExpected(); \ + } \ + else \ + catchAssertionHandler.handleThrowingCallSkipped(); \ + INTERNAL_CATCH_REACT( catchAssertionHandler ) \ + } while( false ) + +/////////////////////////////////////////////////////////////////////////////// +#define INTERNAL_CATCH_THROWS_AS( macroName, exceptionType, resultDisposition, expr ) \ + do { \ + Catch::AssertionHandler catchAssertionHandler( macroName##_catch_sr, CATCH_INTERNAL_LINEINFO, CATCH_INTERNAL_STRINGIFY(expr) ", " CATCH_INTERNAL_STRINGIFY(exceptionType), resultDisposition ); \ + if( catchAssertionHandler.allowThrows() ) \ + try { \ + static_cast(expr); \ + catchAssertionHandler.handleUnexpectedExceptionNotThrown(); \ + } \ + catch( exceptionType const& ) { \ + catchAssertionHandler.handleExceptionThrownAsExpected(); \ + } \ + catch( ... ) { \ + catchAssertionHandler.handleUnexpectedInflightException(); \ + } \ + else \ + catchAssertionHandler.handleThrowingCallSkipped(); \ + INTERNAL_CATCH_REACT( catchAssertionHandler ) \ + } while( false ) + +/////////////////////////////////////////////////////////////////////////////// +#define INTERNAL_CATCH_MSG( macroName, messageType, resultDisposition, ... ) \ + do { \ + Catch::AssertionHandler catchAssertionHandler( macroName##_catch_sr, CATCH_INTERNAL_LINEINFO, Catch::StringRef(), resultDisposition ); \ + catchAssertionHandler.handleMessage( messageType, ( Catch::MessageStream() << __VA_ARGS__ + ::Catch::StreamEndStop() ).m_stream.str() ); \ + INTERNAL_CATCH_REACT( catchAssertionHandler ) \ + } while( false ) + +/////////////////////////////////////////////////////////////////////////////// +#define INTERNAL_CATCH_CAPTURE( varName, macroName, ... ) \ + auto varName = Catch::Capturer( macroName, CATCH_INTERNAL_LINEINFO, Catch::ResultWas::Info, #__VA_ARGS__ ); \ + varName.captureValues( 0, __VA_ARGS__ ) + +/////////////////////////////////////////////////////////////////////////////// +#define INTERNAL_CATCH_INFO( macroName, log ) \ + Catch::ScopedMessage INTERNAL_CATCH_UNIQUE_NAME( scopedMessage )( Catch::MessageBuilder( macroName##_catch_sr, CATCH_INTERNAL_LINEINFO, Catch::ResultWas::Info ) << log ); + +/////////////////////////////////////////////////////////////////////////////// +#define INTERNAL_CATCH_UNSCOPED_INFO( macroName, log ) \ + Catch::getResultCapture().emplaceUnscopedMessage( Catch::MessageBuilder( macroName##_catch_sr, CATCH_INTERNAL_LINEINFO, Catch::ResultWas::Info ) << log ) + +/////////////////////////////////////////////////////////////////////////////// +// Although this is matcher-based, it can be used with just a string +#define INTERNAL_CATCH_THROWS_STR_MATCHES( macroName, resultDisposition, matcher, ... ) \ + do { \ + Catch::AssertionHandler catchAssertionHandler( macroName##_catch_sr, CATCH_INTERNAL_LINEINFO, CATCH_INTERNAL_STRINGIFY(__VA_ARGS__) ", " CATCH_INTERNAL_STRINGIFY(matcher), resultDisposition ); \ + if( catchAssertionHandler.allowThrows() ) \ + try { \ + static_cast(__VA_ARGS__); \ + catchAssertionHandler.handleUnexpectedExceptionNotThrown(); \ + } \ + catch( ... ) { \ + Catch::handleExceptionMatchExpr( catchAssertionHandler, matcher, #matcher##_catch_sr ); \ + } \ + else \ + catchAssertionHandler.handleThrowingCallSkipped(); \ + INTERNAL_CATCH_REACT( catchAssertionHandler ) \ + } while( false ) + +#endif // CATCH_CONFIG_DISABLE + +// end catch_capture.hpp +// start catch_section.h + +// start catch_section_info.h + +// start catch_totals.h + +#include + +namespace Catch { + + struct Counts { + Counts operator - ( Counts const& other ) const; + Counts& operator += ( Counts const& other ); + + std::size_t total() const; + bool allPassed() const; + bool allOk() const; + + std::size_t passed = 0; + std::size_t failed = 0; + std::size_t failedButOk = 0; + }; + + struct Totals { + + Totals operator - ( Totals const& other ) const; + Totals& operator += ( Totals const& other ); + + Totals delta( Totals const& prevTotals ) const; + + int error = 0; + Counts assertions; + Counts testCases; + }; +} + +// end catch_totals.h +#include + +namespace Catch { + + struct SectionInfo { + SectionInfo + ( SourceLineInfo const& _lineInfo, + std::string const& _name ); + + // Deprecated + SectionInfo + ( SourceLineInfo const& _lineInfo, + std::string const& _name, + std::string const& ) : SectionInfo( _lineInfo, _name ) {} + + std::string name; + std::string description; // !Deprecated: this will always be empty + SourceLineInfo lineInfo; + }; + + struct SectionEndInfo { + SectionInfo sectionInfo; + Counts prevAssertions; + double durationInSeconds; + }; + +} // end namespace Catch + +// end catch_section_info.h +// start catch_timer.h + +#include + +namespace Catch { + + auto getCurrentNanosecondsSinceEpoch() -> uint64_t; + auto getEstimatedClockResolution() -> uint64_t; + + class Timer { + uint64_t m_nanoseconds = 0; + public: + void start(); + auto getElapsedNanoseconds() const -> uint64_t; + auto getElapsedMicroseconds() const -> uint64_t; + auto getElapsedMilliseconds() const -> unsigned int; + auto getElapsedSeconds() const -> double; + }; + +} // namespace Catch + +// end catch_timer.h +#include + +namespace Catch { + + class Section : NonCopyable { + public: + Section( SectionInfo const& info ); + ~Section(); + + // This indicates whether the section should be executed or not + explicit operator bool() const; + + private: + SectionInfo m_info; + + std::string m_name; + Counts m_assertions; + bool m_sectionIncluded; + Timer m_timer; + }; + +} // end namespace Catch + +#define INTERNAL_CATCH_SECTION( ... ) \ + CATCH_INTERNAL_SUPPRESS_UNUSED_WARNINGS \ + if( Catch::Section const& INTERNAL_CATCH_UNIQUE_NAME( catch_internal_Section ) = Catch::SectionInfo( CATCH_INTERNAL_LINEINFO, __VA_ARGS__ ) ) \ + CATCH_INTERNAL_UNSUPPRESS_UNUSED_WARNINGS + +#define INTERNAL_CATCH_DYNAMIC_SECTION( ... ) \ + CATCH_INTERNAL_SUPPRESS_UNUSED_WARNINGS \ + if( Catch::Section const& INTERNAL_CATCH_UNIQUE_NAME( catch_internal_Section ) = Catch::SectionInfo( CATCH_INTERNAL_LINEINFO, (Catch::ReusableStringStream() << __VA_ARGS__).str() ) ) \ + CATCH_INTERNAL_UNSUPPRESS_UNUSED_WARNINGS + +// end catch_section.h +// start catch_benchmark.h + +#include +#include + +namespace Catch { + + class BenchmarkLooper { + + std::string m_name; + std::size_t m_count = 0; + std::size_t m_iterationsToRun = 1; + uint64_t m_resolution; + Timer m_timer; + + static auto getResolution() -> uint64_t; + public: + // Keep most of this inline as it's on the code path that is being timed + BenchmarkLooper( StringRef name ) + : m_name( name ), + m_resolution( getResolution() ) + { + reportStart(); + m_timer.start(); + } + + explicit operator bool() { + if( m_count < m_iterationsToRun ) + return true; + return needsMoreIterations(); + } + + void increment() { + ++m_count; + } + + void reportStart(); + auto needsMoreIterations() -> bool; + }; + +} // end namespace Catch + +#define BENCHMARK( name ) \ + for( Catch::BenchmarkLooper looper( name ); looper; looper.increment() ) + +// end catch_benchmark.h +// start catch_interfaces_exception.h + +// start catch_interfaces_registry_hub.h + +#include +#include + +namespace Catch { + + class TestCase; + struct ITestCaseRegistry; + struct IExceptionTranslatorRegistry; + struct IExceptionTranslator; + struct IReporterRegistry; + struct IReporterFactory; + struct ITagAliasRegistry; + class StartupExceptionRegistry; + + using IReporterFactoryPtr = std::shared_ptr; + + struct IRegistryHub { + virtual ~IRegistryHub(); + + virtual IReporterRegistry const& getReporterRegistry() const = 0; + virtual ITestCaseRegistry const& getTestCaseRegistry() const = 0; + virtual ITagAliasRegistry const& getTagAliasRegistry() const = 0; + + virtual IExceptionTranslatorRegistry const& getExceptionTranslatorRegistry() const = 0; + + virtual StartupExceptionRegistry const& getStartupExceptionRegistry() const = 0; + }; + + struct IMutableRegistryHub { + virtual ~IMutableRegistryHub(); + virtual void registerReporter( std::string const& name, IReporterFactoryPtr const& factory ) = 0; + virtual void registerListener( IReporterFactoryPtr const& factory ) = 0; + virtual void registerTest( TestCase const& testInfo ) = 0; + virtual void registerTranslator( const IExceptionTranslator* translator ) = 0; + virtual void registerTagAlias( std::string const& alias, std::string const& tag, SourceLineInfo const& lineInfo ) = 0; + virtual void registerStartupException() noexcept = 0; + }; + + IRegistryHub const& getRegistryHub(); + IMutableRegistryHub& getMutableRegistryHub(); + void cleanUp(); + std::string translateActiveException(); + +} + +// end catch_interfaces_registry_hub.h +#if defined(CATCH_CONFIG_DISABLE) + #define INTERNAL_CATCH_TRANSLATE_EXCEPTION_NO_REG( translatorName, signature) \ + static std::string translatorName( signature ) +#endif + +#include +#include +#include + +namespace Catch { + using exceptionTranslateFunction = std::string(*)(); + + struct IExceptionTranslator; + using ExceptionTranslators = std::vector>; + + struct IExceptionTranslator { + virtual ~IExceptionTranslator(); + virtual std::string translate( ExceptionTranslators::const_iterator it, ExceptionTranslators::const_iterator itEnd ) const = 0; + }; + + struct IExceptionTranslatorRegistry { + virtual ~IExceptionTranslatorRegistry(); + + virtual std::string translateActiveException() const = 0; + }; + + class ExceptionTranslatorRegistrar { + template + class ExceptionTranslator : public IExceptionTranslator { + public: + + ExceptionTranslator( std::string(*translateFunction)( T& ) ) + : m_translateFunction( translateFunction ) + {} + + std::string translate( ExceptionTranslators::const_iterator it, ExceptionTranslators::const_iterator itEnd ) const override { + try { + if( it == itEnd ) + std::rethrow_exception(std::current_exception()); + else + return (*it)->translate( it+1, itEnd ); + } + catch( T& ex ) { + return m_translateFunction( ex ); + } + } + + protected: + std::string(*m_translateFunction)( T& ); + }; + + public: + template + ExceptionTranslatorRegistrar( std::string(*translateFunction)( T& ) ) { + getMutableRegistryHub().registerTranslator + ( new ExceptionTranslator( translateFunction ) ); + } + }; +} + +/////////////////////////////////////////////////////////////////////////////// +#define INTERNAL_CATCH_TRANSLATE_EXCEPTION2( translatorName, signature ) \ + static std::string translatorName( signature ); \ + CATCH_INTERNAL_SUPPRESS_GLOBALS_WARNINGS \ + namespace{ Catch::ExceptionTranslatorRegistrar INTERNAL_CATCH_UNIQUE_NAME( catch_internal_ExceptionRegistrar )( &translatorName ); } \ + CATCH_INTERNAL_UNSUPPRESS_GLOBALS_WARNINGS \ + static std::string translatorName( signature ) + +#define INTERNAL_CATCH_TRANSLATE_EXCEPTION( signature ) INTERNAL_CATCH_TRANSLATE_EXCEPTION2( INTERNAL_CATCH_UNIQUE_NAME( catch_internal_ExceptionTranslator ), signature ) + +// end catch_interfaces_exception.h +// start catch_approx.h + +#include + +namespace Catch { +namespace Detail { + + class Approx { + private: + bool equalityComparisonImpl(double other) const; + // Validates the new margin (margin >= 0) + // out-of-line to avoid including stdexcept in the header + void setMargin(double margin); + // Validates the new epsilon (0 < epsilon < 1) + // out-of-line to avoid including stdexcept in the header + void setEpsilon(double epsilon); + + public: + explicit Approx ( double value ); + + static Approx custom(); + + Approx operator-() const; + + template ::value>::type> + Approx operator()( T const& value ) { + Approx approx( static_cast(value) ); + approx.m_epsilon = m_epsilon; + approx.m_margin = m_margin; + approx.m_scale = m_scale; + return approx; + } + + template ::value>::type> + explicit Approx( T const& value ): Approx(static_cast(value)) + {} + + template ::value>::type> + friend bool operator == ( const T& lhs, Approx const& rhs ) { + auto lhs_v = static_cast(lhs); + return rhs.equalityComparisonImpl(lhs_v); + } + + template ::value>::type> + friend bool operator == ( Approx const& lhs, const T& rhs ) { + return operator==( rhs, lhs ); + } + + template ::value>::type> + friend bool operator != ( T const& lhs, Approx const& rhs ) { + return !operator==( lhs, rhs ); + } + + template ::value>::type> + friend bool operator != ( Approx const& lhs, T const& rhs ) { + return !operator==( rhs, lhs ); + } + + template ::value>::type> + friend bool operator <= ( T const& lhs, Approx const& rhs ) { + return static_cast(lhs) < rhs.m_value || lhs == rhs; + } + + template ::value>::type> + friend bool operator <= ( Approx const& lhs, T const& rhs ) { + return lhs.m_value < static_cast(rhs) || lhs == rhs; + } + + template ::value>::type> + friend bool operator >= ( T const& lhs, Approx const& rhs ) { + return static_cast(lhs) > rhs.m_value || lhs == rhs; + } + + template ::value>::type> + friend bool operator >= ( Approx const& lhs, T const& rhs ) { + return lhs.m_value > static_cast(rhs) || lhs == rhs; + } + + template ::value>::type> + Approx& epsilon( T const& newEpsilon ) { + double epsilonAsDouble = static_cast(newEpsilon); + setEpsilon(epsilonAsDouble); + return *this; + } + + template ::value>::type> + Approx& margin( T const& newMargin ) { + double marginAsDouble = static_cast(newMargin); + setMargin(marginAsDouble); + return *this; + } + + template ::value>::type> + Approx& scale( T const& newScale ) { + m_scale = static_cast(newScale); + return *this; + } + + std::string toString() const; + + private: + double m_epsilon; + double m_margin; + double m_scale; + double m_value; + }; +} // end namespace Detail + +namespace literals { + Detail::Approx operator "" _a(long double val); + Detail::Approx operator "" _a(unsigned long long val); +} // end namespace literals + +template<> +struct StringMaker { + static std::string convert(Catch::Detail::Approx const& value); +}; + +} // end namespace Catch + +// end catch_approx.h +// start catch_string_manip.h + +#include +#include + +namespace Catch { + + bool startsWith( std::string const& s, std::string const& prefix ); + bool startsWith( std::string const& s, char prefix ); + bool endsWith( std::string const& s, std::string const& suffix ); + bool endsWith( std::string const& s, char suffix ); + bool contains( std::string const& s, std::string const& infix ); + void toLowerInPlace( std::string& s ); + std::string toLower( std::string const& s ); + std::string trim( std::string const& str ); + bool replaceInPlace( std::string& str, std::string const& replaceThis, std::string const& withThis ); + + struct pluralise { + pluralise( std::size_t count, std::string const& label ); + + friend std::ostream& operator << ( std::ostream& os, pluralise const& pluraliser ); + + std::size_t m_count; + std::string m_label; + }; +} + +// end catch_string_manip.h +#ifndef CATCH_CONFIG_DISABLE_MATCHERS +// start catch_capture_matchers.h + +// start catch_matchers.h + +#include +#include + +namespace Catch { +namespace Matchers { + namespace Impl { + + template struct MatchAllOf; + template struct MatchAnyOf; + template struct MatchNotOf; + + class MatcherUntypedBase { + public: + MatcherUntypedBase() = default; + MatcherUntypedBase ( MatcherUntypedBase const& ) = default; + MatcherUntypedBase& operator = ( MatcherUntypedBase const& ) = delete; + std::string toString() const; + + protected: + virtual ~MatcherUntypedBase(); + virtual std::string describe() const = 0; + mutable std::string m_cachedToString; + }; + +#ifdef __clang__ +# pragma clang diagnostic push +# pragma clang diagnostic ignored "-Wnon-virtual-dtor" +#endif + + template + struct MatcherMethod { + virtual bool match( ObjectT const& arg ) const = 0; + }; + +#ifdef __clang__ +# pragma clang diagnostic pop +#endif + + template + struct MatcherBase : MatcherUntypedBase, MatcherMethod { + + MatchAllOf operator && ( MatcherBase const& other ) const; + MatchAnyOf operator || ( MatcherBase const& other ) const; + MatchNotOf operator ! () const; + }; + + template + struct MatchAllOf : MatcherBase { + bool match( ArgT const& arg ) const override { + for( auto matcher : m_matchers ) { + if (!matcher->match(arg)) + return false; + } + return true; + } + std::string describe() const override { + std::string description; + description.reserve( 4 + m_matchers.size()*32 ); + description += "( "; + bool first = true; + for( auto matcher : m_matchers ) { + if( first ) + first = false; + else + description += " and "; + description += matcher->toString(); + } + description += " )"; + return description; + } + + MatchAllOf& operator && ( MatcherBase const& other ) { + m_matchers.push_back( &other ); + return *this; + } + + std::vector const*> m_matchers; + }; + template + struct MatchAnyOf : MatcherBase { + + bool match( ArgT const& arg ) const override { + for( auto matcher : m_matchers ) { + if (matcher->match(arg)) + return true; + } + return false; + } + std::string describe() const override { + std::string description; + description.reserve( 4 + m_matchers.size()*32 ); + description += "( "; + bool first = true; + for( auto matcher : m_matchers ) { + if( first ) + first = false; + else + description += " or "; + description += matcher->toString(); + } + description += " )"; + return description; + } + + MatchAnyOf& operator || ( MatcherBase const& other ) { + m_matchers.push_back( &other ); + return *this; + } + + std::vector const*> m_matchers; + }; + + template + struct MatchNotOf : MatcherBase { + + MatchNotOf( MatcherBase const& underlyingMatcher ) : m_underlyingMatcher( underlyingMatcher ) {} + + bool match( ArgT const& arg ) const override { + return !m_underlyingMatcher.match( arg ); + } + + std::string describe() const override { + return "not " + m_underlyingMatcher.toString(); + } + MatcherBase const& m_underlyingMatcher; + }; + + template + MatchAllOf MatcherBase::operator && ( MatcherBase const& other ) const { + return MatchAllOf() && *this && other; + } + template + MatchAnyOf MatcherBase::operator || ( MatcherBase const& other ) const { + return MatchAnyOf() || *this || other; + } + template + MatchNotOf MatcherBase::operator ! () const { + return MatchNotOf( *this ); + } + + } // namespace Impl + +} // namespace Matchers + +using namespace Matchers; +using Matchers::Impl::MatcherBase; + +} // namespace Catch + +// end catch_matchers.h +// start catch_matchers_floating.h + +#include +#include + +namespace Catch { +namespace Matchers { + + namespace Floating { + + enum class FloatingPointKind : uint8_t; + + struct WithinAbsMatcher : MatcherBase { + WithinAbsMatcher(double target, double margin); + bool match(double const& matchee) const override; + std::string describe() const override; + private: + double m_target; + double m_margin; + }; + + struct WithinUlpsMatcher : MatcherBase { + WithinUlpsMatcher(double target, int ulps, FloatingPointKind baseType); + bool match(double const& matchee) const override; + std::string describe() const override; + private: + double m_target; + int m_ulps; + FloatingPointKind m_type; + }; + + } // namespace Floating + + // The following functions create the actual matcher objects. + // This allows the types to be inferred + Floating::WithinUlpsMatcher WithinULP(double target, int maxUlpDiff); + Floating::WithinUlpsMatcher WithinULP(float target, int maxUlpDiff); + Floating::WithinAbsMatcher WithinAbs(double target, double margin); + +} // namespace Matchers +} // namespace Catch + +// end catch_matchers_floating.h +// start catch_matchers_generic.hpp + +#include +#include + +namespace Catch { +namespace Matchers { +namespace Generic { + +namespace Detail { + std::string finalizeDescription(const std::string& desc); +} + +template +class PredicateMatcher : public MatcherBase { + std::function m_predicate; + std::string m_description; +public: + + PredicateMatcher(std::function const& elem, std::string const& descr) + :m_predicate(std::move(elem)), + m_description(Detail::finalizeDescription(descr)) + {} + + bool match( T const& item ) const override { + return m_predicate(item); + } + + std::string describe() const override { + return m_description; + } +}; + +} // namespace Generic + + // The following functions create the actual matcher objects. + // The user has to explicitly specify type to the function, because + // infering std::function is hard (but possible) and + // requires a lot of TMP. + template + Generic::PredicateMatcher Predicate(std::function const& predicate, std::string const& description = "") { + return Generic::PredicateMatcher(predicate, description); + } + +} // namespace Matchers +} // namespace Catch + +// end catch_matchers_generic.hpp +// start catch_matchers_string.h + +#include + +namespace Catch { +namespace Matchers { + + namespace StdString { + + struct CasedString + { + CasedString( std::string const& str, CaseSensitive::Choice caseSensitivity ); + std::string adjustString( std::string const& str ) const; + std::string caseSensitivitySuffix() const; + + CaseSensitive::Choice m_caseSensitivity; + std::string m_str; + }; + + struct StringMatcherBase : MatcherBase { + StringMatcherBase( std::string const& operation, CasedString const& comparator ); + std::string describe() const override; + + CasedString m_comparator; + std::string m_operation; + }; + + struct EqualsMatcher : StringMatcherBase { + EqualsMatcher( CasedString const& comparator ); + bool match( std::string const& source ) const override; + }; + struct ContainsMatcher : StringMatcherBase { + ContainsMatcher( CasedString const& comparator ); + bool match( std::string const& source ) const override; + }; + struct StartsWithMatcher : StringMatcherBase { + StartsWithMatcher( CasedString const& comparator ); + bool match( std::string const& source ) const override; + }; + struct EndsWithMatcher : StringMatcherBase { + EndsWithMatcher( CasedString const& comparator ); + bool match( std::string const& source ) const override; + }; + + struct RegexMatcher : MatcherBase { + RegexMatcher( std::string regex, CaseSensitive::Choice caseSensitivity ); + bool match( std::string const& matchee ) const override; + std::string describe() const override; + + private: + std::string m_regex; + CaseSensitive::Choice m_caseSensitivity; + }; + + } // namespace StdString + + // The following functions create the actual matcher objects. + // This allows the types to be inferred + + StdString::EqualsMatcher Equals( std::string const& str, CaseSensitive::Choice caseSensitivity = CaseSensitive::Yes ); + StdString::ContainsMatcher Contains( std::string const& str, CaseSensitive::Choice caseSensitivity = CaseSensitive::Yes ); + StdString::EndsWithMatcher EndsWith( std::string const& str, CaseSensitive::Choice caseSensitivity = CaseSensitive::Yes ); + StdString::StartsWithMatcher StartsWith( std::string const& str, CaseSensitive::Choice caseSensitivity = CaseSensitive::Yes ); + StdString::RegexMatcher Matches( std::string const& regex, CaseSensitive::Choice caseSensitivity = CaseSensitive::Yes ); + +} // namespace Matchers +} // namespace Catch + +// end catch_matchers_string.h +// start catch_matchers_vector.h + +#include + +namespace Catch { +namespace Matchers { + + namespace Vector { + namespace Detail { + template + size_t count(InputIterator first, InputIterator last, T const& item) { + size_t cnt = 0; + for (; first != last; ++first) { + if (*first == item) { + ++cnt; + } + } + return cnt; + } + template + bool contains(InputIterator first, InputIterator last, T const& item) { + for (; first != last; ++first) { + if (*first == item) { + return true; + } + } + return false; + } + } + + template + struct ContainsElementMatcher : MatcherBase> { + + ContainsElementMatcher(T const &comparator) : m_comparator( comparator) {} + + bool match(std::vector const &v) const override { + for (auto const& el : v) { + if (el == m_comparator) { + return true; + } + } + return false; + } + + std::string describe() const override { + return "Contains: " + ::Catch::Detail::stringify( m_comparator ); + } + + T const& m_comparator; + }; + + template + struct ContainsMatcher : MatcherBase> { + + ContainsMatcher(std::vector const &comparator) : m_comparator( comparator ) {} + + bool match(std::vector const &v) const override { + // !TBD: see note in EqualsMatcher + if (m_comparator.size() > v.size()) + return false; + for (auto const& comparator : m_comparator) { + auto present = false; + for (const auto& el : v) { + if (el == comparator) { + present = true; + break; + } + } + if (!present) { + return false; + } + } + return true; + } + std::string describe() const override { + return "Contains: " + ::Catch::Detail::stringify( m_comparator ); + } + + std::vector const& m_comparator; + }; + + template + struct EqualsMatcher : MatcherBase> { + + EqualsMatcher(std::vector const &comparator) : m_comparator( comparator ) {} + + bool match(std::vector const &v) const override { + // !TBD: This currently works if all elements can be compared using != + // - a more general approach would be via a compare template that defaults + // to using !=. but could be specialised for, e.g. std::vector etc + // - then just call that directly + if (m_comparator.size() != v.size()) + return false; + for (std::size_t i = 0; i < v.size(); ++i) + if (m_comparator[i] != v[i]) + return false; + return true; + } + std::string describe() const override { + return "Equals: " + ::Catch::Detail::stringify( m_comparator ); + } + std::vector const& m_comparator; + }; + + template + struct UnorderedEqualsMatcher : MatcherBase> { + UnorderedEqualsMatcher(std::vector const& target) : m_target(target) {} + bool match(std::vector const& vec) const override { + // Note: This is a reimplementation of std::is_permutation, + // because I don't want to include inside the common path + if (m_target.size() != vec.size()) { + return false; + } + auto lfirst = m_target.begin(), llast = m_target.end(); + auto rfirst = vec.begin(), rlast = vec.end(); + // Cut common prefix to optimize checking of permuted parts + while (lfirst != llast && *lfirst == *rfirst) { + ++lfirst; ++rfirst; + } + if (lfirst == llast) { + return true; + } + + for (auto mid = lfirst; mid != llast; ++mid) { + // Skip already counted items + if (Detail::contains(lfirst, mid, *mid)) { + continue; + } + size_t num_vec = Detail::count(rfirst, rlast, *mid); + if (num_vec == 0 || Detail::count(lfirst, llast, *mid) != num_vec) { + return false; + } + } + + return true; + } + + std::string describe() const override { + return "UnorderedEquals: " + ::Catch::Detail::stringify(m_target); + } + private: + std::vector const& m_target; + }; + + } // namespace Vector + + // The following functions create the actual matcher objects. + // This allows the types to be inferred + + template + Vector::ContainsMatcher Contains( std::vector const& comparator ) { + return Vector::ContainsMatcher( comparator ); + } + + template + Vector::ContainsElementMatcher VectorContains( T const& comparator ) { + return Vector::ContainsElementMatcher( comparator ); + } + + template + Vector::EqualsMatcher Equals( std::vector const& comparator ) { + return Vector::EqualsMatcher( comparator ); + } + + template + Vector::UnorderedEqualsMatcher UnorderedEquals(std::vector const& target) { + return Vector::UnorderedEqualsMatcher(target); + } + +} // namespace Matchers +} // namespace Catch + +// end catch_matchers_vector.h +namespace Catch { + + template + class MatchExpr : public ITransientExpression { + ArgT const& m_arg; + MatcherT m_matcher; + StringRef m_matcherString; + public: + MatchExpr( ArgT const& arg, MatcherT const& matcher, StringRef const& matcherString ) + : ITransientExpression{ true, matcher.match( arg ) }, + m_arg( arg ), + m_matcher( matcher ), + m_matcherString( matcherString ) + {} + + void streamReconstructedExpression( std::ostream &os ) const override { + auto matcherAsString = m_matcher.toString(); + os << Catch::Detail::stringify( m_arg ) << ' '; + if( matcherAsString == Detail::unprintableString ) + os << m_matcherString; + else + os << matcherAsString; + } + }; + + using StringMatcher = Matchers::Impl::MatcherBase; + + void handleExceptionMatchExpr( AssertionHandler& handler, StringMatcher const& matcher, StringRef const& matcherString ); + + template + auto makeMatchExpr( ArgT const& arg, MatcherT const& matcher, StringRef const& matcherString ) -> MatchExpr { + return MatchExpr( arg, matcher, matcherString ); + } + +} // namespace Catch + +/////////////////////////////////////////////////////////////////////////////// +#define INTERNAL_CHECK_THAT( macroName, matcher, resultDisposition, arg ) \ + do { \ + Catch::AssertionHandler catchAssertionHandler( macroName##_catch_sr, CATCH_INTERNAL_LINEINFO, CATCH_INTERNAL_STRINGIFY(arg) ", " CATCH_INTERNAL_STRINGIFY(matcher), resultDisposition ); \ + INTERNAL_CATCH_TRY { \ + catchAssertionHandler.handleExpr( Catch::makeMatchExpr( arg, matcher, #matcher##_catch_sr ) ); \ + } INTERNAL_CATCH_CATCH( catchAssertionHandler ) \ + INTERNAL_CATCH_REACT( catchAssertionHandler ) \ + } while( false ) + +/////////////////////////////////////////////////////////////////////////////// +#define INTERNAL_CATCH_THROWS_MATCHES( macroName, exceptionType, resultDisposition, matcher, ... ) \ + do { \ + Catch::AssertionHandler catchAssertionHandler( macroName##_catch_sr, CATCH_INTERNAL_LINEINFO, CATCH_INTERNAL_STRINGIFY(__VA_ARGS__) ", " CATCH_INTERNAL_STRINGIFY(exceptionType) ", " CATCH_INTERNAL_STRINGIFY(matcher), resultDisposition ); \ + if( catchAssertionHandler.allowThrows() ) \ + try { \ + static_cast(__VA_ARGS__ ); \ + catchAssertionHandler.handleUnexpectedExceptionNotThrown(); \ + } \ + catch( exceptionType const& ex ) { \ + catchAssertionHandler.handleExpr( Catch::makeMatchExpr( ex, matcher, #matcher##_catch_sr ) ); \ + } \ + catch( ... ) { \ + catchAssertionHandler.handleUnexpectedInflightException(); \ + } \ + else \ + catchAssertionHandler.handleThrowingCallSkipped(); \ + INTERNAL_CATCH_REACT( catchAssertionHandler ) \ + } while( false ) + +// end catch_capture_matchers.h +#endif +// start catch_generators.hpp + +// start catch_interfaces_generatortracker.h + + +#include + +namespace Catch { + + namespace Generators { + class GeneratorUntypedBase { + public: + GeneratorUntypedBase() = default; + virtual ~GeneratorUntypedBase(); + // Attempts to move the generator to the next element + // + // Returns true iff the move succeeded (and a valid element + // can be retrieved). + virtual bool next() = 0; + }; + using GeneratorBasePtr = std::unique_ptr; + + } // namespace Generators + + struct IGeneratorTracker { + virtual ~IGeneratorTracker(); + virtual auto hasGenerator() const -> bool = 0; + virtual auto getGenerator() const -> Generators::GeneratorBasePtr const& = 0; + virtual void setGenerator( Generators::GeneratorBasePtr&& generator ) = 0; + }; + +} // namespace Catch + +// end catch_interfaces_generatortracker.h +// start catch_enforce.h + +#include + +namespace Catch { +#if !defined(CATCH_CONFIG_DISABLE_EXCEPTIONS) + template + [[noreturn]] + void throw_exception(Ex const& e) { + throw e; + } +#else // ^^ Exceptions are enabled // Exceptions are disabled vv + [[noreturn]] + void throw_exception(std::exception const& e); +#endif +} // namespace Catch; + +#define CATCH_PREPARE_EXCEPTION( type, msg ) \ + type( ( Catch::ReusableStringStream() << msg ).str() ) +#define CATCH_INTERNAL_ERROR( msg ) \ + Catch::throw_exception(CATCH_PREPARE_EXCEPTION( std::logic_error, CATCH_INTERNAL_LINEINFO << ": Internal Catch error: " << msg)) +#define CATCH_ERROR( msg ) \ + Catch::throw_exception(CATCH_PREPARE_EXCEPTION( std::domain_error, msg )) +#define CATCH_RUNTIME_ERROR( msg ) \ + Catch::throw_exception(CATCH_PREPARE_EXCEPTION( std::runtime_error, msg )) +#define CATCH_ENFORCE( condition, msg ) \ + do{ if( !(condition) ) CATCH_ERROR( msg ); } while(false) + +// end catch_enforce.h +#include +#include +#include + +#include +#include + +namespace Catch { + +class GeneratorException : public std::exception { + const char* const m_msg = ""; + +public: + GeneratorException(const char* msg): + m_msg(msg) + {} + + const char* what() const noexcept override final; +}; + +namespace Generators { + + // !TBD move this into its own location? + namespace pf{ + template + std::unique_ptr make_unique( Args&&... args ) { + return std::unique_ptr(new T(std::forward(args)...)); + } + } + + template + struct IGenerator : GeneratorUntypedBase { + virtual ~IGenerator() = default; + + // Returns the current element of the generator + // + // \Precondition The generator is either freshly constructed, + // or the last call to `next()` returned true + virtual T const& get() const = 0; + using type = T; + }; + + template + class SingleValueGenerator final : public IGenerator { + T m_value; + public: + SingleValueGenerator(T const& value) : m_value( value ) {} + SingleValueGenerator(T&& value) : m_value(std::move(value)) {} + + T const& get() const override { + return m_value; + } + bool next() override { + return false; + } + }; + + template + class FixedValuesGenerator final : public IGenerator { + std::vector m_values; + size_t m_idx = 0; + public: + FixedValuesGenerator( std::initializer_list values ) : m_values( values ) {} + + T const& get() const override { + return m_values[m_idx]; + } + bool next() override { + ++m_idx; + return m_idx < m_values.size(); + } + }; + + template + class GeneratorWrapper final { + std::unique_ptr> m_generator; + public: + GeneratorWrapper(std::unique_ptr> generator): + m_generator(std::move(generator)) + {} + T const& get() const { + return m_generator->get(); + } + bool next() { + return m_generator->next(); + } + }; + + template + GeneratorWrapper value(T&& value) { + return GeneratorWrapper(pf::make_unique>(std::forward(value))); + } + template + GeneratorWrapper values(std::initializer_list values) { + return GeneratorWrapper(pf::make_unique>(values)); + } + + template + class Generators : public IGenerator { + std::vector> m_generators; + size_t m_current = 0; + + void populate(GeneratorWrapper&& generator) { + m_generators.emplace_back(std::move(generator)); + } + void populate(T&& val) { + m_generators.emplace_back(value(std::move(val))); + } + template + void populate(U&& val) { + populate(T(std::move(val))); + } + template + void populate(U&& valueOrGenerator, Gs... moreGenerators) { + populate(std::forward(valueOrGenerator)); + populate(std::forward(moreGenerators)...); + } + + public: + template + Generators(Gs... moreGenerators) { + m_generators.reserve(sizeof...(Gs)); + populate(std::forward(moreGenerators)...); + } + + T const& get() const override { + return m_generators[m_current].get(); + } + + bool next() override { + if (m_current >= m_generators.size()) { + return false; + } + const bool current_status = m_generators[m_current].next(); + if (!current_status) { + ++m_current; + } + return m_current < m_generators.size(); + } + }; + + template + GeneratorWrapper> table( std::initializer_list::type...>> tuples ) { + return values>( tuples ); + } + + // Tag type to signal that a generator sequence should convert arguments to a specific type + template + struct as {}; + + template + auto makeGenerators( GeneratorWrapper&& generator, Gs... moreGenerators ) -> Generators { + return Generators(std::move(generator), std::forward(moreGenerators)...); + } + template + auto makeGenerators( GeneratorWrapper&& generator ) -> Generators { + return Generators(std::move(generator)); + } + template + auto makeGenerators( T&& val, Gs... moreGenerators ) -> Generators { + return makeGenerators( value( std::forward( val ) ), std::forward( moreGenerators )... ); + } + template + auto makeGenerators( as, U&& val, Gs... moreGenerators ) -> Generators { + return makeGenerators( value( T( std::forward( val ) ) ), std::forward( moreGenerators )... ); + } + + auto acquireGeneratorTracker( SourceLineInfo const& lineInfo ) -> IGeneratorTracker&; + + template + // Note: The type after -> is weird, because VS2015 cannot parse + // the expression used in the typedef inside, when it is in + // return type. Yeah. + auto generate( SourceLineInfo const& lineInfo, L const& generatorExpression ) -> decltype(std::declval().get()) { + using UnderlyingType = typename decltype(generatorExpression())::type; + + IGeneratorTracker& tracker = acquireGeneratorTracker( lineInfo ); + if (!tracker.hasGenerator()) { + tracker.setGenerator(pf::make_unique>(generatorExpression())); + } + + auto const& generator = static_cast const&>( *tracker.getGenerator() ); + return generator.get(); + } + +} // namespace Generators +} // namespace Catch + +#define GENERATE( ... ) \ + Catch::Generators::generate( CATCH_INTERNAL_LINEINFO, []{ using namespace Catch::Generators; return makeGenerators( __VA_ARGS__ ); } ) + +// end catch_generators.hpp +// start catch_generators_generic.hpp + +namespace Catch { +namespace Generators { + + template + class TakeGenerator : public IGenerator { + GeneratorWrapper m_generator; + size_t m_returned = 0; + size_t m_target; + public: + TakeGenerator(size_t target, GeneratorWrapper&& generator): + m_generator(std::move(generator)), + m_target(target) + { + assert(target != 0 && "Empty generators are not allowed"); + } + T const& get() const override { + return m_generator.get(); + } + bool next() override { + ++m_returned; + if (m_returned >= m_target) { + return false; + } + + const auto success = m_generator.next(); + // If the underlying generator does not contain enough values + // then we cut short as well + if (!success) { + m_returned = m_target; + } + return success; + } + }; + + template + GeneratorWrapper take(size_t target, GeneratorWrapper&& generator) { + return GeneratorWrapper(pf::make_unique>(target, std::move(generator))); + } + + template + class FilterGenerator : public IGenerator { + GeneratorWrapper m_generator; + Predicate m_predicate; + public: + template + FilterGenerator(P&& pred, GeneratorWrapper&& generator): + m_generator(std::move(generator)), + m_predicate(std::forward

(pred)) + { + if (!m_predicate(m_generator.get())) { + // It might happen that there are no values that pass the + // filter. In that case we throw an exception. + auto has_initial_value = next(); + if (!has_initial_value) { + Catch::throw_exception(GeneratorException("No valid value found in filtered generator")); + } + } + } + + T const& get() const override { + return m_generator.get(); + } + + bool next() override { + bool success = m_generator.next(); + if (!success) { + return false; + } + while (!m_predicate(m_generator.get()) && (success = m_generator.next()) == true); + return success; + } + }; + + template + GeneratorWrapper filter(Predicate&& pred, GeneratorWrapper&& generator) { + return GeneratorWrapper(std::unique_ptr>(pf::make_unique>(std::forward(pred), std::move(generator)))); + } + + template + class RepeatGenerator : public IGenerator { + GeneratorWrapper m_generator; + mutable std::vector m_returned; + size_t m_target_repeats; + size_t m_current_repeat = 0; + size_t m_repeat_index = 0; + public: + RepeatGenerator(size_t repeats, GeneratorWrapper&& generator): + m_generator(std::move(generator)), + m_target_repeats(repeats) + { + assert(m_target_repeats > 0 && "Repeat generator must repeat at least once"); + } + + T const& get() const override { + if (m_current_repeat == 0) { + m_returned.push_back(m_generator.get()); + return m_returned.back(); + } + return m_returned[m_repeat_index]; + } + + bool next() override { + // There are 2 basic cases: + // 1) We are still reading the generator + // 2) We are reading our own cache + + // In the first case, we need to poke the underlying generator. + // If it happily moves, we are left in that state, otherwise it is time to start reading from our cache + if (m_current_repeat == 0) { + const auto success = m_generator.next(); + if (!success) { + ++m_current_repeat; + } + return m_current_repeat < m_target_repeats; + } + + // In the second case, we need to move indices forward and check that we haven't run up against the end + ++m_repeat_index; + if (m_repeat_index == m_returned.size()) { + m_repeat_index = 0; + ++m_current_repeat; + } + return m_current_repeat < m_target_repeats; + } + }; + + template + GeneratorWrapper repeat(size_t repeats, GeneratorWrapper&& generator) { + return GeneratorWrapper(pf::make_unique>(repeats, std::move(generator))); + } + + template + class MapGenerator : public IGenerator { + // TBD: provide static assert for mapping function, for friendly error message + GeneratorWrapper m_generator; + Func m_function; + // To avoid returning dangling reference, we have to save the values + T m_cache; + public: + template + MapGenerator(F2&& function, GeneratorWrapper&& generator) : + m_generator(std::move(generator)), + m_function(std::forward(function)), + m_cache(m_function(m_generator.get())) + {} + + T const& get() const override { + return m_cache; + } + bool next() override { + const auto success = m_generator.next(); + if (success) { + m_cache = m_function(m_generator.get()); + } + return success; + } + }; + + template + GeneratorWrapper map(Func&& function, GeneratorWrapper&& generator) { + return GeneratorWrapper( + pf::make_unique>(std::forward(function), std::move(generator)) + ); + } + template + GeneratorWrapper map(Func&& function, GeneratorWrapper&& generator) { + return GeneratorWrapper( + pf::make_unique>(std::forward(function), std::move(generator)) + ); + } + + template + class ChunkGenerator final : public IGenerator> { + std::vector m_chunk; + size_t m_chunk_size; + GeneratorWrapper m_generator; + bool m_used_up = false; + public: + ChunkGenerator(size_t size, GeneratorWrapper generator) : + m_chunk_size(size), m_generator(std::move(generator)) + { + m_chunk.reserve(m_chunk_size); + m_chunk.push_back(m_generator.get()); + for (size_t i = 1; i < m_chunk_size; ++i) { + if (!m_generator.next()) { + Catch::throw_exception(GeneratorException("Not enough values to initialize the first chunk")); + } + m_chunk.push_back(m_generator.get()); + } + } + std::vector const& get() const override { + return m_chunk; + } + bool next() override { + m_chunk.clear(); + for (size_t idx = 0; idx < m_chunk_size; ++idx) { + if (!m_generator.next()) { + return false; + } + m_chunk.push_back(m_generator.get()); + } + return true; + } + }; + + template + GeneratorWrapper> chunk(size_t size, GeneratorWrapper&& generator) { + return GeneratorWrapper>( + pf::make_unique>(size, std::move(generator)) + ); + } + +} // namespace Generators +} // namespace Catch + +// end catch_generators_generic.hpp +// start catch_generators_specific.hpp + +// start catch_context.h + +#include + +namespace Catch { + + struct IResultCapture; + struct IRunner; + struct IConfig; + struct IMutableContext; + + using IConfigPtr = std::shared_ptr; + + struct IContext + { + virtual ~IContext(); + + virtual IResultCapture* getResultCapture() = 0; + virtual IRunner* getRunner() = 0; + virtual IConfigPtr const& getConfig() const = 0; + }; + + struct IMutableContext : IContext + { + virtual ~IMutableContext(); + virtual void setResultCapture( IResultCapture* resultCapture ) = 0; + virtual void setRunner( IRunner* runner ) = 0; + virtual void setConfig( IConfigPtr const& config ) = 0; + + private: + static IMutableContext *currentContext; + friend IMutableContext& getCurrentMutableContext(); + friend void cleanUpContext(); + static void createContext(); + }; + + inline IMutableContext& getCurrentMutableContext() + { + if( !IMutableContext::currentContext ) + IMutableContext::createContext(); + return *IMutableContext::currentContext; + } + + inline IContext& getCurrentContext() + { + return getCurrentMutableContext(); + } + + void cleanUpContext(); +} + +// end catch_context.h +// start catch_interfaces_config.h + +#include +#include +#include +#include + +namespace Catch { + + enum class Verbosity { + Quiet = 0, + Normal, + High + }; + + struct WarnAbout { enum What { + Nothing = 0x00, + NoAssertions = 0x01, + NoTests = 0x02 + }; }; + + struct ShowDurations { enum OrNot { + DefaultForReporter, + Always, + Never + }; }; + struct RunTests { enum InWhatOrder { + InDeclarationOrder, + InLexicographicalOrder, + InRandomOrder + }; }; + struct UseColour { enum YesOrNo { + Auto, + Yes, + No + }; }; + struct WaitForKeypress { enum When { + Never, + BeforeStart = 1, + BeforeExit = 2, + BeforeStartAndExit = BeforeStart | BeforeExit + }; }; + + class TestSpec; + + struct IConfig : NonCopyable { + + virtual ~IConfig(); + + virtual bool allowThrows() const = 0; + virtual std::ostream& stream() const = 0; + virtual std::string name() const = 0; + virtual bool includeSuccessfulResults() const = 0; + virtual bool shouldDebugBreak() const = 0; + virtual bool warnAboutMissingAssertions() const = 0; + virtual bool warnAboutNoTests() const = 0; + virtual int abortAfter() const = 0; + virtual bool showInvisibles() const = 0; + virtual ShowDurations::OrNot showDurations() const = 0; + virtual TestSpec const& testSpec() const = 0; + virtual bool hasTestFilters() const = 0; + virtual RunTests::InWhatOrder runOrder() const = 0; + virtual unsigned int rngSeed() const = 0; + virtual int benchmarkResolutionMultiple() const = 0; + virtual UseColour::YesOrNo useColour() const = 0; + virtual std::vector const& getSectionsToRun() const = 0; + virtual Verbosity verbosity() const = 0; + }; + + using IConfigPtr = std::shared_ptr; +} + +// end catch_interfaces_config.h +#include + +namespace Catch { +namespace Generators { + +template +class RandomFloatingGenerator final : public IGenerator { + // FIXME: What is the right seed? + std::minstd_rand m_rand; + std::uniform_real_distribution m_dist; + Float m_current_number; +public: + + RandomFloatingGenerator(Float a, Float b): + m_rand(getCurrentContext().getConfig()->rngSeed()), + m_dist(a, b) { + static_cast(next()); + } + + Float const& get() const override { + return m_current_number; + } + bool next() override { + m_current_number = m_dist(m_rand); + return true; + } +}; + +template +class RandomIntegerGenerator final : public IGenerator { + std::minstd_rand m_rand; + std::uniform_int_distribution m_dist; + Integer m_current_number; +public: + + RandomIntegerGenerator(Integer a, Integer b): + m_rand(getCurrentContext().getConfig()->rngSeed()), + m_dist(a, b) { + static_cast(next()); + } + + Integer const& get() const override { + return m_current_number; + } + bool next() override { + m_current_number = m_dist(m_rand); + return true; + } +}; + +// TODO: Ideally this would be also constrained against the various char types, +// but I don't expect users to run into that in practice. +template +typename std::enable_if::value && !std::is_same::value, +GeneratorWrapper>::type +random(T a, T b) { + return GeneratorWrapper( + pf::make_unique>(a, b) + ); +} + +template +typename std::enable_if::value, +GeneratorWrapper>::type +random(T a, T b) { + return GeneratorWrapper( + pf::make_unique>(a, b) + ); +} + +template +class RangeGenerator final : public IGenerator { + T m_current; + T m_end; + T m_step; + bool m_positive; + +public: + RangeGenerator(T const& start, T const& end, T const& step): + m_current(start), + m_end(end), + m_step(step), + m_positive(m_step > T(0)) + { + assert(m_current != m_end && "Range start and end cannot be equal"); + assert(m_step != T(0) && "Step size cannot be zero"); + assert(((m_positive && m_current <= m_end) || (!m_positive && m_current >= m_end)) && "Step moves away from end"); + } + + RangeGenerator(T const& start, T const& end): + RangeGenerator(start, end, (start < end) ? T(1) : T(-1)) + {} + + T const& get() const override { + return m_current; + } + + bool next() override { + m_current += m_step; + return (m_positive) ? (m_current < m_end) : (m_current > m_end); + } +}; + +template +GeneratorWrapper range(T const& start, T const& end, T const& step) { + static_assert(std::is_integral::value && !std::is_same::value, "Type must be an integer"); + return GeneratorWrapper(pf::make_unique>(start, end, step)); +} + +template +GeneratorWrapper range(T const& start, T const& end) { + static_assert(std::is_integral::value && !std::is_same::value, "Type must be an integer"); + return GeneratorWrapper(pf::make_unique>(start, end)); +} + +} // namespace Generators +} // namespace Catch + +// end catch_generators_specific.hpp + +// These files are included here so the single_include script doesn't put them +// in the conditionally compiled sections +// start catch_test_case_info.h + +#include +#include +#include + +#ifdef __clang__ +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wpadded" +#endif + +namespace Catch { + + struct ITestInvoker; + + struct TestCaseInfo { + enum SpecialProperties{ + None = 0, + IsHidden = 1 << 1, + ShouldFail = 1 << 2, + MayFail = 1 << 3, + Throws = 1 << 4, + NonPortable = 1 << 5, + Benchmark = 1 << 6 + }; + + TestCaseInfo( std::string const& _name, + std::string const& _className, + std::string const& _description, + std::vector const& _tags, + SourceLineInfo const& _lineInfo ); + + friend void setTags( TestCaseInfo& testCaseInfo, std::vector tags ); + + bool isHidden() const; + bool throws() const; + bool okToFail() const; + bool expectedToFail() const; + + std::string tagsAsString() const; + + std::string name; + std::string className; + std::string description; + std::vector tags; + std::vector lcaseTags; + SourceLineInfo lineInfo; + SpecialProperties properties; + }; + + class TestCase : public TestCaseInfo { + public: + + TestCase( ITestInvoker* testCase, TestCaseInfo&& info ); + + TestCase withName( std::string const& _newName ) const; + + void invoke() const; + + TestCaseInfo const& getTestCaseInfo() const; + + bool operator == ( TestCase const& other ) const; + bool operator < ( TestCase const& other ) const; + + private: + std::shared_ptr test; + }; + + TestCase makeTestCase( ITestInvoker* testCase, + std::string const& className, + NameAndTags const& nameAndTags, + SourceLineInfo const& lineInfo ); +} + +#ifdef __clang__ +#pragma clang diagnostic pop +#endif + +// end catch_test_case_info.h +// start catch_interfaces_runner.h + +namespace Catch { + + struct IRunner { + virtual ~IRunner(); + virtual bool aborting() const = 0; + }; +} + +// end catch_interfaces_runner.h + +#ifdef __OBJC__ +// start catch_objc.hpp + +#import + +#include + +// NB. Any general catch headers included here must be included +// in catch.hpp first to make sure they are included by the single +// header for non obj-usage + +/////////////////////////////////////////////////////////////////////////////// +// This protocol is really only here for (self) documenting purposes, since +// all its methods are optional. +@protocol OcFixture + +@optional + +-(void) setUp; +-(void) tearDown; + +@end + +namespace Catch { + + class OcMethod : public ITestInvoker { + + public: + OcMethod( Class cls, SEL sel ) : m_cls( cls ), m_sel( sel ) {} + + virtual void invoke() const { + id obj = [[m_cls alloc] init]; + + performOptionalSelector( obj, @selector(setUp) ); + performOptionalSelector( obj, m_sel ); + performOptionalSelector( obj, @selector(tearDown) ); + + arcSafeRelease( obj ); + } + private: + virtual ~OcMethod() {} + + Class m_cls; + SEL m_sel; + }; + + namespace Detail{ + + inline std::string getAnnotation( Class cls, + std::string const& annotationName, + std::string const& testCaseName ) { + NSString* selStr = [[NSString alloc] initWithFormat:@"Catch_%s_%s", annotationName.c_str(), testCaseName.c_str()]; + SEL sel = NSSelectorFromString( selStr ); + arcSafeRelease( selStr ); + id value = performOptionalSelector( cls, sel ); + if( value ) + return [(NSString*)value UTF8String]; + return ""; + } + } + + inline std::size_t registerTestMethods() { + std::size_t noTestMethods = 0; + int noClasses = objc_getClassList( nullptr, 0 ); + + Class* classes = (CATCH_UNSAFE_UNRETAINED Class *)malloc( sizeof(Class) * noClasses); + objc_getClassList( classes, noClasses ); + + for( int c = 0; c < noClasses; c++ ) { + Class cls = classes[c]; + { + u_int count; + Method* methods = class_copyMethodList( cls, &count ); + for( u_int m = 0; m < count ; m++ ) { + SEL selector = method_getName(methods[m]); + std::string methodName = sel_getName(selector); + if( startsWith( methodName, "Catch_TestCase_" ) ) { + std::string testCaseName = methodName.substr( 15 ); + std::string name = Detail::getAnnotation( cls, "Name", testCaseName ); + std::string desc = Detail::getAnnotation( cls, "Description", testCaseName ); + const char* className = class_getName( cls ); + + getMutableRegistryHub().registerTest( makeTestCase( new OcMethod( cls, selector ), className, NameAndTags( name.c_str(), desc.c_str() ), SourceLineInfo("",0) ) ); + noTestMethods++; + } + } + free(methods); + } + } + return noTestMethods; + } + +#if !defined(CATCH_CONFIG_DISABLE_MATCHERS) + + namespace Matchers { + namespace Impl { + namespace NSStringMatchers { + + struct StringHolder : MatcherBase{ + StringHolder( NSString* substr ) : m_substr( [substr copy] ){} + StringHolder( StringHolder const& other ) : m_substr( [other.m_substr copy] ){} + StringHolder() { + arcSafeRelease( m_substr ); + } + + bool match( NSString* arg ) const override { + return false; + } + + NSString* CATCH_ARC_STRONG m_substr; + }; + + struct Equals : StringHolder { + Equals( NSString* substr ) : StringHolder( substr ){} + + bool match( NSString* str ) const override { + return (str != nil || m_substr == nil ) && + [str isEqualToString:m_substr]; + } + + std::string describe() const override { + return "equals string: " + Catch::Detail::stringify( m_substr ); + } + }; + + struct Contains : StringHolder { + Contains( NSString* substr ) : StringHolder( substr ){} + + bool match( NSString* str ) const { + return (str != nil || m_substr == nil ) && + [str rangeOfString:m_substr].location != NSNotFound; + } + + std::string describe() const override { + return "contains string: " + Catch::Detail::stringify( m_substr ); + } + }; + + struct StartsWith : StringHolder { + StartsWith( NSString* substr ) : StringHolder( substr ){} + + bool match( NSString* str ) const override { + return (str != nil || m_substr == nil ) && + [str rangeOfString:m_substr].location == 0; + } + + std::string describe() const override { + return "starts with: " + Catch::Detail::stringify( m_substr ); + } + }; + struct EndsWith : StringHolder { + EndsWith( NSString* substr ) : StringHolder( substr ){} + + bool match( NSString* str ) const override { + return (str != nil || m_substr == nil ) && + [str rangeOfString:m_substr].location == [str length] - [m_substr length]; + } + + std::string describe() const override { + return "ends with: " + Catch::Detail::stringify( m_substr ); + } + }; + + } // namespace NSStringMatchers + } // namespace Impl + + inline Impl::NSStringMatchers::Equals + Equals( NSString* substr ){ return Impl::NSStringMatchers::Equals( substr ); } + + inline Impl::NSStringMatchers::Contains + Contains( NSString* substr ){ return Impl::NSStringMatchers::Contains( substr ); } + + inline Impl::NSStringMatchers::StartsWith + StartsWith( NSString* substr ){ return Impl::NSStringMatchers::StartsWith( substr ); } + + inline Impl::NSStringMatchers::EndsWith + EndsWith( NSString* substr ){ return Impl::NSStringMatchers::EndsWith( substr ); } + + } // namespace Matchers + + using namespace Matchers; + +#endif // CATCH_CONFIG_DISABLE_MATCHERS + +} // namespace Catch + +/////////////////////////////////////////////////////////////////////////////// +#define OC_MAKE_UNIQUE_NAME( root, uniqueSuffix ) root##uniqueSuffix +#define OC_TEST_CASE2( name, desc, uniqueSuffix ) \ ++(NSString*) OC_MAKE_UNIQUE_NAME( Catch_Name_test_, uniqueSuffix ) \ +{ \ +return @ name; \ +} \ ++(NSString*) OC_MAKE_UNIQUE_NAME( Catch_Description_test_, uniqueSuffix ) \ +{ \ +return @ desc; \ +} \ +-(void) OC_MAKE_UNIQUE_NAME( Catch_TestCase_test_, uniqueSuffix ) + +#define OC_TEST_CASE( name, desc ) OC_TEST_CASE2( name, desc, __LINE__ ) + +// end catch_objc.hpp +#endif + +#ifdef CATCH_CONFIG_EXTERNAL_INTERFACES +// start catch_external_interfaces.h + +// start catch_reporter_bases.hpp + +// start catch_interfaces_reporter.h + +// start catch_config.hpp + +// start catch_test_spec_parser.h + +#ifdef __clang__ +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wpadded" +#endif + +// start catch_test_spec.h + +#ifdef __clang__ +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wpadded" +#endif + +// start catch_wildcard_pattern.h + +namespace Catch +{ + class WildcardPattern { + enum WildcardPosition { + NoWildcard = 0, + WildcardAtStart = 1, + WildcardAtEnd = 2, + WildcardAtBothEnds = WildcardAtStart | WildcardAtEnd + }; + + public: + + WildcardPattern( std::string const& pattern, CaseSensitive::Choice caseSensitivity ); + virtual ~WildcardPattern() = default; + virtual bool matches( std::string const& str ) const; + + private: + std::string adjustCase( std::string const& str ) const; + CaseSensitive::Choice m_caseSensitivity; + WildcardPosition m_wildcard = NoWildcard; + std::string m_pattern; + }; +} + +// end catch_wildcard_pattern.h +#include +#include +#include + +namespace Catch { + + class TestSpec { + struct Pattern { + virtual ~Pattern(); + virtual bool matches( TestCaseInfo const& testCase ) const = 0; + }; + using PatternPtr = std::shared_ptr; + + class NamePattern : public Pattern { + public: + NamePattern( std::string const& name ); + virtual ~NamePattern(); + virtual bool matches( TestCaseInfo const& testCase ) const override; + private: + WildcardPattern m_wildcardPattern; + }; + + class TagPattern : public Pattern { + public: + TagPattern( std::string const& tag ); + virtual ~TagPattern(); + virtual bool matches( TestCaseInfo const& testCase ) const override; + private: + std::string m_tag; + }; + + class ExcludedPattern : public Pattern { + public: + ExcludedPattern( PatternPtr const& underlyingPattern ); + virtual ~ExcludedPattern(); + virtual bool matches( TestCaseInfo const& testCase ) const override; + private: + PatternPtr m_underlyingPattern; + }; + + struct Filter { + std::vector m_patterns; + + bool matches( TestCaseInfo const& testCase ) const; + }; + + public: + bool hasFilters() const; + bool matches( TestCaseInfo const& testCase ) const; + + private: + std::vector m_filters; + + friend class TestSpecParser; + }; +} + +#ifdef __clang__ +#pragma clang diagnostic pop +#endif + +// end catch_test_spec.h +// start catch_interfaces_tag_alias_registry.h + +#include + +namespace Catch { + + struct TagAlias; + + struct ITagAliasRegistry { + virtual ~ITagAliasRegistry(); + // Nullptr if not present + virtual TagAlias const* find( std::string const& alias ) const = 0; + virtual std::string expandAliases( std::string const& unexpandedTestSpec ) const = 0; + + static ITagAliasRegistry const& get(); + }; + +} // end namespace Catch + +// end catch_interfaces_tag_alias_registry.h +namespace Catch { + + class TestSpecParser { + enum Mode{ None, Name, QuotedName, Tag, EscapedName }; + Mode m_mode = None; + bool m_exclusion = false; + std::size_t m_start = std::string::npos, m_pos = 0; + std::string m_arg; + std::vector m_escapeChars; + TestSpec::Filter m_currentFilter; + TestSpec m_testSpec; + ITagAliasRegistry const* m_tagAliases = nullptr; + + public: + TestSpecParser( ITagAliasRegistry const& tagAliases ); + + TestSpecParser& parse( std::string const& arg ); + TestSpec testSpec(); + + private: + void visitChar( char c ); + void startNewMode( Mode mode, std::size_t start ); + void escape(); + std::string subString() const; + + template + void addPattern() { + std::string token = subString(); + for( std::size_t i = 0; i < m_escapeChars.size(); ++i ) + token = token.substr( 0, m_escapeChars[i]-m_start-i ) + token.substr( m_escapeChars[i]-m_start-i+1 ); + m_escapeChars.clear(); + if( startsWith( token, "exclude:" ) ) { + m_exclusion = true; + token = token.substr( 8 ); + } + if( !token.empty() ) { + TestSpec::PatternPtr pattern = std::make_shared( token ); + if( m_exclusion ) + pattern = std::make_shared( pattern ); + m_currentFilter.m_patterns.push_back( pattern ); + } + m_exclusion = false; + m_mode = None; + } + + void addFilter(); + }; + TestSpec parseTestSpec( std::string const& arg ); + +} // namespace Catch + +#ifdef __clang__ +#pragma clang diagnostic pop +#endif + +// end catch_test_spec_parser.h +// Libstdc++ doesn't like incomplete classes for unique_ptr + +#include +#include +#include + +#ifndef CATCH_CONFIG_CONSOLE_WIDTH +#define CATCH_CONFIG_CONSOLE_WIDTH 80 +#endif + +namespace Catch { + + struct IStream; + + struct ConfigData { + bool listTests = false; + bool listTags = false; + bool listReporters = false; + bool listTestNamesOnly = false; + + bool showSuccessfulTests = false; + bool shouldDebugBreak = false; + bool noThrow = false; + bool showHelp = false; + bool showInvisibles = false; + bool filenamesAsTags = false; + bool libIdentify = false; + + int abortAfter = -1; + unsigned int rngSeed = 0; + int benchmarkResolutionMultiple = 100; + + Verbosity verbosity = Verbosity::Normal; + WarnAbout::What warnings = WarnAbout::Nothing; + ShowDurations::OrNot showDurations = ShowDurations::DefaultForReporter; + RunTests::InWhatOrder runOrder = RunTests::InDeclarationOrder; + UseColour::YesOrNo useColour = UseColour::Auto; + WaitForKeypress::When waitForKeypress = WaitForKeypress::Never; + + std::string outputFilename; + std::string name; + std::string processName; +#ifndef CATCH_CONFIG_DEFAULT_REPORTER +#define CATCH_CONFIG_DEFAULT_REPORTER "console" +#endif + std::string reporterName = CATCH_CONFIG_DEFAULT_REPORTER; +#undef CATCH_CONFIG_DEFAULT_REPORTER + + std::vector testsOrTags; + std::vector sectionsToRun; + }; + + class Config : public IConfig { + public: + + Config() = default; + Config( ConfigData const& data ); + virtual ~Config() = default; + + std::string const& getFilename() const; + + bool listTests() const; + bool listTestNamesOnly() const; + bool listTags() const; + bool listReporters() const; + + std::string getProcessName() const; + std::string const& getReporterName() const; + + std::vector const& getTestsOrTags() const; + std::vector const& getSectionsToRun() const override; + + virtual TestSpec const& testSpec() const override; + bool hasTestFilters() const override; + + bool showHelp() const; + + // IConfig interface + bool allowThrows() const override; + std::ostream& stream() const override; + std::string name() const override; + bool includeSuccessfulResults() const override; + bool warnAboutMissingAssertions() const override; + bool warnAboutNoTests() const override; + ShowDurations::OrNot showDurations() const override; + RunTests::InWhatOrder runOrder() const override; + unsigned int rngSeed() const override; + int benchmarkResolutionMultiple() const override; + UseColour::YesOrNo useColour() const override; + bool shouldDebugBreak() const override; + int abortAfter() const override; + bool showInvisibles() const override; + Verbosity verbosity() const override; + + private: + + IStream const* openStream(); + ConfigData m_data; + + std::unique_ptr m_stream; + TestSpec m_testSpec; + bool m_hasTestFilters = false; + }; + +} // end namespace Catch + +// end catch_config.hpp +// start catch_assertionresult.h + +#include + +namespace Catch { + + struct AssertionResultData + { + AssertionResultData() = delete; + + AssertionResultData( ResultWas::OfType _resultType, LazyExpression const& _lazyExpression ); + + std::string message; + mutable std::string reconstructedExpression; + LazyExpression lazyExpression; + ResultWas::OfType resultType; + + std::string reconstructExpression() const; + }; + + class AssertionResult { + public: + AssertionResult() = delete; + AssertionResult( AssertionInfo const& info, AssertionResultData const& data ); + + bool isOk() const; + bool succeeded() const; + ResultWas::OfType getResultType() const; + bool hasExpression() const; + bool hasMessage() const; + std::string getExpression() const; + std::string getExpressionInMacro() const; + bool hasExpandedExpression() const; + std::string getExpandedExpression() const; + std::string getMessage() const; + SourceLineInfo getSourceInfo() const; + StringRef getTestMacroName() const; + + //protected: + AssertionInfo m_info; + AssertionResultData m_resultData; + }; + +} // end namespace Catch + +// end catch_assertionresult.h +// start catch_option.hpp + +namespace Catch { + + // An optional type + template + class Option { + public: + Option() : nullableValue( nullptr ) {} + Option( T const& _value ) + : nullableValue( new( storage ) T( _value ) ) + {} + Option( Option const& _other ) + : nullableValue( _other ? new( storage ) T( *_other ) : nullptr ) + {} + + ~Option() { + reset(); + } + + Option& operator= ( Option const& _other ) { + if( &_other != this ) { + reset(); + if( _other ) + nullableValue = new( storage ) T( *_other ); + } + return *this; + } + Option& operator = ( T const& _value ) { + reset(); + nullableValue = new( storage ) T( _value ); + return *this; + } + + void reset() { + if( nullableValue ) + nullableValue->~T(); + nullableValue = nullptr; + } + + T& operator*() { return *nullableValue; } + T const& operator*() const { return *nullableValue; } + T* operator->() { return nullableValue; } + const T* operator->() const { return nullableValue; } + + T valueOr( T const& defaultValue ) const { + return nullableValue ? *nullableValue : defaultValue; + } + + bool some() const { return nullableValue != nullptr; } + bool none() const { return nullableValue == nullptr; } + + bool operator !() const { return nullableValue == nullptr; } + explicit operator bool() const { + return some(); + } + + private: + T *nullableValue; + alignas(alignof(T)) char storage[sizeof(T)]; + }; + +} // end namespace Catch + +// end catch_option.hpp +#include +#include +#include +#include +#include + +namespace Catch { + + struct ReporterConfig { + explicit ReporterConfig( IConfigPtr const& _fullConfig ); + + ReporterConfig( IConfigPtr const& _fullConfig, std::ostream& _stream ); + + std::ostream& stream() const; + IConfigPtr fullConfig() const; + + private: + std::ostream* m_stream; + IConfigPtr m_fullConfig; + }; + + struct ReporterPreferences { + bool shouldRedirectStdOut = false; + bool shouldReportAllAssertions = false; + }; + + template + struct LazyStat : Option { + LazyStat& operator=( T const& _value ) { + Option::operator=( _value ); + used = false; + return *this; + } + void reset() { + Option::reset(); + used = false; + } + bool used = false; + }; + + struct TestRunInfo { + TestRunInfo( std::string const& _name ); + std::string name; + }; + struct GroupInfo { + GroupInfo( std::string const& _name, + std::size_t _groupIndex, + std::size_t _groupsCount ); + + std::string name; + std::size_t groupIndex; + std::size_t groupsCounts; + }; + + struct AssertionStats { + AssertionStats( AssertionResult const& _assertionResult, + std::vector const& _infoMessages, + Totals const& _totals ); + + AssertionStats( AssertionStats const& ) = default; + AssertionStats( AssertionStats && ) = default; + AssertionStats& operator = ( AssertionStats const& ) = delete; + AssertionStats& operator = ( AssertionStats && ) = delete; + virtual ~AssertionStats(); + + AssertionResult assertionResult; + std::vector infoMessages; + Totals totals; + }; + + struct SectionStats { + SectionStats( SectionInfo const& _sectionInfo, + Counts const& _assertions, + double _durationInSeconds, + bool _missingAssertions ); + SectionStats( SectionStats const& ) = default; + SectionStats( SectionStats && ) = default; + SectionStats& operator = ( SectionStats const& ) = default; + SectionStats& operator = ( SectionStats && ) = default; + virtual ~SectionStats(); + + SectionInfo sectionInfo; + Counts assertions; + double durationInSeconds; + bool missingAssertions; + }; + + struct TestCaseStats { + TestCaseStats( TestCaseInfo const& _testInfo, + Totals const& _totals, + std::string const& _stdOut, + std::string const& _stdErr, + bool _aborting ); + + TestCaseStats( TestCaseStats const& ) = default; + TestCaseStats( TestCaseStats && ) = default; + TestCaseStats& operator = ( TestCaseStats const& ) = default; + TestCaseStats& operator = ( TestCaseStats && ) = default; + virtual ~TestCaseStats(); + + TestCaseInfo testInfo; + Totals totals; + std::string stdOut; + std::string stdErr; + bool aborting; + }; + + struct TestGroupStats { + TestGroupStats( GroupInfo const& _groupInfo, + Totals const& _totals, + bool _aborting ); + TestGroupStats( GroupInfo const& _groupInfo ); + + TestGroupStats( TestGroupStats const& ) = default; + TestGroupStats( TestGroupStats && ) = default; + TestGroupStats& operator = ( TestGroupStats const& ) = default; + TestGroupStats& operator = ( TestGroupStats && ) = default; + virtual ~TestGroupStats(); + + GroupInfo groupInfo; + Totals totals; + bool aborting; + }; + + struct TestRunStats { + TestRunStats( TestRunInfo const& _runInfo, + Totals const& _totals, + bool _aborting ); + + TestRunStats( TestRunStats const& ) = default; + TestRunStats( TestRunStats && ) = default; + TestRunStats& operator = ( TestRunStats const& ) = default; + TestRunStats& operator = ( TestRunStats && ) = default; + virtual ~TestRunStats(); + + TestRunInfo runInfo; + Totals totals; + bool aborting; + }; + + struct BenchmarkInfo { + std::string name; + }; + struct BenchmarkStats { + BenchmarkInfo info; + std::size_t iterations; + uint64_t elapsedTimeInNanoseconds; + }; + + struct IStreamingReporter { + virtual ~IStreamingReporter() = default; + + // Implementing class must also provide the following static methods: + // static std::string getDescription(); + // static std::set getSupportedVerbosities() + + virtual ReporterPreferences getPreferences() const = 0; + + virtual void noMatchingTestCases( std::string const& spec ) = 0; + + virtual void testRunStarting( TestRunInfo const& testRunInfo ) = 0; + virtual void testGroupStarting( GroupInfo const& groupInfo ) = 0; + + virtual void testCaseStarting( TestCaseInfo const& testInfo ) = 0; + virtual void sectionStarting( SectionInfo const& sectionInfo ) = 0; + + // *** experimental *** + virtual void benchmarkStarting( BenchmarkInfo const& ) {} + + virtual void assertionStarting( AssertionInfo const& assertionInfo ) = 0; + + // The return value indicates if the messages buffer should be cleared: + virtual bool assertionEnded( AssertionStats const& assertionStats ) = 0; + + // *** experimental *** + virtual void benchmarkEnded( BenchmarkStats const& ) {} + + virtual void sectionEnded( SectionStats const& sectionStats ) = 0; + virtual void testCaseEnded( TestCaseStats const& testCaseStats ) = 0; + virtual void testGroupEnded( TestGroupStats const& testGroupStats ) = 0; + virtual void testRunEnded( TestRunStats const& testRunStats ) = 0; + + virtual void skipTest( TestCaseInfo const& testInfo ) = 0; + + // Default empty implementation provided + virtual void fatalErrorEncountered( StringRef name ); + + virtual bool isMulti() const; + }; + using IStreamingReporterPtr = std::unique_ptr; + + struct IReporterFactory { + virtual ~IReporterFactory(); + virtual IStreamingReporterPtr create( ReporterConfig const& config ) const = 0; + virtual std::string getDescription() const = 0; + }; + using IReporterFactoryPtr = std::shared_ptr; + + struct IReporterRegistry { + using FactoryMap = std::map; + using Listeners = std::vector; + + virtual ~IReporterRegistry(); + virtual IStreamingReporterPtr create( std::string const& name, IConfigPtr const& config ) const = 0; + virtual FactoryMap const& getFactories() const = 0; + virtual Listeners const& getListeners() const = 0; + }; + +} // end namespace Catch + +// end catch_interfaces_reporter.h +#include +#include +#include +#include +#include +#include +#include + +namespace Catch { + void prepareExpandedExpression(AssertionResult& result); + + // Returns double formatted as %.3f (format expected on output) + std::string getFormattedDuration( double duration ); + + template + struct StreamingReporterBase : IStreamingReporter { + + StreamingReporterBase( ReporterConfig const& _config ) + : m_config( _config.fullConfig() ), + stream( _config.stream() ) + { + m_reporterPrefs.shouldRedirectStdOut = false; + if( !DerivedT::getSupportedVerbosities().count( m_config->verbosity() ) ) + CATCH_ERROR( "Verbosity level not supported by this reporter" ); + } + + ReporterPreferences getPreferences() const override { + return m_reporterPrefs; + } + + static std::set getSupportedVerbosities() { + return { Verbosity::Normal }; + } + + ~StreamingReporterBase() override = default; + + void noMatchingTestCases(std::string const&) override {} + + void testRunStarting(TestRunInfo const& _testRunInfo) override { + currentTestRunInfo = _testRunInfo; + } + void testGroupStarting(GroupInfo const& _groupInfo) override { + currentGroupInfo = _groupInfo; + } + + void testCaseStarting(TestCaseInfo const& _testInfo) override { + currentTestCaseInfo = _testInfo; + } + void sectionStarting(SectionInfo const& _sectionInfo) override { + m_sectionStack.push_back(_sectionInfo); + } + + void sectionEnded(SectionStats const& /* _sectionStats */) override { + m_sectionStack.pop_back(); + } + void testCaseEnded(TestCaseStats const& /* _testCaseStats */) override { + currentTestCaseInfo.reset(); + } + void testGroupEnded(TestGroupStats const& /* _testGroupStats */) override { + currentGroupInfo.reset(); + } + void testRunEnded(TestRunStats const& /* _testRunStats */) override { + currentTestCaseInfo.reset(); + currentGroupInfo.reset(); + currentTestRunInfo.reset(); + } + + void skipTest(TestCaseInfo const&) override { + // Don't do anything with this by default. + // It can optionally be overridden in the derived class. + } + + IConfigPtr m_config; + std::ostream& stream; + + LazyStat currentTestRunInfo; + LazyStat currentGroupInfo; + LazyStat currentTestCaseInfo; + + std::vector m_sectionStack; + ReporterPreferences m_reporterPrefs; + }; + + template + struct CumulativeReporterBase : IStreamingReporter { + template + struct Node { + explicit Node( T const& _value ) : value( _value ) {} + virtual ~Node() {} + + using ChildNodes = std::vector>; + T value; + ChildNodes children; + }; + struct SectionNode { + explicit SectionNode(SectionStats const& _stats) : stats(_stats) {} + virtual ~SectionNode() = default; + + bool operator == (SectionNode const& other) const { + return stats.sectionInfo.lineInfo == other.stats.sectionInfo.lineInfo; + } + bool operator == (std::shared_ptr const& other) const { + return operator==(*other); + } + + SectionStats stats; + using ChildSections = std::vector>; + using Assertions = std::vector; + ChildSections childSections; + Assertions assertions; + std::string stdOut; + std::string stdErr; + }; + + struct BySectionInfo { + BySectionInfo( SectionInfo const& other ) : m_other( other ) {} + BySectionInfo( BySectionInfo const& other ) : m_other( other.m_other ) {} + bool operator() (std::shared_ptr const& node) const { + return ((node->stats.sectionInfo.name == m_other.name) && + (node->stats.sectionInfo.lineInfo == m_other.lineInfo)); + } + void operator=(BySectionInfo const&) = delete; + + private: + SectionInfo const& m_other; + }; + + using TestCaseNode = Node; + using TestGroupNode = Node; + using TestRunNode = Node; + + CumulativeReporterBase( ReporterConfig const& _config ) + : m_config( _config.fullConfig() ), + stream( _config.stream() ) + { + m_reporterPrefs.shouldRedirectStdOut = false; + if( !DerivedT::getSupportedVerbosities().count( m_config->verbosity() ) ) + CATCH_ERROR( "Verbosity level not supported by this reporter" ); + } + ~CumulativeReporterBase() override = default; + + ReporterPreferences getPreferences() const override { + return m_reporterPrefs; + } + + static std::set getSupportedVerbosities() { + return { Verbosity::Normal }; + } + + void testRunStarting( TestRunInfo const& ) override {} + void testGroupStarting( GroupInfo const& ) override {} + + void testCaseStarting( TestCaseInfo const& ) override {} + + void sectionStarting( SectionInfo const& sectionInfo ) override { + SectionStats incompleteStats( sectionInfo, Counts(), 0, false ); + std::shared_ptr node; + if( m_sectionStack.empty() ) { + if( !m_rootSection ) + m_rootSection = std::make_shared( incompleteStats ); + node = m_rootSection; + } + else { + SectionNode& parentNode = *m_sectionStack.back(); + auto it = + std::find_if( parentNode.childSections.begin(), + parentNode.childSections.end(), + BySectionInfo( sectionInfo ) ); + if( it == parentNode.childSections.end() ) { + node = std::make_shared( incompleteStats ); + parentNode.childSections.push_back( node ); + } + else + node = *it; + } + m_sectionStack.push_back( node ); + m_deepestSection = std::move(node); + } + + void assertionStarting(AssertionInfo const&) override {} + + bool assertionEnded(AssertionStats const& assertionStats) override { + assert(!m_sectionStack.empty()); + // AssertionResult holds a pointer to a temporary DecomposedExpression, + // which getExpandedExpression() calls to build the expression string. + // Our section stack copy of the assertionResult will likely outlive the + // temporary, so it must be expanded or discarded now to avoid calling + // a destroyed object later. + prepareExpandedExpression(const_cast( assertionStats.assertionResult ) ); + SectionNode& sectionNode = *m_sectionStack.back(); + sectionNode.assertions.push_back(assertionStats); + return true; + } + void sectionEnded(SectionStats const& sectionStats) override { + assert(!m_sectionStack.empty()); + SectionNode& node = *m_sectionStack.back(); + node.stats = sectionStats; + m_sectionStack.pop_back(); + } + void testCaseEnded(TestCaseStats const& testCaseStats) override { + auto node = std::make_shared(testCaseStats); + assert(m_sectionStack.size() == 0); + node->children.push_back(m_rootSection); + m_testCases.push_back(node); + m_rootSection.reset(); + + assert(m_deepestSection); + m_deepestSection->stdOut = testCaseStats.stdOut; + m_deepestSection->stdErr = testCaseStats.stdErr; + } + void testGroupEnded(TestGroupStats const& testGroupStats) override { + auto node = std::make_shared(testGroupStats); + node->children.swap(m_testCases); + m_testGroups.push_back(node); + } + void testRunEnded(TestRunStats const& testRunStats) override { + auto node = std::make_shared(testRunStats); + node->children.swap(m_testGroups); + m_testRuns.push_back(node); + testRunEndedCumulative(); + } + virtual void testRunEndedCumulative() = 0; + + void skipTest(TestCaseInfo const&) override {} + + IConfigPtr m_config; + std::ostream& stream; + std::vector m_assertions; + std::vector>> m_sections; + std::vector> m_testCases; + std::vector> m_testGroups; + + std::vector> m_testRuns; + + std::shared_ptr m_rootSection; + std::shared_ptr m_deepestSection; + std::vector> m_sectionStack; + ReporterPreferences m_reporterPrefs; + }; + + template + char const* getLineOfChars() { + static char line[CATCH_CONFIG_CONSOLE_WIDTH] = {0}; + if( !*line ) { + std::memset( line, C, CATCH_CONFIG_CONSOLE_WIDTH-1 ); + line[CATCH_CONFIG_CONSOLE_WIDTH-1] = 0; + } + return line; + } + + struct TestEventListenerBase : StreamingReporterBase { + TestEventListenerBase( ReporterConfig const& _config ); + + static std::set getSupportedVerbosities(); + + void assertionStarting(AssertionInfo const&) override; + bool assertionEnded(AssertionStats const&) override; + }; + +} // end namespace Catch + +// end catch_reporter_bases.hpp +// start catch_console_colour.h + +namespace Catch { + + struct Colour { + enum Code { + None = 0, + + White, + Red, + Green, + Blue, + Cyan, + Yellow, + Grey, + + Bright = 0x10, + + BrightRed = Bright | Red, + BrightGreen = Bright | Green, + LightGrey = Bright | Grey, + BrightWhite = Bright | White, + BrightYellow = Bright | Yellow, + + // By intention + FileName = LightGrey, + Warning = BrightYellow, + ResultError = BrightRed, + ResultSuccess = BrightGreen, + ResultExpectedFailure = Warning, + + Error = BrightRed, + Success = Green, + + OriginalExpression = Cyan, + ReconstructedExpression = BrightYellow, + + SecondaryText = LightGrey, + Headers = White + }; + + // Use constructed object for RAII guard + Colour( Code _colourCode ); + Colour( Colour&& other ) noexcept; + Colour& operator=( Colour&& other ) noexcept; + ~Colour(); + + // Use static method for one-shot changes + static void use( Code _colourCode ); + + private: + bool m_moved = false; + }; + + std::ostream& operator << ( std::ostream& os, Colour const& ); + +} // end namespace Catch + +// end catch_console_colour.h +// start catch_reporter_registrars.hpp + + +namespace Catch { + + template + class ReporterRegistrar { + + class ReporterFactory : public IReporterFactory { + + virtual IStreamingReporterPtr create( ReporterConfig const& config ) const override { + return std::unique_ptr( new T( config ) ); + } + + virtual std::string getDescription() const override { + return T::getDescription(); + } + }; + + public: + + explicit ReporterRegistrar( std::string const& name ) { + getMutableRegistryHub().registerReporter( name, std::make_shared() ); + } + }; + + template + class ListenerRegistrar { + + class ListenerFactory : public IReporterFactory { + + virtual IStreamingReporterPtr create( ReporterConfig const& config ) const override { + return std::unique_ptr( new T( config ) ); + } + virtual std::string getDescription() const override { + return std::string(); + } + }; + + public: + + ListenerRegistrar() { + getMutableRegistryHub().registerListener( std::make_shared() ); + } + }; +} + +#if !defined(CATCH_CONFIG_DISABLE) + +#define CATCH_REGISTER_REPORTER( name, reporterType ) \ + CATCH_INTERNAL_SUPPRESS_GLOBALS_WARNINGS \ + namespace{ Catch::ReporterRegistrar catch_internal_RegistrarFor##reporterType( name ); } \ + CATCH_INTERNAL_UNSUPPRESS_GLOBALS_WARNINGS + +#define CATCH_REGISTER_LISTENER( listenerType ) \ + CATCH_INTERNAL_SUPPRESS_GLOBALS_WARNINGS \ + namespace{ Catch::ListenerRegistrar catch_internal_RegistrarFor##listenerType; } \ + CATCH_INTERNAL_SUPPRESS_GLOBALS_WARNINGS +#else // CATCH_CONFIG_DISABLE + +#define CATCH_REGISTER_REPORTER(name, reporterType) +#define CATCH_REGISTER_LISTENER(listenerType) + +#endif // CATCH_CONFIG_DISABLE + +// end catch_reporter_registrars.hpp +// Allow users to base their work off existing reporters +// start catch_reporter_compact.h + +namespace Catch { + + struct CompactReporter : StreamingReporterBase { + + using StreamingReporterBase::StreamingReporterBase; + + ~CompactReporter() override; + + static std::string getDescription(); + + ReporterPreferences getPreferences() const override; + + void noMatchingTestCases(std::string const& spec) override; + + void assertionStarting(AssertionInfo const&) override; + + bool assertionEnded(AssertionStats const& _assertionStats) override; + + void sectionEnded(SectionStats const& _sectionStats) override; + + void testRunEnded(TestRunStats const& _testRunStats) override; + + }; + +} // end namespace Catch + +// end catch_reporter_compact.h +// start catch_reporter_console.h + +#if defined(_MSC_VER) +#pragma warning(push) +#pragma warning(disable:4061) // Not all labels are EXPLICITLY handled in switch + // Note that 4062 (not all labels are handled + // and default is missing) is enabled +#endif + +namespace Catch { + // Fwd decls + struct SummaryColumn; + class TablePrinter; + + struct ConsoleReporter : StreamingReporterBase { + std::unique_ptr m_tablePrinter; + + ConsoleReporter(ReporterConfig const& config); + ~ConsoleReporter() override; + static std::string getDescription(); + + void noMatchingTestCases(std::string const& spec) override; + + void assertionStarting(AssertionInfo const&) override; + + bool assertionEnded(AssertionStats const& _assertionStats) override; + + void sectionStarting(SectionInfo const& _sectionInfo) override; + void sectionEnded(SectionStats const& _sectionStats) override; + + void benchmarkStarting(BenchmarkInfo const& info) override; + void benchmarkEnded(BenchmarkStats const& stats) override; + + void testCaseEnded(TestCaseStats const& _testCaseStats) override; + void testGroupEnded(TestGroupStats const& _testGroupStats) override; + void testRunEnded(TestRunStats const& _testRunStats) override; + + private: + + void lazyPrint(); + + void lazyPrintWithoutClosingBenchmarkTable(); + void lazyPrintRunInfo(); + void lazyPrintGroupInfo(); + void printTestCaseAndSectionHeader(); + + void printClosedHeader(std::string const& _name); + void printOpenHeader(std::string const& _name); + + // if string has a : in first line will set indent to follow it on + // subsequent lines + void printHeaderString(std::string const& _string, std::size_t indent = 0); + + void printTotals(Totals const& totals); + void printSummaryRow(std::string const& label, std::vector const& cols, std::size_t row); + + void printTotalsDivider(Totals const& totals); + void printSummaryDivider(); + + private: + bool m_headerPrinted = false; + }; + +} // end namespace Catch + +#if defined(_MSC_VER) +#pragma warning(pop) +#endif + +// end catch_reporter_console.h +// start catch_reporter_junit.h + +// start catch_xmlwriter.h + +#include + +namespace Catch { + + class XmlEncode { + public: + enum ForWhat { ForTextNodes, ForAttributes }; + + XmlEncode( std::string const& str, ForWhat forWhat = ForTextNodes ); + + void encodeTo( std::ostream& os ) const; + + friend std::ostream& operator << ( std::ostream& os, XmlEncode const& xmlEncode ); + + private: + std::string m_str; + ForWhat m_forWhat; + }; + + class XmlWriter { + public: + + class ScopedElement { + public: + ScopedElement( XmlWriter* writer ); + + ScopedElement( ScopedElement&& other ) noexcept; + ScopedElement& operator=( ScopedElement&& other ) noexcept; + + ~ScopedElement(); + + ScopedElement& writeText( std::string const& text, bool indent = true ); + + template + ScopedElement& writeAttribute( std::string const& name, T const& attribute ) { + m_writer->writeAttribute( name, attribute ); + return *this; + } + + private: + mutable XmlWriter* m_writer = nullptr; + }; + + XmlWriter( std::ostream& os = Catch::cout() ); + ~XmlWriter(); + + XmlWriter( XmlWriter const& ) = delete; + XmlWriter& operator=( XmlWriter const& ) = delete; + + XmlWriter& startElement( std::string const& name ); + + ScopedElement scopedElement( std::string const& name ); + + XmlWriter& endElement(); + + XmlWriter& writeAttribute( std::string const& name, std::string const& attribute ); + + XmlWriter& writeAttribute( std::string const& name, bool attribute ); + + template + XmlWriter& writeAttribute( std::string const& name, T const& attribute ) { + ReusableStringStream rss; + rss << attribute; + return writeAttribute( name, rss.str() ); + } + + XmlWriter& writeText( std::string const& text, bool indent = true ); + + XmlWriter& writeComment( std::string const& text ); + + void writeStylesheetRef( std::string const& url ); + + XmlWriter& writeBlankLine(); + + void ensureTagClosed(); + + private: + + void writeDeclaration(); + + void newlineIfNecessary(); + + bool m_tagIsOpen = false; + bool m_needsNewline = false; + std::vector m_tags; + std::string m_indent; + std::ostream& m_os; + }; + +} + +// end catch_xmlwriter.h +namespace Catch { + + class JunitReporter : public CumulativeReporterBase { + public: + JunitReporter(ReporterConfig const& _config); + + ~JunitReporter() override; + + static std::string getDescription(); + + void noMatchingTestCases(std::string const& /*spec*/) override; + + void testRunStarting(TestRunInfo const& runInfo) override; + + void testGroupStarting(GroupInfo const& groupInfo) override; + + void testCaseStarting(TestCaseInfo const& testCaseInfo) override; + bool assertionEnded(AssertionStats const& assertionStats) override; + + void testCaseEnded(TestCaseStats const& testCaseStats) override; + + void testGroupEnded(TestGroupStats const& testGroupStats) override; + + void testRunEndedCumulative() override; + + void writeGroup(TestGroupNode const& groupNode, double suiteTime); + + void writeTestCase(TestCaseNode const& testCaseNode); + + void writeSection(std::string const& className, + std::string const& rootName, + SectionNode const& sectionNode); + + void writeAssertions(SectionNode const& sectionNode); + void writeAssertion(AssertionStats const& stats); + + XmlWriter xml; + Timer suiteTimer; + std::string stdOutForSuite; + std::string stdErrForSuite; + unsigned int unexpectedExceptions = 0; + bool m_okToFail = false; + }; + +} // end namespace Catch + +// end catch_reporter_junit.h +// start catch_reporter_xml.h + +namespace Catch { + class XmlReporter : public StreamingReporterBase { + public: + XmlReporter(ReporterConfig const& _config); + + ~XmlReporter() override; + + static std::string getDescription(); + + virtual std::string getStylesheetRef() const; + + void writeSourceInfo(SourceLineInfo const& sourceInfo); + + public: // StreamingReporterBase + + void noMatchingTestCases(std::string const& s) override; + + void testRunStarting(TestRunInfo const& testInfo) override; + + void testGroupStarting(GroupInfo const& groupInfo) override; + + void testCaseStarting(TestCaseInfo const& testInfo) override; + + void sectionStarting(SectionInfo const& sectionInfo) override; + + void assertionStarting(AssertionInfo const&) override; + + bool assertionEnded(AssertionStats const& assertionStats) override; + + void sectionEnded(SectionStats const& sectionStats) override; + + void testCaseEnded(TestCaseStats const& testCaseStats) override; + + void testGroupEnded(TestGroupStats const& testGroupStats) override; + + void testRunEnded(TestRunStats const& testRunStats) override; + + private: + Timer m_testCaseTimer; + XmlWriter m_xml; + int m_sectionDepth = 0; + }; + +} // end namespace Catch + +// end catch_reporter_xml.h + +// end catch_external_interfaces.h +#endif + +#endif // ! CATCH_CONFIG_IMPL_ONLY + +#ifdef CATCH_IMPL +// start catch_impl.hpp + +#ifdef __clang__ +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wweak-vtables" +#endif + +// Keep these here for external reporters +// start catch_test_case_tracker.h + +#include +#include +#include + +namespace Catch { +namespace TestCaseTracking { + + struct NameAndLocation { + std::string name; + SourceLineInfo location; + + NameAndLocation( std::string const& _name, SourceLineInfo const& _location ); + }; + + struct ITracker; + + using ITrackerPtr = std::shared_ptr; + + struct ITracker { + virtual ~ITracker(); + + // static queries + virtual NameAndLocation const& nameAndLocation() const = 0; + + // dynamic queries + virtual bool isComplete() const = 0; // Successfully completed or failed + virtual bool isSuccessfullyCompleted() const = 0; + virtual bool isOpen() const = 0; // Started but not complete + virtual bool hasChildren() const = 0; + + virtual ITracker& parent() = 0; + + // actions + virtual void close() = 0; // Successfully complete + virtual void fail() = 0; + virtual void markAsNeedingAnotherRun() = 0; + + virtual void addChild( ITrackerPtr const& child ) = 0; + virtual ITrackerPtr findChild( NameAndLocation const& nameAndLocation ) = 0; + virtual void openChild() = 0; + + // Debug/ checking + virtual bool isSectionTracker() const = 0; + virtual bool isGeneratorTracker() const = 0; + }; + + class TrackerContext { + + enum RunState { + NotStarted, + Executing, + CompletedCycle + }; + + ITrackerPtr m_rootTracker; + ITracker* m_currentTracker = nullptr; + RunState m_runState = NotStarted; + + public: + + static TrackerContext& instance(); + + ITracker& startRun(); + void endRun(); + + void startCycle(); + void completeCycle(); + + bool completedCycle() const; + ITracker& currentTracker(); + void setCurrentTracker( ITracker* tracker ); + }; + + class TrackerBase : public ITracker { + protected: + enum CycleState { + NotStarted, + Executing, + ExecutingChildren, + NeedsAnotherRun, + CompletedSuccessfully, + Failed + }; + + using Children = std::vector; + NameAndLocation m_nameAndLocation; + TrackerContext& m_ctx; + ITracker* m_parent; + Children m_children; + CycleState m_runState = NotStarted; + + public: + TrackerBase( NameAndLocation const& nameAndLocation, TrackerContext& ctx, ITracker* parent ); + + NameAndLocation const& nameAndLocation() const override; + bool isComplete() const override; + bool isSuccessfullyCompleted() const override; + bool isOpen() const override; + bool hasChildren() const override; + + void addChild( ITrackerPtr const& child ) override; + + ITrackerPtr findChild( NameAndLocation const& nameAndLocation ) override; + ITracker& parent() override; + + void openChild() override; + + bool isSectionTracker() const override; + bool isGeneratorTracker() const override; + + void open(); + + void close() override; + void fail() override; + void markAsNeedingAnotherRun() override; + + private: + void moveToParent(); + void moveToThis(); + }; + + class SectionTracker : public TrackerBase { + std::vector m_filters; + public: + SectionTracker( NameAndLocation const& nameAndLocation, TrackerContext& ctx, ITracker* parent ); + + bool isSectionTracker() const override; + + bool isComplete() const override; + + static SectionTracker& acquire( TrackerContext& ctx, NameAndLocation const& nameAndLocation ); + + void tryOpen(); + + void addInitialFilters( std::vector const& filters ); + void addNextFilters( std::vector const& filters ); + }; + +} // namespace TestCaseTracking + +using TestCaseTracking::ITracker; +using TestCaseTracking::TrackerContext; +using TestCaseTracking::SectionTracker; + +} // namespace Catch + +// end catch_test_case_tracker.h + +// start catch_leak_detector.h + +namespace Catch { + + struct LeakDetector { + LeakDetector(); + ~LeakDetector(); + }; + +} +// end catch_leak_detector.h +// Cpp files will be included in the single-header file here +// start catch_approx.cpp + +#include +#include + +namespace { + +// Performs equivalent check of std::fabs(lhs - rhs) <= margin +// But without the subtraction to allow for INFINITY in comparison +bool marginComparison(double lhs, double rhs, double margin) { + return (lhs + margin >= rhs) && (rhs + margin >= lhs); +} + +} + +namespace Catch { +namespace Detail { + + Approx::Approx ( double value ) + : m_epsilon( std::numeric_limits::epsilon()*100 ), + m_margin( 0.0 ), + m_scale( 0.0 ), + m_value( value ) + {} + + Approx Approx::custom() { + return Approx( 0 ); + } + + Approx Approx::operator-() const { + auto temp(*this); + temp.m_value = -temp.m_value; + return temp; + } + + std::string Approx::toString() const { + ReusableStringStream rss; + rss << "Approx( " << ::Catch::Detail::stringify( m_value ) << " )"; + return rss.str(); + } + + bool Approx::equalityComparisonImpl(const double other) const { + // First try with fixed margin, then compute margin based on epsilon, scale and Approx's value + // Thanks to Richard Harris for his help refining the scaled margin value + return marginComparison(m_value, other, m_margin) || marginComparison(m_value, other, m_epsilon * (m_scale + std::fabs(m_value))); + } + + void Approx::setMargin(double margin) { + CATCH_ENFORCE(margin >= 0, + "Invalid Approx::margin: " << margin << '.' + << " Approx::Margin has to be non-negative."); + m_margin = margin; + } + + void Approx::setEpsilon(double epsilon) { + CATCH_ENFORCE(epsilon >= 0 && epsilon <= 1.0, + "Invalid Approx::epsilon: " << epsilon << '.' + << " Approx::epsilon has to be in [0, 1]"); + m_epsilon = epsilon; + } + +} // end namespace Detail + +namespace literals { + Detail::Approx operator "" _a(long double val) { + return Detail::Approx(val); + } + Detail::Approx operator "" _a(unsigned long long val) { + return Detail::Approx(val); + } +} // end namespace literals + +std::string StringMaker::convert(Catch::Detail::Approx const& value) { + return value.toString(); +} + +} // end namespace Catch +// end catch_approx.cpp +// start catch_assertionhandler.cpp + +// start catch_debugger.h + +namespace Catch { + bool isDebuggerActive(); +} + +#ifdef CATCH_PLATFORM_MAC + + #define CATCH_TRAP() __asm__("int $3\n" : : ) /* NOLINT */ + +#elif defined(CATCH_PLATFORM_LINUX) + // If we can use inline assembler, do it because this allows us to break + // directly at the location of the failing check instead of breaking inside + // raise() called from it, i.e. one stack frame below. + #if defined(__GNUC__) && (defined(__i386) || defined(__x86_64)) + #define CATCH_TRAP() asm volatile ("int $3") /* NOLINT */ + #else // Fall back to the generic way. + #include + + #define CATCH_TRAP() raise(SIGTRAP) + #endif +#elif defined(_MSC_VER) + #define CATCH_TRAP() __debugbreak() +#elif defined(__MINGW32__) + extern "C" __declspec(dllimport) void __stdcall DebugBreak(); + #define CATCH_TRAP() DebugBreak() +#endif + +#ifdef CATCH_TRAP + #define CATCH_BREAK_INTO_DEBUGGER() []{ if( Catch::isDebuggerActive() ) { CATCH_TRAP(); } }() +#else + #define CATCH_BREAK_INTO_DEBUGGER() []{}() +#endif + +// end catch_debugger.h +// start catch_run_context.h + +// start catch_fatal_condition.h + +// start catch_windows_h_proxy.h + + +#if defined(CATCH_PLATFORM_WINDOWS) + +#if !defined(NOMINMAX) && !defined(CATCH_CONFIG_NO_NOMINMAX) +# define CATCH_DEFINED_NOMINMAX +# define NOMINMAX +#endif +#if !defined(WIN32_LEAN_AND_MEAN) && !defined(CATCH_CONFIG_NO_WIN32_LEAN_AND_MEAN) +# define CATCH_DEFINED_WIN32_LEAN_AND_MEAN +# define WIN32_LEAN_AND_MEAN +#endif + +#ifdef __AFXDLL +#include +#else +#include +#endif + +#ifdef CATCH_DEFINED_NOMINMAX +# undef NOMINMAX +#endif +#ifdef CATCH_DEFINED_WIN32_LEAN_AND_MEAN +# undef WIN32_LEAN_AND_MEAN +#endif + +#endif // defined(CATCH_PLATFORM_WINDOWS) + +// end catch_windows_h_proxy.h +#if defined( CATCH_CONFIG_WINDOWS_SEH ) + +namespace Catch { + + struct FatalConditionHandler { + + static LONG CALLBACK handleVectoredException(PEXCEPTION_POINTERS ExceptionInfo); + FatalConditionHandler(); + static void reset(); + ~FatalConditionHandler(); + + private: + static bool isSet; + static ULONG guaranteeSize; + static PVOID exceptionHandlerHandle; + }; + +} // namespace Catch + +#elif defined ( CATCH_CONFIG_POSIX_SIGNALS ) + +#include + +namespace Catch { + + struct FatalConditionHandler { + + static bool isSet; + static struct sigaction oldSigActions[]; + static stack_t oldSigStack; + static char altStackMem[]; + + static void handleSignal( int sig ); + + FatalConditionHandler(); + ~FatalConditionHandler(); + static void reset(); + }; + +} // namespace Catch + +#else + +namespace Catch { + struct FatalConditionHandler { + void reset(); + }; +} + +#endif + +// end catch_fatal_condition.h +#include + +namespace Catch { + + struct IMutableContext; + + /////////////////////////////////////////////////////////////////////////// + + class RunContext : public IResultCapture, public IRunner { + + public: + RunContext( RunContext const& ) = delete; + RunContext& operator =( RunContext const& ) = delete; + + explicit RunContext( IConfigPtr const& _config, IStreamingReporterPtr&& reporter ); + + ~RunContext() override; + + void testGroupStarting( std::string const& testSpec, std::size_t groupIndex, std::size_t groupsCount ); + void testGroupEnded( std::string const& testSpec, Totals const& totals, std::size_t groupIndex, std::size_t groupsCount ); + + Totals runTest(TestCase const& testCase); + + IConfigPtr config() const; + IStreamingReporter& reporter() const; + + public: // IResultCapture + + // Assertion handlers + void handleExpr + ( AssertionInfo const& info, + ITransientExpression const& expr, + AssertionReaction& reaction ) override; + void handleMessage + ( AssertionInfo const& info, + ResultWas::OfType resultType, + StringRef const& message, + AssertionReaction& reaction ) override; + void handleUnexpectedExceptionNotThrown + ( AssertionInfo const& info, + AssertionReaction& reaction ) override; + void handleUnexpectedInflightException + ( AssertionInfo const& info, + std::string const& message, + AssertionReaction& reaction ) override; + void handleIncomplete + ( AssertionInfo const& info ) override; + void handleNonExpr + ( AssertionInfo const &info, + ResultWas::OfType resultType, + AssertionReaction &reaction ) override; + + bool sectionStarted( SectionInfo const& sectionInfo, Counts& assertions ) override; + + void sectionEnded( SectionEndInfo const& endInfo ) override; + void sectionEndedEarly( SectionEndInfo const& endInfo ) override; + + auto acquireGeneratorTracker( SourceLineInfo const& lineInfo ) -> IGeneratorTracker& override; + + void benchmarkStarting( BenchmarkInfo const& info ) override; + void benchmarkEnded( BenchmarkStats const& stats ) override; + + void pushScopedMessage( MessageInfo const& message ) override; + void popScopedMessage( MessageInfo const& message ) override; + + void emplaceUnscopedMessage( MessageBuilder const& builder ) override; + + std::string getCurrentTestName() const override; + + const AssertionResult* getLastResult() const override; + + void exceptionEarlyReported() override; + + void handleFatalErrorCondition( StringRef message ) override; + + bool lastAssertionPassed() override; + + void assertionPassed() override; + + public: + // !TBD We need to do this another way! + bool aborting() const final; + + private: + + void runCurrentTest( std::string& redirectedCout, std::string& redirectedCerr ); + void invokeActiveTestCase(); + + void resetAssertionInfo(); + bool testForMissingAssertions( Counts& assertions ); + + void assertionEnded( AssertionResult const& result ); + void reportExpr + ( AssertionInfo const &info, + ResultWas::OfType resultType, + ITransientExpression const *expr, + bool negated ); + + void populateReaction( AssertionReaction& reaction ); + + private: + + void handleUnfinishedSections(); + + TestRunInfo m_runInfo; + IMutableContext& m_context; + TestCase const* m_activeTestCase = nullptr; + ITracker* m_testCaseTracker = nullptr; + Option m_lastResult; + + IConfigPtr m_config; + Totals m_totals; + IStreamingReporterPtr m_reporter; + std::vector m_messages; + std::vector m_messageScopes; /* Keeps owners of so-called unscoped messages. */ + AssertionInfo m_lastAssertionInfo; + std::vector m_unfinishedSections; + std::vector m_activeSections; + TrackerContext m_trackerContext; + bool m_lastAssertionPassed = false; + bool m_shouldReportUnexpected = true; + bool m_includeSuccessfulResults; + }; + +} // end namespace Catch + +// end catch_run_context.h +namespace Catch { + + namespace { + auto operator <<( std::ostream& os, ITransientExpression const& expr ) -> std::ostream& { + expr.streamReconstructedExpression( os ); + return os; + } + } + + LazyExpression::LazyExpression( bool isNegated ) + : m_isNegated( isNegated ) + {} + + LazyExpression::LazyExpression( LazyExpression const& other ) : m_isNegated( other.m_isNegated ) {} + + LazyExpression::operator bool() const { + return m_transientExpression != nullptr; + } + + auto operator << ( std::ostream& os, LazyExpression const& lazyExpr ) -> std::ostream& { + if( lazyExpr.m_isNegated ) + os << "!"; + + if( lazyExpr ) { + if( lazyExpr.m_isNegated && lazyExpr.m_transientExpression->isBinaryExpression() ) + os << "(" << *lazyExpr.m_transientExpression << ")"; + else + os << *lazyExpr.m_transientExpression; + } + else { + os << "{** error - unchecked empty expression requested **}"; + } + return os; + } + + AssertionHandler::AssertionHandler + ( StringRef const& macroName, + SourceLineInfo const& lineInfo, + StringRef capturedExpression, + ResultDisposition::Flags resultDisposition ) + : m_assertionInfo{ macroName, lineInfo, capturedExpression, resultDisposition }, + m_resultCapture( getResultCapture() ) + {} + + void AssertionHandler::handleExpr( ITransientExpression const& expr ) { + m_resultCapture.handleExpr( m_assertionInfo, expr, m_reaction ); + } + void AssertionHandler::handleMessage(ResultWas::OfType resultType, StringRef const& message) { + m_resultCapture.handleMessage( m_assertionInfo, resultType, message, m_reaction ); + } + + auto AssertionHandler::allowThrows() const -> bool { + return getCurrentContext().getConfig()->allowThrows(); + } + + void AssertionHandler::complete() { + setCompleted(); + if( m_reaction.shouldDebugBreak ) { + + // If you find your debugger stopping you here then go one level up on the + // call-stack for the code that caused it (typically a failed assertion) + + // (To go back to the test and change execution, jump over the throw, next) + CATCH_BREAK_INTO_DEBUGGER(); + } + if (m_reaction.shouldThrow) { +#if !defined(CATCH_CONFIG_DISABLE_EXCEPTIONS) + throw Catch::TestFailureException(); +#else + CATCH_ERROR( "Test failure requires aborting test!" ); +#endif + } + } + void AssertionHandler::setCompleted() { + m_completed = true; + } + + void AssertionHandler::handleUnexpectedInflightException() { + m_resultCapture.handleUnexpectedInflightException( m_assertionInfo, Catch::translateActiveException(), m_reaction ); + } + + void AssertionHandler::handleExceptionThrownAsExpected() { + m_resultCapture.handleNonExpr(m_assertionInfo, ResultWas::Ok, m_reaction); + } + void AssertionHandler::handleExceptionNotThrownAsExpected() { + m_resultCapture.handleNonExpr(m_assertionInfo, ResultWas::Ok, m_reaction); + } + + void AssertionHandler::handleUnexpectedExceptionNotThrown() { + m_resultCapture.handleUnexpectedExceptionNotThrown( m_assertionInfo, m_reaction ); + } + + void AssertionHandler::handleThrowingCallSkipped() { + m_resultCapture.handleNonExpr(m_assertionInfo, ResultWas::Ok, m_reaction); + } + + // This is the overload that takes a string and infers the Equals matcher from it + // The more general overload, that takes any string matcher, is in catch_capture_matchers.cpp + void handleExceptionMatchExpr( AssertionHandler& handler, std::string const& str, StringRef const& matcherString ) { + handleExceptionMatchExpr( handler, Matchers::Equals( str ), matcherString ); + } + +} // namespace Catch +// end catch_assertionhandler.cpp +// start catch_assertionresult.cpp + +namespace Catch { + AssertionResultData::AssertionResultData(ResultWas::OfType _resultType, LazyExpression const & _lazyExpression): + lazyExpression(_lazyExpression), + resultType(_resultType) {} + + std::string AssertionResultData::reconstructExpression() const { + + if( reconstructedExpression.empty() ) { + if( lazyExpression ) { + ReusableStringStream rss; + rss << lazyExpression; + reconstructedExpression = rss.str(); + } + } + return reconstructedExpression; + } + + AssertionResult::AssertionResult( AssertionInfo const& info, AssertionResultData const& data ) + : m_info( info ), + m_resultData( data ) + {} + + // Result was a success + bool AssertionResult::succeeded() const { + return Catch::isOk( m_resultData.resultType ); + } + + // Result was a success, or failure is suppressed + bool AssertionResult::isOk() const { + return Catch::isOk( m_resultData.resultType ) || shouldSuppressFailure( m_info.resultDisposition ); + } + + ResultWas::OfType AssertionResult::getResultType() const { + return m_resultData.resultType; + } + + bool AssertionResult::hasExpression() const { + return m_info.capturedExpression[0] != 0; + } + + bool AssertionResult::hasMessage() const { + return !m_resultData.message.empty(); + } + + std::string AssertionResult::getExpression() const { + if( isFalseTest( m_info.resultDisposition ) ) + return "!(" + m_info.capturedExpression + ")"; + else + return m_info.capturedExpression; + } + + std::string AssertionResult::getExpressionInMacro() const { + std::string expr; + if( m_info.macroName[0] == 0 ) + expr = m_info.capturedExpression; + else { + expr.reserve( m_info.macroName.size() + m_info.capturedExpression.size() + 4 ); + expr += m_info.macroName; + expr += "( "; + expr += m_info.capturedExpression; + expr += " )"; + } + return expr; + } + + bool AssertionResult::hasExpandedExpression() const { + return hasExpression() && getExpandedExpression() != getExpression(); + } + + std::string AssertionResult::getExpandedExpression() const { + std::string expr = m_resultData.reconstructExpression(); + return expr.empty() + ? getExpression() + : expr; + } + + std::string AssertionResult::getMessage() const { + return m_resultData.message; + } + SourceLineInfo AssertionResult::getSourceInfo() const { + return m_info.lineInfo; + } + + StringRef AssertionResult::getTestMacroName() const { + return m_info.macroName; + } + +} // end namespace Catch +// end catch_assertionresult.cpp +// start catch_benchmark.cpp + +namespace Catch { + + auto BenchmarkLooper::getResolution() -> uint64_t { + return getEstimatedClockResolution() * getCurrentContext().getConfig()->benchmarkResolutionMultiple(); + } + + void BenchmarkLooper::reportStart() { + getResultCapture().benchmarkStarting( { m_name } ); + } + auto BenchmarkLooper::needsMoreIterations() -> bool { + auto elapsed = m_timer.getElapsedNanoseconds(); + + // Exponentially increasing iterations until we're confident in our timer resolution + if( elapsed < m_resolution ) { + m_iterationsToRun *= 10; + return true; + } + + getResultCapture().benchmarkEnded( { { m_name }, m_count, elapsed } ); + return false; + } + +} // end namespace Catch +// end catch_benchmark.cpp +// start catch_capture_matchers.cpp + +namespace Catch { + + using StringMatcher = Matchers::Impl::MatcherBase; + + // This is the general overload that takes a any string matcher + // There is another overload, in catch_assertionhandler.h/.cpp, that only takes a string and infers + // the Equals matcher (so the header does not mention matchers) + void handleExceptionMatchExpr( AssertionHandler& handler, StringMatcher const& matcher, StringRef const& matcherString ) { + std::string exceptionMessage = Catch::translateActiveException(); + MatchExpr expr( exceptionMessage, matcher, matcherString ); + handler.handleExpr( expr ); + } + +} // namespace Catch +// end catch_capture_matchers.cpp +// start catch_commandline.cpp + +// start catch_commandline.h + +// start catch_clara.h + +// Use Catch's value for console width (store Clara's off to the side, if present) +#ifdef CLARA_CONFIG_CONSOLE_WIDTH +#define CATCH_TEMP_CLARA_CONFIG_CONSOLE_WIDTH CATCH_CLARA_TEXTFLOW_CONFIG_CONSOLE_WIDTH +#undef CATCH_CLARA_TEXTFLOW_CONFIG_CONSOLE_WIDTH +#endif +#define CATCH_CLARA_TEXTFLOW_CONFIG_CONSOLE_WIDTH CATCH_CONFIG_CONSOLE_WIDTH-1 + +#ifdef __clang__ +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wweak-vtables" +#pragma clang diagnostic ignored "-Wexit-time-destructors" +#pragma clang diagnostic ignored "-Wshadow" +#endif + +// start clara.hpp +// Copyright 2017 Two Blue Cubes Ltd. All rights reserved. +// +// Distributed under the Boost Software License, Version 1.0. (See accompanying +// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt) +// +// See https://github.com/philsquared/Clara for more details + +// Clara v1.1.5 + + +#ifndef CATCH_CLARA_CONFIG_CONSOLE_WIDTH +#define CATCH_CLARA_CONFIG_CONSOLE_WIDTH 80 +#endif + +#ifndef CATCH_CLARA_TEXTFLOW_CONFIG_CONSOLE_WIDTH +#define CATCH_CLARA_TEXTFLOW_CONFIG_CONSOLE_WIDTH CATCH_CLARA_CONFIG_CONSOLE_WIDTH +#endif + +#ifndef CLARA_CONFIG_OPTIONAL_TYPE +#ifdef __has_include +#if __has_include() && __cplusplus >= 201703L +#include +#define CLARA_CONFIG_OPTIONAL_TYPE std::optional +#endif +#endif +#endif + +// ----------- #included from clara_textflow.hpp ----------- + +// TextFlowCpp +// +// A single-header library for wrapping and laying out basic text, by Phil Nash +// +// Distributed under the Boost Software License, Version 1.0. (See accompanying +// file LICENSE.txt or copy at http://www.boost.org/LICENSE_1_0.txt) +// +// This project is hosted at https://github.com/philsquared/textflowcpp + + +#include +#include +#include +#include + +#ifndef CATCH_CLARA_TEXTFLOW_CONFIG_CONSOLE_WIDTH +#define CATCH_CLARA_TEXTFLOW_CONFIG_CONSOLE_WIDTH 80 +#endif + +namespace Catch { +namespace clara { +namespace TextFlow { + +inline auto isWhitespace(char c) -> bool { + static std::string chars = " \t\n\r"; + return chars.find(c) != std::string::npos; +} +inline auto isBreakableBefore(char c) -> bool { + static std::string chars = "[({<|"; + return chars.find(c) != std::string::npos; +} +inline auto isBreakableAfter(char c) -> bool { + static std::string chars = "])}>.,:;*+-=&/\\"; + return chars.find(c) != std::string::npos; +} + +class Columns; + +class Column { + std::vector m_strings; + size_t m_width = CATCH_CLARA_TEXTFLOW_CONFIG_CONSOLE_WIDTH; + size_t m_indent = 0; + size_t m_initialIndent = std::string::npos; + +public: + class iterator { + friend Column; + + Column const& m_column; + size_t m_stringIndex = 0; + size_t m_pos = 0; + + size_t m_len = 0; + size_t m_end = 0; + bool m_suffix = false; + + iterator(Column const& column, size_t stringIndex) + : m_column(column), + m_stringIndex(stringIndex) {} + + auto line() const -> std::string const& { return m_column.m_strings[m_stringIndex]; } + + auto isBoundary(size_t at) const -> bool { + assert(at > 0); + assert(at <= line().size()); + + return at == line().size() || + (isWhitespace(line()[at]) && !isWhitespace(line()[at - 1])) || + isBreakableBefore(line()[at]) || + isBreakableAfter(line()[at - 1]); + } + + void calcLength() { + assert(m_stringIndex < m_column.m_strings.size()); + + m_suffix = false; + auto width = m_column.m_width - indent(); + m_end = m_pos; + while (m_end < line().size() && line()[m_end] != '\n') + ++m_end; + + if (m_end < m_pos + width) { + m_len = m_end - m_pos; + } else { + size_t len = width; + while (len > 0 && !isBoundary(m_pos + len)) + --len; + while (len > 0 && isWhitespace(line()[m_pos + len - 1])) + --len; + + if (len > 0) { + m_len = len; + } else { + m_suffix = true; + m_len = width - 1; + } + } + } + + auto indent() const -> size_t { + auto initial = m_pos == 0 && m_stringIndex == 0 ? m_column.m_initialIndent : std::string::npos; + return initial == std::string::npos ? m_column.m_indent : initial; + } + + auto addIndentAndSuffix(std::string const &plain) const -> std::string { + return std::string(indent(), ' ') + (m_suffix ? plain + "-" : plain); + } + + public: + using difference_type = std::ptrdiff_t; + using value_type = std::string; + using pointer = value_type * ; + using reference = value_type & ; + using iterator_category = std::forward_iterator_tag; + + explicit iterator(Column const& column) : m_column(column) { + assert(m_column.m_width > m_column.m_indent); + assert(m_column.m_initialIndent == std::string::npos || m_column.m_width > m_column.m_initialIndent); + calcLength(); + if (m_len == 0) + m_stringIndex++; // Empty string + } + + auto operator *() const -> std::string { + assert(m_stringIndex < m_column.m_strings.size()); + assert(m_pos <= m_end); + return addIndentAndSuffix(line().substr(m_pos, m_len)); + } + + auto operator ++() -> iterator& { + m_pos += m_len; + if (m_pos < line().size() && line()[m_pos] == '\n') + m_pos += 1; + else + while (m_pos < line().size() && isWhitespace(line()[m_pos])) + ++m_pos; + + if (m_pos == line().size()) { + m_pos = 0; + ++m_stringIndex; + } + if (m_stringIndex < m_column.m_strings.size()) + calcLength(); + return *this; + } + auto operator ++(int) -> iterator { + iterator prev(*this); + operator++(); + return prev; + } + + auto operator ==(iterator const& other) const -> bool { + return + m_pos == other.m_pos && + m_stringIndex == other.m_stringIndex && + &m_column == &other.m_column; + } + auto operator !=(iterator const& other) const -> bool { + return !operator==(other); + } + }; + using const_iterator = iterator; + + explicit Column(std::string const& text) { m_strings.push_back(text); } + + auto width(size_t newWidth) -> Column& { + assert(newWidth > 0); + m_width = newWidth; + return *this; + } + auto indent(size_t newIndent) -> Column& { + m_indent = newIndent; + return *this; + } + auto initialIndent(size_t newIndent) -> Column& { + m_initialIndent = newIndent; + return *this; + } + + auto width() const -> size_t { return m_width; } + auto begin() const -> iterator { return iterator(*this); } + auto end() const -> iterator { return { *this, m_strings.size() }; } + + inline friend std::ostream& operator << (std::ostream& os, Column const& col) { + bool first = true; + for (auto line : col) { + if (first) + first = false; + else + os << "\n"; + os << line; + } + return os; + } + + auto operator + (Column const& other)->Columns; + + auto toString() const -> std::string { + std::ostringstream oss; + oss << *this; + return oss.str(); + } +}; + +class Spacer : public Column { + +public: + explicit Spacer(size_t spaceWidth) : Column("") { + width(spaceWidth); + } +}; + +class Columns { + std::vector m_columns; + +public: + + class iterator { + friend Columns; + struct EndTag {}; + + std::vector const& m_columns; + std::vector m_iterators; + size_t m_activeIterators; + + iterator(Columns const& columns, EndTag) + : m_columns(columns.m_columns), + m_activeIterators(0) { + m_iterators.reserve(m_columns.size()); + + for (auto const& col : m_columns) + m_iterators.push_back(col.end()); + } + + public: + using difference_type = std::ptrdiff_t; + using value_type = std::string; + using pointer = value_type * ; + using reference = value_type & ; + using iterator_category = std::forward_iterator_tag; + + explicit iterator(Columns const& columns) + : m_columns(columns.m_columns), + m_activeIterators(m_columns.size()) { + m_iterators.reserve(m_columns.size()); + + for (auto const& col : m_columns) + m_iterators.push_back(col.begin()); + } + + auto operator ==(iterator const& other) const -> bool { + return m_iterators == other.m_iterators; + } + auto operator !=(iterator const& other) const -> bool { + return m_iterators != other.m_iterators; + } + auto operator *() const -> std::string { + std::string row, padding; + + for (size_t i = 0; i < m_columns.size(); ++i) { + auto width = m_columns[i].width(); + if (m_iterators[i] != m_columns[i].end()) { + std::string col = *m_iterators[i]; + row += padding + col; + if (col.size() < width) + padding = std::string(width - col.size(), ' '); + else + padding = ""; + } else { + padding += std::string(width, ' '); + } + } + return row; + } + auto operator ++() -> iterator& { + for (size_t i = 0; i < m_columns.size(); ++i) { + if (m_iterators[i] != m_columns[i].end()) + ++m_iterators[i]; + } + return *this; + } + auto operator ++(int) -> iterator { + iterator prev(*this); + operator++(); + return prev; + } + }; + using const_iterator = iterator; + + auto begin() const -> iterator { return iterator(*this); } + auto end() const -> iterator { return { *this, iterator::EndTag() }; } + + auto operator += (Column const& col) -> Columns& { + m_columns.push_back(col); + return *this; + } + auto operator + (Column const& col) -> Columns { + Columns combined = *this; + combined += col; + return combined; + } + + inline friend std::ostream& operator << (std::ostream& os, Columns const& cols) { + + bool first = true; + for (auto line : cols) { + if (first) + first = false; + else + os << "\n"; + os << line; + } + return os; + } + + auto toString() const -> std::string { + std::ostringstream oss; + oss << *this; + return oss.str(); + } +}; + +inline auto Column::operator + (Column const& other) -> Columns { + Columns cols; + cols += *this; + cols += other; + return cols; +} +} + +} +} + +// ----------- end of #include from clara_textflow.hpp ----------- +// ........... back in clara.hpp + +#include +#include +#include +#include +#include + +#if !defined(CATCH_PLATFORM_WINDOWS) && ( defined(WIN32) || defined(__WIN32__) || defined(_WIN32) || defined(_MSC_VER) ) +#define CATCH_PLATFORM_WINDOWS +#endif + +namespace Catch { namespace clara { +namespace detail { + + // Traits for extracting arg and return type of lambdas (for single argument lambdas) + template + struct UnaryLambdaTraits : UnaryLambdaTraits {}; + + template + struct UnaryLambdaTraits { + static const bool isValid = false; + }; + + template + struct UnaryLambdaTraits { + static const bool isValid = true; + using ArgType = typename std::remove_const::type>::type; + using ReturnType = ReturnT; + }; + + class TokenStream; + + // Transport for raw args (copied from main args, or supplied via init list for testing) + class Args { + friend TokenStream; + std::string m_exeName; + std::vector m_args; + + public: + Args( int argc, char const* const* argv ) + : m_exeName(argv[0]), + m_args(argv + 1, argv + argc) {} + + Args( std::initializer_list args ) + : m_exeName( *args.begin() ), + m_args( args.begin()+1, args.end() ) + {} + + auto exeName() const -> std::string { + return m_exeName; + } + }; + + // Wraps a token coming from a token stream. These may not directly correspond to strings as a single string + // may encode an option + its argument if the : or = form is used + enum class TokenType { + Option, Argument + }; + struct Token { + TokenType type; + std::string token; + }; + + inline auto isOptPrefix( char c ) -> bool { + return c == '-' +#ifdef CATCH_PLATFORM_WINDOWS + || c == '/' +#endif + ; + } + + // Abstracts iterators into args as a stream of tokens, with option arguments uniformly handled + class TokenStream { + using Iterator = std::vector::const_iterator; + Iterator it; + Iterator itEnd; + std::vector m_tokenBuffer; + + void loadBuffer() { + m_tokenBuffer.resize( 0 ); + + // Skip any empty strings + while( it != itEnd && it->empty() ) + ++it; + + if( it != itEnd ) { + auto const &next = *it; + if( isOptPrefix( next[0] ) ) { + auto delimiterPos = next.find_first_of( " :=" ); + if( delimiterPos != std::string::npos ) { + m_tokenBuffer.push_back( { TokenType::Option, next.substr( 0, delimiterPos ) } ); + m_tokenBuffer.push_back( { TokenType::Argument, next.substr( delimiterPos + 1 ) } ); + } else { + if( next[1] != '-' && next.size() > 2 ) { + std::string opt = "- "; + for( size_t i = 1; i < next.size(); ++i ) { + opt[1] = next[i]; + m_tokenBuffer.push_back( { TokenType::Option, opt } ); + } + } else { + m_tokenBuffer.push_back( { TokenType::Option, next } ); + } + } + } else { + m_tokenBuffer.push_back( { TokenType::Argument, next } ); + } + } + } + + public: + explicit TokenStream( Args const &args ) : TokenStream( args.m_args.begin(), args.m_args.end() ) {} + + TokenStream( Iterator it, Iterator itEnd ) : it( it ), itEnd( itEnd ) { + loadBuffer(); + } + + explicit operator bool() const { + return !m_tokenBuffer.empty() || it != itEnd; + } + + auto count() const -> size_t { return m_tokenBuffer.size() + (itEnd - it); } + + auto operator*() const -> Token { + assert( !m_tokenBuffer.empty() ); + return m_tokenBuffer.front(); + } + + auto operator->() const -> Token const * { + assert( !m_tokenBuffer.empty() ); + return &m_tokenBuffer.front(); + } + + auto operator++() -> TokenStream & { + if( m_tokenBuffer.size() >= 2 ) { + m_tokenBuffer.erase( m_tokenBuffer.begin() ); + } else { + if( it != itEnd ) + ++it; + loadBuffer(); + } + return *this; + } + }; + + class ResultBase { + public: + enum Type { + Ok, LogicError, RuntimeError + }; + + protected: + ResultBase( Type type ) : m_type( type ) {} + virtual ~ResultBase() = default; + + virtual void enforceOk() const = 0; + + Type m_type; + }; + + template + class ResultValueBase : public ResultBase { + public: + auto value() const -> T const & { + enforceOk(); + return m_value; + } + + protected: + ResultValueBase( Type type ) : ResultBase( type ) {} + + ResultValueBase( ResultValueBase const &other ) : ResultBase( other ) { + if( m_type == ResultBase::Ok ) + new( &m_value ) T( other.m_value ); + } + + ResultValueBase( Type, T const &value ) : ResultBase( Ok ) { + new( &m_value ) T( value ); + } + + auto operator=( ResultValueBase const &other ) -> ResultValueBase & { + if( m_type == ResultBase::Ok ) + m_value.~T(); + ResultBase::operator=(other); + if( m_type == ResultBase::Ok ) + new( &m_value ) T( other.m_value ); + return *this; + } + + ~ResultValueBase() override { + if( m_type == Ok ) + m_value.~T(); + } + + union { + T m_value; + }; + }; + + template<> + class ResultValueBase : public ResultBase { + protected: + using ResultBase::ResultBase; + }; + + template + class BasicResult : public ResultValueBase { + public: + template + explicit BasicResult( BasicResult const &other ) + : ResultValueBase( other.type() ), + m_errorMessage( other.errorMessage() ) + { + assert( type() != ResultBase::Ok ); + } + + template + static auto ok( U const &value ) -> BasicResult { return { ResultBase::Ok, value }; } + static auto ok() -> BasicResult { return { ResultBase::Ok }; } + static auto logicError( std::string const &message ) -> BasicResult { return { ResultBase::LogicError, message }; } + static auto runtimeError( std::string const &message ) -> BasicResult { return { ResultBase::RuntimeError, message }; } + + explicit operator bool() const { return m_type == ResultBase::Ok; } + auto type() const -> ResultBase::Type { return m_type; } + auto errorMessage() const -> std::string { return m_errorMessage; } + + protected: + void enforceOk() const override { + + // Errors shouldn't reach this point, but if they do + // the actual error message will be in m_errorMessage + assert( m_type != ResultBase::LogicError ); + assert( m_type != ResultBase::RuntimeError ); + if( m_type != ResultBase::Ok ) + std::abort(); + } + + std::string m_errorMessage; // Only populated if resultType is an error + + BasicResult( ResultBase::Type type, std::string const &message ) + : ResultValueBase(type), + m_errorMessage(message) + { + assert( m_type != ResultBase::Ok ); + } + + using ResultValueBase::ResultValueBase; + using ResultBase::m_type; + }; + + enum class ParseResultType { + Matched, NoMatch, ShortCircuitAll, ShortCircuitSame + }; + + class ParseState { + public: + + ParseState( ParseResultType type, TokenStream const &remainingTokens ) + : m_type(type), + m_remainingTokens( remainingTokens ) + {} + + auto type() const -> ParseResultType { return m_type; } + auto remainingTokens() const -> TokenStream { return m_remainingTokens; } + + private: + ParseResultType m_type; + TokenStream m_remainingTokens; + }; + + using Result = BasicResult; + using ParserResult = BasicResult; + using InternalParseResult = BasicResult; + + struct HelpColumns { + std::string left; + std::string right; + }; + + template + inline auto convertInto( std::string const &source, T& target ) -> ParserResult { + std::stringstream ss; + ss << source; + ss >> target; + if( ss.fail() ) + return ParserResult::runtimeError( "Unable to convert '" + source + "' to destination type" ); + else + return ParserResult::ok( ParseResultType::Matched ); + } + inline auto convertInto( std::string const &source, std::string& target ) -> ParserResult { + target = source; + return ParserResult::ok( ParseResultType::Matched ); + } + inline auto convertInto( std::string const &source, bool &target ) -> ParserResult { + std::string srcLC = source; + std::transform( srcLC.begin(), srcLC.end(), srcLC.begin(), []( char c ) { return static_cast( std::tolower(c) ); } ); + if (srcLC == "y" || srcLC == "1" || srcLC == "true" || srcLC == "yes" || srcLC == "on") + target = true; + else if (srcLC == "n" || srcLC == "0" || srcLC == "false" || srcLC == "no" || srcLC == "off") + target = false; + else + return ParserResult::runtimeError( "Expected a boolean value but did not recognise: '" + source + "'" ); + return ParserResult::ok( ParseResultType::Matched ); + } +#ifdef CLARA_CONFIG_OPTIONAL_TYPE + template + inline auto convertInto( std::string const &source, CLARA_CONFIG_OPTIONAL_TYPE& target ) -> ParserResult { + T temp; + auto result = convertInto( source, temp ); + if( result ) + target = std::move(temp); + return result; + } +#endif // CLARA_CONFIG_OPTIONAL_TYPE + + struct NonCopyable { + NonCopyable() = default; + NonCopyable( NonCopyable const & ) = delete; + NonCopyable( NonCopyable && ) = delete; + NonCopyable &operator=( NonCopyable const & ) = delete; + NonCopyable &operator=( NonCopyable && ) = delete; + }; + + struct BoundRef : NonCopyable { + virtual ~BoundRef() = default; + virtual auto isContainer() const -> bool { return false; } + virtual auto isFlag() const -> bool { return false; } + }; + struct BoundValueRefBase : BoundRef { + virtual auto setValue( std::string const &arg ) -> ParserResult = 0; + }; + struct BoundFlagRefBase : BoundRef { + virtual auto setFlag( bool flag ) -> ParserResult = 0; + virtual auto isFlag() const -> bool { return true; } + }; + + template + struct BoundValueRef : BoundValueRefBase { + T &m_ref; + + explicit BoundValueRef( T &ref ) : m_ref( ref ) {} + + auto setValue( std::string const &arg ) -> ParserResult override { + return convertInto( arg, m_ref ); + } + }; + + template + struct BoundValueRef> : BoundValueRefBase { + std::vector &m_ref; + + explicit BoundValueRef( std::vector &ref ) : m_ref( ref ) {} + + auto isContainer() const -> bool override { return true; } + + auto setValue( std::string const &arg ) -> ParserResult override { + T temp; + auto result = convertInto( arg, temp ); + if( result ) + m_ref.push_back( temp ); + return result; + } + }; + + struct BoundFlagRef : BoundFlagRefBase { + bool &m_ref; + + explicit BoundFlagRef( bool &ref ) : m_ref( ref ) {} + + auto setFlag( bool flag ) -> ParserResult override { + m_ref = flag; + return ParserResult::ok( ParseResultType::Matched ); + } + }; + + template + struct LambdaInvoker { + static_assert( std::is_same::value, "Lambda must return void or clara::ParserResult" ); + + template + static auto invoke( L const &lambda, ArgType const &arg ) -> ParserResult { + return lambda( arg ); + } + }; + + template<> + struct LambdaInvoker { + template + static auto invoke( L const &lambda, ArgType const &arg ) -> ParserResult { + lambda( arg ); + return ParserResult::ok( ParseResultType::Matched ); + } + }; + + template + inline auto invokeLambda( L const &lambda, std::string const &arg ) -> ParserResult { + ArgType temp{}; + auto result = convertInto( arg, temp ); + return !result + ? result + : LambdaInvoker::ReturnType>::invoke( lambda, temp ); + } + + template + struct BoundLambda : BoundValueRefBase { + L m_lambda; + + static_assert( UnaryLambdaTraits::isValid, "Supplied lambda must take exactly one argument" ); + explicit BoundLambda( L const &lambda ) : m_lambda( lambda ) {} + + auto setValue( std::string const &arg ) -> ParserResult override { + return invokeLambda::ArgType>( m_lambda, arg ); + } + }; + + template + struct BoundFlagLambda : BoundFlagRefBase { + L m_lambda; + + static_assert( UnaryLambdaTraits::isValid, "Supplied lambda must take exactly one argument" ); + static_assert( std::is_same::ArgType, bool>::value, "flags must be boolean" ); + + explicit BoundFlagLambda( L const &lambda ) : m_lambda( lambda ) {} + + auto setFlag( bool flag ) -> ParserResult override { + return LambdaInvoker::ReturnType>::invoke( m_lambda, flag ); + } + }; + + enum class Optionality { Optional, Required }; + + struct Parser; + + class ParserBase { + public: + virtual ~ParserBase() = default; + virtual auto validate() const -> Result { return Result::ok(); } + virtual auto parse( std::string const& exeName, TokenStream const &tokens) const -> InternalParseResult = 0; + virtual auto cardinality() const -> size_t { return 1; } + + auto parse( Args const &args ) const -> InternalParseResult { + return parse( args.exeName(), TokenStream( args ) ); + } + }; + + template + class ComposableParserImpl : public ParserBase { + public: + template + auto operator|( T const &other ) const -> Parser; + + template + auto operator+( T const &other ) const -> Parser; + }; + + // Common code and state for Args and Opts + template + class ParserRefImpl : public ComposableParserImpl { + protected: + Optionality m_optionality = Optionality::Optional; + std::shared_ptr m_ref; + std::string m_hint; + std::string m_description; + + explicit ParserRefImpl( std::shared_ptr const &ref ) : m_ref( ref ) {} + + public: + template + ParserRefImpl( T &ref, std::string const &hint ) + : m_ref( std::make_shared>( ref ) ), + m_hint( hint ) + {} + + template + ParserRefImpl( LambdaT const &ref, std::string const &hint ) + : m_ref( std::make_shared>( ref ) ), + m_hint(hint) + {} + + auto operator()( std::string const &description ) -> DerivedT & { + m_description = description; + return static_cast( *this ); + } + + auto optional() -> DerivedT & { + m_optionality = Optionality::Optional; + return static_cast( *this ); + }; + + auto required() -> DerivedT & { + m_optionality = Optionality::Required; + return static_cast( *this ); + }; + + auto isOptional() const -> bool { + return m_optionality == Optionality::Optional; + } + + auto cardinality() const -> size_t override { + if( m_ref->isContainer() ) + return 0; + else + return 1; + } + + auto hint() const -> std::string { return m_hint; } + }; + + class ExeName : public ComposableParserImpl { + std::shared_ptr m_name; + std::shared_ptr m_ref; + + template + static auto makeRef(LambdaT const &lambda) -> std::shared_ptr { + return std::make_shared>( lambda) ; + } + + public: + ExeName() : m_name( std::make_shared( "" ) ) {} + + explicit ExeName( std::string &ref ) : ExeName() { + m_ref = std::make_shared>( ref ); + } + + template + explicit ExeName( LambdaT const& lambda ) : ExeName() { + m_ref = std::make_shared>( lambda ); + } + + // The exe name is not parsed out of the normal tokens, but is handled specially + auto parse( std::string const&, TokenStream const &tokens ) const -> InternalParseResult override { + return InternalParseResult::ok( ParseState( ParseResultType::NoMatch, tokens ) ); + } + + auto name() const -> std::string { return *m_name; } + auto set( std::string const& newName ) -> ParserResult { + + auto lastSlash = newName.find_last_of( "\\/" ); + auto filename = ( lastSlash == std::string::npos ) + ? newName + : newName.substr( lastSlash+1 ); + + *m_name = filename; + if( m_ref ) + return m_ref->setValue( filename ); + else + return ParserResult::ok( ParseResultType::Matched ); + } + }; + + class Arg : public ParserRefImpl { + public: + using ParserRefImpl::ParserRefImpl; + + auto parse( std::string const &, TokenStream const &tokens ) const -> InternalParseResult override { + auto validationResult = validate(); + if( !validationResult ) + return InternalParseResult( validationResult ); + + auto remainingTokens = tokens; + auto const &token = *remainingTokens; + if( token.type != TokenType::Argument ) + return InternalParseResult::ok( ParseState( ParseResultType::NoMatch, remainingTokens ) ); + + assert( !m_ref->isFlag() ); + auto valueRef = static_cast( m_ref.get() ); + + auto result = valueRef->setValue( remainingTokens->token ); + if( !result ) + return InternalParseResult( result ); + else + return InternalParseResult::ok( ParseState( ParseResultType::Matched, ++remainingTokens ) ); + } + }; + + inline auto normaliseOpt( std::string const &optName ) -> std::string { +#ifdef CATCH_PLATFORM_WINDOWS + if( optName[0] == '/' ) + return "-" + optName.substr( 1 ); + else +#endif + return optName; + } + + class Opt : public ParserRefImpl { + protected: + std::vector m_optNames; + + public: + template + explicit Opt( LambdaT const &ref ) : ParserRefImpl( std::make_shared>( ref ) ) {} + + explicit Opt( bool &ref ) : ParserRefImpl( std::make_shared( ref ) ) {} + + template + Opt( LambdaT const &ref, std::string const &hint ) : ParserRefImpl( ref, hint ) {} + + template + Opt( T &ref, std::string const &hint ) : ParserRefImpl( ref, hint ) {} + + auto operator[]( std::string const &optName ) -> Opt & { + m_optNames.push_back( optName ); + return *this; + } + + auto getHelpColumns() const -> std::vector { + std::ostringstream oss; + bool first = true; + for( auto const &opt : m_optNames ) { + if (first) + first = false; + else + oss << ", "; + oss << opt; + } + if( !m_hint.empty() ) + oss << " <" << m_hint << ">"; + return { { oss.str(), m_description } }; + } + + auto isMatch( std::string const &optToken ) const -> bool { + auto normalisedToken = normaliseOpt( optToken ); + for( auto const &name : m_optNames ) { + if( normaliseOpt( name ) == normalisedToken ) + return true; + } + return false; + } + + using ParserBase::parse; + + auto parse( std::string const&, TokenStream const &tokens ) const -> InternalParseResult override { + auto validationResult = validate(); + if( !validationResult ) + return InternalParseResult( validationResult ); + + auto remainingTokens = tokens; + if( remainingTokens && remainingTokens->type == TokenType::Option ) { + auto const &token = *remainingTokens; + if( isMatch(token.token ) ) { + if( m_ref->isFlag() ) { + auto flagRef = static_cast( m_ref.get() ); + auto result = flagRef->setFlag( true ); + if( !result ) + return InternalParseResult( result ); + if( result.value() == ParseResultType::ShortCircuitAll ) + return InternalParseResult::ok( ParseState( result.value(), remainingTokens ) ); + } else { + auto valueRef = static_cast( m_ref.get() ); + ++remainingTokens; + if( !remainingTokens ) + return InternalParseResult::runtimeError( "Expected argument following " + token.token ); + auto const &argToken = *remainingTokens; + if( argToken.type != TokenType::Argument ) + return InternalParseResult::runtimeError( "Expected argument following " + token.token ); + auto result = valueRef->setValue( argToken.token ); + if( !result ) + return InternalParseResult( result ); + if( result.value() == ParseResultType::ShortCircuitAll ) + return InternalParseResult::ok( ParseState( result.value(), remainingTokens ) ); + } + return InternalParseResult::ok( ParseState( ParseResultType::Matched, ++remainingTokens ) ); + } + } + return InternalParseResult::ok( ParseState( ParseResultType::NoMatch, remainingTokens ) ); + } + + auto validate() const -> Result override { + if( m_optNames.empty() ) + return Result::logicError( "No options supplied to Opt" ); + for( auto const &name : m_optNames ) { + if( name.empty() ) + return Result::logicError( "Option name cannot be empty" ); +#ifdef CATCH_PLATFORM_WINDOWS + if( name[0] != '-' && name[0] != '/' ) + return Result::logicError( "Option name must begin with '-' or '/'" ); +#else + if( name[0] != '-' ) + return Result::logicError( "Option name must begin with '-'" ); +#endif + } + return ParserRefImpl::validate(); + } + }; + + struct Help : Opt { + Help( bool &showHelpFlag ) + : Opt([&]( bool flag ) { + showHelpFlag = flag; + return ParserResult::ok( ParseResultType::ShortCircuitAll ); + }) + { + static_cast( *this ) + ("display usage information") + ["-?"]["-h"]["--help"] + .optional(); + } + }; + + struct Parser : ParserBase { + + mutable ExeName m_exeName; + std::vector m_options; + std::vector m_args; + + auto operator|=( ExeName const &exeName ) -> Parser & { + m_exeName = exeName; + return *this; + } + + auto operator|=( Arg const &arg ) -> Parser & { + m_args.push_back(arg); + return *this; + } + + auto operator|=( Opt const &opt ) -> Parser & { + m_options.push_back(opt); + return *this; + } + + auto operator|=( Parser const &other ) -> Parser & { + m_options.insert(m_options.end(), other.m_options.begin(), other.m_options.end()); + m_args.insert(m_args.end(), other.m_args.begin(), other.m_args.end()); + return *this; + } + + template + auto operator|( T const &other ) const -> Parser { + return Parser( *this ) |= other; + } + + // Forward deprecated interface with '+' instead of '|' + template + auto operator+=( T const &other ) -> Parser & { return operator|=( other ); } + template + auto operator+( T const &other ) const -> Parser { return operator|( other ); } + + auto getHelpColumns() const -> std::vector { + std::vector cols; + for (auto const &o : m_options) { + auto childCols = o.getHelpColumns(); + cols.insert( cols.end(), childCols.begin(), childCols.end() ); + } + return cols; + } + + void writeToStream( std::ostream &os ) const { + if (!m_exeName.name().empty()) { + os << "usage:\n" << " " << m_exeName.name() << " "; + bool required = true, first = true; + for( auto const &arg : m_args ) { + if (first) + first = false; + else + os << " "; + if( arg.isOptional() && required ) { + os << "["; + required = false; + } + os << "<" << arg.hint() << ">"; + if( arg.cardinality() == 0 ) + os << " ... "; + } + if( !required ) + os << "]"; + if( !m_options.empty() ) + os << " options"; + os << "\n\nwhere options are:" << std::endl; + } + + auto rows = getHelpColumns(); + size_t consoleWidth = CATCH_CLARA_CONFIG_CONSOLE_WIDTH; + size_t optWidth = 0; + for( auto const &cols : rows ) + optWidth = (std::max)(optWidth, cols.left.size() + 2); + + optWidth = (std::min)(optWidth, consoleWidth/2); + + for( auto const &cols : rows ) { + auto row = + TextFlow::Column( cols.left ).width( optWidth ).indent( 2 ) + + TextFlow::Spacer(4) + + TextFlow::Column( cols.right ).width( consoleWidth - 7 - optWidth ); + os << row << std::endl; + } + } + + friend auto operator<<( std::ostream &os, Parser const &parser ) -> std::ostream& { + parser.writeToStream( os ); + return os; + } + + auto validate() const -> Result override { + for( auto const &opt : m_options ) { + auto result = opt.validate(); + if( !result ) + return result; + } + for( auto const &arg : m_args ) { + auto result = arg.validate(); + if( !result ) + return result; + } + return Result::ok(); + } + + using ParserBase::parse; + + auto parse( std::string const& exeName, TokenStream const &tokens ) const -> InternalParseResult override { + + struct ParserInfo { + ParserBase const* parser = nullptr; + size_t count = 0; + }; + const size_t totalParsers = m_options.size() + m_args.size(); + assert( totalParsers < 512 ); + // ParserInfo parseInfos[totalParsers]; // <-- this is what we really want to do + ParserInfo parseInfos[512]; + + { + size_t i = 0; + for (auto const &opt : m_options) parseInfos[i++].parser = &opt; + for (auto const &arg : m_args) parseInfos[i++].parser = &arg; + } + + m_exeName.set( exeName ); + + auto result = InternalParseResult::ok( ParseState( ParseResultType::NoMatch, tokens ) ); + while( result.value().remainingTokens() ) { + bool tokenParsed = false; + + for( size_t i = 0; i < totalParsers; ++i ) { + auto& parseInfo = parseInfos[i]; + if( parseInfo.parser->cardinality() == 0 || parseInfo.count < parseInfo.parser->cardinality() ) { + result = parseInfo.parser->parse(exeName, result.value().remainingTokens()); + if (!result) + return result; + if (result.value().type() != ParseResultType::NoMatch) { + tokenParsed = true; + ++parseInfo.count; + break; + } + } + } + + if( result.value().type() == ParseResultType::ShortCircuitAll ) + return result; + if( !tokenParsed ) + return InternalParseResult::runtimeError( "Unrecognised token: " + result.value().remainingTokens()->token ); + } + // !TBD Check missing required options + return result; + } + }; + + template + template + auto ComposableParserImpl::operator|( T const &other ) const -> Parser { + return Parser() | static_cast( *this ) | other; + } +} // namespace detail + +// A Combined parser +using detail::Parser; + +// A parser for options +using detail::Opt; + +// A parser for arguments +using detail::Arg; + +// Wrapper for argc, argv from main() +using detail::Args; + +// Specifies the name of the executable +using detail::ExeName; + +// Convenience wrapper for option parser that specifies the help option +using detail::Help; + +// enum of result types from a parse +using detail::ParseResultType; + +// Result type for parser operation +using detail::ParserResult; + +}} // namespace Catch::clara + +// end clara.hpp +#ifdef __clang__ +#pragma clang diagnostic pop +#endif + +// Restore Clara's value for console width, if present +#ifdef CATCH_TEMP_CLARA_CONFIG_CONSOLE_WIDTH +#define CATCH_CLARA_TEXTFLOW_CONFIG_CONSOLE_WIDTH CATCH_TEMP_CLARA_CONFIG_CONSOLE_WIDTH +#undef CATCH_TEMP_CLARA_CONFIG_CONSOLE_WIDTH +#endif + +// end catch_clara.h +namespace Catch { + + clara::Parser makeCommandLineParser( ConfigData& config ); + +} // end namespace Catch + +// end catch_commandline.h +#include +#include + +namespace Catch { + + clara::Parser makeCommandLineParser( ConfigData& config ) { + + using namespace clara; + + auto const setWarning = [&]( std::string const& warning ) { + auto warningSet = [&]() { + if( warning == "NoAssertions" ) + return WarnAbout::NoAssertions; + + if ( warning == "NoTests" ) + return WarnAbout::NoTests; + + return WarnAbout::Nothing; + }(); + + if (warningSet == WarnAbout::Nothing) + return ParserResult::runtimeError( "Unrecognised warning: '" + warning + "'" ); + config.warnings = static_cast( config.warnings | warningSet ); + return ParserResult::ok( ParseResultType::Matched ); + }; + auto const loadTestNamesFromFile = [&]( std::string const& filename ) { + std::ifstream f( filename.c_str() ); + if( !f.is_open() ) + return ParserResult::runtimeError( "Unable to load input file: '" + filename + "'" ); + + std::string line; + while( std::getline( f, line ) ) { + line = trim(line); + if( !line.empty() && !startsWith( line, '#' ) ) { + if( !startsWith( line, '"' ) ) + line = '"' + line + '"'; + config.testsOrTags.push_back( line + ',' ); + } + } + return ParserResult::ok( ParseResultType::Matched ); + }; + auto const setTestOrder = [&]( std::string const& order ) { + if( startsWith( "declared", order ) ) + config.runOrder = RunTests::InDeclarationOrder; + else if( startsWith( "lexical", order ) ) + config.runOrder = RunTests::InLexicographicalOrder; + else if( startsWith( "random", order ) ) + config.runOrder = RunTests::InRandomOrder; + else + return clara::ParserResult::runtimeError( "Unrecognised ordering: '" + order + "'" ); + return ParserResult::ok( ParseResultType::Matched ); + }; + auto const setRngSeed = [&]( std::string const& seed ) { + if( seed != "time" ) + return clara::detail::convertInto( seed, config.rngSeed ); + config.rngSeed = static_cast( std::time(nullptr) ); + return ParserResult::ok( ParseResultType::Matched ); + }; + auto const setColourUsage = [&]( std::string const& useColour ) { + auto mode = toLower( useColour ); + + if( mode == "yes" ) + config.useColour = UseColour::Yes; + else if( mode == "no" ) + config.useColour = UseColour::No; + else if( mode == "auto" ) + config.useColour = UseColour::Auto; + else + return ParserResult::runtimeError( "colour mode must be one of: auto, yes or no. '" + useColour + "' not recognised" ); + return ParserResult::ok( ParseResultType::Matched ); + }; + auto const setWaitForKeypress = [&]( std::string const& keypress ) { + auto keypressLc = toLower( keypress ); + if( keypressLc == "start" ) + config.waitForKeypress = WaitForKeypress::BeforeStart; + else if( keypressLc == "exit" ) + config.waitForKeypress = WaitForKeypress::BeforeExit; + else if( keypressLc == "both" ) + config.waitForKeypress = WaitForKeypress::BeforeStartAndExit; + else + return ParserResult::runtimeError( "keypress argument must be one of: start, exit or both. '" + keypress + "' not recognised" ); + return ParserResult::ok( ParseResultType::Matched ); + }; + auto const setVerbosity = [&]( std::string const& verbosity ) { + auto lcVerbosity = toLower( verbosity ); + if( lcVerbosity == "quiet" ) + config.verbosity = Verbosity::Quiet; + else if( lcVerbosity == "normal" ) + config.verbosity = Verbosity::Normal; + else if( lcVerbosity == "high" ) + config.verbosity = Verbosity::High; + else + return ParserResult::runtimeError( "Unrecognised verbosity, '" + verbosity + "'" ); + return ParserResult::ok( ParseResultType::Matched ); + }; + auto const setReporter = [&]( std::string const& reporter ) { + IReporterRegistry::FactoryMap const& factories = getRegistryHub().getReporterRegistry().getFactories(); + + auto lcReporter = toLower( reporter ); + auto result = factories.find( lcReporter ); + + if( factories.end() != result ) + config.reporterName = lcReporter; + else + return ParserResult::runtimeError( "Unrecognized reporter, '" + reporter + "'. Check available with --list-reporters" ); + return ParserResult::ok( ParseResultType::Matched ); + }; + + auto cli + = ExeName( config.processName ) + | Help( config.showHelp ) + | Opt( config.listTests ) + ["-l"]["--list-tests"] + ( "list all/matching test cases" ) + | Opt( config.listTags ) + ["-t"]["--list-tags"] + ( "list all/matching tags" ) + | Opt( config.showSuccessfulTests ) + ["-s"]["--success"] + ( "include successful tests in output" ) + | Opt( config.shouldDebugBreak ) + ["-b"]["--break"] + ( "break into debugger on failure" ) + | Opt( config.noThrow ) + ["-e"]["--nothrow"] + ( "skip exception tests" ) + | Opt( config.showInvisibles ) + ["-i"]["--invisibles"] + ( "show invisibles (tabs, newlines)" ) + | Opt( config.outputFilename, "filename" ) + ["-o"]["--out"] + ( "output filename" ) + | Opt( setReporter, "name" ) + ["-r"]["--reporter"] + ( "reporter to use (defaults to console)" ) + | Opt( config.name, "name" ) + ["-n"]["--name"] + ( "suite name" ) + | Opt( [&]( bool ){ config.abortAfter = 1; } ) + ["-a"]["--abort"] + ( "abort at first failure" ) + | Opt( [&]( int x ){ config.abortAfter = x; }, "no. failures" ) + ["-x"]["--abortx"] + ( "abort after x failures" ) + | Opt( setWarning, "warning name" ) + ["-w"]["--warn"] + ( "enable warnings" ) + | Opt( [&]( bool flag ) { config.showDurations = flag ? ShowDurations::Always : ShowDurations::Never; }, "yes|no" ) + ["-d"]["--durations"] + ( "show test durations" ) + | Opt( loadTestNamesFromFile, "filename" ) + ["-f"]["--input-file"] + ( "load test names to run from a file" ) + | Opt( config.filenamesAsTags ) + ["-#"]["--filenames-as-tags"] + ( "adds a tag for the filename" ) + | Opt( config.sectionsToRun, "section name" ) + ["-c"]["--section"] + ( "specify section to run" ) + | Opt( setVerbosity, "quiet|normal|high" ) + ["-v"]["--verbosity"] + ( "set output verbosity" ) + | Opt( config.listTestNamesOnly ) + ["--list-test-names-only"] + ( "list all/matching test cases names only" ) + | Opt( config.listReporters ) + ["--list-reporters"] + ( "list all reporters" ) + | Opt( setTestOrder, "decl|lex|rand" ) + ["--order"] + ( "test case order (defaults to decl)" ) + | Opt( setRngSeed, "'time'|number" ) + ["--rng-seed"] + ( "set a specific seed for random numbers" ) + | Opt( setColourUsage, "yes|no" ) + ["--use-colour"] + ( "should output be colourised" ) + | Opt( config.libIdentify ) + ["--libidentify"] + ( "report name and version according to libidentify standard" ) + | Opt( setWaitForKeypress, "start|exit|both" ) + ["--wait-for-keypress"] + ( "waits for a keypress before exiting" ) + | Opt( config.benchmarkResolutionMultiple, "multiplier" ) + ["--benchmark-resolution-multiple"] + ( "multiple of clock resolution to run benchmarks" ) + + | Arg( config.testsOrTags, "test name|pattern|tags" ) + ( "which test or tests to use" ); + + return cli; + } + +} // end namespace Catch +// end catch_commandline.cpp +// start catch_common.cpp + +#include +#include + +namespace Catch { + + bool SourceLineInfo::empty() const noexcept { + return file[0] == '\0'; + } + bool SourceLineInfo::operator == ( SourceLineInfo const& other ) const noexcept { + return line == other.line && (file == other.file || std::strcmp(file, other.file) == 0); + } + bool SourceLineInfo::operator < ( SourceLineInfo const& other ) const noexcept { + // We can assume that the same file will usually have the same pointer. + // Thus, if the pointers are the same, there is no point in calling the strcmp + return line < other.line || ( line == other.line && file != other.file && (std::strcmp(file, other.file) < 0)); + } + + std::ostream& operator << ( std::ostream& os, SourceLineInfo const& info ) { +#ifndef __GNUG__ + os << info.file << '(' << info.line << ')'; +#else + os << info.file << ':' << info.line; +#endif + return os; + } + + std::string StreamEndStop::operator+() const { + return std::string(); + } + + NonCopyable::NonCopyable() = default; + NonCopyable::~NonCopyable() = default; + +} +// end catch_common.cpp +// start catch_config.cpp + +namespace Catch { + + Config::Config( ConfigData const& data ) + : m_data( data ), + m_stream( openStream() ) + { + TestSpecParser parser(ITagAliasRegistry::get()); + if (data.testsOrTags.empty()) { + parser.parse("~[.]"); // All not hidden tests + } + else { + m_hasTestFilters = true; + for( auto const& testOrTags : data.testsOrTags ) + parser.parse( testOrTags ); + } + m_testSpec = parser.testSpec(); + } + + std::string const& Config::getFilename() const { + return m_data.outputFilename ; + } + + bool Config::listTests() const { return m_data.listTests; } + bool Config::listTestNamesOnly() const { return m_data.listTestNamesOnly; } + bool Config::listTags() const { return m_data.listTags; } + bool Config::listReporters() const { return m_data.listReporters; } + + std::string Config::getProcessName() const { return m_data.processName; } + std::string const& Config::getReporterName() const { return m_data.reporterName; } + + std::vector const& Config::getTestsOrTags() const { return m_data.testsOrTags; } + std::vector const& Config::getSectionsToRun() const { return m_data.sectionsToRun; } + + TestSpec const& Config::testSpec() const { return m_testSpec; } + bool Config::hasTestFilters() const { return m_hasTestFilters; } + + bool Config::showHelp() const { return m_data.showHelp; } + + // IConfig interface + bool Config::allowThrows() const { return !m_data.noThrow; } + std::ostream& Config::stream() const { return m_stream->stream(); } + std::string Config::name() const { return m_data.name.empty() ? m_data.processName : m_data.name; } + bool Config::includeSuccessfulResults() const { return m_data.showSuccessfulTests; } + bool Config::warnAboutMissingAssertions() const { return !!(m_data.warnings & WarnAbout::NoAssertions); } + bool Config::warnAboutNoTests() const { return !!(m_data.warnings & WarnAbout::NoTests); } + ShowDurations::OrNot Config::showDurations() const { return m_data.showDurations; } + RunTests::InWhatOrder Config::runOrder() const { return m_data.runOrder; } + unsigned int Config::rngSeed() const { return m_data.rngSeed; } + int Config::benchmarkResolutionMultiple() const { return m_data.benchmarkResolutionMultiple; } + UseColour::YesOrNo Config::useColour() const { return m_data.useColour; } + bool Config::shouldDebugBreak() const { return m_data.shouldDebugBreak; } + int Config::abortAfter() const { return m_data.abortAfter; } + bool Config::showInvisibles() const { return m_data.showInvisibles; } + Verbosity Config::verbosity() const { return m_data.verbosity; } + + IStream const* Config::openStream() { + return Catch::makeStream(m_data.outputFilename); + } + +} // end namespace Catch +// end catch_config.cpp +// start catch_console_colour.cpp + +#if defined(__clang__) +# pragma clang diagnostic push +# pragma clang diagnostic ignored "-Wexit-time-destructors" +#endif + +// start catch_errno_guard.h + +namespace Catch { + + class ErrnoGuard { + public: + ErrnoGuard(); + ~ErrnoGuard(); + private: + int m_oldErrno; + }; + +} + +// end catch_errno_guard.h +#include + +namespace Catch { + namespace { + + struct IColourImpl { + virtual ~IColourImpl() = default; + virtual void use( Colour::Code _colourCode ) = 0; + }; + + struct NoColourImpl : IColourImpl { + void use( Colour::Code ) {} + + static IColourImpl* instance() { + static NoColourImpl s_instance; + return &s_instance; + } + }; + + } // anon namespace +} // namespace Catch + +#if !defined( CATCH_CONFIG_COLOUR_NONE ) && !defined( CATCH_CONFIG_COLOUR_WINDOWS ) && !defined( CATCH_CONFIG_COLOUR_ANSI ) +# ifdef CATCH_PLATFORM_WINDOWS +# define CATCH_CONFIG_COLOUR_WINDOWS +# else +# define CATCH_CONFIG_COLOUR_ANSI +# endif +#endif + +#if defined ( CATCH_CONFIG_COLOUR_WINDOWS ) ///////////////////////////////////////// + +namespace Catch { +namespace { + + class Win32ColourImpl : public IColourImpl { + public: + Win32ColourImpl() : stdoutHandle( GetStdHandle(STD_OUTPUT_HANDLE) ) + { + CONSOLE_SCREEN_BUFFER_INFO csbiInfo; + GetConsoleScreenBufferInfo( stdoutHandle, &csbiInfo ); + originalForegroundAttributes = csbiInfo.wAttributes & ~( BACKGROUND_GREEN | BACKGROUND_RED | BACKGROUND_BLUE | BACKGROUND_INTENSITY ); + originalBackgroundAttributes = csbiInfo.wAttributes & ~( FOREGROUND_GREEN | FOREGROUND_RED | FOREGROUND_BLUE | FOREGROUND_INTENSITY ); + } + + virtual void use( Colour::Code _colourCode ) override { + switch( _colourCode ) { + case Colour::None: return setTextAttribute( originalForegroundAttributes ); + case Colour::White: return setTextAttribute( FOREGROUND_GREEN | FOREGROUND_RED | FOREGROUND_BLUE ); + case Colour::Red: return setTextAttribute( FOREGROUND_RED ); + case Colour::Green: return setTextAttribute( FOREGROUND_GREEN ); + case Colour::Blue: return setTextAttribute( FOREGROUND_BLUE ); + case Colour::Cyan: return setTextAttribute( FOREGROUND_BLUE | FOREGROUND_GREEN ); + case Colour::Yellow: return setTextAttribute( FOREGROUND_RED | FOREGROUND_GREEN ); + case Colour::Grey: return setTextAttribute( 0 ); + + case Colour::LightGrey: return setTextAttribute( FOREGROUND_INTENSITY ); + case Colour::BrightRed: return setTextAttribute( FOREGROUND_INTENSITY | FOREGROUND_RED ); + case Colour::BrightGreen: return setTextAttribute( FOREGROUND_INTENSITY | FOREGROUND_GREEN ); + case Colour::BrightWhite: return setTextAttribute( FOREGROUND_INTENSITY | FOREGROUND_GREEN | FOREGROUND_RED | FOREGROUND_BLUE ); + case Colour::BrightYellow: return setTextAttribute( FOREGROUND_INTENSITY | FOREGROUND_RED | FOREGROUND_GREEN ); + + case Colour::Bright: CATCH_INTERNAL_ERROR( "not a colour" ); + + default: + CATCH_ERROR( "Unknown colour requested" ); + } + } + + private: + void setTextAttribute( WORD _textAttribute ) { + SetConsoleTextAttribute( stdoutHandle, _textAttribute | originalBackgroundAttributes ); + } + HANDLE stdoutHandle; + WORD originalForegroundAttributes; + WORD originalBackgroundAttributes; + }; + + IColourImpl* platformColourInstance() { + static Win32ColourImpl s_instance; + + IConfigPtr config = getCurrentContext().getConfig(); + UseColour::YesOrNo colourMode = config + ? config->useColour() + : UseColour::Auto; + if( colourMode == UseColour::Auto ) + colourMode = UseColour::Yes; + return colourMode == UseColour::Yes + ? &s_instance + : NoColourImpl::instance(); + } + +} // end anon namespace +} // end namespace Catch + +#elif defined( CATCH_CONFIG_COLOUR_ANSI ) ////////////////////////////////////// + +#include + +namespace Catch { +namespace { + + // use POSIX/ ANSI console terminal codes + // Thanks to Adam Strzelecki for original contribution + // (http://github.com/nanoant) + // https://github.com/philsquared/Catch/pull/131 + class PosixColourImpl : public IColourImpl { + public: + virtual void use( Colour::Code _colourCode ) override { + switch( _colourCode ) { + case Colour::None: + case Colour::White: return setColour( "[0m" ); + case Colour::Red: return setColour( "[0;31m" ); + case Colour::Green: return setColour( "[0;32m" ); + case Colour::Blue: return setColour( "[0;34m" ); + case Colour::Cyan: return setColour( "[0;36m" ); + case Colour::Yellow: return setColour( "[0;33m" ); + case Colour::Grey: return setColour( "[1;30m" ); + + case Colour::LightGrey: return setColour( "[0;37m" ); + case Colour::BrightRed: return setColour( "[1;31m" ); + case Colour::BrightGreen: return setColour( "[1;32m" ); + case Colour::BrightWhite: return setColour( "[1;37m" ); + case Colour::BrightYellow: return setColour( "[1;33m" ); + + case Colour::Bright: CATCH_INTERNAL_ERROR( "not a colour" ); + default: CATCH_INTERNAL_ERROR( "Unknown colour requested" ); + } + } + static IColourImpl* instance() { + static PosixColourImpl s_instance; + return &s_instance; + } + + private: + void setColour( const char* _escapeCode ) { + getCurrentContext().getConfig()->stream() + << '\033' << _escapeCode; + } + }; + + bool useColourOnPlatform() { + return +#ifdef CATCH_PLATFORM_MAC + !isDebuggerActive() && +#endif +#if !(defined(__DJGPP__) && defined(__STRICT_ANSI__)) + isatty(STDOUT_FILENO) +#else + false +#endif + ; + } + IColourImpl* platformColourInstance() { + ErrnoGuard guard; + IConfigPtr config = getCurrentContext().getConfig(); + UseColour::YesOrNo colourMode = config + ? config->useColour() + : UseColour::Auto; + if( colourMode == UseColour::Auto ) + colourMode = useColourOnPlatform() + ? UseColour::Yes + : UseColour::No; + return colourMode == UseColour::Yes + ? PosixColourImpl::instance() + : NoColourImpl::instance(); + } + +} // end anon namespace +} // end namespace Catch + +#else // not Windows or ANSI /////////////////////////////////////////////// + +namespace Catch { + + static IColourImpl* platformColourInstance() { return NoColourImpl::instance(); } + +} // end namespace Catch + +#endif // Windows/ ANSI/ None + +namespace Catch { + + Colour::Colour( Code _colourCode ) { use( _colourCode ); } + Colour::Colour( Colour&& rhs ) noexcept { + m_moved = rhs.m_moved; + rhs.m_moved = true; + } + Colour& Colour::operator=( Colour&& rhs ) noexcept { + m_moved = rhs.m_moved; + rhs.m_moved = true; + return *this; + } + + Colour::~Colour(){ if( !m_moved ) use( None ); } + + void Colour::use( Code _colourCode ) { + static IColourImpl* impl = platformColourInstance(); + impl->use( _colourCode ); + } + + std::ostream& operator << ( std::ostream& os, Colour const& ) { + return os; + } + +} // end namespace Catch + +#if defined(__clang__) +# pragma clang diagnostic pop +#endif + +// end catch_console_colour.cpp +// start catch_context.cpp + +namespace Catch { + + class Context : public IMutableContext, NonCopyable { + + public: // IContext + virtual IResultCapture* getResultCapture() override { + return m_resultCapture; + } + virtual IRunner* getRunner() override { + return m_runner; + } + + virtual IConfigPtr const& getConfig() const override { + return m_config; + } + + virtual ~Context() override; + + public: // IMutableContext + virtual void setResultCapture( IResultCapture* resultCapture ) override { + m_resultCapture = resultCapture; + } + virtual void setRunner( IRunner* runner ) override { + m_runner = runner; + } + virtual void setConfig( IConfigPtr const& config ) override { + m_config = config; + } + + friend IMutableContext& getCurrentMutableContext(); + + private: + IConfigPtr m_config; + IRunner* m_runner = nullptr; + IResultCapture* m_resultCapture = nullptr; + }; + + IMutableContext *IMutableContext::currentContext = nullptr; + + void IMutableContext::createContext() + { + currentContext = new Context(); + } + + void cleanUpContext() { + delete IMutableContext::currentContext; + IMutableContext::currentContext = nullptr; + } + IContext::~IContext() = default; + IMutableContext::~IMutableContext() = default; + Context::~Context() = default; +} +// end catch_context.cpp +// start catch_debug_console.cpp + +// start catch_debug_console.h + +#include + +namespace Catch { + void writeToDebugConsole( std::string const& text ); +} + +// end catch_debug_console.h +#ifdef CATCH_PLATFORM_WINDOWS + + namespace Catch { + void writeToDebugConsole( std::string const& text ) { + ::OutputDebugStringA( text.c_str() ); + } + } + +#else + + namespace Catch { + void writeToDebugConsole( std::string const& text ) { + // !TBD: Need a version for Mac/ XCode and other IDEs + Catch::cout() << text; + } + } + +#endif // Platform +// end catch_debug_console.cpp +// start catch_debugger.cpp + +#ifdef CATCH_PLATFORM_MAC + +# include +# include +# include +# include +# include +# include +# include + +namespace Catch { + + // The following function is taken directly from the following technical note: + // http://developer.apple.com/library/mac/#qa/qa2004/qa1361.html + + // Returns true if the current process is being debugged (either + // running under the debugger or has a debugger attached post facto). + bool isDebuggerActive(){ + + int mib[4]; + struct kinfo_proc info; + std::size_t size; + + // Initialize the flags so that, if sysctl fails for some bizarre + // reason, we get a predictable result. + + info.kp_proc.p_flag = 0; + + // Initialize mib, which tells sysctl the info we want, in this case + // we're looking for information about a specific process ID. + + mib[0] = CTL_KERN; + mib[1] = KERN_PROC; + mib[2] = KERN_PROC_PID; + mib[3] = getpid(); + + // Call sysctl. + + size = sizeof(info); + if( sysctl(mib, sizeof(mib) / sizeof(*mib), &info, &size, nullptr, 0) != 0 ) { + Catch::cerr() << "\n** Call to sysctl failed - unable to determine if debugger is active **\n" << std::endl; + return false; + } + + // We're being debugged if the P_TRACED flag is set. + + return ( (info.kp_proc.p_flag & P_TRACED) != 0 ); + } + } // namespace Catch + +#elif defined(CATCH_PLATFORM_LINUX) + #include + #include + + namespace Catch{ + // The standard POSIX way of detecting a debugger is to attempt to + // ptrace() the process, but this needs to be done from a child and not + // this process itself to still allow attaching to this process later + // if wanted, so is rather heavy. Under Linux we have the PID of the + // "debugger" (which doesn't need to be gdb, of course, it could also + // be strace, for example) in /proc/$PID/status, so just get it from + // there instead. + bool isDebuggerActive(){ + // Libstdc++ has a bug, where std::ifstream sets errno to 0 + // This way our users can properly assert over errno values + ErrnoGuard guard; + std::ifstream in("/proc/self/status"); + for( std::string line; std::getline(in, line); ) { + static const int PREFIX_LEN = 11; + if( line.compare(0, PREFIX_LEN, "TracerPid:\t") == 0 ) { + // We're traced if the PID is not 0 and no other PID starts + // with 0 digit, so it's enough to check for just a single + // character. + return line.length() > PREFIX_LEN && line[PREFIX_LEN] != '0'; + } + } + + return false; + } + } // namespace Catch +#elif defined(_MSC_VER) + extern "C" __declspec(dllimport) int __stdcall IsDebuggerPresent(); + namespace Catch { + bool isDebuggerActive() { + return IsDebuggerPresent() != 0; + } + } +#elif defined(__MINGW32__) + extern "C" __declspec(dllimport) int __stdcall IsDebuggerPresent(); + namespace Catch { + bool isDebuggerActive() { + return IsDebuggerPresent() != 0; + } + } +#else + namespace Catch { + bool isDebuggerActive() { return false; } + } +#endif // Platform +// end catch_debugger.cpp +// start catch_decomposer.cpp + +namespace Catch { + + ITransientExpression::~ITransientExpression() = default; + + void formatReconstructedExpression( std::ostream &os, std::string const& lhs, StringRef op, std::string const& rhs ) { + if( lhs.size() + rhs.size() < 40 && + lhs.find('\n') == std::string::npos && + rhs.find('\n') == std::string::npos ) + os << lhs << " " << op << " " << rhs; + else + os << lhs << "\n" << op << "\n" << rhs; + } +} +// end catch_decomposer.cpp +// start catch_enforce.cpp + +namespace Catch { +#if defined(CATCH_CONFIG_DISABLE_EXCEPTIONS) && !defined(CATCH_CONFIG_DISABLE_EXCEPTIONS_CUSTOM_HANDLER) + [[noreturn]] + void throw_exception(std::exception const& e) { + Catch::cerr() << "Catch will terminate because it needed to throw an exception.\n" + << "The message was: " << e.what() << '\n'; + std::terminate(); + } +#endif +} // namespace Catch; +// end catch_enforce.cpp +// start catch_errno_guard.cpp + +#include + +namespace Catch { + ErrnoGuard::ErrnoGuard():m_oldErrno(errno){} + ErrnoGuard::~ErrnoGuard() { errno = m_oldErrno; } +} +// end catch_errno_guard.cpp +// start catch_exception_translator_registry.cpp + +// start catch_exception_translator_registry.h + +#include +#include +#include + +namespace Catch { + + class ExceptionTranslatorRegistry : public IExceptionTranslatorRegistry { + public: + ~ExceptionTranslatorRegistry(); + virtual void registerTranslator( const IExceptionTranslator* translator ); + virtual std::string translateActiveException() const override; + std::string tryTranslators() const; + + private: + std::vector> m_translators; + }; +} + +// end catch_exception_translator_registry.h +#ifdef __OBJC__ +#import "Foundation/Foundation.h" +#endif + +namespace Catch { + + ExceptionTranslatorRegistry::~ExceptionTranslatorRegistry() { + } + + void ExceptionTranslatorRegistry::registerTranslator( const IExceptionTranslator* translator ) { + m_translators.push_back( std::unique_ptr( translator ) ); + } + +#if !defined(CATCH_CONFIG_DISABLE_EXCEPTIONS) + std::string ExceptionTranslatorRegistry::translateActiveException() const { + try { +#ifdef __OBJC__ + // In Objective-C try objective-c exceptions first + @try { + return tryTranslators(); + } + @catch (NSException *exception) { + return Catch::Detail::stringify( [exception description] ); + } +#else + // Compiling a mixed mode project with MSVC means that CLR + // exceptions will be caught in (...) as well. However, these + // do not fill-in std::current_exception and thus lead to crash + // when attempting rethrow. + // /EHa switch also causes structured exceptions to be caught + // here, but they fill-in current_exception properly, so + // at worst the output should be a little weird, instead of + // causing a crash. + if (std::current_exception() == nullptr) { + return "Non C++ exception. Possibly a CLR exception."; + } + return tryTranslators(); +#endif + } + catch( TestFailureException& ) { + std::rethrow_exception(std::current_exception()); + } + catch( std::exception& ex ) { + return ex.what(); + } + catch( std::string& msg ) { + return msg; + } + catch( const char* msg ) { + return msg; + } + catch(...) { + return "Unknown exception"; + } + } + + std::string ExceptionTranslatorRegistry::tryTranslators() const { + if (m_translators.empty()) { + std::rethrow_exception(std::current_exception()); + } else { + return m_translators[0]->translate(m_translators.begin() + 1, m_translators.end()); + } + } + +#else // ^^ Exceptions are enabled // Exceptions are disabled vv + std::string ExceptionTranslatorRegistry::translateActiveException() const { + CATCH_INTERNAL_ERROR("Attempted to translate active exception under CATCH_CONFIG_DISABLE_EXCEPTIONS!"); + } + + std::string ExceptionTranslatorRegistry::tryTranslators() const { + CATCH_INTERNAL_ERROR("Attempted to use exception translators under CATCH_CONFIG_DISABLE_EXCEPTIONS!"); + } +#endif + +} +// end catch_exception_translator_registry.cpp +// start catch_fatal_condition.cpp + +#if defined(__GNUC__) +# pragma GCC diagnostic push +# pragma GCC diagnostic ignored "-Wmissing-field-initializers" +#endif + +#if defined( CATCH_CONFIG_WINDOWS_SEH ) || defined( CATCH_CONFIG_POSIX_SIGNALS ) + +namespace { + // Report the error condition + void reportFatal( char const * const message ) { + Catch::getCurrentContext().getResultCapture()->handleFatalErrorCondition( message ); + } +} + +#endif // signals/SEH handling + +#if defined( CATCH_CONFIG_WINDOWS_SEH ) + +namespace Catch { + struct SignalDefs { DWORD id; const char* name; }; + + // There is no 1-1 mapping between signals and windows exceptions. + // Windows can easily distinguish between SO and SigSegV, + // but SigInt, SigTerm, etc are handled differently. + static SignalDefs signalDefs[] = { + { EXCEPTION_ILLEGAL_INSTRUCTION, "SIGILL - Illegal instruction signal" }, + { EXCEPTION_STACK_OVERFLOW, "SIGSEGV - Stack overflow" }, + { EXCEPTION_ACCESS_VIOLATION, "SIGSEGV - Segmentation violation signal" }, + { EXCEPTION_INT_DIVIDE_BY_ZERO, "Divide by zero error" }, + }; + + LONG CALLBACK FatalConditionHandler::handleVectoredException(PEXCEPTION_POINTERS ExceptionInfo) { + for (auto const& def : signalDefs) { + if (ExceptionInfo->ExceptionRecord->ExceptionCode == def.id) { + reportFatal(def.name); + } + } + // If its not an exception we care about, pass it along. + // This stops us from eating debugger breaks etc. + return EXCEPTION_CONTINUE_SEARCH; + } + + FatalConditionHandler::FatalConditionHandler() { + isSet = true; + // 32k seems enough for Catch to handle stack overflow, + // but the value was found experimentally, so there is no strong guarantee + guaranteeSize = 32 * 1024; + exceptionHandlerHandle = nullptr; + // Register as first handler in current chain + exceptionHandlerHandle = AddVectoredExceptionHandler(1, handleVectoredException); + // Pass in guarantee size to be filled + SetThreadStackGuarantee(&guaranteeSize); + } + + void FatalConditionHandler::reset() { + if (isSet) { + RemoveVectoredExceptionHandler(exceptionHandlerHandle); + SetThreadStackGuarantee(&guaranteeSize); + exceptionHandlerHandle = nullptr; + isSet = false; + } + } + + FatalConditionHandler::~FatalConditionHandler() { + reset(); + } + +bool FatalConditionHandler::isSet = false; +ULONG FatalConditionHandler::guaranteeSize = 0; +PVOID FatalConditionHandler::exceptionHandlerHandle = nullptr; + +} // namespace Catch + +#elif defined( CATCH_CONFIG_POSIX_SIGNALS ) + +namespace Catch { + + struct SignalDefs { + int id; + const char* name; + }; + + // 32kb for the alternate stack seems to be sufficient. However, this value + // is experimentally determined, so that's not guaranteed. + constexpr static std::size_t sigStackSize = 32768 >= MINSIGSTKSZ ? 32768 : MINSIGSTKSZ; + + static SignalDefs signalDefs[] = { + { SIGINT, "SIGINT - Terminal interrupt signal" }, + { SIGILL, "SIGILL - Illegal instruction signal" }, + { SIGFPE, "SIGFPE - Floating point error signal" }, + { SIGSEGV, "SIGSEGV - Segmentation violation signal" }, + { SIGTERM, "SIGTERM - Termination request signal" }, + { SIGABRT, "SIGABRT - Abort (abnormal termination) signal" } + }; + + void FatalConditionHandler::handleSignal( int sig ) { + char const * name = ""; + for (auto const& def : signalDefs) { + if (sig == def.id) { + name = def.name; + break; + } + } + reset(); + reportFatal(name); + raise( sig ); + } + + FatalConditionHandler::FatalConditionHandler() { + isSet = true; + stack_t sigStack; + sigStack.ss_sp = altStackMem; + sigStack.ss_size = sigStackSize; + sigStack.ss_flags = 0; + sigaltstack(&sigStack, &oldSigStack); + struct sigaction sa = { }; + + sa.sa_handler = handleSignal; + sa.sa_flags = SA_ONSTACK; + for (std::size_t i = 0; i < sizeof(signalDefs)/sizeof(SignalDefs); ++i) { + sigaction(signalDefs[i].id, &sa, &oldSigActions[i]); + } + } + + FatalConditionHandler::~FatalConditionHandler() { + reset(); + } + + void FatalConditionHandler::reset() { + if( isSet ) { + // Set signals back to previous values -- hopefully nobody overwrote them in the meantime + for( std::size_t i = 0; i < sizeof(signalDefs)/sizeof(SignalDefs); ++i ) { + sigaction(signalDefs[i].id, &oldSigActions[i], nullptr); + } + // Return the old stack + sigaltstack(&oldSigStack, nullptr); + isSet = false; + } + } + + bool FatalConditionHandler::isSet = false; + struct sigaction FatalConditionHandler::oldSigActions[sizeof(signalDefs)/sizeof(SignalDefs)] = {}; + stack_t FatalConditionHandler::oldSigStack = {}; + char FatalConditionHandler::altStackMem[sigStackSize] = {}; + +} // namespace Catch + +#else + +namespace Catch { + void FatalConditionHandler::reset() {} +} + +#endif // signals/SEH handling + +#if defined(__GNUC__) +# pragma GCC diagnostic pop +#endif +// end catch_fatal_condition.cpp +// start catch_generators.cpp + +// start catch_random_number_generator.h + +#include +#include + +namespace Catch { + + struct IConfig; + + std::mt19937& rng(); + void seedRng( IConfig const& config ); + unsigned int rngSeed(); + +} + +// end catch_random_number_generator.h +#include +#include + +namespace Catch { + +IGeneratorTracker::~IGeneratorTracker() {} + +const char* GeneratorException::what() const noexcept { + return m_msg; +} + +namespace Generators { + + GeneratorUntypedBase::~GeneratorUntypedBase() {} + + auto acquireGeneratorTracker( SourceLineInfo const& lineInfo ) -> IGeneratorTracker& { + return getResultCapture().acquireGeneratorTracker( lineInfo ); + } + +} // namespace Generators +} // namespace Catch +// end catch_generators.cpp +// start catch_interfaces_capture.cpp + +namespace Catch { + IResultCapture::~IResultCapture() = default; +} +// end catch_interfaces_capture.cpp +// start catch_interfaces_config.cpp + +namespace Catch { + IConfig::~IConfig() = default; +} +// end catch_interfaces_config.cpp +// start catch_interfaces_exception.cpp + +namespace Catch { + IExceptionTranslator::~IExceptionTranslator() = default; + IExceptionTranslatorRegistry::~IExceptionTranslatorRegistry() = default; +} +// end catch_interfaces_exception.cpp +// start catch_interfaces_registry_hub.cpp + +namespace Catch { + IRegistryHub::~IRegistryHub() = default; + IMutableRegistryHub::~IMutableRegistryHub() = default; +} +// end catch_interfaces_registry_hub.cpp +// start catch_interfaces_reporter.cpp + +// start catch_reporter_listening.h + +namespace Catch { + + class ListeningReporter : public IStreamingReporter { + using Reporters = std::vector; + Reporters m_listeners; + IStreamingReporterPtr m_reporter = nullptr; + ReporterPreferences m_preferences; + + public: + ListeningReporter(); + + void addListener( IStreamingReporterPtr&& listener ); + void addReporter( IStreamingReporterPtr&& reporter ); + + public: // IStreamingReporter + + ReporterPreferences getPreferences() const override; + + void noMatchingTestCases( std::string const& spec ) override; + + static std::set getSupportedVerbosities(); + + void benchmarkStarting( BenchmarkInfo const& benchmarkInfo ) override; + void benchmarkEnded( BenchmarkStats const& benchmarkStats ) override; + + void testRunStarting( TestRunInfo const& testRunInfo ) override; + void testGroupStarting( GroupInfo const& groupInfo ) override; + void testCaseStarting( TestCaseInfo const& testInfo ) override; + void sectionStarting( SectionInfo const& sectionInfo ) override; + void assertionStarting( AssertionInfo const& assertionInfo ) override; + + // The return value indicates if the messages buffer should be cleared: + bool assertionEnded( AssertionStats const& assertionStats ) override; + void sectionEnded( SectionStats const& sectionStats ) override; + void testCaseEnded( TestCaseStats const& testCaseStats ) override; + void testGroupEnded( TestGroupStats const& testGroupStats ) override; + void testRunEnded( TestRunStats const& testRunStats ) override; + + void skipTest( TestCaseInfo const& testInfo ) override; + bool isMulti() const override; + + }; + +} // end namespace Catch + +// end catch_reporter_listening.h +namespace Catch { + + ReporterConfig::ReporterConfig( IConfigPtr const& _fullConfig ) + : m_stream( &_fullConfig->stream() ), m_fullConfig( _fullConfig ) {} + + ReporterConfig::ReporterConfig( IConfigPtr const& _fullConfig, std::ostream& _stream ) + : m_stream( &_stream ), m_fullConfig( _fullConfig ) {} + + std::ostream& ReporterConfig::stream() const { return *m_stream; } + IConfigPtr ReporterConfig::fullConfig() const { return m_fullConfig; } + + TestRunInfo::TestRunInfo( std::string const& _name ) : name( _name ) {} + + GroupInfo::GroupInfo( std::string const& _name, + std::size_t _groupIndex, + std::size_t _groupsCount ) + : name( _name ), + groupIndex( _groupIndex ), + groupsCounts( _groupsCount ) + {} + + AssertionStats::AssertionStats( AssertionResult const& _assertionResult, + std::vector const& _infoMessages, + Totals const& _totals ) + : assertionResult( _assertionResult ), + infoMessages( _infoMessages ), + totals( _totals ) + { + assertionResult.m_resultData.lazyExpression.m_transientExpression = _assertionResult.m_resultData.lazyExpression.m_transientExpression; + + if( assertionResult.hasMessage() ) { + // Copy message into messages list. + // !TBD This should have been done earlier, somewhere + MessageBuilder builder( assertionResult.getTestMacroName(), assertionResult.getSourceInfo(), assertionResult.getResultType() ); + builder << assertionResult.getMessage(); + builder.m_info.message = builder.m_stream.str(); + + infoMessages.push_back( builder.m_info ); + } + } + + AssertionStats::~AssertionStats() = default; + + SectionStats::SectionStats( SectionInfo const& _sectionInfo, + Counts const& _assertions, + double _durationInSeconds, + bool _missingAssertions ) + : sectionInfo( _sectionInfo ), + assertions( _assertions ), + durationInSeconds( _durationInSeconds ), + missingAssertions( _missingAssertions ) + {} + + SectionStats::~SectionStats() = default; + + TestCaseStats::TestCaseStats( TestCaseInfo const& _testInfo, + Totals const& _totals, + std::string const& _stdOut, + std::string const& _stdErr, + bool _aborting ) + : testInfo( _testInfo ), + totals( _totals ), + stdOut( _stdOut ), + stdErr( _stdErr ), + aborting( _aborting ) + {} + + TestCaseStats::~TestCaseStats() = default; + + TestGroupStats::TestGroupStats( GroupInfo const& _groupInfo, + Totals const& _totals, + bool _aborting ) + : groupInfo( _groupInfo ), + totals( _totals ), + aborting( _aborting ) + {} + + TestGroupStats::TestGroupStats( GroupInfo const& _groupInfo ) + : groupInfo( _groupInfo ), + aborting( false ) + {} + + TestGroupStats::~TestGroupStats() = default; + + TestRunStats::TestRunStats( TestRunInfo const& _runInfo, + Totals const& _totals, + bool _aborting ) + : runInfo( _runInfo ), + totals( _totals ), + aborting( _aborting ) + {} + + TestRunStats::~TestRunStats() = default; + + void IStreamingReporter::fatalErrorEncountered( StringRef ) {} + bool IStreamingReporter::isMulti() const { return false; } + + IReporterFactory::~IReporterFactory() = default; + IReporterRegistry::~IReporterRegistry() = default; + +} // end namespace Catch +// end catch_interfaces_reporter.cpp +// start catch_interfaces_runner.cpp + +namespace Catch { + IRunner::~IRunner() = default; +} +// end catch_interfaces_runner.cpp +// start catch_interfaces_testcase.cpp + +namespace Catch { + ITestInvoker::~ITestInvoker() = default; + ITestCaseRegistry::~ITestCaseRegistry() = default; +} +// end catch_interfaces_testcase.cpp +// start catch_leak_detector.cpp + +#ifdef CATCH_CONFIG_WINDOWS_CRTDBG +#include + +namespace Catch { + + LeakDetector::LeakDetector() { + int flag = _CrtSetDbgFlag(_CRTDBG_REPORT_FLAG); + flag |= _CRTDBG_LEAK_CHECK_DF; + flag |= _CRTDBG_ALLOC_MEM_DF; + _CrtSetDbgFlag(flag); + _CrtSetReportMode(_CRT_WARN, _CRTDBG_MODE_FILE | _CRTDBG_MODE_DEBUG); + _CrtSetReportFile(_CRT_WARN, _CRTDBG_FILE_STDERR); + // Change this to leaking allocation's number to break there + _CrtSetBreakAlloc(-1); + } +} + +#else + + Catch::LeakDetector::LeakDetector() {} + +#endif + +Catch::LeakDetector::~LeakDetector() { + Catch::cleanUp(); +} +// end catch_leak_detector.cpp +// start catch_list.cpp + +// start catch_list.h + +#include + +namespace Catch { + + std::size_t listTests( Config const& config ); + + std::size_t listTestsNamesOnly( Config const& config ); + + struct TagInfo { + void add( std::string const& spelling ); + std::string all() const; + + std::set spellings; + std::size_t count = 0; + }; + + std::size_t listTags( Config const& config ); + + std::size_t listReporters(); + + Option list( std::shared_ptr const& config ); + +} // end namespace Catch + +// end catch_list.h +// start catch_text.h + +namespace Catch { + using namespace clara::TextFlow; +} + +// end catch_text.h +#include +#include +#include + +namespace Catch { + + std::size_t listTests( Config const& config ) { + TestSpec testSpec = config.testSpec(); + if( config.hasTestFilters() ) + Catch::cout() << "Matching test cases:\n"; + else { + Catch::cout() << "All available test cases:\n"; + } + + auto matchedTestCases = filterTests( getAllTestCasesSorted( config ), testSpec, config ); + for( auto const& testCaseInfo : matchedTestCases ) { + Colour::Code colour = testCaseInfo.isHidden() + ? Colour::SecondaryText + : Colour::None; + Colour colourGuard( colour ); + + Catch::cout() << Column( testCaseInfo.name ).initialIndent( 2 ).indent( 4 ) << "\n"; + if( config.verbosity() >= Verbosity::High ) { + Catch::cout() << Column( Catch::Detail::stringify( testCaseInfo.lineInfo ) ).indent(4) << std::endl; + std::string description = testCaseInfo.description; + if( description.empty() ) + description = "(NO DESCRIPTION)"; + Catch::cout() << Column( description ).indent(4) << std::endl; + } + if( !testCaseInfo.tags.empty() ) + Catch::cout() << Column( testCaseInfo.tagsAsString() ).indent( 6 ) << "\n"; + } + + if( !config.hasTestFilters() ) + Catch::cout() << pluralise( matchedTestCases.size(), "test case" ) << '\n' << std::endl; + else + Catch::cout() << pluralise( matchedTestCases.size(), "matching test case" ) << '\n' << std::endl; + return matchedTestCases.size(); + } + + std::size_t listTestsNamesOnly( Config const& config ) { + TestSpec testSpec = config.testSpec(); + std::size_t matchedTests = 0; + std::vector matchedTestCases = filterTests( getAllTestCasesSorted( config ), testSpec, config ); + for( auto const& testCaseInfo : matchedTestCases ) { + matchedTests++; + if( startsWith( testCaseInfo.name, '#' ) ) + Catch::cout() << '"' << testCaseInfo.name << '"'; + else + Catch::cout() << testCaseInfo.name; + if ( config.verbosity() >= Verbosity::High ) + Catch::cout() << "\t@" << testCaseInfo.lineInfo; + Catch::cout() << std::endl; + } + return matchedTests; + } + + void TagInfo::add( std::string const& spelling ) { + ++count; + spellings.insert( spelling ); + } + + std::string TagInfo::all() const { + std::string out; + for( auto const& spelling : spellings ) + out += "[" + spelling + "]"; + return out; + } + + std::size_t listTags( Config const& config ) { + TestSpec testSpec = config.testSpec(); + if( config.hasTestFilters() ) + Catch::cout() << "Tags for matching test cases:\n"; + else { + Catch::cout() << "All available tags:\n"; + } + + std::map tagCounts; + + std::vector matchedTestCases = filterTests( getAllTestCasesSorted( config ), testSpec, config ); + for( auto const& testCase : matchedTestCases ) { + for( auto const& tagName : testCase.getTestCaseInfo().tags ) { + std::string lcaseTagName = toLower( tagName ); + auto countIt = tagCounts.find( lcaseTagName ); + if( countIt == tagCounts.end() ) + countIt = tagCounts.insert( std::make_pair( lcaseTagName, TagInfo() ) ).first; + countIt->second.add( tagName ); + } + } + + for( auto const& tagCount : tagCounts ) { + ReusableStringStream rss; + rss << " " << std::setw(2) << tagCount.second.count << " "; + auto str = rss.str(); + auto wrapper = Column( tagCount.second.all() ) + .initialIndent( 0 ) + .indent( str.size() ) + .width( CATCH_CONFIG_CONSOLE_WIDTH-10 ); + Catch::cout() << str << wrapper << '\n'; + } + Catch::cout() << pluralise( tagCounts.size(), "tag" ) << '\n' << std::endl; + return tagCounts.size(); + } + + std::size_t listReporters() { + Catch::cout() << "Available reporters:\n"; + IReporterRegistry::FactoryMap const& factories = getRegistryHub().getReporterRegistry().getFactories(); + std::size_t maxNameLen = 0; + for( auto const& factoryKvp : factories ) + maxNameLen = (std::max)( maxNameLen, factoryKvp.first.size() ); + + for( auto const& factoryKvp : factories ) { + Catch::cout() + << Column( factoryKvp.first + ":" ) + .indent(2) + .width( 5+maxNameLen ) + + Column( factoryKvp.second->getDescription() ) + .initialIndent(0) + .indent(2) + .width( CATCH_CONFIG_CONSOLE_WIDTH - maxNameLen-8 ) + << "\n"; + } + Catch::cout() << std::endl; + return factories.size(); + } + + Option list( std::shared_ptr const& config ) { + Option listedCount; + getCurrentMutableContext().setConfig( config ); + if( config->listTests() ) + listedCount = listedCount.valueOr(0) + listTests( *config ); + if( config->listTestNamesOnly() ) + listedCount = listedCount.valueOr(0) + listTestsNamesOnly( *config ); + if( config->listTags() ) + listedCount = listedCount.valueOr(0) + listTags( *config ); + if( config->listReporters() ) + listedCount = listedCount.valueOr(0) + listReporters(); + return listedCount; + } + +} // end namespace Catch +// end catch_list.cpp +// start catch_matchers.cpp + +namespace Catch { +namespace Matchers { + namespace Impl { + + std::string MatcherUntypedBase::toString() const { + if( m_cachedToString.empty() ) + m_cachedToString = describe(); + return m_cachedToString; + } + + MatcherUntypedBase::~MatcherUntypedBase() = default; + + } // namespace Impl +} // namespace Matchers + +using namespace Matchers; +using Matchers::Impl::MatcherBase; + +} // namespace Catch +// end catch_matchers.cpp +// start catch_matchers_floating.cpp + +// start catch_polyfills.hpp + +namespace Catch { + bool isnan(float f); + bool isnan(double d); +} + +// end catch_polyfills.hpp +// start catch_to_string.hpp + +#include + +namespace Catch { + template + std::string to_string(T const& t) { +#if defined(CATCH_CONFIG_CPP11_TO_STRING) + return std::to_string(t); +#else + ReusableStringStream rss; + rss << t; + return rss.str(); +#endif + } +} // end namespace Catch + +// end catch_to_string.hpp +#include +#include +#include + +namespace Catch { +namespace Matchers { +namespace Floating { +enum class FloatingPointKind : uint8_t { + Float, + Double +}; +} +} +} + +namespace { + +template +struct Converter; + +template <> +struct Converter { + static_assert(sizeof(float) == sizeof(int32_t), "Important ULP matcher assumption violated"); + Converter(float f) { + std::memcpy(&i, &f, sizeof(f)); + } + int32_t i; +}; + +template <> +struct Converter { + static_assert(sizeof(double) == sizeof(int64_t), "Important ULP matcher assumption violated"); + Converter(double d) { + std::memcpy(&i, &d, sizeof(d)); + } + int64_t i; +}; + +template +auto convert(T t) -> Converter { + return Converter(t); +} + +template +bool almostEqualUlps(FP lhs, FP rhs, int maxUlpDiff) { + // Comparison with NaN should always be false. + // This way we can rule it out before getting into the ugly details + if (Catch::isnan(lhs) || Catch::isnan(rhs)) { + return false; + } + + auto lc = convert(lhs); + auto rc = convert(rhs); + + if ((lc.i < 0) != (rc.i < 0)) { + // Potentially we can have +0 and -0 + return lhs == rhs; + } + + auto ulpDiff = std::abs(lc.i - rc.i); + return ulpDiff <= maxUlpDiff; +} + +} + +namespace Catch { +namespace Matchers { +namespace Floating { + WithinAbsMatcher::WithinAbsMatcher(double target, double margin) + :m_target{ target }, m_margin{ margin } { + CATCH_ENFORCE(margin >= 0, "Invalid margin: " << margin << '.' + << " Margin has to be non-negative."); + } + + // Performs equivalent check of std::fabs(lhs - rhs) <= margin + // But without the subtraction to allow for INFINITY in comparison + bool WithinAbsMatcher::match(double const& matchee) const { + return (matchee + m_margin >= m_target) && (m_target + m_margin >= matchee); + } + + std::string WithinAbsMatcher::describe() const { + return "is within " + ::Catch::Detail::stringify(m_margin) + " of " + ::Catch::Detail::stringify(m_target); + } + + WithinUlpsMatcher::WithinUlpsMatcher(double target, int ulps, FloatingPointKind baseType) + :m_target{ target }, m_ulps{ ulps }, m_type{ baseType } { + CATCH_ENFORCE(ulps >= 0, "Invalid ULP setting: " << ulps << '.' + << " ULPs have to be non-negative."); + } + +#if defined(__clang__) +#pragma clang diagnostic push +// Clang <3.5 reports on the default branch in the switch below +#pragma clang diagnostic ignored "-Wunreachable-code" +#endif + + bool WithinUlpsMatcher::match(double const& matchee) const { + switch (m_type) { + case FloatingPointKind::Float: + return almostEqualUlps(static_cast(matchee), static_cast(m_target), m_ulps); + case FloatingPointKind::Double: + return almostEqualUlps(matchee, m_target, m_ulps); + default: + CATCH_INTERNAL_ERROR( "Unknown FloatingPointKind value" ); + } + } + +#if defined(__clang__) +#pragma clang diagnostic pop +#endif + + std::string WithinUlpsMatcher::describe() const { + return "is within " + Catch::to_string(m_ulps) + " ULPs of " + ::Catch::Detail::stringify(m_target) + ((m_type == FloatingPointKind::Float)? "f" : ""); + } + +}// namespace Floating + +Floating::WithinUlpsMatcher WithinULP(double target, int maxUlpDiff) { + return Floating::WithinUlpsMatcher(target, maxUlpDiff, Floating::FloatingPointKind::Double); +} + +Floating::WithinUlpsMatcher WithinULP(float target, int maxUlpDiff) { + return Floating::WithinUlpsMatcher(target, maxUlpDiff, Floating::FloatingPointKind::Float); +} + +Floating::WithinAbsMatcher WithinAbs(double target, double margin) { + return Floating::WithinAbsMatcher(target, margin); +} + +} // namespace Matchers +} // namespace Catch + +// end catch_matchers_floating.cpp +// start catch_matchers_generic.cpp + +std::string Catch::Matchers::Generic::Detail::finalizeDescription(const std::string& desc) { + if (desc.empty()) { + return "matches undescribed predicate"; + } else { + return "matches predicate: \"" + desc + '"'; + } +} +// end catch_matchers_generic.cpp +// start catch_matchers_string.cpp + +#include + +namespace Catch { +namespace Matchers { + + namespace StdString { + + CasedString::CasedString( std::string const& str, CaseSensitive::Choice caseSensitivity ) + : m_caseSensitivity( caseSensitivity ), + m_str( adjustString( str ) ) + {} + std::string CasedString::adjustString( std::string const& str ) const { + return m_caseSensitivity == CaseSensitive::No + ? toLower( str ) + : str; + } + std::string CasedString::caseSensitivitySuffix() const { + return m_caseSensitivity == CaseSensitive::No + ? " (case insensitive)" + : std::string(); + } + + StringMatcherBase::StringMatcherBase( std::string const& operation, CasedString const& comparator ) + : m_comparator( comparator ), + m_operation( operation ) { + } + + std::string StringMatcherBase::describe() const { + std::string description; + description.reserve(5 + m_operation.size() + m_comparator.m_str.size() + + m_comparator.caseSensitivitySuffix().size()); + description += m_operation; + description += ": \""; + description += m_comparator.m_str; + description += "\""; + description += m_comparator.caseSensitivitySuffix(); + return description; + } + + EqualsMatcher::EqualsMatcher( CasedString const& comparator ) : StringMatcherBase( "equals", comparator ) {} + + bool EqualsMatcher::match( std::string const& source ) const { + return m_comparator.adjustString( source ) == m_comparator.m_str; + } + + ContainsMatcher::ContainsMatcher( CasedString const& comparator ) : StringMatcherBase( "contains", comparator ) {} + + bool ContainsMatcher::match( std::string const& source ) const { + return contains( m_comparator.adjustString( source ), m_comparator.m_str ); + } + + StartsWithMatcher::StartsWithMatcher( CasedString const& comparator ) : StringMatcherBase( "starts with", comparator ) {} + + bool StartsWithMatcher::match( std::string const& source ) const { + return startsWith( m_comparator.adjustString( source ), m_comparator.m_str ); + } + + EndsWithMatcher::EndsWithMatcher( CasedString const& comparator ) : StringMatcherBase( "ends with", comparator ) {} + + bool EndsWithMatcher::match( std::string const& source ) const { + return endsWith( m_comparator.adjustString( source ), m_comparator.m_str ); + } + + RegexMatcher::RegexMatcher(std::string regex, CaseSensitive::Choice caseSensitivity): m_regex(std::move(regex)), m_caseSensitivity(caseSensitivity) {} + + bool RegexMatcher::match(std::string const& matchee) const { + auto flags = std::regex::ECMAScript; // ECMAScript is the default syntax option anyway + if (m_caseSensitivity == CaseSensitive::Choice::No) { + flags |= std::regex::icase; + } + auto reg = std::regex(m_regex, flags); + return std::regex_match(matchee, reg); + } + + std::string RegexMatcher::describe() const { + return "matches " + ::Catch::Detail::stringify(m_regex) + ((m_caseSensitivity == CaseSensitive::Choice::Yes)? " case sensitively" : " case insensitively"); + } + + } // namespace StdString + + StdString::EqualsMatcher Equals( std::string const& str, CaseSensitive::Choice caseSensitivity ) { + return StdString::EqualsMatcher( StdString::CasedString( str, caseSensitivity) ); + } + StdString::ContainsMatcher Contains( std::string const& str, CaseSensitive::Choice caseSensitivity ) { + return StdString::ContainsMatcher( StdString::CasedString( str, caseSensitivity) ); + } + StdString::EndsWithMatcher EndsWith( std::string const& str, CaseSensitive::Choice caseSensitivity ) { + return StdString::EndsWithMatcher( StdString::CasedString( str, caseSensitivity) ); + } + StdString::StartsWithMatcher StartsWith( std::string const& str, CaseSensitive::Choice caseSensitivity ) { + return StdString::StartsWithMatcher( StdString::CasedString( str, caseSensitivity) ); + } + + StdString::RegexMatcher Matches(std::string const& regex, CaseSensitive::Choice caseSensitivity) { + return StdString::RegexMatcher(regex, caseSensitivity); + } + +} // namespace Matchers +} // namespace Catch +// end catch_matchers_string.cpp +// start catch_message.cpp + +// start catch_uncaught_exceptions.h + +namespace Catch { + bool uncaught_exceptions(); +} // end namespace Catch + +// end catch_uncaught_exceptions.h +#include +#include + +namespace Catch { + + MessageInfo::MessageInfo( StringRef const& _macroName, + SourceLineInfo const& _lineInfo, + ResultWas::OfType _type ) + : macroName( _macroName ), + lineInfo( _lineInfo ), + type( _type ), + sequence( ++globalCount ) + {} + + bool MessageInfo::operator==( MessageInfo const& other ) const { + return sequence == other.sequence; + } + + bool MessageInfo::operator<( MessageInfo const& other ) const { + return sequence < other.sequence; + } + + // This may need protecting if threading support is added + unsigned int MessageInfo::globalCount = 0; + + //////////////////////////////////////////////////////////////////////////// + + Catch::MessageBuilder::MessageBuilder( StringRef const& macroName, + SourceLineInfo const& lineInfo, + ResultWas::OfType type ) + :m_info(macroName, lineInfo, type) {} + + //////////////////////////////////////////////////////////////////////////// + + ScopedMessage::ScopedMessage( MessageBuilder const& builder ) + : m_info( builder.m_info ), m_moved() + { + m_info.message = builder.m_stream.str(); + getResultCapture().pushScopedMessage( m_info ); + } + + ScopedMessage::ScopedMessage( ScopedMessage&& old ) + : m_info( old.m_info ), m_moved() + { + old.m_moved = true; + } + + ScopedMessage::~ScopedMessage() { + if ( !uncaught_exceptions() && !m_moved ){ + getResultCapture().popScopedMessage(m_info); + } + } + + Capturer::Capturer( StringRef macroName, SourceLineInfo const& lineInfo, ResultWas::OfType resultType, StringRef names ) { + auto trimmed = [&] (size_t start, size_t end) { + while (names[start] == ',' || isspace(names[start])) { + ++start; + } + while (names[end] == ',' || isspace(names[end])) { + --end; + } + return names.substr(start, end - start + 1); + }; + + size_t start = 0; + std::stack openings; + for (size_t pos = 0; pos < names.size(); ++pos) { + char c = names[pos]; + switch (c) { + case '[': + case '{': + case '(': + // It is basically impossible to disambiguate between + // comparison and start of template args in this context +// case '<': + openings.push(c); + break; + case ']': + case '}': + case ')': +// case '>': + openings.pop(); + break; + case ',': + if (start != pos && openings.size() == 0) { + m_messages.emplace_back(macroName, lineInfo, resultType); + m_messages.back().message = trimmed(start, pos); + m_messages.back().message += " := "; + start = pos; + } + } + } + assert(openings.size() == 0 && "Mismatched openings"); + m_messages.emplace_back(macroName, lineInfo, resultType); + m_messages.back().message = trimmed(start, names.size() - 1); + m_messages.back().message += " := "; + } + Capturer::~Capturer() { + if ( !uncaught_exceptions() ){ + assert( m_captured == m_messages.size() ); + for( size_t i = 0; i < m_captured; ++i ) + m_resultCapture.popScopedMessage( m_messages[i] ); + } + } + + void Capturer::captureValue( size_t index, std::string const& value ) { + assert( index < m_messages.size() ); + m_messages[index].message += value; + m_resultCapture.pushScopedMessage( m_messages[index] ); + m_captured++; + } + +} // end namespace Catch +// end catch_message.cpp +// start catch_output_redirect.cpp + +// start catch_output_redirect.h +#ifndef TWOBLUECUBES_CATCH_OUTPUT_REDIRECT_H +#define TWOBLUECUBES_CATCH_OUTPUT_REDIRECT_H + +#include +#include +#include + +namespace Catch { + + class RedirectedStream { + std::ostream& m_originalStream; + std::ostream& m_redirectionStream; + std::streambuf* m_prevBuf; + + public: + RedirectedStream( std::ostream& originalStream, std::ostream& redirectionStream ); + ~RedirectedStream(); + }; + + class RedirectedStdOut { + ReusableStringStream m_rss; + RedirectedStream m_cout; + public: + RedirectedStdOut(); + auto str() const -> std::string; + }; + + // StdErr has two constituent streams in C++, std::cerr and std::clog + // This means that we need to redirect 2 streams into 1 to keep proper + // order of writes + class RedirectedStdErr { + ReusableStringStream m_rss; + RedirectedStream m_cerr; + RedirectedStream m_clog; + public: + RedirectedStdErr(); + auto str() const -> std::string; + }; + + class RedirectedStreams { + public: + RedirectedStreams(RedirectedStreams const&) = delete; + RedirectedStreams& operator=(RedirectedStreams const&) = delete; + RedirectedStreams(RedirectedStreams&&) = delete; + RedirectedStreams& operator=(RedirectedStreams&&) = delete; + + RedirectedStreams(std::string& redirectedCout, std::string& redirectedCerr); + ~RedirectedStreams(); + private: + std::string& m_redirectedCout; + std::string& m_redirectedCerr; + RedirectedStdOut m_redirectedStdOut; + RedirectedStdErr m_redirectedStdErr; + }; + +#if defined(CATCH_CONFIG_NEW_CAPTURE) + + // Windows's implementation of std::tmpfile is terrible (it tries + // to create a file inside system folder, thus requiring elevated + // privileges for the binary), so we have to use tmpnam(_s) and + // create the file ourselves there. + class TempFile { + public: + TempFile(TempFile const&) = delete; + TempFile& operator=(TempFile const&) = delete; + TempFile(TempFile&&) = delete; + TempFile& operator=(TempFile&&) = delete; + + TempFile(); + ~TempFile(); + + std::FILE* getFile(); + std::string getContents(); + + private: + std::FILE* m_file = nullptr; + #if defined(_MSC_VER) + char m_buffer[L_tmpnam] = { 0 }; + #endif + }; + + class OutputRedirect { + public: + OutputRedirect(OutputRedirect const&) = delete; + OutputRedirect& operator=(OutputRedirect const&) = delete; + OutputRedirect(OutputRedirect&&) = delete; + OutputRedirect& operator=(OutputRedirect&&) = delete; + + OutputRedirect(std::string& stdout_dest, std::string& stderr_dest); + ~OutputRedirect(); + + private: + int m_originalStdout = -1; + int m_originalStderr = -1; + TempFile m_stdoutFile; + TempFile m_stderrFile; + std::string& m_stdoutDest; + std::string& m_stderrDest; + }; + +#endif + +} // end namespace Catch + +#endif // TWOBLUECUBES_CATCH_OUTPUT_REDIRECT_H +// end catch_output_redirect.h +#include +#include +#include +#include +#include + +#if defined(CATCH_CONFIG_NEW_CAPTURE) + #if defined(_MSC_VER) + #include //_dup and _dup2 + #define dup _dup + #define dup2 _dup2 + #define fileno _fileno + #else + #include // dup and dup2 + #endif +#endif + +namespace Catch { + + RedirectedStream::RedirectedStream( std::ostream& originalStream, std::ostream& redirectionStream ) + : m_originalStream( originalStream ), + m_redirectionStream( redirectionStream ), + m_prevBuf( m_originalStream.rdbuf() ) + { + m_originalStream.rdbuf( m_redirectionStream.rdbuf() ); + } + + RedirectedStream::~RedirectedStream() { + m_originalStream.rdbuf( m_prevBuf ); + } + + RedirectedStdOut::RedirectedStdOut() : m_cout( Catch::cout(), m_rss.get() ) {} + auto RedirectedStdOut::str() const -> std::string { return m_rss.str(); } + + RedirectedStdErr::RedirectedStdErr() + : m_cerr( Catch::cerr(), m_rss.get() ), + m_clog( Catch::clog(), m_rss.get() ) + {} + auto RedirectedStdErr::str() const -> std::string { return m_rss.str(); } + + RedirectedStreams::RedirectedStreams(std::string& redirectedCout, std::string& redirectedCerr) + : m_redirectedCout(redirectedCout), + m_redirectedCerr(redirectedCerr) + {} + + RedirectedStreams::~RedirectedStreams() { + m_redirectedCout += m_redirectedStdOut.str(); + m_redirectedCerr += m_redirectedStdErr.str(); + } + +#if defined(CATCH_CONFIG_NEW_CAPTURE) + +#if defined(_MSC_VER) + TempFile::TempFile() { + if (tmpnam_s(m_buffer)) { + CATCH_RUNTIME_ERROR("Could not get a temp filename"); + } + if (fopen_s(&m_file, m_buffer, "w")) { + char buffer[100]; + if (strerror_s(buffer, errno)) { + CATCH_RUNTIME_ERROR("Could not translate errno to a string"); + } + CATCH_RUNTIME_ERROR("Coul dnot open the temp file: '" << m_buffer << "' because: " << buffer); + } + } +#else + TempFile::TempFile() { + m_file = std::tmpfile(); + if (!m_file) { + CATCH_RUNTIME_ERROR("Could not create a temp file."); + } + } + +#endif + + TempFile::~TempFile() { + // TBD: What to do about errors here? + std::fclose(m_file); + // We manually create the file on Windows only, on Linux + // it will be autodeleted +#if defined(_MSC_VER) + std::remove(m_buffer); +#endif + } + + FILE* TempFile::getFile() { + return m_file; + } + + std::string TempFile::getContents() { + std::stringstream sstr; + char buffer[100] = {}; + std::rewind(m_file); + while (std::fgets(buffer, sizeof(buffer), m_file)) { + sstr << buffer; + } + return sstr.str(); + } + + OutputRedirect::OutputRedirect(std::string& stdout_dest, std::string& stderr_dest) : + m_originalStdout(dup(1)), + m_originalStderr(dup(2)), + m_stdoutDest(stdout_dest), + m_stderrDest(stderr_dest) { + dup2(fileno(m_stdoutFile.getFile()), 1); + dup2(fileno(m_stderrFile.getFile()), 2); + } + + OutputRedirect::~OutputRedirect() { + Catch::cout() << std::flush; + fflush(stdout); + // Since we support overriding these streams, we flush cerr + // even though std::cerr is unbuffered + Catch::cerr() << std::flush; + Catch::clog() << std::flush; + fflush(stderr); + + dup2(m_originalStdout, 1); + dup2(m_originalStderr, 2); + + m_stdoutDest += m_stdoutFile.getContents(); + m_stderrDest += m_stderrFile.getContents(); + } + +#endif // CATCH_CONFIG_NEW_CAPTURE + +} // namespace Catch + +#if defined(CATCH_CONFIG_NEW_CAPTURE) + #if defined(_MSC_VER) + #undef dup + #undef dup2 + #undef fileno + #endif +#endif +// end catch_output_redirect.cpp +// start catch_polyfills.cpp + +#include + +namespace Catch { + +#if !defined(CATCH_CONFIG_POLYFILL_ISNAN) + bool isnan(float f) { + return std::isnan(f); + } + bool isnan(double d) { + return std::isnan(d); + } +#else + // For now we only use this for embarcadero + bool isnan(float f) { + return std::_isnan(f); + } + bool isnan(double d) { + return std::_isnan(d); + } +#endif + +} // end namespace Catch +// end catch_polyfills.cpp +// start catch_random_number_generator.cpp + +namespace Catch { + + std::mt19937& rng() { + static std::mt19937 s_rng; + return s_rng; + } + + void seedRng( IConfig const& config ) { + if( config.rngSeed() != 0 ) { + std::srand( config.rngSeed() ); + rng().seed( config.rngSeed() ); + } + } + + unsigned int rngSeed() { + return getCurrentContext().getConfig()->rngSeed(); + } +} +// end catch_random_number_generator.cpp +// start catch_registry_hub.cpp + +// start catch_test_case_registry_impl.h + +#include +#include +#include +#include + +namespace Catch { + + class TestCase; + struct IConfig; + + std::vector sortTests( IConfig const& config, std::vector const& unsortedTestCases ); + bool matchTest( TestCase const& testCase, TestSpec const& testSpec, IConfig const& config ); + + void enforceNoDuplicateTestCases( std::vector const& functions ); + + std::vector filterTests( std::vector const& testCases, TestSpec const& testSpec, IConfig const& config ); + std::vector const& getAllTestCasesSorted( IConfig const& config ); + + class TestRegistry : public ITestCaseRegistry { + public: + virtual ~TestRegistry() = default; + + virtual void registerTest( TestCase const& testCase ); + + std::vector const& getAllTests() const override; + std::vector const& getAllTestsSorted( IConfig const& config ) const override; + + private: + std::vector m_functions; + mutable RunTests::InWhatOrder m_currentSortOrder = RunTests::InDeclarationOrder; + mutable std::vector m_sortedFunctions; + std::size_t m_unnamedCount = 0; + std::ios_base::Init m_ostreamInit; // Forces cout/ cerr to be initialised + }; + + /////////////////////////////////////////////////////////////////////////// + + class TestInvokerAsFunction : public ITestInvoker { + void(*m_testAsFunction)(); + public: + TestInvokerAsFunction( void(*testAsFunction)() ) noexcept; + + void invoke() const override; + }; + + std::string extractClassName( StringRef const& classOrQualifiedMethodName ); + + /////////////////////////////////////////////////////////////////////////// + +} // end namespace Catch + +// end catch_test_case_registry_impl.h +// start catch_reporter_registry.h + +#include + +namespace Catch { + + class ReporterRegistry : public IReporterRegistry { + + public: + + ~ReporterRegistry() override; + + IStreamingReporterPtr create( std::string const& name, IConfigPtr const& config ) const override; + + void registerReporter( std::string const& name, IReporterFactoryPtr const& factory ); + void registerListener( IReporterFactoryPtr const& factory ); + + FactoryMap const& getFactories() const override; + Listeners const& getListeners() const override; + + private: + FactoryMap m_factories; + Listeners m_listeners; + }; +} + +// end catch_reporter_registry.h +// start catch_tag_alias_registry.h + +// start catch_tag_alias.h + +#include + +namespace Catch { + + struct TagAlias { + TagAlias(std::string const& _tag, SourceLineInfo _lineInfo); + + std::string tag; + SourceLineInfo lineInfo; + }; + +} // end namespace Catch + +// end catch_tag_alias.h +#include + +namespace Catch { + + class TagAliasRegistry : public ITagAliasRegistry { + public: + ~TagAliasRegistry() override; + TagAlias const* find( std::string const& alias ) const override; + std::string expandAliases( std::string const& unexpandedTestSpec ) const override; + void add( std::string const& alias, std::string const& tag, SourceLineInfo const& lineInfo ); + + private: + std::map m_registry; + }; + +} // end namespace Catch + +// end catch_tag_alias_registry.h +// start catch_startup_exception_registry.h + +#include +#include + +namespace Catch { + + class StartupExceptionRegistry { + public: + void add(std::exception_ptr const& exception) noexcept; + std::vector const& getExceptions() const noexcept; + private: + std::vector m_exceptions; + }; + +} // end namespace Catch + +// end catch_startup_exception_registry.h +// start catch_singletons.hpp + +namespace Catch { + + struct ISingleton { + virtual ~ISingleton(); + }; + + void addSingleton( ISingleton* singleton ); + void cleanupSingletons(); + + template + class Singleton : SingletonImplT, public ISingleton { + + static auto getInternal() -> Singleton* { + static Singleton* s_instance = nullptr; + if( !s_instance ) { + s_instance = new Singleton; + addSingleton( s_instance ); + } + return s_instance; + } + + public: + static auto get() -> InterfaceT const& { + return *getInternal(); + } + static auto getMutable() -> MutableInterfaceT& { + return *getInternal(); + } + }; + +} // namespace Catch + +// end catch_singletons.hpp +namespace Catch { + + namespace { + + class RegistryHub : public IRegistryHub, public IMutableRegistryHub, + private NonCopyable { + + public: // IRegistryHub + RegistryHub() = default; + IReporterRegistry const& getReporterRegistry() const override { + return m_reporterRegistry; + } + ITestCaseRegistry const& getTestCaseRegistry() const override { + return m_testCaseRegistry; + } + IExceptionTranslatorRegistry const& getExceptionTranslatorRegistry() const override { + return m_exceptionTranslatorRegistry; + } + ITagAliasRegistry const& getTagAliasRegistry() const override { + return m_tagAliasRegistry; + } + StartupExceptionRegistry const& getStartupExceptionRegistry() const override { + return m_exceptionRegistry; + } + + public: // IMutableRegistryHub + void registerReporter( std::string const& name, IReporterFactoryPtr const& factory ) override { + m_reporterRegistry.registerReporter( name, factory ); + } + void registerListener( IReporterFactoryPtr const& factory ) override { + m_reporterRegistry.registerListener( factory ); + } + void registerTest( TestCase const& testInfo ) override { + m_testCaseRegistry.registerTest( testInfo ); + } + void registerTranslator( const IExceptionTranslator* translator ) override { + m_exceptionTranslatorRegistry.registerTranslator( translator ); + } + void registerTagAlias( std::string const& alias, std::string const& tag, SourceLineInfo const& lineInfo ) override { + m_tagAliasRegistry.add( alias, tag, lineInfo ); + } + void registerStartupException() noexcept override { + m_exceptionRegistry.add(std::current_exception()); + } + + private: + TestRegistry m_testCaseRegistry; + ReporterRegistry m_reporterRegistry; + ExceptionTranslatorRegistry m_exceptionTranslatorRegistry; + TagAliasRegistry m_tagAliasRegistry; + StartupExceptionRegistry m_exceptionRegistry; + }; + } + + using RegistryHubSingleton = Singleton; + + IRegistryHub const& getRegistryHub() { + return RegistryHubSingleton::get(); + } + IMutableRegistryHub& getMutableRegistryHub() { + return RegistryHubSingleton::getMutable(); + } + void cleanUp() { + cleanupSingletons(); + cleanUpContext(); + } + std::string translateActiveException() { + return getRegistryHub().getExceptionTranslatorRegistry().translateActiveException(); + } + +} // end namespace Catch +// end catch_registry_hub.cpp +// start catch_reporter_registry.cpp + +namespace Catch { + + ReporterRegistry::~ReporterRegistry() = default; + + IStreamingReporterPtr ReporterRegistry::create( std::string const& name, IConfigPtr const& config ) const { + auto it = m_factories.find( name ); + if( it == m_factories.end() ) + return nullptr; + return it->second->create( ReporterConfig( config ) ); + } + + void ReporterRegistry::registerReporter( std::string const& name, IReporterFactoryPtr const& factory ) { + m_factories.emplace(name, factory); + } + void ReporterRegistry::registerListener( IReporterFactoryPtr const& factory ) { + m_listeners.push_back( factory ); + } + + IReporterRegistry::FactoryMap const& ReporterRegistry::getFactories() const { + return m_factories; + } + IReporterRegistry::Listeners const& ReporterRegistry::getListeners() const { + return m_listeners; + } + +} +// end catch_reporter_registry.cpp +// start catch_result_type.cpp + +namespace Catch { + + bool isOk( ResultWas::OfType resultType ) { + return ( resultType & ResultWas::FailureBit ) == 0; + } + bool isJustInfo( int flags ) { + return flags == ResultWas::Info; + } + + ResultDisposition::Flags operator | ( ResultDisposition::Flags lhs, ResultDisposition::Flags rhs ) { + return static_cast( static_cast( lhs ) | static_cast( rhs ) ); + } + + bool shouldContinueOnFailure( int flags ) { return ( flags & ResultDisposition::ContinueOnFailure ) != 0; } + bool shouldSuppressFailure( int flags ) { return ( flags & ResultDisposition::SuppressFail ) != 0; } + +} // end namespace Catch +// end catch_result_type.cpp +// start catch_run_context.cpp + +#include +#include +#include + +namespace Catch { + + namespace Generators { + struct GeneratorTracker : TestCaseTracking::TrackerBase, IGeneratorTracker { + GeneratorBasePtr m_generator; + + GeneratorTracker( TestCaseTracking::NameAndLocation const& nameAndLocation, TrackerContext& ctx, ITracker* parent ) + : TrackerBase( nameAndLocation, ctx, parent ) + {} + ~GeneratorTracker(); + + static GeneratorTracker& acquire( TrackerContext& ctx, TestCaseTracking::NameAndLocation const& nameAndLocation ) { + std::shared_ptr tracker; + + ITracker& currentTracker = ctx.currentTracker(); + if( TestCaseTracking::ITrackerPtr childTracker = currentTracker.findChild( nameAndLocation ) ) { + assert( childTracker ); + assert( childTracker->isGeneratorTracker() ); + tracker = std::static_pointer_cast( childTracker ); + } + else { + tracker = std::make_shared( nameAndLocation, ctx, ¤tTracker ); + currentTracker.addChild( tracker ); + } + + if( !ctx.completedCycle() && !tracker->isComplete() ) { + tracker->open(); + } + + return *tracker; + } + + // TrackerBase interface + bool isGeneratorTracker() const override { return true; } + auto hasGenerator() const -> bool override { + return !!m_generator; + } + void close() override { + TrackerBase::close(); + // Generator interface only finds out if it has another item on atual move + if (m_runState == CompletedSuccessfully && m_generator->next()) { + m_children.clear(); + m_runState = Executing; + } + } + + // IGeneratorTracker interface + auto getGenerator() const -> GeneratorBasePtr const& override { + return m_generator; + } + void setGenerator( GeneratorBasePtr&& generator ) override { + m_generator = std::move( generator ); + } + }; + GeneratorTracker::~GeneratorTracker() {} + } + + RunContext::RunContext(IConfigPtr const& _config, IStreamingReporterPtr&& reporter) + : m_runInfo(_config->name()), + m_context(getCurrentMutableContext()), + m_config(_config), + m_reporter(std::move(reporter)), + m_lastAssertionInfo{ StringRef(), SourceLineInfo("",0), StringRef(), ResultDisposition::Normal }, + m_includeSuccessfulResults( m_config->includeSuccessfulResults() || m_reporter->getPreferences().shouldReportAllAssertions ) + { + m_context.setRunner(this); + m_context.setConfig(m_config); + m_context.setResultCapture(this); + m_reporter->testRunStarting(m_runInfo); + } + + RunContext::~RunContext() { + m_reporter->testRunEnded(TestRunStats(m_runInfo, m_totals, aborting())); + } + + void RunContext::testGroupStarting(std::string const& testSpec, std::size_t groupIndex, std::size_t groupsCount) { + m_reporter->testGroupStarting(GroupInfo(testSpec, groupIndex, groupsCount)); + } + + void RunContext::testGroupEnded(std::string const& testSpec, Totals const& totals, std::size_t groupIndex, std::size_t groupsCount) { + m_reporter->testGroupEnded(TestGroupStats(GroupInfo(testSpec, groupIndex, groupsCount), totals, aborting())); + } + + Totals RunContext::runTest(TestCase const& testCase) { + Totals prevTotals = m_totals; + + std::string redirectedCout; + std::string redirectedCerr; + + auto const& testInfo = testCase.getTestCaseInfo(); + + m_reporter->testCaseStarting(testInfo); + + m_activeTestCase = &testCase; + + ITracker& rootTracker = m_trackerContext.startRun(); + assert(rootTracker.isSectionTracker()); + static_cast(rootTracker).addInitialFilters(m_config->getSectionsToRun()); + do { + m_trackerContext.startCycle(); + m_testCaseTracker = &SectionTracker::acquire(m_trackerContext, TestCaseTracking::NameAndLocation(testInfo.name, testInfo.lineInfo)); + runCurrentTest(redirectedCout, redirectedCerr); + } while (!m_testCaseTracker->isSuccessfullyCompleted() && !aborting()); + + Totals deltaTotals = m_totals.delta(prevTotals); + if (testInfo.expectedToFail() && deltaTotals.testCases.passed > 0) { + deltaTotals.assertions.failed++; + deltaTotals.testCases.passed--; + deltaTotals.testCases.failed++; + } + m_totals.testCases += deltaTotals.testCases; + m_reporter->testCaseEnded(TestCaseStats(testInfo, + deltaTotals, + redirectedCout, + redirectedCerr, + aborting())); + + m_activeTestCase = nullptr; + m_testCaseTracker = nullptr; + + return deltaTotals; + } + + IConfigPtr RunContext::config() const { + return m_config; + } + + IStreamingReporter& RunContext::reporter() const { + return *m_reporter; + } + + void RunContext::assertionEnded(AssertionResult const & result) { + if (result.getResultType() == ResultWas::Ok) { + m_totals.assertions.passed++; + m_lastAssertionPassed = true; + } else if (!result.isOk()) { + m_lastAssertionPassed = false; + if( m_activeTestCase->getTestCaseInfo().okToFail() ) + m_totals.assertions.failedButOk++; + else + m_totals.assertions.failed++; + } + else { + m_lastAssertionPassed = true; + } + + // We have no use for the return value (whether messages should be cleared), because messages were made scoped + // and should be let to clear themselves out. + static_cast(m_reporter->assertionEnded(AssertionStats(result, m_messages, m_totals))); + + if (result.getResultType() != ResultWas::Warning) + m_messageScopes.clear(); + + // Reset working state + resetAssertionInfo(); + m_lastResult = result; + } + void RunContext::resetAssertionInfo() { + m_lastAssertionInfo.macroName = StringRef(); + m_lastAssertionInfo.capturedExpression = "{Unknown expression after the reported line}"_sr; + } + + bool RunContext::sectionStarted(SectionInfo const & sectionInfo, Counts & assertions) { + ITracker& sectionTracker = SectionTracker::acquire(m_trackerContext, TestCaseTracking::NameAndLocation(sectionInfo.name, sectionInfo.lineInfo)); + if (!sectionTracker.isOpen()) + return false; + m_activeSections.push_back(§ionTracker); + + m_lastAssertionInfo.lineInfo = sectionInfo.lineInfo; + + m_reporter->sectionStarting(sectionInfo); + + assertions = m_totals.assertions; + + return true; + } + auto RunContext::acquireGeneratorTracker( SourceLineInfo const& lineInfo ) -> IGeneratorTracker& { + using namespace Generators; + GeneratorTracker& tracker = GeneratorTracker::acquire( m_trackerContext, TestCaseTracking::NameAndLocation( "generator", lineInfo ) ); + assert( tracker.isOpen() ); + m_lastAssertionInfo.lineInfo = lineInfo; + return tracker; + } + + bool RunContext::testForMissingAssertions(Counts& assertions) { + if (assertions.total() != 0) + return false; + if (!m_config->warnAboutMissingAssertions()) + return false; + if (m_trackerContext.currentTracker().hasChildren()) + return false; + m_totals.assertions.failed++; + assertions.failed++; + return true; + } + + void RunContext::sectionEnded(SectionEndInfo const & endInfo) { + Counts assertions = m_totals.assertions - endInfo.prevAssertions; + bool missingAssertions = testForMissingAssertions(assertions); + + if (!m_activeSections.empty()) { + m_activeSections.back()->close(); + m_activeSections.pop_back(); + } + + m_reporter->sectionEnded(SectionStats(endInfo.sectionInfo, assertions, endInfo.durationInSeconds, missingAssertions)); + m_messages.clear(); + m_messageScopes.clear(); + } + + void RunContext::sectionEndedEarly(SectionEndInfo const & endInfo) { + if (m_unfinishedSections.empty()) + m_activeSections.back()->fail(); + else + m_activeSections.back()->close(); + m_activeSections.pop_back(); + + m_unfinishedSections.push_back(endInfo); + } + void RunContext::benchmarkStarting( BenchmarkInfo const& info ) { + m_reporter->benchmarkStarting( info ); + } + void RunContext::benchmarkEnded( BenchmarkStats const& stats ) { + m_reporter->benchmarkEnded( stats ); + } + + void RunContext::pushScopedMessage(MessageInfo const & message) { + m_messages.push_back(message); + } + + void RunContext::popScopedMessage(MessageInfo const & message) { + m_messages.erase(std::remove(m_messages.begin(), m_messages.end(), message), m_messages.end()); + } + + void RunContext::emplaceUnscopedMessage( MessageBuilder const& builder ) { + m_messageScopes.emplace_back( builder ); + } + + std::string RunContext::getCurrentTestName() const { + return m_activeTestCase + ? m_activeTestCase->getTestCaseInfo().name + : std::string(); + } + + const AssertionResult * RunContext::getLastResult() const { + return &(*m_lastResult); + } + + void RunContext::exceptionEarlyReported() { + m_shouldReportUnexpected = false; + } + + void RunContext::handleFatalErrorCondition( StringRef message ) { + // First notify reporter that bad things happened + m_reporter->fatalErrorEncountered(message); + + // Don't rebuild the result -- the stringification itself can cause more fatal errors + // Instead, fake a result data. + AssertionResultData tempResult( ResultWas::FatalErrorCondition, { false } ); + tempResult.message = message; + AssertionResult result(m_lastAssertionInfo, tempResult); + + assertionEnded(result); + + handleUnfinishedSections(); + + // Recreate section for test case (as we will lose the one that was in scope) + auto const& testCaseInfo = m_activeTestCase->getTestCaseInfo(); + SectionInfo testCaseSection(testCaseInfo.lineInfo, testCaseInfo.name); + + Counts assertions; + assertions.failed = 1; + SectionStats testCaseSectionStats(testCaseSection, assertions, 0, false); + m_reporter->sectionEnded(testCaseSectionStats); + + auto const& testInfo = m_activeTestCase->getTestCaseInfo(); + + Totals deltaTotals; + deltaTotals.testCases.failed = 1; + deltaTotals.assertions.failed = 1; + m_reporter->testCaseEnded(TestCaseStats(testInfo, + deltaTotals, + std::string(), + std::string(), + false)); + m_totals.testCases.failed++; + testGroupEnded(std::string(), m_totals, 1, 1); + m_reporter->testRunEnded(TestRunStats(m_runInfo, m_totals, false)); + } + + bool RunContext::lastAssertionPassed() { + return m_lastAssertionPassed; + } + + void RunContext::assertionPassed() { + m_lastAssertionPassed = true; + ++m_totals.assertions.passed; + resetAssertionInfo(); + m_messageScopes.clear(); + } + + bool RunContext::aborting() const { + return m_totals.assertions.failed >= static_cast(m_config->abortAfter()); + } + + void RunContext::runCurrentTest(std::string & redirectedCout, std::string & redirectedCerr) { + auto const& testCaseInfo = m_activeTestCase->getTestCaseInfo(); + SectionInfo testCaseSection(testCaseInfo.lineInfo, testCaseInfo.name); + m_reporter->sectionStarting(testCaseSection); + Counts prevAssertions = m_totals.assertions; + double duration = 0; + m_shouldReportUnexpected = true; + m_lastAssertionInfo = { "TEST_CASE"_sr, testCaseInfo.lineInfo, StringRef(), ResultDisposition::Normal }; + + seedRng(*m_config); + + Timer timer; + CATCH_TRY { + if (m_reporter->getPreferences().shouldRedirectStdOut) { +#if !defined(CATCH_CONFIG_EXPERIMENTAL_REDIRECT) + RedirectedStreams redirectedStreams(redirectedCout, redirectedCerr); + + timer.start(); + invokeActiveTestCase(); +#else + OutputRedirect r(redirectedCout, redirectedCerr); + timer.start(); + invokeActiveTestCase(); +#endif + } else { + timer.start(); + invokeActiveTestCase(); + } + duration = timer.getElapsedSeconds(); + } CATCH_CATCH_ANON (TestFailureException&) { + // This just means the test was aborted due to failure + } CATCH_CATCH_ALL { + // Under CATCH_CONFIG_FAST_COMPILE, unexpected exceptions under REQUIRE assertions + // are reported without translation at the point of origin. + if( m_shouldReportUnexpected ) { + AssertionReaction dummyReaction; + handleUnexpectedInflightException( m_lastAssertionInfo, translateActiveException(), dummyReaction ); + } + } + Counts assertions = m_totals.assertions - prevAssertions; + bool missingAssertions = testForMissingAssertions(assertions); + + m_testCaseTracker->close(); + handleUnfinishedSections(); + m_messages.clear(); + m_messageScopes.clear(); + + SectionStats testCaseSectionStats(testCaseSection, assertions, duration, missingAssertions); + m_reporter->sectionEnded(testCaseSectionStats); + } + + void RunContext::invokeActiveTestCase() { + FatalConditionHandler fatalConditionHandler; // Handle signals + m_activeTestCase->invoke(); + fatalConditionHandler.reset(); + } + + void RunContext::handleUnfinishedSections() { + // If sections ended prematurely due to an exception we stored their + // infos here so we can tear them down outside the unwind process. + for (auto it = m_unfinishedSections.rbegin(), + itEnd = m_unfinishedSections.rend(); + it != itEnd; + ++it) + sectionEnded(*it); + m_unfinishedSections.clear(); + } + + void RunContext::handleExpr( + AssertionInfo const& info, + ITransientExpression const& expr, + AssertionReaction& reaction + ) { + m_reporter->assertionStarting( info ); + + bool negated = isFalseTest( info.resultDisposition ); + bool result = expr.getResult() != negated; + + if( result ) { + if (!m_includeSuccessfulResults) { + assertionPassed(); + } + else { + reportExpr(info, ResultWas::Ok, &expr, negated); + } + } + else { + reportExpr(info, ResultWas::ExpressionFailed, &expr, negated ); + populateReaction( reaction ); + } + } + void RunContext::reportExpr( + AssertionInfo const &info, + ResultWas::OfType resultType, + ITransientExpression const *expr, + bool negated ) { + + m_lastAssertionInfo = info; + AssertionResultData data( resultType, LazyExpression( negated ) ); + + AssertionResult assertionResult{ info, data }; + assertionResult.m_resultData.lazyExpression.m_transientExpression = expr; + + assertionEnded( assertionResult ); + } + + void RunContext::handleMessage( + AssertionInfo const& info, + ResultWas::OfType resultType, + StringRef const& message, + AssertionReaction& reaction + ) { + m_reporter->assertionStarting( info ); + + m_lastAssertionInfo = info; + + AssertionResultData data( resultType, LazyExpression( false ) ); + data.message = message; + AssertionResult assertionResult{ m_lastAssertionInfo, data }; + assertionEnded( assertionResult ); + if( !assertionResult.isOk() ) + populateReaction( reaction ); + } + void RunContext::handleUnexpectedExceptionNotThrown( + AssertionInfo const& info, + AssertionReaction& reaction + ) { + handleNonExpr(info, Catch::ResultWas::DidntThrowException, reaction); + } + + void RunContext::handleUnexpectedInflightException( + AssertionInfo const& info, + std::string const& message, + AssertionReaction& reaction + ) { + m_lastAssertionInfo = info; + + AssertionResultData data( ResultWas::ThrewException, LazyExpression( false ) ); + data.message = message; + AssertionResult assertionResult{ info, data }; + assertionEnded( assertionResult ); + populateReaction( reaction ); + } + + void RunContext::populateReaction( AssertionReaction& reaction ) { + reaction.shouldDebugBreak = m_config->shouldDebugBreak(); + reaction.shouldThrow = aborting() || (m_lastAssertionInfo.resultDisposition & ResultDisposition::Normal); + } + + void RunContext::handleIncomplete( + AssertionInfo const& info + ) { + m_lastAssertionInfo = info; + + AssertionResultData data( ResultWas::ThrewException, LazyExpression( false ) ); + data.message = "Exception translation was disabled by CATCH_CONFIG_FAST_COMPILE"; + AssertionResult assertionResult{ info, data }; + assertionEnded( assertionResult ); + } + void RunContext::handleNonExpr( + AssertionInfo const &info, + ResultWas::OfType resultType, + AssertionReaction &reaction + ) { + m_lastAssertionInfo = info; + + AssertionResultData data( resultType, LazyExpression( false ) ); + AssertionResult assertionResult{ info, data }; + assertionEnded( assertionResult ); + + if( !assertionResult.isOk() ) + populateReaction( reaction ); + } + + IResultCapture& getResultCapture() { + if (auto* capture = getCurrentContext().getResultCapture()) + return *capture; + else + CATCH_INTERNAL_ERROR("No result capture instance"); + } +} +// end catch_run_context.cpp +// start catch_section.cpp + +namespace Catch { + + Section::Section( SectionInfo const& info ) + : m_info( info ), + m_sectionIncluded( getResultCapture().sectionStarted( m_info, m_assertions ) ) + { + m_timer.start(); + } + + Section::~Section() { + if( m_sectionIncluded ) { + SectionEndInfo endInfo{ m_info, m_assertions, m_timer.getElapsedSeconds() }; + if( uncaught_exceptions() ) + getResultCapture().sectionEndedEarly( endInfo ); + else + getResultCapture().sectionEnded( endInfo ); + } + } + + // This indicates whether the section should be executed or not + Section::operator bool() const { + return m_sectionIncluded; + } + +} // end namespace Catch +// end catch_section.cpp +// start catch_section_info.cpp + +namespace Catch { + + SectionInfo::SectionInfo + ( SourceLineInfo const& _lineInfo, + std::string const& _name ) + : name( _name ), + lineInfo( _lineInfo ) + {} + +} // end namespace Catch +// end catch_section_info.cpp +// start catch_session.cpp + +// start catch_session.h + +#include + +namespace Catch { + + class Session : NonCopyable { + public: + + Session(); + ~Session() override; + + void showHelp() const; + void libIdentify(); + + int applyCommandLine( int argc, char const * const * argv ); + #if defined(CATCH_CONFIG_WCHAR) && defined(WIN32) && defined(UNICODE) + int applyCommandLine( int argc, wchar_t const * const * argv ); + #endif + + void useConfigData( ConfigData const& configData ); + + template + int run(int argc, CharT const * const argv[]) { + if (m_startupExceptions) + return 1; + int returnCode = applyCommandLine(argc, argv); + if (returnCode == 0) + returnCode = run(); + return returnCode; + } + + int run(); + + clara::Parser const& cli() const; + void cli( clara::Parser const& newParser ); + ConfigData& configData(); + Config& config(); + private: + int runInternal(); + + clara::Parser m_cli; + ConfigData m_configData; + std::shared_ptr m_config; + bool m_startupExceptions = false; + }; + +} // end namespace Catch + +// end catch_session.h +// start catch_version.h + +#include + +namespace Catch { + + // Versioning information + struct Version { + Version( Version const& ) = delete; + Version& operator=( Version const& ) = delete; + Version( unsigned int _majorVersion, + unsigned int _minorVersion, + unsigned int _patchNumber, + char const * const _branchName, + unsigned int _buildNumber ); + + unsigned int const majorVersion; + unsigned int const minorVersion; + unsigned int const patchNumber; + + // buildNumber is only used if branchName is not null + char const * const branchName; + unsigned int const buildNumber; + + friend std::ostream& operator << ( std::ostream& os, Version const& version ); + }; + + Version const& libraryVersion(); +} + +// end catch_version.h +#include +#include + +namespace Catch { + + namespace { + const int MaxExitCode = 255; + + IStreamingReporterPtr createReporter(std::string const& reporterName, IConfigPtr const& config) { + auto reporter = Catch::getRegistryHub().getReporterRegistry().create(reporterName, config); + CATCH_ENFORCE(reporter, "No reporter registered with name: '" << reporterName << "'"); + + return reporter; + } + + IStreamingReporterPtr makeReporter(std::shared_ptr const& config) { + if (Catch::getRegistryHub().getReporterRegistry().getListeners().empty()) { + return createReporter(config->getReporterName(), config); + } + + // On older platforms, returning std::unique_ptr + // when the return type is std::unique_ptr + // doesn't compile without a std::move call. However, this causes + // a warning on newer platforms. Thus, we have to work around + // it a bit and downcast the pointer manually. + auto ret = std::unique_ptr(new ListeningReporter); + auto& multi = static_cast(*ret); + auto const& listeners = Catch::getRegistryHub().getReporterRegistry().getListeners(); + for (auto const& listener : listeners) { + multi.addListener(listener->create(Catch::ReporterConfig(config))); + } + multi.addReporter(createReporter(config->getReporterName(), config)); + return ret; + } + + Catch::Totals runTests(std::shared_ptr const& config) { + auto reporter = makeReporter(config); + + RunContext context(config, std::move(reporter)); + + Totals totals; + + context.testGroupStarting(config->name(), 1, 1); + + TestSpec testSpec = config->testSpec(); + + auto const& allTestCases = getAllTestCasesSorted(*config); + for (auto const& testCase : allTestCases) { + if (!context.aborting() && matchTest(testCase, testSpec, *config)) + totals += context.runTest(testCase); + else + context.reporter().skipTest(testCase); + } + + if (config->warnAboutNoTests() && totals.testCases.total() == 0) { + ReusableStringStream testConfig; + + bool first = true; + for (const auto& input : config->getTestsOrTags()) { + if (!first) { testConfig << ' '; } + first = false; + testConfig << input; + } + + context.reporter().noMatchingTestCases(testConfig.str()); + totals.error = -1; + } + + context.testGroupEnded(config->name(), totals, 1, 1); + return totals; + } + + void applyFilenamesAsTags(Catch::IConfig const& config) { + auto& tests = const_cast&>(getAllTestCasesSorted(config)); + for (auto& testCase : tests) { + auto tags = testCase.tags; + + std::string filename = testCase.lineInfo.file; + auto lastSlash = filename.find_last_of("\\/"); + if (lastSlash != std::string::npos) { + filename.erase(0, lastSlash); + filename[0] = '#'; + } + + auto lastDot = filename.find_last_of('.'); + if (lastDot != std::string::npos) { + filename.erase(lastDot); + } + + tags.push_back(std::move(filename)); + setTags(testCase, tags); + } + } + + } // anon namespace + + Session::Session() { + static bool alreadyInstantiated = false; + if( alreadyInstantiated ) { + CATCH_TRY { CATCH_INTERNAL_ERROR( "Only one instance of Catch::Session can ever be used" ); } + CATCH_CATCH_ALL { getMutableRegistryHub().registerStartupException(); } + } + + // There cannot be exceptions at startup in no-exception mode. +#if !defined(CATCH_CONFIG_DISABLE_EXCEPTIONS) + const auto& exceptions = getRegistryHub().getStartupExceptionRegistry().getExceptions(); + if ( !exceptions.empty() ) { + m_startupExceptions = true; + Colour colourGuard( Colour::Red ); + Catch::cerr() << "Errors occurred during startup!" << '\n'; + // iterate over all exceptions and notify user + for ( const auto& ex_ptr : exceptions ) { + try { + std::rethrow_exception(ex_ptr); + } catch ( std::exception const& ex ) { + Catch::cerr() << Column( ex.what() ).indent(2) << '\n'; + } + } + } +#endif + + alreadyInstantiated = true; + m_cli = makeCommandLineParser( m_configData ); + } + Session::~Session() { + Catch::cleanUp(); + } + + void Session::showHelp() const { + Catch::cout() + << "\nCatch v" << libraryVersion() << "\n" + << m_cli << std::endl + << "For more detailed usage please see the project docs\n" << std::endl; + } + void Session::libIdentify() { + Catch::cout() + << std::left << std::setw(16) << "description: " << "A Catch test executable\n" + << std::left << std::setw(16) << "category: " << "testframework\n" + << std::left << std::setw(16) << "framework: " << "Catch Test\n" + << std::left << std::setw(16) << "version: " << libraryVersion() << std::endl; + } + + int Session::applyCommandLine( int argc, char const * const * argv ) { + if( m_startupExceptions ) + return 1; + + auto result = m_cli.parse( clara::Args( argc, argv ) ); + if( !result ) { + config(); + getCurrentMutableContext().setConfig(m_config); + Catch::cerr() + << Colour( Colour::Red ) + << "\nError(s) in input:\n" + << Column( result.errorMessage() ).indent( 2 ) + << "\n\n"; + Catch::cerr() << "Run with -? for usage\n" << std::endl; + return MaxExitCode; + } + + if( m_configData.showHelp ) + showHelp(); + if( m_configData.libIdentify ) + libIdentify(); + m_config.reset(); + return 0; + } + +#if defined(CATCH_CONFIG_WCHAR) && defined(WIN32) && defined(UNICODE) + int Session::applyCommandLine( int argc, wchar_t const * const * argv ) { + + char **utf8Argv = new char *[ argc ]; + + for ( int i = 0; i < argc; ++i ) { + int bufSize = WideCharToMultiByte( CP_UTF8, 0, argv[i], -1, NULL, 0, NULL, NULL ); + + utf8Argv[ i ] = new char[ bufSize ]; + + WideCharToMultiByte( CP_UTF8, 0, argv[i], -1, utf8Argv[i], bufSize, NULL, NULL ); + } + + int returnCode = applyCommandLine( argc, utf8Argv ); + + for ( int i = 0; i < argc; ++i ) + delete [] utf8Argv[ i ]; + + delete [] utf8Argv; + + return returnCode; + } +#endif + + void Session::useConfigData( ConfigData const& configData ) { + m_configData = configData; + m_config.reset(); + } + + int Session::run() { + if( ( m_configData.waitForKeypress & WaitForKeypress::BeforeStart ) != 0 ) { + Catch::cout() << "...waiting for enter/ return before starting" << std::endl; + static_cast(std::getchar()); + } + int exitCode = runInternal(); + if( ( m_configData.waitForKeypress & WaitForKeypress::BeforeExit ) != 0 ) { + Catch::cout() << "...waiting for enter/ return before exiting, with code: " << exitCode << std::endl; + static_cast(std::getchar()); + } + return exitCode; + } + + clara::Parser const& Session::cli() const { + return m_cli; + } + void Session::cli( clara::Parser const& newParser ) { + m_cli = newParser; + } + ConfigData& Session::configData() { + return m_configData; + } + Config& Session::config() { + if( !m_config ) + m_config = std::make_shared( m_configData ); + return *m_config; + } + + int Session::runInternal() { + if( m_startupExceptions ) + return 1; + + if (m_configData.showHelp || m_configData.libIdentify) { + return 0; + } + + CATCH_TRY { + config(); // Force config to be constructed + + seedRng( *m_config ); + + if( m_configData.filenamesAsTags ) + applyFilenamesAsTags( *m_config ); + + // Handle list request + if( Option listed = list( m_config ) ) + return static_cast( *listed ); + + auto totals = runTests( m_config ); + // Note that on unices only the lower 8 bits are usually used, clamping + // the return value to 255 prevents false negative when some multiple + // of 256 tests has failed + return (std::min) (MaxExitCode, (std::max) (totals.error, static_cast(totals.assertions.failed))); + } +#if !defined(CATCH_CONFIG_DISABLE_EXCEPTIONS) + catch( std::exception& ex ) { + Catch::cerr() << ex.what() << std::endl; + return MaxExitCode; + } +#endif + } + +} // end namespace Catch +// end catch_session.cpp +// start catch_singletons.cpp + +#include + +namespace Catch { + + namespace { + static auto getSingletons() -> std::vector*& { + static std::vector* g_singletons = nullptr; + if( !g_singletons ) + g_singletons = new std::vector(); + return g_singletons; + } + } + + ISingleton::~ISingleton() {} + + void addSingleton(ISingleton* singleton ) { + getSingletons()->push_back( singleton ); + } + void cleanupSingletons() { + auto& singletons = getSingletons(); + for( auto singleton : *singletons ) + delete singleton; + delete singletons; + singletons = nullptr; + } + +} // namespace Catch +// end catch_singletons.cpp +// start catch_startup_exception_registry.cpp + +namespace Catch { +void StartupExceptionRegistry::add( std::exception_ptr const& exception ) noexcept { + CATCH_TRY { + m_exceptions.push_back(exception); + } CATCH_CATCH_ALL { + // If we run out of memory during start-up there's really not a lot more we can do about it + std::terminate(); + } + } + + std::vector const& StartupExceptionRegistry::getExceptions() const noexcept { + return m_exceptions; + } + +} // end namespace Catch +// end catch_startup_exception_registry.cpp +// start catch_stream.cpp + +#include +#include +#include +#include +#include +#include + +namespace Catch { + + Catch::IStream::~IStream() = default; + + namespace detail { namespace { + template + class StreamBufImpl : public std::streambuf { + char data[bufferSize]; + WriterF m_writer; + + public: + StreamBufImpl() { + setp( data, data + sizeof(data) ); + } + + ~StreamBufImpl() noexcept { + StreamBufImpl::sync(); + } + + private: + int overflow( int c ) override { + sync(); + + if( c != EOF ) { + if( pbase() == epptr() ) + m_writer( std::string( 1, static_cast( c ) ) ); + else + sputc( static_cast( c ) ); + } + return 0; + } + + int sync() override { + if( pbase() != pptr() ) { + m_writer( std::string( pbase(), static_cast( pptr() - pbase() ) ) ); + setp( pbase(), epptr() ); + } + return 0; + } + }; + + /////////////////////////////////////////////////////////////////////////// + + struct OutputDebugWriter { + + void operator()( std::string const&str ) { + writeToDebugConsole( str ); + } + }; + + /////////////////////////////////////////////////////////////////////////// + + class FileStream : public IStream { + mutable std::ofstream m_ofs; + public: + FileStream( StringRef filename ) { + m_ofs.open( filename.c_str() ); + CATCH_ENFORCE( !m_ofs.fail(), "Unable to open file: '" << filename << "'" ); + } + ~FileStream() override = default; + public: // IStream + std::ostream& stream() const override { + return m_ofs; + } + }; + + /////////////////////////////////////////////////////////////////////////// + + class CoutStream : public IStream { + mutable std::ostream m_os; + public: + // Store the streambuf from cout up-front because + // cout may get redirected when running tests + CoutStream() : m_os( Catch::cout().rdbuf() ) {} + ~CoutStream() override = default; + + public: // IStream + std::ostream& stream() const override { return m_os; } + }; + + /////////////////////////////////////////////////////////////////////////// + + class DebugOutStream : public IStream { + std::unique_ptr> m_streamBuf; + mutable std::ostream m_os; + public: + DebugOutStream() + : m_streamBuf( new StreamBufImpl() ), + m_os( m_streamBuf.get() ) + {} + + ~DebugOutStream() override = default; + + public: // IStream + std::ostream& stream() const override { return m_os; } + }; + + }} // namespace anon::detail + + /////////////////////////////////////////////////////////////////////////// + + auto makeStream( StringRef const &filename ) -> IStream const* { + if( filename.empty() ) + return new detail::CoutStream(); + else if( filename[0] == '%' ) { + if( filename == "%debug" ) + return new detail::DebugOutStream(); + else + CATCH_ERROR( "Unrecognised stream: '" << filename << "'" ); + } + else + return new detail::FileStream( filename ); + } + + // This class encapsulates the idea of a pool of ostringstreams that can be reused. + struct StringStreams { + std::vector> m_streams; + std::vector m_unused; + std::ostringstream m_referenceStream; // Used for copy state/ flags from + + auto add() -> std::size_t { + if( m_unused.empty() ) { + m_streams.push_back( std::unique_ptr( new std::ostringstream ) ); + return m_streams.size()-1; + } + else { + auto index = m_unused.back(); + m_unused.pop_back(); + return index; + } + } + + void release( std::size_t index ) { + m_streams[index]->copyfmt( m_referenceStream ); // Restore initial flags and other state + m_unused.push_back(index); + } + }; + + ReusableStringStream::ReusableStringStream() + : m_index( Singleton::getMutable().add() ), + m_oss( Singleton::getMutable().m_streams[m_index].get() ) + {} + + ReusableStringStream::~ReusableStringStream() { + static_cast( m_oss )->str(""); + m_oss->clear(); + Singleton::getMutable().release( m_index ); + } + + auto ReusableStringStream::str() const -> std::string { + return static_cast( m_oss )->str(); + } + + /////////////////////////////////////////////////////////////////////////// + +#ifndef CATCH_CONFIG_NOSTDOUT // If you #define this you must implement these functions + std::ostream& cout() { return std::cout; } + std::ostream& cerr() { return std::cerr; } + std::ostream& clog() { return std::clog; } +#endif +} +// end catch_stream.cpp +// start catch_string_manip.cpp + +#include +#include +#include +#include + +namespace Catch { + + namespace { + char toLowerCh(char c) { + return static_cast( std::tolower( c ) ); + } + } + + bool startsWith( std::string const& s, std::string const& prefix ) { + return s.size() >= prefix.size() && std::equal(prefix.begin(), prefix.end(), s.begin()); + } + bool startsWith( std::string const& s, char prefix ) { + return !s.empty() && s[0] == prefix; + } + bool endsWith( std::string const& s, std::string const& suffix ) { + return s.size() >= suffix.size() && std::equal(suffix.rbegin(), suffix.rend(), s.rbegin()); + } + bool endsWith( std::string const& s, char suffix ) { + return !s.empty() && s[s.size()-1] == suffix; + } + bool contains( std::string const& s, std::string const& infix ) { + return s.find( infix ) != std::string::npos; + } + void toLowerInPlace( std::string& s ) { + std::transform( s.begin(), s.end(), s.begin(), toLowerCh ); + } + std::string toLower( std::string const& s ) { + std::string lc = s; + toLowerInPlace( lc ); + return lc; + } + std::string trim( std::string const& str ) { + static char const* whitespaceChars = "\n\r\t "; + std::string::size_type start = str.find_first_not_of( whitespaceChars ); + std::string::size_type end = str.find_last_not_of( whitespaceChars ); + + return start != std::string::npos ? str.substr( start, 1+end-start ) : std::string(); + } + + bool replaceInPlace( std::string& str, std::string const& replaceThis, std::string const& withThis ) { + bool replaced = false; + std::size_t i = str.find( replaceThis ); + while( i != std::string::npos ) { + replaced = true; + str = str.substr( 0, i ) + withThis + str.substr( i+replaceThis.size() ); + if( i < str.size()-withThis.size() ) + i = str.find( replaceThis, i+withThis.size() ); + else + i = std::string::npos; + } + return replaced; + } + + pluralise::pluralise( std::size_t count, std::string const& label ) + : m_count( count ), + m_label( label ) + {} + + std::ostream& operator << ( std::ostream& os, pluralise const& pluraliser ) { + os << pluraliser.m_count << ' ' << pluraliser.m_label; + if( pluraliser.m_count != 1 ) + os << 's'; + return os; + } + +} +// end catch_string_manip.cpp +// start catch_stringref.cpp + +#if defined(__clang__) +# pragma clang diagnostic push +# pragma clang diagnostic ignored "-Wexit-time-destructors" +#endif + +#include +#include +#include + +namespace { + const uint32_t byte_2_lead = 0xC0; + const uint32_t byte_3_lead = 0xE0; + const uint32_t byte_4_lead = 0xF0; +} + +namespace Catch { + StringRef::StringRef( char const* rawChars ) noexcept + : StringRef( rawChars, static_cast(std::strlen(rawChars) ) ) + {} + + StringRef::operator std::string() const { + return std::string( m_start, m_size ); + } + + void StringRef::swap( StringRef& other ) noexcept { + std::swap( m_start, other.m_start ); + std::swap( m_size, other.m_size ); + std::swap( m_data, other.m_data ); + } + + auto StringRef::c_str() const -> char const* { + if( isSubstring() ) + const_cast( this )->takeOwnership(); + return m_start; + } + auto StringRef::currentData() const noexcept -> char const* { + return m_start; + } + + auto StringRef::isOwned() const noexcept -> bool { + return m_data != nullptr; + } + auto StringRef::isSubstring() const noexcept -> bool { + return m_start[m_size] != '\0'; + } + + void StringRef::takeOwnership() { + if( !isOwned() ) { + m_data = new char[m_size+1]; + memcpy( m_data, m_start, m_size ); + m_data[m_size] = '\0'; + m_start = m_data; + } + } + auto StringRef::substr( size_type start, size_type size ) const noexcept -> StringRef { + if( start < m_size ) + return StringRef( m_start+start, size ); + else + return StringRef(); + } + auto StringRef::operator == ( StringRef const& other ) const noexcept -> bool { + return + size() == other.size() && + (std::strncmp( m_start, other.m_start, size() ) == 0); + } + auto StringRef::operator != ( StringRef const& other ) const noexcept -> bool { + return !operator==( other ); + } + + auto StringRef::operator[](size_type index) const noexcept -> char { + return m_start[index]; + } + + auto StringRef::numberOfCharacters() const noexcept -> size_type { + size_type noChars = m_size; + // Make adjustments for uft encodings + for( size_type i=0; i < m_size; ++i ) { + char c = m_start[i]; + if( ( c & byte_2_lead ) == byte_2_lead ) { + noChars--; + if (( c & byte_3_lead ) == byte_3_lead ) + noChars--; + if( ( c & byte_4_lead ) == byte_4_lead ) + noChars--; + } + } + return noChars; + } + + auto operator + ( StringRef const& lhs, StringRef const& rhs ) -> std::string { + std::string str; + str.reserve( lhs.size() + rhs.size() ); + str += lhs; + str += rhs; + return str; + } + auto operator + ( StringRef const& lhs, const char* rhs ) -> std::string { + return std::string( lhs ) + std::string( rhs ); + } + auto operator + ( char const* lhs, StringRef const& rhs ) -> std::string { + return std::string( lhs ) + std::string( rhs ); + } + + auto operator << ( std::ostream& os, StringRef const& str ) -> std::ostream& { + return os.write(str.currentData(), str.size()); + } + + auto operator+=( std::string& lhs, StringRef const& rhs ) -> std::string& { + lhs.append(rhs.currentData(), rhs.size()); + return lhs; + } + +} // namespace Catch + +#if defined(__clang__) +# pragma clang diagnostic pop +#endif +// end catch_stringref.cpp +// start catch_tag_alias.cpp + +namespace Catch { + TagAlias::TagAlias(std::string const & _tag, SourceLineInfo _lineInfo): tag(_tag), lineInfo(_lineInfo) {} +} +// end catch_tag_alias.cpp +// start catch_tag_alias_autoregistrar.cpp + +namespace Catch { + + RegistrarForTagAliases::RegistrarForTagAliases(char const* alias, char const* tag, SourceLineInfo const& lineInfo) { + CATCH_TRY { + getMutableRegistryHub().registerTagAlias(alias, tag, lineInfo); + } CATCH_CATCH_ALL { + // Do not throw when constructing global objects, instead register the exception to be processed later + getMutableRegistryHub().registerStartupException(); + } + } + +} +// end catch_tag_alias_autoregistrar.cpp +// start catch_tag_alias_registry.cpp + +#include + +namespace Catch { + + TagAliasRegistry::~TagAliasRegistry() {} + + TagAlias const* TagAliasRegistry::find( std::string const& alias ) const { + auto it = m_registry.find( alias ); + if( it != m_registry.end() ) + return &(it->second); + else + return nullptr; + } + + std::string TagAliasRegistry::expandAliases( std::string const& unexpandedTestSpec ) const { + std::string expandedTestSpec = unexpandedTestSpec; + for( auto const& registryKvp : m_registry ) { + std::size_t pos = expandedTestSpec.find( registryKvp.first ); + if( pos != std::string::npos ) { + expandedTestSpec = expandedTestSpec.substr( 0, pos ) + + registryKvp.second.tag + + expandedTestSpec.substr( pos + registryKvp.first.size() ); + } + } + return expandedTestSpec; + } + + void TagAliasRegistry::add( std::string const& alias, std::string const& tag, SourceLineInfo const& lineInfo ) { + CATCH_ENFORCE( startsWith(alias, "[@") && endsWith(alias, ']'), + "error: tag alias, '" << alias << "' is not of the form [@alias name].\n" << lineInfo ); + + CATCH_ENFORCE( m_registry.insert(std::make_pair(alias, TagAlias(tag, lineInfo))).second, + "error: tag alias, '" << alias << "' already registered.\n" + << "\tFirst seen at: " << find(alias)->lineInfo << "\n" + << "\tRedefined at: " << lineInfo ); + } + + ITagAliasRegistry::~ITagAliasRegistry() {} + + ITagAliasRegistry const& ITagAliasRegistry::get() { + return getRegistryHub().getTagAliasRegistry(); + } + +} // end namespace Catch +// end catch_tag_alias_registry.cpp +// start catch_test_case_info.cpp + +#include +#include +#include +#include + +namespace Catch { + + namespace { + TestCaseInfo::SpecialProperties parseSpecialTag( std::string const& tag ) { + if( startsWith( tag, '.' ) || + tag == "!hide" ) + return TestCaseInfo::IsHidden; + else if( tag == "!throws" ) + return TestCaseInfo::Throws; + else if( tag == "!shouldfail" ) + return TestCaseInfo::ShouldFail; + else if( tag == "!mayfail" ) + return TestCaseInfo::MayFail; + else if( tag == "!nonportable" ) + return TestCaseInfo::NonPortable; + else if( tag == "!benchmark" ) + return static_cast( TestCaseInfo::Benchmark | TestCaseInfo::IsHidden ); + else + return TestCaseInfo::None; + } + bool isReservedTag( std::string const& tag ) { + return parseSpecialTag( tag ) == TestCaseInfo::None && tag.size() > 0 && !std::isalnum( static_cast(tag[0]) ); + } + void enforceNotReservedTag( std::string const& tag, SourceLineInfo const& _lineInfo ) { + CATCH_ENFORCE( !isReservedTag(tag), + "Tag name: [" << tag << "] is not allowed.\n" + << "Tag names starting with non alpha-numeric characters are reserved\n" + << _lineInfo ); + } + } + + TestCase makeTestCase( ITestInvoker* _testCase, + std::string const& _className, + NameAndTags const& nameAndTags, + SourceLineInfo const& _lineInfo ) + { + bool isHidden = false; + + // Parse out tags + std::vector tags; + std::string desc, tag; + bool inTag = false; + std::string _descOrTags = nameAndTags.tags; + for (char c : _descOrTags) { + if( !inTag ) { + if( c == '[' ) + inTag = true; + else + desc += c; + } + else { + if( c == ']' ) { + TestCaseInfo::SpecialProperties prop = parseSpecialTag( tag ); + if( ( prop & TestCaseInfo::IsHidden ) != 0 ) + isHidden = true; + else if( prop == TestCaseInfo::None ) + enforceNotReservedTag( tag, _lineInfo ); + + tags.push_back( tag ); + tag.clear(); + inTag = false; + } + else + tag += c; + } + } + if( isHidden ) { + tags.push_back( "." ); + } + + TestCaseInfo info( nameAndTags.name, _className, desc, tags, _lineInfo ); + return TestCase( _testCase, std::move(info) ); + } + + void setTags( TestCaseInfo& testCaseInfo, std::vector tags ) { + std::sort(begin(tags), end(tags)); + tags.erase(std::unique(begin(tags), end(tags)), end(tags)); + testCaseInfo.lcaseTags.clear(); + + for( auto const& tag : tags ) { + std::string lcaseTag = toLower( tag ); + testCaseInfo.properties = static_cast( testCaseInfo.properties | parseSpecialTag( lcaseTag ) ); + testCaseInfo.lcaseTags.push_back( lcaseTag ); + } + testCaseInfo.tags = std::move(tags); + } + + TestCaseInfo::TestCaseInfo( std::string const& _name, + std::string const& _className, + std::string const& _description, + std::vector const& _tags, + SourceLineInfo const& _lineInfo ) + : name( _name ), + className( _className ), + description( _description ), + lineInfo( _lineInfo ), + properties( None ) + { + setTags( *this, _tags ); + } + + bool TestCaseInfo::isHidden() const { + return ( properties & IsHidden ) != 0; + } + bool TestCaseInfo::throws() const { + return ( properties & Throws ) != 0; + } + bool TestCaseInfo::okToFail() const { + return ( properties & (ShouldFail | MayFail ) ) != 0; + } + bool TestCaseInfo::expectedToFail() const { + return ( properties & (ShouldFail ) ) != 0; + } + + std::string TestCaseInfo::tagsAsString() const { + std::string ret; + // '[' and ']' per tag + std::size_t full_size = 2 * tags.size(); + for (const auto& tag : tags) { + full_size += tag.size(); + } + ret.reserve(full_size); + for (const auto& tag : tags) { + ret.push_back('['); + ret.append(tag); + ret.push_back(']'); + } + + return ret; + } + + TestCase::TestCase( ITestInvoker* testCase, TestCaseInfo&& info ) : TestCaseInfo( std::move(info) ), test( testCase ) {} + + TestCase TestCase::withName( std::string const& _newName ) const { + TestCase other( *this ); + other.name = _newName; + return other; + } + + void TestCase::invoke() const { + test->invoke(); + } + + bool TestCase::operator == ( TestCase const& other ) const { + return test.get() == other.test.get() && + name == other.name && + className == other.className; + } + + bool TestCase::operator < ( TestCase const& other ) const { + return name < other.name; + } + + TestCaseInfo const& TestCase::getTestCaseInfo() const + { + return *this; + } + +} // end namespace Catch +// end catch_test_case_info.cpp +// start catch_test_case_registry_impl.cpp + +#include + +namespace Catch { + + std::vector sortTests( IConfig const& config, std::vector const& unsortedTestCases ) { + + std::vector sorted = unsortedTestCases; + + switch( config.runOrder() ) { + case RunTests::InLexicographicalOrder: + std::sort( sorted.begin(), sorted.end() ); + break; + case RunTests::InRandomOrder: + seedRng( config ); + std::shuffle( sorted.begin(), sorted.end(), rng() ); + break; + case RunTests::InDeclarationOrder: + // already in declaration order + break; + } + return sorted; + } + bool matchTest( TestCase const& testCase, TestSpec const& testSpec, IConfig const& config ) { + return testSpec.matches( testCase ) && ( config.allowThrows() || !testCase.throws() ); + } + + void enforceNoDuplicateTestCases( std::vector const& functions ) { + std::set seenFunctions; + for( auto const& function : functions ) { + auto prev = seenFunctions.insert( function ); + CATCH_ENFORCE( prev.second, + "error: TEST_CASE( \"" << function.name << "\" ) already defined.\n" + << "\tFirst seen at " << prev.first->getTestCaseInfo().lineInfo << "\n" + << "\tRedefined at " << function.getTestCaseInfo().lineInfo ); + } + } + + std::vector filterTests( std::vector const& testCases, TestSpec const& testSpec, IConfig const& config ) { + std::vector filtered; + filtered.reserve( testCases.size() ); + for( auto const& testCase : testCases ) + if( matchTest( testCase, testSpec, config ) ) + filtered.push_back( testCase ); + return filtered; + } + std::vector const& getAllTestCasesSorted( IConfig const& config ) { + return getRegistryHub().getTestCaseRegistry().getAllTestsSorted( config ); + } + + void TestRegistry::registerTest( TestCase const& testCase ) { + std::string name = testCase.getTestCaseInfo().name; + if( name.empty() ) { + ReusableStringStream rss; + rss << "Anonymous test case " << ++m_unnamedCount; + return registerTest( testCase.withName( rss.str() ) ); + } + m_functions.push_back( testCase ); + } + + std::vector const& TestRegistry::getAllTests() const { + return m_functions; + } + std::vector const& TestRegistry::getAllTestsSorted( IConfig const& config ) const { + if( m_sortedFunctions.empty() ) + enforceNoDuplicateTestCases( m_functions ); + + if( m_currentSortOrder != config.runOrder() || m_sortedFunctions.empty() ) { + m_sortedFunctions = sortTests( config, m_functions ); + m_currentSortOrder = config.runOrder(); + } + return m_sortedFunctions; + } + + /////////////////////////////////////////////////////////////////////////// + TestInvokerAsFunction::TestInvokerAsFunction( void(*testAsFunction)() ) noexcept : m_testAsFunction( testAsFunction ) {} + + void TestInvokerAsFunction::invoke() const { + m_testAsFunction(); + } + + std::string extractClassName( StringRef const& classOrQualifiedMethodName ) { + std::string className = classOrQualifiedMethodName; + if( startsWith( className, '&' ) ) + { + std::size_t lastColons = className.rfind( "::" ); + std::size_t penultimateColons = className.rfind( "::", lastColons-1 ); + if( penultimateColons == std::string::npos ) + penultimateColons = 1; + className = className.substr( penultimateColons, lastColons-penultimateColons ); + } + return className; + } + +} // end namespace Catch +// end catch_test_case_registry_impl.cpp +// start catch_test_case_tracker.cpp + +#include +#include +#include +#include +#include + +#if defined(__clang__) +# pragma clang diagnostic push +# pragma clang diagnostic ignored "-Wexit-time-destructors" +#endif + +namespace Catch { +namespace TestCaseTracking { + + NameAndLocation::NameAndLocation( std::string const& _name, SourceLineInfo const& _location ) + : name( _name ), + location( _location ) + {} + + ITracker::~ITracker() = default; + + TrackerContext& TrackerContext::instance() { + static TrackerContext s_instance; + return s_instance; + } + + ITracker& TrackerContext::startRun() { + m_rootTracker = std::make_shared( NameAndLocation( "{root}", CATCH_INTERNAL_LINEINFO ), *this, nullptr ); + m_currentTracker = nullptr; + m_runState = Executing; + return *m_rootTracker; + } + + void TrackerContext::endRun() { + m_rootTracker.reset(); + m_currentTracker = nullptr; + m_runState = NotStarted; + } + + void TrackerContext::startCycle() { + m_currentTracker = m_rootTracker.get(); + m_runState = Executing; + } + void TrackerContext::completeCycle() { + m_runState = CompletedCycle; + } + + bool TrackerContext::completedCycle() const { + return m_runState == CompletedCycle; + } + ITracker& TrackerContext::currentTracker() { + return *m_currentTracker; + } + void TrackerContext::setCurrentTracker( ITracker* tracker ) { + m_currentTracker = tracker; + } + + TrackerBase::TrackerBase( NameAndLocation const& nameAndLocation, TrackerContext& ctx, ITracker* parent ) + : m_nameAndLocation( nameAndLocation ), + m_ctx( ctx ), + m_parent( parent ) + {} + + NameAndLocation const& TrackerBase::nameAndLocation() const { + return m_nameAndLocation; + } + bool TrackerBase::isComplete() const { + return m_runState == CompletedSuccessfully || m_runState == Failed; + } + bool TrackerBase::isSuccessfullyCompleted() const { + return m_runState == CompletedSuccessfully; + } + bool TrackerBase::isOpen() const { + return m_runState != NotStarted && !isComplete(); + } + bool TrackerBase::hasChildren() const { + return !m_children.empty(); + } + + void TrackerBase::addChild( ITrackerPtr const& child ) { + m_children.push_back( child ); + } + + ITrackerPtr TrackerBase::findChild( NameAndLocation const& nameAndLocation ) { + auto it = std::find_if( m_children.begin(), m_children.end(), + [&nameAndLocation]( ITrackerPtr const& tracker ){ + return + tracker->nameAndLocation().location == nameAndLocation.location && + tracker->nameAndLocation().name == nameAndLocation.name; + } ); + return( it != m_children.end() ) + ? *it + : nullptr; + } + ITracker& TrackerBase::parent() { + assert( m_parent ); // Should always be non-null except for root + return *m_parent; + } + + void TrackerBase::openChild() { + if( m_runState != ExecutingChildren ) { + m_runState = ExecutingChildren; + if( m_parent ) + m_parent->openChild(); + } + } + + bool TrackerBase::isSectionTracker() const { return false; } + bool TrackerBase::isGeneratorTracker() const { return false; } + + void TrackerBase::open() { + m_runState = Executing; + moveToThis(); + if( m_parent ) + m_parent->openChild(); + } + + void TrackerBase::close() { + + // Close any still open children (e.g. generators) + while( &m_ctx.currentTracker() != this ) + m_ctx.currentTracker().close(); + + switch( m_runState ) { + case NeedsAnotherRun: + break; + + case Executing: + m_runState = CompletedSuccessfully; + break; + case ExecutingChildren: + if( m_children.empty() || m_children.back()->isComplete() ) + m_runState = CompletedSuccessfully; + break; + + case NotStarted: + case CompletedSuccessfully: + case Failed: + CATCH_INTERNAL_ERROR( "Illogical state: " << m_runState ); + + default: + CATCH_INTERNAL_ERROR( "Unknown state: " << m_runState ); + } + moveToParent(); + m_ctx.completeCycle(); + } + void TrackerBase::fail() { + m_runState = Failed; + if( m_parent ) + m_parent->markAsNeedingAnotherRun(); + moveToParent(); + m_ctx.completeCycle(); + } + void TrackerBase::markAsNeedingAnotherRun() { + m_runState = NeedsAnotherRun; + } + + void TrackerBase::moveToParent() { + assert( m_parent ); + m_ctx.setCurrentTracker( m_parent ); + } + void TrackerBase::moveToThis() { + m_ctx.setCurrentTracker( this ); + } + + SectionTracker::SectionTracker( NameAndLocation const& nameAndLocation, TrackerContext& ctx, ITracker* parent ) + : TrackerBase( nameAndLocation, ctx, parent ) + { + if( parent ) { + while( !parent->isSectionTracker() ) + parent = &parent->parent(); + + SectionTracker& parentSection = static_cast( *parent ); + addNextFilters( parentSection.m_filters ); + } + } + + bool SectionTracker::isComplete() const { + bool complete = true; + + if ((m_filters.empty() || m_filters[0] == "") || + std::find(m_filters.begin(), m_filters.end(), + m_nameAndLocation.name) != m_filters.end()) + complete = TrackerBase::isComplete(); + return complete; + + } + + bool SectionTracker::isSectionTracker() const { return true; } + + SectionTracker& SectionTracker::acquire( TrackerContext& ctx, NameAndLocation const& nameAndLocation ) { + std::shared_ptr section; + + ITracker& currentTracker = ctx.currentTracker(); + if( ITrackerPtr childTracker = currentTracker.findChild( nameAndLocation ) ) { + assert( childTracker ); + assert( childTracker->isSectionTracker() ); + section = std::static_pointer_cast( childTracker ); + } + else { + section = std::make_shared( nameAndLocation, ctx, ¤tTracker ); + currentTracker.addChild( section ); + } + if( !ctx.completedCycle() ) + section->tryOpen(); + return *section; + } + + void SectionTracker::tryOpen() { + if( !isComplete() && (m_filters.empty() || m_filters[0].empty() || m_filters[0] == m_nameAndLocation.name ) ) + open(); + } + + void SectionTracker::addInitialFilters( std::vector const& filters ) { + if( !filters.empty() ) { + m_filters.push_back(""); // Root - should never be consulted + m_filters.push_back(""); // Test Case - not a section filter + m_filters.insert( m_filters.end(), filters.begin(), filters.end() ); + } + } + void SectionTracker::addNextFilters( std::vector const& filters ) { + if( filters.size() > 1 ) + m_filters.insert( m_filters.end(), ++filters.begin(), filters.end() ); + } + +} // namespace TestCaseTracking + +using TestCaseTracking::ITracker; +using TestCaseTracking::TrackerContext; +using TestCaseTracking::SectionTracker; + +} // namespace Catch + +#if defined(__clang__) +# pragma clang diagnostic pop +#endif +// end catch_test_case_tracker.cpp +// start catch_test_registry.cpp + +namespace Catch { + + auto makeTestInvoker( void(*testAsFunction)() ) noexcept -> ITestInvoker* { + return new(std::nothrow) TestInvokerAsFunction( testAsFunction ); + } + + NameAndTags::NameAndTags( StringRef const& name_ , StringRef const& tags_ ) noexcept : name( name_ ), tags( tags_ ) {} + + AutoReg::AutoReg( ITestInvoker* invoker, SourceLineInfo const& lineInfo, StringRef const& classOrMethod, NameAndTags const& nameAndTags ) noexcept { + CATCH_TRY { + getMutableRegistryHub() + .registerTest( + makeTestCase( + invoker, + extractClassName( classOrMethod ), + nameAndTags, + lineInfo)); + } CATCH_CATCH_ALL { + // Do not throw when constructing global objects, instead register the exception to be processed later + getMutableRegistryHub().registerStartupException(); + } + } + + AutoReg::~AutoReg() = default; +} +// end catch_test_registry.cpp +// start catch_test_spec.cpp + +#include +#include +#include +#include + +namespace Catch { + + TestSpec::Pattern::~Pattern() = default; + TestSpec::NamePattern::~NamePattern() = default; + TestSpec::TagPattern::~TagPattern() = default; + TestSpec::ExcludedPattern::~ExcludedPattern() = default; + + TestSpec::NamePattern::NamePattern( std::string const& name ) + : m_wildcardPattern( toLower( name ), CaseSensitive::No ) + {} + bool TestSpec::NamePattern::matches( TestCaseInfo const& testCase ) const { + return m_wildcardPattern.matches( toLower( testCase.name ) ); + } + + TestSpec::TagPattern::TagPattern( std::string const& tag ) : m_tag( toLower( tag ) ) {} + bool TestSpec::TagPattern::matches( TestCaseInfo const& testCase ) const { + return std::find(begin(testCase.lcaseTags), + end(testCase.lcaseTags), + m_tag) != end(testCase.lcaseTags); + } + + TestSpec::ExcludedPattern::ExcludedPattern( PatternPtr const& underlyingPattern ) : m_underlyingPattern( underlyingPattern ) {} + bool TestSpec::ExcludedPattern::matches( TestCaseInfo const& testCase ) const { return !m_underlyingPattern->matches( testCase ); } + + bool TestSpec::Filter::matches( TestCaseInfo const& testCase ) const { + // All patterns in a filter must match for the filter to be a match + for( auto const& pattern : m_patterns ) { + if( !pattern->matches( testCase ) ) + return false; + } + return true; + } + + bool TestSpec::hasFilters() const { + return !m_filters.empty(); + } + bool TestSpec::matches( TestCaseInfo const& testCase ) const { + // A TestSpec matches if any filter matches + for( auto const& filter : m_filters ) + if( filter.matches( testCase ) ) + return true; + return false; + } +} +// end catch_test_spec.cpp +// start catch_test_spec_parser.cpp + +namespace Catch { + + TestSpecParser::TestSpecParser( ITagAliasRegistry const& tagAliases ) : m_tagAliases( &tagAliases ) {} + + TestSpecParser& TestSpecParser::parse( std::string const& arg ) { + m_mode = None; + m_exclusion = false; + m_start = std::string::npos; + m_arg = m_tagAliases->expandAliases( arg ); + m_escapeChars.clear(); + for( m_pos = 0; m_pos < m_arg.size(); ++m_pos ) + visitChar( m_arg[m_pos] ); + if( m_mode == Name ) + addPattern(); + return *this; + } + TestSpec TestSpecParser::testSpec() { + addFilter(); + return m_testSpec; + } + + void TestSpecParser::visitChar( char c ) { + if( m_mode == None ) { + switch( c ) { + case ' ': return; + case '~': m_exclusion = true; return; + case '[': return startNewMode( Tag, ++m_pos ); + case '"': return startNewMode( QuotedName, ++m_pos ); + case '\\': return escape(); + default: startNewMode( Name, m_pos ); break; + } + } + if( m_mode == Name ) { + if( c == ',' ) { + addPattern(); + addFilter(); + } + else if( c == '[' ) { + if( subString() == "exclude:" ) + m_exclusion = true; + else + addPattern(); + startNewMode( Tag, ++m_pos ); + } + else if( c == '\\' ) + escape(); + } + else if( m_mode == EscapedName ) + m_mode = Name; + else if( m_mode == QuotedName && c == '"' ) + addPattern(); + else if( m_mode == Tag && c == ']' ) + addPattern(); + } + void TestSpecParser::startNewMode( Mode mode, std::size_t start ) { + m_mode = mode; + m_start = start; + } + void TestSpecParser::escape() { + if( m_mode == None ) + m_start = m_pos; + m_mode = EscapedName; + m_escapeChars.push_back( m_pos ); + } + std::string TestSpecParser::subString() const { return m_arg.substr( m_start, m_pos - m_start ); } + + void TestSpecParser::addFilter() { + if( !m_currentFilter.m_patterns.empty() ) { + m_testSpec.m_filters.push_back( m_currentFilter ); + m_currentFilter = TestSpec::Filter(); + } + } + + TestSpec parseTestSpec( std::string const& arg ) { + return TestSpecParser( ITagAliasRegistry::get() ).parse( arg ).testSpec(); + } + +} // namespace Catch +// end catch_test_spec_parser.cpp +// start catch_timer.cpp + +#include + +static const uint64_t nanosecondsInSecond = 1000000000; + +namespace Catch { + + auto getCurrentNanosecondsSinceEpoch() -> uint64_t { + return std::chrono::duration_cast( std::chrono::high_resolution_clock::now().time_since_epoch() ).count(); + } + + namespace { + auto estimateClockResolution() -> uint64_t { + uint64_t sum = 0; + static const uint64_t iterations = 1000000; + + auto startTime = getCurrentNanosecondsSinceEpoch(); + + for( std::size_t i = 0; i < iterations; ++i ) { + + uint64_t ticks; + uint64_t baseTicks = getCurrentNanosecondsSinceEpoch(); + do { + ticks = getCurrentNanosecondsSinceEpoch(); + } while( ticks == baseTicks ); + + auto delta = ticks - baseTicks; + sum += delta; + + // If we have been calibrating for over 3 seconds -- the clock + // is terrible and we should move on. + // TBD: How to signal that the measured resolution is probably wrong? + if (ticks > startTime + 3 * nanosecondsInSecond) { + return sum / ( i + 1u ); + } + } + + // We're just taking the mean, here. To do better we could take the std. dev and exclude outliers + // - and potentially do more iterations if there's a high variance. + return sum/iterations; + } + } + auto getEstimatedClockResolution() -> uint64_t { + static auto s_resolution = estimateClockResolution(); + return s_resolution; + } + + void Timer::start() { + m_nanoseconds = getCurrentNanosecondsSinceEpoch(); + } + auto Timer::getElapsedNanoseconds() const -> uint64_t { + return getCurrentNanosecondsSinceEpoch() - m_nanoseconds; + } + auto Timer::getElapsedMicroseconds() const -> uint64_t { + return getElapsedNanoseconds()/1000; + } + auto Timer::getElapsedMilliseconds() const -> unsigned int { + return static_cast(getElapsedMicroseconds()/1000); + } + auto Timer::getElapsedSeconds() const -> double { + return getElapsedMicroseconds()/1000000.0; + } + +} // namespace Catch +// end catch_timer.cpp +// start catch_tostring.cpp + +#if defined(__clang__) +# pragma clang diagnostic push +# pragma clang diagnostic ignored "-Wexit-time-destructors" +# pragma clang diagnostic ignored "-Wglobal-constructors" +#endif + +// Enable specific decls locally +#if !defined(CATCH_CONFIG_ENABLE_CHRONO_STRINGMAKER) +#define CATCH_CONFIG_ENABLE_CHRONO_STRINGMAKER +#endif + +#include +#include + +namespace Catch { + +namespace Detail { + + const std::string unprintableString = "{?}"; + + namespace { + const int hexThreshold = 255; + + struct Endianness { + enum Arch { Big, Little }; + + static Arch which() { + union _{ + int asInt; + char asChar[sizeof (int)]; + } u; + + u.asInt = 1; + return ( u.asChar[sizeof(int)-1] == 1 ) ? Big : Little; + } + }; + } + + std::string rawMemoryToString( const void *object, std::size_t size ) { + // Reverse order for little endian architectures + int i = 0, end = static_cast( size ), inc = 1; + if( Endianness::which() == Endianness::Little ) { + i = end-1; + end = inc = -1; + } + + unsigned char const *bytes = static_cast(object); + ReusableStringStream rss; + rss << "0x" << std::setfill('0') << std::hex; + for( ; i != end; i += inc ) + rss << std::setw(2) << static_cast(bytes[i]); + return rss.str(); + } +} + +template +std::string fpToString( T value, int precision ) { + if (Catch::isnan(value)) { + return "nan"; + } + + ReusableStringStream rss; + rss << std::setprecision( precision ) + << std::fixed + << value; + std::string d = rss.str(); + std::size_t i = d.find_last_not_of( '0' ); + if( i != std::string::npos && i != d.size()-1 ) { + if( d[i] == '.' ) + i++; + d = d.substr( 0, i+1 ); + } + return d; +} + +//// ======================================================= //// +// +// Out-of-line defs for full specialization of StringMaker +// +//// ======================================================= //// + +std::string StringMaker::convert(const std::string& str) { + if (!getCurrentContext().getConfig()->showInvisibles()) { + return '"' + str + '"'; + } + + std::string s("\""); + for (char c : str) { + switch (c) { + case '\n': + s.append("\\n"); + break; + case '\t': + s.append("\\t"); + break; + default: + s.push_back(c); + break; + } + } + s.append("\""); + return s; +} + +#ifdef CATCH_CONFIG_CPP17_STRING_VIEW +std::string StringMaker::convert(std::string_view str) { + return ::Catch::Detail::stringify(std::string{ str }); +} +#endif + +std::string StringMaker::convert(char const* str) { + if (str) { + return ::Catch::Detail::stringify(std::string{ str }); + } else { + return{ "{null string}" }; + } +} +std::string StringMaker::convert(char* str) { + if (str) { + return ::Catch::Detail::stringify(std::string{ str }); + } else { + return{ "{null string}" }; + } +} + +#ifdef CATCH_CONFIG_WCHAR +std::string StringMaker::convert(const std::wstring& wstr) { + std::string s; + s.reserve(wstr.size()); + for (auto c : wstr) { + s += (c <= 0xff) ? static_cast(c) : '?'; + } + return ::Catch::Detail::stringify(s); +} + +# ifdef CATCH_CONFIG_CPP17_STRING_VIEW +std::string StringMaker::convert(std::wstring_view str) { + return StringMaker::convert(std::wstring(str)); +} +# endif + +std::string StringMaker::convert(wchar_t const * str) { + if (str) { + return ::Catch::Detail::stringify(std::wstring{ str }); + } else { + return{ "{null string}" }; + } +} +std::string StringMaker::convert(wchar_t * str) { + if (str) { + return ::Catch::Detail::stringify(std::wstring{ str }); + } else { + return{ "{null string}" }; + } +} +#endif + +std::string StringMaker::convert(int value) { + return ::Catch::Detail::stringify(static_cast(value)); +} +std::string StringMaker::convert(long value) { + return ::Catch::Detail::stringify(static_cast(value)); +} +std::string StringMaker::convert(long long value) { + ReusableStringStream rss; + rss << value; + if (value > Detail::hexThreshold) { + rss << " (0x" << std::hex << value << ')'; + } + return rss.str(); +} + +std::string StringMaker::convert(unsigned int value) { + return ::Catch::Detail::stringify(static_cast(value)); +} +std::string StringMaker::convert(unsigned long value) { + return ::Catch::Detail::stringify(static_cast(value)); +} +std::string StringMaker::convert(unsigned long long value) { + ReusableStringStream rss; + rss << value; + if (value > Detail::hexThreshold) { + rss << " (0x" << std::hex << value << ')'; + } + return rss.str(); +} + +std::string StringMaker::convert(bool b) { + return b ? "true" : "false"; +} + +std::string StringMaker::convert(signed char value) { + if (value == '\r') { + return "'\\r'"; + } else if (value == '\f') { + return "'\\f'"; + } else if (value == '\n') { + return "'\\n'"; + } else if (value == '\t') { + return "'\\t'"; + } else if ('\0' <= value && value < ' ') { + return ::Catch::Detail::stringify(static_cast(value)); + } else { + char chstr[] = "' '"; + chstr[1] = value; + return chstr; + } +} +std::string StringMaker::convert(char c) { + return ::Catch::Detail::stringify(static_cast(c)); +} +std::string StringMaker::convert(unsigned char c) { + return ::Catch::Detail::stringify(static_cast(c)); +} + +std::string StringMaker::convert(std::nullptr_t) { + return "nullptr"; +} + +std::string StringMaker::convert(float value) { + return fpToString(value, 5) + 'f'; +} +std::string StringMaker::convert(double value) { + return fpToString(value, 10); +} + +std::string ratio_string::symbol() { return "a"; } +std::string ratio_string::symbol() { return "f"; } +std::string ratio_string::symbol() { return "p"; } +std::string ratio_string::symbol() { return "n"; } +std::string ratio_string::symbol() { return "u"; } +std::string ratio_string::symbol() { return "m"; } + +} // end namespace Catch + +#if defined(__clang__) +# pragma clang diagnostic pop +#endif + +// end catch_tostring.cpp +// start catch_totals.cpp + +namespace Catch { + + Counts Counts::operator - ( Counts const& other ) const { + Counts diff; + diff.passed = passed - other.passed; + diff.failed = failed - other.failed; + diff.failedButOk = failedButOk - other.failedButOk; + return diff; + } + + Counts& Counts::operator += ( Counts const& other ) { + passed += other.passed; + failed += other.failed; + failedButOk += other.failedButOk; + return *this; + } + + std::size_t Counts::total() const { + return passed + failed + failedButOk; + } + bool Counts::allPassed() const { + return failed == 0 && failedButOk == 0; + } + bool Counts::allOk() const { + return failed == 0; + } + + Totals Totals::operator - ( Totals const& other ) const { + Totals diff; + diff.assertions = assertions - other.assertions; + diff.testCases = testCases - other.testCases; + return diff; + } + + Totals& Totals::operator += ( Totals const& other ) { + assertions += other.assertions; + testCases += other.testCases; + return *this; + } + + Totals Totals::delta( Totals const& prevTotals ) const { + Totals diff = *this - prevTotals; + if( diff.assertions.failed > 0 ) + ++diff.testCases.failed; + else if( diff.assertions.failedButOk > 0 ) + ++diff.testCases.failedButOk; + else + ++diff.testCases.passed; + return diff; + } + +} +// end catch_totals.cpp +// start catch_uncaught_exceptions.cpp + +#include + +namespace Catch { + bool uncaught_exceptions() { +#if defined(CATCH_CONFIG_CPP17_UNCAUGHT_EXCEPTIONS) + return std::uncaught_exceptions() > 0; +#else + return std::uncaught_exception(); +#endif + } +} // end namespace Catch +// end catch_uncaught_exceptions.cpp +// start catch_version.cpp + +#include + +namespace Catch { + + Version::Version + ( unsigned int _majorVersion, + unsigned int _minorVersion, + unsigned int _patchNumber, + char const * const _branchName, + unsigned int _buildNumber ) + : majorVersion( _majorVersion ), + minorVersion( _minorVersion ), + patchNumber( _patchNumber ), + branchName( _branchName ), + buildNumber( _buildNumber ) + {} + + std::ostream& operator << ( std::ostream& os, Version const& version ) { + os << version.majorVersion << '.' + << version.minorVersion << '.' + << version.patchNumber; + // branchName is never null -> 0th char is \0 if it is empty + if (version.branchName[0]) { + os << '-' << version.branchName + << '.' << version.buildNumber; + } + return os; + } + + Version const& libraryVersion() { + static Version version( 2, 7, 0, "", 0 ); + return version; + } + +} +// end catch_version.cpp +// start catch_wildcard_pattern.cpp + +#include + +namespace Catch { + + WildcardPattern::WildcardPattern( std::string const& pattern, + CaseSensitive::Choice caseSensitivity ) + : m_caseSensitivity( caseSensitivity ), + m_pattern( adjustCase( pattern ) ) + { + if( startsWith( m_pattern, '*' ) ) { + m_pattern = m_pattern.substr( 1 ); + m_wildcard = WildcardAtStart; + } + if( endsWith( m_pattern, '*' ) ) { + m_pattern = m_pattern.substr( 0, m_pattern.size()-1 ); + m_wildcard = static_cast( m_wildcard | WildcardAtEnd ); + } + } + + bool WildcardPattern::matches( std::string const& str ) const { + switch( m_wildcard ) { + case NoWildcard: + return m_pattern == adjustCase( str ); + case WildcardAtStart: + return endsWith( adjustCase( str ), m_pattern ); + case WildcardAtEnd: + return startsWith( adjustCase( str ), m_pattern ); + case WildcardAtBothEnds: + return contains( adjustCase( str ), m_pattern ); + default: + CATCH_INTERNAL_ERROR( "Unknown enum" ); + } + } + + std::string WildcardPattern::adjustCase( std::string const& str ) const { + return m_caseSensitivity == CaseSensitive::No ? toLower( str ) : str; + } +} +// end catch_wildcard_pattern.cpp +// start catch_xmlwriter.cpp + +#include + +using uchar = unsigned char; + +namespace Catch { + +namespace { + + size_t trailingBytes(unsigned char c) { + if ((c & 0xE0) == 0xC0) { + return 2; + } + if ((c & 0xF0) == 0xE0) { + return 3; + } + if ((c & 0xF8) == 0xF0) { + return 4; + } + CATCH_INTERNAL_ERROR("Invalid multibyte utf-8 start byte encountered"); + } + + uint32_t headerValue(unsigned char c) { + if ((c & 0xE0) == 0xC0) { + return c & 0x1F; + } + if ((c & 0xF0) == 0xE0) { + return c & 0x0F; + } + if ((c & 0xF8) == 0xF0) { + return c & 0x07; + } + CATCH_INTERNAL_ERROR("Invalid multibyte utf-8 start byte encountered"); + } + + void hexEscapeChar(std::ostream& os, unsigned char c) { + std::ios_base::fmtflags f(os.flags()); + os << "\\x" + << std::uppercase << std::hex << std::setfill('0') << std::setw(2) + << static_cast(c); + os.flags(f); + } + +} // anonymous namespace + + XmlEncode::XmlEncode( std::string const& str, ForWhat forWhat ) + : m_str( str ), + m_forWhat( forWhat ) + {} + + void XmlEncode::encodeTo( std::ostream& os ) const { + // Apostrophe escaping not necessary if we always use " to write attributes + // (see: http://www.w3.org/TR/xml/#syntax) + + for( std::size_t idx = 0; idx < m_str.size(); ++ idx ) { + uchar c = m_str[idx]; + switch (c) { + case '<': os << "<"; break; + case '&': os << "&"; break; + + case '>': + // See: http://www.w3.org/TR/xml/#syntax + if (idx > 2 && m_str[idx - 1] == ']' && m_str[idx - 2] == ']') + os << ">"; + else + os << c; + break; + + case '\"': + if (m_forWhat == ForAttributes) + os << """; + else + os << c; + break; + + default: + // Check for control characters and invalid utf-8 + + // Escape control characters in standard ascii + // see http://stackoverflow.com/questions/404107/why-are-control-characters-illegal-in-xml-1-0 + if (c < 0x09 || (c > 0x0D && c < 0x20) || c == 0x7F) { + hexEscapeChar(os, c); + break; + } + + // Plain ASCII: Write it to stream + if (c < 0x7F) { + os << c; + break; + } + + // UTF-8 territory + // Check if the encoding is valid and if it is not, hex escape bytes. + // Important: We do not check the exact decoded values for validity, only the encoding format + // First check that this bytes is a valid lead byte: + // This means that it is not encoded as 1111 1XXX + // Or as 10XX XXXX + if (c < 0xC0 || + c >= 0xF8) { + hexEscapeChar(os, c); + break; + } + + auto encBytes = trailingBytes(c); + // Are there enough bytes left to avoid accessing out-of-bounds memory? + if (idx + encBytes - 1 >= m_str.size()) { + hexEscapeChar(os, c); + break; + } + // The header is valid, check data + // The next encBytes bytes must together be a valid utf-8 + // This means: bitpattern 10XX XXXX and the extracted value is sane (ish) + bool valid = true; + uint32_t value = headerValue(c); + for (std::size_t n = 1; n < encBytes; ++n) { + uchar nc = m_str[idx + n]; + valid &= ((nc & 0xC0) == 0x80); + value = (value << 6) | (nc & 0x3F); + } + + if ( + // Wrong bit pattern of following bytes + (!valid) || + // Overlong encodings + (value < 0x80) || + (0x80 <= value && value < 0x800 && encBytes > 2) || + (0x800 < value && value < 0x10000 && encBytes > 3) || + // Encoded value out of range + (value >= 0x110000) + ) { + hexEscapeChar(os, c); + break; + } + + // If we got here, this is in fact a valid(ish) utf-8 sequence + for (std::size_t n = 0; n < encBytes; ++n) { + os << m_str[idx + n]; + } + idx += encBytes - 1; + break; + } + } + } + + std::ostream& operator << ( std::ostream& os, XmlEncode const& xmlEncode ) { + xmlEncode.encodeTo( os ); + return os; + } + + XmlWriter::ScopedElement::ScopedElement( XmlWriter* writer ) + : m_writer( writer ) + {} + + XmlWriter::ScopedElement::ScopedElement( ScopedElement&& other ) noexcept + : m_writer( other.m_writer ){ + other.m_writer = nullptr; + } + XmlWriter::ScopedElement& XmlWriter::ScopedElement::operator=( ScopedElement&& other ) noexcept { + if ( m_writer ) { + m_writer->endElement(); + } + m_writer = other.m_writer; + other.m_writer = nullptr; + return *this; + } + + XmlWriter::ScopedElement::~ScopedElement() { + if( m_writer ) + m_writer->endElement(); + } + + XmlWriter::ScopedElement& XmlWriter::ScopedElement::writeText( std::string const& text, bool indent ) { + m_writer->writeText( text, indent ); + return *this; + } + + XmlWriter::XmlWriter( std::ostream& os ) : m_os( os ) + { + writeDeclaration(); + } + + XmlWriter::~XmlWriter() { + while( !m_tags.empty() ) + endElement(); + } + + XmlWriter& XmlWriter::startElement( std::string const& name ) { + ensureTagClosed(); + newlineIfNecessary(); + m_os << m_indent << '<' << name; + m_tags.push_back( name ); + m_indent += " "; + m_tagIsOpen = true; + return *this; + } + + XmlWriter::ScopedElement XmlWriter::scopedElement( std::string const& name ) { + ScopedElement scoped( this ); + startElement( name ); + return scoped; + } + + XmlWriter& XmlWriter::endElement() { + newlineIfNecessary(); + m_indent = m_indent.substr( 0, m_indent.size()-2 ); + if( m_tagIsOpen ) { + m_os << "/>"; + m_tagIsOpen = false; + } + else { + m_os << m_indent << ""; + } + m_os << std::endl; + m_tags.pop_back(); + return *this; + } + + XmlWriter& XmlWriter::writeAttribute( std::string const& name, std::string const& attribute ) { + if( !name.empty() && !attribute.empty() ) + m_os << ' ' << name << "=\"" << XmlEncode( attribute, XmlEncode::ForAttributes ) << '"'; + return *this; + } + + XmlWriter& XmlWriter::writeAttribute( std::string const& name, bool attribute ) { + m_os << ' ' << name << "=\"" << ( attribute ? "true" : "false" ) << '"'; + return *this; + } + + XmlWriter& XmlWriter::writeText( std::string const& text, bool indent ) { + if( !text.empty() ){ + bool tagWasOpen = m_tagIsOpen; + ensureTagClosed(); + if( tagWasOpen && indent ) + m_os << m_indent; + m_os << XmlEncode( text ); + m_needsNewline = true; + } + return *this; + } + + XmlWriter& XmlWriter::writeComment( std::string const& text ) { + ensureTagClosed(); + m_os << m_indent << ""; + m_needsNewline = true; + return *this; + } + + void XmlWriter::writeStylesheetRef( std::string const& url ) { + m_os << "\n"; + } + + XmlWriter& XmlWriter::writeBlankLine() { + ensureTagClosed(); + m_os << '\n'; + return *this; + } + + void XmlWriter::ensureTagClosed() { + if( m_tagIsOpen ) { + m_os << ">" << std::endl; + m_tagIsOpen = false; + } + } + + void XmlWriter::writeDeclaration() { + m_os << "\n"; + } + + void XmlWriter::newlineIfNecessary() { + if( m_needsNewline ) { + m_os << std::endl; + m_needsNewline = false; + } + } +} +// end catch_xmlwriter.cpp +// start catch_reporter_bases.cpp + +#include +#include +#include +#include +#include + +namespace Catch { + void prepareExpandedExpression(AssertionResult& result) { + result.getExpandedExpression(); + } + + // Because formatting using c++ streams is stateful, drop down to C is required + // Alternatively we could use stringstream, but its performance is... not good. + std::string getFormattedDuration( double duration ) { + // Max exponent + 1 is required to represent the whole part + // + 1 for decimal point + // + 3 for the 3 decimal places + // + 1 for null terminator + const std::size_t maxDoubleSize = DBL_MAX_10_EXP + 1 + 1 + 3 + 1; + char buffer[maxDoubleSize]; + + // Save previous errno, to prevent sprintf from overwriting it + ErrnoGuard guard; +#ifdef _MSC_VER + sprintf_s(buffer, "%.3f", duration); +#else + std::sprintf(buffer, "%.3f", duration); +#endif + return std::string(buffer); + } + + TestEventListenerBase::TestEventListenerBase(ReporterConfig const & _config) + :StreamingReporterBase(_config) {} + + std::set TestEventListenerBase::getSupportedVerbosities() { + return { Verbosity::Quiet, Verbosity::Normal, Verbosity::High }; + } + + void TestEventListenerBase::assertionStarting(AssertionInfo const &) {} + + bool TestEventListenerBase::assertionEnded(AssertionStats const &) { + return false; + } + +} // end namespace Catch +// end catch_reporter_bases.cpp +// start catch_reporter_compact.cpp + +namespace { + +#ifdef CATCH_PLATFORM_MAC + const char* failedString() { return "FAILED"; } + const char* passedString() { return "PASSED"; } +#else + const char* failedString() { return "failed"; } + const char* passedString() { return "passed"; } +#endif + + // Colour::LightGrey + Catch::Colour::Code dimColour() { return Catch::Colour::FileName; } + + std::string bothOrAll( std::size_t count ) { + return count == 1 ? std::string() : + count == 2 ? "both " : "all " ; + } + +} // anon namespace + +namespace Catch { +namespace { +// Colour, message variants: +// - white: No tests ran. +// - red: Failed [both/all] N test cases, failed [both/all] M assertions. +// - white: Passed [both/all] N test cases (no assertions). +// - red: Failed N tests cases, failed M assertions. +// - green: Passed [both/all] N tests cases with M assertions. +void printTotals(std::ostream& out, const Totals& totals) { + if (totals.testCases.total() == 0) { + out << "No tests ran."; + } else if (totals.testCases.failed == totals.testCases.total()) { + Colour colour(Colour::ResultError); + const std::string qualify_assertions_failed = + totals.assertions.failed == totals.assertions.total() ? + bothOrAll(totals.assertions.failed) : std::string(); + out << + "Failed " << bothOrAll(totals.testCases.failed) + << pluralise(totals.testCases.failed, "test case") << ", " + "failed " << qualify_assertions_failed << + pluralise(totals.assertions.failed, "assertion") << '.'; + } else if (totals.assertions.total() == 0) { + out << + "Passed " << bothOrAll(totals.testCases.total()) + << pluralise(totals.testCases.total(), "test case") + << " (no assertions)."; + } else if (totals.assertions.failed) { + Colour colour(Colour::ResultError); + out << + "Failed " << pluralise(totals.testCases.failed, "test case") << ", " + "failed " << pluralise(totals.assertions.failed, "assertion") << '.'; + } else { + Colour colour(Colour::ResultSuccess); + out << + "Passed " << bothOrAll(totals.testCases.passed) + << pluralise(totals.testCases.passed, "test case") << + " with " << pluralise(totals.assertions.passed, "assertion") << '.'; + } +} + +// Implementation of CompactReporter formatting +class AssertionPrinter { +public: + AssertionPrinter& operator= (AssertionPrinter const&) = delete; + AssertionPrinter(AssertionPrinter const&) = delete; + AssertionPrinter(std::ostream& _stream, AssertionStats const& _stats, bool _printInfoMessages) + : stream(_stream) + , result(_stats.assertionResult) + , messages(_stats.infoMessages) + , itMessage(_stats.infoMessages.begin()) + , printInfoMessages(_printInfoMessages) {} + + void print() { + printSourceInfo(); + + itMessage = messages.begin(); + + switch (result.getResultType()) { + case ResultWas::Ok: + printResultType(Colour::ResultSuccess, passedString()); + printOriginalExpression(); + printReconstructedExpression(); + if (!result.hasExpression()) + printRemainingMessages(Colour::None); + else + printRemainingMessages(); + break; + case ResultWas::ExpressionFailed: + if (result.isOk()) + printResultType(Colour::ResultSuccess, failedString() + std::string(" - but was ok")); + else + printResultType(Colour::Error, failedString()); + printOriginalExpression(); + printReconstructedExpression(); + printRemainingMessages(); + break; + case ResultWas::ThrewException: + printResultType(Colour::Error, failedString()); + printIssue("unexpected exception with message:"); + printMessage(); + printExpressionWas(); + printRemainingMessages(); + break; + case ResultWas::FatalErrorCondition: + printResultType(Colour::Error, failedString()); + printIssue("fatal error condition with message:"); + printMessage(); + printExpressionWas(); + printRemainingMessages(); + break; + case ResultWas::DidntThrowException: + printResultType(Colour::Error, failedString()); + printIssue("expected exception, got none"); + printExpressionWas(); + printRemainingMessages(); + break; + case ResultWas::Info: + printResultType(Colour::None, "info"); + printMessage(); + printRemainingMessages(); + break; + case ResultWas::Warning: + printResultType(Colour::None, "warning"); + printMessage(); + printRemainingMessages(); + break; + case ResultWas::ExplicitFailure: + printResultType(Colour::Error, failedString()); + printIssue("explicitly"); + printRemainingMessages(Colour::None); + break; + // These cases are here to prevent compiler warnings + case ResultWas::Unknown: + case ResultWas::FailureBit: + case ResultWas::Exception: + printResultType(Colour::Error, "** internal error **"); + break; + } + } + +private: + void printSourceInfo() const { + Colour colourGuard(Colour::FileName); + stream << result.getSourceInfo() << ':'; + } + + void printResultType(Colour::Code colour, std::string const& passOrFail) const { + if (!passOrFail.empty()) { + { + Colour colourGuard(colour); + stream << ' ' << passOrFail; + } + stream << ':'; + } + } + + void printIssue(std::string const& issue) const { + stream << ' ' << issue; + } + + void printExpressionWas() { + if (result.hasExpression()) { + stream << ';'; + { + Colour colour(dimColour()); + stream << " expression was:"; + } + printOriginalExpression(); + } + } + + void printOriginalExpression() const { + if (result.hasExpression()) { + stream << ' ' << result.getExpression(); + } + } + + void printReconstructedExpression() const { + if (result.hasExpandedExpression()) { + { + Colour colour(dimColour()); + stream << " for: "; + } + stream << result.getExpandedExpression(); + } + } + + void printMessage() { + if (itMessage != messages.end()) { + stream << " '" << itMessage->message << '\''; + ++itMessage; + } + } + + void printRemainingMessages(Colour::Code colour = dimColour()) { + if (itMessage == messages.end()) + return; + + // using messages.end() directly yields (or auto) compilation error: + std::vector::const_iterator itEnd = messages.end(); + const std::size_t N = static_cast(std::distance(itMessage, itEnd)); + + { + Colour colourGuard(colour); + stream << " with " << pluralise(N, "message") << ':'; + } + + for (; itMessage != itEnd; ) { + // If this assertion is a warning ignore any INFO messages + if (printInfoMessages || itMessage->type != ResultWas::Info) { + stream << " '" << itMessage->message << '\''; + if (++itMessage != itEnd) { + Colour colourGuard(dimColour()); + stream << " and"; + } + } + } + } + +private: + std::ostream& stream; + AssertionResult const& result; + std::vector messages; + std::vector::const_iterator itMessage; + bool printInfoMessages; +}; + +} // anon namespace + + std::string CompactReporter::getDescription() { + return "Reports test results on a single line, suitable for IDEs"; + } + + ReporterPreferences CompactReporter::getPreferences() const { + return m_reporterPrefs; + } + + void CompactReporter::noMatchingTestCases( std::string const& spec ) { + stream << "No test cases matched '" << spec << '\'' << std::endl; + } + + void CompactReporter::assertionStarting( AssertionInfo const& ) {} + + bool CompactReporter::assertionEnded( AssertionStats const& _assertionStats ) { + AssertionResult const& result = _assertionStats.assertionResult; + + bool printInfoMessages = true; + + // Drop out if result was successful and we're not printing those + if( !m_config->includeSuccessfulResults() && result.isOk() ) { + if( result.getResultType() != ResultWas::Warning ) + return false; + printInfoMessages = false; + } + + AssertionPrinter printer( stream, _assertionStats, printInfoMessages ); + printer.print(); + + stream << std::endl; + return true; + } + + void CompactReporter::sectionEnded(SectionStats const& _sectionStats) { + if (m_config->showDurations() == ShowDurations::Always) { + stream << getFormattedDuration(_sectionStats.durationInSeconds) << " s: " << _sectionStats.sectionInfo.name << std::endl; + } + } + + void CompactReporter::testRunEnded( TestRunStats const& _testRunStats ) { + printTotals( stream, _testRunStats.totals ); + stream << '\n' << std::endl; + StreamingReporterBase::testRunEnded( _testRunStats ); + } + + CompactReporter::~CompactReporter() {} + + CATCH_REGISTER_REPORTER( "compact", CompactReporter ) + +} // end namespace Catch +// end catch_reporter_compact.cpp +// start catch_reporter_console.cpp + +#include +#include + +#if defined(_MSC_VER) +#pragma warning(push) +#pragma warning(disable:4061) // Not all labels are EXPLICITLY handled in switch + // Note that 4062 (not all labels are handled + // and default is missing) is enabled +#endif + +namespace Catch { + +namespace { + +// Formatter impl for ConsoleReporter +class ConsoleAssertionPrinter { +public: + ConsoleAssertionPrinter& operator= (ConsoleAssertionPrinter const&) = delete; + ConsoleAssertionPrinter(ConsoleAssertionPrinter const&) = delete; + ConsoleAssertionPrinter(std::ostream& _stream, AssertionStats const& _stats, bool _printInfoMessages) + : stream(_stream), + stats(_stats), + result(_stats.assertionResult), + colour(Colour::None), + message(result.getMessage()), + messages(_stats.infoMessages), + printInfoMessages(_printInfoMessages) { + switch (result.getResultType()) { + case ResultWas::Ok: + colour = Colour::Success; + passOrFail = "PASSED"; + //if( result.hasMessage() ) + if (_stats.infoMessages.size() == 1) + messageLabel = "with message"; + if (_stats.infoMessages.size() > 1) + messageLabel = "with messages"; + break; + case ResultWas::ExpressionFailed: + if (result.isOk()) { + colour = Colour::Success; + passOrFail = "FAILED - but was ok"; + } else { + colour = Colour::Error; + passOrFail = "FAILED"; + } + if (_stats.infoMessages.size() == 1) + messageLabel = "with message"; + if (_stats.infoMessages.size() > 1) + messageLabel = "with messages"; + break; + case ResultWas::ThrewException: + colour = Colour::Error; + passOrFail = "FAILED"; + messageLabel = "due to unexpected exception with "; + if (_stats.infoMessages.size() == 1) + messageLabel += "message"; + if (_stats.infoMessages.size() > 1) + messageLabel += "messages"; + break; + case ResultWas::FatalErrorCondition: + colour = Colour::Error; + passOrFail = "FAILED"; + messageLabel = "due to a fatal error condition"; + break; + case ResultWas::DidntThrowException: + colour = Colour::Error; + passOrFail = "FAILED"; + messageLabel = "because no exception was thrown where one was expected"; + break; + case ResultWas::Info: + messageLabel = "info"; + break; + case ResultWas::Warning: + messageLabel = "warning"; + break; + case ResultWas::ExplicitFailure: + passOrFail = "FAILED"; + colour = Colour::Error; + if (_stats.infoMessages.size() == 1) + messageLabel = "explicitly with message"; + if (_stats.infoMessages.size() > 1) + messageLabel = "explicitly with messages"; + break; + // These cases are here to prevent compiler warnings + case ResultWas::Unknown: + case ResultWas::FailureBit: + case ResultWas::Exception: + passOrFail = "** internal error **"; + colour = Colour::Error; + break; + } + } + + void print() const { + printSourceInfo(); + if (stats.totals.assertions.total() > 0) { + printResultType(); + printOriginalExpression(); + printReconstructedExpression(); + } else { + stream << '\n'; + } + printMessage(); + } + +private: + void printResultType() const { + if (!passOrFail.empty()) { + Colour colourGuard(colour); + stream << passOrFail << ":\n"; + } + } + void printOriginalExpression() const { + if (result.hasExpression()) { + Colour colourGuard(Colour::OriginalExpression); + stream << " "; + stream << result.getExpressionInMacro(); + stream << '\n'; + } + } + void printReconstructedExpression() const { + if (result.hasExpandedExpression()) { + stream << "with expansion:\n"; + Colour colourGuard(Colour::ReconstructedExpression); + stream << Column(result.getExpandedExpression()).indent(2) << '\n'; + } + } + void printMessage() const { + if (!messageLabel.empty()) + stream << messageLabel << ':' << '\n'; + for (auto const& msg : messages) { + // If this assertion is a warning ignore any INFO messages + if (printInfoMessages || msg.type != ResultWas::Info) + stream << Column(msg.message).indent(2) << '\n'; + } + } + void printSourceInfo() const { + Colour colourGuard(Colour::FileName); + stream << result.getSourceInfo() << ": "; + } + + std::ostream& stream; + AssertionStats const& stats; + AssertionResult const& result; + Colour::Code colour; + std::string passOrFail; + std::string messageLabel; + std::string message; + std::vector messages; + bool printInfoMessages; +}; + +std::size_t makeRatio(std::size_t number, std::size_t total) { + std::size_t ratio = total > 0 ? CATCH_CONFIG_CONSOLE_WIDTH * number / total : 0; + return (ratio == 0 && number > 0) ? 1 : ratio; +} + +std::size_t& findMax(std::size_t& i, std::size_t& j, std::size_t& k) { + if (i > j && i > k) + return i; + else if (j > k) + return j; + else + return k; +} + +struct ColumnInfo { + enum Justification { Left, Right }; + std::string name; + int width; + Justification justification; +}; +struct ColumnBreak {}; +struct RowBreak {}; + +class Duration { + enum class Unit { + Auto, + Nanoseconds, + Microseconds, + Milliseconds, + Seconds, + Minutes + }; + static const uint64_t s_nanosecondsInAMicrosecond = 1000; + static const uint64_t s_nanosecondsInAMillisecond = 1000 * s_nanosecondsInAMicrosecond; + static const uint64_t s_nanosecondsInASecond = 1000 * s_nanosecondsInAMillisecond; + static const uint64_t s_nanosecondsInAMinute = 60 * s_nanosecondsInASecond; + + uint64_t m_inNanoseconds; + Unit m_units; + +public: + explicit Duration(uint64_t inNanoseconds, Unit units = Unit::Auto) + : m_inNanoseconds(inNanoseconds), + m_units(units) { + if (m_units == Unit::Auto) { + if (m_inNanoseconds < s_nanosecondsInAMicrosecond) + m_units = Unit::Nanoseconds; + else if (m_inNanoseconds < s_nanosecondsInAMillisecond) + m_units = Unit::Microseconds; + else if (m_inNanoseconds < s_nanosecondsInASecond) + m_units = Unit::Milliseconds; + else if (m_inNanoseconds < s_nanosecondsInAMinute) + m_units = Unit::Seconds; + else + m_units = Unit::Minutes; + } + + } + + auto value() const -> double { + switch (m_units) { + case Unit::Microseconds: + return m_inNanoseconds / static_cast(s_nanosecondsInAMicrosecond); + case Unit::Milliseconds: + return m_inNanoseconds / static_cast(s_nanosecondsInAMillisecond); + case Unit::Seconds: + return m_inNanoseconds / static_cast(s_nanosecondsInASecond); + case Unit::Minutes: + return m_inNanoseconds / static_cast(s_nanosecondsInAMinute); + default: + return static_cast(m_inNanoseconds); + } + } + auto unitsAsString() const -> std::string { + switch (m_units) { + case Unit::Nanoseconds: + return "ns"; + case Unit::Microseconds: + return "us"; + case Unit::Milliseconds: + return "ms"; + case Unit::Seconds: + return "s"; + case Unit::Minutes: + return "m"; + default: + return "** internal error **"; + } + + } + friend auto operator << (std::ostream& os, Duration const& duration) -> std::ostream& { + return os << duration.value() << " " << duration.unitsAsString(); + } +}; +} // end anon namespace + +class TablePrinter { + std::ostream& m_os; + std::vector m_columnInfos; + std::ostringstream m_oss; + int m_currentColumn = -1; + bool m_isOpen = false; + +public: + TablePrinter( std::ostream& os, std::vector columnInfos ) + : m_os( os ), + m_columnInfos( std::move( columnInfos ) ) {} + + auto columnInfos() const -> std::vector const& { + return m_columnInfos; + } + + void open() { + if (!m_isOpen) { + m_isOpen = true; + *this << RowBreak(); + for (auto const& info : m_columnInfos) + *this << info.name << ColumnBreak(); + *this << RowBreak(); + m_os << Catch::getLineOfChars<'-'>() << "\n"; + } + } + void close() { + if (m_isOpen) { + *this << RowBreak(); + m_os << std::endl; + m_isOpen = false; + } + } + + template + friend TablePrinter& operator << (TablePrinter& tp, T const& value) { + tp.m_oss << value; + return tp; + } + + friend TablePrinter& operator << (TablePrinter& tp, ColumnBreak) { + auto colStr = tp.m_oss.str(); + // This takes account of utf8 encodings + auto strSize = Catch::StringRef(colStr).numberOfCharacters(); + tp.m_oss.str(""); + tp.open(); + if (tp.m_currentColumn == static_cast(tp.m_columnInfos.size() - 1)) { + tp.m_currentColumn = -1; + tp.m_os << "\n"; + } + tp.m_currentColumn++; + + auto colInfo = tp.m_columnInfos[tp.m_currentColumn]; + auto padding = (strSize + 2 < static_cast(colInfo.width)) + ? std::string(colInfo.width - (strSize + 2), ' ') + : std::string(); + if (colInfo.justification == ColumnInfo::Left) + tp.m_os << colStr << padding << " "; + else + tp.m_os << padding << colStr << " "; + return tp; + } + + friend TablePrinter& operator << (TablePrinter& tp, RowBreak) { + if (tp.m_currentColumn > 0) { + tp.m_os << "\n"; + tp.m_currentColumn = -1; + } + return tp; + } +}; + +ConsoleReporter::ConsoleReporter(ReporterConfig const& config) + : StreamingReporterBase(config), + m_tablePrinter(new TablePrinter(config.stream(), + { + { "benchmark name", CATCH_CONFIG_CONSOLE_WIDTH - 32, ColumnInfo::Left }, + { "iters", 8, ColumnInfo::Right }, + { "elapsed ns", 14, ColumnInfo::Right }, + { "average", 14, ColumnInfo::Right } + })) {} +ConsoleReporter::~ConsoleReporter() = default; + +std::string ConsoleReporter::getDescription() { + return "Reports test results as plain lines of text"; +} + +void ConsoleReporter::noMatchingTestCases(std::string const& spec) { + stream << "No test cases matched '" << spec << '\'' << std::endl; +} + +void ConsoleReporter::assertionStarting(AssertionInfo const&) {} + +bool ConsoleReporter::assertionEnded(AssertionStats const& _assertionStats) { + AssertionResult const& result = _assertionStats.assertionResult; + + bool includeResults = m_config->includeSuccessfulResults() || !result.isOk(); + + // Drop out if result was successful but we're not printing them. + if (!includeResults && result.getResultType() != ResultWas::Warning) + return false; + + lazyPrint(); + + ConsoleAssertionPrinter printer(stream, _assertionStats, includeResults); + printer.print(); + stream << std::endl; + return true; +} + +void ConsoleReporter::sectionStarting(SectionInfo const& _sectionInfo) { + m_headerPrinted = false; + StreamingReporterBase::sectionStarting(_sectionInfo); +} +void ConsoleReporter::sectionEnded(SectionStats const& _sectionStats) { + m_tablePrinter->close(); + if (_sectionStats.missingAssertions) { + lazyPrint(); + Colour colour(Colour::ResultError); + if (m_sectionStack.size() > 1) + stream << "\nNo assertions in section"; + else + stream << "\nNo assertions in test case"; + stream << " '" << _sectionStats.sectionInfo.name << "'\n" << std::endl; + } + if (m_config->showDurations() == ShowDurations::Always) { + stream << getFormattedDuration(_sectionStats.durationInSeconds) << " s: " << _sectionStats.sectionInfo.name << std::endl; + } + if (m_headerPrinted) { + m_headerPrinted = false; + } + StreamingReporterBase::sectionEnded(_sectionStats); +} + +void ConsoleReporter::benchmarkStarting(BenchmarkInfo const& info) { + lazyPrintWithoutClosingBenchmarkTable(); + + auto nameCol = Column( info.name ).width( static_cast( m_tablePrinter->columnInfos()[0].width - 2 ) ); + + bool firstLine = true; + for (auto line : nameCol) { + if (!firstLine) + (*m_tablePrinter) << ColumnBreak() << ColumnBreak() << ColumnBreak(); + else + firstLine = false; + + (*m_tablePrinter) << line << ColumnBreak(); + } +} +void ConsoleReporter::benchmarkEnded(BenchmarkStats const& stats) { + Duration average(stats.elapsedTimeInNanoseconds / stats.iterations); + (*m_tablePrinter) + << stats.iterations << ColumnBreak() + << stats.elapsedTimeInNanoseconds << ColumnBreak() + << average << ColumnBreak(); +} + +void ConsoleReporter::testCaseEnded(TestCaseStats const& _testCaseStats) { + m_tablePrinter->close(); + StreamingReporterBase::testCaseEnded(_testCaseStats); + m_headerPrinted = false; +} +void ConsoleReporter::testGroupEnded(TestGroupStats const& _testGroupStats) { + if (currentGroupInfo.used) { + printSummaryDivider(); + stream << "Summary for group '" << _testGroupStats.groupInfo.name << "':\n"; + printTotals(_testGroupStats.totals); + stream << '\n' << std::endl; + } + StreamingReporterBase::testGroupEnded(_testGroupStats); +} +void ConsoleReporter::testRunEnded(TestRunStats const& _testRunStats) { + printTotalsDivider(_testRunStats.totals); + printTotals(_testRunStats.totals); + stream << std::endl; + StreamingReporterBase::testRunEnded(_testRunStats); +} + +void ConsoleReporter::lazyPrint() { + + m_tablePrinter->close(); + lazyPrintWithoutClosingBenchmarkTable(); +} + +void ConsoleReporter::lazyPrintWithoutClosingBenchmarkTable() { + + if (!currentTestRunInfo.used) + lazyPrintRunInfo(); + if (!currentGroupInfo.used) + lazyPrintGroupInfo(); + + if (!m_headerPrinted) { + printTestCaseAndSectionHeader(); + m_headerPrinted = true; + } +} +void ConsoleReporter::lazyPrintRunInfo() { + stream << '\n' << getLineOfChars<'~'>() << '\n'; + Colour colour(Colour::SecondaryText); + stream << currentTestRunInfo->name + << " is a Catch v" << libraryVersion() << " host application.\n" + << "Run with -? for options\n\n"; + + if (m_config->rngSeed() != 0) + stream << "Randomness seeded to: " << m_config->rngSeed() << "\n\n"; + + currentTestRunInfo.used = true; +} +void ConsoleReporter::lazyPrintGroupInfo() { + if (!currentGroupInfo->name.empty() && currentGroupInfo->groupsCounts > 1) { + printClosedHeader("Group: " + currentGroupInfo->name); + currentGroupInfo.used = true; + } +} +void ConsoleReporter::printTestCaseAndSectionHeader() { + assert(!m_sectionStack.empty()); + printOpenHeader(currentTestCaseInfo->name); + + if (m_sectionStack.size() > 1) { + Colour colourGuard(Colour::Headers); + + auto + it = m_sectionStack.begin() + 1, // Skip first section (test case) + itEnd = m_sectionStack.end(); + for (; it != itEnd; ++it) + printHeaderString(it->name, 2); + } + + SourceLineInfo lineInfo = m_sectionStack.back().lineInfo; + + if (!lineInfo.empty()) { + stream << getLineOfChars<'-'>() << '\n'; + Colour colourGuard(Colour::FileName); + stream << lineInfo << '\n'; + } + stream << getLineOfChars<'.'>() << '\n' << std::endl; +} + +void ConsoleReporter::printClosedHeader(std::string const& _name) { + printOpenHeader(_name); + stream << getLineOfChars<'.'>() << '\n'; +} +void ConsoleReporter::printOpenHeader(std::string const& _name) { + stream << getLineOfChars<'-'>() << '\n'; + { + Colour colourGuard(Colour::Headers); + printHeaderString(_name); + } +} + +// if string has a : in first line will set indent to follow it on +// subsequent lines +void ConsoleReporter::printHeaderString(std::string const& _string, std::size_t indent) { + std::size_t i = _string.find(": "); + if (i != std::string::npos) + i += 2; + else + i = 0; + stream << Column(_string).indent(indent + i).initialIndent(indent) << '\n'; +} + +struct SummaryColumn { + + SummaryColumn( std::string _label, Colour::Code _colour ) + : label( std::move( _label ) ), + colour( _colour ) {} + SummaryColumn addRow( std::size_t count ) { + ReusableStringStream rss; + rss << count; + std::string row = rss.str(); + for (auto& oldRow : rows) { + while (oldRow.size() < row.size()) + oldRow = ' ' + oldRow; + while (oldRow.size() > row.size()) + row = ' ' + row; + } + rows.push_back(row); + return *this; + } + + std::string label; + Colour::Code colour; + std::vector rows; + +}; + +void ConsoleReporter::printTotals( Totals const& totals ) { + if (totals.testCases.total() == 0) { + stream << Colour(Colour::Warning) << "No tests ran\n"; + } else if (totals.assertions.total() > 0 && totals.testCases.allPassed()) { + stream << Colour(Colour::ResultSuccess) << "All tests passed"; + stream << " (" + << pluralise(totals.assertions.passed, "assertion") << " in " + << pluralise(totals.testCases.passed, "test case") << ')' + << '\n'; + } else { + + std::vector columns; + columns.push_back(SummaryColumn("", Colour::None) + .addRow(totals.testCases.total()) + .addRow(totals.assertions.total())); + columns.push_back(SummaryColumn("passed", Colour::Success) + .addRow(totals.testCases.passed) + .addRow(totals.assertions.passed)); + columns.push_back(SummaryColumn("failed", Colour::ResultError) + .addRow(totals.testCases.failed) + .addRow(totals.assertions.failed)); + columns.push_back(SummaryColumn("failed as expected", Colour::ResultExpectedFailure) + .addRow(totals.testCases.failedButOk) + .addRow(totals.assertions.failedButOk)); + + printSummaryRow("test cases", columns, 0); + printSummaryRow("assertions", columns, 1); + } +} +void ConsoleReporter::printSummaryRow(std::string const& label, std::vector const& cols, std::size_t row) { + for (auto col : cols) { + std::string value = col.rows[row]; + if (col.label.empty()) { + stream << label << ": "; + if (value != "0") + stream << value; + else + stream << Colour(Colour::Warning) << "- none -"; + } else if (value != "0") { + stream << Colour(Colour::LightGrey) << " | "; + stream << Colour(col.colour) + << value << ' ' << col.label; + } + } + stream << '\n'; +} + +void ConsoleReporter::printTotalsDivider(Totals const& totals) { + if (totals.testCases.total() > 0) { + std::size_t failedRatio = makeRatio(totals.testCases.failed, totals.testCases.total()); + std::size_t failedButOkRatio = makeRatio(totals.testCases.failedButOk, totals.testCases.total()); + std::size_t passedRatio = makeRatio(totals.testCases.passed, totals.testCases.total()); + while (failedRatio + failedButOkRatio + passedRatio < CATCH_CONFIG_CONSOLE_WIDTH - 1) + findMax(failedRatio, failedButOkRatio, passedRatio)++; + while (failedRatio + failedButOkRatio + passedRatio > CATCH_CONFIG_CONSOLE_WIDTH - 1) + findMax(failedRatio, failedButOkRatio, passedRatio)--; + + stream << Colour(Colour::Error) << std::string(failedRatio, '='); + stream << Colour(Colour::ResultExpectedFailure) << std::string(failedButOkRatio, '='); + if (totals.testCases.allPassed()) + stream << Colour(Colour::ResultSuccess) << std::string(passedRatio, '='); + else + stream << Colour(Colour::Success) << std::string(passedRatio, '='); + } else { + stream << Colour(Colour::Warning) << std::string(CATCH_CONFIG_CONSOLE_WIDTH - 1, '='); + } + stream << '\n'; +} +void ConsoleReporter::printSummaryDivider() { + stream << getLineOfChars<'-'>() << '\n'; +} + +CATCH_REGISTER_REPORTER("console", ConsoleReporter) + +} // end namespace Catch + +#if defined(_MSC_VER) +#pragma warning(pop) +#endif +// end catch_reporter_console.cpp +// start catch_reporter_junit.cpp + +#include +#include +#include +#include + +namespace Catch { + + namespace { + std::string getCurrentTimestamp() { + // Beware, this is not reentrant because of backward compatibility issues + // Also, UTC only, again because of backward compatibility (%z is C++11) + time_t rawtime; + std::time(&rawtime); + auto const timeStampSize = sizeof("2017-01-16T17:06:45Z"); + +#ifdef _MSC_VER + std::tm timeInfo = {}; + gmtime_s(&timeInfo, &rawtime); +#else + std::tm* timeInfo; + timeInfo = std::gmtime(&rawtime); +#endif + + char timeStamp[timeStampSize]; + const char * const fmt = "%Y-%m-%dT%H:%M:%SZ"; + +#ifdef _MSC_VER + std::strftime(timeStamp, timeStampSize, fmt, &timeInfo); +#else + std::strftime(timeStamp, timeStampSize, fmt, timeInfo); +#endif + return std::string(timeStamp); + } + + std::string fileNameTag(const std::vector &tags) { + auto it = std::find_if(begin(tags), + end(tags), + [] (std::string const& tag) {return tag.front() == '#'; }); + if (it != tags.end()) + return it->substr(1); + return std::string(); + } + } // anonymous namespace + + JunitReporter::JunitReporter( ReporterConfig const& _config ) + : CumulativeReporterBase( _config ), + xml( _config.stream() ) + { + m_reporterPrefs.shouldRedirectStdOut = true; + m_reporterPrefs.shouldReportAllAssertions = true; + } + + JunitReporter::~JunitReporter() {} + + std::string JunitReporter::getDescription() { + return "Reports test results in an XML format that looks like Ant's junitreport target"; + } + + void JunitReporter::noMatchingTestCases( std::string const& /*spec*/ ) {} + + void JunitReporter::testRunStarting( TestRunInfo const& runInfo ) { + CumulativeReporterBase::testRunStarting( runInfo ); + xml.startElement( "testsuites" ); + if( m_config->rngSeed() != 0 ) { + xml.startElement( "properties" ); + xml.scopedElement( "property" ) + .writeAttribute( "name", "random-seed" ) + .writeAttribute( "value", m_config->rngSeed() ); + xml.endElement(); + } + } + + void JunitReporter::testGroupStarting( GroupInfo const& groupInfo ) { + suiteTimer.start(); + stdOutForSuite.clear(); + stdErrForSuite.clear(); + unexpectedExceptions = 0; + CumulativeReporterBase::testGroupStarting( groupInfo ); + } + + void JunitReporter::testCaseStarting( TestCaseInfo const& testCaseInfo ) { + m_okToFail = testCaseInfo.okToFail(); + } + + bool JunitReporter::assertionEnded( AssertionStats const& assertionStats ) { + if( assertionStats.assertionResult.getResultType() == ResultWas::ThrewException && !m_okToFail ) + unexpectedExceptions++; + return CumulativeReporterBase::assertionEnded( assertionStats ); + } + + void JunitReporter::testCaseEnded( TestCaseStats const& testCaseStats ) { + stdOutForSuite += testCaseStats.stdOut; + stdErrForSuite += testCaseStats.stdErr; + CumulativeReporterBase::testCaseEnded( testCaseStats ); + } + + void JunitReporter::testGroupEnded( TestGroupStats const& testGroupStats ) { + double suiteTime = suiteTimer.getElapsedSeconds(); + CumulativeReporterBase::testGroupEnded( testGroupStats ); + writeGroup( *m_testGroups.back(), suiteTime ); + } + + void JunitReporter::testRunEndedCumulative() { + xml.endElement(); + } + + void JunitReporter::writeGroup( TestGroupNode const& groupNode, double suiteTime ) { + XmlWriter::ScopedElement e = xml.scopedElement( "testsuite" ); + TestGroupStats const& stats = groupNode.value; + xml.writeAttribute( "name", stats.groupInfo.name ); + xml.writeAttribute( "errors", unexpectedExceptions ); + xml.writeAttribute( "failures", stats.totals.assertions.failed-unexpectedExceptions ); + xml.writeAttribute( "tests", stats.totals.assertions.total() ); + xml.writeAttribute( "hostname", "tbd" ); // !TBD + if( m_config->showDurations() == ShowDurations::Never ) + xml.writeAttribute( "time", "" ); + else + xml.writeAttribute( "time", suiteTime ); + xml.writeAttribute( "timestamp", getCurrentTimestamp() ); + + // Write test cases + for( auto const& child : groupNode.children ) + writeTestCase( *child ); + + xml.scopedElement( "system-out" ).writeText( trim( stdOutForSuite ), false ); + xml.scopedElement( "system-err" ).writeText( trim( stdErrForSuite ), false ); + } + + void JunitReporter::writeTestCase( TestCaseNode const& testCaseNode ) { + TestCaseStats const& stats = testCaseNode.value; + + // All test cases have exactly one section - which represents the + // test case itself. That section may have 0-n nested sections + assert( testCaseNode.children.size() == 1 ); + SectionNode const& rootSection = *testCaseNode.children.front(); + + std::string className = stats.testInfo.className; + + if( className.empty() ) { + className = fileNameTag(stats.testInfo.tags); + if ( className.empty() ) + className = "global"; + } + + if ( !m_config->name().empty() ) + className = m_config->name() + "." + className; + + writeSection( className, "", rootSection ); + } + + void JunitReporter::writeSection( std::string const& className, + std::string const& rootName, + SectionNode const& sectionNode ) { + std::string name = trim( sectionNode.stats.sectionInfo.name ); + if( !rootName.empty() ) + name = rootName + '/' + name; + + if( !sectionNode.assertions.empty() || + !sectionNode.stdOut.empty() || + !sectionNode.stdErr.empty() ) { + XmlWriter::ScopedElement e = xml.scopedElement( "testcase" ); + if( className.empty() ) { + xml.writeAttribute( "classname", name ); + xml.writeAttribute( "name", "root" ); + } + else { + xml.writeAttribute( "classname", className ); + xml.writeAttribute( "name", name ); + } + xml.writeAttribute( "time", ::Catch::Detail::stringify( sectionNode.stats.durationInSeconds ) ); + + writeAssertions( sectionNode ); + + if( !sectionNode.stdOut.empty() ) + xml.scopedElement( "system-out" ).writeText( trim( sectionNode.stdOut ), false ); + if( !sectionNode.stdErr.empty() ) + xml.scopedElement( "system-err" ).writeText( trim( sectionNode.stdErr ), false ); + } + for( auto const& childNode : sectionNode.childSections ) + if( className.empty() ) + writeSection( name, "", *childNode ); + else + writeSection( className, name, *childNode ); + } + + void JunitReporter::writeAssertions( SectionNode const& sectionNode ) { + for( auto const& assertion : sectionNode.assertions ) + writeAssertion( assertion ); + } + + void JunitReporter::writeAssertion( AssertionStats const& stats ) { + AssertionResult const& result = stats.assertionResult; + if( !result.isOk() ) { + std::string elementName; + switch( result.getResultType() ) { + case ResultWas::ThrewException: + case ResultWas::FatalErrorCondition: + elementName = "error"; + break; + case ResultWas::ExplicitFailure: + elementName = "failure"; + break; + case ResultWas::ExpressionFailed: + elementName = "failure"; + break; + case ResultWas::DidntThrowException: + elementName = "failure"; + break; + + // We should never see these here: + case ResultWas::Info: + case ResultWas::Warning: + case ResultWas::Ok: + case ResultWas::Unknown: + case ResultWas::FailureBit: + case ResultWas::Exception: + elementName = "internalError"; + break; + } + + XmlWriter::ScopedElement e = xml.scopedElement( elementName ); + + xml.writeAttribute( "message", result.getExpandedExpression() ); + xml.writeAttribute( "type", result.getTestMacroName() ); + + ReusableStringStream rss; + if( !result.getMessage().empty() ) + rss << result.getMessage() << '\n'; + for( auto const& msg : stats.infoMessages ) + if( msg.type == ResultWas::Info ) + rss << msg.message << '\n'; + + rss << "at " << result.getSourceInfo(); + xml.writeText( rss.str(), false ); + } + } + + CATCH_REGISTER_REPORTER( "junit", JunitReporter ) + +} // end namespace Catch +// end catch_reporter_junit.cpp +// start catch_reporter_listening.cpp + +#include + +namespace Catch { + + ListeningReporter::ListeningReporter() { + // We will assume that listeners will always want all assertions + m_preferences.shouldReportAllAssertions = true; + } + + void ListeningReporter::addListener( IStreamingReporterPtr&& listener ) { + m_listeners.push_back( std::move( listener ) ); + } + + void ListeningReporter::addReporter(IStreamingReporterPtr&& reporter) { + assert(!m_reporter && "Listening reporter can wrap only 1 real reporter"); + m_reporter = std::move( reporter ); + m_preferences.shouldRedirectStdOut = m_reporter->getPreferences().shouldRedirectStdOut; + } + + ReporterPreferences ListeningReporter::getPreferences() const { + return m_preferences; + } + + std::set ListeningReporter::getSupportedVerbosities() { + return std::set{ }; + } + + void ListeningReporter::noMatchingTestCases( std::string const& spec ) { + for ( auto const& listener : m_listeners ) { + listener->noMatchingTestCases( spec ); + } + m_reporter->noMatchingTestCases( spec ); + } + + void ListeningReporter::benchmarkStarting( BenchmarkInfo const& benchmarkInfo ) { + for ( auto const& listener : m_listeners ) { + listener->benchmarkStarting( benchmarkInfo ); + } + m_reporter->benchmarkStarting( benchmarkInfo ); + } + void ListeningReporter::benchmarkEnded( BenchmarkStats const& benchmarkStats ) { + for ( auto const& listener : m_listeners ) { + listener->benchmarkEnded( benchmarkStats ); + } + m_reporter->benchmarkEnded( benchmarkStats ); + } + + void ListeningReporter::testRunStarting( TestRunInfo const& testRunInfo ) { + for ( auto const& listener : m_listeners ) { + listener->testRunStarting( testRunInfo ); + } + m_reporter->testRunStarting( testRunInfo ); + } + + void ListeningReporter::testGroupStarting( GroupInfo const& groupInfo ) { + for ( auto const& listener : m_listeners ) { + listener->testGroupStarting( groupInfo ); + } + m_reporter->testGroupStarting( groupInfo ); + } + + void ListeningReporter::testCaseStarting( TestCaseInfo const& testInfo ) { + for ( auto const& listener : m_listeners ) { + listener->testCaseStarting( testInfo ); + } + m_reporter->testCaseStarting( testInfo ); + } + + void ListeningReporter::sectionStarting( SectionInfo const& sectionInfo ) { + for ( auto const& listener : m_listeners ) { + listener->sectionStarting( sectionInfo ); + } + m_reporter->sectionStarting( sectionInfo ); + } + + void ListeningReporter::assertionStarting( AssertionInfo const& assertionInfo ) { + for ( auto const& listener : m_listeners ) { + listener->assertionStarting( assertionInfo ); + } + m_reporter->assertionStarting( assertionInfo ); + } + + // The return value indicates if the messages buffer should be cleared: + bool ListeningReporter::assertionEnded( AssertionStats const& assertionStats ) { + for( auto const& listener : m_listeners ) { + static_cast( listener->assertionEnded( assertionStats ) ); + } + return m_reporter->assertionEnded( assertionStats ); + } + + void ListeningReporter::sectionEnded( SectionStats const& sectionStats ) { + for ( auto const& listener : m_listeners ) { + listener->sectionEnded( sectionStats ); + } + m_reporter->sectionEnded( sectionStats ); + } + + void ListeningReporter::testCaseEnded( TestCaseStats const& testCaseStats ) { + for ( auto const& listener : m_listeners ) { + listener->testCaseEnded( testCaseStats ); + } + m_reporter->testCaseEnded( testCaseStats ); + } + + void ListeningReporter::testGroupEnded( TestGroupStats const& testGroupStats ) { + for ( auto const& listener : m_listeners ) { + listener->testGroupEnded( testGroupStats ); + } + m_reporter->testGroupEnded( testGroupStats ); + } + + void ListeningReporter::testRunEnded( TestRunStats const& testRunStats ) { + for ( auto const& listener : m_listeners ) { + listener->testRunEnded( testRunStats ); + } + m_reporter->testRunEnded( testRunStats ); + } + + void ListeningReporter::skipTest( TestCaseInfo const& testInfo ) { + for ( auto const& listener : m_listeners ) { + listener->skipTest( testInfo ); + } + m_reporter->skipTest( testInfo ); + } + + bool ListeningReporter::isMulti() const { + return true; + } + +} // end namespace Catch +// end catch_reporter_listening.cpp +// start catch_reporter_xml.cpp + +#if defined(_MSC_VER) +#pragma warning(push) +#pragma warning(disable:4061) // Not all labels are EXPLICITLY handled in switch + // Note that 4062 (not all labels are handled + // and default is missing) is enabled +#endif + +namespace Catch { + XmlReporter::XmlReporter( ReporterConfig const& _config ) + : StreamingReporterBase( _config ), + m_xml(_config.stream()) + { + m_reporterPrefs.shouldRedirectStdOut = true; + m_reporterPrefs.shouldReportAllAssertions = true; + } + + XmlReporter::~XmlReporter() = default; + + std::string XmlReporter::getDescription() { + return "Reports test results as an XML document"; + } + + std::string XmlReporter::getStylesheetRef() const { + return std::string(); + } + + void XmlReporter::writeSourceInfo( SourceLineInfo const& sourceInfo ) { + m_xml + .writeAttribute( "filename", sourceInfo.file ) + .writeAttribute( "line", sourceInfo.line ); + } + + void XmlReporter::noMatchingTestCases( std::string const& s ) { + StreamingReporterBase::noMatchingTestCases( s ); + } + + void XmlReporter::testRunStarting( TestRunInfo const& testInfo ) { + StreamingReporterBase::testRunStarting( testInfo ); + std::string stylesheetRef = getStylesheetRef(); + if( !stylesheetRef.empty() ) + m_xml.writeStylesheetRef( stylesheetRef ); + m_xml.startElement( "Catch" ); + if( !m_config->name().empty() ) + m_xml.writeAttribute( "name", m_config->name() ); + if( m_config->rngSeed() != 0 ) + m_xml.scopedElement( "Randomness" ) + .writeAttribute( "seed", m_config->rngSeed() ); + } + + void XmlReporter::testGroupStarting( GroupInfo const& groupInfo ) { + StreamingReporterBase::testGroupStarting( groupInfo ); + m_xml.startElement( "Group" ) + .writeAttribute( "name", groupInfo.name ); + } + + void XmlReporter::testCaseStarting( TestCaseInfo const& testInfo ) { + StreamingReporterBase::testCaseStarting(testInfo); + m_xml.startElement( "TestCase" ) + .writeAttribute( "name", trim( testInfo.name ) ) + .writeAttribute( "description", testInfo.description ) + .writeAttribute( "tags", testInfo.tagsAsString() ); + + writeSourceInfo( testInfo.lineInfo ); + + if ( m_config->showDurations() == ShowDurations::Always ) + m_testCaseTimer.start(); + m_xml.ensureTagClosed(); + } + + void XmlReporter::sectionStarting( SectionInfo const& sectionInfo ) { + StreamingReporterBase::sectionStarting( sectionInfo ); + if( m_sectionDepth++ > 0 ) { + m_xml.startElement( "Section" ) + .writeAttribute( "name", trim( sectionInfo.name ) ); + writeSourceInfo( sectionInfo.lineInfo ); + m_xml.ensureTagClosed(); + } + } + + void XmlReporter::assertionStarting( AssertionInfo const& ) { } + + bool XmlReporter::assertionEnded( AssertionStats const& assertionStats ) { + + AssertionResult const& result = assertionStats.assertionResult; + + bool includeResults = m_config->includeSuccessfulResults() || !result.isOk(); + + if( includeResults || result.getResultType() == ResultWas::Warning ) { + // Print any info messages in tags. + for( auto const& msg : assertionStats.infoMessages ) { + if( msg.type == ResultWas::Info && includeResults ) { + m_xml.scopedElement( "Info" ) + .writeText( msg.message ); + } else if ( msg.type == ResultWas::Warning ) { + m_xml.scopedElement( "Warning" ) + .writeText( msg.message ); + } + } + } + + // Drop out if result was successful but we're not printing them. + if( !includeResults && result.getResultType() != ResultWas::Warning ) + return true; + + // Print the expression if there is one. + if( result.hasExpression() ) { + m_xml.startElement( "Expression" ) + .writeAttribute( "success", result.succeeded() ) + .writeAttribute( "type", result.getTestMacroName() ); + + writeSourceInfo( result.getSourceInfo() ); + + m_xml.scopedElement( "Original" ) + .writeText( result.getExpression() ); + m_xml.scopedElement( "Expanded" ) + .writeText( result.getExpandedExpression() ); + } + + // And... Print a result applicable to each result type. + switch( result.getResultType() ) { + case ResultWas::ThrewException: + m_xml.startElement( "Exception" ); + writeSourceInfo( result.getSourceInfo() ); + m_xml.writeText( result.getMessage() ); + m_xml.endElement(); + break; + case ResultWas::FatalErrorCondition: + m_xml.startElement( "FatalErrorCondition" ); + writeSourceInfo( result.getSourceInfo() ); + m_xml.writeText( result.getMessage() ); + m_xml.endElement(); + break; + case ResultWas::Info: + m_xml.scopedElement( "Info" ) + .writeText( result.getMessage() ); + break; + case ResultWas::Warning: + // Warning will already have been written + break; + case ResultWas::ExplicitFailure: + m_xml.startElement( "Failure" ); + writeSourceInfo( result.getSourceInfo() ); + m_xml.writeText( result.getMessage() ); + m_xml.endElement(); + break; + default: + break; + } + + if( result.hasExpression() ) + m_xml.endElement(); + + return true; + } + + void XmlReporter::sectionEnded( SectionStats const& sectionStats ) { + StreamingReporterBase::sectionEnded( sectionStats ); + if( --m_sectionDepth > 0 ) { + XmlWriter::ScopedElement e = m_xml.scopedElement( "OverallResults" ); + e.writeAttribute( "successes", sectionStats.assertions.passed ); + e.writeAttribute( "failures", sectionStats.assertions.failed ); + e.writeAttribute( "expectedFailures", sectionStats.assertions.failedButOk ); + + if ( m_config->showDurations() == ShowDurations::Always ) + e.writeAttribute( "durationInSeconds", sectionStats.durationInSeconds ); + + m_xml.endElement(); + } + } + + void XmlReporter::testCaseEnded( TestCaseStats const& testCaseStats ) { + StreamingReporterBase::testCaseEnded( testCaseStats ); + XmlWriter::ScopedElement e = m_xml.scopedElement( "OverallResult" ); + e.writeAttribute( "success", testCaseStats.totals.assertions.allOk() ); + + if ( m_config->showDurations() == ShowDurations::Always ) + e.writeAttribute( "durationInSeconds", m_testCaseTimer.getElapsedSeconds() ); + + if( !testCaseStats.stdOut.empty() ) + m_xml.scopedElement( "StdOut" ).writeText( trim( testCaseStats.stdOut ), false ); + if( !testCaseStats.stdErr.empty() ) + m_xml.scopedElement( "StdErr" ).writeText( trim( testCaseStats.stdErr ), false ); + + m_xml.endElement(); + } + + void XmlReporter::testGroupEnded( TestGroupStats const& testGroupStats ) { + StreamingReporterBase::testGroupEnded( testGroupStats ); + // TODO: Check testGroupStats.aborting and act accordingly. + m_xml.scopedElement( "OverallResults" ) + .writeAttribute( "successes", testGroupStats.totals.assertions.passed ) + .writeAttribute( "failures", testGroupStats.totals.assertions.failed ) + .writeAttribute( "expectedFailures", testGroupStats.totals.assertions.failedButOk ); + m_xml.endElement(); + } + + void XmlReporter::testRunEnded( TestRunStats const& testRunStats ) { + StreamingReporterBase::testRunEnded( testRunStats ); + m_xml.scopedElement( "OverallResults" ) + .writeAttribute( "successes", testRunStats.totals.assertions.passed ) + .writeAttribute( "failures", testRunStats.totals.assertions.failed ) + .writeAttribute( "expectedFailures", testRunStats.totals.assertions.failedButOk ); + m_xml.endElement(); + } + + CATCH_REGISTER_REPORTER( "xml", XmlReporter ) + +} // end namespace Catch + +#if defined(_MSC_VER) +#pragma warning(pop) +#endif +// end catch_reporter_xml.cpp + +namespace Catch { + LeakDetector leakDetector; +} + +#ifdef __clang__ +#pragma clang diagnostic pop +#endif + +// end catch_impl.hpp +#endif + +#ifdef CATCH_CONFIG_MAIN +// start catch_default_main.hpp + +#ifndef __OBJC__ + +#if defined(CATCH_CONFIG_WCHAR) && defined(WIN32) && defined(_UNICODE) && !defined(DO_NOT_USE_WMAIN) +// Standard C/C++ Win32 Unicode wmain entry point +extern "C" int wmain (int argc, wchar_t * argv[], wchar_t * []) { +#else +// Standard C/C++ main entry point +int main (int argc, char * argv[]) { +#endif + + return Catch::Session().run( argc, argv ); +} + +#else // __OBJC__ + +// Objective-C entry point +int main (int argc, char * const argv[]) { +#if !CATCH_ARC_ENABLED + NSAutoreleasePool * pool = [[NSAutoreleasePool alloc] init]; +#endif + + Catch::registerTestMethods(); + int result = Catch::Session().run( argc, (char**)argv ); + +#if !CATCH_ARC_ENABLED + [pool drain]; +#endif + + return result; +} + +#endif // __OBJC__ + +// end catch_default_main.hpp +#endif + +#if !defined(CATCH_CONFIG_IMPL_ONLY) + +#ifdef CLARA_CONFIG_MAIN_NOT_DEFINED +# undef CLARA_CONFIG_MAIN +#endif + +#if !defined(CATCH_CONFIG_DISABLE) +////// +// If this config identifier is defined then all CATCH macros are prefixed with CATCH_ +#ifdef CATCH_CONFIG_PREFIX_ALL + +#define CATCH_REQUIRE( ... ) INTERNAL_CATCH_TEST( "CATCH_REQUIRE", Catch::ResultDisposition::Normal, __VA_ARGS__ ) +#define CATCH_REQUIRE_FALSE( ... ) INTERNAL_CATCH_TEST( "CATCH_REQUIRE_FALSE", Catch::ResultDisposition::Normal | Catch::ResultDisposition::FalseTest, __VA_ARGS__ ) + +#define CATCH_REQUIRE_THROWS( ... ) INTERNAL_CATCH_THROWS( "CATCH_REQUIRE_THROWS", Catch::ResultDisposition::Normal, __VA_ARGS__ ) +#define CATCH_REQUIRE_THROWS_AS( expr, exceptionType ) INTERNAL_CATCH_THROWS_AS( "CATCH_REQUIRE_THROWS_AS", exceptionType, Catch::ResultDisposition::Normal, expr ) +#define CATCH_REQUIRE_THROWS_WITH( expr, matcher ) INTERNAL_CATCH_THROWS_STR_MATCHES( "CATCH_REQUIRE_THROWS_WITH", Catch::ResultDisposition::Normal, matcher, expr ) +#if !defined(CATCH_CONFIG_DISABLE_MATCHERS) +#define CATCH_REQUIRE_THROWS_MATCHES( expr, exceptionType, matcher ) INTERNAL_CATCH_THROWS_MATCHES( "CATCH_REQUIRE_THROWS_MATCHES", exceptionType, Catch::ResultDisposition::Normal, matcher, expr ) +#endif// CATCH_CONFIG_DISABLE_MATCHERS +#define CATCH_REQUIRE_NOTHROW( ... ) INTERNAL_CATCH_NO_THROW( "CATCH_REQUIRE_NOTHROW", Catch::ResultDisposition::Normal, __VA_ARGS__ ) + +#define CATCH_CHECK( ... ) INTERNAL_CATCH_TEST( "CATCH_CHECK", Catch::ResultDisposition::ContinueOnFailure, __VA_ARGS__ ) +#define CATCH_CHECK_FALSE( ... ) INTERNAL_CATCH_TEST( "CATCH_CHECK_FALSE", Catch::ResultDisposition::ContinueOnFailure | Catch::ResultDisposition::FalseTest, __VA_ARGS__ ) +#define CATCH_CHECKED_IF( ... ) INTERNAL_CATCH_IF( "CATCH_CHECKED_IF", Catch::ResultDisposition::ContinueOnFailure, __VA_ARGS__ ) +#define CATCH_CHECKED_ELSE( ... ) INTERNAL_CATCH_ELSE( "CATCH_CHECKED_ELSE", Catch::ResultDisposition::ContinueOnFailure, __VA_ARGS__ ) +#define CATCH_CHECK_NOFAIL( ... ) INTERNAL_CATCH_TEST( "CATCH_CHECK_NOFAIL", Catch::ResultDisposition::ContinueOnFailure | Catch::ResultDisposition::SuppressFail, __VA_ARGS__ ) + +#define CATCH_CHECK_THROWS( ... ) INTERNAL_CATCH_THROWS( "CATCH_CHECK_THROWS", Catch::ResultDisposition::ContinueOnFailure, __VA_ARGS__ ) +#define CATCH_CHECK_THROWS_AS( expr, exceptionType ) INTERNAL_CATCH_THROWS_AS( "CATCH_CHECK_THROWS_AS", exceptionType, Catch::ResultDisposition::ContinueOnFailure, expr ) +#define CATCH_CHECK_THROWS_WITH( expr, matcher ) INTERNAL_CATCH_THROWS_STR_MATCHES( "CATCH_CHECK_THROWS_WITH", Catch::ResultDisposition::ContinueOnFailure, matcher, expr ) +#if !defined(CATCH_CONFIG_DISABLE_MATCHERS) +#define CATCH_CHECK_THROWS_MATCHES( expr, exceptionType, matcher ) INTERNAL_CATCH_THROWS_MATCHES( "CATCH_CHECK_THROWS_MATCHES", exceptionType, Catch::ResultDisposition::ContinueOnFailure, matcher, expr ) +#endif // CATCH_CONFIG_DISABLE_MATCHERS +#define CATCH_CHECK_NOTHROW( ... ) INTERNAL_CATCH_NO_THROW( "CATCH_CHECK_NOTHROW", Catch::ResultDisposition::ContinueOnFailure, __VA_ARGS__ ) + +#if !defined(CATCH_CONFIG_DISABLE_MATCHERS) +#define CATCH_CHECK_THAT( arg, matcher ) INTERNAL_CHECK_THAT( "CATCH_CHECK_THAT", matcher, Catch::ResultDisposition::ContinueOnFailure, arg ) + +#define CATCH_REQUIRE_THAT( arg, matcher ) INTERNAL_CHECK_THAT( "CATCH_REQUIRE_THAT", matcher, Catch::ResultDisposition::Normal, arg ) +#endif // CATCH_CONFIG_DISABLE_MATCHERS + +#define CATCH_INFO( msg ) INTERNAL_CATCH_INFO( "CATCH_INFO", msg ) +#define CATCH_WARN( msg ) INTERNAL_CATCH_MSG( "CATCH_WARN", Catch::ResultWas::Warning, Catch::ResultDisposition::ContinueOnFailure, msg ) +#define CATCH_CAPTURE( ... ) INTERNAL_CATCH_CAPTURE( INTERNAL_CATCH_UNIQUE_NAME(capturer), "CATCH_CAPTURE",__VA_ARGS__ ) + +#define CATCH_TEST_CASE( ... ) INTERNAL_CATCH_TESTCASE( __VA_ARGS__ ) +#define CATCH_TEST_CASE_METHOD( className, ... ) INTERNAL_CATCH_TEST_CASE_METHOD( className, __VA_ARGS__ ) +#define CATCH_METHOD_AS_TEST_CASE( method, ... ) INTERNAL_CATCH_METHOD_AS_TEST_CASE( method, __VA_ARGS__ ) +#define CATCH_REGISTER_TEST_CASE( Function, ... ) INTERNAL_CATCH_REGISTER_TESTCASE( Function, __VA_ARGS__ ) +#define CATCH_SECTION( ... ) INTERNAL_CATCH_SECTION( __VA_ARGS__ ) +#define CATCH_DYNAMIC_SECTION( ... ) INTERNAL_CATCH_DYNAMIC_SECTION( __VA_ARGS__ ) +#define CATCH_FAIL( ... ) INTERNAL_CATCH_MSG( "CATCH_FAIL", Catch::ResultWas::ExplicitFailure, Catch::ResultDisposition::Normal, __VA_ARGS__ ) +#define CATCH_FAIL_CHECK( ... ) INTERNAL_CATCH_MSG( "CATCH_FAIL_CHECK", Catch::ResultWas::ExplicitFailure, Catch::ResultDisposition::ContinueOnFailure, __VA_ARGS__ ) +#define CATCH_SUCCEED( ... ) INTERNAL_CATCH_MSG( "CATCH_SUCCEED", Catch::ResultWas::Ok, Catch::ResultDisposition::ContinueOnFailure, __VA_ARGS__ ) + +#define CATCH_ANON_TEST_CASE() INTERNAL_CATCH_TESTCASE() + +#ifndef CATCH_CONFIG_TRADITIONAL_MSVC_PREPROCESSOR +#define CATCH_TEMPLATE_TEST_CASE( ... ) INTERNAL_CATCH_TEMPLATE_TEST_CASE( __VA_ARGS__ ) +#define CATCH_TEMPLATE_TEST_CASE_METHOD( className, ... ) INTERNAL_CATCH_TEMPLATE_TEST_CASE_METHOD( className, __VA_ARGS__ ) +#define CATCH_TEMPLATE_PRODUCT_TEST_CASE( ... ) INTERNAL_CATCH_TEMPLATE_PRODUCT_TEST_CASE( __VA_ARGS__ ) +#define CATCH_TEMPLATE_PRODUCT_TEST_CASE_METHOD( className, ... ) INTERNAL_CATCH_TEMPLATE_PRODUCT_TEST_CASE_METHOD( className, __VA_ARGS__ ) +#else +#define CATCH_TEMPLATE_TEST_CASE( ... ) INTERNAL_CATCH_EXPAND_VARGS( INTERNAL_CATCH_TEMPLATE_TEST_CASE( __VA_ARGS__ ) ) +#define CATCH_TEMPLATE_TEST_CASE_METHOD( className, ... ) INTERNAL_CATCH_EXPAND_VARGS( INTERNAL_CATCH_TEMPLATE_TEST_CASE_METHOD( className, __VA_ARGS__ ) ) +#define CATCH_TEMPLATE_PRODUCT_TEST_CASE( ... ) INTERNAL_CATCH_EXPAND_VARGS( INTERNAL_CATCH_TEMPLATE_PRODUCT_TEST_CASE( __VA_ARGS__ ) ) +#define CATCH_TEMPLATE_PRODUCT_TEST_CASE_METHOD( className, ... ) INTERNAL_CATCH_EXPAND_VARGS( INTERNAL_CATCH_TEMPLATE_PRODUCT_TEST_CASE_METHOD( className, __VA_ARGS__ ) ) +#endif + +#if !defined(CATCH_CONFIG_RUNTIME_STATIC_REQUIRE) +#define CATCH_STATIC_REQUIRE( ... ) static_assert( __VA_ARGS__ , #__VA_ARGS__ ); CATCH_SUCCEED( #__VA_ARGS__ ) +#define CATCH_STATIC_REQUIRE_FALSE( ... ) static_assert( !(__VA_ARGS__), "!(" #__VA_ARGS__ ")" ); CATCH_SUCCEED( #__VA_ARGS__ ) +#else +#define CATCH_STATIC_REQUIRE( ... ) CATCH_REQUIRE( __VA_ARGS__ ) +#define CATCH_STATIC_REQUIRE_FALSE( ... ) CATCH_REQUIRE_FALSE( __VA_ARGS__ ) +#endif + +// "BDD-style" convenience wrappers +#define CATCH_SCENARIO( ... ) CATCH_TEST_CASE( "Scenario: " __VA_ARGS__ ) +#define CATCH_SCENARIO_METHOD( className, ... ) INTERNAL_CATCH_TEST_CASE_METHOD( className, "Scenario: " __VA_ARGS__ ) +#define CATCH_GIVEN( desc ) INTERNAL_CATCH_DYNAMIC_SECTION( " Given: " << desc ) +#define CATCH_AND_GIVEN( desc ) INTERNAL_CATCH_DYNAMIC_SECTION( "And given: " << desc ) +#define CATCH_WHEN( desc ) INTERNAL_CATCH_DYNAMIC_SECTION( " When: " << desc ) +#define CATCH_AND_WHEN( desc ) INTERNAL_CATCH_DYNAMIC_SECTION( " And when: " << desc ) +#define CATCH_THEN( desc ) INTERNAL_CATCH_DYNAMIC_SECTION( " Then: " << desc ) +#define CATCH_AND_THEN( desc ) INTERNAL_CATCH_DYNAMIC_SECTION( " And: " << desc ) + +// If CATCH_CONFIG_PREFIX_ALL is not defined then the CATCH_ prefix is not required +#else + +#define REQUIRE( ... ) INTERNAL_CATCH_TEST( "REQUIRE", Catch::ResultDisposition::Normal, __VA_ARGS__ ) +#define REQUIRE_FALSE( ... ) INTERNAL_CATCH_TEST( "REQUIRE_FALSE", Catch::ResultDisposition::Normal | Catch::ResultDisposition::FalseTest, __VA_ARGS__ ) + +#define REQUIRE_THROWS( ... ) INTERNAL_CATCH_THROWS( "REQUIRE_THROWS", Catch::ResultDisposition::Normal, __VA_ARGS__ ) +#define REQUIRE_THROWS_AS( expr, exceptionType ) INTERNAL_CATCH_THROWS_AS( "REQUIRE_THROWS_AS", exceptionType, Catch::ResultDisposition::Normal, expr ) +#define REQUIRE_THROWS_WITH( expr, matcher ) INTERNAL_CATCH_THROWS_STR_MATCHES( "REQUIRE_THROWS_WITH", Catch::ResultDisposition::Normal, matcher, expr ) +#if !defined(CATCH_CONFIG_DISABLE_MATCHERS) +#define REQUIRE_THROWS_MATCHES( expr, exceptionType, matcher ) INTERNAL_CATCH_THROWS_MATCHES( "REQUIRE_THROWS_MATCHES", exceptionType, Catch::ResultDisposition::Normal, matcher, expr ) +#endif // CATCH_CONFIG_DISABLE_MATCHERS +#define REQUIRE_NOTHROW( ... ) INTERNAL_CATCH_NO_THROW( "REQUIRE_NOTHROW", Catch::ResultDisposition::Normal, __VA_ARGS__ ) + +#define CHECK( ... ) INTERNAL_CATCH_TEST( "CHECK", Catch::ResultDisposition::ContinueOnFailure, __VA_ARGS__ ) +#define CHECK_FALSE( ... ) INTERNAL_CATCH_TEST( "CHECK_FALSE", Catch::ResultDisposition::ContinueOnFailure | Catch::ResultDisposition::FalseTest, __VA_ARGS__ ) +#define CHECKED_IF( ... ) INTERNAL_CATCH_IF( "CHECKED_IF", Catch::ResultDisposition::ContinueOnFailure, __VA_ARGS__ ) +#define CHECKED_ELSE( ... ) INTERNAL_CATCH_ELSE( "CHECKED_ELSE", Catch::ResultDisposition::ContinueOnFailure, __VA_ARGS__ ) +#define CHECK_NOFAIL( ... ) INTERNAL_CATCH_TEST( "CHECK_NOFAIL", Catch::ResultDisposition::ContinueOnFailure | Catch::ResultDisposition::SuppressFail, __VA_ARGS__ ) + +#define CHECK_THROWS( ... ) INTERNAL_CATCH_THROWS( "CHECK_THROWS", Catch::ResultDisposition::ContinueOnFailure, __VA_ARGS__ ) +#define CHECK_THROWS_AS( expr, exceptionType ) INTERNAL_CATCH_THROWS_AS( "CHECK_THROWS_AS", exceptionType, Catch::ResultDisposition::ContinueOnFailure, expr ) +#define CHECK_THROWS_WITH( expr, matcher ) INTERNAL_CATCH_THROWS_STR_MATCHES( "CHECK_THROWS_WITH", Catch::ResultDisposition::ContinueOnFailure, matcher, expr ) +#if !defined(CATCH_CONFIG_DISABLE_MATCHERS) +#define CHECK_THROWS_MATCHES( expr, exceptionType, matcher ) INTERNAL_CATCH_THROWS_MATCHES( "CHECK_THROWS_MATCHES", exceptionType, Catch::ResultDisposition::ContinueOnFailure, matcher, expr ) +#endif // CATCH_CONFIG_DISABLE_MATCHERS +#define CHECK_NOTHROW( ... ) INTERNAL_CATCH_NO_THROW( "CHECK_NOTHROW", Catch::ResultDisposition::ContinueOnFailure, __VA_ARGS__ ) + +#if !defined(CATCH_CONFIG_DISABLE_MATCHERS) +#define CHECK_THAT( arg, matcher ) INTERNAL_CHECK_THAT( "CHECK_THAT", matcher, Catch::ResultDisposition::ContinueOnFailure, arg ) + +#define REQUIRE_THAT( arg, matcher ) INTERNAL_CHECK_THAT( "REQUIRE_THAT", matcher, Catch::ResultDisposition::Normal, arg ) +#endif // CATCH_CONFIG_DISABLE_MATCHERS + +#define INFO( msg ) INTERNAL_CATCH_INFO( "INFO", msg ) +#define UNSCOPED_INFO( msg ) INTERNAL_CATCH_UNSCOPED_INFO( "UNSCOPED_INFO", msg ) +#define WARN( msg ) INTERNAL_CATCH_MSG( "WARN", Catch::ResultWas::Warning, Catch::ResultDisposition::ContinueOnFailure, msg ) +#define CAPTURE( ... ) INTERNAL_CATCH_CAPTURE( INTERNAL_CATCH_UNIQUE_NAME(capturer), "CAPTURE",__VA_ARGS__ ) + +#define TEST_CASE( ... ) INTERNAL_CATCH_TESTCASE( __VA_ARGS__ ) +#define TEST_CASE_METHOD( className, ... ) INTERNAL_CATCH_TEST_CASE_METHOD( className, __VA_ARGS__ ) +#define METHOD_AS_TEST_CASE( method, ... ) INTERNAL_CATCH_METHOD_AS_TEST_CASE( method, __VA_ARGS__ ) +#define REGISTER_TEST_CASE( Function, ... ) INTERNAL_CATCH_REGISTER_TESTCASE( Function, __VA_ARGS__ ) +#define SECTION( ... ) INTERNAL_CATCH_SECTION( __VA_ARGS__ ) +#define DYNAMIC_SECTION( ... ) INTERNAL_CATCH_DYNAMIC_SECTION( __VA_ARGS__ ) +#define FAIL( ... ) INTERNAL_CATCH_MSG( "FAIL", Catch::ResultWas::ExplicitFailure, Catch::ResultDisposition::Normal, __VA_ARGS__ ) +#define FAIL_CHECK( ... ) INTERNAL_CATCH_MSG( "FAIL_CHECK", Catch::ResultWas::ExplicitFailure, Catch::ResultDisposition::ContinueOnFailure, __VA_ARGS__ ) +#define SUCCEED( ... ) INTERNAL_CATCH_MSG( "SUCCEED", Catch::ResultWas::Ok, Catch::ResultDisposition::ContinueOnFailure, __VA_ARGS__ ) +#define ANON_TEST_CASE() INTERNAL_CATCH_TESTCASE() + +#ifndef CATCH_CONFIG_TRADITIONAL_MSVC_PREPROCESSOR +#define TEMPLATE_TEST_CASE( ... ) INTERNAL_CATCH_TEMPLATE_TEST_CASE( __VA_ARGS__ ) +#define TEMPLATE_TEST_CASE_METHOD( className, ... ) INTERNAL_CATCH_TEMPLATE_TEST_CASE_METHOD( className, __VA_ARGS__ ) +#define TEMPLATE_PRODUCT_TEST_CASE( ... ) INTERNAL_CATCH_TEMPLATE_PRODUCT_TEST_CASE( __VA_ARGS__ ) +#define TEMPLATE_PRODUCT_TEST_CASE_METHOD( className, ... ) INTERNAL_CATCH_TEMPLATE_PRODUCT_TEST_CASE_METHOD( className, __VA_ARGS__ ) +#else +#define TEMPLATE_TEST_CASE( ... ) INTERNAL_CATCH_EXPAND_VARGS( INTERNAL_CATCH_TEMPLATE_TEST_CASE( __VA_ARGS__ ) ) +#define TEMPLATE_TEST_CASE_METHOD( className, ... ) INTERNAL_CATCH_EXPAND_VARGS( INTERNAL_CATCH_TEMPLATE_TEST_CASE_METHOD( className, __VA_ARGS__ ) ) +#define TEMPLATE_PRODUCT_TEST_CASE( ... ) INTERNAL_CATCH_EXPAND_VARGS( INTERNAL_CATCH_TEMPLATE_PRODUCT_TEST_CASE( __VA_ARGS__ ) ) +#define TEMPLATE_PRODUCT_TEST_CASE_METHOD( className, ... ) INTERNAL_CATCH_EXPAND_VARGS( INTERNAL_CATCH_TEMPLATE_PRODUCT_TEST_CASE_METHOD( className, __VA_ARGS__ ) ) +#endif + +#if !defined(CATCH_CONFIG_RUNTIME_STATIC_REQUIRE) +#define STATIC_REQUIRE( ... ) static_assert( __VA_ARGS__, #__VA_ARGS__ ); SUCCEED( #__VA_ARGS__ ) +#define STATIC_REQUIRE_FALSE( ... ) static_assert( !(__VA_ARGS__), "!(" #__VA_ARGS__ ")" ); SUCCEED( "!(" #__VA_ARGS__ ")" ) +#else +#define STATIC_REQUIRE( ... ) REQUIRE( __VA_ARGS__ ) +#define STATIC_REQUIRE_FALSE( ... ) REQUIRE_FALSE( __VA_ARGS__ ) +#endif + +#endif + +#define CATCH_TRANSLATE_EXCEPTION( signature ) INTERNAL_CATCH_TRANSLATE_EXCEPTION( signature ) + +// "BDD-style" convenience wrappers +#define SCENARIO( ... ) TEST_CASE( "Scenario: " __VA_ARGS__ ) +#define SCENARIO_METHOD( className, ... ) INTERNAL_CATCH_TEST_CASE_METHOD( className, "Scenario: " __VA_ARGS__ ) + +#define GIVEN( desc ) INTERNAL_CATCH_DYNAMIC_SECTION( " Given: " << desc ) +#define AND_GIVEN( desc ) INTERNAL_CATCH_DYNAMIC_SECTION( "And given: " << desc ) +#define WHEN( desc ) INTERNAL_CATCH_DYNAMIC_SECTION( " When: " << desc ) +#define AND_WHEN( desc ) INTERNAL_CATCH_DYNAMIC_SECTION( " And when: " << desc ) +#define THEN( desc ) INTERNAL_CATCH_DYNAMIC_SECTION( " Then: " << desc ) +#define AND_THEN( desc ) INTERNAL_CATCH_DYNAMIC_SECTION( " And: " << desc ) + +using Catch::Detail::Approx; + +#else // CATCH_CONFIG_DISABLE + +////// +// If this config identifier is defined then all CATCH macros are prefixed with CATCH_ +#ifdef CATCH_CONFIG_PREFIX_ALL + +#define CATCH_REQUIRE( ... ) (void)(0) +#define CATCH_REQUIRE_FALSE( ... ) (void)(0) + +#define CATCH_REQUIRE_THROWS( ... ) (void)(0) +#define CATCH_REQUIRE_THROWS_AS( expr, exceptionType ) (void)(0) +#define CATCH_REQUIRE_THROWS_WITH( expr, matcher ) (void)(0) +#if !defined(CATCH_CONFIG_DISABLE_MATCHERS) +#define CATCH_REQUIRE_THROWS_MATCHES( expr, exceptionType, matcher ) (void)(0) +#endif// CATCH_CONFIG_DISABLE_MATCHERS +#define CATCH_REQUIRE_NOTHROW( ... ) (void)(0) + +#define CATCH_CHECK( ... ) (void)(0) +#define CATCH_CHECK_FALSE( ... ) (void)(0) +#define CATCH_CHECKED_IF( ... ) if (__VA_ARGS__) +#define CATCH_CHECKED_ELSE( ... ) if (!(__VA_ARGS__)) +#define CATCH_CHECK_NOFAIL( ... ) (void)(0) + +#define CATCH_CHECK_THROWS( ... ) (void)(0) +#define CATCH_CHECK_THROWS_AS( expr, exceptionType ) (void)(0) +#define CATCH_CHECK_THROWS_WITH( expr, matcher ) (void)(0) +#if !defined(CATCH_CONFIG_DISABLE_MATCHERS) +#define CATCH_CHECK_THROWS_MATCHES( expr, exceptionType, matcher ) (void)(0) +#endif // CATCH_CONFIG_DISABLE_MATCHERS +#define CATCH_CHECK_NOTHROW( ... ) (void)(0) + +#if !defined(CATCH_CONFIG_DISABLE_MATCHERS) +#define CATCH_CHECK_THAT( arg, matcher ) (void)(0) + +#define CATCH_REQUIRE_THAT( arg, matcher ) (void)(0) +#endif // CATCH_CONFIG_DISABLE_MATCHERS + +#define CATCH_INFO( msg ) (void)(0) +#define CATCH_WARN( msg ) (void)(0) +#define CATCH_CAPTURE( msg ) (void)(0) + +#define CATCH_TEST_CASE( ... ) INTERNAL_CATCH_TESTCASE_NO_REGISTRATION(INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_S_T____ )) +#define CATCH_TEST_CASE_METHOD( className, ... ) INTERNAL_CATCH_TESTCASE_NO_REGISTRATION(INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_S_T____ )) +#define CATCH_METHOD_AS_TEST_CASE( method, ... ) +#define CATCH_REGISTER_TEST_CASE( Function, ... ) (void)(0) +#define CATCH_SECTION( ... ) +#define CATCH_DYNAMIC_SECTION( ... ) +#define CATCH_FAIL( ... ) (void)(0) +#define CATCH_FAIL_CHECK( ... ) (void)(0) +#define CATCH_SUCCEED( ... ) (void)(0) + +#define CATCH_ANON_TEST_CASE() INTERNAL_CATCH_TESTCASE_NO_REGISTRATION(INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_S_T____ )) + +#ifndef CATCH_CONFIG_TRADITIONAL_MSVC_PREPROCESSOR +#define CATCH_TEMPLATE_TEST_CASE( ... ) INTERNAL_CATCH_TEMPLATE_TEST_CASE_NO_REGISTRATION(INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____ ) ) +#define CATCH_TEMPLATE_TEST_CASE_METHOD( className, ... ) INTERNAL_CATCH_TEMPLATE_TEST_CASE_METHOD_NO_REGISTRATION(INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____ ), className ) +#define CATCH_TEMPLATE_PRODUCT_TEST_CASE( ... ) CATCH_TEMPLATE_TEST_CASE( __VA_ARGS__ ) +#define CATCH_TEMPLATE_PRODUCT_TEST_CASE_METHOD( className, ... ) CATCH_TEMPLATE_TEST_CASE_METHOD( className, __VA_ARGS__ ) +#else +#define CATCH_TEMPLATE_TEST_CASE( ... ) INTERNAL_CATCH_EXPAND_VARGS( INTERNAL_CATCH_TEMPLATE_TEST_CASE_NO_REGISTRATION(INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____ ) ) ) +#define CATCH_TEMPLATE_TEST_CASE_METHOD( className, ... ) INTERNAL_CATCH_EXPAND_VARGS( INTERNAL_CATCH_TEMPLATE_TEST_CASE_METHOD_NO_REGISTRATION(INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____ ), className ) ) +#define CATCH_TEMPLATE_PRODUCT_TEST_CASE( ... ) CATCH_TEMPLATE_TEST_CASE( __VA_ARGS__ ) +#define CATCH_TEMPLATE_PRODUCT_TEST_CASE_METHOD( className, ... ) CATCH_TEMPLATE_TEST_CASE_METHOD( className, __VA_ARGS__ ) +#endif + +// "BDD-style" convenience wrappers +#define CATCH_SCENARIO( ... ) INTERNAL_CATCH_TESTCASE_NO_REGISTRATION(INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_S_T____ )) +#define CATCH_SCENARIO_METHOD( className, ... ) INTERNAL_CATCH_TESTCASE_METHOD_NO_REGISTRATION(INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_S_T____ ), className ) +#define CATCH_GIVEN( desc ) +#define CATCH_AND_GIVEN( desc ) +#define CATCH_WHEN( desc ) +#define CATCH_AND_WHEN( desc ) +#define CATCH_THEN( desc ) +#define CATCH_AND_THEN( desc ) + +#define CATCH_STATIC_REQUIRE( ... ) (void)(0) +#define CATCH_STATIC_REQUIRE_FALSE( ... ) (void)(0) + +// If CATCH_CONFIG_PREFIX_ALL is not defined then the CATCH_ prefix is not required +#else + +#define REQUIRE( ... ) (void)(0) +#define REQUIRE_FALSE( ... ) (void)(0) + +#define REQUIRE_THROWS( ... ) (void)(0) +#define REQUIRE_THROWS_AS( expr, exceptionType ) (void)(0) +#define REQUIRE_THROWS_WITH( expr, matcher ) (void)(0) +#if !defined(CATCH_CONFIG_DISABLE_MATCHERS) +#define REQUIRE_THROWS_MATCHES( expr, exceptionType, matcher ) (void)(0) +#endif // CATCH_CONFIG_DISABLE_MATCHERS +#define REQUIRE_NOTHROW( ... ) (void)(0) + +#define CHECK( ... ) (void)(0) +#define CHECK_FALSE( ... ) (void)(0) +#define CHECKED_IF( ... ) if (__VA_ARGS__) +#define CHECKED_ELSE( ... ) if (!(__VA_ARGS__)) +#define CHECK_NOFAIL( ... ) (void)(0) + +#define CHECK_THROWS( ... ) (void)(0) +#define CHECK_THROWS_AS( expr, exceptionType ) (void)(0) +#define CHECK_THROWS_WITH( expr, matcher ) (void)(0) +#if !defined(CATCH_CONFIG_DISABLE_MATCHERS) +#define CHECK_THROWS_MATCHES( expr, exceptionType, matcher ) (void)(0) +#endif // CATCH_CONFIG_DISABLE_MATCHERS +#define CHECK_NOTHROW( ... ) (void)(0) + +#if !defined(CATCH_CONFIG_DISABLE_MATCHERS) +#define CHECK_THAT( arg, matcher ) (void)(0) + +#define REQUIRE_THAT( arg, matcher ) (void)(0) +#endif // CATCH_CONFIG_DISABLE_MATCHERS + +#define INFO( msg ) (void)(0) +#define WARN( msg ) (void)(0) +#define CAPTURE( msg ) (void)(0) + +#define TEST_CASE( ... ) INTERNAL_CATCH_TESTCASE_NO_REGISTRATION(INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_S_T____ )) +#define TEST_CASE_METHOD( className, ... ) INTERNAL_CATCH_TESTCASE_NO_REGISTRATION(INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_S_T____ )) +#define METHOD_AS_TEST_CASE( method, ... ) +#define REGISTER_TEST_CASE( Function, ... ) (void)(0) +#define SECTION( ... ) +#define DYNAMIC_SECTION( ... ) +#define FAIL( ... ) (void)(0) +#define FAIL_CHECK( ... ) (void)(0) +#define SUCCEED( ... ) (void)(0) +#define ANON_TEST_CASE() INTERNAL_CATCH_TESTCASE_NO_REGISTRATION(INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_S_T____ )) + +#ifndef CATCH_CONFIG_TRADITIONAL_MSVC_PREPROCESSOR +#define TEMPLATE_TEST_CASE( ... ) INTERNAL_CATCH_TEMPLATE_TEST_CASE_NO_REGISTRATION(INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____ ) ) +#define TEMPLATE_TEST_CASE_METHOD( className, ... ) INTERNAL_CATCH_TEMPLATE_TEST_CASE_METHOD_NO_REGISTRATION(INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____ ), className ) +#define TEMPLATE_PRODUCT_TEST_CASE( ... ) TEMPLATE_TEST_CASE( __VA_ARGS__ ) +#define TEMPLATE_PRODUCT_TEST_CASE_METHOD( className, ... ) TEMPLATE_TEST_CASE_METHOD( className, __VA_ARGS__ ) +#else +#define TEMPLATE_TEST_CASE( ... ) INTERNAL_CATCH_EXPAND_VARGS( INTERNAL_CATCH_TEMPLATE_TEST_CASE_NO_REGISTRATION(INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____ ) ) ) +#define TEMPLATE_TEST_CASE_METHOD( className, ... ) INTERNAL_CATCH_EXPAND_VARGS( INTERNAL_CATCH_TEMPLATE_TEST_CASE_METHOD_NO_REGISTRATION(INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____ ), className ) ) +#define TEMPLATE_PRODUCT_TEST_CASE( ... ) TEMPLATE_TEST_CASE( __VA_ARGS__ ) +#define TEMPLATE_PRODUCT_TEST_CASE_METHOD( className, ... ) TEMPLATE_TEST_CASE_METHOD( className, __VA_ARGS__ ) +#endif + +#define STATIC_REQUIRE( ... ) (void)(0) +#define STATIC_REQUIRE_FALSE( ... ) (void)(0) + +#endif + +#define CATCH_TRANSLATE_EXCEPTION( signature ) INTERNAL_CATCH_TRANSLATE_EXCEPTION_NO_REG( INTERNAL_CATCH_UNIQUE_NAME( catch_internal_ExceptionTranslator ), signature ) + +// "BDD-style" convenience wrappers +#define SCENARIO( ... ) INTERNAL_CATCH_TESTCASE_NO_REGISTRATION(INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_S_T____ ) ) +#define SCENARIO_METHOD( className, ... ) INTERNAL_CATCH_TESTCASE_METHOD_NO_REGISTRATION(INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_S_T____ ), className ) + +#define GIVEN( desc ) +#define AND_GIVEN( desc ) +#define WHEN( desc ) +#define AND_WHEN( desc ) +#define THEN( desc ) +#define AND_THEN( desc ) + +using Catch::Detail::Approx; + +#endif + +#endif // ! CATCH_CONFIG_IMPL_ONLY + +// start catch_reenable_warnings.h + + +#ifdef __clang__ +# ifdef __ICC // icpc defines the __clang__ macro +# pragma warning(pop) +# else +# pragma clang diagnostic pop +# endif +#elif defined __GNUC__ +# pragma GCC diagnostic pop +#endif + +// end catch_reenable_warnings.h +// end catch.hpp +#endif // TWOBLUECUBES_SINGLE_INCLUDE_CATCH_HPP_INCLUDED + diff --git a/hw-libs/printf/test/test_suite.cpp b/hw-libs/printf/test/test_suite.cpp new file mode 100644 index 000000000..c26dc7696 --- /dev/null +++ b/hw-libs/printf/test/test_suite.cpp @@ -0,0 +1,1513 @@ +/////////////////////////////////////////////////////////////////////////////// +// \author (c) Marco Paland (info@paland.com) +// 2017-2019, PALANDesign Hannover, Germany +// +// \license The MIT License (MIT) +// +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +// THE SOFTWARE. +// +// \brief printf unit tests +// +/////////////////////////////////////////////////////////////////////////////// + +// use the 'catch' test framework +#define CATCH_CONFIG_MAIN +#include "catch.hpp" + +#include +#include +#include + + +namespace test { + // use functions in own test namespace to avoid stdio conflicts + #include "../printf.h" + #include "../printf.c" +} // namespace test + + +// dummy putchar +static char printf_buffer[100]; +static size_t printf_idx = 0U; + +void test::_putchar(char character) +{ + printf_buffer[printf_idx++] = character; +} + +void _out_fct(char character, void* arg) +{ + (void)arg; + printf_buffer[printf_idx++] = character; +} + + +TEST_CASE("printf", "[]" ) { + printf_idx = 0U; + memset(printf_buffer, 0xCC, 100U); + REQUIRE(test::printf("% d", 4232) == 5); + REQUIRE(printf_buffer[5] == (char)0xCC); + printf_buffer[5] = 0; + REQUIRE(!strcmp(printf_buffer, " 4232")); +} + + +TEST_CASE("fctprintf", "[]" ) { + printf_idx = 0U; + memset(printf_buffer, 0xCC, 100U); + test::fctprintf(&_out_fct, nullptr, "This is a test of %X", 0x12EFU); + REQUIRE(!strncmp(printf_buffer, "This is a test of 12EF", 22U)); + REQUIRE(printf_buffer[22] == (char)0xCC); +} + + +TEST_CASE("snprintf", "[]" ) { + char buffer[100]; + + test::snprintf(buffer, 100U, "%d", -1000); + REQUIRE(!strcmp(buffer, "-1000")); + + test::snprintf(buffer, 3U, "%d", -1000); + REQUIRE(!strcmp(buffer, "-1")); +} + +static void vprintf_builder_1(char* buffer, ...) +{ + va_list args; + va_start(args, buffer); + test::vprintf("%d", args); + va_end(args); +} + +static void vsnprintf_builder_1(char* buffer, ...) +{ + va_list args; + va_start(args, buffer); + test::vsnprintf(buffer, 100U, "%d", args); + va_end(args); +} + +static void vsnprintf_builder_3(char* buffer, ...) +{ + va_list args; + va_start(args, buffer); + test::vsnprintf(buffer, 100U, "%d %d %s", args); + va_end(args); +} + + +TEST_CASE("vprintf", "[]" ) { + char buffer[100]; + printf_idx = 0U; + memset(printf_buffer, 0xCC, 100U); + vprintf_builder_1(buffer, 2345); + REQUIRE(printf_buffer[4] == (char)0xCC); + printf_buffer[4] = 0; + REQUIRE(!strcmp(printf_buffer, "2345")); +} + + +TEST_CASE("vsnprintf", "[]" ) { + char buffer[100]; + + vsnprintf_builder_1(buffer, -1); + REQUIRE(!strcmp(buffer, "-1")); + + vsnprintf_builder_3(buffer, 3, -1000, "test"); + REQUIRE(!strcmp(buffer, "3 -1000 test")); +} + + +TEST_CASE("space flag", "[]" ) { + char buffer[100]; + + test::sprintf(buffer, "% d", 42); + REQUIRE(!strcmp(buffer, " 42")); + + test::sprintf(buffer, "% d", -42); + REQUIRE(!strcmp(buffer, "-42")); + + test::sprintf(buffer, "% 5d", 42); + REQUIRE(!strcmp(buffer, " 42")); + + test::sprintf(buffer, "% 5d", -42); + REQUIRE(!strcmp(buffer, " -42")); + + test::sprintf(buffer, "% 15d", 42); + REQUIRE(!strcmp(buffer, " 42")); + + test::sprintf(buffer, "% 15d", -42); + REQUIRE(!strcmp(buffer, " -42")); + + test::sprintf(buffer, "% 15d", -42); + REQUIRE(!strcmp(buffer, " -42")); + + test::sprintf(buffer, "% 15.3f", -42.987); + REQUIRE(!strcmp(buffer, " -42.987")); + + test::sprintf(buffer, "% 15.3f", 42.987); + REQUIRE(!strcmp(buffer, " 42.987")); + + test::sprintf(buffer, "% s", "Hello testing"); + REQUIRE(!strcmp(buffer, "Hello testing")); + + test::sprintf(buffer, "% d", 1024); + REQUIRE(!strcmp(buffer, " 1024")); + + test::sprintf(buffer, "% d", -1024); + REQUIRE(!strcmp(buffer, "-1024")); + + test::sprintf(buffer, "% i", 1024); + REQUIRE(!strcmp(buffer, " 1024")); + + test::sprintf(buffer, "% i", -1024); + REQUIRE(!strcmp(buffer, "-1024")); + + test::sprintf(buffer, "% u", 1024); + REQUIRE(!strcmp(buffer, "1024")); + + test::sprintf(buffer, "% u", 4294966272U); + REQUIRE(!strcmp(buffer, "4294966272")); + + test::sprintf(buffer, "% o", 511); + REQUIRE(!strcmp(buffer, "777")); + + test::sprintf(buffer, "% o", 4294966785U); + REQUIRE(!strcmp(buffer, "37777777001")); + + test::sprintf(buffer, "% x", 305441741); + REQUIRE(!strcmp(buffer, "1234abcd")); + + test::sprintf(buffer, "% x", 3989525555U); + REQUIRE(!strcmp(buffer, "edcb5433")); + + test::sprintf(buffer, "% X", 305441741); + REQUIRE(!strcmp(buffer, "1234ABCD")); + + test::sprintf(buffer, "% X", 3989525555U); + REQUIRE(!strcmp(buffer, "EDCB5433")); + + test::sprintf(buffer, "% c", 'x'); + REQUIRE(!strcmp(buffer, "x")); +} + + +TEST_CASE("+ flag", "[]" ) { + char buffer[100]; + + test::sprintf(buffer, "%+d", 42); + REQUIRE(!strcmp(buffer, "+42")); + + test::sprintf(buffer, "%+d", -42); + REQUIRE(!strcmp(buffer, "-42")); + + test::sprintf(buffer, "%+5d", 42); + REQUIRE(!strcmp(buffer, " +42")); + + test::sprintf(buffer, "%+5d", -42); + REQUIRE(!strcmp(buffer, " -42")); + + test::sprintf(buffer, "%+15d", 42); + REQUIRE(!strcmp(buffer, " +42")); + + test::sprintf(buffer, "%+15d", -42); + REQUIRE(!strcmp(buffer, " -42")); + + test::sprintf(buffer, "%+s", "Hello testing"); + REQUIRE(!strcmp(buffer, "Hello testing")); + + test::sprintf(buffer, "%+d", 1024); + REQUIRE(!strcmp(buffer, "+1024")); + + test::sprintf(buffer, "%+d", -1024); + REQUIRE(!strcmp(buffer, "-1024")); + + test::sprintf(buffer, "%+i", 1024); + REQUIRE(!strcmp(buffer, "+1024")); + + test::sprintf(buffer, "%+i", -1024); + REQUIRE(!strcmp(buffer, "-1024")); + + test::sprintf(buffer, "%+u", 1024); + REQUIRE(!strcmp(buffer, "1024")); + + test::sprintf(buffer, "%+u", 4294966272U); + REQUIRE(!strcmp(buffer, "4294966272")); + + test::sprintf(buffer, "%+o", 511); + REQUIRE(!strcmp(buffer, "777")); + + test::sprintf(buffer, "%+o", 4294966785U); + REQUIRE(!strcmp(buffer, "37777777001")); + + test::sprintf(buffer, "%+x", 305441741); + REQUIRE(!strcmp(buffer, "1234abcd")); + + test::sprintf(buffer, "%+x", 3989525555U); + REQUIRE(!strcmp(buffer, "edcb5433")); + + test::sprintf(buffer, "%+X", 305441741); + REQUIRE(!strcmp(buffer, "1234ABCD")); + + test::sprintf(buffer, "%+X", 3989525555U); + REQUIRE(!strcmp(buffer, "EDCB5433")); + + test::sprintf(buffer, "%+c", 'x'); + REQUIRE(!strcmp(buffer, "x")); + + test::sprintf(buffer, "%+.0d", 0); + REQUIRE(!strcmp(buffer, "+")); +} + + +TEST_CASE("0 flag", "[]" ) { + char buffer[100]; + + test::sprintf(buffer, "%0d", 42); + REQUIRE(!strcmp(buffer, "42")); + + test::sprintf(buffer, "%0ld", 42L); + REQUIRE(!strcmp(buffer, "42")); + + test::sprintf(buffer, "%0d", -42); + REQUIRE(!strcmp(buffer, "-42")); + + test::sprintf(buffer, "%05d", 42); + REQUIRE(!strcmp(buffer, "00042")); + + test::sprintf(buffer, "%05d", -42); + REQUIRE(!strcmp(buffer, "-0042")); + + test::sprintf(buffer, "%015d", 42); + REQUIRE(!strcmp(buffer, "000000000000042")); + + test::sprintf(buffer, "%015d", -42); + REQUIRE(!strcmp(buffer, "-00000000000042")); + + test::sprintf(buffer, "%015.2f", 42.1234); + REQUIRE(!strcmp(buffer, "000000000042.12")); + + test::sprintf(buffer, "%015.3f", 42.9876); + REQUIRE(!strcmp(buffer, "00000000042.988")); + + test::sprintf(buffer, "%015.5f", -42.9876); + REQUIRE(!strcmp(buffer, "-00000042.98760")); +} + + +TEST_CASE("- flag", "[]" ) { + char buffer[100]; + + test::sprintf(buffer, "%-d", 42); + REQUIRE(!strcmp(buffer, "42")); + + test::sprintf(buffer, "%-d", -42); + REQUIRE(!strcmp(buffer, "-42")); + + test::sprintf(buffer, "%-5d", 42); + REQUIRE(!strcmp(buffer, "42 ")); + + test::sprintf(buffer, "%-5d", -42); + REQUIRE(!strcmp(buffer, "-42 ")); + + test::sprintf(buffer, "%-15d", 42); + REQUIRE(!strcmp(buffer, "42 ")); + + test::sprintf(buffer, "%-15d", -42); + REQUIRE(!strcmp(buffer, "-42 ")); + + test::sprintf(buffer, "%-0d", 42); + REQUIRE(!strcmp(buffer, "42")); + + test::sprintf(buffer, "%-0d", -42); + REQUIRE(!strcmp(buffer, "-42")); + + test::sprintf(buffer, "%-05d", 42); + REQUIRE(!strcmp(buffer, "42 ")); + + test::sprintf(buffer, "%-05d", -42); + REQUIRE(!strcmp(buffer, "-42 ")); + + test::sprintf(buffer, "%-015d", 42); + REQUIRE(!strcmp(buffer, "42 ")); + + test::sprintf(buffer, "%-015d", -42); + REQUIRE(!strcmp(buffer, "-42 ")); + + test::sprintf(buffer, "%0-d", 42); + REQUIRE(!strcmp(buffer, "42")); + + test::sprintf(buffer, "%0-d", -42); + REQUIRE(!strcmp(buffer, "-42")); + + test::sprintf(buffer, "%0-5d", 42); + REQUIRE(!strcmp(buffer, "42 ")); + + test::sprintf(buffer, "%0-5d", -42); + REQUIRE(!strcmp(buffer, "-42 ")); + + test::sprintf(buffer, "%0-15d", 42); + REQUIRE(!strcmp(buffer, "42 ")); + + test::sprintf(buffer, "%0-15d", -42); + REQUIRE(!strcmp(buffer, "-42 ")); + + test::sprintf(buffer, "%0-15.3e", -42.); +#ifndef PRINTF_DISABLE_SUPPORT_EXPONENTIAL + REQUIRE(!strcmp(buffer, "-4.200e+01 ")); +#else + REQUIRE(!strcmp(buffer, "e")); +#endif + + test::sprintf(buffer, "%0-15.3g", -42.); +#ifndef PRINTF_DISABLE_SUPPORT_EXPONENTIAL + REQUIRE(!strcmp(buffer, "-42.0 ")); +#else + REQUIRE(!strcmp(buffer, "g")); +#endif +} + + +TEST_CASE("# flag", "[]" ) { + char buffer[100]; + + test::sprintf(buffer, "%#.0x", 0); + REQUIRE(!strcmp(buffer, "")); + test::sprintf(buffer, "%#.1x", 0); + REQUIRE(!strcmp(buffer, "0")); + test::sprintf(buffer, "%#.0llx", (long long)0); + REQUIRE(!strcmp(buffer, "")); + test::sprintf(buffer, "%#.8x", 0x614e); + REQUIRE(!strcmp(buffer, "0x0000614e")); + test::sprintf(buffer,"%#b", 6); + REQUIRE(!strcmp(buffer, "0b110")); +} + + +TEST_CASE("specifier", "[]" ) { + char buffer[100]; + + test::sprintf(buffer, "Hello testing"); + REQUIRE(!strcmp(buffer, "Hello testing")); + + test::sprintf(buffer, "%s", "Hello testing"); + REQUIRE(!strcmp(buffer, "Hello testing")); + + test::sprintf(buffer, "%d", 1024); + REQUIRE(!strcmp(buffer, "1024")); + + test::sprintf(buffer, "%d", -1024); + REQUIRE(!strcmp(buffer, "-1024")); + + test::sprintf(buffer, "%i", 1024); + REQUIRE(!strcmp(buffer, "1024")); + + test::sprintf(buffer, "%i", -1024); + REQUIRE(!strcmp(buffer, "-1024")); + + test::sprintf(buffer, "%u", 1024); + REQUIRE(!strcmp(buffer, "1024")); + + test::sprintf(buffer, "%u", 4294966272U); + REQUIRE(!strcmp(buffer, "4294966272")); + + test::sprintf(buffer, "%o", 511); + REQUIRE(!strcmp(buffer, "777")); + + test::sprintf(buffer, "%o", 4294966785U); + REQUIRE(!strcmp(buffer, "37777777001")); + + test::sprintf(buffer, "%x", 305441741); + REQUIRE(!strcmp(buffer, "1234abcd")); + + test::sprintf(buffer, "%x", 3989525555U); + REQUIRE(!strcmp(buffer, "edcb5433")); + + test::sprintf(buffer, "%X", 305441741); + REQUIRE(!strcmp(buffer, "1234ABCD")); + + test::sprintf(buffer, "%X", 3989525555U); + REQUIRE(!strcmp(buffer, "EDCB5433")); + + test::sprintf(buffer, "%%"); + REQUIRE(!strcmp(buffer, "%")); +} + + +TEST_CASE("width", "[]" ) { + char buffer[100]; + + test::sprintf(buffer, "%1s", "Hello testing"); + REQUIRE(!strcmp(buffer, "Hello testing")); + + test::sprintf(buffer, "%1d", 1024); + REQUIRE(!strcmp(buffer, "1024")); + + test::sprintf(buffer, "%1d", -1024); + REQUIRE(!strcmp(buffer, "-1024")); + + test::sprintf(buffer, "%1i", 1024); + REQUIRE(!strcmp(buffer, "1024")); + + test::sprintf(buffer, "%1i", -1024); + REQUIRE(!strcmp(buffer, "-1024")); + + test::sprintf(buffer, "%1u", 1024); + REQUIRE(!strcmp(buffer, "1024")); + + test::sprintf(buffer, "%1u", 4294966272U); + REQUIRE(!strcmp(buffer, "4294966272")); + + test::sprintf(buffer, "%1o", 511); + REQUIRE(!strcmp(buffer, "777")); + + test::sprintf(buffer, "%1o", 4294966785U); + REQUIRE(!strcmp(buffer, "37777777001")); + + test::sprintf(buffer, "%1x", 305441741); + REQUIRE(!strcmp(buffer, "1234abcd")); + + test::sprintf(buffer, "%1x", 3989525555U); + REQUIRE(!strcmp(buffer, "edcb5433")); + + test::sprintf(buffer, "%1X", 305441741); + REQUIRE(!strcmp(buffer, "1234ABCD")); + + test::sprintf(buffer, "%1X", 3989525555U); + REQUIRE(!strcmp(buffer, "EDCB5433")); + + test::sprintf(buffer, "%1c", 'x'); + REQUIRE(!strcmp(buffer, "x")); +} + + +TEST_CASE("width 20", "[]" ) { + char buffer[100]; + + test::sprintf(buffer, "%20s", "Hello"); + REQUIRE(!strcmp(buffer, " Hello")); + + test::sprintf(buffer, "%20d", 1024); + REQUIRE(!strcmp(buffer, " 1024")); + + test::sprintf(buffer, "%20d", -1024); + REQUIRE(!strcmp(buffer, " -1024")); + + test::sprintf(buffer, "%20i", 1024); + REQUIRE(!strcmp(buffer, " 1024")); + + test::sprintf(buffer, "%20i", -1024); + REQUIRE(!strcmp(buffer, " -1024")); + + test::sprintf(buffer, "%20u", 1024); + REQUIRE(!strcmp(buffer, " 1024")); + + test::sprintf(buffer, "%20u", 4294966272U); + REQUIRE(!strcmp(buffer, " 4294966272")); + + test::sprintf(buffer, "%20o", 511); + REQUIRE(!strcmp(buffer, " 777")); + + test::sprintf(buffer, "%20o", 4294966785U); + REQUIRE(!strcmp(buffer, " 37777777001")); + + test::sprintf(buffer, "%20x", 305441741); + REQUIRE(!strcmp(buffer, " 1234abcd")); + + test::sprintf(buffer, "%20x", 3989525555U); + REQUIRE(!strcmp(buffer, " edcb5433")); + + test::sprintf(buffer, "%20X", 305441741); + REQUIRE(!strcmp(buffer, " 1234ABCD")); + + test::sprintf(buffer, "%20X", 3989525555U); + REQUIRE(!strcmp(buffer, " EDCB5433")); + + test::sprintf(buffer, "%20c", 'x'); + REQUIRE(!strcmp(buffer, " x")); +} + + +TEST_CASE("width *20", "[]" ) { + char buffer[100]; + + test::sprintf(buffer, "%*s", 20, "Hello"); + REQUIRE(!strcmp(buffer, " Hello")); + + test::sprintf(buffer, "%*d", 20, 1024); + REQUIRE(!strcmp(buffer, " 1024")); + + test::sprintf(buffer, "%*d", 20, -1024); + REQUIRE(!strcmp(buffer, " -1024")); + + test::sprintf(buffer, "%*i", 20, 1024); + REQUIRE(!strcmp(buffer, " 1024")); + + test::sprintf(buffer, "%*i", 20, -1024); + REQUIRE(!strcmp(buffer, " -1024")); + + test::sprintf(buffer, "%*u", 20, 1024); + REQUIRE(!strcmp(buffer, " 1024")); + + test::sprintf(buffer, "%*u", 20, 4294966272U); + REQUIRE(!strcmp(buffer, " 4294966272")); + + test::sprintf(buffer, "%*o", 20, 511); + REQUIRE(!strcmp(buffer, " 777")); + + test::sprintf(buffer, "%*o", 20, 4294966785U); + REQUIRE(!strcmp(buffer, " 37777777001")); + + test::sprintf(buffer, "%*x", 20, 305441741); + REQUIRE(!strcmp(buffer, " 1234abcd")); + + test::sprintf(buffer, "%*x", 20, 3989525555U); + REQUIRE(!strcmp(buffer, " edcb5433")); + + test::sprintf(buffer, "%*X", 20, 305441741); + REQUIRE(!strcmp(buffer, " 1234ABCD")); + + test::sprintf(buffer, "%*X", 20, 3989525555U); + REQUIRE(!strcmp(buffer, " EDCB5433")); + + test::sprintf(buffer, "%*c", 20,'x'); + REQUIRE(!strcmp(buffer, " x")); +} + + +TEST_CASE("width -20", "[]" ) { + char buffer[100]; + + test::sprintf(buffer, "%-20s", "Hello"); + REQUIRE(!strcmp(buffer, "Hello ")); + + test::sprintf(buffer, "%-20d", 1024); + REQUIRE(!strcmp(buffer, "1024 ")); + + test::sprintf(buffer, "%-20d", -1024); + REQUIRE(!strcmp(buffer, "-1024 ")); + + test::sprintf(buffer, "%-20i", 1024); + REQUIRE(!strcmp(buffer, "1024 ")); + + test::sprintf(buffer, "%-20i", -1024); + REQUIRE(!strcmp(buffer, "-1024 ")); + + test::sprintf(buffer, "%-20u", 1024); + REQUIRE(!strcmp(buffer, "1024 ")); + + test::sprintf(buffer, "%-20.4f", 1024.1234); + REQUIRE(!strcmp(buffer, "1024.1234 ")); + + test::sprintf(buffer, "%-20u", 4294966272U); + REQUIRE(!strcmp(buffer, "4294966272 ")); + + test::sprintf(buffer, "%-20o", 511); + REQUIRE(!strcmp(buffer, "777 ")); + + test::sprintf(buffer, "%-20o", 4294966785U); + REQUIRE(!strcmp(buffer, "37777777001 ")); + + test::sprintf(buffer, "%-20x", 305441741); + REQUIRE(!strcmp(buffer, "1234abcd ")); + + test::sprintf(buffer, "%-20x", 3989525555U); + REQUIRE(!strcmp(buffer, "edcb5433 ")); + + test::sprintf(buffer, "%-20X", 305441741); + REQUIRE(!strcmp(buffer, "1234ABCD ")); + + test::sprintf(buffer, "%-20X", 3989525555U); + REQUIRE(!strcmp(buffer, "EDCB5433 ")); + + test::sprintf(buffer, "%-20c", 'x'); + REQUIRE(!strcmp(buffer, "x ")); + + test::sprintf(buffer, "|%5d| |%-2d| |%5d|", 9, 9, 9); + REQUIRE(!strcmp(buffer, "| 9| |9 | | 9|")); + + test::sprintf(buffer, "|%5d| |%-2d| |%5d|", 10, 10, 10); + REQUIRE(!strcmp(buffer, "| 10| |10| | 10|")); + + test::sprintf(buffer, "|%5d| |%-12d| |%5d|", 9, 9, 9); + REQUIRE(!strcmp(buffer, "| 9| |9 | | 9|")); + + test::sprintf(buffer, "|%5d| |%-12d| |%5d|", 10, 10, 10); + REQUIRE(!strcmp(buffer, "| 10| |10 | | 10|")); +} + + +TEST_CASE("width 0-20", "[]" ) { + char buffer[100]; + + test::sprintf(buffer, "%0-20s", "Hello"); + REQUIRE(!strcmp(buffer, "Hello ")); + + test::sprintf(buffer, "%0-20d", 1024); + REQUIRE(!strcmp(buffer, "1024 ")); + + test::sprintf(buffer, "%0-20d", -1024); + REQUIRE(!strcmp(buffer, "-1024 ")); + + test::sprintf(buffer, "%0-20i", 1024); + REQUIRE(!strcmp(buffer, "1024 ")); + + test::sprintf(buffer, "%0-20i", -1024); + REQUIRE(!strcmp(buffer, "-1024 ")); + + test::sprintf(buffer, "%0-20u", 1024); + REQUIRE(!strcmp(buffer, "1024 ")); + + test::sprintf(buffer, "%0-20u", 4294966272U); + REQUIRE(!strcmp(buffer, "4294966272 ")); + + test::sprintf(buffer, "%0-20o", 511); + REQUIRE(!strcmp(buffer, "777 ")); + + test::sprintf(buffer, "%0-20o", 4294966785U); + REQUIRE(!strcmp(buffer, "37777777001 ")); + + test::sprintf(buffer, "%0-20x", 305441741); + REQUIRE(!strcmp(buffer, "1234abcd ")); + + test::sprintf(buffer, "%0-20x", 3989525555U); + REQUIRE(!strcmp(buffer, "edcb5433 ")); + + test::sprintf(buffer, "%0-20X", 305441741); + REQUIRE(!strcmp(buffer, "1234ABCD ")); + + test::sprintf(buffer, "%0-20X", 3989525555U); + REQUIRE(!strcmp(buffer, "EDCB5433 ")); + + test::sprintf(buffer, "%0-20c", 'x'); + REQUIRE(!strcmp(buffer, "x ")); +} + + +TEST_CASE("padding 20", "[]" ) { + char buffer[100]; + + test::sprintf(buffer, "%020d", 1024); + REQUIRE(!strcmp(buffer, "00000000000000001024")); + + test::sprintf(buffer, "%020d", -1024); + REQUIRE(!strcmp(buffer, "-0000000000000001024")); + + test::sprintf(buffer, "%020i", 1024); + REQUIRE(!strcmp(buffer, "00000000000000001024")); + + test::sprintf(buffer, "%020i", -1024); + REQUIRE(!strcmp(buffer, "-0000000000000001024")); + + test::sprintf(buffer, "%020u", 1024); + REQUIRE(!strcmp(buffer, "00000000000000001024")); + + test::sprintf(buffer, "%020u", 4294966272U); + REQUIRE(!strcmp(buffer, "00000000004294966272")); + + test::sprintf(buffer, "%020o", 511); + REQUIRE(!strcmp(buffer, "00000000000000000777")); + + test::sprintf(buffer, "%020o", 4294966785U); + REQUIRE(!strcmp(buffer, "00000000037777777001")); + + test::sprintf(buffer, "%020x", 305441741); + REQUIRE(!strcmp(buffer, "0000000000001234abcd")); + + test::sprintf(buffer, "%020x", 3989525555U); + REQUIRE(!strcmp(buffer, "000000000000edcb5433")); + + test::sprintf(buffer, "%020X", 305441741); + REQUIRE(!strcmp(buffer, "0000000000001234ABCD")); + + test::sprintf(buffer, "%020X", 3989525555U); + REQUIRE(!strcmp(buffer, "000000000000EDCB5433")); +} + + +TEST_CASE("padding .20", "[]" ) { + char buffer[100]; + + test::sprintf(buffer, "%.20d", 1024); + REQUIRE(!strcmp(buffer, "00000000000000001024")); + + test::sprintf(buffer, "%.20d", -1024); + REQUIRE(!strcmp(buffer, "-00000000000000001024")); + + test::sprintf(buffer, "%.20i", 1024); + REQUIRE(!strcmp(buffer, "00000000000000001024")); + + test::sprintf(buffer, "%.20i", -1024); + REQUIRE(!strcmp(buffer, "-00000000000000001024")); + + test::sprintf(buffer, "%.20u", 1024); + REQUIRE(!strcmp(buffer, "00000000000000001024")); + + test::sprintf(buffer, "%.20u", 4294966272U); + REQUIRE(!strcmp(buffer, "00000000004294966272")); + + test::sprintf(buffer, "%.20o", 511); + REQUIRE(!strcmp(buffer, "00000000000000000777")); + + test::sprintf(buffer, "%.20o", 4294966785U); + REQUIRE(!strcmp(buffer, "00000000037777777001")); + + test::sprintf(buffer, "%.20x", 305441741); + REQUIRE(!strcmp(buffer, "0000000000001234abcd")); + + test::sprintf(buffer, "%.20x", 3989525555U); + REQUIRE(!strcmp(buffer, "000000000000edcb5433")); + + test::sprintf(buffer, "%.20X", 305441741); + REQUIRE(!strcmp(buffer, "0000000000001234ABCD")); + + test::sprintf(buffer, "%.20X", 3989525555U); + REQUIRE(!strcmp(buffer, "000000000000EDCB5433")); +} + + +TEST_CASE("padding #020", "[]" ) { + char buffer[100]; + + test::sprintf(buffer, "%#020d", 1024); + REQUIRE(!strcmp(buffer, "00000000000000001024")); + + test::sprintf(buffer, "%#020d", -1024); + REQUIRE(!strcmp(buffer, "-0000000000000001024")); + + test::sprintf(buffer, "%#020i", 1024); + REQUIRE(!strcmp(buffer, "00000000000000001024")); + + test::sprintf(buffer, "%#020i", -1024); + REQUIRE(!strcmp(buffer, "-0000000000000001024")); + + test::sprintf(buffer, "%#020u", 1024); + REQUIRE(!strcmp(buffer, "00000000000000001024")); + + test::sprintf(buffer, "%#020u", 4294966272U); + REQUIRE(!strcmp(buffer, "00000000004294966272")); + + test::sprintf(buffer, "%#020o", 511); + REQUIRE(!strcmp(buffer, "00000000000000000777")); + + test::sprintf(buffer, "%#020o", 4294966785U); + REQUIRE(!strcmp(buffer, "00000000037777777001")); + + test::sprintf(buffer, "%#020x", 305441741); + REQUIRE(!strcmp(buffer, "0x00000000001234abcd")); + + test::sprintf(buffer, "%#020x", 3989525555U); + REQUIRE(!strcmp(buffer, "0x0000000000edcb5433")); + + test::sprintf(buffer, "%#020X", 305441741); + REQUIRE(!strcmp(buffer, "0X00000000001234ABCD")); + + test::sprintf(buffer, "%#020X", 3989525555U); + REQUIRE(!strcmp(buffer, "0X0000000000EDCB5433")); +} + + +TEST_CASE("padding #20", "[]" ) { + char buffer[100]; + + test::sprintf(buffer, "%#20d", 1024); + REQUIRE(!strcmp(buffer, " 1024")); + + test::sprintf(buffer, "%#20d", -1024); + REQUIRE(!strcmp(buffer, " -1024")); + + test::sprintf(buffer, "%#20i", 1024); + REQUIRE(!strcmp(buffer, " 1024")); + + test::sprintf(buffer, "%#20i", -1024); + REQUIRE(!strcmp(buffer, " -1024")); + + test::sprintf(buffer, "%#20u", 1024); + REQUIRE(!strcmp(buffer, " 1024")); + + test::sprintf(buffer, "%#20u", 4294966272U); + REQUIRE(!strcmp(buffer, " 4294966272")); + + test::sprintf(buffer, "%#20o", 511); + REQUIRE(!strcmp(buffer, " 0777")); + + test::sprintf(buffer, "%#20o", 4294966785U); + REQUIRE(!strcmp(buffer, " 037777777001")); + + test::sprintf(buffer, "%#20x", 305441741); + REQUIRE(!strcmp(buffer, " 0x1234abcd")); + + test::sprintf(buffer, "%#20x", 3989525555U); + REQUIRE(!strcmp(buffer, " 0xedcb5433")); + + test::sprintf(buffer, "%#20X", 305441741); + REQUIRE(!strcmp(buffer, " 0X1234ABCD")); + + test::sprintf(buffer, "%#20X", 3989525555U); + REQUIRE(!strcmp(buffer, " 0XEDCB5433")); +} + + +TEST_CASE("padding 20.5", "[]" ) { + char buffer[100]; + + test::sprintf(buffer, "%20.5d", 1024); + REQUIRE(!strcmp(buffer, " 01024")); + + test::sprintf(buffer, "%20.5d", -1024); + REQUIRE(!strcmp(buffer, " -01024")); + + test::sprintf(buffer, "%20.5i", 1024); + REQUIRE(!strcmp(buffer, " 01024")); + + test::sprintf(buffer, "%20.5i", -1024); + REQUIRE(!strcmp(buffer, " -01024")); + + test::sprintf(buffer, "%20.5u", 1024); + REQUIRE(!strcmp(buffer, " 01024")); + + test::sprintf(buffer, "%20.5u", 4294966272U); + REQUIRE(!strcmp(buffer, " 4294966272")); + + test::sprintf(buffer, "%20.5o", 511); + REQUIRE(!strcmp(buffer, " 00777")); + + test::sprintf(buffer, "%20.5o", 4294966785U); + REQUIRE(!strcmp(buffer, " 37777777001")); + + test::sprintf(buffer, "%20.5x", 305441741); + REQUIRE(!strcmp(buffer, " 1234abcd")); + + test::sprintf(buffer, "%20.10x", 3989525555U); + REQUIRE(!strcmp(buffer, " 00edcb5433")); + + test::sprintf(buffer, "%20.5X", 305441741); + REQUIRE(!strcmp(buffer, " 1234ABCD")); + + test::sprintf(buffer, "%20.10X", 3989525555U); + REQUIRE(!strcmp(buffer, " 00EDCB5433")); +} + + +TEST_CASE("padding neg numbers", "[]" ) { + char buffer[100]; + + // space padding + test::sprintf(buffer, "% 1d", -5); + REQUIRE(!strcmp(buffer, "-5")); + + test::sprintf(buffer, "% 2d", -5); + REQUIRE(!strcmp(buffer, "-5")); + + test::sprintf(buffer, "% 3d", -5); + REQUIRE(!strcmp(buffer, " -5")); + + test::sprintf(buffer, "% 4d", -5); + REQUIRE(!strcmp(buffer, " -5")); + + // zero padding + test::sprintf(buffer, "%01d", -5); + REQUIRE(!strcmp(buffer, "-5")); + + test::sprintf(buffer, "%02d", -5); + REQUIRE(!strcmp(buffer, "-5")); + + test::sprintf(buffer, "%03d", -5); + REQUIRE(!strcmp(buffer, "-05")); + + test::sprintf(buffer, "%04d", -5); + REQUIRE(!strcmp(buffer, "-005")); +} + + +TEST_CASE("float padding neg numbers", "[]" ) { + char buffer[100]; + + // space padding + test::sprintf(buffer, "% 3.1f", -5.); + REQUIRE(!strcmp(buffer, "-5.0")); + + test::sprintf(buffer, "% 4.1f", -5.); + REQUIRE(!strcmp(buffer, "-5.0")); + + test::sprintf(buffer, "% 5.1f", -5.); + REQUIRE(!strcmp(buffer, " -5.0")); + +#ifndef PRINTF_DISABLE_SUPPORT_EXPONENTIAL + test::sprintf(buffer, "% 6.1g", -5.); + REQUIRE(!strcmp(buffer, " -5")); + + test::sprintf(buffer, "% 6.1e", -5.); + REQUIRE(!strcmp(buffer, "-5.0e+00")); + + test::sprintf(buffer, "% 10.1e", -5.); + REQUIRE(!strcmp(buffer, " -5.0e+00")); +#endif + + // zero padding + test::sprintf(buffer, "%03.1f", -5.); + REQUIRE(!strcmp(buffer, "-5.0")); + + test::sprintf(buffer, "%04.1f", -5.); + REQUIRE(!strcmp(buffer, "-5.0")); + + test::sprintf(buffer, "%05.1f", -5.); + REQUIRE(!strcmp(buffer, "-05.0")); + + // zero padding no decimal point + test::sprintf(buffer, "%01.0f", -5.); + REQUIRE(!strcmp(buffer, "-5")); + + test::sprintf(buffer, "%02.0f", -5.); + REQUIRE(!strcmp(buffer, "-5")); + + test::sprintf(buffer, "%03.0f", -5.); + REQUIRE(!strcmp(buffer, "-05")); + +#ifndef PRINTF_DISABLE_SUPPORT_EXPONENTIAL + test::sprintf(buffer, "%010.1e", -5.); + REQUIRE(!strcmp(buffer, "-005.0e+00")); + + test::sprintf(buffer, "%07.0E", -5.); + REQUIRE(!strcmp(buffer, "-05E+00")); + + test::sprintf(buffer, "%03.0g", -5.); + REQUIRE(!strcmp(buffer, "-05")); +#endif +} + +TEST_CASE("length", "[]" ) { + char buffer[100]; + + test::sprintf(buffer, "%.0s", "Hello testing"); + REQUIRE(!strcmp(buffer, "")); + + test::sprintf(buffer, "%20.0s", "Hello testing"); + REQUIRE(!strcmp(buffer, " ")); + + test::sprintf(buffer, "%.s", "Hello testing"); + REQUIRE(!strcmp(buffer, "")); + + test::sprintf(buffer, "%20.s", "Hello testing"); + REQUIRE(!strcmp(buffer, " ")); + + test::sprintf(buffer, "%20.0d", 1024); + REQUIRE(!strcmp(buffer, " 1024")); + + test::sprintf(buffer, "%20.0d", -1024); + REQUIRE(!strcmp(buffer, " -1024")); + + test::sprintf(buffer, "%20.d", 0); + REQUIRE(!strcmp(buffer, " ")); + + test::sprintf(buffer, "%20.0i", 1024); + REQUIRE(!strcmp(buffer, " 1024")); + + test::sprintf(buffer, "%20.i", -1024); + REQUIRE(!strcmp(buffer, " -1024")); + + test::sprintf(buffer, "%20.i", 0); + REQUIRE(!strcmp(buffer, " ")); + + test::sprintf(buffer, "%20.u", 1024); + REQUIRE(!strcmp(buffer, " 1024")); + + test::sprintf(buffer, "%20.0u", 4294966272U); + REQUIRE(!strcmp(buffer, " 4294966272")); + + test::sprintf(buffer, "%20.u", 0U); + REQUIRE(!strcmp(buffer, " ")); + + test::sprintf(buffer, "%20.o", 511); + REQUIRE(!strcmp(buffer, " 777")); + + test::sprintf(buffer, "%20.0o", 4294966785U); + REQUIRE(!strcmp(buffer, " 37777777001")); + + test::sprintf(buffer, "%20.o", 0U); + REQUIRE(!strcmp(buffer, " ")); + + test::sprintf(buffer, "%20.x", 305441741); + REQUIRE(!strcmp(buffer, " 1234abcd")); + + test::sprintf(buffer, "%50.x", 305441741); + REQUIRE(!strcmp(buffer, " 1234abcd")); + + test::sprintf(buffer, "%50.x%10.u", 305441741, 12345); + REQUIRE(!strcmp(buffer, " 1234abcd 12345")); + + test::sprintf(buffer, "%20.0x", 3989525555U); + REQUIRE(!strcmp(buffer, " edcb5433")); + + test::sprintf(buffer, "%20.x", 0U); + REQUIRE(!strcmp(buffer, " ")); + + test::sprintf(buffer, "%20.X", 305441741); + REQUIRE(!strcmp(buffer, " 1234ABCD")); + + test::sprintf(buffer, "%20.0X", 3989525555U); + REQUIRE(!strcmp(buffer, " EDCB5433")); + + test::sprintf(buffer, "%20.X", 0U); + REQUIRE(!strcmp(buffer, " ")); + + test::sprintf(buffer, "%02.0u", 0U); + REQUIRE(!strcmp(buffer, " ")); + + test::sprintf(buffer, "%02.0d", 0); + REQUIRE(!strcmp(buffer, " ")); +} + + +TEST_CASE("float", "[]" ) { + char buffer[100]; + + // test special-case floats using math.h macros + test::sprintf(buffer, "%8f", NAN); + REQUIRE(!strcmp(buffer, " nan")); + + test::sprintf(buffer, "%8f", INFINITY); + REQUIRE(!strcmp(buffer, " inf")); + + test::sprintf(buffer, "%-8f", -INFINITY); + REQUIRE(!strcmp(buffer, "-inf ")); + +#ifndef PRINTF_DISABLE_SUPPORT_EXPONENTIAL + test::sprintf(buffer, "%+8e", INFINITY); + REQUIRE(!strcmp(buffer, " +inf")); +#endif + + test::sprintf(buffer, "%.4f", 3.1415354); + REQUIRE(!strcmp(buffer, "3.1415")); + + test::sprintf(buffer, "%.3f", 30343.1415354); + REQUIRE(!strcmp(buffer, "30343.142")); + + test::sprintf(buffer, "%.0f", 34.1415354); + REQUIRE(!strcmp(buffer, "34")); + + test::sprintf(buffer, "%.0f", 1.3); + REQUIRE(!strcmp(buffer, "1")); + + test::sprintf(buffer, "%.0f", 1.55); + REQUIRE(!strcmp(buffer, "2")); + + test::sprintf(buffer, "%.1f", 1.64); + REQUIRE(!strcmp(buffer, "1.6")); + + test::sprintf(buffer, "%.2f", 42.8952); + REQUIRE(!strcmp(buffer, "42.90")); + + test::sprintf(buffer, "%.9f", 42.8952); + REQUIRE(!strcmp(buffer, "42.895200000")); + + test::sprintf(buffer, "%.10f", 42.895223); + REQUIRE(!strcmp(buffer, "42.8952230000")); + + // this testcase checks, that the precision is truncated to 9 digits. + // a perfect working float should return the whole number + test::sprintf(buffer, "%.12f", 42.89522312345678); + REQUIRE(!strcmp(buffer, "42.895223123000")); + + // this testcase checks, that the precision is truncated AND rounded to 9 digits. + // a perfect working float should return the whole number + test::sprintf(buffer, "%.12f", 42.89522387654321); + REQUIRE(!strcmp(buffer, "42.895223877000")); + + test::sprintf(buffer, "%6.2f", 42.8952); + REQUIRE(!strcmp(buffer, " 42.90")); + + test::sprintf(buffer, "%+6.2f", 42.8952); + REQUIRE(!strcmp(buffer, "+42.90")); + + test::sprintf(buffer, "%+5.1f", 42.9252); + REQUIRE(!strcmp(buffer, "+42.9")); + + test::sprintf(buffer, "%f", 42.5); + REQUIRE(!strcmp(buffer, "42.500000")); + + test::sprintf(buffer, "%.1f", 42.5); + REQUIRE(!strcmp(buffer, "42.5")); + + test::sprintf(buffer, "%f", 42167.0); + REQUIRE(!strcmp(buffer, "42167.000000")); + + test::sprintf(buffer, "%.9f", -12345.987654321); + REQUIRE(!strcmp(buffer, "-12345.987654321")); + + test::sprintf(buffer, "%.1f", 3.999); + REQUIRE(!strcmp(buffer, "4.0")); + + test::sprintf(buffer, "%.0f", 3.5); + REQUIRE(!strcmp(buffer, "4")); + + test::sprintf(buffer, "%.0f", 4.5); + REQUIRE(!strcmp(buffer, "4")); + + test::sprintf(buffer, "%.0f", 3.49); + REQUIRE(!strcmp(buffer, "3")); + + test::sprintf(buffer, "%.1f", 3.49); + REQUIRE(!strcmp(buffer, "3.5")); + + test::sprintf(buffer, "a%-5.1f", 0.5); + REQUIRE(!strcmp(buffer, "a0.5 ")); + + test::sprintf(buffer, "a%-5.1fend", 0.5); + REQUIRE(!strcmp(buffer, "a0.5 end")); + +#ifndef PRINTF_DISABLE_SUPPORT_EXPONENTIAL + test::sprintf(buffer, "%G", 12345.678); + REQUIRE(!strcmp(buffer, "12345.7")); + + test::sprintf(buffer, "%.7G", 12345.678); + REQUIRE(!strcmp(buffer, "12345.68")); + + test::sprintf(buffer, "%.5G", 123456789.); + REQUIRE(!strcmp(buffer, "1.2346E+08")); + + test::sprintf(buffer, "%.6G", 12345.); + REQUIRE(!strcmp(buffer, "12345.0")); + + test::sprintf(buffer, "%+12.4g", 123456789.); + REQUIRE(!strcmp(buffer, " +1.235e+08")); + + test::sprintf(buffer, "%.2G", 0.001234); + REQUIRE(!strcmp(buffer, "0.0012")); + + test::sprintf(buffer, "%+10.4G", 0.001234); + REQUIRE(!strcmp(buffer, " +0.001234")); + + test::sprintf(buffer, "%+012.4g", 0.00001234); + REQUIRE(!strcmp(buffer, "+001.234e-05")); + + test::sprintf(buffer, "%.3g", -1.2345e-308); + REQUIRE(!strcmp(buffer, "-1.23e-308")); + + test::sprintf(buffer, "%+.3E", 1.23e+308); + REQUIRE(!strcmp(buffer, "+1.230E+308")); +#endif + + // out of range for float: should switch to exp notation if supported, else empty + test::sprintf(buffer, "%.1f", 1E20); +#ifndef PRINTF_DISABLE_SUPPORT_EXPONENTIAL + REQUIRE(!strcmp(buffer, "1.0e+20")); +#else + REQUIRE(!strcmp(buffer, "")); +#endif + + // brute force float + bool fail = false; + std::stringstream str; + str.precision(5); + for (float i = -100000; i < 100000; i += 1) { + test::sprintf(buffer, "%.5f", i / 10000); + str.str(""); + str << std::fixed << i / 10000; + fail = fail || !!strcmp(buffer, str.str().c_str()); + } + REQUIRE(!fail); + + +#ifndef PRINTF_DISABLE_SUPPORT_EXPONENTIAL + // brute force exp + str.setf(std::ios::scientific, std::ios::floatfield); + for (float i = -1e20; i < 1e20; i += 1e15) { + test::sprintf(buffer, "%.5f", i); + str.str(""); + str << i; + fail = fail || !!strcmp(buffer, str.str().c_str()); + } + REQUIRE(!fail); +#endif +} + + +TEST_CASE("types", "[]" ) { + char buffer[100]; + + test::sprintf(buffer, "%i", 0); + REQUIRE(!strcmp(buffer, "0")); + + test::sprintf(buffer, "%i", 1234); + REQUIRE(!strcmp(buffer, "1234")); + + test::sprintf(buffer, "%i", 32767); + REQUIRE(!strcmp(buffer, "32767")); + + test::sprintf(buffer, "%i", -32767); + REQUIRE(!strcmp(buffer, "-32767")); + + test::sprintf(buffer, "%li", 30L); + REQUIRE(!strcmp(buffer, "30")); + + test::sprintf(buffer, "%li", -2147483647L); + REQUIRE(!strcmp(buffer, "-2147483647")); + + test::sprintf(buffer, "%li", 2147483647L); + REQUIRE(!strcmp(buffer, "2147483647")); + + test::sprintf(buffer, "%lli", 30LL); + REQUIRE(!strcmp(buffer, "30")); + + test::sprintf(buffer, "%lli", -9223372036854775807LL); + REQUIRE(!strcmp(buffer, "-9223372036854775807")); + + test::sprintf(buffer, "%lli", 9223372036854775807LL); + REQUIRE(!strcmp(buffer, "9223372036854775807")); + + test::sprintf(buffer, "%lu", 100000L); + REQUIRE(!strcmp(buffer, "100000")); + + test::sprintf(buffer, "%lu", 0xFFFFFFFFL); + REQUIRE(!strcmp(buffer, "4294967295")); + + test::sprintf(buffer, "%llu", 281474976710656LLU); + REQUIRE(!strcmp(buffer, "281474976710656")); + + test::sprintf(buffer, "%llu", 18446744073709551615LLU); + REQUIRE(!strcmp(buffer, "18446744073709551615")); + + test::sprintf(buffer, "%zu", 2147483647UL); + REQUIRE(!strcmp(buffer, "2147483647")); + + test::sprintf(buffer, "%zd", 2147483647UL); + REQUIRE(!strcmp(buffer, "2147483647")); + + if (sizeof(size_t) == sizeof(long)) { + test::sprintf(buffer, "%zi", -2147483647L); + REQUIRE(!strcmp(buffer, "-2147483647")); + } + else { + test::sprintf(buffer, "%zi", -2147483647LL); + REQUIRE(!strcmp(buffer, "-2147483647")); + } + + test::sprintf(buffer, "%b", 60000); + REQUIRE(!strcmp(buffer, "1110101001100000")); + + test::sprintf(buffer, "%lb", 12345678L); + REQUIRE(!strcmp(buffer, "101111000110000101001110")); + + test::sprintf(buffer, "%o", 60000); + REQUIRE(!strcmp(buffer, "165140")); + + test::sprintf(buffer, "%lo", 12345678L); + REQUIRE(!strcmp(buffer, "57060516")); + + test::sprintf(buffer, "%lx", 0x12345678L); + REQUIRE(!strcmp(buffer, "12345678")); + + test::sprintf(buffer, "%llx", 0x1234567891234567LLU); + REQUIRE(!strcmp(buffer, "1234567891234567")); + + test::sprintf(buffer, "%lx", 0xabcdefabL); + REQUIRE(!strcmp(buffer, "abcdefab")); + + test::sprintf(buffer, "%lX", 0xabcdefabL); + REQUIRE(!strcmp(buffer, "ABCDEFAB")); + + test::sprintf(buffer, "%c", 'v'); + REQUIRE(!strcmp(buffer, "v")); + + test::sprintf(buffer, "%cv", 'w'); + REQUIRE(!strcmp(buffer, "wv")); + + test::sprintf(buffer, "%s", "A Test"); + REQUIRE(!strcmp(buffer, "A Test")); + + test::sprintf(buffer, "%hhu", 0xFFFFUL); + REQUIRE(!strcmp(buffer, "255")); + + test::sprintf(buffer, "%hu", 0x123456UL); + REQUIRE(!strcmp(buffer, "13398")); + + test::sprintf(buffer, "%s%hhi %hu", "Test", 10000, 0xFFFFFFFF); + REQUIRE(!strcmp(buffer, "Test16 65535")); + + test::sprintf(buffer, "%tx", &buffer[10] - &buffer[0]); + REQUIRE(!strcmp(buffer, "a")); + +// TBD + if (sizeof(intmax_t) == sizeof(long)) { + test::sprintf(buffer, "%ji", -2147483647L); + REQUIRE(!strcmp(buffer, "-2147483647")); + } + else { + test::sprintf(buffer, "%ji", -2147483647LL); + REQUIRE(!strcmp(buffer, "-2147483647")); + } +} + + +TEST_CASE("pointer", "[]" ) { + char buffer[100]; + + test::sprintf(buffer, "%p", (void*)0x1234U); + if (sizeof(void*) == 4U) { + REQUIRE(!strcmp(buffer, "00001234")); + } + else { + REQUIRE(!strcmp(buffer, "0000000000001234")); + } + + test::sprintf(buffer, "%p", (void*)0x12345678U); + if (sizeof(void*) == 4U) { + REQUIRE(!strcmp(buffer, "12345678")); + } + else { + REQUIRE(!strcmp(buffer, "0000000012345678")); + } + + test::sprintf(buffer, "%p-%p", (void*)0x12345678U, (void*)0x7EDCBA98U); + if (sizeof(void*) == 4U) { + REQUIRE(!strcmp(buffer, "12345678-7EDCBA98")); + } + else { + REQUIRE(!strcmp(buffer, "0000000012345678-000000007EDCBA98")); + } + + if (sizeof(uintptr_t) == sizeof(uint64_t)) { + test::sprintf(buffer, "%p", (void*)(uintptr_t)0xFFFFFFFFU); + REQUIRE(!strcmp(buffer, "00000000FFFFFFFF")); + } + else { + test::sprintf(buffer, "%p", (void*)(uintptr_t)0xFFFFFFFFU); + REQUIRE(!strcmp(buffer, "FFFFFFFF")); + } +} + + +TEST_CASE("unknown flag", "[]" ) { + char buffer[100]; + + test::sprintf(buffer, "%kmarco", 42, 37); + REQUIRE(!strcmp(buffer, "kmarco")); +} + + +TEST_CASE("string length", "[]" ) { + char buffer[100]; + + test::sprintf(buffer, "%.4s", "This is a test"); + REQUIRE(!strcmp(buffer, "This")); + + test::sprintf(buffer, "%.4s", "test"); + REQUIRE(!strcmp(buffer, "test")); + + test::sprintf(buffer, "%.7s", "123"); + REQUIRE(!strcmp(buffer, "123")); + + test::sprintf(buffer, "%.7s", ""); + REQUIRE(!strcmp(buffer, "")); + + test::sprintf(buffer, "%.4s%.2s", "123456", "abcdef"); + REQUIRE(!strcmp(buffer, "1234ab")); + + test::sprintf(buffer, "%.4.2s", "123456"); + REQUIRE(!strcmp(buffer, ".2s")); + + test::sprintf(buffer, "%.*s", 3, "123456"); + REQUIRE(!strcmp(buffer, "123")); +} + + +TEST_CASE("buffer length", "[]" ) { + char buffer[100]; + int ret; + + ret = test::snprintf(nullptr, 10, "%s", "Test"); + REQUIRE(ret == 4); + ret = test::snprintf(nullptr, 0, "%s", "Test"); + REQUIRE(ret == 4); + + buffer[0] = (char)0xA5; + ret = test::snprintf(buffer, 0, "%s", "Test"); + REQUIRE(buffer[0] == (char)0xA5); + REQUIRE(ret == 4); + + buffer[0] = (char)0xCC; + test::snprintf(buffer, 1, "%s", "Test"); + REQUIRE(buffer[0] == '\0'); + + test::snprintf(buffer, 2, "%s", "Hello"); + REQUIRE(!strcmp(buffer, "H")); +} + + +TEST_CASE("ret value", "[]" ) { + char buffer[100] ; + int ret; + + ret = test::snprintf(buffer, 6, "0%s", "1234"); + REQUIRE(!strcmp(buffer, "01234")); + REQUIRE(ret == 5); + + ret = test::snprintf(buffer, 6, "0%s", "12345"); + REQUIRE(!strcmp(buffer, "01234")); + REQUIRE(ret == 6); // '5' is truncated + + ret = test::snprintf(buffer, 6, "0%s", "1234567"); + REQUIRE(!strcmp(buffer, "01234")); + REQUIRE(ret == 8); // '567' are truncated + + ret = test::snprintf(buffer, 10, "hello, world"); + REQUIRE(ret == 12); + + ret = test::snprintf(buffer, 3, "%d", 10000); + REQUIRE(ret == 5); + REQUIRE(strlen(buffer) == 2U); + REQUIRE(buffer[0] == '1'); + REQUIRE(buffer[1] == '0'); + REQUIRE(buffer[2] == '\0'); +} + + +TEST_CASE("misc", "[]" ) { + char buffer[100]; + + test::sprintf(buffer, "%u%u%ctest%d %s", 5, 3000, 'a', -20, "bit"); + REQUIRE(!strcmp(buffer, "53000atest-20 bit")); + + test::sprintf(buffer, "%.*f", 2, 0.33333333); + REQUIRE(!strcmp(buffer, "0.33")); + + test::sprintf(buffer, "%.*d", -1, 1); + REQUIRE(!strcmp(buffer, "1")); + + test::sprintf(buffer, "%.3s", "foobar"); + REQUIRE(!strcmp(buffer, "foo")); + + test::sprintf(buffer, "% .0d", 0); + REQUIRE(!strcmp(buffer, " ")); + + test::sprintf(buffer, "%10.5d", 4); + REQUIRE(!strcmp(buffer, " 00004")); + + test::sprintf(buffer, "%*sx", -3, "hi"); + REQUIRE(!strcmp(buffer, "hi x")); + +#ifndef PRINTF_DISABLE_SUPPORT_EXPONENTIAL + test::sprintf(buffer, "%.*g", 2, 0.33333333); + REQUIRE(!strcmp(buffer, "0.33")); + + test::sprintf(buffer, "%.*e", 2, 0.33333333); + REQUIRE(!strcmp(buffer, "3.33e-01")); +#endif +} diff --git a/scripts/build_firmware_evb2.sh b/scripts/build_firmware_evb2.sh new file mode 100755 index 000000000..bdbe263c6 --- /dev/null +++ b/scripts/build_firmware_evb2.sh @@ -0,0 +1,66 @@ +#!/usr/bin/env bash +set -o errexit +SCRIPT_DIR=$( cd -- "$( dirname -- "${BASH_SOURCE[0]}" )" &> /dev/null && pwd ) +pushd "$(dirname "$(realpath $0)")" > /dev/null + +BOLD="\x1b[1m" +GREEN="\x1b[32m" +BLUE="\x1b[34m" +RESET="\x1b[0m" + +DEBUG= + +for i in "$@"; do + case "$1" in + -c|--clean) + clean="true" + shift + ;; + -d|--debug) + DEBUG=GDB + shift + ;; + esac +done + +pushd "../EVB-2" > /dev/null + if [ -n "${clean}" ]; then + echo -e "\n\n=== Running make clean... ===" + make clean + else + echo -e "\n\n=== Running make... ===" + make -j`nproc` DEBUG=${DEBUG} + + set +o errexit + source $SCRIPT_DIR/lib/release_append_header_version.sh ../../EVB-2/Release/IS_EVB-2.hex ../../EVB-2/IS_EVB-2/src $1 + set -o errexit + fi + +popd > /dev/null + +commit="$(git rev-parse --short HEAD)" +branch="$(git symbolic-ref --short HEAD|| echo '(detached head)')" +version="$(git describe --tags)" + +# Because of `set -o errexit`, we will only get to this point if the build was successful. +# Print build information +echo -e "${RESET}" +echo -e "${BOLD}EVB-2 ${GREEN}Firmware build complete on ${BUILD_DATE_FORMAT} ${BUILD_TIME_FORMAT}${RESET}" + +echo -ne "${BOLD}${CYAN}Build options: ${RESET}" +if [ "${DEBUG}" == "GDB" ]; then + echo -ne "${BOLD}${RED}DEBUG${RESET} " +fi +if [ -n "${clean}" ]; then + echo -ne "${BOLD}CLEAN${RESET} " +fi +echo + +echo -ne "${BOLD}${BLUE}branch: ${RESET}${branch} " +echo -ne "${BOLD}${BLUE}commit: ${RESET}${commit} " +echo -e "${BOLD}${BLUE}version: ${RESET}${version}" +echo -ne "${BOLD}${GREEN}Firmware path: ${RESET}" +echo -e "${BOLD}"$(realpath ../EVB-2/obj/EVB-2.hex)"${RESET}" +echo + +popd > /dev/null diff --git a/scripts/clean_all.sh b/scripts/clean_all.sh index f985b13e5..fe2ba1608 100755 --- a/scripts/clean_all.sh +++ b/scripts/clean_all.sh @@ -24,6 +24,10 @@ build_footer $? clean_directory "SDK_Examples" ../ExampleProjects/build clean_directory "SDK_Unit_Tests" ../tests/build +build_header "EVB-2" +./build_firmware_evb2.sh --clean +build_footer $? + ############################################################################### # Summary diff --git a/src/DeviceLog.cpp b/src/DeviceLog.cpp index f73a4c73e..234424c19 100644 --- a/src/DeviceLog.cpp +++ b/src/DeviceLog.cpp @@ -37,7 +37,11 @@ cDeviceLog::cDeviceLog() { cDeviceLog::cDeviceLog(const ISDevice* dev) : device(dev) { if (dev == nullptr) +#if PLATFORM_IS_EMBEDDED + while(1){} +#else throw std::invalid_argument("cDeviceLog() must be passed a valid ISDevice instance."); +#endif m_devHdwId = ENCODE_DEV_INFO_TO_HDW_ID(dev->devInfo); m_devSerialNo = dev->devInfo.serialNumber; m_logStats.Clear(); @@ -243,6 +247,19 @@ bool cDeviceLog::OpenNextReadFile() string cDeviceLog::GetNewFileName(uint32_t serialNumber, uint32_t fileCount, const char* suffix) { +#if PLATFORM_IS_EMBEDDED + char filename[200]; + SNPRINTF(filename, sizeof(filename), "%s/%s%d_%s_%04d%s%s", + m_directory.c_str(), + IS_LOG_FILE_PREFIX, + (int)serialNumber, + m_timeStamp.c_str(), + (int)(fileCount % 10000), + (suffix == NULL || *suffix == 0 ? "" : (string("_") + suffix).c_str()), + LogFileExtention().c_str() + ); + return filename; +#else return utils::string_format("%s/%s%d_%s_%04d%s%s", m_directory.c_str(), IS_LOG_FILE_PREFIX, @@ -252,6 +269,7 @@ string cDeviceLog::GetNewFileName(uint32_t serialNumber, uint32_t fileCount, con (suffix == NULL || *suffix == 0 ? "" : (string("_") + suffix).c_str()), LogFileExtention().c_str() ); +#endif } ISDevice* cDeviceLog::Device() { diff --git a/src/ISBootloaderAPP.cpp b/src/ISBootloaderAPP.cpp index 6553ed593..7dd8b626a 100644 --- a/src/ISBootloaderAPP.cpp +++ b/src/ISBootloaderAPP.cpp @@ -51,6 +51,11 @@ eImageSignature devInfoToValidSignatures(dev_info_t *devInfo) valid_signatures |= IS_IMAGE_SIGN_UINS_3_16K | IS_IMAGE_SIGN_UINS_3_24K; valid_signatures |= IS_IMAGE_SIGN_ISB_SAMx70_16K | IS_IMAGE_SIGN_ISB_SAMx70_24K; } + else if (devInfo->hardwareType == IS_HARDWARE_TYPE_EVB && devInfo->hardwareVer[0] == 2) + { /** EVB-2 */ + valid_signatures |= IS_IMAGE_SIGN_EVB_2_16K | IS_IMAGE_SIGN_EVB_2_24K; + valid_signatures |= IS_IMAGE_SIGN_ISB_SAMx70_16K | IS_IMAGE_SIGN_ISB_SAMx70_24K; + } return (eImageSignature)valid_signatures; } @@ -63,7 +68,7 @@ eImageSignature cISBootloaderAPP::check_is_compatible() is_comm_instance_t comm; uint8_t buffer[2048]; is_comm_init(&comm, buffer, sizeof(buffer)); - int messageSize, n, i; + int n, i; // clear the Rx serial buffer n = is_comm_free(&comm); @@ -86,12 +91,6 @@ eImageSignature cISBootloaderAPP::check_is_compatible() return IS_IMAGE_SIGN_NONE; } } - messageSize = is_comm_get_data_to_buf(buffer, sizeof(buffer), &comm, DID_EVB_DEV_INFO, 0, 0, 0); - if (messageSize != serialPortWrite(m_port, buffer, messageSize)) - { - //serialPortClose(m_port); - return IS_IMAGE_SIGN_NONE; - } protocol_type_t ptype; n = is_comm_free(&comm); @@ -136,10 +135,25 @@ eImageSignature cISBootloaderAPP::check_is_compatible() { // IMX device Info dev_info_t devInfo; nmea_parse_info(devInfo, (const char*)comm.rxPkt.data.ptr, comm.rxPkt.data.size); - memcpy(m_app.uins_version, devInfo.hardwareVer, 4); - m_sn = devInfo.serialNumber; - valid_signatures = devInfoToValidSignatures(&devInfo); - return (eImageSignature)valid_signatures; + if (devInfo.hardwareType == IS_HARDWARE_TYPE_EVB) + { // EVB2 + memcpy(m_app.evb_version, devInfo.hardwareVer, 4); + if (m_isEVB) + { + valid_signatures = devInfoToValidSignatures(&devInfo); + return (eImageSignature)valid_signatures; + } + } + else + { // IMX + memcpy(m_app.uins_version, devInfo.hardwareVer, 4); + m_sn = devInfo.serialNumber; + if (!m_isEVB) + { + valid_signatures = devInfoToValidSignatures(&devInfo); + return (eImageSignature)valid_signatures; + } + } } break; } diff --git a/src/ISBootloaderBase.cpp b/src/ISBootloaderBase.cpp index c9a01f81b..5e4a5e9f2 100644 --- a/src/ISBootloaderBase.cpp +++ b/src/ISBootloaderBase.cpp @@ -191,7 +191,8 @@ is_operation_result cISBootloaderBase::mode_device_app uint32_t fw_EVB_2 = get_image_signature(filenames.fw_EVB_2.path) & (IS_IMAGE_SIGN_EVB_2_16K | IS_IMAGE_SIGN_EVB_2_24K); obj = new cISBootloaderAPP(updateProgress, verifyProgress, statusfn, handle); - + obj->m_isEVB = fw_EVB_2 != 0; + // Tell device to stop broadcasting serialPortWriteAscii(obj->m_port, "STPB", 4); diff --git a/src/ISBootloaderBase.h b/src/ISBootloaderBase.h index c3148487a..cdecbfb48 100644 --- a/src/ISBootloaderBase.h +++ b/src/ISBootloaderBase.h @@ -127,6 +127,7 @@ class cISBootloaderBase m_start_time_ms = 0; m_finished_flash = false; m_verify = false; + m_isEVB = false; if(m_update_callback == NULL) m_update_callback = dummy_update_callback; if(m_verify_callback == NULL) m_verify_callback = dummy_verify_callback; @@ -278,6 +279,7 @@ class cISBootloaderBase std::string m_filename; bool m_isISB; + bool m_isEVB; protected: void status_update(const char* info, eLogLevel level) diff --git a/src/ISComm.c b/src/ISComm.c index 55755096d..f4f6d3b0d 100644 --- a/src/ISComm.c +++ b/src/ISComm.c @@ -182,7 +182,7 @@ void is_comm_init(is_comm_instance_t* c, uint8_t *buffer, int bufferSize) c->rxErrorState = 1; } -void setParserStart(is_comm_instance_t* c, pFnProcessPkt processPkt) +static void setParserStart(is_comm_instance_t* c, pFnProcessPkt processPkt) { is_comm_parser_t *p = &(c->parser); p->state = 1; diff --git a/src/ISConstants.h b/src/ISConstants.h index 5981b8269..26daaf8dd 100644 --- a/src/ISConstants.h +++ b/src/ISConstants.h @@ -134,7 +134,7 @@ extern "C" { #define FREE(m) free(m) #endif -#if __ZEPHYR__ +#ifdef __ZEPHYR__ // #define SNPRINTF snprintfcb #define SNPRINTF snprintf #define VSNPRINTF vsnprintf @@ -178,7 +178,7 @@ extern "C" { #endif #endif // defined(_MSC_VER) -#if __ZEPHYR__ +#ifdef __ZEPHYR__ #include #define BEGIN_CRITICAL_SECTION irq_lock(); #define END_CRITICAL_SECTION irq_unlock(0); diff --git a/src/ISFileManager.cpp b/src/ISFileManager.cpp index 4ef634fa6..40a7c0d39 100644 --- a/src/ISFileManager.cpp +++ b/src/ISFileManager.cpp @@ -462,7 +462,7 @@ namespace ISFileManager { std::string CurrentWorkingDirectory() { char curdir[256] = { 0 }; - if (_GETCWD(curdir, sizeof(curdir)) != nullptr) + if (_GETCWD(curdir, sizeof(curdir)) != 0) { return std::string(curdir); } diff --git a/src/ISUtilities.cpp b/src/ISUtilities.cpp index bf8d7ed61..f9f00b79a 100644 --- a/src/ISUtilities.cpp +++ b/src/ISUtilities.cpp @@ -26,7 +26,7 @@ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLI #endif #if PLATFORM_IS_EMBEDDED - #include "drivers/d_time.h" + #include "d_time.h" #elif PLATFORM_IS_WINDOWS #include #include diff --git a/src/InertialSense.cpp b/src/InertialSense.cpp index b19a3e4cf..4b6a8d954 100644 --- a/src/InertialSense.cpp +++ b/src/InertialSense.cpp @@ -971,11 +971,20 @@ void InertialSense::ProcessRxNmea(int pHandle, const uint8_t* msg, int msgSize) ISDevice& device = m_comManagerState.devices[pHandle]; - switch (getNmeaMsgId(msg, msgSize)) - { + switch (getNmeaMsgId(msg, msgSize)) + { case NMEA_MSG_ID_INFO: - { // IMX device Info - nmea_parse_info(device.devInfo, (const char*)msg, msgSize); + { // Device Info + dev_info_t info; + nmea_parse_info(info, (const char*)msg, msgSize); + if (info.hardwareType == IS_HARDWARE_TYPE_EVB) + { + device.evbDevInfo = info; + } + else + { + device.devInfo = info; + } } break; } diff --git a/src/com_manager.c b/src/com_manager.c index 4737beb89..e2382a072 100644 --- a/src/com_manager.c +++ b/src/com_manager.c @@ -181,7 +181,7 @@ int initComManagerInstanceInternal com_manager_port_t *port = &(cmInstance->ports[i]); is_comm_init(&(port->comm), port->comm_buffer, MEMBERSIZE(com_manager_port_t, comm_buffer)); -#if ENABLE_PACKET_CONTINUATION +#ifdef ENABLE_PACKET_CONTINUATION // Packet data continuation memset(&(port->con), 0, MEMBERSIZE(com_manager_port_t,con)); #endif @@ -620,7 +620,7 @@ int processBinaryRxPacket(com_manager_t* cmInstance, int pHandle, packet_t *pkt) data.hdr.size = _MIN(data.hdr.size, (uint8_t)size); } -#if ENABLE_PACKET_CONTINUATION +#ifdef ENABLE_PACKET_CONTINUATION // Consolidate datasets that were broken-up across multiple packets p_data_t* con = &cmInstance->ports[pHandle].con; @@ -685,7 +685,7 @@ int processBinaryRxPacket(com_manager_t* cmInstance, int pHandle, packet_t *pkt) cmInstance->pstRxFnc(pHandle, &data); } -#if ENABLE_PACKET_CONTINUATION +#ifdef ENABLE_PACKET_CONTINUATION // Clear dataset consolidation con->hdr.id = con->hdr.size = con->hdr.offset = 0; diff --git a/src/com_manager.h b/src/com_manager.h index cf8c476d9..40aae116f 100644 --- a/src/com_manager.h +++ b/src/com_manager.h @@ -128,7 +128,7 @@ typedef struct // Comm instance data buffer uint8_t comm_buffer[PKT_BUF_SIZE]; -#if ENABLE_PACKET_CONTINUATION +#ifdef ENABLE_PACKET_CONTINUATION // Continuation data for packets p_data_t con; diff --git a/src/rtk_defines.h b/src/rtk_defines.h index 701b07976..6fe9b2801 100644 --- a/src/rtk_defines.h +++ b/src/rtk_defines.h @@ -183,7 +183,7 @@ typedef uint32_t pthread_t; typedef uint32_t pthread_mutex_t; typedef int lock_t; -typedef int DIR; +// typedef int DIR; struct dirent { char* d_name; }; #define pthread_mutex_init(f, f2) diff --git a/src/util/util.h b/src/util/util.h index d8a1cb753..f7df799bb 100644 --- a/src/util/util.h +++ b/src/util/util.h @@ -13,18 +13,22 @@ #include #include +#if !PLATFORM_IS_EMBEDDED +#define SNPRINTF std::snprintf +#endif + namespace utils { std::string getCurrentTimestamp(); template std::string string_format(const std::string& format, Args ... args) { - int size_s = std::snprintf( nullptr, 0, format.c_str(), args ... ) + 1; // Extra space for '\0' + int size_s = SNPRINTF( nullptr, 0, format.c_str(), args ... ) + 1; // Extra space for '\0' if( size_s <= 0 ) { throw std::runtime_error( "Error during formatting." ); } auto size = static_cast( size_s ); std::unique_ptr buf( new char[ size ] ); - std::snprintf( buf.get(), size, format.c_str(), args ... ); + SNPRINTF( buf.get(), size, format.c_str(), args ... ); return std::string( buf.get(), buf.get() + size - 1 ); // We don't want the '\0' inside } };