diff --git a/.gitignore b/.gitignore new file mode 100644 index 00000000..5b8464f1 --- /dev/null +++ b/.gitignore @@ -0,0 +1,60 @@ +#==============================================================================# +# This file specifies intentionally untracked files that git should ignore. +# See: http://www.kernel.org/pub/software/scm/git/docs/gitignore.html +# +# This file is intentionally different from the output of `git svn show-ignore`, +# as most of those are useless. +#==============================================================================# + +#==============================================================================# +# File extensions to be ignored anywhere in the tree. +#==============================================================================# +# Temp files created by most text editors. +*~ +# Merge files created by git. +*.orig +# Byte compiled python modules. +*.pyc +# vim swap files +.*.sw? +.sw? +#OS X specific files. +.DS_store + +# Nested build directory +/build + +#==============================================================================# +# Explicit files to ignore (only matches one). +#==============================================================================# +# Various tag programs +/tags +/TAGS +/GPATH +/GRTAGS +/GSYMS +/GTAGS +.gitusers +autom4te.cache +cscope.files +cscope.out +autoconf/aclocal.m4 +autoconf/autom4te.cache +/compile_commands.json +tags +# Visual Studio built-in CMake configuration +/CMakeSettings.json +# CLion project configuration +/.idea + +#==============================================================================# +# Directories to ignore (do not add trailing '/'s, they skip symlinks). +#==============================================================================# +# Sphinx build tree, if building in-source dir. +GenXIntrinsics/docs/_build +GenXIntrinsics/docs/autogenerated +# VS2017 and VSCode config files. +.vscode +.vs +# clangd index +.clangd diff --git a/CMakeLists.txt b/CMakeLists.txt index 4dffb68e..19f38151 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,12 +1,22 @@ +#=========================== begin_copyright_notice ============================ +# +# Copyright (C) 2019-2021 Intel Corporation +# +# SPDX-License-Identifier: MIT +# +#============================ end_copyright_notice ============================= + cmake_minimum_required(VERSION 3.13.4) set(LLVM_GENX_INTRINSICS_VERSION 1.0) +set(LLVM_GENX_INTRINSICS_ROOT_DIR ${CMAKE_CURRENT_SOURCE_DIR}) + # check if we build inside llvm or not if(CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR) get_filename_component(LLVM_CMAKE_PATH ${LLVM_DIR} ABSOLUTE BASE_DIR ${CMAKE_BINARY_DIR}) set(BUILD_EXTERNAL YES) - if (NOT DEFINED INSTALL_REQUIRED) + if(NOT DEFINED INSTALL_REQUIRED) set(INSTALL_REQUIRED YES) endif() project(LLVM_GenXIntrinsics @@ -36,28 +46,26 @@ else(CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR) # LLVM_CMAKE_DIR is not set for non-standalone builds. Use LLVM_CMAKE_PATH # instead. (see clang/CMakeLists.txt) - if (NOT LLVM_CMAKE_DIR) + if(NOT LLVM_CMAKE_DIR) set(LLVM_CMAKE_DIR ${LLVM_CMAKE_PATH}) endif() - - # we require include_directories because other components may include intrinsics headers. - include_directories(${CMAKE_CURRENT_SOURCE_DIR}/GenXIntrinsics/include) - include_directories(${CMAKE_CURRENT_BINARY_DIR}/GenXIntrinsics/include) endif(CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR) +if(LLVM_VERSION_MAJOR VERSION_LESS 8) + message(FATAL_ERROR "VC-intrinsics do not support ${LLVM_VERSION} LLVM version") +endif() + include(FindPythonInterp) -if( NOT PYTHONINTERP_FOUND ) +if(NOT PYTHONINTERP_FOUND) message(FATAL_ERROR "Unable to find Python interpreter, required for builds and testing. Please install Python or specify the PYTHON_EXECUTABLE CMake variable.") endif() -if( "${PYTHON_VERSION_STRING}" VERSION_LESS 2.7 ) +if("${PYTHON_VERSION_STRING}" VERSION_LESS 2.7) message(FATAL_ERROR "Python 2.7 or newer is required") endif() add_subdirectory(GenXIntrinsics) - - diff --git a/GenXIntrinsics/CMakeLists.txt b/GenXIntrinsics/CMakeLists.txt index 35c135ea..689e7558 100644 --- a/GenXIntrinsics/CMakeLists.txt +++ b/GenXIntrinsics/CMakeLists.txt @@ -1,14 +1,30 @@ +#=========================== begin_copyright_notice ============================ +# +# Copyright (C) 2019-2021 Intel Corporation +# +# SPDX-License-Identifier: MIT +# +#============================ end_copyright_notice ============================= + cmake_minimum_required(VERSION 3.13.4) include(GNUInstallDirs) set(GENX_INTRINSICS_MAIN_INCLUDE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/include) +set(GENX_INTRINSICS_MAIN_DIR ${CMAKE_CURRENT_SOURCE_DIR}) + if(IGC_INFRA) set(GENX_INTRINSICS_MAIN_INCLUDE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/include PARENT_SCOPE) endif() include(cmake/utils.cmake) +# Global config. +add_compile_definitions(VC_INTR_LLVM_VERSION_MAJOR=${LLVM_VERSION_MAJOR}) + +include_directories(${CMAKE_CURRENT_SOURCE_DIR}/include) +include_directories(${CMAKE_CURRENT_BINARY_DIR}/include) + set(GENX_INTRINSICS_DESCRIPTION "GenXIntrinsicDescription.gen") add_subdirectory(include/llvm) @@ -59,9 +75,16 @@ if(INSTALL_REQUIRED) INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} ) + # Legacy export. To remove when all clients switch to new name. install(EXPORT LLVMGenXIntrinsicsTargets FILE LLVMGenXIntrinsicsConfig.cmake DESTINATION ${CMAKE_INSTALL_LIBDIR}/cmake/LLVMGenXIntrinsics ) + + set(PACKAGE_NAME VCIntrinsics${LLVM_VERSION_MAJOR}) + install(EXPORT LLVMGenXIntrinsicsTargets + FILE ${PACKAGE_NAME}Config.cmake + DESTINATION ${CMAKE_INSTALL_LIBDIR}/cmake/${PACKAGE_NAME} + ) endif() # BUILD_EXTERNAL endif() # INSTALL_REQUIRED diff --git a/GenXIntrinsics/cmake/utils.cmake b/GenXIntrinsics/cmake/utils.cmake index b42a539c..2adb09df 100644 --- a/GenXIntrinsics/cmake/utils.cmake +++ b/GenXIntrinsics/cmake/utils.cmake @@ -1,3 +1,11 @@ +#=========================== begin_copyright_notice ============================ +# +# Copyright (C) 2020-2021 Intel Corporation +# +# SPDX-License-Identifier: MIT +# +#============================ end_copyright_notice ============================= + # Convenience function to get list of LLVM components for # target_link_library. If LLVM was configured with llvm dylib, then # included in dylib llvm targets should be replaced with LLVM diff --git a/GenXIntrinsics/docs/GenXLangRef.rst b/GenXIntrinsics/docs/GenXLangRef.rst index ebab2ead..99878e25 100644 --- a/GenXIntrinsics/docs/GenXLangRef.rst +++ b/GenXIntrinsics/docs/GenXLangRef.rst @@ -1,3 +1,11 @@ +.. ========================= begin_copyright_notice ============================ + + Copyright (C) 2015-2021 Intel Corporation + + SPDX-License-Identifier: MIT + + =========================== end_copyright_notice ============================= + ============================ LLVM IR for the GenX backend ============================ diff --git a/GenXIntrinsics/docs/LangRefIndex.rst b/GenXIntrinsics/docs/LangRefIndex.rst index 7db6fedd..4154183e 100644 --- a/GenXIntrinsics/docs/LangRefIndex.rst +++ b/GenXIntrinsics/docs/LangRefIndex.rst @@ -1,3 +1,11 @@ +.. ========================= begin_copyright_notice ============================ + + Copyright (C) 2019-2021 Intel Corporation + + SPDX-License-Identifier: MIT + + =========================== end_copyright_notice ============================= + VC Intrinsics documentation (language reference) ================================================== diff --git a/GenXIntrinsics/docs/Makefile.sphinx b/GenXIntrinsics/docs/Makefile.sphinx index 788f6e7e..fbf43401 100644 --- a/GenXIntrinsics/docs/Makefile.sphinx +++ b/GenXIntrinsics/docs/Makefile.sphinx @@ -1,3 +1,11 @@ +#=========================== begin_copyright_notice ============================ +# +# Copyright (C) 2019-2021 Intel Corporation +# +# SPDX-License-Identifier: MIT +# +#============================ end_copyright_notice ============================= + # Minimal makefile for Sphinx documentation # diff --git a/GenXIntrinsics/docs/ReadMe.txt b/GenXIntrinsics/docs/ReadMe.txt new file mode 100644 index 00000000..06e9d93a --- /dev/null +++ b/GenXIntrinsics/docs/ReadMe.txt @@ -0,0 +1,8 @@ + + diff --git a/GenXIntrinsics/docs/conf.py b/GenXIntrinsics/docs/conf.py index 64af9243..8201c69e 100644 --- a/GenXIntrinsics/docs/conf.py +++ b/GenXIntrinsics/docs/conf.py @@ -1,3 +1,11 @@ +# ========================== begin_copyright_notice ============================ +# +# Copyright (C) 2019-2021 Intel Corporation +# +# SPDX-License-Identifier: MIT +# +# =========================== end_copyright_notice ============================= + # -*- coding: utf-8 -*- # # VC Intrinsics documentation build configuration file. diff --git a/GenXIntrinsics/include/llvm/CMakeLists.txt b/GenXIntrinsics/include/llvm/CMakeLists.txt index d279a88a..0836db4e 100644 --- a/GenXIntrinsics/include/llvm/CMakeLists.txt +++ b/GenXIntrinsics/include/llvm/CMakeLists.txt @@ -1 +1,9 @@ +#=========================== begin_copyright_notice ============================ +# +# Copyright (C) 2019-2021 Intel Corporation +# +# SPDX-License-Identifier: MIT +# +#============================ end_copyright_notice ============================= + add_subdirectory(GenXIntrinsics) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/CMakeLists.txt b/GenXIntrinsics/include/llvm/GenXIntrinsics/CMakeLists.txt index 1b4b9714..c46e47c4 100755 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/CMakeLists.txt +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/CMakeLists.txt @@ -1,3 +1,11 @@ +#=========================== begin_copyright_notice ============================ +# +# Copyright (C) 2019-2021 Intel Corporation +# +# SPDX-License-Identifier: MIT +# +#============================ end_copyright_notice ============================= + add_custom_command( OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${GENX_INTRINSICS_DESCRIPTION} COMMAND ${PYTHON_EXECUTABLE} -B @@ -10,8 +18,44 @@ add_custom_command( COMMENT "Building ${GENX_INTRINSICS_DESCRIPTION}..." ) +find_first_existing_vc_file(intrinsics_vc "${GENX_INTRINSICS_MAIN_DIR}") + +set(version_inc ${CMAKE_CURRENT_BINARY_DIR}/GenXVersion.inc) + +if(LLVM_GENX_INTRINSICS_ROOT_DIR) + set(LLVM_GENX_INTRINSICS_REPO_DIR ${LLVM_GENX_INTRINSICS_ROOT_DIR}) +else() + set(LLVM_GENX_INTRINSICS_REPO_DIR ${GENX_INTRINSICS_MAIN_DIR}/..) +endif() + +if(${LLVM_VERSION_MAJOR} LESS 9) + find_file(FOUND_VCS GetSVN.cmake PATHS ${LLVM_CMAKE_DIR} REQUIRED) + add_custom_command( + OUTPUT "${version_inc}" + COMMAND + ${CMAKE_COMMAND} "-DSOURCE_DIRS=${LLVM_GENX_INTRINSICS_REPO_DIR}" + "-DNAMES=VCI" + "-DHEADER_FILE=${version_inc}" + -P "${FOUND_VCS}") +else() + find_file(FOUND_VCS VersionFromVCS.cmake PATHS ${LLVM_CMAKE_DIR} REQUIRED) + add_custom_command( + OUTPUT "${version_inc}" + COMMAND + ${CMAKE_COMMAND} "-DSOURCE_DIR=${LLVM_GENX_INTRINSICS_REPO_DIR}" + "-DNAME=VCI" + "-DHEADER_FILE=${version_inc}" + "-DVCS_SCRIPT=${FOUND_VCS}" + -P "${CMAKE_CURRENT_SOURCE_DIR}/ConfigureVersionFile.cmake") +endif() + +set_source_files_properties("${version_inc}" + PROPERTIES GENERATED TRUE + HEADER_FILE_ONLY TRUE) + add_custom_target(GenXIntrinsicDescriptionGen DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${GENX_INTRINSICS_DESCRIPTION} + ${version_inc} ) add_custom_target(GenXIntrinsicsGen) add_dependencies(GenXIntrinsicsGen GenXIntrinsicDescriptionGen) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/ConfigureVersionFile.cmake b/GenXIntrinsics/include/llvm/GenXIntrinsics/ConfigureVersionFile.cmake new file mode 100644 index 00000000..e4b4256a --- /dev/null +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/ConfigureVersionFile.cmake @@ -0,0 +1,22 @@ +#=========================== begin_copyright_notice ============================ +# +# Copyright (C) 2020-2021 Intel Corporation +# +# SPDX-License-Identifier: MIT +# +#============================ end_copyright_notice ============================= + +include(${VCS_SCRIPT}) + +function(generate_version_file output_file) + get_source_info(${SOURCE_DIR} rev repo) + file(APPEND "${output_file}.txt" "#define ${NAME}_REVISION \"${rev}\"\n") + file(APPEND "${output_file}.txt" "#define ${NAME}_REPOSITORY \"${repo}\"\n") + execute_process(COMMAND ${CMAKE_COMMAND} -E copy_if_different + "${output_file}.txt" "${output_file}") + file(REMOVE "${output_file}.txt") + +endfunction() + +generate_version_file(${HEADER_FILE}) + diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrOpts.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrOpts.h index 4441f784..f5e644fb 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrOpts.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrOpts.h @@ -1,16 +1,20 @@ -//===-- GenXIntrOpts.h - GenX Transformations -------------------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// +/*========================== begin_copyright_notice ============================ + +Copyright (C) 2020-2021 Intel Corporation + +SPDX-License-Identifier: MIT + +============================= end_copyright_notice ===========================*/ + +/*========================== begin_copyright_notice ============================ + +This file is distributed under the University of Illinois Open Source License. +See LICENSE.TXT for details. + +============================= end_copyright_notice ===========================*/ + // This header file defines prototypes for accessor functions that expose passes // in the GenX Intrinsics transformations library. -// -//===----------------------------------------------------------------------===// #ifndef LLVM_GENX_INTR_OPTS_H #define LLVM_GENX_INTR_OPTS_H diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsicInst.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsicInst.h index a3a4ec88..fb37eddd 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsicInst.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsicInst.h @@ -1,27 +1,10 @@ -/*===================== begin_copyright_notice ================================== +/*========================== begin_copyright_notice ============================ - Copyright (c) 2020, Intel Corporation +Copyright (C) 2019-2021 Intel Corporation +SPDX-License-Identifier: MIT - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ - +============================= end_copyright_notice ===========================*/ //===----------------------------------------------------------------------===// // @@ -67,13 +50,13 @@ class GenXIntrinsicInst : public CallInst { } // Methods for support type inquiry through isa, cast, and dyn_cast: - static inline bool classof(const CallInst *I) { + static bool classof(const CallInst *I) { if (const Function *CF = I->getCalledFunction()) { return CF->getName().startswith(GenXIntrinsic::getGenXIntrinsicPrefix()); } return false; } - static inline bool classof(const Value *V) { + static bool classof(const Value *V) { return isa(V) && classof(cast(V)); } }; diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h index 0fe1ea65..48ab26cf 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h @@ -1,27 +1,10 @@ -/*===================== begin_copyright_notice ================================== +/*========================== begin_copyright_notice ============================ - Copyright (c) 2020, Intel Corporation +Copyright (C) 2019-2021 Intel Corporation +SPDX-License-Identifier: MIT - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ - +============================= end_copyright_notice ===========================*/ //===----------------------------------------------------------------------===// // @@ -40,6 +23,7 @@ #include "llvm/IR/Function.h" #include "llvm/IR/Intrinsics.h" #include "llvm/IR/Instructions.h" +#include "llvm/GenXIntrinsics/GenXVersion.h" namespace llvm { @@ -55,14 +39,59 @@ enum ID : unsigned { }; namespace GenXResult { - enum ResultIndexes { - IdxAddc_Add = 1, - IdxAddc_Carry = 0, - IdxSubb_Sub = 1, - IdxSubb_Borrow = 0 - }; +enum ResultIndexes { + IdxAddc_Add = 1, + IdxAddc_Carry = 0, + IdxSubb_Sub = 1, + IdxSubb_Borrow = 0, + IdxAdd3c_Add = 1, + IdxAdd3c_Carry = 0 +}; } +// The number of elements to load per address (vector size) +// NOTE: taken from cmc/support +enum class LSCVectorSize : uint8_t { + N0 = 0, + N1 = 1, // 1 element + N2 = 2, // 2 element + N3 = 3, // 3 element + N4 = 4, // 4 element + N8 = 5, // 8 element + N16 = 6, // 16 element + N32 = 7, // 32 element + N64 = 8 // 64 element +}; + +enum class LSCDataSize : uint8_t { + Invalid, + D8, + D16, + D32, + D64, + D8U32, + D16U32, + D16U32H, +}; + +enum class LSCDataOrder : uint8_t { + Invalid, + NonTranspose, + Transpose +}; + +enum class LSCCategory : uint8_t { + Load, + Load2D, + Prefetch, + Prefetch2D, + Store, + Store2D, + Fence, + LegacyAtomic, + Atomic, + NotLSC +}; namespace GenXRegion { enum { @@ -83,13 +112,13 @@ enum { }; } // namespace GenXRegion -static inline const char *getGenXIntrinsicPrefix() { return "llvm.genx."; } +inline const char *getGenXIntrinsicPrefix() { return "llvm.genx."; } ID getGenXIntrinsicID(const Function *F); /// Utility function to get the genx_intrinsic ID if V is a GenXIntrinsic call. /// V is allowed to be 0. -static inline ID getGenXIntrinsicID(const Value *V) { +inline ID getGenXIntrinsicID(const Value *V) { if (V) if (const CallInst *CI = dyn_cast(V)) if (Function *Callee = CI->getCalledFunction()) @@ -100,7 +129,7 @@ static inline ID getGenXIntrinsicID(const Value *V) { /// GenXIntrinsic::isGenXIntrinsic(ID) - Is GenX intrinsic /// NOTE that this is include not_genx_intrinsic /// BUT DOES NOT include not_any_intrinsic -static inline bool isGenXIntrinsic(unsigned ID) { +inline bool isGenXIntrinsic(unsigned ID) { return ID >= not_genx_intrinsic && ID < num_genx_intrinsics; } @@ -108,7 +137,7 @@ static inline bool isGenXIntrinsic(unsigned ID) { /// the function's name starts with "llvm.genx.". /// It's possible for this function to return true while getGenXIntrinsicID() /// returns GenXIntrinsic::not_genx_intrinsic! -static inline bool isGenXIntrinsic(const Function *CF) { +inline bool isGenXIntrinsic(const Function *CF) { return CF->getName().startswith(getGenXIntrinsicPrefix()); } @@ -116,7 +145,7 @@ static inline bool isGenXIntrinsic(const Function *CF) { /// the function's name starts with "llvm.genx.". /// It's possible for this function to return true while getGenXIntrinsicID() /// returns GenXIntrinsic::not_genx_intrinsic! -static inline bool isGenXIntrinsic(const Value *V) { +inline bool isGenXIntrinsic(const Value *V) { if (V) if (const CallInst *CI = dyn_cast(V)) if (Function *Callee = CI->getCalledFunction()) @@ -126,19 +155,19 @@ static inline bool isGenXIntrinsic(const Value *V) { /// GenXIntrinsic::isGenXNonTrivialIntrinsic(ID) - Is GenX intrinsic, /// which is not equal to not_genx_intrinsic or not_any_intrinsic -static inline bool isGenXNonTrivialIntrinsic(unsigned ID) { +inline bool isGenXNonTrivialIntrinsic(unsigned ID) { return ID > not_genx_intrinsic && ID < num_genx_intrinsics; } /// GenXIntrinsic::isGenXNonTrivialIntrinsic(CF) - Returns true if /// CF is genx intrinsic, not equal to not_any_intrinsic or not_genx_intrinsic -static inline bool isGenXNonTrivialIntrinsic(const Function *CF) { +inline bool isGenXNonTrivialIntrinsic(const Function *CF) { return isGenXNonTrivialIntrinsic(getGenXIntrinsicID(CF)); } /// GenXIntrinsic::isGenXNonTrivialIntrinsic(V) - Returns true if /// V is genx intrinsic, not equal to not_any_intrinsic or not_genx_intrinsic -static inline bool isGenXNonTrivialIntrinsic(const Value *V) { +inline bool isGenXNonTrivialIntrinsic(const Value *V) { return isGenXNonTrivialIntrinsic(getGenXIntrinsicID(V)); } @@ -177,7 +206,7 @@ void resetGenXAttributes(Function* F); /// GenXIntrinsic::getAnyIntrinsicID(F) - Return LLVM or GenX intrinsic ID /// If is not intrinsic returns not_any_intrinsic /// Note that Function::getIntrinsicID returns ONLY LLVM intrinsics -static inline unsigned getAnyIntrinsicID(const Function *F) { +inline unsigned getAnyIntrinsicID(const Function *F) { if (isGenXNonTrivialIntrinsic(F)) return getGenXIntrinsicID(F); else { @@ -193,7 +222,7 @@ static inline unsigned getAnyIntrinsicID(const Function *F) { /// Utility function to get the LLVM or GenX intrinsic ID if V is an intrinsic /// call. /// V is allowed to be 0. -static inline unsigned getAnyIntrinsicID(const Value *V) { +inline unsigned getAnyIntrinsicID(const Value *V) { if (V) if (const CallInst *CI = dyn_cast(V)) if (Function *Callee = CI->getCalledFunction()) @@ -203,7 +232,7 @@ static inline unsigned getAnyIntrinsicID(const Value *V) { /// GenXIntrinsic::isAnyIntrinsic(ID) - Is any intrinsic /// including not_any_intrinsic -static inline bool isAnyIntrinsic(unsigned id) { +inline bool isAnyIntrinsic(unsigned id) { assert(id != not_genx_intrinsic && id != Intrinsic::not_intrinsic && "Do not use this method with getGenXIntrinsicID or getIntrinsicID!"); return id < num_genx_intrinsics || id == not_any_intrinsic; @@ -211,7 +240,7 @@ static inline bool isAnyIntrinsic(unsigned id) { /// GenXIntrinsic::isAnyNonTrivialIntrinsic(id) - Is GenX or LLVM intrinsic, /// which is not equal to not_any_intrinsic -static inline bool isAnyNonTrivialIntrinsic(unsigned id) { +inline bool isAnyNonTrivialIntrinsic(unsigned id) { assert(id != not_genx_intrinsic && id != Intrinsic::not_intrinsic && "Do not use this method with getGenXIntrinsicID or getIntrinsicID!"); return id < num_genx_intrinsics && @@ -220,14 +249,14 @@ static inline bool isAnyNonTrivialIntrinsic(unsigned id) { /// GenXIntrinsic::isAnyNonTrivialIntrinsic(ID) - Is GenX or LLVM intrinsic, /// which is not equal to not_genx_intrinsic, not_any_intrinsic or not_intrinsic -static inline bool isAnyNonTrivialIntrinsic(const Function *CF) { +inline bool isAnyNonTrivialIntrinsic(const Function *CF) { return isAnyNonTrivialIntrinsic(getAnyIntrinsicID(CF)); } /// Utility function to check if V is LLVM or GenX intrinsic call, /// which is not not_intrinsic, not_genx_intrinsic or not_any_intrinsic /// V is allowed to be 0. -static inline bool isAnyNonTrivialIntrinsic(const Value *V) { +inline bool isAnyNonTrivialIntrinsic(const Value *V) { return isAnyNonTrivialIntrinsic(getAnyIntrinsicID(V)); } @@ -236,8 +265,8 @@ static inline bool isAnyNonTrivialIntrinsic(const Value *V) { std::string getAnyName(unsigned id, ArrayRef Tys = None); /// GenXIntrinsic::getAnyType(ID) - Return the function type for an intrinsic. -static inline FunctionType *getAnyType(LLVMContext &Context, unsigned id, - ArrayRef Tys = None) { +inline FunctionType *getAnyType(LLVMContext &Context, unsigned id, + ArrayRef Tys = None) { assert(isAnyNonTrivialIntrinsic(id)); if (isGenXIntrinsic(id)) return getGenXType(Context, (ID)id, Tys); @@ -245,6 +274,10 @@ static inline FunctionType *getAnyType(LLVMContext &Context, unsigned id, return Intrinsic::getType(Context, (Intrinsic::ID)id, Tys); } +/// GenXIntrinsic::isSupportedPlatform(CPU, ID) - Return true if GenxIntrinsic +// is supported by current platform +bool isSupportedPlatform(const std::string &CPU, unsigned id); + /// GenXIntrinsic::isOverloadedArg(ID, ArgNum) - Return true if ArgNum /// in intrinsic overloaded bool isOverloadedArg(unsigned IntrinID, unsigned ArgNum); @@ -260,8 +293,8 @@ bool isOverloadedRet(unsigned IntrinID); /// using iAny, fAny, vAny, or iPTRAny). For a declaration of an overloaded /// intrinsic, Tys must provide exactly one type for each overloaded type in /// the intrinsic. -static inline Function *getAnyDeclaration(Module *M, unsigned id, - ArrayRef Tys = None) { +inline Function *getAnyDeclaration(Module *M, unsigned id, + ArrayRef Tys = None) { assert(isAnyNonTrivialIntrinsic(id)); if (isGenXIntrinsic(id)) { return getGenXDeclaration(M, (ID)id, Tys); @@ -270,9 +303,16 @@ static inline Function *getAnyDeclaration(Module *M, unsigned id, } } +/// GenXIntrinsic::getGenXMulIID(S1, S2) - returns GenXIntrinsic::ID for +/// the enx_XXmul opertation, where XX is is defined by the input arguments +/// which represent signs of the operands +inline GenXIntrinsic::ID getGenXMulIID(bool LHSign, bool RHSign) { + return LHSign + ? (RHSign ? GenXIntrinsic::genx_ssmul : GenXIntrinsic::genx_sumul) + : (RHSign ? GenXIntrinsic::genx_usmul : GenXIntrinsic::genx_uumul); +} - -static inline bool isRdRegion(unsigned IntrinID) { +inline bool isRdRegion(unsigned IntrinID) { switch (IntrinID) { case GenXIntrinsic::genx_rdregioni: case GenXIntrinsic::genx_rdregionf: @@ -282,15 +322,15 @@ static inline bool isRdRegion(unsigned IntrinID) { } } -static inline bool isRdRegion(const Function *F) { +inline bool isRdRegion(const Function *F) { return isRdRegion(getGenXIntrinsicID(F)); } -static inline bool isRdRegion(const Value *V) { +inline bool isRdRegion(const Value *V) { return isRdRegion(getGenXIntrinsicID(V)); } -static inline bool isWrRegion(unsigned IntrinID) { +inline bool isWrRegion(unsigned IntrinID) { switch (IntrinID) { case GenXIntrinsic::genx_wrregioni: case GenXIntrinsic::genx_wrregionf: @@ -301,29 +341,29 @@ static inline bool isWrRegion(unsigned IntrinID) { } } -static inline bool isWrRegion(const Function *F) { +inline bool isWrRegion(const Function *F) { return isWrRegion(getGenXIntrinsicID(F)); } -static inline bool isWrRegion(const Value *V) { +inline bool isWrRegion(const Value *V) { return isWrRegion(getGenXIntrinsicID(V)); } -static inline bool isAbs(unsigned IntrinID) { +inline bool isAbs(unsigned IntrinID) { if (IntrinID == GenXIntrinsic::genx_absf || IntrinID == GenXIntrinsic::genx_absi) return true; return false; } -static inline bool isAbs(const Function *F) { +inline bool isAbs(const Function *F) { return isAbs(getGenXIntrinsicID(F)); } -static inline bool isAbs(const Value *V) { +inline bool isAbs(const Value *V) { return isAbs(getGenXIntrinsicID(V)); } -static inline bool isIntegerSat(unsigned IID) { +inline bool isIntegerSat(unsigned IID) { switch (IID) { case GenXIntrinsic::genx_sstrunc_sat: case GenXIntrinsic::genx_sutrunc_sat: @@ -335,88 +375,538 @@ static inline bool isIntegerSat(unsigned IID) { } } -static inline bool isIntegerSat(const Function *F) { +inline bool isIntegerSat(const Function *F) { return isIntegerSat(getGenXIntrinsicID(F)); } -static inline bool isIntegerSat(const Value *V) { +inline bool isIntegerSat(const Value *V) { return isIntegerSat(getGenXIntrinsicID(V)); } -static inline bool isVLoad(unsigned IntrinID) { +inline bool isVLoad(unsigned IntrinID) { return IntrinID == GenXIntrinsic::genx_vload; } -static inline bool isVLoad(const Function *F) { +inline bool isVLoad(const Function *F) { return isVLoad(getGenXIntrinsicID(F)); } -static inline bool isVLoad(const Value *V) { +inline bool isVLoad(const Value *V) { return isVLoad(getGenXIntrinsicID(V)); } -static inline bool isVStore(unsigned IntrinID) { +inline bool isVStore(unsigned IntrinID) { return IntrinID == GenXIntrinsic::genx_vstore; } -static inline bool isVStore(const Function *F) { +inline bool isVStore(const Function *F) { return isVStore(getGenXIntrinsicID(F)); } -static inline bool isVStore(const Value *V) { +inline bool isVStore(const Value *V) { return isVStore(getGenXIntrinsicID(V)); } -static inline bool isVLoadStore(unsigned IntrinID) { +inline bool isVLoadStore(unsigned IntrinID) { return isVLoad(IntrinID) || isVStore(IntrinID); } -static inline bool isVLoadStore(const Function *F) { +inline bool isVLoadStore(const Function *F) { return isVLoadStore(getGenXIntrinsicID(F)); } -static inline bool isVLoadStore(const Value *V) { +inline bool isVLoadStore(const Value *V) { return isVLoadStore(getGenXIntrinsicID(V)); } -static inline bool isReadPredefReg(unsigned IntrinID) { +inline bool isReadPredefReg(unsigned IntrinID) { return IntrinID == GenXIntrinsic::genx_read_predef_reg; } -static inline bool isReadPredefReg(const Function *F) { +inline bool isReadPredefReg(const Function *F) { return isReadPredefReg(getGenXIntrinsicID(F)); } -static inline bool isReadPredefReg(const Value *V) { +inline bool isReadPredefReg(const Value *V) { return isReadPredefReg(getGenXIntrinsicID(V)); } -static inline bool isWritePredefReg(unsigned IntrinID) { +inline bool isWritePredefReg(unsigned IntrinID) { return IntrinID == GenXIntrinsic::genx_write_predef_reg; } -static inline bool isWritePredefReg(const Function *F) { +inline bool isWritePredefReg(const Function *F) { return isWritePredefReg(getGenXIntrinsicID(F)); } -static inline bool isWritePredefReg(const Value *V) { +inline bool isWritePredefReg(const Value *V) { return isWritePredefReg(getGenXIntrinsicID(V)); } -static inline bool isReadWritePredefReg(unsigned IntrinID) { +inline bool isReadWritePredefReg(unsigned IntrinID) { return isWritePredefReg(IntrinID) || isReadPredefReg(IntrinID); } -static inline bool isReadWritePredefReg(const Value *V) { +inline bool isReadWritePredefReg(const Value *V) { return isWritePredefReg(getGenXIntrinsicID(V)) || isReadPredefReg(getGenXIntrinsicID(V)); } -static inline bool isReadWritePredefReg(const Function *F) { +inline bool isReadWritePredefReg(const Function *F) { return isWritePredefReg(getGenXIntrinsicID(F)) || isReadPredefReg(getGenXIntrinsicID(F)); } +inline LSCCategory getLSCCategory(unsigned IntrinID) { + switch(IntrinID) { + case GenXIntrinsic::genx_lsc_load_bti: + case GenXIntrinsic::genx_lsc_load_stateless: + case GenXIntrinsic::genx_lsc_load_slm: + case GenXIntrinsic::genx_lsc_load_bindless: + case GenXIntrinsic::genx_lsc_load_quad_bti: + case GenXIntrinsic::genx_lsc_load_quad_slm: + case GenXIntrinsic::genx_lsc_load_quad_stateless: + return LSCCategory::Load; + case GenXIntrinsic::genx_lsc_load2d_stateless: + return LSCCategory::Load2D; + case GenXIntrinsic::genx_lsc_prefetch_bti: + case GenXIntrinsic::genx_lsc_prefetch_stateless: + return LSCCategory::Prefetch; + case GenXIntrinsic::genx_lsc_prefetch2d_stateless: + return LSCCategory::Prefetch2D; + case GenXIntrinsic::genx_lsc_store_bti: + case GenXIntrinsic::genx_lsc_store_stateless: + case GenXIntrinsic::genx_lsc_store_slm: + case GenXIntrinsic::genx_lsc_store_bindless: + case GenXIntrinsic::genx_lsc_store_quad_bti: + case GenXIntrinsic::genx_lsc_store_quad_slm: + case GenXIntrinsic::genx_lsc_store_quad_stateless: + return LSCCategory::Store; + case GenXIntrinsic::genx_lsc_store2d_stateless: + return LSCCategory::Store2D; + case GenXIntrinsic::genx_lsc_fence: + return LSCCategory::Fence; + case GenXIntrinsic::genx_lsc_atomic_bti: + case GenXIntrinsic::genx_lsc_atomic_stateless: + case GenXIntrinsic::genx_lsc_atomic_slm: + case GenXIntrinsic::genx_lsc_atomic_bindless: + return LSCCategory::LegacyAtomic; + case GenXIntrinsic::genx_lsc_xatomic_bti: + case GenXIntrinsic::genx_lsc_xatomic_stateless: + case GenXIntrinsic::genx_lsc_xatomic_slm: + case GenXIntrinsic::genx_lsc_xatomic_bindless: + return LSCCategory::Atomic; + default: + return LSCCategory::NotLSC; + } +} + +inline LSCCategory getLSCCategory(const Value *V) { + return getLSCCategory(getGenXIntrinsicID(V)); +} + +inline LSCCategory getLSCCategory(const Function *F) { + return getLSCCategory(getGenXIntrinsicID(F)); +} + +inline bool isLSCLoad(unsigned IntrinID) { + return getLSCCategory(IntrinID) == LSCCategory::Load; +} + +inline bool isLSCLoad(const Value *V) { + return isLSCLoad(getGenXIntrinsicID(V)); +} + +inline bool isLSCLoad(const Function *F) { + return isLSCLoad(getGenXIntrinsicID(F)); +} + +inline bool isLSCLoad2D(unsigned IntrinID) { + return getLSCCategory(IntrinID) == LSCCategory::Load2D; +} + +inline bool isLSCLoad2D(const Value *V) { + return isLSCLoad2D(getGenXIntrinsicID(V)); +} + +inline bool isLSCLoad2D(const Function *F) { + return isLSCLoad2D(getGenXIntrinsicID(F)); +} + + +inline bool isLSCPrefetch(unsigned IntrinID) { + return getLSCCategory(IntrinID) == LSCCategory::Prefetch; +} + +inline bool isLSCPrefetch(const Value *V) { + return isLSCPrefetch(getGenXIntrinsicID(V)); +} + +inline bool isLSCPrefetch(const Function *F) { + return isLSCPrefetch(getGenXIntrinsicID(F)); +} + +inline bool isLSCPrefetch2D(unsigned IntrinID) { + return getLSCCategory(IntrinID) == LSCCategory::Prefetch2D; +} + +inline bool isLSCPrefetch2D(const Value *V) { + return isLSCPrefetch2D(getGenXIntrinsicID(V)); +} + +inline bool isLSCPrefetch2D(const Function *F) { + return isLSCPrefetch2D(getGenXIntrinsicID(F)); +} + +inline bool isLSCStore(unsigned IntrinID) { + return getLSCCategory(IntrinID) == LSCCategory::Store; +} + +inline bool isLSCStore(const Value *V) { + return isLSCStore(getGenXIntrinsicID(V)); +} + +inline bool isLSCStore(const Function *F) { + return isLSCStore(getGenXIntrinsicID(F)); +} + +inline bool isLSCStore2D(unsigned IntrinID) { + return getLSCCategory(IntrinID) == LSCCategory::Store2D; +} + +inline bool isLSCStore2D(const Value *V) { + return isLSCStore2D(getGenXIntrinsicID(V)); +} + +inline bool isLSCStore2D(const Function *F) { + return isLSCStore2D(getGenXIntrinsicID(F)); +} + + +inline bool isLSCFence(unsigned IntrinID) { + return getLSCCategory(IntrinID) == LSCCategory::Fence; +} + +inline bool isLSCFence(const Value *V) { + return isLSCFence(getGenXIntrinsicID(V)); +} + +inline bool isLSCFence(const Function *F) { + return isLSCFence(getGenXIntrinsicID(F)); +} + +inline bool isLSCLegacyAtomic(unsigned IntrinID) { + return getLSCCategory(IntrinID) == LSCCategory::LegacyAtomic; +} + +inline bool isLSCLegacyAtomic(const Value *V) { + return isLSCLegacyAtomic(getGenXIntrinsicID(V)); +} + +inline bool isLSCLegacyAtomic(const Function *F) { + return isLSCLegacyAtomic(getGenXIntrinsicID(F)); +} + +inline bool isLSCAtomic(unsigned IntrinID) { + return getLSCCategory(IntrinID) == LSCCategory::Atomic; +} + +inline bool isLSCAtomic(const Value *V) { + return isLSCAtomic(getGenXIntrinsicID(V)); +} + +inline bool isLSCAtomic(const Function *F) { + return isLSCAtomic(getGenXIntrinsicID(F)); +} + +inline bool isLSC(unsigned IntrinID) { + return getLSCCategory(IntrinID) != LSCCategory::NotLSC; +} + +inline bool isLSC(const Value *V) { + return isLSC(getGenXIntrinsicID(V)); +} + +inline bool isLSC(const Function *F) { + return isLSC(getGenXIntrinsicID(F)); +} + +inline bool isLSC2D(unsigned IntrinID) { + switch (getLSCCategory(IntrinID)) { + case LSCCategory::Load2D: + case LSCCategory::Prefetch2D: + case LSCCategory::Store2D: + return true; + case LSCCategory::Load: + case LSCCategory::Prefetch: + case LSCCategory::Store: + case LSCCategory::Fence: + case LSCCategory::LegacyAtomic: + case LSCCategory::Atomic: + case LSCCategory::NotLSC: + return false; + } + llvm_unreachable("Unknown LSC category"); +} + +inline bool isLSC2D(const Value *V) { + return isLSC2D(getGenXIntrinsicID(V)); +} + +inline bool isLSC2D(const Function *F) { + return isLSC2D(getGenXIntrinsicID(F)); +} + + +// Dependency from visa_igc_common_header. +// Converts vector size into LSC-appropriate code. +inline LSCVectorSize getLSCVectorSize(unsigned N) { + switch (N) { + case 0: + return LSCVectorSize::N0; + case 1: + return LSCVectorSize::N1; + case 2: + return LSCVectorSize::N2; + case 3: + return LSCVectorSize::N3; + case 4: + return LSCVectorSize::N4; + case 8: + return LSCVectorSize::N8; + case 16: + return LSCVectorSize::N16; + case 32: + return LSCVectorSize::N32; + case 64: + return LSCVectorSize::N64; + } + llvm_unreachable("Unknown vector size"); +} +// Gets encoded vector size for LSC instruction. +inline uint8_t getEncodedLSCVectorSize(unsigned N) { + return static_cast(getLSCVectorSize(N)); +} + +// Functions in this namespace return argument index for LSC instruction. +namespace LSCArgIdx { +constexpr int Invalid = -1; +// Returns VectorSize index. +inline int getLSCVectorSize(LSCCategory Cat) { + switch (Cat) { + case LSCCategory::Load: + case LSCCategory::Prefetch: + case LSCCategory::Store: + case LSCCategory::Atomic: + return 7; + case LSCCategory::LegacyAtomic: + return 8; + case LSCCategory::Prefetch2D: + case LSCCategory::Load2D: + case LSCCategory::Store2D: + case LSCCategory::Fence: + case LSCCategory::NotLSC: + llvm_unreachable("no such argument"); + return Invalid; + } + return Invalid; +} +// Returns VectorSize index. +inline int getLSCVectorSize(unsigned IID) { + return LSCArgIdx::getLSCVectorSize(getLSCCategory(IID)); +} + +// Returns DataSize index. +inline int getLSCDataSize(LSCCategory Cat) { + switch (Cat) { + case LSCCategory::Load: + case LSCCategory::Prefetch: + case LSCCategory::Store: + case LSCCategory::LegacyAtomic: + case LSCCategory::Atomic: + return 6; + case LSCCategory::Load2D: + case LSCCategory::Prefetch2D: + case LSCCategory::Store2D: + return 3; + case LSCCategory::Fence: + case LSCCategory::NotLSC: + llvm_unreachable("no such argument"); + return Invalid; + } + return Invalid; +} +// Returns DataSize index. +inline int getLSCDataSize(unsigned IID) { + return LSCArgIdx::getLSCDataSize(getLSCCategory(IID)); +} + +// Returns immediate offset index. +inline int getLSCImmOffset(LSCCategory Cat) { + switch (Cat) { + case LSCCategory::Load: + case LSCCategory::Prefetch: + case LSCCategory::Store: + case LSCCategory::LegacyAtomic: + case LSCCategory::Atomic: + return 5; + case LSCCategory::Prefetch2D: + case LSCCategory::Load2D: + case LSCCategory::Store2D: + case LSCCategory::Fence: + case LSCCategory::NotLSC: + llvm_unreachable("no such argument"); + return Invalid; + } + return Invalid; +} +// Returns immediate offset index. +inline int getLSCImmOffset(unsigned IID) { + return LSCArgIdx::getLSCImmOffset(getLSCCategory(IID)); +} + +// Returns data order index. +inline int getLSCDataOrder(LSCCategory Cat) { + switch (Cat) { + case LSCCategory::Load: + case LSCCategory::Prefetch: + case LSCCategory::Store: + case LSCCategory::Atomic: + return 8; + case LSCCategory::LegacyAtomic: + return 7; + case LSCCategory::Load2D: + case LSCCategory::Prefetch2D: + case LSCCategory::Store2D: + return 4; + case LSCCategory::Fence: + case LSCCategory::NotLSC: + llvm_unreachable("no such argument"); + return Invalid; + } + return Invalid; +} +// Returns data order index. +inline int getLSCDataOrder(unsigned IID) { + return LSCArgIdx::getLSCDataOrder(getLSCCategory(IID)); +} + +// Returns width index. +inline int getLSCWidth(LSCCategory Cat) { + switch (Cat) { + case LSCCategory::Load: + case LSCCategory::Prefetch: + case LSCCategory::Store: + case LSCCategory::Fence: + case LSCCategory::LegacyAtomic: + case LSCCategory::Atomic: + case LSCCategory::Load2D: + case LSCCategory::Prefetch2D: + case LSCCategory::Store2D: + return 0; + case LSCCategory::NotLSC: + llvm_unreachable("no such argument"); + return Invalid; + } + return Invalid; +} +// Returns width index. +inline int getLSCWidth(unsigned IID) { + return LSCArgIdx::getLSCWidth(getLSCCategory(IID)); +} + +} // namespace LSCArgIdx + +inline unsigned getLSCNumVectorElements(LSCVectorSize VS) { + switch (VS) { + case LSCVectorSize::N0: + break; + case LSCVectorSize::N1: + return 1; + case LSCVectorSize::N2: + return 2; + case LSCVectorSize::N3: + return 3; + case LSCVectorSize::N4: + return 4; + case LSCVectorSize::N8: + return 8; + case LSCVectorSize::N16: + return 16; + case LSCVectorSize::N32: + return 32; + case LSCVectorSize::N64: + return 64; + } + llvm_unreachable("Unknown vector size"); +} + +LSCVectorSize getLSCVectorSize(const Instruction *I); + +inline unsigned getLSCNumVectorElements(const Instruction *I) { + return GenXIntrinsic::getLSCNumVectorElements(getLSCVectorSize(I)); +} + +inline unsigned getLSCDataBitsRegister(LSCDataSize DS) { + switch(DS) { + case LSCDataSize::Invalid: + break; + case LSCDataSize::D8: + return 8; + case LSCDataSize::D16: + return 16; + case LSCDataSize::D32: + case LSCDataSize::D8U32: + case LSCDataSize::D16U32: + case LSCDataSize::D16U32H: + return 32; + case LSCDataSize::D64: + return 64; + } + llvm_unreachable("Unknown data size"); +} + +inline unsigned getLSCDataBitsMemory(LSCDataSize DS) { + switch(DS) { + case LSCDataSize::Invalid: + break; + case LSCDataSize::D8: + case LSCDataSize::D8U32: + return 8; + case LSCDataSize::D16: + case LSCDataSize::D16U32: + case LSCDataSize::D16U32H: + return 16; + case LSCDataSize::D32: + return 32; + case LSCDataSize::D64: + return 64; + } + llvm_unreachable("Unknown data size"); +} + +LSCDataSize getLSCDataSize(const Instruction *I); + +inline unsigned getLSCDataBitsRegister(const Instruction *I) { + return getLSCDataBitsRegister(getLSCDataSize(I)); +} + +inline unsigned getLSCDataBitsMemory(const Instruction *I) { + return getLSCDataBitsMemory(getLSCDataSize(I)); +} + +LSCDataOrder getLSCDataOrder(const Instruction *I); + +inline bool isLSCNonTransposed(const Instruction *I) { + return getLSCDataOrder(I) == LSCDataOrder::NonTranspose; +} + +inline bool isLSCTransposed(const Instruction *I) { + return getLSCDataOrder(I) == LSCDataOrder::Transpose; +} + +unsigned getLSCWidth(const Instruction *I); + } // namespace GenXIntrinsic // todo: delete this diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h index 7ec895e8..e95512db 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h @@ -1,27 +1,10 @@ -/*===================== begin_copyright_notice ================================== +/*========================== begin_copyright_notice ============================ - Copyright (c) 2020, Intel Corporation +Copyright (C) 2020-2021 Intel Corporation +SPDX-License-Identifier: MIT - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ - +============================= end_copyright_notice ===========================*/ //===----------------------------------------------------------------------===// // @@ -34,6 +17,10 @@ #define GENX_METADATA_H namespace llvm { + +class MDNode; +class Function; + namespace genx { namespace FunctionMD { @@ -43,6 +30,7 @@ static constexpr const char GenXVolatile[] = "genx_volatile"; static constexpr const char CMGenXMain[] = "CMGenxMain"; static constexpr const char CMStackCall[] = "CMStackCall"; static constexpr const char CMCallable[] = "CMCallable"; +static constexpr const char CMEntry[] = "CMEntry"; static constexpr const char CMFloatControl[] = "CMFloatControl"; static constexpr const char CMGenxSIMT[] = "CMGenxSIMT"; static constexpr const char CMGenxReplicateMask[] = "CMGenxReplicateMask"; @@ -54,19 +42,21 @@ namespace VCModuleMD { static constexpr const char VCGlobalVariable[] = "VCGlobalVariable"; static constexpr const char VCVolatile[] = "VCVolatile"; static constexpr const char VCByteOffset[] = "VCByteOffset"; +static constexpr const char VCSingleElementVector[] = "VCSingleElementVector"; } // namespace VCModuleMD namespace VCFunctionMD { static constexpr const char VCFunction[] = "VCFunction"; static constexpr const char VCStackCall[] = "VCStackCall"; static constexpr const char VCCallable[] = "VCCallable"; +static constexpr const char VCFCEntry[] = "VCFCEntry"; static constexpr const char VCArgumentIOKind[] = "VCArgumentIOKind"; static constexpr const char VCFloatControl[] = "VCFloatControl"; static constexpr const char VCSLMSize[] = "VCSLMSize"; static constexpr const char VCArgumentKind[] = "VCArgumentKind"; static constexpr const char VCArgumentDesc[] = "VCArgumentDesc"; static constexpr const char VCSIMTCall[] = "VCSIMTCall"; -static constexpr const char VCSingleElementVector[] = "VCSingleElementVector"; +static constexpr const char VCNamedBarrierCount[] = "VCNamedBarrierCount"; } // namespace VCFunctionMD enum KernelMDOp { @@ -78,26 +68,11 @@ enum KernelMDOp { ArgIOKinds, // Reference to metadata node containing kernel argument // input/output kinds ArgTypeDescs, // Kernel argument type descriptors - Reserved_0, + NBarrierCnt, // Named barrier count BarrierCnt // Barrier count }; -inline MDNode *GetOldStyleKernelMD(Function const &F) { - auto *KernelMD = static_cast(nullptr); - auto *KernelMDs = F.getParent()->getNamedMetadata(FunctionMD::GenXKernels); - if (!KernelMDs) - return KernelMD; - - for (unsigned I = 0, E = KernelMDs->getNumOperands(); I < E; ++I) { - auto *Kernel = mdconst::dyn_extract( - KernelMDs->getOperand(I)->getOperand(KernelMDOp::FunctionRef)); - if (Kernel == &F) { - KernelMD = KernelMDs->getOperand(I); - break; - } - } - return KernelMD; -} +MDNode *GetOldStyleKernelMD(const Function &F); } // namespace genx } // namespace llvm diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVReaderAdaptor.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVReaderAdaptor.h index cec6737f..347a535f 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVReaderAdaptor.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVReaderAdaptor.h @@ -1,26 +1,10 @@ -/*===================== begin_copyright_notice ================================== +/*========================== begin_copyright_notice ============================ - Copyright (c) 2020, Intel Corporation +Copyright (C) 2020-2021 Intel Corporation +SPDX-License-Identifier: MIT - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ +============================= end_copyright_notice ===========================*/ /// /// GenXSPIRVReaderAdaptor diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVWriterAdaptor.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVWriterAdaptor.h index c96a61bd..12e92f43 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVWriterAdaptor.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVWriterAdaptor.h @@ -1,26 +1,10 @@ -/*===================== begin_copyright_notice ================================== +/*========================== begin_copyright_notice ============================ - Copyright (c) 2020, Intel Corporation +Copyright (C) 2020-2021 Intel Corporation +SPDX-License-Identifier: MIT - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ +============================= end_copyright_notice ===========================*/ /// /// GenXSPIRVWriterAdaptor diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSimdCFLowering.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSimdCFLowering.h index 8b0b8056..e71633e9 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSimdCFLowering.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSimdCFLowering.h @@ -1,36 +1,13 @@ -/*===================== begin_copyright_notice ================================== - - Copyright (c) 2020, Intel Corporation - - - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ - -//===----------------------------------------------------------------------===// -// -/// LowerCMSimdCF -/// ------------- -/// -/// This is the worker class to lowers CM SIMD control flow into a form where -/// the IR reflects the semantics. See CMSimdCFLowering.cpp for details. -/// -//===----------------------------------------------------------------------===// +/*========================== begin_copyright_notice ============================ + +Copyright (C) 2019-2021 Intel Corporation + +SPDX-License-Identifier: MIT + +============================= end_copyright_notice ===========================*/ + +// This is the worker class to lowers CM SIMD control flow into a form where +// the IR reflects the semantics. See CMSimdCFLowering.cpp for details. #ifndef CMSIMDCF_LOWER_H #define CMSIMDCF_LOWER_H @@ -40,6 +17,7 @@ #include "llvm/IR/GlobalVariable.h" #include "llvm/IR/Instructions.h" #include +#include #include namespace llvm { diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXVersion.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXVersion.h new file mode 100644 index 00000000..8241726e --- /dev/null +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXVersion.h @@ -0,0 +1,26 @@ +/*========================== begin_copyright_notice ============================ + +Copyright (C) 2020-2021 Intel Corporation + +SPDX-License-Identifier: MIT + +============================= end_copyright_notice ===========================*/ + +// This file declares interface functions used to aquire version info. + +#ifndef GENX_VERSION +#define GENX_VERSION + +#include + +namespace llvm { + +namespace GenXIntrinsic { + +std::string getVCIntrinsicsRevision(); +std::string getVCIntrinsicsRepository(); + +} // namespace GenXIntrinsic +} // namespace llvm + +#endif diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py index bfd22262..6d09b35b 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py @@ -1,32 +1,10 @@ - -#===================== begin_copyright_notice ================================== - -#Copyright (c) 2020, Intel Corporation - - -#Permission is hereby granted, free of charge, to any person obtaining a -#copy of this software and associated documentation files (the -#"Software"), to deal in the Software without restriction, including -#without limitation the rights to use, copy, modify, merge, publish, -#distribute, sublicense, and/or sell copies of the Software, and to -#permit persons to whom the Software is furnished to do so, subject to -#the following conditions: - -#The above copyright notice and this permission notice shall be included -#in all copies or substantial portions of the Software. - -#THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS -#OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -#MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -#IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY -#CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -#TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE -#SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - - -#======================= end_copyright_notice ================================== - - +# ========================== begin_copyright_notice ============================ +# +# Copyright (C) 2019-2021 Intel Corporation +# +# SPDX-License-Identifier: MIT +# +# =========================== end_copyright_notice ============================= #===----------------------------------------------------------------------===// # @@ -47,7 +25,7 @@ #IntrinsicsProperties = ["None", "NoMem", "ReadArgMem", "ReadMem", "ReadWriteArgMem", "NoReturn", "NoDuplicate", "Convergent"] #IntrinsicsProperties may be specified as a comma separated list(e.g., "Convergent,NoMem") # -# EX. "blah": [{return_type}, [arg1_type, arg2_type.....], Property] +# EX. "blah": {"result" : {return_type}, "arguments" : [arg1_type, arg2_type.....], "attributes" : Property } # # The "any" type can be followed by a default type if a type is not explicitly specified : Ex. "any:int" # @@ -55,6 +33,17 @@ # 1 - LLVMMatchType<1> # {int} - LLVMMatchType<{int}> +#------------ Supported platforms ---------------------- +# Every intrinsic has optinal field "platforms" : "CPU" +# CPU can be any from "platforms" in Intrinsics.py or "ALL" +# when field is absent - ALL by default +# additional commands : +# "CPU" = "-SKL" - unsupported since SKL +# "CPU" = "KBL+" - supported from KBL +# "CPU" = "~ICLLP" - unsupported on ICLLP +# CPU can be list: +# ["CNL+", "KBL"] - supported on KBL and all started from CNL +# ["ALL", "~TGLLP"] - supported everyvere except TGLLP Imported_Intrinsics = \ { @@ -62,8 +51,14 @@ ##-------------------------------------------------------------------- ## Start and end markers of the genx intrinsic enum values. This relies on ## tablegen outputting the intrinsics in sorted by name order. - "aaaabegin" : ["anyvector",[],"None"], - "zzzzend" : ["anyvector",[],"None"], + "aaaabegin" : { "result" : "anyvector", + "arguments" : [], + "attributes" : "None" + }, + "zzzzend" : { "result" : "anyvector", + "arguments" : [], + "attributes" : "None" + }, ### ``llvm.genx.alloca.`` : CMC internal, no VISA ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -74,7 +69,10 @@ ### ### * Return value: offset in stack surface ### - "alloca" : ["anyint",["any"],"None"], + "alloca" : { "result" : "anyint", + "arguments" : ["any"], + "attributes" : "None" + }, ### ``llvm.genx.faddr.`` : take an address of the function provided ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -86,7 +84,10 @@ ### ### * Return value: i64 address ready to be consumed by an indirect call ### - "faddr" : ["long", ["any"], "NoMem"], + "faddr" : { "result" : "long", + "arguments" : ["any"], + "attributes" : "NoMem" + }, ## -------------------------------- ### Region/element access intrinsics @@ -132,8 +133,14 @@ ### cross a multiple of parent width boundary. This is used by the backend ### to determine whether the region can be collapsed into another region. ### - "rdregioni" : ["anyint",["anyvector","int","int","int","anyint","int"],"NoMem"], - "rdregionf" : ["anyfloat",["anyvector","int","int","int","anyint","int"],"NoMem"], + "rdregioni" : { "result" : "anyint", + "arguments" : ["anyvector","int","int","int","anyint","int"], + "attributes" : "NoMem" + }, + "rdregionf" : { "result" : "anyfloat", + "arguments" : ["anyvector","int","int","int","anyint","int"], + "attributes" : "NoMem" + }, ### ``llvm.genx.wrregion*`` : write a region, direct or single-indirect ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -189,8 +196,14 @@ ### cross a multiple of parent width boundary. This is used by the backend ### to determine whether the region can be collapsed into another region. ### - "wrregioni" : ["anyvector",[0,"anyint","int","int","int","anyint","int","anyint"],"NoMem"], - "wrregionf" : ["anyvector",[0,"anyfloat","int","int","int","anyint","int","anyint"],"NoMem"], + "wrregioni" : { "result" : "anyvector", + "arguments" : [0,"anyint","int","int","int","anyint","int","anyint"], + "attributes" : "NoMem" + }, + "wrregionf" : { "result" : "anyvector", + "arguments" : [0,"anyfloat","int","int","int","anyint","int","anyint"], + "attributes" : "NoMem" + }, ### ``llvm.genx.vstore..`` : store a vector value into memory ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -203,7 +216,10 @@ ### * arg0: the vector to read from ### * arg1: the memory to be accessed ### - "vstore" : ["void",["anyvector","anyptr"],"None"], + "vstore" : { "result" : "void", + "arguments" : ["anyvector","anyptr"], + "attributes" : "None" + }, ### ``llvm.genx.vload..`` : load a vector value from memory ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -216,7 +232,10 @@ ### * arg0: the memory to be accessed (overloaded) ### * Return value: the vector value read ### - "vload" : ["anyvector",["anyptr"],"None"], + "vload" : { "result" : "anyvector", + "arguments" : ["anyptr"], + "attributes" : "None" + }, ## ------------------------------ ### ALU type conversion intrinsics @@ -230,7 +249,10 @@ ### * Return value: converted value, any scalar or vector integer type ### (treated as signed) with same vector width as arg0 ### - "fptosi_sat" : ["anyint",["anyfloat"],"NoMem"], + "fptosi_sat" : { "result" : "anyint", + "arguments" : ["anyfloat"], + "attributes" : "NoMem" + }, ### ``llvm.genx.fptoui.sat..`` : convert floating point to unsigned integer with saturate ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -240,7 +262,10 @@ ### * Return value: converted value, any scalar or vector integer type ### (treated as unsigned) with same vector width as arg0 ### - "fptoui_sat" : ["anyint",["anyfloat"],"NoMem"], + "fptoui_sat" : { "result" : "anyint", + "arguments" : ["anyfloat"], + "attributes" : "NoMem" + }, ### ``llvm.genx.sat..`` : floating point saturate ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -258,7 +283,10 @@ ### Instead, any integer operation that supports saturation needs an ### intrinsic for the saturating variant. ### - "sat" : ["anyfloat",[0],"NoMem"], + "sat" : { "result" : "anyfloat", + "arguments" : [0], + "attributes" : "NoMem" + }, ### ``llvm.genx.*trunc.sat..`` : integer truncation with saturation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -272,10 +300,22 @@ ### * Return value: truncated value, any scalar or vector integer type ### with same vector width as arg0 ### - "sstrunc_sat" : ["anyint",["anyint"],"NoMem"], - "sutrunc_sat" : ["anyint",["anyint"],"NoMem"], - "ustrunc_sat" : ["anyint",["anyint"],"NoMem"], - "uutrunc_sat" : ["anyint",["anyint"],"NoMem"], + "sstrunc_sat" : { "result" : "anyint", + "arguments" : ["anyint"], + "attributes" : "NoMem" + }, + "sutrunc_sat" : { "result" : "anyint", + "arguments" : ["anyint"], + "attributes" : "NoMem" + }, + "ustrunc_sat" : { "result" : "anyint", + "arguments" : ["anyint"], + "attributes" : "NoMem" + }, + "uutrunc_sat" : { "result" : "anyint", + "arguments" : ["anyint"], + "attributes" : "NoMem" + }, ## ------------------- ### Modifier intrinsics @@ -293,8 +333,14 @@ ### ### * Return value: result, same type ### - "absf" : ["anyfloat",[0],"NoMem"], - "absi" : ["anyint",[0],"NoMem"], + "absf" : { "result" : "anyfloat", + "arguments" : [0], + "attributes" : "NoMem" + }, + "absi" : { "result" : "anyint", + "arguments" : [0], + "attributes" : "NoMem" + }, ## ---------------------------- ### Boolean reduction intrinsics @@ -307,7 +353,10 @@ ### ### * Return value: i1 result ### - "all" : ["bool",["anyint"],"NoMem"], + "all" : { "result" : "bool", + "arguments" : ["anyint"], + "attributes" : "NoMem" + }, ### ``llvm.genx.any.`` : true if any input element is true ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -316,7 +365,10 @@ ### ### * Return value: i1 result ### - "any" : ["bool",["anyint"],"NoMem"], + "any" : { "result" : "bool", + "arguments" : ["anyint"], + "attributes" : "NoMem" + }, ## ---------------------------- ### SIMD control flow intrinsics @@ -496,7 +548,10 @@ ### Note that SimdCond has the same sense as in the Gen goto instruction, but ### the opposite sense to that in a vISA forward goto instruction. ### - "simdcf_goto" : [["anyvector","anyvector","bool"],[0,1,1],"NoMem"], + "simdcf_goto" : { "result" : ["anyvector","anyvector","bool"], + "arguments" : [0,1,1], + "attributes" : "NoMem" + }, ### ``llvm.genx.simdcf.join..`` : join instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -539,14 +594,20 @@ ### still disabled, then BranchCond is true and the conditional branch in which it ### is used branches to the next join point in sequence. ### - "simdcf_join" : [["anyvector","bool"],[0,"anyvector"],"None"], + "simdcf_join" : { "result" : ["anyvector","bool"], + "arguments" : [0,"anyvector"], + "attributes" : "None" + }, ### ``llvm.genx.simdcf.savemask.`` : ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ### ### * arg0: OldEM (old execution mask): v32i1 (overloaded) ### * ret: temp i32 for saving the oldEM - "simdcf_savemask" : ["int",["anyvector"],"WriteMem,SideEffects"], + "simdcf_savemask" : { "result" : "int", + "arguments" : ["anyvector"], + "attributes" : "WriteMem,SideEffects" + }, ### ``llvm.genx.simdcf.unmask.`` : ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -554,7 +615,10 @@ ### * arg0: temp i32 from savemask ### * arg1: i32 constant, should be all-one ### * ret: NewEM (updated execution mask, all-one): v32i1 - "simdcf_unmask" : ["anyvector",["int","int"],"WriteMem,SideEffects"], + "simdcf_unmask" : { "result" : "anyvector", + "arguments" : ["int","int"], + "attributes" : "WriteMem,SideEffects" + }, ### ``llvm.genx.simdcf.remask.`` : ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -564,7 +628,10 @@ ### ### Return value: NewEM (updated execution mask): v32i1 ### - "simdcf_remask" : ["anyvector",[0,"int"],"WriteMem,SideEffects"], + "simdcf_remask" : { "result" : "anyvector", + "arguments" : [0,"int"], + "attributes" : "WriteMem,SideEffects" + }, ### ``llvm.genx.simdcf.get.em`` : ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -582,7 +649,10 @@ ### EM is different in different locations even when the ### dominance of DF is not corrupted. ### - "simdcf_get_em" : ["anyvector",[0],"WriteMem,SideEffects"], + "simdcf_get_em" : { "result" : "anyvector", + "arguments" : [0], + "attributes" : "WriteMem,SideEffects" + }, ### -------------- ### ALU intrinsics @@ -611,10 +681,22 @@ ### For an fp add, use the LLVM IR FAdd instruction, followed by ### llvm.genx.sat if saturation is required. ### - "ssadd_sat" : ["anyint",["anyint",1],"NoMem"], - "suadd_sat" : ["anyint",["anyint",1],"NoMem"], - "usadd_sat" : ["anyint",["anyint",1],"NoMem"], - "uuadd_sat" : ["anyint",["anyint",1],"NoMem"], + "ssadd_sat" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "suadd_sat" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "usadd_sat" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "uuadd_sat" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, ### asr ### ^^^ @@ -636,10 +718,22 @@ ### * Return value: result, any scalar/vector integer type (not i64) ### with same vector width ### - "ssavg" : ["anyint",["anyint",1],"NoMem"], - "suavg" : ["anyint",["anyint",1],"NoMem"], - "usavg" : ["anyint",["anyint",1],"NoMem"], - "uuavg" : ["anyint",["anyint",1],"NoMem"], + "ssavg" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "suavg" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "usavg" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "uuavg" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, ### ``llvm.genx.*avg.sat..`` : integer averaging with saturation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -654,10 +748,22 @@ ### * Return value: result, any scalar/vector integer type (not i64) ### with same vector width ### - "ssavg_sat" : ["anyint",["anyint",1],"NoMem"], - "suavg_sat" : ["anyint",["anyint",1],"NoMem"], - "usavg_sat" : ["anyint",["anyint",1],"NoMem"], - "uuavg_sat" : ["anyint",["anyint",1],"NoMem"], + "ssavg_sat" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "suavg_sat" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "usavg_sat" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "uuavg_sat" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, ### ``llvm.genx.*bfe.`` : bitfield extract ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -670,8 +776,14 @@ ### ### * Return value: result, same type as arg0 ### - "sbfe" : ["anyint",[0,0,0],"NoMem"], - "ubfe" : ["anyint",[0,0,0],"NoMem"], + "sbfe" : { "result" : "anyint", + "arguments" : [0,0,0], + "attributes" : "NoMem" + }, + "ubfe" : { "result" : "anyint", + "arguments" : [0,0,0], + "attributes" : "NoMem" + }, ### ``llvm.genx.bfi.`` : bitfield insert ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -683,7 +795,10 @@ ### ### * Return value: result, same type as arg0 ### - "bfi" : ["anyint",[0,0,0,0],"NoMem"], + "bfi" : { "result" : "anyint", + "arguments" : [0,0,0,0], + "attributes" : "NoMem" + }, ### ``llvm.genx.bfrev.`` : reverse bits ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -692,7 +807,10 @@ ### ### * Return value: result, same type as arg0 ### - "bfrev" : ["anyint",[0],"NoMem"], + "bfrev" : { "result" : "anyint", + "arguments" : [0], + "attributes" : "NoMem" + }, ### ``llvm.genx.cbit..`` : count set bits ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -701,7 +819,10 @@ ### ### * Return value: result, int32 of same width as arg0 ### - "cbit" : ["anyint",["anyint"],"NoMem"], + "cbit" : { "result" : "anyint", + "arguments" : ["anyint"], + "attributes" : "NoMem" + }, ### cmp ### ^^^ @@ -716,7 +837,10 @@ ### ### * Return value: result, same type ### - "cos" : ["anyfloat",[0],"NoMem"], + "cos" : { "result" : "anyfloat", + "arguments" : [0], + "attributes" : "NoMem" + }, ### div ### ^^^ @@ -732,7 +856,10 @@ ### ### * Return value: result, same type ### - "ieee_div" : ["anyfloat",[0,0],"NoMem"], + "ieee_div" : { "result" : "anyfloat", + "arguments" : [0,0], + "attributes" : "NoMem" + }, ### ``llvm.genx.dp2.`` : dp2 instruction (dot product on groups of 4 elements) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -742,7 +869,10 @@ ### ### * Return value: result, same type ### - "dp2" : ["anyfloat",[0,0],"NoMem"], + "dp2" : { "result" : "anyfloat", + "arguments" : [0,0], + "attributes" : "NoMem" + }, ### ``llvm.genx.dp3.`` : dp3 instruction (dot product on groups of 3 elements) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -752,7 +882,10 @@ ### ### * Return value: result, same type ### - "dp3" : ["anyfloat",[0,0],"NoMem"], + "dp3" : { "result" : "anyfloat", + "arguments" : [0,0], + "attributes" : "NoMem" + }, ### ``llvm.genx.dp4.`` : dp4 instruction (dot product on groups of 4 elements) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -762,7 +895,10 @@ ### ### * Return value: result, same type ### - "dp4" : ["anyfloat",[0,0],"NoMem"], + "dp4" : { "result" : "anyfloat", + "arguments" : [0,0], + "attributes" : "NoMem" + }, ### ``llvm.genx.dph.`` : dph instruction (dot product homogenous) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -772,7 +908,10 @@ ### ### * Return value: result, same type ### - "dph" : ["anyfloat",[0,0],"NoMem"], + "dph" : { "result" : "anyfloat", + "arguments" : [0,0], + "attributes" : "NoMem" + }, ### ``llvm.genx.exp.`` : base 2 exponent ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -781,7 +920,10 @@ ### ### * Return value: result, same type ### - "exp" : ["anyfloat",[0],"NoMem"], + "exp" : { "result" : "anyfloat", + "arguments" : [0], + "attributes" : "NoMem" + }, ### ``llvm.genx.*fbh.`` : find bit high ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -792,8 +934,14 @@ ### ### * Return value: result, same type ### - "sfbh" : ["anyint",[0],"NoMem"], - "ufbh" : ["anyint",[0],"NoMem"], + "sfbh" : { "result" : "anyint", + "arguments" : [0], + "attributes" : "NoMem" + }, + "ufbh" : { "result" : "anyint", + "arguments" : [0], + "attributes" : "NoMem" + }, ### ``llvm.genx.fbl.`` : find bit low ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -802,7 +950,10 @@ ### ### * Return value: result, same type ### - "fbl" : ["anyint",[0],"NoMem"], + "fbl" : { "result" : "anyint", + "arguments" : [0], + "attributes" : "NoMem" + }, ### ``llvm.genx.frc.`` : fractional part ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -811,7 +962,10 @@ ### ### * Return value: result, same type ### - "frc" : ["anyfloat",[0],"NoMem"], + "frc" : { "result" : "anyfloat", + "arguments" : [0], + "attributes" : "NoMem" + }, ### ``llvm.genx.inv.`` : reciprocal ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -820,7 +974,10 @@ ### ### * Return value: result, same type ### - "inv" : ["anyfloat",[0],"NoMem"], + "inv" : { "result" : "anyfloat", + "arguments" : [0], + "attributes" : "NoMem" + }, ### ``llvm.genx.line.`` : linear equation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -830,7 +987,10 @@ ### ### * Return value: result, same type as arg1 ### - "line" : ["anyfloat",["float4",0],"NoMem"], + "line" : { "result" : "anyfloat", + "arguments" : ["float4",0], + "attributes" : "NoMem" + }, ### ``llvm.genx.log.`` : base 2 logarithm ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -839,7 +999,10 @@ ### ### * Return value: result, same type ### - "log" : ["anyfloat",[0],"NoMem"], + "log" : { "result" : "anyfloat", + "arguments" : [0], + "attributes" : "NoMem" + }, ### ``llvm.genx.lrp.`` : linear interpolation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -850,7 +1013,10 @@ ### ### * Return value: result, same type ### - "lrp" : ["anyfloat",[0,0,0],"NoMem"], + "lrp" : { "result" : "anyfloat", + "arguments" : [0,0,0], + "attributes" : "NoMem" + }, ### ``llvm.genx.lzd.`` : leading zero detection ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -859,7 +1025,10 @@ ### ### * Return value: result, same type ### - "lzd" : ["anyint",[0],"NoMem"], + "lzd" : { "result" : "anyint", + "arguments" : [0], + "attributes" : "NoMem" + }, ### ``llvm.genx.*mad..`` : mad instruction, no saturation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -877,10 +1046,22 @@ ### * arg1: second input, same type as arg0 ### * arg2: third input, same type as result ### - "ssmad" : ["anyint",["anyint",1,0],"NoMem"], - "sumad" : ["anyint",["anyint",1,0],"NoMem"], - "usmad" : ["anyint",["anyint",1,0],"NoMem"], - "uumad" : ["anyint",["anyint",1,0],"NoMem"], + "ssmad" : { "result" : "anyint", + "arguments" : ["anyint",1,0], + "attributes" : "NoMem" + }, + "sumad" : { "result" : "anyint", + "arguments" : ["anyint",1,0], + "attributes" : "NoMem" + }, + "usmad" : { "result" : "anyint", + "arguments" : ["anyint",1,0], + "attributes" : "NoMem" + }, + "uumad" : { "result" : "anyint", + "arguments" : ["anyint",1,0], + "attributes" : "NoMem" + }, ### ``llvm.genx.*mad.sat..`` : mad instruction with saturation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -898,10 +1079,22 @@ ### * arg1: second input, same type as arg0 ### * arg2: third input, same type as result ### - "ssmad_sat" : ["anyint",["anyint",1,0],"NoMem"], - "sumad_sat" : ["anyint",["anyint",1,0],"NoMem"], - "usmad_sat" : ["anyint",["anyint",1,0],"NoMem"], - "uumad_sat" : ["anyint",["anyint",1,0],"NoMem"], + "ssmad_sat" : { "result" : "anyint", + "arguments" : ["anyint",1,0], + "attributes" : "NoMem" + }, + "sumad_sat" : { "result" : "anyint", + "arguments" : ["anyint",1,0], + "attributes" : "NoMem" + }, + "usmad_sat" : { "result" : "anyint", + "arguments" : ["anyint",1,0], + "attributes" : "NoMem" + }, + "uumad_sat" : { "result" : "anyint", + "arguments" : ["anyint",1,0], + "attributes" : "NoMem" + }, ### ``llvm.genx.*max..`` : max instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -920,9 +1113,18 @@ ### by this non-saturating max followed by the applicable one of the ### saturating trunc intrinsics. ### - "smax" : ["anyint",["anyint",1],"NoMem"], - "umax" : ["anyint",["anyint",1],"NoMem"], - "fmax" : ["anyfloat",["anyfloat",1],"NoMem"], + "smax" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "umax" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "fmax" : { "result" : "anyfloat", + "arguments" : ["anyfloat",1], + "attributes" : "NoMem" + }, ### ``llvm.genx.*min.`` : min instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -941,9 +1143,18 @@ ### by this non-saturating min followed by the applicable one of the ### saturating trunc intrinsics. ### - "smin" : ["anyint",["anyint",1],"NoMem"], - "umin" : ["anyint",["anyint",1],"NoMem"], - "fmin" : ["anyfloat",["anyfloat",1],"NoMem"], + "smin" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "umin" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "fmin" : { "result" : "anyfloat", + "arguments" : ["anyfloat",1], + "attributes" : "NoMem" + }, ### mod ### ^^^ @@ -951,6 +1162,29 @@ ### cover vISA functionality ### +### imad +### ^^^^ +### +### ``llvm.genx.*imad.<{hi, lo}>.`` : imad instruction +### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +### * ``llvm.genx.simad`` : result and operands signed +### * ``llvm.genx.uimad`` : result and operands unsigned +### +### result := {hi, lo} = arg0 * arg1 + arg2 +### +### * arg0: first input, i32 scalar/vector integer type +### * arg1: second input, same type as arg0 +### * arg2: third input, same type as arg0 +### + "simad" : { "result" : ["anyint", "anyint"], + "arguments" : [0, 0, 0], + "attributes" : "NoMem" + }, + "uimad" : { "result" : ["anyint", "anyint"], + "arguments" : [0, 0, 0], + "attributes" : "NoMem" + }, + ### mul ### ^^^ ### Still need non-saaturating mul intrinsic as def-hoist/copy-prop in jitter @@ -971,10 +1205,22 @@ ### * arg0: first input, any scalar/vector integer type (not i64) (overloaded) ### * arg1: second input, same type as arg0 ### - "ssmul" : ["anyint",["anyint",1],"NoMem"], - "sumul" : ["anyint",["anyint",1],"NoMem"], - "usmul" : ["anyint",["anyint",1],"NoMem"], - "uumul" : ["anyint",["anyint",1],"NoMem"], + "ssmul" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "sumul" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "usmul" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "uumul" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, ### ``llvm.genx.*mul.sat..`` : mul instruction with saturation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -992,10 +1238,22 @@ ### For an fp mul, use the LLVM IR FMul instruction, followed by ### llvm.genx.sat if saturation is required. ### - "ssmul_sat" : ["anyint",["anyint",1],"NoMem"], - "sumul_sat" : ["anyint",["anyint",1],"NoMem"], - "usmul_sat" : ["anyint",["anyint",1],"NoMem"], - "uumul_sat" : ["anyint",["anyint",1],"NoMem"], + "ssmul_sat" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "sumul_sat" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "usmul_sat" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "uumul_sat" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, ### ``llvm.genx.*mulh..`` : mulh instruction, no saturation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1007,8 +1265,14 @@ ### ### * Return value: result, same type as arg0 ### - "smulh" : ["anyint",["anyint",1],"NoMem"], - "umulh" : ["anyint",["anyint",1],"NoMem"], + "smulh" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "umulh" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, ### not ### ^^^ @@ -1028,7 +1292,10 @@ ### ### * Return value: result, vector float with half as many elements as arg1 ### - "pln" : ["anyfloat",["float4","anyfloat"],"NoMem"], + "pln" : { "result" : "anyfloat", + "arguments" : ["float4","anyfloat"], + "attributes" : "NoMem" + }, ### ``llvm.genx.pow.`` : power ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1038,7 +1305,10 @@ ### ### * Return value: result, same type ### - "pow" : ["anyfloat",[0,0],"NoMem"], + "pow" : { "result" : "anyfloat", + "arguments" : [0,0], + "attributes" : "NoMem" + }, ### ``llvm.genx.rndd.`` : round down ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1047,7 +1317,10 @@ ### ### * Return value: result, same type ### - "rndd" : ["anyfloat",[0],"NoMem"], + "rndd" : { "result" : "anyfloat", + "arguments" : [0], + "attributes" : "NoMem" + }, ### ``llvm.genx.rnde.`` : round to even ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1056,7 +1329,10 @@ ### ### * Return value: result, same type ### - "rnde" : ["anyfloat",[0],"NoMem"], + "rnde" : { "result" : "anyfloat", + "arguments" : [0], + "attributes" : "NoMem" + }, ### ``llvm.genx.rndu.`` : round up ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1065,7 +1341,10 @@ ### ### * Return value: result, same type ### - "rndu" : ["anyfloat",[0],"NoMem"], + "rndu" : { "result" : "anyfloat", + "arguments" : [0], + "attributes" : "NoMem" + }, ### ``llvm.genx.rndz.`` : round to zero ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1074,7 +1353,10 @@ ### ### * Return value: result, same type ### - "rndz" : ["anyfloat",[0],"NoMem"], + "rndz" : { "result" : "anyfloat", + "arguments" : [0], + "attributes" : "NoMem" + }, ### ``llvm.genx.rsqrt.`` : reciprocal square root ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1083,7 +1365,10 @@ ### ### * Return value: result, same type ### - "rsqrt" : ["anyfloat",[0],"NoMem"], + "rsqrt" : { "result" : "anyfloat", + "arguments" : [0], + "attributes" : "NoMem" + }, ### ``llvm.genx.*sad2..`` : two-wide sum of absolute differences ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1095,8 +1380,14 @@ ### ### * Return value: result, vector of i16 of same vector width ### - "ssad2" : ["anyint",["anyint",1],"NoMem"], - "usad2" : ["anyint",["anyint",1],"NoMem"], + "ssad2" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "usad2" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, ### ``llvm.genx.*sad2add..`` : two-wide sum of absolute differences and add ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1111,10 +1402,22 @@ ### ### * Return value: result, same type as arg2 ### - "sssad2add" : ["anyint",["anyint",1,0],"NoMem"], - "uusad2add" : ["anyint",["anyint",1,0],"NoMem"], - "ussad2add" : ["anyint",["anyint",1,0],"NoMem"], - "susad2add" : ["anyint",["anyint",1,0],"NoMem"], + "sssad2add" : { "result" : "anyint", + "arguments" : ["anyint",1,0], + "attributes" : "NoMem" + }, + "uusad2add" : { "result" : "anyint", + "arguments" : ["anyint",1,0], + "attributes" : "NoMem" + }, + "ussad2add" : { "result" : "anyint", + "arguments" : ["anyint",1,0], + "attributes" : "NoMem" + }, + "susad2add" : { "result" : "anyint", + "arguments" : ["anyint",1,0], + "attributes" : "NoMem" + }, ### ``llvm.genx.*sad2add.sat..`` : two-wide sum of absolute differences and add, saturated ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1129,10 +1432,22 @@ ### ### * Return value: result, same type as arg2 ### - "sssad2add_sat" : ["anyint",["anyint",1,0],"NoMem"], - "uusad2add_sat" : ["anyint",["anyint",1,0],"NoMem"], - "ussad2add_sat" : ["anyint",["anyint",1,0],"NoMem"], - "susad2add_sat" : ["anyint",["anyint",1,0],"NoMem"], + "sssad2add_sat" : { "result" : "anyint", + "arguments" : ["anyint",1,0], + "attributes" : "NoMem" + }, + "uusad2add_sat" : { "result" : "anyint", + "arguments" : ["anyint",1,0], + "attributes" : "NoMem" + }, + "ussad2add_sat" : { "result" : "anyint", + "arguments" : ["anyint",1,0], + "attributes" : "NoMem" + }, + "susad2add_sat" : { "result" : "anyint", + "arguments" : ["anyint",1,0], + "attributes" : "NoMem" + }, ### ``llvm.genx.*shl..`` : shl instruction, no saturation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1147,10 +1462,22 @@ ### * Return value: result, any scalar or vector integer type with same ### vector width, even i64 ### - "ssshl" : ["anyint",["anyint",1],"NoMem"], - "sushl" : ["anyint",["anyint",1],"NoMem"], - "usshl" : ["anyint",["anyint",1],"NoMem"], - "uushl" : ["anyint",["anyint",1],"NoMem"], + "ssshl" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "sushl" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "usshl" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "uushl" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, ### ``llvm.genx.*shl.sat..`` : shl instruction with saturation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1165,10 +1492,22 @@ ### * Return value: result, any scalar/vector integer type with same ### vector width, even i64 ### - "ssshl_sat" : ["anyint",["anyint",1],"NoMem"], - "sushl_sat" : ["anyint",["anyint",1],"NoMem"], - "usshl_sat" : ["anyint",["anyint",1],"NoMem"], - "uushl_sat" : ["anyint",["anyint",1],"NoMem"], + "ssshl_sat" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "sushl_sat" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "usshl_sat" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "uushl_sat" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, ### shr ### ^^^ @@ -1188,8 +1527,14 @@ ### * Return value: result, any scalar or vector integer type with same ### vector width (even i64) ### - "rol" : ["anyint",["anyint",1],"NoMem"], - "ror" : ["anyint",["anyint",1],"NoMem"], + "rol" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "ror" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, ### ``llvm.genx.sin.`` : reciprocal square root ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1198,7 +1543,10 @@ ### ### * Return value: result, same type ### - "sin" : ["anyfloat",[0],"NoMem"], + "sin" : { "result" : "anyfloat", + "arguments" : [0], + "attributes" : "NoMem" + }, ### ``llvm.genx.sqrt.`` : reciprocal square root ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1207,7 +1555,10 @@ ### ### * Return value: result, same type ### - "sqrt" : ["anyfloat",[0],"NoMem"], + "sqrt" : { "result" : "anyfloat", + "arguments" : [0], + "attributes" : "NoMem" + }, ### ``llvm.genx.ieee.sqrt.`` : reciprocal square root, IEEE variant ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1216,7 +1567,10 @@ ### ### * Return value: result, same type ### - "ieee_sqrt" : ["anyfloat",[0],"NoMem"], + "ieee_sqrt" : { "result" : "anyfloat", + "arguments" : [0], + "attributes" : "NoMem" + }, ### ``llvm.genx.dpas...`` : dpas instruction (Dot Product Accumulate Systolic) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1228,7 +1582,10 @@ ### ### * Return value: result, same type as arg0 ### - "dpas" : ["anyvector",[0,"anyvector","anyvector","int"],"NoMem"], + "dpas" : { "result" : "anyvector", + "arguments" : [0,"anyvector","anyvector","int"], + "attributes" : "NoMem" + }, ### ``llvm.genx.dpas2....`` : dpas instruction (Dot Product Accumulate Systolic) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1245,7 +1602,10 @@ ### ### * Return value: result ### - "dpas2" : ["anyvector",["anyvector","anyvector","anyvector","int","int", "int", "int", "int", "int"],"NoMem"], + "dpas2" : { "result" : "anyvector", + "arguments" : ["anyvector","anyvector","anyvector","int","int", "int", "int", "int", "int"], + "attributes" : "NoMem" + }, ### ``llvm.genx.dpas.nosrc0...`` : dpas instruction (Dot Product Accumulate Systolic) with no src0 ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1256,7 +1616,10 @@ ### ### * Return value: result ### - "dpas_nosrc0" : ["anyvector",["anyvector","anyvector","int"],"NoMem"], + "dpas_nosrc0" : { "result" : "anyvector", + "arguments" : ["anyvector","anyvector","int"], + "attributes" : "NoMem" + }, ### ``llvm.genx.dpasw...`` : dpasw instruction (Dot Product Accumulate Systolic) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1268,7 +1631,10 @@ ### ### * Return value: result, same type as arg0 ### - "dpasw" : ["anyvector",[0,"anyvector","anyvector","int"],"NoMem"], + "dpasw" : { "result" : "anyvector", + "arguments" : [0,"anyvector","anyvector","int"], + "attributes" : "NoMem" + }, ### ``llvm.genx.dpasw.nosrc0...`` : dpasw instruction (Dot Product Accumulate Systolic) with no src0 ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1279,7 +1645,10 @@ ### ### * Return value: result ### - "dpasw_nosrc0" : ["anyvector",["anyvector","anyvector","int"],"NoMem"], + "dpasw_nosrc0" : { "result" : "anyvector", + "arguments" : ["anyvector","anyvector","int"], + "attributes" : "NoMem" + }, ### ``llvm.genx.*dp4a*....`` : dp4a instruction (Dot Product 4 Accumulate) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1299,14 +1668,38 @@ ### ### * Return value: result, vector integer type ### - "ssdp4a" : ["anyvector",["anyvector","anyvector","anyvector"],"NoMem"], - "sudp4a" : ["anyvector",["anyvector","anyvector","anyvector"],"NoMem"], - "usdp4a" : ["anyvector",["anyvector","anyvector","anyvector"],"NoMem"], - "uudp4a" : ["anyvector",["anyvector","anyvector","anyvector"],"NoMem"], - "ssdp4a_sat" : ["anyvector",["anyvector","anyvector","anyvector"],"NoMem"], - "sudp4a_sat" : ["anyvector",["anyvector","anyvector","anyvector"],"NoMem"], - "usdp4a_sat" : ["anyvector",["anyvector","anyvector","anyvector"],"NoMem"], - "uudp4a_sat" : ["anyvector",["anyvector","anyvector","anyvector"],"NoMem"], + "ssdp4a" : { "result" : "anyvector", + "arguments" : ["anyvector","anyvector","anyvector"], + "attributes" : "NoMem" + }, + "sudp4a" : { "result" : "anyvector", + "arguments" : ["anyvector","anyvector","anyvector"], + "attributes" : "NoMem" + }, + "usdp4a" : { "result" : "anyvector", + "arguments" : ["anyvector","anyvector","anyvector"], + "attributes" : "NoMem" + }, + "uudp4a" : { "result" : "anyvector", + "arguments" : ["anyvector","anyvector","anyvector"], + "attributes" : "NoMem" + }, + "ssdp4a_sat" : { "result" : "anyvector", + "arguments" : ["anyvector","anyvector","anyvector"], + "attributes" : "NoMem" + }, + "sudp4a_sat" : { "result" : "anyvector", + "arguments" : ["anyvector","anyvector","anyvector"], + "attributes" : "NoMem" + }, + "usdp4a_sat" : { "result" : "anyvector", + "arguments" : ["anyvector","anyvector","anyvector"], + "attributes" : "NoMem" + }, + "uudp4a_sat" : { "result" : "anyvector", + "arguments" : ["anyvector","anyvector","anyvector"], + "attributes" : "NoMem" + }, ### addc ### ^^^^ @@ -1317,7 +1710,10 @@ ### ### * arg0: first input, i32 scalar/vector integer type ### * arg1: second input, same type as arg0 - "addc" : [["anyint", "anyint"], [0, 0], "NoMem"], + "addc" : { "result" : ["anyint", "anyint"], + "arguments" : [0, 0], + "attributes" : "NoMem" + }, ### subb ### ^^^^ @@ -1328,7 +1724,10 @@ ### ### * arg0: first input, i32 scalar/vector integer type ### * arg1: second input, same type as arg0 - "subb" : [["anyint", "anyint"], [0, 0], "NoMem"], + "subb" : { "result" : ["anyint", "anyint"], + "arguments" : [0, 0], + "attributes" : "NoMem" + }, ### add3 ### ^^^^ @@ -1340,7 +1739,10 @@ ### * arg0: first input, any scalar/vector integer type, i16/i32 (overloaded) ### * arg1: second input, same type as arg0 ### * arg2: third input, same type as arg0 - "add3" : ["anyint",["anyint",1,1],"NoMem"], + "add3" : { "result" : "anyint", + "arguments" : ["anyint",1,1], + "attributes" : "NoMem" + }, ### ``llvm.genx.*add3.sat..`` : add3 instruction with saturation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1356,10 +1758,37 @@ ### * Return value: result, any scalar or vector integer type with same ### vector width ### - "ssadd3_sat" : ["anyint",["anyint",1,1],"NoMem"], - "suadd3_sat" : ["anyint",["anyint",1,1],"NoMem"], - "usadd3_sat" : ["anyint",["anyint",1,1],"NoMem"], - "uuadd3_sat" : ["anyint",["anyint",1,1],"NoMem"], + "ssadd3_sat" : { "result" : "anyint", + "arguments" : ["anyint",1,1], + "attributes" : "NoMem" + }, + "suadd3_sat" : { "result" : "anyint", + "arguments" : ["anyint",1,1], + "attributes" : "NoMem" + }, + "usadd3_sat" : { "result" : "anyint", + "arguments" : ["anyint",1,1], + "attributes" : "NoMem" + }, + "uuadd3_sat" : { "result" : "anyint", + "arguments" : ["anyint",1,1], + "attributes" : "NoMem" + }, + +### add3c +### ^^^^^ +### +### ``llvm.genx.add3c.<{carry, add3}>.`` : add3 with carry +### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +### * ``llvm.genx.add3c`` : +### +### * arg0: first input, i32 scalar/vector integer type +### * arg1: second input, same type as arg0 +### * arg2: third input, same type as arg0 + "add3c" : { "result" : ["anyint", "intvector"], + "arguments" : ["anyint",1,1,1], + "attributes" : "NoMem" + }, ### bfn ### ^^^ @@ -1372,7 +1801,472 @@ ### * arg1: second input, same type as arg0 ### * arg2: third input, same type as arg0 ### * arg3: fourth input, byte, constant - "bfn" : ["anyint",["anyint",1,1,"char"],"NoMem"], + "bfn" : { "result" : "anyint", + "arguments" : ["anyint",1,1,"char"], + "attributes" : "NoMem" + }, + +### srnd +### ^^^ +### +### ``llvm.genx.srnd...`` : srnd instruction +### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +### * ``llvm.genx.srnd`` : +### +### * arg0: first input, any vector f32/hf16 type +### * arg1: second input, same type as arg0 +### * Return value: result, must be half if arg0 is f32, or ub if arg0 is half. + "srnd" : { "result" : "anyvector", + "arguments" : ["anyvector", "anyvector"], + "attributes" : "NoMem" + }, + +### bf_cvt +### ^^^^^^ +### +### ``llvm.genx.bf.cvt..`` : bf_cvt instruction +### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +### * ``llvm.genx.bf.cvt`` : +### +### * arg0: first input, any scalar/vector bf/float type (overloaded) +### +### * Return value: result, must be float if arg0 is half, or half if arg0 is float. +### + "bf_cvt" : { "result" : "anyfloat", + "arguments" : ["anyfloat"], + "attributes" : "NoMem" + }, + +### tf32_cvt +### ^^^^^^ +### +### ``llvm.genx.tf32.cvt..`` : tf32_cvt instruction +### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +### * ``llvm.genx.tf32.cvt`` : +### +### * arg0: first input, vector float type fp32/hf16 +### +### * Return value: result, must be ud( Unsigned Doubleword) +### + "tf32_cvt" : { "result" : "anyvector", + "arguments" : ["anyvector"], + "attributes" : "NoMem" + }, + +### qf_cvt +### ^^^^^^ +### +### ``llvm.genx.qf.cvt..`` : qf_cvt instruction +### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +### * ``llvm.genx.qf.cvt`` : +### +### * arg0: first input, any scalar/vector i8/half type (overloaded) +### +### * Return value: result, must be i8 if arg0 is half, or half if arg0 is i8. +### + "qf_cvt" : { "result" : "anyvector", + "arguments" : ["anyvector"], + "attributes" : "NoMem" + }, + +### ``llvm.genx.lsc.load.*...`` : lsc_load instructions +### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +### +### * ``llvm.genx.lsc.load.slm`` : +### * ``llvm.genx.lsc.load.bti`` : +### * ``llvm.genx.lsc.load.stateless`` : +### * ``llvm.genx.lsc.prefetch.bti`` : +### * ``llvm.genx.lsc.prefetch.stateless`` : +### +### * Exec_size ignored unless operation is transposed (DataOrder == Tranpose) +### * arg0: {1,32}Xi1 predicate (overloaded) +### * arg1: i8 Subopcode, [MBZ] +### * arg2: i8 Caching behavior for L1, [MBC] +### * arg3: i8 Caching behavior for L3, [MBC] +### * arg4: i16 Address scale, [MBC] +### * arg5: i32 Immediate offset added to each address, [MBC] +### * arg6: i8 The dataum size, [MBC] +### * arg7: i8 Number of elements to load per address (vector size), [MBC] +### * arg8: i8 Indicates if the data is transposed during the transfer, [MBC] +### * arg9: i8 Channel mask for quad versions, [MBC] +### * arg10: {1,32}Xi{16,32,64} The vector register holding offsets (overloaded) +### for flat version Base Address + Offset[i] goes here +### * arg11: i32 surface to use for this operation. This can be an immediate or a register +### for flat and bindless version pass zero here +### +### * Return value: the value read or void for prefetch +### +### Cache mappings are: +### +### - 0 -> .df (default) +### - 1 -> .uc (uncached) +### - 2 -> .ca (cached) +### - 3 -> .wb (writeback) +### - 4 -> .wt (writethrough) +### - 5 -> .st (streaming) +### - 6 -> .ri (read-invalidate) +### +### Only certain combinations of CachingL1 with CachingL3 are valid on hardware. +### +### +---------+-----+-----------------------------------------------------------------------+ +### | L1 | L3 | Notes | +### +---------+-----+-----------------------------------------------------------------------+ +### | .df | .df | default behavior on both L1 and L3 (L3 uses MOCS settings) | +### +---------+-----+-----------------------------------------------------------------------+ +### | .uc | .uc | uncached (bypass) both L1 and L3 | +### +---------+-----+-----------------------------------------------------------------------+ +### | .st | .uc | streaming L1 / bypass L3 | +### +---------+-----+-----------------------------------------------------------------------+ +### | .uc | .ca | bypass L1 / cache in L3 | +### +---------+-----+-----------------------------------------------------------------------+ +### | .ca | .uc | cache in L1 / bypass L3 | +### +---------+-----+-----------------------------------------------------------------------+ +### | .ca | .ca | cache in both L1 and L3 | +### +---------+-----+-----------------------------------------------------------------------+ +### | .st | .ca | streaming L1 / cache in L3 | +### +---------+-----+-----------------------------------------------------------------------+ +### | .ri | .ca | read-invalidate (e.g. last-use) on L1 loads / cache in L3 | +### +---------+-----+-----------------------------------------------------------------------+ +### +### Immediate offset. The compiler may be able to fuse this add into the message, otherwise +### additional instructions are generated to honor the semantics. +### +### Dataum size mapping is +### +### - 1 = :u8 +### - 2 = :u16 +### - 3 = :u32 +### - 4 = :u64 +### - 5 = :u8u32 (load 8b, zero extend to 32b; store the opposite), +### - 6 = :u16u32 (load 8b, zero extend to 32b; store the opposite), +### - 7 = :u16u32h (load 16b into high 16 of each 32b; store the high 16) +### + "lsc_load_slm" : { "result" : "anyvector", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","int"], + "attributes" : "ReadMem" + }, + "lsc_load_stateless" : { "result" : "anyvector", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","int"], + "attributes" : "ReadMem" + }, + "lsc_load_bindless" : { "result" : "anyvector", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","int"], + "attributes" : "ReadMem" + }, + "lsc_load_bti" : { "result" : "anyvector", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","int"], + "attributes" : "ReadMem" + }, + "lsc_prefetch_slm" : { "result" : "void", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","int"], + "attributes" : "None" + }, + "lsc_prefetch_bti" : { "result" : "void", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","int"], + "attributes" : "None" + }, + "lsc_prefetch_stateless" : { "result" : "void", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","int"], + "attributes" : "None" + }, + "lsc_prefetch_bindless" : { "result" : "void", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","int"], + "attributes" : "None" + }, + "lsc_load_quad_slm" : { "result" : "anyvector", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","int"], + "attributes" : "ReadMem" + }, + "lsc_load_quad_stateless" : { "result" : "anyvector", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","int"], + "attributes" : "ReadMem" + }, + "lsc_load_quad_bindless" : { "result" : "anyvector", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","int"], + "attributes" : "ReadMem" + }, + "lsc_load_quad_bti" : { "result" : "anyvector", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","int"], + "attributes" : "ReadMem" + }, + +### ``llvm.genx.lsc.store.*...`` : lsc_store instructions +### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +### +### * ``llvm.genx.lsc.store.slm`` : +### * ``llvm.genx.lsc.store.bti`` : +### * ``llvm.genx.lsc.store.stateless`` : +### +### * Exec_size ignored unless operation is transposed (DataOrder == Tranpose) +### * arg0: {1,32}Xi1 predicate(overloaded) +### * arg1: i8 Subopcode, [MBZ] +### * arg2: i8 Caching behavior for L1, [MBC] +### * arg3: i8 Caching behavior for L3, [MBC] +### * arg4: i16 Address scale, [MBC] +### * arg5: {1,32}Xi32 Immediate offset added to each address, [MBC] +### * arg6: i8 The dataum size, [MBC] +### * arg7: i8 Number of elements to load per address (vector size), [MBC] +### * arg8: i8 Indicates if the data is transposed during the transfer, [MBC] +### * arg9: i8 Channel mask for quad version, [MBC] +### * arg10: {1,32}Xi{16,32,64} The vector register holding offsets (overloaded) +### for flat version Base Address + Offset[i] goes here +### * arg11: VXi{16,32,64} The data to write (overloaded) +### * arg12: i32 surface to use for this operation. This can be an immediate or a register +### for flat and bindless version pass zero here +### +### * Return value: void +### +### Cache mappings are: +### +### - 0 -> .df (default) +### - 1 -> .uc (uncached) +### - 2 -> .ca (cached) +### - 3 -> .wb (writeback) +### - 4 -> .wt (writethrough) +### - 5 -> .st (streaming) +### - 6 -> .ri (read-invalidate) +### +### Only certain combinations of CachingL1 with CachingL3 are valid on hardware. +### +### +---------+-----+-----------------------------------------------------------------------+ +### | L1 | L3 | Notes | +### +---------+-----+-----------------------------------------------------------------------+ +### | .df | .df | default behavior on both L1 and L3 (L3 uses MOCS settings) | +### +---------+-----+-----------------------------------------------------------------------+ +### | .uc | .uc | uncached (bypass) both L1 and L3 | +### +---------+-----+-----------------------------------------------------------------------+ +### | .st | .uc | streaming L1 / bypass L3 | +### +---------+-----+-----------------------------------------------------------------------+ +### | .uc | .wb | bypass L1/ writeback L3 | +### +---------+-----+-----------------------------------------------------------------------+ +### | .wt | .uc | writethrough L1 / bypass L3 | +### +---------+-----+-----------------------------------------------------------------------+ +### | .wt | .wb | writethrough L1 / writeback L3 | +### +---------+-----+-----------------------------------------------------------------------+ +### | .st | .wb | streaming L1 / writeback L3 | +### +---------+-----+-----------------------------------------------------------------------+ +### | .wb | .wb | writeback both L1 and L3 | +### +---------+-----+-----------------------------------------------------------------------+ +### + "lsc_store_slm" : { "result" : "void", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","anyvector","int"], + "attributes" : "None" + }, + "lsc_store_stateless" : { "result" : "void", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","anyvector","int"], + "attributes" : "None" + }, + "lsc_store_bindless" : { "result" : "void", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","anyvector","int"], + "attributes" : "None" + }, + "lsc_store_bti" : { "result" : "void", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","anyvector","int"], + "attributes" : "None" + }, + "lsc_store_quad_slm" : { "result" : "void", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","anyvector","int"], + "attributes" : "None" + }, + "lsc_store_quad_stateless" : { "result" : "void", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","anyvector","int"], + "attributes" : "None" + }, + "lsc_store_quad_bindless" : { "result" : "void", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","anyvector","int"], + "attributes" : "None" + }, + "lsc_store_quad_bti" : { "result" : "void", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","anyvector","int"], + "attributes" : "None" + }, + +### ``llvm.genx.lsc.*2d.stateless.[return type]..
`` : 2d stateless load/prefecth instructions +### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +### +### * ``llvm.genx.lsc.load2d.stateless...
`` : +### * ``llvm.genx.lsc.prefetch2d.stateless..
`` : +### +### * Exec_size ignored unless operation is transposed (DataOrder == Tranpose) +### * arg0: {1,32}Xi1 predicate (overloaded) +### * arg1: i8 Caching behavior for L1, [MBC] +### * arg2: i8 Caching behavior for L3, [MBC] +### * arg3: i8 The dataum size, [MBC] +### * arg4: i8 Indicates if the data is transposed during the transfer, [MBC] +### * arg5: i8 number of blocks, [MBC] +### * arg6: i32 BlockWidth, [MBC] +### * arg7: i32 BlockHeight, [MBC] +### * arg8: i8 VNNI. This performs a VNNI transform during the access. +### * arg9: i32/i64 surface base address for this operation. +### * arg10: i32 surface width minus 1. +### * arg11: i32 surface height minus 1. +### * arg12: i32 surface pitch minus 1. +### * arg13: i32 Src0AddrX, the base X position of the 2D region to load or store. +### * arg14: i32 Src0AddrY, the base Y position of the 2D region to load or store. +### +### * Return value: the value read or void for prefetch +### + "lsc_load2d_stateless" : { "result" : "anyvector", + "arguments" : ["anyvector","char","char","char","char","char","short","short","char","anyint","int","int","int","int","int"], + "attributes" : "ReadMem" + }, + "lsc_prefetch2d_stateless" : { "result" : "void", + "arguments" : ["anyvector","char","char","char","char","char","short","short","char","anyint","int","int","int","int","int"], + "attributes" : "None" + }, + +## ``llvm.genx.lsc.store2d.stateless..
.`` : 2d stateless store +### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +### +### * Exec_size ignored unless operation is transposed (DataOrder == Tranpose) +### * arg0: {1,32}Xi1 predicate (overloaded) +### * arg1: i8 Caching behavior for L1, [MBC] +### * arg2: i8 Caching behavior for L3, [MBC] +### * arg3: i8 The dataum size, [MBC] +### * arg4: i8 Indicates if the data is transposed during the transfer, [MBC] +### * arg5: i8 number of blocks, [MBC] +### * arg7: i32 BlockWidth, [MBC] +### * arg6: i32 BlockHeight, [MBC] +### * arg8: i8 VNNI. This performs a VNNI transform during the access. +### * arg9: i32/i64 surface base address for this operation. +### * arg10: i32 surface width minus 1. +### * arg11: i32 surface height minus 1. +### * arg12: i32 surface pitch minus 1. +### * arg13: i32 Src0AddrX, the base X position of the 2D region to load or store. +### * arg14: i32 Src0AddrY, the base Y position of the 2D region to load or store. +### * arg15: data to write (overloaded) +### +### * Return value: void +### + "lsc_store2d_stateless" : { "result" : "void", + "arguments" : ["anyvector","char","char","char","char","char","short","short","char","anyint","int","int","int","int","int","anyvector"], + "attributes" : "None" + }, + + +### ``llvm.genx.lsc.atomic.*...`` : lsc_atomic instructions +### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +### +### !!! Those are legacy ones! Use xatomic version instead !!! +### +### * ``llvm.genx.lsc.atomic.bti`` : +### * ``llvm.genx.lsc.atomic.slm`` : +### * ``llvm.genx.lsc.atomic.slateless`` : +### +### * arg0: {1,32}Xi1 predicate (overloaded) +### * arg1: i8 Subopcode, [MBZ] +### * arg2: i8 Caching behavior for L1, [MBC] +### * arg3: i8 Caching behavior for L3, [MBC] +### * arg4: i16 Address scale, [MBC] +### * arg5: {1,32}Xi32 Immediate offset added to each address, [MBC] +### * arg6: i8 The dataum size, [MBC] +### * arg7: i8 Indicates if the data is transposed during the transfer, [MBC] +### * arg8: i8 Number of elements to load per address (vector size), [MBC] +### * arg9: i8 Channel mask, currently ignored, [MBC]. +### * arg10: i32/i64 surface base address for this operation. +### * arg11: {1,32}Xi{16,32,64} The vector register holding addresses. (overloaded) +### * arg12: i32 {1,32}Xi32 Src0 or undef (same vector size as predicate) +### * arg13: i32 {1,32}Xi32 Src1 or undef (same vector size as predicate) +### * arg14: i32 {1,32}Xi32 Old value of destination (same vector size as predicate), now always undef +### + "lsc_atomic_bti" : { "result" : "any", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","int","anyvector",0,0,0], + "attributes" : "None" + }, + "lsc_atomic_slm" : { "result" : "any", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","int","anyvector",0,0,0], + "attributes" : "None" + }, + "lsc_atomic_stateless" : { "result" : "any", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","int","anyvector",0,0,0], + "attributes" : "None" + }, + "lsc_atomic_bindless" : { "result" : "any", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","int","anyvector",0,0,0], + "attributes" : "None" + }, + +### ``llvm.genx.lsc.xatomic.*...`` : lsc_atomic instructions +### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +### +### * ``llvm.genx.lsc.xatomic.bti`` : +### * ``llvm.genx.lsc.xatomic.slm`` : +### * ``llvm.genx.lsc.xatomic.slateless`` : +### * ``llvm.genx.lsc.xatomic.bindless`` : +### +### * arg0: {1,32}Xi1 predicate (overloaded) +### * arg1: i8 Subopcode, [MBZ] +### * arg2: i8 Caching behavior for L1, [MBC] +### * arg3: i8 Caching behavior for L3, [MBC] +### * arg4: i16 Address scale, [MBC] +### * arg5: {1,32}Xi32 Immediate offset added to each address, [MBC] +### * arg6: i8 Data size, [MBC] +### * arg7: i8 Number of elements to load per address (vector size), [MBC] +### * arg8: i8 Indicates if the data is transposed during the transfer, [MBC] +### * arg9: i8 Channel mask, currently ignored, [MBC] +### * arg10: {1,32}Xi{16,32,64} The vector register holding offsets (overloaded) +### for flat version Base Address + Offset[i] goes here +### * arg11: i32 {1,32}Xi32 Src0 or undef (same vector size as predicate) +### * arg12: i32 {1,32}Xi32 Src1 or undef (same vector size as predicate) +### * arg13: i32 surface to use for this operation. This can be an immediate or a register +### for flat and bindless version pass zero here +### * arg14: i32 {1,32}Xi32 Old value of destination (same vector size as predicate), now always undef +### + "lsc_xatomic_bti" : { "result" : "any", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","anyvector",0,0,"int",0], + "attributes" : "None" + }, + "lsc_xatomic_slm" : { "result" : "any", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","anyvector",0,0,"int",0], + "attributes" : "None" + }, + "lsc_xatomic_stateless" : { "result" : "any", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","anyvector",0,0,"int",0], + "attributes" : "None" + }, + "lsc_xatomic_bindless" : { "result" : "any", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","anyvector",0,0,"int",0], + "attributes" : "None" + }, + +### ``llvm.genx.lsc.fence.`` : lsc_fence instruction +### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +### +### * ``llvm.genx.lsc.fence`` : +### +### * Exec_size ignored unless operation is transposed (DataOrder == Tranpose) +### * arg0: {1,32}Xi1 predicate (overloaded) +### * arg1: i8 SFID +### * arg2: i8 Fence operation +### * arg3: i8 Fence operation scope +### +### [2] Mappings are: +### 0 -> .ugm (unified global memory) +### 1 -> .ugml (low-bandwith untyped global memory) +### 2 -> .tgm (typed global memory) +### 3 -> .slm (shared local memory) +### +### [3] Mappings are: +### 0 -> .none (no operation) +### 1 -> .evict (dirty lines evicted and invalidated from L1) +### 2 -> .invalidate (invalidate all clean lines) +### 3 -> .discard (direct and clean lines are discarded w/o eviction) +### 4 -> .clean (dirty lines are written to memory, but retained in cache in clean state) +### 5 -> .flushl3 (flush only L3) +### +### [4] Mappings are: +### 0 -> .group (flush out to the threadgroup's scope) +### 1 -> .local (flush out to the local scope) +### 2 -> .tile (tile, flush out to several DSSs) +### 3 -> .gpu (entire GPU, flush out to the GPUs LLC) +### 4 -> .gpus (all GPUs in the system, flush out to memory shared by all GPUs) +### 5 -> .system (the entire system memory space) +### 6 -> .sysacq (the entire system memory space with system-acquire semantics) +### + "lsc_fence" : { "result" : "void", + "arguments" : ["anyvector","char","char","char"], + "attributes" : "None" + }, ### xor ### ^^^ @@ -1390,8 +2284,14 @@ ### ### * Return value: i16 the value read ### - "thread_x" : ["short",[],"NoMem"], - "thread_y" : ["short",[],"NoMem"], + "thread_x" : { "result" : "short", + "arguments" : [], + "attributes" : "NoMem" + }, + "thread_y" : { "result" : "short", + "arguments" : [], + "attributes" : "NoMem" + }, ### ``llvm.genx.group.id.*`` : read group ID register ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1401,9 +2301,18 @@ ### ### * Return value: i32 the value read ### - "group_id_x" : ["int",[],"NoMem"], - "group_id_y" : ["int",[],"NoMem"], - "group_id_z" : ["int",[],"NoMem"], + "group_id_x" : { "result" : "int", + "arguments" : [], + "attributes" : "NoMem" + }, + "group_id_y" : { "result" : "int", + "arguments" : [], + "attributes" : "NoMem" + }, + "group_id_z" : { "result" : "int", + "arguments" : [], + "attributes" : "NoMem" + }, ### ``llvm.genx.timestamp.`` : read vISA v11 (%timestamp) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1412,7 +2321,10 @@ ### ### The vector width must be power of 2 and no larger than 4. ### - "timestamp" : ["anyint",[],"None"], + "timestamp" : { "result" : "anyint", + "arguments" : [], + "attributes" : "None" + }, ### ``llvm.genx.r0.`` : read vISA v12 (%r0) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1421,7 +2333,10 @@ ### ### The vector width must be power of 2 and no larger than 8. ### - "r0" : ["anyint",[],"ReadMem"], + "r0" : { "result" : "anyint", + "arguments" : [], + "attributes" : "ReadMem" + }, ### ``llvm.genx.sr0.`` : read vISA v13 (%sr0) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1431,7 +2346,10 @@ ### The vector width must be 4 ### ### - "sr0" : ["anyint",[],"ReadMem"], + "sr0" : { "result" : "anyint", + "arguments" : [], + "attributes" : "ReadMem" + }, ### ``llvm.genx.set.sr0.2`` : write vISA v13(0, 2) (%sr0.2) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1440,7 +2358,10 @@ ### ### * Return value: void ### - "set_sr0_2" : ["void",["int"],"None"], + "set_sr0_2" : { "result" : "void", + "arguments" : ["int"], + "attributes" : "None" + }, ### ``llvm.genx.get.color`` : read color value of the thread origin ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1450,21 +2371,30 @@ ### This may not be the most appropriate way to access this value, ### but is a stop-gap solution. ### - "get_color" : ["short",[],"NoMem"], + "get_color" : { "result" : "short", + "arguments" : [], + "attributes" : "NoMem" + }, ### ``llvm.genx.get.hwid`` : read hw_id value ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ### ### Return Value: i32 the value read ### - "get_hwid" : ["int",[],"NoMem"], + "get_hwid" : { "result" : "int", + "arguments" : [], + "attributes" : "NoMem" + }, ### ``llvm.genx.ce0`` : read channel-enable register ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ### ### Return Value: i32 the value read ### - "ce0" : ["int",[],"ReadMem"], + "ce0" : { "result" : "int", + "arguments" : [], + "attributes" : "ReadMem" + }, ### ``llvm.genx.set.pause`` : set the pause register (v11.4) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1479,7 +2409,10 @@ ### ### We set this intrinsic to have side-effects (last field empty) to stop it being removed as it ### otherwise looks dead - "set_pause" : ["void",["short"],"None"], + "set_pause" : { "result" : "void", + "arguments" : ["short"], + "attributes" : "None" + }, ### ``llvm.genx.dummy.mov`` : insert a dummy mov to v0 ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1496,7 +2429,10 @@ ### ### We set this intrinsic to have side-effects (last field empty) to stop it being removed as it ### otherwise looks dead and also to prevent any kind of code motion optimisation - "dummy_mov" : ["void",["short"],"None"], + "dummy_mov" : { "result" : "void", + "arguments" : ["short"], + "attributes" : "None" + }, ### The following 2 predef.reg intrinsics aren't translated directly to read/writes of the reg, ### instead they're baled together with rd/wrregions and in fact indicate that those rdr/wrrs @@ -1511,7 +2447,10 @@ ### * Return value: value read ### ### - "read_predef_reg" : ["any",["int", "any"],"ReadMem"], + "read_predef_reg" : { "result" : "any", + "arguments" : ["int", "any"], + "attributes" : "ReadMem" + }, ### ``llvm.write.predef.reg..`` : write value to predefined vISA reg ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1521,7 +2460,10 @@ ### ### * Return value: value written ### - "write_predef_reg" : ["any",["int", "any"],"WriteMem"], + "write_predef_reg" : { "result" : "any", + "arguments" : ["int", "any"], + "attributes" : "WriteMem" + }, ## -------------------------- ### Shared function intrinsics @@ -1555,16 +2497,46 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width, which must be 1, 8 or 16. ### - "dword_atomic_add" : ["anyvector",["anyvector","int","anyint",0,0],"None"], - "dword_atomic_sub" : ["anyvector",["anyvector","int","anyint",0,0],"None"], - "dword_atomic_min" : ["anyvector",["anyvector","int","anyint",0,0],"None"], - "dword_atomic_max" : ["anyvector",["anyvector","int","anyint",0,0],"None"], - "dword_atomic_xchg" : ["anyvector",["anyvector","int","anyint",0,0],"None"], - "dword_atomic_and" : ["anyvector",["anyvector","int","anyint",0,0],"None"], - "dword_atomic_or" : ["anyvector",["anyvector","int","anyint",0,0],"None"], - "dword_atomic_xor" : ["anyvector",["anyvector","int","anyint",0,0],"None"], - "dword_atomic_imin" : ["anyvector",["anyvector","int","anyint",0,0],"None"], - "dword_atomic_imax" : ["anyvector",["anyvector","int","anyint",0,0],"None"], + "dword_atomic_add" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0,0], + "attributes" : "None", + }, + "dword_atomic_sub" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0,0], + "attributes" : "None", + }, + "dword_atomic_min" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0,0], + "attributes" : "None", + }, + "dword_atomic_max" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0,0], + "attributes" : "None", + }, + "dword_atomic_xchg" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0,0], + "attributes" : "None", + }, + "dword_atomic_and" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0,0], + "attributes" : "None", + }, + "dword_atomic_or" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0,0], + "attributes" : "None", + }, + "dword_atomic_xor" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0,0], + "attributes" : "None", + }, + "dword_atomic_imin" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0,0], + "attributes" : "None", + }, + "dword_atomic_imax" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0,0], + "attributes" : "None", + }, ### ``llvm.genx.dword.atomic2.*..`` : dword atomic with binary operator (variant with no oldval) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1590,16 +2562,46 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width, which must be 1, 8 or 16. ### - "dword_atomic2_add" : ["anyvector",["anyvector","int","anyint",0],"None"], - "dword_atomic2_sub" : ["anyvector",["anyvector","int","anyint",0],"None"], - "dword_atomic2_min" : ["anyvector",["anyvector","int","anyint",0],"None"], - "dword_atomic2_max" : ["anyvector",["anyvector","int","anyint",0],"None"], - "dword_atomic2_xchg" : ["anyvector",["anyvector","int","anyint",0],"None"], - "dword_atomic2_and" : ["anyvector",["anyvector","int","anyint",0],"None"], - "dword_atomic2_or" : ["anyvector",["anyvector","int","anyint",0],"None"], - "dword_atomic2_xor" : ["anyvector",["anyvector","int","anyint",0],"None"], - "dword_atomic2_imin" : ["anyvector",["anyvector","int","anyint",0],"None"], - "dword_atomic2_imax" : ["anyvector",["anyvector","int","anyint",0],"None"], + "dword_atomic2_add" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_sub" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_min" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_max" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_xchg" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_and" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_or" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_xor" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_imin" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_imax" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0], + "attributes" : "None", + }, ### ``llvm.genx.dword.atomic.*...`` : dword atomic with fmin/fmax operation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1618,8 +2620,22 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width, which must be 1, 8 or 16. ### - "dword_atomic_fmin" : ["anyvector",["anyvector","int","anyint",0,0],"None"], - "dword_atomic_fmax" : ["anyvector",["anyvector","int","anyint",0,0],"None"], + "dword_atomic_fmin" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0,0], + "attributes" : "None", + }, + "dword_atomic_fmax" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0,0], + "attributes" : "None", + }, + "dword_atomic_fadd" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0,0], + "attributes" : "None", + }, + "dword_atomic_fsub" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0,0], + "attributes" : "None", + }, ### ``llvm.genx.dword.atomic2.*...`` : dword atomic with fmin/fmax operation (variant with no oldval) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1637,8 +2653,22 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width, which must be 1, 8 or 16. ### - "dword_atomic2_fmin" : ["anyvector",["anyvector","int","anyint",0],"None"], - "dword_atomic2_fmax" : ["anyvector",["anyvector","int","anyint",0],"None"], + "dword_atomic2_fmin" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_fmax" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_fadd" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_fsub" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0], + "attributes" : "None", + }, ### ``llvm.genx.dword.atomic.*..`` : dword atomic with inc/dec operation @@ -1657,8 +2687,14 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width, which must be 1, 8 or 16. ### - "dword_atomic_inc" : ["anyvector",["anyvector","int",0,0],"None"], - "dword_atomic_dec" : ["anyvector",["anyvector","int",0,0],"None"], + "dword_atomic_inc" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,0], + "attributes" : "None", + }, + "dword_atomic_dec" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,0], + "attributes" : "None", + }, ### ``llvm.genx.dword.atomic2.*..`` : dword atomic with inc/dec operation (variant with no oldval) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1675,8 +2711,14 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width, which must be 1, 8 or 16. ### - "dword_atomic2_inc" : ["anyvector",["anyvector","int",0],"None"], - "dword_atomic2_dec" : ["anyvector",["anyvector","int",0],"None"], + "dword_atomic2_inc" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0], + "attributes" : "None", + }, + "dword_atomic2_dec" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0], + "attributes" : "None", + }, ### ``llvm.genx.dword.atomic.cmpxchg..`` : vISA DWORD_ATOMIC CMPXCHG instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1694,7 +2736,10 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width, which must be 1, 8 or 16. ### - "dword_atomic_cmpxchg" : ["anyvector",["anyvector","int",0,0,0,0],"None"], + "dword_atomic_cmpxchg" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,0,0,0], + "attributes" : "None", + }, ### ``llvm.genx.dword.atomic2.cmpxchg..`` : vISA DWORD_ATOMIC CMPXCHG instruction (variant with no oldval) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1711,7 +2756,10 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width, which must be 1, 8 or 16. ### - "dword_atomic2_cmpxchg" : ["anyvector",["anyvector","int",0,0,0],"None"], + "dword_atomic2_cmpxchg" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,0,0], + "attributes" : "None", + }, ### ``llvm.genx.dword.atomic.fcmpwr...`` : vISA DWORD_ATOMIC FCMPWR instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1729,7 +2777,10 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width, which must be 1, 8 or 16. ### - "dword_atomic_fcmpwr" : ["anyvector",["anyvector","int","anyint",0,0,0],"None"], + "dword_atomic_fcmpwr" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0,0,0], + "attributes" : "None", + }, ### ``llvm.genx.dword.atomic2.fcmpwr...`` : vISA DWORD_ATOMIC FCMPWR instruction (variant with no oldval) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1746,7 +2797,10 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width, which must be 1, 8 or 16. ### - "dword_atomic2_fcmpwr" : ["anyvector",["anyvector","int","anyint",0,0],"None"], + "dword_atomic2_fcmpwr" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0,0], + "attributes" : "None", + }, ### ``llvm.genx.typed.atomic.*...`` : atomic typed with binary operator ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1775,16 +2829,46 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width (which in reality must be 8) ### - "typed_atomic_add" : ["anyvector",["anyvector","int",0,"anyint",2,2,2],"None"], - "typed_atomic_sub" : ["anyvector",["anyvector","int",0,"anyint",2,2,2],"None"], - "typed_atomic_min" : ["anyvector",["anyvector","int",0,"anyint",2,2,2],"None"], - "typed_atomic_max" : ["anyvector",["anyvector","int",0,"anyint",2,2,2],"None"], - "typed_atomic_xchg" : ["anyvector",["anyvector","int",0,"anyint",2,2,2],"None"], - "typed_atomic_and" : ["anyvector",["anyvector","int",0,"anyint",2,2,2],"None"], - "typed_atomic_or" : ["anyvector",["anyvector","int",0,"anyint",2,2,2],"None"], - "typed_atomic_xor" : ["anyvector",["anyvector","int",0,"anyint",2,2,2],"None"], - "typed_atomic_imin" : ["anyvector",["anyvector","int",0,"anyint",2,2,2],"None"], - "typed_atomic_imax" : ["anyvector",["anyvector","int",0,"anyint",2,2,2],"None"], + "typed_atomic_add" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "attributes" : "None" + }, + "typed_atomic_sub" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "attributes" : "None" + }, + "typed_atomic_min" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "attributes" : "None" + }, + "typed_atomic_max" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "attributes" : "None" + }, + "typed_atomic_xchg" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "attributes" : "None" + }, + "typed_atomic_and" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "attributes" : "None" + }, + "typed_atomic_or" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "attributes" : "None" + }, + "typed_atomic_xor" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "attributes" : "None" + }, + "typed_atomic_imin" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "attributes" : "None" + }, + "typed_atomic_imax" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "attributes" : "None" + }, ### ``llvm.genx.typed.atomic.*...`` : atomic typed with fmin/fmax operation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1805,8 +2889,22 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width (which in reality must be 8) ### - "typed_atomic_fmin" : ["anyvector",["anyvector","int",0,"anyint",2,2,2],"None"], - "typed_atomic_fmax" : ["anyvector",["anyvector","int",0,"anyint",2,2,2],"None"], + "typed_atomic_fmin" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "attributes" : "None" + }, + "typed_atomic_fmax" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "attributes" : "None" + }, + "typed_atomic_fadd" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "attributes" : "None" + }, + "typed_atomic_fsub" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "attributes" : "None" + }, ### ``llvm.genx.typed.atomic.*...`` : atomic typed with inc/dec operation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1826,8 +2924,14 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width (which in reality must be 8) ### - "typed_atomic_inc" : ["anyvector",["anyvector","int","anyint",2,2,2],"None"], - "typed_atomic_dec" : ["anyvector",["anyvector","int","anyint",2,2,2],"None"], + "typed_atomic_inc" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",2,2,2], + "attributes" : "None" + }, + "typed_atomic_dec" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",2,2,2], + "attributes" : "None" + }, ### ``llvm.genx.typed.atomic.cmpxchg...`` : vISA TYPED_ATOMIC CMPXCHG instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1847,7 +2951,10 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width (which in reality must be 8) ### - "typed_atomic_cmpxchg" : ["anyvector",["anyvector","int",0,0,"anyint",2,2,2],"None"], + "typed_atomic_cmpxchg" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,0,"anyint",2,2,2], + "attributes" : "None" + }, ### ``llvm.genx.typed.atomic.fcmpwr...`` : vISA TYPED_ATOMIC FCMPWR instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1867,7 +2974,10 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width (which in reality must be 8) ### - "typed_atomic_fcmpwr" : ["anyvector",["anyvector","int",0,0,"anyint",2,2,2],"None"], + "typed_atomic_fcmpwr" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,0,"anyint",2,2,2], + "attributes" : "None" + }, ### ``llvm.genx.gather.private...`` : CMC internal, no VISA ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1885,7 +2995,10 @@ ### ### The element offset arg must have the same vector width. ### - "gather_private" : ["anyvector",["anyvector","anyptr","anyint",0],"ReadMem"], + "gather_private" : { "result" : "anyvector", + "arguments" : ["anyvector","anyptr","anyint",0], + "attributes" : "ReadMem" + }, ### ``llvm.genx.gather.scaled...`` : vISA GATHER_SCALED instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1910,7 +3023,10 @@ ### F type. For 1 and 2 byte (1 x num blocks) reads the upper bytes have ### undefined values in the returned value. ### - "gather_scaled" : ["anyvector",["anyvector","int","short","int","int","anyint",0],"ReadMem"], + "gather_scaled" : { "result" : "anyvector", + "arguments" : ["anyvector","int","short","int","int","anyint",0], + "attributes" : "ReadMem", + }, ### ``llvm.genx.gather.scaled2`` : vISA GATHER_SCALED instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1933,7 +3049,10 @@ ### For 1 and 2 byte (1 x num blocks) reads the upper bytes have ### undefined values in the returned value. ### - "gather_scaled2" : ["anyvector",["int","short","int","int","anyint"],"ReadMem"], + "gather_scaled2" : { "result" : "anyvector", + "arguments" : ["int","short","int","int","anyint"], + "attributes" : "ReadMem", + }, ### ``llvm.genx.gather.masked.scaled2`` : vISA GATHER_SCALED instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1949,7 +3068,10 @@ ### ### * Return value: the data read ### - "gather_masked_scaled2" : ["anyvector",["int","short","int","int","anyint","anyvector"],"ReadMem"], + "gather_masked_scaled2" : { "result" : "anyvector", + "arguments" : ["int","short","int","int","anyint","anyvector"], + "attributes" : "ReadMem", + }, ### ``llvm.genx.gather4.scaled...`` : vISA GATHER4_SCALED instruction @@ -1977,7 +3099,10 @@ ### times the number of channels to read per element. ### The element type of the return value must be i32 or float. ### - "gather4_scaled" : ["anyvector",["anyvector","int","short","int","int","anyint",0],"ReadMem"], + "gather4_scaled" : { "result" : "anyvector", + "arguments" : ["anyvector","int","short","int","int","anyint",0], + "attributes" : "ReadMem" , + }, ### ``llvm.genx.gather4.scaled2`` : vISA GATHER4_SCALED instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2005,7 +3130,10 @@ ### times the number of channels to read per element. ### The element type of the return value must be i32 or float. ### - "gather4_scaled2" : ["anyvector",["int","short","int","int","anyint"],"ReadMem"], + "gather4_scaled2" : { "result" : "anyvector", + "arguments" : ["int","short","int","int","anyint"], + "attributes" : "ReadMem", + }, ### ``llvm.genx.gather4.masked.scaled2`` : vISA GATHER4_SCALED instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2020,7 +3148,10 @@ ### ### * Return value: the data read ### - "gather4_masked_scaled2" : ["anyvector",["int","short","int","int","anyint","anyvector"],"ReadMem"], + "gather4_masked_scaled2" : { "result" : "anyvector", + "arguments" : ["int","short","int","int","anyint","anyvector"], + "attributes" : "ReadMem", + }, ### ``llvm.genx.gather4.typed...`` : vISA GATHER4_TYPED instruction @@ -2048,7 +3179,10 @@ ### times the number of channels to read per element. ### The element type of the return value must be i32 or float. ### - "gather4_typed" : ["anyvector",["int","anyvector","int","anyvector",2,2,0],"ReadMem"], + "gather4_typed" : { "result" : "anyvector", + "arguments" : ["int","anyvector","int","anyvector",2,2,0], + "attributes" : "ReadMem", + }, ### ``llvm.genx.media.ld.`` : vISA MEDIA_LD instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2071,7 +3205,10 @@ ### The block width has a maximum of 32 (64 on BDW+). The maxmimum byte ### size of the return type is 256. ### - "media_ld" : ["anyvector",["int","int","int","int","int","int"],"ReadMem"], + "media_ld" : { "result" : "anyvector", + "arguments" : ["int","int","int","int","int","int"], + "attributes" : "ReadMem", + }, ### ``llvm.genx.media.st.`` : vISA MEDIA_ST instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2093,7 +3230,10 @@ ### The block width has a maximum of 32 (64 on BDW+). The maxmimum byte ### size of the data to write is 256. ### - "media_st" : ["void",["int","int","int","int","int","int","anyvector"],"None"], + "media_st" : { "result" : "void", + "arguments" : ["int","int","int","int","int","int","anyvector"], + "attributes" : "None", + }, ### ``llvm.genx.oword.ld*.`` : oword load instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2109,8 +3249,14 @@ ### ### The byte size of the return type must be 16, 32, 64, or 128. ### - "oword_ld" : ["anyvector",["int","int","int"],"ReadMem"], - "oword_ld_unaligned" : ["anyvector",["int","int","int"],"ReadMem"], + "oword_ld" : { "result" : "anyvector", + "arguments" : ["int","int","int"], + "attributes" : "ReadMem", + }, + "oword_ld_unaligned" : { "result" : "anyvector", + "arguments" : ["int","int","int"], + "attributes" : "ReadMem", + }, ### ``llvm.genx.oword.st.`` : vISA OWORD_ST instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2122,7 +3268,10 @@ ### ### The byte size of the data to write must be 16, 32, 64, or 128. ### - "oword_st" : ["void",["int","int","anyvector"],"None"], + "oword_st" : { "result" : "void", + "arguments" : ["int","int","anyvector"], + "attributes" : "None", + }, ### ``llvm.genx.scatter.private....`` : CM internal, no VISA ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2136,7 +3285,10 @@ ### which must be 1, 8 or 16. ### The element offset arg must have the same vector width. ### - "scatter_private" : ["void",["anyvector","anyptr","anyint","anyvector"],"None"], + "scatter_private" : { "result" : "void", + "arguments" : ["anyvector","anyptr","anyint","anyvector"], + "attributes" : "None" + }, ### ``llvm.genx.scatter.scaled...`` : vISA SCATTER_SCALED instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2158,7 +3310,10 @@ ### The data type to write must have UD, D or F type. For 1 and 2 byte (1 x num ### blocks) accesses the upper bytes will be ignored. ### - "scatter_scaled" : ["void",["anyvector","int","short","int","int","anyint","anyvector"],"None"], + "scatter_scaled" : { "result" : "void", + "arguments" : ["anyvector","int","short","int","int","anyint","anyvector"], + "attributes" : "None", + }, ### ``llvm.genx.scatter4.scaled...`` : vISA SCATTER4_SCALED instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2184,7 +3339,10 @@ ### times the number of channels to write per element. ### The element type of the data to write must be i32 or float. ### - "scatter4_scaled" : ["void",["anyvector","int","short","int","int","anyint","anyvector"],"None"], + "scatter4_scaled" : { "result" : "void", + "arguments" : ["anyvector","int","short","int","int","anyint","anyvector"], + "attributes" : "None", + }, ### ``llvm.genx.scatter4.typed...`` : vISA SCATTER4_TYPED instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2209,7 +3367,10 @@ ### times the number of channels to read per element. ### The element type of the source value must be i32 or float. ### - "scatter4_typed" : ["void",["int","anyvector","int","anyvector",1,1,"anyvector"],"None"], + "scatter4_typed" : { "result" : "void", + "arguments" : ["int","anyvector","int","anyvector",1,1,"anyvector"], + "attributes" : "None", + }, ### ``llvm.genx.transpose.ld.`` : vISA TRANSPOSE_LD instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2227,7 +3388,10 @@ ### inferred from those values. ### The element type of the return value must be i32 or float. ### - "transpose_ld" : ["anyvector",["int","int","int","int"],"ReadMem"], + "transpose_ld" : { "result" : "anyvector", + "arguments" : ["int","int","int","int"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.untyped.atomic.*..`` : vISA UNTYPED_ATOMIC with binary operator ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2254,16 +3418,46 @@ ### Predicate, element offset, src, and the return value must all have the ##same vector / width, which must be 8 or 16. ### - "untyped_atomic_add" : ["anyvector",["anyvector","int","int",0,0,0],"None"], - "untyped_atomic_sub" : ["anyvector",["anyvector","int","int",0,0,0],"None"], - "untyped_atomic_min" : ["anyvector",["anyvector","int","int",0,0,0],"None"], - "untyped_atomic_max" : ["anyvector",["anyvector","int","int",0,0,0],"None"], - "untyped_atomic_xchg" : ["anyvector",["anyvector","int","int",0,0,0],"None"], - "untyped_atomic_and" : ["anyvector",["anyvector","int","int",0,0,0],"None"], - "untyped_atomic_or" : ["anyvector",["anyvector","int","int",0,0,0],"None"], - "untyped_atomic_xor" : ["anyvector",["anyvector","int","int",0,0,0],"None"], - "untyped_atomic_imin" : ["anyvector",["anyvector","int","int",0,0,0],"None"], - "untyped_atomic_imax" : ["anyvector",["anyvector","int","int",0,0,0],"None"], + "untyped_atomic_add" : { "result" : "anyvector", + "arguments" : ["anyvector","int","int",0,0,0], + "attributes" : "None" + }, + "untyped_atomic_sub" : { "result" : "anyvector", + "arguments" : ["anyvector","int","int",0,0,0], + "attributes" : "None" + }, + "untyped_atomic_min" : { "result" : "anyvector", + "arguments" : ["anyvector","int","int",0,0,0], + "attributes" : "None" + }, + "untyped_atomic_max" : { "result" : "anyvector", + "arguments" : ["anyvector","int","int",0,0,0], + "attributes" : "None" + }, + "untyped_atomic_xchg" : { "result" : "anyvector", + "arguments" : ["anyvector","int","int",0,0,0], + "attributes" : "None" + }, + "untyped_atomic_and" : { "result" : "anyvector", + "arguments" : ["anyvector","int","int",0,0,0], + "attributes" : "None" + }, + "untyped_atomic_or" : { "result" : "anyvector", + "arguments" : ["anyvector","int","int",0,0,0], + "attributes" : "None" + }, + "untyped_atomic_xor" : { "result" : "anyvector", + "arguments" : ["anyvector","int","int",0,0,0], + "attributes" : "None" + }, + "untyped_atomic_imin" : { "result" : "anyvector", + "arguments" : ["anyvector","int","int",0,0,0], + "attributes" : "None" + }, + "untyped_atomic_imax" : { "result" : "anyvector", + "arguments" : ["anyvector","int","int",0,0,0], + "attributes" : "None" + }, ### ``llvm.genx.untyped.atomic.*..`` : vISA UNTYPED_ATOMIC with inc/dec ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2281,8 +3475,14 @@ ### Predicate, element offset and the return value must have the same vector ### width, which must be 8 or 16. ### - "untyped_atomic_inc" : ["anyvector",["anyvector","int","int",0,0],"None"], - "untyped_atomic_dec" : ["anyvector",["anyvector","int","int",0,0],"None"], + "untyped_atomic_inc" : { "result" : "anyvector", + "arguments" : ["anyvector","int","int",0,0], + "attributes" : "None" + }, + "untyped_atomic_dec" : { "result" : "anyvector", + "arguments" : ["anyvector","int","int",0,0], + "attributes" : "None" + }, ### ``llvm.genx.untyped.atomic.cmpxchg..`` : vISA UNTYPED_ATOMIC CMPXCHG instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2300,7 +3500,10 @@ ### Predicate, element offset, src0, src1, and the return value must all have ### the same vector width, which must be 8 or 16. ### - "untyped_atomic_cmpxchg" : ["anyvector",["anyvector","int","int",0,0,0,0],"None"], + "untyped_atomic_cmpxchg" : { "result" : "anyvector", + "arguments" : ["anyvector","int","int",0,0,0,0], + "attributes" : "None" + }, ### ``llvm.genx.svm.block.ld*..
`` : vISA SVM BLOCK_LD instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2317,8 +3520,14 @@ ### The data read must have a size that is a power of two from 16 to 128 ### bytes. ### - "svm_block_ld" : ["anyvector",["anyint"],"ReadMem"], - "svm_block_ld_unaligned" : ["anyvector",["anyint"],"ReadMem"], + "svm_block_ld" : { "result" : "anyvector", + "arguments" : ["anyint"], + "attributes" : "ReadMem" + }, + "svm_block_ld_unaligned" : { "result" : "anyvector", + "arguments" : ["anyint"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.svm.block.st.
`` : vISA SVM BLOCK_ST instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2330,7 +3539,10 @@ ### The data to write must have a size that is a power of two from 16 to 128 ### bytes. ### - "svm_block_st" : ["void",["anyint","anyvector"],"None"], + "svm_block_st" : { "result" : "void", + "arguments" : ["anyint","anyvector"], + "attributes" : "None" + }, ### ``llvm.genx.svm.gather...`` : vISA SVM GATHER instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2349,7 +3561,10 @@ ### The return value vector width is the address vector width times ### number of blocks (rounded up to 4 if block size is 1). ### - "svm_gather" : ["anyvector",["anyvector","int","anyint",0],"ReadMem"], + "svm_gather" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0], + "attributes" : "ReadMem" + }, ### ``llvm.genx.svm.gather4.scaled...`` : vISA SVM GATHER4_SCALED instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2376,7 +3591,10 @@ ### times the number of channels to read per element. ### The element type of the return value must be i32 or float. ### - "svm_gather4_scaled" : ["anyvector",["anyvector","int","short","long","anyint",0],"ReadMem"], + "svm_gather4_scaled" : { "result" : "anyvector", + "arguments" : ["anyvector","int","short","long","anyint",0], + "attributes" : "ReadMem" + }, ### ``llvm.genx.svm.scatter...`` : vISA SVM SCATTER instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2393,7 +3611,10 @@ ### The data vector width is the address vector width times ### number of blocks (rounded up to 4 if block size is 1). ### - "svm_scatter" : ["void",["anyvector","int","anyint","anyvector"],"None"], + "svm_scatter" : { "result" : "void", + "arguments" : ["anyvector","int","anyint","anyvector"], + "attributes" : "None" + }, ### ``llvm.genx.svm.scatter4.scaled...`` : vISA SVM SCATTER4_SCALED instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2418,7 +3639,10 @@ ### times the number of channels to read per element. ### The element type of the data to write arg must be i32 or float. ### - "svm_scatter4_scaled" : ["void",["anyvector","int","short","long","anyint","anyvector"],"None"], + "svm_scatter4_scaled" : { "result" : "void", + "arguments" : ["anyvector","int","short","long","anyint","anyvector"], + "attributes" : "None" + }, ### ``llvm.genx.svm.atomic.*...`` : vISA SVM_ATOMIC with binary operator ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2443,16 +3667,46 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width, which must be 1, 2, 4, or 8. ### - "svm_atomic_add" : ["anyvector",["anyvector","anyint",0,0],"None"], - "svm_atomic_sub" : ["anyvector",["anyvector","anyint",0,0],"None"], - "svm_atomic_min" : ["anyvector",["anyvector","anyint",0,0],"None"], - "svm_atomic_max" : ["anyvector",["anyvector","anyint",0,0],"None"], - "svm_atomic_xchg" : ["anyvector",["anyvector","anyint",0,0],"None"], - "svm_atomic_and" : ["anyvector",["anyvector","anyint",0,0],"None"], - "svm_atomic_or" : ["anyvector",["anyvector","anyint",0,0],"None"], - "svm_atomic_xor" : ["anyvector",["anyvector","anyint",0,0],"None"], - "svm_atomic_imin" : ["anyvector",["anyvector","anyint",0,0],"None"], - "svm_atomic_imax" : ["anyvector",["anyvector","anyint",0,0],"None"], + "svm_atomic_add" : { "result" : "anyvector", + "arguments" : ["anyvector","anyint",0,0], + "attributes" : "None" + }, + "svm_atomic_sub" : { "result" : "anyvector", + "arguments" : ["anyvector","anyint",0,0], + "attributes" : "None" + }, + "svm_atomic_min" : { "result" : "anyvector", + "arguments" : ["anyvector","anyint",0,0], + "attributes" : "None" + }, + "svm_atomic_max" : { "result" : "anyvector", + "arguments" : ["anyvector","anyint",0,0], + "attributes" : "None" + }, + "svm_atomic_xchg" : { "result" : "anyvector", + "arguments" : ["anyvector","anyint",0,0], + "attributes" : "None" + }, + "svm_atomic_and" : { "result" : "anyvector", + "arguments" : ["anyvector","anyint",0,0], + "attributes" : "None" + }, + "svm_atomic_or" : { "result" : "anyvector", + "arguments" : ["anyvector","anyint",0,0], + "attributes" : "None" + }, + "svm_atomic_xor" : { "result" : "anyvector", + "arguments" : ["anyvector","anyint",0,0], + "attributes" : "None" + }, + "svm_atomic_imin" : { "result" : "anyvector", + "arguments" : ["anyvector","anyint",0,0], + "attributes" : "None" + }, + "svm_atomic_imax" : { "result" : "anyvector", + "arguments" : ["anyvector","anyint",0,0], + "attributes" : "None" + }, ### ``llvm.genx.svm.atomic.*...`` : vISA SVM_ATOMIC with inc/dec ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2468,8 +3722,14 @@ ### Predicate, element offset and the return value must have the same vector ### width, which must be 1, 2, 4 or 8. ### - "svm_atomic_inc" : ["anyvector",["anyvector","anyint",0],"None"], - "svm_atomic_dec" : ["anyvector",["anyvector","anyint",0],"None"], + "svm_atomic_inc" : { "result" : "anyvector", + "arguments" : ["anyvector","anyint",0], + "attributes" : "None" + }, + "svm_atomic_dec" : { "result" : "anyvector", + "arguments" : ["anyvector","anyint",0], + "attributes" : "None" + }, ### ``llvm.genx.svm.atomic.cmpxchg...`` : vISA SVM_ATOMIC CMPXCHG instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2485,7 +3745,10 @@ ### Predicate, element offset, src0, src1, and the return value must all have ### the same vector width, which must be 1, 2, 4 or 8. ### - "svm_atomic_cmpxchg" : ["anyvector",["anyvector","anyint",0,0,0],"None"], + "svm_atomic_cmpxchg" : { "result" : "anyvector", + "arguments" : ["anyvector","anyint",0,0,0], + "attributes" : "None" + }, ### ``llvm.genx.svm.atomic.*...`` : vISA SVM_ATOMIC with binary operator ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2502,8 +3765,14 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width, which must be 1, 2, 4, or 8. ### - "svm_atomic_fmin" : ["anyvector",["anyvector","anyint",0,0],"None"], - "svm_atomic_fmax" : ["anyvector",["anyvector","anyint",0,0],"None"], + "svm_atomic_fmin" : { "result" : "anyvector", + "arguments" : ["anyvector","anyint",0,0], + "attributes" : "None" + }, + "svm_atomic_fmax" : { "result" : "anyvector", + "arguments" : ["anyvector","anyint",0,0], + "attributes" : "None" + }, ### ``llvm.genx.svm.atomic.fcmpwr...`` : vISA SVM_ATOMIC FCMPWR instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2519,7 +3788,10 @@ ### Predicate, element offset, src0, src1, and the return value must all have ### the same vector width, which must be 1, 2, 4 or 8. ### - "svm_atomic_fcmpwr" : ["anyvector",["anyvector","anyint",0,0,0],"None"], + "svm_atomic_fcmpwr" : { "result" : "anyvector", + "arguments" : ["anyvector","anyint",0,0,0], + "attributes" : "None" + }, ### ``llvm.genx.load..`` : vISA LOAD (sampler load) instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2546,7 +3818,10 @@ ### ### The element type of the return value must be i32 or float. ### - "load" : ["anyvector",["int","int","anyint",1,1],"ReadMem"], + "load" : { "result" : "anyvector", + "arguments" : ["int","int","anyint",1,1], + "attributes" : "ReadMem" + }, ### ``llvm.genx.sample..`` : vISA SAMPLE instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2574,7 +3849,10 @@ ### ### The element type of the return value must be i32 or float. ### - "sample" : ["anyvector",["int","int","int","anyfloat",1,1],"ReadMem"], + "sample" : { "result" : "anyvector", + "arguments" : ["int","int","int","anyfloat",1,1], + "attributes" : "ReadMem" + }, ### ``llvm.genx.sample..unorm`` : vISA SAMPLE_UNORM instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2594,7 +3872,10 @@ ### The number of 0 bits in that lower 4 bits of the channel mask arg is the ### number of channels to read per element. ### - "sample_unorm" : ["anyvector",["int","int","int","float","float","float","float"],"ReadMem"], + "sample_unorm" : { "result" : "anyvector", + "arguments" : ["int","int","int","float","float","float","float"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.3d.sample......`` : vISA 3D_SAMPLE instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2609,7 +3890,10 @@ ### ### * Return value: the data read ### - "3d_sample" : ["anyvector",["int","anyvector","int","short","int","int","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector"],"ReadMem"], + "3d_sample" : { "result" : "anyvector", + "arguments" : ["int","anyvector","int","short","int","int","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.3d.load......`` : vISA 3D_LOAD instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2623,7 +3907,10 @@ ### ### * Return value: the data read ### - "3d_load" : ["anyvector",["int","anyvector","int","short","int","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector"],"ReadMem"], + "3d_load" : { "result" : "anyvector", + "arguments" : ["int","anyvector","int","short","int","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.avs.`` : vISA AVS instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2651,44 +3938,76 @@ ### ### SIMD Control Flow: channel enable is ignored. ### - "avs" : ["anyvector",["int","int","int","float","float","float","float","float","int","int","int","float","int","char"],"ReadMem"], + "avs" : { "result" : "anyvector", + "arguments" : ["int","int","int","float","float","float","float","float","int","int","int","float","int","char"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.barrier`` : vISA BARRIER instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ### - "barrier" : ["void",[],"Convergent"], + "barrier" : { "result" : "void", + "arguments" : [], + "attributes" : "Convergent" + }, ### ``llvm.genx.sbarrier`` : vISA SBARRIER instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ### ### * arg0: i8 signal flag, constant ### - "sbarrier" : ["void",["char"],"Convergent"], + "sbarrier" : { "result" : "void", + "arguments" : ["char"], + "attributes" : "Convergent" + }, +### ``llvm.genx.nbarrier`` : vISA NBARRIER instruction +### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +### +### * arg0: i8 signal flag, constant +### * arg1: i8 barrier id +### * arg2: i8 number of threads +### + "nbarrier" : { "result" : "void", + "arguments" : ["char","char","char"], + "attributes" : "Convergent" + }, ### ``llvm.genx.cache.flush`` : vISA CACHE_FLUSH instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ### - "cache_flush" : ["void",[],"None"], + "cache_flush" : { "result" : "void", + "arguments" : [], + "attributes" : "None" + }, ### ``llvm.genx.fence`` : vISA FENCE instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ### ### * arg0: i8 mask, constant ### - "fence" : ["void",["char"],"None"], + "fence" : { "result" : "void", + "arguments" : ["char"], + "attributes" : "None" + }, ### ``llvm.genx.wait`` : vISA WAIT instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ### ### * arg0: i8 thread mask ### - "wait" : ["void",["char"],"None"], + "wait" : { "result" : "void", + "arguments" : ["char"], + "attributes" : "None" + }, ### ``llvm.genx.yield`` : vISA YIELD instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ### - "yield" : ["void",[],"None"], + "yield" : { "result" : "void", + "arguments" : [], + "attributes" : "None" + }, ### ``llvm.genx.raw.send...`` : vISA RAW_SEND instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2721,7 +4040,10 @@ ### predicatable. For a predicatable message, it must be a vector of i1 with ### width determining the execution size. ### - "raw_send" : ["anyvector",["int","anyint","int","int","anyvector",0],"None"], + "raw_send" : { "result" : "anyvector", + "arguments" : ["int","anyint","int","int","anyvector",0], + "attributes" : "None" + }, ### ``llvm.genx.raw.send.noresult..`` : vISA RAW_SEND instruction with no result ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2743,7 +4065,10 @@ ### predicatable. For a predicatable message, it must be a vector of i1 with ### width determining the execution size. ### - "raw_send_noresult" : ["void",["int","anyint","int","int","anyvector"],"None"], + "raw_send_noresult" : { "result" : "void", + "arguments" : ["int","anyint","int","int","anyvector"], + "attributes" : "None" + }, ### ``llvm.genx.raw.sends....`` : vISA RAW_SENDS instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2779,7 +4104,10 @@ ### predicatable. For a predicatable message, it must be a vector of i1 with ### width determining the execution size. ### - "raw_sends" : ["anyvector",["int","anyint","char","int","int","anyvector","anyvector",0],"None"], + "raw_sends" : { "result" : "anyvector", + "arguments" : ["int","anyint","char","int","int","anyvector","anyvector",0], + "attributes" : "None" + }, ### ``llvm.genx.raw.sends.noresult...`` : vISA RAW_SENDS instruction with no result ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2805,7 +4133,10 @@ ### predicatable. For a predicatable message, it must be a vector of i1 with ### width determining the execution size. ### - "raw_sends_noresult" : ["void",["int","anyint","char","int","int","anyvector","anyvector"],"None"], + "raw_sends_noresult" : { "result" : "void", + "arguments" : ["int","anyint","char","int","int","anyvector","anyvector"], + "attributes" : "None" + }, ### ``llvm.genx.raw.send2...`` : vISA RAW_SEND instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2826,7 +4157,10 @@ ### ### This intrinsic supports full encoding of the vISA raw_send instruction. ### - "raw_send2" : ["anyvector",["char","char","anyvector","char","char","char","int","int","anyvector",0],"None"], + "raw_send2" : { "result" : "anyvector", + "arguments" : ["char","char","anyvector","char","char","char","int","int","anyvector",0], + "attributes" : "None" + }, ### ``llvm.genx.raw.send2.noresult..`` : vISA RAW_SEND instruction with no result ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2845,7 +4179,10 @@ ### ### This intrinsic supports full encoding of the vISA raw_send instruction with no result. ### - "raw_send2_noresult" : ["void",["char","char","anyvector","char","char","int","int","anyvector"],"None"], + "raw_send2_noresult" : { "result" : "void", + "arguments" : ["char","char","anyvector","char","char","int","int","anyvector"], + "attributes" : "None" + }, ### ``llvm.genx.raw.sends2....`` : vISA RAW_SENDS instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2867,7 +4204,10 @@ ### ### This intrinsic supports full encoding of the vISA raw_sends instruction. ### - "raw_sends2" : ["anyvector",["char","char","anyvector","char","char","char","char","int","int","anyvector","anyvector",0],"None"], + "raw_sends2" : { "result" : "anyvector", + "arguments" : ["char","char","anyvector","char","char","char","char","int","int","anyvector","anyvector",0], + "attributes" : "None" + }, ### ``llvm.genx.raw.sends2.noresult...`` : vISA RAW_SENDS instruction with no result ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2886,7 +4226,10 @@ ### ### This intrinsic supports full encoding of the vISA raw_sends instruction with no result. ### - "raw_sends2_noresult" : ["void",["char","char","anyvector","char","char","char","int","int","anyvector","anyvector"],"None"], + "raw_sends2_noresult" : { "result" : "void", + "arguments" : ["char","char","anyvector","char","char","char","int","int","anyvector","anyvector"], + "attributes" : "None" + }, ## --------------------------- ### Video Analytics Instrinsics @@ -2903,7 +4246,10 @@ ### ### * Return value: v64i16 or v16i16 matrix, depending on properties value ### - "va_convolve2d" : ["anyint",["int","int","float","float","int"],"ReadMem"], + "va_convolve2d" : { "result" : "anyint", + "arguments" : ["int","int","float","float","int"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.va.hdc.convolve2d`` vISA VA HDC 2d Convolve instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2917,7 +4263,10 @@ ### * arg6: i16 destination surface x-offset ### * arg7: i16 destination surface y-offset ### - "va_hdc_convolve2d" : ["void",["int","int","float","float","int","int","short","short"],"None"], + "va_hdc_convolve2d" : { "result" : "void", + "arguments" : ["int","int","float","float","int","int","short","short"], + "attributes" : "None" + }, ### ``llvm.genx.va.erode.`` vISA VA Erode instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2930,7 +4279,10 @@ ### ### * Return value: vXi32 ### - "va_erode" : ["anyint",["int","int","float","float","int"],"ReadMem"], + "va_erode" : { "result" : "anyint", + "arguments" : ["int","int","float","float","int"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.va.hdc.erode`` vISA VA HDC Erode instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2943,7 +4295,10 @@ ### * arg5: i16 destination surface x-offset ### * arg6: i16 destination surface y-offset ### - "va_hdc_erode" : ["void",["int","int","float","float","int","short","short"],"None"], + "va_hdc_erode" : { "result" : "void", + "arguments" : ["int","int","float","float","int","short","short"], + "attributes" : "None" + }, ### ``llvm.genx.va.dilate.`` vISA VA Dilate instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2956,7 +4311,10 @@ ### ### * Return value: vXi32 ### - "va_dilate" : ["anyint",["int","int","float","float","int"],"ReadMem"], + "va_dilate" : { "result" : "anyint", + "arguments" : ["int","int","float","float","int"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.va.hdc.dilate`` vISA VA HDC Dilate instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2969,7 +4327,10 @@ ### * arg5: i16 destination surface x-offset ### * arg6: i16 destination surface y-offset ### - "va_hdc_dilate" : ["void",["int","int","float","float","int","short","short"],"None"], + "va_hdc_dilate" : { "result" : "void", + "arguments" : ["int","int","float","float","int","short","short"], + "attributes" : "None" + }, ### ``llvm.genx.va.minmax.`` vISA MinMax instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2981,7 +4342,10 @@ ### ### * Return: v32i8 or v16i16 depending on the surface format ### - "va_minmax" : ["anyint",["int","float","float","int"],"ReadMem"], + "va_minmax" : { "result" : "anyint", + "arguments" : ["int","float","float","int"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.va.minmax.filter.`` vISA MinMax Filter instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2996,7 +4360,10 @@ ### ### * Return: vXi8 or vXi16 depending on return data size and format ### - "va_minmax_filter" : ["anyint",["int","int","float","float","int","int","int"],"ReadMem"], + "va_minmax_filter" : { "result" : "anyint", + "arguments" : ["int","int","float","float","int","int","int"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.va.hdc.minmax.filter`` vISA HDC MinMax Filter instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3011,7 +4378,10 @@ ### * arg7: i16 destination surface x-offset ### * arg8: i16 destination surface y-offset ### - "va_hdc_minmax_filter" : ["void",["int","int","float","float","int","int","int","short","short"],"None"], + "va_hdc_minmax_filter" : { "result" : "void", + "arguments" : ["int","int","float","float","int","int","int","short","short"], + "attributes" : "None" + }, ### ``llvm.genx.va.bool.centroid.`` vISA Boolean Centroid instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3024,7 +4394,10 @@ ### ### * Return: v16i8 or v16i16 depending on surface format ### - "va_bool_centroid" : ["anyint",["int","float","float","char","char"],"ReadMem"], + "va_bool_centroid" : { "result" : "anyint", + "arguments" : ["int","float","float","char","char"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.va.centroid.`` vISA Centroid instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3036,7 +4409,10 @@ ### ### * Return: v32i32 ### - "va_centroid" : ["anyint",["int","float","float","char"],"ReadMem"], + "va_centroid" : { "result" : "anyint", + "arguments" : ["int","float","float","char"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.va.1d.convolve.horizontal.`` vISA 1d convolve horizontal instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3049,7 +4425,10 @@ ### ### * Return: v16i16 or v64i16 depending on mode ### - "va_1d_convolve_horizontal" : ["anyint",["int","int","float","float","int"],"ReadMem"], + "va_1d_convolve_horizontal" : { "result" : "anyint", + "arguments" : ["int","int","float","float","int"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.va.hdc.1d.convolve.horizontal`` vISA HDC 1d convolve horizontal instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3063,7 +4442,10 @@ ### * arg6: i16 destination surface x-offset ### * arg7: i16 destination surface y-offset ### - "va_hdc_1d_convolve_horizontal" : ["void",["int","int","float","float","int","int","short","short"],"None"], + "va_hdc_1d_convolve_horizontal" : { "result" : "void", + "arguments" : ["int","int","float","float","int","int","short","short"], + "attributes" : "None" + }, ### ``llvm.genx.va.1d.convolve.vertical.`` vISA 1d convolve vertical instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3076,7 +4458,10 @@ ### ### * Return: v16i16 or v64i16 depending on mode ### - "va_1d_convolve_vertical" : ["anyint",["int","int","float","float","int"],"ReadMem"], + "va_1d_convolve_vertical" : { "result" : "anyint", + "arguments" : ["int","int","float","float","int"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.va.hdc.1d.convolve.vertical`` vISA HDC 1d convolve vertical instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3090,7 +4475,10 @@ ### * arg6: i16 destination surface x-offset ### * arg7: i16 destination surface y-offset ### - "va_hdc_1d_convolve_vertical" : ["void",["int","int","float","float","int","int","short","short"],"None"], + "va_hdc_1d_convolve_vertical" : { "result" : "void", + "arguments" : ["int","int","float","float","int","int","short","short"], + "attributes" : "None" + }, ### ``llvm.genx.va.1pixel.convolve..`` vISA 1 Pixel Convolve instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3104,7 +4492,10 @@ ### ### * Return: v64i16 or v16i16 depending on mode. ### - "va_1pixel_convolve" : ["anyint",["int","int","float","float","int","anyint"],"ReadMem"], + "va_1pixel_convolve" : { "result" : "anyint", + "arguments" : ["int","int","float","float","int","anyint"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.va.hdc.1pixel.convolve`` vISA HDC 1 Pixel Convolve instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3119,7 +4510,10 @@ ### * arg7: i16 destination surface x-offset ### * arg8: i16 destination surface y-offset ### - "va_hdc_1pixel_convolve" : ["void",["int","int","float","float","int","anyint","int","short","short"],"None"], + "va_hdc_1pixel_convolve" : { "result" : "void", + "arguments" : ["int","int","float","float","int","anyint","int","short","short"], + "attributes" : "None" + }, ### ``llvm.genx.va.1pixel.convolve.1x1mode.`` vISA 1 Pixel Convolve (1x1 mode) instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3131,7 +4525,10 @@ ### ### * Return: v64i16 or v16i16 depending on mode. ### - "va_1pixel_convolve_1x1mode" : ["anyint",["int","int","float","float"],"ReadMem"], + "va_1pixel_convolve_1x1mode" : { "result" : "anyint", + "arguments" : ["int","int","float","float"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.va.lbp.creation.`` vISA LBP Creation instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3143,7 +4540,10 @@ ### ### * Return: v64i8 or v128i8 depending on mode ### - "va_lbp_creation" : ["anyint",["int","float","float","int"],"ReadMem"], + "va_lbp_creation" : { "result" : "anyint", + "arguments" : ["int","float","float","int"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.va.hdc.lbp.creation`` vISA HDC LBP Creation instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3156,7 +4556,10 @@ ### * arg5: i16 destination surface x-offset ### * arg6: i16 destination surface y-offset ### - "va_hdc_lbp_creation" : ["void",["int","float","float","int","int","short","short"],"None"], + "va_hdc_lbp_creation" : { "result" : "void", + "arguments" : ["int","float","float","int","int","short","short"], + "attributes" : "None" + }, ### ``llvm.genx.va.lbp.correlation.`` vISA LBP Correlation instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3168,7 +4571,10 @@ ### ### * Return: v64i8 ### - "va_lbp_correlation" : ["anyint",["int","float","float","short"],"ReadMem"], + "va_lbp_correlation" : { "result" : "anyint", + "arguments" : ["int","float","float","short"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.va.hdc.lbp.correlation`` vISA HDC LBP Correlation instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3181,7 +4587,10 @@ ### * arg5: i16 destination surface x-offset ### * arg6: i16 destination surface y-offset ### - "va_hdc_lbp_correlation" : ["void",["int","float","float","short","int","short","short"],"None"], + "va_hdc_lbp_correlation" : { "result" : "void", + "arguments" : ["int","float","float","short","int","short","short"], + "attributes" : "None" + }, ### ``llvm.genx.va.correlation.search.`` vISA Correlation Search instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3198,7 +4607,10 @@ ### ### * Return: vXi32 ### - "va_correlation_search" : ["anyint",["int","float","float","float","float","char","char","char","char"],"ReadMem"], + "va_correlation_search" : { "result" : "anyint", + "arguments" : ["int","float","float","float","float","char","char","char","char"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.va.flood.fill..`` vISA Flood Fill instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3211,7 +4623,10 @@ ### ### * Return: v8i16 ### - "va_flood_fill" : ["anyint",["char","anyint","short","short","short"],"ReadMem"], + "va_flood_fill" : { "result" : "anyint", + "arguments" : ["char","anyint","short","short","short"], + "attributes" : "ReadMem" + }, ##-------------------------------------------------------------------- ### CM codegen internal intrinsics @@ -3229,7 +4644,10 @@ ### reduction functions (cm_sum etc) whose behavior is sensitive to the ### surrounding SIMD CF context. It is lowered by the CMSimdCFLowering pass. ### - "simdcf_predicate" : ["anyvector",[0,0],"None"], + "simdcf_predicate" : { "result" : "anyvector", + "arguments" : [0,0], + "attributes" : "None" + }, ### llvm.genx.simdcf.any. : simd cf marker intrinsic. ### @@ -3243,7 +4661,10 @@ ### This is generated by clang codegen in the implementation of SIMD control ### flow, and lowered by the CMSimdCFLowering pass. ### - "simdcf_any" : ["bool",["anyvector"],"None"], + "simdcf_any" : { "result" : "bool", + "arguments" : ["anyvector"], + "attributes" : "None" + }, ### ``llvm.genx.unmask.begin`` : simd-unmask region begin ### @@ -3254,7 +4675,10 @@ ### the old mask in a temp. ### this intrinsic will be replaced by genx.simdcf.unmask by SimdCFLowering ### - "unmask_begin" : ["int",[],"WriteMem,SideEffects"], + "unmask_begin" : { "result" : "int", + "arguments" : [], + "attributes" : "WriteMem,SideEffects" + }, ### ``llvm.genx.unmask.end`` : simd-unmask region end ### @@ -3265,7 +4689,10 @@ ### region, set execution mask back using the temp value from unmask-begin. ### this intrinsic will be replaced by genx.simdcf.remask by SimdCFLowering ### - "unmask_end" : ["void",["int"],"WriteMem,SideEffects"], + "unmask_end" : { "result" : "void", + "arguments" : ["int"], + "attributes" : "WriteMem,SideEffects" + }, ### ``llvm.genx.lane.id`` : implicit lane-id in the simd-fork statement ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3273,7 +4700,10 @@ ### ### * Return value: i32 ### - "lane_id" : ["int",[],"NoMem"], + "lane_id" : { "result" : "int", + "arguments" : [], + "attributes" : "NoMem" + }, ### ``llvm.genx.local.*.`` : read local ID register ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3286,36 +4716,18 @@ ### ### This is generated by clang codegen and lowered by CMImpParam. ### - "local_id" : ["anyvector",[],"NoMem"], - "local_id16" : ["anyvector",[],"NoMem"], - "local_size" : ["anyvector",[],"NoMem"], - -### ``llvm.genx.group.or.local.size`` : read local or group size register -### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -### -### * Return value: v8i32 -### -### [GROUP_X, GROUP_Y, GROUP_Z, LOCAL_X, LOCAL_Y, LOCAL_Z, UNDEF, UNDEF] -### -### This is generated by CMImpParam. This is to match OpenCL thread -### payload layout. -### - "group_or_local_size" : ["int8",[],"NoMem"], - -### ``llvm.genx.local.id.*`` : read local ID register -### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -### * ``llvm.genx.local.id.x`` : read implicit arg local id x -### * ``llvm.genx.local.id.y`` : read implicit arg local id y -### * ``llvm.genx.local.id.z`` : read implicit arg local id z -### -### * Return value: v8i16 - SIMD8 dispatch but only the first componentis used. -### -### This is generated by CMImpParam. This is to match OpenCL thread -### payload layout. -### - "local_id_x" : ["short8",[],"NoMem"], - "local_id_y" : ["short8",[],"NoMem"], - "local_id_z" : ["short8",[],"NoMem"], + "local_id" : { "result" : "anyvector", + "arguments" : [], + "attributes" : "NoMem" + }, + "local_id16" : { "result" : "anyvector", + "arguments" : [], + "attributes" : "NoMem" + }, + "local_size" : { "result" : "anyvector", + "arguments" : [], + "attributes" : "NoMem" + }, ### ``llvm.genx.group.count.`` : read group count register ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3325,7 +4737,10 @@ ### ### This is generated by clang codegen and lowered by CMImpParam. ### - "group_count" : ["anyvector",[],"NoMem"], + "group_count" : { "result" : "anyvector", + "arguments" : [], + "attributes" : "NoMem" + }, ### ``llvm.genx.get.scoreboard.bti`` : get scoreboard surface implicit ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3334,7 +4749,10 @@ ### ###This is generated by clang codegen and lowered by CMImpParam. ### - "get_scoreboard_bti" : ["int",[],"NoMem"], + "get_scoreboard_bti" : { "result" : "int", + "arguments" : [], + "attributes" : "NoMem" + }, ### ``llvm.genx.get.scoreboard.deltas`` : get scoreboard deltas ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3343,7 +4761,10 @@ ### ### This is generated by clang codegen and lowered by CMImpParam. ### - "get_scoreboard_deltas" : ["char16",[],"NoMem"], + "get_scoreboard_deltas" : { "result" : "char16", + "arguments" : [], + "attributes" : "NoMem" + }, ### ``llvm.genx.get.scoreboard.depcnt`` : get the maximal scoreboard dependency count ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3352,7 +4773,10 @@ ### ### This is generated by clang codegen and lowered by CMImpParam. ### - "get_scoreboard_depcnt" : ["int",[],"NoMem"], + "get_scoreboard_depcnt" : { "result" : "int", + "arguments" : [], + "attributes" : "NoMem" + }, ### ``llvm.genx.predefined.surface`` : get predefined surface ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3361,7 +4785,10 @@ ### ### This is generated by clang codegen when predefined surface is accessed. ### - "predefined_surface" : ["int",["int"],"NoMem"], + "predefined_surface" : { "result" : "int", + "arguments" : ["int"], + "attributes" : "NoMem" + }, ##-------------------------------------------------------------------- ### GenX backend internal intrinsics @@ -3383,8 +4810,14 @@ ### There are two variants simply because there is no way of saying here ### that an argument can have any scalar or vector type. ### - "constanti" : ["anyint",[0],"NoMem"], - "constantf" : ["anyfloat",[0],"NoMem"], + "constanti" : { "result" : "anyint", + "arguments" : [0], + "attributes" : "NoMem" + }, + "constantf" : { "result" : "anyfloat", + "arguments" : [0], + "attributes" : "NoMem" + }, ### llvm.genx.convert. : convert register category (non address) ### @@ -3402,7 +4835,10 @@ ### of a value of category other than general. Thus the input and output ### might be both the same category, but not both general. ### - "convert" : ["anyint",[0],"NoMem"], + "convert" : { "result" : "anyint", + "arguments" : [0], + "attributes" : "NoMem" + }, ### llvm.genx.convert.addr. : convert to address register category ### @@ -3418,7 +4854,10 @@ ### stop the address conversion falling outside of the register into which it ### points to avoid going out of spec (bug 4395). ### - "convert_addr" : ["anyint",[0,"short"],"NoMem"], + "convert_addr" : { "result" : "anyint", + "arguments" : [0,"short"], + "attributes" : "NoMem" + }, ### llvm.genx.constantpred. : load constant predicate (i1 or vector of i1) ### @@ -3430,7 +4869,10 @@ ### We could just use a bitcast, except that EarlyCSE follows ### GenXConstantMaterialization and it has a habit of putting the constant ### back in the wrregion. - "constantpred" : ["anyint",[0],"NoMem"], + "constantpred" : { "result" : "anyint", + "arguments" : [0], + "attributes" : "NoMem" + }, ### llvm.genx.add.addr.. : add an offset onto an address register ### @@ -3443,7 +4885,10 @@ ### a region access, GenXCategoryConversion converts it into this intrinsic ### so that it will be considered an add to an address register. ### - "add_addr" : ["anyint",["anyint",0],"NoMem"], + "add_addr" : { "result" : "anyint", + "arguments" : ["anyint",0], + "attributes" : "NoMem" + }, ### llvm.genx.rdpredregion.. : read region at specified offset from a predicate ### @@ -3456,7 +4901,10 @@ ### in the return type, and must be 4, 8 or 16. ### The offset must be a multiple of the number of elements. ### - "rdpredregion" : ["anyint",["anyint","int"],"NoMem"], + "rdpredregion" : { "result" : "anyint", + "arguments" : ["anyint","int"], + "attributes" : "NoMem" + }, ### llvm.genx.wrpredregion.. : write region at specified offset into a predicate ### @@ -3470,7 +4918,10 @@ ### in the "subvector to write" arg, and must be 4, 8 or 16. ### The offset must be a multiple of the number of elements. ### - "wrpredregion" : ["anyint",[0,"anyint","int"],"NoMem"], + "wrpredregion" : { "result" : "anyint", + "arguments" : [0,"anyint","int"], + "attributes" : "NoMem" + }, ### llvm.genx.wrpredpredregion.. : predicated write region at specified offset ### into a predicate @@ -3490,7 +4941,10 @@ ### intrinsic is valid only if the predicate is an EM value, and the subvector ### operand is the result of a cmp (which is then baled in). ### - "wrpredpredregion" : ["anyint",[0,"anyint","int",0],"NoMem"], + "wrpredpredregion" : { "result" : "anyint", + "arguments" : [0,"anyint","int",0], + "attributes" : "NoMem" + }, ### ``llvm.genx.wrconstregion....`` : write a constant region ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3519,7 +4973,10 @@ ### The operands are the same as llvm.genx.wrregion so it can mostly be handled ### by the same code as llvm.genx.wrregion. ### - "wrconstregion" : ["anyvector",[0,"anyvector","int","int","int","anyint","int","anyint"],"NoMem"], + "wrconstregion" : { "result" : "anyvector", + "arguments" : [0,"anyvector","int","int","int","anyint","int","anyint"], + "attributes" : "NoMem" + }, ### ``llvm.genx.output`` : Mark output arguments ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3530,7 +4987,10 @@ ### This intrinsic call only extends the live range of marked arguments and ### emits no code. ### - "output" : ["void",["vararg"],"None"], + "output" : { "result" : "void", + "arguments" : ["vararg"], + "attributes" : "None" + }, ### ``llvm.genx.output.1.`` : Mark output argument ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3543,7 +5003,10 @@ ### This intrinsic call only extends the live range of marked argument and ### emits no code. ### - "output_1" : ["void",["any"],"None"], + "output_1" : { "result" : "void", + "arguments" : ["any"], + "attributes" : "None" + }, ## ``llvm.genx.print.buffer`` : read stateless pointer to print buffer ## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3553,7 +5016,10 @@ ## ## this is generated by clang codegen and lowered by cmimpparam. ## - "print_buffer" : ["long",[],"None"], + "print_buffer" : { "result" : "long", + "arguments" : [], + "attributes" : "None" + }, ## ``llvm.genx.print.format.index`` : add printf format string to collection ## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3563,7 +5029,10 @@ ## ## * Return value: the vector value read ## - "print_format_index" : ["int",["anyptr"],"NoMem"], + "print_format_index" : { "result" : "int", + "arguments" : ["anyptr"], + "attributes" : "NoMem" + }, ## ``llvm.genx.address.convert`` : convert dataport address to integer ## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3577,7 +5046,10 @@ ## used across all memory instructions. This is needed to encode ## SPIRV with appropriate types for kernel arguments. ## - "address_convert" : ["anyint",["anyptr"],"NoMem"], + "address_convert" : { "result" : "anyint", + "arguments" : ["anyptr"], + "attributes" : "NoMem" + }, ## ``llvm.genx.gaddr`` : take an address of a global variable ## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3589,7 +5061,10 @@ ## ## * Return value: i64/i32 (depending on data layout) value of pointer ## - "gaddr" : ["anyint", ["anyptr"], "NoMem"], + "gaddr" : { "result" : "anyint", + "arguments" : ["anyptr"], + "attributes" : "NoMem" + }, ## ``llvm.genx.jump.table`` : CMC internal, no VISA ## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3603,5 +5078,358 @@ ## will be used by visa switchjmp as index. Return value and arg1-N are ## used to make ir semantically legal. ## - "jump_table" : ["anyptr", ["anyint", "vararg"], "NoMem"] + "jump_table" : { "result" : "anyptr", + "arguments" : ["anyint", "vararg"], + "attributes" : "NoMem" + }, + +## ``llvm.genx.write.predef.surface`` : write predefined surface variable +## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +## +## * arg0: ptr predefined surface variable +## * arg1: i32 value to write +## +## This corresponds to MOVS visa instruction and utilizes technique of using +## global variable in LLVM IR for predefined surfaces. +## + "write_predef_surface" : { "result": "void", + "arguments" : ["anyptr", "int"], + "attributes" : "WriteMem", + }, + +## Internal VC memory intrinsics. +## These versions are supposed to use predefined visa variables like %bss. +## Intrinsics are supposed to be internal to VC backend. + +## ``llvm.genx.dword.atomic2.*.predef.surface`` : dword atomic with binary operator with predefined surface +## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +## * ``llvm.genx.dword.atomic2.add.predef.surface`` : vISA DWORD_ATOMIC ADD instruction +## * ``llvm.genx.dword.atomic2.sub.predef.surface`` : vISA DWORD_ATOMIC SUB instruction +## * ``llvm.genx.dword.atomic2.min.predef.surface`` : vISA DWORD_ATOMIC MIN instruction +## * ``llvm.genx.dword.atomic2.max.predef.surface`` : vISA DWORD_ATOMIC MAX instruction +## * ``llvm.genx.dword.atomic2.xchg.predef.surface`` : vISA DWORD_ATOMIC XCHG instruction +## * ``llvm.genx.dword.atomic2.and.predef.surface`` : vISA DWORD_ATOMIC AND instruction +## * ``llvm.genx.dword.atomic2.or.predef.surface`` : vISA DWORD_ATOMIC OR instruction +## * ``llvm.genx.dword.atomic2.xor.predef.surface`` : vISA DWORD_ATOMIC XOR instruction +## * ``llvm.genx.dword.atomic2.imin.predef.surface`` : vISA DWORD_ATOMIC IMIN instruction +## * ``llvm.genx.dword.atomic2.imax.predef.surface`` : vISA DWORD_ATOMIC IMAX instruction +## +## * (Exec_size inferred from element offset type) +## * arg0: vXi1 predicate (overloaded) +## * arg1: ptr predefined surface (overloaded) +## * arg2: vXi32 element offset in bytes (overloaded) +## * arg3: vXi32 src +## +## * Return value: vXi32 the old value read +## +## Predicate, element offset, src, and the return value must all have the +## same vector width, which must be 1, 8 or 16. +## + "dword_atomic2_add_predef_surface" : { "result" : "anyvector", + "arguments" : ["anyvector","anyptr","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_sub_predef_surface" : { "result" : "anyvector", + "arguments" : ["anyvector","anyptr","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_min_predef_surface" : { "result" : "anyvector", + "arguments" : ["anyvector","anyptr","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_max_predef_surface" : { "result" : "anyvector", + "arguments" : ["anyvector","anyptr","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_xchg_predef_surface" : { "result" : "anyvector", + "arguments" : ["anyvector","anyptr","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_and_predef_surface" : { "result" : "anyvector", + "arguments" : ["anyvector","anyptr","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_or_predef_surface" : { "result" : "anyvector", + "arguments" : ["anyvector","anyptr","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_xor_predef_surface" : { "result" : "anyvector", + "arguments" : ["anyvector","anyptr","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_imin_predef_surface" : { "result" : "anyvector", + "arguments" : ["anyvector","anyptr","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_imax_predef_surface" : { "result" : "anyvector", + "arguments" : ["anyvector","anyptr","anyint",0], + "attributes" : "None", + }, + +## ``llvm.genx.dword.atomic2.*.predef.surface`` : dword atomic with fmin/fmax operation with predefined surface +## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +## * ``llvm.genx.dword.atomic2.fmin.predef.surface`` : vISA DWORD_ATOMIC FMIN instruction +## * ``llvm.genx.dword.atomic2.fmax.predef.surface`` : vISA DWORD_ATOMIC FMAX instruction +## * ``llvm.genx.dword.atomic2.fadd.predef.surface`` : vISA DWORD_ATOMIC FADD instruction +## * ``llvm.genx.dword.atomic2.fsub.predef.surface`` : vISA DWORD_ATOMIC FSUB instruction +## +## * (Exec_size inferred from element offset type) +## * arg0: vXi1 predicate (overloaded) +## * arg1: ptr predefined surface (overloaded) +## * arg2: vXi32 element offset in bytes (overloaded) +## * arg3: vXfloat src +## +## * Return value: vXfloat the old value read +## +## Predicate, element offset, src, and the return value must all have the +## same vector width, which must be 1, 8 or 16. +## + "dword_atomic2_fmin_predef_surface" : { "result" : "anyvector", + "arguments" : ["anyvector","anyptr","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_fmax_predef_surface" : { "result" : "anyvector", + "arguments" : ["anyvector","anyptr","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_fadd_predef_surface" : { "result" : "anyvector", + "arguments" : ["anyvector","anyptr","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_fsub_predef_surface" : { "result" : "anyvector", + "arguments" : ["anyvector","anyptr","anyint",0], + "attributes" : "None", + }, + +## ``llvm.genx.dword.atomic2.*.predef.surface`` : dword atomic with inc/dec operation with predefined surface +## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +## * ``llvm.genx.dword.atomic2.inc.predef.surface`` : vISA DWORD_ATOMIC INC instruction +## * ``llvm.genx.dword.atomic2.dec.predef.surface`` : vISA DWORD_ATOMIC DEC instruction +## +## * (Exec_size inferred from element offset type) +## * arg0: vXi1 predicate (overloaded) +## * arg1: ptr predefined surface (overloaded) +## * arg2: vXi32 element offset in bytes (overloaded) +## +## * Return value: vXi32 the old value read +## +## Predicate, element offset, src, and the return value must all have the +## same vector width, which must be 1, 8 or 16. +## + "dword_atomic2_inc_predef_surface" : { "result" : "anyvector", + "arguments" : ["anyvector","anyptr","anyint"], + "attributes" : "None", + }, + "dword_atomic2_dec_predef_surface" : { "result" : "anyvector", + "arguments" : ["anyvector","anyptr","anyint"], + "attributes" : "None", + }, + +## ``llvm.genx.dword.atomic2.cmpxchg.predef.surface`` : vISA DWORD_ATOMIC CMPXCHG instruction with predefined surface +## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +## +## * (Exec_size inferred from element offset type) +## * arg0: vXi1 predicate (overloaded) +## * arg1: ptr predefined surface (overloaded) +## * arg2: vXi32 element offset in bytes (overloaded) +## * arg3: vXi32 src0 +## * arg4: vXi32 src1 +## +## * Return value: vXi32 the old value read +## +## Predicate, element offset, src, and the return value must all have the +## same vector width, which must be 1, 8 or 16. +## + "dword_atomic2_cmpxchg_predef_surface" : { "result" : "anyvector", + "arguments" : ["anyvector","anyptr","anyint",0,0], + "attributes" : "None", + }, + +## ``llvm.genx.dword.atomic2.fcmpwr.predef.surface`` : vISA DWORD_ATOMIC FCMPWR instruction with predefined surface +## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +## +## * (Exec_size inferred from element offset type) +## * arg0: vXi1 predicate (overloaded) +## * arg1: ptr predefined surface (overloaded) +## * arg2: vXi32 element offset in bytes (overloaded) +## * arg3: vXfloat src0 +## * arg4: vXfloat src1 +## +## * Return value: vXfloat the old value read +## +## Predicate, element offset, src, and the return value must all have the +## same vector width, which must be 1, 8 or 16. +## + "dword_atomic2_fcmpwr_predef_surface" : { "result" : "anyvector", + "arguments" : ["anyvector","anyptr","anyint",0,0], + "attributes" : "None", + }, + +## ``llvm.genx.gather.masked.scaled2.predef.surface`` : vISA GATHER_SCALED instruction with predefined surface +## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +## +## * (Exec_size inferred from element offset type) +## * arg0: i32 log2 num blocks, constant (0/1/2 for num blocks 1/2/4) +## * arg1: i16 scale, constant +## * arg2: ptr predefined surface (overloaded) +## * arg3: i32 global offset in bytes +## * arg4: vXi32 element offset in bytes (overloaded) +## * arg5: vXi1 predicate (overloaded) +## +## * Return value: vXi32/float the data read +## + "gather_masked_scaled2_predef_surface" : { "result" : "anyvector", + "arguments" : ["int","short","anyptr","int","anyint","anyvector"], + "attributes" : "ReadMem", + }, + +## ``llvm.genx.gather4.masked.scaled2.predef.surface`` : vISA GATHER4_SCALED instruction with predefined surface +## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +## +## * (Exec_size inferred from element offset type) +## * arg0: i32 channel mask, constant +## * arg1: i16 scale, constant +## * arg2: ptr predefined surface (overloaded) +## * arg3: i32 global offset in bytes +## * arg4: vXi32 element offset in bytes +## * arg5: vXi1 predicate (overloaded) +## +## * Return value: vXi32/float the data read +## + "gather4_masked_scaled2_predef_surface" : { "result" : "anyvector", + "arguments" : ["int","short","anyptr","int","anyint","anyvector"], + "attributes" : "ReadMem", + }, + +## ``llvm.genx.scatter.scaled.predef.surface`` : vISA SCATTER_SCALED instruction with predefined surface +## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +## +## * (Exec_size inferred from element offset type) +## * arg0: vXi1 predicate (overloaded) +## * arg1: i32 log2 num blocks, constant (0/1/2 for num blocks 1/2/4) +## * arg2: i16 scale, constant +## * arg3: ptr predefined surface (overloaded) +## * arg4: i32 global offset in bytes +## * arg5: vXi32 element offset (overloaded) +## * arg6: data to write (overloaded) +## +## The vector width of the element offset arg is the number of elements to +## write, which must be power of 2 and less than or equal to 32. +## +## The predicate arg must have the same vector width. +## +## The data type to write must have UD, D or F type. For 1 and 2 byte (1 x num +## blocks) accesses the upper bytes will be ignored. +## + "scatter_scaled_predef_surface" : { "result" : "void", + "arguments" : ["anyvector","int","short","anyptr","int","anyint","anyvector"], + "attributes" : "None", + }, + +## ``llvm.genx.scatter4.scaled.predef.surface`` : vISA SCATTER4_SCALED instruction with predefined surface +## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +## +## * (Exec_size inferred from element offset type) +## * arg0: vXi1 predicate (overloaded) +## * arg1: i32 channel mask, constant +## * arg2: i16 scale, constant +## * arg3: ptr predefined surface (overloaded) +## * arg4: i32 global offset in bytes +## * arg5: vXi32 element offset in bytes (overloaded) +## * arg6: data to write (overloaded) +## +## The vector width of the element offset arg is the number of elements to +## write, which must be 8 or 16. +## The predicate arg must have the same vector width. +## The instruction writes up to 4 channels per element, with the lowest 4 +## bits of the channel mask arg giving the mask of channels _not_ to read. +## The number of 0 bits in that lower 4 bits of the channel mask arg is the +## number of channels to write per element. +## The channels to write must be contiguous and starting at channel 0. +## The vector width of the data to write must be the number of elements +## times the number of channels to write per element. +## The element type of the data to write must be i32 or float. +## + "scatter4_scaled_predef_surface" : { "result" : "void", + "arguments" : ["anyvector","int","short","anyptr","int","anyint","anyvector"], + "attributes" : "None", + }, + +## ``llvm.genx.oword.ld*.predef.surface`` : oword load instruction with predefined surface +## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +## * ``llvm.genx.oword.ld.predef.surface`` : vISA OWORD_LD instruction +## * ``llvm.genx.oword.ld.unaligned.predef.surface`` : vISA OWORD_LD_UNALIGNED instruction +## +## * (log2 number of owords inferred from return type) +## * arg0: i32 is_modified, constant +## * arg1: ptr predefined surface variable (overloaded) +## * arg2: i32 offset (in owords for .ld / in bytes for .ld.unaligned) +## +## * Return value: vXiN the data read. +## +## The byte size of the return type must be 16, 32, 64, or 128. +## + "oword_ld_predef_surface" : { "result" : "anyvector", + "arguments" : ["int", "anyptr", "int"], + "attributes": "ReadMem", + }, + + "oword_ld_unaligned_predef_surface" : { "result" : "anyvector", + "arguments": ["int", "anyptr", "int"], + "attributes" : "ReadMem", + }, + +## ``llvm.genx.oword.st.predef.surface`` : vISA OWORD_ST instruction with predefined surface +## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +## +## * (log2 number of owords inferred from return type) +## * arg0: ptr predefined surface variable (overloaded) +## * arg1: i32 offset (in owords) +## * arg2: data to write (overloaded) +## +## The byte size of the data to write must be 16, 32, 64, or 128. +## + "oword_st_predef_surface" : { "result" : "void", + "arguments" : ["anyptr", "int", "anyvector"], + "attributes" : "None", + }, + + +## ``llvm.genx.*madw..`` : madw instruction, no saturation +## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +## * ``llvm.genx.smadw`` : result signed +## * ``llvm.genx.umadw`` : result unsigned +## +## result := arg0 * arg1 + arg2 +## +## * Return value: result, the full 64-bit of the results of multiplying two 32-bit +## integers and adding 32-bit integer(32b*32b+32b->64b). +## The low 32b of results are stored in the lower GRF and +## the high 32b of results are stored in the high GRF. +## +## Return width must be 2*GRF/sizeof(i32) +## Args width must be no more than GRF/sizeof(i32) and must be a power of two +## +## * arg0: first input, same element type as result +## * arg1: second input, same type as arg0 +## * arg2: third input, same type as arg0 +## + "umadw" : { "result" : "anyint", + "arguments" : ["anyint", 1, 1], + "attributes" : "NoMem" + }, + "smadw" : { "result" : "anyint", + "arguments" : ["anyint", 1, 1], + "attributes" : "NoMem" + }, + +### ``llvm.genx.slm.init`` : slm_init instruction +### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +### +### * arg0: slm size, i32 scalar integer type +### + "slm_init" : { "result" : "void", + "arguments" : ["int"], + "attributes" : "None" + }, } diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py old mode 100644 new mode 100755 index 49d4f682..c44ca94f --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py @@ -1,33 +1,12 @@ #!/usr/bin/env python -#===================== begin_copyright_notice ================================== - -#Copyright (c) 2020, Intel Corporation - - -#Permission is hereby granted, free of charge, to any person obtaining a -#copy of this software and associated documentation files (the -#"Software"), to deal in the Software without restriction, including -#without limitation the rights to use, copy, modify, merge, publish, -#distribute, sublicense, and/or sell copies of the Software, and to -#permit persons to whom the Software is furnished to do so, subject to -#the following conditions: - -#The above copyright notice and this permission notice shall be included -#in all copies or substantial portions of the Software. - -#THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS -#OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -#MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -#IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY -#CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -#TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE -#SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - - -#======================= end_copyright_notice ================================== - - +# ========================== begin_copyright_notice ============================ +# +# Copyright (C) 2019-2021 Intel Corporation +# +# SPDX-License-Identifier: MIT +# +# =========================== end_copyright_notice ============================= import os import sys @@ -97,6 +76,32 @@ "SideEffects": set(["NoUnwind"]), } +# order does really matter. +# It is used to define ordering between the respected platforms +platform_list = [ + "HSW", + "BDW", + "CHV", + "SKL", + "BXT", + "KBL", + "GLK", + "CNL", + "ICL", + "ICLLP", + "TGLLP", + "RKL", + "DG1", + "ADLP", + "ADLS", + "ADLN", + "XEHP", + "DG2", + "PVC", + "PVCXT_A0", + "PVCXT", +] + def getAttributeList(Attrs): """ Takes a list of attribute names, calculates the union, @@ -112,6 +117,7 @@ def getAttributeList(Attrs): #Populate the dictionary with the appropriate Intrinsics if i != 0: if (".py" in parse[i]): + sys.path.append(os.path.split(parse[i])[0]) module = importlib.import_module(os.path.split(parse[i])[1].replace(".py","")) Intrinsics.update(module.Imported_Intrinsics) @@ -301,16 +307,17 @@ def createOverloadTable(): f.write(",\n 0") isOverloadable = False genISA_Intrinsic = Intrinsics[ID_array[i]] - for j in range(3): - if isinstance(genISA_Intrinsic[j],list): - for z in range(len(genISA_Intrinsic[j])): - if isinstance(genISA_Intrinsic[j][z],int): + for key in genISA_Intrinsic: + val = genISA_Intrinsic[key] + if isinstance(val,list): + for z in range(len(val)): + if isinstance(val[z],int): continue - elif "any" in genISA_Intrinsic[j][z]: + elif "any" in val[z]: isOverloadable = True break else: - if "any" in genISA_Intrinsic[j]: + if "any" in val: isOverloadable = True break if isOverloadable: @@ -332,11 +339,12 @@ def createOverloadRetTable(): for i in range(len(ID_array)): genISA_Intrinsic = Intrinsics[ID_array[i]] isOverloadable = False - if "any" in genISA_Intrinsic[0]: + ret = genISA_Intrinsic["result"] + if "any" in ret: isOverloadable = True - elif isinstance(genISA_Intrinsic[0], list): - for j in range(len(genISA_Intrinsic[0])): - if "any" in genISA_Intrinsic[0][j]: + elif isinstance(ret, list): + for j in range(len(ret)): + if "any" in ret[j]: isOverloadable = True if isOverloadable: f.write("case GenXIntrinsic::genx_" + ID_array[i] + ":\n") @@ -356,15 +364,16 @@ def createOverloadArgsTable(): f.write("case GenXIntrinsic::genx_" + ID_array[i]+": ") argNums = [] genISA_Intrinsic = Intrinsics[ID_array[i]] - if isinstance(genISA_Intrinsic[1],list): - for z in range(len(genISA_Intrinsic[1])): - if isinstance(genISA_Intrinsic[1][z],int): + args = genISA_Intrinsic["arguments"] + if isinstance(args,list): + for z in range(len(args)): + if isinstance(args[z],int): continue - elif "any" in genISA_Intrinsic[1][z]: + elif "any" in args[z]: argNums.append(z) else: - if "any" in genISA_Intrinsic[1]: - append.append(0) + if "any" in args: + argNums.append(0) if not argNums: f.write("\n return false;\n") else: @@ -432,8 +441,8 @@ def createTypeTable(): # For the first part we will create the basic type table for i in range(len(ID_array)): genISA_Intrinsic = Intrinsics[ID_array[i]] # This is our array of types - dest = genISA_Intrinsic[0] - source_list = genISA_Intrinsic[1] + dest = genISA_Intrinsic['result'] + source_list = genISA_Intrinsic['arguments'] anyArgs_array = [] type_string = str() @@ -511,7 +520,7 @@ def createAttributeTable(): attribute_Array = [] for i in range(len(ID_array)): found = False - intrinsic_attribute = Intrinsics[ID_array[i]][2] #This is the location of that attribute + intrinsic_attribute = Intrinsics[ID_array[i]]['attributes'] #This is the location of that attribute for j in range(len(attribute_Array)): if intrinsic_attribute == attribute_Array[j]: found = True @@ -549,6 +558,78 @@ def createAttributeTable(): "#endif // GET_INTRINSIC_ATTRIBUTES\n\n") f.close() +def platformExprProcess(curr_line,platf_expr,platforms): + platf_expr = platf_expr.strip() + # simple case + platf_id = platforms.get(platf_expr) + if platf_id is not None: + curr_line[platf_id] = 1; + # "platform+" case: + elif platf_expr[-1] == "+": + platf_id = platforms.get(platf_expr[:-1]) + if platf_id is None: + raise NameError("Error in platf in " + str(Intrinsics[ID_array[i]])) + for j in range(platf_id,len(platforms)): + curr_line[j] = 1; + # "-platform" case: + elif platf_expr[0] == "-": + platf_id = platforms.get(platf_expr[1:]) + if platf_id is None: + raise NameError("Error in platf in " + str(Intrinsics[ID_array[i]])) + for j in range(platf_id): + curr_line[j] = 1; + # "~platform" case + elif platf_expr[0] == "~": + platf_id = platforms.get(platf_expr[1:]) + if platf_id is None: + raise NameError("Error in platf in " + str(Intrinsics[ID_array[i]])) + curr_line[j] = 0; + elif platf_expr == "ALL": + curr_line = [1]*len(platforms) + else: + raise NameError("Error in platf in " + str(Intrinsics[ID_array[i]])) + + return curr_line + +def override_platform_name(platform): + return platform + +def createPlatformTable(): + f = open(outputFile,"a") + # platforms dict "platform" : number + platforms = { platform_list[i] : i for i in range(len(platform_list)) } + + # by default all platfroms are supported + support_matrix = [ [1]*len(platforms) for i in range(len(ID_array))] + + # fill support matrix + for i in range(len(ID_array)): + platf_expr = Intrinsics[ID_array[i]].get('platforms') + if platf_expr is None: + continue + curr_line = [0]*len(platforms) + if not isinstance(platf_expr,list): + platf_expr = [platf_expr] + for expr in platf_expr: + curr_line = platformExprProcess(curr_line,expr,platforms) + # swope line + support_matrix[i] = curr_line + + f.write("// Add list of supported intrinsics for each platform.\n" + "#ifdef GET_INTRINSIC_PLATFORMS\n" + "static const std::map> SupportedIntrinsics {\n") + transformed_matrix = [list(x) for x in zip(*support_matrix)] + for pl,ar in zip(platforms,transformed_matrix): + dump_ar = str(ar).replace("[", "{" ,1).replace("]", "}" ,1) + name = override_platform_name(pl) + wrstring = "{MANGLE(\"" + str(name) + "\") , " + str(dump_ar) + " },\n" + f.write(wrstring) + f.write("};\n") + f.write("#endif // GET_INTRINSIC_PLATFORMS\n") + f.close() + + def emitSuffix(): f = open(outputFile,"a") f.write("#if defined(_MSC_VER) && defined(setjmp_undefined_for_msvc)\n" @@ -558,7 +639,7 @@ def emitSuffix(): "#endif\n\n") f.close() -#main functions in order +# main functions in order emitPrefix() createTargetData() generateEnums() @@ -569,4 +650,5 @@ def emitSuffix(): sortedIntrinsicsOnLenth() createTypeTable() createAttributeTable() +createPlatformTable() emitSuffix() diff --git a/GenXIntrinsics/include/llvmVCWrapper/Analysis/InstructionSimplify.h b/GenXIntrinsics/include/llvmVCWrapper/Analysis/InstructionSimplify.h new file mode 100644 index 00000000..9933fd38 --- /dev/null +++ b/GenXIntrinsics/include/llvmVCWrapper/Analysis/InstructionSimplify.h @@ -0,0 +1,49 @@ +/*========================== begin_copyright_notice ============================ + +Copyright (C) 2022 Intel Corporation + +SPDX-License-Identifier: MIT + +============================= end_copyright_notice ===========================*/ + +#ifndef VCINTR_ANALYSIS_INSTRUCTIONSIMPLIFY_H +#define VCINTR_ANALYSIS_INSTRUCTIONSIMPLIFY_H + +#include + +namespace VCINTR { + +inline llvm::Value *SimplifyInsertElementInst(llvm::Value *Vec, + llvm::Value *Elt, + llvm::Value *Idx, + const llvm::SimplifyQuery &Q) { +#if VC_INTR_LLVM_VERSION_MAJOR <= 14 + return llvm::SimplifyInsertElementInst(Vec, Elt, Idx, Q); +#else + return llvm::simplifyInsertElementInst(Vec, Elt, Idx, Q); +#endif +} + +inline llvm::Value *SimplifyExtractElementInst(llvm::Value *Vec, + llvm::Value *Idx, + const llvm::SimplifyQuery &Q) { +#if VC_INTR_LLVM_VERSION_MAJOR <= 14 + return llvm::SimplifyExtractElementInst(Vec, Idx, Q); +#else + return llvm::simplifyExtractElementInst(Vec, Idx, Q); +#endif +} + +inline llvm::Value *SimplifyCastInst(unsigned CastOpc, llvm::Value *Op, + llvm::Type *Ty, + const llvm::SimplifyQuery &Q) { +#if VC_INTR_LLVM_VERSION_MAJOR <= 14 + return llvm::SimplifyCastInst(CastOpc, Op, Ty, Q); +#else + return llvm::simplifyCastInst(CastOpc, Op, Ty, Q); +#endif +} + +} // namespace VCINTR + +#endif // VCINTR_ANALYSIS_INSTRUCTIONSIMPLIFY_H diff --git a/GenXIntrinsics/include/llvmVCWrapper/IR/Attributes.h b/GenXIntrinsics/include/llvmVCWrapper/IR/Attributes.h new file mode 100644 index 00000000..149336b0 --- /dev/null +++ b/GenXIntrinsics/include/llvmVCWrapper/IR/Attributes.h @@ -0,0 +1,101 @@ +/*========================== begin_copyright_notice ============================ + +Copyright (C) 2021 Intel Corporation + +SPDX-License-Identifier: MIT + +============================= end_copyright_notice ===========================*/ + +#ifndef VCINTR_IR_ATTRIBUTES_H +#define VCINTR_IR_ATTRIBUTES_H + +#include + +namespace VCINTR { + +namespace AttributeList { + +inline bool hasFnAttr(const llvm::AttributeList &AttrList, + llvm::Attribute::AttrKind Kind) { +#if VC_INTR_LLVM_VERSION_MAJOR >= 14 + return AttrList.hasFnAttr(Kind); +#else + return AttrList.hasFnAttribute(Kind); +#endif +} + +inline bool hasFnAttr(const llvm::AttributeList &AttrList, + llvm::StringRef Kind) { +#if VC_INTR_LLVM_VERSION_MAJOR >= 14 + return AttrList.hasFnAttr(Kind); +#else + return AttrList.hasFnAttribute(Kind); +#endif +} + +inline bool hasAttributeAtIndex(const llvm::AttributeList &AttrList, + unsigned Index, + llvm::Attribute::AttrKind Kind) { +#if VC_INTR_LLVM_VERSION_MAJOR >= 14 + return AttrList.hasAttributeAtIndex(Index, Kind); +#else + return AttrList.hasAttribute(Index, Kind); +#endif +} + +inline bool hasAttributeAtIndex(const llvm::AttributeList &AttrList, + unsigned Index, llvm::StringRef Kind) { +#if VC_INTR_LLVM_VERSION_MAJOR >= 14 + return AttrList.hasAttributeAtIndex(Index, Kind); +#else + return AttrList.hasAttribute(Index, Kind); +#endif +} + +inline llvm::Attribute getAttributeAtIndex(const llvm::AttributeList &AttrList, + unsigned Index, + llvm::Attribute::AttrKind Kind) { +#if VC_INTR_LLVM_VERSION_MAJOR >= 14 + return AttrList.getAttributeAtIndex(Index, Kind); +#else + return AttrList.getAttribute(Index, Kind); +#endif +} + +inline llvm::Attribute getAttributeAtIndex(const llvm::AttributeList &AttrList, + unsigned Index, + llvm::StringRef Kind) { +#if VC_INTR_LLVM_VERSION_MAJOR >= 14 + return AttrList.getAttributeAtIndex(Index, Kind); +#else + return AttrList.getAttribute(Index, Kind); +#endif +} + +inline llvm::AttributeList +removeAttributeAtIndex(llvm::LLVMContext &C, + const llvm::AttributeList &AttrList, unsigned Index, + llvm::Attribute::AttrKind Kind) { +#if VC_INTR_LLVM_VERSION_MAJOR >= 14 + return AttrList.removeAttributeAtIndex(C, Index, Kind); +#else + return AttrList.removeAttribute(C, Index, Kind); +#endif +} + +inline llvm::AttributeList +removeAttributeAtIndex(llvm::LLVMContext &C, + const llvm::AttributeList &AttrList, unsigned Index, + llvm::StringRef Kind) { +#if VC_INTR_LLVM_VERSION_MAJOR >= 14 + return AttrList.removeAttributeAtIndex(C, Index, Kind); +#else + return AttrList.removeAttribute(C, Index, Kind); +#endif +} + +} // namespace AttributeList + +} // namespace VCINTR + +#endif // VCINTR_IR_ATTRIBUTES_H diff --git a/GenXIntrinsics/include/llvmVCWrapper/IR/DerivedTypes.h b/GenXIntrinsics/include/llvmVCWrapper/IR/DerivedTypes.h index 56ce6c33..e0982450 100644 --- a/GenXIntrinsics/include/llvmVCWrapper/IR/DerivedTypes.h +++ b/GenXIntrinsics/include/llvmVCWrapper/IR/DerivedTypes.h @@ -1,44 +1,28 @@ -/*===================== begin_copyright_notice ================================== +/*========================== begin_copyright_notice ============================ - Copyright (c) 2020, Intel Corporation +Copyright (C) 2020-2021 Intel Corporation +SPDX-License-Identifier: MIT - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ - +============================= end_copyright_notice ===========================*/ #ifndef VCINTR_IR_DERIVEDYPES_H #define VCINTR_IR_DERIVEDYPES_H #include +#include namespace VCINTR { // TODO: move this to namespace VectorType and rename to "get" #if VC_INTR_LLVM_VERSION_MAJOR >= 9 - static inline llvm::VectorType *getVectorType(llvm::Type *ElementType, - llvm::ElementCount EC) { + inline llvm::VectorType *getVectorType(llvm::Type *ElementType, + llvm::ElementCount EC) { return llvm::VectorType::get(ElementType, EC); } #endif - static inline llvm::VectorType *getVectorType(llvm::Type *ElementType, - unsigned NumElements) { + inline llvm::VectorType *getVectorType(llvm::Type *ElementType, + unsigned NumElements) { #if VC_INTR_LLVM_VERSION_MAJOR >= 11 return llvm::VectorType::get(ElementType, NumElements, false /*Scalable*/); #else @@ -46,8 +30,8 @@ namespace VCINTR { #endif } - static inline llvm::StructType *getTypeByName(llvm::Module *M, - llvm::StringRef Name) { + inline llvm::StructType *getTypeByName(llvm::Module *M, + llvm::StringRef Name) { #if VC_INTR_LLVM_VERSION_MAJOR >= 12 return llvm::StructType::getTypeByName(M->getContext(), Name); #else @@ -57,7 +41,7 @@ namespace VCINTR { namespace VectorType { -static unsigned getNumElements(llvm::VectorType *VecType) { +inline unsigned getNumElements(llvm::VectorType *VecType) { using namespace llvm; #if VC_INTR_LLVM_VERSION_MAJOR <= 10 return VecType->getNumElements(); diff --git a/GenXIntrinsics/include/llvmVCWrapper/IR/Function.h b/GenXIntrinsics/include/llvmVCWrapper/IR/Function.h index 6ed092e7..0180a931 100644 --- a/GenXIntrinsics/include/llvmVCWrapper/IR/Function.h +++ b/GenXIntrinsics/include/llvmVCWrapper/IR/Function.h @@ -1,27 +1,10 @@ -/*===================== begin_copyright_notice ================================== +/*========================== begin_copyright_notice ============================ - Copyright (c) 2020, Intel Corporation +Copyright (C) 2020-2021 Intel Corporation +SPDX-License-Identifier: MIT - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ - +============================= end_copyright_notice ===========================*/ #ifndef VCINTR_IR_FUNCTION_H #define VCINTR_IR_FUNCTION_H @@ -32,16 +15,30 @@ namespace VCINTR { namespace Function { -inline llvm::Function *Create(llvm::FunctionType *FTy, - llvm::Function::LinkageTypes Linkage, - unsigned AddressSpace, const llvm::Twine &N = "", - llvm::Module *M = nullptr) { -#if VC_INTR_LLVM_VERSION_MAJOR <= 7 - // Let's stick to newer LLVM versions interface. - (void)AddressSpace; - return llvm::Function::Create(FTy, Linkage, N, M); +inline void addAttributeAtIndex(llvm::Function &F, unsigned Index, + llvm::Attribute Attr) { +#if VC_INTR_LLVM_VERSION_MAJOR >= 14 + F.addAttributeAtIndex(Index, Attr); +#else + F.addAttribute(Index, Attr); +#endif +} + +inline void removeAttributeAtIndex(llvm::Function &F, unsigned Index, + llvm::Attribute::AttrKind Kind) { +#if VC_INTR_LLVM_VERSION_MAJOR >= 14 + F.removeAttributeAtIndex(Index, Kind); +#else + F.removeAttribute(Index, Kind); +#endif +} + +inline void removeAttributeAtIndex(llvm::Function &F, unsigned Index, + llvm::StringRef Kind) { +#if VC_INTR_LLVM_VERSION_MAJOR >= 14 + F.removeAttributeAtIndex(Index, Kind); #else - return llvm::Function::Create(FTy, Linkage, AddressSpace, N, M); + F.removeAttribute(Index, Kind); #endif } diff --git a/GenXIntrinsics/include/llvmVCWrapper/IR/GlobalValue.h b/GenXIntrinsics/include/llvmVCWrapper/IR/GlobalValue.h deleted file mode 100644 index 98a88f3a..00000000 --- a/GenXIntrinsics/include/llvmVCWrapper/IR/GlobalValue.h +++ /dev/null @@ -1,47 +0,0 @@ -/*===================== begin_copyright_notice ================================== - - Copyright (c) 2020, Intel Corporation - - - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ - - -#ifndef VCINTR_IR_GLOBALVALUE_H -#define VCINTR_IR_GLOBALVALUE_H - -#include - -namespace VCINTR { - -namespace GlobalValue { - -inline unsigned getAddressSpace(const llvm::GlobalValue &GV) { -#if VC_INTR_LLVM_VERSION_MAJOR <= 7 - return GV.getType()->getAddressSpace(); -#else - return GV.getAddressSpace(); -#endif -} - -} // namespace GlobalValue - -} // namespace VCINTR - -#endif // VCINTR_IR_GLOBALVARIABLE_H diff --git a/GenXIntrinsics/include/llvmVCWrapper/IR/InstrTypes.h b/GenXIntrinsics/include/llvmVCWrapper/IR/InstrTypes.h deleted file mode 100644 index a7fadef3..00000000 --- a/GenXIntrinsics/include/llvmVCWrapper/IR/InstrTypes.h +++ /dev/null @@ -1,39 +0,0 @@ -/*===================== begin_copyright_notice ================================== - - Copyright (c) 2020, Intel Corporation - - - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ - - -#ifndef VCINTR_IR_INSTRTYPES_H -#define VCINTR_IR_INSTRTYPES_H - -#include - -namespace VCINTR { -#if VC_INTR_LLVM_VERSION_MAJOR <= 7 -using llvm::TerminatorInst; -#elif VC_INTR_LLVM_VERSION_MAJOR >= 8 -using TerminatorInst = llvm::Instruction; -#endif -} // namespace VCINTR - -#endif // VCINTR_IR_INSTRTYPES_H diff --git a/GenXIntrinsics/include/llvmVCWrapper/IR/Instructions.h b/GenXIntrinsics/include/llvmVCWrapper/IR/Instructions.h index 1f1e08e3..c4871e30 100644 --- a/GenXIntrinsics/include/llvmVCWrapper/IR/Instructions.h +++ b/GenXIntrinsics/include/llvmVCWrapper/IR/Instructions.h @@ -1,27 +1,10 @@ -/*===================== begin_copyright_notice ================================== +/*========================== begin_copyright_notice ============================ - Copyright (c) 2020, Intel Corporation +Copyright (C) 2020-2021 Intel Corporation +SPDX-License-Identifier: MIT - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ - +============================= end_copyright_notice ===========================*/ #ifndef VCINTR_IR_INSTRUCTIONS_H #define VCINTR_IR_INSTRUCTIONS_H @@ -36,7 +19,7 @@ auto static constexpr UndefMaskElem = -1; // LLVM <= 10 does not have ShuffleVectorInst ctor which accepts ArrayRef // This method returns mask with appropriate type for ShuffleVectorInst ctor #if VC_INTR_LLVM_VERSION_MAJOR <= 10 -static llvm::Constant *getShuffleMask(llvm::ArrayRef Mask, +inline llvm::Constant *getShuffleMask(llvm::ArrayRef Mask, llvm::LLVMContext &Context) { using namespace llvm; auto Indices = SmallVector{}; @@ -51,7 +34,7 @@ static llvm::Constant *getShuffleMask(llvm::ArrayRef Mask, return ConstantVector::get(Indices); } #else -static llvm::ArrayRef getShuffleMask(llvm::ArrayRef Mask, +inline llvm::ArrayRef getShuffleMask(llvm::ArrayRef Mask, llvm::LLVMContext &Context) { return Mask; } diff --git a/GenXIntrinsics/include/llvmVCWrapper/IR/Intrinsics.h b/GenXIntrinsics/include/llvmVCWrapper/IR/Intrinsics.h new file mode 100644 index 00000000..039eda74 --- /dev/null +++ b/GenXIntrinsics/include/llvmVCWrapper/IR/Intrinsics.h @@ -0,0 +1,29 @@ +/*========================== begin_copyright_notice ============================ + +Copyright (C) 2021-2021 Intel Corporation + +SPDX-License-Identifier: MIT + +============================= end_copyright_notice ===========================*/ + +#ifndef VCINTR_IR_INTRINSICS_H +#define VCINTR_IR_INTRINSICS_H + +#include + +namespace VCINTR { + +namespace Intrinsic { +inline std::string getName(llvm::Intrinsic::ID Id, + llvm::ArrayRef Tys) { +#if VC_INTR_LLVM_VERSION_MAJOR >= 13 + return llvm::Intrinsic::getNameNoUnnamedTypes(Id, Tys); +#else + return llvm::Intrinsic::getName(Id, Tys); +#endif +} + +} // namespace Intrinsic +} // namespace VCINTR + +#endif // VCINTR_IR_INTRINSICS_H diff --git a/GenXIntrinsics/include/llvmVCWrapper/Support/Alignment.h b/GenXIntrinsics/include/llvmVCWrapper/Support/Alignment.h index be2b8a4a..7ef5d2b4 100644 --- a/GenXIntrinsics/include/llvmVCWrapper/Support/Alignment.h +++ b/GenXIntrinsics/include/llvmVCWrapper/Support/Alignment.h @@ -1,27 +1,10 @@ -/*===================== begin_copyright_notice ================================== +/*========================== begin_copyright_notice ============================ - Copyright (c) 2020, Intel Corporation +Copyright (C) 2020-2021 Intel Corporation +SPDX-License-Identifier: MIT - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ - +============================= end_copyright_notice ===========================*/ #ifndef VCINTR_IR_ALIGNMENT_H #define VCINTR_IR_ALIGNMENT_H @@ -43,7 +26,7 @@ template llvm::MaybeAlign getAlign(TValue *Val) { return llvm::MaybeAlign(Val->getAlignment()); } #else -template llvm::Align getAlign(TValue *Val) { +template auto getAlign(TValue *Val) { return Val->getAlign(); } #endif diff --git a/GenXIntrinsics/lib/CMakeLists.txt b/GenXIntrinsics/lib/CMakeLists.txt index 76198d0d..0836db4e 100644 --- a/GenXIntrinsics/lib/CMakeLists.txt +++ b/GenXIntrinsics/lib/CMakeLists.txt @@ -1,3 +1,9 @@ -add_definitions(-DVC_INTR_LLVM_VERSION_MAJOR=${LLVM_VERSION_MAJOR}) +#=========================== begin_copyright_notice ============================ +# +# Copyright (C) 2019-2021 Intel Corporation +# +# SPDX-License-Identifier: MIT +# +#============================ end_copyright_notice ============================= add_subdirectory(GenXIntrinsics) diff --git a/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.cpp b/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.cpp new file mode 100644 index 00000000..536a2c5b --- /dev/null +++ b/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.cpp @@ -0,0 +1,64 @@ +/*========================== begin_copyright_notice ============================ + +Copyright (C) 2021 Intel Corporation + +SPDX-License-Identifier: MIT + +============================= end_copyright_notice ===========================*/ + +#include "AdaptorsCommon.h" + +#include "llvm/IR/Function.h" +#include "llvm/IR/Instructions.h" +#include "llvm/IR/Type.h" + +namespace llvm { +namespace genx { +#if VC_INTR_LLVM_VERSION_MAJOR >= 9 + +static void legalizeAttribute(Argument &Arg, Type *NewType, + Attribute::AttrKind Kind) { + + if (!Arg.hasAttribute(Kind) || + Arg.getAttribute(Kind).getValueAsType() == NewType) + return; + + Arg.removeAttr(Kind); + Arg.addAttr(Attribute::get(Arg.getParent()->getContext(), Kind, NewType)); +} + +#endif + +void legalizeParamAttributes(Function *F) { + assert(F && "Valid function ptr must be passed"); + +#if VC_INTR_LLVM_VERSION_MAJOR >= 9 + for (auto &Arg : F->args()) { + auto *PTy = dyn_cast(Arg.getType()); + if (!PTy) + continue; + +#if VC_INTR_LLVM_VERSION_MAJOR >= 13 + if (PTy->isOpaque()) + continue; +#endif // VC_INTR_LLVM_VERSION_MAJOR >= 13 + + auto *ElemType = PTy->getPointerElementType(); + + legalizeAttribute(Arg, ElemType, Attribute::ByVal); + +#if VC_INTR_LLVM_VERSION_MAJOR >= 11 + legalizeAttribute(Arg, ElemType, Attribute::Preallocated); +#if VC_INTR_LLVM_VERSION_MAJOR >= 12 + legalizeAttribute(Arg, ElemType, Attribute::ByRef); +#if VC_INTR_LLVM_VERSION_MAJOR >= 13 + legalizeAttribute(Arg, ElemType, Attribute::InAlloca); + legalizeAttribute(Arg, ElemType, Attribute::ElementType); +#endif // VC_INTR_LLVM_VERSION_MAJOR >= 13 +#endif // VC_INTR_LLVM_VERSION_MAJOR >= 12 +#endif // VC_INTR_LLVM_VERSION_MAJOR >= 11 + } +#endif // VC_INTR_LLVM_VERSION_MAJOR >= 9 +} +} // namespace genx +} // namespace llvm diff --git a/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.h b/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.h index 82d1be7a..413f4e41 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.h +++ b/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.h @@ -1,35 +1,17 @@ -/*===================== begin_copyright_notice ================================== +/*========================== begin_copyright_notice ============================ - Copyright (c) 2020, Intel Corporation +Copyright (C) 2020-2021 Intel Corporation +SPDX-License-Identifier: MIT - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: +============================= end_copyright_notice ===========================*/ - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ - - -//===----------------------------------------------------------------------===// -// // This file defines common constants for writer/reader spirv adaptors. -// -//===----------------------------------------------------------------------===// namespace llvm { + +class Function; + namespace genx { enum class ArgKind { @@ -47,8 +29,11 @@ static constexpr const char Buffer[] = "buffer_t"; static constexpr const char SVM[] = "svmptr_t"; static constexpr const char Sampler[] = "sampler_t"; static constexpr const char Image1d[] = "image1d_t"; +static constexpr const char Image1dArray[] = "image1d_array_t"; static constexpr const char Image1dBuffer[] = "image1d_buffer_t"; static constexpr const char Image2d[] = "image2d_t"; +static constexpr const char Image2dArray[] = "image2d_array_t"; +static constexpr const char Image2dMediaBlock[] = "image2d_media_block_t"; static constexpr const char Image3d[] = "image3d_t"; } // namespace ArgDesc @@ -59,8 +44,11 @@ enum class SPIRVType { // Surfaces + corresponding desc. Buffer, Image1d, + Image1dArray, Image1dBuffer, Image2d, + Image2dArray, + Image2dMediaBlock, Image3d, // Sampler + sampler_t. Sampler, @@ -95,13 +83,25 @@ static constexpr const char TypePrefix[] = "opencl."; // Currently used image types. static constexpr const char Image[] = "image"; static constexpr const char Dim1d[] = "1d"; +static constexpr const char Dim1dArray[] = "1d_array"; static constexpr const char Dim1dBuffer[] = "1d_buffer"; static constexpr const char Dim2d[] = "2d"; +static constexpr const char Dim2dArray[] = "2d_array"; static constexpr const char Dim3d[] = "3d"; // Sampler type. static constexpr const char Sampler[] = "sampler"; } // namespace OCLTypes +// SPIRV friendly IR types. May be generated by SPIRV-LLVM-Translator. +namespace SPIRVIRTypes { + +static constexpr const char TypePrefix[] = "spirv."; + +enum Dim { Dim1D = 0, Dim2D = 1, Dim3D = 2, DimBuffer = 5 }; +static constexpr const char Image[] = "Image."; +static constexpr const char Sampler[] = "Sampler"; +} // namespace SPIRVIRTypes + // These are not really standardized names. // Just something for POC implementation. namespace IntelTypes { @@ -110,6 +110,8 @@ static constexpr const char TypePrefix[] = "intel."; // Stateful buffer type. static constexpr const char Buffer[] = "buffer"; +// Media block image. +static constexpr const char MediaBlockImage[] = "image2d_media_block"; } // namespace IntelTypes namespace CommonTypes { @@ -142,8 +144,11 @@ inline unsigned getOpaqueTypeAddressSpace(SPIRVType Ty) { return SPIRVParams::SPIRVConstantAS; case SPIRVType::Buffer: case SPIRVType::Image1d: + case SPIRVType::Image1dArray: case SPIRVType::Image1dBuffer: case SPIRVType::Image2d: + case SPIRVType::Image2dArray: + case SPIRVType::Image2dMediaBlock: case SPIRVType::Image3d: return SPIRVParams::SPIRVGlobalAS; default: @@ -152,5 +157,17 @@ inline unsigned getOpaqueTypeAddressSpace(SPIRVType Ty) { } } +// Overrides specific attributes of function parameters. +// +// Function arguments of PointerType can have specific +// attributes like ByVal, ByRef, Preallocated, InAlloca +// that contain Pointee Type of that pointer as parameter. +// SPIRV Adaptor passes may change Pointee type, so we must +// explicitly change this type in corresponding attributes +// in order to construct valid llvm-IR. +// +// (see more here: https://llvm.org/docs/LangRef.html#parameter-attributes) +void legalizeParamAttributes(Function* F); + } // namespace genx } // namespace llvm diff --git a/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt b/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt index 33de403b..9b48788f 100755 --- a/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt +++ b/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt @@ -1,3 +1,11 @@ +#=========================== begin_copyright_notice ============================ +# +# Copyright (C) 2019-2021 Intel Corporation +# +# SPDX-License-Identifier: MIT +# +#============================ end_copyright_notice ============================= + set(LLVM_COMPONENTS CodeGen Support @@ -5,44 +13,61 @@ set(LLVM_COMPONENTS Analysis ) +set(SRC_LIST + GenXIntrinsics.cpp + GenXRestoreIntrAttr.cpp + GenXSimdCFLowering.cpp + GenXSingleElementVectorUtil.cpp + GenXSPIRVReaderAdaptor.cpp + GenXSPIRVWriterAdaptor.cpp + GenXVersion.cpp + AdaptorsCommon.cpp + GenXMetadata.cpp +) + if(BUILD_EXTERNAL) - add_library(LLVMGenXIntrinsics - GenXIntrinsics.cpp - GenXRestoreIntrAttr.cpp - GenXSimdCFLowering.cpp - GenXSingleElementVectorUtil.cpp - GenXSPIRVReaderAdaptor.cpp - GenXSPIRVWriterAdaptor.cpp - ) + add_library(LLVMGenXIntrinsics ${SRC_LIST}) llvm_update_compile_flags(LLVMGenXIntrinsics) add_dependencies(LLVMGenXIntrinsics GenXIntrinsicsGen) vc_get_llvm_targets(LLVM_LIBS ${LLVM_COMPONENTS}) target_link_libraries(LLVMGenXIntrinsics ${LLVM_LIBS}) - - target_include_directories(LLVMGenXIntrinsics PUBLIC - $ - $ - $ - ) else() # when we are building in LLVM infra, we need to conform set(LLVM_LINK_COMPONENTS ${LLVM_COMPONENTS} ) - add_llvm_library(LLVMGenXIntrinsics - GenXIntrinsics.cpp - GenXRestoreIntrAttr.cpp - GenXSimdCFLowering.cpp - GenXSingleElementVectorUtil.cpp - GenXSPIRVReaderAdaptor.cpp - GenXSPIRVWriterAdaptor.cpp - ADDITIONAL_HEADER_DIRS - ${GENX_INTRINSICS_MAIN_INCLUDE_DIR}/llvm/GenXIntrinsics + if(LLVM_LINK_LLVM_DYLIB) + add_llvm_library(LLVMGenXIntrinsics STATIC DISABLE_LLVM_LINK_LLVM_DYLIB + ${SRC_LIST} + + ADDITIONAL_HEADER_DIRS + ${GENX_INTRINSICS_MAIN_INCLUDE_DIR}/llvm/GenXIntrinsics + DEPENDS + GenXIntrinsicsGen + intrinsics_gen + LLVMCodeGen + LLVMSupport + LLVMCore + LLVMAnalysis + LLVMSPIRVLib + ) + else() + add_llvm_library(LLVMGenXIntrinsics + ${SRC_LIST} + + ADDITIONAL_HEADER_DIRS + ${GENX_INTRINSICS_MAIN_INCLUDE_DIR}/llvm/GenXIntrinsics + DEPENDS + GenXIntrinsicsGen + intrinsics_gen + ) + endif() +endif() - DEPENDS - GenXIntrinsicsGen - intrinsics_gen +target_include_directories(LLVMGenXIntrinsics PUBLIC + $ + $ + $ ) -endif() diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp index 1e7107e3..118a27e8 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp @@ -1,42 +1,22 @@ -/*===================== begin_copyright_notice ================================== - - Copyright (c) 2020, Intel Corporation - - - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ - - -/** Originated from llvm source lib/IR/Function.cpp **/ - -//===- Function.cpp - Implement the Global object classes -----------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// +/*========================== begin_copyright_notice ============================ + +Copyright (C) 2019-2021 Intel Corporation + +SPDX-License-Identifier: MIT + +============================= end_copyright_notice ===========================*/ + +/*========================== begin_copyright_notice ============================ + +This file is distributed under the University of Illinois Open Source License. +See LICENSE.TXT for details. + +============================= end_copyright_notice ===========================*/ + +// Originated from llvm source lib/IR/Function.cpp +// Function.cpp - Implement the Global object classes + // Implementation of methods declared in llvm/GenXIntrinsics/GenXIntrinsics.h -// -//===----------------------------------------------------------------------===// #include "llvm/GenXIntrinsics/GenXIntrinsics.h" @@ -52,8 +32,10 @@ #include #include "llvmVCWrapper/IR/DerivedTypes.h" +#include "llvmVCWrapper/IR/Intrinsics.h" #include +#include using namespace llvm; @@ -430,7 +412,7 @@ static std::string getMangledTypeStr(Type* Ty) { std::string Result; if (PointerType* PTyp = dyn_cast(Ty)) { Result += "p" + llvm::utostr(PTyp->getAddressSpace()) + - getMangledTypeStr(PTyp->getElementType()); + getMangledTypeStr(PTyp->getPointerElementType()); } else if (ArrayType* ATyp = dyn_cast(Ty)) { Result += "a" + llvm::utostr(ATyp->getNumElements()) + getMangledTypeStr(ATyp->getElementType()); @@ -481,6 +463,23 @@ bool isOverloaded(GenXIntrinsic::ID id) { static StringRef GenXIntrinsicMDName{ "genx_intrinsic_id" }; +bool GenXIntrinsic::isSupportedPlatform(const std::string &CPU, unsigned id) { +#define GET_INTRINSIC_PLATFORMS +#include "llvm/GenXIntrinsics/GenXIntrinsicDescription.gen" +#undef GET_INTRINSIC_PLATFORMS + assert(SupportedIntrinsics.find(CPU) != SupportedIntrinsics.end() && + "Unknown Platform"); + assert(GenXIntrinsic::isGenXIntrinsic(id) && + "this function should be used only for GenXIntrinsics"); + auto PlatformInfoIt = SupportedIntrinsics.find(CPU); + if (PlatformInfoIt == SupportedIntrinsics.end()) + return false; + const auto &IntrinsicInfo = PlatformInfoIt->second; + size_t IntrinsicIdx = id - GenXIntrinsic::ID::not_genx_intrinsic - 1; + if (IntrinsicIdx < IntrinsicInfo.size()) + return IntrinsicInfo[IntrinsicIdx]; + return false; +} /// Table of per-target intrinsic name tables. #define GET_INTRINSIC_TARGET_DATA @@ -683,6 +682,46 @@ std::string GenXIntrinsic::getAnyName(unsigned id, ArrayRef Tys) { } else if (isGenXIntrinsic(id)) return getGenXName((GenXIntrinsic::ID)id, Tys); else - return Intrinsic::getName((Intrinsic::ID)id, Tys); + return VCINTR::Intrinsic::getName((Intrinsic::ID)id, Tys); +} + +GenXIntrinsic::LSCVectorSize GenXIntrinsic::getLSCVectorSize( + const Instruction *I) { + assert(isLSC(I)); + const int VectorSizeIdx = LSCArgIdx::getLSCVectorSize(getLSCCategory(I)); + if (VectorSizeIdx == LSCArgIdx::Invalid) + return LSCVectorSize::N0; + return static_cast( + cast(I->getOperand(VectorSizeIdx))->getZExtValue()); +} + +GenXIntrinsic::LSCDataSize GenXIntrinsic::getLSCDataSize( + const Instruction *I) { + assert(isLSC(I)); + const int DataSizeIdx = LSCArgIdx::getLSCDataSize(getLSCCategory(I)); + if (DataSizeIdx == LSCArgIdx::Invalid) + return LSCDataSize::Invalid; + return static_cast( + cast(I->getOperand(DataSizeIdx))->getZExtValue()); +} + +GenXIntrinsic::LSCDataOrder GenXIntrinsic::getLSCDataOrder( + const Instruction *I) { + assert(isLSC(I)); + const int DataOrderIdx = LSCArgIdx::getLSCDataOrder(getLSCCategory(I)); + if (DataOrderIdx == LSCArgIdx::Invalid) + return LSCDataOrder::Invalid; + return static_cast( + cast(I->getOperand(DataOrderIdx))->getZExtValue()); +} + +unsigned GenXIntrinsic::getLSCWidth(const Instruction *I) { + assert(isLSC(I)); + const int WidthIdx = LSCArgIdx::getLSCWidth(getLSCCategory(I)); + if (WidthIdx == LSCArgIdx::Invalid) + return 1; + if (auto VT = dyn_cast(I->getOperand(WidthIdx)->getType())) + return VCINTR::VectorType::getNumElements(VT); + return 1; } diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXMetadata.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXMetadata.cpp new file mode 100644 index 00000000..30b9d8c4 --- /dev/null +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXMetadata.cpp @@ -0,0 +1,32 @@ +/*========================== begin_copyright_notice ============================ + +Copyright (C) 2021 Intel Corporation + +SPDX-License-Identifier: MIT + +============================= end_copyright_notice ===========================*/ + +#include "llvm/GenXIntrinsics/GenXMetadata.h" + +#include +#include +#include + +using namespace llvm; + +MDNode *llvm::genx::GetOldStyleKernelMD(Function const &F) { + auto *KernelMD = static_cast(nullptr); + auto *KernelMDs = F.getParent()->getNamedMetadata(FunctionMD::GenXKernels); + if (!KernelMDs) + return KernelMD; + + for (unsigned I = 0, E = KernelMDs->getNumOperands(); I < E; ++I) { + auto *Kernel = mdconst::dyn_extract( + KernelMDs->getOperand(I)->getOperand(KernelMDOp::FunctionRef)); + if (Kernel == &F) { + KernelMD = KernelMDs->getOperand(I); + break; + } + } + return KernelMD; +} diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXRestoreIntrAttr.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXRestoreIntrAttr.cpp index c8fb6ce3..dcd2d455 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXRestoreIntrAttr.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXRestoreIntrAttr.cpp @@ -1,35 +1,18 @@ -/*===================== begin_copyright_notice ================================== +/*========================== begin_copyright_notice ============================ - Copyright (c) 2020, Intel Corporation +Copyright (C) 2020-2021 Intel Corporation +SPDX-License-Identifier: MIT - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: +============================= end_copyright_notice ===========================*/ - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. +/*========================== begin_copyright_notice ============================ - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ +This file is distributed under the University of Illinois Open Source License. +See LICENSE.TXT for details. +============================= end_copyright_notice ===========================*/ -//===-- GenXRestoreIntrAttr.cpp - GenX Restore Intrinsics' attributes pass --===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// //===----------------------------------------------------------------------===// // /// GenXRestoreIntrAttr @@ -44,13 +27,13 @@ /// //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "GENX_RESTOREINTRATTR" - #include "llvm/GenXIntrinsics/GenXIntrOpts.h" #include "llvm/GenXIntrinsics/GenXIntrinsics.h" #include "llvm/Support/Debug.h" #include "llvm/Pass.h" +#define DEBUG_TYPE "GENX_RESTOREINTRATTR" + using namespace llvm; namespace { diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp index ab170a89..00e59e62 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp @@ -1,31 +1,12 @@ -/*===================== begin_copyright_notice ================================== +/*========================== begin_copyright_notice ============================ - Copyright (c) 2020, Intel Corporation +Copyright (C) 2020-2021 Intel Corporation +SPDX-License-Identifier: MIT - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: +============================= end_copyright_notice ===========================*/ - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ - -/// -/// GenXSPIRVReaderAdaptor -/// --------------------------- -/// This pass converts metadata from SPIRV format to whichever used in backend +// This pass converts metadata from SPIRV format to whichever used in backend. #include "AdaptorsCommon.h" #include "GenXSingleElementVectorUtil.h" @@ -41,8 +22,8 @@ #include "llvm/IR/Module.h" #include "llvm/Pass.h" +#include "llvmVCWrapper/IR/Attributes.h" #include "llvmVCWrapper/IR/Function.h" -#include "llvmVCWrapper/IR/GlobalValue.h" using namespace llvm; using namespace genx; @@ -61,6 +42,18 @@ class GenXSPIRVReaderAdaptor final : public ModulePass { private: bool runOnFunction(Function &F); + + bool processVCFunctionAttributes(Function &F); + bool processVCKernelAttributes(Function &F); + + void dropAttributeAtIndex(Function &F, unsigned Index, StringRef Kind) { + auto NewAttributes = VCINTR::AttributeList::removeAttributeAtIndex( + F.getContext(), F.getAttributes(), Index, Kind); + F.setAttributes(NewAttributes); + } + void dropFnAttribute(Function &F, StringRef Kind) { + dropAttributeAtIndex(F, AttributeList::FunctionIndex, Kind); + } }; } // namespace @@ -85,9 +78,15 @@ static std::pair parseImageDim(StringRef TyName) { if (TyName.consume_front(OCLTypes::Dim1dBuffer)) return {SPIRVType::Image1dBuffer, TyName}; + if (TyName.consume_front(OCLTypes::Dim1dArray)) + return {SPIRVType::Image1dArray, TyName}; + if (TyName.consume_front(OCLTypes::Dim1d)) return {SPIRVType::Image1d, TyName}; + if (TyName.consume_front(OCLTypes::Dim2dArray)) + return {SPIRVType::Image2dArray, TyName}; + if (TyName.consume_front(OCLTypes::Dim2d)) return {SPIRVType::Image2d, TyName}; @@ -123,19 +122,112 @@ static SPIRVArgDesc parseImageType(StringRef TyName) { return {ImageType, AccType}; } -static Optional parseBufferType(StringRef TyName) { - if (!TyName.consume_front(IntelTypes::TypePrefix)) - return None; +static std::pair parseIntelMainType(StringRef TyName) { + if (TyName.consume_front(IntelTypes::Buffer)) + return {SPIRVType::Buffer, TyName}; + + if (TyName.consume_front(IntelTypes::MediaBlockImage)) + return {SPIRVType::Image2dMediaBlock, TyName}; + + llvm_unreachable("Unexpected intel extension type"); +} + +template T consumeIntegerLiteral(StringRef TyName) { + int Literal; + + auto ProperlyConsumed = !TyName.consumeInteger(0, Literal); + assert(ProperlyConsumed && "Expected string to rpresent integer literal"); + (void)ProperlyConsumed; + + return static_cast(Literal); +} + +static SPIRVType evaluateImageTypeFromSPVIR(SPIRVIRTypes::Dim Dim, + bool Arrayed) { + SPIRVType ResultType; + if (!Arrayed) { + switch (Dim) { + case SPIRVIRTypes::Dim1D: + ResultType = SPIRVType::Image1d; + break; + case SPIRVIRTypes::Dim2D: + ResultType = SPIRVType::Image2d; + break; + case SPIRVIRTypes::Dim3D: + ResultType = SPIRVType::Image3d; + break; + case SPIRVIRTypes::DimBuffer: + ResultType = SPIRVType::Image1dBuffer; + break; + default: + llvm_unreachable("Bad Image Type"); + } + } else { + switch (Dim) { + case SPIRVIRTypes::Dim1D: + ResultType = SPIRVType::Image1dArray; + break; + case SPIRVIRTypes::Dim2D: + ResultType = SPIRVType::Image2dArray; + break; + default: + llvm_unreachable("Bad Image Type"); + } + } + + return ResultType; +} + +static StringRef skipUnderscores(StringRef StrRef, int Count) { + for (int i = 0; i < Count; ++i) { + StrRef = StrRef.drop_while([](char C) { return C != '_'; }); + StrRef = StrRef.drop_front(1); + } + + return StrRef; +} + +static SPIRVArgDesc parseSPIRVIRImageType(StringRef TyName) { + const bool Consumed = TyName.consume_front(SPIRVIRTypes::Image); + assert(Consumed && "Unexpected SPIRV friendly IR type"); + (void)Consumed; + + // SPIRV friendly Ir image type looks like this: + // spirv.Image._{Sampled T}_{Dim}_{Depth}_{Arrayed}_{MS}_{Fmt}_{Acc} + + // skip Samled Type. + TyName = skipUnderscores(TyName, 2); + + auto Dim = consumeIntegerLiteral(TyName); + + // Skip Depth. + TyName = skipUnderscores(TyName, 2); - if (!TyName.consume_front(IntelTypes::Buffer)) + auto Arrayed = consumeIntegerLiteral(TyName); + + // Skip Multisampling and Format. + TyName = skipUnderscores(TyName, 4); + + AccessType AccessTy = AccessType::ReadOnly; + + if (!TyName.empty()) + AccessTy = consumeIntegerLiteral(TyName); + + auto ResultType = evaluateImageTypeFromSPVIR(Dim, Arrayed); + + return {ResultType, AccessTy}; +} + +static Optional parseIntelType(StringRef TyName) { + if (!TyName.consume_front(IntelTypes::TypePrefix)) return None; - // Now assume that buffer type is correct. + SPIRVType MainType; + std::tie(MainType, TyName) = parseIntelMainType(TyName); AccessType AccType; - StringRef Suffix; - std::tie(AccType, Suffix) = parseAccessQualifier(TyName); - assert(Suffix == CommonTypes::TypeSuffix && "Bad buffer type"); - return SPIRVArgDesc{SPIRVType::Buffer, AccType}; + std::tie(AccType, TyName) = parseAccessQualifier(TyName); + assert(TyName == CommonTypes::TypeSuffix && "Bad intel type"); + return SPIRVArgDesc{MainType, AccType}; } static Optional parseOCLType(StringRef TyName) { @@ -152,18 +244,35 @@ static Optional parseOCLType(StringRef TyName) { return parseImageType(TyName); } +static Optional parseSPIRVIRType(StringRef TyName) { + if (!TyName.consume_front(SPIRVIRTypes::TypePrefix)) + return None; + + if (TyName.consume_front(SPIRVIRTypes::Sampler)) + return {SPIRVType::Sampler}; + + return parseSPIRVIRImageType(TyName); +} // Parse opaque type name. -// Ty -> "opencl." OCLTy | "intel.buffer" Acc "_t" +// Ty -> "opencl." OCLTy | "spirv." SPVIRTy | "intel" IntelTy // OCLTy -> "sampler_t" | ImageTy +// IntelTy -> MainIntelTy Acc "_t" +// MainIntelTy -> "buffer" | "image2d_media_block" // ImageTy -> "image" Dim Acc "_t" // Dim -> "1d" | "1d_buffer" | "2d" | "3d" // Acc -> "_ro" | "_wo" | "_rw" -// Assume that "opencl." and "intel.buffer" types are well-formed. +// SPVIRTy -> "Sampler" | SPVImageTy +// SPVImageTy -> "Image." _..._{Dim}_..._{Arrayed}_..._{Acc} +// Dim, Arrayed, Acc - literal operands matching OpTypeImage operands in SPIRV +// Assume that "opencl." "spirv." and "intel.buffer" types are well-formed. static Optional parseOpaqueType(StringRef TyName) { - if (auto MaybeBuffer = parseBufferType(TyName)) - return MaybeBuffer.getValue(); + if (auto MaybeIntelTy = parseIntelType(TyName)) + return MaybeIntelTy.getValue(); - return parseOCLType(TyName); + if (auto MaybeOCL = parseOCLType(TyName)) + return MaybeOCL.getValue(); + + return parseSPIRVIRType(TyName); } static SPIRVArgDesc analyzeKernelArg(const Argument &Arg) { @@ -185,7 +294,7 @@ static SPIRVArgDesc analyzeKernelArg(const Argument &Arg) { AddressSpace != SPIRVParams::SPIRVConstantAS) return {SPIRVType::Other}; - Type *PointeeTy = PointerTy->getElementType(); + Type *PointeeTy = PointerTy->getPointerElementType(); // Not a pointer to struct, cannot be sampler or image. if (!isa(PointeeTy)) return {SPIRVType::Pointer}; @@ -239,8 +348,11 @@ static ArgKind mapSPIRVTypeToArgKind(SPIRVType Ty) { switch (Ty) { case SPIRVType::Buffer: case SPIRVType::Image1d: + case SPIRVType::Image1dArray: case SPIRVType::Image1dBuffer: case SPIRVType::Image2d: + case SPIRVType::Image2dArray: + case SPIRVType::Image2dMediaBlock: case SPIRVType::Image3d: return ArgKind::Surface; case SPIRVType::Sampler: @@ -263,12 +375,21 @@ static std::string mapSPIRVDescToArgDesc(SPIRVArgDesc SPIRVDesc) { case SPIRVType::Image1d: Desc += ArgDesc::Image1d; break; + case SPIRVType::Image1dArray: + Desc += ArgDesc::Image1dArray; + break; case SPIRVType::Image1dBuffer: Desc += ArgDesc::Image1dBuffer; break; case SPIRVType::Image2d: Desc += ArgDesc::Image2d; break; + case SPIRVType::Image2dArray: + Desc += ArgDesc::Image2dArray; + break; + case SPIRVType::Image2dMediaBlock: + Desc += ArgDesc::Image2dMediaBlock; + break; case SPIRVType::Image3d: Desc += ArgDesc::Image3d; break; @@ -312,14 +433,14 @@ transformKernelSignature(Function &F, const std::vector &Descs) { [](Argument &Arg) { return getOriginalValue(Arg)->getType(); }); auto *NewFTy = FunctionType::get(F.getReturnType(), NewTypes, false); - auto *NewF = VCINTR::Function::Create( - NewFTy, F.getLinkage(), VCINTR::GlobalValue::getAddressSpace(F)); + auto *NewF = Function::Create(NewFTy, F.getLinkage(), F.getAddressSpace()); // Copy function info. LLVMContext &Ctx = F.getContext(); NewF->copyAttributesFrom(&F); NewF->takeName(&F); NewF->copyMetadata(&F, 0); + NewF->setComdat(F.getComdat()); // Set appropriate argument attributes related to kind and desc. std::string ArgDesc; @@ -339,6 +460,8 @@ transformKernelSignature(Function &F, const std::vector &Descs) { NewF->addParamAttr(i, Attr); } + legalizeParamAttributes(NewF); + return NewF; } @@ -395,7 +518,8 @@ static void rewriteKernelsTypes(Module &M) { // Skip things that are not VC kernels. if (F->getCallingConv() != CallingConv::SPIR_KERNEL) continue; - if (!F->getAttributes().hasFnAttribute(VCFunctionMD::VCFunction)) + if (!VCINTR::AttributeList::hasFnAttr(F->getAttributes(), + VCFunctionMD::VCFunction)) continue; rewriteKernelArguments(*F); } @@ -427,58 +551,75 @@ bool GenXSPIRVReaderAdaptor::runOnModule(Module &M) { return true; } -bool GenXSPIRVReaderAdaptor::runOnFunction(Function &F) { +bool GenXSPIRVReaderAdaptor::processVCFunctionAttributes(Function &F) { auto Attrs = F.getAttributes(); - if (!Attrs.hasFnAttribute(VCFunctionMD::VCFunction)) - return true; + if (!VCINTR::AttributeList::hasFnAttr(Attrs, VCFunctionMD::VCFunction)) + return false; - if (Attrs.hasFnAttribute(VCFunctionMD::VCStackCall)) { + dropFnAttribute(F, VCFunctionMD::VCFunction); + + if (VCINTR::AttributeList::hasFnAttr(Attrs, VCFunctionMD::VCStackCall)) { F.addFnAttr(FunctionMD::CMStackCall); - F.addFnAttr(Attribute::NoInline); + dropFnAttribute(F, VCFunctionMD::VCStackCall); } - if (Attrs.hasFnAttribute(VCFunctionMD::VCCallable)){ + if (VCINTR::AttributeList::hasFnAttr(Attrs, VCFunctionMD::VCCallable)) { F.addFnAttr(FunctionMD::CMCallable); + dropFnAttribute(F, VCFunctionMD::VCCallable); + } + + if (VCINTR::AttributeList::hasFnAttr(Attrs, VCFunctionMD::VCFCEntry)) { + F.addFnAttr(FunctionMD::CMEntry); + dropFnAttribute(F, VCFunctionMD::VCFCEntry); } - if (Attrs.hasFnAttribute(VCFunctionMD::VCSIMTCall)) { + if (VCINTR::AttributeList::hasFnAttr(Attrs, VCFunctionMD::VCSIMTCall)) { auto SIMTMode = StringRef(); - SIMTMode = Attrs - .getAttribute(AttributeList::FunctionIndex, - VCFunctionMD::VCSIMTCall) - .getValueAsString(); + SIMTMode = + VCINTR::AttributeList::getAttributeAtIndex( + Attrs, AttributeList::FunctionIndex, VCFunctionMD::VCSIMTCall) + .getValueAsString(); F.addFnAttr(FunctionMD::CMGenxSIMT, SIMTMode); + dropFnAttribute(F, VCFunctionMD::VCSIMTCall); } auto &&Context = F.getContext(); - if (Attrs.hasFnAttribute(VCFunctionMD::VCFloatControl)) { + if (VCINTR::AttributeList::hasFnAttr(Attrs, VCFunctionMD::VCFloatControl)) { auto FloatControl = unsigned(0); - Attrs - .getAttribute(AttributeList::FunctionIndex, - VCFunctionMD::VCFloatControl) + VCINTR::AttributeList::getAttributeAtIndex( + Attrs, AttributeList::FunctionIndex, VCFunctionMD::VCFloatControl) .getValueAsString() .getAsInteger(0, FloatControl); auto Attr = Attribute::get(Context, FunctionMD::CMFloatControl, std::to_string(FloatControl)); - F.addAttribute(AttributeList::FunctionIndex, Attr); + VCINTR::Function::addAttributeAtIndex(F, AttributeList::FunctionIndex, + Attr); + dropFnAttribute(F, VCFunctionMD::VCFloatControl); } if (auto *ReqdSubgroupSize = F.getMetadata(SPIRVParams::SPIRVSIMDSubgroupSize)) { auto SIMDSize = - mdconst::dyn_extract(ReqdSubgroupSize->getOperand(0)) + mdconst::extract(ReqdSubgroupSize->getOperand(0)) ->getZExtValue(); Attribute Attr = Attribute::get(Context, FunctionMD::OCLRuntime, std::to_string(SIMDSize)); - F.addAttribute(AttributeList::FunctionIndex, Attr); + VCINTR::Function::addAttributeAtIndex(F, AttributeList::FunctionIndex, + Attr); } + return true; +} +bool GenXSPIRVReaderAdaptor::processVCKernelAttributes(Function &F) { if (!(F.getCallingConv() == CallingConv::SPIR_KERNEL)) - return true; + return false; + F.addFnAttr(FunctionMD::CMGenXMain); F.setDLLStorageClass(llvm::GlobalVariable::DLLExportStorageClass); + auto Attrs = F.getAttributes(); + auto *FunctionRef = ValueAsMetadata::get(&F); auto KernelName = F.getName(); auto ArgKinds = llvm::SmallVector(); @@ -486,34 +627,41 @@ bool GenXSPIRVReaderAdaptor::runOnFunction(Function &F) { auto ArgOffset = unsigned(0); auto ArgIOKinds = llvm::SmallVector(); auto ArgDescs = llvm::SmallVector(); + auto NBarrierCnt = unsigned(0); + auto &&Context = F.getContext(); llvm::Type *I32Ty = llvm::Type::getInt32Ty(Context); - if (Attrs.hasFnAttribute(VCFunctionMD::VCSLMSize)) { - Attrs.getAttribute(AttributeList::FunctionIndex, VCFunctionMD::VCSLMSize) - .getValueAsString() - .getAsInteger(0, SLMSize); - } - for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { auto ArgNo = I->getArgNo(); auto ArgKind = unsigned(0); auto ArgIOKind = unsigned(0); auto ArgDesc = std::string(); - if (Attrs.hasAttribute(ArgNo + 1, VCFunctionMD::VCArgumentKind)) { - Attrs.getAttribute(ArgNo + 1, VCFunctionMD::VCArgumentKind) + auto AttrIndex = ArgNo + 1; + + if (VCINTR::AttributeList::hasAttributeAtIndex( + Attrs, AttrIndex, VCFunctionMD::VCArgumentKind)) { + VCINTR::AttributeList::getAttributeAtIndex(Attrs, AttrIndex, + VCFunctionMD::VCArgumentKind) .getValueAsString() .getAsInteger(0, ArgKind); + dropAttributeAtIndex(F, AttrIndex, VCFunctionMD::VCArgumentKind); } - if (Attrs.hasAttribute(ArgNo + 1, VCFunctionMD::VCArgumentIOKind)) { - Attrs.getAttribute(ArgNo + 1, VCFunctionMD::VCArgumentIOKind) + if (VCINTR::AttributeList::hasAttributeAtIndex( + Attrs, AttrIndex, VCFunctionMD::VCArgumentIOKind)) { + VCINTR::AttributeList::getAttributeAtIndex(Attrs, AttrIndex, + VCFunctionMD::VCArgumentIOKind) .getValueAsString() .getAsInteger(0, ArgIOKind); + dropAttributeAtIndex(F, AttrIndex, VCFunctionMD::VCArgumentIOKind); } - if (Attrs.hasAttribute(ArgNo + 1, VCFunctionMD::VCArgumentDesc)) { - ArgDesc = Attrs.getAttribute(ArgNo + 1, VCFunctionMD::VCArgumentDesc) + if (VCINTR::AttributeList::hasAttributeAtIndex( + Attrs, AttrIndex, VCFunctionMD::VCArgumentDesc)) { + ArgDesc = VCINTR::AttributeList::getAttributeAtIndex( + Attrs, AttrIndex, VCFunctionMD::VCArgumentDesc) .getValueAsString() .str(); + dropAttributeAtIndex(F, AttrIndex, VCFunctionMD::VCArgumentDesc); } ArgKinds.push_back( llvm::ValueAsMetadata::get(llvm::ConstantInt::get(I32Ty, ArgKind))); @@ -522,6 +670,23 @@ bool GenXSPIRVReaderAdaptor::runOnFunction(Function &F) { ArgDescs.push_back(llvm::MDString::get(Context, ArgDesc)); } + if (VCINTR::AttributeList::hasFnAttr(Attrs, VCFunctionMD::VCSLMSize)) { + VCINTR::AttributeList::getAttributeAtIndex( + Attrs, AttributeList::FunctionIndex, VCFunctionMD::VCSLMSize) + .getValueAsString() + .getAsInteger(0, SLMSize); + dropFnAttribute(F, VCFunctionMD::VCSLMSize); + } + + if (VCINTR::AttributeList::hasFnAttr(Attrs, + VCFunctionMD::VCNamedBarrierCount)) { + VCINTR::AttributeList::getAttributeAtIndex( + Attrs, AttributeList::FunctionIndex, VCFunctionMD::VCNamedBarrierCount) + .getValueAsString() + .getAsInteger(0, NBarrierCnt); + dropFnAttribute(F, VCFunctionMD::VCNamedBarrierCount); + } + auto KernelMD = std::vector(); KernelMD.push_back(FunctionRef); KernelMD.push_back(llvm::MDString::get(Context, KernelName)); @@ -531,11 +696,20 @@ bool GenXSPIRVReaderAdaptor::runOnFunction(Function &F) { ConstantAsMetadata::get(ConstantInt::get(I32Ty, ArgOffset))); KernelMD.push_back(llvm::MDNode::get(Context, ArgIOKinds)); KernelMD.push_back(llvm::MDNode::get(Context, ArgDescs)); - KernelMD.push_back(ConstantAsMetadata::get(ConstantInt::get(I32Ty, 0))); - + KernelMD.push_back( + ConstantAsMetadata::get(ConstantInt::get(I32Ty, NBarrierCnt))); NamedMDNode *KernelMDs = F.getParent()->getOrInsertNamedMetadata(FunctionMD::GenXKernels); llvm::MDNode *Node = MDNode::get(F.getContext(), KernelMD); KernelMDs->addOperand(Node); + + return true; +} + +bool GenXSPIRVReaderAdaptor::runOnFunction(Function &F) { + if (!processVCFunctionAttributes(F)) + return true; + + processVCKernelAttributes(F); return true; } diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp index a6504283..e0e895a9 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp @@ -1,31 +1,12 @@ -/*===================== begin_copyright_notice ================================== +/*========================== begin_copyright_notice ============================ - Copyright (c) 2020, Intel Corporation +Copyright (C) 2020-2021 Intel Corporation +SPDX-License-Identifier: MIT - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: +============================= end_copyright_notice ===========================*/ - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ - -/// -/// GenXSPIRVWriterAdaptor -/// --------------------------- -/// This pass converts metadata to SPIRV format from whichever used in frontend +// This pass converts metadata to SPIRV format from whichever used in frontend. #include "AdaptorsCommon.h" #include "GenXSingleElementVectorUtil.h" @@ -43,9 +24,9 @@ #include "llvm/Pass.h" #include "llvm/Support/Process.h" +#include "llvmVCWrapper/IR/Attributes.h" #include "llvmVCWrapper/IR/DerivedTypes.h" #include "llvmVCWrapper/IR/Function.h" -#include "llvmVCWrapper/IR/GlobalValue.h" using namespace llvm; using namespace genx; @@ -131,12 +112,18 @@ static Type *getImageType(SPIRVArgDesc Desc, Module *M) { case SPIRVType::Image1d: Name += OCLTypes::Dim1d; break; + case SPIRVType::Image1dArray: + Name += OCLTypes::Dim1dArray; + break; case SPIRVType::Image1dBuffer: Name += OCLTypes::Dim1dBuffer; break; case SPIRVType::Image2d: Name += OCLTypes::Dim2d; break; + case SPIRVType::Image2dArray: + Name += OCLTypes::Dim2dArray; + break; case SPIRVType::Image3d: Name += OCLTypes::Dim3d; break; @@ -149,15 +136,23 @@ static Type *getImageType(SPIRVArgDesc Desc, Module *M) { return getOpaquePtrType(M, Name, getOpaqueTypeAddressSpace(Desc.Ty)); } -// Get or create buffer type with given access qualifier. -static Type *getBufferType(AccessType Acc, Module *M) { +// Get or create vector compute extension type with given access qualifier. +static Type *getIntelExtType(SPIRVArgDesc Desc, Module *M) { std::string Name = IntelTypes::TypePrefix; - Name += IntelTypes::Buffer; + switch (Desc.Ty) { + case SPIRVType::Buffer: + Name += IntelTypes::Buffer; + break; + case SPIRVType::Image2dMediaBlock: + Name += IntelTypes::MediaBlockImage; + break; + default: + llvm_unreachable("Unexpected spirv type for intel extensions"); + } - addCommonTypesPostfix(Name, Acc); + addCommonTypesPostfix(Name, Desc.Acc); - return getOpaquePtrType(M, Name, - getOpaqueTypeAddressSpace(SPIRVType::Buffer)); + return getOpaquePtrType(M, Name, getOpaqueTypeAddressSpace(Desc.Ty)); } // Sampler and surface arguments require opaque types that will be @@ -167,7 +162,8 @@ static Type *getOpaqueType(SPIRVArgDesc Desc, Module *M) { case SPIRVType::Sampler: return getSamplerType(M); case SPIRVType::Buffer: - return getBufferType(Desc.Acc, M); + case SPIRVType::Image2dMediaBlock: + return getIntelExtType(Desc, M); default: return getImageType(Desc, M); } @@ -200,11 +196,11 @@ transformKernelSignature(Function &F, const std::vector &Descs) { assert(!F.isVarArg() && "Kernel cannot be vararg"); auto *NewFTy = FunctionType::get(F.getReturnType(), NewParams, false); - auto *NewF = VCINTR::Function::Create( - NewFTy, F.getLinkage(), VCINTR::GlobalValue::getAddressSpace(F)); + auto *NewF = Function::Create(NewFTy, F.getLinkage(), F.getAddressSpace()); NewF->copyAttributesFrom(&F); NewF->takeName(&F); NewF->copyMetadata(&F, 0); + NewF->setComdat(F.getComdat()); // Remove no more needed attributes. for (int i = 0, e = Descs.size(); i != e; ++i) { @@ -215,6 +211,8 @@ transformKernelSignature(Function &F, const std::vector &Descs) { NewF->removeParamAttr(i, VCFunctionMD::VCArgumentDesc); } + legalizeParamAttributes(NewF); + return NewF; } @@ -233,6 +231,7 @@ static Instruction *rewriteArgumentUses(Argument &OldArg, Argument &NewArg) { Module *M = OldArg.getParent()->getParent(); Function *ConvFn = GenXIntrinsic::getGenXDeclaration( M, GenXIntrinsic::genx_address_convert, {OldTy, NewTy}); + ConvFn->addFnAttr(VCFunctionMD::VCFunction); auto *Conv = CallInst::Create(ConvFn, {&NewArg}); OldArg.replaceAllUsesWith(Conv); return Conv; @@ -255,8 +254,11 @@ static SPIRVArgDesc parseArgDesc(StringRef Desc) { Ty = StringSwitch>(Tok) .Case(ArgDesc::Buffer, SPIRVType::Buffer) .Case(ArgDesc::Image1d, SPIRVType::Image1d) + .Case(ArgDesc::Image1dArray, SPIRVType::Image1dArray) .Case(ArgDesc::Image1dBuffer, SPIRVType::Image1dBuffer) .Case(ArgDesc::Image2d, SPIRVType::Image2d) + .Case(ArgDesc::Image2dArray, SPIRVType::Image2dArray) + .Case(ArgDesc::Image2dMediaBlock, SPIRVType::Image2dMediaBlock) .Case(ArgDesc::Image3d, SPIRVType::Image3d) .Case(ArgDesc::SVM, SPIRVType::Pointer) .Case(ArgDesc::Sampler, SPIRVType::Sampler) @@ -305,8 +307,11 @@ static SPIRVArgDesc analyzeSurfaceArg(StringRef Desc) { switch (SPVDesc.Ty) { case SPIRVType::Buffer: case SPIRVType::Image1d: + case SPIRVType::Image1dArray: case SPIRVType::Image1dBuffer: case SPIRVType::Image2d: + case SPIRVType::Image2dArray: + case SPIRVType::Image2dMediaBlock: case SPIRVType::Image3d: return SPVDesc; // CMRT does not require to annotate arguments. @@ -462,12 +467,13 @@ bool GenXSPIRVWriterAdaptorImpl::run(Module &M) { } } - if (auto *MD = M.getNamedMetadata(FunctionMD::GenXKernels)) { - for (auto &&F : M) + + for (auto &&F : M) runOnFunction(F); - // Old metadata is not needed anymore at this point. + + // Old metadata is not needed anymore at this point. + if (auto *MD = M.getNamedMetadata(FunctionMD::GenXKernels)) M.eraseNamedMetadata(MD); - } if (RewriteTypes) rewriteKernelsTypes(M); @@ -484,41 +490,48 @@ bool GenXSPIRVWriterAdaptorImpl::runOnFunction(Function &F) { F.addFnAttr(VCFunctionMD::VCFunction); auto Attrs = F.getAttributes(); - if (Attrs.hasFnAttribute(FunctionMD::CMStackCall)) { + if (VCINTR::AttributeList::hasFnAttr(Attrs, FunctionMD::CMStackCall)) { F.addFnAttr(VCFunctionMD::VCStackCall); } - if (Attrs.hasFnAttribute(FunctionMD::CMCallable)) { + if (VCINTR::AttributeList::hasFnAttr(Attrs, FunctionMD::CMCallable)) { F.addFnAttr(VCFunctionMD::VCCallable); } - if (Attrs.hasFnAttribute(FunctionMD::CMGenxSIMT)) { + if (VCINTR::AttributeList::hasFnAttr(Attrs, FunctionMD::CMEntry)) { + F.addFnAttr(VCFunctionMD::VCFCEntry); + } + + if (VCINTR::AttributeList::hasFnAttr(Attrs, FunctionMD::CMGenxSIMT)) { auto SIMTMode = StringRef(); - SIMTMode = - Attrs.getAttribute(AttributeList::FunctionIndex, FunctionMD::CMGenxSIMT) - .getValueAsString(); + SIMTMode = VCINTR::AttributeList::getAttributeAtIndex( + Attrs, AttributeList::FunctionIndex, FunctionMD::CMGenxSIMT) + .getValueAsString(); F.addFnAttr(VCFunctionMD::VCSIMTCall, SIMTMode); } auto &&Context = F.getContext(); - if (Attrs.hasFnAttribute(FunctionMD::CMFloatControl)) { + if (VCINTR::AttributeList::hasFnAttr(Attrs, FunctionMD::CMFloatControl)) { auto FloatControl = unsigned(0); - Attrs.getAttribute(AttributeList::FunctionIndex, FunctionMD::CMFloatControl) + VCINTR::AttributeList::getAttributeAtIndex( + Attrs, AttributeList::FunctionIndex, FunctionMD::CMFloatControl) .getValueAsString() .getAsInteger(0, FloatControl); auto Attr = Attribute::get(Context, VCFunctionMD::VCFloatControl, std::to_string(FloatControl)); - F.addAttribute(AttributeList::FunctionIndex, Attr); + VCINTR::Function::addAttributeAtIndex(F, AttributeList::FunctionIndex, + Attr); } auto *KernelMDs = F.getParent()->getNamedMetadata(FunctionMD::GenXKernels); if (!KernelMDs) return true; - if (Attrs.hasFnAttribute(FunctionMD::OCLRuntime)) { + if (VCINTR::AttributeList::hasFnAttr(Attrs, FunctionMD::OCLRuntime)) { auto SIMDSize = unsigned(0); - Attrs.getAttribute(AttributeList::FunctionIndex, FunctionMD::OCLRuntime) + VCINTR::AttributeList::getAttributeAtIndex( + Attrs, AttributeList::FunctionIndex, FunctionMD::OCLRuntime) .getValueAsString() .getAsInteger(0, SIMDSize); auto SizeMD = ConstantAsMetadata::get( @@ -548,7 +561,7 @@ bool GenXSPIRVWriterAdaptorImpl::runOnFunction(Function &F) { auto ArgKind = V->getZExtValue(); auto Attr = Attribute::get(Context, VCFunctionMD::VCArgumentKind, std::to_string(ArgKind)); - F.addAttribute(ArgNo + 1, Attr); + VCINTR::Function::addAttributeAtIndex(F, ArgNo + 1, Attr); } } } @@ -561,7 +574,8 @@ bool GenXSPIRVWriterAdaptorImpl::runOnFunction(Function &F) { auto SLMSize = V->getZExtValue(); auto Attr = Attribute::get(Context, VCFunctionMD::VCSLMSize, std::to_string(SLMSize)); - F.addAttribute(AttributeList::FunctionIndex, Attr); + VCINTR::Function::addAttributeAtIndex(F, AttributeList::FunctionIndex, + Attr); } } @@ -575,7 +589,7 @@ bool GenXSPIRVWriterAdaptorImpl::runOnFunction(Function &F) { auto ArgKind = V->getZExtValue(); auto Attr = Attribute::get(Context, VCFunctionMD::VCArgumentIOKind, std::to_string(ArgKind)); - F.addAttribute(ArgNo + 1, Attr); + VCINTR::Function::addAttributeAtIndex(F, ArgNo + 1, Attr); } } } @@ -590,12 +604,24 @@ bool GenXSPIRVWriterAdaptorImpl::runOnFunction(Function &F) { auto &&Desc = MS->getString(); auto Attr = Attribute::get(Context, VCFunctionMD::VCArgumentDesc, Desc); - F.addAttribute(ArgNo + 1, Attr); + VCINTR::Function::addAttributeAtIndex(F, ArgNo + 1, Attr); } } } } + if (KernelMD->getNumOperands() > KernelMDOp::NBarrierCnt) { + if (auto VM = dyn_cast( + KernelMD->getOperand(KernelMDOp::NBarrierCnt))) + if (auto V = dyn_cast(VM->getValue())) { + auto NBarrierCnt = V->getZExtValue(); + auto Attr = Attribute::get(Context, VCFunctionMD::VCNamedBarrierCount, + std::to_string(NBarrierCnt)); + VCINTR::Function::addAttributeAtIndex(F, AttributeList::FunctionIndex, + Attr); + } + } + return true; } diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp index 37f94706..ba6748ab 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp @@ -1,29 +1,13 @@ -/*===================== begin_copyright_notice ================================== +/*========================== begin_copyright_notice ============================ - Copyright (c) 2020, Intel Corporation +Copyright (C) 2015-2021 Intel Corporation +SPDX-License-Identifier: MIT - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: +============================= end_copyright_notice ===========================*/ - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. +// Lower CM SIMD control flow - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ - -//===----------------------------------------------------------------------===// -// /// CMSimdCFLowering /// ---------------- /// @@ -165,23 +149,22 @@ /// //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "cmsimdcflowering" - +#include "llvm/GenXIntrinsics/GenXSimdCFLowering.h" #include "llvm/ADT/MapVector.h" #include "llvm/Analysis/PostDominators.h" +#include "llvm/GenXIntrinsics/GenXIntrOpts.h" #include "llvm/GenXIntrinsics/GenXIntrinsics.h" #include "llvm/GenXIntrinsics/GenXMetadata.h" -#include "llvm/GenXIntrinsics/GenXIntrOpts.h" -#include "llvm/GenXIntrinsics/GenXSimdCFLowering.h" #include "llvm/IR/Constants.h" #include "llvm/IR/DebugInfo.h" #include "llvm/IR/DiagnosticInfo.h" #include "llvm/IR/DiagnosticPrinter.h" +#include "llvm/IR/IRBuilder.h" #include "llvm/IR/Instructions.h" #include "llvm/IR/Intrinsics.h" -#include "llvm/IR/IRBuilder.h" #include "llvm/IR/LLVMContext.h" #include "llvm/IR/Module.h" +#include "llvm/IR/PatternMatch.h" #include "llvm/IR/ValueHandle.h" #include "llvm/Pass.h" #include "llvm/Support/Debug.h" @@ -189,13 +172,9 @@ #include #include -#if VC_INTR_LLVM_VERSION_MAJOR >= 8 -#include -#endif - -#include "llvmVCWrapper/IR/GlobalValue.h" #include "llvmVCWrapper/IR/DerivedTypes.h" -#include "llvmVCWrapper/IR/InstrTypes.h" + +#define DEBUG_TYPE "cmsimdcflowering" using namespace llvm; @@ -349,7 +328,7 @@ bool CMSimdCFLowering::doInitialization(Module &M) continue; // Transform all load store on volatile globals to vload/vstore to disable // optimizations on this global (no PHI will be produced.). - auto AS0 = VCINTR::GlobalValue::getAddressSpace(G); + auto AS0 = G.getAddressSpace(); std::vector WL; for (auto UI = G.user_begin(); UI != G.user_end();) { auto U = *UI++; @@ -383,7 +362,7 @@ bool CMSimdCFLowering::doInitialization(Module &M) auto AS1 = LI->getPointerAddressSpace(); if (AS1 != AS0) { auto PtrTy = cast(Ptr->getType()); - PtrTy = PointerType::get(PtrTy->getElementType(), AS0); + PtrTy = PointerType::get(PtrTy->getPointerElementType(), AS0); Ptr = Builder.CreateAddrSpaceCast(Ptr, PtrTy); } Type* Tys[] = { LI->getType(), Ptr->getType() }; @@ -400,7 +379,7 @@ bool CMSimdCFLowering::doInitialization(Module &M) auto AS1 = SI->getPointerAddressSpace(); if (AS1 != AS0) { auto PtrTy = cast(Ptr->getType()); - PtrTy = PointerType::get(PtrTy->getElementType(), AS0); + PtrTy = PointerType::get(PtrTy->getPointerElementType(), AS0); Ptr = Builder.CreateAddrSpaceCast(Ptr, PtrTy); } Type* Tys[] = { SI->getValueOperand()->getType(), Ptr->getType() }; @@ -794,7 +773,7 @@ void CMSimdCFLower::findAndSplitJoinPoints() } for (auto sji = Jumps.begin(), sje = Jumps.end(); sji != sje; ++sji) { assert((*sji)->isTerminator() && "Expected terminator inst"); - auto Br = cast(*sji); + auto *Br = *sji; unsigned SimdWidth = SimdBranches[Br->getParent()]; LLVM_DEBUG(dbgs() << *Br << "\n"); auto JP = Br->getSuccessor(0); @@ -851,7 +830,7 @@ void CMSimdCFLower::determineJIPs() for (auto NextBB = &F->front(), EndBB = &F->back(); NextBB;) { auto BB = NextBB; NextBB = BB == EndBB ? nullptr : BB->getNextNode(); - auto Term = cast(BB->getTerminator()); + auto *Term = BB->getTerminator(); for (unsigned si = 0, se = Term->getNumSuccessors(); si != se; ++si) { BasicBlock *Succ = Term->getSuccessor(si); if (Succ == NextBB) @@ -960,7 +939,7 @@ void CMSimdCFLower::determineJIP(BasicBlock *BB, if (NeedNextJoin && JoinPoints.count(JP)) break; // found join point // See if JP finishes with a branch to BB or before. - auto Term = cast(JP->getTerminator()); + auto *Term = JP->getTerminator(); for (unsigned si = 0, se = Term->getNumSuccessors(); si != se; ++si) { auto Succ = Term->getSuccessor(si); if ((*Numbers)[Succ] <= BBNum) { @@ -1094,7 +1073,7 @@ void CMSimdCFLower::predicateInst(Instruction *Inst, unsigned SimdWidth) { return; } // An IntrNoMem intrinsic is an ALU intrinsic and can be ignored. - if (Callee->doesNotAccessMemory() || CI->getNumArgOperands() == 0) + if (Callee->doesNotAccessMemory() || CI->arg_size() == 0) return; // no predication for intrinsic marked as ISPC uniform, // for example, atomic and oword_store used in printf @@ -1102,7 +1081,7 @@ void CMSimdCFLower::predicateInst(Instruction *Inst, unsigned SimdWidth) { return; // Look for a predicate operand in operand 2, 1 or 0. - unsigned PredNum = CI->getNumArgOperands() - 1; + unsigned PredNum = CI->arg_size() - 1; for (;;) { if (auto VT = dyn_cast(CI->getArgOperand(PredNum)->getType())) { @@ -1234,6 +1213,17 @@ unsigned CMSimdCFLower::deduceNumChannels(Instruction *SI) { NumChannels = ResultElems / AddrElems; break; } + case GenXIntrinsic::genx_lsc_load_slm: + case GenXIntrinsic::genx_lsc_load_stateless: + case GenXIntrinsic::genx_lsc_load_bindless: + case GenXIntrinsic::genx_lsc_load_bti: + case GenXIntrinsic::genx_lsc_prefetch_bti: + case GenXIntrinsic::genx_lsc_prefetch_stateless: + case GenXIntrinsic::genx_lsc_prefetch_bindless: + NumChannels = GenXIntrinsic::getLSCNumVectorElements( + static_cast( + cast(CI->getOperand(7))->getZExtValue())); + break; default: break; } @@ -1462,7 +1452,7 @@ void CMSimdCFLower::predicateSend(CallInst *CI, unsigned IntrinsicID, break; } SmallVector Args; - for (unsigned i = 0, e = CI->getNumArgOperands(); i != e; ++i) + for (unsigned i = 0, e = CI->arg_size(); i != e; ++i) if (i == PredOperandNum) Args.push_back(Pred); else @@ -1523,7 +1513,7 @@ CallInst *CMSimdCFLower::predicateWrRegion(CallInst *WrR, unsigned SimdWidth) { // First gather the args of the original wrregion. SmallVector Args; - for (unsigned i = 0, e = WrR->getNumArgOperands(); i != e; ++i) + for (unsigned i = 0, e = WrR->arg_size(); i != e; ++i) Args.push_back(WrR->getArgOperand(i)); // Modify the predicate in Args. Value *Pred = Args[GenXIntrinsic::GenXRegion::PredicateOperandNum]; diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp index 6a22e479..fa3ef25c 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp @@ -1,34 +1,13 @@ -/*===================== begin_copyright_notice ================================== +/*========================== begin_copyright_notice ============================ - Copyright (c) 2020, Intel Corporation +Copyright (C) 2020-2021 Intel Corporation +SPDX-License-Identifier: MIT - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: +============================= end_copyright_notice ===========================*/ - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ - - -//===----------------------------------------------------------------------===// -// // This file defines common functions for rewriting single element vectors -// in GenXSPIRV adaptors -// -//===----------------------------------------------------------------------===// +// in GenXSPIRV adaptors. #include "GenXSingleElementVectorUtil.h" #include "llvm/GenXIntrinsics/GenXIntrinsics.h" @@ -43,9 +22,10 @@ #include "llvm/IR/Module.h" #include "llvm/Pass.h" +#include "llvmVCWrapper/Analysis/InstructionSimplify.h" +#include "llvmVCWrapper/IR/Attributes.h" #include "llvmVCWrapper/IR/DerivedTypes.h" #include "llvmVCWrapper/IR/Function.h" -#include "llvmVCWrapper/IR/GlobalValue.h" #include "llvmVCWrapper/IR/Instructions.h" #include "llvmVCWrapper/Support/Alignment.h" @@ -73,6 +53,15 @@ static std::vector getFunctions(Module &M) { return Functions; } +// Globals with SEVs are deleted from module +// This util allows to continue iteration even after deletion +static std::vector getGlobalVariables(Module &M) { + auto Globals = std::vector{}; + std::transform(M.global_begin(), M.global_end(), std::back_inserter(Globals), + [](GlobalVariable &GV) { return &GV; }); + return Globals; +} + // Instructions with SEVs are deleted from module // This util allows to continue iteration even after deletion static std::vector getInstructions(Function &F) { @@ -103,7 +92,7 @@ static size_t getPointerNesting(Type *T, Type **ReturnNested = nullptr) { auto NPtrs = size_t{0}; auto *NestedType = T; while (dyn_cast(NestedType)) { - NestedType = cast(NestedType)->getElementType(); + NestedType = cast(NestedType)->getPointerElementType(); ++NPtrs; } if (ReturnNested) @@ -149,8 +138,8 @@ static size_t getInnerPointerVectorNesting(Type *T) { static Type *getTypeFreeFromSingleElementVector(Type *T) { // Pointer types should be "undressed" first if (auto *Ptr = dyn_cast(T)) { - auto UT = getTypeFreeFromSingleElementVector(Ptr->getElementType()); - if (UT == Ptr->getElementType()) + auto UT = getTypeFreeFromSingleElementVector(Ptr->getPointerElementType()); + if (UT == Ptr->getPointerElementType()) return Ptr; return PointerType::get(UT, Ptr->getAddressSpace()); } else if (auto *VecTy = dyn_cast(T)) { @@ -177,8 +166,8 @@ static Type *getTypeWithSingleElementVector(Type *T, size_t InnerPointers = 0) { return VCINTR::getVectorType(T, 1); auto *Ptr = cast(T); - auto *UT = - getTypeWithSingleElementVector(Ptr->getElementType(), InnerPointers); + auto *UT = getTypeWithSingleElementVector(Ptr->getPointerElementType(), + InnerPointers); return PointerType::get(UT, Ptr->getAddressSpace()); } @@ -213,17 +202,24 @@ static Value *createVectorToScalarValue(Value *Vector, Instruction *InsertBefore, size_t idx = 0) { assert(hasSingleElementVector(Vector->getType())); - if (isa(Vector->getType())) - return new BitCastInst( - Vector, getTypeFreeFromSingleElementVector(Vector->getType()), "", - InsertBefore); + Instruction *Val = nullptr; + if (isa(Vector)) + return UndefValue::get( + getTypeFreeFromSingleElementVector(Vector->getType())); + else if (isa(Vector->getType())) + Val = new BitCastInst(Vector, + getTypeFreeFromSingleElementVector(Vector->getType()), + "sev.cast.", InsertBefore); else if (auto *Const = dyn_cast(Vector)) return Const->getAggregateElement(idx); else { auto *M = InsertBefore->getModule(); - return ExtractElementInst::Create(Vector, getVectorIndex(*M, idx), "", - InsertBefore); + Val = ExtractElementInst::Create(Vector, getVectorIndex(*M, idx), + "sev.cast.", InsertBefore); } + if (auto *InVector = dyn_cast(Vector)) + Val->setDebugLoc(InVector->getDebugLoc()); + return Val; } // This util accepts SEV-rich Value and returns new, SEV-free one @@ -233,15 +229,24 @@ static Value *createVectorToScalarValue(Value *Vector, static Value *createVectorToScalarValue(Value *Vector, BasicBlock *BB, size_t idx = 0) { assert(hasSingleElementVector(Vector->getType())); - if (isa(Vector->getType())) - return new BitCastInst( - Vector, getTypeFreeFromSingleElementVector(Vector->getType()), "", BB); + Instruction *Val = nullptr; + if (isa(Vector)) + return UndefValue::get( + getTypeFreeFromSingleElementVector(Vector->getType())); + else if (isa(Vector->getType())) + Val = new BitCastInst(Vector, + getTypeFreeFromSingleElementVector(Vector->getType()), + "sev.cast.", BB); else if (auto *Const = dyn_cast(Vector)) return Const->getAggregateElement(idx); else { auto *M = BB->getModule(); - return ExtractElementInst::Create(Vector, getVectorIndex(*M, idx), "", BB); + Val = ExtractElementInst::Create(Vector, getVectorIndex(*M, idx), + "sev.cast.", BB); } + if (auto *InVector = dyn_cast(Vector)) + Val->setDebugLoc(InVector->getDebugLoc()); + return Val; } // This util accepts Scalar Value and returns new SEV-rich Value @@ -250,19 +255,20 @@ static Value *createVectorToScalarValue(Value *Vector, BasicBlock *BB, // For non-constant vectors it returns InsertElementInst static Value *createScalarToVectorValue(Value *Scalar, Type *ReferenceType, Instruction *InsertBefore) { - if (isa(Scalar->getType())) { + if (isa(Scalar)) + return UndefValue::get(ReferenceType); + else if (isa(Scalar->getType())) { auto Inner = getInnerPointerVectorNesting(ReferenceType); return new BitCastInst( - Scalar, getTypeWithSingleElementVector(Scalar->getType(), Inner), "", - InsertBefore); - } else if (isa(Scalar)) - return UndefValue::get(ReferenceType); - else if (auto *Const = dyn_cast(Scalar)) + Scalar, getTypeWithSingleElementVector(Scalar->getType(), Inner), + "sev.cast.", InsertBefore); + } else if (auto *Const = dyn_cast(Scalar)) return ConstantInt::getSigned(ReferenceType, getConstantElement(Const)); else { auto *M = InsertBefore->getModule(); return InsertElementInst::Create(UndefValue::get(ReferenceType), Scalar, - getVectorIndex(*M, 0), "", InsertBefore); + getVectorIndex(*M, 0), "sev.cast.", + InsertBefore); } } @@ -390,7 +396,11 @@ static void replaceAllUsesWith(Function &OldF, Function &NewF) { } auto *NewCall = CallInst::Create(&NewF, NewParams, "", OldInst); - NewCall->setTailCall(OldInst->isTailCall()); + NewCall->setCallingConv(OldInst->getCallingConv()); + NewCall->setTailCallKind(OldInst->getTailCallKind()); + NewCall->copyIRFlags(OldInst); + NewCall->copyMetadata(*OldInst); + NewCall->setAttributes(OldInst->getAttributes()); replaceAllUsesWith(OldInst, NewCall); } } @@ -462,11 +472,12 @@ static void manageSingleElementVectorAttribute(Function &NewF, Type *OldT, assert(!hasSingleElementVector(NewT)); auto InnerPtrs = std::to_string(getInnerPointerVectorNesting(OldT)); auto Attr = Attribute::get(NewF.getContext(), - VCFunctionMD::VCSingleElementVector, InnerPtrs); - NewF.addAttribute(AttrNo, Attr); + VCModuleMD::VCSingleElementVector, InnerPtrs); + VCINTR::Function::addAttributeAtIndex(NewF, AttrNo, Attr); } else if (hasSingleElementVector(NewT)) { assert(!hasSingleElementVector(OldT)); - NewF.removeAttribute(AttrNo, VCFunctionMD::VCSingleElementVector); + VCINTR::Function::removeAttributeAtIndex(NewF, AttrNo, + VCModuleMD::VCSingleElementVector); } } @@ -495,11 +506,12 @@ static Type *getOriginalType(Function &F, size_t AttrNo) { auto *T = AttrNo == 0 ? FuncT->getReturnType() : FuncT->getParamType(AttrNo - 1); auto Attrs = F.getAttributes(); - if (!Attrs.hasAttribute(AttrNo, VCFunctionMD::VCSingleElementVector)) + if (!VCINTR::AttributeList::hasAttributeAtIndex( + Attrs, AttrNo, VCModuleMD::VCSingleElementVector)) return T; - auto InnerPtrsStr = - Attrs.getAttribute(AttrNo, VCFunctionMD::VCSingleElementVector) - .getValueAsString(); + auto InnerPtrsStr = VCINTR::AttributeList::getAttributeAtIndex( + Attrs, AttrNo, VCModuleMD::VCSingleElementVector) + .getValueAsString(); auto InnerPtrs = InnerPtrsStr.empty() ? 0 : std::stoull(InnerPtrsStr.str()); return getTypeWithSingleElementVector(T, InnerPtrs); } @@ -532,8 +544,8 @@ static Function &getSingleElementVectorSignature(Function &F, if (NewFunctionType == F.getFunctionType()) return F; - auto &&NewF = *VCINTR::Function::Create( - NewFunctionType, F.getLinkage(), VCINTR::GlobalValue::getAddressSpace(F)); + auto &&NewF = + *Function::Create(NewFunctionType, F.getLinkage(), F.getAddressSpace()); assert(doesSignatureHaveSingleElementVector(F) || doesSignatureHaveSingleElementVector(NewF)); @@ -702,14 +714,12 @@ class SingleElementVectorInstRewriter OldInst.getOrdering(), OldInst.getSyncScopeID(), &OldInst); } -#if VC_INTR_LLVM_VERSION_MAJOR >= 8 Instruction *visitUnaryOperator(UnaryOperator &OldInst) { auto *NewT = static_cast(nullptr); auto NewVals = ValueCont{}; std::tie(NewT, NewVals) = getOperandsFreeFromSingleElementVector(OldInst); return UnaryOperator::Create(OldInst.getOpcode(), NewVals[0], "", &OldInst); } -#endif Instruction *visitVAArgInst(VAArgInst &OldInst) { auto *NewT = static_cast(nullptr); auto NewVals = ValueCont{}; @@ -744,6 +754,93 @@ class SingleElementVectorInstRewriter } }; +/// This section contains utils for rewriting global variables + +// For conversion in SEV-rich to SEV-free direction +// this function adds VCSingleElementVector attribute to global var +static void manageSingleElementVectorAttribute(GlobalVariable &GV, Type *OldT, + Type *NewT) { + if (hasSingleElementVector(OldT)) { + assert(!hasSingleElementVector(NewT)); + auto InnerPtrs = std::to_string(getInnerPointerVectorNesting(OldT)); + GV.addAttribute(VCModuleMD::VCSingleElementVector, InnerPtrs); + } +} + +static GlobalVariable &createAndTakeFrom(GlobalVariable &GV, PointerType *NewT, + Constant *Initializer) { + auto *NewGV = new GlobalVariable( + *GV.getParent(), NewT->getPointerElementType(), GV.isConstant(), + GV.getLinkage(), Initializer, "sev.global.", &GV, GV.getThreadLocalMode(), + GV.getAddressSpace(), GV.isExternallyInitialized()); + auto DebugInfoVec = SmallVector{}; + GV.getDebugInfo(DebugInfoVec); + NewGV->takeName(&GV); + NewGV->setAttributes(GV.getAttributes()); + NewGV->copyMetadata(&GV, 0); + NewGV->setComdat(GV.getComdat()); + NewGV->setAlignment(VCINTR::Align::getAlign(&GV)); + for (auto *DebugInf : DebugInfoVec) + NewGV->addDebugInfo(DebugInf); + return *NewGV; +} + +static void rewriteGlobalVariable(GlobalVariable &GV) { + auto *T = cast(GV.getType()); + auto *NewT = cast(getTypeFreeFromSingleElementVector(T)); + if (NewT == T) + return; + auto *Initializer = static_cast(nullptr); + if (GV.hasInitializer()) + Initializer = cast(createVectorToScalarValue( + GV.getInitializer(), static_cast(nullptr))); + auto &&NewGV = createAndTakeFrom(GV, NewT, Initializer); + while (GV.use_begin() != GV.use_end()) { + auto &&Use = GV.use_begin(); + auto *Inst = cast(Use->getUser()); + auto *V = createScalarToVectorValue(&NewGV, T, Inst); + *Use = V; + } + manageSingleElementVectorAttribute(NewGV, T, NewT); + GV.eraseFromParent(); +} + +static void restoreGlobalVariable(GlobalVariable &GV) { + auto *T = cast(GV.getType()); + if (!GV.hasAttribute(VCModuleMD::VCSingleElementVector)) + return; + auto InnerPtrsStr = + GV.getAttribute(VCModuleMD::VCSingleElementVector).getValueAsString(); + auto InnerPtrs = InnerPtrsStr.empty() ? 0 : std::stoull(InnerPtrsStr.str()); + auto *NewT = cast(getTypeWithSingleElementVector(T, InnerPtrs)); + if (NewT == T) + return; + auto *Initializer = static_cast(nullptr); + if (GV.hasInitializer()) + Initializer = cast(createScalarToVectorValue( + GV.getInitializer(), NewT->getPointerElementType(), + static_cast(nullptr))); + auto &&NewGV = createAndTakeFrom(GV, NewT, Initializer); + while (GV.use_begin() != GV.use_end()) { + auto &&Use = GV.use_begin(); + auto *Inst = cast(Use->getUser()); + auto *V = createVectorToScalarValue(&NewGV, Inst); + *Use = V; + } + manageSingleElementVectorAttribute(NewGV, T, NewT); + GV.eraseFromParent(); +} + +static void rewriteGlobalVariables(Module &M, bool IsScalarToVector = false) { + auto &&Globals = getGlobalVariables(M); + for (auto *GV : Globals) { + if (IsScalarToVector) + restoreGlobalVariable(*GV); + else + rewriteGlobalVariable(*GV); + } +} + /// This section contains utils for collapsing pairs of convertion instructions /// After rewriting all insructions in the module there are lots of pairs /// Extract-insert and bitcast-bitcast conversions left @@ -756,7 +853,7 @@ static void collapseBitcastInst(BitCastInst *BitCast, bool CollapseCannotFail) { } auto &&M = *BitCast->getModule(); auto &&Q = SimplifyQuery(M.getDataLayout()); - auto *ReplaceWith = SimplifyCastInst( + auto *ReplaceWith = VCINTR::SimplifyCastInst( BitCast->getOpcode(), BitCast->getOperand(0), BitCast->getType(), Q); if (!CollapseCannotFail && !ReplaceWith) return; @@ -797,8 +894,8 @@ static void collapseExtractInst(ExtractElementInst *Extract, } auto &&M = *Extract->getModule(); auto &&Q = SimplifyQuery(M.getDataLayout()); - auto *ReplaceWith = SimplifyExtractElementInst(Extract->getOperand(0), - Extract->getOperand(1), Q); + auto *ReplaceWith = VCINTR::SimplifyExtractElementInst( + Extract->getOperand(0), Extract->getOperand(1), Q); if (!CollapseCannotFail && !ReplaceWith) return; assert(ReplaceWith && "Oops... Cannot collapse ExtractElement instruction"); @@ -814,7 +911,7 @@ static void collapseInsertInst(InsertElementInst *Insert, } auto &&M = *Insert->getModule(); auto &&Q = SimplifyQuery(M.getDataLayout()); - auto *ReplaceWith = SimplifyInsertElementInst( + auto *ReplaceWith = VCINTR::SimplifyInsertElementInst( Insert->getOperand(0), Insert->getOperand(1), Insert->getOperand(2), Q); // SimplifyInsertElementInst provides too simple analysis @@ -894,7 +991,7 @@ static void collapseInsertInstructions(Function &F, /// They either remove or restore Single Element Vectors in the module void rewriteSingleElementVectors(Module &M) { - // TODO: rewrite globals + rewriteGlobalVariables(M, /*IsScalarToVector=*/false); auto Functions = getFunctions(M); for (auto *F : Functions) @@ -914,7 +1011,7 @@ void rewriteSingleElementVectors(Module &M) { } void restoreSingleElementVectors(Module &M) { - // TODO: rewrite globals + rewriteGlobalVariables(M, /*IsScalarToVector=*/true); auto Functions = getFunctions(M); for (auto *F : Functions) diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.h b/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.h index 0378f630..d7177578 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.h +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.h @@ -1,34 +1,13 @@ -/*===================== begin_copyright_notice ================================== +/*========================== begin_copyright_notice ============================ - Copyright (c) 2020, Intel Corporation +Copyright (C) 2020-2021 Intel Corporation +SPDX-License-Identifier: MIT - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: +============================= end_copyright_notice ===========================*/ - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ - - -//===----------------------------------------------------------------------===// -// // This file declares functions for rewriting single element vectors -// in GenXSPIRV adaptors -// -//===----------------------------------------------------------------------===// +// in GenXSPIRV adaptors. #include "llvm/IR/Module.h" diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXVersion.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXVersion.cpp new file mode 100644 index 00000000..9375c691 --- /dev/null +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXVersion.cpp @@ -0,0 +1,28 @@ +/*========================== begin_copyright_notice ============================ + +Copyright (C) 2020-2021 Intel Corporation + +SPDX-License-Identifier: MIT + +============================= end_copyright_notice ===========================*/ + +// This source file defines interface functions to retrive version info. + +#include "llvm/GenXIntrinsics/GenXVersion.h" +#include "llvm/GenXIntrinsics/GenXVersion.inc" + +std::string llvm::GenXIntrinsic::getVCIntrinsicsRevision() { +#ifdef VCI_REVISION + return VCI_REVISION; +#else + return ""; +#endif +} + +std::string llvm::GenXIntrinsic::getVCIntrinsicsRepository() { +#ifdef VCI_REPOSITORY + return VCI_REPOSITORY; +#else + return ""; +#endif +} diff --git a/GenXIntrinsics/test/Adaptors/addr_conv_attribute_writer.ll b/GenXIntrinsics/test/Adaptors/addr_conv_attribute_writer.ll new file mode 100644 index 00000000..62b1ccb1 --- /dev/null +++ b/GenXIntrinsics/test/Adaptors/addr_conv_attribute_writer.ll @@ -0,0 +1,34 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2021-2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; Test @llvm.genx.address.convert intrinsic generation with proper attributes + +; RUN: opt -S -GenXSPIRVWriterAdaptor < %s | FileCheck %s + +define void @test(i32 %buf) { +; CHECK-LABEL: @test( +; CHECK: %intel.buffer_rw_t addrspace(1)* +; CHECK: [[BUF:%[^,]+]]) +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.genx.address.convert.i32.p1intel.buffer_rw_t(%intel.buffer_rw_t addrspace(1)* [[BUF]]) +; CHECK-NEXT: ret void +; +entry: + ret void +} + +; CHECK: declare !genx_intrinsic_id !{{[0-9]+}} i32 @llvm.genx.address.convert.i32.p1intel.buffer_rw_t(%intel.buffer_rw_t addrspace(1)*) #[[ATTRS:[0-9]+]] +!genx.kernels = !{!0} + +; CHECK: attributes #[[ATTRS]] +; CHECK-SAME: "VCFunction" + +!0 = !{void (i32)* @test, !"test", !1, i32 0, i32 0, !2, !3, i32 0, i32 0} +!1 = !{i32 2} +!2 = !{i32 0} +!3 = !{!"buffer_t"} diff --git a/GenXIntrinsics/test/Adaptors/annot_mess_writer.ll b/GenXIntrinsics/test/Adaptors/annot_mess_writer.ll index 9f817005..e708908a 100644 --- a/GenXIntrinsics/test/Adaptors/annot_mess_writer.ll +++ b/GenXIntrinsics/test/Adaptors/annot_mess_writer.ll @@ -1,3 +1,11 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + ; Test messy annnotations translation in writer. First valid ; annotation should be matched. diff --git a/GenXIntrinsics/test/Adaptors/annotated_args_mixed_reader.ll b/GenXIntrinsics/test/Adaptors/annotated_args_mixed_reader.ll index 59f0f74a..84815aea 100644 --- a/GenXIntrinsics/test/Adaptors/annotated_args_mixed_reader.ll +++ b/GenXIntrinsics/test/Adaptors/annotated_args_mixed_reader.ll @@ -1,4 +1,12 @@ -; XFAIL: llvm13 +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; XFAIL: llvm13, llvm14, llvm15 ; Test that reader can cope with mixed mode when some ; arguments use address convert and some do not. diff --git a/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_reader.ll b/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_reader.ll index 0408dc42..9a47be46 100644 --- a/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_reader.ll +++ b/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_reader.ll @@ -1,4 +1,12 @@ -; XFAIL: llvm13 +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; XFAIL: llvm13, llvm14, llvm15 ; Test that reader correctly restores metadata and does ; not change other things if there is no address conversion ; but correct SPIRV types in signature. diff --git a/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_writer.ll b/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_writer.ll index 377b628f..baab71ca 100644 --- a/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_writer.ll +++ b/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_writer.ll @@ -1,3 +1,11 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + ; Test that writer does not changes signature if correct ; types are already used. Just drop all annotations. diff --git a/GenXIntrinsics/test/Adaptors/annotated_args_reader.ll b/GenXIntrinsics/test/Adaptors/annotated_args_reader.ll index a1a4d987..db7c3a15 100644 --- a/GenXIntrinsics/test/Adaptors/annotated_args_reader.ll +++ b/GenXIntrinsics/test/Adaptors/annotated_args_reader.ll @@ -1,4 +1,12 @@ -; XFAIL: llvm13 +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; XFAIL: llvm13, llvm14, llvm15 ; Test kernel argument translation from new style with opaque types ; that SPIRV translator can understand to old style with ; metadata. Here annotations for OCL runtime are used. diff --git a/GenXIntrinsics/test/Adaptors/annotated_args_writer.ll b/GenXIntrinsics/test/Adaptors/annotated_args_writer.ll index c9f6fe9e..3125f98e 100644 --- a/GenXIntrinsics/test/Adaptors/annotated_args_writer.ll +++ b/GenXIntrinsics/test/Adaptors/annotated_args_writer.ll @@ -1,3 +1,11 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + ; Test kernel arguments translation from old style with metadata to ; new style with opaque types that SPIRV translator can ; understand. Here annotations for OCL runtime are used. diff --git a/GenXIntrinsics/test/Adaptors/args_attributes_transform_reader.ll b/GenXIntrinsics/test/Adaptors/args_attributes_transform_reader.ll new file mode 100644 index 00000000..5310a881 --- /dev/null +++ b/GenXIntrinsics/test/Adaptors/args_attributes_transform_reader.ll @@ -0,0 +1,26 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; Test that adaptor correctly handles parameter attributes with types. + +; UNSUPPORTED: llvm8 +; XFAIL: llvm13, llvm14, llvm15 +; RUN: opt -S -GenXSPIRVReaderAdaptor < %s | FileCheck %s +; CHECK: @test +; CHECK-SAME: (%foo addrspace(1)* byval(%foo) %arg) + +%foo = type { i32 } + +define spir_kernel void @test(i8 addrspace(1)* byval(i8) "VCArgumentIOKind"="0" %arg) #0 { + %1 = call %foo addrspace(1)* @llvm.genx.address.convert.p1foo.p1i8(i8 addrspace(1)* %arg) + ret void +} + +declare %foo addrspace(1)* @llvm.genx.address.convert.p1foo.p1i8(i8 addrspace(1)*) + +attributes #0 = { "VCFunction" } diff --git a/GenXIntrinsics/test/Adaptors/args_attributes_transform_writer.ll b/GenXIntrinsics/test/Adaptors/args_attributes_transform_writer.ll new file mode 100644 index 00000000..c0496773 --- /dev/null +++ b/GenXIntrinsics/test/Adaptors/args_attributes_transform_writer.ll @@ -0,0 +1,28 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; Test that adaptor correctly handles parameter attributes with types. + +; UNSUPPORTED: llvm8 +; RUN: opt -S -GenXSPIRVWriterAdaptor < %s | FileCheck %s +; CHECK: @test +; CHECK-SAME: i8 +; CHECK-SAME: byval(i8) +; CHECK-SAME: arg + +%foo = type { i32 } + +define spir_kernel void @test(%foo addrspace(1)* byval(%foo) %arg) { + ret void +} + +!genx.kernels = !{!0} +!0 = !{void (%foo addrspace(1)*)* @test, !"test", !1, i32 0, i32 0, !2, !3, i32 0} +!1 = !{i32 0} +!2 = !{i32 0} +!3 = !{!"svmptr_t"} diff --git a/GenXIntrinsics/test/Adaptors/combined_args_reader.ll b/GenXIntrinsics/test/Adaptors/combined_args_reader.ll index 0940c0bf..fe1dc276 100644 --- a/GenXIntrinsics/test/Adaptors/combined_args_reader.ll +++ b/GenXIntrinsics/test/Adaptors/combined_args_reader.ll @@ -1,4 +1,12 @@ -; XFAIL: llvm13 +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; XFAIL: llvm13, llvm14, llvm15 ; Test combined reader translation: kernel has both native SPIRV types ; and impicit arguments. Implicit arguments would not show in normal ; flow, though they appear in old cmc. diff --git a/GenXIntrinsics/test/Adaptors/combined_args_writer.ll b/GenXIntrinsics/test/Adaptors/combined_args_writer.ll index 0b7b9e60..3be41ad4 100644 --- a/GenXIntrinsics/test/Adaptors/combined_args_writer.ll +++ b/GenXIntrinsics/test/Adaptors/combined_args_writer.ll @@ -1,3 +1,11 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + ; Test combined writer translation: kernel has both annotated explicit ; arguments and impicit arguments. Implicit arguments would not show ; in normal flow, though they appear in old cmc. diff --git a/GenXIntrinsics/test/Adaptors/empty_kernel_writer.ll b/GenXIntrinsics/test/Adaptors/empty_kernel_writer.ll index 0c211f00..2fb013d2 100644 --- a/GenXIntrinsics/test/Adaptors/empty_kernel_writer.ll +++ b/GenXIntrinsics/test/Adaptors/empty_kernel_writer.ll @@ -1,3 +1,11 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + ; Test empty kernel metadata translation: old -> new. ; RUN: opt -S -GenXSPIRVWriterAdaptor < %s | FileCheck %s diff --git a/GenXIntrinsics/test/Adaptors/fun_attributes_transform_reader.ll b/GenXIntrinsics/test/Adaptors/fun_attributes_transform_reader.ll new file mode 100644 index 00000000..68b0f336 --- /dev/null +++ b/GenXIntrinsics/test/Adaptors/fun_attributes_transform_reader.ll @@ -0,0 +1,67 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; Test that adaptor correctly translates function attributes to VC-specific +; metadata (the processed attributes are expected to be discarded) + +; UNSUPPORTED: llvm8 +; XFAIL: llvm13, llvm14, llvm15 +; RUN: opt -S -GenXSPIRVReaderAdaptor < %s | FileCheck %s +; CHECK: @test_VCFunction() +; CHECK: @test_VCStackCall() +; CHECK-SAME: #[[FATR_STACK_CALL_ATTR_IDX:[0-9]+]] +; CHECK: @test_VCCallable() +; CHECK-SAME: #[[FATR_CALLABLE_ATTR_IDX:[0-9]+]] +; CHECK: @test_VCFCEntry() +; CHECK-SAME: #[[FATR_FC_ENTRY_IDX:[0-9]+]] +; CHECK: @test_VCSIMTCall() +; CHECK-SAME: #[[FATR_SIMT_CALL_IDX:[0-9]+]] +; CHECK: @test_VCFloatControl() +; CHECK-SAME: #[[FATR_FLOAT_CONTROL_IDX:[0-9]+]] +; CHECK: @test_VCSLMSize() +; CHECK-SAME: #[[FATR_SLM_SIZE_IDX:[0-9]+]] + +define void @test_VCFunction() #0 { + ret void +} +define void @test_VCStackCall() #1 { + ret void +} +define void @test_VCCallable() #2 { + ret void +} +define void @test_VCFCEntry() #3 { + ret void +} +define void @test_VCSIMTCall() #4 { + ret void +} +define void @test_VCFloatControl() #5 { + ret void +} +define spir_kernel void @test_VCSLMSize() #6 { + ret void +} + +; CHECK-DAG: attributes #[[FATR_STACK_CALL_ATTR_IDX]] = { "CMStackCall" } +; CHECK-DAG: attributes #[[FATR_CALLABLE_ATTR_IDX]] = { "CMCallable" } +; CHECK-DAG: attributes #[[FATR_FC_ENTRY_IDX]] = { "CMEntry" } +; CHECK-DAG: attributes #[[FATR_SIMT_CALL_IDX]] = { "CMGenxSIMT" } +; CHECK-DAG: attributes #[[FATR_FLOAT_CONTROL_IDX]] = { "CMFloatControl"="0" } +; CHECK-DAG: attributes #[[FATR_SLM_SIZE_IDX]] = { "CMGenxMain" } + +; CHECK-DAG: !{void ()* @test_VCSLMSize, !"test_VCSLMSize", !{{[0-9]+}}, i32 100500, i32 0, !{{[0-9]+}}, !{{[0-9]+}}, i32 0} + +attributes #0 = { "VCFunction" } +attributes #1 = { "VCFunction" "VCStackCall" } +attributes #2 = { "VCFunction" "VCCallable" } +attributes #3 = { "VCFunction" "VCFCEntry" } +attributes #4 = { "VCFunction" "VCSIMTCall" } +attributes #5 = { "VCFunction" "VCFloatControl"="0" } +attributes #6 = { "VCFunction" "VCSLMSize"="100500" } + diff --git a/GenXIntrinsics/test/Adaptors/image_array_reader.ll b/GenXIntrinsics/test/Adaptors/image_array_reader.ll new file mode 100644 index 00000000..28965a55 --- /dev/null +++ b/GenXIntrinsics/test/Adaptors/image_array_reader.ll @@ -0,0 +1,43 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; XFAIL: llvm13, llvm14, llvm15 +; Test reader translation of image array arguments. + +; RUN: opt -S -GenXSPIRVReaderAdaptor < %s | FileCheck %s + +%opencl.image1d_array_ro_t = type opaque +%opencl.image2d_array_wo_t = type opaque + +define spir_kernel void @test(%opencl.image1d_array_ro_t addrspace(1)* %im1d, %opencl.image2d_array_wo_t addrspace(1)* %im2d) #0 { +; CHECK-LABEL: @test( + +; CHECK: i32 +; CHECK: [[IM1D:%[^,]+]], + +; CHECK: i32 +; CHECK: [[IM2D:%[^,]+]]) + +; CHECK-NEXT: entry: +; CHECK-NEXT: ret void +; +entry: + %0 = call i32 @llvm.genx.address.convert.i32.p1opencl.image1d_array_ro_t(%opencl.image1d_array_ro_t addrspace(1)* %im1d) + %1 = call i32 @llvm.genx.address.convert.i32.p1opencl.image2d_array_wo_t(%opencl.image2d_array_wo_t addrspace(1)* %im2d) + ret void +} + +declare i32 @llvm.genx.address.convert.i32.p1opencl.image1d_array_ro_t(%opencl.image1d_array_ro_t addrspace(1)*) +declare i32 @llvm.genx.address.convert.i32.p1opencl.image2d_array_wo_t(%opencl.image2d_array_wo_t addrspace(1)*) + +attributes #0 = { "VCFunction" } + +; CHECK: !genx.kernels = !{[[KERNEL:![0-9]+]]} +; CHECK: [[KERNEL]] = !{void (i32, i32)* @test, !"test", [[KINDS:![0-9]+]], i32 0, i32 0, !{{[0-9]+}}, [[DESCS:![0-9]+]], i32 0} +; CHECK-DAG: [[KINDS]] = !{i32 2, i32 2} +; CHECK-DAG: [[DESCS]] = !{!"image1d_array_t read_only", !"image2d_array_t write_only"} diff --git a/GenXIntrinsics/test/Adaptors/image_array_writer.ll b/GenXIntrinsics/test/Adaptors/image_array_writer.ll new file mode 100644 index 00000000..79f16761 --- /dev/null +++ b/GenXIntrinsics/test/Adaptors/image_array_writer.ll @@ -0,0 +1,36 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; Test writer translation of image array arguments. + +; RUN: opt -S -GenXSPIRVWriterAdaptor < %s | FileCheck %s + +define void @test(i32 %im1darr, i32 %im2darr) { +; CHECK-LABEL: @test( + +; CHECK: %opencl.image1d_array_ro_t addrspace(1)* +; CHECK: [[IM1D:%[^,]+]], + +; CHECK: %opencl.image2d_array_wo_t addrspace(1)* +; CHECK: [[IM2D:%[^)]+]]) + +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.genx.address.convert.i32.p1opencl.image1d_array_ro_t(%opencl.image1d_array_ro_t addrspace(1)* [[IM1D]]) +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.genx.address.convert.i32.p1opencl.image2d_array_wo_t(%opencl.image2d_array_wo_t addrspace(1)* [[IM2D]]) +; CHECK-NEXT: ret void +; +entry: + ret void +} + +!genx.kernels = !{!0} + +!0 = !{void (i32, i32)* @test, !"test", !1, i32 0, i32 0, !2, !3, i32 0, i32 0} +!1 = !{i32 2, i32 2} +!2 = !{i32 0, i32 0} +!3 = !{!"image1d_array_t read_only", !"image2d_array_t write_only"} diff --git a/GenXIntrinsics/test/Adaptors/media_block_reader.ll b/GenXIntrinsics/test/Adaptors/media_block_reader.ll new file mode 100644 index 00000000..95d5ac76 --- /dev/null +++ b/GenXIntrinsics/test/Adaptors/media_block_reader.ll @@ -0,0 +1,37 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; XFAIL: llvm13, llvm14, llvm15 +; Test reader translation of media block image arguments. + +; RUN: opt -S -GenXSPIRVReaderAdaptor < %s | FileCheck %s + +%intel.image2d_media_block_ro_t = type opaque + +define spir_kernel void @test(%intel.image2d_media_block_ro_t addrspace(1)* %image) #0 { +; CHECK-LABEL: @test( + +; CHECK: i32 +; CHECK [[IMAGE:%[^)]+]]) + +; CHECK-NEXT: entry: +; CHECK-NEXT: ret void +; +entry: + %0 = call i32 @llvm.genx.address.convert.i32.p1intel.image2d_media_block_ro_t(%intel.image2d_media_block_ro_t addrspace(1)* %image) + ret void +} + +declare i32 @llvm.genx.address.convert.i32.p1intel.image2d_media_block_ro_t(%intel.image2d_media_block_ro_t addrspace(1)*) + +attributes #0 = { "VCFunction" } + +; CHECK: !genx.kernels = !{[[KERNEL:![0-9]+]]} +; CHECK: [[KERNEL]] = !{void (i32)* @test, !"test", [[KINDS:![0-9]+]], i32 0, i32 0, !{{[0-9]+}}, [[DESCS:![0-9]+]], i32 0} +; CHECK-DAG: [[KINDS]] = !{i32 2} +; CHECK-DAG: [[DESCS]] = !{!"image2d_media_block_t read_only"} diff --git a/GenXIntrinsics/test/Adaptors/media_block_writer.ll b/GenXIntrinsics/test/Adaptors/media_block_writer.ll new file mode 100644 index 00000000..8238ee0b --- /dev/null +++ b/GenXIntrinsics/test/Adaptors/media_block_writer.ll @@ -0,0 +1,32 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; Test writer translation of media block images arguments. + +; RUN: opt -S -GenXSPIRVWriterAdaptor < %s | FileCheck %s + +define void @test(i32 %image) { +; CHECK-LABEL: @test( + +; CHECK: %intel.image2d_media_block_ro_t addrspace(1)* +; CHECK: [[IMAGE:%[^)]+]]) + +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.genx.address.convert.i32.p1intel.image2d_media_block_ro_t(%intel.image2d_media_block_ro_t addrspace(1)* [[IMAGE]]) +; CHECK-NEXT: ret void +; +entry: + ret void +} + +!genx.kernels = !{!0} + +!0 = !{void (i32)* @test, !"test", !1, i32 0, i32 0, !2, !3, i32 0, i32 0} +!1 = !{i32 2} +!2 = !{i32 0} +!3 = !{!"image2d_media_block_t read_only"} diff --git a/GenXIntrinsics/test/Adaptors/no_kernels_module_reader.ll b/GenXIntrinsics/test/Adaptors/no_kernels_module_reader.ll new file mode 100644 index 00000000..8f7e4a8e --- /dev/null +++ b/GenXIntrinsics/test/Adaptors/no_kernels_module_reader.ll @@ -0,0 +1,23 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; XFAIL: llvm13, llvm14, llvm15 +; Test general translation of attributes within module that has no kernels + +; RUN: opt -S -GenXSPIRVReaderAdaptor < %s | FileCheck %s + +; CHECK: @some_func +; CHECK-SAME: #[[ATTR_GROUP:[0-9]+]] +define <16 x float> @some_func(<16 x float> %x) local_unnamed_addr #0 { + ret <16 x float> %x +} + +; CHECK: attributes #[[ATTR_GROUP]] = { +; CHECK: "CMStackCall" +; CHECK: } +attributes #0 = { "VCStackCall" "VCFunction"} diff --git a/GenXIntrinsics/test/Adaptors/no_kernels_module_writer.ll b/GenXIntrinsics/test/Adaptors/no_kernels_module_writer.ll new file mode 100644 index 00000000..e5d7093e --- /dev/null +++ b/GenXIntrinsics/test/Adaptors/no_kernels_module_writer.ll @@ -0,0 +1,24 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; Test general translation of attributes within module that has no kernels + +; RUN: opt -S -GenXSPIRVWriterAdaptor < %s | FileCheck %s + +; CHECK: @some_func +; CHECK: #[[ATTR_GROUP:[0-9]+]] + +define <16 x float> @some_func(<16 x float> %x) local_unnamed_addr #0 { + ret <16 x float> %x +} + +; CHECK: attributes #[[ATTR_GROUP]] = { +; CHECK-DAG: "VCFunction" +; CHECK-DAG: "VCStackCall" +; CHECK: } +attributes #0 = { "CMStackCall" } diff --git a/GenXIntrinsics/test/Adaptors/no_vcfunction_reader.ll b/GenXIntrinsics/test/Adaptors/no_vcfunction_reader.ll index 48a77d38..74fa9fc3 100644 --- a/GenXIntrinsics/test/Adaptors/no_vcfunction_reader.ll +++ b/GenXIntrinsics/test/Adaptors/no_vcfunction_reader.ll @@ -1,4 +1,12 @@ -; XFAIL: llvm13 +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; XFAIL: llvm13, llvm14, llvm15 ; Test that reader ignores signature rewriting for kernels ; that are not VCFunction. diff --git a/GenXIntrinsics/test/Adaptors/non_global_ptr_reader.ll b/GenXIntrinsics/test/Adaptors/non_global_ptr_reader.ll index 135c1a2f..5f0704e5 100644 --- a/GenXIntrinsics/test/Adaptors/non_global_ptr_reader.ll +++ b/GenXIntrinsics/test/Adaptors/non_global_ptr_reader.ll @@ -1,15 +1,21 @@ -; XFAIL: llvm13 +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; XFAIL: llvm13, llvm14, llvm15 ; Test that reader treats only global pointer as svmptr type ; and ignores other address spaces. ; RUN: opt -S -GenXSPIRVReaderAdaptor < %s | FileCheck %s define spir_kernel void @test(i32* %ptr) #0 { -; CHECK-LABEL: @test( -; CHECK: i32* -; CHECK: "VCArgumentKind"="0" -; CHECK: [[PTR:%[^)]+]]) +; CHECK-LABEL: @test +; CHECK-SAME: (i32* [[PTR:%[^)]+]]) ; CHECK-NEXT: entry: ; CHECK-NEXT: ret void diff --git a/GenXIntrinsics/test/Adaptors/old_decorated_args_reader.ll b/GenXIntrinsics/test/Adaptors/old_decorated_args_reader.ll index 9721c710..4eac7c5a 100644 --- a/GenXIntrinsics/test/Adaptors/old_decorated_args_reader.ll +++ b/GenXIntrinsics/test/Adaptors/old_decorated_args_reader.ll @@ -1,4 +1,12 @@ -; XFAIL: llvm13 +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; XFAIL: llvm13, llvm14, llvm15 ; Test reader translation of old-style decorated arguments. ; Annotations for these are directly translated from attributes to ; kernel metadata without any checks. Required until full transition @@ -7,16 +15,9 @@ ; RUN: opt -S -GenXSPIRVReaderAdaptor < %s | FileCheck %s define spir_kernel void @test(i32 "VCArgumentDesc"="image2d_t read_only" "VCArgumentKind"="2" %in, i32 "VCArgumentDesc"="image2d_t write_only" "VCArgumentKind"="2" %out, <3 x i32> "VCArgumentKind"="24" %__arg_llvm.genx.local.id) #0 { -; CHECK-LABEL: @test( - -; CHECK: i32 -; CHECK: [[IN:%[^,]+]], - -; CHECK: i32 -; CHECK: [[OUT:%[^,]+]], +; CHECK-LABEL: @test -; CHECK: <3 x i32> -; CHECK: [[LOCAL_ID:%[^)]+]]) +; CHECK-SAME: (i32 [[IN:%[^,]+]], i32 [[OUT:%[^,]+]], <3 x i32> [[LOCAL_ID:%[^)]+]]) ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP0:%.*]] = extractelement <3 x i32> [[LOCAL_ID]], i32 0 diff --git a/GenXIntrinsics/test/Adaptors/plain_args_reader.ll b/GenXIntrinsics/test/Adaptors/plain_args_reader.ll index 43137295..fca3883d 100644 --- a/GenXIntrinsics/test/Adaptors/plain_args_reader.ll +++ b/GenXIntrinsics/test/Adaptors/plain_args_reader.ll @@ -1,4 +1,12 @@ -; XFAIL: llvm13 +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; XFAIL: llvm13, llvm14, llvm15 ; Test kernel argument translation from new style with opaque types ; that SPIRV translator can understand to old style with ; metadata. Arguments without annotations are used here (CMRT like). diff --git a/GenXIntrinsics/test/Adaptors/plain_args_writer.ll b/GenXIntrinsics/test/Adaptors/plain_args_writer.ll index d322df80..b3f35231 100644 --- a/GenXIntrinsics/test/Adaptors/plain_args_writer.ll +++ b/GenXIntrinsics/test/Adaptors/plain_args_writer.ll @@ -1,3 +1,11 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + ; Test kernel arguments translation from old style with metadata to ; new style with opaque types that SPIRV translator can ; understand. Arguments without annotations are used here (CMRT like). diff --git a/GenXIntrinsics/test/Adaptors/sev_calling_conv_reader.ll b/GenXIntrinsics/test/Adaptors/sev_calling_conv_reader.ll new file mode 100644 index 00000000..fe680683 --- /dev/null +++ b/GenXIntrinsics/test/Adaptors/sev_calling_conv_reader.ll @@ -0,0 +1,37 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2022 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; Test GenXSingleElementVectorUtil preserves calling convention +; (spir_func here) + +; XFAIL: llvm13, llvm14, llvm15 +; RUN: opt -S -GenXSPIRVReaderAdaptor < %s | FileCheck %s + + +; ModuleID = 'start.ll' +source_filename = "start.ll" +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024" +target triple = "spir64-unknown-unknown" + +; Function Attrs: noinline nounwind +; CHECK: define internal spir_func void @bar(<1 x i32>* %a) #0 { +define internal spir_func void @bar(i32* "VCSingleElementVector"="0" %a) #0 { + ret void +} + +; Function Attrs: noinline nounwind +define spir_kernel void @foo() #1 !intel_reqd_sub_group_size !0 { +; CHECK: call spir_func void @bar(<1 x i32>* undef) + call spir_func void @bar(i32* undef) + ret void +} + +attributes #0 = { noinline nounwind "VCFunction" } +attributes #1 = { noinline nounwind "VCFunction" "VCNamedBarrierCount"="0" "VCSLMSize"="0" } + +!0 = !{i32 1} diff --git a/GenXIntrinsics/test/Adaptors/sev_calling_conv_writer.ll b/GenXIntrinsics/test/Adaptors/sev_calling_conv_writer.ll new file mode 100644 index 00000000..14e5853f --- /dev/null +++ b/GenXIntrinsics/test/Adaptors/sev_calling_conv_writer.ll @@ -0,0 +1,39 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2022 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; Test GenXSingleElementVectorUtil preserves calling convention +; (spir_func here) + +; RUN: opt -S -GenXSPIRVWriterAdaptor < %s | FileCheck %s + +; ModuleID = 'sev_calling_conv_reader.ll' +source_filename = "start.ll" +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024" +target triple = "spir64-unknown-unknown" + +; Function Attrs: noinline nounwind +; CHECK: define internal spir_func void @bar(i32* "VCSingleElementVector"="0" %a) #0 +define internal spir_func void @bar(<1 x i32>* %a) #0 { + ret void +} + +; Function Attrs: noinline nounwind +define dllexport spir_kernel void @foo() #1 !intel_reqd_sub_group_size !2 { +; CHECK: call spir_func void @bar(i32* undef) + call spir_func void @bar(<1 x i32>* undef) + ret void +} + +attributes #0 = { noinline nounwind } +attributes #1 = { noinline nounwind "CMGenxMain" "oclrt"="1" } + +!genx.kernels = !{!0} + +!0 = !{void ()* @foo, !"foo", !1, i32 0, i32 0, !1, !1, i32 0} +!1 = !{} +!2 = !{i32 1} diff --git a/GenXIntrinsics/test/Adaptors/sev_signature_reader.ll b/GenXIntrinsics/test/Adaptors/sev_signature_reader.ll index c311d315..7a030732 100644 --- a/GenXIntrinsics/test/Adaptors/sev_signature_reader.ll +++ b/GenXIntrinsics/test/Adaptors/sev_signature_reader.ll @@ -1,11 +1,41 @@ -; XFAIL: llvm13 +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; XFAIL: llvm13, llvm14, llvm15 ; Test simple signatures tranform ; RUN: opt -S -GenXSPIRVReaderAdaptor < %s | FileCheck %s +; CHECK: @global_var_0 = internal global <1 x i32> undef, align 4 +@global_var_0 = internal global i32 undef, align 4 #2 + +; CHECK: @global_var_1 = internal global <1 x i32**> undef, align 4 +@global_var_1 = internal global i32** undef, align 4 #3 + +; CHECK: @global_var_2 = external global <1 x i32**> +@global_var_2 = external global i32** #3 + +; CHECK: @global_var_3 = internal global i32** undef, align 4 +@global_var_3 = internal global i32** undef, align 4 + ; CHECK: <1 x i32> @some.func.1(<1 x i32> %a, <1 x i32> %b) define internal "VCSingleElementVector" i32 @some.func.1(i32 "VCSingleElementVector" %a, i32 "VCSingleElementVector" %b) local_unnamed_addr #0 { entry: + +; CHECK: call void @llvm.genx.some.intr.0(<1 x i32>* @global_var_0) + call void @llvm.genx.some.intr.0(i32* @global_var_0) + +; CHECK: call void @llvm.genx.some.intr.1(<1 x i32**>* @global_var_1) + call void @llvm.genx.some.intr.1(i32*** @global_var_1) + +; CHECK: call void @llvm.genx.some.intr.1(<1 x i32**>* @global_var_2) + call void @llvm.genx.some.intr.1(i32*** @global_var_2) + ret i32 %a } @@ -32,5 +62,10 @@ entry: ret void } +declare void @llvm.genx.some.intr.0(i32* "VCSingleElementVector") +declare void @llvm.genx.some.intr.1(i32*** "VCSingleElementVector"="2") + attributes #0 = { "VCFunction" } -attributes #1 = { "VCFunction" "VCNamedBarrierCount"="0" "VCSLMSize"="0" } +attributes #1 = { "VCFunction" "VCSLMSize"="0" } +attributes #2 = { "VCGlobalVariable" "VCSingleElementVector"="0" } +attributes #3 = { "VCGlobalVariable" "VCSingleElementVector"="2" } diff --git a/GenXIntrinsics/test/Adaptors/sev_signature_writer.ll b/GenXIntrinsics/test/Adaptors/sev_signature_writer.ll index 64dfbd29..de5da211 100644 --- a/GenXIntrinsics/test/Adaptors/sev_signature_writer.ll +++ b/GenXIntrinsics/test/Adaptors/sev_signature_writer.ll @@ -1,10 +1,37 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + ; Test simple signatures tranform ; RUN: opt -S -GenXSPIRVWriterAdaptor < %s | FileCheck %s +; CHECK: @global_var_0 = internal global i32 undef, align 4 +@global_var_0 = internal global <1 x i32> undef, align 4 #0 + +; CHECK: @global_var_1 = internal global i32** undef, align 4 +@global_var_1 = internal global <1 x i32**> undef, align 4 #0 + +; CHECK: @global_var_2 = external global i32** +@global_var_2 = external global <1 x i32**> #0 + ; CHECK: "VCSingleElementVector"="0" i32 @some.func.1(i32 "VCSingleElementVector"="0" %a, i32 "VCSingleElementVector"="0" %b) define dso_local <1 x i32> @some.func.1(<1 x i32> %a, <1 x i32> %b) local_unnamed_addr { entry: + +; CHECK: call void @llvm.genx.some.intr.0(i32* @global_var_0) + call void @llvm.genx.some.intr.0(<1 x i32>* @global_var_0) + +; CHECK: call void @llvm.genx.some.intr.1(i32*** @global_var_1) + call void @llvm.genx.some.intr.1(<1 x i32**>* @global_var_1) + +; CHECK: call void @llvm.genx.some.intr.1(i32*** @global_var_2) + call void @llvm.genx.some.intr.1(<1 x i32**>* @global_var_2) + ret <1 x i32> %a } @@ -34,6 +61,13 @@ entry: ret void } +declare void @llvm.genx.some.intr.0(<1 x i32>*) +declare void @llvm.genx.some.intr.1(<1 x i32**>*) + +; CHECK: "VCSingleElementVector"="0" +; CHECK: "VCSingleElementVector"="2" +attributes #0 = { "VCGlobalVariable" } + !genx.kernels = !{!0} !0 = !{void ()* @test, !"test", !1, i32 0, i32 0, !2, !3, i32 0} diff --git a/GenXIntrinsics/test/Adaptors/spirv_friendly_types_reader.ll b/GenXIntrinsics/test/Adaptors/spirv_friendly_types_reader.ll new file mode 100644 index 00000000..76a50f0e --- /dev/null +++ b/GenXIntrinsics/test/Adaptors/spirv_friendly_types_reader.ll @@ -0,0 +1,55 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; XFAIL: llvm13, llvm14, llvm15 +; Test reader translation of SPIRV friendly IR types + +; RUN: opt -S -GenXSPIRVReaderAdaptor < %s | FileCheck %s + +%spirv.Sampler = type opaque +%spirv.Image._void_0_0_1_0_0_0_0 = type opaque +%spirv.Image._void_1_0_1_0_0_0_1 = type opaque +%spirv.Image._void_2_0_0_0_0_0_2 = type opaque + +define spir_kernel void @test(%spirv.Sampler addrspace(2)* %smp, %spirv.Image._void_0_0_1_0_0_0_0 addrspace(1)* %im1d, %spirv.Image._void_1_0_1_0_0_0_1 addrspace(1)* %im2d, %spirv.Image._void_2_0_0_0_0_0_2 addrspace(1)* %im3d) #0 { +; CHECK-LABEL: @test( + +; CHECK: i32 +; CHECK: [[SMP:%[^,]+]], + +; CHECK: i32 +; CHECK: [[IM1D:%[^,]+]], + +; CHECK: i32 +; CHECK: [[IM2D:%[^,]+]], + +; CHECK: i32 +; CHECK: [[IM3D:%[^,]+]]) + +; CHECK-NEXT: entry: +; CHECK-NEXT: ret void +; +entry: + %0 = call i32 @llvm.genx.address.convert.i32.p2spirv.Sampler(%spirv.Sampler addrspace(2)* %smp) + %1 = call i32 @llvm.genx.address.convert.i32.p1spirv.Image._void_0_0_1_0_0_0_0(%spirv.Image._void_0_0_1_0_0_0_0 addrspace(1)* %im1d) + %2 = call i32 @llvm.genx.address.convert.i32.p1spirv.Image._void_1_0_1_0_0_0_1(%spirv.Image._void_1_0_1_0_0_0_1 addrspace(1)* %im2d) + %3 = call i32 @llvm.genx.address.convert.i32.p1spirv.Image._void_2_0_0_0_0_0_2(%spirv.Image._void_2_0_0_0_0_0_2 addrspace(1)* %im3d) + ret void +} + +declare i32 @llvm.genx.address.convert.i32.p2spirv.Sampler(%spirv.Sampler addrspace(2)*) +declare i32 @llvm.genx.address.convert.i32.p1spirv.Image._void_0_0_1_0_0_0_0(%spirv.Image._void_0_0_1_0_0_0_0 addrspace(1)*) +declare i32 @llvm.genx.address.convert.i32.p1spirv.Image._void_1_0_1_0_0_0_1(%spirv.Image._void_1_0_1_0_0_0_1 addrspace(1)*) +declare i32 @llvm.genx.address.convert.i32.p1spirv.Image._void_2_0_0_0_0_0_2(%spirv.Image._void_2_0_0_0_0_0_2 addrspace(1)*) + +attributes #0 = { "VCFunction" } + +; CHECK: !genx.kernels = !{[[KERNEL:![0-9]+]]} +; CHECK: [[KERNEL]] = !{void (i32, i32, i32, i32)* @test, !"test", [[KINDS:![0-9]+]], i32 0, i32 0, !{{[0-9]+}}, [[DESCS:![0-9]+]], i32 0} +; CHECK-DAG: [[KINDS]] = !{i32 1, i32 2, i32 2, i32 2} +; CHECK-DAG: [[DESCS]] = !{!"sampler_t", !"image1d_array_t read_only", !"image2d_array_t write_only", !"image3d_t read_write"} diff --git a/GenXIntrinsics/test/Adaptors/surface_access_reader.ll b/GenXIntrinsics/test/Adaptors/surface_access_reader.ll index f34792a4..6fbf8d1d 100644 --- a/GenXIntrinsics/test/Adaptors/surface_access_reader.ll +++ b/GenXIntrinsics/test/Adaptors/surface_access_reader.ll @@ -1,4 +1,12 @@ -; XFAIL: llvm13 +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; XFAIL: llvm13, llvm14, llvm15 ; Test kernel surface argument translation from new style with opaque ; types that SPIRV translator can understand to old style with ; metadata. This test checks access qualifiers translation. diff --git a/GenXIntrinsics/test/Adaptors/surface_access_writer.ll b/GenXIntrinsics/test/Adaptors/surface_access_writer.ll index 5f2d4065..609d445c 100644 --- a/GenXIntrinsics/test/Adaptors/surface_access_writer.ll +++ b/GenXIntrinsics/test/Adaptors/surface_access_writer.ll @@ -1,3 +1,11 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + ; Test kernel surface argument translation from old style with ; metadata to new style with opaque types that SPIRV translator can ; understand. This test checks access qualifiers translation. diff --git a/GenXIntrinsics/test/Adaptors/unknown_arg_reader.ll b/GenXIntrinsics/test/Adaptors/unknown_arg_reader.ll index 71e2a800..b1e3b1e3 100644 --- a/GenXIntrinsics/test/Adaptors/unknown_arg_reader.ll +++ b/GenXIntrinsics/test/Adaptors/unknown_arg_reader.ll @@ -1,15 +1,21 @@ -; XFAIL: llvm13 +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; XFAIL: llvm13, llvm14, llvm15 ; Test reader translation of implicit argument with argument kind ; decoration. ; RUN: opt -S -GenXSPIRVReaderAdaptor < %s | FileCheck %s define spir_kernel void @test(<3 x i32> "VCArgumentKind"="24" %__arg_llvm.genx.local.id) #0 { -; CHECK-LABEL: @test( -; CHECK: <3 x i32> -; CHECK: "VCArgumentKind"="24" -; CHECK: [[LOCAL_ID:%[^)]+]]) +; CHECK-LABEL: @test +; CHECK-SAME: (<3 x i32> [[LOCAL_ID:%[^)]+]]) ; CHECK-NEXT: entry: ; CHECK-NEXT: ret void diff --git a/GenXIntrinsics/test/Adaptors/unknown_arg_writer.ll b/GenXIntrinsics/test/Adaptors/unknown_arg_writer.ll index 8a196767..085b69e9 100644 --- a/GenXIntrinsics/test/Adaptors/unknown_arg_writer.ll +++ b/GenXIntrinsics/test/Adaptors/unknown_arg_writer.ll @@ -1,3 +1,11 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + ; Test writer translation of implicit argument. Implicit arguments ; should not appear in current form after transition from cmc. diff --git a/GenXIntrinsics/test/CMakeLists.txt b/GenXIntrinsics/test/CMakeLists.txt index c6f8bdb2..62d22032 100644 --- a/GenXIntrinsics/test/CMakeLists.txt +++ b/GenXIntrinsics/test/CMakeLists.txt @@ -1,3 +1,11 @@ +#=========================== begin_copyright_notice ============================ +# +# Copyright (C) 2020-2021 Intel Corporation +# +# SPDX-License-Identifier: MIT +# +#============================ end_copyright_notice ============================= + if(BUILD_EXTERNAL) if(NOT EXISTS ${LLVM_EXTERNAL_LIT}) message(FATAL_ERROR "External build requires LLVM_EXTERNAL_LIT to be defined to lit executable") diff --git a/GenXIntrinsics/test/Plugin/CMakeLists.txt b/GenXIntrinsics/test/Plugin/CMakeLists.txt index e0f15e9b..a03393ce 100644 --- a/GenXIntrinsics/test/Plugin/CMakeLists.txt +++ b/GenXIntrinsics/test/Plugin/CMakeLists.txt @@ -1,3 +1,11 @@ +#=========================== begin_copyright_notice ============================ +# +# Copyright (C) 2020-2021 Intel Corporation +# +# SPDX-License-Identifier: MIT +# +#============================ end_copyright_notice ============================= + set(PLUGIN_SOURCES Plugin.cpp ) diff --git a/GenXIntrinsics/test/Plugin/Plugin.cpp b/GenXIntrinsics/test/Plugin/Plugin.cpp index 8ef522d4..522d2ba6 100644 --- a/GenXIntrinsics/test/Plugin/Plugin.cpp +++ b/GenXIntrinsics/test/Plugin/Plugin.cpp @@ -1,27 +1,10 @@ -/*===================== begin_copyright_notice ================================== +/*========================== begin_copyright_notice ============================ - Copyright (c) 2020, Intel Corporation +Copyright (C) 2020-2021 Intel Corporation +SPDX-License-Identifier: MIT - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ - +============================= end_copyright_notice ===========================*/ #include "llvm/GenXIntrinsics/GenXSimdCFLowering.h" #include "llvm/GenXIntrinsics/GenXSPIRVReaderAdaptor.h" diff --git a/GenXIntrinsics/test/SimdCFLowering/bitcast_between_wrrs.ll b/GenXIntrinsics/test/SimdCFLowering/bitcast_between_wrrs.ll index 862e3589..109ca229 100644 --- a/GenXIntrinsics/test/SimdCFLowering/bitcast_between_wrrs.ll +++ b/GenXIntrinsics/test/SimdCFLowering/bitcast_between_wrrs.ll @@ -1,4 +1,12 @@ -; XFAIL: llvm13 +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; XFAIL: llvm13, llvm14, llvm15 ; RUN: opt -S -cmsimdcflowering < %s | FileCheck %s @Rcp_T2 = internal global <64 x double> undef diff --git a/GenXIntrinsics/test/SimdCFLowering/predicate_masked_gather.ll b/GenXIntrinsics/test/SimdCFLowering/predicate_masked_gather.ll index a192f52a..67f4cb43 100644 --- a/GenXIntrinsics/test/SimdCFLowering/predicate_masked_gather.ll +++ b/GenXIntrinsics/test/SimdCFLowering/predicate_masked_gather.ll @@ -1,4 +1,12 @@ -; XFAIL: llvm13 +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; XFAIL: llvm13, llvm14, llvm15 ; RUN: opt -S -cmsimdcflowering < %s | FileCheck %s ; CHECK: @EM = internal global <32 x i1> diff --git a/GenXIntrinsics/test/SimdCFLowering/replicate_mask.ll b/GenXIntrinsics/test/SimdCFLowering/replicate_mask.ll index f976d0cd..594ca3ec 100644 --- a/GenXIntrinsics/test/SimdCFLowering/replicate_mask.ll +++ b/GenXIntrinsics/test/SimdCFLowering/replicate_mask.ll @@ -1,4 +1,12 @@ -; XFAIL: llvm13 +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; XFAIL: llvm13, llvm14, llvm15 ; RUN: opt -S -cmsimdcflowering < %s | FileCheck %s @g1 = internal global <64 x i32> undef diff --git a/GenXIntrinsics/test/SimdCFLowering/replicate_mask_masked_gather4.ll b/GenXIntrinsics/test/SimdCFLowering/replicate_mask_masked_gather4.ll index a4f47591..86eabdfa 100644 --- a/GenXIntrinsics/test/SimdCFLowering/replicate_mask_masked_gather4.ll +++ b/GenXIntrinsics/test/SimdCFLowering/replicate_mask_masked_gather4.ll @@ -1,4 +1,12 @@ -; XFAIL: llvm13 +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; XFAIL: llvm13, llvm14, llvm15 ; RUN: opt -S -cmsimdcflowering < %s | FileCheck %s @Rcp_T2 = internal global <64 x i32> undef diff --git a/GenXIntrinsics/test/SimdCFLowering/update_mask_masked_gather4.ll b/GenXIntrinsics/test/SimdCFLowering/update_mask_masked_gather4.ll index 3a19baf4..9e5d2ac1 100644 --- a/GenXIntrinsics/test/SimdCFLowering/update_mask_masked_gather4.ll +++ b/GenXIntrinsics/test/SimdCFLowering/update_mask_masked_gather4.ll @@ -1,4 +1,12 @@ -; XFAIL: llvm13 +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; XFAIL: llvm13, llvm14, llvm15 ; RUN: opt -S -cmsimdcflowering < %s | FileCheck %s @g1 = internal global <64 x i32> undef diff --git a/GenXIntrinsics/test/lit.cfg.py b/GenXIntrinsics/test/lit.cfg.py index 3a26cfa6..2e3a4eae 100644 --- a/GenXIntrinsics/test/lit.cfg.py +++ b/GenXIntrinsics/test/lit.cfg.py @@ -1,3 +1,11 @@ +# ========================== begin_copyright_notice ============================ +# +# Copyright (C) 2020-2021 Intel Corporation +# +# SPDX-License-Identifier: MIT +# +# =========================== end_copyright_notice ============================= + # -*- Python -*- import lit.formats diff --git a/GenXIntrinsics/test/lit.site.cfg.py.in b/GenXIntrinsics/test/lit.site.cfg.py.in index 35b4aa42..588e895d 100644 --- a/GenXIntrinsics/test/lit.site.cfg.py.in +++ b/GenXIntrinsics/test/lit.site.cfg.py.in @@ -1,3 +1,11 @@ +# ========================== begin_copyright_notice ============================ +# +# Copyright (C) 2020-2021 Intel Corporation +# +# SPDX-License-Identifier: MIT +# +# =========================== end_copyright_notice ============================= + @LIT_SITE_CFG_IN_HEADER@ import sys diff --git a/GenXIntrinsics/unittests/CMakeLists.txt b/GenXIntrinsics/unittests/CMakeLists.txt index b011d537..46393500 100644 --- a/GenXIntrinsics/unittests/CMakeLists.txt +++ b/GenXIntrinsics/unittests/CMakeLists.txt @@ -1,3 +1,11 @@ +#=========================== begin_copyright_notice ============================ +# +# Copyright (C) 2019-2021 Intel Corporation +# +# SPDX-License-Identifier: MIT +# +#============================ end_copyright_notice ============================= + add_custom_target(GenXIntrinsicsUnitTests) set_target_properties(GenXIntrinsicsUnitTests PROPERTIES FOLDER "GenXIntrinsicsTests") diff --git a/GenXIntrinsics/unittests/GenXIntrinsics/CMakeLists.txt b/GenXIntrinsics/unittests/GenXIntrinsics/CMakeLists.txt index e44c3b4e..8befa3c5 100644 --- a/GenXIntrinsics/unittests/GenXIntrinsics/CMakeLists.txt +++ b/GenXIntrinsics/unittests/GenXIntrinsics/CMakeLists.txt @@ -1,3 +1,11 @@ +#=========================== begin_copyright_notice ============================ +# +# Copyright (C) 2019-2021 Intel Corporation +# +# SPDX-License-Identifier: MIT +# +#============================ end_copyright_notice ============================= + set(LLVM_LINK_COMPONENTS Core Support diff --git a/GenXIntrinsics/unittests/GenXIntrinsics/GenXIntrinsicsTest.cpp b/GenXIntrinsics/unittests/GenXIntrinsics/GenXIntrinsicsTest.cpp index 8c8980ee..01fef597 100644 --- a/GenXIntrinsics/unittests/GenXIntrinsics/GenXIntrinsicsTest.cpp +++ b/GenXIntrinsics/unittests/GenXIntrinsics/GenXIntrinsicsTest.cpp @@ -1,27 +1,10 @@ -/*===================== begin_copyright_notice ================================== +/*========================== begin_copyright_notice ============================ - Copyright (c) 2020, Intel Corporation +Copyright (C) 2019-2021 Intel Corporation +SPDX-License-Identifier: MIT - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ - +============================= end_copyright_notice ===========================*/ #include "llvm/ADT/StringRef.h" #include "llvm/GenXIntrinsics/GenXIntrinsics.h" diff --git a/License.md b/License.md deleted file mode 100644 index 4e66ab4c..00000000 --- a/License.md +++ /dev/null @@ -1,21 +0,0 @@ -MIT License - -Copyright (c) 2020 Intel Corporation - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in all -copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -SOFTWARE. diff --git a/Readme.md b/Readme.md index 9289b331..cc385d7c 100644 --- a/Readme.md +++ b/Readme.md @@ -1,3 +1,11 @@ + + # VC Intrinsics ## Introduction @@ -45,7 +53,7 @@ To build documentation: ## Building VC Intrinsics can be built in two major modes: in-tree and -external. All major LLVM versions starting from LLVM 7 are supported. +external. All major LLVM versions starting from LLVM 8 are supported. LLVM ToT can be used too, but there is no guarantee that it will always work (because of sudden breaking changes in LLVM C++