0005-RISCV-Add-basic-RISCV-InstrFormats-InstrInfo-Registe.patch

From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Alex Bradbury <asb@lowrisc.org>
Subject: [RISCV] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.td

For now, only add instruction definitions for basic ALU operations. Our
initial target is a working MC layer rather than codegen, so appropriate
SelectionDAG patterns will come later.

Differential Revision: https://reviews.llvm.org/D23561
Upstream commit: https://reviews.llvm.org/rL285769

NOTE: This patch has been updated since being committed upstream.
---
 lib/Target/RISCV/CMakeLists.txt       |   7 ++
 lib/Target/RISCV/RISCV.td             |  45 +++++++++
 lib/Target/RISCV/RISCVInstrFormats.td | 185 ++++++++++++++++++++++++++++++++++
 lib/Target/RISCV/RISCVInstrInfo.td    |  57 +++++++++++
 lib/Target/RISCV/RISCVRegisterInfo.td |  69 +++++++++++++
 5 files changed, 363 insertions(+)
 create mode 100644 lib/Target/RISCV/RISCV.td
 create mode 100644 lib/Target/RISCV/RISCVInstrFormats.td
 create mode 100644 lib/Target/RISCV/RISCVInstrInfo.td
 create mode 100644 lib/Target/RISCV/RISCVRegisterInfo.td

diff --git a/lib/Target/RISCV/CMakeLists.txt b/lib/Target/RISCV/CMakeLists.txt
index 1de4d3b5d0b..5a98f9f719d 100644
--- a/lib/Target/RISCV/CMakeLists.txt
+++ b/lib/Target/RISCV/CMakeLists.txt
@@ -1,3 +1,10 @@
+set(LLVM_TARGET_DEFINITIONS RISCV.td)
+
+tablegen(LLVM RISCVGenRegisterInfo.inc -gen-register-info)
+tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info)
+
+add_public_tablegen_target(RISCVCommonTableGen)
+
 add_llvm_target(RISCVCodeGen
   RISCVTargetMachine.cpp
   )
diff --git a/lib/Target/RISCV/RISCV.td b/lib/Target/RISCV/RISCV.td
new file mode 100644
index 00000000000..2d9a52f18bc
--- /dev/null
+++ b/lib/Target/RISCV/RISCV.td
@@ -0,0 +1,45 @@
+//===-- RISCV.td - Describe the RISCV Target Machine -------*- tablegen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+include "llvm/Target/Target.td"
+
+//===----------------------------------------------------------------------===//
+// RISC-V subtarget features and instruction predicates.
+//===----------------------------------------------------------------------===//
+
+def Feature64Bit : SubtargetFeature<"64bit", "HasRV64", "true",
+                                    "Implements RV64">;
+
+def RV64         : HwMode<"+64bit">;
+def RV32         : HwMode<"-64bit">;
+
+//===----------------------------------------------------------------------===//
+// Register file, instruction descriptions.
+//===----------------------------------------------------------------------===//
+
+include "RISCVRegisterInfo.td"
+include "RISCVInstrInfo.td"
+
+def RISCVInstrInfo : InstrInfo;
+
+//===----------------------------------------------------------------------===//
+// RISC-V processors supported.
+//===----------------------------------------------------------------------===//
+
+def : ProcessorModel<"generic-rv32", NoSchedModel, []>;
+
+def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>;
+
+//===----------------------------------------------------------------------===//
+// Define the RISC-V target.
+//===----------------------------------------------------------------------===//
+
+def RISCV : Target {
+  let InstructionSet = RISCVInstrInfo;
+}
diff --git a/lib/Target/RISCV/RISCVInstrFormats.td b/lib/Target/RISCV/RISCVInstrFormats.td
new file mode 100644
index 00000000000..59ddc703c1d
--- /dev/null
+++ b/lib/Target/RISCV/RISCVInstrFormats.td
@@ -0,0 +1,185 @@
+//===-- RISCVInstrFormats.td - RISCV Instruction Formats ---*- tablegen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+//
+//  These instruction format definitions are structured to match the
+//  description in the RISC-V User-Level ISA specification as closely as
+//  possible. For instance, the specification describes instructions with the
+//  MSB (31st bit) on the left and the LSB (0th bit) on the right. This is
+//  reflected in the order of parameters to each instruction class.
+//
+//  One area of divergence is in the description of immediates. The
+//  specification describes immediate encoding in terms of bit-slicing
+//  operations on the logical value represented. The immediate argument to
+//  these instruction formats instead represents the bit sequence that will be
+//  inserted into the instruction. e.g. although JAL's immediate is logically
+//  a 21-bit value (where the LSB is always zero), we describe it as an imm20
+//  to match how it is encoded.
+//
+//===----------------------------------------------------------------------===//
+
+// The following opcode names and match those given in Table 19.1 in the
+// RISC-V User-level ISA specification ("RISC-V base opcode map").
+class RISCVOpcode<bits<7> val> {
+  bits<7> Value = val;
+}
+def OPC_LOAD      : RISCVOpcode<0b0000011>;
+def OPC_LOAD_FP   : RISCVOpcode<0b0000111>;
+def OPC_MISC_MEM  : RISCVOpcode<0b0001111>;
+def OPC_OP_IMM    : RISCVOpcode<0b0010011>;
+def OPC_AUIPC     : RISCVOpcode<0b0010111>;
+def OPC_OP_IMM_32 : RISCVOpcode<0b0011011>;
+def OPC_STORE     : RISCVOpcode<0b0100011>;
+def OPC_STORE_FP  : RISCVOpcode<0b0100111>;
+def OPC_AMO       : RISCVOpcode<0b0101111>;
+def OPC_OP        : RISCVOpcode<0b0110011>;
+def OPC_LUI       : RISCVOpcode<0b0110111>;
+def OPC_OP_32     : RISCVOpcode<0b0111011>;
+def OPC_MADD      : RISCVOpcode<0b1000011>;
+def OPC_MSUB      : RISCVOpcode<0b1000111>;
+def OPC_NMSUB     : RISCVOpcode<0b1001011>;
+def OPC_NMADD     : RISCVOpcode<0b1001111>;
+def OPC_OP_FP     : RISCVOpcode<0b1010011>;
+def OPC_BRANCH    : RISCVOpcode<0b1100011>;
+def OPC_JALR      : RISCVOpcode<0b1100111>;
+def OPC_JAL       : RISCVOpcode<0b1101111>;
+def OPC_SYSTEM    : RISCVOpcode<0b1110011>;
+
+class RVInst<dag outs, dag ins, string opcodestr, string argstr,
+             list<dag> pattern>
+    : Instruction {
+  field bits<32> Inst;
+  let Size = 4;
+
+  bits<7> Opcode = 0;
+
+  let Inst{6-0} = Opcode;
+
+  let Namespace = "RISCV";
+
+  dag OutOperandList = outs;
+  dag InOperandList = ins;
+  let AsmString = opcodestr # "\t" # argstr;
+  let Pattern = pattern;
+}
+
+// Pseudo instructions
+class Pseudo<dag outs, dag ins, list<dag> pattern>
+    : RVInst<outs, ins, "", "", pattern> {
+  let isPseudo = 1;
+  let isCodeGenOnly = 1;
+}
+
+// Instruction formats are listed in the order they appear in the RISC-V
+// instruction set manual (R, I, S, B, U, J) with sub-formats (e.g. RVInstR4,
+// RVInstRAtomic) sorted alphabetically.
+
+class RVInstR<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode, dag outs,
+              dag ins, string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, []> {
+  bits<5> rs2;
+  bits<5> rs1;
+  bits<5> rd;
+
+  let Inst{31-25} = funct7;
+  let Inst{24-20} = rs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rd;
+  let Opcode = opcode.Value;
+}
+
+class RVInstI<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
+              string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, []> {
+  bits<12> imm12;
+  bits<5> rs1;
+  bits<5> rd;
+
+  let Inst{31-20} = imm12;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rd;
+  let Opcode = opcode.Value;
+}
+
+class RVInstIShift<bit arithshift, bits<3> funct3, RISCVOpcode opcode,
+                   dag outs, dag ins, string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, []> {
+  bits<5> shamt;
+  bits<5> rs1;
+  bits<5> rd;
+
+  let Inst{31} = 0;
+  let Inst{30} = arithshift;
+  let Inst{29-25} = 0;
+  let Inst{24-20} = shamt;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rd;
+  let Opcode = opcode.Value;
+}
+
+class RVInstS<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
+              string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, []> {
+  bits<12> imm12;
+  bits<5> rs2;
+  bits<5> rs1;
+
+  let Inst{31-25} = imm12{11-5};
+  let Inst{24-20} = rs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = imm12{4-0};
+  let Opcode = opcode.Value;
+}
+
+class RVInstB<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
+              string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, []> {
+  bits<12> imm12;
+  bits<5> rs2;
+  bits<5> rs1;
+
+  let Inst{31} = imm12{11};
+  let Inst{30-25} = imm12{9-4};
+  let Inst{24-20} = rs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-8} = imm12{3-0};
+  let Inst{7} = imm12{10};
+  let Opcode = opcode.Value;
+}
+
+class RVInstU<RISCVOpcode opcode, dag outs, dag ins, string opcodestr,
+              string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, []> {
+  bits<20> imm20;
+  bits<5> rd;
+
+  let Inst{31-12} = imm20;
+  let Inst{11-7} = rd;
+  let Opcode = opcode.Value;
+}
+
+class RVInstJ<RISCVOpcode opcode, dag outs, dag ins, string opcodestr,
+              string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, []> {
+  bits<20> imm20;
+  bits<5> rd;
+
+  let Inst{31} = imm20{19};
+  let Inst{30-21} = imm20{9-0};
+  let Inst{20} = imm20{10};
+  let Inst{19-12} = imm20{18-11};
+  let Inst{11-7} = rd;
+  let Opcode = opcode.Value;
+}
diff --git a/lib/Target/RISCV/RISCVInstrInfo.td b/lib/Target/RISCV/RISCVInstrInfo.td
new file mode 100644
index 00000000000..9ef2b7460ca
--- /dev/null
+++ b/lib/Target/RISCV/RISCVInstrInfo.td
@@ -0,0 +1,57 @@
+//===-- RISCVInstrInfo.td - Target Description for RISCV ---*- tablegen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the RISC-V instructions in TableGen format.
+//
+//===----------------------------------------------------------------------===//
+
+include "RISCVInstrFormats.td"
+
+//===----------------------------------------------------------------------===//
+// Operand and SDNode transformation definitions.
+//===----------------------------------------------------------------------===//
+
+def simm12 : Operand<XLenVT>;
+
+//===----------------------------------------------------------------------===//
+// Instruction Class Templates
+//===----------------------------------------------------------------------===//
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class ALU_ri<bits<3> funct3, string opcodestr>
+    : RVInstI<funct3, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12),
+              opcodestr, "$rd, $rs1, $imm12">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class ALU_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_OP, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
+              opcodestr, "$rd, $rs1, $rs2">;
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+def ADDI  : ALU_ri<0b000, "addi">;
+def SLTI  : ALU_ri<0b010, "slti">;
+def SLTIU : ALU_ri<0b011, "sltiu">;
+def XORI  : ALU_ri<0b100, "xori">;
+def ORI   : ALU_ri<0b110, "ori">;
+def ANDI  : ALU_ri<0b111, "andi">;
+
+def ADD  : ALU_rr<0b0000000, 0b000, "add">;
+def SUB  : ALU_rr<0b0100000, 0b000, "sub">;
+def SLL  : ALU_rr<0b0000000, 0b001, "sll">;
+def SLT  : ALU_rr<0b0000000, 0b010, "slt">;
+def SLTU : ALU_rr<0b0000000, 0b011, "sltu">;
+def XOR  : ALU_rr<0b0000000, 0b100, "xor">;
+def SRL  : ALU_rr<0b0000000, 0b101, "srl">;
+def SRA  : ALU_rr<0b0100000, 0b101, "sra">;
+def OR   : ALU_rr<0b0000000, 0b110, "or">;
+def AND  : ALU_rr<0b0000000, 0b111, "and">;
+
diff --git a/lib/Target/RISCV/RISCVRegisterInfo.td b/lib/Target/RISCV/RISCVRegisterInfo.td
new file mode 100644
index 00000000000..a5484130dfc
--- /dev/null
+++ b/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -0,0 +1,69 @@
+//===-- RISCVRegisterInfo.td - RISC-V Register defs --------*- tablegen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+//  Declarations that describe the RISC-V register files
+//===----------------------------------------------------------------------===//
+
+let Namespace = "RISCV" in {
+class RISCVReg<bits<5> Enc, string n, list<string> alt = []> : Register<n> {
+  let HWEncoding{4-0} = Enc;
+  let AltNames = alt;
+}
+def ABIRegAltName : RegAltNameIndex;
+} // Namespace = "RISCV"
+
+// Integer registers
+let RegAltNameIndices = [ABIRegAltName] in {
+  def X0  : RISCVReg<0, "x0", ["zero"]>, DwarfRegNum<[0]>;
+  def X1  : RISCVReg<1, "x1", ["ra"]>, DwarfRegNum<[1]>;
+  def X2  : RISCVReg<2, "x2", ["sp"]>, DwarfRegNum<[2]>;
+  def X3  : RISCVReg<3, "x3", ["gp"]>, DwarfRegNum<[3]>;
+  def X4  : RISCVReg<4, "x4", ["tp"]>, DwarfRegNum<[4]>;
+  def X5  : RISCVReg<5, "x5", ["t0"]>, DwarfRegNum<[5]>;
+  def X6  : RISCVReg<6, "x6", ["t1"]>, DwarfRegNum<[6]>;
+  def X7  : RISCVReg<7, "x7", ["t2"]>, DwarfRegNum<[7]>;
+  def X8  : RISCVReg<8, "x8", ["s0"]>, DwarfRegNum<[8]>;
+  def X9  : RISCVReg<9, "x9", ["s1"]>, DwarfRegNum<[9]>;
+  def X10 : RISCVReg<10,"x10", ["a0"]>, DwarfRegNum<[10]>;
+  def X11 : RISCVReg<11,"x11", ["a1"]>, DwarfRegNum<[11]>;
+  def X12 : RISCVReg<12,"x12", ["a2"]>, DwarfRegNum<[12]>;
+  def X13 : RISCVReg<13,"x13", ["a3"]>, DwarfRegNum<[13]>;
+  def X14 : RISCVReg<14,"x14", ["a4"]>, DwarfRegNum<[14]>;
+  def X15 : RISCVReg<15,"x15", ["a5"]>, DwarfRegNum<[15]>;
+  def X16 : RISCVReg<16,"x16", ["a6"]>, DwarfRegNum<[16]>;
+  def X17 : RISCVReg<17,"x17", ["a7"]>, DwarfRegNum<[17]>;
+  def X18 : RISCVReg<18,"x18", ["s2"]>, DwarfRegNum<[18]>;
+  def X19 : RISCVReg<19,"x19", ["s3"]>, DwarfRegNum<[19]>;
+  def X20 : RISCVReg<20,"x20", ["s4"]>, DwarfRegNum<[20]>;
+  def X21 : RISCVReg<21,"x21", ["s5"]>, DwarfRegNum<[21]>;
+  def X22 : RISCVReg<22,"x22", ["s6"]>, DwarfRegNum<[22]>;
+  def X23 : RISCVReg<23,"x23", ["s7"]>, DwarfRegNum<[23]>;
+  def X24 : RISCVReg<24,"x24", ["s8"]>, DwarfRegNum<[24]>;
+  def X25 : RISCVReg<25,"x25", ["s9"]>, DwarfRegNum<[25]>;
+  def X26 : RISCVReg<26,"x26", ["s10"]>, DwarfRegNum<[26]>;
+  def X27 : RISCVReg<27,"x27", ["s11"]>, DwarfRegNum<[27]>;
+  def X28 : RISCVReg<28,"x28", ["t3"]>, DwarfRegNum<[28]>;
+  def X29 : RISCVReg<29,"x29", ["t4"]>, DwarfRegNum<[29]>;
+  def X30 : RISCVReg<30,"x30", ["t5"]>, DwarfRegNum<[30]>;
+  def X31 : RISCVReg<31,"x31", ["t6"]>, DwarfRegNum<[31]>;
+}
+
+def XLenVT : ValueTypeByHwMode<[RV32, RV64, DefaultMode],
+                               [i32,  i64,  i32]>;
+
+// TODO: once codegen is implemented, registers should be listed in an order
+// reflecting the preferred register allocation sequence.
+def GPR : RegisterClass< "RISCV", [XLenVT], 32, (add
+    (sequence "X%u", 0, 31)
+  )> {
+  let RegInfos = RegInfoByHwMode<
+      [RV32,              RV64,              DefaultMode],
+      [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>;
+}
-- 
2.16.2