diff --git a/core/axi_shim.sv b/core/axi_shim.sv index c4d93bd9e2..19fc63d6ac 100644 --- a/core/axi_shim.sv +++ b/core/axi_shim.sv @@ -114,7 +114,7 @@ module axi_shim #( // tx counter assign wr_cnt_done = (wr_cnt_q == wr_blen_i); - assign wr_cnt_d = (wr_cnt_clr) ? '0 : (wr_cnt_en) ? wr_cnt_q + 1 : wr_cnt_q; + assign wr_cnt_d = (wr_cnt_clr) ? '0 : (wr_cnt_en && CVA6Cfg.AxiBurstWriteEn) ? wr_cnt_q + 1 : wr_cnt_q; always_comb begin : p_axi_write_fsm // default @@ -149,7 +149,7 @@ module axi_shim #( default: wr_state_d = IDLE; endcase // its a request for the whole cache line - end else begin + end else if(CVA6Cfg.AxiBurstWriteEn) begin wr_cnt_en = axi_resp_i.w_ready; case ({ @@ -174,52 +174,6 @@ module axi_shim #( end end /////////////////////////////////// - // ~> we need to wait for an aw_ready and there is at least one outstanding write - WAIT_LAST_W_READY_AW_READY: begin - axi_req_o.w_valid = 1'b1; - axi_req_o.aw_valid = 1'b1; - // we got an aw_ready - case ({ - axi_resp_i.aw_ready, axi_resp_i.w_ready - }) - // we got an aw ready - 2'b01: begin - // are there any outstanding transactions? - if (wr_cnt_done) begin - wr_state_d = WAIT_AW_READY_BURST; - wr_cnt_clr = 1'b1; - end else begin - // yes, so reduce the count and stay here - wr_cnt_en = 1'b1; - end - end - 2'b10: wr_state_d = WAIT_LAST_W_READY; - 2'b11: begin - // we are finished - if (wr_cnt_done) begin - wr_state_d = IDLE; - wr_gnt_o = 1'b1; - wr_cnt_clr = 1'b1; - // there are outstanding transactions - end else begin - wr_state_d = WAIT_LAST_W_READY; - wr_cnt_en = 1'b1; - end - end - default: ; - endcase - end - /////////////////////////////////// - // ~> all data has already been sent, we are only waiting for the aw_ready - WAIT_AW_READY_BURST: begin - axi_req_o.aw_valid = 1'b1; - - if (axi_resp_i.aw_ready) begin - wr_state_d = IDLE; - wr_gnt_o = 1'b1; - end - end - /////////////////////////////////// // ~> from write, there is an outstanding write WAIT_LAST_W_READY: begin axi_req_o.w_valid = 1'b1; @@ -231,13 +185,62 @@ module axi_shim #( wr_cnt_clr = 1'b1; wr_gnt_o = 1'b1; end - end else if (axi_resp_i.w_ready) begin + end else if (CVA6Cfg.AxiBurstWriteEn && axi_resp_i.w_ready) begin wr_cnt_en = 1'b1; end end /////////////////////////////////// default: begin - wr_state_d = IDLE; + /////////////////////////////////// + // ~> we need to wait for an aw_ready and there is at least one outstanding write + if(CVA6Cfg.AxiBurstWriteEn) begin + if (wr_state_q == WAIT_LAST_W_READY_AW_READY) begin + axi_req_o.w_valid = 1'b1; + axi_req_o.aw_valid = 1'b1; + // we got an aw_ready + case ({ + axi_resp_i.aw_ready, axi_resp_i.w_ready + }) + // we got an aw ready + 2'b01: begin + // are there any outstanding transactions? + if (wr_cnt_done) begin + wr_state_d = WAIT_AW_READY_BURST; + wr_cnt_clr = 1'b1; + end else begin + // yes, so reduce the count and stay here + wr_cnt_en = 1'b1; + end + end + 2'b10: wr_state_d = WAIT_LAST_W_READY; + 2'b11: begin + // we are finished + if (wr_cnt_done) begin + wr_state_d = IDLE; + wr_gnt_o = 1'b1; + wr_cnt_clr = 1'b1; + // there are outstanding transactions + end else begin + wr_state_d = WAIT_LAST_W_READY; + wr_cnt_en = 1'b1; + end + end + default: ; + endcase + end + /////////////////////////////////// + // ~> all data has already been sent, we are only waiting for the aw_ready + else if (wr_state_q == WAIT_AW_READY_BURST) begin + axi_req_o.aw_valid = 1'b1; + + if (axi_resp_i.aw_ready) begin + wr_state_d = IDLE; + wr_gnt_o = 1'b1; + end + end + end else begin + wr_state_d = IDLE; + end end endcase end diff --git a/core/cva6.sv b/core/cva6.sv index d186515ad0..6d25d6ac67 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -217,7 +217,8 @@ module cva6 CVA6Cfg.CachedRegionLength, CVA6Cfg.MaxOutstandingStores, CVA6Cfg.DebugEn, - NonIdemPotenceEn + NonIdemPotenceEn, + CVA6Cfg.AxiBurstWriteEn }; diff --git a/core/include/config_pkg.sv b/core/include/config_pkg.sv index 5a8d51d331..edad7d68fa 100644 --- a/core/include/config_pkg.sv +++ b/core/include/config_pkg.sv @@ -113,6 +113,7 @@ package config_pkg; int unsigned MaxOutstandingStores; bit DebugEn; bit NonIdemPotenceEn; + bit AxiBurstWriteEn; } cva6_cfg_t; diff --git a/core/include/cv32a60x_config_pkg.sv b/core/include/cv32a60x_config_pkg.sv index 2c11026292..cf2a399875 100644 --- a/core/include/cv32a60x_config_pkg.sv +++ b/core/include/cv32a60x_config_pkg.sv @@ -139,7 +139,8 @@ package cva6_config_pkg; CachedRegionLength: 1024'({64'h40000000}), MaxOutstandingStores: unsigned'(7), DebugEn: bit'(1), - NonIdemPotenceEn: bit'(0) + NonIdemPotenceEn: bit'(0), + AxiBurstWriteEn: bit'(0) }; endpackage diff --git a/core/include/cv32a6_embedded_config_pkg.sv b/core/include/cv32a6_embedded_config_pkg.sv index 8bb019b984..8b9fc355d0 100644 --- a/core/include/cv32a6_embedded_config_pkg.sv +++ b/core/include/cv32a6_embedded_config_pkg.sv @@ -138,7 +138,8 @@ package cva6_config_pkg; CachedRegionLength: 1024'({64'h40000000}), MaxOutstandingStores: unsigned'(7), DebugEn: bit'(0), - NonIdemPotenceEn: bit'(0) + NonIdemPotenceEn: bit'(0), + AxiBurstWriteEn: bit'(0) }; endpackage diff --git a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv index 24febac5a3..ef5816c74c 100644 --- a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv +++ b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv @@ -139,7 +139,8 @@ package cva6_config_pkg; CachedRegionLength: 1024'({64'h40000000}), MaxOutstandingStores: unsigned'(7), DebugEn: bit'(1), - NonIdemPotenceEn: bit'(0) + NonIdemPotenceEn: bit'(0), + AxiBurstWriteEn: bit'(0) }; endpackage diff --git a/core/include/cv32a6_imac_sv0_config_pkg.sv b/core/include/cv32a6_imac_sv0_config_pkg.sv index b389b0093b..248db63ab5 100644 --- a/core/include/cv32a6_imac_sv0_config_pkg.sv +++ b/core/include/cv32a6_imac_sv0_config_pkg.sv @@ -139,6 +139,7 @@ package cva6_config_pkg; CachedRegionLength: 1024'({64'h40000000}), MaxOutstandingStores: unsigned'(7), DebugEn: bit'(1), - NonIdemPotenceEn: bit'(0) + NonIdemPotenceEn: bit'(0), + AxiBurstWriteEn: bit'(0) }; endpackage diff --git a/core/include/cv32a6_imac_sv32_config_pkg.sv b/core/include/cv32a6_imac_sv32_config_pkg.sv index 1b4c593519..1dc6c990c1 100644 --- a/core/include/cv32a6_imac_sv32_config_pkg.sv +++ b/core/include/cv32a6_imac_sv32_config_pkg.sv @@ -139,7 +139,8 @@ package cva6_config_pkg; CachedRegionLength: 1024'({64'h40000000}), MaxOutstandingStores: unsigned'(7), DebugEn: bit'(1), - NonIdemPotenceEn: bit'(0) + NonIdemPotenceEn: bit'(0), + AxiBurstWriteEn: bit'(0) }; endpackage diff --git a/core/include/cv32a6_imafc_sv32_config_pkg.sv b/core/include/cv32a6_imafc_sv32_config_pkg.sv index b6b1609f0d..19a947ad09 100644 --- a/core/include/cv32a6_imafc_sv32_config_pkg.sv +++ b/core/include/cv32a6_imafc_sv32_config_pkg.sv @@ -139,7 +139,8 @@ package cva6_config_pkg; CachedRegionLength: 1024'({64'h40000000}), MaxOutstandingStores: unsigned'(7), DebugEn: bit'(1), - NonIdemPotenceEn: bit'(0) + NonIdemPotenceEn: bit'(0), + AxiBurstWriteEn: bit'(0) }; endpackage diff --git a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv index 88c537e41f..535ee76510 100644 --- a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv +++ b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv @@ -138,7 +138,8 @@ package cva6_config_pkg; CachedRegionLength: 1024'({64'h40000000}), MaxOutstandingStores: unsigned'(7), DebugEn: bit'(1), - NonIdemPotenceEn: bit'(0) + NonIdemPotenceEn: bit'(0), + AxiBurstWriteEn: bit'(0) }; endpackage diff --git a/core/include/cv64a6_imafdc_sv39_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_config_pkg.sv index 542806392a..1ee4e4dfad 100644 --- a/core/include/cv64a6_imafdc_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_config_pkg.sv @@ -139,7 +139,8 @@ package cva6_config_pkg; CachedRegionLength: 1024'({64'h40000000}), MaxOutstandingStores: unsigned'(7), DebugEn: bit'(1), - NonIdemPotenceEn: bit'(0) + NonIdemPotenceEn: bit'(0), + AxiBurstWriteEn: bit'(0) }; endpackage diff --git a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv index d5cf27fdd6..cc0381aba8 100644 --- a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv @@ -145,7 +145,8 @@ package cva6_config_pkg; CachedRegionAddrBase: 1024'({64'h8000_0000}), CachedRegionLength: 1024'({64'h40000000}), DebugEn: bit'(1), - NonIdemPotenceEn: bit'(0) + NonIdemPotenceEn: bit'(0), + AxiBurstWriteEn: bit'(0) }; endpackage diff --git a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv index d1377d30aa..ea7c8affd9 100644 --- a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv @@ -139,7 +139,8 @@ package cva6_config_pkg; CachedRegionLength: 1024'({64'h40000000}), MaxOutstandingStores: unsigned'(7), DebugEn: bit'(1), - NonIdemPotenceEn: bit'(0) + NonIdemPotenceEn: bit'(0), + AxiBurstWriteEn: bit'(0) }; endpackage diff --git a/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv index 3ab7b0eec7..6b3a5eb395 100644 --- a/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv @@ -139,7 +139,8 @@ package cva6_config_pkg; CachedRegionLength: 1024'({64'h40000000}), MaxOutstandingStores: unsigned'(7), DebugEn: bit'(1), - NonIdemPotenceEn: bit'(0) + NonIdemPotenceEn: bit'(0), + AxiBurstWriteEn: bit'(0) }; endpackage diff --git a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv index 0a233c2106..66bc4caefa 100644 --- a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv @@ -138,6 +138,7 @@ package cva6_config_pkg; CachedRegionLength: 1024'({64'h40000000}), MaxOutstandingStores: unsigned'(7), DebugEn: bit'(1), - NonIdemPotenceEn: bit'(0) + NonIdemPotenceEn: bit'(0), + AxiBurstWriteEn: bit'(0) }; endpackage diff --git a/corev_apu/fpga/src/ariane_xilinx.sv b/corev_apu/fpga/src/ariane_xilinx.sv index 46d94974ef..774fe1e93c 100644 --- a/corev_apu/fpga/src/ariane_xilinx.sv +++ b/corev_apu/fpga/src/ariane_xilinx.sv @@ -210,7 +210,8 @@ localparam config_pkg::cva6_cfg_t CVA6Cfg = '{ CachedRegionLength: 1024'({ariane_soc::DRAMLength}), MaxOutstandingStores: unsigned'(7), DebugEn: bit'(1), - NonIdemPotenceEn: bit'(0) + NonIdemPotenceEn: bit'(0), + AxiBurstWriteEn: bit'(0) }; localparam type rvfi_instr_t = logic;