diff --git a/core/alu.sv b/core/alu.sv index 01533b6c0a..05fcabf67c 100644 --- a/core/alu.sv +++ b/core/alu.sv @@ -87,11 +87,11 @@ module alu endcase end unique case (fu_data_i.operation) - SH1ADD: operand_a_bitmanip = fu_data_i.operand_a << 1; - SH2ADD: operand_a_bitmanip = fu_data_i.operand_a << 2; - SH3ADD: operand_a_bitmanip = fu_data_i.operand_a << 3; - CTZ: operand_a_bitmanip = operand_a_rev; - default: ; + SH1ADD: operand_a_bitmanip = fu_data_i.operand_a << 1; + SH2ADD: operand_a_bitmanip = fu_data_i.operand_a << 2; + SH3ADD: operand_a_bitmanip = fu_data_i.operand_a << 3; + CTZ: operand_a_bitmanip = operand_a_rev; + default: ; endcase end end @@ -228,11 +228,33 @@ module alu end if (ariane_pkg::BITMANIP) begin : gen_orcbw_rev8w_results - assign orcbw = {{8{|fu_data_i.operand_a[31:24]}}, {8{|fu_data_i.operand_a[23:16]}}, {8{|fu_data_i.operand_a[15:8]}}, {8{|fu_data_i.operand_a[7:0]}}}; - assign rev8w = {{fu_data_i.operand_a[7:0]}, {fu_data_i.operand_a[15:8]}, {fu_data_i.operand_a[23:16]}, {fu_data_i.operand_a[31:24]}}; + assign orcbw = { + {8{|fu_data_i.operand_a[31:24]}}, + {8{|fu_data_i.operand_a[23:16]}}, + {8{|fu_data_i.operand_a[15:8]}}, + {8{|fu_data_i.operand_a[7:0]}} + }; + assign rev8w = { + {fu_data_i.operand_a[7:0]}, + {fu_data_i.operand_a[15:8]}, + {fu_data_i.operand_a[23:16]}, + {fu_data_i.operand_a[31:24]} + }; if (riscv::IS_XLEN64) begin : gen_64b - assign orcbw_result = {{8{|fu_data_i.operand_a[63:56]}}, {8{|fu_data_i.operand_a[55:48]}}, {8{|fu_data_i.operand_a[47:40]}}, {8{|fu_data_i.operand_a[39:32]}}, orcbw}; - assign rev8w_result = {rev8w , {fu_data_i.operand_a[39:32]}, {fu_data_i.operand_a[47:40]}, {fu_data_i.operand_a[55:48]}, {fu_data_i.operand_a[63:56]}}; + assign orcbw_result = { + {8{|fu_data_i.operand_a[63:56]}}, + {8{|fu_data_i.operand_a[55:48]}}, + {8{|fu_data_i.operand_a[47:40]}}, + {8{|fu_data_i.operand_a[39:32]}}, + orcbw + }; + assign rev8w_result = { + rev8w, + {fu_data_i.operand_a[39:32]}, + {fu_data_i.operand_a[47:40]}, + {fu_data_i.operand_a[55:48]}, + {fu_data_i.operand_a[63:56]} + }; end else begin : gen_32b assign orcbw_result = orcbw; assign rev8w_result = rev8w; @@ -257,11 +279,10 @@ module alu unique case (fu_data_i.operation) // Standard Operations ANDL, ANDN: result_o = fu_data_i.operand_a & operand_b_neg[riscv::XLEN:1]; - ORL, ORN: result_o = fu_data_i.operand_a | operand_b_neg[riscv::XLEN:1]; + ORL, ORN: result_o = fu_data_i.operand_a | operand_b_neg[riscv::XLEN:1]; XORL, XNOR: result_o = fu_data_i.operand_a ^ operand_b_neg[riscv::XLEN:1]; // Adder Operations - ADD, SUB, ADDUW, SH1ADD, SH2ADD, SH3ADD: - result_o = adder_result; + ADD, SUB, ADDUW, SH1ADD, SH2ADD, SH3ADD: result_o = adder_result; // Shift Operations SLL, SRL, SRA: result_o = (riscv::IS_XLEN64) ? shift_result : shift_result32; // Comparison Operations @@ -277,7 +298,8 @@ module alu rorw = ({{riscv::XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} >> fu_data_i.operand_b[4:0]) | ({{riscv::XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} << (riscv::XLEN-32-fu_data_i.operand_b[4:0])); if (riscv::IS_XLEN64) begin unique case (fu_data_i.operation) - CLZW, CTZW: result_o = (lz_tz_wempty) ? 32 : {{riscv::XLEN - 5{1'b0}}, lz_tz_wcount}; // change + CLZW, CTZW: + result_o = (lz_tz_wempty) ? 32 : {{riscv::XLEN - 5{1'b0}}, lz_tz_wcount}; // change ROLW: result_o = {{riscv::XLEN - 32{rolw[31]}}, rolw}; RORW, RORIW: result_o = {{riscv::XLEN - 32{rorw[31]}}, rorw}; default: ; @@ -319,10 +341,8 @@ module alu ROR, RORI: result_o = (riscv::IS_XLEN64) ? ((fu_data_i.operand_a >> fu_data_i.operand_b[5:0]) | (fu_data_i.operand_a << (riscv::XLEN-fu_data_i.operand_b[5:0]))) : ((fu_data_i.operand_a >> fu_data_i.operand_b[4:0]) | (fu_data_i.operand_a << (riscv::XLEN-fu_data_i.operand_b[4:0]))); - ORCB: - result_o = orcbw_result; - REV8: - result_o = rev8w_result; + ORCB: result_o = orcbw_result; + REV8: result_o = rev8w_result; default: ; // default case to suppress unique warning endcase diff --git a/core/axi_shim.sv b/core/axi_shim.sv index 19fc63d6ac..fff40ed3f6 100644 --- a/core/axi_shim.sv +++ b/core/axi_shim.sv @@ -84,36 +84,36 @@ module axi_shim #( logic [AddrIndex-1:0] wr_cnt_d, wr_cnt_q; logic wr_single_req, wr_cnt_done, wr_cnt_clr, wr_cnt_en; - assign wr_single_req = (wr_blen_i == 0); + assign wr_single_req = (wr_blen_i == 0); // address - assign axi_req_o.aw.burst = axi_pkg::BURST_INCR; // Use BURST_INCR for AXI regular transaction - assign axi_req_o.aw.addr = wr_addr_i[CVA6Cfg.AxiAddrWidth-1:0]; - assign axi_req_o.aw.size = wr_size_i; - assign axi_req_o.aw.len = wr_blen_i; - assign axi_req_o.aw.id = wr_id_i; - assign axi_req_o.aw.prot = 3'b0; + assign axi_req_o.aw.burst = axi_pkg::BURST_INCR; // Use BURST_INCR for AXI regular transaction + assign axi_req_o.aw.addr = wr_addr_i[CVA6Cfg.AxiAddrWidth-1:0]; + assign axi_req_o.aw.size = wr_size_i; + assign axi_req_o.aw.len = wr_blen_i; + assign axi_req_o.aw.id = wr_id_i; + assign axi_req_o.aw.prot = 3'b0; assign axi_req_o.aw.region = 4'b0; - assign axi_req_o.aw.lock = wr_lock_i; - assign axi_req_o.aw.cache = axi_pkg::CACHE_MODIFIABLE; - assign axi_req_o.aw.qos = 4'b0; - assign axi_req_o.aw.atop = wr_atop_i; - assign axi_req_o.aw.user = '0; + assign axi_req_o.aw.lock = wr_lock_i; + assign axi_req_o.aw.cache = axi_pkg::CACHE_MODIFIABLE; + assign axi_req_o.aw.qos = 4'b0; + assign axi_req_o.aw.atop = wr_atop_i; + assign axi_req_o.aw.user = '0; // data - assign axi_req_o.w.data = wr_data_i[wr_cnt_q]; - assign axi_req_o.w.user = wr_user_i[wr_cnt_q]; - assign axi_req_o.w.strb = wr_be_i[wr_cnt_q]; - assign axi_req_o.w.last = wr_cnt_done; + assign axi_req_o.w.data = wr_data_i[wr_cnt_q]; + assign axi_req_o.w.user = wr_user_i[wr_cnt_q]; + assign axi_req_o.w.strb = wr_be_i[wr_cnt_q]; + assign axi_req_o.w.last = wr_cnt_done; // write response - assign wr_exokay_o = (axi_resp_i.b.resp == axi_pkg::RESP_EXOKAY); - assign axi_req_o.b_ready = wr_rdy_i; - assign wr_valid_o = axi_resp_i.b_valid; - assign wr_id_o = axi_resp_i.b.id; + assign wr_exokay_o = (axi_resp_i.b.resp == axi_pkg::RESP_EXOKAY); + assign axi_req_o.b_ready = wr_rdy_i; + assign wr_valid_o = axi_resp_i.b_valid; + assign wr_id_o = axi_resp_i.b.id; // tx counter - assign wr_cnt_done = (wr_cnt_q == wr_blen_i); + assign wr_cnt_done = (wr_cnt_q == wr_blen_i); assign wr_cnt_d = (wr_cnt_clr) ? '0 : (wr_cnt_en && CVA6Cfg.AxiBurstWriteEn) ? wr_cnt_q + 1 : wr_cnt_q; always_comb begin : p_axi_write_fsm @@ -149,7 +149,7 @@ module axi_shim #( default: wr_state_d = IDLE; endcase // its a request for the whole cache line - end else if(CVA6Cfg.AxiBurstWriteEn) begin + end else if (CVA6Cfg.AxiBurstWriteEn) begin wr_cnt_en = axi_resp_i.w_ready; case ({ @@ -193,7 +193,7 @@ module axi_shim #( default: begin /////////////////////////////////// // ~> we need to wait for an aw_ready and there is at least one outstanding write - if(CVA6Cfg.AxiBurstWriteEn) begin + if (CVA6Cfg.AxiBurstWriteEn) begin if (wr_state_q == WAIT_LAST_W_READY_AW_READY) begin axi_req_o.w_valid = 1'b1; axi_req_o.aw_valid = 1'b1; @@ -227,12 +227,11 @@ module axi_shim #( end default: ; endcase - end - /////////////////////////////////// - // ~> all data has already been sent, we are only waiting for the aw_ready + end /////////////////////////////////// + // ~> all data has already been sent, we are only waiting for the aw_ready else if (wr_state_q == WAIT_AW_READY_BURST) begin axi_req_o.aw_valid = 1'b1; - + if (axi_resp_i.aw_ready) begin wr_state_d = IDLE; wr_gnt_o = 1'b1; diff --git a/core/cache_subsystem/axi_adapter.sv b/core/cache_subsystem/axi_adapter.sv index f9982759a3..0b8f9eb17f 100644 --- a/core/cache_subsystem/axi_adapter.sv +++ b/core/cache_subsystem/axi_adapter.sv @@ -55,7 +55,11 @@ module axi_adapter #( DATA_WIDTH / CVA6Cfg.AxiDataWidth ) : 1; localparam MAX_OUTSTANDING_AW = CVA6Cfg.MaxOutstandingStores; - localparam MAX_OUTSTANDING_AW_CNT_WIDTH = $clog2(MAX_OUTSTANDING_AW + 1) > 0 ? $clog2(MAX_OUTSTANDING_AW + 1) : 1; + localparam MAX_OUTSTANDING_AW_CNT_WIDTH = $clog2( + MAX_OUTSTANDING_AW + 1 + ) > 0 ? $clog2( + MAX_OUTSTANDING_AW + 1 + ) : 1; typedef logic [MAX_OUTSTANDING_AW_CNT_WIDTH-1:0] outstanding_aw_cnt_t; @@ -369,8 +373,8 @@ module axi_adapter #( end end end - // if the request was not an atomic we can possibly issue - // other requests while waiting for the response + // if the request was not an atomic we can possibly issue + // other requests while waiting for the response end else begin if ((amo_q == ariane_pkg::AMO_NONE) && (outstanding_aw_cnt_q != MAX_OUTSTANDING_AW)) begin state_d = IDLE; diff --git a/core/cache_subsystem/cva6_icache.sv b/core/cache_subsystem/cva6_icache.sv index e8819bfe09..37dd8d1dff 100644 --- a/core/cache_subsystem/cva6_icache.sv +++ b/core/cache_subsystem/cva6_icache.sv @@ -176,7 +176,9 @@ module cva6_icache // main control logic /////////////////////////////////////////////////////// logic addr_ni; - assign addr_ni = config_pkg::is_inside_nonidempotent_regions(CVA6Cfg, {{64-riscv::PLEN{1'b0}}, areq_i.fetch_paddr}); + assign addr_ni = config_pkg::is_inside_nonidempotent_regions( + CVA6Cfg, {{64 - riscv::PLEN{1'b0}}, areq_i.fetch_paddr} + ); always_comb begin : p_fsm // default assignment state_d = state_q; diff --git a/core/cache_subsystem/miss_handler.sv b/core/cache_subsystem/miss_handler.sv index 228b3e37ee..9c69378f66 100644 --- a/core/cache_subsystem/miss_handler.sv +++ b/core/cache_subsystem/miss_handler.sv @@ -689,7 +689,11 @@ module axi_adapter_arbiter #( input rsp_t rsp_i ); - localparam MAX_OUTSTANDING_CNT_WIDTH = $clog2(MAX_OUTSTANDING_REQ + 1) > 0 ? $clog2(MAX_OUTSTANDING_REQ + 1) : 1; + localparam MAX_OUTSTANDING_CNT_WIDTH = $clog2( + MAX_OUTSTANDING_REQ + 1 + ) > 0 ? $clog2( + MAX_OUTSTANDING_REQ + 1 + ) : 1; typedef logic [MAX_OUTSTANDING_CNT_WIDTH-1:0] outstanding_cnt_t; diff --git a/core/cache_subsystem/wt_axi_adapter.sv b/core/cache_subsystem/wt_axi_adapter.sv index f3eb698989..af65b49911 100644 --- a/core/cache_subsystem/wt_axi_adapter.sv +++ b/core/cache_subsystem/wt_axi_adapter.sv @@ -161,16 +161,16 @@ module wt_axi_adapter // arbiter mux if (arb_idx) begin // Cast to AXI address width - axi_rd_addr = {{CVA6Cfg.AxiAddrWidth-riscv::PLEN{1'b0}}, dcache_data.paddr}; + axi_rd_addr = {{CVA6Cfg.AxiAddrWidth - riscv::PLEN{1'b0}}, dcache_data.paddr}; // If dcache_data.size MSB is set, we want to read as much as possible - axi_rd_size = dcache_data.size[2] ? MaxNumWords[2:0] : dcache_data.size; + axi_rd_size = dcache_data.size[2] ? MaxNumWords[2:0] : dcache_data.size; if (dcache_data.size[2]) begin axi_rd_blen = AxiRdBlenDcache[$clog2(AxiNumWords)-1:0]; end end else begin // Cast to AXI address width - axi_rd_addr = {{CVA6Cfg.AxiAddrWidth-riscv::PLEN{1'b0}}, icache_data.paddr}; - axi_rd_size = MaxNumWords[2:0]; // always request max number of words in case of ifill + axi_rd_addr = {{CVA6Cfg.AxiAddrWidth - riscv::PLEN{1'b0}}, icache_data.paddr}; + axi_rd_size = MaxNumWords[2:0]; // always request max number of words in case of ifill if (!icache_data.nc) begin axi_rd_blen = AxiRdBlenIcache[$clog2(AxiNumWords)-1:0]; end @@ -210,58 +210,89 @@ module wt_axi_adapter end ////////////////////////////////////// wt_cache_pkg::DCACHE_ATOMIC_REQ: begin - if(CVA6Cfg.RVA) begin - // default - // push back an invalidation here. - // since we only keep one read tx in flight, and since - // the dcache drains all writes/reads before executing - // an atomic, this is safe. - invalidate = arb_gnt; - axi_wr_req = 1'b1; - axi_wr_be = '0; - unique case(dcache_data.size[1:0]) - 2'b00: axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0]] = '1; // byte - 2'b01: axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0] +:2 ] = '1; // hword - 2'b10: axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0] +:4 ] = '1; // word - default: axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0] +:8 ] = '1; // dword - endcase - amo_gen_r_d = 1'b1; - // need to use a separate ID here, so concat an additional bit - axi_wr_id_in[1] = 1'b1; - - unique case (dcache_data.amo_op) - AMO_LR: begin - axi_rd_lock = 1'b1; - axi_rd_req = 1'b1; - axi_rd_id_in[1] = 1'b1; - // tie to zero in this special case - axi_wr_req = 1'b0; - axi_wr_be = '0; - end - AMO_SC: begin - axi_wr_lock = 1'b1; - amo_gen_r_d = 1'b0; - // needed to properly encode success. store the result at offset within the returned - // AXI data word aligned with the requested word size. - amo_off_d = dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0] & ~((1 << dcache_data.size[1:0]) - 1); - end - // RISC-V atops have a load semantic - AMO_SWAP: axi_wr_atop = axi_pkg::ATOP_ATOMICSWAP; - AMO_ADD: axi_wr_atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_ADD}; - AMO_AND: begin - // in this case we need to invert the data to get a "CLR" - axi_wr_data[0] = ~{(CVA6Cfg.AxiDataWidth/riscv::XLEN){dcache_data.data}}; - axi_wr_user = ~{(CVA6Cfg.AxiDataWidth/riscv::XLEN){dcache_data.user}}; - axi_wr_atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_CLR}; - end - AMO_OR: axi_wr_atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_SET}; - AMO_XOR: axi_wr_atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_EOR}; - AMO_MAX: axi_wr_atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_SMAX}; - AMO_MAXU: axi_wr_atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_UMAX}; - AMO_MIN: axi_wr_atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_SMIN}; - AMO_MINU: axi_wr_atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_UMIN}; - default: ; // Do nothing - endcase + if (CVA6Cfg.RVA) begin + // default + // push back an invalidation here. + // since we only keep one read tx in flight, and since + // the dcache drains all writes/reads before executing + // an atomic, this is safe. + invalidate = arb_gnt; + axi_wr_req = 1'b1; + axi_wr_be = '0; + unique case (dcache_data.size[1:0]) + 2'b00: + axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0]] = '1; // byte + 2'b01: + axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0]+:2] = + '1; // hword + 2'b10: + axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0]+:4] = + '1; // word + default: + axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0]+:8] = + '1; // dword + endcase + amo_gen_r_d = 1'b1; + // need to use a separate ID here, so concat an additional bit + axi_wr_id_in[1] = 1'b1; + + unique case (dcache_data.amo_op) + AMO_LR: begin + axi_rd_lock = 1'b1; + axi_rd_req = 1'b1; + axi_rd_id_in[1] = 1'b1; + // tie to zero in this special case + axi_wr_req = 1'b0; + axi_wr_be = '0; + end + AMO_SC: begin + axi_wr_lock = 1'b1; + amo_gen_r_d = 1'b0; + // needed to properly encode success. store the result at offset within the returned + // AXI data word aligned with the requested word size. + amo_off_d = dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)- + 1:0] & ~((1 << dcache_data.size[1:0]) - 1); + end + // RISC-V atops have a load semantic + AMO_SWAP: axi_wr_atop = axi_pkg::ATOP_ATOMICSWAP; + AMO_ADD: + axi_wr_atop = { + axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_ADD + }; + AMO_AND: begin + // in this case we need to invert the data to get a "CLR" + axi_wr_data[0] = ~{(CVA6Cfg.AxiDataWidth / riscv::XLEN) {dcache_data.data}}; + axi_wr_user = ~{(CVA6Cfg.AxiDataWidth / riscv::XLEN) {dcache_data.user}}; + axi_wr_atop = { + axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_CLR + }; + end + AMO_OR: + axi_wr_atop = { + axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_SET + }; + AMO_XOR: + axi_wr_atop = { + axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_EOR + }; + AMO_MAX: + axi_wr_atop = { + axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_SMAX + }; + AMO_MAXU: + axi_wr_atop = { + axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_UMAX + }; + AMO_MIN: + axi_wr_atop = { + axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_SMIN + }; + AMO_MINU: + axi_wr_atop = { + axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_UMIN + }; + default: ; // Do nothing + endcase end end default: ; // Do nothing @@ -520,8 +551,8 @@ module wt_axi_adapter // write-through cache architecture, which is aligned with the openpiton // cache subsystem. end else if (CVA6Cfg.RVA && invalidate) begin - dcache_rtrn_type_d = wt_cache_pkg::DCACHE_INV_REQ; - dcache_rtrn_vld_d = 1'b1; + dcache_rtrn_type_d = wt_cache_pkg::DCACHE_INV_REQ; + dcache_rtrn_vld_d = 1'b1; dcache_rtrn_inv_d.all = 1'b1; dcache_rtrn_inv_d.idx = dcache_data.paddr[ariane_pkg::DCACHE_INDEX_WIDTH-1:0]; diff --git a/core/cache_subsystem/wt_dcache.sv b/core/cache_subsystem/wt_dcache.sv index fd4aa62b80..af672d888e 100644 --- a/core/cache_subsystem/wt_dcache.sv +++ b/core/cache_subsystem/wt_dcache.sv @@ -171,7 +171,7 @@ module wt_dcache // 0 is used by MMU, 1 by READ access requests for (genvar k = 0; k < NumPorts - 1; k++) begin : gen_rd_ports // set these to high prio ports - if ((k==0 && MMU_PRESENT) || (k==1) || (k==2 && CVA6Cfg.EnableAccelerator)) begin + if ((k == 0 && MMU_PRESENT) || (k == 1) || (k == 2 && CVA6Cfg.EnableAccelerator)) begin assign rd_prio[k] = 1'b1; wt_dcache_ctrl #( .CVA6Cfg(CVA6Cfg), @@ -215,16 +215,16 @@ module wt_dcache assign req_ports_o[k] = '0; assign miss_req[k] = 1'b0; assign miss_we[k] = 1'b0; - assign miss_wdata[k] = {{riscv::XLEN}{1'b0}}; - assign miss_wuser[k] = {{DCACHE_USER_WIDTH}{1'b0}}; - assign miss_vld_bits_o[k] = {{DCACHE_SET_ASSOC}{1'b0}}; - assign miss_paddr[k] = {{riscv::PLEN}{1'b0}}; + assign miss_wdata[k] = {{riscv::XLEN} {1'b0}}; + assign miss_wuser[k] = {{DCACHE_USER_WIDTH} {1'b0}}; + assign miss_vld_bits_o[k] = {{DCACHE_SET_ASSOC} {1'b0}}; + assign miss_paddr[k] = {{riscv::PLEN} {1'b0}}; assign miss_nc[k] = 1'b0; assign miss_size[k] = 3'b0; - assign miss_id[k] = {{CACHE_ID_WIDTH}{1'b0}}; - assign rd_tag[k] = {{DCACHE_TAG_WIDTH}{1'b0}}; - assign rd_idx[k] = {{DCACHE_CL_IDX_WIDTH}{1'b0}}; - assign rd_off[k] = {{DCACHE_OFFSET_WIDTH}{1'b0}}; + assign miss_id[k] = {{CACHE_ID_WIDTH} {1'b0}}; + assign rd_tag[k] = {{DCACHE_TAG_WIDTH} {1'b0}}; + assign rd_idx[k] = {{DCACHE_CL_IDX_WIDTH} {1'b0}}; + assign rd_off[k] = {{DCACHE_OFFSET_WIDTH} {1'b0}}; assign rd_req[k] = 1'b0; assign rd_tag_only[k] = 1'b0; end diff --git a/core/cache_subsystem/wt_dcache_missunit.sv b/core/cache_subsystem/wt_dcache_missunit.sv index 6cedc28c6a..3e06a92e04 100644 --- a/core/cache_subsystem/wt_dcache_missunit.sv +++ b/core/cache_subsystem/wt_dcache_missunit.sv @@ -245,10 +245,10 @@ module wt_dcache_missunit if (CVA6Cfg.RVA) begin if (riscv::IS_XLEN64) begin : gen_amo_64b_data - assign amo_data_a = {amo_req_i.operand_b[0 +: 32], amo_req_i.operand_b[0 +: 32]}; + assign amo_data_a = {amo_req_i.operand_b[0+:32], amo_req_i.operand_b[0+:32]}; assign amo_data_b = amo_req_i.operand_b; end else begin : gen_amo_32b_data - assign amo_data_a = amo_req_i.operand_b[0 +: 32]; + assign amo_data_a = amo_req_i.operand_b[0+:32]; end end @@ -292,16 +292,16 @@ module wt_dcache_missunit end // outgoing memory requests (AMOs are always uncached) - assign mem_data_o.tid = (CVA6Cfg.RVA && amo_sel) ? AmoTxId : miss_id_i[miss_port_idx]; - assign mem_data_o.nc = (CVA6Cfg.RVA && amo_sel) ? 1'b1 : miss_nc_i[miss_port_idx]; - assign mem_data_o.way = (CVA6Cfg.RVA && amo_sel) ? '0 : repl_way; - assign mem_data_o.data = (CVA6Cfg.RVA && amo_sel) ? amo_data : miss_wdata_i[miss_port_idx]; - assign mem_data_o.user = (CVA6Cfg.RVA && amo_sel) ? amo_user : miss_wuser_i[miss_port_idx]; + assign mem_data_o.tid = (CVA6Cfg.RVA && amo_sel) ? AmoTxId : miss_id_i[miss_port_idx]; + assign mem_data_o.nc = (CVA6Cfg.RVA && amo_sel) ? 1'b1 : miss_nc_i[miss_port_idx]; + assign mem_data_o.way = (CVA6Cfg.RVA && amo_sel) ? '0 : repl_way; + assign mem_data_o.data = (CVA6Cfg.RVA && amo_sel) ? amo_data : miss_wdata_i[miss_port_idx]; + assign mem_data_o.user = (CVA6Cfg.RVA && amo_sel) ? amo_user : miss_wuser_i[miss_port_idx]; assign mem_data_o.size = (CVA6Cfg.RVA && amo_sel) ? {1'b0, amo_req_i.size} : miss_size_i [miss_port_idx]; - assign mem_data_o.amo_op = (CVA6Cfg.RVA && amo_sel) ? amo_req_i.amo_op : AMO_NONE; + assign mem_data_o.amo_op = (CVA6Cfg.RVA && amo_sel) ? amo_req_i.amo_op : AMO_NONE; assign tmp_paddr = (CVA6Cfg.RVA && amo_sel) ? amo_req_i.operand_a[riscv::PLEN-1:0] : miss_paddr_i[miss_port_idx]; - assign mem_data_o.paddr = paddrSizeAlign(tmp_paddr, mem_data_o.size); + assign mem_data_o.paddr = paddrSizeAlign(tmp_paddr, mem_data_o.size); /////////////////////////////////////////////////////// // back-off mechanism for LR/SC completion guarantee @@ -358,19 +358,19 @@ module wt_dcache_missunit end end DCACHE_ATOMIC_ACK: begin - if(CVA6Cfg.RVA) begin - if (amo_req_q) begin - amo_ack = 1'b1; - // need to set SC backoff counter if - // this op failed - if (amo_req_i.amo_op == AMO_SC) begin - if (amo_resp_o.result>0) begin - sc_fail = 1'b1; - end else begin - sc_pass = 1'b1; - end + if (CVA6Cfg.RVA) begin + if (amo_req_q) begin + amo_ack = 1'b1; + // need to set SC backoff counter if + // this op failed + if (amo_req_i.amo_op == AMO_SC) begin + if (amo_resp_o.result > 0) begin + sc_fail = 1'b1; + end else begin + sc_pass = 1'b1; end end + end end end DCACHE_INV_REQ: begin @@ -546,27 +546,27 @@ module wt_dcache_missunit ////////////////////////////////// // send out amo op request AMO: begin - if(CVA6Cfg.RVA) begin - mem_data_o.rtype = DCACHE_ATOMIC_REQ; - amo_sel = 1'b1; - // if this is an LR, we need to consult the backoff counter - if ((amo_req_i.amo_op != AMO_LR) || sc_backoff_over) begin - mem_data_req_o = 1'b1; - if (mem_data_ack_i) begin - state_d = AMO_WAIT; - end - end + if (CVA6Cfg.RVA) begin + mem_data_o.rtype = DCACHE_ATOMIC_REQ; + amo_sel = 1'b1; + // if this is an LR, we need to consult the backoff counter + if ((amo_req_i.amo_op != AMO_LR) || sc_backoff_over) begin + mem_data_req_o = 1'b1; + if (mem_data_ack_i) begin + state_d = AMO_WAIT; + end + end end end ////////////////////////////////// // block and wait until AMO OP returns AMO_WAIT: begin - if(CVA6Cfg.RVA) begin - amo_sel = 1'b1; - if (amo_ack) begin - amo_resp_o.ack = 1'b1; - state_d = IDLE; - end + if (CVA6Cfg.RVA) begin + amo_sel = 1'b1; + if (amo_ack) begin + amo_resp_o.ack = 1'b1; + state_d = IDLE; + end end end ////////////////////////////////// diff --git a/core/cache_subsystem/wt_dcache_wbuffer.sv b/core/cache_subsystem/wt_dcache_wbuffer.sv index 0b0806283a..8e9c39d485 100644 --- a/core/cache_subsystem/wt_dcache_wbuffer.sv +++ b/core/cache_subsystem/wt_dcache_wbuffer.sv @@ -166,8 +166,10 @@ module wt_dcache_wbuffer assign wbuffer_data_o = wbuffer_q; for (genvar k = 0; k < DCACHE_MAX_TX; k++) begin : gen_tx_vld - assign tx_vld_o[k] = tx_stat_q[k].vld; - assign tx_paddr_o[k] = {{riscv::XLEN_ALIGN_BYTES{1'b0}}, wbuffer_q[tx_stat_q[k].ptr].wtag << riscv::XLEN_ALIGN_BYTES}; + assign tx_vld_o[k] = tx_stat_q[k].vld; + assign tx_paddr_o[k] = { + {riscv::XLEN_ALIGN_BYTES{1'b0}}, wbuffer_q[tx_stat_q[k].ptr].wtag << riscv::XLEN_ALIGN_BYTES + }; end /////////////////////////////////////////////////////// @@ -201,7 +203,7 @@ module wt_dcache_wbuffer // note: openpiton can only handle aligned offsets + size, and hence // we have to split unaligned data into multiple transfers (see toSize64) // e.g. if we have the following valid bytes: 0011_1001 -> TX0: 0000_0001, TX1: 0000_1000, TX2: 0011_0000 - if(riscv::IS_XLEN64) begin : gen_size_64b + if (riscv::IS_XLEN64) begin : gen_size_64b assign miss_size_o = {1'b0, toSize64(bdirty[dirty_ptr])}; end else begin : gen_size_32b assign miss_size_o = {1'b0, toSize32(bdirty[dirty_ptr])}; @@ -306,28 +308,32 @@ module wt_dcache_wbuffer // cache readout & update /////////////////////////////////////////////////////// - assign extract_tag = rd_paddr >> DCACHE_INDEX_WIDTH; - assign rd_tag_d = extract_tag[DCACHE_TAG_WIDTH-1:0]; + assign extract_tag = rd_paddr >> DCACHE_INDEX_WIDTH; + assign rd_tag_d = extract_tag[DCACHE_TAG_WIDTH-1:0]; // trigger TAG readout in cache assign rd_tag_only_o = 1'b1; - assign rd_paddr = {{riscv::XLEN_ALIGN_BYTES{1'b0}}, wbuffer_check_mux.wtag << riscv::XLEN_ALIGN_BYTES}; - assign rd_req_o = |tocheck; - assign rd_tag_o = rd_tag_q; //delay by one cycle - assign rd_idx_o = rd_paddr[DCACHE_INDEX_WIDTH-1:DCACHE_OFFSET_WIDTH]; - assign rd_off_o = rd_paddr[DCACHE_OFFSET_WIDTH-1:0]; - assign check_en_d = rd_req_o & rd_ack_i; + assign rd_paddr = { + {riscv::XLEN_ALIGN_BYTES{1'b0}}, wbuffer_check_mux.wtag << riscv::XLEN_ALIGN_BYTES + }; + assign rd_req_o = |tocheck; + assign rd_tag_o = rd_tag_q; //delay by one cycle + assign rd_idx_o = rd_paddr[DCACHE_INDEX_WIDTH-1:DCACHE_OFFSET_WIDTH]; + assign rd_off_o = rd_paddr[DCACHE_OFFSET_WIDTH-1:0]; + assign check_en_d = rd_req_o & rd_ack_i; // cache update port - assign rtrn_ptr = tx_stat_q[rtrn_id].ptr; + assign rtrn_ptr = tx_stat_q[rtrn_id].ptr; // if we wrote into a word while it was in-flight, we cannot write the dirty bytes to the cache // when the TX returns - assign wr_data_be_o = tx_stat_q[rtrn_id].be & (~wbuffer_q[rtrn_ptr].dirty); - assign wr_paddr = {{riscv::XLEN_ALIGN_BYTES{1'b0}}, wbuffer_q[rtrn_ptr].wtag << riscv::XLEN_ALIGN_BYTES}; - assign wr_idx_o = wr_paddr[DCACHE_INDEX_WIDTH-1:DCACHE_OFFSET_WIDTH]; - assign wr_off_o = wr_paddr[DCACHE_OFFSET_WIDTH-1:0]; - assign wr_data_o = wbuffer_q[rtrn_ptr].data; - assign wr_user_o = wbuffer_q[rtrn_ptr].user; + assign wr_data_be_o = tx_stat_q[rtrn_id].be & (~wbuffer_q[rtrn_ptr].dirty); + assign wr_paddr = { + {riscv::XLEN_ALIGN_BYTES{1'b0}}, wbuffer_q[rtrn_ptr].wtag << riscv::XLEN_ALIGN_BYTES + }; + assign wr_idx_o = wr_paddr[DCACHE_INDEX_WIDTH-1:DCACHE_OFFSET_WIDTH]; + assign wr_off_o = wr_paddr[DCACHE_OFFSET_WIDTH-1:0]; + assign wr_data_o = wbuffer_q[rtrn_ptr].data; + assign wr_user_o = wbuffer_q[rtrn_ptr].user; /////////////////////////////////////////////////////// @@ -341,8 +347,10 @@ module wt_dcache_wbuffer for (genvar k = 0; k < DCACHE_WBUF_DEPTH; k++) begin : gen_flags // only for debug, will be pruned - if(CVA6Cfg.DebugEn) begin - assign debug_paddr[k] = {{riscv::XLEN_ALIGN_BYTES{1'b0}}, wbuffer_q[k].wtag << riscv::XLEN_ALIGN_BYTES}; + if (CVA6Cfg.DebugEn) begin + assign debug_paddr[k] = { + {riscv::XLEN_ALIGN_BYTES{1'b0}}, wbuffer_q[k].wtag << riscv::XLEN_ALIGN_BYTES + }; end // dirty bytes that are ready for transmission. diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv index e39e3b0674..1ab6d55d20 100644 --- a/core/csr_regfile.sv +++ b/core/csr_regfile.sv @@ -692,7 +692,7 @@ module csr_regfile if (CVA6Cfg.DebugEn) dscratch1_d = csr_wdata; else update_access_exception = 1'b1; // trigger module CSRs - riscv::CSR_TSELECT: update_access_exception = 1'b1 ; // not implemented + riscv::CSR_TSELECT: update_access_exception = 1'b1; // not implemented riscv::CSR_TDATA1: update_access_exception = 1'b1; // not implemented riscv::CSR_TDATA2: update_access_exception = 1'b1; // not implemented riscv::CSR_TDATA3: update_access_exception = 1'b1; // not implemented diff --git a/core/cva6.sv b/core/cva6.sv index 6d25d6ac67..ff29f29633 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -1313,7 +1313,7 @@ module cva6 else begin case (priv_lvl) riscv::PRIV_LVL_M: mode = "M"; - riscv::PRIV_LVL_S: if(CVA6Cfg.RVS) mode = "S"; + riscv::PRIV_LVL_S: if (CVA6Cfg.RVS) mode = "S"; riscv::PRIV_LVL_U: mode = "U"; default: ; // Do nothing endcase diff --git a/core/cvxif_fu.sv b/core/cvxif_fu.sv index 74be472a7b..fb0058b9ca 100644 --- a/core/cvxif_fu.sv +++ b/core/cvxif_fu.sv @@ -33,7 +33,7 @@ module cvxif_fu output cvxif_pkg::cvxif_req_t cvxif_req_o, input cvxif_pkg::cvxif_resp_t cvxif_resp_i ); - localparam X_NUM_RS = ariane_pkg::NR_RGPR_PORTS; + localparam X_NUM_RS = ariane_pkg::NR_RGPR_PORTS; logic illegal_n, illegal_q; logic [TRANS_ID_BITS-1:0] illegal_id_n, illegal_id_q; diff --git a/core/ex_stage.sv b/core/ex_stage.sv index 92f871c8e2..d698a4b8cd 100644 --- a/core/ex_stage.sv +++ b/core/ex_stage.sv @@ -386,7 +386,7 @@ module ex_stage assign x_valid_o = '0; end - if(CVA6Cfg.RVS) begin + if (CVA6Cfg.RVS) begin always_ff @(posedge clk_i or negedge rst_ni) begin if (~rst_ni) begin current_instruction_is_sfence_vma <= 1'b0; @@ -411,9 +411,9 @@ module ex_stage end end end else begin - assign current_instruction_is_sfence_vma = 1'b0; - assign asid_to_be_flushed = '0; - assign vaddr_to_be_flushed = '0; + assign current_instruction_is_sfence_vma = 1'b0; + assign asid_to_be_flushed = '0; + assign vaddr_to_be_flushed = '0; end endmodule diff --git a/core/include/config_pkg.sv b/core/include/config_pkg.sv index edad7d68fa..7c455dd08e 100644 --- a/core/include/config_pkg.sv +++ b/core/include/config_pkg.sv @@ -71,8 +71,8 @@ package config_pkg; int unsigned NrRgprPorts; int unsigned NrWbPorts; bit EnableAccelerator; - bit RVS; //Supervisor mode - bit RVU; //User mode + bit RVS; //Supervisor mode + bit RVU; //User mode // Debug Module // address to which a hart should jump when it was requested to halt logic [63:0] HaltAddress; diff --git a/core/include/wt_cache_pkg.sv b/core/include/wt_cache_pkg.sv index 3884a6b08d..9a8c0ce034 100644 --- a/core/include/wt_cache_pkg.sv +++ b/core/include/wt_cache_pkg.sv @@ -265,7 +265,8 @@ package wt_cache_pkg; return cnt; endfunction : popcnt64 - function automatic logic [(riscv::XLEN/8)-1:0] to_byte_enable8(input logic [riscv::XLEN_ALIGN_BYTES-1:0] offset, input logic [1:0] size); + function automatic logic [(riscv::XLEN/8)-1:0] to_byte_enable8( + input logic [riscv::XLEN_ALIGN_BYTES-1:0] offset, input logic [1:0] size); logic [(riscv::XLEN/8)-1:0] be; be = '0; unique case (size) @@ -277,7 +278,8 @@ package wt_cache_pkg; return be; endfunction : to_byte_enable8 - function automatic logic [(riscv::XLEN/8)-1:0] to_byte_enable4(input logic [riscv::XLEN_ALIGN_BYTES-1:0] offset, input logic [1:0] size); + function automatic logic [(riscv::XLEN/8)-1:0] to_byte_enable4( + input logic [riscv::XLEN_ALIGN_BYTES-1:0] offset, input logic [1:0] size); logic [3:0] be; be = '0; unique case (size) @@ -289,8 +291,9 @@ package wt_cache_pkg; endfunction : to_byte_enable4 // openpiton requires the data to be replicated in case of smaller sizes than dwords - function automatic riscv::xlen_t repData64(input riscv::xlen_t data, input logic [riscv::XLEN_ALIGN_BYTES-1:0] offset, - input logic [1:0] size); + function automatic riscv::xlen_t repData64(input riscv::xlen_t data, + input logic [riscv::XLEN_ALIGN_BYTES-1:0] offset, + input logic [1:0] size); riscv::xlen_t out; unique case (size) 2'b00: for (int k = 0; k < 8; k++) out[k*8+:8] = data[offset*8+:8]; // byte @@ -301,8 +304,9 @@ package wt_cache_pkg; return out; endfunction : repData64 - function automatic riscv::xlen_t repData32(input riscv::xlen_t data, input logic [riscv::XLEN_ALIGN_BYTES-1:0] offset, - input logic [1:0] size); + function automatic riscv::xlen_t repData32(input riscv::xlen_t data, + input logic [riscv::XLEN_ALIGN_BYTES-1:0] offset, + input logic [1:0] size); riscv::xlen_t out; unique case (size) 2'b00: for (int k = 0; k < 4; k++) out[k*8+:8] = data[offset*8+:8]; // byte diff --git a/core/instr_realign.sv b/core/instr_realign.sv index 8e65806480..043a13116d 100644 --- a/core/instr_realign.sv +++ b/core/instr_realign.sv @@ -99,7 +99,7 @@ module instr_realign unaligned_instr_d = data_i[15:0]; // the instruction isn't compressed but only the lower is ready end else begin - valid_o = {{INSTR_PER_FETCH-1{1'b0}}, 1'b1}; + valid_o = {{INSTR_PER_FETCH - 1{1'b0}}, 1'b1}; end end end diff --git a/core/issue_read_operands.sv b/core/issue_read_operands.sv index c28e826627..e698e3c4be 100644 --- a/core/issue_read_operands.sv +++ b/core/issue_read_operands.sv @@ -86,7 +86,10 @@ module issue_read_operands logic stall; logic fu_busy; // functional unit is busy riscv::xlen_t operand_a_regfile, operand_b_regfile; // operands coming from regfile - rs3_len_t operand_c_regfile, operand_c_fpr, operand_c_gpr; // third operand from fp regfile or gp regfile if NR_RGPR_PORTS == 3 + rs3_len_t + operand_c_regfile, + operand_c_fpr, + operand_c_gpr; // third operand from fp regfile or gp regfile if NR_RGPR_PORTS == 3 // output flipflop (ID <-> EX) riscv::xlen_t operand_a_n, operand_a_q, operand_b_n, operand_b_q, imm_n, imm_q, imm_forward_rs3; @@ -223,9 +226,9 @@ module issue_read_operands // third operand from fp regfile or gp regfile if NR_RGPR_PORTS == 3 if (CVA6Cfg.NrRgprPorts == 3) begin : gen_gp_rs3 - assign imm_forward_rs3 = rs3_i; + assign imm_forward_rs3 = rs3_i; end else begin : gen_fp_rs3 - assign imm_forward_rs3 = {{riscv::XLEN-CVA6Cfg.FLen{1'b0}}, rs3_i}; + assign imm_forward_rs3 = {{riscv::XLEN - CVA6Cfg.FLen{1'b0}}, rs3_i}; end // Forwarding/Output MUX @@ -536,7 +539,7 @@ module issue_read_operands endgenerate if (CVA6Cfg.NrRgprPorts == 3) begin : gen_operand_c - assign operand_c_fpr = {{riscv::XLEN-CVA6Cfg.FLen{1'b0}}, fprdata[2]}; + assign operand_c_fpr = {{riscv::XLEN - CVA6Cfg.FLen{1'b0}}, fprdata[2]}; assign operand_c_gpr = rdata[2]; end else begin assign operand_c_fpr = fprdata[2]; @@ -548,7 +551,9 @@ module issue_read_operands assign operand_b_regfile = (CVA6Cfg.FpPresent && is_rs2_fpr( issue_instr_i.op )) ? {{riscv::XLEN - CVA6Cfg.FLen{1'b0}}, fprdata[1]} : rdata[1]; - assign operand_c_regfile = (CVA6Cfg.NrRgprPorts == 3) ? ((CVA6Cfg.FpPresent && is_imm_fpr(issue_instr_i.op)) ? operand_c_fpr : operand_c_gpr) : operand_c_fpr; + assign operand_c_regfile = (CVA6Cfg.NrRgprPorts == 3) ? ((CVA6Cfg.FpPresent && is_imm_fpr( + issue_instr_i.op + )) ? operand_c_fpr : operand_c_gpr) : operand_c_fpr; // ---------------------- diff --git a/core/load_unit.sv b/core/load_unit.sv index d6143ffe47..14236b1a04 100644 --- a/core/load_unit.sv +++ b/core/load_unit.sv @@ -186,7 +186,9 @@ module load_unit logic not_commit_time; logic inflight_stores; logic stall_ni; - assign paddr_ni = config_pkg::is_inside_nonidempotent_regions(CVA6Cfg, {{52-riscv::PPNW{1'b0}}, dtlb_ppn_i, 12'd0}); + assign paddr_ni = config_pkg::is_inside_nonidempotent_regions( + CVA6Cfg, {{52 - riscv::PPNW{1'b0}}, dtlb_ppn_i, 12'd0} + ); assign not_commit_time = commit_tran_id_i != lsu_ctrl_i.trans_id; assign inflight_stores = (!dcache_wbuffer_not_ni_i || !store_buffer_empty_i); assign stall_ni = (inflight_stores || not_commit_time) && (paddr_ni && CVA6Cfg.NonIdemPotenceEn); @@ -259,7 +261,7 @@ module load_unit // we are here because of a TLB miss, we need to abort the current request and give way for the // PTW walker to satisfy the TLB miss ABORT_TRANSACTION: begin - if(ariane_pkg::MMU_PRESENT) begin + if (ariane_pkg::MMU_PRESENT) begin req_port_o.kill_req = 1'b1; req_port_o.tag_valid = 1'b1; // wait until the WB is empty @@ -268,7 +270,7 @@ module load_unit end ABORT_TRANSACTION_NI: begin - if(CVA6Cfg.NonIdemPotenceEn) begin + if (CVA6Cfg.NonIdemPotenceEn) begin req_port_o.kill_req = 1'b1; req_port_o.tag_valid = 1'b1; // re-do the request @@ -283,7 +285,7 @@ module load_unit end WAIT_TRANSLATION: begin - if(ariane_pkg::MMU_PRESENT || CVA6Cfg.NonIdemPotenceEn) begin + if (ariane_pkg::MMU_PRESENT || CVA6Cfg.NonIdemPotenceEn) begin translation_req_o = 1'b1; // we've got a hit and we can continue with the request process if (dtlb_hit_i) state_d = WAIT_GNT; diff --git a/core/mmu_sv32/cva6_mmu_sv32.sv b/core/mmu_sv32/cva6_mmu_sv32.sv index 2be172e457..d194306eb7 100644 --- a/core/mmu_sv32/cva6_mmu_sv32.sv +++ b/core/mmu_sv32/cva6_mmu_sv32.sv @@ -278,7 +278,9 @@ module cva6_mmu_sv32 {riscv::PLEN - riscv::VLEN{1'b0}}, icache_areq_i.fetch_vaddr }; // play through in case we disabled address translation else - icache_areq_o.fetch_paddr = {2'b00, icache_areq_i.fetch_vaddr[riscv::VLEN-1:0]};// play through in case we disabled address translation + icache_areq_o.fetch_paddr = { + 2'b00, icache_areq_i.fetch_vaddr[riscv::VLEN-1:0] + }; // play through in case we disabled address translation // two potential exception sources: // 1. HPTW threw an exception -> signal with a page fault exception // 2. We got an access error because of insufficient permissions -> throw an access exception diff --git a/core/scoreboard.sv b/core/scoreboard.sv index 25c54346c6..e924cd6709 100644 --- a/core/scoreboard.sv +++ b/core/scoreboard.sv @@ -173,10 +173,10 @@ module scoreboard #( // check if this instruction was issued (e.g.: it could happen after a flush that there is still // something in the pipeline e.g. an incomplete memory operation) if (wt_valid_i[i] && mem_q[trans_id_i[i]].issued) begin - mem_n[trans_id_i[i]].sbe.valid = 1'b1; + mem_n[trans_id_i[i]].sbe.valid = 1'b1; mem_n[trans_id_i[i]].sbe.result = wbdata_i[i]; // save the target address of a branch (needed for debug in commit stage) - if(CVA6Cfg.DebugEn) begin + if (CVA6Cfg.DebugEn) begin mem_n[trans_id_i[i]].sbe.bp.predict_address = resolved_branch_i.target_address; end if (mem_n[trans_id_i[i]].sbe.fu == ariane_pkg::CVXIF && ~x_we_i) begin @@ -223,8 +223,9 @@ module scoreboard #( assign num_commit = commit_ack_i[0]; end - assign issue_cnt_n = (flush_i) ? '0 : issue_cnt_q - {{BITS_ENTRIES-$clog2(CVA6Cfg.NrCommitPorts){1'b0}}, num_commit} - + {{BITS_ENTRIES-1{1'b0}}, issue_en}; + assign issue_cnt_n = (flush_i) ? '0 : issue_cnt_q - {{BITS_ENTRIES - $clog2( + CVA6Cfg.NrCommitPorts + ) {1'b0}}, num_commit} + {{BITS_ENTRIES - 1{1'b0}}, issue_en}; assign commit_pointer_n[0] = (flush_i) ? '0 : commit_pointer_q[0] + num_commit; assign issue_pointer_n = (flush_i) ? '0 : issue_pointer_q + issue_en; @@ -447,9 +448,9 @@ module scoreboard #( @(posedge clk_i) disable iff (!rst_ni) commit_ack_i[0] |-> commit_instr_o[0].valid) else $fatal(1, "Commit acknowledged but instruction is not valid"); if (CVA6Cfg.NrCommitPorts == 2) begin : gen_two_commit_ports - assert property ( + assert property ( @(posedge clk_i) disable iff (!rst_ni) commit_ack_i[1] |-> commit_instr_o[1].valid) - else $fatal(1, "Commit acknowledged but instruction is not valid"); + else $fatal(1, "Commit acknowledged but instruction is not valid"); end // assert that we never give an issue ack signal if the instruction is not valid assert property (@(posedge clk_i) disable iff (!rst_ni) issue_ack_i |-> issue_instr_valid_o) diff --git a/core/store_unit.sv b/core/store_unit.sv index 9ece2d2104..721bcde37b 100644 --- a/core/store_unit.sv +++ b/core/store_unit.sv @@ -188,26 +188,26 @@ module store_unit st_be_n = lsu_ctrl_i.be; // don't shift the data if we are going to perform an AMO as we still need to operate on this data st_data_n = (CVA6Cfg.RVA && instr_is_amo) ? lsu_ctrl_i.data[riscv::XLEN-1:0] : - data_align(lsu_ctrl_i.vaddr[2:0], {{64-riscv::XLEN{1'b0}}, lsu_ctrl_i.data}); + data_align(lsu_ctrl_i.vaddr[2:0], {{64 - riscv::XLEN{1'b0}}, lsu_ctrl_i.data}); st_data_size_n = extract_transfer_size(lsu_ctrl_i.operation); // save AMO op for next cycle - if(CVA6Cfg.RVA) begin - case (lsu_ctrl_i.operation) - AMO_LRW, AMO_LRD: amo_op_d = AMO_LR; - AMO_SCW, AMO_SCD: amo_op_d = AMO_SC; - AMO_SWAPW, AMO_SWAPD: amo_op_d = AMO_SWAP; - AMO_ADDW, AMO_ADDD: amo_op_d = AMO_ADD; - AMO_ANDW, AMO_ANDD: amo_op_d = AMO_AND; - AMO_ORW, AMO_ORD: amo_op_d = AMO_OR; - AMO_XORW, AMO_XORD: amo_op_d = AMO_XOR; - AMO_MAXW, AMO_MAXD: amo_op_d = AMO_MAX; - AMO_MAXWU, AMO_MAXDU: amo_op_d = AMO_MAXU; - AMO_MINW, AMO_MIND: amo_op_d = AMO_MIN; - AMO_MINWU, AMO_MINDU: amo_op_d = AMO_MINU; - default: amo_op_d = AMO_NONE; - endcase + if (CVA6Cfg.RVA) begin + case (lsu_ctrl_i.operation) + AMO_LRW, AMO_LRD: amo_op_d = AMO_LR; + AMO_SCW, AMO_SCD: amo_op_d = AMO_SC; + AMO_SWAPW, AMO_SWAPD: amo_op_d = AMO_SWAP; + AMO_ADDW, AMO_ADDD: amo_op_d = AMO_ADD; + AMO_ANDW, AMO_ANDD: amo_op_d = AMO_AND; + AMO_ORW, AMO_ORD: amo_op_d = AMO_OR; + AMO_XORW, AMO_XORD: amo_op_d = AMO_XOR; + AMO_MAXW, AMO_MAXD: amo_op_d = AMO_MAX; + AMO_MAXWU, AMO_MAXDU: amo_op_d = AMO_MAXU; + AMO_MINW, AMO_MIND: amo_op_d = AMO_MIN; + AMO_MINWU, AMO_MINDU: amo_op_d = AMO_MINU; + default: amo_op_d = AMO_NONE; + endcase end else begin - amo_op_d = AMO_NONE; + amo_op_d = AMO_NONE; end end @@ -253,28 +253,28 @@ module store_unit .req_port_o (req_port_o) ); - if(CVA6Cfg.RVA) begin - amo_buffer #( - .CVA6Cfg ( CVA6Cfg ) - ) i_amo_buffer ( - .clk_i, - .rst_ni, - .flush_i, - .valid_i ( amo_buffer_valid ), - .ready_o ( amo_buffer_ready ), - .paddr_i ( paddr_i ), - .amo_op_i ( amo_op_q ), - .data_i ( st_data_q ), - .data_size_i ( st_data_size_q ), - .amo_req_o ( amo_req_o ), - .amo_resp_i ( amo_resp_i ), - .amo_valid_commit_i ( amo_valid_commit_i ), - .no_st_pending_i ( no_st_pending_o ) - ); - end else begin - assign amo_buffer_ready = '1; - assign amo_req_o = '0; - end + if (CVA6Cfg.RVA) begin + amo_buffer #( + .CVA6Cfg(CVA6Cfg) + ) i_amo_buffer ( + .clk_i, + .rst_ni, + .flush_i, + .valid_i (amo_buffer_valid), + .ready_o (amo_buffer_ready), + .paddr_i (paddr_i), + .amo_op_i (amo_op_q), + .data_i (st_data_q), + .data_size_i (st_data_size_q), + .amo_req_o (amo_req_o), + .amo_resp_i (amo_resp_i), + .amo_valid_commit_i(amo_valid_commit_i), + .no_st_pending_i (no_st_pending_o) + ); + end else begin + assign amo_buffer_ready = '1; + assign amo_req_o = '0; + end // --------------- // Registers