From 9c57436b24ea4ee8a9bd6efc1a8f1d9acefebc1b Mon Sep 17 00:00:00 2001 From: Ludovic Pion Date: Fri, 6 Dec 2024 13:57:47 +0100 Subject: [PATCH 1/4] Added cv64a65x_config_pkg.sv for CVA6 64bits config. To be reviewed! --- core/include/cv64a65x_config_pkg.sv | 101 ++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) create mode 100644 core/include/cv64a65x_config_pkg.sv diff --git a/core/include/cv64a65x_config_pkg.sv b/core/include/cv64a65x_config_pkg.sv new file mode 100644 index 0000000000..2b492264e5 --- /dev/null +++ b/core/include/cv64a65x_config_pkg.sv @@ -0,0 +1,101 @@ +// Copyright 2022 Thales DIS design services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Jean-Roch COULON - Thales + +package cva6_config_pkg; + + localparam CVA6ConfigXlen = 64; + + localparam CVA6ConfigRvfiTrace = 1; + + localparam CVA6ConfigAxiIdWidth = 6; // axi_pkg.sv + localparam CVA6ConfigAxiAddrWidth = 64; // axi_pkg.sv + localparam CVA6ConfigAxiDataWidth = 64; // axi_pkg.sv + localparam CVA6ConfigDataUserWidth = 64; // axi_pkg.sv + + localparam CVA6ConfigSuperscalarEn = 0; // superscalar + + localparam CVA6ConfigNrScoreboardEntries = 8; // cvxif_pkg.sv + + localparam config_pkg::cache_type_t CVA6ConfigDcacheType = config_pkg::HPDCACHE; + + localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ + XLEN: unsigned'(CVA6ConfigXlen), + FpgaEn: bit'(0), + NrCommitPorts: unsigned'(2), + AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), + AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), + AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth), + AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth), + MemTidWidth: unsigned'(CVA6ConfigAxiIdWidth), + NrLoadBufEntries: unsigned'(8), + RVF: bit'(1), + RVD: bit'(1), + XF16: bit'(0), + XF16ALT: bit'(0), + XF8: bit'(0), + RVA: bit'(1), + RVB: bit'(1), + RVV: bit'(0), + RVC: bit'(1), + RVH: bit'(0), + RVZCB: bit'(1), + RVZCMP: bit'(0), + XFVec: bit'(0), + CvxifEn: bit'(1), + RVZiCond: bit'(1), + NrScoreboardEntries: unsigned'(CVA6ConfigNrScoreboardEntries), + PerfCounterEn: bit'(1), + MmuPresent: bit'(1), + RVS: bit'(1), + RVU: bit'(1), + HaltAddress: 64'h800, + ExceptionAddress: 64'h808, + RASDepth: unsigned'(2), + BTBEntries: unsigned'(32), + BHTEntries: unsigned'(128), + DmBaseAddress: 64'h0, + TvalEn: bit'(0), + NrPMPEntries: unsigned'(8), + PMPCfgRstVal: {16{64'h0}}, + PMPAddrRstVal: {16{64'h0}}, + PMPEntryReadOnly: 16'd0, + NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, + NrNonIdempotentRules: unsigned'(2), + NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), + NonIdempotentLength: 1024'({64'b0, 64'b0}), + NrExecuteRegionRules: unsigned'(3), + ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}), + ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}), + NrCachedRegionRules: unsigned'(1), + CachedRegionAddrBase: 1024'({64'h8000_0000}), + CachedRegionLength: 1024'({64'h40000000}), + MaxOutstandingStores: unsigned'(7), + DebugEn: bit'(1), + AxiBurstWriteEn: bit'(0), + IcacheByteSize: unsigned'(32768), + IcacheSetAssoc: unsigned'(8), + IcacheLineWidth: unsigned'(512), + DCacheType: config_pkg::HPDCACHE, + DcacheByteSize: unsigned'(32768), + DcacheSetAssoc: unsigned'(8), + DcacheLineWidth: unsigned'(512), + DataUserEn: unsigned'(1), + WtDcacheWbufDepth: int'(8), + FetchUserWidth: unsigned'(64), + FetchUserEn: unsigned'(0), + InstrTlbEntries: int'(16), + DataTlbEntries: int'(16), + UseSharedTlb: bit'(0), + SharedTlbDepth: int'(64), + NrLoadPipeRegs: int'(1), + NrStorePipeRegs: int'(0), + DcacheIdWidth: int'(3) + }; + +endpackage From c6288116d1e285090e5e07d535e1e8a4952ef0ab Mon Sep 17 00:00:00 2001 From: Ludovic Pion Date: Tue, 17 Dec 2024 16:34:42 +0100 Subject: [PATCH 2/4] renamed comfiguration file --- core/include/cv64aTBD_config_pkg.sv | 89 +++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) create mode 100644 core/include/cv64aTBD_config_pkg.sv diff --git a/core/include/cv64aTBD_config_pkg.sv b/core/include/cv64aTBD_config_pkg.sv new file mode 100644 index 0000000000..3d3418b444 --- /dev/null +++ b/core/include/cv64aTBD_config_pkg.sv @@ -0,0 +1,89 @@ +// Copyright 2022 Thales DIS design services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Ludovic PION - CEA + +package cva6_config_pkg; + + + localparam CVA6ConfigSuperscalarEn = 0; // superscalar + + localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ + XLEN: unsigned'(64), + FpgaEn: bit'(0), + NrCommitPorts: unsigned'(2), + AxiAddrWidth: unsigned'(64), + AxiDataWidth: unsigned'(64), //Ideally we would like to target 256 bits of data + AxiIdWidth: unsigned'(6), + AxiUserWidth: unsigned'(32), + MemTidWidth: unsigned'(6), + NrLoadBufEntries: unsigned'(8), + RVF: bit'(1), + RVD: bit'(1), + XF16: bit'(0), + XF16ALT: bit'(0), + XF8: bit'(0), + RVA: bit'(1), + RVB: bit'(1), + RVV: bit'(0), + RVC: bit'(1), + RVH: bit'(0), + RVZCB: bit'(1), + RVZCMP: bit'(0), + XFVec: bit'(0), + CvxifEn: bit'(1), + RVZiCond: bit'(1), + NrScoreboardEntries: unsigned'(8), + PerfCounterEn: bit'(1), + MmuPresent: bit'(1), + RVS: bit'(1), + RVU: bit'(1), + HaltAddress: 64'h800, + ExceptionAddress: 64'h808, + RASDepth: unsigned'(4), + BTBEntries: unsigned'(16), + BHTEntries: unsigned'(64), + DmBaseAddress: 64'h0, + TvalEn: bit'(1), + NrPMPEntries: unsigned'(8), + PMPCfgRstVal: {16{64'h0}}, + PMPAddrRstVal: {16{64'h0}}, + PMPEntryReadOnly: 16'd0, + NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, + NrNonIdempotentRules: unsigned'(0), + NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), + NonIdempotentLength: 1024'({64'b0, 64'b0}), + NrExecuteRegionRules: unsigned'(4), + ExecuteRegionAddrBase: 1024'({64'h1_0000_0000, 64'h8000_0000, 4'h1_0000, 64'h0}), + ExecuteRegionLength: 1024'({64'h2_0000_0000, 64'h1_0000, 64'h1_0000, 64'h100}), + NrCachedRegionRules: unsigned'(1), + CachedRegionAddrBase: 1024'({64'h8000_0000}), + CachedRegionLength: 1024'({64'h4000_0000}), + MaxOutstandingStores: unsigned'(7), + DebugEn: bit'(1), + AxiBurstWriteEn: bit'(1), + IcacheByteSize: unsigned'(32768), + IcacheSetAssoc: unsigned'(8), + IcacheLineWidth: unsigned'(512), + DCacheType: config_pkg::HPDCACHE, + DcacheByteSize: unsigned'(32768), + DcacheSetAssoc: unsigned'(8), + DcacheLineWidth: unsigned'(512), + DataUserEn: unsigned'(0), + WtDcacheWbufDepth: int'(8), + FetchUserWidth: unsigned'(32), + FetchUserEn: unsigned'(0), + InstrTlbEntries: int'(16), + DataTlbEntries: int'(16), + UseSharedTlb: bit'(0), + SharedTlbDepth: int'(64), + NrLoadPipeRegs: int'(0), + NrStorePipeRegs: int'(0), + DcacheIdWidth: int'(3) + }; + +endpackage From c732b1c4f518d1dc10d59874d4ea4d9cc9689596 Mon Sep 17 00:00:00 2001 From: Ludovic Pion Date: Tue, 17 Dec 2024 16:34:59 +0100 Subject: [PATCH 3/4] renamed comfiguration file --- core/include/cv64a65x_config_pkg.sv | 101 ---------------------------- 1 file changed, 101 deletions(-) delete mode 100644 core/include/cv64a65x_config_pkg.sv diff --git a/core/include/cv64a65x_config_pkg.sv b/core/include/cv64a65x_config_pkg.sv deleted file mode 100644 index 2b492264e5..0000000000 --- a/core/include/cv64a65x_config_pkg.sv +++ /dev/null @@ -1,101 +0,0 @@ -// Copyright 2022 Thales DIS design services SAS -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 -// You may obtain a copy of the License at https://solderpad.org/licenses/ -// -// Original Author: Jean-Roch COULON - Thales - -package cva6_config_pkg; - - localparam CVA6ConfigXlen = 64; - - localparam CVA6ConfigRvfiTrace = 1; - - localparam CVA6ConfigAxiIdWidth = 6; // axi_pkg.sv - localparam CVA6ConfigAxiAddrWidth = 64; // axi_pkg.sv - localparam CVA6ConfigAxiDataWidth = 64; // axi_pkg.sv - localparam CVA6ConfigDataUserWidth = 64; // axi_pkg.sv - - localparam CVA6ConfigSuperscalarEn = 0; // superscalar - - localparam CVA6ConfigNrScoreboardEntries = 8; // cvxif_pkg.sv - - localparam config_pkg::cache_type_t CVA6ConfigDcacheType = config_pkg::HPDCACHE; - - localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ - XLEN: unsigned'(CVA6ConfigXlen), - FpgaEn: bit'(0), - NrCommitPorts: unsigned'(2), - AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), - AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), - AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth), - AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth), - MemTidWidth: unsigned'(CVA6ConfigAxiIdWidth), - NrLoadBufEntries: unsigned'(8), - RVF: bit'(1), - RVD: bit'(1), - XF16: bit'(0), - XF16ALT: bit'(0), - XF8: bit'(0), - RVA: bit'(1), - RVB: bit'(1), - RVV: bit'(0), - RVC: bit'(1), - RVH: bit'(0), - RVZCB: bit'(1), - RVZCMP: bit'(0), - XFVec: bit'(0), - CvxifEn: bit'(1), - RVZiCond: bit'(1), - NrScoreboardEntries: unsigned'(CVA6ConfigNrScoreboardEntries), - PerfCounterEn: bit'(1), - MmuPresent: bit'(1), - RVS: bit'(1), - RVU: bit'(1), - HaltAddress: 64'h800, - ExceptionAddress: 64'h808, - RASDepth: unsigned'(2), - BTBEntries: unsigned'(32), - BHTEntries: unsigned'(128), - DmBaseAddress: 64'h0, - TvalEn: bit'(0), - NrPMPEntries: unsigned'(8), - PMPCfgRstVal: {16{64'h0}}, - PMPAddrRstVal: {16{64'h0}}, - PMPEntryReadOnly: 16'd0, - NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, - NrNonIdempotentRules: unsigned'(2), - NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), - NonIdempotentLength: 1024'({64'b0, 64'b0}), - NrExecuteRegionRules: unsigned'(3), - ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}), - ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}), - NrCachedRegionRules: unsigned'(1), - CachedRegionAddrBase: 1024'({64'h8000_0000}), - CachedRegionLength: 1024'({64'h40000000}), - MaxOutstandingStores: unsigned'(7), - DebugEn: bit'(1), - AxiBurstWriteEn: bit'(0), - IcacheByteSize: unsigned'(32768), - IcacheSetAssoc: unsigned'(8), - IcacheLineWidth: unsigned'(512), - DCacheType: config_pkg::HPDCACHE, - DcacheByteSize: unsigned'(32768), - DcacheSetAssoc: unsigned'(8), - DcacheLineWidth: unsigned'(512), - DataUserEn: unsigned'(1), - WtDcacheWbufDepth: int'(8), - FetchUserWidth: unsigned'(64), - FetchUserEn: unsigned'(0), - InstrTlbEntries: int'(16), - DataTlbEntries: int'(16), - UseSharedTlb: bit'(0), - SharedTlbDepth: int'(64), - NrLoadPipeRegs: int'(1), - NrStorePipeRegs: int'(0), - DcacheIdWidth: int'(3) - }; - -endpackage From 206e832329165cb4dca81212c989190a2097d9ec Mon Sep 17 00:00:00 2001 From: Ludovic Pion Date: Tue, 17 Dec 2024 16:40:12 +0100 Subject: [PATCH 4/4] set superscalar to 1 --- core/include/cv64aTBD_config_pkg.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/include/cv64aTBD_config_pkg.sv b/core/include/cv64aTBD_config_pkg.sv index 3d3418b444..f59ed12cfb 100644 --- a/core/include/cv64aTBD_config_pkg.sv +++ b/core/include/cv64aTBD_config_pkg.sv @@ -10,7 +10,7 @@ package cva6_config_pkg; - localparam CVA6ConfigSuperscalarEn = 0; // superscalar + localparam CVA6ConfigSuperscalarEn = 1; // superscalar localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ XLEN: unsigned'(64),