From 649695a5269f884aea0b59c06edb7aa9a04c3a35 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9=20Sintzoff?= Date: Wed, 8 Jan 2025 15:44:13 +0100 Subject: [PATCH] doc: RVZicntr extension can be not supported MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: André Sintzoff --- docs/riscv-isa/src/counters.adoc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/docs/riscv-isa/src/counters.adoc b/docs/riscv-isa/src/counters.adoc index ec0676006e..7a3baa1ec5 100644 --- a/docs/riscv-isa/src/counters.adoc +++ b/docs/riscv-isa/src/counters.adoc @@ -9,6 +9,7 @@ divided between the "Zicntr" and "Zihpm" extensions. === "Zicntr" Extension for Base Counters and Timers +ifeval::[{RVZicntr} == true] The Zicntr standard extension comprises the first three of these counters (CYCLE, TIME, and INSTRET), which have dedicated functions (cycle count, real-time clock, and instructions retired, respectively). @@ -171,6 +172,11 @@ reading its upper and lower halves. rdcycle x2 rdcycleh x4 bne x3, x4, again +endif::[] + +ifeval::[{RVZicntr} == false] +{ohg-config}: This extension is not supported. +endif::[] === "Zihpm" Extension for Hardware Performance Counters