From 1da7f2c6b0471802d3409a43cd3efd1a63e115fc Mon Sep 17 00:00:00 2001
From: Simone Corbetta <simone.corbetta@gmail.com>
Date: Wed, 20 Mar 2024 08:28:13 +0100
Subject: [PATCH] Test

---
 test/Makefile | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/test/Makefile b/test/Makefile
index cffef7f..bd12276 100644
--- a/test/Makefile
+++ b/test/Makefile
@@ -3,6 +3,7 @@
 VERILOG_SOURCES = 
 SRC_DIR = $(PWD)/../src
 IVERILOG_ARGS =
+COCOTB_PREFIX = $(shell cocotb-config --prefix)
 
 ifneq ($(GATES),yes)
 
@@ -23,11 +24,8 @@ default:
 	pip3 install fxpmath
 	rm -fR sim_build
 	mkdir sim_build
-	update_db
-	locate libcocotbvpi_icarus.vpi
-	python3 -m site --user-site
 	`which iverilog` -o sim_build/sim.vvp $(IVERILOG_ARGS) -g2012 $(VERILOG_SOURCES)
-	MODULE=test TESTCASE= TOPLEVEL=tb TOPLEVEL_LANG=verilog `which vvp` -M `python3 -m site --user-site`/cocotb/libs -m libcocotbvpi_icarus sim_build/sim.vvp
+	MODULE=test TESTCASE= TOPLEVEL=tb TOPLEVEL_LANG=verilog `which vvp` -M $(COCOTB_PREFIX)/cocotb/libs -m libcocotbvpi_icarus sim_build/sim.vvp
 
 clean:
 	find . -name __pycache__ -exec rm -fR {} +