From f9bb86521c0b449ec83cdaf6eae32055e662ea69 Mon Sep 17 00:00:00 2001 From: Simone Corbetta Date: Tue, 2 Apr 2024 15:17:01 +0200 Subject: [PATCH] - Docs update --- docs/info.md | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/docs/info.md b/docs/info.md index b2d06b8..3797674 100644 --- a/docs/info.md +++ b/docs/info.md @@ -8,7 +8,7 @@ of registers for control and observation. The neuron core works on 8 (eight) bit arithmetic with 5 (five) reserved for the fraction. # Neuron internals -The next figure shows the simplified block diargram of the Neuron. +The next figure shows the simplified block diagram of the Neuron. ![Neuron architecture](Neuron.png) @@ -116,6 +116,20 @@ table. # Configuration The configuration of the neuron is implemented by means of local registers that hold the values for the weights and the bias. In addition, control registers are used to trigger the neuron operations. +All resigsters are 8 (eight) bits wide + +| REGISTER | OFFSET | TYPE | CONTENTS | +|-|-|-|-| +| `WEIGHT_0` | 0x0 | R/W | Weight of input #0 | +| `WEIGHT_1` | 0x1 | R/W | Weight of input #1 | +| `BIAS` | 0x2 | R/W | Bias | +| `VALUE_IN` | 0x3 | R/W | Input value | +| `CTRL` | 0x4 | R/W | Control register | +| `STATUS` | 0x5 | R | Status register | +| `RESULT` | 0x6 | R | Neuron solution | +| `MULT_RESULT` | 0x7 | R | Intermediate multiplie result | +| `ADD_RESULT` | 0x8 | R | Intermediate adder result w/o bias | +| `BIAS_ADD_RESULT` | 0x9 | R | Intermediate adder result w/ bias | # External hardware The main clock `clk` is generated by the on-board RP2040 chip. It is used solely for debug purposes.