From 9d33a943bdd6dc81ecb5c075038fc3621ed00ea8 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov <19325847+AndreySmirnov81@users.noreply.github.com> Date: Mon, 14 Mar 2022 12:40:02 +0300 Subject: [PATCH 1/2] rcc: delete `rcc` param. from `Enable` and `Reset` --- src/adc.rs | 11 ++++------- src/afio.rs | 7 +++---- src/can.rs | 8 +++----- src/crc.rs | 5 ++--- src/dma.rs | 5 ++--- src/gpio.rs | 7 +++---- src/i2c.rs | 7 +++---- src/rcc.rs | 14 ++++++-------- src/rcc/enable.rs | 15 ++++++++++----- src/serial.rs | 7 +++---- src/spi.rs | 12 +++++------- src/timer.rs | 22 +++++++--------------- src/usb.rs | 14 +++++--------- 13 files changed, 56 insertions(+), 78 deletions(-) diff --git a/src/adc.rs b/src/adc.rs index 873b5b58..322b48b1 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -13,7 +13,7 @@ use core::sync::atomic::{self, Ordering}; use cortex_m::asm::delay; use embedded_dma::WriteBuffer; -use crate::pac::{self, RCC}; +use crate::pac; /// Continuous mode pub struct Continuous; @@ -271,18 +271,15 @@ macro_rules! adc_hal { } fn reset(&mut self) { - let rcc = unsafe { &(*RCC::ptr()) }; - <$ADC>::reset(rcc); + <$ADC>::reset(); } fn enable_clock(&mut self) { - let rcc = unsafe { &(*RCC::ptr()) }; - <$ADC>::enable(rcc); + <$ADC>::enable(); } fn disable_clock(&mut self) { - let rcc = unsafe { &(*RCC::ptr()) }; - <$ADC>::disable(rcc); + <$ADC>::disable(); } fn calibrate(&mut self) { diff --git a/src/afio.rs b/src/afio.rs index ef5c9359..038098ff 100644 --- a/src/afio.rs +++ b/src/afio.rs @@ -1,5 +1,5 @@ //! # Alternate Function I/Os -use crate::pac::{afio, AFIO, RCC}; +use crate::pac::{afio, AFIO}; use crate::rcc::{Enable, Reset}; @@ -13,9 +13,8 @@ pub trait AfioExt { impl AfioExt for AFIO { fn constrain(self) -> Parts { - let rcc = unsafe { &(*RCC::ptr()) }; - AFIO::enable(rcc); - AFIO::reset(rcc); + AFIO::enable(); + AFIO::reset(); Parts { evcr: EVCR { _0: () }, diff --git a/src/can.rs b/src/can.rs index 7073763d..4af95f63 100644 --- a/src/can.rs +++ b/src/can.rs @@ -21,7 +21,7 @@ use crate::afio::MAPR; use crate::gpio::{self, Alternate, Input}; -use crate::pac::{self, RCC}; +use crate::pac; pub trait Pins: crate::Sealed { type Instance; @@ -95,8 +95,7 @@ where /// prevent accidental shared usage. #[cfg(not(feature = "connectivity"))] pub fn new(can: Instance, _usb: pac::USB) -> Can { - let rcc = unsafe { &(*RCC::ptr()) }; - Instance::enable(rcc); + Instance::enable(); Can { _peripheral: can } } @@ -104,8 +103,7 @@ where /// Creates a CAN interaface. #[cfg(feature = "connectivity")] pub fn new(can: Instance) -> Can { - let rcc = unsafe { &(*RCC::ptr()) }; - Instance::enable(rcc); + Instance::enable(); Can { _peripheral: can } } diff --git a/src/crc.rs b/src/crc.rs index 252ee171..6b163154 100644 --- a/src/crc.rs +++ b/src/crc.rs @@ -1,6 +1,6 @@ //! CRC -use crate::pac::{CRC, RCC}; +use crate::pac::CRC; use crate::rcc::Enable; /// Extension trait to constrain the CRC peripheral @@ -12,8 +12,7 @@ pub trait CrcExt { impl CrcExt for CRC { fn new(self) -> Crc { - let rcc = unsafe { &(*RCC::ptr()) }; - CRC::enable(rcc); + CRC::enable(); Crc { crc: self } } diff --git a/src/dma.rs b/src/dma.rs index d215861c..a93b41e8 100644 --- a/src/dma.rs +++ b/src/dma.rs @@ -124,7 +124,7 @@ macro_rules! dma { pub mod $dmaX { use core::{sync::atomic::{self, Ordering}, ptr, mem, convert::TryFrom}; - use crate::pac::{RCC, $DMAX, dma1}; + use crate::pac::{$DMAX, dma1}; use crate::dma::{CircBuffer, DmaExt, Error, Event, Half, Transfer, W, RxDma, TxDma, RxTxDma, TransferPayload}; use crate::rcc::Enable; @@ -447,8 +447,7 @@ macro_rules! dma { type Channels = Channels; fn split(self) -> Channels { - let rcc = unsafe { &(*RCC::ptr()) }; - $DMAX::enable(rcc); + $DMAX::enable(); // reset the DMA control registers (stops all on-going transfers) $( diff --git a/src/gpio.rs b/src/gpio.rs index 190729a9..cb26501f 100644 --- a/src/gpio.rs +++ b/src/gpio.rs @@ -340,7 +340,7 @@ macro_rules! gpio { ]) => { /// GPIO pub mod $gpiox { - use crate::pac::{$GPIOX, RCC}; + use crate::pac::$GPIOX; use crate::rcc::{Enable, Reset}; use super::{Active, Floating, GpioExt, Input, PartiallyErasedPin, ErasedPin, Pin, Cr}; #[allow(unused)] @@ -366,9 +366,8 @@ macro_rules! gpio { type Parts = Parts; fn split(self) -> Parts { - let rcc = unsafe { &(*RCC::ptr()) }; - $GPIOX::enable(rcc); - $GPIOX::reset(rcc); + $GPIOX::enable(); + $GPIOX::reset(); Parts { crl: Cr::<$port_id, false>(()), diff --git a/src/i2c.rs b/src/i2c.rs index 532d0d05..37c688fe 100644 --- a/src/i2c.rs +++ b/src/i2c.rs @@ -7,7 +7,7 @@ use crate::afio::MAPR; use crate::gpio::{self, Alternate, OpenDrain}; use crate::hal::blocking::i2c::{Read, Write, WriteRead}; -use crate::pac::{DWT, I2C1, I2C2, RCC}; +use crate::pac::{DWT, I2C1, I2C2}; use crate::rcc::{BusClock, Clocks, Enable, Reset}; use crate::time::{kHz, Hertz}; use core::ops::Deref; @@ -166,9 +166,8 @@ where /// Configures the I2C peripheral to work in master mode fn configure>(i2c: I2C, pins: PINS, mode: M, clocks: Clocks) -> Self { let mode = mode.into(); - let rcc = unsafe { &(*RCC::ptr()) }; - I2C::enable(rcc); - I2C::reset(rcc); + I2C::enable(); + I2C::reset(); let pclk1 = I2C::clock(&clocks); diff --git a/src/rcc.rs b/src/rcc.rs index c12bdd3c..06aa920c 100644 --- a/src/rcc.rs +++ b/src/rcc.rs @@ -76,8 +76,7 @@ impl APB1 { impl APB1 { /// Set power interface clock (PWREN) bit in RCC_APB1ENR pub fn set_pwren() { - let rcc = unsafe { &*RCC::ptr() }; - PWR::enable(rcc); + PWR::enable(); } } @@ -309,9 +308,8 @@ impl BKP { /// Enables write access to the registers in the backup domain pub fn constrain(self, bkp: crate::pac::BKP, pwr: &mut PWR) -> BackupDomain { // Enable the backup interface by setting PWREN and BKPEN - let rcc = unsafe { &(*RCC::ptr()) }; - crate::pac::BKP::enable(rcc); - crate::pac::PWR::enable(rcc); + crate::pac::BKP::enable(); + crate::pac::PWR::enable(); // Enable access to the backup registers pwr.cr.modify(|_r, w| w.dbp().set_bit()); @@ -470,12 +468,12 @@ pub trait RccBus: crate::Sealed { /// Enable/disable peripheral pub trait Enable: RccBus { - fn enable(rcc: &rcc::RegisterBlock); - fn disable(rcc: &rcc::RegisterBlock); + fn enable(); + fn disable(); } /// Reset peripheral pub trait Reset: RccBus { - fn reset(rcc: &rcc::RegisterBlock); + fn reset(); } #[derive(Clone, Copy, Debug, PartialEq)] diff --git a/src/rcc/enable.rs b/src/rcc/enable.rs index a0374e97..bab4db4e 100644 --- a/src/rcc/enable.rs +++ b/src/rcc/enable.rs @@ -11,13 +11,15 @@ macro_rules! bus { } impl Enable for crate::pac::$PER { #[inline(always)] - fn enable(rcc: &rcc::RegisterBlock) { + fn enable() { + let rcc = unsafe { &(*RCC::ptr()) }; unsafe { bb::set(Self::Bus::enr(rcc), $bit); } } #[inline(always)] - fn disable(rcc: &rcc::RegisterBlock) { + fn disable() { + let rcc = unsafe { &(*RCC::ptr()) }; unsafe { bb::clear(Self::Bus::enr(rcc), $bit); } @@ -25,7 +27,8 @@ macro_rules! bus { } impl Reset for crate::pac::$PER { #[inline(always)] - fn reset(rcc: &rcc::RegisterBlock) { + fn reset() { + let rcc = unsafe { &(*RCC::ptr()) }; unsafe { bb::set(Self::Bus::rstr(rcc), $bit); bb::clear(Self::Bus::rstr(rcc), $bit); @@ -46,13 +49,15 @@ macro_rules! ahb_bus { } impl Enable for crate::pac::$PER { #[inline(always)] - fn enable(rcc: &rcc::RegisterBlock) { + fn enable() { + let rcc = unsafe { &(*RCC::ptr()) }; unsafe { bb::set(Self::Bus::enr(rcc), $bit); } } #[inline(always)] - fn disable(rcc: &rcc::RegisterBlock) { + fn disable() { + let rcc = unsafe { &(*RCC::ptr()) }; unsafe { bb::clear(Self::Bus::enr(rcc), $bit); } diff --git a/src/serial.rs b/src/serial.rs index afd396cf..b458e886 100644 --- a/src/serial.rs +++ b/src/serial.rs @@ -70,7 +70,7 @@ use embedded_dma::{ReadBuffer, WriteBuffer}; use crate::afio::MAPR; use crate::dma::{dma1, CircBuffer, RxDma, Transfer, TxDma, R, W}; use crate::gpio::{self, Alternate, Input}; -use crate::pac::{RCC, USART1, USART2, USART3}; +use crate::pac::{USART1, USART2, USART3}; use crate::rcc::{BusClock, Clocks, Enable, Reset}; use crate::time::{Bps, U32Ext}; @@ -292,9 +292,8 @@ impl Serial { PINS: Pins, { // Enable and reset USART - let rcc = unsafe { &(*RCC::ptr()) }; - USART::enable(rcc); - USART::reset(rcc); + USART::enable(); + USART::reset(); PINS::remap(mapr); diff --git a/src/spi.rs b/src/spi.rs index 48bc9071..bcc2b289 100644 --- a/src/spi.rs +++ b/src/spi.rs @@ -37,7 +37,7 @@ use core::ops::Deref; use core::ptr; pub use crate::hal::spi::{FullDuplex, Mode, Phase, Polarity}; -use crate::pac::{self, RCC}; +use crate::pac; use crate::afio::MAPR; use crate::dma::dma1; @@ -468,9 +468,8 @@ where { fn configure(spi: SPI, pins: PINS, mode: Mode, freq: Hertz, clocks: Clocks) -> Self { // enable or reset SPI - let rcc = unsafe { &(*RCC::ptr()) }; - SPI::enable(rcc); - SPI::reset(rcc); + SPI::enable(); + SPI::reset(); // disable SS output spi.cr2.write(|w| w.ssoe().clear_bit()); @@ -540,9 +539,8 @@ where { fn configure(spi: SPI, pins: PINS, mode: Mode) -> Self { // enable or reset SPI - let rcc = unsafe { &(*RCC::ptr()) }; - SPI::enable(rcc); - SPI::reset(rcc); + SPI::enable(); + SPI::reset(); // disable SS output spi.cr2.write(|w| w.ssoe().clear_bit()); diff --git a/src/timer.rs b/src/timer.rs index 17392940..6907d532 100644 --- a/src/timer.rs +++ b/src/timer.rs @@ -49,7 +49,7 @@ #![allow(non_upper_case_globals)] use crate::bb; -use crate::pac::{self, DBGMCU as DBG, RCC}; +use crate::pac::{self, DBGMCU as DBG}; use crate::rcc::{self, Clocks}; use core::convert::TryFrom; @@ -636,13 +636,9 @@ macro_rules! with_pwm { impl Timer { /// Initialize timer pub fn new(tim: TIM, clocks: &Clocks) -> Self { - unsafe { - //NOTE(unsafe) this reference will only be used for atomic writes with no side effects - let rcc = &(*RCC::ptr()); - // Enable and reset the timer peripheral - TIM::enable(rcc); - TIM::reset(rcc); - } + // Enable and reset the timer peripheral + TIM::enable(); + TIM::reset(); Self { clk: TIM::timer_clock(clocks), @@ -713,13 +709,9 @@ pub type FTimerMs = FTimer; impl FTimer { /// Initialize timer pub fn new(tim: TIM, clocks: &Clocks) -> Self { - unsafe { - //NOTE(unsafe) this reference will only be used for atomic writes with no side effects - let rcc = &(*RCC::ptr()); - // Enable and reset the timer peripheral - TIM::enable(rcc); - TIM::reset(rcc); - } + // Enable and reset the timer peripheral + TIM::enable(); + TIM::reset(); let mut t = Self { tim }; t.configure(clocks); diff --git a/src/usb.rs b/src/usb.rs index e457d9f0..4bfede8c 100644 --- a/src/usb.rs +++ b/src/usb.rs @@ -4,7 +4,7 @@ //! See https://github.com/stm32-rs/stm32f1xx-hal/tree/master/examples //! for usage examples. -use crate::pac::{RCC, USB}; +use crate::pac::USB; use crate::rcc::{Enable, Reset}; use stm32_usbd::UsbPeripheral; @@ -28,14 +28,10 @@ unsafe impl UsbPeripheral for Peripheral { const EP_MEMORY_ACCESS_2X16: bool = false; fn enable() { - unsafe { - let rcc = &*RCC::ptr(); - - // Enable USB peripheral - USB::enable(rcc); - // Reset USB peripheral - USB::reset(rcc); - } + // Enable USB peripheral + USB::enable(); + // Reset USB peripheral + USB::reset(); } fn startup_delay() { From 45cce7d46d4154b1c069c6225502d0be51c80886 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov <19325847+AndreySmirnov81@users.noreply.github.com> Date: Mon, 14 Mar 2022 15:20:04 +0300 Subject: [PATCH 2/2] rcc: access to `Enable` and `Reset` for owner only --- src/adc.rs | 6 +++--- src/afio.rs | 4 ++-- src/can.rs | 4 ++-- src/crc.rs | 2 +- src/dma.rs | 2 +- src/gpio.rs | 4 ++-- src/i2c.rs | 4 ++-- src/rcc.rs | 17 +++++------------ src/rcc/enable.rs | 10 +++++----- src/serial.rs | 4 ++-- src/spi.rs | 8 ++++---- src/timer.rs | 8 ++++---- src/usb.rs | 6 ++++-- 13 files changed, 37 insertions(+), 42 deletions(-) diff --git a/src/adc.rs b/src/adc.rs index 322b48b1..072b523d 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -271,15 +271,15 @@ macro_rules! adc_hal { } fn reset(&mut self) { - <$ADC>::reset(); + self.rb.reset(); } fn enable_clock(&mut self) { - <$ADC>::enable(); + self.rb.enable(); } fn disable_clock(&mut self) { - <$ADC>::disable(); + self.rb.disable(); } fn calibrate(&mut self) { diff --git a/src/afio.rs b/src/afio.rs index 038098ff..297b6777 100644 --- a/src/afio.rs +++ b/src/afio.rs @@ -13,8 +13,8 @@ pub trait AfioExt { impl AfioExt for AFIO { fn constrain(self) -> Parts { - AFIO::enable(); - AFIO::reset(); + self.enable(); + self.reset(); Parts { evcr: EVCR { _0: () }, diff --git a/src/can.rs b/src/can.rs index 4af95f63..3ea598a6 100644 --- a/src/can.rs +++ b/src/can.rs @@ -95,7 +95,7 @@ where /// prevent accidental shared usage. #[cfg(not(feature = "connectivity"))] pub fn new(can: Instance, _usb: pac::USB) -> Can { - Instance::enable(); + can.enable(); Can { _peripheral: can } } @@ -103,7 +103,7 @@ where /// Creates a CAN interaface. #[cfg(feature = "connectivity")] pub fn new(can: Instance) -> Can { - Instance::enable(); + can.enable(); Can { _peripheral: can } } diff --git a/src/crc.rs b/src/crc.rs index 6b163154..30087eb9 100644 --- a/src/crc.rs +++ b/src/crc.rs @@ -12,7 +12,7 @@ pub trait CrcExt { impl CrcExt for CRC { fn new(self) -> Crc { - CRC::enable(); + self.enable(); Crc { crc: self } } diff --git a/src/dma.rs b/src/dma.rs index a93b41e8..92ab00ac 100644 --- a/src/dma.rs +++ b/src/dma.rs @@ -447,7 +447,7 @@ macro_rules! dma { type Channels = Channels; fn split(self) -> Channels { - $DMAX::enable(); + self.enable(); // reset the DMA control registers (stops all on-going transfers) $( diff --git a/src/gpio.rs b/src/gpio.rs index cb26501f..eab4236f 100644 --- a/src/gpio.rs +++ b/src/gpio.rs @@ -366,8 +366,8 @@ macro_rules! gpio { type Parts = Parts; fn split(self) -> Parts { - $GPIOX::enable(); - $GPIOX::reset(); + self.enable(); + self.reset(); Parts { crl: Cr::<$port_id, false>(()), diff --git a/src/i2c.rs b/src/i2c.rs index 37c688fe..fabc4c34 100644 --- a/src/i2c.rs +++ b/src/i2c.rs @@ -166,8 +166,8 @@ where /// Configures the I2C peripheral to work in master mode fn configure>(i2c: I2C, pins: PINS, mode: M, clocks: Clocks) -> Self { let mode = mode.into(); - I2C::enable(); - I2C::reset(); + i2c.enable(); + i2c.reset(); let pclk1 = I2C::clock(&clocks); diff --git a/src/rcc.rs b/src/rcc.rs index 06aa920c..9039788d 100644 --- a/src/rcc.rs +++ b/src/rcc.rs @@ -73,13 +73,6 @@ impl APB1 { } } -impl APB1 { - /// Set power interface clock (PWREN) bit in RCC_APB1ENR - pub fn set_pwren() { - PWR::enable(); - } -} - /// Advanced Peripheral Bus 2 (APB2) registers pub struct APB2 { _0: (), @@ -308,8 +301,8 @@ impl BKP { /// Enables write access to the registers in the backup domain pub fn constrain(self, bkp: crate::pac::BKP, pwr: &mut PWR) -> BackupDomain { // Enable the backup interface by setting PWREN and BKPEN - crate::pac::BKP::enable(); - crate::pac::PWR::enable(); + bkp.enable(); + pwr.enable(); // Enable access to the backup registers pwr.cr.modify(|_r, w| w.dbp().set_bit()); @@ -468,12 +461,12 @@ pub trait RccBus: crate::Sealed { /// Enable/disable peripheral pub trait Enable: RccBus { - fn enable(); - fn disable(); + fn enable(&self); + fn disable(&self); } /// Reset peripheral pub trait Reset: RccBus { - fn reset(); + fn reset(&self); } #[derive(Clone, Copy, Debug, PartialEq)] diff --git a/src/rcc/enable.rs b/src/rcc/enable.rs index bab4db4e..b1b0be27 100644 --- a/src/rcc/enable.rs +++ b/src/rcc/enable.rs @@ -11,14 +11,14 @@ macro_rules! bus { } impl Enable for crate::pac::$PER { #[inline(always)] - fn enable() { + fn enable(&self) { let rcc = unsafe { &(*RCC::ptr()) }; unsafe { bb::set(Self::Bus::enr(rcc), $bit); } } #[inline(always)] - fn disable() { + fn disable(&self) { let rcc = unsafe { &(*RCC::ptr()) }; unsafe { bb::clear(Self::Bus::enr(rcc), $bit); @@ -27,7 +27,7 @@ macro_rules! bus { } impl Reset for crate::pac::$PER { #[inline(always)] - fn reset() { + fn reset(&self) { let rcc = unsafe { &(*RCC::ptr()) }; unsafe { bb::set(Self::Bus::rstr(rcc), $bit); @@ -49,14 +49,14 @@ macro_rules! ahb_bus { } impl Enable for crate::pac::$PER { #[inline(always)] - fn enable() { + fn enable(&self) { let rcc = unsafe { &(*RCC::ptr()) }; unsafe { bb::set(Self::Bus::enr(rcc), $bit); } } #[inline(always)] - fn disable() { + fn disable(&self) { let rcc = unsafe { &(*RCC::ptr()) }; unsafe { bb::clear(Self::Bus::enr(rcc), $bit); diff --git a/src/serial.rs b/src/serial.rs index b458e886..63aff0fb 100644 --- a/src/serial.rs +++ b/src/serial.rs @@ -292,8 +292,8 @@ impl Serial { PINS: Pins, { // Enable and reset USART - USART::enable(); - USART::reset(); + usart.enable(); + usart.reset(); PINS::remap(mapr); diff --git a/src/spi.rs b/src/spi.rs index bcc2b289..4a88fcb8 100644 --- a/src/spi.rs +++ b/src/spi.rs @@ -468,8 +468,8 @@ where { fn configure(spi: SPI, pins: PINS, mode: Mode, freq: Hertz, clocks: Clocks) -> Self { // enable or reset SPI - SPI::enable(); - SPI::reset(); + spi.enable(); + spi.reset(); // disable SS output spi.cr2.write(|w| w.ssoe().clear_bit()); @@ -539,8 +539,8 @@ where { fn configure(spi: SPI, pins: PINS, mode: Mode) -> Self { // enable or reset SPI - SPI::enable(); - SPI::reset(); + spi.enable(); + spi.reset(); // disable SS output spi.cr2.write(|w| w.ssoe().clear_bit()); diff --git a/src/timer.rs b/src/timer.rs index 6907d532..2c62beff 100644 --- a/src/timer.rs +++ b/src/timer.rs @@ -637,8 +637,8 @@ impl Timer { /// Initialize timer pub fn new(tim: TIM, clocks: &Clocks) -> Self { // Enable and reset the timer peripheral - TIM::enable(); - TIM::reset(); + tim.enable(); + tim.reset(); Self { clk: TIM::timer_clock(clocks), @@ -710,8 +710,8 @@ impl FTimer { /// Initialize timer pub fn new(tim: TIM, clocks: &Clocks) -> Self { // Enable and reset the timer peripheral - TIM::enable(); - TIM::reset(); + tim.enable(); + tim.reset(); let mut t = Self { tim }; t.configure(clocks); diff --git a/src/usb.rs b/src/usb.rs index 4bfede8c..69e621a6 100644 --- a/src/usb.rs +++ b/src/usb.rs @@ -28,10 +28,12 @@ unsafe impl UsbPeripheral for Peripheral { const EP_MEMORY_ACCESS_2X16: bool = false; fn enable() { + // TODO: use self.usb, after adding the &self parameter + let usb = unsafe { crate::pac::Peripherals::steal().USB }; // Enable USB peripheral - USB::enable(); + usb.enable(); // Reset USB peripheral - USB::reset(); + usb.reset(); } fn startup_delay() {