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rah.peri.xml
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<?xml version="1.0" encoding="UTF-8"?>
<efxpt:design_db name="rah" device_def="T120F324" location="/home/dj/soft/rah-bit" version="2023.2.307" db_version="20232999" last_change_date="Mon May 27 11:58:50 2024" xmlns:efxpt="http://www.efinixinc.com/peri_design_db" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/peri_design_db peri_design_db.xsd ">
<efxpt:device_info>
<efxpt:iobank_info>
<efxpt:iobank name="1A" iostd="3.3 V LVTTL / LVCMOS"/>
<efxpt:iobank name="1B_1C" iostd="3.3 V LVTTL / LVCMOS"/>
<efxpt:iobank name="1D_1E_1F_1G" iostd="3.3 V LVTTL / LVCMOS"/>
<efxpt:iobank name="2D" iostd="3.3 V LVTTL / LVCMOS"/>
<efxpt:iobank name="2E" iostd="3.3 V LVTTL / LVCMOS"/>
<efxpt:iobank name="2F" iostd="3.3 V LVTTL / LVCMOS"/>
<efxpt:iobank name="3A" iostd="1.2 V"/>
<efxpt:iobank name="3B" iostd="1.2 V"/>
<efxpt:iobank name="3D_TR_BR" iostd="3.3 V LVTTL / LVCMOS"/>
<efxpt:iobank name="4E" iostd="3.3 V LVTTL / LVCMOS"/>
<efxpt:iobank name="4F" iostd="3.3 V LVTTL / LVCMOS"/>
<efxpt:iobank name="BL" iostd="1.2 V"/>
<efxpt:iobank name="TL" iostd="1.2 V"/>
</efxpt:iobank_info>
<efxpt:ctrl_info>
<efxpt:ctrl name="cfg" ctrl_def="CONFIG_CTRL0" clock_name="" is_clk_invert="false" cbsel_bus_name="cfg_CBSEL" config_ctrl_name="cfg_CONFIG" ena_capture_name="cfg_ENA" error_status_name="cfg_ERROR" um_signal_status_name="cfg_USR_STATUS" is_remote_update_enable="false" is_user_mode_enable="false"/>
</efxpt:ctrl_info>
</efxpt:device_info>
<efxpt:gpio_info device_def="T120F324">
<efxpt:gpio name="mipi_refclk" gpio_def="GPIOR_169" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="mipi_refclk" name_ddio_lo="" conn_type="mipi_clkin" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
</efxpt:gpio>
<efxpt:gpio name="mipi_rx_refclk" gpio_def="GPIOR_188" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="mipi_rx_refclk" name_ddio_lo="" conn_type="pll_clkin" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
</efxpt:gpio>
<efxpt:gpio name="mipi_tx_refclk" gpio_def="GPIOL_15" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="mipi_tx_refclk" name_ddio_lo="" conn_type="pll_clkin" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
</efxpt:gpio>
<efxpt:gpio name="uart_rx_pin" gpio_def="GPIOT_RXN24" mode="input" bus_name="" is_lvds_gpio="true" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="uart_rx_pin" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="weak pullup" is_schmitt_trigger="false" ddio_type="none"/>
</efxpt:gpio>
<efxpt:gpio name="uart_tx_pin" gpio_def="GPIOT_RXP24" mode="output" bus_name="" is_lvds_gpio="true" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="uart_tx_pin" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
</efxpt:gpio>
<efxpt:global_unused_config state="input with weak pullup"/>
</efxpt:gpio_info>
<efxpt:pll_info>
<efxpt:pll name="pll_inst1" pll_def="PLL_BR2" ref_clock_name="" ref_clock_freq="10.0000" multiplier="108" pre_divider="1" post_divider="2" reset_name="" locked_name="" is_ipfrz="false" is_bypass_lock="true">
<efxpt:output_clock name="rx_pixel_clk" number="0" out_divider="10" adv_out_phase_shift="0"/>
<efxpt:output_clock name="mipi_rx_cal_clk" number="1" out_divider="5" adv_out_phase_shift="0"/>
<efxpt:adv_prop ref_clock_mode="external" ref_clock1_name="" ext_ref_clock_id="2" clksel_name="" feedback_clock_name="" feedback_mode="internal"/>
</efxpt:pll>
<efxpt:pll name="pll_inst2" pll_def="PLL_BL0" ref_clock_name="" ref_clock_freq="30.0000" multiplier="36" pre_divider="1" post_divider="2" reset_name="" locked_name="" is_ipfrz="false" is_bypass_lock="true">
<efxpt:output_clock name="tx_pixel_clk" number="0" out_divider="10" adv_out_phase_shift="0"/>
<efxpt:output_clock name="tx_vga_clk" number="2" out_divider="5" adv_out_phase_shift="0"/>
<efxpt:output_clock name="tx_esc_clk" number="1" out_divider="5" adv_out_phase_shift="0"/>
<efxpt:adv_prop ref_clock_mode="external" ref_clock1_name="" ext_ref_clock_id="2" clksel_name="" feedback_clock_name="" feedback_mode="internal"/>
</efxpt:pll>
</efxpt:pll_info>
<efxpt:lvds_info/>
<efxpt:mipi_info>
<efxpt:mipi name="my_mipi_tx" mipi_def="MIPI_TX0" ops_type="tx">
<efxpt:mtx_info ref_clock_freq="25.0" phy_tx_freq_code="204" is_cont_phy_clocking="false" esc_clock_freq="20.0">
<efxpt:gen_pin>
<efxpt:pin name="tx_pixel_clk" type_name="PIXEL_CLK" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="tx_esc_clk" type_name="ESC_CLK" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="my_mipi_tx_DPHY_RSTN" type_name="DPHY_RSTN" is_bus="false"/>
<efxpt:pin name="my_mipi_tx_RSTN" type_name="RSTN" is_bus="false"/>
<efxpt:pin name="my_mipi_tx_VSYNC" type_name="VSYNC" is_bus="false"/>
<efxpt:pin name="my_mipi_tx_HSYNC" type_name="HSYNC" is_bus="false"/>
<efxpt:pin name="my_mipi_tx_VALID" type_name="VALID" is_bus="false"/>
<efxpt:pin name="my_mipi_tx_FRAME_MODE" type_name="FRAME_MODE" is_bus="false"/>
<efxpt:pin name="my_mipi_tx_ULPS_CLK_ENTER" type_name="ULPS_CLK_ENTER" is_bus="false"/>
<efxpt:pin name="my_mipi_tx_ULPS_CLK_EXIT" type_name="ULPS_CLK_EXIT" is_bus="false"/>
<efxpt:pin name="my_mipi_tx_LANES" type_name="LANES" is_bus="true"/>
<efxpt:pin name="my_mipi_tx_HRES" type_name="HRES" is_bus="true"/>
<efxpt:pin name="my_mipi_tx_DATA" type_name="DATA" is_bus="true"/>
<efxpt:pin name="my_mipi_tx_TYPE" type_name="TYPE" is_bus="true"/>
<efxpt:pin name="my_mipi_tx_VC" type_name="VC" is_bus="true"/>
<efxpt:pin name="my_mipi_tx_ULPS_ENTER" type_name="ULPS_ENTER" is_bus="true"/>
<efxpt:pin name="my_mipi_tx_ULPS_EXIT" type_name="ULPS_EXIT" is_bus="true"/>
<efxpt:pin name="my_mipi_tx_TXDP" type_name="TXDP" is_bus="true"/>
<efxpt:pin name="my_mipi_tx_TXDN" type_name="TXDN" is_bus="true"/>
</efxpt:gen_pin>
<efxpt:phy_lane lane_id="0" logical_lane_id="0" is_pn_swap="false"/>
<efxpt:phy_lane lane_id="1" logical_lane_id="1" is_pn_swap="false"/>
<efxpt:phy_lane lane_id="2" logical_lane_id="4" is_pn_swap="false"/>
<efxpt:phy_lane lane_id="3" logical_lane_id="2" is_pn_swap="false"/>
<efxpt:phy_lane lane_id="4" logical_lane_id="3" is_pn_swap="false"/>
<efxpt:tx_timing t_clk_post="8" t_clk_trail="7" t_clk_prepare="2" t_clk_zero="3" t_clk_pre="2" t_hs_prepare="2" t_hs_zero="2" t_hs_trail="24"/>
</efxpt:mtx_info>
</efxpt:mipi>
<efxpt:mipi name="my_mipi_rx" mipi_def="MIPI_RX0" ops_type="rx">
<efxpt:mrx_info dphy_calib_clock_freq="100.0">
<efxpt:gen_pin>
<efxpt:pin name="rx_pixel_clk" type_name="PIXEL_CLK" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="mipi_rx_cal_clk" type_name="CAL_CLK" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="my_mipi_rx_DPHY_RSTN" type_name="DPHY_RSTN" is_bus="false"/>
<efxpt:pin name="my_mipi_rx_RSTN" type_name="RSTN" is_bus="false"/>
<efxpt:pin name="my_mipi_rx_VALID" type_name="VALID" is_bus="false"/>
<efxpt:pin name="my_mipi_rx_CLEAR" type_name="CLEAR" is_bus="false"/>
<efxpt:pin name="my_mipi_rx_ULPS_CLK" type_name="ULPS_CLK" is_bus="false"/>
<efxpt:pin name="my_mipi_rx_TST_CLK" type_name="TST_CLK" is_bus="false"/>
<efxpt:pin name="my_mipi_rx_DPHY_TST_CLK" type_name="DPHY_TST_CLK" is_bus="false"/>
<efxpt:pin name="my_mipi_rx_TST_LOAD" type_name="TST_LOAD" is_bus="false"/>
<efxpt:pin name="my_mipi_rx_TST_OUT" type_name="TST_OUT" is_bus="false"/>
<efxpt:pin name="my_mipi_rx_VC_ENA" type_name="VC_ENA" is_bus="true"/>
<efxpt:pin name="my_mipi_rx_LANES" type_name="LANES" is_bus="true"/>
<efxpt:pin name="my_mipi_rx_VSYNC" type_name="VSYNC" is_bus="true"/>
<efxpt:pin name="my_mipi_rx_HSYNC" type_name="HSYNC" is_bus="true"/>
<efxpt:pin name="my_mipi_rx_CNT" type_name="CNT" is_bus="true"/>
<efxpt:pin name="my_mipi_rx_DATA" type_name="DATA" is_bus="true"/>
<efxpt:pin name="my_mipi_rx_TYPE" type_name="TYPE" is_bus="true"/>
<efxpt:pin name="my_mipi_rx_VC" type_name="VC" is_bus="true"/>
<efxpt:pin name="my_mipi_rx_ERROR" type_name="ERROR" is_bus="true"/>
<efxpt:pin name="my_mipi_rx_ULPS" type_name="ULPS" is_bus="true"/>
<efxpt:pin name="my_mipi_rx_TST_DATA" type_name="TST_DATA" is_bus="true"/>
<efxpt:pin name="my_mipi_rx_RXDP" type_name="RXDP" is_bus="true"/>
<efxpt:pin name="my_mipi_rx_RXDN" type_name="RXDN" is_bus="true"/>
</efxpt:gen_pin>
<efxpt:phy_lane lane_id="0" logical_lane_id="0" is_pn_swap="false"/>
<efxpt:phy_lane lane_id="1" logical_lane_id="1" is_pn_swap="false"/>
<efxpt:phy_lane lane_id="2" logical_lane_id="4" is_pn_swap="false"/>
<efxpt:phy_lane lane_id="3" logical_lane_id="2" is_pn_swap="false"/>
<efxpt:phy_lane lane_id="4" logical_lane_id="3" is_pn_swap="false"/>
<efxpt:rx_timing t_clk_settle="9" t_hs_settle="8"/>
</efxpt:mrx_info>
</efxpt:mipi>
</efxpt:mipi_info>
<efxpt:jtag_info/>
<efxpt:ddr_info/>
</efxpt:design_db>