v3.2.0

Detailed changelog (since v3.1.0)

Note: This was already published previously. If you just got a second notification for this, it's because something went wrong when placing the original tag on the right commit, and the corresponding release was deleted by GitHub when the tag was adjusted. No action is required and if you previously pulled from the old tag, you still have the latest released code. Sorry for the inconvenience!

Decoder

• Added flags_read and flags_written masks to ZydisDecodedInstruction for more intuitive and performant access
• Added support for 4FMAPS multisource operands
• Added support for CET no-track prefix
• Fixed Load-op SwizzUpConv(F32)
• Fixed wrong eviction hint formatter-string
• Fixed MVEX rounding mode decoding
• Improved handling of 16-bit relative operands
• Improved general segment override handling
• XOP/VEX/EVEX is invalid in 16-bit real mode
• Scale base register of implicit SP/BP memory operands by stack- instead of address-size
• Set ZYDIS_ATTRIB_ACCEPTS_SEGMENT for non legacy instructions

Formatter

• Added formatter option to control printing of scale *1
• Fixed relative disp printing for 0 disps
• Fixed incorrect formatting of signed displacements
• Fixed formatting of offset for PTR operands
• Fixed {sae}/{rc} formatting
• Enhanced formatting for MIB operands
• Print missing {z} decorator for instructions with control-masking
• Print asterisk in front of absolute jmp/call address (AT&T)

Database

• Added AVX-512 FP16 instructions
• Added VNNI instructions
• Added HRESET instructions
• Added KEYLOCKER instructions
• Added TDX instructions
• Added AMD INVLPGB instructions
• Added AMD mcommit instruction
• Added SERIALIZE and TSX-LDTRK instructions
• Added AMD SNP instructions
• Added AMX instructions
• Added missing conditional-write registers for STOS{B|W|D|Q} and LODS{B|W|D|Q}
• Fixed privilege level of CET instructions
• Fixed decoding of RDSSPD in 64-bit mode
• Fixed segment register for leave instruction
• Fixed invlpga and pvalidate pseudo memory operand register width
• Fixed bsf/bsr destination operand action
• Fixed DI/SI operand access action for stos{b|w|d|q}/movs{b|w|d|q} instructions
• Fixed CET/VMX decoding in real mode
• Fixed ECX scaling for pcmpestri/vpcmpestri/pcmpistri/vpcmpistri
• Set fixed vector-length for EVEX instructions that ignore EVEX.LL (LIG)
• Removed impossible jcxz/jrcxz encodings
• Ignore segment override for memory operands with hardcoded ES segment
• Ignore segment override for BNDC{L|N|U}
• Display implicit pseudo memory operand for vmrun and vmsave
• Allow invlpgb with 16-bit address-size
• Change branch-type from short -> near for jkzd/jknzd

Misc

• Improve CMake files
• Fix buffer overflow and off-by-one in ZydisInfo tool