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Merge pull request chipsalliance#3871 from Apotell/names
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Add property to track end labels for scopes
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@alaindargelas
alaindargelas authored Sep 22, 2023
2 parents 0218651 + f3a8102 commit 49632f1
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Showing 65 changed files with 270 additions and 49 deletions.
30 changes: 23 additions & 7 deletions include/Surelog/Design/ModuleDefinition.h
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Expand Up @@ -98,22 +98,38 @@ class ModuleDefinition : public DesignComponent, public ClockingBlockHolder {
void setModuleArrays(std::vector<UHDM::module_array*>* modules) {
m_moduleArrays = modules;
}

std::vector<UHDM::ref_module*>* getRefModules() { return m_ref_modules; }
void setRefModules(std::vector<UHDM::ref_module*>* modules) {
m_ref_modules = modules;
}

UHDM::VectorOfprimitive* getPrimitives() { return m_subPrimitives; }
UHDM::VectorOfprimitive_array* getPrimitiveArrays() { return m_subPrimitiveArrays; }
UHDM::VectorOfgen_scope_array* getGenScopeArrays() { return m_subGenScopeArrays; }
UHDM::VectorOfprimitive_array* getPrimitiveArrays() {
return m_subPrimitiveArrays;
}
UHDM::VectorOfgen_scope_array* getGenScopeArrays() {
return m_subGenScopeArrays;
}
std::vector<UHDM::gen_stmt*>* getGenStmts() { return m_genStmts; }
void setPrimitives(UHDM::VectorOfprimitive* primitives) { m_subPrimitives = primitives; }
void setPrimitiveArrays(UHDM::VectorOfprimitive_array* primitives) { m_subPrimitiveArrays = primitives; }
void setGenScopeArrays(UHDM::VectorOfgen_scope_array* gen_arrays) { m_subGenScopeArrays = gen_arrays; }
void setGenStmts(std::vector<UHDM::gen_stmt*>* gen_stmts) { m_genStmts = gen_stmts; }
void setPrimitives(UHDM::VectorOfprimitive* primitives) {
m_subPrimitives = primitives;
}
void setPrimitiveArrays(UHDM::VectorOfprimitive_array* primitives) {
m_subPrimitiveArrays = primitives;
}
void setGenScopeArrays(UHDM::VectorOfgen_scope_array* gen_arrays) {
m_subGenScopeArrays = gen_arrays;
}
void setGenStmts(std::vector<UHDM::gen_stmt*>* gen_stmts) {
m_genStmts = gen_stmts;
}
std::string_view getEndLabel() const { return m_endLabel; }
void setEndLabel(std::string_view endLabel) { m_endLabel = endLabel; }

private:
const std::string m_name;
std::string m_endLabel;
ModPortSignalMap m_modportSignalMap;
ModPortClockingBlockMap m_modportClockingBlockMap;
ClassNameClassDefinitionMultiMap m_classDefinitions;
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4 changes: 4 additions & 0 deletions include/Surelog/Package/Package.h
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Expand Up @@ -84,8 +84,12 @@ class Package : public DesignComponent {

Package* getUnElabPackage() { return m_unElabPackage; }

std::string_view getEndLabel() const { return m_endLabel; }
void setEndLabel(std::string_view endLabel) { m_endLabel = endLabel; }

private:
std::string m_name;
std::string m_endLabel;
Library* m_library;
ExprBuilder m_exprBuilder;
ClassNameClassDefinitionMultiMap m_classDefinitions;
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4 changes: 4 additions & 0 deletions include/Surelog/Testbench/ClassDefinition.h
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Expand Up @@ -119,8 +119,12 @@ class ClassDefinition : public DesignComponent, public DataType {
return true;
}

std::string_view getEndLabel() const { return m_endLabel; }
void setEndLabel(std::string_view endLabel) { m_endLabel = endLabel; }

private:
std::string m_name;
std::string m_endLabel;
Library* m_library;
DesignComponent* m_container;
ClassDefinition* m_parent;
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4 changes: 4 additions & 0 deletions include/Surelog/Testbench/Program.h
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Expand Up @@ -69,8 +69,12 @@ class Program : public DesignComponent, public ClockingBlockHolder {
return true;
}

std::string_view getEndLabel() const { return m_endLabel; }
void setEndLabel(std::string_view endLabel) { m_endLabel = endLabel; }

private:
std::string m_name;
std::string m_endLabel;
Library* m_library;
ClassNameClassDefinitionMultiMap m_classDefinitions;

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1 change: 1 addition & 0 deletions src/DesignCompile/CompileClass.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -227,6 +227,7 @@ bool CompileClass::compile() {
if (fC->Type(fC->Parent(id)) != VObjectType::paClass_declaration)
break;
const std::string_view endLabel = fC->SymName(id);
m_class->setEndLabel(endLabel);
std::string_view moduleName =
StringUtils::ltrim_until(m_class->getName(), '@');
if (endLabel != moduleName) {
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2 changes: 2 additions & 0 deletions src/DesignCompile/CompileModule.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -897,6 +897,7 @@ bool CompileModule::collectModuleObjects_(CollectType collectType) {
if (fC->Type(fC->Parent(id)) != VObjectType::paModule_declaration)
break;
const std::string_view endLabel = fC->SymName(id);
m_module->setEndLabel(endLabel);
std::string_view moduleName = m_module->getName();
moduleName = StringUtils::ltrim_until(moduleName, '@');
moduleName = StringUtils::ltrim_until(moduleName, ':');
Expand Down Expand Up @@ -1382,6 +1383,7 @@ bool CompileModule::collectInterfaceObjects_(CollectType collectType) {
if (InterfaceIdentifier) {
NodeId label = fC->Child(InterfaceIdentifier);
const std::string_view endLabel = fC->SymName(label);
m_module->setEndLabel(endLabel);
std::string_view moduleName = m_module->getName();
moduleName = StringUtils::ltrim_until(moduleName, '@');
moduleName = StringUtils::ltrim_until(moduleName, ':');
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1 change: 1 addition & 0 deletions src/DesignCompile/CompilePackage.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -282,6 +282,7 @@ bool CompilePackage::collectObjects_(CollectType collectType, Reduce reduce) {
if (fC->Type(fC->Parent(id)) != VObjectType::paPackage_declaration)
break;
const std::string_view endLabel = fC->SymName(id);
m_package->setEndLabel(endLabel);
std::string_view moduleName =
StringUtils::ltrim_until(m_package->getName(), '@');
if (endLabel != moduleName) {
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1 change: 1 addition & 0 deletions src/DesignCompile/CompileProgram.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -342,6 +342,7 @@ bool CompileProgram::collectObjects_(CollectType collectType) {
if (fC->Type(fC->Parent(id)) != VObjectType::paProgram_declaration)
break;
const std::string_view endLabel = fC->SymName(id);
m_program->setEndLabel(endLabel);
std::string_view moduleName =
StringUtils::ltrim_until(m_program->getName(), '@');
if (endLabel != moduleName) {
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88 changes: 57 additions & 31 deletions src/DesignCompile/CompileStmt.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -274,8 +274,8 @@ VectorOfany* CompileHelper::compileStmt(DesignComponent* component,
NodeId item = fC->Child(the_stmt);
VectorOfany* stmts = s.MakeAnyVec();
UHDM::scope* scope = nullptr;
std::string label;
NodeId labelId;
std::string label, endLabel;
NodeId labelId, endLabelId;
if (fC->Type(item) == VObjectType::slStringConst) {
labelId = item;
item = fC->Sibling(item);
Expand All @@ -287,12 +287,26 @@ VectorOfany* CompileHelper::compileStmt(DesignComponent* component,
if (fC->Type(Label) == VObjectType::slStringConst) labelId = Label;
}
}

if (labelId) {
NodeId tempItem = item;
while (tempItem) {
if (fC->Type(tempItem) == VObjectType::paEND) {
if ((endLabelId = fC->Sibling(tempItem))) {
break;
}
}
tempItem = fC->Sibling(tempItem);
}
if (labelId || endLabelId) {
UHDM::named_begin* begin = s.MakeNamed_begin();
begin->Stmts(stmts);
label = fC->SymName(labelId);
begin->VpiName(label);
if (labelId) {
label = fC->SymName(labelId);
begin->VpiName(label);
}
if (endLabelId) {
endLabel = fC->SymName(endLabelId);
begin->VpiEndLabel(endLabel);
}
stmt = begin;
scope = begin;
} else {
Expand All @@ -304,26 +318,19 @@ VectorOfany* CompileHelper::compileStmt(DesignComponent* component,
}
scope->VpiParent(pstmt);
fC->populateCoreMembers(labelId, labelId, scope);
while (item) {
if (item && (fC->Type(item) == VObjectType::paEND)) {
if (NodeId endLabel = fC->Sibling(item)) {
const std::string_view endlabel = fC->SymName(endLabel);
if (endlabel != label) {
ErrorContainer* errors =
compileDesign->getCompiler()->getErrorContainer();
SymbolTable* symbols =
compileDesign->getCompiler()->getSymbolTable();
Location loc(fC->getFileId(), fC->Line(labelId),
fC->Column(labelId), symbols->registerSymbol(label));
Location loc2(fC->getFileId(), fC->Line(endLabel),
fC->Column(endLabel),
symbols->registerSymbol(endlabel));
Error err(ErrorDefinition::COMP_UNMATCHED_LABEL, loc, loc2);
errors->addError(err);
}
}
break;
}
if (labelId && endLabelId && (label != endLabel)) {
ErrorContainer* errors =
compileDesign->getCompiler()->getErrorContainer();
SymbolTable* symbols = compileDesign->getCompiler()->getSymbolTable();
Location loc(fC->getFileId(), fC->Line(labelId), fC->Column(labelId),
symbols->registerSymbol(label));
Location loc2(fC->getFileId(), fC->Line(endLabelId),
fC->Column(endLabelId),
symbols->registerSymbol(endLabel));
Error err(ErrorDefinition::COMP_UNMATCHED_LABEL, loc, loc2);
errors->addError(err);
}
while (item && (fC->Type(item) != VObjectType::paEND)) {
if (VectorOfany* cstmts =
compileStmt(component, fC, item, compileDesign, Reduce::No,
stmt, instance, muteErrors)) {
Expand Down Expand Up @@ -358,8 +365,8 @@ VectorOfany* CompileHelper::compileStmt(DesignComponent* component,
NodeId item = fC->Child(the_stmt);
VectorOfany* stmts = s.MakeAnyVec();
UHDM::scope* scope = nullptr;
std::string label;
NodeId labelId;
std::string label, endLabel;
NodeId labelId, endLabelId;
if (fC->Type(item) == VObjectType::slStringConst) {
labelId = item;
item = fC->Sibling(item);
Expand All @@ -371,11 +378,30 @@ VectorOfany* CompileHelper::compileStmt(DesignComponent* component,
if (fC->Type(Label) == VObjectType::slStringConst) labelId = Label;
}
}
if (labelId) {
// Get join label if any
NodeId tempItem = fC->Sibling(item);
while (tempItem) {
VObjectType type = fC->Type(tempItem);
if ((type == VObjectType::paJoin_keyword) ||
(type == VObjectType::paJoin_any_keyword) ||
(type == VObjectType::paJoin_none_keyword)) {
if ((endLabelId = fC->Sibling(tempItem))) {
break;
}
}
tempItem = fC->Sibling(tempItem);
}
if (labelId || endLabelId) {
UHDM::named_fork* fork = s.MakeNamed_fork();
fork->Stmts(stmts);
label = fC->SymName(labelId);
fork->VpiName(label);
if (labelId) {
label = fC->SymName(labelId);
fork->VpiName(label);
}
if (endLabelId) {
endLabel = fC->SymName(endLabelId);
fork->VpiEndLabel(endLabel);
}
stmt = fork;
scope = fork;
} else {
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9 changes: 9 additions & 0 deletions src/DesignCompile/UhdmWriter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -853,6 +853,7 @@ void UhdmWriter::writeClass(ClassDefinition* classDef,
class_defn* c = classDef->getUhdmDefinition();
m_componentMap.emplace(classDef, c);
c->VpiParent(parent);
c->VpiEndLabel(classDef->getEndLabel());
// Typepecs
VectorOftypespec* typespecs = s.MakeTypespecVec();
c->Typespecs(typespecs);
Expand Down Expand Up @@ -1044,6 +1045,7 @@ void reInstanceTypespec(Serializer& serializer, any* root, package* p) {

void UhdmWriter::writePackage(Package* pack, package* p, Serializer& s,
bool elaborated) {
p->VpiEndLabel(pack->getEndLabel());
p->VpiFullName(StrCat(pack->getName(), "::"));
VectorOfclass_defn* dest_classes = nullptr;

Expand Down Expand Up @@ -1177,6 +1179,8 @@ void UhdmWriter::writeModule(ModuleDefinition* mod, module_inst* m,
SignalMap portMap;
SignalMap netMap;

m->VpiEndLabel(mod->getEndLabel());

// Let decls
if (!mod->getLetStmts().empty()) {
VectorOflet_decl* decls = s.MakeLet_declVec();
Expand Down Expand Up @@ -1385,6 +1389,8 @@ void UhdmWriter::writeInterface(ModuleDefinition* mod, interface_inst* m,
SignalMap portMap;
SignalMap netMap;

m->VpiEndLabel(mod->getEndLabel());

// Let decls
if (!mod->getLetStmts().empty()) {
VectorOflet_decl* decls = s.MakeLet_declVec();
Expand Down Expand Up @@ -1537,6 +1543,9 @@ void UhdmWriter::writeProgram(Program* mod, program* m, Serializer& s,
SignalBaseClassMap signalBaseMap;
SignalMap portMap;
SignalMap netMap;

m->VpiEndLabel(mod->getEndLabel());

// Typepecs
VectorOftypespec* typespecs = s.MakeTypespecVec();
m->Typespecs(typespecs);
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4 changes: 4 additions & 0 deletions tests/AllPackageSignal/AllPackageSignal.log
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Original file line number Diff line number Diff line change
Expand Up @@ -461,6 +461,7 @@ design: (unnamed)
|vpiLhs:
\_parameter: (pkg_b::ParameterIntEqual4), line:17:17, endln:17:35
|vpiDefName:pkg_b
|vpiEndLabel:pkg_b
|uhdmallPackages:
\_package: pkg_a (pkg_a::), file:${SURELOG_DIR}/tests/AllPackageSignal/dut.sv, line:21:1, endln:34:19
|vpiParent:
Expand Down Expand Up @@ -945,6 +946,7 @@ design: (unnamed)
|vpiConstType:9
|vpiInstance:
\_package: pkg_a (pkg_a::), file:${SURELOG_DIR}/tests/AllPackageSignal/dut.sv, line:21:1, endln:34:19
|vpiEndLabel:pkg_a
|uhdmtopPackages:
\_package: pkg_b (pkg_b::), file:${SURELOG_DIR}/tests/AllPackageSignal/dut.sv, line:16:1, endln:18:19
|vpiParent:
Expand Down Expand Up @@ -989,6 +991,7 @@ design: (unnamed)
\_parameter: (pkg_b::ParameterIntEqual4), line:17:17, endln:17:35
|vpiDefName:pkg_b
|vpiTop:1
|vpiEndLabel:pkg_b
|uhdmtopPackages:
\_package: pkg_a (pkg_a::), file:${SURELOG_DIR}/tests/AllPackageSignal/dut.sv, line:21:1, endln:34:19
|vpiParent:
Expand Down Expand Up @@ -1474,6 +1477,7 @@ design: (unnamed)
|vpiConstType:9
|vpiInstance:
\_package: pkg_a (pkg_a::), file:${SURELOG_DIR}/tests/AllPackageSignal/dut.sv, line:21:1, endln:34:19
|vpiEndLabel:pkg_a
\_weaklyReferenced:
\_int_typespec: , line:17:13, endln:17:16
|vpiParent:
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1 change: 1 addition & 0 deletions tests/Assertions/Assertions.log
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Original file line number Diff line number Diff line change
Expand Up @@ -708,6 +708,7 @@ design: (work@m)
|vpiActual:
\_logic_net: (work@m.b), line:2:17, endln:2:18
|vpiAlwaysType:2
|vpiEndLabel:m
|uhdmtopModules:
\_module_inst: work@m (work@m), file:${SURELOG_DIR}/tests/Assertions/dut.sv, line:1:1, endln:13:14
|vpiName:work@m
Expand Down
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