Adicionando processador Grande Risco 5

LSC-Unicamp · Nov 29, 2024 · cd8beb6 · cd8beb6
1 parent 84cd3f2
commit cd8beb6
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Showing 46 changed files with 1,663 additions and 805 deletions.
diff --git a/config.json b/config.json
diff --git a/core/fpga.py b/core/fpga.py
@@ -154,7 +154,9 @@ def make_build_file(config: dict, board: str, toolchain_path: str) -> str:
         )
 
         for i in config['files']:
-            prefix = get_prefix(board, vhdl=i.endswith('.vhd'), sverilog=i.endswith('.sv'))
+            prefix = get_prefix(
+                board, vhdl=i.endswith('.vhd'), sverilog=i.endswith('.sv')
+            )
             file.write(prefix + f' {CURRENT_DIR}/' + i + '\n')
 
         file.write(base_config)

diff --git a/core/jenkins.py b/core/jenkins.py
@@ -111,7 +111,8 @@ def generate_jenkinsfile(
     elif is_verilog and not is_vhdl:
         # Verilog simulation command
         simulation_command = (
-            f'sh "iverilog -o simulation.out -g{lang_version} {extra_flags_str}'
+            f'sh "/eda/oss-cad-suite/bin/iverilog -o simulation.out -g{lang_version} \
+                {extra_flags_str}'
             + f' -s {config["top_module"]} {include_dirs} {files} {sim_files}"'
         )
     else:

diff --git a/jenkins_pipeline/AUK-V-Aethia.Jenkinsfile b/jenkins_pipeline/AUK-V-Aethia.Jenkinsfile
@@ -5,7 +5,7 @@ pipeline {
         stage('Git Clone') {
             steps {
                 sh 'rm -rf AUK-V-Aethia'
-                sh 'git clone --recursive https://github.com/veeYceeY/AUK-V-Aethia AUK-V-Aethia'
+                sh 'git clone --recursive --depth=1 https://github.com/veeYceeY/AUK-V-Aethia AUK-V-Aethia'
             }
         }
 
@@ -14,7 +14,7 @@ pipeline {
         stage('Simulation') {
             steps {
                 dir("AUK-V-Aethia") {
-                    sh "iverilog -o simulation.out -g2005  -s aukv  rtl/core/aukv.v rtl/core/aukv_alu.v rtl/core/aukv_csr_regfile.v rtl/core/aukv_decode.v rtl/core/aukv_execute.v rtl/core/aukv_fetch.v rtl/core/aukv_gpr_regfilie.v rtl/core/aukv_mem.v "
+                    sh "/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005                  -s aukv  rtl/core/aukv.v rtl/core/aukv_alu.v rtl/core/aukv_csr_regfile.v rtl/core/aukv_decode.v rtl/core/aukv_execute.v rtl/core/aukv_fetch.v rtl/core/aukv_gpr_regfilie.v rtl/core/aukv_mem.v "
                 }
             }
         }
@@ -27,27 +27,30 @@ pipeline {
                         lock(resource: 'colorlight_i9')
                     }
                     stages {
-                        stage('Síntese e PnR') {
+                        stage('Synthesis and PnR') {
                             steps {
                                 dir("AUK-V-Aethia") {
-                                    echo 'Iniciando síntese para FPGA colorlight_i9.'
-                                    sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p AUK-V-Aethia -b colorlight_i9'
+                                    echo 'Starting synthesis for FPGA colorlight_i9.'
+                                sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \
+                                            -p AUK-V-Aethia -b colorlight_i9'
                                 }
                             }
                         }
                         stage('Flash colorlight_i9') {
                             steps {
                                 dir("AUK-V-Aethia") {
-                                    echo 'FPGA colorlight_i9 bloqueada para flash.'
-                                    sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p AUK-V-Aethia -b colorlight_i9 -l'
+                                    echo 'Flashing FPGA colorlight_i9.'
+                                sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \
+                                            -p AUK-V-Aethia -b colorlight_i9 -l'
                                 }
                             }
                         }
-                        stage('Teste colorlight_i9') {
+                        stage('Test colorlight_i9') {
                             steps {
-                                echo 'Testando FPGA colorlight_i9.'
+                                echo 'Testing FPGA colorlight_i9.'
                                 dir("AUK-V-Aethia") {
-                                    sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' 
+                                    sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \
+                                    python /eda/processor-ci-communication/run_tests.py'
                                 }
                             }
                         }
@@ -59,27 +62,30 @@ pipeline {
                         lock(resource: 'digilent_nexys4_ddr')
                     }
                     stages {
-                        stage('Síntese e PnR') {
+                        stage('Synthesis and PnR') {
                             steps {
                                 dir("AUK-V-Aethia") {
-                                    echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.'
-                                    sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p AUK-V-Aethia -b digilent_nexys4_ddr'
+                                    echo 'Starting synthesis for FPGA digilent_nexys4_ddr.'
+                                sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \
+                                            -p AUK-V-Aethia -b digilent_nexys4_ddr'
                                 }
                             }
                         }
                         stage('Flash digilent_nexys4_ddr') {
                             steps {
                                 dir("AUK-V-Aethia") {
-                                    echo 'FPGA digilent_nexys4_ddr bloqueada para flash.'
-                                    sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p AUK-V-Aethia -b digilent_nexys4_ddr -l'
+                                    echo 'Flashing FPGA digilent_nexys4_ddr.'
+                                sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \
+                                            -p AUK-V-Aethia -b digilent_nexys4_ddr -l'
                                 }
                             }
                         }
-                        stage('Teste digilent_nexys4_ddr') {
+                        stage('Test digilent_nexys4_ddr') {
                             steps {
-                                echo 'Testando FPGA digilent_nexys4_ddr.'
+                                echo 'Testing FPGA digilent_nexys4_ddr.'
                                 dir("AUK-V-Aethia") {
-                                    sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' 
+                                    sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \
+                                    python /eda/processor-ci-communication/run_tests.py'
                                 }
                             }
                         }

diff --git a/jenkins_pipeline/Cores-SweRV-EH2.Jenkinsfile b/jenkins_pipeline/Cores-SweRV-EH2.Jenkinsfile
@@ -5,7 +5,7 @@ pipeline {
         stage('Git Clone') {
             steps {
                 sh 'rm -rf Cores-SweRV-EH2'
-                sh 'git clone --recursive https://github.com/chipsalliance/Cores-SweRV-EH2 Cores-SweRV-EH2'
+                sh 'git clone --recursive --depth=1 https://github.com/chipsalliance/Cores-SweRV-EH2 Cores-SweRV-EH2'
             }
         }
 
@@ -14,7 +14,7 @@ pipeline {
         stage('Simulation') {
             steps {
                 dir("Cores-SweRV-EH2") {
-                    sh "iverilog -o simulation.out -g2012  -s eh2_veer -I design/include design/dmi/dmi_jtag_to_core_sync.v design/dmi/dmi_wrapper.v design/dmi/rvjtag_tap.v design/eh2_dma_ctrl.sv design/eh2_mem.sv design/eh2_pic_ctrl.sv design/eh2_veer.sv design/eh2_veer_wrapper.sv design/dbg/eh2_dbg.sv design/dec/eh2_dec.sv design/dec/eh2_dec_csr.sv design/dec/eh2_dec_decode_ctl.sv design/dec/eh2_dec_gpr_ctl.sv design/dec/eh2_dec_ib_ctl.sv design/dec/eh2_dec_tlu_ctl.sv design/dec/eh2_dec_tlu_top.sv design/dec/eh2_dec_trigger.sv design/exu/eh2_exu.sv design/exu/eh2_exu_alu_ctl.sv design/exu/eh2_exu_div_ctl.sv design/exu/eh2_exu_mul_ctl.sv design/ifu/eh2_ifu.sv design/ifu/eh2_ifu_aln_ctl.sv design/ifu/eh2_ifu_bp_ctl.sv design/ifu/eh2_ifu_compress_ctl.sv design/ifu/eh2_ifu_ic_mem.sv design/ifu/eh2_ifu_iccm_mem.sv design/ifu/eh2_ifu_ifc_ctl.sv design/ifu/eh2_ifu_mem_ctl.sv design/include/eh2_def.sv design/lib/ahb_to_axi4.sv design/lib/axi4_to_ahb.sv design/lib/beh_lib.sv design/lib/eh2_lib.sv design/lib/mem_lib.sv design/lsu/eh2_lsu.sv design/lsu/eh2_lsu_addrcheck.sv design/lsu/eh2_lsu_amo.sv design/lsu/eh2_lsu_bus_buffer.sv design/lsu/eh2_lsu_bus_intf.sv design/lsu/eh2_lsu_clkdomain.sv design/lsu/eh2_lsu_dccm_ctl.sv design/lsu/eh2_lsu_dccm_mem.sv design/lsu/eh2_lsu_ecc.sv design/lsu/eh2_lsu_lsc_ctl.sv design/lsu/eh2_lsu_trigger.sv "
+                    sh "/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2012                  -s eh2_veer -I design/include design/dmi/dmi_jtag_to_core_sync.v design/dmi/dmi_wrapper.v design/dmi/rvjtag_tap.v design/eh2_dma_ctrl.sv design/eh2_mem.sv design/eh2_pic_ctrl.sv design/eh2_veer.sv design/eh2_veer_wrapper.sv design/dbg/eh2_dbg.sv design/dec/eh2_dec.sv design/dec/eh2_dec_csr.sv design/dec/eh2_dec_decode_ctl.sv design/dec/eh2_dec_gpr_ctl.sv design/dec/eh2_dec_ib_ctl.sv design/dec/eh2_dec_tlu_ctl.sv design/dec/eh2_dec_tlu_top.sv design/dec/eh2_dec_trigger.sv design/exu/eh2_exu.sv design/exu/eh2_exu_alu_ctl.sv design/exu/eh2_exu_div_ctl.sv design/exu/eh2_exu_mul_ctl.sv design/ifu/eh2_ifu.sv design/ifu/eh2_ifu_aln_ctl.sv design/ifu/eh2_ifu_bp_ctl.sv design/ifu/eh2_ifu_compress_ctl.sv design/ifu/eh2_ifu_ic_mem.sv design/ifu/eh2_ifu_iccm_mem.sv design/ifu/eh2_ifu_ifc_ctl.sv design/ifu/eh2_ifu_mem_ctl.sv design/include/eh2_def.sv design/lib/ahb_to_axi4.sv design/lib/axi4_to_ahb.sv design/lib/beh_lib.sv design/lib/eh2_lib.sv design/lib/mem_lib.sv design/lsu/eh2_lsu.sv design/lsu/eh2_lsu_addrcheck.sv design/lsu/eh2_lsu_amo.sv design/lsu/eh2_lsu_bus_buffer.sv design/lsu/eh2_lsu_bus_intf.sv design/lsu/eh2_lsu_clkdomain.sv design/lsu/eh2_lsu_dccm_ctl.sv design/lsu/eh2_lsu_dccm_mem.sv design/lsu/eh2_lsu_ecc.sv design/lsu/eh2_lsu_lsc_ctl.sv design/lsu/eh2_lsu_trigger.sv "
                 }
             }
         }
@@ -27,27 +27,30 @@ pipeline {
                         lock(resource: 'colorlight_i9')
                     }
                     stages {
-                        stage('Síntese e PnR') {
+                        stage('Synthesis and PnR') {
                             steps {
                                 dir("Cores-SweRV-EH2") {
-                                    echo 'Iniciando síntese para FPGA colorlight_i9.'
-                                    sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Cores-SweRV-EH2 -b colorlight_i9'
+                                    echo 'Starting synthesis for FPGA colorlight_i9.'
+                                sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \
+                                            -p Cores-SweRV-EH2 -b colorlight_i9'
                                 }
                             }
                         }
                         stage('Flash colorlight_i9') {
                             steps {
                                 dir("Cores-SweRV-EH2") {
-                                    echo 'FPGA colorlight_i9 bloqueada para flash.'
-                                    sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Cores-SweRV-EH2 -b colorlight_i9 -l'
+                                    echo 'Flashing FPGA colorlight_i9.'
+                                sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \
+                                            -p Cores-SweRV-EH2 -b colorlight_i9 -l'
                                 }
                             }
                         }
-                        stage('Teste colorlight_i9') {
+                        stage('Test colorlight_i9') {
                             steps {
-                                echo 'Testando FPGA colorlight_i9.'
+                                echo 'Testing FPGA colorlight_i9.'
                                 dir("Cores-SweRV-EH2") {
-                                    sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py' 
+                                    sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyACM0" \
+                                    python /eda/processor-ci-communication/run_tests.py'
                                 }
                             }
                         }
@@ -59,27 +62,30 @@ pipeline {
                         lock(resource: 'digilent_nexys4_ddr')
                     }
                     stages {
-                        stage('Síntese e PnR') {
+                        stage('Synthesis and PnR') {
                             steps {
                                 dir("Cores-SweRV-EH2") {
-                                    echo 'Iniciando síntese para FPGA digilent_nexys4_ddr.'
-                                    sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Cores-SweRV-EH2 -b digilent_nexys4_ddr'
+                                    echo 'Starting synthesis for FPGA digilent_nexys4_ddr.'
+                                sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \
+                                            -p Cores-SweRV-EH2 -b digilent_nexys4_ddr'
                                 }
                             }
                         }
                         stage('Flash digilent_nexys4_ddr') {
                             steps {
                                 dir("Cores-SweRV-EH2") {
-                                    echo 'FPGA digilent_nexys4_ddr bloqueada para flash.'
-                                    sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Cores-SweRV-EH2 -b digilent_nexys4_ddr -l'
+                                    echo 'Flashing FPGA digilent_nexys4_ddr.'
+                                sh 'python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json \
+                                            -p Cores-SweRV-EH2 -b digilent_nexys4_ddr -l'
                                 }
                             }
                         }
-                        stage('Teste digilent_nexys4_ddr') {
+                        stage('Test digilent_nexys4_ddr') {
                             steps {
-                                echo 'Testando FPGA digilent_nexys4_ddr.'
+                                echo 'Testing FPGA digilent_nexys4_ddr.'
                                 dir("Cores-SweRV-EH2") {
-                                    sh 'PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyUSB1 python /eda/processor-ci-communication/run_tests.py' 
+                                    sh 'PYTHONPATH=/eda/processor-ci-communication PORT="/dev/ttyUSB1" \
+                                    python /eda/processor-ci-communication/run_tests.py'
                                 }
                             }
                         }