Atualizando geracão de config para systemverilog

core/fpga.py

@@ -79,7 +79,7 @@ def get_macros(board: str) -> str:
     return '-tclargs "ID=0x6a6a6a6a" "CLOCK_FREQ=50000000" "MEMORY_SIZE=4096"'
 
 
-def get_prefix(board: str, vhdl: bool) -> str:
+def get_prefix(board: str, vhdl: bool, sverilog: bool) -> str:
     """
     Determines the file prefix command based on the target board and file type.
 
@@ -99,6 +99,8 @@ def get_prefix(board: str, vhdl: bool) -> str:
         return 'read_vhdl'
 
     if board == 'colorlight_i9':
+        if sverilog:
+            return 'yosys read_verilog -sv'
         return 'yosys read_verilog'
 
     return 'read_verilog'
@@ -152,7 +154,7 @@ def make_build_file(config: dict, board: str, toolchain_path: str) -> str:
         )
 
         for i in config['files']:
-            prefix = get_prefix(board, i.endswith('.vhd'))
+            prefix = get_prefix(board, vhdl=i.endswith('.vhd'), sverilog=i.endswith('.sv'))
             file.write(prefix + f' {CURRENT_DIR}/' + i + '\n')
 
         file.write(base_config)