GitHub - MadhanSaiKrishna/4-bit-cla-adder: VLSI Design Course Project - Spice, Layout, Post-layout, Verilog, FPGA implementation of 4-bit CLA Adder

Project Completion Status: ~70%

Pending Work:

Fix the working of the final stage D-Flip flop, Post layout simulations,
Final Report consisting the STA, Stick diagrams, Design specifications, Power consumption, Frequency of operation, etc.

Name		Name	Last commit message	Last commit date
Latest commit History 45 Commits
FPGA Implementatioin/Vivado Files/4_bit_adder		FPGA Implementatioin/Vivado Files/4_bit_adder
LTSpice		LTSpice
Magic		Magic
NGSpice		NGSpice
Verilog		Verilog
README.md		README.md