Arm support #24

weizhou-chaojixx · 2020-01-04T01:34:03Z

I have rebased all your current commits in master. By the way, since the CPU state struct of ARM has been dramatically changed from 1.0 to 3.0. And the QEMU client has to use some CPU state vars for interrupts. If I use VM exit to sync these var will make the VM exit too frequent, so I just sync these vars by writing 1.0 CPU state with the fixed offset of 3.0 state, which is ugly and will also lead the compiling warning. However, that is a more efficient and timely method. When you update libcpu from 1.0 to the 3.0 or 4.0. I will fix this problem.

vitalych · 2020-01-04T12:31:21Z

src/cpu-exec.c

@@ -28,7 +28,7 @@

 #define barrier() asm volatile("" ::: "memory")

-// #define DEBUG_EXEC
+#define DEBUG_EXEC


You forgot to disable it

Typo in commit msg

vitalych · 2020-01-04T12:42:25Z

src/softmmu_template.h

@@ -234,7 +234,7 @@ DATA_TYPE glue(glue(io_read_chk, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_p
    res.res = glue(glue(io_read, SUFFIX), MMUSUFFIX)(env, origaddr, addr, retaddr);

 end:
-    tcg_llvm_trace_mmio_access(addr, res.res, DATA_SIZE, 0);
+    res.res = tcg_llvm_trace_mmio_access(addr, res.res, DATA_SIZE, 0);


This is independent and should go into a separate PR.

vitalych · 2020-01-04T12:42:58Z

src/cpu-all.h

@@ -174,7 +174,7 @@ static inline int _se_check_concrete(void *objectState, target_ulong offset, int
 static inline void *_se_check_translate_ram_access(const void *p, unsigned size) {
 #if defined(SE_ENABLE_PHYSRAM_TLB)
    extern CPUArchState *env;
-    uintptr_t tlb_index = ((uintptr_t) p >> 12) & (CPU_TLB_SIZE - 1);
+    uintptr_t tlb_index = ((uintptr_t) p >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);


This is independent and should go into a separate PR.

vitalych · 2020-01-04T12:43:44Z

src/bswap.h

+static inline int lduw_le_p(const void *ptr)
+{
+#ifdef _ARCH_PPC
+    int val;


S2E will probably never run on ARM hosts, so not sure if this is useful.

vitalych · 2020-01-04T12:44:27Z

src/target-arm/cpu.h

 /* Load an instruction and return it in the standard little-endian order */
-static inline uint32_t arm_ldl_code(uint32_t addr, bool do_swap) {
-    uint32_t insn = ldl_raw(addr);
+/*


Removed commented-out code

vitalych · 2020-01-04T12:45:18Z

src/bswap.h

@@ -267,7 +267,7 @@ typedef union {
 } CPU_QuadU;

 static inline int ldub_p(const void *ptr) {
-    return *(uint8_t *) ptr;
+	return *(uint8_t *) ptr;


Run clang-format

vitalych · 2020-01-04T12:46:19Z

include/cpu/arm/kvm_arm.h

@@ -67,6 +67,23 @@ struct kvm_regs {
 	unsigned long fiq_regs[8];	/* R8_fiq - R14_fiq, SPSR_fiq */
 };

+struct kvm_m_regs {


The commit msg should be prefixed with cpu/arm:...

vitalych · 2020-01-04T12:46:59Z

include/cpu/kvm.h

+#define KVM_GET_M_SREGS _IOR(KVMIO, 0xc2, struct kvm_m_sregs)
+#define KVM_SET_M_SREGS _IOW(KVMIO, 0xc3, struct kvm_m_sregs)
+
+


Too many blank lines

vitalych · 2020-01-04T12:50:35Z

src/cpu-exec.c

@@ -266,7 +266,7 @@ static uintptr_t fetch_and_run_tb(TranslationBlock *prev_tb, int tb_exit_code, C
            (uint64_t) env->eip, (uint64_t) env->eip + tb->size, (uint64_t) env->mflags,
            env->kvm_request_interrupt_window);
 #elif defined(TARGET_ARM)
-    DPRINTF("   fetch_and_run_tb r15=0x%x sp=0x%x cpsr=0x%x \n", (uint32_t) env->regs[15], env->regs[13], env->uncached_cpsr);
+    DPRINTF("   fetch_and_run_tb pc=0x%x sp=0x%x cpsr=0x%x \n", (uint32_t) env->regs[15], env->regs[13], env->uncached_cpsr);


Please squash this commit with the one that introduced the change.
There shouldn't be commits that fix previous commits in the same PR.

vitalych · 2020-01-04T12:51:42Z

include/cpu/apic.h

@@ -21,7 +21,7 @@

 #include <cpu/config.h>

-#if defined(TARGET_I386)
+#if defined(TARGET_I386) || defined(TARGET_X86_64)


Is this necessary? AFAIK, TARGET_X86_64 implies TARGET_I386.
In anycase, this should be sent to a separate PR.

vitalych · 2020-01-04T12:52:16Z

src/cpu-exec.c

@@ -504,7 +504,7 @@ static bool execution_loop(CPUArchState *env) {
             * ensure that no TB jump will be modified as
             * the program flow was changed
             */
-            last_tb = 0;
+            ltb = NULL;


Separate PR.

vitalych · 2020-01-04T12:54:14Z

src/softmmu_template.h

@@ -160,17 +160,20 @@ DATA_TYPE glue(glue(io_read, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_phys_

    SE_SET_MEM_IO_VADDR(env, addr, 0);

+    if (likely(!g_sqi.mem.is_mmio_symbolic(addr, DATA_SIZE))) {


Actually, you would still need to call the original handler for concolic execution (you need the original concrete value).

This commit could be sent to a separate PR