Specs:
-64 bytes of instruction cache
-4 stage pipeline: FETCH, DECODE, EXECUTE, WRITEBACK
-Classic harvard memory
-Uses the BatPU2 ISA, made by Mattbatwings: https://docs.google.com/spreadsheets/d/1Bj3wHV-JifR2vP4HRYoCWrdXYp3sGMG0Q58Nm56W4aI/edit?gid=0#gid=0
Pipeline diagram of the core:
RTL view of the core: (Yellow is fetch, purple is decode, red is execute, orange is writeback)
Simulation of the fibonacci sequence:
