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README.md

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 ## Abstract
-Artificial intelligence ("AI") is deployed in various applications, from noise cancellation to image recognition.  AI-based products often come with high hardware and electricity costs, making them inaccessible for consumer devices and small-scale edge electronics.  Inspired by biological brains, deep neural networks ("DNNs") are modeled using mathematical formulae, but general-purpose processors treat otherwise-parallelizable AI algorithms as step-by-step sequential logic.  In contrast, programmable logic devices ("PLDs") can be customized to the specific parameters of a trained DNN, thereby ensuring data-tailored computation and algorithmic parallelism at the register transfer level.  Furthermore, a subgroup of PLDs, field-programmable gate arrays ("FPGAs"), are dynamically reconfigurable.  So, to improve AI runtime performance, I designed and open-sourced my hardware compiler, Innervator, using the VHDL-2008 language.  Innervator takes any DNN's metadata and parameters (e.g., number of layers, neurons per layer, and their weights/biases), generating its synthesizable FPGA hardware description with the appropriate pipelining and batch processing; Innervator is entirely portable and vendor-independent.  As a proof of concept, I used Innervator to implement a sample 8x8-pixel handwritten digit-recognizing neural network in a low-cost Xilinx Artix-7 FPGA @ 100 MHz.  With 3 pipeline stages and 2 batches at 60% area utilization, the Network achieved ~4.75 GOP/s, predicting the output in 630 ns and under 0.25 W of power.  In comparison, an Intel Core i7-12700H @ 4.70 GHz would take 40,000 to 60,000 ns at 45 to 115 W.  Ultimately, Innervator's hardware-accelerated approach bridges the inherent mismatch between current AI algorithms and the general-purpose digital hardware they run on.
+Artificial intelligence ("AI") is deployed in various applications, from noise cancellation to image recognition.  AI-based products often come with high hardware and electricity costs, making them inaccessible for consumer devices and small-scale edge electronics.  Inspired by biological brains, deep neural networks ("DNNs") are modeled using mathematical formulae, but general-purpose processors treat otherwise-parallelizable AI algorithms as step-by-step sequential logic.  In contrast, programmable logic devices ("PLDs") can be customized to the specific parameters of a trained DNN, thereby ensuring data-tailored computation and algorithmic parallelism at the register-transfer level.  Furthermore, a subgroup of PLDs, field-programmable gate arrays ("FPGAs"), are dynamically reconfigurable.  So, to improve AI runtime performance, I designed and open-sourced my hardware compiler: Innervator.  Written entirely in VHDL-2008, Innervator takes any DNN's metadata and parameters (e.g., number of layers, neurons per layer, and their weights/biases), generating its synthesizable FPGA hardware description with the appropriate pipelining and batch processing; Innervator is entirely portable and vendor-independent.  As a proof of concept, I used Innervator to implement a sample 8x8-pixel handwritten digit-recognizing neural network in a low-cost AMD Xilinx Artix-7(TM) FPGA @ 100 MHz.  With 3 pipeline stages and 2 batches at about 60% area utilization, the Network achieved ~4.75 GOP/s, predicting the output in 630 ns and under 0.25 W of power.  In comparison, an Intel(R) Core(TM) i7-12700H CPU @ 4.70 GHz would take 40,000-60,000 ns at 45 to 115 W.  Ultimately, Innervator's hardware-accelerated approach bridges the inherent mismatch between current AI algorithms and the general-purpose digital hardware they run on.
 
 ## Notice
 Although the Abstract specifically talks about an image-recognizing neural network, I endeavoured to generalize Innervator: in practice, it is capable of implementing any number of neurons and layers, and in any possible application (e.g., speech recognition), not just imagery.  In the `./data` folder, you will find weight and bias parameters that will be used during Innervator's synthesis.  Because of the incredibly broken implementation of VHDL's `std.textio` library across most synthesis tools, I was limited to only reading `std_logic_vector`s from files; due to that, weights and biases had to be pre-formatted in a fixed-point representation.  (More information is available in [`file_parser.vhd`](https://github.com/Thraetaona/Innervator/blob/main/src/neural/utils/file_parser.vhd).