Remove dependency on six and remove unnecessary __future__ imports.

pyrtl/analysis.py

@@ -4,8 +4,6 @@
 by either using internal models or by making calls out to external tool chains.
 """
 
-from __future__ import print_function, unicode_literals
-
 import re
 import os
 import math

pyrtl/compilesim.py

@@ -1,5 +1,3 @@
-from __future__ import print_function, unicode_literals
-
 import ctypes
 import subprocess
 import tempfile

pyrtl/conditional.py

@@ -70,8 +70,6 @@
 # Access should be done through instances "conditional_update" and "otherwise",
 # as described above, not through the classes themselves.
 
-from __future__ import print_function, unicode_literals
-
 from .pyrtlexceptions import PyrtlError, PyrtlInternalError
 from .wire import WireVector, Const, Register
 

pyrtl/core.py

@@ -8,7 +8,6 @@
 * `modes` -- access methods for "modes" such as debug
 
 """
-from __future__ import print_function, unicode_literals
 import collections
 import re
 import keyword
@@ -584,8 +583,7 @@ def __iter__(self):
                             if gate.op != 'r':
                                 to_clear.update(gate.dests)
         except KeyError as e:
-            import six
-            six.raise_from(PyrtlError("Cannot Iterate through malformed block"), e)
+            raise PyrtlError("Cannot Iterate through malformed block") from e
 
         if len(remaining) != 0:
             from pyrtl.helperfuncs import find_and_print_loop

pyrtl/corecircuits.py

@@ -1,8 +1,6 @@
 """ Some useful hardware generators (e.g. muxes, signed multipliers, etc.)  """
 
-from __future__ import division
-
-import six
+import itertools
 import math
 
 from .pyrtlexceptions import PyrtlError, PyrtlInternalError
@@ -400,7 +398,7 @@ def myhardware(input_a, input_b):
     from .memory import _MemIndexed
     block = working_block(block)
 
-    if isinstance(val, (int, six.string_types)):
+    if isinstance(val, (int, str)):
         # note that this case captures bool as well (as bools are instances of ints)
         return Const(val, bitwidth=bitwidth, block=block)
     elif isinstance(val, _MemIndexed):
@@ -706,8 +704,7 @@ def _basic_mult(A, B):
                 deferred[i].extend(w_array)
         bits = deferred[:result_bitwidth]
 
-    import six
-    add_wires = tuple(six.moves.zip_longest(*bits, fillvalue=Const(0)))
+    add_wires = tuple(itertools.zip_longest(*bits, fillvalue=Const(0)))
     adder_result = concat_list(add_wires[0]) + concat_list(add_wires[1])
     return adder_result[:result_bitwidth]
 

pyrtl/helperfuncs.py

@@ -1,12 +1,9 @@
 """ Helper functions that make constructing hardware easier.
 """
 
-from __future__ import print_function, unicode_literals
-
 import collections
 import math
 import numbers
-import six
 import sys
 from functools import reduce
 
@@ -248,7 +245,7 @@ def match_bitpattern(w, bitpattern, field_map=None):
 
     """
     w = as_wires(w)
-    if not isinstance(bitpattern, six.string_types):
+    if not isinstance(bitpattern, str):
         raise PyrtlError('bitpattern must be a string')
     nospace_string = ''.join(bitpattern.replace('_', '').split())
     if len(w) != len(nospace_string):
@@ -696,7 +693,7 @@ def infer_val_and_bitwidth(rawinput, bitwidth=None, signed=False):
         return _convert_bool(rawinput, bitwidth, signed)
     elif isinstance(rawinput, numbers.Integral):
         return _convert_int(rawinput, bitwidth, signed)
-    elif isinstance(rawinput, six.string_types):
+    elif isinstance(rawinput, str):
         return _convert_verilog_str(rawinput, bitwidth, signed)
     else:
         raise PyrtlError('error, the value provided is of an improper type, "%s"'

pyrtl/importexport.py

@@ -6,13 +6,11 @@
 accordingly, or write information from the Block out to the file.
 """
 
-from __future__ import print_function, unicode_literals
 import re
 import collections
 import tempfile
 import os
 import subprocess
-import six
 import sys
 import functools
 import operator
@@ -124,7 +122,6 @@ def input_from_blif(blif, block=None, merge_io_vectors=True, clock_name='clk', t
     It currently ignores the reset signal (which it assumes is input only to the flip flops).
     """
     import pyparsing
-    import six
     from pyparsing import (Word, Literal, OneOrMore, ZeroOrMore,
                            Suppress, Group, Keyword, Opt, one_of)
 
@@ -133,7 +130,7 @@ def input_from_blif(blif, block=None, merge_io_vectors=True, clock_name='clk', t
     try:
         blif_string = blif.read()
     except AttributeError:
-        if isinstance(blif, six.string_types):
+        if isinstance(blif, str):
             blif_string = blif
         else:
             raise PyrtlError('input_from_blif expecting either open file or string')
@@ -556,7 +553,7 @@ def input_from_verilog(verilog, clock_name='clk', toplevel=None, leave_in_dir=No
     try:
         verilog_string = verilog.read()
     except AttributeError:
-        if isinstance(verilog, six.string_types):
+        if isinstance(verilog, str):
             verilog_string = verilog
         else:
             raise PyrtlError('input_from_verilog expecting either open file or string')
@@ -1241,7 +1238,6 @@ def input_from_iscas_bench(bench, block=None):
     '''
 
     import pyparsing
-    import six
     from pyparsing import (Word, Literal, OneOrMore, ZeroOrMore,
                            Suppress, Group, Keyword, one_of)
 
@@ -1250,7 +1246,7 @@ def input_from_iscas_bench(bench, block=None):
     try:
         bench_string = bench.read()
     except AttributeError:
-        if isinstance(bench, six.string_types):
+        if isinstance(bench, str):
             bench_string = bench
         else:
             raise PyrtlError('input_from_bench expecting either open file or string')

pyrtl/memory.py

@@ -12,7 +12,6 @@
 with the correct number of ports to support that
 """
 
-from __future__ import print_function, unicode_literals
 import collections
 
 from .pyrtlexceptions import PyrtlError

pyrtl/passes.py

@@ -4,7 +4,6 @@
 ways to change a block.
 """
 
-from __future__ import print_function, unicode_literals
 import collections
 
 from .core import working_block, set_working_block, _get_debug_mode, LogicNet, PostSynthBlock

pyrtl/rtllib/adders.py

@@ -1,4 +1,5 @@
-from __future__ import absolute_import
+import itertools
+
 import pyrtl
 from . import libutils
 
@@ -249,9 +250,8 @@ def _sparse_adder(wire_array_2, adder):
             break
         result.append(wire_array_2[single_w_index][0])
 
-    import six
     wires_to_zip = wire_array_2[single_w_index:]
-    add_wires = tuple(six.moves.zip_longest(*wires_to_zip, fillvalue=pyrtl.Const(0)))
+    add_wires = tuple(itertools.zip_longest(*wires_to_zip, fillvalue=pyrtl.Const(0)))
     adder_result = adder(pyrtl.concat_list(add_wires[0]), pyrtl.concat_list(add_wires[1]))
     return pyrtl.concat(adder_result, *reversed(result))
 

pyrtl/rtllib/aes.py

@@ -33,7 +33,6 @@
 
 """
 
-from __future__ import division, absolute_import
 import pyrtl
 from pyrtl.rtllib import libutils
 

pyrtl/rtllib/barrel.py

@@ -1,4 +1,3 @@
-from __future__ import absolute_import
 import pyrtl
 import math
 

pyrtl/rtllib/libutils.py

@@ -1,5 +1,3 @@
-from __future__ import absolute_import
-
 import pyrtl
 
 

pyrtl/rtllib/matrix.py

@@ -1,5 +1,5 @@
 from functools import reduce
-from six.moves import builtins
+import builtins
 
 from pyrtl.rtllib import multipliers as mult
 

pyrtl/rtllib/multipliers.py

@@ -3,7 +3,6 @@
 Multipliers contains various PyRTL sample multipliers for people to use
 
 """
-from __future__ import absolute_import
 import pyrtl
 from . import adders, libutils
 

pyrtl/rtllib/prngs.py

@@ -70,7 +70,6 @@
 """
 
 
-from __future__ import absolute_import
 import pyrtl
 
 

pyrtl/simulation.py

@@ -1,13 +1,10 @@
 """Classes for executing and tracing circuit simulations."""
 
-from __future__ import print_function
-
 import copy
 import math
 import numbers
 import os
 import re
-import six
 import sys
 
 from .pyrtlexceptions import PyrtlError, PyrtlInternalError
@@ -739,7 +736,7 @@ def step_multiple(self, provided_inputs={}, expected_outputs={}, nsteps=None,
                 "each step of simulation")
 
         def to_num(v):
-            if isinstance(v, six.string_types):
+            if isinstance(v, str):
                 # Don't use infer_val_and_bitwidth because they aren't in
                 # Verilog-style format, but are instead in plain decimal.
                 return int(v)

pyrtl/visualization.py

@@ -5,7 +5,6 @@
 The functions provided write the block as a given visual format to the file.
 """
 
-from __future__ import print_function, unicode_literals
 import collections
 
 from .pyrtlexceptions import PyrtlError, PyrtlInternalError

pyrtl/wire.py

@@ -10,10 +10,7 @@
 * `Register` -- a wire vector that is latched each cycle
 """
 
-from __future__ import print_function, unicode_literals
-
 import numbers
-import six
 import re
 import sys
 
@@ -134,7 +131,7 @@ def name(self):
 
     @name.setter
     def name(self, value):
-        if not isinstance(value, six.string_types):
+        if not isinstance(value, str):
             raise PyrtlError('WireVector names must be strings')
         self._block.wirevector_by_name.pop(self._name, None)
         self._name = value

requirements.txt

@@ -4,4 +4,3 @@ pylint
 pyparsing
 pytest
 pytest-cov
-six

tests/test_analysis.py

@@ -1,7 +1,6 @@
-from __future__ import print_function, absolute_import
-
-import unittest
 import io
+import unittest
+
 import pyrtl