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Modified the aie-rt function APIs and updated the datatype of its par…
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…ameter from u8 to u16

Signed-off-by: Manoj Takasi <mtakasi@amd.com>
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Manoj Takasi committed Jan 7, 2025
1 parent acc1449 commit 4ea8348
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Showing 20 changed files with 167 additions and 167 deletions.
2 changes: 1 addition & 1 deletion build/petalinux.build
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@@ -1,3 +1,3 @@
# When updating Petalinux build please file a SH ticket to retain the build
# https://jira.xilinx.com/secure/CreateIssue!default.jspa
PETALINUX=/proj/petalinux/2025.1/petalinux-v2025.1_12231101/tool/petalinux-v2025.1-final
PETALINUX=/proj/petalinux/2025.1/petalinux-v2025.1_01061007/tool/petalinux-v2025.1-final
8 changes: 4 additions & 4 deletions src/runtime_src/core/edge/ps_kernels/profiling/aie2_profile_config/aie2_profile_config.cpp
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Expand Up @@ -408,10 +408,10 @@ namespace {
mPerfCounters.push_back(perfCounter);

// Convert enums to physical event IDs for reporting purposes
uint8_t tmpStart;
uint8_t tmpEnd;
XAie_EventLogicalToPhysicalConv(aieDevInst, loc, mod, startEvent, &tmpStart);
XAie_EventLogicalToPhysicalConv(aieDevInst, loc, mod, endEvent, &tmpEnd);
uint16_t tmpStart;
uint16_t tmpEnd;
XAie_EventLogicalToPhysicalConv_16(aieDevInst, loc, mod, startEvent, &tmpStart);
XAie_EventLogicalToPhysicalConv_16(aieDevInst, loc, mod, endEvent, &tmpEnd);
uint16_t phyStartEvent = tmpStart + config.mCounterBases[type];
uint16_t phyEndEvent = tmpEnd + config.mCounterBases[type];

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42 changes: 21 additions & 21 deletions src/runtime_src/core/edge/ps_kernels/profiling/aie2_trace_config/aie2_trace_config.cpp
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Expand Up @@ -391,13 +391,13 @@ namespace {
numCoreCounters++;

// Update config file
uint8_t phyEvent = 0;
uint16_t phyEvent = 0;
auto& cfg = cfgTile.core_trace_config.pc[idx];
XAie_EventLogicalToPhysicalConv(aieDevInst, loc, mod, config.coreCounterStartEvents[i], &phyEvent);
XAie_EventLogicalToPhysicalConv_16(aieDevInst, loc, mod, config.coreCounterStartEvents[i], &phyEvent);
cfg.start_event = phyEvent;
XAie_EventLogicalToPhysicalConv(aieDevInst, loc, mod, config.coreCounterEndEvents[i], &phyEvent);
XAie_EventLogicalToPhysicalConv_16(aieDevInst, loc, mod, config.coreCounterEndEvents[i], &phyEvent);
cfg.stop_event = phyEvent;
XAie_EventLogicalToPhysicalConv(aieDevInst, loc, mod, counterEvent, &phyEvent);
XAie_EventLogicalToPhysicalConv_16(aieDevInst, loc, mod, counterEvent, &phyEvent);
cfg.reset_event = phyEvent;
cfg.event_value = config.coreCounterEventValues[i];
}
Expand Down Expand Up @@ -433,13 +433,13 @@ namespace {
numMemoryCounters++;

// Update config file
uint8_t phyEvent = 0;
uint16_t phyEvent = 0;
auto& cfg = cfgTile.memory_trace_config.pc[idx];
XAie_EventLogicalToPhysicalConv(aieDevInst, loc, mod, config.memoryCounterStartEvents[i], &phyEvent);
XAie_EventLogicalToPhysicalConv_16(aieDevInst, loc, mod, config.memoryCounterStartEvents[i], &phyEvent);
cfg.start_event = phyEvent;
XAie_EventLogicalToPhysicalConv(aieDevInst, loc, mod, config.memoryCounterEndEvents[i], &phyEvent);
XAie_EventLogicalToPhysicalConv_16(aieDevInst, loc, mod, config.memoryCounterEndEvents[i], &phyEvent);
cfg.stop_event = phyEvent;
XAie_EventLogicalToPhysicalConv(aieDevInst, loc, mod, counterEvent, &phyEvent);
XAie_EventLogicalToPhysicalConv_16(aieDevInst, loc, mod, counterEvent, &phyEvent);
cfg.reset_event = phyEvent;
cfg.event_value = config.memoryCounterEventValues[i];
}
Expand All @@ -461,7 +461,7 @@ namespace {
//
if (type == xdp::module_type::core) {
XAie_ModuleType mod = XAIE_CORE_MOD;
uint8_t phyEvent = 0;
uint16_t phyEvent = 0;
auto coreTrace = core.traceControl();

// Delay cycles and user control are not compatible with each other
Expand Down Expand Up @@ -495,13 +495,13 @@ namespace {
numCoreTraceEvents++;

// Update config file
XAie_EventLogicalToPhysicalConv(aieDevInst, loc, mod, coreEvents[i], &phyEvent);
XAie_EventLogicalToPhysicalConv_16(aieDevInst, loc, mod, coreEvents[i], &phyEvent);
cfgTile.core_trace_config.traced_events[slot] = phyEvent;
}
// Update config file
XAie_EventLogicalToPhysicalConv(aieDevInst, loc, mod, config.coreTraceStartEvent, &phyEvent);
XAie_EventLogicalToPhysicalConv_16(aieDevInst, loc, mod, config.coreTraceStartEvent, &phyEvent);
cfgTile.core_trace_config.start_event = phyEvent;
XAie_EventLogicalToPhysicalConv(aieDevInst, loc, mod, config.coreTraceEndEvent, &phyEvent);
XAie_EventLogicalToPhysicalConv_16(aieDevInst, loc, mod, config.coreTraceEndEvent, &phyEvent);
cfgTile.core_trace_config.stop_event = phyEvent;

coreEvents.clear();
Expand Down Expand Up @@ -589,8 +589,8 @@ namespace {
XAie_ModuleType M;
TraceE->getRscId(L, M, S);

uint8_t phyEvent = 0;
XAie_EventLogicalToPhysicalConv(aieDevInst, loc, XAIE_CORE_MOD, memoryCrossEvents[i], &phyEvent);
uint16_t phyEvent = 0;
XAie_EventLogicalToPhysicalConv_16(aieDevInst, loc, XAIE_CORE_MOD, memoryCrossEvents[i], &phyEvent);

if (type == xdp::module_type::mem_tile) {
cfgTile.memory_tile_trace_config.traced_events[S] = phyEvent;
Expand Down Expand Up @@ -618,8 +618,8 @@ namespace {
TraceE->getRscId(L, M, S);
// Get Physical event

uint8_t phyEvent = 0;
XAie_EventLogicalToPhysicalConv(aieDevInst, loc, XAIE_MEM_MOD, memoryEvents[i], &phyEvent);
uint16_t phyEvent = 0;
XAie_EventLogicalToPhysicalConv_16(aieDevInst, loc, XAIE_MEM_MOD, memoryEvents[i], &phyEvent);
// cfgTile.memory_trace_config.traced_events[S] = phyEvent;

if (type == xdp::module_type::mem_tile)
Expand All @@ -634,14 +634,14 @@ namespace {
uint32_t bcBit = 0x1;
auto bcId = memoryTrace->getStartBc();
coreToMemBcMask |= (bcBit << bcId);
uint8_t phyEvent = 0;
uint16_t phyEvent = 0;

if (type == xdp::module_type::mem_tile) {
XAie_EventLogicalToPhysicalConv(aieDevInst, loc, XAIE_MEM_MOD, traceStartEvent, &phyEvent);
XAie_EventLogicalToPhysicalConv_16(aieDevInst, loc, XAIE_MEM_MOD, traceStartEvent, &phyEvent);
cfgTile.memory_tile_trace_config.start_event = phyEvent;

} else {
XAie_EventLogicalToPhysicalConv(aieDevInst, loc, XAIE_CORE_MOD, traceStartEvent, &phyEvent);
XAie_EventLogicalToPhysicalConv_16(aieDevInst, loc, XAIE_CORE_MOD, traceStartEvent, &phyEvent);
cfgTile.memory_trace_config.start_event = bcIdToEvent(bcId);
cfgTile.core_trace_config.internal_events_broadcast[bcId] = phyEvent;
}
Expand All @@ -650,10 +650,10 @@ namespace {
bcId = memoryTrace->getStopBc();
coreToMemBcMask |= (bcBit << bcId);
if (type == xdp::module_type::mem_tile) {
XAie_EventLogicalToPhysicalConv(aieDevInst, loc, XAIE_MEM_MOD, traceEndEvent, &phyEvent);
XAie_EventLogicalToPhysicalConv_16(aieDevInst, loc, XAIE_MEM_MOD, traceEndEvent, &phyEvent);
cfgTile.memory_tile_trace_config.stop_event = bcIdToEvent(bcId);
} else {
XAie_EventLogicalToPhysicalConv(aieDevInst, loc, XAIE_CORE_MOD, traceEndEvent, &phyEvent);
XAie_EventLogicalToPhysicalConv_16(aieDevInst, loc, XAIE_CORE_MOD, traceEndEvent, &phyEvent);
cfgTile.memory_trace_config.stop_event = bcIdToEvent(bcId);
cfgTile.core_trace_config.internal_events_broadcast[bcId] = phyEvent;

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8 changes: 4 additions & 4 deletions src/runtime_src/core/edge/ps_kernels/profiling/aie_profile_config/aie_profile_config.cpp
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Expand Up @@ -315,10 +315,10 @@ namespace {
mPerfCounters.push_back(perfCounter);

// Convert enums to physical event IDs for reporting purposes
uint8_t tmpStart;
uint8_t tmpEnd;
XAie_EventLogicalToPhysicalConv(aieDevInst, loc, mod, startEvent, &tmpStart);
XAie_EventLogicalToPhysicalConv(aieDevInst, loc, mod, endEvent, &tmpEnd);
uint16_t tmpStart;
uint16_t tmpEnd;
XAie_EventLogicalToPhysicalConv_16(aieDevInst, loc, mod, startEvent, &tmpStart);
XAie_EventLogicalToPhysicalConv_16(aieDevInst, loc, mod, endEvent, &tmpEnd);
uint16_t phyStartEvent = tmpStart + config.mCounterBases[type];
uint16_t phyEndEvent = tmpEnd + config.mCounterBases[type];

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38 changes: 19 additions & 19 deletions src/runtime_src/core/edge/ps_kernels/profiling/aie_trace_config/aie_trace_config.cpp
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Expand Up @@ -343,13 +343,13 @@ namespace {
numCoreCounters++;

// Update config file
uint8_t phyEvent = 0;
uint16_t phyEvent = 0;
auto& cfg = cfgTile.core_trace_config.pc[idx];
XAie_EventLogicalToPhysicalConv(aieDevInst, loc, mod, config.coreCounterStartEvents[i], &phyEvent);
XAie_EventLogicalToPhysicalConv_16(aieDevInst, loc, mod, config.coreCounterStartEvents[i], &phyEvent);
cfg.start_event = phyEvent;
XAie_EventLogicalToPhysicalConv(aieDevInst, loc, mod, config.coreCounterEndEvents[i], &phyEvent);
XAie_EventLogicalToPhysicalConv_16(aieDevInst, loc, mod, config.coreCounterEndEvents[i], &phyEvent);
cfg.stop_event = phyEvent;
XAie_EventLogicalToPhysicalConv(aieDevInst, loc, mod, counterEvent, &phyEvent);
XAie_EventLogicalToPhysicalConv_16(aieDevInst, loc, mod, counterEvent, &phyEvent);
cfg.reset_event = phyEvent;
cfg.event_value = config.coreCounterEventValues[i];
}
Expand Down Expand Up @@ -386,13 +386,13 @@ namespace {
numMemoryCounters++;

// Update config file
uint8_t phyEvent = 0;
uint16_t phyEvent = 0;
auto& cfg = cfgTile.memory_trace_config.pc[idx];
XAie_EventLogicalToPhysicalConv(aieDevInst, loc, mod, config.memoryCounterStartEvents[i], &phyEvent);
XAie_EventLogicalToPhysicalConv_16(aieDevInst, loc, mod, config.memoryCounterStartEvents[i], &phyEvent);
cfg.start_event = phyEvent;
XAie_EventLogicalToPhysicalConv(aieDevInst, loc, mod, config.memoryCounterEndEvents[i], &phyEvent);
XAie_EventLogicalToPhysicalConv_16(aieDevInst, loc, mod, config.memoryCounterEndEvents[i], &phyEvent);
cfg.stop_event = phyEvent;
XAie_EventLogicalToPhysicalConv(aieDevInst, loc, mod, counterEvent, &phyEvent);
XAie_EventLogicalToPhysicalConv_16(aieDevInst, loc, mod, counterEvent, &phyEvent);
cfg.reset_event = phyEvent;
cfg.event_value = config.memoryCounterEventValues[i];
}
Expand All @@ -414,7 +414,7 @@ namespace {
//
{
XAie_ModuleType mod = XAIE_CORE_MOD;
uint8_t phyEvent = 0;
uint16_t phyEvent = 0;
auto coreTrace = core.traceControl();

// Delay cycles and user control are not compatible with each other
Expand Down Expand Up @@ -449,13 +449,13 @@ namespace {
numTraceEvents++;

// Update config file
XAie_EventLogicalToPhysicalConv(aieDevInst, loc, mod, coreEvents[i], &phyEvent);
XAie_EventLogicalToPhysicalConv_16(aieDevInst, loc, mod, coreEvents[i], &phyEvent);
cfgTile.core_trace_config.traced_events[slot] = phyEvent;
}
// Update config file
XAie_EventLogicalToPhysicalConv(aieDevInst, loc, mod, config.coreTraceStartEvent, &phyEvent);
XAie_EventLogicalToPhysicalConv_16(aieDevInst, loc, mod, config.coreTraceStartEvent, &phyEvent);
cfgTile.core_trace_config.start_event = phyEvent;
XAie_EventLogicalToPhysicalConv(aieDevInst, loc, mod, config.coreTraceEndEvent, &phyEvent);
XAie_EventLogicalToPhysicalConv_16(aieDevInst, loc, mod, config.coreTraceEndEvent, &phyEvent);
cfgTile.core_trace_config.stop_event = phyEvent;

coreEvents.clear();
Expand Down Expand Up @@ -517,8 +517,8 @@ namespace {
TraceE->getRscId(L, M, S);
cfgTile.memory_trace_config.traced_events[S] = bcIdToEvent(bcId);
auto mod = XAIE_CORE_MOD;
uint8_t phyEvent = 0;
XAie_EventLogicalToPhysicalConv(aieDevInst, loc, mod, memoryCrossEvents[i], &phyEvent);
uint16_t phyEvent = 0;
XAie_EventLogicalToPhysicalConv_16(aieDevInst, loc, mod, memoryCrossEvents[i], &phyEvent);
cfgTile.core_trace_config.internal_events_broadcast[bcId] = phyEvent;
}

Expand All @@ -540,8 +540,8 @@ namespace {
TraceE->getRscId(L, M, S);
// Get Physical event
auto mod = XAIE_MEM_MOD;
uint8_t phyEvent = 0;
XAie_EventLogicalToPhysicalConv(aieDevInst, loc, mod, memoryEvents[i], &phyEvent);
uint16_t phyEvent = 0;
XAie_EventLogicalToPhysicalConv_16(aieDevInst, loc, mod, memoryEvents[i], &phyEvent);
cfgTile.memory_trace_config.traced_events[S] = phyEvent;
}

Expand All @@ -552,15 +552,15 @@ namespace {
auto bcId = memoryTrace->getStartBc();
coreToMemBcMask |= (bcBit << bcId);
auto mod = XAIE_CORE_MOD;
uint8_t phyEvent = 0;
XAie_EventLogicalToPhysicalConv(aieDevInst, loc, mod, config.coreTraceStartEvent, &phyEvent);
uint16_t phyEvent = 0;
XAie_EventLogicalToPhysicalConv_16(aieDevInst, loc, mod, config.coreTraceStartEvent, &phyEvent);
cfgTile.memory_trace_config.start_event = bcIdToEvent(bcId);
cfgTile.core_trace_config.internal_events_broadcast[bcId] = phyEvent;

bcBit = 0x1;
bcId = memoryTrace->getStopBc();
coreToMemBcMask |= (bcBit << bcId);
XAie_EventLogicalToPhysicalConv(aieDevInst, loc, mod, config.coreTraceEndEvent, &phyEvent);
XAie_EventLogicalToPhysicalConv_16(aieDevInst, loc, mod, config.coreTraceEndEvent, &phyEvent);
cfgTile.memory_trace_config.stop_event = bcIdToEvent(bcId);
cfgTile.core_trace_config.internal_events_broadcast[bcId] = phyEvent;
}
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6 changes: 3 additions & 3 deletions src/runtime_src/core/edge/ps_kernels/profiling/aie_trace_gmio/gmio_config_kernel.cpp
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Expand Up @@ -92,12 +92,12 @@ namespace {
XAie_DmaEnableBd(&(gmioDMAInsts[i].shimDmaInst));

// For trace, use bd# 0 for S2MM0, use bd# 4 for S2MM1
int bdNum = channelNumber * 4;
uint16_t bdNum = channelNumber * 4;

// Write to shim DMA BD AxiMM registers
XAie_DmaWriteBd(aieDevInst, &(gmioDMAInsts[i].shimDmaInst), gmioDMAInsts[i].gmioTileLoc, bdNum);
XAie_DmaWriteBd_16(aieDevInst, &(gmioDMAInsts[i].shimDmaInst), gmioDMAInsts[i].gmioTileLoc, bdNum);
// Enqueue BD
XAie_DmaChannelPushBdToQueue(aieDevInst, gmioDMAInsts[i].gmioTileLoc, channelNumber, dir, bdNum);
XAie_DmaChannelPushBdToQueue_16(aieDevInst, gmioDMAInsts[i].gmioTileLoc, channelNumber, dir, bdNum);
}

return 0;
Expand Down
4 changes: 2 additions & 2 deletions src/runtime_src/core/edge/user/aie/aie.cpp
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Expand Up @@ -231,11 +231,11 @@ sync_external_buffer(std::vector<xrt::bo>& bos, adf::external_buffer_config& con
int start_bd = -1;
for (const auto& shim_bd_info : port_config.shim_bd_infos) {
auto buf_idx = shim_bd_info.buf_idx;
dma_api_obj.updateBDAddressLin(&bds[buf_idx].mem_inst, port_config.shim_column, 0, static_cast<uint8_t>(shim_bd_info.bd_id), shim_bd_info.offset * 4);
dma_api_obj.updateBDAddressLin(&bds[buf_idx].mem_inst, port_config.shim_column, 0, static_cast<uint16_t>(shim_bd_info.bd_id), shim_bd_info.offset * 4);
if (start_bd < 0)
start_bd = shim_bd_info.bd_id;
}
dma_api_obj.enqueueTask(1, port_config.shim_column, 0, port_config.direction, port_config.channel_number, port_config.task_repetition, port_config.enable_task_complete_token, static_cast<uint8_t>(start_bd));
dma_api_obj.enqueueTask(1, port_config.shim_column, 0, port_config.direction, port_config.channel_number, port_config.task_repetition, port_config.enable_task_complete_token, static_cast<uint16_t>(start_bd));
}

for (auto& bd :bds) {
Expand Down
22 changes: 11 additions & 11 deletions src/runtime_src/core/edge/user/aie/common_layer/adf_aie_control_api.h
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Expand Up @@ -89,15 +89,15 @@ class dma_api
/// Lock acquire value (signed). acq_ge if less than 0. acq_eq if larger than or equal to 0.
int8_t lock_acq_value = 0;
/// Lock id to acquire
uint8_t lock_acq_id = 0;
uint16_t lock_acq_id = 0;
/// Lock release value (signed). 0: do not release a lock.
int8_t lock_rel_value = 0;
/// Lock id to release
uint8_t lock_rel_id = 0;
uint16_t lock_rel_id = 0;
/// Continue with next BD
bool use_next_bd = false;
/// Next BD ID
uint8_t next_bd = 0;
uint16_t next_bd = 0;
/// AXI burst length. Shim tile only. In binary format 00: BLEN = 4 (64B), 01: BLEN = 8 (128B), 10: BLEN = 16 (256B), 11: Undefined
uint8_t burst_length = 4;
};
Expand All @@ -107,14 +107,14 @@ class dma_api
/// @param column AIE array column
/// @param row AIE array row relative to tileType
/// @param dir 0 (XAie_DmaDirection::DMA_S2MM), 1 (XAie_DmaDirection::DMA_MM2S)
err_code configureBdWaitQueueEnqueueTask(int tileType, uint8_t column, uint8_t row, int dir, uint8_t channel, uint32_t repeatCount, bool enableTaskCompleteToken, std::vector<uint8_t> bdIds, std::vector<dma_api::buffer_descriptor> bdParams);
err_code configureBdWaitQueueEnqueueTask(int tileType, uint8_t column, uint8_t row, int dir, uint8_t channel, uint32_t repeatCount, bool enableTaskCompleteToken, std::vector<uint16_t> bdIds, std::vector<dma_api::buffer_descriptor> bdParams);

err_code configureBD(int tileType, uint8_t column, uint8_t row, uint8_t bdId, const dma_api::buffer_descriptor& bdParam);
err_code enqueueTask(int tileType, uint8_t column, uint8_t row, int dir, uint8_t channel, uint32_t repeatCount, bool enableTaskCompleteToken, uint8_t startBdId);
err_code configureBD(int tileType, uint8_t column, uint8_t row, uint16_t bdId, const dma_api::buffer_descriptor& bdParam);
err_code enqueueTask(int tileType, uint8_t column, uint8_t row, int dir, uint8_t channel, uint32_t repeatCount, bool enableTaskCompleteToken, uint16_t startBdId);
err_code waitDMAChannelTaskQueue(int tileType, uint8_t column, uint8_t row, int dir, uint8_t channel);
err_code waitDMAChannelDone(int tileType, uint8_t column, uint8_t row, int dir, uint8_t channel);
err_code updateBDAddress(int tileType, uint8_t column, uint8_t row, uint8_t bdId, uint64_t address);
err_code updateBDAddressLin(XAie_MemInst* memInst , uint8_t column, uint8_t row, uint8_t bdId, uint64_t offset);
err_code updateBDAddress(int tileType, uint8_t column, uint8_t row, uint16_t bdId, uint64_t address);
err_code updateBDAddressLin(XAie_MemInst* memInst , uint8_t column, uint8_t row, uint16_t bdId, uint64_t offset);

std::shared_ptr<config_manager> get_config()
{
Expand All @@ -134,9 +134,9 @@ class lock_api
/// @param tileType 0 (adf::tile_type::aie_tile), 1 (adf::tile_type::shim_tile), 2 (adf::tile_type::memory_tile)
/// @param column AIE array column
/// @param row AIE array row relative to tileType
err_code initializeLock(int tileType, uint8_t column, uint8_t row, unsigned short lockId, int8_t initVal);
err_code acquireLock(int tileType, uint8_t column, uint8_t row, unsigned short lockId, int8_t acqVal);
err_code releaseLock(int tileType, uint8_t column, uint8_t row, unsigned short lockId, int8_t relVal);
err_code initializeLock(int tileType, uint8_t column, uint8_t row, uint16_t lockId, int8_t initVal);
err_code acquireLock(int tileType, uint8_t column, uint8_t row, uint16_t lockId, int8_t acqVal);
err_code releaseLock(int tileType, uint8_t column, uint8_t row, uint16_t lockId, int8_t relVal);
std::shared_ptr<config_manager> get_config()
{
return config;
Expand Down
6 changes: 3 additions & 3 deletions src/runtime_src/core/edge/user/aie/common_layer/adf_api_config.h
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Original file line number Diff line number Diff line change
Expand Up @@ -78,15 +78,15 @@ struct rtp_config
short selectorColumn;
short selectorRow;
size_t selectorAddr;
unsigned short selectorLockId;
uint16_t selectorLockId;
short pingColumn;
short pingRow;
size_t pingAddr;
unsigned short pingLockId;
uint16_t pingLockId;
short pongColumn;
short pongRow;
size_t pongAddr;
unsigned short pongLockId;
uint16_t pongLockId;
bool blocking;
};

Expand Down
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