Added info about AHB Master/Slave error response and added possibilit…

…y for masters to ignore errors while issuing pip. transactions

Signed-off-by: Anderson Ignacio <anderson@aignacio.com>

README.md

@@ -181,6 +181,8 @@ class AHBLiteMaster:
     ):
 ```
 
+In case of AHB Slave error response, the master will cancel the current transaction changing HTRANS from NSEQ to IDLE in the second clock cycle of the error response and then it will retry immediately after (following clock cycle). This is not mandatory but gives time for the master to decide whether it needs to be aborted or not the following transaction.
+
 Its methods are composed by **read()**, **write()** and **custom()**. 
 
 #### Write
@@ -278,6 +280,11 @@ class AHBLiteSlave:
 
 The AHB slaves will not provide any specific data (always zero) or unexpected response, they serve as a basic slave just to check its connectivity while testing AHB Master and as a base class for the AHB Lite Slave RAM. The back-pressure feature is a way to force the slave to demonstrated unavailability while the master issue AHB transactions. The generator needs to return bool type values where bool True indicates slave available and bool False indicate slave unavailable. 
 
+In case of an AHB error response, the Slave inserts a wait state (HREADY == LOW && HRESP == OKAY) however this not required and might change in the future sticking only to the mandatory obligation of 2-cycle error response:
+
+* First: HREADY == LOW / HRESP == ERROR
+* Second: HREADY == HIGH / HRESP == ERROR
+
 #### AHB Lite Slave RAM 
 
 The AHB Lite Slave RAM is a basic memory slave that can receive reads and write like a normal memory-mapped device. The only difference between the normal slave vs this one is the fact that as part of its constructor, a new argument **mem_size** is listed. This argument defines a memory size in bytes for the AHB slave. The only limitation for now, is the fact that all memory addresses have to be aligned to the data bus width, i.e for 32-bit slaves, address[1:0] == 2'b00.

cocotbext/ahb/ahb_monitor.py

@@ -52,6 +52,9 @@ async def _mon_master_txn(self):
 
         while True:
             await FallingEdge(self.clk)
+            if self.bus.htrans.value.is_resolvable and self.bus.hready.value.is_resolvable:
+                if self.bus.htrans.value == 0 and self.bus.hready == 0:
+                    raise AssertionError("AHB PROTOCOL VIOLATION - TEST")
 
             # print(f"pending: {pending}")
             # Ensure master does not change its qualifiers before hready

cocotbext/ahb/ahb_slave.py

@@ -4,7 +4,7 @@
 # License           : MIT license <Check LICENSE>
 # Author            : Anderson I. da Silva (aignacio) <anderson@aignacio.com>
 # Date              : 16.10.2023
-# Last Modified Date: 12.11.2023
+# Last Modified Date: 13.11.2023
 
 import cocotb
 import logging
@@ -118,7 +118,6 @@ async def _proc_txn(self):
             # Check for new txn
             if (
                 (cur_hready == 1)
-                and (cur_hresp != AHBResp.ERROR)
                 and self._check_inputs()
                 and self._check_valid_txn()
             ):

cocotbext/ahb/version.py

@@ -1 +1 @@
-__version__ = "0.1.9"
+__version__ = "0.2.0"