AHB seems to be working

Signed-off-by: Anderson Ignacio da Silva <anderson@aignacio.com>

ahb_template.gtkw

@@ -0,0 +1,128 @@
+[*]
+[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
+[*] Tue May 21 22:13:34 2024
+[*]
+[dumpfile] "nox_waves.fst"
+[dumpfile_mtime] "Tue May 21 22:05:46 2024"
+[dumpfile_size] 3059157
+[savefile] "ahb_template.gtkw"
+[timestart] 182791
+[size] 2384 1412
+[pos] 2005 426
+*-6.047431 182560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+[markername] AA
+[markername] BB
+[markername] CC
+[markername] DD
+[markername] EE
+[markername] FF
+[markername] GG
+[markername] HH
+[markername] II
+[markername] JJ
+[markername] KK
+[markername] LL
+[markername] MM
+[markername] NN
+[markername] OO
+[markername] PP
+[markername] QQ
+[markername] RR
+[markername] SS
+[markername] TT
+[markername] UU
+[markername] VV
+[markername] WW
+[markername] XX
+[markername] YY
+[markername] ZZ
+[treeopen] TOP.
+[treeopen] TOP.nox_soc.
+[treeopen] TOP.nox_soc.u_nox_wrapper.
+[treeopen] TOP.nox_soc.u_nox_wrapper.u_nox.
+[treeopen] TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch.
+[sst_width] 362
+[signals_width] 296
+[sst_expanded] 1
+[sst_vpaned_height] 611
+@28
+TOP.nox_soc.rst
+TOP.nox_soc.clk
+@200
+-
+@10023
+TOP.nox_soc.u_nox_intcon_wrapper.m0_cpu_fetch_mosi.haddr[31:0]
+@800200
+-instr_nox
+@28
+TOP.nox_soc.u_nox_intcon_wrapper.m0_cpu_fetch_mosi.hready
+@22
+TOP.nox_soc.u_nox_intcon_wrapper.m0_cpu_fetch_mosi.haddr[31:0]
+@28
+TOP.nox_soc.u_nox_intcon_wrapper.m0_cpu_fetch_mosi.hsel
+@100000028
+TOP.nox_soc.u_nox_intcon_wrapper.m0_cpu_fetch_mosi.hsize[2:0]
+TOP.nox_soc.u_nox_intcon_wrapper.m0_cpu_fetch_mosi.htrans[1:0]
+@22
+TOP.nox_soc.u_nox_intcon_wrapper.m0_cpu_fetch_mosi.hwdata[31:0]
+@28
+TOP.nox_soc.u_nox_intcon_wrapper.m0_cpu_fetch_mosi.hwrite
+@200
+-
+@28
+TOP.nox_soc.u_nox_intcon_wrapper.m0_cpu_fetch_miso.hready
+TOP.nox_soc.u_nox_intcon_wrapper.m0_cpu_fetch_miso.hresp
+@22
+TOP.nox_soc.u_nox_intcon_wrapper.m0_cpu_fetch_miso.hrdata[31:0]
+@1000200
+-instr_nox
+@c00200
+-lsu_nox
+@28
+TOP.nox_soc.u_nox_intcon_wrapper.m1_cpu_lsu_mosi.hready
+@22
+TOP.nox_soc.u_nox_intcon_wrapper.m1_cpu_lsu_mosi.haddr[31:0]
+@28
+TOP.nox_soc.u_nox_intcon_wrapper.m1_cpu_lsu_mosi.hsel
+@100000028
+TOP.nox_soc.u_nox_intcon_wrapper.m1_cpu_lsu_mosi.hsize[2:0]
+TOP.nox_soc.u_nox_intcon_wrapper.m1_cpu_lsu_mosi.htrans[1:0]
+@22
+TOP.nox_soc.u_nox_intcon_wrapper.m1_cpu_lsu_mosi.hwdata[31:0]
+@28
+TOP.nox_soc.u_nox_intcon_wrapper.m1_cpu_lsu_mosi.hwrite
+@200
+-
+@28
+TOP.nox_soc.u_nox_intcon_wrapper.m1_cpu_lsu_miso.hready
+TOP.nox_soc.u_nox_intcon_wrapper.m1_cpu_lsu_miso.hresp
+@22
+TOP.nox_soc.u_nox_intcon_wrapper.m1_cpu_lsu_miso.hrdata[31:0]
+@1401200
+-lsu_nox
+@28
+TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch.fetch_req_i
+@22
+TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch.fetch_addr_i[31:0]
+@28
+TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch.next_req
+@100000028
+TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch.st_ff[1:0]
+@28
+TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch.jump
+TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch.req_ff
+TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch.dp_ff
+@200
+-
+@28
+TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch.fetch_valid_o
+@22
+TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch.fetch_instr_o[31:0]
+@28
+TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch.fetch_ready_i
+@24
+TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch.buffer_space[1:0]
+@420
+TOP.nox_soc.u_nox_wrapper.u_nox.u_fetch.L0_BUFFER_SIZE
+[pattern_trace] 1
+[pattern_trace] 0

makefile

@@ -1,4 +1,4 @@
-AXI_IF				?=	1
+AXI_IF				?=	0
 GTKWAVE_PRE		:=	/Applications/gtkwave.app/Contents/Resources/bin/
 # Design files
 _SRC_VERILOG	?=	bus_arch_sv_pkg/amba_axi_pkg.sv
@@ -42,7 +42,13 @@ _SOC_VERILOG 	+=	xlnx/rtl/nox_wrapper.sv
 _SOC_VERILOG 	+=	xlnx/rtl/cdc_async_fifo.sv
 _SOC_VERILOG 	+=	xlnx/rtl/axi_spi_master.sv
 _SOC_VERILOG 	+=	xlnx/rtl/axi_mtimer.sv
+_SOC_VERILOG 	+=	xlnx/rtl/ahb_mem.sv
+_SOC_VERILOG 	+=	xlnx/rtl/cmsdk_ahb_to_sram.v
+_SOC_VERILOG 	+=	xlnx/rtl/cmsdk_fpga_sram.v
+_SOC_VERILOG 	+=	xlnx/rtl/nox_ahb_ram.sv
 _SOC_VERILOG 	+=	sw/bootloader/output/boot_rom.sv
+_SOC_VERILOG 	+=	$(shell find xlnx/rtl/ahb_interconnect -type f -iname *.v)
+_SOC_VERILOG 	+=	$(shell find xlnx/rtl/ahb_interconnect -type f -iname *.sv)
 
 ifeq ($(AXI_IF),0)
 _SOC_VERILOG 	+=	xlnx/rtl/nox_soc_ahb.sv
@@ -59,12 +65,12 @@ INCS_VLOG			:=	$(addprefix -I,$(_INCS_VLOG))
 #IRAM_KB_SIZE	?=	2*1024 #2MB due to J-Tests on RV Compliance tests
 IRAM_KB_SIZE	?=	128
 DRAM_KB_SIZE	?=	32
-ENTRY_ADDR		?=	\'h8000_0000
-IRAM_ADDR			?=	0x80000000
-DRAM_ADDR			?=	0x10000000
+ENTRY_ADDR		?=	\'h0000_0000
+IRAM_ADDR			?=	0x00000000
+DRAM_ADDR			?=	0x00020000
 # For NoX SoC
-IRAM_ADDR_SOC	?=	0xa0000000
-DRAM_ADDR_SOC	?=	0x10000000
+IRAM_ADDR_SOC	?=	0x00000000
+DRAM_ADDR_SOC	?=	0x00020000
 DISPLAY_TEST	?=	0 # Enable $display in axi_mem.sv [compliance test]
 WAVEFORM_USE	?=	1 # Use 0 to not generate waves [compliance test]
 
@@ -120,7 +126,8 @@ RUN_CMD_COMP	:=	docker run --rm --name ship_nox	\
 
 RUN_SW				:=	sw/hello_world/output/hello_world.elf
 #RUN_SW_SOC		:=	sw/bootloader/output/bootloader.elf
-RUN_SW_SOC		:=	sw/soc_hello_world/output/soc_hello_world.elf
+#RUN_SW_SOC		:=	sw/soc_hello_world/output/soc_hello_world.elf
+RUN_SW_SOC		:=	sw/hello_world/output/hello_world.elf
 #RUN_SW_SOC		:=	sw/FreeRTOS_demo/output/FreeRTOS_demo.elf
 
 CPPFLAGS_VERI	:=	"$(INCS_CPP) -O0 -g3 -Wall						\
@@ -244,7 +251,7 @@ soc: clean $(VERI_EXE_SOC)
 	@echo "\n"
 
 $(RUN_SW_SOC):
-	make -C sw/soc_hello_world all UART_MODE=UART_SIM
+	make -C sw/hello_world all UART_MODE=UART_SIM
 
 run_soc: $(RUN_SW_SOC)
 	$(RUN_CMD) ./$(VERI_EXE_SOC) -s 100000 -e $<

rtl/cb_to_ahb.sv

@@ -3,20 +3,36 @@
  * License           : MIT license <Check LICENSE>
  * Author            : Anderson Ignacio da Silva (aignacio) <anderson@aignacio.com>
  * Date              : 23.10.2021
- * Last Modified Date: 25.02.2022
+ * Last Modified Date: 15.05.2024
  */
 module cb_to_ahb
   import amba_axi_pkg::*;
   import amba_ahb_pkg::*;
   import nox_utils_pkg::*;
 (
+  input                 clk,
+  input                 rst,
   // Core bus Master I/F
   input   s_cb_mosi_t   cb_mosi_i,
   output  s_cb_miso_t   cb_miso_o,
   // AXI Master I/F
   output  s_ahb_mosi_t  ahb_mosi_o,
   input   s_ahb_miso_t  ahb_miso_i
 );
+  logic req_rd_ff, next_rd_req;
+  logic req_wr_ff, next_wr_req;
+
+  `CLK_PROC(clk, rst) begin
+    `RST_TYPE(rst) begin
+      req_rd_ff <= 1'b0;
+      req_wr_ff <= '0;
+    end
+    else begin
+      req_rd_ff <= next_rd_req;
+      req_wr_ff <= next_wr_req;
+    end
+  end
+
   always_comb begin
     ahb_mosi_o = s_ahb_mosi_t'('0);
     cb_miso_o  = s_cb_miso_t'('0);
@@ -33,15 +49,36 @@ module cb_to_ahb
     end
     ahb_mosi_o.hwdata = cb_mosi_i.wr_data_valid ? cb_mosi_i.wr_data : 'h0;
 
+    next_rd_req = req_rd_ff;
+    next_wr_req = req_wr_ff;
+
+    if (req_rd_ff && ahb_miso_i.hready) begin
+      next_rd_req = 1'b0;
+    end
+
+    if (req_wr_ff && ahb_miso_i.hready) begin
+      next_wr_req = 1'b0;
+    end
+
+
+    if (ahb_mosi_o.hsel && (ahb_mosi_o.htrans != AHB_IDLE) && ahb_miso_i.hready) begin
+      if (ahb_mosi_o.hwrite) begin
+        next_wr_req = 1'b1;
+      end
+      else begin
+        next_rd_req = 1'b1;
+      end
+    end
+
     // MISO
     cb_miso_o.wr_addr_ready = ahb_miso_i.hready;
-    cb_miso_o.wr_data_ready = ahb_miso_i.hready;
+    cb_miso_o.wr_data_ready = ahb_miso_i.hready && req_wr_ff;
     cb_miso_o.wr_resp_error = cb_error_t'(ahb_miso_i.hresp);
-    cb_miso_o.wr_resp_valid = 'b1;
+    cb_miso_o.wr_resp_valid = ahb_miso_i.hready;
     cb_miso_o.rd_addr_ready = ahb_miso_i.hready;
     cb_miso_o.rd_data       = ahb_miso_i.hrdata;
     cb_miso_o.rd_resp       = cb_error_t'(ahb_miso_i.hresp);
-    cb_miso_o.rd_valid      = ~ahb_miso_i.hready;
+    cb_miso_o.rd_valid      = ahb_miso_i.hready && req_rd_ff;
   end
 
 endmodule