Merge pull request #2 from aignacio/synthesis_yosys

Added synthesis / yosys setup

.gitignore

@@ -32,3 +32,4 @@ output_temp/
 riscof_work/
 riscv-arch-test/
 *.txt
+synth/syn_out

.gitmodules

@@ -10,3 +10,6 @@
 [submodule "bus_arch_sv_pkg"]
 	path = bus_arch_sv_pkg
 	url = https://github.com/aignacio/bus_arch_sv_pkg.git
+[submodule "synth/pdk_45nm"]
+	path = synth/pdk_45nm
+	url = https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts

Dockerfile.nox

@@ -6,7 +6,7 @@ RUN ln -snf /usr/share/zoneinfo/$TZ /etc/localtime && echo $TZ > /etc/timezone
 RUN apt-get update && apt-get upgrade -y
 RUN apt-get install git file gcc make time wget zip -y
 #[sv2v]
-RUN wget https://github.com/zachjs/sv2v/releases/download/v0.0.9/sv2v-Linux.zip
+RUN wget https://github.com/zachjs/sv2v/releases/download/v0.0.11/sv2v-Linux.zip
 RUN unzip sv2v-Linux.zip && rm sv2v-Linux.zip
 RUN ln -s /sv2v-Linux/sv2v /usr/bin/sv2v && chmod +x /sv2v-Linux/sv2v
 # [Verilator]

Dockerfile.synlig

@@ -0,0 +1,21 @@
+FROM ubuntu:latest
+LABEL author="Anderson Ignacio da Silva"
+LABEL maintainer="anderson@aignacio.com"
+ENV TZ=Europe/Dublin
+RUN ln -snf /usr/share/zoneinfo/$TZ /etc/localtime && echo $TZ > /etc/timezone
+RUN apt-get update && apt-get upgrade -y
+RUN apt-get install git file gcc make time wget zip -y
+# Install synlig / Yosys / surelog
+RUN apt install -y gcc-11 g++-11 build-essential cmake tclsh ant default-jre swig google-perftools libgoogle-perftools-dev python3 python3-dev python3-pip uuid uuid-dev tcl-dev flex libfl-dev git pkg-config libreadline-dev bison libffi-dev wget python3-orderedmultidict
+RUN git clone https://github.com/chipsalliance/synlig.git
+WORKDIR /synlig
+RUN git submodule sync
+RUN git submodule init
+ENV GIT_TRACE=1
+RUN git submodule update --init --recursive third_party/surelog
+RUN git submodule update --init --recursive third_party/yosys
+RUN make install
+ENV PATH=/synlig/out/release/bin:$PATH
+
+
+

Dockerfile.yosys

@@ -0,0 +1,21 @@
+FROM ubuntu:latest
+LABEL author="Anderson Ignacio da Silva"
+LABEL maintainer="anderson@aignacio.com"
+ENV TZ=Europe/Dublin
+RUN ln -snf /usr/share/zoneinfo/$TZ /etc/localtime && echo $TZ > /etc/timezone
+RUN apt-get update && apt-get upgrade -y
+RUN apt-get install git file gcc make time wget zip -y
+# OSS CAD suite
+RUN wget -c http://github.com/YosysHQ/oss-cad-suite-build/releases/download/2024-04-23/oss-cad-suite-linux-x64-20240423.tgz -O - | tar -xz
+ENV PATH="/oss-cad-suite/bin:$PATH"
+#[sv2v]
+RUN wget https://github.com/zachjs/sv2v/releases/download/v0.0.11/sv2v-Linux.zip
+RUN unzip sv2v-Linux.zip && rm sv2v-Linux.zip
+RUN ln -s /sv2v-Linux/sv2v /usr/bin/sv2v && chmod +x /sv2v-Linux/sv2v
+RUN git clone https://github.com/parallaxsw/OpenSTA.git /opensta
+RUN apt-get install cmake build-essential flex bison swig clang expect tcl-dev libeigen3-dev -y
+WORKDIR /opensta
+RUN mkdir build
+RUN cd build && cmake ../
+RUN cd build && make -j`nproc`
+RUN cd build && make install

README.md

@@ -13,6 +13,7 @@
 * [FreeRTOS](#freertos)
 * [Compliance Tests](#compliance)
 * [CoreMark](#coremark)
+* [Synthesis](#synth)
 * [License](#lic)
 
 ## <a name="intro"></a> Introduction
@@ -244,7 +245,25 @@ seedcrc          : 0x18f2
 [0]crcfinal      : 0x0cac
 Correct operation validated. See README.md for run and reporting rules.
 ```
+## <a name="synth"></a> Synthesis
+
+Adapting the setup to [Ibex Core - low risc](https://github.com/lowRISC/ibex/tree/master/syn), attached is the command to perform synthesis on the 45nm nangate PDK.
+```bash
+docker run  -v .:/test -w /test --rm aignacio/oss_cad_suite:latest bash -c "cd /test/synth && ./syn_yosys.sh"
+```
+
+### Area results:
+* 27.04 kGE @ 250MHz in 45nm
+
+```bash
+...
+End of script. Logfile hash: 39230763f8, CPU: user 15.51s system 0.15s, MEM: 175.05 MB peak
+Yosys 0.40+25 (git sha1 171577f90, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os)
+Time spent: 72% 2416x select (5 sec), 22% 2x read_verilog (1 sec), ...
+Area in kGE =  27.04
+```
 
 ## <a name="lic"></a> License
+
 NoX is licensed under the permissive MIT license. Please refer to the [LICENSE](LICENSE) file for details.
 

synth/README.md

@@ -0,0 +1,145 @@
+**This synthesis flow is experimental and under development, it does not produce
+tape-out quality netlists and area/timing numbers it generates are not
+representative of what would be achievable with a tape-out quality flow**
+
+# Yosys/OpenSTA Ibex Synthesis Flow
+
+This is a synthesis-only implementation flow using Yosys for Synthesis and
+OpenSTA to produce timing reports. Its outputs are:
+
+* A pre-mapping netlist - Gate-level verilog using generic gates that hasn't
+  been mapped to a standard-cell library yet
+* A post synthesis netlist - Gate-level verilog after optimisation mapped to a
+  standard-cell library
+* An STA netlist - Logically equivilent to the netlist above but with changes to
+  allow processing by OpenSTA
+* Area/Cell Usage report - Total area consumed by utilised cells and counts of
+  each cell instance used
+* Timing reports - Overal timing report and reports broken down into various
+  path groups (register to register paths and per IO reports)
+
+Yosys doesn't yet support the full subset of SystemVerilog used by Ibex so the
+sv2v tool is used to first convert the Ibex RTL into the SystemVerilog subset
+Yosys can process.
+
+# Synthesis flow requirements
+
+The following must be installed:
+
+* Python 3 (version >= 3.5)
+* sv2v - https://github.com/zachjs/sv2v
+* Yosys - https://github.com/YosysHQ/yosys
+* OpenSTA - https://github.com/The-OpenROAD-Project/OpenSTA
+
+The flow was tested with yosys 0.9 and OpenSTA 2.2 but may work with other
+versions.  A standard cell library is also required in the liberty (.lib)
+format. The following Open Libraries can be used:
+
+* Nangate45 - https://github.com/The-OpenROAD-Project/OpenROAD-flow/tree/master/flow/platforms/nangate45
+
+# Synthesis flow setup
+
+The synthesis flow is configured via environment variables. The `syn_setup.sh`
+file is used to set the environment variables for the flow and any changes made
+should be placed there.  An example `syn_setup.example.sh` is included. A copy
+of this named `syn_setup.sh` must be made and the values in it set appropriately
+for the flow to work.
+
+The environment variables that must be set in `syn_setup.sh` are
+
+* `LR_SYNTH_CELL_LIBRARY_PATH` - The path to the standard cell library, this
+  should point to the absolute path of the Nangate45 library
+  (`NangateOpenCellLibrary_typical.lib`).
+* `LR_SYNTH_CELL_LIBRARY_NAME` - The name of the standard cell library, this is
+  used to alter the flow configuration for the library, currently 'nangate' is
+  the only supported value
+
+# Running the synthesis flow
+
+Once `syn_setup.sh` has been created, call `syn_yosys.sh` to run the entire
+flow. All outputs are placed under the `syn/syn_out` directory with the prefix
+`ibex_` with the current date/time forming the rest of the name, e.g.
+`syn/syn_out/ibex_06_01_2020_11_19_15`
+
+- `syn/syn_out/ibex_date`
+  - `reports` - All of the generated reports
+    - area.rpt - Total area used and per cell instance counts
+    - `timing`
+      - *.rpt - Raw reports from OpenSTA, gives full paths
+      - *.csv.rpt - CSV reports gives start and end point and slack
+    - `log`
+      - syn.log - Log of the Yosys run
+      - sta.log - Log of the OpenSTA run
+    - `generated`
+      - *.v - Ibex RTL after sv2v processing
+      - ibex_top.pre_map.v - Pre-mapping synthesis netlists
+      - ibex_top_netlist.v - Post-synthesis netlist
+      - ibex_top_netlist.sta.v - Post-synthesis netlist usable by OpenSTA
+      - ibex_top.[library-name].out.sdc - Generated .sdc timing constraints
+        file
+
+If you wish to change the results directory naming or location edit
+`syn_setup.sh` appropriately.
+
+# Timing constraints
+
+Two files specify the timing constraints and timing related settings for the
+flow. These are used to generate a single .sdc file
+
+* `ibex_top_lr_synth_core.tcl` - This specifies the constraints on all inputs
+  and outputs as a fraction of a clock cycle, the names of the clock and reset
+  inputs and the desired clock period in ps
+* `ibex.[library-name].sdc` - Header to include in generated .sdc file. Settings
+  can be library dependent so the `LR_SYNTH_CELL_LIBRARY_NAME` environment
+  varible is used to supply the `[library-name]` part of the name
+
+# Timing reports
+
+Timing reports are produced for the following path groups
+* Overall - Every path in the design, WNS (worst negative slack) from this report is the design WNS
+  that limits the frequency
+* reg2reg - Paths from register to register
+* in2reg - Paths from any input to any register
+* reg2out - Paths from any register to any output
+* in2out - Paths from any input to any output
+
+They are available in two formats .rpt and .csv.rpt. The .rpt is the full output
+from OpenSTA and gives the full path between the start and end points. The CSV
+version contains the start-point, end-point and WNS (one path per line). CSV
+reports have had their start and end points translated to human readable names
+(though this isn't 100% reliable). The raw OpenSTA reports generally contain
+only generated cell names so will require further netlist inspection (via Yosys
+or simply looking at the netlist .v) to make sense of.
+
+# Post-synthesis inspection
+
+Both Yosys and OpenSTA can be run to perform further inspection on the generated
+synthesis. TCL is provided to setup the tools appropriately.
+
+First the environment variables must be setup for the flow and the directory
+containing the synthesis output set. This can be done with `syn_setup.sh`
+
+```
+$ source syn_setup.sh syn_out_06_01_2020_11_19_15/
+```
+
+Where `syn_out_06_01_2020_11_19_15/` is directory containing the synthesis
+outputs. Then start Yosys or OpenSTA and run one of the provided TCL files
+
+* `./tcl/yosys_pre_map.tcl` - Loads the pre-mapping netlist
+* `./tcl/yosys_post_synth.tcl` - Load the post-synthesis netlist
+
+So to load the post-synthesis netlist in Yosys:
+
+```
+$ yosys
+yosys> tcl ./tcl/yosys_post_synth.tcl
+```
+
+To open the design in OpenSTA
+
+```
+$ sta
+% source ./tcl/sta_open_design.tcl
+```
+

synth/lec_sv2v.do

@@ -0,0 +1,55 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// LEC dofile for script lec_sv2v.sh.  A similar script is used in 
+// OpenTitan, any updates or fixes here may need to be reflected in the 
+// OpenTitan script as well:
+// https://github.com/lowRISC/opentitan/blob/master/hw/formal/lec_sv2v.do
+
+//-------------------------------------------------------------------------
+// read in golden (SystemVerilog) and revised (Verilog)
+//-------------------------------------------------------------------------
+
+// map all multi-dimensional ports (including structs) onto 1-dim. ports
+set naming rule -mdportflatten
+
+read design -golden -sv09 -f flist_gold -rootonly -root $LEC_TOP
+read design -revised -sys -f flist_rev  -rootonly -root $LEC_TOP
+// TODO: instead of using switch -sys (for old SystemVerilog,
+// older than sv2009) we should use -ve (for Verilog). But
+// this currently doesn't work because sv2v doesn't translate
+// .* port connections. Is that an sv2v bug?
+
+//-------------------------------------------------------------------------
+// pre-LEC reports
+//-------------------------------------------------------------------------
+report rule check -verbose
+report design data
+report black box
+report module
+
+//-------------------------------------------------------------------------
+// compare
+//-------------------------------------------------------------------------
+set system mode lec
+set parallel option -threads 8
+
+// map unreachable points
+set mapping method -nets -mem -unreach
+map key points
+report unmapped points
+
+add compare point -all
+compare -threads 8 -noneq_stop 1
+analyze abort -compare
+
+//-------------------------------------------------------------------------
+// reports
+//-------------------------------------------------------------------------
+report compare data -class nonequivalent -class abort -class notcompared
+report verification -verbose
+report statistics
+usage
+
+exit -force

synth/lec_sv2v.sh

@@ -0,0 +1,82 @@
+#!/bin/bash
+
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+# This script converts all SystemVerilog RTL files to Verilog
+# using sv2v and then runs LEC (Cadence Conformal) to check if
+# the generated Verilog is logically equivalent to the original
+# SystemVerilog.  A similar script is used in OpenTitan, any updates 
+# or fixes here may need to be reflected in the OpenTitan script as well
+# https://github.com/lowRISC/opentitan/blob/master/util/syn_yosys.sh
+#
+# The following tools are required:
+#  - sv2v: SystemVerilog-to-Verilog converter from github.com/zachjs/sv2v
+#  - Cadence Conformal
+#
+# Usage:
+#   ./lec_sv2v.sh |& tee lec.log
+
+#-------------------------------------------------------------------------
+# use fusesoc to generate files and file list
+#-------------------------------------------------------------------------
+rm -Rf build lec_out
+fusesoc --cores-root .. run --tool=icarus --target=lint \
+  --setup "lowrisc:ibex:ibex_top" > /dev/null 2>&1
+
+# copy all files to lec_out
+mkdir lec_out
+cp build/*/src/*/*.sv build/*/src/*/*/*.sv lec_out
+cd lec_out || exit
+
+# copy file list and remove incdir, RVFI define, and sim-file
+grep -E -v 'incdir|RVFI|simulator_ctrl' ../build/*/*/*.scr > flist_gold
+
+# remove all hierarchical paths
+sed -i 's!.*/!!' flist_gold
+
+# generate revised flist by replacing '.sv' by '.v' and removing packages
+sed 's/.sv/.v/' flist_gold | grep -v "_pkg.v" > flist_rev
+
+#-------------------------------------------------------------------------
+# convert all RTL files to Verilog using sv2v
+#-------------------------------------------------------------------------
+printf "\nSV2V ERRORS:\n"
+
+for file in *.sv; do
+  module=$(basename -s .sv "$file")
+  sv2v --define=SYNTHESIS ./*_pkg.sv prim_assert.sv "$file" > "${module}".v
+done
+
+# remove *pkg.v files (they are empty files and not needed)
+rm -f ./*_pkg.v prim_assert.v prim_util_memload.v
+
+# overwrite the prim_clock_gating modules with the module from ../rtl
+cp ../rtl/prim_clock_gating.v .
+cp ../rtl/prim_clock_gating.v prim_clock_gating.sv
+
+#-------------------------------------------------------------------------
+# run LEC (generated Verilog vs. original SystemVerilog)
+#-------------------------------------------------------------------------
+printf "\n\nLEC RESULTS:\n"
+
+for file in *.v; do
+  LEC_TOP=$(basename -s .v "$file")
+  export LEC_TOP
+
+  # run Conformal LEC
+  lec -xl -nogui -nobanner \
+    -dofile  ../lec_sv2v.do \
+    -logfile lec_"${LEC_TOP}".log \
+    <<< "exit -force" > /dev/null 2>&1
+
+  # summarize results
+  check=$(grep "Compare Results" lec_"${LEC_TOP}".log)
+  if [ $? -ne 0 ]; then
+    result="CRASH"
+  else
+    result=$(echo "$check" | awk '{ print $4 }')
+  fi
+  printf "%-25s %s\n" "$LEC_TOP" "$result"
+done

synth/nox.nangate.sdc

@@ -0,0 +1,6 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+set_driving_cell [all_inputs] -lib_cell BUF_X2
+set_load 10.0 [all_outputs]

synth/nox_abc.nangate.sdc

@@ -0,0 +1,6 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+set_driving_cell BUF_X2
+set_load 10.0 [all_outputs]