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This Repo consists of implementation for RISC V Architecture on how instructions are fetched, decoded and executed. I have implemented the Out of order Execution, Dynamic Branch Prediction and Cache Simulations

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Name		Name	Last commit message	Last commit date
Latest commit History 40 Commits
Images		Images
assembler		assembler
pa0		pa0
pa1		pa1
pa2		pa2
pa3		pa3
pa4		pa4
project		project
.gitignore		.gitignore
README.md		README.md
riscv-uconn-PA0-PA1.pdf		riscv-uconn-PA0-PA1.pdf
riscv-uconn-encodings.pdf		riscv-uconn-encodings.pdf
riscv-uconn.pdf		riscv-uconn.pdf

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Computer-Architecture

A UCONN course

Helpful Resources

C Bitwise Operators: https://www.youtube.com/watch?v=BGeOwlIGRGI

RISC V

GDB Debugger

Start GDB debugger for code compilation
```
gdb ./simulator
```
Set a Breakpoint where you want to
```
(gdb) break main
```
Run the Program: Start running the program:
```
Copy code
(gdb) run
```
The program will run and pause at the breakpoint you've set.
Find the Struct Information: If you know the name of the struct instance, use the ptype command to print the type definition of the struct. This will reveal all its members.

For example:
```
(gdb) ptype struct_instance
```
This will print the struct definition, including the data members (names and types).

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This Repo consists of implementation for RISC V Architecture on how instructions are fetched, decoded and executed. I have implemented the Out of order Execution, Dynamic Branch Prediction and Cache Simulations

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