default to flash 1060

workaround SysTick race condition in FreeRTOS example

examples/nxp/rt1060-evk-make-baremetal-builtin/Makefile

@@ -3,7 +3,7 @@ CFLAGS += -Wformat-truncation -fno-common -Wconversion -Wno-sign-conversion
 CFLAGS += -g3 -Os -ffunction-sections -fdata-sections
 CFLAGS += -I. -Icmsis_core/CMSIS/Core/Include -Icmsis_mcu/devices/MIMXRT1062 #-DCPU_MIMXRT1062DVL6B
 CFLAGS += -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16 $(CFLAGS_EXTRA)
-LDSCRIPT = link_ram.ld
+LDSCRIPT = link.ld
 LDFLAGS ?= -T$(LDSCRIPT) -nostdlib -nostartfiles --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map 
 
 SOURCES = main.c syscalls.c sysinit.c
@@ -22,11 +22,11 @@ else
   RM = rm -rf
 endif
 
+all build example update: SOURCES += flash_image.c
 all build example: firmware.bin
 
-image: LDSCRIPT = link.ld
-image: SOURCES += flash_image.c
-image: firmware.bin
+ram: LDSCRIPT = link_ram.ld
+ram: firmware.bin
 
 firmware.bin: firmware.elf
 	arm-none-eabi-objcopy -O binary $< $@
@@ -36,7 +36,7 @@ firmware.elf: cmsis_core cmsis_mcu $(SOURCES) hal.h link_ram.ld link.ld Makefile
 	arm-none-eabi-size $@
 
 flash: firmware.bin
-	st-flash --reset write $< 0x8000000
+# flash
 
 cmsis_core:     # ARM CMSIS core headers
 	git clone -q --depth 1 -b 5.9.0 https://github.com/ARM-software/CMSIS_5 $@
@@ -56,6 +56,16 @@ endif
 DEVICE_URL ?= https://dash.vcon.io/api/v3/devices/13
 update: firmware.bin
 	curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/ota --data-binary @$<
+
+update updateram: CFLAGS += -DUART_DEBUG=LPUART3
+
+test: update
+	curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=5 | tee /tmp/output.txt
+	grep 'READY, IP:' /tmp/output.txt       # Check for network init
+
+
+updateram: ram
+	curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/ota --data-binary @firmware.bin
 	curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"init"}'
 	curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"wm,e000edf0,a05f0003 wm,e000edfc,1 wm,e000ed0c,5fa0004"}'
 	curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"init"}'
@@ -65,12 +75,10 @@ update: firmware.bin
 	curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"'"$$REQ"'"}'
 	curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"wm,e000edf0,a05f0001"}'
 
-test update testimage: CFLAGS += -DUART_DEBUG=LPUART3
-test: update
+testram: updateram
 	curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=5 | tee /tmp/output.txt
 	grep 'READY, IP:' /tmp/output.txt       # Check for network init
 
-testimage: image
 
 clean:
 	$(RM) firmware.* *.su cmsis_core cmsis_mcu mbedtls *.zip

examples/nxp/rt1060-evk-make-freertos-builtin/FreeRTOSConfig.h

@@ -35,4 +35,4 @@
 
 #define vPortSVCHandler SVC_Handler
 #define xPortPendSVHandler PendSV_Handler
-#define xPortSysTickHandler SysTick_Handler
+//#define xPortSysTickHandler SysTick_Handler

examples/nxp/rt1060-evk-make-freertos-builtin/Makefile

@@ -3,7 +3,8 @@ CFLAGS += -Wformat-truncation -fno-common -Wconversion -Wno-sign-conversion
 CFLAGS += -g3 -Os -ffunction-sections -fdata-sections
 CFLAGS += -I. -Icmsis_core/CMSIS/Core/Include -Icmsis_mcu/devices/MIMXRT1062 #-DCPU_MIMXRT1062DVL6B
 CFLAGS += -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16 $(CFLAGS_EXTRA)
-LDFLAGS ?= -Tlink_ram.ld -nostdlib -nostartfiles --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map 
+LDSCRIPT = link.ld
+LDFLAGS ?= -T$(LDSCRIPT) -nostdlib -nostartfiles --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map 
 
 SOURCES = main.c syscalls.c sysinit.c
 SOURCES += cmsis_mcu/devices/MIMXRT1062/gcc/startup_MIMXRT1062.S # NXP startup file. Compiler-dependent!
@@ -27,19 +28,23 @@ else
   RM = rm -rf
 endif
 
+all build example update: SOURCES += flash_image.c
 all build example: firmware.bin
 
+ram: LDSCRIPT = link_ram.ld
+ram: firmware.bin
+
 firmware.bin: firmware.elf
 	arm-none-eabi-objcopy -O binary $< $@
 
-firmware.elf: FreeRTOS-Kernel cmsis_core cmsis_mcu $(SOURCES) hal.h link_ram.ld mongoose_custom.h
+firmware.elf: FreeRTOS-Kernel cmsis_core cmsis_mcu $(SOURCES) hal.h link_ram.ld link.ld mongoose_custom.h
 	arm-none-eabi-gcc $(SOURCES) $(wildcard FreeRTOS-Kernel/*.c) $(CFLAGS) $(LDFLAGS) -o $@
 
 flash: firmware.bin
-	st-flash --reset write $< 0x8000000
+# flash
 
-cmsis_core:  # ARM CMSIS core headers
-	git clone --depth 1 -b 5.9.0 https://github.com/ARM-software/CMSIS_5 $@
+cmsis_core:     # ARM CMSIS core headers
+	git clone -q --depth 1 -b 5.9.0 https://github.com/ARM-software/CMSIS_5 $@
 cmsis_mcu:
 	curl -sL https://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMXRT1062_DFP.17.1.0.pack -o $@.zip
 	mkdir $@ && cd $@ && unzip -q ../$@.zip
@@ -50,6 +55,16 @@ FreeRTOS-Kernel:  # FreeRTOS sources
 DEVICE_URL ?= https://dash.vcon.io/api/v3/devices/13
 update: firmware.bin
 	curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/ota --data-binary @$<
+
+update updateram: CFLAGS += -DUART_DEBUG=LPUART3
+
+test: update
+	curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=5 | tee /tmp/output.txt
+	grep 'READY, IP:' /tmp/output.txt       # Check for network init
+
+
+updateram: ram
+	curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/ota --data-binary @firmware.bin
 	curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"init"}'
 	curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"wm,e000edf0,a05f0003 wm,e000edfc,1 wm,e000ed0c,5fa0004"}'
 	curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"init"}'
@@ -59,11 +74,10 @@ update: firmware.bin
 	curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"'"$$REQ"'"}'
 	curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"wm,e000edf0,a05f0001"}'
 
-test update: CFLAGS += -DUART_DEBUG=LPUART3
-test: update
+testram: updateram
 	curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=5 | tee /tmp/output.txt
 	grep 'READY, IP:' /tmp/output.txt       # Check for network init
-#	grep 'MQTT connected' /tmp/output.txt   # Check for MQTT connection success
+
 
 clean:
 	$(RM) firmware.* *.su cmsis_core cmsis_mcu FreeRTOS-Kernel *.zip

examples/nxp/rt1060-evk-make-freertos-builtin/dcd.h

@@ -0,0 +1 @@
+../rt1060-evk-make-baremetal-builtin/dcd.h

examples/nxp/rt1060-evk-make-freertos-builtin/flash_image.c

@@ -0,0 +1 @@
+../rt1060-evk-make-baremetal-builtin/flash_image.c

examples/nxp/rt1060-evk-make-freertos-builtin/flexspi.h

@@ -0,0 +1 @@
+../rt1060-evk-make-baremetal-builtin/flexspi.h

examples/nxp/rt1060-evk-make-freertos-builtin/hal.h

@@ -319,3 +319,38 @@ static inline void ethernet_init(void) {
   }
 // NOTE: You can fuse your own MAC and read it from OCOTP->MAC0, OCOTP->MAC1,
 // OCOTP->MAC2
+
+static inline void flash_init(void) { // QSPI in FlexSPI
+  // set pins
+  clock_periph(4, CCM_CCGR4_CG1_SHIFT, CLOCK_ON_RUN_WAIT);  // iomuxc_ipg_clk_s
+  gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05, 1);  // set for DQS
+  IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05] |= IOMUXC_SW_MUX_CTL_PAD_SION(1);  // loop signal back from pin
+  periph_mux_config(kIOMUXC_FLEXSPIA_DQS_SELECT_INPUT, 0);  // drive peripheral from B1_05
+  gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE);
+  gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06, 1);  // set for SS
+  IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06] |= IOMUXC_SW_MUX_CTL_PAD_SION(1);  // loop signal back from pin
+  gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE);
+  gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07, 1);  // set for SCLK
+  IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07] |= IOMUXC_SW_MUX_CTL_PAD_SION(1);  // loop signal back from pin
+  periph_mux_config(kIOMUXC_FLEXSPIA_SCK_SELECT_INPUT, 0);  // drive peripheral from B1_07
+  gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE);
+  gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08, 1);  // set for DATA0
+  IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08] |= IOMUXC_SW_MUX_CTL_PAD_SION(1);  // loop signal back from pin
+  periph_mux_config(kIOMUXC_FLEXSPIA_DATA0_SELECT_INPUT, 0);  // drive peripheral from B1_08
+  gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE);
+  gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09, 1);  // set for DATA1
+  IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09] |= IOMUXC_SW_MUX_CTL_PAD_SION(1);  // loop signal back from pin
+  periph_mux_config(kIOMUXC_FLEXSPIA_DATA1_SELECT_INPUT, 0);  // drive peripheral from B1_09
+  gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE);
+  gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10, 1);  // set for DATA2
+  IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10] |= IOMUXC_SW_MUX_CTL_PAD_SION(1);  // loop signal back from pin
+  periph_mux_config(kIOMUXC_FLEXSPIA_DATA2_SELECT_INPUT, 0);  // drive peripheral from B1_10
+  gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE);
+  gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11, 1);  // set for DATA3
+  IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11] |= IOMUXC_SW_MUX_CTL_PAD_SION(1);  // loop signal back from pin
+  periph_mux_config(kIOMUXC_FLEXSPIA_DATA3_SELECT_INPUT, 0);  // drive peripheral from B1_11
+  gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE);
+  // set FlexSPI clock
+  SETBITS(CCM->CSCMR1, CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK | CCM_CSCMR1_FLEXSPI_PODF_MASK, CCM_CSCMR1_FLEXSPI_CLK_SEL(3) | CCM_CSCMR1_FLEXSPI_PODF(7));  // select PLL3 PFD0 /8
+  clock_periph(6, CCM_CCGR6_CG5_SHIFT, CLOCK_ON_RUN_WAIT);  // enable
+}

examples/nxp/rt1060-evk-make-freertos-builtin/link.ld

@@ -1,22 +1,22 @@
 ENTRY(Reset_Handler);
 MEMORY {
-  flash_cfg(rx)  : ORIGIN = 0x60000000, LENGTH = 4k
-  flash_ivt(rx)  : ORIGIN = 0x60001000, LENGTH = 4k
+  flash_hdr(rx)  : ORIGIN = 0x60000000, LENGTH = 8k
   flash_irq(rx)  : ORIGIN = 0x60002000, LENGTH = 1k
   flash_code(rx) : ORIGIN = 0x60002400, LENGTH = 8183k
 
-  ram0(rx)       : ORIGIN = 0x00000000, LENGTH = 128k
-  ram1(rw)       : ORIGIN = 0x20000000, LENGTH = 128k 
-  ram2(rw)       : ORIGIN = 0x20200000, LENGTH = 256k
+  itcram(rx)       : ORIGIN = 0x00000000, LENGTH = 128k
+  dtcram(rw)       : ORIGIN = 0x20000000, LENGTH = 128k
+  ocram(rw)        : ORIGIN = 0x20200000, LENGTH = 256k   /* Is this cached ? */
 }
-__StackTop = ORIGIN(ram2) + LENGTH(ram2);
+__StackTop = ORIGIN(dtcram) + LENGTH(dtcram);
 
 SECTIONS {
-  .cfg  : { __FLASH_BASE = .; KEEP(* (.cfg)) } > flash_cfg
-  .ivt  : { KEEP(*(.ivt)) } > flash_ivt
+  .hdr  : { FILL(0xff) ; KEEP(*(.cfg)) . = 0x1000 ; KEEP(*(.ivt)) . = 0x1020 ;
+            KEEP(*(.dat)) . = 0x1030 ; KEEP(*(.dcd)) . = 0x2000 ;} >flash_hdr
   .irq  : { KEEP(*(.isr_vector)) }  > flash_irq
-  .text : { *(.text* .text.*) *(.rodata*) __etext = .; } > flash_code
-  .data : { __data_start__ = .; *(.data SORT(.data.*)) __data_end__ = .; } > ram1 AT > flash_code
-  .bss  : { __bss_start__ = .; *(.bss SORT(.bss.*) COMMON) __bss_end__ = .; } > ram1
+  .text : { *(.text* .text.*) *(.rodata*) ; } > flash_code
+  .data : { __data_start__ = .; *(.data SORT(.data.*)) __data_end__ = .; } > dtcram AT > flash_code
+  __etext = LOADADDR(.data);
+  .bss  : { __bss_start__ = .; *(.bss SORT(.bss.*) COMMON) __bss_end__ = .; } > dtcram
   _end = .;
 }

examples/nxp/rt1060-evk-make-freertos-builtin/main.c

@@ -7,6 +7,14 @@
 
 #define BLINK_PERIOD_MS 1000  // LED blinking period in millis
 
+// workaround optimizer somehow causing SysTick to fire before FreeRTOS has
+// fully initialized
+extern void xPortSysTickHandler(void);
+void SysTick_Handler(void) {
+  if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED)
+    xPortSysTickHandler();
+}
+
 void mg_random(void *buf, size_t len) {  // Use on-board RNG
   for (size_t n = 0; n < len; n += sizeof(uint32_t)) {
     uint32_t r = rng_read();

examples/nxp/rt1060-evk-make-freertos-builtin/sysinit.c

@@ -10,14 +10,18 @@
 uint32_t SystemCoreClock = SYS_FREQUENCY;
 
 // - 14.4, Figure 14-2: clock tree
-// - 14.7.4: ARM_PODF defaults to /2
+// - 14.7.4: ARM_PODF defaults to /2; 9.5.3 Table 9-7: ROM agrees
 // - 14.7.5: AHB_PODF defaults to /1; IPG_PODF defaults to /4; PERIPH_CLK_SEL
 // defaults to derive clock from pre_periph_clk_sel
-// - 14.7.6: PRE_PERIPH_CLK_SEL defaults to derive clock from divided PLL1.
-// - (For 528MHz operation, we need to set it to derive clock from PLL2).
+//   - 9.5.3 Table 9-7: ROM changes IPG_PODF to /3
+// - 14.7.6: PRE_PERIPH_CLK_SEL defaults to derive clock from divided
+// PLL1; 9.5.3 Table 9-7: ROM agrees
+// - (For 528MHz operation, we need to set it to derive clock from PLL2)
+// - 14.7.7: PER_CLK defaults to IPG/1; 9.5.3 Table 9-7: ROM changes it to IPG/2
 // - 14.6.1.3.1 ARM PLL (PLL1); 13.3.2.2 PLLs
 // - 14.8.1: PLL1 is powered off and bypassed to 24MHz. Fout = 24MHz *
 // div_select/2
+//   - 9.5.3 Table 9-7: ROM enables this PLL and sets it up
 // - For 600MHz operation, we need to set PLL1 on
 // - Datasheet 4.1.3: System frequency/Bus frequency max 600/150MHz respectively
 // (AHB/IPG)
@@ -42,9 +46,15 @@ void SystemInit(void) {  // Called automatically by startup code (ints masked)
   SETBITS(DCDC->REG3, DCDC_REG3_TRG_MASK, DCDC_REG3_TRG(0x12));
   while ((DCDC->REG0 & DCDC_REG0_STS_DC_OK_MASK) == 0)
     spin(1);  // Wait for DCDC_STS_DC_OK
+  // ROM fiddles with AHB divider, wait and then keep bits at 0 (expected)
+  while (CCM->CDHIPR & CCM_CDHIPR_AHB_PODF_BUSY_MASK) spin(1);
+  SETBITS(CCM->CBCDR, CCM_CBCDR_IPG_PODF_MASK | CCM_CBCDR_AHB_PODF_MASK,
+          CCM_CBCDR_IPG_PODF(3)); // keep AHB, set IPG divider /4 (150MHz)
   SETBITS(CCM->CSCMR1, CCM_CSCMR1_PERCLK_PODF_MASK,
           CCM_CSCMR1_PERCLK_PODF(1));  // Set PERCLK divider /2 (75MHz)
-  // Set clock to 600 MHz. Power PLL on and configure divider
+  // Set clock to 600 MHz. Power PLL on and configure divider (ROM boot code
+  // fiddles with the PLL, bypass first)
+  CCM_ANALOG->PLL_ARM |= CCM_ANALOG_PLL_ARM_BYPASS_MASK;
   SETBITS(CCM_ANALOG->PLL_ARM,
           CCM_ANALOG_PLL_ARM_POWERDOWN_MASK |
               CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK,
@@ -55,12 +65,14 @@ void SystemInit(void) {  // Called automatically by startup code (ints masked)
       ~CCM_ANALOG_PLL_ARM_BYPASS_MASK;  // Disable Bypass (switch to PLL)
   // 14.5 Table 14-4: uart_clk_root
   // 14.4: uart_clk_root = PLL3/6 or OSC; CCM_CSCDR1 (14.7.9) defaults to
-  // PLL3/6/1
+  // PLL3/6/1; but ROM boot code fiddles with the divider (9.5.3 Table 9-7)
   CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_POWER_MASK;  // Power PLL on
   while ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_LOCK_MASK) == 0)
     spin(1);  // wait until it is stable
   CCM_ANALOG->PLL_USB1 &=
       ~CCM_ANALOG_PLL_USB1_BYPASS_MASK;  // Disable Bypass (switch to PLL)
+  CCM->CSCDR1 &=
+      ~(CCM_CSCDR1_UART_CLK_SEL_MASK | CCM_CSCDR1_UART_CLK_PODF_MASK);
   rng_init();  // Initialise random number generator
   // NXP startup code calls SystemInit BEFORE initializing RAM...
   SysTick_Config(SYS_FREQUENCY / 1000);  // Sys tick every 1ms