[JIT] Enable EGPRs in JIT by adding REX2 encoding to the backend. #106557
+974
−161
There are no files selected for viewing
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
|
|
@@ -9053,6 +9053,223 @@ void CodeGen::genAmd64EmitterUnitTestsSse2() | |
| GetEmitter()->emitIns_R_R_R(INS_cvtsd2ss, EA_8BYTE, REG_XMM0, REG_XMM1, REG_XMM2); | ||
| } | ||
|
|
||
| /***************************************************************************** | ||
| * Unit tests for the APX instructions. | ||
| */ | ||
|
|
||
| void CodeGen::genAmd64EmitterUnitTestsApx() | ||
| { | ||
| emitter* theEmitter = GetEmitter(); | ||
|
|
||
| genDefineTempLabel(genCreateTempLabel()); | ||
|
|
||
| // This test suite needs REX2 enabled. | ||
| assert(theEmitter->UseRex2Encoding() || theEmitter->emitComp->DoJitStressRex2Encoding()); | ||
|
There was a problem hiding this comment. Is it the case that these are all "normal" non-APX / non-REX2 instructions, that only test REX2 if REX2 stress is enabled? So to use this, you need to set Note that these asserts will cause Presumably there will be additional cases, with EGPR high registers, where the REX2 encodings will be required. There was a problem hiding this comment. If we temporarily turn on REX2 stress only in this function, then only the code generator will do its work using REX2 encoding, after we exit the function and turn off REX2 stress, the corresponding emitter will emit code under REX2 off. I can make it an early return if REX2 is not stressed. And yes, currently the emitter unit test can only perform encoding on GPR0~15, while we are still waiting for the EGPR definition, that will come with the PR for LSRA. I can add a TODO item for more unit tests with EGPRs to #110414 if needed. |
||
|
|
||
| theEmitter->emitIns_R_R(INS_add, EA_1BYTE, REG_EAX, REG_ECX); | ||
| theEmitter->emitIns_R_R(INS_add, EA_2BYTE, REG_EAX, REG_ECX); | ||
| theEmitter->emitIns_R_R(INS_add, EA_4BYTE, REG_EAX, REG_ECX); | ||
| theEmitter->emitIns_R_R(INS_add, EA_8BYTE, REG_EAX, REG_ECX); | ||
tannergooding marked this conversation as resolved.
Show resolved
Hide resolved
|
||
| theEmitter->emitIns_R_R(INS_or, EA_4BYTE, REG_EAX, REG_ECX); | ||
| theEmitter->emitIns_R_R(INS_adc, EA_4BYTE, REG_EAX, REG_ECX); | ||
| theEmitter->emitIns_R_R(INS_sbb, EA_4BYTE, REG_EAX, REG_ECX); | ||
| theEmitter->emitIns_R_R(INS_and, EA_4BYTE, REG_EAX, REG_ECX); | ||
| theEmitter->emitIns_R_R(INS_sub, EA_4BYTE, REG_EAX, REG_ECX); | ||
| theEmitter->emitIns_R_R(INS_xor, EA_4BYTE, REG_EAX, REG_ECX); | ||
| theEmitter->emitIns_R_R(INS_cmp, EA_4BYTE, REG_EAX, REG_ECX); | ||
| theEmitter->emitIns_R_R(INS_test, EA_4BYTE, REG_EAX, REG_ECX); | ||
| theEmitter->emitIns_R_R(INS_bsf, EA_4BYTE, REG_EAX, REG_ECX); | ||
| theEmitter->emitIns_R_R(INS_bsr, EA_4BYTE, REG_EAX, REG_ECX); | ||
|
|
||
| theEmitter->emitIns_R_R(INS_cmovo, EA_4BYTE, REG_EAX, REG_ECX); | ||
|
|
||
| theEmitter->emitIns_Mov(INS_mov, EA_4BYTE, REG_EAX, REG_ECX, false); | ||
| theEmitter->emitIns_Mov(INS_movsx, EA_2BYTE, REG_EAX, REG_ECX, false); | ||
| theEmitter->emitIns_Mov(INS_movzx, EA_2BYTE, REG_EAX, REG_ECX, false); | ||
|
|
||
| theEmitter->emitIns_R_R(INS_popcnt, EA_4BYTE, REG_EAX, REG_ECX); | ||
| theEmitter->emitIns_R_R(INS_lzcnt, EA_4BYTE, REG_EAX, REG_ECX); | ||
| theEmitter->emitIns_R_R(INS_tzcnt, EA_4BYTE, REG_EAX, REG_ECX); | ||
|
|
||
| theEmitter->emitIns_R_I(INS_add, EA_4BYTE, REG_ECX, 0x05); | ||
| theEmitter->emitIns_R_I(INS_add, EA_2BYTE, REG_ECX, 0x05); | ||
| theEmitter->emitIns_R_I(INS_or, EA_4BYTE, REG_EAX, 0x05); | ||
| theEmitter->emitIns_R_I(INS_adc, EA_4BYTE, REG_EAX, 0x05); | ||
| theEmitter->emitIns_R_I(INS_sbb, EA_4BYTE, REG_EAX, 0x05); | ||
| theEmitter->emitIns_R_I(INS_and, EA_4BYTE, REG_EAX, 0x05); | ||
| theEmitter->emitIns_R_I(INS_sub, EA_4BYTE, REG_EAX, 0x05); | ||
| theEmitter->emitIns_R_I(INS_xor, EA_4BYTE, REG_EAX, 0x05); | ||
| theEmitter->emitIns_R_I(INS_cmp, EA_4BYTE, REG_EAX, 0x05); | ||
| theEmitter->emitIns_R_I(INS_test, EA_4BYTE, REG_EAX, 0x05); | ||
|
|
||
| theEmitter->emitIns_R_I(INS_mov, EA_4BYTE, REG_EAX, 0xE0); | ||
|
|
||
| // JIT tend to compress imm64 to imm32 if higher half is all-zero, make sure this test checks the path for imm64. | ||
| theEmitter->emitIns_R_I(INS_mov, EA_8BYTE, REG_RAX, 0xFFFF000000000000); | ||
|
|
||
| // shf reg, cl | ||
| theEmitter->emitIns_R(INS_rol, EA_4BYTE, REG_EAX); | ||
| theEmitter->emitIns_R(INS_ror, EA_4BYTE, REG_EAX); | ||
| theEmitter->emitIns_R(INS_rcl, EA_4BYTE, REG_EAX); | ||
| theEmitter->emitIns_R(INS_rcr, EA_4BYTE, REG_EAX); | ||
| theEmitter->emitIns_R(INS_shl, EA_4BYTE, REG_EAX); | ||
| theEmitter->emitIns_R(INS_shr, EA_4BYTE, REG_EAX); | ||
| theEmitter->emitIns_R(INS_sar, EA_4BYTE, REG_EAX); | ||
|
|
||
| // shf reg, 1 | ||
| theEmitter->emitIns_R(INS_rol_1, EA_4BYTE, REG_EAX); | ||
| theEmitter->emitIns_R(INS_ror_1, EA_4BYTE, REG_EAX); | ||
| theEmitter->emitIns_R(INS_rcl_1, EA_4BYTE, REG_EAX); | ||
| theEmitter->emitIns_R(INS_rcr_1, EA_4BYTE, REG_EAX); | ||
| theEmitter->emitIns_R(INS_shl_1, EA_4BYTE, REG_EAX); | ||
| theEmitter->emitIns_R(INS_shr_1, EA_4BYTE, REG_EAX); | ||
| theEmitter->emitIns_R(INS_sar_1, EA_4BYTE, REG_EAX); | ||
|
|
||
| // shf reg, imm8 | ||
| theEmitter->emitIns_R_I(INS_shl_N, EA_4BYTE, REG_ECX, 0x05); | ||
| theEmitter->emitIns_R_I(INS_shr_N, EA_4BYTE, REG_ECX, 0x05); | ||
| theEmitter->emitIns_R_I(INS_sar_N, EA_4BYTE, REG_ECX, 0x05); | ||
| theEmitter->emitIns_R_I(INS_rol_N, EA_4BYTE, REG_ECX, 0x05); | ||
| theEmitter->emitIns_R_I(INS_ror_N, EA_4BYTE, REG_ECX, 0x05); | ||
| // TODO-xarch-apx: not enable these 2 for now. | ||
| // theEmitter->emitIns_R_I(INS_rcl_N, EA_4BYTE, REG_ECX, 0x05); | ||
| // theEmitter->emitIns_R_I(INS_rcr_N, EA_4BYTE, REG_ECX, 0x05); | ||
|
Comment on lines
+9137
to
+9139
There was a problem hiding this comment. What's the reason for these ones being skipped? Can we open tracking issues and list the issue number as part of the comment? There was a problem hiding this comment. https://github.com/dotnet/runtime/blob/main/src/coreclr/jit/emitxarch.cpp#L18695 It seems that the latency/tp information is missing for There was a problem hiding this comment. Its not required in this PR, but it would be good to ensure its all handled or tracked long term. I imagine this is representative of a potentially missing optimization. There was a problem hiding this comment. Thanks, I can submit an issue accordingly. |
||
|
|
||
| theEmitter->emitIns_R(INS_neg, EA_2BYTE, REG_EAX); | ||
| theEmitter->emitIns_R(INS_not, EA_2BYTE, REG_EAX); | ||
|
|
||
| theEmitter->emitIns_R_AR(INS_lea, EA_4BYTE, REG_ECX, REG_EAX, 4); | ||
|
|
||
| theEmitter->emitIns_R_AR(INS_mov, EA_1BYTE, REG_ECX, REG_EAX, 4); | ||
| theEmitter->emitIns_R_AR(INS_mov, EA_2BYTE, REG_ECX, REG_EAX, 4); | ||
| theEmitter->emitIns_R_AR(INS_mov, EA_4BYTE, REG_ECX, REG_EAX, 4); | ||
| theEmitter->emitIns_R_AR(INS_mov, EA_8BYTE, REG_ECX, REG_EAX, 4); | ||
|
|
||
| theEmitter->emitIns_R_AR(INS_add, EA_1BYTE, REG_EAX, REG_ECX, 4); | ||
| theEmitter->emitIns_R_AR(INS_add, EA_2BYTE, REG_EAX, REG_ECX, 4); | ||
| theEmitter->emitIns_R_AR(INS_add, EA_4BYTE, REG_EAX, REG_ECX, 4); | ||
| theEmitter->emitIns_R_AR(INS_add, EA_8BYTE, REG_EAX, REG_ECX, 4); | ||
| theEmitter->emitIns_R_AR(INS_or, EA_4BYTE, REG_EAX, REG_ECX, 4); | ||
| theEmitter->emitIns_R_AR(INS_adc, EA_4BYTE, REG_EAX, REG_ECX, 4); | ||
| theEmitter->emitIns_R_AR(INS_sbb, EA_4BYTE, REG_EAX, REG_ECX, 4); | ||
| theEmitter->emitIns_R_AR(INS_and, EA_4BYTE, REG_EAX, REG_ECX, 4); | ||
| theEmitter->emitIns_R_AR(INS_sub, EA_4BYTE, REG_EAX, REG_ECX, 4); | ||
| theEmitter->emitIns_R_AR(INS_xor, EA_4BYTE, REG_EAX, REG_ECX, 4); | ||
| theEmitter->emitIns_R_AR(INS_cmp, EA_4BYTE, REG_EAX, REG_ECX, 4); | ||
| theEmitter->emitIns_R_AR(INS_test, EA_4BYTE, REG_EAX, REG_ECX, 4); | ||
| theEmitter->emitIns_R_AR(INS_bsf, EA_4BYTE, REG_EAX, REG_ECX, 4); | ||
| theEmitter->emitIns_R_AR(INS_bsr, EA_4BYTE, REG_EAX, REG_ECX, 4); | ||
| theEmitter->emitIns_R_AR(INS_popcnt, EA_4BYTE, REG_EAX, REG_ECX, 4); | ||
| theEmitter->emitIns_R_AR(INS_lzcnt, EA_4BYTE, REG_EAX, REG_ECX, 4); | ||
| theEmitter->emitIns_R_AR(INS_tzcnt, EA_4BYTE, REG_EAX, REG_ECX, 4); | ||
|
|
||
| theEmitter->emitIns_AR_R(INS_add, EA_1BYTE, REG_EAX, REG_ECX, 4); | ||
| theEmitter->emitIns_AR_R(INS_add, EA_2BYTE, REG_EAX, REG_ECX, 4); | ||
| theEmitter->emitIns_AR_R(INS_add, EA_4BYTE, REG_EAX, REG_ECX, 4); | ||
| theEmitter->emitIns_AR_R(INS_add, EA_8BYTE, REG_EAX, REG_ECX, 4); | ||
| theEmitter->emitIns_AR_R(INS_or, EA_4BYTE, REG_EAX, REG_ECX, 4); | ||
| theEmitter->emitIns_AR_R(INS_adc, EA_4BYTE, REG_EAX, REG_ECX, 4); | ||
| theEmitter->emitIns_AR_R(INS_sbb, EA_4BYTE, REG_EAX, REG_ECX, 4); | ||
| theEmitter->emitIns_AR_R(INS_and, EA_4BYTE, REG_EAX, REG_ECX, 4); | ||
| theEmitter->emitIns_AR_R(INS_sub, EA_4BYTE, REG_EAX, REG_ECX, 4); | ||
| theEmitter->emitIns_AR_R(INS_xor, EA_4BYTE, REG_EAX, REG_ECX, 4); | ||
| theEmitter->emitIns_AR_R(INS_cmp, EA_4BYTE, REG_EAX, REG_ECX, 4); | ||
| theEmitter->emitIns_AR_R(INS_test, EA_4BYTE, REG_EAX, REG_ECX, 4); | ||
|
|
||
| theEmitter->emitIns_R_AR(INS_movsx, EA_2BYTE, REG_ECX, REG_EAX, 4); | ||
| theEmitter->emitIns_R_AR(INS_movzx, EA_2BYTE, REG_EAX, REG_ECX, 4); | ||
| theEmitter->emitIns_R_AR(INS_cmovo, EA_4BYTE, REG_EAX, REG_ECX, 4); | ||
|
|
||
| theEmitter->emitIns_AR_R(INS_xadd, EA_4BYTE, REG_EAX, REG_EDX, 2); | ||
|
|
||
| theEmitter->emitIns_R_R_I(INS_shld, EA_4BYTE, REG_EAX, REG_ECX, 5); | ||
| theEmitter->emitIns_R_R_I(INS_shrd, EA_2BYTE, REG_EAX, REG_ECX, 5); | ||
| // TODO-XArch-apx: S_R_I path only accepts SEE or VEX instructions, | ||
| // so I assuem shld/shrd will not be taking the first argument from stack. | ||
| // theEmitter->emitIns_S_R_I(INS_shld, EA_2BYTE, 1, 2, REG_EAX, 5); | ||
| // theEmitter->emitIns_S_R_I(INS_shrd, EA_2BYTE, 1, 2, REG_EAX, 5); | ||
|
|
||
| theEmitter->emitIns_AR_R(INS_cmpxchg, EA_2BYTE, REG_EAX, REG_EDX, 2); | ||
|
|
||
| theEmitter->emitIns_R(INS_seto, EA_1BYTE, REG_EDX); | ||
|
|
||
| theEmitter->emitIns_R(INS_bswap, EA_8BYTE, REG_EDX); | ||
|
|
||
| // INS_bt only has reg-to-reg form. | ||
| theEmitter->emitIns_R_R(INS_bt, EA_2BYTE, REG_EAX, REG_EDX); | ||
|
|
||
| theEmitter->emitIns_R(INS_idiv, EA_8BYTE, REG_EDX); | ||
|
|
||
| theEmitter->emitIns_R_R(INS_xchg, EA_8BYTE, REG_EAX, REG_EDX); | ||
|
|
||
| theEmitter->emitIns_R(INS_div, EA_8BYTE, REG_EDX); | ||
| theEmitter->emitIns_R(INS_mulEAX, EA_8BYTE, REG_EDX); | ||
|
|
||
| // Note: | ||
| // All the tests below rely on the runtime status of the stack this unit tests attaching to, | ||
| // it might fail due to stack value unavailable/mismatch, since these tests are mainly for | ||
| // encoding correctness check, this kind of failures may be considered as not harmful. | ||
|
|
||
| GenTree* stkNum = theEmitter->emitComp->stackState.esStack[0].val; | ||
|
There was a problem hiding this comment. I don't see the relationship to the Couldn't you: to create |
||
| stkNum->SetRegNum(REG_EDX); | ||
| stkNum->SetUnusedValue(); | ||
| GenTreeIndir load = indirForm(TYP_INT, stkNum); | ||
|
|
||
| theEmitter->emitIns_R_A(INS_add, EA_4BYTE, REG_EAX, &load); | ||
| theEmitter->emitIns_R_A(INS_add, EA_4BYTE, REG_EAX, &load); | ||
| theEmitter->emitIns_R_A(INS_add, EA_4BYTE, REG_EAX, &load); | ||
| theEmitter->emitIns_R_A(INS_add, EA_8BYTE, REG_EAX, &load); | ||
| theEmitter->emitIns_R_A(INS_or, EA_4BYTE, REG_EAX, &load); | ||
| theEmitter->emitIns_R_A(INS_adc, EA_4BYTE, REG_EAX, &load); | ||
| theEmitter->emitIns_R_A(INS_sbb, EA_4BYTE, REG_EAX, &load); | ||
| theEmitter->emitIns_R_A(INS_and, EA_4BYTE, REG_EAX, &load); | ||
| theEmitter->emitIns_R_A(INS_sub, EA_4BYTE, REG_EAX, &load); | ||
| theEmitter->emitIns_R_A(INS_xor, EA_4BYTE, REG_EAX, &load); | ||
| theEmitter->emitIns_R_A(INS_cmp, EA_4BYTE, REG_EAX, &load); | ||
| theEmitter->emitIns_R_A(INS_test, EA_4BYTE, REG_EAX, &load); | ||
| theEmitter->emitIns_R_A(INS_bsf, EA_4BYTE, REG_EAX, &load); | ||
| theEmitter->emitIns_R_A(INS_bsr, EA_4BYTE, REG_EAX, &load); | ||
|
|
||
| theEmitter->emitIns_R_S(INS_add, EA_1BYTE, REG_EAX, 0, 0); | ||
| theEmitter->emitIns_R_S(INS_add, EA_2BYTE, REG_EAX, 0, 0); | ||
| theEmitter->emitIns_R_S(INS_add, EA_4BYTE, REG_EAX, 0, 0); | ||
| theEmitter->emitIns_R_S(INS_add, EA_8BYTE, REG_EAX, 0, 0); | ||
| theEmitter->emitIns_R_S(INS_or, EA_4BYTE, REG_EAX, 0, 0); | ||
| theEmitter->emitIns_R_S(INS_adc, EA_4BYTE, REG_EAX, 0, 0); | ||
| theEmitter->emitIns_R_S(INS_sbb, EA_4BYTE, REG_EAX, 0, 0); | ||
| theEmitter->emitIns_R_S(INS_and, EA_4BYTE, REG_EAX, 0, 0); | ||
| theEmitter->emitIns_R_S(INS_sub, EA_4BYTE, REG_EAX, 0, 0); | ||
| theEmitter->emitIns_R_S(INS_xor, EA_4BYTE, REG_EAX, 0, 0); | ||
| theEmitter->emitIns_R_S(INS_cmp, EA_4BYTE, REG_EAX, 0, 0); | ||
| theEmitter->emitIns_R_S(INS_test, EA_4BYTE, REG_EAX, 0, 0); | ||
| theEmitter->emitIns_S_R(INS_xadd, EA_2BYTE, REG_EAX, 0, 0); | ||
|
|
||
| theEmitter->emitIns_S_I(INS_shl_N, EA_4BYTE, 0, 0, 4); | ||
| theEmitter->emitIns_S(INS_shl_1, EA_4BYTE, 0, 4); | ||
|
|
||
| theEmitter->emitIns_R_S(INS_movsx, EA_2BYTE, REG_ECX, 0, 0); | ||
| theEmitter->emitIns_R_S(INS_movzx, EA_2BYTE, REG_EAX, 0, 0); | ||
| theEmitter->emitIns_R_S(INS_cmovo, EA_4BYTE, REG_EAX, 0, 0); | ||
|
|
||
| theEmitter->emitIns_R(INS_pop, EA_PTRSIZE, REG_EAX); | ||
| theEmitter->emitIns_R(INS_push, EA_PTRSIZE, REG_EAX); | ||
| theEmitter->emitIns_R(INS_pop_hide, EA_PTRSIZE, REG_EAX); | ||
| theEmitter->emitIns_R(INS_push_hide, EA_PTRSIZE, REG_EAX); | ||
|
|
||
| theEmitter->emitIns_S(INS_pop, EA_PTRSIZE, 0, 0); | ||
| theEmitter->emitIns_I(INS_push, EA_PTRSIZE, 50); | ||
|
|
||
| theEmitter->emitIns_R(INS_inc, EA_4BYTE, REG_EAX); | ||
| theEmitter->emitIns_AR(INS_inc, EA_2BYTE, REG_EAX, 2); | ||
| theEmitter->emitIns_S(INS_inc, EA_2BYTE, 0, 0); | ||
| theEmitter->emitIns_R(INS_dec, EA_4BYTE, REG_EAX); | ||
| theEmitter->emitIns_AR(INS_dec, EA_2BYTE, REG_EAX, 2); | ||
| theEmitter->emitIns_S(INS_dec, EA_2BYTE, 0, 0); | ||
|
|
||
| theEmitter->emitIns_S(INS_neg, EA_2BYTE, 0, 0); | ||
| theEmitter->emitIns_S(INS_not, EA_2BYTE, 0, 0); | ||
| } | ||
|
|
||
| #endif // defined(DEBUG) && defined(TARGET_AMD64) | ||
|
|
||
| #ifdef PROFILING_SUPPORTED | ||
|
|
||
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
|
|
@@ -9945,6 +9945,17 @@ class Compiler | |
| return (compOpportunisticallyDependsOn(InstructionSet_EVEX)); | ||
| } | ||
|
|
||
| //------------------------------------------------------------------------ | ||
| // canUseRex2Encoding - Answer the question: Is Rex2 encoding supported on this target. | ||
| // | ||
| // Returns: | ||
| // `true` if Rex2 encoding is supported, `false` if not. | ||
| // | ||
| bool canUseApxEncoding() const | ||
| { | ||
| return compOpportunisticallyDependsOn(InstructionSet_APX); | ||
| } | ||
|
|
||
| private: | ||
| //------------------------------------------------------------------------ | ||
| // DoJitStressEvexEncoding- Answer the question: Do we force EVEX encoding. | ||
|
|
@@ -9980,6 +9991,27 @@ class Compiler | |
|
|
||
| return false; | ||
| } | ||
|
|
||
| //------------------------------------------------------------------------ | ||
| // DoJitStressRex2Encoding- Answer the question: Do we force REX2 encoding. | ||
| // | ||
| // Returns: | ||
| // `true` if user requests REX2 encoding. | ||
| // | ||
| bool DoJitStressRex2Encoding() const | ||
| { | ||
| #ifdef DEBUG | ||
| if (JitConfig.JitStressRex2Encoding() && compOpportunisticallyDependsOn(InstructionSet_APX)) | ||
| { | ||
| // we should make sure EVEX is also stressed when REX2 is stressed, as we will need to guarantee EGPR | ||
| // functionality is properly turned on for every instructions when REX2 is stress. | ||
| assert(JitConfig.JitStressEvexEncoding()); | ||
|
There was a problem hiding this comment. This means that if you set If it's required to also stress EVEX, I suggest creating a small helper function: and replace all occurrences of calls to There was a problem hiding this comment. We had more discussion on this here: #106557 (comment) I will replace the EVEX encoding check with the suggested helper, thanks for pointing out. |
||
| return true; | ||
| } | ||
| #endif // DEBUG | ||
|
|
||
| return false; | ||
| } | ||
| #endif // TARGET_XARCH | ||
|
|
||
| /* | ||
|
|
||
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Oops, something went wrong.
Oops, something went wrong.
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Not related to this PR really, but it'd be nice if we had similar tests for other ISAs/encodings (VEX, EVEX, etc). Sse2 itself is, afair, really just SimdLegacyEncoding.