core/msi: Switch to LiteXModule.

litepcie/core/msi.py

@@ -1,19 +1,21 @@
 #
 # This file is part of LitePCIe.
 #
-# Copyright (c) 2015-2022 Florent Kermarrec <florent@enjoy-digital.fr>
+# Copyright (c) 2015-2023 Florent Kermarrec <florent@enjoy-digital.fr>
 # SPDX-License-Identifier: BSD-2-Clause
 
 from migen import *
 
+from litex.gen import *
+
 from litex.soc.interconnect.csr import *
 from litex.soc.interconnect.csr_bus import SRAM
 
 from litepcie.common import *
 
 # LitePCIeMSI --------------------------------------------------------------------------------------
 
-class LitePCIeMSI(Module, AutoCSR):
+class LitePCIeMSI(LiteXModule):
     def __init__(self, width=32):
         self.irqs   = Signal(width)
         self.source = stream.Endpoint(msi_layout())
@@ -49,7 +51,7 @@ def __init__(self, width=32):
 
 # LitePCIeMSIMultiVector ---------------------------------------------------------------------------
 
-class LitePCIeMSIMultiVector(Module, AutoCSR):
+class LitePCIeMSIMultiVector(LiteXModule):
   def __init__(self, width=32):
         self.irqs   = Signal(width)
         self.source = stream.Endpoint(msi_layout())
@@ -81,7 +83,7 @@ def __init__(self, width=32):
 
 # LitePCIeMSIX -------------------------------------------------------------------------------------
 
-class LitePCIeMSIX(Module, AutoCSR):
+class LitePCIeMSIX(LiteXModule):
     def __init__(self, endpoint, width=32):
         assert width <= 64
         self.irqs           = Signal(width)
@@ -122,11 +124,11 @@ def __init__(self, endpoint, width=32):
             ]
 
         # Send MSI-X as TLP-Write ------------------------------------------------------------------
-        port     = endpoint.crossbar.get_master_port()
+        port       = endpoint.crossbar.get_master_port()
         table_port = self.table.get_port(has_re=True)
         self.specials += table_port
 
-        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
+        self.fsm = fsm = FSM(reset_state="IDLE")
         fsm.act("IDLE",
             table_port.adr.eq(msix_num),
             table_port.re.eq(1),