Merge pull request #126 from smunaut/usp-phy-straddle

phy/usppciephy,uspciephy: Disable straddle mode for request completion
enjoy-digital · Feb 1, 2024 · 600bd13 · 600bd13
2 parents 2bda716 + b7f8bfd
commit 600bd13
Show file tree

Hide file tree

Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/litepcie/phy/uspciephy.py b/litepcie/phy/uspciephy.py
@@ -382,7 +382,7 @@ def add_sources(self, platform, phy_path=None, phy_filename=None):
                 "PL_LINK_CAP_MAX_LINK_WIDTH"   : f"X{self.nlanes}",
                 "PL_LINK_CAP_MAX_LINK_SPEED"   : "8.0_GT/s", # CHECKME.
                 "axisten_if_width"             : f"{self.pcie_data_width}_bit",
-                "AXISTEN_IF_RC_STRADDLE"       : True,
+                "AXISTEN_IF_RC_STRADDLE"       : False,
                 "PF0_DEVICE_ID"                : 8030 + self.nlanes,
                 "axisten_freq"                 : 250, # CHECKME.
                 "axisten_if_enable_client_tag" : True,

diff --git a/litepcie/phy/usppciephy.py b/litepcie/phy/usppciephy.py
@@ -383,7 +383,7 @@ def add_sources(self, platform, phy_path=None, phy_filename=None, hbm=False):
                 "PL_LINK_CAP_MAX_LINK_WIDTH"   : f"X{self.nlanes}",
                 "PL_LINK_CAP_MAX_LINK_SPEED"   : "8.0_GT/s", # CHECKME.
                 "axisten_if_width"             : f"{self.pcie_data_width}_bit",
-                "AXISTEN_IF_RC_STRADDLE"       : True,
+                "AXISTEN_IF_RC_STRADDLE"       : False,
                 "PF0_DEVICE_ID"                : 9030 + self.nlanes,
                 "axisten_freq"                 : 250, # CHECKME.
                 "axisten_if_enable_client_tag" : True,