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Merge pull request #130 from enjoy-digital/litepcie_gen_dma_dict
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Add DMA Channels dict support to litepcie_gen.
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@enjoy-digital
enjoy-digital authored Feb 22, 2024
2 parents 9bccbfb + 811f27d commit 636c3e4
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Showing 4 changed files with 154 additions and 88 deletions.
42 changes: 21 additions & 21 deletions examples/ac701.yml
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@@ -1,45 +1,45 @@
#
# This file is part of LitePCIe.
#
# Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
# Copyright (c) 2019-2024 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause

{
# PHY ----------------------------------------------------------------------
"phy": "S7PCIEPHY", # Type of PCIe PHY
"phy_device": "xc7a", # Type of Device
"phy_lanes": 4, # Number of lanes
"phy_pcie_data_width": 128, # PCIe data_width
"phy_data_width": 128, # Bus data_width
"phy_bar0_size": 0x40000, # BAR0 size
"phy" : "S7PCIEPHY", # Type of PCIe PHY
"phy_device" : "xc7a", # Type of Device
"phy_lanes" : 4, # Number of lanes
"phy_pcie_data_width" : 128, # PCIe data_width
"phy_data_width" : 128, # Bus data_width
"phy_bar0_size" : 0x40000, # BAR0 size

# Clocking -----------------------------------------------------------------
"clk_freq": 125e6, # User Clk Freq (AXI MMAP/DMA)
"clk_external": False, # Use external User provided Clk
"clk_freq" : 125e6, # User Clk Freq (AXI MMAP/DMA)
"clk_external" : False, # Use external User provided Clk

# Endpoint -----------------------------------------------------------------
"ep_max_pending_requests" : 8,
"ep_address_width" : 32,

# Control ------------------------------------------------------------------
"ctrl": False,
"ctrl" : False,

# MMAP Master --------------------------------------------------------------
"mmap": True,
"mmap_base": 0x00020000,
"mmap_size": 0x00020000,
"mmap" : True,
"mmap_base" : 0x00020000,
"mmap_size" : 0x00020000,

# MMAP Slave ---------------------------------------------------------------
"mmap_slave": True,
"mmap_slave_axi_full": True,
"mmap_slave" : True,
"mmap_slave_axi_full" : True,

# DMA channels -------------------------------------------------------------
"dma_channels" : 4, # Number of DMA channels
"dma_buffering" : 8192, # Buffering for each channel (in bytes)
"dma_loopback" : True, # Enable DMA loopback capability
"dma_synchronizer" : True, # Enable DMA synchronizer capability
"dma_monitor" : True, # Enable DMA monitoring capability
"dma_channels" : 4, # Number of DMA channels
"dma_buffering" : 8192, # Buffering for each channel (in bytes)
"dma_loopback" : True, # Enable DMA loopback capability
"dma_synchronizer" : True, # Enable DMA synchronizer capability
"dma_monitor" : True, # Enable DMA monitoring capability

# MSI IRQs -----------------------------------------------------------------
"msi_irqs": 16, # Number or MSI IRQs
"msi_irqs" : 16, # Number or MSI IRQs
}
42 changes: 21 additions & 21 deletions examples/acorn.yml
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Original file line number Diff line number Diff line change
@@ -1,45 +1,45 @@
#
# This file is part of LitePCIe.
#
# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
# Copyright (c) 2019-2024 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause

{
# PHY ----------------------------------------------------------------------
"phy": "S7PCIEPHY", # Type of PCIe PHY
"phy_device": "xc7a", # Type of Device
"phy_lanes": 4, # Number of lanes
"phy_pcie_data_width": 128, # PCIe data_width
"phy_data_width": 128, # Bus data_width
"phy_bar0_size": 0x40000, # BAR0 size
"phy" : "S7PCIEPHY", # Type of PCIe PHY
"phy_device" : "xc7a", # Type of Device
"phy_lanes" : 4, # Number of lanes
"phy_pcie_data_width" : 128, # PCIe data_width
"phy_data_width" : 128, # Bus data_width
"phy_bar0_size" : 0x40000, # BAR0 size

# Clocking -----------------------------------------------------------------
"clk_freq": 125e6, # User Clk Freq (AXI MMAP/DMA)
"clk_external": True, # Use external User provided Clk
"clk_freq" : 125e6, # User Clk Freq (AXI MMAP/DMA)
"clk_external" : True, # Use external User provided Clk

# Endpoint -----------------------------------------------------------------
"ep_max_pending_requests" : 8,
"ep_address_width" : 32,

# Control ------------------------------------------------------------------
"ctrl": False,
"ctrl" : False,

# MMAP Master --------------------------------------------------------------
"mmap": True,
"mmap_base": 0x00020000,
"mmap_size": 0x00020000,
"mmap" : True,
"mmap_base" : 0x00020000,
"mmap_size" : 0x00020000,

# MMAP Slave ---------------------------------------------------------------
"mmap_slave": True,
"mmap_slave_axi_full": True,
"mmap_slave" : True,
"mmap_slave_axi_full" : True,

# DMA channels -------------------------------------------------------------
"dma_channels" : 4, # Number of DMA channels
"dma_buffering" : 1024, # Buffering for each channel (in bytes)
"dma_loopback" : True, # Enable DMA loopback capability
"dma_synchronizer" : False, # Enable DMA synchronizer capability
"dma_monitor" : False, # Enable DMA monitoring capability
"dma_channels" : 4, # Number of DMA channels
"dma_buffering" : 1024, # Buffering for each channel (in bytes)
"dma_loopback" : True, # Enable DMA loopback capability
"dma_synchronizer" : False, # Enable DMA synchronizer capability
"dma_monitor" : False, # Enable DMA monitoring capability

# MSI IRQs -----------------------------------------------------------------
"msi_irqs": 16, # Number or MSI IRQs
"msi_irqs" : 16, # Number or MSI IRQs
}
55 changes: 33 additions & 22 deletions examples/kcu105.yml
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@@ -1,46 +1,57 @@
#
# This file is part of LitePCIe.
#
# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
# Copyright (c) 2019-2024 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause

{
# PHY ----------------------------------------------------------------------
"phy": "USPCIEPHY", # Type of PCIe PHY
"phy_device": "xcku", # Type of Device
"phy_lanes": 4, # Number of lanes
"phy_pcie_data_width": 128, # PCIe data_width
"phy_data_width": 128, # Bus data_width
"phy_bar0_size": 0x40000, # BAR0 size
"phy" : "USPCIEPHY", # Type of PCIe PHY
"phy_device" : "xcku", # Type of Device
"phy_lanes" : 4, # Number of lanes
"phy_pcie_data_width" : 128, # PCIe data_width
"phy_data_width" : 128, # Bus data_width
"phy_bar0_size" : 0x40000, # BAR0 size

# Clocking -----------------------------------------------------------------
"clk_freq": 125e6, # User Clk Freq (AXI MMAP/DMA)
"clk_external": False, # Use external User provided Clk
"clk_freq" : 125e6, # User Clk Freq (AXI MMAP/DMA)
"clk_external" : False, # Use external User provided Clk

# Endpoint -----------------------------------------------------------------
"ep_max_pending_requests" : 8,
"ep_address_width" : 64,

# Control ------------------------------------------------------------------
"ctrl": False,
"ctrl" : False,

# MMAP Master --------------------------------------------------------------
"mmap": True,
"mmap_base": 0x00020000,
"mmap_size": 0x00020000,
"mmap" : True,
"mmap_base" : 0x00020000,
"mmap_size" : 0x00020000,

# MMAP Slave ---------------------------------------------------------------
"mmap_slave": True,
"mmap_slave" : True,

# DMA channels -------------------------------------------------------------
"dma_channels" : 4, # Number of DMA channels
"dma_writer" : True, # Enable DMA Writer.
"dma_reader" : True, # Disable DMA Reader.
"dma_buffering" : 8192, # Buffering for each channel (in bytes)
"dma_loopback" : False, # Disable DMA loopback capability
"dma_synchronizer" : False, # Disable DMA synchronizer capability
"dma_monitor" : True, # Enable DMA monitoring capability
"dma_channels": {
"dma0": {
"dma_writer" : True, # Enable DMA Writer.
"dma_reader" : True, # Disable DMA Reader.
"dma_buffering" : 8192, # Buffering for each channel (in bytes)
"dma_loopback" : False, # Disable DMA loopback capability
"dma_synchronizer" : False, # Disable DMA synchronizer capability
"dma_monitor" : True, # Enable DMA monitoring capability
},
"dma1": {
"dma_writer" : True, # Enable DMA Writer.
"dma_reader" : True, # Disable DMA Reader.
"dma_buffering" : 8192, # Buffering for each channel (in bytes)
"dma_loopback" : False, # Disable DMA loopback capability
"dma_synchronizer" : False, # Disable DMA synchronizer capability
"dma_monitor" : True, # Enable DMA monitoring capability
},
},

# MSI IRQs -----------------------------------------------------------------
"msi_irqs": 16, # Number or MSI IRQs
"msi_irqs" : 16, # Number or MSI IRQs
}
103 changes: 79 additions & 24 deletions litepcie/gen.py
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Original file line number Diff line number Diff line change
Expand Up @@ -266,53 +266,108 @@ def __init__(self, platform, core_config):
self.comb += wb.connect(pcie_wishbone_slave.wishbone)

# PCIe DMA ---------------------------------------------------------------------------------
with_writer = core_config.get("dma_writer", True)
with_reader = core_config.get("dma_reader", True)

pcie_dmas = []
self.add_constant("DMA_CHANNELS", core_config["dma_channels"])

# Parameters.
# -----------

dmas_params = []

class DMAParams:
def __init__(self, writer, reader, buffering, loopback, synchronizer, monitor):
self.writer = writer
self.reader = reader
self.buffering = buffering
self.loopback = loopback
self.synchronizer = synchronizer
self.monitor = monitor

# DMA Channels configured separately.
if isinstance(core_config.get("dma_channels"), dict):
print(core_config.get("dma_channels"))
for name, params in core_config["dma_channels"].items():
dma_params = DMAParams(
writer = params.get("dma_writer", True),
reader = params.get("dma_reader", True),
buffering = params.get("dma_buffering", 1024),
loopback = params.get("dma_loopback", True),
synchronizer = params.get("dma_synchronizer", False),
monitor = params.get("dma_monitor", False),
)
dmas_params.append(dma_params)

# DMA Channels configured identically.
else:
print("here1")
for n in range(core_config["dma_channels"]):
dma_params = DMAParams(
writer = core_config.get("dma_writer", True),
reader = core_config.get("dma_reader", True),
buffering = core_config.get("dma_buffering", 1024),
loopback = core_config.get("dma_loopback", True),
synchronizer = core_config.get("dma_synchronizer", False),
monitor = core_config.get("dma_monitor", False),
)
dmas_params.append(dma_params)

self.add_constant("DMA_CHANNELS", len(dmas_params))
self.add_constant("DMA_ADDR_WIDTH", ep_address_width)
for i in range(core_config["dma_channels"]):

# PCIe DMAs.
# ----------
for i, dma_params in enumerate(dmas_params):
# DMA.
# ----
pcie_dma = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
address_width = ep_address_width,
with_writer = with_writer,
with_reader = with_reader,
with_buffering = core_config["dma_buffering"] != 0,
buffering_depth = core_config["dma_buffering"],
with_loopback = core_config["dma_loopback"],
with_synchronizer = core_config["dma_synchronizer"],
with_monitor = core_config["dma_monitor"],
with_writer = dma_params.writer,
with_reader = dma_params.reader,
with_buffering = dma_params.buffering != 0,
buffering_depth = dma_params.buffering,
with_loopback = dma_params.loopback,
with_synchronizer = dma_params.synchronizer,
with_monitor = dma_params.monitor,
)
# DMA Endpoint Buffers (For timings).
# -------------------------------
pcie_dma = stream.BufferizeEndpoints({"sink" : stream.DIR_SINK})(pcie_dma)
pcie_dma = stream.BufferizeEndpoints({"source" : stream.DIR_SOURCE})(pcie_dma)
setattr(self.submodules, "pcie_dma" + str(i), pcie_dma)
self.add_module(f"pcie_dma{i}", pcie_dma)

# DMA IOs.
# --------
platform.add_extension(get_axi_dma_ios(i,
data_width = core_config["phy_data_width"],
with_writer = with_writer,
with_reader = with_reader,
with_writer = dma_params.writer,
with_reader = dma_params.reader,
))
dma_status_ios = platform.request(f"dma{i}_status")

if hasattr(pcie_dma, "writer"):
dma_writer_ios = platform.request("dma{}_writer_axi".format(i))
# DMA Writer <-> IOs Connection.
# ------------------------------
if dma_params.writer:
dma_writer_ios = platform.request(f"dma{i}_writer_axi")
self.comb += [
# Status IOs
# Status IOs.
dma_status_ios.writer_enable.eq(pcie_dma.writer.enable),

# Writer IOs
# Writer IOs.
pcie_dma.sink.valid.eq(dma_writer_ios.tvalid & pcie_dma.writer.enable),
dma_writer_ios.tready.eq(pcie_dma.sink.ready & pcie_dma.writer.enable),
pcie_dma.sink.last.eq(dma_writer_ios.tlast),
pcie_dma.sink.data.eq(dma_writer_ios.tdata),
pcie_dma.sink.first.eq(dma_writer_ios.tuser),
]
if hasattr(pcie_dma, "reader"):
dma_reader_ios = platform.request("dma{}_reader_axi".format(i))

# DMA Reader <-> IOs Connection.
# ------------------------------
if dma_params.reader:
dma_reader_ios = platform.request(f"dma{i}_reader_axi")
self.comb += [
# Status IOs
# Status IOs.
dma_status_ios.reader_enable.eq(pcie_dma.reader.enable),

# Reader IOs
# Reader IOs.
dma_reader_ios.tvalid.eq(pcie_dma.source.valid & pcie_dma.reader.enable),
pcie_dma.source.ready.eq(dma_reader_ios.tready | ~pcie_dma.reader.enable),
dma_reader_ios.tlast.eq(pcie_dma.source.last),
Expand All @@ -335,7 +390,7 @@ def __init__(self, platform, core_config):
self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
self.comb += self.pcie_msi.irqs[16:16+core_config["msi_irqs"]].eq(platform.request("msi_irqs"))
self.interrupts = {}
for i in range(core_config["dma_channels"]):
for i in range(len(dmas_params)):
pcie_dma = getattr(self, f"pcie_dma{i}")
if hasattr(pcie_dma, "writer"):
self.interrupts[f"pcie_dma{i}_writer"] = pcie_dma.writer.irq
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