phy/xilinx_us(p): Switch to pcie_data_width suffix and avoid Gen4 wor…

…karound.
enjoy-digital · May 6, 2024 · 662b78a · 662b78a
1 parent 0e9ba37
commit 662b78a
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Showing 2 changed files with 9 additions and 12 deletions.
diff --git a/litepcie/phy/uspciephy.py b/litepcie/phy/uspciephy.py
@@ -411,10 +411,10 @@ def add_sources(self, platform, phy_path=None, phy_filename=None):
 
         verilog_path = os.path.join(os.path.abspath(os.path.dirname(__file__)), "xilinx_us")
         platform.add_source(os.path.join(verilog_path, "axis_iff.v"))
-        platform.add_source(os.path.join(verilog_path, f"s_axis_rq_adapt_x{self.nlanes}.v"))
-        platform.add_source(os.path.join(verilog_path, f"m_axis_rc_adapt_x{self.nlanes}.v"))
-        platform.add_source(os.path.join(verilog_path, f"m_axis_cq_adapt_x{self.nlanes}.v"))
-        platform.add_source(os.path.join(verilog_path, f"s_axis_cc_adapt_x{self.nlanes}.v"))
+        platform.add_source(os.path.join(verilog_path, f"s_axis_rq_adapt_{self.pcie_data_width}b.v"))
+        platform.add_source(os.path.join(verilog_path, f"m_axis_rc_adapt_{self.pcie_data_width}b.v"))
+        platform.add_source(os.path.join(verilog_path, f"m_axis_cq_adapt_{self.pcie_data_width}b.v"))
+        platform.add_source(os.path.join(verilog_path, f"s_axis_cc_adapt_{self.pcie_data_width}b.v"))
         platform.add_source(os.path.join(verilog_path, "pcie_us_support.v"))
 
     # External Hard IP -----------------------------------------------------------------------------

diff --git a/litepcie/phy/usppciephy.py b/litepcie/phy/usppciephy.py
@@ -416,14 +416,11 @@ def add_sources(self, platform, phy_path=None, phy_filename=None):
 
         verilog_path = os.path.join(os.path.abspath(os.path.dirname(__file__)), "xilinx_usp")
         platform.add_source(os.path.join(verilog_path, "axis_iff.v"))
-
-        nvlanes = {"gen3": self.nlanes, "gen4": self.nlanes*2}[self.speed]
-
-        platform.add_source(os.path.join(verilog_path, f"s_axis_rq_adapt_x{nvlanes}.v"))
-        platform.add_source(os.path.join(verilog_path, f"m_axis_rc_adapt_x{nvlanes}.v"))
-        platform.add_source(os.path.join(verilog_path, f"m_axis_cq_adapt_x{nvlanes}.v"))
-        platform.add_source(os.path.join(verilog_path, f"s_axis_cc_adapt_x{nvlanes}.v"))
-
+
+        platform.add_source(os.path.join(verilog_path, f"s_axis_rq_adapt_{self.pcie_data_width}b.v"))
+        platform.add_source(os.path.join(verilog_path, f"m_axis_rc_adapt_{self.pcie_data_width}b.v"))
+        platform.add_source(os.path.join(verilog_path, f"m_axis_cq_adapt_{self.pcie_data_width}b.v"))
+        platform.add_source(os.path.join(verilog_path, f"s_axis_cc_adapt_{self.pcie_data_width}b.v"))
         platform.add_source(os.path.join(verilog_path, "pcie_usp_support.v"))
 
     # External Hard IP -----------------------------------------------------------------------------