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core/crossbar: Cosmetic cleanup.
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enjoy-digital committed Jul 8, 2024
1 parent 391cdd0 commit 7d776d6
Showing 1 changed file with 8 additions and 9 deletions.
17 changes: 8 additions & 9 deletions litepcie/core/crossbar.py
Original file line number Diff line number Diff line change
Expand Up @@ -84,13 +84,13 @@ def master_arbitrate_dispatch(self, masters, master, dispatch=True):
if m.channel is not None:
self.comb += m_dispatcher.sel[i].eq(master.source.channel == m.channel)
else:
# Connect to first master
# Connect to first master.
self.comb += master.source.connect(masters[0].source)

def do_finalize(self):
# Slave path -------------------------------------------------------------------------------
# Dispatch request to user sources (according to address decoder)
# Arbitrate completion from user sinks
# - Dispatch request to user sources (according to address decoder).
# - Arbitrate completion from user sinks.
if self.user_slaves != []:
self.slave_dispatch_arbitrate(self.user_slaves, self.slave)

Expand All @@ -113,16 +113,15 @@ def do_finalize(self):
# cmps<--- | PORTS |-----|Arb/Disp|-----------------+
# +-------+ +--------+
#
# The controller blocks RD requests when the max number of pending
# requests have been sent (max_pending_requests parameters).
# To avoid blocking write_only ports when RD requests are blocked,
# a separate arbitration stage is used.
# The controller blocks RD requests when the max number of pending requests have been sent
# (max_pending_requests parameters).
# To avoid blocking write_only ports when RD requests are blocked, a separate arbitration
# stage is used.

if self.user_masters != []:
masters = []

# Arbitrate / dispatch read_only / read_write ports ------------------------------------
# and insert controller
# Arbitrate / dispatch read_only / read_write ports and insert controller --------------
rd_rw_masters = self.filter_masters(False, True)
rd_rw_masters += self.filter_masters(False, False)
if rd_rw_masters != []:
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