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--
fe643e1 by Zenithal <i@zenithal.me>:

ASM: suggest block arg name for secret.generic
COPYBARA_INTEGRATE_REVIEW=#1224 from ZenithalHourlyRate:secret-generic-asm fe643e1
PiperOrigin-RevId: 711268690
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@ZenithalHourlyRate @copybara-github
ZenithalHourlyRate authored and copybara-github committed Jan 2, 2025
1 parent df47fd4 commit 5a47426
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Showing 3 changed files with 49 additions and 16 deletions.
35 changes: 34 additions & 1 deletion lib/Dialect/Secret/IR/SecretOps.td
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Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,7 @@
include "SecretDialect.td"
include "SecretTypes.td"
include "mlir/IR/BuiltinAttributeInterfaces.td"
include "mlir/IR/OpAsmInterface.td"
include "mlir/Interfaces/ControlFlowInterfaces.td"
include "mlir/Interfaces/InferTypeOpInterface.td"
include "mlir/Interfaces/SideEffectInterfaces.td"
Expand Down Expand Up @@ -110,7 +111,8 @@ def Secret_YieldOp : Secret_Op<"yield", [

def Secret_GenericOp : Secret_Op<"generic", [
SingleBlock,
SingleBlockImplicitTerminator<"YieldOp">
SingleBlockImplicitTerminator<"YieldOp">,
OpAsmOpInterface
]> {
let summary = "Lift a plaintext computation to operate on secrets.";
let description = [{
Expand Down Expand Up @@ -303,6 +305,37 @@ def Secret_GenericOp : Secret_Op<"generic", [
}
return attr;
}

//===------------------------------------------------------------------===//
// OpAsmOpInterface Methods
//===------------------------------------------------------------------===//

// void getAsmResultNames(::mlir::OpAsmSetValueNameFn setNameFn) {
// if (getNumResults() == 1) {
// setNameFn(getResult(0), "computed");
// return;
// }
// for (auto result : getResults()) {
// setNameFn(result, "computed" + std::to_string(result.getResultNumber()));
// }
// }

void getAsmBlockArgumentNames(::mlir::Region &region,
::mlir::OpAsmSetValueNameFn setNameFn) {
for (auto &block : region) {
for (auto arg : block.getArguments()) {
setNameFn(arg, "input" + std::to_string(arg.getArgNumber()));
}
}
}

// void getAsmBlockNames(::mlir::OpAsmSetBlockNameFn setNameFn) {
// for (auto &block : getRegion().getBlocks()) {
// setNameFn(&block, "body");
// }
// }

// static ::llvm::StringRef getDefaultDialect() { return "secret"; }
}];

let hasCanonicalizer = 1;
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2 changes: 1 addition & 1 deletion tests/Transforms/heir_simd_vectorizer/box_blur_64x64.mlir
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Expand Up @@ -17,7 +17,7 @@ module {
// CHECK-NEXT: %[[v4:.*]] = arith.addi %[[v3]], %[[arg1]]
// CHECK-NEXT: %[[v5:.*]] = tensor_ext.rotate %[[v4]], %[[c63]]
// CHECK-NEXT: %[[v6:.*]] = arith.addi %[[v5]], %[[v2]]
// CHECK-NEXT: %[[v7:.*]] = arith.addi %[[v6]], %arg1
// CHECK-NEXT: %[[v7:.*]] = arith.addi %[[v6]], %[[arg1]]
// CHECK-NEXT: %[[v8:.*]] = tensor_ext.rotate %[[v7]], %[[c63]]
// CHECK-NEXT: %[[v9:.*]] = tensor_ext.rotate %[[arg1]], %[[c127]]
// CHECK-NEXT: %[[v10:.*]] = arith.addi %[[v8]], %[[v9]]
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28 changes: 14 additions & 14 deletions tests/Transforms/yosys_optimizer/unroll_and_optimize.mlir
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Original file line number Diff line number Diff line change
Expand Up @@ -66,21 +66,21 @@ func.func @basic_example(%arg0: !in_ty) -> (!out_ty) {
// CHECK-NEXT: secret.generic
// CHECK-NEXT: ^bb{{.*}}(%[[arg2:.*]]: memref<8xi1>, %[[arg3:.*]]: memref<8xi1>):
// Note bit 7 is never loaded because it is shifted out
// CHECK-DAG: %[[arg2bit0:.*]] = memref.load %arg2[%[[c0]]] : memref<8xi1>
// CHECK-DAG: %[[arg2bit1:.*]] = memref.load %arg2[%[[c1]]] : memref<8xi1>
// CHECK-DAG: %[[arg2bit2:.*]] = memref.load %arg2[%[[c2]]] : memref<8xi1>
// CHECK-DAG: %[[arg2bit3:.*]] = memref.load %arg2[%[[c3]]] : memref<8xi1>
// CHECK-DAG: %[[arg2bit4:.*]] = memref.load %arg2[%[[c4]]] : memref<8xi1>
// CHECK-DAG: %[[arg2bit5:.*]] = memref.load %arg2[%[[c5]]] : memref<8xi1>
// CHECK-DAG: %[[arg2bit6:.*]] = memref.load %arg2[%[[c6]]] : memref<8xi1>
// CHECK-DAG: %[[arg2bit0:.*]] = memref.load %[[arg2]][%[[c0]]] : memref<8xi1>
// CHECK-DAG: %[[arg2bit1:.*]] = memref.load %[[arg2]][%[[c1]]] : memref<8xi1>
// CHECK-DAG: %[[arg2bit2:.*]] = memref.load %[[arg2]][%[[c2]]] : memref<8xi1>
// CHECK-DAG: %[[arg2bit3:.*]] = memref.load %[[arg2]][%[[c3]]] : memref<8xi1>
// CHECK-DAG: %[[arg2bit4:.*]] = memref.load %[[arg2]][%[[c4]]] : memref<8xi1>
// CHECK-DAG: %[[arg2bit5:.*]] = memref.load %[[arg2]][%[[c5]]] : memref<8xi1>
// CHECK-DAG: %[[arg2bit6:.*]] = memref.load %[[arg2]][%[[c6]]] : memref<8xi1>
//
// CHECK-DAG: %[[arg3bit0:.*]] = memref.load %arg3[%[[c0]]] : memref<8xi1>
// CHECK-DAG: %[[arg3bit1:.*]] = memref.load %arg3[%[[c1]]] : memref<8xi1>
// CHECK-DAG: %[[arg3bit2:.*]] = memref.load %arg3[%[[c2]]] : memref<8xi1>
// CHECK-DAG: %[[arg3bit3:.*]] = memref.load %arg3[%[[c3]]] : memref<8xi1>
// CHECK-DAG: %[[arg3bit4:.*]] = memref.load %arg3[%[[c4]]] : memref<8xi1>
// CHECK-DAG: %[[arg3bit5:.*]] = memref.load %arg3[%[[c5]]] : memref<8xi1>
// CHECK-DAG: %[[arg3bit6:.*]] = memref.load %arg3[%[[c6]]] : memref<8xi1>
// CHECK-DAG: %[[arg3bit0:.*]] = memref.load %[[arg3]][%[[c0]]] : memref<8xi1>
// CHECK-DAG: %[[arg3bit1:.*]] = memref.load %[[arg3]][%[[c1]]] : memref<8xi1>
// CHECK-DAG: %[[arg3bit2:.*]] = memref.load %[[arg3]][%[[c2]]] : memref<8xi1>
// CHECK-DAG: %[[arg3bit3:.*]] = memref.load %[[arg3]][%[[c3]]] : memref<8xi1>
// CHECK-DAG: %[[arg3bit4:.*]] = memref.load %[[arg3]][%[[c4]]] : memref<8xi1>
// CHECK-DAG: %[[arg3bit5:.*]] = memref.load %[[arg3]][%[[c5]]] : memref<8xi1>
// CHECK-DAG: %[[arg3bit6:.*]] = memref.load %[[arg3]][%[[c6]]] : memref<8xi1>
//
// The order of use of the two allocs seem arbitrary and nondeterministic,
// so check the stores without the memref names
Expand Down

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